forked from OSchip/llvm-project
66 lines
2.1 KiB
C++
66 lines
2.1 KiB
C++
//===-- SPUTargetMachine.cpp - Define TargetMachine for Cell SPU ----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Top-level implementation for the Cell SPU target.
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//
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//===----------------------------------------------------------------------===//
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#include "SPU.h"
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#include "SPUTargetMachine.h"
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#include "llvm/PassManager.h"
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#include "llvm/CodeGen/RegAllocRegistry.h"
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#include "llvm/CodeGen/SchedulerRegistry.h"
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#include "llvm/Target/TargetRegistry.h"
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using namespace llvm;
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extern "C" void LLVMInitializeCellSPUTarget() {
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// Register the target.
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RegisterTargetMachine<SPUTargetMachine> X(TheCellSPUTarget);
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}
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const std::pair<unsigned, int> *
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SPUFrameLowering::getCalleeSaveSpillSlots(unsigned &NumEntries) const {
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NumEntries = 1;
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return &LR[0];
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}
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SPUTargetMachine::SPUTargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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Reloc::Model RM, CodeModel::Model CM)
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: LLVMTargetMachine(T, TT, CPU, FS, RM, CM),
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Subtarget(TT, CPU, FS),
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DataLayout(Subtarget.getTargetDataString()),
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InstrInfo(*this),
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FrameLowering(Subtarget),
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TLInfo(*this),
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TSInfo(*this),
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InstrItins(Subtarget.getInstrItineraryData()) {
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}
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//===----------------------------------------------------------------------===//
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// Pass Pipeline Configuration
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//===----------------------------------------------------------------------===//
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bool SPUTargetMachine::addInstSelector(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel) {
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// Install an instruction selector.
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PM.add(createSPUISelDag(*this));
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return false;
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}
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// passes to run just before printing the assembly
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bool SPUTargetMachine::
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addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel)
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{
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//align instructions with nops/lnops for dual issue
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PM.add(createSPUNopFillerPass(*this));
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return true;
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}
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