forked from OSchip/llvm-project
400 lines
12 KiB
C++
400 lines
12 KiB
C++
//===-- MLxExpansionPass.cpp - Expand MLx instrs to avoid hazards ---------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Expand VFP / NEON floating point MLA / MLS instructions (each to a pair of
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// multiple and add / sub instructions) when special VMLx hazards are detected.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "mlx-expansion"
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#include "ARM.h"
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#include "ARMBaseInstrInfo.h"
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#include "ARMSubtarget.h"
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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using namespace llvm;
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static cl::opt<bool>
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ForceExapnd("expand-all-fp-mlx", cl::init(false), cl::Hidden);
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static cl::opt<unsigned>
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ExpandLimit("expand-limit", cl::init(~0U), cl::Hidden);
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STATISTIC(NumExpand, "Number of fp MLA / MLS instructions expanded");
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namespace {
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struct MLxExpansion : public MachineFunctionPass {
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static char ID;
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MLxExpansion() : MachineFunctionPass(ID) {}
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virtual bool runOnMachineFunction(MachineFunction &Fn);
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virtual const char *getPassName() const {
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return "ARM MLA / MLS expansion pass";
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}
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private:
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const ARMBaseInstrInfo *TII;
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const TargetRegisterInfo *TRI;
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MachineRegisterInfo *MRI;
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bool isLikeA9;
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bool isSwift;
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unsigned MIIdx;
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MachineInstr* LastMIs[4];
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SmallPtrSet<MachineInstr*, 4> IgnoreStall;
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void clearStack();
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void pushStack(MachineInstr *MI);
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MachineInstr *getAccDefMI(MachineInstr *MI) const;
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unsigned getDefReg(MachineInstr *MI) const;
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bool hasLoopHazard(MachineInstr *MI) const;
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bool hasRAWHazard(unsigned Reg, MachineInstr *MI) const;
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bool FindMLxHazard(MachineInstr *MI);
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void ExpandFPMLxInstruction(MachineBasicBlock &MBB, MachineInstr *MI,
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unsigned MulOpc, unsigned AddSubOpc,
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bool NegAcc, bool HasLane);
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bool ExpandFPMLxInstructions(MachineBasicBlock &MBB);
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};
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char MLxExpansion::ID = 0;
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}
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void MLxExpansion::clearStack() {
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std::fill(LastMIs, LastMIs + 4, (MachineInstr*)0);
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MIIdx = 0;
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}
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void MLxExpansion::pushStack(MachineInstr *MI) {
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LastMIs[MIIdx] = MI;
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if (++MIIdx == 4)
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MIIdx = 0;
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}
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MachineInstr *MLxExpansion::getAccDefMI(MachineInstr *MI) const {
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// Look past COPY and INSERT_SUBREG instructions to find the
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// real definition MI. This is important for _sfp instructions.
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unsigned Reg = MI->getOperand(1).getReg();
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if (TargetRegisterInfo::isPhysicalRegister(Reg))
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return 0;
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MachineBasicBlock *MBB = MI->getParent();
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MachineInstr *DefMI = MRI->getVRegDef(Reg);
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while (true) {
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if (DefMI->getParent() != MBB)
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break;
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if (DefMI->isCopyLike()) {
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Reg = DefMI->getOperand(1).getReg();
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if (TargetRegisterInfo::isVirtualRegister(Reg)) {
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DefMI = MRI->getVRegDef(Reg);
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continue;
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}
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} else if (DefMI->isInsertSubreg()) {
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Reg = DefMI->getOperand(2).getReg();
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if (TargetRegisterInfo::isVirtualRegister(Reg)) {
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DefMI = MRI->getVRegDef(Reg);
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continue;
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}
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}
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break;
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}
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return DefMI;
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}
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unsigned MLxExpansion::getDefReg(MachineInstr *MI) const {
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unsigned Reg = MI->getOperand(0).getReg();
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if (TargetRegisterInfo::isPhysicalRegister(Reg) ||
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!MRI->hasOneNonDBGUse(Reg))
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return Reg;
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MachineBasicBlock *MBB = MI->getParent();
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MachineInstr *UseMI = &*MRI->use_nodbg_begin(Reg);
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if (UseMI->getParent() != MBB)
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return Reg;
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while (UseMI->isCopy() || UseMI->isInsertSubreg()) {
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Reg = UseMI->getOperand(0).getReg();
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if (TargetRegisterInfo::isPhysicalRegister(Reg) ||
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!MRI->hasOneNonDBGUse(Reg))
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return Reg;
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UseMI = &*MRI->use_nodbg_begin(Reg);
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if (UseMI->getParent() != MBB)
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return Reg;
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}
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return Reg;
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}
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/// hasLoopHazard - Check whether an MLx instruction is chained to itself across
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/// a single-MBB loop.
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bool MLxExpansion::hasLoopHazard(MachineInstr *MI) const {
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unsigned Reg = MI->getOperand(1).getReg();
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if (TargetRegisterInfo::isPhysicalRegister(Reg))
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return false;
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MachineBasicBlock *MBB = MI->getParent();
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MachineInstr *DefMI = MRI->getVRegDef(Reg);
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while (true) {
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outer_continue:
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if (DefMI->getParent() != MBB)
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break;
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if (DefMI->isPHI()) {
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for (unsigned i = 1, e = DefMI->getNumOperands(); i < e; i += 2) {
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if (DefMI->getOperand(i + 1).getMBB() == MBB) {
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unsigned SrcReg = DefMI->getOperand(i).getReg();
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if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
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DefMI = MRI->getVRegDef(SrcReg);
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goto outer_continue;
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}
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}
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}
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} else if (DefMI->isCopyLike()) {
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Reg = DefMI->getOperand(1).getReg();
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if (TargetRegisterInfo::isVirtualRegister(Reg)) {
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DefMI = MRI->getVRegDef(Reg);
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continue;
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}
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} else if (DefMI->isInsertSubreg()) {
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Reg = DefMI->getOperand(2).getReg();
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if (TargetRegisterInfo::isVirtualRegister(Reg)) {
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DefMI = MRI->getVRegDef(Reg);
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continue;
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}
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}
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break;
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}
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return DefMI == MI;
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}
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bool MLxExpansion::hasRAWHazard(unsigned Reg, MachineInstr *MI) const {
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// FIXME: Detect integer instructions properly.
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const MCInstrDesc &MCID = MI->getDesc();
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unsigned Domain = MCID.TSFlags & ARMII::DomainMask;
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if (MI->mayStore())
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return false;
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unsigned Opcode = MCID.getOpcode();
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if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
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return false;
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if ((Domain & ARMII::DomainVFP) || (Domain & ARMII::DomainNEON))
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return MI->readsRegister(Reg, TRI);
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return false;
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}
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static bool isFpMulInstruction(unsigned Opcode) {
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switch (Opcode) {
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case ARM::VMULS:
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case ARM::VMULfd:
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case ARM::VMULfq:
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case ARM::VMULD:
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case ARM::VMULslfd:
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case ARM::VMULslfq:
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return true;
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default:
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return false;
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}
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}
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bool MLxExpansion::FindMLxHazard(MachineInstr *MI) {
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if (NumExpand >= ExpandLimit)
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return false;
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if (ForceExapnd)
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return true;
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MachineInstr *DefMI = getAccDefMI(MI);
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if (TII->isFpMLxInstruction(DefMI->getOpcode())) {
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// r0 = vmla
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// r3 = vmla r0, r1, r2
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// takes 16 - 17 cycles
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//
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// r0 = vmla
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// r4 = vmul r1, r2
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// r3 = vadd r0, r4
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// takes about 14 - 15 cycles even with vmul stalling for 4 cycles.
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IgnoreStall.insert(DefMI);
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return true;
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}
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// On Swift, we mostly care about hazards from multiplication instructions
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// writing the accumulator and the pipelining of loop iterations by out-of-
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// order execution.
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if (isSwift)
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return isFpMulInstruction(DefMI->getOpcode()) || hasLoopHazard(MI);
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if (IgnoreStall.count(MI))
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return false;
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// If a VMLA.F is followed by an VADD.F or VMUL.F with no RAW hazard, the
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// VADD.F or VMUL.F will stall 4 cycles before issue. The 4 cycle stall
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// preserves the in-order retirement of the instructions.
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// Look at the next few instructions, if *most* of them can cause hazards,
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// then the scheduler can't *fix* this, we'd better break up the VMLA.
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unsigned Limit1 = isLikeA9 ? 1 : 4;
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unsigned Limit2 = isLikeA9 ? 1 : 4;
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for (unsigned i = 1; i <= 4; ++i) {
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int Idx = ((int)MIIdx - i + 4) % 4;
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MachineInstr *NextMI = LastMIs[Idx];
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if (!NextMI)
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continue;
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if (TII->canCauseFpMLxStall(NextMI->getOpcode())) {
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if (i <= Limit1)
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return true;
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}
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// Look for VMLx RAW hazard.
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if (i <= Limit2 && hasRAWHazard(getDefReg(MI), NextMI))
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return true;
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}
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return false;
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}
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/// ExpandFPMLxInstructions - Expand a MLA / MLS instruction into a pair
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/// of MUL + ADD / SUB instructions.
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void
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MLxExpansion::ExpandFPMLxInstruction(MachineBasicBlock &MBB, MachineInstr *MI,
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unsigned MulOpc, unsigned AddSubOpc,
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bool NegAcc, bool HasLane) {
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unsigned DstReg = MI->getOperand(0).getReg();
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bool DstDead = MI->getOperand(0).isDead();
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unsigned AccReg = MI->getOperand(1).getReg();
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unsigned Src1Reg = MI->getOperand(2).getReg();
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unsigned Src2Reg = MI->getOperand(3).getReg();
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bool Src1Kill = MI->getOperand(2).isKill();
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bool Src2Kill = MI->getOperand(3).isKill();
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unsigned LaneImm = HasLane ? MI->getOperand(4).getImm() : 0;
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unsigned NextOp = HasLane ? 5 : 4;
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ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NextOp).getImm();
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unsigned PredReg = MI->getOperand(++NextOp).getReg();
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const MCInstrDesc &MCID1 = TII->get(MulOpc);
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const MCInstrDesc &MCID2 = TII->get(AddSubOpc);
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const MachineFunction &MF = *MI->getParent()->getParent();
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unsigned TmpReg = MRI->createVirtualRegister(
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TII->getRegClass(MCID1, 0, TRI, MF));
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MachineInstrBuilder MIB = BuildMI(MBB, MI, MI->getDebugLoc(), MCID1, TmpReg)
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.addReg(Src1Reg, getKillRegState(Src1Kill))
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.addReg(Src2Reg, getKillRegState(Src2Kill));
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if (HasLane)
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MIB.addImm(LaneImm);
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MIB.addImm(Pred).addReg(PredReg);
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MIB = BuildMI(MBB, MI, MI->getDebugLoc(), MCID2)
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.addReg(DstReg, getDefRegState(true) | getDeadRegState(DstDead));
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if (NegAcc) {
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bool AccKill = MRI->hasOneNonDBGUse(AccReg);
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MIB.addReg(TmpReg, getKillRegState(true))
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.addReg(AccReg, getKillRegState(AccKill));
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} else {
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MIB.addReg(AccReg).addReg(TmpReg, getKillRegState(true));
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}
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MIB.addImm(Pred).addReg(PredReg);
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DEBUG({
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dbgs() << "Expanding: " << *MI;
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dbgs() << " to:\n";
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MachineBasicBlock::iterator MII = MI;
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MII = llvm::prior(MII);
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MachineInstr &MI2 = *MII;
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MII = llvm::prior(MII);
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MachineInstr &MI1 = *MII;
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dbgs() << " " << MI1;
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dbgs() << " " << MI2;
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});
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MI->eraseFromParent();
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++NumExpand;
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}
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bool MLxExpansion::ExpandFPMLxInstructions(MachineBasicBlock &MBB) {
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bool Changed = false;
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clearStack();
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IgnoreStall.clear();
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unsigned Skip = 0;
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MachineBasicBlock::reverse_iterator MII = MBB.rbegin(), E = MBB.rend();
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while (MII != E) {
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MachineInstr *MI = &*MII;
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if (MI->isLabel() || MI->isImplicitDef() || MI->isCopy()) {
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++MII;
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continue;
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}
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const MCInstrDesc &MCID = MI->getDesc();
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if (MI->isBarrier()) {
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clearStack();
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Skip = 0;
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++MII;
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continue;
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}
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unsigned Domain = MCID.TSFlags & ARMII::DomainMask;
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if (Domain == ARMII::DomainGeneral) {
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if (++Skip == 2)
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// Assume dual issues of non-VFP / NEON instructions.
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pushStack(0);
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} else {
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Skip = 0;
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unsigned MulOpc, AddSubOpc;
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bool NegAcc, HasLane;
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if (!TII->isFpMLxInstruction(MCID.getOpcode(),
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MulOpc, AddSubOpc, NegAcc, HasLane) ||
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!FindMLxHazard(MI))
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pushStack(MI);
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else {
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ExpandFPMLxInstruction(MBB, MI, MulOpc, AddSubOpc, NegAcc, HasLane);
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E = MBB.rend(); // May have changed if MI was the 1st instruction.
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Changed = true;
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continue;
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}
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}
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++MII;
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}
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return Changed;
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}
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bool MLxExpansion::runOnMachineFunction(MachineFunction &Fn) {
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TII = static_cast<const ARMBaseInstrInfo*>(Fn.getTarget().getInstrInfo());
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TRI = Fn.getTarget().getRegisterInfo();
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MRI = &Fn.getRegInfo();
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const ARMSubtarget *STI = &Fn.getTarget().getSubtarget<ARMSubtarget>();
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isLikeA9 = STI->isLikeA9() || STI->isSwift();
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isSwift = STI->isSwift();
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bool Modified = false;
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for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E;
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++MFI) {
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MachineBasicBlock &MBB = *MFI;
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Modified |= ExpandFPMLxInstructions(MBB);
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}
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return Modified;
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}
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FunctionPass *llvm::createMLxExpansionPass() {
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return new MLxExpansion();
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}
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