Elena Demikhovsky 0ccdd1315b I optimized the following patterns: ... sext <4 x i1> to <4 x i64> sext <4 x i8> to <4 x i64> sext <4 x i16> to <4 x i64> I'm running Combine on SIGN_EXTEND_IN_REG and revert SEXT patterns: (sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) -> (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT))) The sext_in_reg (v4i32 x) may be lowered to shl+sar operations. The "sar" does not exist on 64-bit operation, so lowering sext_in_reg (v4i64 x) has no vector solution. I also added a cost of this operations to the AVX costs table. llvm-svn: 175619		2013-02-20 12:42:54 +00:00
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arith.ll	Cost Model: change the default cost of control flow instructions (br / ret / ...) to zero.	2012-12-05 21:21:26 +00:00
cast.ll	I optimized the following patterns:	2013-02-20 12:42:54 +00:00
cmp.ll	Reverse order of checking SSE level when calculating compare cost, so we check	2012-12-18 22:57:56 +00:00
gep.ll	ARM cost model: Address computation in vector mem ops not free	2013-02-08 14:50:48 +00:00
i32.ll	We are not ready to estimate the cost of integer expansions based on the number of parts. This test is too noisy.	2012-12-23 09:11:07 +00:00
insert-extract-at-zero.ll	Cost Model: Normalize the insert/extract index when splitting types	2012-11-05 21:12:13 +00:00
lit.local.cfg	…
load_store.ll	Improve the X86 cost model for loads and stores.	2012-12-21 01:33:59 +00:00
loop_v2.ll	…
tiny.ll	Cost Model: change the default cost of control flow instructions (br / ret / ...) to zero.	2012-12-05 21:21:26 +00:00
vectorized-loop.ll	Improve the X86 cost model for loads and stores.	2012-12-21 01:33:59 +00:00