forked from OSchip/llvm-project
126 lines
4.4 KiB
C++
126 lines
4.4 KiB
C++
//===- MIParser.h - Machine Instructions Parser -----------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares the function that parses the machine instructions.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_CODEGEN_MIRPARSER_MIPARSER_H
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#define LLVM_LIB_CODEGEN_MIRPARSER_MIPARSER_H
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/StringMap.h"
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#include "llvm/Support/Allocator.h"
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namespace llvm {
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class MachineBasicBlock;
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class MachineFunction;
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class MDNode;
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class RegisterBank;
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struct SlotMapping;
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class SMDiagnostic;
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class SourceMgr;
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class StringRef;
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class TargetRegisterClass;
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struct VRegInfo {
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enum uint8_t {
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UNKNOWN, NORMAL, GENERIC, REGBANK
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} Kind = UNKNOWN;
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bool Explicit = false; ///< VReg was explicitly specified in the .mir file.
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union {
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const TargetRegisterClass *RC;
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const RegisterBank *RegBank;
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} D;
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unsigned VReg;
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unsigned PreferredReg = 0;
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};
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using Name2RegClassMap = StringMap<const TargetRegisterClass *>;
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using Name2RegBankMap = StringMap<const RegisterBank *>;
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struct PerFunctionMIParsingState {
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BumpPtrAllocator Allocator;
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MachineFunction &MF;
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SourceMgr *SM;
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const SlotMapping &IRSlots;
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const Name2RegClassMap &Names2RegClasses;
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const Name2RegBankMap &Names2RegBanks;
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DenseMap<unsigned, MachineBasicBlock *> MBBSlots;
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DenseMap<unsigned, VRegInfo*> VRegInfos;
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StringMap<VRegInfo*> VRegInfosNamed;
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DenseMap<unsigned, int> FixedStackObjectSlots;
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DenseMap<unsigned, int> StackObjectSlots;
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DenseMap<unsigned, unsigned> ConstantPoolSlots;
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DenseMap<unsigned, unsigned> JumpTableSlots;
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PerFunctionMIParsingState(MachineFunction &MF, SourceMgr &SM,
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const SlotMapping &IRSlots,
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const Name2RegClassMap &Names2RegClasses,
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const Name2RegBankMap &Names2RegBanks);
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VRegInfo &getVRegInfo(unsigned Num);
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VRegInfo &getVRegInfoNamed(StringRef RegName);
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};
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/// Parse the machine basic block definitions, and skip the machine
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/// instructions.
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///
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/// This function runs the first parsing pass on the machine function's body.
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/// It parses only the machine basic block definitions and creates the machine
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/// basic blocks in the given machine function.
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///
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/// The machine instructions aren't parsed during the first pass because all
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/// the machine basic blocks aren't defined yet - this makes it impossible to
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/// resolve the machine basic block references.
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///
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/// Return true if an error occurred.
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bool parseMachineBasicBlockDefinitions(PerFunctionMIParsingState &PFS,
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StringRef Src, SMDiagnostic &Error);
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/// Parse the machine instructions.
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///
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/// This function runs the second parsing pass on the machine function's body.
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/// It skips the machine basic block definitions and parses only the machine
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/// instructions and basic block attributes like liveins and successors.
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///
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/// The second parsing pass assumes that the first parsing pass already ran
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/// on the given source string.
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///
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/// Return true if an error occurred.
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bool parseMachineInstructions(PerFunctionMIParsingState &PFS, StringRef Src,
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SMDiagnostic &Error);
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bool parseMBBReference(PerFunctionMIParsingState &PFS,
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MachineBasicBlock *&MBB, StringRef Src,
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SMDiagnostic &Error);
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bool parseRegisterReference(PerFunctionMIParsingState &PFS,
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unsigned &Reg, StringRef Src,
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SMDiagnostic &Error);
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bool parseNamedRegisterReference(PerFunctionMIParsingState &PFS, unsigned &Reg,
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StringRef Src, SMDiagnostic &Error);
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bool parseVirtualRegisterReference(PerFunctionMIParsingState &PFS,
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VRegInfo *&Info, StringRef Src,
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SMDiagnostic &Error);
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bool parseStackObjectReference(PerFunctionMIParsingState &PFS, int &FI,
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StringRef Src, SMDiagnostic &Error);
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bool parseMDNode(PerFunctionMIParsingState &PFS, MDNode *&Node, StringRef Src,
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SMDiagnostic &Error);
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} // end namespace llvm
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#endif // LLVM_LIB_CODEGEN_MIRPARSER_MIPARSER_H
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