wingsummer/WingHexDisasm
wingsummer
/
WingHexDisasm
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

first commit

This commit is contained in:
寂静的羽夏 2022-08-22 19:31:42 +08:00
commit c3677df93b
44 changed files with 16961 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
.gitignore vendored Executable file
View File

@ -0,0 +1,2 @@
**/*.pro.user
push.sh

661
LICENSE Normal file
View File

@ -0,0 +1,661 @@
GNU AFFERO GENERAL PUBLIC LICENSE
Version 3, 19 November 2007
Copyright (C) 2007 Free Software Foundation, Inc. httpfsf.org
Everyone is permitted to copy and distribute verbatim copies
of this license document, but changing it is not allowed.
Preamble
The GNU Affero General Public License is a free, copyleft license for
software and other kinds of works, specifically designed to ensure
cooperation with the community in the case of network server software.
The licenses for most software and other practical works are designed
to take away your freedom to share and change the works. By contrast,
our General Public Licenses are intended to guarantee your freedom to
share and change all versions of a program--to make sure it remains free
software for all its users.
When we speak of free software, we are referring to freedom, not
price. Our General Public Licenses are designed to make sure that you
have the freedom to distribute copies of free software (and charge for
them if you wish), that you receive source code or can get it if you
want it, that you can change the software or use pieces of it in new
free programs, and that you know you can do these things.
Developers that use our General Public Licenses protect your rights
with two steps (1) assert copyright on the software, and (2) offer
you this License which gives you legal permission to copy, distribute
andor modify the software.
A secondary benefit of defending all users' freedom is that
improvements made in alternate versions of the program, if they
receive widespread use, become available for other developers to
incorporate. Many developers of free software are heartened and
encouraged by the resulting cooperation. However, in the case of
software used on network servers, this result may fail to come about.
The GNU General Public License permits making a modified version and
letting the public access it on a server without ever releasing its
source code to the public.
The GNU Affero General Public License is designed specifically to
ensure that, in such cases, the modified source code becomes available
to the community. It requires the operator of a network server to
provide the source code of the modified version running there to the
users of that server. Therefore, public use of a modified version, on
a publicly accessible server, gives the public access to the source
code of the modified version.
An older license, called the Affero General Public License and
published by Affero, was designed to accomplish similar goals. This is
a different license, not a version of the Affero GPL, but Affero has
released a new version of the Affero GPL which permits relicensing under
this license.
The precise terms and conditions for copying, distribution and
modification follow.
TERMS AND CONDITIONS
0. Definitions.
This License refers to version 3 of the GNU Affero General Public License.
Copyright also means copyright-like laws that apply to other kinds of
works, such as semiconductor masks.
The Program refers to any copyrightable work licensed under this
License. Each licensee is addressed as you. Licensees and
recipients may be individuals or organizations.
To modify a work means to copy from or adapt all or part of the work
in a fashion requiring copyright permission, other than the making of an
exact copy. The resulting work is called a modified version of the
earlier work or a work based on the earlier work.
A covered work means either the unmodified Program or a work based
on the Program.
To propagate a work means to do anything with it that, without
permission, would make you directly or secondarily liable for
infringement under applicable copyright law, except executing it on a
computer or modifying a private copy. Propagation includes copying,
distribution (with or without modification), making available to the
public, and in some countries other activities as well.
To convey a work means any kind of propagation that enables other
parties to make or receive copies. Mere interaction with a user through
a computer network, with no transfer of a copy, is not conveying.
An interactive user interface displays Appropriate Legal Notices
to the extent that it includes a convenient and prominently visible
feature that (1) displays an appropriate copyright notice, and (2)
tells the user that there is no warranty for the work (except to the
extent that warranties are provided), that licensees may convey the
work under this License, and how to view a copy of this License. If
the interface presents a list of user commands or options, such as a
menu, a prominent item in the list meets this criterion.
1. Source Code.
The source code for a work means the preferred form of the work
for making modifications to it. Object code means any non-source
form of a work.
A Standard Interface means an interface that either is an official
standard defined by a recognized standards body, or, in the case of
interfaces specified for a particular programming language, one that
is widely used among developers working in that language.
The System Libraries of an executable work include anything, other
than the work as a whole, that (a) is included in the normal form of
packaging a Major Component, but which is not part of that Major
Component, and (b) serves only to enable use of the work with that
Major Component, or to implement a Standard Interface for which an
implementation is available to the public in source code form. A
Major Component, in this context, means a major essential component
(kernel, window system, and so on) of the specific operating system
(if any) on which the executable work runs, or a compiler used to
produce the work, or an object code interpreter used to run it.
The Corresponding Source for a work in object code form means all
the source code needed to generate, install, and (for an executable
work) run the object code and to modify the work, including scripts to
control those activities. However, it does not include the work's
System Libraries, or general-purpose tools or generally available free
programs which are used unmodified in performing those activities but
which are not part of the work. For example, Corresponding Source
includes interface definition files associated with source files for
the work, and the source code for shared libraries and dynamically
linked subprograms that the work is specifically designed to require,
such as by intimate data communication or control flow between those
subprograms and other parts of the work.
The Corresponding Source need not include anything that users
can regenerate automatically from other parts of the Corresponding
Source.
The Corresponding Source for a work in source code form is that
same work.
2. Basic Permissions.
All rights granted under this License are granted for the term of
copyright on the Program, and are irrevocable provided the stated
conditions are met. This License explicitly affirms your unlimited
permission to run the unmodified Program. The output from running a
covered work is covered by this License only if the output, given its
content, constitutes a covered work. This License acknowledges your
rights of fair use or other equivalent, as provided by copyright law.
You may make, run and propagate covered works that you do not
convey, without conditions so long as your license otherwise remains
in force. You may convey covered works to others for the sole purpose
of having them make modifications exclusively for you, or provide you
with facilities for running those works, provided that you comply with
the terms of this License in conveying all material for which you do
not control copyright. Those thus making or running the covered works
for you must do so exclusively on your behalf, under your direction
and control, on terms that prohibit them from making any copies of
your copyrighted material outside their relationship with you.
Conveying under any other circumstances is permitted solely under
the conditions stated below. Sublicensing is not allowed; section 10
makes it unnecessary.
3. Protecting Users' Legal Rights From Anti-Circumvention Law.
No covered work shall be deemed part of an effective technological
measure under any applicable law fulfilling obligations under article
11 of the WIPO copyright treaty adopted on 20 December 1996, or
similar laws prohibiting or restricting circumvention of such
measures.
When you convey a covered work, you waive any legal power to forbid
circumvention of technological measures to the extent such circumvention
is effected by exercising rights under this License with respect to
the covered work, and you disclaim any intention to limit operation or
modification of the work as a means of enforcing, against the work's
users, your or third parties' legal rights to forbid circumvention of
technological measures.
4. Conveying Verbatim Copies.
You may convey verbatim copies of the Program's source code as you
receive it, in any medium, provided that you conspicuously and
appropriately publish on each copy an appropriate copyright notice;
keep intact all notices stating that this License and any
non-permissive terms added in accord with section 7 apply to the code;
keep intact all notices of the absence of any warranty; and give all
recipients a copy of this License along with the Program.
You may charge any price or no price for each copy that you convey,
and you may offer support or warranty protection for a fee.
5. Conveying Modified Source Versions.
You may convey a work based on the Program, or the modifications to
produce it from the Program, in the form of source code under the
terms of section 4, provided that you also meet all of these conditions
a) The work must carry prominent notices stating that you modified
it, and giving a relevant date.
b) The work must carry prominent notices stating that it is
released under this License and any conditions added under section
7. This requirement modifies the requirement in section 4 to
keep intact all notices.
c) You must license the entire work, as a whole, under this
License to anyone who comes into possession of a copy. This
License will therefore apply, along with any applicable section 7
additional terms, to the whole of the work, and all its parts,
regardless of how they are packaged. This License gives no
permission to license the work in any other way, but it does not
invalidate such permission if you have separately received it.
d) If the work has interactive user interfaces, each must display
Appropriate Legal Notices; however, if the Program has interactive
interfaces that do not display Appropriate Legal Notices, your
work need not make them do so.
A compilation of a covered work with other separate and independent
works, which are not by their nature extensions of the covered work,
and which are not combined with it such as to form a larger program,
in or on a volume of a storage or distribution medium, is called an
aggregate if the compilation and its resulting copyright are not
used to limit the access or legal rights of the compilation's users
beyond what the individual works permit. Inclusion of a covered work
in an aggregate does not cause this License to apply to the other
parts of the aggregate.
6. Conveying Non-Source Forms.
You may convey a covered work in object code form under the terms
of sections 4 and 5, provided that you also convey the
machine-readable Corresponding Source under the terms of this License,
in one of these ways
a) Convey the object code in, or embodied in, a physical product
(including a physical distribution medium), accompanied by the
Corresponding Source fixed on a durable physical medium
customarily used for software interchange.
b) Convey the object code in, or embodied in, a physical product
(including a physical distribution medium), accompanied by a
written offer, valid for at least three years and valid for as
long as you offer spare parts or customer support for that product
model, to give anyone who possesses the object code either (1) a
copy of the Corresponding Source for all the software in the
product that is covered by this License, on a durable physical
medium customarily used for software interchange, for a price no
more than your reasonable cost of physically performing this
conveying of source, or (2) access to copy the
Corresponding Source from a network server at no charge.
c) Convey individual copies of the object code with a copy of the
written offer to provide the Corresponding Source. This
alternative is allowed only occasionally and noncommercially, and
only if you received the object code with such an offer, in accord
with subsection 6b.
d) Convey the object code by offering access from a designated
place (gratis or for a charge), and offer equivalent access to the
Corresponding Source in the same way through the same place at no
further charge. You need not require recipients to copy the
Corresponding Source along with the object code. If the place to
copy the object code is a network server, the Corresponding Source
may be on a different server (operated by you or a third party)
that supports equivalent copying facilities, provided you maintain
clear directions next to the object code saying where to find the
Corresponding Source. Regardless of what server hosts the
Corresponding Source, you remain obligated to ensure that it is
available for as long as needed to satisfy these requirements.
e) Convey the object code using peer-to-peer transmission, provided
you inform other peers where the object code and Corresponding
Source of the work are being offered to the general public at no
charge under subsection 6d.
A separable portion of the object code, whose source code is excluded
from the Corresponding Source as a System Library, need not be
included in conveying the object code work.
A User Product is either (1) a consumer product, which means any
tangible personal property which is normally used for personal, family,
or household purposes, or (2) anything designed or sold for incorporation
into a dwelling. In determining whether a product is a consumer product,
doubtful cases shall be resolved in favor of coverage. For a particular
product received by a particular user, normally used refers to a
typical or common use of that class of product, regardless of the status
of the particular user or of the way in which the particular user
actually uses, or expects or is expected to use, the product. A product
is a consumer product regardless of whether the product has substantial
commercial, industrial or non-consumer uses, unless such uses represent
the only significant mode of use of the product.
Installation Information for a User Product means any methods,
procedures, authorization keys, or other information required to install
and execute modified versions of a covered work in that User Product from
a modified version of its Corresponding Source. The information must
suffice to ensure that the continued functioning of the modified object
code is in no case prevented or interfered with solely because
modification has been made.
If you convey an object code work under this section in, or with, or
specifically for use in, a User Product, and the conveying occurs as
part of a transaction in which the right of possession and use of the
User Product is transferred to the recipient in perpetuity or for a
fixed term (regardless of how the transaction is characterized), the
Corresponding Source conveyed under this section must be accompanied
by the Installation Information. But this requirement does not apply
if neither you nor any third party retains the ability to install
modified object code on the User Product (for example, the work has
been installed in ROM).
The requirement to provide Installation Information does not include a
requirement to continue to provide support service, warranty, or updates
for a work that has been modified or installed by the recipient, or for
the User Product in which it has been modified or installed. Access to a
network may be denied when the modification itself materially and
adversely affects the operation of the network or violates the rules and
protocols for communication across the network.
Corresponding Source conveyed, and Installation Information provided,
in accord with this section must be in a format that is publicly
documented (and with an implementation available to the public in
source code form), and must require no special password or key for
unpacking, reading or copying.
7. Additional Terms.
Additional permissions are terms that supplement the terms of this
License by making exceptions from one or more of its conditions.
Additional permissions that are applicable to the entire Program shall
be treated as though they were included in this License, to the extent
that they are valid under applicable law. If additional permissions
apply only to part of the Program, that part may be used separately
under those permissions, but the entire Program remains governed by
this License without regard to the additional permissions.
When you convey a copy of a covered work, you may at your option
remove any additional permissions from that copy, or from any part of
it. (Additional permissions may be written to require their own
removal in certain cases when you modify the work.) You may place
additional permissions on material, added by you to a covered work,
for which you have or can give appropriate copyright permission.
Notwithstanding any other provision of this License, for material you
add to a covered work, you may (if authorized by the copyright holders of
that material) supplement the terms of this License with terms
a) Disclaiming warranty or limiting liability differently from the
terms of sections 15 and 16 of this License; or
b) Requiring preservation of specified reasonable legal notices or
author attributions in that material or in the Appropriate Legal
Notices displayed by works containing it; or
c) Prohibiting misrepresentation of the origin of that material, or
requiring that modified versions of such material be marked in
reasonable ways as different from the original version; or
d) Limiting the use for publicity purposes of names of licensors or
authors of the material; or
e) Declining to grant rights under trademark law for use of some
trade names, trademarks, or service marks; or
f) Requiring indemnification of licensors and authors of that
material by anyone who conveys the material (or modified versions of
it) with contractual assumptions of liability to the recipient, for
any liability that these contractual assumptions directly impose on
those licensors and authors.
All other non-permissive additional terms are considered further
restrictions within the meaning of section 10. If the Program as you
received it, or any part of it, contains a notice stating that it is
governed by this License along with a term that is a further
restriction, you may remove that term. If a license document contains
a further restriction but permits relicensing or conveying under this
License, you may add to a covered work material governed by the terms
of that license document, provided that the further restriction does
not survive such relicensing or conveying.
If you add terms to a covered work in accord with this section, you
must place, in the relevant source files, a statement of the
additional terms that apply to those files, or a notice indicating
where to find the applicable terms.
Additional terms, permissive or non-permissive, may be stated in the
form of a separately written license, or stated as exceptions;
the above requirements apply either way.
8. Termination.
You may not propagate or modify a covered work except as expressly
provided under this License. Any attempt otherwise to propagate or
modify it is void, and will automatically terminate your rights under
this License (including any patent licenses granted under the third
paragraph of section 11).
However, if you cease all violation of this License, then your
license from a particular copyright holder is reinstated (a)
provisionally, unless and until the copyright holder explicitly and
finally terminates your license, and (b) permanently, if the copyright
holder fails to notify you of the violation by some reasonable means
prior to 60 days after the cessation.
Moreover, your license from a particular copyright holder is
reinstated permanently if the copyright holder notifies you of the
violation by some reasonable means, this is the first time you have
received notice of violation of this License (for any work) from that
copyright holder, and you cure the violation prior to 30 days after
your receipt of the notice.
Termination of your rights under this section does not terminate the
licenses of parties who have received copies or rights from you under
this License. If your rights have been terminated and not permanently
reinstated, you do not qualify to receive new licenses for the same
material under section 10.
9. Acceptance Not Required for Having Copies.
You are not required to accept this License in order to receive or
run a copy of the Program. Ancillary propagation of a covered work
occurring solely as a consequence of using peer-to-peer transmission
to receive a copy likewise does not require acceptance. However,
nothing other than this License grants you permission to propagate or
modify any covered work. These actions infringe copyright if you do
not accept this License. Therefore, by modifying or propagating a
covered work, you indicate your acceptance of this License to do so.
10. Automatic Licensing of Downstream Recipients.
Each time you convey a covered work, the recipient automatically
receives a license from the original licensors, to run, modify and
propagate that work, subject to this License. You are not responsible
for enforcing compliance by third parties with this License.
An entity transaction is a transaction transferring control of an
organization, or substantially all assets of one, or subdividing an
organization, or merging organizations. If propagation of a covered
work results from an entity transaction, each party to that
transaction who receives a copy of the work also receives whatever
licenses to the work the party's predecessor in interest had or could
give under the previous paragraph, plus a right to possession of the
Corresponding Source of the work from the predecessor in interest, if
the predecessor has it or can get it with reasonable efforts.
You may not impose any further restrictions on the exercise of the
rights granted or affirmed under this License. For example, you may
not impose a license fee, royalty, or other charge for exercise of
rights granted under this License, and you may not initiate litigation
(including a cross-claim or counterclaim in a lawsuit) alleging that
any patent claim is infringed by making, using, selling, offering for
sale, or importing the Program or any portion of it.
11. Patents.
A contributor is a copyright holder who authorizes use under this
License of the Program or a work on which the Program is based. The
work thus licensed is called the contributor's contributor version.
A contributor's essential patent claims are all patent claims
owned or controlled by the contributor, whether already acquired or
hereafter acquired, that would be infringed by some manner, permitted
by this License, of making, using, or selling its contributor version,
but do not include claims that would be infringed only as a
consequence of further modification of the contributor version. For
purposes of this definition, control includes the right to grant
patent sublicenses in a manner consistent with the requirements of
this License.
Each contributor grants you a non-exclusive, worldwide, royalty-free
patent license under the contributor's essential patent claims, to
make, use, sell, offer for sale, import and otherwise run, modify and
propagate the contents of its contributor version.
In the following three paragraphs, a patent license is any express
agreement or commitment, however denominated, not to enforce a patent
(such as an express permission to practice a patent or covenant not to
sue for patent infringement). To grant such a patent license to a
party means to make such an agreement or commitment not to enforce a
patent against the party.
If you convey a covered work, knowingly relying on a patent license,
and the Corresponding Source of the work is not available for anyone
to copy, free of charge and under the terms of this License, through a
publicly available network server or other readily accessible means,
then you must either (1) cause the Corresponding Source to be so
available, or (2) arrange to deprive yourself of the benefit of the
patent license for this particular work, or (3) arrange, in a manner
consistent with the requirements of this License, to extend the patent
license to downstream recipients. Knowingly relying means you have
actual knowledge that, but for the patent license, your conveying the
covered work in a country, or your recipient's use of the covered work
in a country, would infringe one or more identifiable patents in that
country that you have reason to believe are valid.
If, pursuant to or in connection with a single transaction or
arrangement, you convey, or propagate by procuring conveyance of, a
covered work, and grant a patent license to some of the parties
receiving the covered work authorizing them to use, propagate, modify
or convey a specific copy of the covered work, then the patent license
you grant is automatically extended to all recipients of the covered
work and works based on it.
A patent license is discriminatory if it does not include within
the scope of its coverage, prohibits the exercise of, or is
conditioned on the non-exercise of one or more of the rights that are
specifically granted under this License. You may not convey a covered
work if you are a party to an arrangement with a third party that is
in the business of distributing software, under which you make payment
to the third party based on the extent of your activity of conveying
the work, and under which the third party grants, to any of the
parties who would receive the covered work from you, a discriminatory
patent license (a) in connection with copies of the covered work
conveyed by you (or copies made from those copies), or (b) primarily
for and in connection with specific products or compilations that
contain the covered work, unless you entered into that arrangement,
or that patent license was granted, prior to 28 March 2007.
Nothing in this License shall be construed as excluding or limiting
any implied license or other defenses to infringement that may
otherwise be available to you under applicable patent law.
12. No Surrender of Others' Freedom.
If conditions are imposed on you (whether by court order, agreement or
otherwise) that contradict the conditions of this License, they do not
excuse you from the conditions of this License. If you cannot convey a
covered work so as to satisfy simultaneously your obligations under this
License and any other pertinent obligations, then as a consequence you may
not convey it at all. For example, if you agree to terms that obligate you
to collect a royalty for further conveying from those to whom you convey
the Program, the only way you could satisfy both those terms and this
License would be to refrain entirely from conveying the Program.
13. Remote Network Interaction; Use with the GNU General Public License.
Notwithstanding any other provision of this License, if you modify the
Program, your modified version must prominently offer all users
interacting with it remotely through a computer network (if your version
supports such interaction) an opportunity to receive the Corresponding
Source of your version by providing access to the Corresponding Source
from a network server at no charge, through some standard or customary
means of facilitating copying of software. This Corresponding Source
shall include the Corresponding Source for any work covered by version 3
of the GNU General Public License that is incorporated pursuant to the
following paragraph.
Notwithstanding any other provision of this License, you have
permission to link or combine any covered work with a work licensed
under version 3 of the GNU General Public License into a single
combined work, and to convey the resulting work. The terms of this
License will continue to apply to the part which is the covered work,
but the work with which it is combined will remain governed by version
3 of the GNU General Public License.
14. Revised Versions of this License.
The Free Software Foundation may publish revised andor new versions of
the GNU Affero General Public License from time to time. Such new versions
will be similar in spirit to the present version, but may differ in detail to
address new problems or concerns.
Each version is given a distinguishing version number. If the
Program specifies that a certain numbered version of the GNU Affero General
Public License or any later version applies to it, you have the
option of following the terms and conditions either of that numbered
version or of any later version published by the Free Software
Foundation. If the Program does not specify a version number of the
GNU Affero General Public License, you may choose any version ever published
by the Free Software Foundation.
If the Program specifies that a proxy can decide which future
versions of the GNU Affero General Public License can be used, that proxy's
public statement of acceptance of a version permanently authorizes you
to choose that version for the Program.
Later license versions may give you additional or different
permissions. However, no additional obligations are imposed on any
author or copyright holder as a result of your choosing to follow a
later version.
15. Disclaimer of Warranty.
THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY
APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT
HOLDERS ANDOR OTHER PARTIES PROVIDE THE PROGRAM AS IS WITHOUT WARRANTY
OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO,
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM
IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF
ALL NECESSARY SERVICING, REPAIR OR CORRECTION.
16. Limitation of Liability.
IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES ANDOR CONVEYS
THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY
GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE
USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF
DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD
PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS),
EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF
SUCH DAMAGES.
17. Interpretation of Sections 15 and 16.
If the disclaimer of warranty and limitation of liability provided
above cannot be given local legal effect according to their terms,
reviewing courts shall apply local law that most closely approximates
an absolute waiver of all civil liability in connection with the
Program, unless a warranty or assumption of liability accompanies a
copy of the Program in return for a fee.
END OF TERMS AND CONDITIONS
How to Apply These Terms to Your New Programs
If you develop a new program, and you want it to be of the greatest
possible use to the public, the best way to achieve this is to make it
free software which everyone can redistribute and change under these terms.
To do so, attach the following notices to the program. It is safest
to attach them to the start of each source file to most effectively
state the exclusion of warranty; and each file should have at least
the copyright line and a pointer to where the full notice is found.
one line to give the program's name and a brief idea of what it does.
Copyright (C) year name of author
This program is free software you can redistribute it andor modify
it under the terms of the GNU Affero General Public License as published
by the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU Affero General Public License for more details.
You should have received a copy of the GNU Affero General Public License
along with this program. If not, see httpwww.gnu.orglicenses.
Also add information on how to contact you by electronic and paper mail.
If your software can interact with users remotely through a computer
network, you should also make sure that it provides a way for users to
get its source. For example, if your program is a web application, its
interface could display a Source link that leads users to an archive
of the code. There are many ways you could offer source, and different
solutions will be better for different programs; see section 13 for the
specific requirements.
You should also get your employer (if you work as a programmer) or school,
if any, to sign a copyright disclaimer for the program, if necessary.
For more information on this, and how to apply and follow the GNU AGPL, see
httpwww.gnu.orglicenses.

58
README.md Normal file
View File

@ -0,0 +1,58 @@
<h1 align="center">WingSummer.WingHexDisasm</h1>
<p align="center">
<img alt="WingHexPy" src="img/icon.png">
<p align="center">WingHexDisasm</p>
</p>
<p align="center">
<img alt="作者" src="https://img.shields.io/badge/Author-Wingsummer-green">
<img alt="开源协议" src="https://img.shields.io/badge/License-AGPL--3.0-red">
</p>
- 开源不易，给个 Star 或者 [捐助](#捐助) 吧
## WingHexDisasm
&emsp;&emsp;`WingHexDisasm`是一个羽云十六进制编辑器插件，它具有对给出字节进行反汇编的能力，基于`capstone`反汇编引擎框架。
### 协议
&emsp;&emsp;本插件仓库将采用`AGPL-3.0`协议，不得将该插件代码用于改协议之外的用途。
## 效果图
<p align="center">
<img alt="效果图" src="screenshot.png">
<p align="center">WingHexDisasm</p>
</p>
## 如何使用
&emsp;&emsp;将插件注册到软件的插件系统当中之后，只需在文档中用鼠标框选字节，执行反汇编命令即可。
## 注意事项
&emsp;&emsp;本插件仅支持`SDKVERSION >= 8`以上的“羽云十六进制编辑器”，也就是 1.4.8 及其以上的版本（该版本未被发布，请自行编译，预计 2022/8/25 发布该版本）。
## 捐助
**<p align="center">您的每一份支持都将是本项目推进的强大动力，十分感谢您的支持</p>**
<p align="center">
<img alt="支付宝" src="img/支付宝捐助.jpg" height=50% width=50%>
<p align="center">感谢支持</p>
</p>
<p align="center">
<img alt="微信" src="img/微信捐助.png" height=50% width=50%>
<p align="center">感谢支持</p>
</p>
## 有关仓库
* Gitea : https://code.gitlink.org.cn/wingsummer/WingHexPy
* Gitee : https://gitee.com/wing-cloud/wing-hex-py

3
WingHexDisasm.json Normal file
View File

@ -0,0 +1,3 @@
{
"Keys" : [ ]
}

67
WingHexDisasm.pro Normal file
View File

@ -0,0 +1,67 @@
#-------------------------------------------------
#
# Project created by QtCreator 2022-08-22T16:21:12
#
#-------------------------------------------------
QT += core gui
greaterThan(QT_MAJOR_VERSION, 4): QT += widgets
TARGET = WingHexDisasm
TEMPLATE = lib
CONFIG += plugin
# The following define makes your compiler emit warnings if you use
# any feature of Qt which has been marked as deprecated (the exact warnings
# depend on your compiler). Please consult the documentation of the
# deprecated API in order to know how to port your code away from it.
DEFINES += QT_DEPRECATED_WARNINGS
# You can also make your code fail to compile if you use deprecated APIs.
# In order to do so, uncomment the following line.
# You can also select to disable deprecated APIs only up to a certain version of Qt.
#DEFINES += QT_DISABLE_DEPRECATED_BEFORE=0x060000 # disables all the APIs deprecated before Qt 6.0.0
SOURCES += \
winghexdisasm.cpp \
authordialog.cpp \
sponsordialog.cpp
HEADERS += \
capstone/arm.h \
capstone/arm64.h \
capstone/bpf.h \
capstone/capstone.h \
capstone/evm.h \
capstone/m680x.h \
capstone/m68k.h \
capstone/mips.h \
capstone/mos65xx.h \
capstone/platform.h \
capstone/ppc.h \
capstone/riscv.h \
capstone/sparc.h \
capstone/systemz.h \
capstone/tms320c64x.h \
capstone/wasm.h \
capstone/x86.h \
capstone/xcore.h \
winghexdisasm.h \
../WingHexExplorer/wing-hex-explorer.sourcecode/WingHexExplorer/plugin/iwingplugin.h \
authordialog.h \
sponsordialog.h
DISTFILES += WingHexDisasm.json
LIBS += $$PWD/capstone/libcapstone.a
RESOURCES += \
resource.qrc
TRANSLATIONS += \
$$PWD/WingHexDisasm.ts
FORMS += \
authordialog.ui \
sponsordialog.ui

BIN
WingHexDisasm.qm Normal file
View File

Binary file not shown.

86
WingHexDisasm.ts Normal file
View File

@ -0,0 +1,86 @@
<?xml version="1.0" encoding="utf-8"?>
<!DOCTYPE TS>
<TS version="2.1" language="zh_CN">
<context>
<name>AuthorDialog</name>
<message>
<location filename="authordialog.ui" line="14"/>
<source>Dialog</source>
<translation>关于作者</translation>
</message>
</context>
<context>
<name>SponsorDialog</name>
<message>
<location filename="sponsordialog.ui" line="14"/>
<source>Dialog</source>
<translation>赞助</translation>
</message>
<message>
<location filename="sponsordialog.ui" line="26"/>
<source>Thanks for sponsor!</source>
<translation>感谢大家的赞助支持！</translation>
</message>
</context>
<context>
<name>WingHexDisasm</name>
<message>
<location filename="winghexdisasm.cpp" line="32"/>
<source>Arch :</source>
<translation>架构：</translation>
</message>
<message>
<location filename="winghexdisasm.cpp" line="45"/>
<source>Mode :</source>
<translation>模式：</translation>
</message>
<message>
<location filename="winghexdisasm.cpp" line="59"/>
<source>DisasmWindow</source>
<translation>反汇编</translation>
</message>
<message>
<location filename="winghexdisasm.cpp" line="61"/>
<location filename="winghexdisasm.cpp" line="108"/>
<source>WingHexDisasm</source>
<translation>羽云反汇编器</translation>
</message>
<message>
<location filename="winghexdisasm.cpp" line="65"/>
<location filename="winghexdisasm.cpp" line="83"/>
<source>Clear</source>
<translation>清空</translation>
</message>
<message>
<location filename="winghexdisasm.cpp" line="63"/>
<location filename="winghexdisasm.cpp" line="81"/>
<source>Disasm</source>
<translation>反汇编</translation>
</message>
<message>
<location filename="winghexdisasm.cpp" line="68"/>
<source>Author</source>
<translation>作者</translation>
</message>
<message>
<location filename="winghexdisasm.cpp" line="72"/>
<source>Sponsor</source>
<translation>赞助</translation>
</message>
<message>
<location filename="winghexdisasm.cpp" line="130"/>
<source>Error: Failed capstone initialization</source>
<translation>【错误】无法初始化 capstone 反汇编引擎</translation>
</message>
<message>
<location filename="winghexdisasm.cpp" line="151"/>
<source>Error: Failed to disassemble given op codes</source>
<translation>【错误】无法对选中字节进行反汇编</translation>
</message>
<message>
<location filename="winghexdisasm.cpp" line="161"/>
<source>No Selection Bytes</source>
<translation>无选择字节！</translation>
</message>
</context>
</TS>

13
authordialog.cpp Normal file
View File

@ -0,0 +1,13 @@
#include "authordialog.h"
#include "ui_authordialog.h"
AuthorDialog::AuthorDialog(QWidget *parent)
: QDialog(parent), ui(new Ui::AuthorDialog) {
ui->setupUi(this);
ui->retranslateUi(this);
auto txtb = ui->txtb;
txtb->setSearchPaths(QStringList({":/", ":/image"}));
txtb->setSource(QUrl("README.md"), QTextDocument::MarkdownResource);
}
AuthorDialog::~AuthorDialog() { delete ui; }

21
authordialog.h Normal file
View File

@ -0,0 +1,21 @@
#ifndef AUTHORDIALOG_H
#define AUTHORDIALOG_H
#include <QDialog>
namespace Ui {
class AuthorDialog;
}
class AuthorDialog : public QDialog {
Q_OBJECT
public:
explicit AuthorDialog(QWidget *parent = nullptr);
~AuthorDialog();
private:
Ui::AuthorDialog *ui;
};
#endif // AUTHORDIALOG_H

56
authordialog.ui Normal file
View File

@ -0,0 +1,56 @@
<?xml version="1.0" encoding="UTF-8"?>
<ui version="4.0">
<class>AuthorDialog</class>
<widget class="QDialog" name="AuthorDialog">
<property name="geometry">
<rect>
<x>0</x>
<y>0</y>
<width>550</width>
<height>600</height>
</rect>
</property>
<property name="windowTitle">
<string>Dialog</string>
</property>
<widget class="QLabel" name="label">
<property name="geometry">
<rect>
<x>200</x>
<y>20</y>
<width>150</width>
<height>150</height>
</rect>
</property>
<property name="text">
<string/>
</property>
<property name="pixmap">
<pixmap resource="resource.qrc">:/img/author.jpg</pixmap>
</property>
<property name="scaledContents">
<bool>true</bool>
</property>
<property name="alignment">
<set>Qt::AlignCenter</set>
</property>
</widget>
<widget class="QTextBrowser" name="txtb">
<property name="geometry">
<rect>
<x>20</x>
<y>190</y>
<width>511</width>
<height>381</height>
</rect>
</property>
<property name="markdown">
<string/>
</property>
</widget>
</widget>
<resources>
<include location="resource.qrc"/>
</resources>
<connections/>
</ui>

990
capstone/arm.h Normal file
View File

@ -0,0 +1,990 @@
#ifndef CAPSTONE_ARM_H
#define CAPSTONE_ARM_H
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
#ifdef __cplusplus
extern "C" {
#endif
#include "platform.h"
#ifdef _MSC_VER
#pragma warning(disable:4201)
#endif
/// ARM shift type
typedef enum arm_shifter {
ARM_SFT_INVALID = 0,
ARM_SFT_ASR, ///< shift with immediate const
ARM_SFT_LSL, ///< shift with immediate const
ARM_SFT_LSR, ///< shift with immediate const
ARM_SFT_ROR, ///< shift with immediate const
ARM_SFT_RRX, ///< shift with immediate const
ARM_SFT_ASR_REG, ///< shift with register
ARM_SFT_LSL_REG, ///< shift with register
ARM_SFT_LSR_REG, ///< shift with register
ARM_SFT_ROR_REG, ///< shift with register
ARM_SFT_RRX_REG, ///< shift with register
} arm_shifter;
/// ARM condition code
typedef enum arm_cc {
ARM_CC_INVALID = 0,
ARM_CC_EQ, ///< Equal Equal
ARM_CC_NE, ///< Not equal Not equal, or unordered
ARM_CC_HS, ///< Carry set >, ==, or unordered
ARM_CC_LO, ///< Carry clear Less than
ARM_CC_MI, ///< Minus, negative Less than
ARM_CC_PL, ///< Plus, positive or zero >, ==, or unordered
ARM_CC_VS, ///< Overflow Unordered
ARM_CC_VC, ///< No overflow Not unordered
ARM_CC_HI, ///< Unsigned higher Greater than, or unordered
ARM_CC_LS, ///< Unsigned lower or same Less than or equal
ARM_CC_GE, ///< Greater than or equal Greater than or equal
ARM_CC_LT, ///< Less than Less than, or unordered
ARM_CC_GT, ///< Greater than Greater than
ARM_CC_LE, ///< Less than or equal <, ==, or unordered
ARM_CC_AL ///< Always (unconditional) Always (unconditional)
} arm_cc;
typedef enum arm_sysreg {
/// Special registers for MSR
ARM_SYSREG_INVALID = 0,
// SPSR* registers can be OR combined
ARM_SYSREG_SPSR_C = 1,
ARM_SYSREG_SPSR_X = 2,
ARM_SYSREG_SPSR_S = 4,
ARM_SYSREG_SPSR_F = 8,
// CPSR* registers can be OR combined
ARM_SYSREG_CPSR_C = 16,
ARM_SYSREG_CPSR_X = 32,
ARM_SYSREG_CPSR_S = 64,
ARM_SYSREG_CPSR_F = 128,
// independent registers
ARM_SYSREG_APSR = 256,
ARM_SYSREG_APSR_G,
ARM_SYSREG_APSR_NZCVQ,
ARM_SYSREG_APSR_NZCVQG,
ARM_SYSREG_IAPSR,
ARM_SYSREG_IAPSR_G,
ARM_SYSREG_IAPSR_NZCVQG,
ARM_SYSREG_IAPSR_NZCVQ,
ARM_SYSREG_EAPSR,
ARM_SYSREG_EAPSR_G,
ARM_SYSREG_EAPSR_NZCVQG,
ARM_SYSREG_EAPSR_NZCVQ,
ARM_SYSREG_XPSR,
ARM_SYSREG_XPSR_G,
ARM_SYSREG_XPSR_NZCVQG,
ARM_SYSREG_XPSR_NZCVQ,
ARM_SYSREG_IPSR,
ARM_SYSREG_EPSR,
ARM_SYSREG_IEPSR,
ARM_SYSREG_MSP,
ARM_SYSREG_PSP,
ARM_SYSREG_PRIMASK,
ARM_SYSREG_BASEPRI,
ARM_SYSREG_BASEPRI_MAX,
ARM_SYSREG_FAULTMASK,
ARM_SYSREG_CONTROL,
ARM_SYSREG_MSPLIM,
ARM_SYSREG_PSPLIM,
ARM_SYSREG_MSP_NS,
ARM_SYSREG_PSP_NS,
ARM_SYSREG_MSPLIM_NS,
ARM_SYSREG_PSPLIM_NS,
ARM_SYSREG_PRIMASK_NS,
ARM_SYSREG_BASEPRI_NS,
ARM_SYSREG_FAULTMASK_NS,
ARM_SYSREG_CONTROL_NS,
ARM_SYSREG_SP_NS,
// Banked Registers
ARM_SYSREG_R8_USR,
ARM_SYSREG_R9_USR,
ARM_SYSREG_R10_USR,
ARM_SYSREG_R11_USR,
ARM_SYSREG_R12_USR,
ARM_SYSREG_SP_USR,
ARM_SYSREG_LR_USR,
ARM_SYSREG_R8_FIQ,
ARM_SYSREG_R9_FIQ,
ARM_SYSREG_R10_FIQ,
ARM_SYSREG_R11_FIQ,
ARM_SYSREG_R12_FIQ,
ARM_SYSREG_SP_FIQ,
ARM_SYSREG_LR_FIQ,
ARM_SYSREG_LR_IRQ,
ARM_SYSREG_SP_IRQ,
ARM_SYSREG_LR_SVC,
ARM_SYSREG_SP_SVC,
ARM_SYSREG_LR_ABT,
ARM_SYSREG_SP_ABT,
ARM_SYSREG_LR_UND,
ARM_SYSREG_SP_UND,
ARM_SYSREG_LR_MON,
ARM_SYSREG_SP_MON,
ARM_SYSREG_ELR_HYP,
ARM_SYSREG_SP_HYP,
ARM_SYSREG_SPSR_FIQ,
ARM_SYSREG_SPSR_IRQ,
ARM_SYSREG_SPSR_SVC,
ARM_SYSREG_SPSR_ABT,
ARM_SYSREG_SPSR_UND,
ARM_SYSREG_SPSR_MON,
ARM_SYSREG_SPSR_HYP,
} arm_sysreg;
/// The memory barrier constants map directly to the 4-bit encoding of
/// the option field for Memory Barrier operations.
typedef enum arm_mem_barrier {
ARM_MB_INVALID = 0,
ARM_MB_RESERVED_0,
ARM_MB_OSHLD,
ARM_MB_OSHST,
ARM_MB_OSH,
ARM_MB_RESERVED_4,
ARM_MB_NSHLD,
ARM_MB_NSHST,
ARM_MB_NSH,
ARM_MB_RESERVED_8,
ARM_MB_ISHLD,
ARM_MB_ISHST,
ARM_MB_ISH,
ARM_MB_RESERVED_12,
ARM_MB_LD,
ARM_MB_ST,
ARM_MB_SY,
} arm_mem_barrier;
/// Operand type for instruction's operands
typedef enum arm_op_type {
ARM_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized).
ARM_OP_REG, ///< = CS_OP_REG (Register operand).
ARM_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
ARM_OP_MEM, ///< = CS_OP_MEM (Memory operand).
ARM_OP_FP, ///< = CS_OP_FP (Floating-Point operand).
ARM_OP_CIMM = 64, ///< C-Immediate (coprocessor registers)
ARM_OP_PIMM, ///< P-Immediate (coprocessor registers)
ARM_OP_SETEND, ///< operand for SETEND instruction
ARM_OP_SYSREG, ///< MSR/MRS special register operand
} arm_op_type;
/// Operand type for SETEND instruction
typedef enum arm_setend_type {
ARM_SETEND_INVALID = 0, ///< Uninitialized.
ARM_SETEND_BE, ///< BE operand.
ARM_SETEND_LE, ///< LE operand
} arm_setend_type;
typedef enum arm_cpsmode_type {
ARM_CPSMODE_INVALID = 0,
ARM_CPSMODE_IE = 2,
ARM_CPSMODE_ID = 3
} arm_cpsmode_type;
/// Operand type for SETEND instruction
typedef enum arm_cpsflag_type {
ARM_CPSFLAG_INVALID = 0,
ARM_CPSFLAG_F = 1,
ARM_CPSFLAG_I = 2,
ARM_CPSFLAG_A = 4,
ARM_CPSFLAG_NONE = 16, ///< no flag
} arm_cpsflag_type;
/// Data type for elements of vector instructions.
typedef enum arm_vectordata_type {
ARM_VECTORDATA_INVALID = 0,
// Integer type
ARM_VECTORDATA_I8,
ARM_VECTORDATA_I16,
ARM_VECTORDATA_I32,
ARM_VECTORDATA_I64,
// Signed integer type
ARM_VECTORDATA_S8,
ARM_VECTORDATA_S16,
ARM_VECTORDATA_S32,
ARM_VECTORDATA_S64,
// Unsigned integer type
ARM_VECTORDATA_U8,
ARM_VECTORDATA_U16,
ARM_VECTORDATA_U32,
ARM_VECTORDATA_U64,
// Data type for VMUL/VMULL
ARM_VECTORDATA_P8,
// Floating type
ARM_VECTORDATA_F16,
ARM_VECTORDATA_F32,
ARM_VECTORDATA_F64,
// Convert float <-> float
ARM_VECTORDATA_F16F64, // f16.f64
ARM_VECTORDATA_F64F16, // f64.f16
ARM_VECTORDATA_F32F16, // f32.f16
ARM_VECTORDATA_F16F32, // f32.f16
ARM_VECTORDATA_F64F32, // f64.f32
ARM_VECTORDATA_F32F64, // f32.f64
// Convert integer <-> float
ARM_VECTORDATA_S32F32, // s32.f32
ARM_VECTORDATA_U32F32, // u32.f32
ARM_VECTORDATA_F32S32, // f32.s32
ARM_VECTORDATA_F32U32, // f32.u32
ARM_VECTORDATA_F64S16, // f64.s16
ARM_VECTORDATA_F32S16, // f32.s16
ARM_VECTORDATA_F64S32, // f64.s32
ARM_VECTORDATA_S16F64, // s16.f64
ARM_VECTORDATA_S16F32, // s16.f64
ARM_VECTORDATA_S32F64, // s32.f64
ARM_VECTORDATA_U16F64, // u16.f64
ARM_VECTORDATA_U16F32, // u16.f32
ARM_VECTORDATA_U32F64, // u32.f64
ARM_VECTORDATA_F64U16, // f64.u16
ARM_VECTORDATA_F32U16, // f32.u16
ARM_VECTORDATA_F64U32, // f64.u32
ARM_VECTORDATA_F16U16, // f16.u16
ARM_VECTORDATA_U16F16, // u16.f16
ARM_VECTORDATA_F16U32, // f16.u32
ARM_VECTORDATA_U32F16, // u32.f16
} arm_vectordata_type;
/// ARM registers
typedef enum arm_reg {
ARM_REG_INVALID = 0,
ARM_REG_APSR,
ARM_REG_APSR_NZCV,
ARM_REG_CPSR,
ARM_REG_FPEXC,
ARM_REG_FPINST,
ARM_REG_FPSCR,
ARM_REG_FPSCR_NZCV,
ARM_REG_FPSID,
ARM_REG_ITSTATE,
ARM_REG_LR,
ARM_REG_PC,
ARM_REG_SP,
ARM_REG_SPSR,
ARM_REG_D0,
ARM_REG_D1,
ARM_REG_D2,
ARM_REG_D3,
ARM_REG_D4,
ARM_REG_D5,
ARM_REG_D6,
ARM_REG_D7,
ARM_REG_D8,
ARM_REG_D9,
ARM_REG_D10,
ARM_REG_D11,
ARM_REG_D12,
ARM_REG_D13,
ARM_REG_D14,
ARM_REG_D15,
ARM_REG_D16,
ARM_REG_D17,
ARM_REG_D18,
ARM_REG_D19,
ARM_REG_D20,
ARM_REG_D21,
ARM_REG_D22,
ARM_REG_D23,
ARM_REG_D24,
ARM_REG_D25,
ARM_REG_D26,
ARM_REG_D27,
ARM_REG_D28,
ARM_REG_D29,
ARM_REG_D30,
ARM_REG_D31,
ARM_REG_FPINST2,
ARM_REG_MVFR0,
ARM_REG_MVFR1,
ARM_REG_MVFR2,
ARM_REG_Q0,
ARM_REG_Q1,
ARM_REG_Q2,
ARM_REG_Q3,
ARM_REG_Q4,
ARM_REG_Q5,
ARM_REG_Q6,
ARM_REG_Q7,
ARM_REG_Q8,
ARM_REG_Q9,
ARM_REG_Q10,
ARM_REG_Q11,
ARM_REG_Q12,
ARM_REG_Q13,
ARM_REG_Q14,
ARM_REG_Q15,
ARM_REG_R0,
ARM_REG_R1,
ARM_REG_R2,
ARM_REG_R3,
ARM_REG_R4,
ARM_REG_R5,
ARM_REG_R6,
ARM_REG_R7,
ARM_REG_R8,
ARM_REG_R9,
ARM_REG_R10,
ARM_REG_R11,
ARM_REG_R12,
ARM_REG_S0,
ARM_REG_S1,
ARM_REG_S2,
ARM_REG_S3,
ARM_REG_S4,
ARM_REG_S5,
ARM_REG_S6,
ARM_REG_S7,
ARM_REG_S8,
ARM_REG_S9,
ARM_REG_S10,
ARM_REG_S11,
ARM_REG_S12,
ARM_REG_S13,
ARM_REG_S14,
ARM_REG_S15,
ARM_REG_S16,
ARM_REG_S17,
ARM_REG_S18,
ARM_REG_S19,
ARM_REG_S20,
ARM_REG_S21,
ARM_REG_S22,
ARM_REG_S23,
ARM_REG_S24,
ARM_REG_S25,
ARM_REG_S26,
ARM_REG_S27,
ARM_REG_S28,
ARM_REG_S29,
ARM_REG_S30,
ARM_REG_S31,
ARM_REG_ENDING, // <-- mark the end of the list or registers
// alias registers
ARM_REG_R13 = ARM_REG_SP,
ARM_REG_R14 = ARM_REG_LR,
ARM_REG_R15 = ARM_REG_PC,
ARM_REG_SB = ARM_REG_R9,
ARM_REG_SL = ARM_REG_R10,
ARM_REG_FP = ARM_REG_R11,
ARM_REG_IP = ARM_REG_R12,
} arm_reg;
/// Instruction's operand referring to memory
/// This is associated with ARM_OP_MEM operand type above
typedef struct arm_op_mem {
arm_reg base; ///< base register
arm_reg index; ///< index register
int scale; ///< scale for index register (can be 1, or -1)
int disp; ///< displacement/offset value
/// left-shift on index register, or 0 if irrelevant
/// NOTE: this value can also be fetched via operand.shift.value
int lshift;
} arm_op_mem;
/// Instruction operand
typedef struct cs_arm_op {
int vector_index; ///< Vector Index for some vector operands (or -1 if irrelevant)
struct {
arm_shifter type;
unsigned int value;
} shift;
arm_op_type type; ///< operand type
union {
int reg; ///< register value for REG/SYSREG operand
int32_t imm; ///< immediate value for C-IMM, P-IMM or IMM operand
double fp; ///< floating point value for FP operand
arm_op_mem mem; ///< base/index/scale/disp value for MEM operand
arm_setend_type setend; ///< SETEND instruction's operand type
};
/// in some instructions, an operand can be subtracted or added to
/// the base register,
/// if TRUE, this operand is subtracted. otherwise, it is added.
bool subtracted;
/// How is this operand accessed? (READ, WRITE or READ|WRITE)
/// This field is combined of cs_ac_type.
/// NOTE: this field is irrelevant if engine is compiled in DIET mode.
uint8_t access;
/// Neon lane index for NEON instructions (or -1 if irrelevant)
int8_t neon_lane;
} cs_arm_op;
/// Instruction structure
typedef struct cs_arm {
bool usermode; ///< User-mode registers to be loaded (for LDM/STM instructions)
int vector_size; ///< Scalar size for vector instructions
arm_vectordata_type vector_data; ///< Data type for elements of vector instructions
arm_cpsmode_type cps_mode; ///< CPS mode for CPS instruction
arm_cpsflag_type cps_flag; ///< CPS mode for CPS instruction
arm_cc cc; ///< conditional code for this insn
bool update_flags; ///< does this insn update flags?
bool writeback; ///< does this insn write-back?
arm_mem_barrier mem_barrier; ///< Option for some memory barrier instructions
/// Number of operands of this instruction,
/// or 0 when instruction has no operand.
uint8_t op_count;
cs_arm_op operands[36]; ///< operands for this instruction.
} cs_arm;
/// ARM instruction
typedef enum arm_insn {
ARM_INS_INVALID = 0,
ARM_INS_ADC,
ARM_INS_ADD,
ARM_INS_ADDW,
ARM_INS_ADR,
ARM_INS_AESD,
ARM_INS_AESE,
ARM_INS_AESIMC,
ARM_INS_AESMC,
ARM_INS_AND,
ARM_INS_ASR,
ARM_INS_B,
ARM_INS_BFC,
ARM_INS_BFI,
ARM_INS_BIC,
ARM_INS_BKPT,
ARM_INS_BL,
ARM_INS_BLX,
ARM_INS_BLXNS,
ARM_INS_BX,
ARM_INS_BXJ,
ARM_INS_BXNS,
ARM_INS_CBNZ,
ARM_INS_CBZ,
ARM_INS_CDP,
ARM_INS_CDP2,
ARM_INS_CLREX,
ARM_INS_CLZ,
ARM_INS_CMN,
ARM_INS_CMP,
ARM_INS_CPS,
ARM_INS_CRC32B,
ARM_INS_CRC32CB,
ARM_INS_CRC32CH,
ARM_INS_CRC32CW,
ARM_INS_CRC32H,
ARM_INS_CRC32W,
ARM_INS_CSDB,
ARM_INS_DBG,
ARM_INS_DCPS1,
ARM_INS_DCPS2,
ARM_INS_DCPS3,
ARM_INS_DFB,
ARM_INS_DMB,
ARM_INS_DSB,
ARM_INS_EOR,
ARM_INS_ERET,
ARM_INS_ESB,
ARM_INS_FADDD,
ARM_INS_FADDS,
ARM_INS_FCMPZD,
ARM_INS_FCMPZS,
ARM_INS_FCONSTD,
ARM_INS_FCONSTS,
ARM_INS_FLDMDBX,
ARM_INS_FLDMIAX,
ARM_INS_FMDHR,
ARM_INS_FMDLR,
ARM_INS_FMSTAT,
ARM_INS_FSTMDBX,
ARM_INS_FSTMIAX,
ARM_INS_FSUBD,
ARM_INS_FSUBS,
ARM_INS_HINT,
ARM_INS_HLT,
ARM_INS_HVC,
ARM_INS_ISB,
ARM_INS_IT,
ARM_INS_LDA,
ARM_INS_LDAB,
ARM_INS_LDAEX,
ARM_INS_LDAEXB,
ARM_INS_LDAEXD,
ARM_INS_LDAEXH,
ARM_INS_LDAH,
ARM_INS_LDC,
ARM_INS_LDC2,
ARM_INS_LDC2L,
ARM_INS_LDCL,
ARM_INS_LDM,
ARM_INS_LDMDA,
ARM_INS_LDMDB,
ARM_INS_LDMIB,
ARM_INS_LDR,
ARM_INS_LDRB,
ARM_INS_LDRBT,
ARM_INS_LDRD,
ARM_INS_LDREX,
ARM_INS_LDREXB,
ARM_INS_LDREXD,
ARM_INS_LDREXH,
ARM_INS_LDRH,
ARM_INS_LDRHT,
ARM_INS_LDRSB,
ARM_INS_LDRSBT,
ARM_INS_LDRSH,
ARM_INS_LDRSHT,
ARM_INS_LDRT,
ARM_INS_LSL,
ARM_INS_LSR,
ARM_INS_MCR,
ARM_INS_MCR2,
ARM_INS_MCRR,
ARM_INS_MCRR2,
ARM_INS_MLA,
ARM_INS_MLS,
ARM_INS_MOV,
ARM_INS_MOVS,
ARM_INS_MOVT,
ARM_INS_MOVW,
ARM_INS_MRC,
ARM_INS_MRC2,
ARM_INS_MRRC,
ARM_INS_MRRC2,
ARM_INS_MRS,
ARM_INS_MSR,
ARM_INS_MUL,
ARM_INS_MVN,
ARM_INS_NEG,
ARM_INS_NOP,
ARM_INS_ORN,
ARM_INS_ORR,
ARM_INS_PKHBT,
ARM_INS_PKHTB,
ARM_INS_PLD,
ARM_INS_PLDW,
ARM_INS_PLI,
ARM_INS_POP,
ARM_INS_PUSH,
ARM_INS_QADD,
ARM_INS_QADD16,
ARM_INS_QADD8,
ARM_INS_QASX,
ARM_INS_QDADD,
ARM_INS_QDSUB,
ARM_INS_QSAX,
ARM_INS_QSUB,
ARM_INS_QSUB16,
ARM_INS_QSUB8,
ARM_INS_RBIT,
ARM_INS_REV,
ARM_INS_REV16,
ARM_INS_REVSH,
ARM_INS_RFEDA,
ARM_INS_RFEDB,
ARM_INS_RFEIA,
ARM_INS_RFEIB,
ARM_INS_ROR,
ARM_INS_RRX,
ARM_INS_RSB,
ARM_INS_RSC,
ARM_INS_SADD16,
ARM_INS_SADD8,
ARM_INS_SASX,
ARM_INS_SBC,
ARM_INS_SBFX,
ARM_INS_SDIV,
ARM_INS_SEL,
ARM_INS_SETEND,
ARM_INS_SETPAN,
ARM_INS_SEV,
ARM_INS_SEVL,
ARM_INS_SG,
ARM_INS_SHA1C,
ARM_INS_SHA1H,
ARM_INS_SHA1M,
ARM_INS_SHA1P,
ARM_INS_SHA1SU0,
ARM_INS_SHA1SU1,
ARM_INS_SHA256H,
ARM_INS_SHA256H2,
ARM_INS_SHA256SU0,
ARM_INS_SHA256SU1,
ARM_INS_SHADD16,
ARM_INS_SHADD8,
ARM_INS_SHASX,
ARM_INS_SHSAX,
ARM_INS_SHSUB16,
ARM_INS_SHSUB8,
ARM_INS_SMC,
ARM_INS_SMLABB,
ARM_INS_SMLABT,
ARM_INS_SMLAD,
ARM_INS_SMLADX,
ARM_INS_SMLAL,
ARM_INS_SMLALBB,
ARM_INS_SMLALBT,
ARM_INS_SMLALD,
ARM_INS_SMLALDX,
ARM_INS_SMLALTB,
ARM_INS_SMLALTT,
ARM_INS_SMLATB,
ARM_INS_SMLATT,
ARM_INS_SMLAWB,
ARM_INS_SMLAWT,
ARM_INS_SMLSD,
ARM_INS_SMLSDX,
ARM_INS_SMLSLD,
ARM_INS_SMLSLDX,
ARM_INS_SMMLA,
ARM_INS_SMMLAR,
ARM_INS_SMMLS,
ARM_INS_SMMLSR,
ARM_INS_SMMUL,
ARM_INS_SMMULR,
ARM_INS_SMUAD,
ARM_INS_SMUADX,
ARM_INS_SMULBB,
ARM_INS_SMULBT,
ARM_INS_SMULL,
ARM_INS_SMULTB,
ARM_INS_SMULTT,
ARM_INS_SMULWB,
ARM_INS_SMULWT,
ARM_INS_SMUSD,
ARM_INS_SMUSDX,
ARM_INS_SRSDA,
ARM_INS_SRSDB,
ARM_INS_SRSIA,
ARM_INS_SRSIB,
ARM_INS_SSAT,
ARM_INS_SSAT16,
ARM_INS_SSAX,
ARM_INS_SSUB16,
ARM_INS_SSUB8,
ARM_INS_STC,
ARM_INS_STC2,
ARM_INS_STC2L,
ARM_INS_STCL,
ARM_INS_STL,
ARM_INS_STLB,
ARM_INS_STLEX,
ARM_INS_STLEXB,
ARM_INS_STLEXD,
ARM_INS_STLEXH,
ARM_INS_STLH,
ARM_INS_STM,
ARM_INS_STMDA,
ARM_INS_STMDB,
ARM_INS_STMIB,
ARM_INS_STR,
ARM_INS_STRB,
ARM_INS_STRBT,
ARM_INS_STRD,
ARM_INS_STREX,
ARM_INS_STREXB,
ARM_INS_STREXD,
ARM_INS_STREXH,
ARM_INS_STRH,
ARM_INS_STRHT,
ARM_INS_STRT,
ARM_INS_SUB,
ARM_INS_SUBS,
ARM_INS_SUBW,
ARM_INS_SVC,
ARM_INS_SWP,
ARM_INS_SWPB,
ARM_INS_SXTAB,
ARM_INS_SXTAB16,
ARM_INS_SXTAH,
ARM_INS_SXTB,
ARM_INS_SXTB16,
ARM_INS_SXTH,
ARM_INS_TBB,
ARM_INS_TBH,
ARM_INS_TEQ,
ARM_INS_TRAP,
ARM_INS_TSB,
ARM_INS_TST,
ARM_INS_TT,
ARM_INS_TTA,
ARM_INS_TTAT,
ARM_INS_TTT,
ARM_INS_UADD16,
ARM_INS_UADD8,
ARM_INS_UASX,
ARM_INS_UBFX,
ARM_INS_UDF,
ARM_INS_UDIV,
ARM_INS_UHADD16,
ARM_INS_UHADD8,
ARM_INS_UHASX,
ARM_INS_UHSAX,
ARM_INS_UHSUB16,
ARM_INS_UHSUB8,
ARM_INS_UMAAL,
ARM_INS_UMLAL,
ARM_INS_UMULL,
ARM_INS_UQADD16,
ARM_INS_UQADD8,
ARM_INS_UQASX,
ARM_INS_UQSAX,
ARM_INS_UQSUB16,
ARM_INS_UQSUB8,
ARM_INS_USAD8,
ARM_INS_USADA8,
ARM_INS_USAT,
ARM_INS_USAT16,
ARM_INS_USAX,
ARM_INS_USUB16,
ARM_INS_USUB8,
ARM_INS_UXTAB,
ARM_INS_UXTAB16,
ARM_INS_UXTAH,
ARM_INS_UXTB,
ARM_INS_UXTB16,
ARM_INS_UXTH,
ARM_INS_VABA,
ARM_INS_VABAL,
ARM_INS_VABD,
ARM_INS_VABDL,
ARM_INS_VABS,
ARM_INS_VACGE,
ARM_INS_VACGT,
ARM_INS_VACLE,
ARM_INS_VACLT,
ARM_INS_VADD,
ARM_INS_VADDHN,
ARM_INS_VADDL,
ARM_INS_VADDW,
ARM_INS_VAND,
ARM_INS_VBIC,
ARM_INS_VBIF,
ARM_INS_VBIT,
ARM_INS_VBSL,
ARM_INS_VCADD,
ARM_INS_VCEQ,
ARM_INS_VCGE,
ARM_INS_VCGT,
ARM_INS_VCLE,
ARM_INS_VCLS,
ARM_INS_VCLT,
ARM_INS_VCLZ,
ARM_INS_VCMLA,
ARM_INS_VCMP,
ARM_INS_VCMPE,
ARM_INS_VCNT,
ARM_INS_VCVT,
ARM_INS_VCVTA,
ARM_INS_VCVTB,
ARM_INS_VCVTM,
ARM_INS_VCVTN,
ARM_INS_VCVTP,
ARM_INS_VCVTR,
ARM_INS_VCVTT,
ARM_INS_VDIV,
ARM_INS_VDUP,
ARM_INS_VEOR,
ARM_INS_VEXT,
ARM_INS_VFMA,
ARM_INS_VFMS,
ARM_INS_VFNMA,
ARM_INS_VFNMS,
ARM_INS_VHADD,
ARM_INS_VHSUB,
ARM_INS_VINS,
ARM_INS_VJCVT,
ARM_INS_VLD1,
ARM_INS_VLD2,
ARM_INS_VLD3,
ARM_INS_VLD4,
ARM_INS_VLDMDB,
ARM_INS_VLDMIA,
ARM_INS_VLDR,
ARM_INS_VLLDM,
ARM_INS_VLSTM,
ARM_INS_VMAX,
ARM_INS_VMAXNM,
ARM_INS_VMIN,
ARM_INS_VMINNM,
ARM_INS_VMLA,
ARM_INS_VMLAL,
ARM_INS_VMLS,
ARM_INS_VMLSL,
ARM_INS_VMOV,
ARM_INS_VMOVL,
ARM_INS_VMOVN,
ARM_INS_VMOVX,
ARM_INS_VMRS,
ARM_INS_VMSR,
ARM_INS_VMUL,
ARM_INS_VMULL,
ARM_INS_VMVN,
ARM_INS_VNEG,
ARM_INS_VNMLA,
ARM_INS_VNMLS,
ARM_INS_VNMUL,
ARM_INS_VORN,
ARM_INS_VORR,
ARM_INS_VPADAL,
ARM_INS_VPADD,
ARM_INS_VPADDL,
ARM_INS_VPMAX,
ARM_INS_VPMIN,
ARM_INS_VPOP,
ARM_INS_VPUSH,
ARM_INS_VQABS,
ARM_INS_VQADD,
ARM_INS_VQDMLAL,
ARM_INS_VQDMLSL,
ARM_INS_VQDMULH,
ARM_INS_VQDMULL,
ARM_INS_VQMOVN,
ARM_INS_VQMOVUN,
ARM_INS_VQNEG,
ARM_INS_VQRDMLAH,
ARM_INS_VQRDMLSH,
ARM_INS_VQRDMULH,
ARM_INS_VQRSHL,
ARM_INS_VQRSHRN,
ARM_INS_VQRSHRUN,
ARM_INS_VQSHL,
ARM_INS_VQSHLU,
ARM_INS_VQSHRN,
ARM_INS_VQSHRUN,
ARM_INS_VQSUB,
ARM_INS_VRADDHN,
ARM_INS_VRECPE,
ARM_INS_VRECPS,
ARM_INS_VREV16,
ARM_INS_VREV32,
ARM_INS_VREV64,
ARM_INS_VRHADD,
ARM_INS_VRINTA,
ARM_INS_VRINTM,
ARM_INS_VRINTN,
ARM_INS_VRINTP,
ARM_INS_VRINTR,
ARM_INS_VRINTX,
ARM_INS_VRINTZ,
ARM_INS_VRSHL,
ARM_INS_VRSHR,
ARM_INS_VRSHRN,
ARM_INS_VRSQRTE,
ARM_INS_VRSQRTS,
ARM_INS_VRSRA,
ARM_INS_VRSUBHN,
ARM_INS_VSDOT,
ARM_INS_VSELEQ,
ARM_INS_VSELGE,
ARM_INS_VSELGT,
ARM_INS_VSELVS,
ARM_INS_VSHL,
ARM_INS_VSHLL,
ARM_INS_VSHR,
ARM_INS_VSHRN,
ARM_INS_VSLI,
ARM_INS_VSQRT,
ARM_INS_VSRA,
ARM_INS_VSRI,
ARM_INS_VST1,
ARM_INS_VST2,
ARM_INS_VST3,
ARM_INS_VST4,
ARM_INS_VSTMDB,
ARM_INS_VSTMIA,
ARM_INS_VSTR,
ARM_INS_VSUB,
ARM_INS_VSUBHN,
ARM_INS_VSUBL,
ARM_INS_VSUBW,
ARM_INS_VSWP,
ARM_INS_VTBL,
ARM_INS_VTBX,
ARM_INS_VTRN,
ARM_INS_VTST,
ARM_INS_VUDOT,
ARM_INS_VUZP,
ARM_INS_VZIP,
ARM_INS_WFE,
ARM_INS_WFI,
ARM_INS_YIELD,
ARM_INS_ENDING, // <-- mark the end of the list of instructions
} arm_insn;
/// Group of ARM instructions
typedef enum arm_insn_group {
ARM_GRP_INVALID = 0, ///< = CS_GRP_INVALID
// Generic groups
// all jump instructions (conditional+direct+indirect jumps)
ARM_GRP_JUMP, ///< = CS_GRP_JUMP
ARM_GRP_CALL, ///< = CS_GRP_CALL
ARM_GRP_INT = 4, ///< = CS_GRP_INT
ARM_GRP_PRIVILEGE = 6, ///< = CS_GRP_PRIVILEGE
ARM_GRP_BRANCH_RELATIVE, ///< = CS_GRP_BRANCH_RELATIVE
// Architecture-specific groups
ARM_GRP_CRYPTO = 128,
ARM_GRP_DATABARRIER,
ARM_GRP_DIVIDE,
ARM_GRP_FPARMV8,
ARM_GRP_MULTPRO,
ARM_GRP_NEON,
ARM_GRP_T2EXTRACTPACK,
ARM_GRP_THUMB2DSP,
ARM_GRP_TRUSTZONE,
ARM_GRP_V4T,
ARM_GRP_V5T,
ARM_GRP_V5TE,
ARM_GRP_V6,
ARM_GRP_V6T2,
ARM_GRP_V7,
ARM_GRP_V8,
ARM_GRP_VFP2,
ARM_GRP_VFP3,
ARM_GRP_VFP4,
ARM_GRP_ARM,
ARM_GRP_MCLASS,
ARM_GRP_NOTMCLASS,
ARM_GRP_THUMB,
ARM_GRP_THUMB1ONLY,
ARM_GRP_THUMB2,
ARM_GRP_PREV8,
ARM_GRP_FPVMLX,
ARM_GRP_MULOPS,
ARM_GRP_CRC,
ARM_GRP_DPVFP,
ARM_GRP_V6M,
ARM_GRP_VIRTUALIZATION,
ARM_GRP_ENDING,
} arm_insn_group;
#ifdef __cplusplus
}
#endif
#endif

2379
capstone/arm64.h Normal file
View File

File diff suppressed because it is too large Load Diff

209
capstone/bpf.h Normal file
View File

@ -0,0 +1,209 @@
/* Capstone Disassembly Engine */
/* BPF Backend by david942j <david942j@gmail.com>, 2019 */
#ifndef CAPSTONE_BPF_H
#define CAPSTONE_BPF_H
#ifdef __cplusplus
extern "C" {
#endif
#include "platform.h"
#ifdef _MSC_VER
#pragma warning(disable:4201)
#endif
/// Operand type for instruction's operands
typedef enum bpf_op_type {
BPF_OP_INVALID = 0,
BPF_OP_REG,
BPF_OP_IMM,
BPF_OP_OFF,
BPF_OP_MEM,
BPF_OP_MMEM, ///< M[k] in cBPF
BPF_OP_MSH, ///< corresponds to cBPF's BPF_MSH mode
BPF_OP_EXT, ///< cBPF's extension (not eBPF)
} bpf_op_type;
/// BPF registers
typedef enum bpf_reg {
BPF_REG_INVALID = 0,
///< cBPF
BPF_REG_A,
BPF_REG_X,
///< eBPF
BPF_REG_R0,
BPF_REG_R1,
BPF_REG_R2,
BPF_REG_R3,
BPF_REG_R4,
BPF_REG_R5,
BPF_REG_R6,
BPF_REG_R7,
BPF_REG_R8,
BPF_REG_R9,
BPF_REG_R10,
BPF_REG_ENDING,
} bpf_reg;
/// Instruction's operand referring to memory
/// This is associated with BPF_OP_MEM operand type above
typedef struct bpf_op_mem {
bpf_reg base; ///< base register
uint32_t disp; ///< offset value
} bpf_op_mem;
typedef enum bpf_ext_type {
BPF_EXT_INVALID = 0,
BPF_EXT_LEN,
} bpf_ext_type;
/// Instruction operand
typedef struct cs_bpf_op {
bpf_op_type type;
union {
uint8_t reg; ///< register value for REG operand
uint64_t imm; ///< immediate value IMM operand
uint32_t off; ///< offset value, used in jump & call
bpf_op_mem mem; ///< base/disp value for MEM operand
/* cBPF only */
uint32_t mmem; ///< M[k] in cBPF
uint32_t msh; ///< corresponds to cBPF's BPF_MSH mode
uint32_t ext; ///< cBPF's extension (not eBPF)
};
/// How is this operand accessed? (READ, WRITE or READ|WRITE)
/// This field is combined of cs_ac_type.
/// NOTE: this field is irrelevant if engine is compiled in DIET mode.
uint8_t access;
} cs_bpf_op;
/// Instruction structure
typedef struct cs_bpf {
uint8_t op_count;
cs_bpf_op operands[4];
} cs_bpf;
/// BPF instruction
typedef enum bpf_insn {
BPF_INS_INVALID = 0,
///< ALU
BPF_INS_ADD,
BPF_INS_SUB,
BPF_INS_MUL,
BPF_INS_DIV,
BPF_INS_OR,
BPF_INS_AND,
BPF_INS_LSH,
BPF_INS_RSH,
BPF_INS_NEG,
BPF_INS_MOD,
BPF_INS_XOR,
BPF_INS_MOV, ///< eBPF only
BPF_INS_ARSH, ///< eBPF only
///< ALU64, eBPF only
BPF_INS_ADD64,
BPF_INS_SUB64,
BPF_INS_MUL64,
BPF_INS_DIV64,
BPF_INS_OR64,
BPF_INS_AND64,
BPF_INS_LSH64,
BPF_INS_RSH64,
BPF_INS_NEG64,
BPF_INS_MOD64,
BPF_INS_XOR64,
BPF_INS_MOV64,
BPF_INS_ARSH64,
///< Byteswap, eBPF only
BPF_INS_LE16,
BPF_INS_LE32,
BPF_INS_LE64,
BPF_INS_BE16,
BPF_INS_BE32,
BPF_INS_BE64,
///< Load
BPF_INS_LDW, ///< eBPF only
BPF_INS_LDH,
BPF_INS_LDB,
BPF_INS_LDDW, ///< eBPF only: load 64-bit imm
BPF_INS_LDXW, ///< eBPF only
BPF_INS_LDXH, ///< eBPF only
BPF_INS_LDXB, ///< eBPF only
BPF_INS_LDXDW, ///< eBPF only
///< Store
BPF_INS_STW, ///< eBPF only
BPF_INS_STH, ///< eBPF only
BPF_INS_STB, ///< eBPF only
BPF_INS_STDW, ///< eBPF only
BPF_INS_STXW, ///< eBPF only
BPF_INS_STXH, ///< eBPF only
BPF_INS_STXB, ///< eBPF only
BPF_INS_STXDW, ///< eBPF only
BPF_INS_XADDW, ///< eBPF only
BPF_INS_XADDDW, ///< eBPF only
///< Jump
BPF_INS_JMP,
BPF_INS_JEQ,
BPF_INS_JGT,
BPF_INS_JGE,
BPF_INS_JSET,
BPF_INS_JNE, ///< eBPF only
BPF_INS_JSGT, ///< eBPF only
BPF_INS_JSGE, ///< eBPF only
BPF_INS_CALL, ///< eBPF only
BPF_INS_CALLX, ///< eBPF only
BPF_INS_EXIT, ///< eBPF only
BPF_INS_JLT, ///< eBPF only
BPF_INS_JLE, ///< eBPF only
BPF_INS_JSLT, ///< eBPF only
BPF_INS_JSLE, ///< eBPF only
///< Return, cBPF only
BPF_INS_RET,
///< Misc, cBPF only
BPF_INS_TAX,
BPF_INS_TXA,
BPF_INS_ENDING,
// alias instructions
BPF_INS_LD = BPF_INS_LDW, ///< cBPF only
BPF_INS_LDX = BPF_INS_LDXW, ///< cBPF only
BPF_INS_ST = BPF_INS_STW, ///< cBPF only
BPF_INS_STX = BPF_INS_STXW, ///< cBPF only
} bpf_insn;
/// Group of BPF instructions
typedef enum bpf_insn_group {
BPF_GRP_INVALID = 0, ///< = CS_GRP_INVALID
BPF_GRP_LOAD,
BPF_GRP_STORE,
BPF_GRP_ALU,
BPF_GRP_JUMP,
BPF_GRP_CALL, ///< eBPF only
BPF_GRP_RETURN,
BPF_GRP_MISC, ///< cBPF only
BPF_GRP_ENDING,
} bpf_insn_group;
#ifdef __cplusplus
}
#endif
#endif

786
capstone/capstone.h Normal file
View File

@ -0,0 +1,786 @@
#ifndef CAPSTONE_ENGINE_H
#define CAPSTONE_ENGINE_H
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2016 */
#ifdef __cplusplus
extern "C" {
#endif
#include <stdarg.h>
#if defined(CAPSTONE_HAS_OSXKERNEL)
#include <libkern/libkern.h>
#else
#include <stdlib.h>
#include <stdio.h>
#endif
#include "platform.h"
#ifdef _MSC_VER
#pragma warning(disable:4201)
#pragma warning(disable:4100)
#define CAPSTONE_API __cdecl
#ifdef CAPSTONE_SHARED
#define CAPSTONE_EXPORT __declspec(dllexport)
#else // defined(CAPSTONE_STATIC)
#define CAPSTONE_EXPORT
#endif
#else
#define CAPSTONE_API
#if (defined(__GNUC__) || defined(__IBMC__)) && !defined(CAPSTONE_STATIC)
#define CAPSTONE_EXPORT __attribute__((visibility("default")))
#else // defined(CAPSTONE_STATIC)
#define CAPSTONE_EXPORT
#endif
#endif
#if (defined(__GNUC__) || defined(__IBMC__))
#define CAPSTONE_DEPRECATED __attribute__((deprecated))
#elif defined(_MSC_VER)
#define CAPSTONE_DEPRECATED __declspec(deprecated)
#else
#pragma message("WARNING: You need to implement CAPSTONE_DEPRECATED for this compiler")
#define CAPSTONE_DEPRECATED
#endif
// Capstone API version
#define CS_API_MAJOR 5
#define CS_API_MINOR 0
// Version for bleeding edge code of the Github's "next" branch.
// Use this if you want the absolutely latest development code.
// This version number will be bumped up whenever we have a new major change.
#define CS_NEXT_VERSION 5
// Capstone package version
#define CS_VERSION_MAJOR CS_API_MAJOR
#define CS_VERSION_MINOR CS_API_MINOR
#define CS_VERSION_EXTRA 0
/// Macro to create combined version which can be compared to
/// result of cs_version() API.
#define CS_MAKE_VERSION(major, minor) ((major << 8) + minor)
/// Maximum size of an instruction mnemonic string.
#define CS_MNEMONIC_SIZE 32
// Handle using with all API
typedef size_t csh;
/// Architecture type
typedef enum cs_arch {
CS_ARCH_ARM = 0, ///< ARM architecture (including Thumb, Thumb-2)
CS_ARCH_ARM64, ///< ARM-64, also called AArch64
CS_ARCH_MIPS, ///< Mips architecture
CS_ARCH_X86, ///< X86 architecture (including x86 & x86-64)
CS_ARCH_PPC, ///< PowerPC architecture
CS_ARCH_SPARC, ///< Sparc architecture
CS_ARCH_SYSZ, ///< SystemZ architecture
CS_ARCH_XCORE, ///< XCore architecture
CS_ARCH_M68K, ///< 68K architecture
CS_ARCH_TMS320C64X, ///< TMS320C64x architecture
CS_ARCH_M680X, ///< 680X architecture
CS_ARCH_EVM, ///< Ethereum architecture
CS_ARCH_MOS65XX, ///< MOS65XX architecture (including MOS6502)
CS_ARCH_WASM, ///< WebAssembly architecture
CS_ARCH_BPF, ///< Berkeley Packet Filter architecture (including eBPF)
CS_ARCH_RISCV, ///< RISCV architecture
CS_ARCH_MAX,
CS_ARCH_ALL = 0xFFFF, // All architectures - for cs_support()
} cs_arch;
// Support value to verify diet mode of the engine.
// If cs_support(CS_SUPPORT_DIET) return True, the engine was compiled
// in diet mode.
#define CS_SUPPORT_DIET (CS_ARCH_ALL + 1)
// Support value to verify X86 reduce mode of the engine.
// If cs_support(CS_SUPPORT_X86_REDUCE) return True, the engine was compiled
// in X86 reduce mode.
#define CS_SUPPORT_X86_REDUCE (CS_ARCH_ALL + 2)
/// Mode type
typedef enum cs_mode {
CS_MODE_LITTLE_ENDIAN = 0, ///< little-endian mode (default mode)
CS_MODE_ARM = 0, ///< 32-bit ARM
CS_MODE_16 = 1 << 1, ///< 16-bit mode (X86)
CS_MODE_32 = 1 << 2, ///< 32-bit mode (X86)
CS_MODE_64 = 1 << 3, ///< 64-bit mode (X86, PPC)
CS_MODE_THUMB = 1 << 4, ///< ARM's Thumb mode, including Thumb-2
CS_MODE_MCLASS = 1 << 5, ///< ARM's Cortex-M series
CS_MODE_V8 = 1 << 6, ///< ARMv8 A32 encodings for ARM
CS_MODE_MICRO = 1 << 4, ///< MicroMips mode (MIPS)
CS_MODE_MIPS3 = 1 << 5, ///< Mips III ISA
CS_MODE_MIPS32R6 = 1 << 6, ///< Mips32r6 ISA
CS_MODE_MIPS2 = 1 << 7, ///< Mips II ISA
CS_MODE_V9 = 1 << 4, ///< SparcV9 mode (Sparc)
CS_MODE_QPX = 1 << 4, ///< Quad Processing eXtensions mode (PPC)
CS_MODE_SPE = 1 << 5, ///< Signal Processing Engine mode (PPC)
CS_MODE_BOOKE = 1 << 6, ///< Book-E mode (PPC)
CS_MODE_PS = 1 << 7, ///< Paired-singles mode (PPC)
CS_MODE_M68K_000 = 1 << 1, ///< M68K 68000 mode
CS_MODE_M68K_010 = 1 << 2, ///< M68K 68010 mode
CS_MODE_M68K_020 = 1 << 3, ///< M68K 68020 mode
CS_MODE_M68K_030 = 1 << 4, ///< M68K 68030 mode
CS_MODE_M68K_040 = 1 << 5, ///< M68K 68040 mode
CS_MODE_M68K_060 = 1 << 6, ///< M68K 68060 mode
CS_MODE_BIG_ENDIAN = 1U << 31, ///< big-endian mode
CS_MODE_MIPS32 = CS_MODE_32, ///< Mips32 ISA (Mips)
CS_MODE_MIPS64 = CS_MODE_64, ///< Mips64 ISA (Mips)
CS_MODE_M680X_6301 = 1 << 1, ///< M680X Hitachi 6301,6303 mode
CS_MODE_M680X_6309 = 1 << 2, ///< M680X Hitachi 6309 mode
CS_MODE_M680X_6800 = 1 << 3, ///< M680X Motorola 6800,6802 mode
CS_MODE_M680X_6801 = 1 << 4, ///< M680X Motorola 6801,6803 mode
CS_MODE_M680X_6805 = 1 << 5, ///< M680X Motorola/Freescale 6805 mode
CS_MODE_M680X_6808 = 1 << 6, ///< M680X Motorola/Freescale/NXP 68HC08 mode
CS_MODE_M680X_6809 = 1 << 7, ///< M680X Motorola 6809 mode
CS_MODE_M680X_6811 = 1 << 8, ///< M680X Motorola/Freescale/NXP 68HC11 mode
CS_MODE_M680X_CPU12 = 1 << 9, ///< M680X Motorola/Freescale/NXP CPU12
///< used on M68HC12/HCS12
CS_MODE_M680X_HCS08 = 1 << 10, ///< M680X Freescale/NXP HCS08 mode
CS_MODE_BPF_CLASSIC = 0, ///< Classic BPF mode (default)
CS_MODE_BPF_EXTENDED = 1 << 0, ///< Extended BPF mode
CS_MODE_RISCV32 = 1 << 0, ///< RISCV RV32G
CS_MODE_RISCV64 = 1 << 1, ///< RISCV RV64G
CS_MODE_RISCVC = 1 << 2, ///< RISCV compressed instructure mode
CS_MODE_MOS65XX_6502 = 1 << 1, ///< MOS65XXX MOS 6502
CS_MODE_MOS65XX_65C02 = 1 << 2, ///< MOS65XXX WDC 65c02
CS_MODE_MOS65XX_W65C02 = 1 << 3, ///< MOS65XXX WDC W65c02
CS_MODE_MOS65XX_65816 = 1 << 4, ///< MOS65XXX WDC 65816, 8-bit m/x
CS_MODE_MOS65XX_65816_LONG_M = (1 << 5), ///< MOS65XXX WDC 65816, 16-bit m, 8-bit x
CS_MODE_MOS65XX_65816_LONG_X = (1 << 6), ///< MOS65XXX WDC 65816, 8-bit m, 16-bit x
CS_MODE_MOS65XX_65816_LONG_MX = CS_MODE_MOS65XX_65816_LONG_M | CS_MODE_MOS65XX_65816_LONG_X,
} cs_mode;
typedef void* (CAPSTONE_API *cs_malloc_t)(size_t size);
typedef void* (CAPSTONE_API *cs_calloc_t)(size_t nmemb, size_t size);
typedef void* (CAPSTONE_API *cs_realloc_t)(void *ptr, size_t size);
typedef void (CAPSTONE_API *cs_free_t)(void *ptr);
typedef int (CAPSTONE_API *cs_vsnprintf_t)(char *str, size_t size, const char *format, va_list ap);
/// User-defined dynamic memory related functions: malloc/calloc/realloc/free/vsnprintf()
/// By default, Capstone uses system's malloc(), calloc(), realloc(), free() & vsnprintf().
typedef struct cs_opt_mem {
cs_malloc_t malloc;
cs_calloc_t calloc;
cs_realloc_t realloc;
cs_free_t free;
cs_vsnprintf_t vsnprintf;
} cs_opt_mem;
/// Customize mnemonic for instructions with alternative name.
/// To reset existing customized instruction to its default mnemonic,
/// call cs_option(CS_OPT_MNEMONIC) again with the same @id and NULL value
/// for @mnemonic.
typedef struct cs_opt_mnem {
/// ID of instruction to be customized.
unsigned int id;
/// Customized instruction mnemonic.
const char *mnemonic;
} cs_opt_mnem;
/// Runtime option for the disassembled engine
typedef enum cs_opt_type {
CS_OPT_INVALID = 0, ///< No option specified
CS_OPT_SYNTAX, ///< Assembly output syntax
CS_OPT_DETAIL, ///< Break down instruction structure into details
CS_OPT_MODE, ///< Change engine's mode at run-time
CS_OPT_MEM, ///< User-defined dynamic memory related functions
CS_OPT_SKIPDATA, ///< Skip data when disassembling. Then engine is in SKIPDATA mode.
CS_OPT_SKIPDATA_SETUP, ///< Setup user-defined function for SKIPDATA option
CS_OPT_MNEMONIC, ///< Customize instruction mnemonic
CS_OPT_UNSIGNED, ///< print immediate operands in unsigned form
} cs_opt_type;
/// Runtime option value (associated with option type above)
typedef enum cs_opt_value {
CS_OPT_OFF = 0, ///< Turn OFF an option - default for CS_OPT_DETAIL, CS_OPT_SKIPDATA, CS_OPT_UNSIGNED.
CS_OPT_ON = 3, ///< Turn ON an option (CS_OPT_DETAIL, CS_OPT_SKIPDATA).
CS_OPT_SYNTAX_DEFAULT = 0, ///< Default asm syntax (CS_OPT_SYNTAX).
CS_OPT_SYNTAX_INTEL, ///< X86 Intel asm syntax - default on X86 (CS_OPT_SYNTAX).
CS_OPT_SYNTAX_ATT, ///< X86 ATT asm syntax (CS_OPT_SYNTAX).
CS_OPT_SYNTAX_NOREGNAME, ///< Prints register name with only number (CS_OPT_SYNTAX)
CS_OPT_SYNTAX_MASM, ///< X86 Intel Masm syntax (CS_OPT_SYNTAX).
CS_OPT_SYNTAX_MOTOROLA, ///< MOS65XX use $ as hex prefix
} cs_opt_value;
/// Common instruction operand types - to be consistent across all architectures.
typedef enum cs_op_type {
CS_OP_INVALID = 0, ///< uninitialized/invalid operand.
CS_OP_REG, ///< Register operand.
CS_OP_IMM, ///< Immediate operand.
CS_OP_MEM, ///< Memory operand.
CS_OP_FP, ///< Floating-Point operand.
} cs_op_type;
/// Common instruction operand access types - to be consistent across all architectures.
/// It is possible to combine access types, for example: CS_AC_READ | CS_AC_WRITE
typedef enum cs_ac_type {
CS_AC_INVALID = 0, ///< Uninitialized/invalid access type.
CS_AC_READ = 1 << 0, ///< Operand read from memory or register.
CS_AC_WRITE = 1 << 1, ///< Operand write to memory or register.
} cs_ac_type;
/// Common instruction groups - to be consistent across all architectures.
typedef enum cs_group_type {
CS_GRP_INVALID = 0, ///< uninitialized/invalid group.
CS_GRP_JUMP, ///< all jump instructions (conditional+direct+indirect jumps)
CS_GRP_CALL, ///< all call instructions
CS_GRP_RET, ///< all return instructions
CS_GRP_INT, ///< all interrupt instructions (int+syscall)
CS_GRP_IRET, ///< all interrupt return instructions
CS_GRP_PRIVILEGE, ///< all privileged instructions
CS_GRP_BRANCH_RELATIVE, ///< all relative branching instructions
} cs_group_type;
/**
User-defined callback function for SKIPDATA option.
See tests/test_skipdata.c for sample code demonstrating this API.
@code: the input buffer containing code to be disassembled.
This is the same buffer passed to cs_disasm().
@code_size: size (in bytes) of the above @code buffer.
@offset: the position of the currently-examining byte in the input
buffer @code mentioned above.
@user_data: user-data passed to cs_option() via @user_data field in
cs_opt_skipdata struct below.
@return: return number of bytes to skip, or 0 to immediately stop disassembling.
*/
typedef size_t (CAPSTONE_API *cs_skipdata_cb_t)(const uint8_t *code, size_t code_size, size_t offset, void *user_data);
/// User-customized setup for SKIPDATA option
typedef struct cs_opt_skipdata {
/// Capstone considers data to skip as special "instructions".
/// User can specify the string for this instruction's "mnemonic" here.
/// By default (if @mnemonic is NULL), Capstone use ".byte".
const char *mnemonic;
/// User-defined callback function to be called when Capstone hits data.
/// If the returned value from this callback is positive (>0), Capstone
/// will skip exactly that number of bytes & continue. Otherwise, if
/// the callback returns 0, Capstone stops disassembling and returns
/// immediately from cs_disasm()
/// NOTE: if this callback pointer is NULL, Capstone would skip a number
/// of bytes depending on architectures, as following:
/// Arm: 2 bytes (Thumb mode) or 4 bytes.
/// Arm64: 4 bytes.
/// Mips: 4 bytes.
/// M680x: 1 byte.
/// PowerPC: 4 bytes.
/// Sparc: 4 bytes.
/// SystemZ: 2 bytes.
/// X86: 1 bytes.
/// XCore: 2 bytes.
/// EVM: 1 bytes.
/// RISCV: 4 bytes.
/// WASM: 1 bytes.
/// MOS65XX: 1 bytes.
/// BPF: 8 bytes.
cs_skipdata_cb_t callback; // default value is NULL
/// User-defined data to be passed to @callback function pointer.
void *user_data;
} cs_opt_skipdata;
#include "arm.h"
#include "arm64.h"
#include "m68k.h"
#include "mips.h"
#include "ppc.h"
#include "sparc.h"
#include "systemz.h"
#include "x86.h"
#include "xcore.h"
#include "tms320c64x.h"
#include "m680x.h"
#include "evm.h"
#include "riscv.h"
#include "wasm.h"
#include "mos65xx.h"
#include "bpf.h"
/// NOTE: All information in cs_detail is only available when CS_OPT_DETAIL = CS_OPT_ON
/// Initialized as memset(., 0, offsetof(cs_detail, ARCH)+sizeof(cs_ARCH))
/// by ARCH_getInstruction in arch/ARCH/ARCHDisassembler.c
/// if cs_detail changes, in particular if a field is added after the union,
/// then update arch/ARCH/ARCHDisassembler.c accordingly
typedef struct cs_detail {
uint16_t regs_read[16]; ///< list of implicit registers read by this insn
uint8_t regs_read_count; ///< number of implicit registers read by this insn
uint16_t regs_write[20]; ///< list of implicit registers modified by this insn
uint8_t regs_write_count; ///< number of implicit registers modified by this insn
uint8_t groups[8]; ///< list of group this instruction belong to
uint8_t groups_count; ///< number of groups this insn belongs to
/// Architecture-specific instruction info
union {
cs_x86 x86; ///< X86 architecture, including 16-bit, 32-bit & 64-bit mode
cs_arm64 arm64; ///< ARM64 architecture (aka AArch64)
cs_arm arm; ///< ARM architecture (including Thumb/Thumb2)
cs_m68k m68k; ///< M68K architecture
cs_mips mips; ///< MIPS architecture
cs_ppc ppc; ///< PowerPC architecture
cs_sparc sparc; ///< Sparc architecture
cs_sysz sysz; ///< SystemZ architecture
cs_xcore xcore; ///< XCore architecture
cs_tms320c64x tms320c64x; ///< TMS320C64x architecture
cs_m680x m680x; ///< M680X architecture
cs_evm evm; ///< Ethereum architecture
cs_mos65xx mos65xx; ///< MOS65XX architecture (including MOS6502)
cs_wasm wasm; ///< Web Assembly architecture
cs_bpf bpf; ///< Berkeley Packet Filter architecture (including eBPF)
cs_riscv riscv; ///< RISCV architecture
};
} cs_detail;
/// Detail information of disassembled instruction
typedef struct cs_insn {
/// Instruction ID (basically a numeric ID for the instruction mnemonic)
/// Find the instruction id in the '[ARCH]_insn' enum in the header file
/// of corresponding architecture, such as 'arm_insn' in arm.h for ARM,
/// 'x86_insn' in x86.h for X86, etc...
/// This information is available even when CS_OPT_DETAIL = CS_OPT_OFF
/// NOTE: in Skipdata mode, "data" instruction has 0 for this id field.
unsigned int id;
/// Address (EIP) of this instruction
/// This information is available even when CS_OPT_DETAIL = CS_OPT_OFF
uint64_t address;
/// Size of this instruction
/// This information is available even when CS_OPT_DETAIL = CS_OPT_OFF
uint16_t size;
/// Machine bytes of this instruction, with number of bytes indicated by @size above
/// This information is available even when CS_OPT_DETAIL = CS_OPT_OFF
uint8_t bytes[24];
/// Ascii text of instruction mnemonic
/// This information is available even when CS_OPT_DETAIL = CS_OPT_OFF
char mnemonic[CS_MNEMONIC_SIZE];
/// Ascii text of instruction operands
/// This information is available even when CS_OPT_DETAIL = CS_OPT_OFF
char op_str[160];
/// Pointer to cs_detail.
/// NOTE: detail pointer is only valid when both requirements below are met:
/// (1) CS_OP_DETAIL = CS_OPT_ON
/// (2) Engine is not in Skipdata mode (CS_OP_SKIPDATA option set to CS_OPT_ON)
///
/// NOTE 2: when in Skipdata mode, or when detail mode is OFF, even if this pointer
/// is not NULL, its content is still irrelevant.
cs_detail *detail;
} cs_insn;
/// Calculate the offset of a disassembled instruction in its buffer, given its position
/// in its array of disassembled insn
/// NOTE: this macro works with position (>=1), not index
#define CS_INSN_OFFSET(insns, post) (insns[post - 1].address - insns[0].address)
/// All type of errors encountered by Capstone API.
/// These are values returned by cs_errno()
typedef enum cs_err {
CS_ERR_OK = 0, ///< No error: everything was fine
CS_ERR_MEM, ///< Out-Of-Memory error: cs_open(), cs_disasm(), cs_disasm_iter()
CS_ERR_ARCH, ///< Unsupported architecture: cs_open()
CS_ERR_HANDLE, ///< Invalid handle: cs_op_count(), cs_op_index()
CS_ERR_CSH, ///< Invalid csh argument: cs_close(), cs_errno(), cs_option()
CS_ERR_MODE, ///< Invalid/unsupported mode: cs_open()
CS_ERR_OPTION, ///< Invalid/unsupported option: cs_option()
CS_ERR_DETAIL, ///< Information is unavailable because detail option is OFF
CS_ERR_MEMSETUP, ///< Dynamic memory management uninitialized (see CS_OPT_MEM)
CS_ERR_VERSION, ///< Unsupported version (bindings)
CS_ERR_DIET, ///< Access irrelevant data in "diet" engine
CS_ERR_SKIPDATA, ///< Access irrelevant data for "data" instruction in SKIPDATA mode
CS_ERR_X86_ATT, ///< X86 AT&T syntax is unsupported (opt-out at compile time)
CS_ERR_X86_INTEL, ///< X86 Intel syntax is unsupported (opt-out at compile time)
CS_ERR_X86_MASM, ///< X86 Masm syntax is unsupported (opt-out at compile time)
} cs_err;
/**
Return combined API version & major and minor version numbers.
@major: major number of API version
@minor: minor number of API version
@return hexical number as (major << 8 | minor), which encodes both
major & minor versions.
NOTE: This returned value can be compared with version number made
with macro CS_MAKE_VERSION
For example, second API version would return 1 in @major, and 1 in @minor
The return value would be 0x0101
NOTE: if you only care about returned value, but not major and minor values,
set both @major & @minor arguments to NULL.
*/
CAPSTONE_EXPORT
unsigned int CAPSTONE_API cs_version(int *major, int *minor);
/**
This API can be used to either ask for archs supported by this library,
or check to see if the library was compile with 'diet' option (or called
in 'diet' mode).
To check if a particular arch is supported by this library, set @query to
arch mode (CS_ARCH_* value).
To verify if this library supports all the archs, use CS_ARCH_ALL.
To check if this library is in 'diet' mode, set @query to CS_SUPPORT_DIET.
@return True if this library supports the given arch, or in 'diet' mode.
*/
CAPSTONE_EXPORT
bool CAPSTONE_API cs_support(int query);
/**
Initialize CS handle: this must be done before any usage of CS.
@arch: architecture type (CS_ARCH_*)
@mode: hardware mode. This is combined of CS_MODE_*
@handle: pointer to handle, which will be updated at return time
@return CS_ERR_OK on success, or other value on failure (refer to cs_err enum
for detailed error).
*/
CAPSTONE_EXPORT
cs_err CAPSTONE_API cs_open(cs_arch arch, cs_mode mode, csh *handle);
/**
Close CS handle: MUST do to release the handle when it is not used anymore.
NOTE: this must be only called when there is no longer usage of Capstone,
not even access to cs_insn array. The reason is the this API releases some
cached memory, thus access to any Capstone API after cs_close() might crash
your application.
In fact,this API invalidate @handle by ZERO out its value (i.e *handle = 0).
@handle: pointer to a handle returned by cs_open()
@return CS_ERR_OK on success, or other value on failure (refer to cs_err enum
for detailed error).
*/
CAPSTONE_EXPORT
cs_err CAPSTONE_API cs_close(csh *handle);
/**
Set option for disassembling engine at runtime
@handle: handle returned by cs_open()
@type: type of option to be set
@value: option value corresponding with @type
@return: CS_ERR_OK on success, or other value on failure.
Refer to cs_err enum for detailed error.
NOTE: in the case of CS_OPT_MEM, handle's value can be anything,
so that cs_option(handle, CS_OPT_MEM, value) can (i.e must) be called
even before cs_open()
*/
CAPSTONE_EXPORT
cs_err CAPSTONE_API cs_option(csh handle, cs_opt_type type, size_t value);
/**
Report the last error number when some API function fail.
Like glibc's errno, cs_errno might not retain its old value once accessed.
@handle: handle returned by cs_open()
@return: error code of cs_err enum type (CS_ERR_*, see above)
*/
CAPSTONE_EXPORT
cs_err CAPSTONE_API cs_errno(csh handle);
/**
Return a string describing given error code.
@code: error code (see CS_ERR_* above)
@return: returns a pointer to a string that describes the error code
passed in the argument @code
*/
CAPSTONE_EXPORT
const char * CAPSTONE_API cs_strerror(cs_err code);
/**
Disassemble binary code, given the code buffer, size, address and number
of instructions to be decoded.
This API dynamically allocate memory to contain disassembled instruction.
Resulting instructions will be put into @*insn
NOTE 1: this API will automatically determine memory needed to contain
output disassembled instructions in @insn.
NOTE 2: caller must free the allocated memory itself to avoid memory leaking.
NOTE 3: for system with scarce memory to be dynamically allocated such as
OS kernel or firmware, the API cs_disasm_iter() might be a better choice than
cs_disasm(). The reason is that with cs_disasm(), based on limited available
memory, we have to calculate in advance how many instructions to be disassembled,
which complicates things. This is especially troublesome for the case @count=0,
when cs_disasm() runs uncontrollably (until either end of input buffer, or
when it encounters an invalid instruction).
@handle: handle returned by cs_open()
@code: buffer containing raw binary code to be disassembled.
@code_size: size of the above code buffer.
@address: address of the first instruction in given raw code buffer.
@insn: array of instructions filled in by this API.
NOTE: @insn will be allocated by this function, and should be freed
with cs_free() API.
@count: number of instructions to be disassembled, or 0 to get all of them
@return: the number of successfully disassembled instructions,
or 0 if this function failed to disassemble the given code
On failure, call cs_errno() for error code.
*/
CAPSTONE_EXPORT
size_t CAPSTONE_API cs_disasm(csh handle,
const uint8_t *code, size_t code_size,
uint64_t address,
size_t count,
cs_insn **insn);
/**
Free memory allocated by cs_malloc() or cs_disasm() (argument @insn)
@insn: pointer returned by @insn argument in cs_disasm() or cs_malloc()
@count: number of cs_insn structures returned by cs_disasm(), or 1
to free memory allocated by cs_malloc().
*/
CAPSTONE_EXPORT
void CAPSTONE_API cs_free(cs_insn *insn, size_t count);
/**
Allocate memory for 1 instruction to be used by cs_disasm_iter().
@handle: handle returned by cs_open()
NOTE: when no longer in use, you can reclaim the memory allocated for
this instruction with cs_free(insn, 1)
*/
CAPSTONE_EXPORT
cs_insn * CAPSTONE_API cs_malloc(csh handle);
/**
Fast API to disassemble binary code, given the code buffer, size, address
and number of instructions to be decoded.
This API puts the resulting instruction into a given cache in @insn.
See tests/test_iter.c for sample code demonstrating this API.
NOTE 1: this API will update @code, @size & @address to point to the next
instruction in the input buffer. Therefore, it is convenient to use
cs_disasm_iter() inside a loop to quickly iterate all the instructions.
While decoding one instruction at a time can also be achieved with
cs_disasm(count=1), some benchmarks shown that cs_disasm_iter() can be 30%
faster on random input.
NOTE 2: the cache in @insn can be created with cs_malloc() API.
NOTE 3: for system with scarce memory to be dynamically allocated such as
OS kernel or firmware, this API is recommended over cs_disasm(), which
allocates memory based on the number of instructions to be disassembled.
The reason is that with cs_disasm(), based on limited available memory,
we have to calculate in advance how many instructions to be disassembled,
which complicates things. This is especially troublesome for the case
@count=0, when cs_disasm() runs uncontrollably (until either end of input
buffer, or when it encounters an invalid instruction).
@handle: handle returned by cs_open()
@code: buffer containing raw binary code to be disassembled
@size: size of above code
@address: address of the first insn in given raw code buffer
@insn: pointer to instruction to be filled in by this API.
@return: true if this API successfully decode 1 instruction,
or false otherwise.
On failure, call cs_errno() for error code.
*/
CAPSTONE_EXPORT
bool CAPSTONE_API cs_disasm_iter(csh handle,
const uint8_t **code, size_t *size,
uint64_t *address, cs_insn *insn);
/**
Return friendly name of register in a string.
Find the instruction id from header file of corresponding architecture (arm.h for ARM,
x86.h for X86, ...)
WARN: when in 'diet' mode, this API is irrelevant because engine does not
store register name.
@handle: handle returned by cs_open()
@reg_id: register id
@return: string name of the register, or NULL if @reg_id is invalid.
*/
CAPSTONE_EXPORT
const char * CAPSTONE_API cs_reg_name(csh handle, unsigned int reg_id);
/**
Return friendly name of an instruction in a string.
Find the instruction id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)
WARN: when in 'diet' mode, this API is irrelevant because the engine does not
store instruction name.
@handle: handle returned by cs_open()
@insn_id: instruction id
@return: string name of the instruction, or NULL if @insn_id is invalid.
*/
CAPSTONE_EXPORT
const char * CAPSTONE_API cs_insn_name(csh handle, unsigned int insn_id);
/**
Return friendly name of a group id (that an instruction can belong to)
Find the group id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)
WARN: when in 'diet' mode, this API is irrelevant because the engine does not
store group name.
@handle: handle returned by cs_open()
@group_id: group id
@return: string name of the group, or NULL if @group_id is invalid.
*/
CAPSTONE_EXPORT
const char * CAPSTONE_API cs_group_name(csh handle, unsigned int group_id);
/**
Check if a disassembled instruction belong to a particular group.
Find the group id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)
Internally, this simply verifies if @group_id matches any member of insn->groups array.
NOTE: this API is only valid when detail option is ON (which is OFF by default).
WARN: when in 'diet' mode, this API is irrelevant because the engine does not
update @groups array.
@handle: handle returned by cs_open()
@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()
@group_id: group that you want to check if this instruction belong to.
@return: true if this instruction indeed belongs to the given group, or false otherwise.
*/
CAPSTONE_EXPORT
bool CAPSTONE_API cs_insn_group(csh handle, const cs_insn *insn, unsigned int group_id);
/**
Check if a disassembled instruction IMPLICITLY used a particular register.
Find the register id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)
Internally, this simply verifies if @reg_id matches any member of insn->regs_read array.
NOTE: this API is only valid when detail option is ON (which is OFF by default)
WARN: when in 'diet' mode, this API is irrelevant because the engine does not
update @regs_read array.
@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()
@reg_id: register that you want to check if this instruction used it.
@return: true if this instruction indeed implicitly used the given register, or false otherwise.
*/
CAPSTONE_EXPORT
bool CAPSTONE_API cs_reg_read(csh handle, const cs_insn *insn, unsigned int reg_id);
/**
Check if a disassembled instruction IMPLICITLY modified a particular register.
Find the register id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)
Internally, this simply verifies if @reg_id matches any member of insn->regs_write array.
NOTE: this API is only valid when detail option is ON (which is OFF by default)
WARN: when in 'diet' mode, this API is irrelevant because the engine does not
update @regs_write array.
@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()
@reg_id: register that you want to check if this instruction modified it.
@return: true if this instruction indeed implicitly modified the given register, or false otherwise.
*/
CAPSTONE_EXPORT
bool CAPSTONE_API cs_reg_write(csh handle, const cs_insn *insn, unsigned int reg_id);
/**
Count the number of operands of a given type.
Find the operand type in header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)
NOTE: this API is only valid when detail option is ON (which is OFF by default)
@handle: handle returned by cs_open()
@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()
@op_type: Operand type to be found.
@return: number of operands of given type @op_type in instruction @insn,
or -1 on failure.
*/
CAPSTONE_EXPORT
int CAPSTONE_API cs_op_count(csh handle, const cs_insn *insn, unsigned int op_type);
/**
Retrieve the position of operand of given type in <arch>.operands[] array.
Later, the operand can be accessed using the returned position.
Find the operand type in header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)
NOTE: this API is only valid when detail option is ON (which is OFF by default)
@handle: handle returned by cs_open()
@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()
@op_type: Operand type to be found.
@position: position of the operand to be found. This must be in the range
[1, cs_op_count(handle, insn, op_type)]
@return: index of operand of given type @op_type in <arch>.operands[] array
in instruction @insn, or -1 on failure.
*/
CAPSTONE_EXPORT
int CAPSTONE_API cs_op_index(csh handle, const cs_insn *insn, unsigned int op_type,
unsigned int position);
/// Type of array to keep the list of registers
typedef uint16_t cs_regs[64];
/**
Retrieve all the registers accessed by an instruction, either explicitly or
implicitly.
WARN: when in 'diet' mode, this API is irrelevant because engine does not
store registers.
@handle: handle returned by cs_open()
@insn: disassembled instruction structure returned from cs_disasm() or cs_disasm_iter()
@regs_read: on return, this array contains all registers read by instruction.
@regs_read_count: number of registers kept inside @regs_read array.
@regs_write: on return, this array contains all registers written by instruction.
@regs_write_count: number of registers kept inside @regs_write array.
@return CS_ERR_OK on success, or other value on failure (refer to cs_err enum
for detailed error).
*/
CAPSTONE_EXPORT
cs_err CAPSTONE_API cs_regs_access(csh handle, const cs_insn *insn,
cs_regs regs_read, uint8_t *regs_read_count,
cs_regs regs_write, uint8_t *regs_write_count);
#ifdef __cplusplus
}
#endif
#endif

188
capstone/evm.h Normal file
View File

@ -0,0 +1,188 @@
#ifndef CAPSTONE_EVM_H
#define CAPSTONE_EVM_H
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2018 */
#ifdef __cplusplus
extern "C" {
#endif
#include "platform.h"
#ifdef _MSC_VER
#pragma warning(disable:4201)
#endif
/// Instruction structure
typedef struct cs_evm {
unsigned char pop; ///< number of items popped from the stack
unsigned char push; ///< number of items pushed into the stack
unsigned int fee; ///< gas fee for the instruction
} cs_evm;
/// EVM instruction
typedef enum evm_insn {
EVM_INS_STOP = 0,
EVM_INS_ADD = 1,
EVM_INS_MUL = 2,
EVM_INS_SUB = 3,
EVM_INS_DIV = 4,
EVM_INS_SDIV = 5,
EVM_INS_MOD = 6,
EVM_INS_SMOD = 7,
EVM_INS_ADDMOD = 8,
EVM_INS_MULMOD = 9,
EVM_INS_EXP = 10,
EVM_INS_SIGNEXTEND = 11,
EVM_INS_LT = 16,
EVM_INS_GT = 17,
EVM_INS_SLT = 18,
EVM_INS_SGT = 19,
EVM_INS_EQ = 20,
EVM_INS_ISZERO = 21,
EVM_INS_AND = 22,
EVM_INS_OR = 23,
EVM_INS_XOR = 24,
EVM_INS_NOT = 25,
EVM_INS_BYTE = 26,
EVM_INS_SHA3 = 32,
EVM_INS_ADDRESS = 48,
EVM_INS_BALANCE = 49,
EVM_INS_ORIGIN = 50,
EVM_INS_CALLER = 51,
EVM_INS_CALLVALUE = 52,
EVM_INS_CALLDATALOAD = 53,
EVM_INS_CALLDATASIZE = 54,
EVM_INS_CALLDATACOPY = 55,
EVM_INS_CODESIZE = 56,
EVM_INS_CODECOPY = 57,
EVM_INS_GASPRICE = 58,
EVM_INS_EXTCODESIZE = 59,
EVM_INS_EXTCODECOPY = 60,
EVM_INS_RETURNDATASIZE = 61,
EVM_INS_RETURNDATACOPY = 62,
EVM_INS_BLOCKHASH = 64,
EVM_INS_COINBASE = 65,
EVM_INS_TIMESTAMP = 66,
EVM_INS_NUMBER = 67,
EVM_INS_DIFFICULTY = 68,
EVM_INS_GASLIMIT = 69,
EVM_INS_POP = 80,
EVM_INS_MLOAD = 81,
EVM_INS_MSTORE = 82,
EVM_INS_MSTORE8 = 83,
EVM_INS_SLOAD = 84,
EVM_INS_SSTORE = 85,
EVM_INS_JUMP = 86,
EVM_INS_JUMPI = 87,
EVM_INS_PC = 88,
EVM_INS_MSIZE = 89,
EVM_INS_GAS = 90,
EVM_INS_JUMPDEST = 91,
EVM_INS_PUSH1 = 96,
EVM_INS_PUSH2 = 97,
EVM_INS_PUSH3 = 98,
EVM_INS_PUSH4 = 99,
EVM_INS_PUSH5 = 100,
EVM_INS_PUSH6 = 101,
EVM_INS_PUSH7 = 102,
EVM_INS_PUSH8 = 103,
EVM_INS_PUSH9 = 104,
EVM_INS_PUSH10 = 105,
EVM_INS_PUSH11 = 106,
EVM_INS_PUSH12 = 107,
EVM_INS_PUSH13 = 108,
EVM_INS_PUSH14 = 109,
EVM_INS_PUSH15 = 110,
EVM_INS_PUSH16 = 111,
EVM_INS_PUSH17 = 112,
EVM_INS_PUSH18 = 113,
EVM_INS_PUSH19 = 114,
EVM_INS_PUSH20 = 115,
EVM_INS_PUSH21 = 116,
EVM_INS_PUSH22 = 117,
EVM_INS_PUSH23 = 118,
EVM_INS_PUSH24 = 119,
EVM_INS_PUSH25 = 120,
EVM_INS_PUSH26 = 121,
EVM_INS_PUSH27 = 122,
EVM_INS_PUSH28 = 123,
EVM_INS_PUSH29 = 124,
EVM_INS_PUSH30 = 125,
EVM_INS_PUSH31 = 126,
EVM_INS_PUSH32 = 127,
EVM_INS_DUP1 = 128,
EVM_INS_DUP2 = 129,
EVM_INS_DUP3 = 130,
EVM_INS_DUP4 = 131,
EVM_INS_DUP5 = 132,
EVM_INS_DUP6 = 133,
EVM_INS_DUP7 = 134,
EVM_INS_DUP8 = 135,
EVM_INS_DUP9 = 136,
EVM_INS_DUP10 = 137,
EVM_INS_DUP11 = 138,
EVM_INS_DUP12 = 139,
EVM_INS_DUP13 = 140,
EVM_INS_DUP14 = 141,
EVM_INS_DUP15 = 142,
EVM_INS_DUP16 = 143,
EVM_INS_SWAP1 = 144,
EVM_INS_SWAP2 = 145,
EVM_INS_SWAP3 = 146,
EVM_INS_SWAP4 = 147,
EVM_INS_SWAP5 = 148,
EVM_INS_SWAP6 = 149,
EVM_INS_SWAP7 = 150,
EVM_INS_SWAP8 = 151,
EVM_INS_SWAP9 = 152,
EVM_INS_SWAP10 = 153,
EVM_INS_SWAP11 = 154,
EVM_INS_SWAP12 = 155,
EVM_INS_SWAP13 = 156,
EVM_INS_SWAP14 = 157,
EVM_INS_SWAP15 = 158,
EVM_INS_SWAP16 = 159,
EVM_INS_LOG0 = 160,
EVM_INS_LOG1 = 161,
EVM_INS_LOG2 = 162,
EVM_INS_LOG3 = 163,
EVM_INS_LOG4 = 164,
EVM_INS_CREATE = 240,
EVM_INS_CALL = 241,
EVM_INS_CALLCODE = 242,
EVM_INS_RETURN = 243,
EVM_INS_DELEGATECALL = 244,
EVM_INS_CALLBLACKBOX = 245,
EVM_INS_STATICCALL = 250,
EVM_INS_REVERT = 253,
EVM_INS_SUICIDE = 255,
EVM_INS_INVALID = 512,
EVM_INS_ENDING, // <-- mark the end of the list of instructions
} evm_insn;
/// Group of EVM instructions
typedef enum evm_insn_group {
EVM_GRP_INVALID = 0, ///< = CS_GRP_INVALID
EVM_GRP_JUMP, ///< all jump instructions
EVM_GRP_MATH = 8, ///< math instructions
EVM_GRP_STACK_WRITE, ///< instructions write to stack
EVM_GRP_STACK_READ, ///< instructions read from stack
EVM_GRP_MEM_WRITE, ///< instructions write to memory
EVM_GRP_MEM_READ, ///< instructions read from memory
EVM_GRP_STORE_WRITE, ///< instructions write to storage
EVM_GRP_STORE_READ, ///< instructions read from storage
EVM_GRP_HALT, ///< instructions halt execution
EVM_GRP_ENDING, ///< <-- mark the end of the list of groups
} evm_insn_group;
#ifdef __cplusplus
}
#endif
#endif

BIN
capstone/libcapstone.a Normal file
View File

Binary file not shown.

537
capstone/m680x.h Normal file
View File

@ -0,0 +1,537 @@
#ifndef CAPSTONE_M680X_H
#define CAPSTONE_M680X_H
/* Capstone Disassembly Engine */
/* M680X Backend by Wolfgang Schwotzer <wolfgang.schwotzer@gmx.net> 2017 */
#ifdef __cplusplus
extern "C" {
#endif
#include "platform.h"
#ifdef _MSC_VER
#pragma warning(disable:4201)
#endif
#define M680X_OPERAND_COUNT 9
/// M680X registers and special registers
typedef enum m680x_reg {
M680X_REG_INVALID = 0,
M680X_REG_A, ///< M6800/1/2/3/9, HD6301/9
M680X_REG_B, ///< M6800/1/2/3/9, HD6301/9
M680X_REG_E, ///< HD6309
M680X_REG_F, ///< HD6309
M680X_REG_0, ///< HD6309
M680X_REG_D, ///< M6801/3/9, HD6301/9
M680X_REG_W, ///< HD6309
M680X_REG_CC, ///< M6800/1/2/3/9, M6301/9
M680X_REG_DP, ///< M6809/M6309
M680X_REG_MD, ///< M6309
M680X_REG_HX, ///< M6808
M680X_REG_H, ///< M6808
M680X_REG_X, ///< M6800/1/2/3/9, M6301/9
M680X_REG_Y, ///< M6809/M6309
M680X_REG_S, ///< M6809/M6309
M680X_REG_U, ///< M6809/M6309
M680X_REG_V, ///< M6309
M680X_REG_Q, ///< M6309
M680X_REG_PC, ///< M6800/1/2/3/9, M6301/9
M680X_REG_TMP2, ///< CPU12
M680X_REG_TMP3, ///< CPU12
M680X_REG_ENDING, ///< <-- mark the end of the list of registers
} m680x_reg;
/// Operand type for instruction's operands
typedef enum m680x_op_type {
M680X_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized).
M680X_OP_REGISTER, ///< = Register operand.
M680X_OP_IMMEDIATE, ///< = Immediate operand.
M680X_OP_INDEXED, ///< = Indexed addressing operand.
M680X_OP_EXTENDED, ///< = Extended addressing operand.
M680X_OP_DIRECT, ///< = Direct addressing operand.
M680X_OP_RELATIVE, ///< = Relative addressing operand.
M680X_OP_CONSTANT, ///< = constant operand (Displayed as number only).
///< Used e.g. for a bit index or page number.
} m680x_op_type;
// Supported bit values for mem.idx.offset_bits
#define M680X_OFFSET_NONE 0
#define M680X_OFFSET_BITS_5 5
#define M680X_OFFSET_BITS_8 8
#define M680X_OFFSET_BITS_9 9
#define M680X_OFFSET_BITS_16 16
// Supported bit flags for mem.idx.flags
// These flags can be combined
#define M680X_IDX_INDIRECT 1
#define M680X_IDX_NO_COMMA 2
#define M680X_IDX_POST_INC_DEC 4
/// Instruction's operand referring to indexed addressing
typedef struct m680x_op_idx {
m680x_reg base_reg; ///< base register (or M680X_REG_INVALID if
///< irrelevant)
m680x_reg offset_reg; ///< offset register (or M680X_REG_INVALID if
///< irrelevant)
int16_t offset; ///< 5-,8- or 16-bit offset. See also offset_bits.
uint16_t offset_addr; ///< = offset addr. if base_reg == M680X_REG_PC.
///< calculated as offset + PC
uint8_t offset_bits; ///< offset width in bits for indexed addressing
int8_t inc_dec; ///< inc. or dec. value:
///< 0: no inc-/decrement
///< 1 .. 8: increment by 1 .. 8
///< -1 .. -8: decrement by 1 .. 8
///< if flag M680X_IDX_POST_INC_DEC set it is post
///< inc-/decrement otherwise pre inc-/decrement
uint8_t flags; ///< 8-bit flags (see above)
} m680x_op_idx;
/// Instruction's memory operand referring to relative addressing (Bcc/LBcc)
typedef struct m680x_op_rel {
uint16_t address; ///< The absolute address.
///< calculated as PC + offset. PC is the first
///< address after the instruction.
int16_t offset; ///< the offset/displacement value
} m680x_op_rel;
/// Instruction's operand referring to extended addressing
typedef struct m680x_op_ext {
uint16_t address; ///< The absolute address
bool indirect; ///< true if extended indirect addressing
} m680x_op_ext;
/// Instruction operand
typedef struct cs_m680x_op {
m680x_op_type type;
union {
int32_t imm; ///< immediate value for IMM operand
m680x_reg reg; ///< register value for REG operand
m680x_op_idx idx; ///< Indexed addressing operand
m680x_op_rel rel; ///< Relative address. operand (Bcc/LBcc)
m680x_op_ext ext; ///< Extended address
uint8_t direct_addr; ///<</ Direct address (lower 8-bit)
uint8_t const_val; ///< constant value (bit index, page nr.)
};
uint8_t size; ///< size of this operand (in bytes)
/// How is this operand accessed? (READ, WRITE or READ|WRITE)
/// This field is combined of cs_ac_type.
/// NOTE: this field is irrelevant if engine is compiled in DIET
uint8_t access;
} cs_m680x_op;
/// Group of M680X instructions
typedef enum m680x_group_type {
M680X_GRP_INVALID = 0, /// = CS_GRP_INVALID
// Generic groups
// all jump instructions (conditional+direct+indirect jumps)
M680X_GRP_JUMP, ///< = CS_GRP_JUMP
// all call instructions
M680X_GRP_CALL, ///< = CS_GRP_CALL
// all return instructions
M680X_GRP_RET, ///< = CS_GRP_RET
// all interrupt instructions (int+syscall)
M680X_GRP_INT, ///< = CS_GRP_INT
// all interrupt return instructions
M680X_GRP_IRET, ///< = CS_GRP_IRET
// all privileged instructions
M680X_GRP_PRIV, ///< = CS_GRP_PRIVILEDGE; not used
// all relative branching instructions
M680X_GRP_BRAREL, ///< = CS_GRP_BRANCH_RELATIVE
// Architecture-specific groups
M680X_GRP_ENDING, // <-- mark the end of the list of groups
} m680x_group_type;
// M680X instruction flags:
/// The first (register) operand is part of the
/// instruction mnemonic
#define M680X_FIRST_OP_IN_MNEM 1
/// The second (register) operand is part of the
/// instruction mnemonic
#define M680X_SECOND_OP_IN_MNEM 2
/// The M680X instruction and it's operands
typedef struct cs_m680x {
uint8_t flags; ///< See: M680X instruction flags
uint8_t op_count; ///< number of operands for the instruction or 0
cs_m680x_op operands[M680X_OPERAND_COUNT]; ///< operands for this insn.
} cs_m680x;
/// M680X instruction IDs
typedef enum m680x_insn {
M680X_INS_INVLD = 0,
M680X_INS_ABA, ///< M6800/1/2/3
M680X_INS_ABX,
M680X_INS_ABY,
M680X_INS_ADC,
M680X_INS_ADCA,
M680X_INS_ADCB,
M680X_INS_ADCD,
M680X_INS_ADCR,
M680X_INS_ADD,
M680X_INS_ADDA,
M680X_INS_ADDB,
M680X_INS_ADDD,
M680X_INS_ADDE,
M680X_INS_ADDF,
M680X_INS_ADDR,
M680X_INS_ADDW,
M680X_INS_AIM,
M680X_INS_AIS,
M680X_INS_AIX,
M680X_INS_AND,
M680X_INS_ANDA,
M680X_INS_ANDB,
M680X_INS_ANDCC,
M680X_INS_ANDD,
M680X_INS_ANDR,
M680X_INS_ASL,
M680X_INS_ASLA,
M680X_INS_ASLB,
M680X_INS_ASLD, ///< or LSLD
M680X_INS_ASR,
M680X_INS_ASRA,
M680X_INS_ASRB,
M680X_INS_ASRD,
M680X_INS_ASRX,
M680X_INS_BAND,
M680X_INS_BCC, ///< or BHS
M680X_INS_BCLR,
M680X_INS_BCS, ///< or BLO
M680X_INS_BEOR,
M680X_INS_BEQ,
M680X_INS_BGE,
M680X_INS_BGND,
M680X_INS_BGT,
M680X_INS_BHCC,
M680X_INS_BHCS,
M680X_INS_BHI,
M680X_INS_BIAND,
M680X_INS_BIEOR,
M680X_INS_BIH,
M680X_INS_BIL,
M680X_INS_BIOR,
M680X_INS_BIT,
M680X_INS_BITA,
M680X_INS_BITB,
M680X_INS_BITD,
M680X_INS_BITMD,
M680X_INS_BLE,
M680X_INS_BLS,
M680X_INS_BLT,
M680X_INS_BMC,
M680X_INS_BMI,
M680X_INS_BMS,
M680X_INS_BNE,
M680X_INS_BOR,
M680X_INS_BPL,
M680X_INS_BRCLR,
M680X_INS_BRSET,
M680X_INS_BRA,
M680X_INS_BRN,
M680X_INS_BSET,
M680X_INS_BSR,
M680X_INS_BVC,
M680X_INS_BVS,
M680X_INS_CALL,
M680X_INS_CBA, ///< M6800/1/2/3
M680X_INS_CBEQ,
M680X_INS_CBEQA,
M680X_INS_CBEQX,
M680X_INS_CLC, ///< M6800/1/2/3
M680X_INS_CLI, ///< M6800/1/2/3
M680X_INS_CLR,
M680X_INS_CLRA,
M680X_INS_CLRB,
M680X_INS_CLRD,
M680X_INS_CLRE,
M680X_INS_CLRF,
M680X_INS_CLRH,
M680X_INS_CLRW,
M680X_INS_CLRX,
M680X_INS_CLV, ///< M6800/1/2/3
M680X_INS_CMP,
M680X_INS_CMPA,
M680X_INS_CMPB,
M680X_INS_CMPD,
M680X_INS_CMPE,
M680X_INS_CMPF,
M680X_INS_CMPR,
M680X_INS_CMPS,
M680X_INS_CMPU,
M680X_INS_CMPW,
M680X_INS_CMPX,
M680X_INS_CMPY,
M680X_INS_COM,
M680X_INS_COMA,
M680X_INS_COMB,
M680X_INS_COMD,
M680X_INS_COME,
M680X_INS_COMF,
M680X_INS_COMW,
M680X_INS_COMX,
M680X_INS_CPD,
M680X_INS_CPHX,
M680X_INS_CPS,
M680X_INS_CPX, ///< M6800/1/2/3
M680X_INS_CPY,
M680X_INS_CWAI,
M680X_INS_DAA,
M680X_INS_DBEQ,
M680X_INS_DBNE,
M680X_INS_DBNZ,
M680X_INS_DBNZA,
M680X_INS_DBNZX,
M680X_INS_DEC,
M680X_INS_DECA,
M680X_INS_DECB,
M680X_INS_DECD,
M680X_INS_DECE,
M680X_INS_DECF,
M680X_INS_DECW,
M680X_INS_DECX,
M680X_INS_DES, ///< M6800/1/2/3
M680X_INS_DEX, ///< M6800/1/2/3
M680X_INS_DEY,
M680X_INS_DIV,
M680X_INS_DIVD,
M680X_INS_DIVQ,
M680X_INS_EDIV,
M680X_INS_EDIVS,
M680X_INS_EIM,
M680X_INS_EMACS,
M680X_INS_EMAXD,
M680X_INS_EMAXM,
M680X_INS_EMIND,
M680X_INS_EMINM,
M680X_INS_EMUL,
M680X_INS_EMULS,
M680X_INS_EOR,
M680X_INS_EORA,
M680X_INS_EORB,
M680X_INS_EORD,
M680X_INS_EORR,
M680X_INS_ETBL,
M680X_INS_EXG,
M680X_INS_FDIV,
M680X_INS_IBEQ,
M680X_INS_IBNE,
M680X_INS_IDIV,
M680X_INS_IDIVS,
M680X_INS_ILLGL,
M680X_INS_INC,
M680X_INS_INCA,
M680X_INS_INCB,
M680X_INS_INCD,
M680X_INS_INCE,
M680X_INS_INCF,
M680X_INS_INCW,
M680X_INS_INCX,
M680X_INS_INS, ///< M6800/1/2/3
M680X_INS_INX, ///< M6800/1/2/3
M680X_INS_INY,
M680X_INS_JMP,
M680X_INS_JSR,
M680X_INS_LBCC, ///< or LBHS
M680X_INS_LBCS, ///< or LBLO
M680X_INS_LBEQ,
M680X_INS_LBGE,
M680X_INS_LBGT,
M680X_INS_LBHI,
M680X_INS_LBLE,
M680X_INS_LBLS,
M680X_INS_LBLT,
M680X_INS_LBMI,
M680X_INS_LBNE,
M680X_INS_LBPL,
M680X_INS_LBRA,
M680X_INS_LBRN,
M680X_INS_LBSR,
M680X_INS_LBVC,
M680X_INS_LBVS,
M680X_INS_LDA,
M680X_INS_LDAA, ///< M6800/1/2/3
M680X_INS_LDAB, ///< M6800/1/2/3
M680X_INS_LDB,
M680X_INS_LDBT,
M680X_INS_LDD,
M680X_INS_LDE,
M680X_INS_LDF,
M680X_INS_LDHX,
M680X_INS_LDMD,
M680X_INS_LDQ,
M680X_INS_LDS,
M680X_INS_LDU,
M680X_INS_LDW,
M680X_INS_LDX,
M680X_INS_LDY,
M680X_INS_LEAS,
M680X_INS_LEAU,
M680X_INS_LEAX,
M680X_INS_LEAY,
M680X_INS_LSL,
M680X_INS_LSLA,
M680X_INS_LSLB,
M680X_INS_LSLD,
M680X_INS_LSLX,
M680X_INS_LSR,
M680X_INS_LSRA,
M680X_INS_LSRB,
M680X_INS_LSRD, ///< or ASRD
M680X_INS_LSRW,
M680X_INS_LSRX,
M680X_INS_MAXA,
M680X_INS_MAXM,
M680X_INS_MEM,
M680X_INS_MINA,
M680X_INS_MINM,
M680X_INS_MOV,
M680X_INS_MOVB,
M680X_INS_MOVW,
M680X_INS_MUL,
M680X_INS_MULD,
M680X_INS_NEG,
M680X_INS_NEGA,
M680X_INS_NEGB,
M680X_INS_NEGD,
M680X_INS_NEGX,
M680X_INS_NOP,
M680X_INS_NSA,
M680X_INS_OIM,
M680X_INS_ORA,
M680X_INS_ORAA, ///< M6800/1/2/3
M680X_INS_ORAB, ///< M6800/1/2/3
M680X_INS_ORB,
M680X_INS_ORCC,
M680X_INS_ORD,
M680X_INS_ORR,
M680X_INS_PSHA, ///< M6800/1/2/3
M680X_INS_PSHB, ///< M6800/1/2/3
M680X_INS_PSHC,
M680X_INS_PSHD,
M680X_INS_PSHH,
M680X_INS_PSHS,
M680X_INS_PSHSW,
M680X_INS_PSHU,
M680X_INS_PSHUW,
M680X_INS_PSHX, ///< M6800/1/2/3
M680X_INS_PSHY,
M680X_INS_PULA, ///< M6800/1/2/3
M680X_INS_PULB, ///< M6800/1/2/3
M680X_INS_PULC,
M680X_INS_PULD,
M680X_INS_PULH,
M680X_INS_PULS,
M680X_INS_PULSW,
M680X_INS_PULU,
M680X_INS_PULUW,
M680X_INS_PULX, ///< M6800/1/2/3
M680X_INS_PULY,
M680X_INS_REV,
M680X_INS_REVW,
M680X_INS_ROL,
M680X_INS_ROLA,
M680X_INS_ROLB,
M680X_INS_ROLD,
M680X_INS_ROLW,
M680X_INS_ROLX,
M680X_INS_ROR,
M680X_INS_RORA,
M680X_INS_RORB,
M680X_INS_RORD,
M680X_INS_RORW,
M680X_INS_RORX,
M680X_INS_RSP,
M680X_INS_RTC,
M680X_INS_RTI,
M680X_INS_RTS,
M680X_INS_SBA, ///< M6800/1/2/3
M680X_INS_SBC,
M680X_INS_SBCA,
M680X_INS_SBCB,
M680X_INS_SBCD,
M680X_INS_SBCR,
M680X_INS_SEC,
M680X_INS_SEI,
M680X_INS_SEV,
M680X_INS_SEX,
M680X_INS_SEXW,
M680X_INS_SLP,
M680X_INS_STA,
M680X_INS_STAA, ///< M6800/1/2/3
M680X_INS_STAB, ///< M6800/1/2/3
M680X_INS_STB,
M680X_INS_STBT,
M680X_INS_STD,
M680X_INS_STE,
M680X_INS_STF,
M680X_INS_STOP,
M680X_INS_STHX,
M680X_INS_STQ,
M680X_INS_STS,
M680X_INS_STU,
M680X_INS_STW,
M680X_INS_STX,
M680X_INS_STY,
M680X_INS_SUB,
M680X_INS_SUBA,
M680X_INS_SUBB,
M680X_INS_SUBD,
M680X_INS_SUBE,
M680X_INS_SUBF,
M680X_INS_SUBR,
M680X_INS_SUBW,
M680X_INS_SWI,
M680X_INS_SWI2,
M680X_INS_SWI3,
M680X_INS_SYNC,
M680X_INS_TAB, ///< M6800/1/2/3
M680X_INS_TAP, ///< M6800/1/2/3
M680X_INS_TAX,
M680X_INS_TBA, ///< M6800/1/2/3
M680X_INS_TBEQ,
M680X_INS_TBL,
M680X_INS_TBNE,
M680X_INS_TEST,
M680X_INS_TFM,
M680X_INS_TFR,
M680X_INS_TIM,
M680X_INS_TPA, ///< M6800/1/2/3
M680X_INS_TST,
M680X_INS_TSTA,
M680X_INS_TSTB,
M680X_INS_TSTD,
M680X_INS_TSTE,
M680X_INS_TSTF,
M680X_INS_TSTW,
M680X_INS_TSTX,
M680X_INS_TSX, ///< M6800/1/2/3
M680X_INS_TSY,
M680X_INS_TXA,
M680X_INS_TXS, ///< M6800/1/2/3
M680X_INS_TYS,
M680X_INS_WAI, ///< M6800/1/2/3
M680X_INS_WAIT,
M680X_INS_WAV,
M680X_INS_WAVR,
M680X_INS_XGDX, ///< HD6301
M680X_INS_XGDY,
M680X_INS_ENDING, // <-- mark the end of the list of instructions
} m680x_insn;
#ifdef __cplusplus
}
#endif
#endif

613
capstone/m68k.h Normal file
View File

@ -0,0 +1,613 @@
#ifndef CAPSTONE_M68K_H
#define CAPSTONE_M68K_H
/* Capstone Disassembly Engine */
/* By Daniel Collin <daniel@collin.com>, 2015-2016 */
#ifdef __cplusplus
extern "C" {
#endif
#include "platform.h"
#ifdef _MSC_VER
#pragma warning(disable:4201)
#endif
#define M68K_OPERAND_COUNT 4
/// M68K registers and special registers
typedef enum m68k_reg {
M68K_REG_INVALID = 0,
M68K_REG_D0,
M68K_REG_D1,
M68K_REG_D2,
M68K_REG_D3,
M68K_REG_D4,
M68K_REG_D5,
M68K_REG_D6,
M68K_REG_D7,
M68K_REG_A0,
M68K_REG_A1,
M68K_REG_A2,
M68K_REG_A3,
M68K_REG_A4,
M68K_REG_A5,
M68K_REG_A6,
M68K_REG_A7,
M68K_REG_FP0,
M68K_REG_FP1,
M68K_REG_FP2,
M68K_REG_FP3,
M68K_REG_FP4,
M68K_REG_FP5,
M68K_REG_FP6,
M68K_REG_FP7,
M68K_REG_PC,
M68K_REG_SR,
M68K_REG_CCR,
M68K_REG_SFC,
M68K_REG_DFC,
M68K_REG_USP,
M68K_REG_VBR,
M68K_REG_CACR,
M68K_REG_CAAR,
M68K_REG_MSP,
M68K_REG_ISP,
M68K_REG_TC,
M68K_REG_ITT0,
M68K_REG_ITT1,
M68K_REG_DTT0,
M68K_REG_DTT1,
M68K_REG_MMUSR,
M68K_REG_URP,
M68K_REG_SRP,
M68K_REG_FPCR,
M68K_REG_FPSR,
M68K_REG_FPIAR,
M68K_REG_ENDING, // <-- mark the end of the list of registers
} m68k_reg;
/// M68K Addressing Modes
typedef enum m68k_address_mode {
M68K_AM_NONE = 0, ///< No address mode.
M68K_AM_REG_DIRECT_DATA, ///< Register Direct - Data
M68K_AM_REG_DIRECT_ADDR, ///< Register Direct - Address
M68K_AM_REGI_ADDR, ///< Register Indirect - Address
M68K_AM_REGI_ADDR_POST_INC, ///< Register Indirect - Address with Postincrement
M68K_AM_REGI_ADDR_PRE_DEC, ///< Register Indirect - Address with Predecrement
M68K_AM_REGI_ADDR_DISP, ///< Register Indirect - Address with Displacement
M68K_AM_AREGI_INDEX_8_BIT_DISP, ///< Address Register Indirect With Index- 8-bit displacement
M68K_AM_AREGI_INDEX_BASE_DISP, ///< Address Register Indirect With Index- Base displacement
M68K_AM_MEMI_POST_INDEX, ///< Memory indirect - Postindex
M68K_AM_MEMI_PRE_INDEX, ///< Memory indirect - Preindex
M68K_AM_PCI_DISP, ///< Program Counter Indirect - with Displacement
M68K_AM_PCI_INDEX_8_BIT_DISP, ///< Program Counter Indirect with Index - with 8-Bit Displacement
M68K_AM_PCI_INDEX_BASE_DISP, ///< Program Counter Indirect with Index - with Base Displacement
M68K_AM_PC_MEMI_POST_INDEX, ///< Program Counter Memory Indirect - Postindexed
M68K_AM_PC_MEMI_PRE_INDEX, ///< Program Counter Memory Indirect - Preindexed
M68K_AM_ABSOLUTE_DATA_SHORT, ///< Absolute Data Addressing - Short
M68K_AM_ABSOLUTE_DATA_LONG, ///< Absolute Data Addressing - Long
M68K_AM_IMMEDIATE, ///< Immediate value
M68K_AM_BRANCH_DISPLACEMENT, ///< Address as displacement from (PC+2) used by branches
} m68k_address_mode;
/// Operand type for instruction's operands
typedef enum m68k_op_type {
M68K_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized).
M68K_OP_REG, ///< = CS_OP_REG (Register operand).
M68K_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
M68K_OP_MEM, ///< = CS_OP_MEM (Memory operand).
M68K_OP_FP_SINGLE, ///< single precision Floating-Point operand
M68K_OP_FP_DOUBLE, ///< double precision Floating-Point operand
M68K_OP_REG_BITS, ///< Register bits move
M68K_OP_REG_PAIR, ///< Register pair in the same op (upper 4 bits for first reg, lower for second)
M68K_OP_BR_DISP, ///< Branch displacement
} m68k_op_type;
/// Instruction's operand referring to memory
/// This is associated with M68K_OP_MEM operand type above
typedef struct m68k_op_mem {
m68k_reg base_reg; ///< base register (or M68K_REG_INVALID if irrelevant)
m68k_reg index_reg; ///< index register (or M68K_REG_INVALID if irrelevant)
m68k_reg in_base_reg; ///< indirect base register (or M68K_REG_INVALID if irrelevant)
uint32_t in_disp; ///< indirect displacement
uint32_t out_disp; ///< other displacement
int16_t disp; ///< displacement value
uint8_t scale; ///< scale for index register
uint8_t bitfield; ///< set to true if the two values below should be used
uint8_t width; ///< used for bf* instructions
uint8_t offset; ///< used for bf* instructions
uint8_t index_size; ///< 0 = w, 1 = l
} m68k_op_mem;
/// Operand type for instruction's operands
typedef enum m68k_op_br_disp_size {
M68K_OP_BR_DISP_SIZE_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized).
M68K_OP_BR_DISP_SIZE_BYTE = 1, ///< signed 8-bit displacement
M68K_OP_BR_DISP_SIZE_WORD = 2, ///< signed 16-bit displacement
M68K_OP_BR_DISP_SIZE_LONG = 4, ///< signed 32-bit displacement
} m68k_op_br_disp_size;
typedef struct m68k_op_br_disp {
int32_t disp; ///< displacement value
uint8_t disp_size; ///< Size from m68k_op_br_disp_size type above
} m68k_op_br_disp;
/// Register pair in one operand.
typedef struct cs_m68k_op_reg_pair {
m68k_reg reg_0;
m68k_reg reg_1;
} cs_m68k_op_reg_pair;
/// Instruction operand
typedef struct cs_m68k_op {
union {
uint64_t imm; ///< immediate value for IMM operand
double dimm; ///< double imm
float simm; ///< float imm
m68k_reg reg; ///< register value for REG operand
cs_m68k_op_reg_pair reg_pair; ///< register pair in one operand
};
m68k_op_mem mem; ///< data when operand is targeting memory
m68k_op_br_disp br_disp; ///< data when operand is a branch displacement
uint32_t register_bits; ///< register bits for movem etc. (always in d0-d7, a0-a7, fp0 - fp7 order)
m68k_op_type type;
m68k_address_mode address_mode; ///< M68K addressing mode for this op
} cs_m68k_op;
/// Operation size of the CPU instructions
typedef enum m68k_cpu_size {
M68K_CPU_SIZE_NONE = 0, ///< unsized or unspecified
M68K_CPU_SIZE_BYTE = 1, ///< 1 byte in size
M68K_CPU_SIZE_WORD = 2, ///< 2 bytes in size
M68K_CPU_SIZE_LONG = 4, ///< 4 bytes in size
} m68k_cpu_size;
/// Operation size of the FPU instructions (Notice that FPU instruction can also use CPU sizes if needed)
typedef enum m68k_fpu_size {
M68K_FPU_SIZE_NONE = 0, ///< unsized like fsave/frestore
M68K_FPU_SIZE_SINGLE = 4, ///< 4 byte in size (single float)
M68K_FPU_SIZE_DOUBLE = 8, ///< 8 byte in size (double)
M68K_FPU_SIZE_EXTENDED = 12, ///< 12 byte in size (extended real format)
} m68k_fpu_size;
/// Type of size that is being used for the current instruction
typedef enum m68k_size_type {
M68K_SIZE_TYPE_INVALID = 0,
M68K_SIZE_TYPE_CPU,
M68K_SIZE_TYPE_FPU,
} m68k_size_type;
/// Operation size of the current instruction (NOT the actually size of instruction)
typedef struct m68k_op_size {
m68k_size_type type;
union {
m68k_cpu_size cpu_size;
m68k_fpu_size fpu_size;
};
} m68k_op_size;
/// The M68K instruction and it's operands
typedef struct cs_m68k {
// Number of operands of this instruction or 0 when instruction has no operand.
cs_m68k_op operands[M68K_OPERAND_COUNT]; ///< operands for this instruction.
m68k_op_size op_size; ///< size of data operand works on in bytes (.b, .w, .l, etc)
uint8_t op_count; ///< number of operands for the instruction
} cs_m68k;
/// M68K instruction
typedef enum m68k_insn {
M68K_INS_INVALID = 0,
M68K_INS_ABCD,
M68K_INS_ADD,
M68K_INS_ADDA,
M68K_INS_ADDI,
M68K_INS_ADDQ,
M68K_INS_ADDX,
M68K_INS_AND,
M68K_INS_ANDI,
M68K_INS_ASL,
M68K_INS_ASR,
M68K_INS_BHS,
M68K_INS_BLO,
M68K_INS_BHI,
M68K_INS_BLS,
M68K_INS_BCC,
M68K_INS_BCS,
M68K_INS_BNE,
M68K_INS_BEQ,
M68K_INS_BVC,
M68K_INS_BVS,
M68K_INS_BPL,
M68K_INS_BMI,
M68K_INS_BGE,
M68K_INS_BLT,
M68K_INS_BGT,
M68K_INS_BLE,
M68K_INS_BRA,
M68K_INS_BSR,
M68K_INS_BCHG,
M68K_INS_BCLR,
M68K_INS_BSET,
M68K_INS_BTST,
M68K_INS_BFCHG,
M68K_INS_BFCLR,
M68K_INS_BFEXTS,
M68K_INS_BFEXTU,
M68K_INS_BFFFO,
M68K_INS_BFINS,
M68K_INS_BFSET,
M68K_INS_BFTST,
M68K_INS_BKPT,
M68K_INS_CALLM,
M68K_INS_CAS,
M68K_INS_CAS2,
M68K_INS_CHK,
M68K_INS_CHK2,
M68K_INS_CLR,
M68K_INS_CMP,
M68K_INS_CMPA,
M68K_INS_CMPI,
M68K_INS_CMPM,
M68K_INS_CMP2,
M68K_INS_CINVL,
M68K_INS_CINVP,
M68K_INS_CINVA,
M68K_INS_CPUSHL,
M68K_INS_CPUSHP,
M68K_INS_CPUSHA,
M68K_INS_DBT,
M68K_INS_DBF,
M68K_INS_DBHI,
M68K_INS_DBLS,
M68K_INS_DBCC,
M68K_INS_DBCS,
M68K_INS_DBNE,
M68K_INS_DBEQ,
M68K_INS_DBVC,
M68K_INS_DBVS,
M68K_INS_DBPL,
M68K_INS_DBMI,
M68K_INS_DBGE,
M68K_INS_DBLT,
M68K_INS_DBGT,
M68K_INS_DBLE,
M68K_INS_DBRA,
M68K_INS_DIVS,
M68K_INS_DIVSL,
M68K_INS_DIVU,
M68K_INS_DIVUL,
M68K_INS_EOR,
M68K_INS_EORI,
M68K_INS_EXG,
M68K_INS_EXT,
M68K_INS_EXTB,
M68K_INS_FABS,
M68K_INS_FSABS,
M68K_INS_FDABS,
M68K_INS_FACOS,
M68K_INS_FADD,
M68K_INS_FSADD,
M68K_INS_FDADD,
M68K_INS_FASIN,
M68K_INS_FATAN,
M68K_INS_FATANH,
M68K_INS_FBF,
M68K_INS_FBEQ,
M68K_INS_FBOGT,
M68K_INS_FBOGE,
M68K_INS_FBOLT,
M68K_INS_FBOLE,
M68K_INS_FBOGL,
M68K_INS_FBOR,
M68K_INS_FBUN,
M68K_INS_FBUEQ,
M68K_INS_FBUGT,
M68K_INS_FBUGE,
M68K_INS_FBULT,
M68K_INS_FBULE,
M68K_INS_FBNE,
M68K_INS_FBT,
M68K_INS_FBSF,
M68K_INS_FBSEQ,
M68K_INS_FBGT,
M68K_INS_FBGE,
M68K_INS_FBLT,
M68K_INS_FBLE,
M68K_INS_FBGL,
M68K_INS_FBGLE,
M68K_INS_FBNGLE,
M68K_INS_FBNGL,
M68K_INS_FBNLE,
M68K_INS_FBNLT,
M68K_INS_FBNGE,
M68K_INS_FBNGT,
M68K_INS_FBSNE,
M68K_INS_FBST,
M68K_INS_FCMP,
M68K_INS_FCOS,
M68K_INS_FCOSH,
M68K_INS_FDBF,
M68K_INS_FDBEQ,
M68K_INS_FDBOGT,
M68K_INS_FDBOGE,
M68K_INS_FDBOLT,
M68K_INS_FDBOLE,
M68K_INS_FDBOGL,
M68K_INS_FDBOR,
M68K_INS_FDBUN,
M68K_INS_FDBUEQ,
M68K_INS_FDBUGT,
M68K_INS_FDBUGE,
M68K_INS_FDBULT,
M68K_INS_FDBULE,
M68K_INS_FDBNE,
M68K_INS_FDBT,
M68K_INS_FDBSF,
M68K_INS_FDBSEQ,
M68K_INS_FDBGT,
M68K_INS_FDBGE,
M68K_INS_FDBLT,
M68K_INS_FDBLE,
M68K_INS_FDBGL,
M68K_INS_FDBGLE,
M68K_INS_FDBNGLE,
M68K_INS_FDBNGL,
M68K_INS_FDBNLE,
M68K_INS_FDBNLT,
M68K_INS_FDBNGE,
M68K_INS_FDBNGT,
M68K_INS_FDBSNE,
M68K_INS_FDBST,
M68K_INS_FDIV,
M68K_INS_FSDIV,
M68K_INS_FDDIV,
M68K_INS_FETOX,
M68K_INS_FETOXM1,
M68K_INS_FGETEXP,
M68K_INS_FGETMAN,
M68K_INS_FINT,
M68K_INS_FINTRZ,
M68K_INS_FLOG10,
M68K_INS_FLOG2,
M68K_INS_FLOGN,
M68K_INS_FLOGNP1,
M68K_INS_FMOD,
M68K_INS_FMOVE,
M68K_INS_FSMOVE,
M68K_INS_FDMOVE,
M68K_INS_FMOVECR,
M68K_INS_FMOVEM,
M68K_INS_FMUL,
M68K_INS_FSMUL,
M68K_INS_FDMUL,
M68K_INS_FNEG,
M68K_INS_FSNEG,
M68K_INS_FDNEG,
M68K_INS_FNOP,
M68K_INS_FREM,
M68K_INS_FRESTORE,
M68K_INS_FSAVE,
M68K_INS_FSCALE,
M68K_INS_FSGLDIV,
M68K_INS_FSGLMUL,
M68K_INS_FSIN,
M68K_INS_FSINCOS,
M68K_INS_FSINH,
M68K_INS_FSQRT,
M68K_INS_FSSQRT,
M68K_INS_FDSQRT,
M68K_INS_FSF,
M68K_INS_FSBEQ,
M68K_INS_FSOGT,
M68K_INS_FSOGE,
M68K_INS_FSOLT,
M68K_INS_FSOLE,
M68K_INS_FSOGL,
M68K_INS_FSOR,
M68K_INS_FSUN,
M68K_INS_FSUEQ,
M68K_INS_FSUGT,
M68K_INS_FSUGE,
M68K_INS_FSULT,
M68K_INS_FSULE,
M68K_INS_FSNE,
M68K_INS_FST,
M68K_INS_FSSF,
M68K_INS_FSSEQ,
M68K_INS_FSGT,
M68K_INS_FSGE,
M68K_INS_FSLT,
M68K_INS_FSLE,
M68K_INS_FSGL,
M68K_INS_FSGLE,
M68K_INS_FSNGLE,
M68K_INS_FSNGL,
M68K_INS_FSNLE,
M68K_INS_FSNLT,
M68K_INS_FSNGE,
M68K_INS_FSNGT,
M68K_INS_FSSNE,
M68K_INS_FSST,
M68K_INS_FSUB,
M68K_INS_FSSUB,
M68K_INS_FDSUB,
M68K_INS_FTAN,
M68K_INS_FTANH,
M68K_INS_FTENTOX,
M68K_INS_FTRAPF,
M68K_INS_FTRAPEQ,
M68K_INS_FTRAPOGT,
M68K_INS_FTRAPOGE,
M68K_INS_FTRAPOLT,
M68K_INS_FTRAPOLE,
M68K_INS_FTRAPOGL,
M68K_INS_FTRAPOR,
M68K_INS_FTRAPUN,
M68K_INS_FTRAPUEQ,
M68K_INS_FTRAPUGT,
M68K_INS_FTRAPUGE,
M68K_INS_FTRAPULT,
M68K_INS_FTRAPULE,
M68K_INS_FTRAPNE,
M68K_INS_FTRAPT,
M68K_INS_FTRAPSF,
M68K_INS_FTRAPSEQ,
M68K_INS_FTRAPGT,
M68K_INS_FTRAPGE,
M68K_INS_FTRAPLT,
M68K_INS_FTRAPLE,
M68K_INS_FTRAPGL,
M68K_INS_FTRAPGLE,
M68K_INS_FTRAPNGLE,
M68K_INS_FTRAPNGL,
M68K_INS_FTRAPNLE,
M68K_INS_FTRAPNLT,
M68K_INS_FTRAPNGE,
M68K_INS_FTRAPNGT,
M68K_INS_FTRAPSNE,
M68K_INS_FTRAPST,
M68K_INS_FTST,
M68K_INS_FTWOTOX,
M68K_INS_HALT,
M68K_INS_ILLEGAL,
M68K_INS_JMP,
M68K_INS_JSR,
M68K_INS_LEA,
M68K_INS_LINK,
M68K_INS_LPSTOP,
M68K_INS_LSL,
M68K_INS_LSR,
M68K_INS_MOVE,
M68K_INS_MOVEA,
M68K_INS_MOVEC,
M68K_INS_MOVEM,
M68K_INS_MOVEP,
M68K_INS_MOVEQ,
M68K_INS_MOVES,
M68K_INS_MOVE16,
M68K_INS_MULS,
M68K_INS_MULU,
M68K_INS_NBCD,
M68K_INS_NEG,
M68K_INS_NEGX,
M68K_INS_NOP,
M68K_INS_NOT,
M68K_INS_OR,
M68K_INS_ORI,
M68K_INS_PACK,
M68K_INS_PEA,
M68K_INS_PFLUSH,
M68K_INS_PFLUSHA,
M68K_INS_PFLUSHAN,
M68K_INS_PFLUSHN,
M68K_INS_PLOADR,
M68K_INS_PLOADW,
M68K_INS_PLPAR,
M68K_INS_PLPAW,
M68K_INS_PMOVE,
M68K_INS_PMOVEFD,
M68K_INS_PTESTR,
M68K_INS_PTESTW,
M68K_INS_PULSE,
M68K_INS_REMS,
M68K_INS_REMU,
M68K_INS_RESET,
M68K_INS_ROL,
M68K_INS_ROR,
M68K_INS_ROXL,
M68K_INS_ROXR,
M68K_INS_RTD,
M68K_INS_RTE,
M68K_INS_RTM,
M68K_INS_RTR,
M68K_INS_RTS,
M68K_INS_SBCD,
M68K_INS_ST,
M68K_INS_SF,
M68K_INS_SHI,
M68K_INS_SLS,
M68K_INS_SCC,
M68K_INS_SHS,
M68K_INS_SCS,
M68K_INS_SLO,
M68K_INS_SNE,
M68K_INS_SEQ,
M68K_INS_SVC,
M68K_INS_SVS,
M68K_INS_SPL,
M68K_INS_SMI,
M68K_INS_SGE,
M68K_INS_SLT,
M68K_INS_SGT,
M68K_INS_SLE,
M68K_INS_STOP,
M68K_INS_SUB,
M68K_INS_SUBA,
M68K_INS_SUBI,
M68K_INS_SUBQ,
M68K_INS_SUBX,
M68K_INS_SWAP,
M68K_INS_TAS,
M68K_INS_TRAP,
M68K_INS_TRAPV,
M68K_INS_TRAPT,
M68K_INS_TRAPF,
M68K_INS_TRAPHI,
M68K_INS_TRAPLS,
M68K_INS_TRAPCC,
M68K_INS_TRAPHS,
M68K_INS_TRAPCS,
M68K_INS_TRAPLO,
M68K_INS_TRAPNE,
M68K_INS_TRAPEQ,
M68K_INS_TRAPVC,
M68K_INS_TRAPVS,
M68K_INS_TRAPPL,
M68K_INS_TRAPMI,
M68K_INS_TRAPGE,
M68K_INS_TRAPLT,
M68K_INS_TRAPGT,
M68K_INS_TRAPLE,
M68K_INS_TST,
M68K_INS_UNLK,
M68K_INS_UNPK,
M68K_INS_ENDING, // <-- mark the end of the list of instructions
} m68k_insn;
/// Group of M68K instructions
typedef enum m68k_group_type {
M68K_GRP_INVALID = 0, ///< CS_GRUP_INVALID
M68K_GRP_JUMP, ///< = CS_GRP_JUMP
M68K_GRP_RET = 3, ///< = CS_GRP_RET
M68K_GRP_IRET = 5, ///< = CS_GRP_IRET
M68K_GRP_BRANCH_RELATIVE = 7, ///< = CS_GRP_BRANCH_RELATIVE
M68K_GRP_ENDING,// <-- mark the end of the list of groups
} m68k_group_type;
#ifdef __cplusplus
}
#endif
#endif

956
capstone/mips.h Normal file
View File

@ -0,0 +1,956 @@
#ifndef CAPSTONE_MIPS_H
#define CAPSTONE_MIPS_H
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
#ifdef __cplusplus
extern "C" {
#endif
#include "platform.h"
// GCC MIPS toolchain has a default macro called "mips" which breaks
// compilation
#undef mips
#ifdef _MSC_VER
#pragma warning(disable:4201)
#endif
/// Operand type for instruction's operands
typedef enum mips_op_type {
MIPS_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized).
MIPS_OP_REG, ///< = CS_OP_REG (Register operand).
MIPS_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
MIPS_OP_MEM, ///< = CS_OP_MEM (Memory operand).
} mips_op_type;
/// MIPS registers
typedef enum mips_reg {
MIPS_REG_INVALID = 0,
// General purpose registers
MIPS_REG_PC,
MIPS_REG_0,
MIPS_REG_1,
MIPS_REG_2,
MIPS_REG_3,
MIPS_REG_4,
MIPS_REG_5,
MIPS_REG_6,
MIPS_REG_7,
MIPS_REG_8,
MIPS_REG_9,
MIPS_REG_10,
MIPS_REG_11,
MIPS_REG_12,
MIPS_REG_13,
MIPS_REG_14,
MIPS_REG_15,
MIPS_REG_16,
MIPS_REG_17,
MIPS_REG_18,
MIPS_REG_19,
MIPS_REG_20,
MIPS_REG_21,
MIPS_REG_22,
MIPS_REG_23,
MIPS_REG_24,
MIPS_REG_25,
MIPS_REG_26,
MIPS_REG_27,
MIPS_REG_28,
MIPS_REG_29,
MIPS_REG_30,
MIPS_REG_31,
// DSP registers
MIPS_REG_DSPCCOND,
MIPS_REG_DSPCARRY,
MIPS_REG_DSPEFI,
MIPS_REG_DSPOUTFLAG,
MIPS_REG_DSPOUTFLAG16_19,
MIPS_REG_DSPOUTFLAG20,
MIPS_REG_DSPOUTFLAG21,
MIPS_REG_DSPOUTFLAG22,
MIPS_REG_DSPOUTFLAG23,
MIPS_REG_DSPPOS,
MIPS_REG_DSPSCOUNT,
// ACC registers
MIPS_REG_AC0,
MIPS_REG_AC1,
MIPS_REG_AC2,
MIPS_REG_AC3,
// COP registers
MIPS_REG_CC0,
MIPS_REG_CC1,
MIPS_REG_CC2,
MIPS_REG_CC3,
MIPS_REG_CC4,
MIPS_REG_CC5,
MIPS_REG_CC6,
MIPS_REG_CC7,
// FPU registers
MIPS_REG_F0,
MIPS_REG_F1,
MIPS_REG_F2,
MIPS_REG_F3,
MIPS_REG_F4,
MIPS_REG_F5,
MIPS_REG_F6,
MIPS_REG_F7,
MIPS_REG_F8,
MIPS_REG_F9,
MIPS_REG_F10,
MIPS_REG_F11,
MIPS_REG_F12,
MIPS_REG_F13,
MIPS_REG_F14,
MIPS_REG_F15,
MIPS_REG_F16,
MIPS_REG_F17,
MIPS_REG_F18,
MIPS_REG_F19,
MIPS_REG_F20,
MIPS_REG_F21,
MIPS_REG_F22,
MIPS_REG_F23,
MIPS_REG_F24,
MIPS_REG_F25,
MIPS_REG_F26,
MIPS_REG_F27,
MIPS_REG_F28,
MIPS_REG_F29,
MIPS_REG_F30,
MIPS_REG_F31,
MIPS_REG_FCC0,
MIPS_REG_FCC1,
MIPS_REG_FCC2,
MIPS_REG_FCC3,
MIPS_REG_FCC4,
MIPS_REG_FCC5,
MIPS_REG_FCC6,
MIPS_REG_FCC7,
// AFPR128
MIPS_REG_W0,
MIPS_REG_W1,
MIPS_REG_W2,
MIPS_REG_W3,
MIPS_REG_W4,
MIPS_REG_W5,
MIPS_REG_W6,
MIPS_REG_W7,
MIPS_REG_W8,
MIPS_REG_W9,
MIPS_REG_W10,
MIPS_REG_W11,
MIPS_REG_W12,
MIPS_REG_W13,
MIPS_REG_W14,
MIPS_REG_W15,
MIPS_REG_W16,
MIPS_REG_W17,
MIPS_REG_W18,
MIPS_REG_W19,
MIPS_REG_W20,
MIPS_REG_W21,
MIPS_REG_W22,
MIPS_REG_W23,
MIPS_REG_W24,
MIPS_REG_W25,
MIPS_REG_W26,
MIPS_REG_W27,
MIPS_REG_W28,
MIPS_REG_W29,
MIPS_REG_W30,
MIPS_REG_W31,
MIPS_REG_HI,
MIPS_REG_LO,
MIPS_REG_P0,
MIPS_REG_P1,
MIPS_REG_P2,
MIPS_REG_MPL0,
MIPS_REG_MPL1,
MIPS_REG_MPL2,
MIPS_REG_ENDING, // <-- mark the end of the list or registers
// alias registers
MIPS_REG_ZERO = MIPS_REG_0,
MIPS_REG_AT = MIPS_REG_1,
MIPS_REG_V0 = MIPS_REG_2,
MIPS_REG_V1 = MIPS_REG_3,
MIPS_REG_A0 = MIPS_REG_4,
MIPS_REG_A1 = MIPS_REG_5,
MIPS_REG_A2 = MIPS_REG_6,
MIPS_REG_A3 = MIPS_REG_7,
MIPS_REG_T0 = MIPS_REG_8,
MIPS_REG_T1 = MIPS_REG_9,
MIPS_REG_T2 = MIPS_REG_10,
MIPS_REG_T3 = MIPS_REG_11,
MIPS_REG_T4 = MIPS_REG_12,
MIPS_REG_T5 = MIPS_REG_13,
MIPS_REG_T6 = MIPS_REG_14,
MIPS_REG_T7 = MIPS_REG_15,
MIPS_REG_S0 = MIPS_REG_16,
MIPS_REG_S1 = MIPS_REG_17,
MIPS_REG_S2 = MIPS_REG_18,
MIPS_REG_S3 = MIPS_REG_19,
MIPS_REG_S4 = MIPS_REG_20,
MIPS_REG_S5 = MIPS_REG_21,
MIPS_REG_S6 = MIPS_REG_22,
MIPS_REG_S7 = MIPS_REG_23,
MIPS_REG_T8 = MIPS_REG_24,
MIPS_REG_T9 = MIPS_REG_25,
MIPS_REG_K0 = MIPS_REG_26,
MIPS_REG_K1 = MIPS_REG_27,
MIPS_REG_GP = MIPS_REG_28,
MIPS_REG_SP = MIPS_REG_29,
MIPS_REG_FP = MIPS_REG_30, MIPS_REG_S8 = MIPS_REG_30,
MIPS_REG_RA = MIPS_REG_31,
MIPS_REG_HI0 = MIPS_REG_AC0,
MIPS_REG_HI1 = MIPS_REG_AC1,
MIPS_REG_HI2 = MIPS_REG_AC2,
MIPS_REG_HI3 = MIPS_REG_AC3,
MIPS_REG_LO0 = MIPS_REG_HI0,
MIPS_REG_LO1 = MIPS_REG_HI1,
MIPS_REG_LO2 = MIPS_REG_HI2,
MIPS_REG_LO3 = MIPS_REG_HI3,
} mips_reg;
/// Instruction's operand referring to memory
/// This is associated with MIPS_OP_MEM operand type above
typedef struct mips_op_mem {
mips_reg base; ///< base register
int64_t disp; ///< displacement/offset value
} mips_op_mem;
/// Instruction operand
typedef struct cs_mips_op {
mips_op_type type; ///< operand type
union {
mips_reg reg; ///< register id for REG operand
int64_t imm; ///< immediate value for IMM operand
mips_op_mem mem; ///< base/index/scale/disp value for MEM operand
};
} cs_mips_op;
/// Instruction structure
typedef struct cs_mips {
/// Number of operands of this instruction,
/// or 0 when instruction has no operand.
uint8_t op_count;
cs_mips_op operands[10]; ///< operands for this instruction.
} cs_mips;
/// MIPS instruction
typedef enum mips_insn {
MIPS_INS_INVALID = 0,
MIPS_INS_ABSQ_S,
MIPS_INS_ADD,
MIPS_INS_ADDIUPC,
MIPS_INS_ADDIUR1SP,
MIPS_INS_ADDIUR2,
MIPS_INS_ADDIUS5,
MIPS_INS_ADDIUSP,
MIPS_INS_ADDQH,
MIPS_INS_ADDQH_R,
MIPS_INS_ADDQ,
MIPS_INS_ADDQ_S,
MIPS_INS_ADDSC,
MIPS_INS_ADDS_A,
MIPS_INS_ADDS_S,
MIPS_INS_ADDS_U,
MIPS_INS_ADDU16,
MIPS_INS_ADDUH,
MIPS_INS_ADDUH_R,
MIPS_INS_ADDU,
MIPS_INS_ADDU_S,
MIPS_INS_ADDVI,
MIPS_INS_ADDV,
MIPS_INS_ADDWC,
MIPS_INS_ADD_A,
MIPS_INS_ADDI,
MIPS_INS_ADDIU,
MIPS_INS_ALIGN,
MIPS_INS_ALUIPC,
MIPS_INS_AND,
MIPS_INS_AND16,
MIPS_INS_ANDI16,
MIPS_INS_ANDI,
MIPS_INS_APPEND,
MIPS_INS_ASUB_S,
MIPS_INS_ASUB_U,
MIPS_INS_AUI,
MIPS_INS_AUIPC,
MIPS_INS_AVER_S,
MIPS_INS_AVER_U,
MIPS_INS_AVE_S,
MIPS_INS_AVE_U,
MIPS_INS_B16,
MIPS_INS_BADDU,
MIPS_INS_BAL,
MIPS_INS_BALC,
MIPS_INS_BALIGN,
MIPS_INS_BBIT0,
MIPS_INS_BBIT032,
MIPS_INS_BBIT1,
MIPS_INS_BBIT132,
MIPS_INS_BC,
MIPS_INS_BC0F,
MIPS_INS_BC0FL,
MIPS_INS_BC0T,
MIPS_INS_BC0TL,
MIPS_INS_BC1EQZ,
MIPS_INS_BC1F,
MIPS_INS_BC1FL,
MIPS_INS_BC1NEZ,
MIPS_INS_BC1T,
MIPS_INS_BC1TL,
MIPS_INS_BC2EQZ,
MIPS_INS_BC2F,
MIPS_INS_BC2FL,
MIPS_INS_BC2NEZ,
MIPS_INS_BC2T,
MIPS_INS_BC2TL,
MIPS_INS_BC3F,
MIPS_INS_BC3FL,
MIPS_INS_BC3T,
MIPS_INS_BC3TL,
MIPS_INS_BCLRI,
MIPS_INS_BCLR,
MIPS_INS_BEQ,
MIPS_INS_BEQC,
MIPS_INS_BEQL,
MIPS_INS_BEQZ16,
MIPS_INS_BEQZALC,
MIPS_INS_BEQZC,
MIPS_INS_BGEC,
MIPS_INS_BGEUC,
MIPS_INS_BGEZ,
MIPS_INS_BGEZAL,
MIPS_INS_BGEZALC,
MIPS_INS_BGEZALL,
MIPS_INS_BGEZALS,
MIPS_INS_BGEZC,
MIPS_INS_BGEZL,
MIPS_INS_BGTZ,
MIPS_INS_BGTZALC,
MIPS_INS_BGTZC,
MIPS_INS_BGTZL,
MIPS_INS_BINSLI,
MIPS_INS_BINSL,
MIPS_INS_BINSRI,
MIPS_INS_BINSR,
MIPS_INS_BITREV,
MIPS_INS_BITSWAP,
MIPS_INS_BLEZ,
MIPS_INS_BLEZALC,
MIPS_INS_BLEZC,
MIPS_INS_BLEZL,
MIPS_INS_BLTC,
MIPS_INS_BLTUC,
MIPS_INS_BLTZ,
MIPS_INS_BLTZAL,
MIPS_INS_BLTZALC,
MIPS_INS_BLTZALL,
MIPS_INS_BLTZALS,
MIPS_INS_BLTZC,
MIPS_INS_BLTZL,
MIPS_INS_BMNZI,
MIPS_INS_BMNZ,
MIPS_INS_BMZI,
MIPS_INS_BMZ,
MIPS_INS_BNE,
MIPS_INS_BNEC,
MIPS_INS_BNEGI,
MIPS_INS_BNEG,
MIPS_INS_BNEL,
MIPS_INS_BNEZ16,
MIPS_INS_BNEZALC,
MIPS_INS_BNEZC,
MIPS_INS_BNVC,
MIPS_INS_BNZ,
MIPS_INS_BOVC,
MIPS_INS_BPOSGE32,
MIPS_INS_BREAK,
MIPS_INS_BREAK16,
MIPS_INS_BSELI,
MIPS_INS_BSEL,
MIPS_INS_BSETI,
MIPS_INS_BSET,
MIPS_INS_BZ,
MIPS_INS_BEQZ,
MIPS_INS_B,
MIPS_INS_BNEZ,
MIPS_INS_BTEQZ,
MIPS_INS_BTNEZ,
MIPS_INS_CACHE,
MIPS_INS_CEIL,
MIPS_INS_CEQI,
MIPS_INS_CEQ,
MIPS_INS_CFC1,
MIPS_INS_CFCMSA,
MIPS_INS_CINS,
MIPS_INS_CINS32,
MIPS_INS_CLASS,
MIPS_INS_CLEI_S,
MIPS_INS_CLEI_U,
MIPS_INS_CLE_S,
MIPS_INS_CLE_U,
MIPS_INS_CLO,
MIPS_INS_CLTI_S,
MIPS_INS_CLTI_U,
MIPS_INS_CLT_S,
MIPS_INS_CLT_U,
MIPS_INS_CLZ,
MIPS_INS_CMPGDU,
MIPS_INS_CMPGU,
MIPS_INS_CMPU,
MIPS_INS_CMP,
MIPS_INS_COPY_S,
MIPS_INS_COPY_U,
MIPS_INS_CTC1,
MIPS_INS_CTCMSA,
MIPS_INS_CVT,
MIPS_INS_C,
MIPS_INS_CMPI,
MIPS_INS_DADD,
MIPS_INS_DADDI,
MIPS_INS_DADDIU,
MIPS_INS_DADDU,
MIPS_INS_DAHI,
MIPS_INS_DALIGN,
MIPS_INS_DATI,
MIPS_INS_DAUI,
MIPS_INS_DBITSWAP,
MIPS_INS_DCLO,
MIPS_INS_DCLZ,
MIPS_INS_DDIV,
MIPS_INS_DDIVU,
MIPS_INS_DERET,
MIPS_INS_DEXT,
MIPS_INS_DEXTM,
MIPS_INS_DEXTU,
MIPS_INS_DI,
MIPS_INS_DINS,
MIPS_INS_DINSM,
MIPS_INS_DINSU,
MIPS_INS_DIV,
MIPS_INS_DIVU,
MIPS_INS_DIV_S,
MIPS_INS_DIV_U,
MIPS_INS_DLSA,
MIPS_INS_DMFC0,
MIPS_INS_DMFC1,
MIPS_INS_DMFC2,
MIPS_INS_DMOD,
MIPS_INS_DMODU,
MIPS_INS_DMTC0,
MIPS_INS_DMTC1,
MIPS_INS_DMTC2,
MIPS_INS_DMUH,
MIPS_INS_DMUHU,
MIPS_INS_DMUL,
MIPS_INS_DMULT,
MIPS_INS_DMULTU,
MIPS_INS_DMULU,
MIPS_INS_DOTP_S,
MIPS_INS_DOTP_U,
MIPS_INS_DPADD_S,
MIPS_INS_DPADD_U,
MIPS_INS_DPAQX_SA,
MIPS_INS_DPAQX_S,
MIPS_INS_DPAQ_SA,
MIPS_INS_DPAQ_S,
MIPS_INS_DPAU,
MIPS_INS_DPAX,
MIPS_INS_DPA,
MIPS_INS_DPOP,
MIPS_INS_DPSQX_SA,
MIPS_INS_DPSQX_S,
MIPS_INS_DPSQ_SA,
MIPS_INS_DPSQ_S,
MIPS_INS_DPSUB_S,
MIPS_INS_DPSUB_U,
MIPS_INS_DPSU,
MIPS_INS_DPSX,
MIPS_INS_DPS,
MIPS_INS_DROTR,
MIPS_INS_DROTR32,
MIPS_INS_DROTRV,
MIPS_INS_DSBH,
MIPS_INS_DSHD,
MIPS_INS_DSLL,
MIPS_INS_DSLL32,
MIPS_INS_DSLLV,
MIPS_INS_DSRA,
MIPS_INS_DSRA32,
MIPS_INS_DSRAV,
MIPS_INS_DSRL,
MIPS_INS_DSRL32,
MIPS_INS_DSRLV,
MIPS_INS_DSUB,
MIPS_INS_DSUBU,
MIPS_INS_EHB,
MIPS_INS_EI,
MIPS_INS_ERET,
MIPS_INS_EXT,
MIPS_INS_EXTP,
MIPS_INS_EXTPDP,
MIPS_INS_EXTPDPV,
MIPS_INS_EXTPV,
MIPS_INS_EXTRV_RS,
MIPS_INS_EXTRV_R,
MIPS_INS_EXTRV_S,
MIPS_INS_EXTRV,
MIPS_INS_EXTR_RS,
MIPS_INS_EXTR_R,
MIPS_INS_EXTR_S,
MIPS_INS_EXTR,
MIPS_INS_EXTS,
MIPS_INS_EXTS32,
MIPS_INS_ABS,
MIPS_INS_FADD,
MIPS_INS_FCAF,
MIPS_INS_FCEQ,
MIPS_INS_FCLASS,
MIPS_INS_FCLE,
MIPS_INS_FCLT,
MIPS_INS_FCNE,
MIPS_INS_FCOR,
MIPS_INS_FCUEQ,
MIPS_INS_FCULE,
MIPS_INS_FCULT,
MIPS_INS_FCUNE,
MIPS_INS_FCUN,
MIPS_INS_FDIV,
MIPS_INS_FEXDO,
MIPS_INS_FEXP2,
MIPS_INS_FEXUPL,
MIPS_INS_FEXUPR,
MIPS_INS_FFINT_S,
MIPS_INS_FFINT_U,
MIPS_INS_FFQL,
MIPS_INS_FFQR,
MIPS_INS_FILL,
MIPS_INS_FLOG2,
MIPS_INS_FLOOR,
MIPS_INS_FMADD,
MIPS_INS_FMAX_A,
MIPS_INS_FMAX,
MIPS_INS_FMIN_A,
MIPS_INS_FMIN,
MIPS_INS_MOV,
MIPS_INS_FMSUB,
MIPS_INS_FMUL,
MIPS_INS_MUL,
MIPS_INS_NEG,
MIPS_INS_FRCP,
MIPS_INS_FRINT,
MIPS_INS_FRSQRT,
MIPS_INS_FSAF,
MIPS_INS_FSEQ,
MIPS_INS_FSLE,
MIPS_INS_FSLT,
MIPS_INS_FSNE,
MIPS_INS_FSOR,
MIPS_INS_FSQRT,
MIPS_INS_SQRT,
MIPS_INS_FSUB,
MIPS_INS_SUB,
MIPS_INS_FSUEQ,
MIPS_INS_FSULE,
MIPS_INS_FSULT,
MIPS_INS_FSUNE,
MIPS_INS_FSUN,
MIPS_INS_FTINT_S,
MIPS_INS_FTINT_U,
MIPS_INS_FTQ,
MIPS_INS_FTRUNC_S,
MIPS_INS_FTRUNC_U,
MIPS_INS_HADD_S,
MIPS_INS_HADD_U,
MIPS_INS_HSUB_S,
MIPS_INS_HSUB_U,
MIPS_INS_ILVEV,
MIPS_INS_ILVL,
MIPS_INS_ILVOD,
MIPS_INS_ILVR,
MIPS_INS_INS,
MIPS_INS_INSERT,
MIPS_INS_INSV,
MIPS_INS_INSVE,
MIPS_INS_J,
MIPS_INS_JAL,
MIPS_INS_JALR,
MIPS_INS_JALRS16,
MIPS_INS_JALRS,
MIPS_INS_JALS,
MIPS_INS_JALX,
MIPS_INS_JIALC,
MIPS_INS_JIC,
MIPS_INS_JR,
MIPS_INS_JR16,
MIPS_INS_JRADDIUSP,
MIPS_INS_JRC,
MIPS_INS_JALRC,
MIPS_INS_LB,
MIPS_INS_LBU16,
MIPS_INS_LBUX,
MIPS_INS_LBU,
MIPS_INS_LD,
MIPS_INS_LDC1,
MIPS_INS_LDC2,
MIPS_INS_LDC3,
MIPS_INS_LDI,
MIPS_INS_LDL,
MIPS_INS_LDPC,
MIPS_INS_LDR,
MIPS_INS_LDXC1,
MIPS_INS_LH,
MIPS_INS_LHU16,
MIPS_INS_LHX,
MIPS_INS_LHU,
MIPS_INS_LI16,
MIPS_INS_LL,
MIPS_INS_LLD,
MIPS_INS_LSA,
MIPS_INS_LUXC1,
MIPS_INS_LUI,
MIPS_INS_LW,
MIPS_INS_LW16,
MIPS_INS_LWC1,
MIPS_INS_LWC2,
MIPS_INS_LWC3,
MIPS_INS_LWL,
MIPS_INS_LWM16,
MIPS_INS_LWM32,
MIPS_INS_LWPC,
MIPS_INS_LWP,
MIPS_INS_LWR,
MIPS_INS_LWUPC,
MIPS_INS_LWU,
MIPS_INS_LWX,
MIPS_INS_LWXC1,
MIPS_INS_LWXS,
MIPS_INS_LI,
MIPS_INS_MADD,
MIPS_INS_MADDF,
MIPS_INS_MADDR_Q,
MIPS_INS_MADDU,
MIPS_INS_MADDV,
MIPS_INS_MADD_Q,
MIPS_INS_MAQ_SA,
MIPS_INS_MAQ_S,
MIPS_INS_MAXA,
MIPS_INS_MAXI_S,
MIPS_INS_MAXI_U,
MIPS_INS_MAX_A,
MIPS_INS_MAX,
MIPS_INS_MAX_S,
MIPS_INS_MAX_U,
MIPS_INS_MFC0,
MIPS_INS_MFC1,
MIPS_INS_MFC2,
MIPS_INS_MFHC1,
MIPS_INS_MFHI,
MIPS_INS_MFLO,
MIPS_INS_MINA,
MIPS_INS_MINI_S,
MIPS_INS_MINI_U,
MIPS_INS_MIN_A,
MIPS_INS_MIN,
MIPS_INS_MIN_S,
MIPS_INS_MIN_U,
MIPS_INS_MOD,
MIPS_INS_MODSUB,
MIPS_INS_MODU,
MIPS_INS_MOD_S,
MIPS_INS_MOD_U,
MIPS_INS_MOVE,
MIPS_INS_MOVEP,
MIPS_INS_MOVF,
MIPS_INS_MOVN,
MIPS_INS_MOVT,
MIPS_INS_MOVZ,
MIPS_INS_MSUB,
MIPS_INS_MSUBF,
MIPS_INS_MSUBR_Q,
MIPS_INS_MSUBU,
MIPS_INS_MSUBV,
MIPS_INS_MSUB_Q,
MIPS_INS_MTC0,
MIPS_INS_MTC1,
MIPS_INS_MTC2,
MIPS_INS_MTHC1,
MIPS_INS_MTHI,
MIPS_INS_MTHLIP,
MIPS_INS_MTLO,
MIPS_INS_MTM0,
MIPS_INS_MTM1,
MIPS_INS_MTM2,
MIPS_INS_MTP0,
MIPS_INS_MTP1,
MIPS_INS_MTP2,
MIPS_INS_MUH,
MIPS_INS_MUHU,
MIPS_INS_MULEQ_S,
MIPS_INS_MULEU_S,
MIPS_INS_MULQ_RS,
MIPS_INS_MULQ_S,
MIPS_INS_MULR_Q,
MIPS_INS_MULSAQ_S,
MIPS_INS_MULSA,
MIPS_INS_MULT,
MIPS_INS_MULTU,
MIPS_INS_MULU,
MIPS_INS_MULV,
MIPS_INS_MUL_Q,
MIPS_INS_MUL_S,
MIPS_INS_NLOC,
MIPS_INS_NLZC,
MIPS_INS_NMADD,
MIPS_INS_NMSUB,
MIPS_INS_NOR,
MIPS_INS_NORI,
MIPS_INS_NOT16,
MIPS_INS_NOT,
MIPS_INS_OR,
MIPS_INS_OR16,
MIPS_INS_ORI,
MIPS_INS_PACKRL,
MIPS_INS_PAUSE,
MIPS_INS_PCKEV,
MIPS_INS_PCKOD,
MIPS_INS_PCNT,
MIPS_INS_PICK,
MIPS_INS_POP,
MIPS_INS_PRECEQU,
MIPS_INS_PRECEQ,
MIPS_INS_PRECEU,
MIPS_INS_PRECRQU_S,
MIPS_INS_PRECRQ,
MIPS_INS_PRECRQ_RS,
MIPS_INS_PRECR,
MIPS_INS_PRECR_SRA,
MIPS_INS_PRECR_SRA_R,
MIPS_INS_PREF,
MIPS_INS_PREPEND,
MIPS_INS_RADDU,
MIPS_INS_RDDSP,
MIPS_INS_RDHWR,
MIPS_INS_REPLV,
MIPS_INS_REPL,
MIPS_INS_RINT,
MIPS_INS_ROTR,
MIPS_INS_ROTRV,
MIPS_INS_ROUND,
MIPS_INS_SAT_S,
MIPS_INS_SAT_U,
MIPS_INS_SB,
MIPS_INS_SB16,
MIPS_INS_SC,
MIPS_INS_SCD,
MIPS_INS_SD,
MIPS_INS_SDBBP,
MIPS_INS_SDBBP16,
MIPS_INS_SDC1,
MIPS_INS_SDC2,
MIPS_INS_SDC3,
MIPS_INS_SDL,
MIPS_INS_SDR,
MIPS_INS_SDXC1,
MIPS_INS_SEB,
MIPS_INS_SEH,
MIPS_INS_SELEQZ,
MIPS_INS_SELNEZ,
MIPS_INS_SEL,
MIPS_INS_SEQ,
MIPS_INS_SEQI,
MIPS_INS_SH,
MIPS_INS_SH16,
MIPS_INS_SHF,
MIPS_INS_SHILO,
MIPS_INS_SHILOV,
MIPS_INS_SHLLV,
MIPS_INS_SHLLV_S,
MIPS_INS_SHLL,
MIPS_INS_SHLL_S,
MIPS_INS_SHRAV,
MIPS_INS_SHRAV_R,
MIPS_INS_SHRA,
MIPS_INS_SHRA_R,
MIPS_INS_SHRLV,
MIPS_INS_SHRL,
MIPS_INS_SLDI,
MIPS_INS_SLD,
MIPS_INS_SLL,
MIPS_INS_SLL16,
MIPS_INS_SLLI,
MIPS_INS_SLLV,
MIPS_INS_SLT,
MIPS_INS_SLTI,
MIPS_INS_SLTIU,
MIPS_INS_SLTU,
MIPS_INS_SNE,
MIPS_INS_SNEI,
MIPS_INS_SPLATI,
MIPS_INS_SPLAT,
MIPS_INS_SRA,
MIPS_INS_SRAI,
MIPS_INS_SRARI,
MIPS_INS_SRAR,
MIPS_INS_SRAV,
MIPS_INS_SRL,
MIPS_INS_SRL16,
MIPS_INS_SRLI,
MIPS_INS_SRLRI,
MIPS_INS_SRLR,
MIPS_INS_SRLV,
MIPS_INS_SSNOP,
MIPS_INS_ST,
MIPS_INS_SUBQH,
MIPS_INS_SUBQH_R,
MIPS_INS_SUBQ,
MIPS_INS_SUBQ_S,
MIPS_INS_SUBSUS_U,
MIPS_INS_SUBSUU_S,
MIPS_INS_SUBS_S,
MIPS_INS_SUBS_U,
MIPS_INS_SUBU16,
MIPS_INS_SUBUH,
MIPS_INS_SUBUH_R,
MIPS_INS_SUBU,
MIPS_INS_SUBU_S,
MIPS_INS_SUBVI,
MIPS_INS_SUBV,
MIPS_INS_SUXC1,
MIPS_INS_SW,
MIPS_INS_SW16,
MIPS_INS_SWC1,
MIPS_INS_SWC2,
MIPS_INS_SWC3,
MIPS_INS_SWL,
MIPS_INS_SWM16,
MIPS_INS_SWM32,
MIPS_INS_SWP,
MIPS_INS_SWR,
MIPS_INS_SWXC1,
MIPS_INS_SYNC,
MIPS_INS_SYNCI,
MIPS_INS_SYSCALL,
MIPS_INS_TEQ,
MIPS_INS_TEQI,
MIPS_INS_TGE,
MIPS_INS_TGEI,
MIPS_INS_TGEIU,
MIPS_INS_TGEU,
MIPS_INS_TLBP,
MIPS_INS_TLBR,
MIPS_INS_TLBWI,
MIPS_INS_TLBWR,
MIPS_INS_TLT,
MIPS_INS_TLTI,
MIPS_INS_TLTIU,
MIPS_INS_TLTU,
MIPS_INS_TNE,
MIPS_INS_TNEI,
MIPS_INS_TRUNC,
MIPS_INS_V3MULU,
MIPS_INS_VMM0,
MIPS_INS_VMULU,
MIPS_INS_VSHF,
MIPS_INS_WAIT,
MIPS_INS_WRDSP,
MIPS_INS_WSBH,
MIPS_INS_XOR,
MIPS_INS_XOR16,
MIPS_INS_XORI,
//> some alias instructions
MIPS_INS_NOP,
MIPS_INS_NEGU,
//> special instructions
MIPS_INS_JALR_HB, // jump and link with Hazard Barrier
MIPS_INS_JR_HB, // jump register with Hazard Barrier
MIPS_INS_ENDING,
} mips_insn;
/// Group of MIPS instructions
typedef enum mips_insn_group {
MIPS_GRP_INVALID = 0, ///< = CS_GRP_INVALID
// Generic groups
// all jump instructions (conditional+direct+indirect jumps)
MIPS_GRP_JUMP, ///< = CS_GRP_JUMP
// all call instructions
MIPS_GRP_CALL, ///< = CS_GRP_CALL
// all return instructions
MIPS_GRP_RET, ///< = CS_GRP_RET
// all interrupt instructions (int+syscall)
MIPS_GRP_INT, ///< = CS_GRP_INT
// all interrupt return instructions
MIPS_GRP_IRET, ///< = CS_GRP_IRET
// all privileged instructions
MIPS_GRP_PRIVILEGE, ///< = CS_GRP_PRIVILEGE
// all relative branching instructions
MIPS_GRP_BRANCH_RELATIVE, ///< = CS_GRP_BRANCH_RELATIVE
// Architecture-specific groups
MIPS_GRP_BITCOUNT = 128,
MIPS_GRP_DSP,
MIPS_GRP_DSPR2,
MIPS_GRP_FPIDX,
MIPS_GRP_MSA,
MIPS_GRP_MIPS32R2,
MIPS_GRP_MIPS64,
MIPS_GRP_MIPS64R2,
MIPS_GRP_SEINREG,
MIPS_GRP_STDENC,
MIPS_GRP_SWAP,
MIPS_GRP_MICROMIPS,
MIPS_GRP_MIPS16MODE,
MIPS_GRP_FP64BIT,
MIPS_GRP_NONANSFPMATH,
MIPS_GRP_NOTFP64BIT,
MIPS_GRP_NOTINMICROMIPS,
MIPS_GRP_NOTNACL,
MIPS_GRP_NOTMIPS32R6,
MIPS_GRP_NOTMIPS64R6,
MIPS_GRP_CNMIPS,
MIPS_GRP_MIPS32,
MIPS_GRP_MIPS32R6,
MIPS_GRP_MIPS64R6,
MIPS_GRP_MIPS2,
MIPS_GRP_MIPS3,
MIPS_GRP_MIPS3_32,
MIPS_GRP_MIPS3_32R2,
MIPS_GRP_MIPS4_32,
MIPS_GRP_MIPS4_32R2,
MIPS_GRP_MIPS5_32R2,
MIPS_GRP_GP32BIT,
MIPS_GRP_GP64BIT,
MIPS_GRP_ENDING,
} mips_insn_group;
#ifdef __cplusplus
}
#endif
#endif

204
capstone/mos65xx.h Normal file
View File

@ -0,0 +1,204 @@
#ifndef CAPSTONE_MOS65XX_H
#define CAPSTONE_MOS65XX_H
/* Capstone Disassembly Engine */
/* By Sebastian Macke <sebastian@macke.de, 2018 */
#ifdef __cplusplus
extern "C" {
#endif
#include "platform.h"
/// MOS65XX registers and special registers
typedef enum mos65xx_reg {
MOS65XX_REG_INVALID = 0,
MOS65XX_REG_ACC, ///< accumulator
MOS65XX_REG_X, ///< X index register
MOS65XX_REG_Y, ///< Y index register
MOS65XX_REG_P, ///< status register
MOS65XX_REG_SP, ///< stack pointer register
MOS65XX_REG_DP, ///< direct page register
MOS65XX_REG_B, ///< data bank register
MOS65XX_REG_K, ///< program bank register
MOS65XX_REG_ENDING, // <-- mark the end of the list of registers
} mos65xx_reg;
/// MOS65XX Addressing Modes
typedef enum mos65xx_address_mode {
MOS65XX_AM_NONE = 0, ///< No address mode.
MOS65XX_AM_IMP, ///< implied addressing (no addressing mode)
MOS65XX_AM_ACC, ///< accumulator addressing
MOS65XX_AM_IMM, ///< 8/16 Bit immediate value
MOS65XX_AM_REL, ///< relative addressing used by branches
MOS65XX_AM_INT, ///< interrupt addressing
MOS65XX_AM_BLOCK, ///< memory block addressing
MOS65XX_AM_ZP, ///< zeropage addressing
MOS65XX_AM_ZP_X, ///< indexed zeropage addressing by the X index register
MOS65XX_AM_ZP_Y, ///< indexed zeropage addressing by the Y index register
MOS65XX_AM_ZP_REL, ///< zero page address, branch relative address
MOS65XX_AM_ZP_IND, ///< indirect zeropage addressing
MOS65XX_AM_ZP_X_IND, ///< indexed zeropage indirect addressing by the X index register
MOS65XX_AM_ZP_IND_Y, ///< indirect zeropage indexed addressing by the Y index register
MOS65XX_AM_ZP_IND_LONG, ///< zeropage indirect long addressing
MOS65XX_AM_ZP_IND_LONG_Y, ///< zeropage indirect long addressing indexed by Y register
MOS65XX_AM_ABS, ///< absolute addressing
MOS65XX_AM_ABS_X, ///< indexed absolute addressing by the X index register
MOS65XX_AM_ABS_Y, ///< indexed absolute addressing by the Y index register
MOS65XX_AM_ABS_IND, ///< absolute indirect addressing
MOS65XX_AM_ABS_X_IND, ///< indexed absolute indirect addressing by the X index register
MOS65XX_AM_ABS_IND_LONG, ///< absolute indirect long addressing
MOS65XX_AM_ABS_LONG, ///< absolute long address mode
MOS65XX_AM_ABS_LONG_X, ///< absolute long address mode, indexed by X register
MOS65XX_AM_SR, ///< stack relative addressing
MOS65XX_AM_SR_IND_Y, ///< indirect stack relative addressing indexed by the Y index register
} mos65xx_address_mode;
/// MOS65XX instruction
typedef enum mos65xx_insn {
MOS65XX_INS_INVALID = 0,
MOS65XX_INS_ADC,
MOS65XX_INS_AND,
MOS65XX_INS_ASL,
MOS65XX_INS_BBR,
MOS65XX_INS_BBS,
MOS65XX_INS_BCC,
MOS65XX_INS_BCS,
MOS65XX_INS_BEQ,
MOS65XX_INS_BIT,
MOS65XX_INS_BMI,
MOS65XX_INS_BNE,
MOS65XX_INS_BPL,
MOS65XX_INS_BRA,
MOS65XX_INS_BRK,
MOS65XX_INS_BRL,
MOS65XX_INS_BVC,
MOS65XX_INS_BVS,
MOS65XX_INS_CLC,
MOS65XX_INS_CLD,
MOS65XX_INS_CLI,
MOS65XX_INS_CLV,
MOS65XX_INS_CMP,
MOS65XX_INS_COP,
MOS65XX_INS_CPX,
MOS65XX_INS_CPY,
MOS65XX_INS_DEC,
MOS65XX_INS_DEX,
MOS65XX_INS_DEY,
MOS65XX_INS_EOR,
MOS65XX_INS_INC,
MOS65XX_INS_INX,
MOS65XX_INS_INY,
MOS65XX_INS_JML,
MOS65XX_INS_JMP,
MOS65XX_INS_JSL,
MOS65XX_INS_JSR,
MOS65XX_INS_LDA,
MOS65XX_INS_LDX,
MOS65XX_INS_LDY,
MOS65XX_INS_LSR,
MOS65XX_INS_MVN,
MOS65XX_INS_MVP,
MOS65XX_INS_NOP,
MOS65XX_INS_ORA,
MOS65XX_INS_PEA,
MOS65XX_INS_PEI,
MOS65XX_INS_PER,
MOS65XX_INS_PHA,
MOS65XX_INS_PHB,
MOS65XX_INS_PHD,
MOS65XX_INS_PHK,
MOS65XX_INS_PHP,
MOS65XX_INS_PHX,
MOS65XX_INS_PHY,
MOS65XX_INS_PLA,
MOS65XX_INS_PLB,
MOS65XX_INS_PLD,
MOS65XX_INS_PLP,
MOS65XX_INS_PLX,
MOS65XX_INS_PLY,
MOS65XX_INS_REP,
MOS65XX_INS_RMB,
MOS65XX_INS_ROL,
MOS65XX_INS_ROR,
MOS65XX_INS_RTI,
MOS65XX_INS_RTL,
MOS65XX_INS_RTS,
MOS65XX_INS_SBC,
MOS65XX_INS_SEC,
MOS65XX_INS_SED,
MOS65XX_INS_SEI,
MOS65XX_INS_SEP,
MOS65XX_INS_SMB,
MOS65XX_INS_STA,
MOS65XX_INS_STP,
MOS65XX_INS_STX,
MOS65XX_INS_STY,
MOS65XX_INS_STZ,
MOS65XX_INS_TAX,
MOS65XX_INS_TAY,
MOS65XX_INS_TCD,
MOS65XX_INS_TCS,
MOS65XX_INS_TDC,
MOS65XX_INS_TRB,
MOS65XX_INS_TSB,
MOS65XX_INS_TSC,
MOS65XX_INS_TSX,
MOS65XX_INS_TXA,
MOS65XX_INS_TXS,
MOS65XX_INS_TXY,
MOS65XX_INS_TYA,
MOS65XX_INS_TYX,
MOS65XX_INS_WAI,
MOS65XX_INS_WDM,
MOS65XX_INS_XBA,
MOS65XX_INS_XCE,
MOS65XX_INS_ENDING, // <-- mark the end of the list of instructions
} mos65xx_insn;
/// Group of MOS65XX instructions
typedef enum mos65xx_group_type {
MOS65XX_GRP_INVALID = 0, ///< CS_GRP_INVALID
MOS65XX_GRP_JUMP, ///< = CS_GRP_JUMP
MOS65XX_GRP_CALL, ///< = CS_GRP_RET
MOS65XX_GRP_RET, ///< = CS_GRP_RET
MOS65XX_GRP_INT, ///< = CS_GRP_INT
MOS65XX_GRP_IRET = 5, ///< = CS_GRP_IRET
MOS65XX_GRP_BRANCH_RELATIVE = 6, ///< = CS_GRP_BRANCH_RELATIVE
MOS65XX_GRP_ENDING,// <-- mark the end of the list of groups
} mos65xx_group_type;
/// Operand type for instruction's operands
typedef enum mos65xx_op_type {
MOS65XX_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized).
MOS65XX_OP_REG, ///< = CS_OP_REG (Register operand).
MOS65XX_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
MOS65XX_OP_MEM, ///< = CS_OP_MEM (Memory operand).
} mos65xx_op_type;
/// Instruction operand
typedef struct cs_mos65xx_op {
mos65xx_op_type type; ///< operand type
union {
mos65xx_reg reg; ///< register value for REG operand
uint16_t imm; ///< immediate value for IMM operand
uint32_t mem; ///< address for MEM operand
};
} cs_mos65xx_op;
/// The MOS65XX address mode and it's operands
typedef struct cs_mos65xx {
mos65xx_address_mode am;
bool modifies_flags;
/// Number of operands of this instruction,
/// or 0 when instruction has no operand.
uint8_t op_count;
cs_mos65xx_op operands[3]; ///< operands for this instruction.
} cs_mos65xx;
#ifdef __cplusplus
}
#endif
#endif //CAPSTONE_MOS65XX_H

122
capstone/platform.h Normal file
View File

@ -0,0 +1,122 @@
/* Capstone Disassembly Engine */
/* By Axel Souchet & Nguyen Anh Quynh, 2014 */
#ifndef CAPSTONE_PLATFORM_H
#define CAPSTONE_PLATFORM_H
// handle C99 issue (for pre-2013 VisualStudio)
#if !defined(__CYGWIN__) && !defined(__MINGW32__) && !defined(__MINGW64__) && (defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64))
// MSVC
// stdbool.h
#if (_MSC_VER < 1800) || defined(_KERNEL_MODE)
// this system does not have stdbool.h
#ifndef __cplusplus
typedef unsigned char bool;
#define false 0
#define true 1
#endif // __cplusplus
#else
// VisualStudio 2013+ -> C99 is supported
#include <stdbool.h>
#endif // (_MSC_VER < 1800) || defined(_KERNEL_MODE)
#else
// not MSVC -> C99 is supported
#include <stdbool.h>
#endif // !defined(__CYGWIN__) && !defined(__MINGW32__) && !defined(__MINGW64__) && (defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64))
// handle inttypes.h / stdint.h compatibility
#if defined(_WIN32_WCE) && (_WIN32_WCE < 0x800)
#include "windowsce/stdint.h"
#endif // defined(_WIN32_WCE) && (_WIN32_WCE < 0x800)
#if defined(CAPSTONE_HAS_OSXKERNEL) || (defined(_MSC_VER) && (_MSC_VER <= 1700 || defined(_KERNEL_MODE)))
// this system does not have inttypes.h
#if defined(_MSC_VER) && (_MSC_VER <= 1600 || defined(_KERNEL_MODE))
// this system does not have stdint.h
typedef signed char int8_t;
typedef signed short int16_t;
typedef signed int int32_t;
typedef unsigned char uint8_t;
typedef unsigned short uint16_t;
typedef unsigned int uint32_t;
typedef signed long long int64_t;
typedef unsigned long long uint64_t;
#endif // defined(_MSC_VER) && (_MSC_VER <= 1600 || defined(_KERNEL_MODE))
#if defined(_MSC_VER) && (_MSC_VER < 1600 || defined(_KERNEL_MODE))
#define INT8_MIN (-127i8 - 1)
#define INT16_MIN (-32767i16 - 1)
#define INT32_MIN (-2147483647i32 - 1)
#define INT64_MIN (-9223372036854775807i64 - 1)
#define INT8_MAX 127i8
#define INT16_MAX 32767i16
#define INT32_MAX 2147483647i32
#define INT64_MAX 9223372036854775807i64
#define UINT8_MAX 0xffui8
#define UINT16_MAX 0xffffui16
#define UINT32_MAX 0xffffffffui32
#define UINT64_MAX 0xffffffffffffffffui64
#endif // defined(_MSC_VER) && (_MSC_VER < 1600 || defined(_KERNEL_MODE))
#ifdef CAPSTONE_HAS_OSXKERNEL
// this system has stdint.h
#include <stdint.h>
#endif
#define __PRI_8_LENGTH_MODIFIER__ "hh"
#define __PRI_64_LENGTH_MODIFIER__ "ll"
#define PRId8 __PRI_8_LENGTH_MODIFIER__ "d"
#define PRIi8 __PRI_8_LENGTH_MODIFIER__ "i"
#define PRIo8 __PRI_8_LENGTH_MODIFIER__ "o"
#define PRIu8 __PRI_8_LENGTH_MODIFIER__ "u"
#define PRIx8 __PRI_8_LENGTH_MODIFIER__ "x"
#define PRIX8 __PRI_8_LENGTH_MODIFIER__ "X"
#define PRId16 "hd"
#define PRIi16 "hi"
#define PRIo16 "ho"
#define PRIu16 "hu"
#define PRIx16 "hx"
#define PRIX16 "hX"
#if defined(_MSC_VER) && _MSC_VER <= 1700
#define PRId32 "ld"
#define PRIi32 "li"
#define PRIo32 "lo"
#define PRIu32 "lu"
#define PRIx32 "lx"
#define PRIX32 "lX"
#else // OSX
#define PRId32 "d"
#define PRIi32 "i"
#define PRIo32 "o"
#define PRIu32 "u"
#define PRIx32 "x"
#define PRIX32 "X"
#endif // defined(_MSC_VER) && _MSC_VER <= 1700
#if defined(_MSC_VER) && _MSC_VER <= 1700
// redefine functions from inttypes.h used in cstool
#define strtoull _strtoui64
#endif
#define PRId64 __PRI_64_LENGTH_MODIFIER__ "d"
#define PRIi64 __PRI_64_LENGTH_MODIFIER__ "i"
#define PRIo64 __PRI_64_LENGTH_MODIFIER__ "o"
#define PRIu64 __PRI_64_LENGTH_MODIFIER__ "u"
#define PRIx64 __PRI_64_LENGTH_MODIFIER__ "x"
#define PRIX64 __PRI_64_LENGTH_MODIFIER__ "X"
#else
// this system has inttypes.h by default
#include <inttypes.h>
#endif // defined(CAPSTONE_HAS_OSXKERNEL) || (defined(_MSC_VER) && (_MSC_VER <= 1700 || defined(_KERNEL_MODE)))
#endif

2108
capstone/ppc.h Normal file
View File

File diff suppressed because it is too large Load Diff

515
capstone/riscv.h Normal file
View File

@ -0,0 +1,515 @@
#ifndef CAPSTONE_RISCV_H
#define CAPSTONE_RISCV_H
/* Capstone Disassembly Engine */
/* RISC-V Backend By Rodrigo Cortes Porto <porto703@gmail.com> &
Shawn Chang <citypw@gmail.com>, HardenedLinux@2018 */
#ifdef __cplusplus
extern "C" {
#endif
#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
#include <stdint.h>
#endif
#include "platform.h"
// GCC MIPS toolchain has a default macro called "mips" which breaks
// compilation
//#undef riscv
#ifdef _MSC_VER
#pragma warning(disable:4201)
#endif
//> Operand type for instruction's operands
typedef enum riscv_op_type {
RISCV_OP_INVALID = 0, // = CS_OP_INVALID (Uninitialized).
RISCV_OP_REG, // = CS_OP_REG (Register operand).
RISCV_OP_IMM, // = CS_OP_IMM (Immediate operand).
RISCV_OP_MEM, // = CS_OP_MEM (Memory operand).
} riscv_op_type;
// Instruction's operand referring to memory
// This is associated with RISCV_OP_MEM operand type above
typedef struct riscv_op_mem {
unsigned int base; // base register
int64_t disp; // displacement/offset value
} riscv_op_mem;
// Instruction operand
typedef struct cs_riscv_op {
riscv_op_type type; // operand type
union {
unsigned int reg; // register value for REG operand
int64_t imm; // immediate value for IMM operand
riscv_op_mem mem; // base/disp value for MEM operand
};
} cs_riscv_op;
// Instruction structure
typedef struct cs_riscv {
// Does this instruction need effective address or not.
bool need_effective_addr;
// Number of operands of this instruction,
// or 0 when instruction has no operand.
uint8_t op_count;
cs_riscv_op operands[8]; // operands for this instruction.
} cs_riscv;
//> RISCV registers
typedef enum riscv_reg {
RISCV_REG_INVALID = 0,
//> General purpose registers
RISCV_REG_X0, // "zero"
RISCV_REG_ZERO = RISCV_REG_X0, // "zero"
RISCV_REG_X1, // "ra"
RISCV_REG_RA = RISCV_REG_X1, // "ra"
RISCV_REG_X2, // "sp"
RISCV_REG_SP = RISCV_REG_X2, // "sp"
RISCV_REG_X3, // "gp"
RISCV_REG_GP = RISCV_REG_X3, // "gp"
RISCV_REG_X4, // "tp"
RISCV_REG_TP = RISCV_REG_X4, // "tp"
RISCV_REG_X5, // "t0"
RISCV_REG_T0 = RISCV_REG_X5, // "t0"
RISCV_REG_X6, // "t1"
RISCV_REG_T1 = RISCV_REG_X6, // "t1"
RISCV_REG_X7, // "t2"
RISCV_REG_T2 = RISCV_REG_X7, // "t2"
RISCV_REG_X8, // "s0/fp"
RISCV_REG_S0 = RISCV_REG_X8, // "s0"
RISCV_REG_FP = RISCV_REG_X8, // "fp"
RISCV_REG_X9, // "s1"
RISCV_REG_S1 = RISCV_REG_X9, // "s1"
RISCV_REG_X10, // "a0"
RISCV_REG_A0 = RISCV_REG_X10, // "a0"
RISCV_REG_X11, // "a1"
RISCV_REG_A1 = RISCV_REG_X11, // "a1"
RISCV_REG_X12, // "a2"
RISCV_REG_A2 = RISCV_REG_X12, // "a2"
RISCV_REG_X13, // "a3"
RISCV_REG_A3 = RISCV_REG_X13, // "a3"
RISCV_REG_X14, // "a4"
RISCV_REG_A4 = RISCV_REG_X14, // "a4"
RISCV_REG_X15, // "a5"
RISCV_REG_A5 = RISCV_REG_X15, // "a5"
RISCV_REG_X16, // "a6"
RISCV_REG_A6 = RISCV_REG_X16, // "a6"
RISCV_REG_X17, // "a7"
RISCV_REG_A7 = RISCV_REG_X17, // "a7"
RISCV_REG_X18, // "s2"
RISCV_REG_S2 = RISCV_REG_X18, // "s2"
RISCV_REG_X19, // "s3"
RISCV_REG_S3 = RISCV_REG_X19, // "s3"
RISCV_REG_X20, // "s4"
RISCV_REG_S4 = RISCV_REG_X20, // "s4"
RISCV_REG_X21, // "s5"
RISCV_REG_S5 = RISCV_REG_X21, // "s5"
RISCV_REG_X22, // "s6"
RISCV_REG_S6 = RISCV_REG_X22, // "s6"
RISCV_REG_X23, // "s7"
RISCV_REG_S7 = RISCV_REG_X23, // "s7"
RISCV_REG_X24, // "s8"
RISCV_REG_S8 = RISCV_REG_X24, // "s8"
RISCV_REG_X25, // "s9"
RISCV_REG_S9 = RISCV_REG_X25, // "s9"
RISCV_REG_X26, // "s10"
RISCV_REG_S10 = RISCV_REG_X26, // "s10"
RISCV_REG_X27, // "s11"
RISCV_REG_S11 = RISCV_REG_X27, // "s11"
RISCV_REG_X28, // "t3"
RISCV_REG_T3 = RISCV_REG_X28, // "t3"
RISCV_REG_X29, // "t4"
RISCV_REG_T4 = RISCV_REG_X29, // "t4"
RISCV_REG_X30, // "t5"
RISCV_REG_T5 = RISCV_REG_X30, // "t5"
RISCV_REG_X31, // "t6"
RISCV_REG_T6 = RISCV_REG_X31, // "t6"
//> Floating-point registers
RISCV_REG_F0_32, // "ft0"
RISCV_REG_F0_64, // "ft0"
RISCV_REG_F1_32, // "ft1"
RISCV_REG_F1_64, // "ft1"
RISCV_REG_F2_32, // "ft2"
RISCV_REG_F2_64, // "ft2"
RISCV_REG_F3_32, // "ft3"
RISCV_REG_F3_64, // "ft3"
RISCV_REG_F4_32, // "ft4"
RISCV_REG_F4_64, // "ft4"
RISCV_REG_F5_32, // "ft5"
RISCV_REG_F5_64, // "ft5"
RISCV_REG_F6_32, // "ft6"
RISCV_REG_F6_64, // "ft6"
RISCV_REG_F7_32, // "ft7"
RISCV_REG_F7_64, // "ft7"
RISCV_REG_F8_32, // "fs0"
RISCV_REG_F8_64, // "fs0"
RISCV_REG_F9_32, // "fs1"
RISCV_REG_F9_64, // "fs1"
RISCV_REG_F10_32, // "fa0"
RISCV_REG_F10_64, // "fa0"
RISCV_REG_F11_32, // "fa1"
RISCV_REG_F11_64, // "fa1"
RISCV_REG_F12_32, // "fa2"
RISCV_REG_F12_64, // "fa2"
RISCV_REG_F13_32, // "fa3"
RISCV_REG_F13_64, // "fa3"
RISCV_REG_F14_32, // "fa4"
RISCV_REG_F14_64, // "fa4"
RISCV_REG_F15_32, // "fa5"
RISCV_REG_F15_64, // "fa5"
RISCV_REG_F16_32, // "fa6"
RISCV_REG_F16_64, // "fa6"
RISCV_REG_F17_32, // "fa7"
RISCV_REG_F17_64, // "fa7"
RISCV_REG_F18_32, // "fs2"
RISCV_REG_F18_64, // "fs2"
RISCV_REG_F19_32, // "fs3"
RISCV_REG_F19_64, // "fs3"
RISCV_REG_F20_32, // "fs4"
RISCV_REG_F20_64, // "fs4"
RISCV_REG_F21_32, // "fs5"
RISCV_REG_F21_64, // "fs5"
RISCV_REG_F22_32, // "fs6"
RISCV_REG_F22_64, // "fs6"
RISCV_REG_F23_32, // "fs7"
RISCV_REG_F23_64, // "fs7"
RISCV_REG_F24_32, // "fs8"
RISCV_REG_F24_64, // "fs8"
RISCV_REG_F25_32, // "fs9"
RISCV_REG_F25_64, // "fs9"
RISCV_REG_F26_32, // "fs10"
RISCV_REG_F26_64, // "fs10"
RISCV_REG_F27_32, // "fs11"
RISCV_REG_F27_64, // "fs11"
RISCV_REG_F28_32, // "ft8"
RISCV_REG_F28_64, // "ft8"
RISCV_REG_F29_32, // "ft9"
RISCV_REG_F29_64, // "ft9"
RISCV_REG_F30_32, // "ft10"
RISCV_REG_F30_64, // "ft10"
RISCV_REG_F31_32, // "ft11"
RISCV_REG_F31_64, // "ft11"
RISCV_REG_ENDING, // <-- mark the end of the list or registers
} riscv_reg;
//> RISCV instruction
typedef enum riscv_insn {
RISCV_INS_INVALID = 0,
RISCV_INS_ADD,
RISCV_INS_ADDI,
RISCV_INS_ADDIW,
RISCV_INS_ADDW,
RISCV_INS_AMOADD_D,
RISCV_INS_AMOADD_D_AQ,
RISCV_INS_AMOADD_D_AQ_RL,
RISCV_INS_AMOADD_D_RL,
RISCV_INS_AMOADD_W,
RISCV_INS_AMOADD_W_AQ,
RISCV_INS_AMOADD_W_AQ_RL,
RISCV_INS_AMOADD_W_RL,
RISCV_INS_AMOAND_D,
RISCV_INS_AMOAND_D_AQ,
RISCV_INS_AMOAND_D_AQ_RL,
RISCV_INS_AMOAND_D_RL,
RISCV_INS_AMOAND_W,
RISCV_INS_AMOAND_W_AQ,
RISCV_INS_AMOAND_W_AQ_RL,
RISCV_INS_AMOAND_W_RL,
RISCV_INS_AMOMAXU_D,
RISCV_INS_AMOMAXU_D_AQ,
RISCV_INS_AMOMAXU_D_AQ_RL,
RISCV_INS_AMOMAXU_D_RL,
RISCV_INS_AMOMAXU_W,
RISCV_INS_AMOMAXU_W_AQ,
RISCV_INS_AMOMAXU_W_AQ_RL,
RISCV_INS_AMOMAXU_W_RL,
RISCV_INS_AMOMAX_D,
RISCV_INS_AMOMAX_D_AQ,
RISCV_INS_AMOMAX_D_AQ_RL,
RISCV_INS_AMOMAX_D_RL,
RISCV_INS_AMOMAX_W,
RISCV_INS_AMOMAX_W_AQ,
RISCV_INS_AMOMAX_W_AQ_RL,
RISCV_INS_AMOMAX_W_RL,
RISCV_INS_AMOMINU_D,
RISCV_INS_AMOMINU_D_AQ,
RISCV_INS_AMOMINU_D_AQ_RL,
RISCV_INS_AMOMINU_D_RL,
RISCV_INS_AMOMINU_W,
RISCV_INS_AMOMINU_W_AQ,
RISCV_INS_AMOMINU_W_AQ_RL,
RISCV_INS_AMOMINU_W_RL,
RISCV_INS_AMOMIN_D,
RISCV_INS_AMOMIN_D_AQ,
RISCV_INS_AMOMIN_D_AQ_RL,
RISCV_INS_AMOMIN_D_RL,
RISCV_INS_AMOMIN_W,
RISCV_INS_AMOMIN_W_AQ,
RISCV_INS_AMOMIN_W_AQ_RL,
RISCV_INS_AMOMIN_W_RL,
RISCV_INS_AMOOR_D,
RISCV_INS_AMOOR_D_AQ,
RISCV_INS_AMOOR_D_AQ_RL,
RISCV_INS_AMOOR_D_RL,
RISCV_INS_AMOOR_W,
RISCV_INS_AMOOR_W_AQ,
RISCV_INS_AMOOR_W_AQ_RL,
RISCV_INS_AMOOR_W_RL,
RISCV_INS_AMOSWAP_D,
RISCV_INS_AMOSWAP_D_AQ,
RISCV_INS_AMOSWAP_D_AQ_RL,
RISCV_INS_AMOSWAP_D_RL,
RISCV_INS_AMOSWAP_W,
RISCV_INS_AMOSWAP_W_AQ,
RISCV_INS_AMOSWAP_W_AQ_RL,
RISCV_INS_AMOSWAP_W_RL,
RISCV_INS_AMOXOR_D,
RISCV_INS_AMOXOR_D_AQ,
RISCV_INS_AMOXOR_D_AQ_RL,
RISCV_INS_AMOXOR_D_RL,
RISCV_INS_AMOXOR_W,
RISCV_INS_AMOXOR_W_AQ,
RISCV_INS_AMOXOR_W_AQ_RL,
RISCV_INS_AMOXOR_W_RL,
RISCV_INS_AND,
RISCV_INS_ANDI,
RISCV_INS_AUIPC,
RISCV_INS_BEQ,
RISCV_INS_BGE,
RISCV_INS_BGEU,
RISCV_INS_BLT,
RISCV_INS_BLTU,
RISCV_INS_BNE,
RISCV_INS_CSRRC,
RISCV_INS_CSRRCI,
RISCV_INS_CSRRS,
RISCV_INS_CSRRSI,
RISCV_INS_CSRRW,
RISCV_INS_CSRRWI,
RISCV_INS_C_ADD,
RISCV_INS_C_ADDI,
RISCV_INS_C_ADDI16SP,
RISCV_INS_C_ADDI4SPN,
RISCV_INS_C_ADDIW,
RISCV_INS_C_ADDW,
RISCV_INS_C_AND,
RISCV_INS_C_ANDI,
RISCV_INS_C_BEQZ,
RISCV_INS_C_BNEZ,
RISCV_INS_C_EBREAK,
RISCV_INS_C_FLD,
RISCV_INS_C_FLDSP,
RISCV_INS_C_FLW,
RISCV_INS_C_FLWSP,
RISCV_INS_C_FSD,
RISCV_INS_C_FSDSP,
RISCV_INS_C_FSW,
RISCV_INS_C_FSWSP,
RISCV_INS_C_J,
RISCV_INS_C_JAL,
RISCV_INS_C_JALR,
RISCV_INS_C_JR,
RISCV_INS_C_LD,
RISCV_INS_C_LDSP,
RISCV_INS_C_LI,
RISCV_INS_C_LUI,
RISCV_INS_C_LW,
RISCV_INS_C_LWSP,
RISCV_INS_C_MV,
RISCV_INS_C_NOP,
RISCV_INS_C_OR,
RISCV_INS_C_SD,
RISCV_INS_C_SDSP,
RISCV_INS_C_SLLI,
RISCV_INS_C_SRAI,
RISCV_INS_C_SRLI,
RISCV_INS_C_SUB,
RISCV_INS_C_SUBW,
RISCV_INS_C_SW,
RISCV_INS_C_SWSP,
RISCV_INS_C_UNIMP,
RISCV_INS_C_XOR,
RISCV_INS_DIV,
RISCV_INS_DIVU,
RISCV_INS_DIVUW,
RISCV_INS_DIVW,
RISCV_INS_EBREAK,
RISCV_INS_ECALL,
RISCV_INS_FADD_D,
RISCV_INS_FADD_S,
RISCV_INS_FCLASS_D,
RISCV_INS_FCLASS_S,
RISCV_INS_FCVT_D_L,
RISCV_INS_FCVT_D_LU,
RISCV_INS_FCVT_D_S,
RISCV_INS_FCVT_D_W,
RISCV_INS_FCVT_D_WU,
RISCV_INS_FCVT_LU_D,
RISCV_INS_FCVT_LU_S,
RISCV_INS_FCVT_L_D,
RISCV_INS_FCVT_L_S,
RISCV_INS_FCVT_S_D,
RISCV_INS_FCVT_S_L,
RISCV_INS_FCVT_S_LU,
RISCV_INS_FCVT_S_W,
RISCV_INS_FCVT_S_WU,
RISCV_INS_FCVT_WU_D,
RISCV_INS_FCVT_WU_S,
RISCV_INS_FCVT_W_D,
RISCV_INS_FCVT_W_S,
RISCV_INS_FDIV_D,
RISCV_INS_FDIV_S,
RISCV_INS_FENCE,
RISCV_INS_FENCE_I,
RISCV_INS_FENCE_TSO,
RISCV_INS_FEQ_D,
RISCV_INS_FEQ_S,
RISCV_INS_FLD,
RISCV_INS_FLE_D,
RISCV_INS_FLE_S,
RISCV_INS_FLT_D,
RISCV_INS_FLT_S,
RISCV_INS_FLW,
RISCV_INS_FMADD_D,
RISCV_INS_FMADD_S,
RISCV_INS_FMAX_D,
RISCV_INS_FMAX_S,
RISCV_INS_FMIN_D,
RISCV_INS_FMIN_S,
RISCV_INS_FMSUB_D,
RISCV_INS_FMSUB_S,
RISCV_INS_FMUL_D,
RISCV_INS_FMUL_S,
RISCV_INS_FMV_D_X,
RISCV_INS_FMV_W_X,
RISCV_INS_FMV_X_D,
RISCV_INS_FMV_X_W,
RISCV_INS_FNMADD_D,
RISCV_INS_FNMADD_S,
RISCV_INS_FNMSUB_D,
RISCV_INS_FNMSUB_S,
RISCV_INS_FSD,
RISCV_INS_FSGNJN_D,
RISCV_INS_FSGNJN_S,
RISCV_INS_FSGNJX_D,
RISCV_INS_FSGNJX_S,
RISCV_INS_FSGNJ_D,
RISCV_INS_FSGNJ_S,
RISCV_INS_FSQRT_D,
RISCV_INS_FSQRT_S,
RISCV_INS_FSUB_D,
RISCV_INS_FSUB_S,
RISCV_INS_FSW,
RISCV_INS_JAL,
RISCV_INS_JALR,
RISCV_INS_LB,
RISCV_INS_LBU,
RISCV_INS_LD,
RISCV_INS_LH,
RISCV_INS_LHU,
RISCV_INS_LR_D,
RISCV_INS_LR_D_AQ,
RISCV_INS_LR_D_AQ_RL,
RISCV_INS_LR_D_RL,
RISCV_INS_LR_W,
RISCV_INS_LR_W_AQ,
RISCV_INS_LR_W_AQ_RL,
RISCV_INS_LR_W_RL,
RISCV_INS_LUI,
RISCV_INS_LW,
RISCV_INS_LWU,
RISCV_INS_MRET,
RISCV_INS_MUL,
RISCV_INS_MULH,
RISCV_INS_MULHSU,
RISCV_INS_MULHU,
RISCV_INS_MULW,
RISCV_INS_OR,
RISCV_INS_ORI,
RISCV_INS_REM,
RISCV_INS_REMU,
RISCV_INS_REMUW,
RISCV_INS_REMW,
RISCV_INS_SB,
RISCV_INS_SC_D,
RISCV_INS_SC_D_AQ,
RISCV_INS_SC_D_AQ_RL,
RISCV_INS_SC_D_RL,
RISCV_INS_SC_W,
RISCV_INS_SC_W_AQ,
RISCV_INS_SC_W_AQ_RL,
RISCV_INS_SC_W_RL,
RISCV_INS_SD,
RISCV_INS_SFENCE_VMA,
RISCV_INS_SH,
RISCV_INS_SLL,
RISCV_INS_SLLI,
RISCV_INS_SLLIW,
RISCV_INS_SLLW,
RISCV_INS_SLT,
RISCV_INS_SLTI,
RISCV_INS_SLTIU,
RISCV_INS_SLTU,
RISCV_INS_SRA,
RISCV_INS_SRAI,
RISCV_INS_SRAIW,
RISCV_INS_SRAW,
RISCV_INS_SRET,
RISCV_INS_SRL,
RISCV_INS_SRLI,
RISCV_INS_SRLIW,
RISCV_INS_SRLW,
RISCV_INS_SUB,
RISCV_INS_SUBW,
RISCV_INS_SW,
RISCV_INS_UNIMP,
RISCV_INS_URET,
RISCV_INS_WFI,
RISCV_INS_XOR,
RISCV_INS_XORI,
RISCV_INS_ENDING,
} riscv_insn;
//> Group of RISCV instructions
typedef enum riscv_insn_group {
RISCV_GRP_INVALID = 0, // = CS_GRP_INVALID
RISCV_GRP_JUMP,
RISCV_GRP_ISRV32 = 128,
RISCV_GRP_ISRV64,
RISCV_GRP_HASSTDEXTA,
RISCV_GRP_HASSTDEXTC,
RISCV_GRP_HASSTDEXTD,
RISCV_GRP_HASSTDEXTF,
RISCV_GRP_HASSTDEXTM,
/*
RISCV_GRP_ISRVA,
RISCV_GRP_ISRVC,
RISCV_GRP_ISRVD,
RISCV_GRP_ISRVCD,
RISCV_GRP_ISRVF,
RISCV_GRP_ISRV32C,
RISCV_GRP_ISRV32CF,
RISCV_GRP_ISRVM,
RISCV_GRP_ISRV64A,
RISCV_GRP_ISRV64C,
RISCV_GRP_ISRV64D,
RISCV_GRP_ISRV64F,
RISCV_GRP_ISRV64M,
*/
RISCV_GRP_ENDING,
} riscv_insn_group;
#ifdef __cplusplus
}
#endif
#endif

520
capstone/sparc.h Normal file
View File

@ -0,0 +1,520 @@
#ifndef CAPSTONE_SPARC_H
#define CAPSTONE_SPARC_H
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2014-2015 */
#ifdef __cplusplus
extern "C" {
#endif
#include "platform.h"
// GCC SPARC toolchain has a default macro called "sparc" which breaks
// compilation
#undef sparc
#ifdef _MSC_VER
#pragma warning(disable:4201)
#endif
/// Enums corresponding to Sparc condition codes, both icc's and fcc's.
typedef enum sparc_cc {
SPARC_CC_INVALID = 0, ///< invalid CC (default)
// Integer condition codes
SPARC_CC_ICC_A = 8+256, ///< Always
SPARC_CC_ICC_N = 0+256, ///< Never
SPARC_CC_ICC_NE = 9+256, ///< Not Equal
SPARC_CC_ICC_E = 1+256, ///< Equal
SPARC_CC_ICC_G = 10+256, ///< Greater
SPARC_CC_ICC_LE = 2+256, ///< Less or Equal
SPARC_CC_ICC_GE = 11+256, ///< Greater or Equal
SPARC_CC_ICC_L = 3+256, ///< Less
SPARC_CC_ICC_GU = 12+256, ///< Greater Unsigned
SPARC_CC_ICC_LEU = 4+256, ///< Less or Equal Unsigned
SPARC_CC_ICC_CC = 13+256, ///< Carry Clear/Great or Equal Unsigned
SPARC_CC_ICC_CS = 5+256, ///< Carry Set/Less Unsigned
SPARC_CC_ICC_POS = 14+256, ///< Positive
SPARC_CC_ICC_NEG = 6+256, ///< Negative
SPARC_CC_ICC_VC = 15+256, ///< Overflow Clear
SPARC_CC_ICC_VS = 7+256, ///< Overflow Set
// Floating condition codes
SPARC_CC_FCC_A = 8+16+256, ///< Always
SPARC_CC_FCC_N = 0+16+256, ///< Never
SPARC_CC_FCC_U = 7+16+256, ///< Unordered
SPARC_CC_FCC_G = 6+16+256, ///< Greater
SPARC_CC_FCC_UG = 5+16+256, ///< Unordered or Greater
SPARC_CC_FCC_L = 4+16+256, ///< Less
SPARC_CC_FCC_UL = 3+16+256, ///< Unordered or Less
SPARC_CC_FCC_LG = 2+16+256, ///< Less or Greater
SPARC_CC_FCC_NE = 1+16+256, ///< Not Equal
SPARC_CC_FCC_E = 9+16+256, ///< Equal
SPARC_CC_FCC_UE = 10+16+256, ///< Unordered or Equal
SPARC_CC_FCC_GE = 11+16+256, ///< Greater or Equal
SPARC_CC_FCC_UGE = 12+16+256, ///< Unordered or Greater or Equal
SPARC_CC_FCC_LE = 13+16+256, ///< Less or Equal
SPARC_CC_FCC_ULE = 14+16+256, ///< Unordered or Less or Equal
SPARC_CC_FCC_O = 15+16+256, ///< Ordered
} sparc_cc;
/// Branch hint
typedef enum sparc_hint {
SPARC_HINT_INVALID = 0, ///< no hint
SPARC_HINT_A = 1 << 0, ///< annul delay slot instruction
SPARC_HINT_PT = 1 << 1, ///< branch taken
SPARC_HINT_PN = 1 << 2, ///< branch NOT taken
} sparc_hint;
/// Operand type for instruction's operands
typedef enum sparc_op_type {
SPARC_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized).
SPARC_OP_REG, ///< = CS_OP_REG (Register operand).
SPARC_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
SPARC_OP_MEM, ///< = CS_OP_MEM (Memory operand).
} sparc_op_type;
/// SPARC registers
typedef enum sparc_reg {
SPARC_REG_INVALID = 0,
SPARC_REG_F0,
SPARC_REG_F1,
SPARC_REG_F2,
SPARC_REG_F3,
SPARC_REG_F4,
SPARC_REG_F5,
SPARC_REG_F6,
SPARC_REG_F7,
SPARC_REG_F8,
SPARC_REG_F9,
SPARC_REG_F10,
SPARC_REG_F11,
SPARC_REG_F12,
SPARC_REG_F13,
SPARC_REG_F14,
SPARC_REG_F15,
SPARC_REG_F16,
SPARC_REG_F17,
SPARC_REG_F18,
SPARC_REG_F19,
SPARC_REG_F20,
SPARC_REG_F21,
SPARC_REG_F22,
SPARC_REG_F23,
SPARC_REG_F24,
SPARC_REG_F25,
SPARC_REG_F26,
SPARC_REG_F27,
SPARC_REG_F28,
SPARC_REG_F29,
SPARC_REG_F30,
SPARC_REG_F31,
SPARC_REG_F32,
SPARC_REG_F34,
SPARC_REG_F36,
SPARC_REG_F38,
SPARC_REG_F40,
SPARC_REG_F42,
SPARC_REG_F44,
SPARC_REG_F46,
SPARC_REG_F48,
SPARC_REG_F50,
SPARC_REG_F52,
SPARC_REG_F54,
SPARC_REG_F56,
SPARC_REG_F58,
SPARC_REG_F60,
SPARC_REG_F62,
SPARC_REG_FCC0, // Floating condition codes
SPARC_REG_FCC1,
SPARC_REG_FCC2,
SPARC_REG_FCC3,
SPARC_REG_FP,
SPARC_REG_G0,
SPARC_REG_G1,
SPARC_REG_G2,
SPARC_REG_G3,
SPARC_REG_G4,
SPARC_REG_G5,
SPARC_REG_G6,
SPARC_REG_G7,
SPARC_REG_I0,
SPARC_REG_I1,
SPARC_REG_I2,
SPARC_REG_I3,
SPARC_REG_I4,
SPARC_REG_I5,
SPARC_REG_I7,
SPARC_REG_ICC, // Integer condition codes
SPARC_REG_L0,
SPARC_REG_L1,
SPARC_REG_L2,
SPARC_REG_L3,
SPARC_REG_L4,
SPARC_REG_L5,
SPARC_REG_L6,
SPARC_REG_L7,
SPARC_REG_O0,
SPARC_REG_O1,
SPARC_REG_O2,
SPARC_REG_O3,
SPARC_REG_O4,
SPARC_REG_O5,
SPARC_REG_O7,
SPARC_REG_SP,
SPARC_REG_Y,
// special register
SPARC_REG_XCC,
SPARC_REG_ENDING, // <-- mark the end of the list of registers
// extras
SPARC_REG_O6 = SPARC_REG_SP,
SPARC_REG_I6 = SPARC_REG_FP,
} sparc_reg;
/// Instruction's operand referring to memory
/// This is associated with SPARC_OP_MEM operand type above
typedef struct sparc_op_mem {
uint8_t base; ///< base register, can be safely interpreted as
///< a value of type `sparc_reg`, but it is only
///< one byte wide
uint8_t index; ///< index register, same conditions apply here
int32_t disp; ///< displacement/offset value
} sparc_op_mem;
/// Instruction operand
typedef struct cs_sparc_op {
sparc_op_type type; ///< operand type
union {
sparc_reg reg; ///< register value for REG operand
int64_t imm; ///< immediate value for IMM operand
sparc_op_mem mem; ///< base/disp value for MEM operand
};
} cs_sparc_op;
/// Instruction structure
typedef struct cs_sparc {
sparc_cc cc; ///< code condition for this insn
sparc_hint hint; ///< branch hint: encoding as bitwise OR of sparc_hint.
/// Number of operands of this instruction,
/// or 0 when instruction has no operand.
uint8_t op_count;
cs_sparc_op operands[4]; ///< operands for this instruction.
} cs_sparc;
/// SPARC instruction
typedef enum sparc_insn {
SPARC_INS_INVALID = 0,
SPARC_INS_ADDCC,
SPARC_INS_ADDX,
SPARC_INS_ADDXCC,
SPARC_INS_ADDXC,
SPARC_INS_ADDXCCC,
SPARC_INS_ADD,
SPARC_INS_ALIGNADDR,
SPARC_INS_ALIGNADDRL,
SPARC_INS_ANDCC,
SPARC_INS_ANDNCC,
SPARC_INS_ANDN,
SPARC_INS_AND,
SPARC_INS_ARRAY16,
SPARC_INS_ARRAY32,
SPARC_INS_ARRAY8,
SPARC_INS_B,
SPARC_INS_JMP,
SPARC_INS_BMASK,
SPARC_INS_FB,
SPARC_INS_BRGEZ,
SPARC_INS_BRGZ,
SPARC_INS_BRLEZ,
SPARC_INS_BRLZ,
SPARC_INS_BRNZ,
SPARC_INS_BRZ,
SPARC_INS_BSHUFFLE,
SPARC_INS_CALL,
SPARC_INS_CASX,
SPARC_INS_CAS,
SPARC_INS_CMASK16,
SPARC_INS_CMASK32,
SPARC_INS_CMASK8,
SPARC_INS_CMP,
SPARC_INS_EDGE16,
SPARC_INS_EDGE16L,
SPARC_INS_EDGE16LN,
SPARC_INS_EDGE16N,
SPARC_INS_EDGE32,
SPARC_INS_EDGE32L,
SPARC_INS_EDGE32LN,
SPARC_INS_EDGE32N,
SPARC_INS_EDGE8,
SPARC_INS_EDGE8L,
SPARC_INS_EDGE8LN,
SPARC_INS_EDGE8N,
SPARC_INS_FABSD,
SPARC_INS_FABSQ,
SPARC_INS_FABSS,
SPARC_INS_FADDD,
SPARC_INS_FADDQ,
SPARC_INS_FADDS,
SPARC_INS_FALIGNDATA,
SPARC_INS_FAND,
SPARC_INS_FANDNOT1,
SPARC_INS_FANDNOT1S,
SPARC_INS_FANDNOT2,
SPARC_INS_FANDNOT2S,
SPARC_INS_FANDS,
SPARC_INS_FCHKSM16,
SPARC_INS_FCMPD,
SPARC_INS_FCMPEQ16,
SPARC_INS_FCMPEQ32,
SPARC_INS_FCMPGT16,
SPARC_INS_FCMPGT32,
SPARC_INS_FCMPLE16,
SPARC_INS_FCMPLE32,
SPARC_INS_FCMPNE16,
SPARC_INS_FCMPNE32,
SPARC_INS_FCMPQ,
SPARC_INS_FCMPS,
SPARC_INS_FDIVD,
SPARC_INS_FDIVQ,
SPARC_INS_FDIVS,
SPARC_INS_FDMULQ,
SPARC_INS_FDTOI,
SPARC_INS_FDTOQ,
SPARC_INS_FDTOS,
SPARC_INS_FDTOX,
SPARC_INS_FEXPAND,
SPARC_INS_FHADDD,
SPARC_INS_FHADDS,
SPARC_INS_FHSUBD,
SPARC_INS_FHSUBS,
SPARC_INS_FITOD,
SPARC_INS_FITOQ,
SPARC_INS_FITOS,
SPARC_INS_FLCMPD,
SPARC_INS_FLCMPS,
SPARC_INS_FLUSHW,
SPARC_INS_FMEAN16,
SPARC_INS_FMOVD,
SPARC_INS_FMOVQ,
SPARC_INS_FMOVRDGEZ,
SPARC_INS_FMOVRQGEZ,
SPARC_INS_FMOVRSGEZ,
SPARC_INS_FMOVRDGZ,
SPARC_INS_FMOVRQGZ,
SPARC_INS_FMOVRSGZ,
SPARC_INS_FMOVRDLEZ,
SPARC_INS_FMOVRQLEZ,
SPARC_INS_FMOVRSLEZ,
SPARC_INS_FMOVRDLZ,
SPARC_INS_FMOVRQLZ,
SPARC_INS_FMOVRSLZ,
SPARC_INS_FMOVRDNZ,
SPARC_INS_FMOVRQNZ,
SPARC_INS_FMOVRSNZ,
SPARC_INS_FMOVRDZ,
SPARC_INS_FMOVRQZ,
SPARC_INS_FMOVRSZ,
SPARC_INS_FMOVS,
SPARC_INS_FMUL8SUX16,
SPARC_INS_FMUL8ULX16,
SPARC_INS_FMUL8X16,
SPARC_INS_FMUL8X16AL,
SPARC_INS_FMUL8X16AU,
SPARC_INS_FMULD,
SPARC_INS_FMULD8SUX16,
SPARC_INS_FMULD8ULX16,
SPARC_INS_FMULQ,
SPARC_INS_FMULS,
SPARC_INS_FNADDD,
SPARC_INS_FNADDS,
SPARC_INS_FNAND,
SPARC_INS_FNANDS,
SPARC_INS_FNEGD,
SPARC_INS_FNEGQ,
SPARC_INS_FNEGS,
SPARC_INS_FNHADDD,
SPARC_INS_FNHADDS,
SPARC_INS_FNOR,
SPARC_INS_FNORS,
SPARC_INS_FNOT1,
SPARC_INS_FNOT1S,
SPARC_INS_FNOT2,
SPARC_INS_FNOT2S,
SPARC_INS_FONE,
SPARC_INS_FONES,
SPARC_INS_FOR,
SPARC_INS_FORNOT1,
SPARC_INS_FORNOT1S,
SPARC_INS_FORNOT2,
SPARC_INS_FORNOT2S,
SPARC_INS_FORS,
SPARC_INS_FPACK16,
SPARC_INS_FPACK32,
SPARC_INS_FPACKFIX,
SPARC_INS_FPADD16,
SPARC_INS_FPADD16S,
SPARC_INS_FPADD32,
SPARC_INS_FPADD32S,
SPARC_INS_FPADD64,
SPARC_INS_FPMERGE,
SPARC_INS_FPSUB16,
SPARC_INS_FPSUB16S,
SPARC_INS_FPSUB32,
SPARC_INS_FPSUB32S,
SPARC_INS_FQTOD,
SPARC_INS_FQTOI,
SPARC_INS_FQTOS,
SPARC_INS_FQTOX,
SPARC_INS_FSLAS16,
SPARC_INS_FSLAS32,
SPARC_INS_FSLL16,
SPARC_INS_FSLL32,
SPARC_INS_FSMULD,
SPARC_INS_FSQRTD,
SPARC_INS_FSQRTQ,
SPARC_INS_FSQRTS,
SPARC_INS_FSRA16,
SPARC_INS_FSRA32,
SPARC_INS_FSRC1,
SPARC_INS_FSRC1S,
SPARC_INS_FSRC2,
SPARC_INS_FSRC2S,
SPARC_INS_FSRL16,
SPARC_INS_FSRL32,
SPARC_INS_FSTOD,
SPARC_INS_FSTOI,
SPARC_INS_FSTOQ,
SPARC_INS_FSTOX,
SPARC_INS_FSUBD,
SPARC_INS_FSUBQ,
SPARC_INS_FSUBS,
SPARC_INS_FXNOR,
SPARC_INS_FXNORS,
SPARC_INS_FXOR,
SPARC_INS_FXORS,
SPARC_INS_FXTOD,
SPARC_INS_FXTOQ,
SPARC_INS_FXTOS,
SPARC_INS_FZERO,
SPARC_INS_FZEROS,
SPARC_INS_JMPL,
SPARC_INS_LDD,
SPARC_INS_LD,
SPARC_INS_LDQ,
SPARC_INS_LDSB,
SPARC_INS_LDSH,
SPARC_INS_LDSW,
SPARC_INS_LDUB,
SPARC_INS_LDUH,
SPARC_INS_LDX,
SPARC_INS_LZCNT,
SPARC_INS_MEMBAR,
SPARC_INS_MOVDTOX,
SPARC_INS_MOV,
SPARC_INS_MOVRGEZ,
SPARC_INS_MOVRGZ,
SPARC_INS_MOVRLEZ,
SPARC_INS_MOVRLZ,
SPARC_INS_MOVRNZ,
SPARC_INS_MOVRZ,
SPARC_INS_MOVSTOSW,
SPARC_INS_MOVSTOUW,
SPARC_INS_MULX,
SPARC_INS_NOP,
SPARC_INS_ORCC,
SPARC_INS_ORNCC,
SPARC_INS_ORN,
SPARC_INS_OR,
SPARC_INS_PDIST,
SPARC_INS_PDISTN,
SPARC_INS_POPC,
SPARC_INS_RD,
SPARC_INS_RESTORE,
SPARC_INS_RETT,
SPARC_INS_SAVE,
SPARC_INS_SDIVCC,
SPARC_INS_SDIVX,
SPARC_INS_SDIV,
SPARC_INS_SETHI,
SPARC_INS_SHUTDOWN,
SPARC_INS_SIAM,
SPARC_INS_SLLX,
SPARC_INS_SLL,
SPARC_INS_SMULCC,
SPARC_INS_SMUL,
SPARC_INS_SRAX,
SPARC_INS_SRA,
SPARC_INS_SRLX,
SPARC_INS_SRL,
SPARC_INS_STBAR,
SPARC_INS_STB,
SPARC_INS_STD,
SPARC_INS_ST,
SPARC_INS_STH,
SPARC_INS_STQ,
SPARC_INS_STX,
SPARC_INS_SUBCC,
SPARC_INS_SUBX,
SPARC_INS_SUBXCC,
SPARC_INS_SUB,
SPARC_INS_SWAP,
SPARC_INS_TADDCCTV,
SPARC_INS_TADDCC,
SPARC_INS_T,
SPARC_INS_TSUBCCTV,
SPARC_INS_TSUBCC,
SPARC_INS_UDIVCC,
SPARC_INS_UDIVX,
SPARC_INS_UDIV,
SPARC_INS_UMULCC,
SPARC_INS_UMULXHI,
SPARC_INS_UMUL,
SPARC_INS_UNIMP,
SPARC_INS_FCMPED,
SPARC_INS_FCMPEQ,
SPARC_INS_FCMPES,
SPARC_INS_WR,
SPARC_INS_XMULX,
SPARC_INS_XMULXHI,
SPARC_INS_XNORCC,
SPARC_INS_XNOR,
SPARC_INS_XORCC,
SPARC_INS_XOR,
// alias instructions
SPARC_INS_RET,
SPARC_INS_RETL,
SPARC_INS_ENDING, // <-- mark the end of the list of instructions
} sparc_insn;
/// Group of SPARC instructions
typedef enum sparc_insn_group {
SPARC_GRP_INVALID = 0, ///< = CS_GRP_INVALID
// Generic groups
// all jump instructions (conditional+direct+indirect jumps)
SPARC_GRP_JUMP, ///< = CS_GRP_JUMP
// Architecture-specific groups
SPARC_GRP_HARDQUAD = 128,
SPARC_GRP_V9,
SPARC_GRP_VIS,
SPARC_GRP_VIS2,
SPARC_GRP_VIS3,
SPARC_GRP_32BIT,
SPARC_GRP_64BIT,
SPARC_GRP_ENDING, // <-- mark the end of the list of groups
} sparc_insn_group;
#ifdef __cplusplus
}
#endif
#endif

2601
capstone/systemz.h Normal file
View File

File diff suppressed because it is too large Load Diff

359
capstone/tms320c64x.h Normal file
View File

@ -0,0 +1,359 @@
/* Capstone Disassembly Engine */
/* TMS320C64x Backend by Fotis Loukos <me@fotisl.com> 2016 */
#ifndef CAPSTONE_TMS320C64X_H
#define CAPSTONE_TMS320C64X_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include "platform.h"
#ifdef _MSC_VER
#pragma warning(disable:4201)
#endif
typedef enum tms320c64x_op_type {
TMS320C64X_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized).
TMS320C64X_OP_REG, ///< = CS_OP_REG (Register operand).
TMS320C64X_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
TMS320C64X_OP_MEM, ///< = CS_OP_MEM (Memory operand).
TMS320C64X_OP_REGPAIR = 64, ///< Register pair for double word ops
} tms320c64x_op_type;
typedef enum tms320c64x_mem_disp {
TMS320C64X_MEM_DISP_INVALID = 0,
TMS320C64X_MEM_DISP_CONSTANT,
TMS320C64X_MEM_DISP_REGISTER,
} tms320c64x_mem_disp;
typedef enum tms320c64x_mem_dir {
TMS320C64X_MEM_DIR_INVALID = 0,
TMS320C64X_MEM_DIR_FW,
TMS320C64X_MEM_DIR_BW,
} tms320c64x_mem_dir;
typedef enum tms320c64x_mem_mod {
TMS320C64X_MEM_MOD_INVALID = 0,
TMS320C64X_MEM_MOD_NO,
TMS320C64X_MEM_MOD_PRE,
TMS320C64X_MEM_MOD_POST,
} tms320c64x_mem_mod;
typedef struct tms320c64x_op_mem {
unsigned int base; ///< base register
unsigned int disp; ///< displacement/offset value
unsigned int unit; ///< unit of base and offset register
unsigned int scaled; ///< offset scaled
unsigned int disptype; ///< displacement type
unsigned int direction; ///< direction
unsigned int modify; ///< modification
} tms320c64x_op_mem;
typedef struct cs_tms320c64x_op {
tms320c64x_op_type type; ///< operand type
union {
unsigned int reg; ///< register value for REG operand or first register for REGPAIR operand
int32_t imm; ///< immediate value for IMM operand
tms320c64x_op_mem mem; ///< base/disp value for MEM operand
};
} cs_tms320c64x_op;
typedef struct cs_tms320c64x {
uint8_t op_count;
cs_tms320c64x_op operands[8]; ///< operands for this instruction.
struct {
unsigned int reg;
unsigned int zero;
} condition;
struct {
unsigned int unit;
unsigned int side;
unsigned int crosspath;
} funit;
unsigned int parallel;
} cs_tms320c64x;
typedef enum tms320c64x_reg {
TMS320C64X_REG_INVALID = 0,
TMS320C64X_REG_AMR,
TMS320C64X_REG_CSR,
TMS320C64X_REG_DIER,
TMS320C64X_REG_DNUM,
TMS320C64X_REG_ECR,
TMS320C64X_REG_GFPGFR,
TMS320C64X_REG_GPLYA,
TMS320C64X_REG_GPLYB,
TMS320C64X_REG_ICR,
TMS320C64X_REG_IER,
TMS320C64X_REG_IERR,
TMS320C64X_REG_ILC,
TMS320C64X_REG_IRP,
TMS320C64X_REG_ISR,
TMS320C64X_REG_ISTP,
TMS320C64X_REG_ITSR,
TMS320C64X_REG_NRP,
TMS320C64X_REG_NTSR,
TMS320C64X_REG_REP,
TMS320C64X_REG_RILC,
TMS320C64X_REG_SSR,
TMS320C64X_REG_TSCH,
TMS320C64X_REG_TSCL,
TMS320C64X_REG_TSR,
TMS320C64X_REG_A0,
TMS320C64X_REG_A1,
TMS320C64X_REG_A2,
TMS320C64X_REG_A3,
TMS320C64X_REG_A4,
TMS320C64X_REG_A5,
TMS320C64X_REG_A6,
TMS320C64X_REG_A7,
TMS320C64X_REG_A8,
TMS320C64X_REG_A9,
TMS320C64X_REG_A10,
TMS320C64X_REG_A11,
TMS320C64X_REG_A12,
TMS320C64X_REG_A13,
TMS320C64X_REG_A14,
TMS320C64X_REG_A15,
TMS320C64X_REG_A16,
TMS320C64X_REG_A17,
TMS320C64X_REG_A18,
TMS320C64X_REG_A19,
TMS320C64X_REG_A20,
TMS320C64X_REG_A21,
TMS320C64X_REG_A22,
TMS320C64X_REG_A23,
TMS320C64X_REG_A24,
TMS320C64X_REG_A25,
TMS320C64X_REG_A26,
TMS320C64X_REG_A27,
TMS320C64X_REG_A28,
TMS320C64X_REG_A29,
TMS320C64X_REG_A30,
TMS320C64X_REG_A31,
TMS320C64X_REG_B0,
TMS320C64X_REG_B1,
TMS320C64X_REG_B2,
TMS320C64X_REG_B3,
TMS320C64X_REG_B4,
TMS320C64X_REG_B5,
TMS320C64X_REG_B6,
TMS320C64X_REG_B7,
TMS320C64X_REG_B8,
TMS320C64X_REG_B9,
TMS320C64X_REG_B10,
TMS320C64X_REG_B11,
TMS320C64X_REG_B12,
TMS320C64X_REG_B13,
TMS320C64X_REG_B14,
TMS320C64X_REG_B15,
TMS320C64X_REG_B16,
TMS320C64X_REG_B17,
TMS320C64X_REG_B18,
TMS320C64X_REG_B19,
TMS320C64X_REG_B20,
TMS320C64X_REG_B21,
TMS320C64X_REG_B22,
TMS320C64X_REG_B23,
TMS320C64X_REG_B24,
TMS320C64X_REG_B25,
TMS320C64X_REG_B26,
TMS320C64X_REG_B27,
TMS320C64X_REG_B28,
TMS320C64X_REG_B29,
TMS320C64X_REG_B30,
TMS320C64X_REG_B31,
TMS320C64X_REG_PCE1,
TMS320C64X_REG_ENDING, // <-- mark the end of the list of registers
// Alias registers
TMS320C64X_REG_EFR = TMS320C64X_REG_ECR,
TMS320C64X_REG_IFR = TMS320C64X_REG_ISR,
} tms320c64x_reg;
typedef enum tms320c64x_insn {
TMS320C64X_INS_INVALID = 0,
TMS320C64X_INS_ABS,
TMS320C64X_INS_ABS2,
TMS320C64X_INS_ADD,
TMS320C64X_INS_ADD2,
TMS320C64X_INS_ADD4,
TMS320C64X_INS_ADDAB,
TMS320C64X_INS_ADDAD,
TMS320C64X_INS_ADDAH,
TMS320C64X_INS_ADDAW,
TMS320C64X_INS_ADDK,
TMS320C64X_INS_ADDKPC,
TMS320C64X_INS_ADDU,
TMS320C64X_INS_AND,
TMS320C64X_INS_ANDN,
TMS320C64X_INS_AVG2,
TMS320C64X_INS_AVGU4,
TMS320C64X_INS_B,
TMS320C64X_INS_BDEC,
TMS320C64X_INS_BITC4,
TMS320C64X_INS_BNOP,
TMS320C64X_INS_BPOS,
TMS320C64X_INS_CLR,
TMS320C64X_INS_CMPEQ,
TMS320C64X_INS_CMPEQ2,
TMS320C64X_INS_CMPEQ4,
TMS320C64X_INS_CMPGT,
TMS320C64X_INS_CMPGT2,
TMS320C64X_INS_CMPGTU4,
TMS320C64X_INS_CMPLT,
TMS320C64X_INS_CMPLTU,
TMS320C64X_INS_DEAL,
TMS320C64X_INS_DOTP2,
TMS320C64X_INS_DOTPN2,
TMS320C64X_INS_DOTPNRSU2,
TMS320C64X_INS_DOTPRSU2,
TMS320C64X_INS_DOTPSU4,
TMS320C64X_INS_DOTPU4,
TMS320C64X_INS_EXT,
TMS320C64X_INS_EXTU,
TMS320C64X_INS_GMPGTU,
TMS320C64X_INS_GMPY4,
TMS320C64X_INS_LDB,
TMS320C64X_INS_LDBU,
TMS320C64X_INS_LDDW,
TMS320C64X_INS_LDH,
TMS320C64X_INS_LDHU,
TMS320C64X_INS_LDNDW,
TMS320C64X_INS_LDNW,
TMS320C64X_INS_LDW,
TMS320C64X_INS_LMBD,
TMS320C64X_INS_MAX2,
TMS320C64X_INS_MAXU4,
TMS320C64X_INS_MIN2,
TMS320C64X_INS_MINU4,
TMS320C64X_INS_MPY,
TMS320C64X_INS_MPY2,
TMS320C64X_INS_MPYH,
TMS320C64X_INS_MPYHI,
TMS320C64X_INS_MPYHIR,
TMS320C64X_INS_MPYHL,
TMS320C64X_INS_MPYHLU,
TMS320C64X_INS_MPYHSLU,
TMS320C64X_INS_MPYHSU,
TMS320C64X_INS_MPYHU,
TMS320C64X_INS_MPYHULS,
TMS320C64X_INS_MPYHUS,
TMS320C64X_INS_MPYLH,
TMS320C64X_INS_MPYLHU,
TMS320C64X_INS_MPYLI,
TMS320C64X_INS_MPYLIR,
TMS320C64X_INS_MPYLSHU,
TMS320C64X_INS_MPYLUHS,
TMS320C64X_INS_MPYSU,
TMS320C64X_INS_MPYSU4,
TMS320C64X_INS_MPYU,
TMS320C64X_INS_MPYU4,
TMS320C64X_INS_MPYUS,
TMS320C64X_INS_MVC,
TMS320C64X_INS_MVD,
TMS320C64X_INS_MVK,
TMS320C64X_INS_MVKL,
TMS320C64X_INS_MVKLH,
TMS320C64X_INS_NOP,
TMS320C64X_INS_NORM,
TMS320C64X_INS_OR,
TMS320C64X_INS_PACK2,
TMS320C64X_INS_PACKH2,
TMS320C64X_INS_PACKH4,
TMS320C64X_INS_PACKHL2,
TMS320C64X_INS_PACKL4,
TMS320C64X_INS_PACKLH2,
TMS320C64X_INS_ROTL,
TMS320C64X_INS_SADD,
TMS320C64X_INS_SADD2,
TMS320C64X_INS_SADDU4,
TMS320C64X_INS_SADDUS2,
TMS320C64X_INS_SAT,
TMS320C64X_INS_SET,
TMS320C64X_INS_SHFL,
TMS320C64X_INS_SHL,
TMS320C64X_INS_SHLMB,
TMS320C64X_INS_SHR,
TMS320C64X_INS_SHR2,
TMS320C64X_INS_SHRMB,
TMS320C64X_INS_SHRU,
TMS320C64X_INS_SHRU2,
TMS320C64X_INS_SMPY,
TMS320C64X_INS_SMPY2,
TMS320C64X_INS_SMPYH,
TMS320C64X_INS_SMPYHL,
TMS320C64X_INS_SMPYLH,
TMS320C64X_INS_SPACK2,
TMS320C64X_INS_SPACKU4,
TMS320C64X_INS_SSHL,
TMS320C64X_INS_SSHVL,
TMS320C64X_INS_SSHVR,
TMS320C64X_INS_SSUB,
TMS320C64X_INS_STB,
TMS320C64X_INS_STDW,
TMS320C64X_INS_STH,
TMS320C64X_INS_STNDW,
TMS320C64X_INS_STNW,
TMS320C64X_INS_STW,
TMS320C64X_INS_SUB,
TMS320C64X_INS_SUB2,
TMS320C64X_INS_SUB4,
TMS320C64X_INS_SUBAB,
TMS320C64X_INS_SUBABS4,
TMS320C64X_INS_SUBAH,
TMS320C64X_INS_SUBAW,
TMS320C64X_INS_SUBC,
TMS320C64X_INS_SUBU,
TMS320C64X_INS_SWAP4,
TMS320C64X_INS_UNPKHU4,
TMS320C64X_INS_UNPKLU4,
TMS320C64X_INS_XOR,
TMS320C64X_INS_XPND2,
TMS320C64X_INS_XPND4,
// Aliases
TMS320C64X_INS_IDLE,
TMS320C64X_INS_MV,
TMS320C64X_INS_NEG,
TMS320C64X_INS_NOT,
TMS320C64X_INS_SWAP2,
TMS320C64X_INS_ZERO,
TMS320C64X_INS_ENDING, // <-- mark the end of the list of instructions
} tms320c64x_insn;
typedef enum tms320c64x_insn_group {
TMS320C64X_GRP_INVALID = 0, ///< = CS_GRP_INVALID
TMS320C64X_GRP_JUMP, ///< = CS_GRP_JUMP
TMS320C64X_GRP_FUNIT_D = 128,
TMS320C64X_GRP_FUNIT_L,
TMS320C64X_GRP_FUNIT_M,
TMS320C64X_GRP_FUNIT_S,
TMS320C64X_GRP_FUNIT_NO,
TMS320C64X_GRP_ENDING, // <-- mark the end of the list of groups
} tms320c64x_insn_group;
typedef enum tms320c64x_funit {
TMS320C64X_FUNIT_INVALID = 0,
TMS320C64X_FUNIT_D,
TMS320C64X_FUNIT_L,
TMS320C64X_FUNIT_M,
TMS320C64X_FUNIT_S,
TMS320C64X_FUNIT_NO
} tms320c64x_funit;
#ifdef __cplusplus
}
#endif
#endif

250
capstone/wasm.h Normal file
View File

@ -0,0 +1,250 @@
/* Capstone Disassembly Engine */
/* By Spike <spikeinhouse@gmail.com>, xwings 2019 */
#ifndef CAPSTONE_WASM_H
#define CAPSTONE_WASM_H
#ifdef __cplusplus
extern "C" {
#endif
#include "platform.h"
#ifdef _MSC_VER
#pragma warning(disable:4201)
#endif
typedef enum wasm_op_type {
WASM_OP_INVALID = 0,
WASM_OP_NONE,
WASM_OP_INT7,
WASM_OP_VARUINT32,
WASM_OP_VARUINT64,
WASM_OP_UINT32,
WASM_OP_UINT64,
WASM_OP_IMM,
WASM_OP_BRTABLE,
} wasm_op_type;
typedef struct cs_wasm_brtable {
uint32_t length;
uint64_t address;
uint32_t default_target;
} cs_wasm_brtable;
typedef struct cs_wasm_op {
wasm_op_type type;
uint32_t size;
union {
int8_t int7;
uint32_t varuint32;
uint64_t varuint64;
uint32_t uint32;
uint64_t uint64;
uint32_t immediate[2];
cs_wasm_brtable brtable;
};
} cs_wasm_op;
/// Instruction structure
typedef struct cs_wasm {
uint8_t op_count;
cs_wasm_op operands[2];
} cs_wasm;
/// WASM instruction
typedef enum wasm_insn {
WASM_INS_UNREACHABLE = 0x0,
WASM_INS_NOP = 0x1,
WASM_INS_BLOCK = 0x2,
WASM_INS_LOOP = 0x3,
WASM_INS_IF = 0x4,
WASM_INS_ELSE = 0x5,
WASM_INS_END = 0xb,
WASM_INS_BR = 0xc,
WASM_INS_BR_IF = 0xd,
WASM_INS_BR_TABLE = 0xe,
WASM_INS_RETURN = 0xf,
WASM_INS_CALL = 0x10,
WASM_INS_CALL_INDIRECT = 0x11,
WASM_INS_DROP = 0x1a,
WASM_INS_SELECT = 0x1b,
WASM_INS_GET_LOCAL = 0x20,
WASM_INS_SET_LOCAL = 0x21,
WASM_INS_TEE_LOCAL = 0x22,
WASM_INS_GET_GLOBAL = 0x23,
WASM_INS_SET_GLOBAL = 0x24,
WASM_INS_I32_LOAD = 0x28,
WASM_INS_I64_LOAD = 0x29,
WASM_INS_F32_LOAD = 0x2a,
WASM_INS_F64_LOAD = 0x2b,
WASM_INS_I32_LOAD8_S = 0x2c,
WASM_INS_I32_LOAD8_U = 0x2d,
WASM_INS_I32_LOAD16_S = 0x2e,
WASM_INS_I32_LOAD16_U = 0x2f,
WASM_INS_I64_LOAD8_S = 0x30,
WASM_INS_I64_LOAD8_U = 0x31,
WASM_INS_I64_LOAD16_S = 0x32,
WASM_INS_I64_LOAD16_U = 0x33,
WASM_INS_I64_LOAD32_S = 0x34,
WASM_INS_I64_LOAD32_U = 0x35,
WASM_INS_I32_STORE = 0x36,
WASM_INS_I64_STORE = 0x37,
WASM_INS_F32_STORE = 0x38,
WASM_INS_F64_STORE = 0x39,
WASM_INS_I32_STORE8 = 0x3a,
WASM_INS_I32_STORE16 = 0x3b,
WASM_INS_I64_STORE8 = 0x3c,
WASM_INS_I64_STORE16 = 0x3d,
WASM_INS_I64_STORE32 = 0x3e,
WASM_INS_CURRENT_MEMORY = 0x3f,
WASM_INS_GROW_MEMORY = 0x40,
WASM_INS_I32_CONST = 0x41,
WASM_INS_I64_CONST = 0x42,
WASM_INS_F32_CONST = 0x43,
WASM_INS_F64_CONST = 0x44,
WASM_INS_I32_EQZ = 0x45,
WASM_INS_I32_EQ = 0x46,
WASM_INS_I32_NE = 0x47,
WASM_INS_I32_LT_S = 0x48,
WASM_INS_I32_LT_U = 0x49,
WASM_INS_I32_GT_S = 0x4a,
WASM_INS_I32_GT_U = 0x4b,
WASM_INS_I32_LE_S = 0x4c,
WASM_INS_I32_LE_U = 0x4d,
WASM_INS_I32_GE_S = 0x4e,
WASM_INS_I32_GE_U = 0x4f,
WASM_INS_I64_EQZ = 0x50,
WASM_INS_I64_EQ = 0x51,
WASM_INS_I64_NE = 0x52,
WASM_INS_I64_LT_S = 0x53,
WASM_INS_I64_LT_U = 0x54,
WASN_INS_I64_GT_S = 0x55,
WASM_INS_I64_GT_U = 0x56,
WASM_INS_I64_LE_S = 0x57,
WASM_INS_I64_LE_U = 0x58,
WASM_INS_I64_GE_S = 0x59,
WASM_INS_I64_GE_U = 0x5a,
WASM_INS_F32_EQ = 0x5b,
WASM_INS_F32_NE = 0x5c,
WASM_INS_F32_LT = 0x5d,
WASM_INS_F32_GT = 0x5e,
WASM_INS_F32_LE = 0x5f,
WASM_INS_F32_GE = 0x60,
WASM_INS_F64_EQ = 0x61,
WASM_INS_F64_NE = 0x62,
WASM_INS_F64_LT = 0x63,
WASM_INS_F64_GT = 0x64,
WASM_INS_F64_LE = 0x65,
WASM_INS_F64_GE = 0x66,
WASM_INS_I32_CLZ = 0x67,
WASM_INS_I32_CTZ = 0x68,
WASM_INS_I32_POPCNT = 0x69,
WASM_INS_I32_ADD = 0x6a,
WASM_INS_I32_SUB = 0x6b,
WASM_INS_I32_MUL = 0x6c,
WASM_INS_I32_DIV_S = 0x6d,
WASM_INS_I32_DIV_U = 0x6e,
WASM_INS_I32_REM_S = 0x6f,
WASM_INS_I32_REM_U = 0x70,
WASM_INS_I32_AND = 0x71,
WASM_INS_I32_OR = 0x72,
WASM_INS_I32_XOR = 0x73,
WASM_INS_I32_SHL = 0x74,
WASM_INS_I32_SHR_S = 0x75,
WASM_INS_I32_SHR_U = 0x76,
WASM_INS_I32_ROTL = 0x77,
WASM_INS_I32_ROTR = 0x78,
WASM_INS_I64_CLZ = 0x79,
WASM_INS_I64_CTZ = 0x7a,
WASM_INS_I64_POPCNT = 0x7b,
WASM_INS_I64_ADD = 0x7c,
WASM_INS_I64_SUB = 0x7d,
WASM_INS_I64_MUL = 0x7e,
WASM_INS_I64_DIV_S = 0x7f,
WASM_INS_I64_DIV_U = 0x80,
WASM_INS_I64_REM_S = 0x81,
WASM_INS_I64_REM_U = 0x82,
WASM_INS_I64_AND = 0x83,
WASM_INS_I64_OR = 0x84,
WASM_INS_I64_XOR = 0x85,
WASM_INS_I64_SHL = 0x86,
WASM_INS_I64_SHR_S = 0x87,
WASM_INS_I64_SHR_U = 0x88,
WASM_INS_I64_ROTL = 0x89,
WASM_INS_I64_ROTR = 0x8a,
WASM_INS_F32_ABS = 0x8b,
WASM_INS_F32_NEG = 0x8c,
WASM_INS_F32_CEIL = 0x8d,
WASM_INS_F32_FLOOR = 0x8e,
WASM_INS_F32_TRUNC = 0x8f,
WASM_INS_F32_NEAREST = 0x90,
WASM_INS_F32_SQRT = 0x91,
WASM_INS_F32_ADD = 0x92,
WASM_INS_F32_SUB = 0x93,
WASM_INS_F32_MUL = 0x94,
WASM_INS_F32_DIV = 0x95,
WASM_INS_F32_MIN = 0x96,
WASM_INS_F32_MAX = 0x97,
WASM_INS_F32_COPYSIGN = 0x98,
WASM_INS_F64_ABS = 0x99,
WASM_INS_F64_NEG = 0x9a,
WASM_INS_F64_CEIL = 0x9b,
WASM_INS_F64_FLOOR = 0x9c,
WASM_INS_F64_TRUNC = 0x9d,
WASM_INS_F64_NEAREST = 0x9e,
WASM_INS_F64_SQRT = 0x9f,
WASM_INS_F64_ADD = 0xa0,
WASM_INS_F64_SUB = 0xa1,
WASM_INS_F64_MUL = 0xa2,
WASM_INS_F64_DIV = 0xa3,
WASM_INS_F64_MIN = 0xa4,
WASM_INS_F64_MAX = 0xa5,
WASM_INS_F64_COPYSIGN = 0xa6,
WASM_INS_I32_WARP_I64 = 0xa7,
WASP_INS_I32_TRUNC_S_F32 = 0xa8,
WASM_INS_I32_TRUNC_U_F32 = 0xa9,
WASM_INS_I32_TRUNC_S_F64 = 0xaa,
WASM_INS_I32_TRUNC_U_F64 = 0xab,
WASM_INS_I64_EXTEND_S_I32 = 0xac,
WASM_INS_I64_EXTEND_U_I32 = 0xad,
WASM_INS_I64_TRUNC_S_F32 = 0xae,
WASM_INS_I64_TRUNC_U_F32 = 0xaf,
WASM_INS_I64_TRUNC_S_F64 = 0xb0,
WASM_INS_I64_TRUNC_U_F64 = 0xb1,
WASM_INS_F32_CONVERT_S_I32 = 0xb2,
WASM_INS_F32_CONVERT_U_I32 = 0xb3,
WASM_INS_F32_CONVERT_S_I64 = 0xb4,
WASM_INS_F32_CONVERT_U_I64 = 0xb5,
WASM_INS_F32_DEMOTE_F64 = 0xb6,
WASM_INS_F64_CONVERT_S_I32 = 0xb7,
WASM_INS_F64_CONVERT_U_I32 = 0xb8,
WASM_INS_F64_CONVERT_S_I64 = 0xb9,
WASM_INS_F64_CONVERT_U_I64 = 0xba,
WASM_INS_F64_PROMOTE_F32 = 0xbb,
WASM_INS_I32_REINTERPRET_F32 = 0xbc,
WASM_INS_I64_REINTERPRET_F64 = 0xbd,
WASM_INS_F32_REINTERPRET_I32 = 0xbe,
WASM_INS_F64_REINTERPRET_I64 = 0xbf,
WASM_INS_INVALID = 512,
WASM_INS_ENDING,
} wasm_insn;
/// Group of WASM instructions
typedef enum wasm_insn_group {
WASM_GRP_INVALID = 0, ///< = CS_GRP_INVALID
WASM_GRP_NUMBERIC = 8,
WASM_GRP_PARAMETRIC,
WASM_GRP_VARIABLE,
WASM_GRP_MEMORY,
WASM_GRP_CONTROL,
WASM_GRP_ENDING, ///< <-- mark the end of the list of groups
} wasm_insn_group;
#ifdef __cplusplus
}
#endif
#endif

1986
capstone/x86.h Normal file
View File

File diff suppressed because it is too large Load Diff

235
capstone/xcore.h Normal file
View File

@ -0,0 +1,235 @@
#ifndef CAPSTONE_XCORE_H
#define CAPSTONE_XCORE_H
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2014-2015 */
#ifdef __cplusplus
extern "C" {
#endif
#include "platform.h"
#ifdef _MSC_VER
#pragma warning(disable:4201)
#endif
/// Operand type for instruction's operands
typedef enum xcore_op_type {
XCORE_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized).
XCORE_OP_REG, ///< = CS_OP_REG (Register operand).
XCORE_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
XCORE_OP_MEM, ///< = CS_OP_MEM (Memory operand).
} xcore_op_type;
/// XCore registers
typedef enum xcore_reg {
XCORE_REG_INVALID = 0,
XCORE_REG_CP,
XCORE_REG_DP,
XCORE_REG_LR,
XCORE_REG_SP,
XCORE_REG_R0,
XCORE_REG_R1,
XCORE_REG_R2,
XCORE_REG_R3,
XCORE_REG_R4,
XCORE_REG_R5,
XCORE_REG_R6,
XCORE_REG_R7,
XCORE_REG_R8,
XCORE_REG_R9,
XCORE_REG_R10,
XCORE_REG_R11,
// pseudo registers
XCORE_REG_PC, ///< pc
// internal thread registers
// see The-XMOS-XS1-Architecture(X7879A).pdf
XCORE_REG_SCP, ///< save pc
XCORE_REG_SSR, //< save status
XCORE_REG_ET, //< exception type
XCORE_REG_ED, //< exception data
XCORE_REG_SED, //< save exception data
XCORE_REG_KEP, //< kernel entry pointer
XCORE_REG_KSP, //< kernel stack pointer
XCORE_REG_ID, //< thread ID
XCORE_REG_ENDING, // <-- mark the end of the list of registers
} xcore_reg;
/// Instruction's operand referring to memory
/// This is associated with XCORE_OP_MEM operand type above
typedef struct xcore_op_mem {
uint8_t base; ///< base register, can be safely interpreted as
///< a value of type `xcore_reg`, but it is only
///< one byte wide
uint8_t index; ///< index register, same conditions apply here
int32_t disp; ///< displacement/offset value
int direct; ///< +1: forward, -1: backward
} xcore_op_mem;
/// Instruction operand
typedef struct cs_xcore_op {
xcore_op_type type; ///< operand type
union {
xcore_reg reg; ///< register value for REG operand
int32_t imm; ///< immediate value for IMM operand
xcore_op_mem mem; ///< base/disp value for MEM operand
};
} cs_xcore_op;
/// Instruction structure
typedef struct cs_xcore {
/// Number of operands of this instruction,
/// or 0 when instruction has no operand.
uint8_t op_count;
cs_xcore_op operands[8]; ///< operands for this instruction.
} cs_xcore;
/// XCore instruction
typedef enum xcore_insn {
XCORE_INS_INVALID = 0,
XCORE_INS_ADD,
XCORE_INS_ANDNOT,
XCORE_INS_AND,
XCORE_INS_ASHR,
XCORE_INS_BAU,
XCORE_INS_BITREV,
XCORE_INS_BLA,
XCORE_INS_BLAT,
XCORE_INS_BL,
XCORE_INS_BF,
XCORE_INS_BT,
XCORE_INS_BU,
XCORE_INS_BRU,
XCORE_INS_BYTEREV,
XCORE_INS_CHKCT,
XCORE_INS_CLRE,
XCORE_INS_CLRPT,
XCORE_INS_CLRSR,
XCORE_INS_CLZ,
XCORE_INS_CRC8,
XCORE_INS_CRC32,
XCORE_INS_DCALL,
XCORE_INS_DENTSP,
XCORE_INS_DGETREG,
XCORE_INS_DIVS,
XCORE_INS_DIVU,
XCORE_INS_DRESTSP,
XCORE_INS_DRET,
XCORE_INS_ECALLF,
XCORE_INS_ECALLT,
XCORE_INS_EDU,
XCORE_INS_EEF,
XCORE_INS_EET,
XCORE_INS_EEU,
XCORE_INS_ENDIN,
XCORE_INS_ENTSP,
XCORE_INS_EQ,
XCORE_INS_EXTDP,
XCORE_INS_EXTSP,
XCORE_INS_FREER,
XCORE_INS_FREET,
XCORE_INS_GETD,
XCORE_INS_GET,
XCORE_INS_GETN,
XCORE_INS_GETR,
XCORE_INS_GETSR,
XCORE_INS_GETST,
XCORE_INS_GETTS,
XCORE_INS_INCT,
XCORE_INS_INIT,
XCORE_INS_INPW,
XCORE_INS_INSHR,
XCORE_INS_INT,
XCORE_INS_IN,
XCORE_INS_KCALL,
XCORE_INS_KENTSP,
XCORE_INS_KRESTSP,
XCORE_INS_KRET,
XCORE_INS_LADD,
XCORE_INS_LD16S,
XCORE_INS_LD8U,
XCORE_INS_LDA16,
XCORE_INS_LDAP,
XCORE_INS_LDAW,
XCORE_INS_LDC,
XCORE_INS_LDW,
XCORE_INS_LDIVU,
XCORE_INS_LMUL,
XCORE_INS_LSS,
XCORE_INS_LSUB,
XCORE_INS_LSU,
XCORE_INS_MACCS,
XCORE_INS_MACCU,
XCORE_INS_MJOIN,
XCORE_INS_MKMSK,
XCORE_INS_MSYNC,
XCORE_INS_MUL,
XCORE_INS_NEG,
XCORE_INS_NOT,
XCORE_INS_OR,
XCORE_INS_OUTCT,
XCORE_INS_OUTPW,
XCORE_INS_OUTSHR,
XCORE_INS_OUTT,
XCORE_INS_OUT,
XCORE_INS_PEEK,
XCORE_INS_REMS,
XCORE_INS_REMU,
XCORE_INS_RETSP,
XCORE_INS_SETCLK,
XCORE_INS_SET,
XCORE_INS_SETC,
XCORE_INS_SETD,
XCORE_INS_SETEV,
XCORE_INS_SETN,
XCORE_INS_SETPSC,
XCORE_INS_SETPT,
XCORE_INS_SETRDY,
XCORE_INS_SETSR,
XCORE_INS_SETTW,
XCORE_INS_SETV,
XCORE_INS_SEXT,
XCORE_INS_SHL,
XCORE_INS_SHR,
XCORE_INS_SSYNC,
XCORE_INS_ST16,
XCORE_INS_ST8,
XCORE_INS_STW,
XCORE_INS_SUB,
XCORE_INS_SYNCR,
XCORE_INS_TESTCT,
XCORE_INS_TESTLCL,
XCORE_INS_TESTWCT,
XCORE_INS_TSETMR,
XCORE_INS_START,
XCORE_INS_WAITEF,
XCORE_INS_WAITET,
XCORE_INS_WAITEU,
XCORE_INS_XOR,
XCORE_INS_ZEXT,
XCORE_INS_ENDING, // <-- mark the end of the list of instructions
} xcore_insn;
/// Group of XCore instructions
typedef enum xcore_insn_group {
XCORE_GRP_INVALID = 0, ///< = CS_GRP_INVALID
// Generic groups
// all jump instructions (conditional+direct+indirect jumps)
XCORE_GRP_JUMP, ///< = CS_GRP_JUMP
XCORE_GRP_ENDING, // <-- mark the end of the list of groups
} xcore_insn_group;
#ifdef __cplusplus
}
#endif
#endif

16
img/README.md Normal file
View File

@ -0,0 +1,16 @@
## WingHexDisasm
&emsp;&emsp;`WingHexDisasm`是一个羽云十六进制编辑器插件，它具有对给出字节进行反汇编的能力，基于`capstone`反汇编引擎框架。
### 协议
&emsp;&emsp;本插件仓库将采用`AGPL-3.0`协议，不得将该插件代码用于改协议之外的用途。
## 如何使用
&emsp;&emsp;将插件注册到软件的插件系统当中之后，只需在文档中用鼠标框选字节，执行反汇编命令即可。
## 有关仓库
* Gitea : https://code.gitlink.org.cn/wingsummer/WingHexPy
* Gitee : https://gitee.com/wing-cloud/wing-hex-py

BIN
img/analyse.png Normal file
View File

Binary file not shown.
Side by Side

After

Width:  |  Height:  |  Size: 6.4 KiB

BIN
img/author.jpg Executable file
View File

Binary file not shown.
Side by Side

After

Width:  |  Height:  |  Size: 49 KiB

BIN
img/author.png Executable file
View File

Binary file not shown.
Side by Side

After

Width:  |  Height:  |  Size: 11 KiB

BIN
img/clear.png Normal file
View File

Binary file not shown.
Side by Side

After

Width:  |  Height:  |  Size: 7.4 KiB

BIN
img/copy.png Executable file
View File

Binary file not shown.
Side by Side

After

Width:  |  Height:  |  Size: 3.4 KiB

BIN
img/icon.png Normal file
View File

Binary file not shown.
Side by Side

After

Width:  |  Height:  |  Size: 3.6 KiB

BIN
img/sp.png Normal file
View File

Binary file not shown.
Side by Side

After

Width:  |  Height:  |  Size: 776 KiB

BIN
img/sponsor.png Executable file
View File

Binary file not shown.
Side by Side

After

Width:  |  Height:  |  Size: 4.2 KiB

13
resource.qrc Normal file
View File

@ -0,0 +1,13 @@
<RCC>
<qresource prefix="/">
<file>img/icon.png</file>
<file>img/analyse.png</file>
<file>img/author.jpg</file>
<file>img/author.png</file>
<file>img/clear.png</file>
<file>img/copy.png</file>
<file>img/sp.png</file>
<file>img/sponsor.png</file>
<file>img/README.md</file>
</qresource>
</RCC>

10
sponsordialog.cpp Normal file
View File

@ -0,0 +1,10 @@
#include "sponsordialog.h"
#include "ui_sponsordialog.h"
SponsorDialog::SponsorDialog(QWidget *parent)
: QDialog(parent), ui(new Ui::SponsorDialog) {
ui->setupUi(this);
ui->retranslateUi(this);
}
SponsorDialog::~SponsorDialog() { delete ui; }

21
sponsordialog.h Normal file
View File

@ -0,0 +1,21 @@
#ifndef SPONSORDIALOG_H
#define SPONSORDIALOG_H
#include <QDialog>
namespace Ui {
class SponsorDialog;
}
class SponsorDialog : public QDialog {
Q_OBJECT
public:
explicit SponsorDialog(QWidget *parent = nullptr);
~SponsorDialog();
private:
Ui::SponsorDialog *ui;
};
#endif // SPONSORDIALOG_H

56
sponsordialog.ui Normal file
View File

@ -0,0 +1,56 @@
<?xml version="1.0" encoding="UTF-8"?>
<ui version="4.0">
<class>SponsorDialog</class>
<widget class="QDialog" name="SponsorDialog">
<property name="geometry">
<rect>
<x>0</x>
<y>0</y>
<width>500</width>
<height>400</height>
</rect>
</property>
<property name="windowTitle">
<string>Dialog</string>
</property>
<widget class="QLabel" name="label">
<property name="geometry">
<rect>
<x>10</x>
<y>10</y>
<width>481</width>
<height>22</height>
</rect>
</property>
<property name="text">
<string>Thanks for sponsor!</string>
</property>
<property name="alignment">
<set>Qt::AlignCenter</set>
</property>
</widget>
<widget class="QLabel" name="label_2">
<property name="geometry">
<rect>
<x>10</x>
<y>40</y>
<width>481</width>
<height>351</height>
</rect>
</property>
<property name="text">
<string/>
</property>
<property name="pixmap">
<pixmap resource="resource.qrc">:/img/sp.png</pixmap>
</property>
<property name="scaledContents">
<bool>true</bool>
</property>
</widget>
</widget>
<resources>
<include location="resource.qrc"/>
</resources>
<connections/>
</ui>

267
winghexdisasm.cpp Normal file
View File

@ -0,0 +1,267 @@
#include "winghexdisasm.h"
#include "authordialog.h"
#include "sponsordialog.h"
#include <QApplication>
#include <QHBoxLayout>
#include <QLabel>
#include <QMessageBox>
#include <QMetaEnum>
#include <QSettings>
#include <QVBoxLayout>
Q_DECLARE_METATYPE(cs_arch)
Q_DECLARE_METATYPE(cs_mode)
#define ICONRES(name) QIcon(":/img/" name ".png")
WingHexDisasm::WingHexDisasm(QObject *parent) { Q_UNUSED(parent); }
bool WingHexDisasm::init(QList<WingPluginInfo> loadedplugin) {
Q_UNUSED(loadedplugin);
if (SDKVERSION < 8) {
QMessageBox::critical(nullptr, "Error",
"UnSupported Plugin System Version!",
QMessageBox::Ok);
return false;
}
auto translator = new QTranslator(this);
auto s = GETPLUGINQM("WingHexDisasm.qm");
if (!translator->load(s) || !QApplication::installTranslator(translator)) {
QMessageBox::critical(nullptr, "Error", "Error Loading Translation File!",
QMessageBox::Ok);
return false;
}
w = new QWidget;
auto vlayout = new QVBoxLayout(w);
auto hlayout = new QHBoxLayout(w);
hlayout->addWidget(new QLabel(tr("Arch :"), w));
hlayout->addSpacing(10);
// 默认 x86_64 64 位指令
arch = new QComboBox(w);
QStringList archs({"ARM", "ARM64", "MIPS", "X86_64", "PPC", "SPARC", "SYSZ",
"XCORE", "M68K", "TMS320C64X", "M680X", "EVM", "MOS65XX",
"WASM", "BPF", "RISCV"});
arch->addItems(archs);
arch->setCurrentIndex(3);
void (QComboBox::*indexChanged)(int index) = &QComboBox::currentIndexChanged;
connect(arch, indexChanged, [=](int index) {
switch (index) {
case 0:
carch = cs_arch::CS_ARCH_ARM;
break;
case 1:
carch = cs_arch::CS_ARCH_ARM64;
break;
case 2:
carch = cs_arch::CS_ARCH_MIPS;
break;
case 3:
carch = cs_arch::CS_ARCH_X86;
break;
case 4:
carch = cs_arch::CS_ARCH_PPC;
break;
case 5:
carch = cs_arch::CS_ARCH_SPARC;
break;
case 6:
carch = cs_arch::CS_ARCH_SYSZ;
break;
case 7:
carch = cs_arch::CS_ARCH_XCORE;
break;
case 8:
carch = cs_arch::CS_ARCH_M68K;
break;
case 9:
carch = cs_arch::CS_ARCH_TMS320C64X;
break;
case 10:
carch = cs_arch::CS_ARCH_M680X;
break;
case 11:
carch = cs_arch::CS_ARCH_EVM;
break;
case 12:
carch = cs_arch::CS_ARCH_MOS65XX;
break;
case 13:
carch = cs_arch::CS_ARCH_WASM;
break;
case 14:
carch = cs_arch::CS_ARCH_BPF;
break;
case 15:
carch = cs_arch::CS_ARCH_RISCV;
break;
}
});
hlayout->addWidget(arch);
hlayout->addSpacing(30);
hlayout->addWidget(new QLabel(tr("Mode :"), w));
hlayout->addSpacing(10);
mode = new QComboBox(w);
QStringList modes({"x16", "x32", "x64", "THUMB", "MIPS32", "MIPS64"});
mode->addItems(modes);
mode->setCurrentIndex(2);
connect(mode, indexChanged, [=](int index) {
switch (index) {
case 0:
cmode = cs_mode::CS_MODE_16;
break;
case 1:
cmode = cs_mode::CS_MODE_32;
break;
case 2:
cmode = cs_mode::CS_MODE_64;
break;
case 3:
cmode = cs_mode::CS_MODE_THUMB;
break;
case 4:
cmode = cs_mode::CS_MODE_MIPS32;
break;
case 5:
cmode = cs_mode::CS_MODE_MIPS64;
break;
}
});
hlayout->addWidget(mode);
hlayout->addStretch();
vlayout->addSpacing(10);
txtAsm = new QTextBrowser(w);
vlayout->addItem(hlayout);
vlayout->addWidget(txtAsm);
PluginDockWidgetInit(dw, w, tr("DisasmWindow"), "DisasmWindow");
PluginMenuInitBegin(menu, tr("WingHexDisasm")) {
menu->setIcon(ICONRES("icon"));
PluginMenuAddItemIconAction(menu, tr("Disasm"), ICONRES("analyse"),
WingHexDisasm::on_disasm);
PluginMenuAddItemIconAction(menu, tr("Clear"), ICONRES("clear"),
WingHexDisasm::on_clear);
menu->addSeparator();
PluginMenuAddItemIconLamba(menu, tr("Author"), ICONRES("author"), [=] {
AuthorDialog d;
d.exec();
});
PluginMenuAddItemIconLamba(menu, tr("Sponsor"), ICONRES("sponsor"), [=] {
SponsorDialog d;
d.exec();
});
}
PluginMenuInitEnd();
QMenu *tmenu;
PluginMenuInitBegin(tmenu, "") {
PluginMenuAddItemIconAction(tmenu, tr("Disasm"), ICONRES("analyse"),
WingHexDisasm::on_disasm);
PluginMenuAddItemIconAction(tmenu, tr("Clear"), ICONRES("clear"),
WingHexDisasm::on_clear);
}
PluginMenuInitEnd();
PluginToolButtonInit(tbtn, tmenu, ICONRES("icon"));
loadSetting();
return true;
}
WingHexDisasm::~WingHexDisasm() {}
void WingHexDisasm::unload() { saveSetting(); }
int WingHexDisasm::sdkVersion() { return SDKVERSION; }
QMenu *WingHexDisasm::registerMenu() { return menu; }
QToolButton *WingHexDisasm::registerToolButton() { return tbtn; }
void WingHexDisasm::registerDockWidget(
QMap<QDockWidget *, Qt::DockWidgetArea> &rdw) {
rdw.insert(dw, Qt::DockWidgetArea::BottomDockWidgetArea);
}
QString WingHexDisasm::pluginName() { return tr("WingHexDisasm"); }
QString WingHexDisasm::pluginAuthor() { return WINGSUMMER; }
uint WingHexDisasm::pluginVersion() { return 1; }
QString WingHexDisasm::signature() { return WINGSUMMER; }
QString WingHexDisasm::pluginComment() { return tr(""); }
void WingHexDisasm::plugin2MessagePipe(WingPluginMessage type,
QList<QVariant> msg) {
Q_UNUSED(type);
Q_UNUSED(msg);
}
void WingHexDisasm::disasm(QByteArray code) {
csh handle;
cs_err err = cs_open(carch, cmode, &handle);
if (err != CS_ERR_OK) {
txtAsm->setText(tr("Error: Failed capstone initialization"));
} else if (code.length()) {
size_t count;
cs_insn *insn;
cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON);
auto *t = code.data();
count = cs_disasm(handle, reinterpret_cast<uint8_t *>(t),
size_t(code.size()), 0, 0, &insn);
if (count > 0) {
txtAsm->clear();
size_t j;
QStringList asms;
for (j = 0; j < count; j++) {
asms << (QString("%1 %2;").arg(insn[j].mnemonic).arg(insn[j].op_str));
}
txtAsm->setText(asms.join('\n'));
cs_free(insn, count);
} else {
txtAsm->setText(tr("Error: Failed to disassemble given op codes"));
}
cs_close(&handle);
}
}
void WingHexDisasm::on_disasm() {
if (reader.selectLength()) {
this->disasm(reader.selectedBytes());
} else {
this->toast(ICONRES("icon"), tr("No Selection Bytes"));
}
}
void WingHexDisasm::on_clear() { txtAsm->clear(); }
void WingHexDisasm::saveSetting() {
QSettings settings("wingsummer", "WingHexDisasm");
settings.setValue("arch", carch);
settings.setValue("mode", cmode);
}
void WingHexDisasm::loadSetting() {
QSettings settings("wingsummer", "WingHexDisasm");
carch = settings.value("arch", cs_arch::CS_ARCH_X86).value<cs_arch>();
cmode = settings.value("mode", cs_mode::CS_MODE_64).value<cs_mode>();
}
#if QT_VERSION < 0x050000
Q_EXPORT_PLUGIN2(WingHexDisasm, GenericPlugin)
#endif // QT_VERSION < 0x050000

53
winghexdisasm.h Normal file
View File

@ -0,0 +1,53 @@
#ifndef GENERICPLUGIN_H
#define GENERICPLUGIN_H
#include "../WingHexExplorer/wing-hex-explorer.sourcecode/WingHexExplorer/plugin/iwingplugin.h"
#include "capstone/capstone.h"
#include <QComboBox>
#include <QTextBrowser>
class WingHexDisasm : public IWingPlugin {
Q_OBJECT
#if QT_VERSION >= 0x050000
Q_PLUGIN_METADATA(IID IWINGPLUGIN_INTERFACE_IID FILE "WingHexDisasm.json")
#endif // QT_VERSION >= 0x050000
Q_INTERFACES(IWingPlugin)
public:
WingHexDisasm(QObject *parent = nullptr);
bool init(QList<WingPluginInfo> loadedplugin) override;
~WingHexDisasm() override;
void unload() override;
int sdkVersion() override;
QMenu *registerMenu() override;
QToolButton *registerToolButton() override;
void
registerDockWidget(QMap<QDockWidget *, Qt::DockWidgetArea> &rdw) override;
QString pluginName() override;
QString pluginAuthor() override;
uint pluginVersion() override;
QString signature() override;
QString pluginComment() override;
void plugin2MessagePipe(WingPluginMessage type, QList<QVariant> msg) override;
private:
void disasm(QByteArray code);
void on_disasm();
void on_clear();
void saveSetting();
void loadSetting();
private:
QMenu *menu;
QToolButton *tbtn;
QWidget *w;
QDockWidget *dw;
QTextBrowser *txtAsm;
QComboBox *arch, *mode;
cs_arch carch = cs_arch::CS_ARCH_X86;
cs_mode cmode = cs_mode::CS_MODE_64;
};
#endif // GENERICPLUGIN_H