add sync_fifo.v

README.md

@@ -1,3 +1,6 @@
 # IC_FPGA_projects
 This repository is used to introduce to some projects or modules bases on the mainly lanuage--verilog.
-# 1 
+# 1 
+
+# 2 Useful references
+[1] https://github.com/sin-x/FPGA/tree/master

common/sync_fifo.v

@@ -3,4 +3,135 @@
 //--Date    : 10-30
 //--Module  : sync_fifo
 //--Function: the sync clk fifo logic
-//====================================
+//====================================
+
+module sync_fifo #(
+//==========================< 参数 >=========================
+    parameter DATA_WIDTH = 8,
+    parameter FIFO_DEPTH = 16
+) (
+//==========================< 端口 >=========================
+    input wire clk,
+    input wire rst_n,
+    input wire wr_en,
+    input wire [DATA_WIDTH -1:0] write_data,
+    output wire wr_full,
+
+    input wire rd_en,
+    input wire [DATA_WIDTH -1:0] read_data,
+    output wire rd_empty
+
+);
+//==========================< 参数 >=========================
+localparam DATA_DEPTH = $clog2(DATA_WIDTH);
+
+//==========================< 信号 >=========================
+reg [DATA_WIDTH -1:0] fifo_mem[FIFO_DEPTH];
+reg [DATA_DEPTH -1:0] fifo_cnt;
+reg [DATA_DEPTH -1:0] wr_ptr;
+reg [DATA_DEPTH -1:0] rd_ptr;
+
+
+//=========================================================
+//-- write_data
+//=========================================================
+always @(posedge clk or negedge rst_n) begin
+    if (!rst_n) begin
+        fifo_mem[wr_ptr] <= 0;
+    end else begin
+        if (wr_en && !wr_full) begin
+            fifo_mem[wr_ptr] <= write_data;
+        end else begin
+            fifo_mem[wr_ptr] <= fifo_mem[wr_ptr] ;
+        end
+    end
+end
+
+//=========================================================
+//-- wr_ptr
+//=========================================================
+always @(posedge clk or negedge rst_n) begin
+    if(!rst_n) begin
+        wr_ptr <= 0;
+    end else begin
+        if(!wr_full && wr_en) begin
+            wr_ptr <= wr_ptr + 1'b1;
+        end else begin
+            wr_ptr <= wr_ptr;
+        end
+    end
+end
+
+//=========================================================
+//-- write_data
+//=========================================================
+
+always @(posedge clk or negedge rst_n) begin
+    if(!rst_n) begin
+        fifo_mem[wr_ptr] <= 'b0;
+    end else begin
+        if(!wr_full && wr_en) begin
+            fifo_mem[wr_ptr] <= write_data;
+        end else begin
+            fifo_mem[wr_ptr] <= fifo_mem[wr_ptr];
+        end
+    end
+end
+
+//=========================================================
+//-- rd_ptr
+//=========================================================
+always @(posedge clk or negedge rst_n) begin
+    if(!rst_n) begin
+        rd_ptr <= 'b0;
+    end else begin
+        if (!rd_empty && rd_en) begin
+            rd_ptr <= rd_ptr + 1'b1;
+        end else begin
+            rd_ptr <= rd_ptr;
+        end
+    end
+end
+    
+//=========================================================
+//-- read_data
+//=========================================================
+reg [DATA_WIDTH -1:0] read_data_tmp;
+always @(posedge clk or negedge rst_n) begin
+    if(!rst_n) begin
+        read_data_tmp <= 'b0;
+    end else begin
+        if (!rd_empty && rd_en) begin
+            read_data_tmp <= fifo_mem[rd_ptr];
+        end else begin
+            read_data_tmp <= read_data_tmp;
+        end
+    end
+end
+
+assign read_data = read_data_tmp;
+
+//=========================================================
+//-- fifo_cnt
+//=========================================================
+always @(posedge clk or negedge rst_n) begin
+    if (!rst_n) begin
+        fifo_cnt <= 'b0;
+    end else begin
+        //--cases:
+        if (wr_en && rd_en) begin
+            fifo_cnt <= fifo_cnt;
+        end else if (wr_en && !rd_en) begin
+            fifo_cnt <= fifo_cnt + 1'b1;
+        end else if (!wr_en && rd_en) begin
+            fifo_cnt <= fifo_cnt - 1'b1;
+        end else begin
+            fifo_cnt <= fifo_cnt;
+        end
+    end
+end
+
+assign wr_full = fifo_cnt == FIFO_DEPTH;
+assign rd_empty= fifo_cnt == 0;
+
+endmodule