sync_multi_bits: finish handshake

common/sync_multi_bits.v

@@ -216,7 +216,164 @@ endmodule
 //==========================================================
 //--Author  : colonel
 //--Date    : 11-01
-//--Module  : sync_multi_bits_slow_2_fast
-//--Function: sync multi bits from slow_clk to fast_clk using MUX
-//--            Only considering the yaWenTai;
-//==========================================================
+//--Module  : sync_multi_bits_using_handShake
+//--Function: sync multi bits of newcoder  
+//==========================================================
+module data_driver (
+//==========================< 端口 >=========================
+    input clk_a,
+    input rst_n,
+    input data_ack,
+    output [4 -1:0] data,
+    output data_req
+);
+//==========================< 信号 >=========================
+reg data_ack_sync1;
+reg data_ack_sync2;
+    
+//=========================================================
+//-- data_ack_sync1/2:sync data_ack to clk_a
+//=========================================================
+always @(posedge clk_a or negedge rst_n) begin
+    if (!rst_n) begin
+        data_ack_sync1 <= 1'b0;
+        data_ack_sync2 <= 1'b0;
+    end else begin
+        data_ack_sync1 <= data_ack;
+        data_ack_sync2 <= data_ack_sync1;
+    end
+end
+
+wire data_ack_sync1_pos = data_ack_sync1 && !data_ack_sync2;    
+
+//==========================< 信号 >=========================
+reg [4 -1:0] data_r;
+
+//=========================================================
+//-- data: can change when ack is ok
+//=========================================================
+always @(posedge clk_a or negedge rst_n) begin
+    if (!rst_n) begin
+        data_r <= 0;
+    end else begin
+        if (data_ack_sync1_pos) begin
+            data_r <= data_r + 1;
+        end else begin
+            data_r <= data_r;
+        end
+    end
+end
+
+assign data = data_r;
+
+//==========================< 信号 >=========================
+reg [3 -1:0] cnt;
+
+//=========================================================
+//-- cnt: cnt is 0 when ack is ok,and keep when data_req 
+//=========================================================
+always @(posedge clk_a or negedge rst_n) begin
+    if (!rst_n) begin
+        cnt <= 0;
+    end else begin
+        if (data_ack_sync1_pos) begin
+            cnt <= 0;
+        end else if (data_req) begin
+            cnt <= cnt;
+        end else begin
+            cnt <= cnt + 1;
+        end
+    end
+end
+
+//==========================< 信号 >=========================
+reg data_req_r;
+
+//=========================================================
+//-- data_req_r: when is 1'b1 and when is 1'b0
+//=========================================================
+always @(posedge clk_a or negedge rst_n) begin
+    if (!rst_n) begin
+        data_req_r <= 1'b0;
+    end else begin
+        if (data_ack_sync1_pos) begin
+            data_req_r <= 1'b0;
+        end else if (cnt==3'd4) begin
+            data_req_r <= 1'b1;
+        end else begin
+            data_req_r <= data_req_r;
+        end
+    end
+end
+
+assign data_req = data_req_r;
+
+endmodule
+
+
+
+module data_receiver (
+//==========================< 端口 >=========================
+    input clk_b,
+    input rst_n,
+    input data_req,
+    input [4 -1:0] data,
+
+    output data_ack,
+    output data_sync
+);
+//==========================< 端口 >=========================
+reg data_req_sync1;
+reg data_req_sync2;
+
+//=========================================================
+//-- data_req_sync1/2
+//=========================================================
+always @(posedge clk_b or negedge rst_n) begin
+    if (!rst_n) begin
+        data_req_sync1 <= 1'b0;
+        data_req_sync2 <= 1'b0;
+    end else begin
+        data_req_sync1 <= data_req;
+        data_req_sync2 <= data_req_sync1;
+    end
+end
+
+wire data_req_sync1_pos = data_req_sync1 && !data_req_sync2;
+
+//==========================< 端口 >=========================
+reg data_ack_r;
+
+//=========================================================
+//-- data_ack_r
+//=========================================================
+always @(posedge clk_b or negedge rst_n) begin
+    if (!rst_n) begin
+        data_ack_r <= 1'b0;
+    end else begin
+        if (data_req_sync1_pos) begin
+            data_ack_r <= 1'b1;
+        end else begin
+            data_ack_r <= 1'b0;
+        end
+    end
+end
+
+//==========================< 端口 >=========================
+reg [4 -1:0] data_sync_r;
+
+always @(posedge clk_b or negedge rst_n) begin
+    if (!rst_n) begin
+        data_sync_r <= 'b0;
+    end else begin
+        if (data_req_sync1_pos) begin
+            data_sync_r <= data;
+        end else begin
+            data_sync_r <= data_sync_r;
+        end
+    end
+end
+
+assign data_sync = data_sync_r;
+    
+endmodule