commit the gray_2_bin asy_handshake
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yunlongLi
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//==========================================================
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//--Author : colonel
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//--Date : 11-14
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//--Module : asy_handshake_data
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//--Function: use handshake to asy the data
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//==========================================================
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module asy_handshake_data(
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input tclk,
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input t_rstn,
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input rclk,
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input r_rstn,
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input [4:0] data_in,
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output [4:0] data_out
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);
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//==========================< 信号 >=========================
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wire ack;
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wire req;
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reg [4:0] data_reg;
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//==========================< instance >====================
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tx u_tx(
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.tclk(tclk),
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.t_rstn(t_rstn),
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.i_ack(ack),
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.i_data_in(data_in),
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.o_req(req),
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.o_tx_data(data_reg)
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);
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rx u_rx(
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.rclk(rclk),
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.r_rstn(r_rstn),
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.i_req(req),
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.i_data_in(data_reg),
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.o_ack(ack),
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.o_rx_data(data_out)
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);
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endmodule
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//=============================tx_module=====================
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module tx (
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input tclk,
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input t_rstn,
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input i_ack,
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input [4:0] i_data_in,
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output reg o_req,
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output reg[4:0] o_tx_data
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);
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//==========================< 信号 >=========================
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reg des_sync_src_ack_1;
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reg des_sync_src_ack_2;
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always @(posedge tclk or negedge t_rstn) begin
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if (!t_rstn) begin
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des_sync_src_ack_1 <= 1'b0;
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des_sync_src_ack_2 <= 1'b0;
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end else begin
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des_sync_src_ack_1 <= i_ack;
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des_sync_src_ack_2 <= des_sync_src_ack_1;
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end
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end
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wire des_sync_src_neg = !des_sync_src_ack_1 & des_sync_src_ack_2;
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always @(posedge tclk or negedge t_rstn) begin
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if (!t_rstn) begin
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o_tx_data <= 'b0;
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end else if (des_sync_src_neg) begin
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o_tx_data <= i_data_in;
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end
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end
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//=============================
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//--o_req
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//=============================
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always @(posedge tclk or negedge t_rstn) begin
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if (!t_rstn) begin
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o_req <= 1'b0;
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end else if (des_sync_src_ack_2) begin
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o_req <= 1'b0;
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end else begin
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o_req <= 1'b1;
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end
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end
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endmodule
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//==============================rx module===========
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module rx(
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input rclk,
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input r_rstn,
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input i_req,
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input [4:0] i_data_in,
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output reg o_ack,
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output reg [4:0] o_rx_data
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);
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//==========================< 信号 >=========================
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reg src_sync_des_req_1;
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reg src_sync_des_req_2;
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always @(posedge rclk or r_rstn) begin
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if (!r_rstn) begin
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src_sync_des_req_1 <= 1'b0;
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src_sync_des_req_2 <= 1'b0;
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end else begin
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src_sync_des_req_1 <= i_req;
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src_sync_des_req_2 <= src_sync_des_req_1;
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end
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end
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always @(posedge rclk or negedge r_rstn) begin
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if (!r_rstn) begin
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o_ack <= 1'b0;
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end else begin
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o_ack <= src_sync_des_req_2;
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end
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end
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always @(posedge rclk or negedge r_rstn) begin
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if (!r_rstn) begin
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o_rx_data <= 'b0;
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end else if (src_sync_des_req_2) begin
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o_rx_data <= i_data_in;
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end else begin
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o_rx_data <= o_rx_data;
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end
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end
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endmodule
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@ -0,0 +1,25 @@
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module gray_trans#(
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parameter SIZE=8
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)(
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input [SIZE-1] bin,
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output[SIZE-1] gray,
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);
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assign gray=bin^{1'b0,bin[SIZE-1:1]};
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endmodule
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module gray_trans#(
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parameter SIZE=8
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)(
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input [SIZE-1:0] gray,
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output[SIZE-1]:0 bin
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);
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assign bin[SIZE-1]=gray[SIZE-1];
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genvar i;
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generate
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for (i=SIZE-2;i>0;i=i-1)
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begin:trans
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assign bin[i]=gray[i]^bin[i+1];
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end
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endgenerate
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endmodule
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@ -0,0 +1,77 @@
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//==========================================================
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//--Author : colonel
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//--Date : 11-14
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//--Module : rr_arbiter
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//--Function: uart is diviede into uart_send,uart_reciver
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//--Reference:https://blog.csdn.net/yueqiu693/article/details/125073144
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//==========================================================
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module rr_arbiter
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(
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input clk,
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input rst_n,
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input [3:0]req,
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input req_en,
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output[3:0]grant_arb
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);
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reg [3:0] state_c_arb;
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reg [3:0] state_n_arb;
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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state_c_arb<=0;
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end
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else if(req_en)begin
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state_c_arb=state_n_arb;
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end
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else begin
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state_c_arb<=0;
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end
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end
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always @(*) begin
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if (!rst_n) begin
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state_n_arb<=0;
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end
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else begin
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case(state_c_arb)
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4'b0001:begin
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case(1'b1)
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req[1]:state_n_arb<=4'b0010;
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req[2]:state_n_arb<=4'b0100;
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req[3]:state_n_arb<=4'b1000;
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req[0]:state_n_arb<=4'b0001;
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default:state_n_arb<=4'b0001;
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endcase
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end
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4'b0010:begin
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case(1'b1)
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req[2]:state_n_arb<=4'b0100;
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req[3]:state_n_arb<=4'b1000;
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req[0]:state_n_arb<=4'b0001;
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req[1]:state_n_arb<=4'b0010;
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default:state_n_arb<=4'b0010;
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endcase
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end
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4'b0100:begin
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case(1'b1)
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req[3]:state_n_arb<=4'b1000;
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req[0]:state_n_arb<=4'b0001;
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req[1]:state_n_arb<=4'b0010;
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req[2]:state_n_arb<=4'b0100;
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default:state_n_arb<=4'b0100;
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endcase
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end
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4'b1000:begin
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case(1'b1)
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req[0]:state_n_arb<=4'b0001;
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req[1]:state_n_arb<=4'b0010;
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req[2]:state_n_arb<=4'b0100;
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req[3]:state_n_arb<=4'b1000;
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default:state_n_arb<=4'b1000;
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endcase
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end
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default:state_n_arb<=4'b0001;
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endcase
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end
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end
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assign grant_arb=state_n_arb;
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endmodule
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