add find_seq_1.v and pipline_adder.v
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yunlongLi
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//=======================================
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//--Author : colonel
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//--Date ：10—28
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//--Module : find_sequ_1
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//--Function: to find the index of 1 when input din
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//=======================================
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module find_sequ_1#(
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//==========================< 参数 >=========================
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parameter DATA_WIDTH = 8,
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parameter INDEX_LEN = $clog2(DATA_WIDTH)
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)(
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//==========================< 端口 >=========================
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input wire clk,
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input wire rst_n,
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input wire din_vld,
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input wire [DATA_WIDTH -1:0] din,
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output wire done,
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output wire idx_vld,
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output wire [INDEX_LEN -1:0] inx,
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input wire idx_rdy
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);
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//==========================< 参数 >=========================
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localparam IDLE = 2'b00;
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localparam SERACHING = 2'b01;
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localparam FOUND = 2'b10;
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//==========================< 信号 >=========================
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reg [INDEX_LEN -1:0] curr_index;
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reg [INDEX_LEN -1:0] found_index;
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reg found_flag;
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//==========================< FSM-0 >=========================
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reg [2 -1:0] sta_cur;
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reg [2 -1:0] sta_nxt;
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//=========================================================
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//-- FSM-1: State transition
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//=========================================================
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always @(negedge clk or negedge rst_n) begin
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if (!rst_n) begin
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sta_cur <= IDLE;
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end else begin
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sta_cur <= sta_nxt;
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end
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end
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//=========================================================
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//-- FSM-2: State Jump Condition
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//=========================================================
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always @(*) begin
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case (sta_cur)
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IDLE: begin
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if(!din_vld) begin
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sta_nxt = IDLE;
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end else begin
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sta_nxt = SERACHING;
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end
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end
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SERACHING: begin
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if (din[curr_index]==1'b1) begin
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sta_nxt = FOUND;
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end else begin
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sta_nxt = SERACHING;
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end
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end
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FOUND: begin
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if(din_vld) begin
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sta_nxt <= SERACHING;
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end else begin
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sta_nxt <= IDLE;
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end
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end
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default: ;
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endcase
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end
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//=========================================================
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//-- FSM-3: State Action
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//=========================================================
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//=========================================================
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//-- FSM-3: State Action
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//-- curr_index
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//=========================================================
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// always @(posedge clk or negedge rst_n) begin
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// if (!rst_n) begin
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// curr_index <= 0;
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// end else begin
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// case (sta_cur)
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// IDLE: begin
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// curr_index <= 0;
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// end
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// SERACHING: begin
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// if(din[curr_index] == 1'b0) begin
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// curr_index <= curr_index + 1;
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// end
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// end
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// FOUND: begin
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// curr_index <= curr_index;
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// end
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// default: begin
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// curr_index <= 0;
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// end
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// endcase
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// end
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// end
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always @(posedge clk or negedge rst_n) begin
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if(!rst_n) begin
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curr_index <= 0;
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end else begin
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if(sta_cur==SERACHING) begin
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curr_index <= curr_index + 1;
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end else begin
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curr_index <= curr_index;
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end
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end
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end
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assign done = (sta_cur==FOUND) && idx_rdy;
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assign idx_vld = (sta_cur==FOUND);
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assign inx = curr_index;
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endmodule
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@ -0,0 +1,70 @@
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//=======================================
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//--Author : colonel
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//--Date ：10—29
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//--Module : pipline_adder
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//--Function: to meet the adder pipline of three input
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//=======================================
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module pipline_adder (
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//==========================< 端口 >=========================
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input wire clk,
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input wire a_in,
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input wire b_in,
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input wire c_in,
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input wire vld_in,
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output reg vld_out,
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output reg[1:0] sum_out
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);
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//==========================< 信号 >=========================
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//--S1 Stage
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reg vld_s1;
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reg a_s1,b_s1,c_s1;
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wire [1:0] a_b_sum_s1;
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//--S2 Stage
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reg vld_s2;
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reg c_s2;
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reg a_b_sum_s2;
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wire [1:0] sum_s2;
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//=========================================================
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//-- S1 Stage
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//=========================================================
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always @(posedge clk) begin
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if(vld_in) begin
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a_s1 <= a_in;
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b_s1 <= b_in;
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c_s2 <= c_in;
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vld_s1 <= vld_in;
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end else begin
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vld_s1 <= 1'b0;
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end
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end
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assign a_b_sum_s1 = {1'b0,a_s1} + {1'b0,b_s1};
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//=========================================================
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//-- S2 Stage
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//=========================================================
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always @(posedge clk) begin
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if (vld_s1) begin
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a_b_sum_s2 <= a_b_sum_s1;
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c_s2 <= c_s1;
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vld_s2 <= vld_s1;
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end
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end
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assign sum_s2 = a_b_sum_s2 + c_s2;
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//=========================================================
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//-- sum_out
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//=========================================================
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always @(posedge clk) begin
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if(vld_s2) begin
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vld_out <= vld_s2;
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sum_out <= sum_s2;
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end
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end
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endmodule
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