finish cpu_top.v

2024-11-07 22:56:15 +08:00 · 2024-11-07 22:56:15 +08:00 · dddd263c4b
parent e5e04968ce
commit dddd263c4b
1 changed files with 155 additions and 0 deletions
--- a/course/hitArchi/cpu/cpu_top.v
+++ b/course/hitArchi/cpu/cpu_top.v
@ -71,5 +71,160 @@ assign debug_wb_rf_wdata= WB_DATA；


 //==========================< IF part >=========================
+pc u_pc(
+    .clk(clk),
+    .rst_n(rst_n),
+    .next_pc(IF_NPC),
+    .pc(IF_PC)
+);
+
+add u_add(
+    .pc(IF_PC),
+    .add_result(IF_ADDNPC)
+);
+
+ins_reg u_ins_reg(
+    .ins_addr(IF_PC),
+    .ins_out(IF_INS)
+);
+
+npc_mux u_npc_mux(
+    .ori_npc(IF_ADDNPC),
+    .jmp_pc(MEM_ALUOUT),
+    .select(MEM_JUDG),
+    .npc(IF_NPC)
+);
+
+if_id u_if_id(
+    .clk(clk),
+    .rst_n(rst_n),
+    .wdata_1_1(IF_NPC),
+    .wdata_1_2(IF_INS),
+    .wdata_1_3(IF_PC),
+    .rdata_1_1(ID_NPC),
+    .rdata_1_2(ID_INS),
+    .rdata_1_3(ID_PC)
+);
+
+//==========================< ID part >=========================
+regs u_regs(
+    .clk(clk),
+    .we(WB_ABLE),
+    .raddr1(ID_INS[25:21]),
+    .raddr2(ID_INS[20:16]),
+    .rdata1(ID_RS),
+    .rdata2(ID_RT),
+    .waddr(WB_ADDR),
+    .wdata(WB_DATA)
+);
+
+externder u_externder(
+    .imm(ID_INS[15:0]),
+    .opcode(ID_INS(31:26)),
+    .extend_result(ID_IMM)
+);
+
+id_ex u_id_ex(
+    .clk(clk),
+    .rst_n(rst_n),
+    .wdata_2_1(ID_NPC),
+    .wdata_2_2(ID_RS),
+    .wdata_2_3(ID_RT),
+    .wdata_2_4(ID_IMM),
+    .wdata_2_5(ID_INS),
+    .wdata_2_6(ID_PC),
+
+    .rdata_2_1(EX_NPC),
+    .rdata_2_2(EX_RS),
+    .rdata_2_3(EX_RT),
+    .rdata_2_4(EX_IMM),
+    .rdata_2_5(EX_INS),
+    .rdata_2_6(EX_PC)
+);
+
+//==========================< EX part >=========================
+zero u_zero(
+    .a(EX_RS),
+    .b(EX_RT),
+    .opcode(EX_INS[31:26]),
+    .judge(EX_JUDG)
+);
+
+mux_1 u_mux_1(
+    .d0(EX_NPC),
+    .d1(EX_RS),
+    .select(EX_INS[31:26]),
+    .out(EX_A)
+);
+
+mux_2 u_mux_2(
+    .d0(EX_IMM),
+    .d1(EX_RT),
+    .select(EX_INS[31:26]),
+    .out(EX_B)
+);
+
+alu u_alu(
+    .a(EX_A),
+    .b(EX_B),
+    .sll(EX_INS[10:6]),
+    .card(EX_INS[5:0]),
+    .opcode(EX_INS[31:26]),
+    .f(EX_ALUOUT)
+);
+
+ex_mem u_ex_mem(
+    .clk(clk),
+    .rst_n(rst_n),
+    .wdata_3_1(EX_JUDG),
+    .wdata_3_2(EX_ALUOUT),
+    .wdata_3_3(EX_RT),
+    .wdata_3_4(EX_INS),
+    .wdata_3_5(EX_PC),
+    .rdata_3_1(MEM_JUDG),
+    .rdata_3_2(MEM_ALUOUT),
+    .rdata_3_3(MEM_RT),
+    .rdata_3_4(MEM_INS),
+    .rdata_3_5(MME_PC)
+);
+
+//==========================< MEM part >=========================
+data_reg u_data_reg(
+    .clk(clk),
+    .opcode(MEM_INS[31:26]),
+    .data_reg_wdata(MEM_RT),
+    .data_reg_addr(MEM_ALUOUT),
+    .data_reg_rdata(MEM_MEMOUT)
+);
+
+mem_wb u_mem_wb(
+    .clk(clk),
+    .rst_n(rst_n),
+    .wdata_4_1(MEM_MEMOUT),
+    .wdata_4_2(MEM_ALUOUT),
+    .wdata_4_3(MEM_INS),
+    .wdata_4_4(MME_PC),
+    
+    .rdata_4_1(WB_MEMOUT),
+    .rdata_4_2(WB_ALUOUT),
+    .rdata_4_3(WB_INS),
+    .rdata_4_4(WB_PC),
+    .wb_enable(WB_ABLE)
+);
+
+//==========================< WB part >=========================
+wb_mux u_wb_mux(
+    .d0(WB_MEMOUT),
+    .d1(WB_ALUOUT),
+    .select(WB_INS[31:26]),
+    .out(WB_DATA)
+);
+
+wb_mux_2 u_wb_mux_2(
+    .a(WB_INS[20:16]),
+    .b(WB_INS[15:11]),
+    .opcode(WB_INS[31:26]),
+    .result(WB_ADDR)
+);

 endmodule