From c7465f3f65179a9f3516b9ae16ca7a86f4c8bcec Mon Sep 17 00:00:00 2001
From: yunlongLi <1203701249@qq.com>
Date: Sun, 27 Oct 2024 21:22:34 +0800
Subject: [PATCH] BPU-TOP Final Report

---
 tests/bpu_top/config.py                       |     2 +-
 tests/bpu_top/env/bpu_agent.py                |   514 +
 tests/bpu_top/env/bpu_bundle.py               |   372 +
 tests/bpu_top/env/bpu_dut.py                  |    27 +
 tests/bpu_top/env/bpu_env.py                  |    62 +
 tests/bpu_top/env/config.py                   |     6 +
 .../GLCC_BPU-TOP模块验证报告.pdf        |   Bin 0 -> 958175 bytes
 .../BPUTop/CAMTemplate.sv.func-sort-c.html    |    72 +
 .../line_dat/BPUTop/CAMTemplate.sv.func.html  |    72 +
 .../line_dat/BPUTop/CAMTemplate.sv.gcov.html  |   212 +
 .../BPUTop/CAMTemplate_32.sv.func-sort-c.html |    72 +
 .../BPUTop/CAMTemplate_32.sv.func.html        |    72 +
 .../BPUTop/CAMTemplate_32.sv.gcov.html        |   212 +
 .../BPUTop/CAMTemplate_33.sv.func-sort-c.html |    72 +
 .../BPUTop/CAMTemplate_33.sv.func.html        |    72 +
 .../BPUTop/CAMTemplate_33.sv.gcov.html        |   260 +
 .../BPUTop/CAMTemplate_41.sv.func-sort-c.html |    72 +
 .../BPUTop/CAMTemplate_41.sv.func.html        |    72 +
 .../BPUTop/CAMTemplate_41.sv.gcov.html        |   186 +
 .../BPUTop/CAMTemplate_43.sv.func-sort-c.html |    72 +
 .../BPUTop/CAMTemplate_43.sv.func.html        |    72 +
 .../BPUTop/CAMTemplate_43.sv.gcov.html        |   188 +
 .../BPUTop/Composer.sv.func-sort-c.html       |    72 +
 .../line_dat/BPUTop/Composer.sv.func.html     |    72 +
 .../line_dat/BPUTop/Composer.sv.gcov.html     |  2502 +
 .../DelayNWithValid.sv.func-sort-c.html       |    72 +
 .../BPUTop/DelayNWithValid.sv.func.html       |    72 +
 .../BPUTop/DelayNWithValid.sv.gcov.html       |   183 +
 .../DelayNWithValid_1.sv.func-sort-c.html     |    72 +
 .../BPUTop/DelayNWithValid_1.sv.func.html     |    72 +
 .../BPUTop/DelayNWithValid_1.sv.gcov.html     |   347 +
 .../BPUTop/DelayN_1.sv.func-sort-c.html       |    72 +
 .../line_dat/BPUTop/DelayN_1.sv.func.html     |    72 +
 .../line_dat/BPUTop/DelayN_1.sv.gcov.html     |   188 +
 .../BPUTop/DelayN_2.sv.func-sort-c.html       |    72 +
 .../line_dat/BPUTop/DelayN_2.sv.func.html     |    72 +
 .../line_dat/BPUTop/DelayN_2.sv.gcov.html     |   178 +
 .../BPUTop/DelayN_4.sv.func-sort-c.html       |    72 +
 .../line_dat/BPUTop/DelayN_4.sv.func.html     |    72 +
 .../line_dat/BPUTop/DelayN_4.sv.gcov.html     |   167 +
 .../line_dat/BPUTop/FTB.sv.func-sort-c.html   |    72 +
 .../line_dat/BPUTop/FTB.sv.func.html          |    72 +
 .../line_dat/BPUTop/FTB.sv.gcov.html          |  1732 +
 .../BPUTop/FTBBank.sv.func-sort-c.html        |    72 +
 .../line_dat/BPUTop/FTBBank.sv.func.html      |    72 +
 .../line_dat/BPUTop/FTBBank.sv.gcov.html      |  6446 ++
 .../BPUTop/FauFTB.sv.func-sort-c.html         |    72 +
 .../line_dat/BPUTop/FauFTB.sv.func.html       |    72 +
 .../line_dat/BPUTop/FauFTB.sv.gcov.html       |  4831 ++
 .../BPUTop/FauFTBWay.sv.func-sort-c.html      |    72 +
 .../line_dat/BPUTop/FauFTBWay.sv.func.html    |    72 +
 .../line_dat/BPUTop/FauFTBWay.sv.gcov.html    |   263 +
 ...ed1WDataModuleTemplate.sv.func-sort-c.html |    72 +
 .../Folded1WDataModuleTemplate.sv.func.html   |    72 +
 .../Folded1WDataModuleTemplate.sv.gcov.html   |   222 +
 ...1WDataModuleTemplate_2.sv.func-sort-c.html |    72 +
 .../Folded1WDataModuleTemplate_2.sv.func.html |    72 +
 .../Folded1WDataModuleTemplate_2.sv.gcov.html |   222 +
 .../FoldedSRAMTemplate.sv.func-sort-c.html    |    72 +
 .../BPUTop/FoldedSRAMTemplate.sv.func.html    |    72 +
 .../BPUTop/FoldedSRAMTemplate.sv.gcov.html    |   300 +
 .../FoldedSRAMTemplate_1.sv.func-sort-c.html  |    72 +
 .../BPUTop/FoldedSRAMTemplate_1.sv.func.html  |    72 +
 .../BPUTop/FoldedSRAMTemplate_1.sv.gcov.html  |   176 +
 .../FoldedSRAMTemplate_20.sv.func-sort-c.html |    72 +
 .../BPUTop/FoldedSRAMTemplate_20.sv.func.html |    72 +
 .../BPUTop/FoldedSRAMTemplate_20.sv.gcov.html |   256 +
 .../FoldedSRAMTemplate_21.sv.func-sort-c.html |    72 +
 .../BPUTop/FoldedSRAMTemplate_21.sv.func.html |    72 +
 .../BPUTop/FoldedSRAMTemplate_21.sv.gcov.html |   166 +
 .../FoldedSRAMTemplate_25.sv.func-sort-c.html |    72 +
 .../BPUTop/FoldedSRAMTemplate_25.sv.func.html |    72 +
 .../BPUTop/FoldedSRAMTemplate_25.sv.gcov.html |   231 +
 .../BPUTop/ITTage.sv.func-sort-c.html         |    72 +
 .../line_dat/BPUTop/ITTage.sv.func.html       |    72 +
 .../line_dat/BPUTop/ITTage.sv.gcov.html       |  1345 +
 .../BPUTop/ITTageTable.sv.func-sort-c.html    |    72 +
 .../line_dat/BPUTop/ITTageTable.sv.func.html  |    72 +
 .../line_dat/BPUTop/ITTageTable.sv.gcov.html  |   302 +
 .../BPUTop/ITTageTable_1.sv.func-sort-c.html  |    72 +
 .../BPUTop/ITTageTable_1.sv.func.html         |    72 +
 .../BPUTop/ITTageTable_1.sv.gcov.html         |   297 +
 .../BPUTop/ITTageTable_2.sv.func-sort-c.html  |    72 +
 .../BPUTop/ITTageTable_2.sv.func.html         |    72 +
 .../BPUTop/ITTageTable_2.sv.gcov.html         |   298 +
 .../BPUTop/ITTageTable_3.sv.func-sort-c.html  |    72 +
 .../BPUTop/ITTageTable_3.sv.func.html         |    72 +
 .../BPUTop/ITTageTable_3.sv.gcov.html         |   298 +
 .../BPUTop/ITTageTable_4.sv.func-sort-c.html  |    72 +
 .../BPUTop/ITTageTable_4.sv.func.html         |    72 +
 .../BPUTop/ITTageTable_4.sv.gcov.html         |   298 +
 .../PriorityMuxModule.sv.func-sort-c.html     |    72 +
 .../BPUTop/PriorityMuxModule.sv.func.html     |    72 +
 .../BPUTop/PriorityMuxModule.sv.gcov.html     |   156 +
 .../PriorityMuxModule_12.sv.func-sort-c.html  |    72 +
 .../BPUTop/PriorityMuxModule_12.sv.func.html  |    72 +
 .../BPUTop/PriorityMuxModule_12.sv.gcov.html  |   526 +
 .../PriorityMuxModule_16.sv.func-sort-c.html  |    72 +
 .../BPUTop/PriorityMuxModule_16.sv.func.html  |    72 +
 .../BPUTop/PriorityMuxModule_16.sv.gcov.html  |   156 +
 .../PriorityMuxModule_20.sv.func-sort-c.html  |    72 +
 .../BPUTop/PriorityMuxModule_20.sv.func.html  |    72 +
 .../BPUTop/PriorityMuxModule_20.sv.gcov.html  |   152 +
 .../PriorityMuxModule_4.sv.func-sort-c.html   |    72 +
 .../BPUTop/PriorityMuxModule_4.sv.func.html   |    72 +
 .../BPUTop/PriorityMuxModule_4.sv.gcov.html   |   430 +
 .../PriorityMuxModule_8.sv.func-sort-c.html   |    72 +
 .../BPUTop/PriorityMuxModule_8.sv.func.html   |    72 +
 .../BPUTop/PriorityMuxModule_8.sv.gcov.html   |   170 +
 .../line_dat/BPUTop/RAS.sv.func-sort-c.html   |    72 +
 .../line_dat/BPUTop/RAS.sv.func.html          |    72 +
 .../line_dat/BPUTop/RAS.sv.gcov.html          |   959 +
 .../BPUTop/RASStack.sv.func-sort-c.html       |    72 +
 .../line_dat/BPUTop/RASStack.sv.func.html     |    72 +
 .../line_dat/BPUTop/RASStack.sv.gcov.html     |  2010 +
 .../BPUTop/SCTable.sv.func-sort-c.html        |    72 +
 .../line_dat/BPUTop/SCTable.sv.func.html      |    72 +
 .../line_dat/BPUTop/SCTable.sv.gcov.html      |   320 +
 .../BPUTop/SCTable_1.sv.func-sort-c.html      |    72 +
 .../line_dat/BPUTop/SCTable_1.sv.func.html    |    72 +
 .../line_dat/BPUTop/SCTable_1.sv.gcov.html    |   326 +
 .../BPUTop/SCTable_2.sv.func-sort-c.html      |    72 +
 .../line_dat/BPUTop/SCTable_2.sv.func.html    |    72 +
 .../line_dat/BPUTop/SCTable_2.sv.gcov.html    |   324 +
 .../BPUTop/SCTable_3.sv.func-sort-c.html      |    72 +
 .../line_dat/BPUTop/SCTable_3.sv.func.html    |    72 +
 .../line_dat/BPUTop/SCTable_3.sv.gcov.html    |   324 +
 .../SRAMTemplate_13.sv.func-sort-c.html       |    72 +
 .../BPUTop/SRAMTemplate_13.sv.func.html       |    72 +
 .../BPUTop/SRAMTemplate_13.sv.gcov.html       |   519 +
 .../SRAMTemplate_14.sv.func-sort-c.html       |    72 +
 .../BPUTop/SRAMTemplate_14.sv.func.html       |    72 +
 .../BPUTop/SRAMTemplate_14.sv.gcov.html       |   324 +
 .../SRAMTemplate_15.sv.func-sort-c.html       |    72 +
 .../BPUTop/SRAMTemplate_15.sv.func.html       |    72 +
 .../BPUTop/SRAMTemplate_15.sv.gcov.html       |   241 +
 .../SRAMTemplate_34.sv.func-sort-c.html       |    72 +
 .../BPUTop/SRAMTemplate_34.sv.func.html       |    72 +
 .../BPUTop/SRAMTemplate_34.sv.gcov.html       |   305 +
 .../SRAMTemplate_35.sv.func-sort-c.html       |    72 +
 .../BPUTop/SRAMTemplate_35.sv.func.html       |    72 +
 .../BPUTop/SRAMTemplate_35.sv.gcov.html       |   272 +
 .../SRAMTemplate_39.sv.func-sort-c.html       |    72 +
 .../BPUTop/SRAMTemplate_39.sv.func.html       |    72 +
 .../BPUTop/SRAMTemplate_39.sv.gcov.html       |   225 +
 .../SRAMTemplate_43.sv.func-sort-c.html       |    72 +
 .../BPUTop/SRAMTemplate_43.sv.func.html       |    72 +
 .../BPUTop/SRAMTemplate_43.sv.gcov.html       |   247 +
 .../BPUTop/TageBTable.sv.func-sort-c.html     |    72 +
 .../line_dat/BPUTop/TageBTable.sv.func.html   |    72 +
 .../line_dat/BPUTop/TageBTable.sv.gcov.html   |   264 +
 .../BPUTop/TageTable.sv.func-sort-c.html      |    72 +
 .../line_dat/BPUTop/TageTable.sv.func.html    |    72 +
 .../line_dat/BPUTop/TageTable.sv.gcov.html    |   828 +
 .../BPUTop/TageTable_1.sv.func-sort-c.html    |    72 +
 .../line_dat/BPUTop/TageTable_1.sv.func.html  |    72 +
 .../line_dat/BPUTop/TageTable_1.sv.gcov.html  |   830 +
 .../BPUTop/TageTable_2.sv.func-sort-c.html    |    72 +
 .../line_dat/BPUTop/TageTable_2.sv.func.html  |    72 +
 .../line_dat/BPUTop/TageTable_2.sv.gcov.html  |   830 +
 .../BPUTop/TageTable_3.sv.func-sort-c.html    |    72 +
 .../line_dat/BPUTop/TageTable_3.sv.func.html  |    72 +
 .../line_dat/BPUTop/TageTable_3.sv.gcov.html  |   830 +
 .../BPUTop/Tage_SC.sv.func-sort-c.html        |    72 +
 .../line_dat/BPUTop/Tage_SC.sv.func.html      |    72 +
 .../line_dat/BPUTop/Tage_SC.sv.gcov.html      |  5986 ++
 .../BPUTop/WrBypass.sv.func-sort-c.html       |    72 +
 .../line_dat/BPUTop/WrBypass.sv.func.html     |    72 +
 .../line_dat/BPUTop/WrBypass.sv.gcov.html     |   357 +
 .../BPUTop/WrBypass_32.sv.func-sort-c.html    |    72 +
 .../line_dat/BPUTop/WrBypass_32.sv.func.html  |    72 +
 .../line_dat/BPUTop/WrBypass_32.sv.gcov.html  |   431 +
 .../BPUTop/WrBypass_33.sv.func-sort-c.html    |    72 +
 .../line_dat/BPUTop/WrBypass_33.sv.func.html  |    72 +
 .../line_dat/BPUTop/WrBypass_33.sv.gcov.html  |   656 +
 .../BPUTop/WrBypass_41.sv.func-sort-c.html    |    72 +
 .../line_dat/BPUTop/WrBypass_41.sv.func.html  |    72 +
 .../line_dat/BPUTop/WrBypass_41.sv.gcov.html  |   233 +
 .../BPUTop/WrBypass_43.sv.func-sort-c.html    |    72 +
 .../line_dat/BPUTop/WrBypass_43.sv.func.html  |    72 +
 .../line_dat/BPUTop/WrBypass_43.sv.gcov.html  |   233 +
 .../BPUTop/array_0_0.sv.func-sort-c.html      |    72 +
 .../line_dat/BPUTop/array_0_0.sv.func.html    |    72 +
 .../line_dat/BPUTop/array_0_0.sv.gcov.html    |   152 +
 .../BPUTop/array_0_0_ext.v.func-sort-c.html   |    72 +
 .../line_dat/BPUTop/array_0_0_ext.v.func.html |    72 +
 .../line_dat/BPUTop/array_0_0_ext.v.gcov.html |   125 +
 .../BPUTop/array_3.sv.func-sort-c.html        |    72 +
 .../line_dat/BPUTop/array_3.sv.func.html      |    72 +
 .../line_dat/BPUTop/array_3.sv.gcov.html      |   154 +
 .../BPUTop/array_3_ext.v.func-sort-c.html     |    72 +
 .../line_dat/BPUTop/array_3_ext.v.func.html   |    72 +
 .../line_dat/BPUTop/array_3_ext.v.gcov.html   |   128 +
 .../BPUTop/array_4.sv.func-sort-c.html        |    72 +
 .../line_dat/BPUTop/array_4.sv.func.html      |    72 +
 .../line_dat/BPUTop/array_4.sv.gcov.html      |   154 +
 .../BPUTop/array_4_ext.v.func-sort-c.html     |    72 +
 .../line_dat/BPUTop/array_4_ext.v.func.html   |    72 +
 .../line_dat/BPUTop/array_4_ext.v.gcov.html   |   124 +
 .../BPUTop/array_5.sv.func-sort-c.html        |    72 +
 .../line_dat/BPUTop/array_5.sv.func.html      |    72 +
 .../line_dat/BPUTop/array_5.sv.gcov.html      |   154 +
 .../BPUTop/array_5_ext.v.func-sort-c.html     |    72 +
 .../line_dat/BPUTop/array_5_ext.v.func.html   |    72 +
 .../line_dat/BPUTop/array_5_ext.v.gcov.html   |   128 +
 .../BPUTop/array_6.sv.func-sort-c.html        |    72 +
 .../line_dat/BPUTop/array_6.sv.func.html      |    72 +
 .../line_dat/BPUTop/array_6.sv.gcov.html      |   158 +
 .../BPUTop/array_6_ext.v.func-sort-c.html     |    72 +
 .../line_dat/BPUTop/array_6_ext.v.func.html   |    72 +
 .../line_dat/BPUTop/array_6_ext.v.gcov.html   |   133 +
 .../BPUTop/array_7.sv.func-sort-c.html        |    72 +
 .../line_dat/BPUTop/array_7.sv.func.html      |    72 +
 .../line_dat/BPUTop/array_7.sv.gcov.html      |   158 +
 .../BPUTop/array_7_ext.v.func-sort-c.html     |    72 +
 .../line_dat/BPUTop/array_7_ext.v.func.html   |    72 +
 .../line_dat/BPUTop/array_7_ext.v.gcov.html   |   129 +
 .../BPUTop/array_8.sv.func-sort-c.html        |    72 +
 .../line_dat/BPUTop/array_8.sv.func.html      |    72 +
 .../line_dat/BPUTop/array_8.sv.gcov.html      |   154 +
 .../BPUTop/array_8_ext.v.func-sort-c.html     |    72 +
 .../line_dat/BPUTop/array_8_ext.v.func.html   |    72 +
 .../line_dat/BPUTop/array_8_ext.v.gcov.html   |   128 +
 .../BPUTop/data_16x16.sv.func-sort-c.html     |    72 +
 .../line_dat/BPUTop/data_16x16.sv.func.html   |    72 +
 .../line_dat/BPUTop/data_16x16.sv.gcov.html   |   171 +
 .../BPUTop/data_32x16.sv.func-sort-c.html     |    72 +
 .../line_dat/BPUTop/data_32x16.sv.func.html   |    72 +
 .../line_dat/BPUTop/data_32x16.sv.gcov.html   |   171 +
 .../BPUTop/data_mem_0_4x2.sv.func-sort-c.html |    72 +
 .../BPUTop/data_mem_0_4x2.sv.func.html        |    72 +
 .../BPUTop/data_mem_0_4x2.sv.gcov.html        |   165 +
 .../BPUTop/data_mem_0_8x3.sv.func-sort-c.html |    72 +
 .../BPUTop/data_mem_0_8x3.sv.func.html        |    72 +
 .../BPUTop/data_mem_0_8x3.sv.gcov.html        |   165 +
 .../BPUTop/data_mem_16x12.sv.func-sort-c.html |    72 +
 .../BPUTop/data_mem_16x12.sv.func.html        |    72 +
 .../BPUTop/data_mem_16x12.sv.gcov.html        |   173 +
 .../BPUTop/data_mem_8x4.sv.func-sort-c.html   |    72 +
 .../line_dat/BPUTop/data_mem_8x4.sv.func.html |    72 +
 .../line_dat/BPUTop/data_mem_8x4.sv.gcov.html |   173 +
 .../line_dat/BPUTop/index-sort-f.html         |   863 +
 .../line_dat/BPUTop/index-sort-l.html         |   863 +
 .../line_dat/BPUTop/index.html                |   863 +
 .../report-20241027201927/line_dat/amber.png  |   Bin 0 -> 141 bytes
 .../line_dat/emerald.png                      |   Bin 0 -> 141 bytes
 .../report-20241027201927/line_dat/gcov.css   |   519 +
 .../report-20241027201927/line_dat/glass.png  |   Bin 0 -> 167 bytes
 .../line_dat/index-sort-f.html                |   103 +
 .../line_dat/index-sort-l.html                |   103 +
 .../report-20241027201927/line_dat/index.html |   103 +
 .../line_dat/merged.info                      | 22109 +++++++
 .../report-20241027201927/line_dat/ruby.png   |   Bin 0 -> 141 bytes
 .../report-20241027201927/line_dat/snow.png   |   Bin 0 -> 141 bytes
 .../report-20241027201927/line_dat/updown.png |   Bin 0 -> 117 bytes
 .../report-20241027201927.html                | 54773 ++++++++++++++++
 tests/bpu_top/test_bpu_sanity.py              |   100 -
 tests/bpu_top/test_bpu_sub_uftb_enable.py     |   113 -
 .../test_bpu_sub_uftb_enable_disable.py       |   121 -
 .../test_bpu_sub_uftb_entry_way_resp_hit.py   |    99 -
 .../test_bpu_sub_uftb_entry_way_update_hit.py |    93 -
 tests/bpu_top/test_bpu_sub_uftb_ready.py      |    87 -
 tests/bpu_top/test_bpu_sub_uftb_reset.py      |    99 -
 .../{ => tests}/test_bpu_reset_true.py        |     0
 .../{ => tests}/test_bpu_reset_vector.py      |     0
 .../bpu_top/tests/test_bpu_sub_ftb_sanity.py  |    22 +
 tests/bpu_top/tests/test_bpu_top_all.py       |  4996 ++
 tests/bpu_top/tests/test_mlvp.py              |   148 +
 tests/bpu_top/tests/test_redirect_signals.py  |  3119 +
 tests/bpu_top/tests/test_sub_predi_enable.py  |   202 +
 tests/bpu_top/tests/test_update_signals.py    |  1247 +
 271 files changed, 147014 insertions(+), 713 deletions(-)
 create mode 100644 tests/bpu_top/env/bpu_agent.py
 create mode 100644 tests/bpu_top/env/bpu_bundle.py
 create mode 100644 tests/bpu_top/env/bpu_dut.py
 create mode 100644 tests/bpu_top/env/bpu_env.py
 create mode 100644 tests/bpu_top/env/config.py
 create mode 100644 tests/bpu_top/reports/GLCC_BPU-TOP模块验证报告.pdf
 create mode 100644 tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/CAMTemplate.sv.func-sort-c.html
 create mode 100644 tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/CAMTemplate.sv.func.html
 create mode 100644 tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/CAMTemplate.sv.gcov.html
 create mode 100644 tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/CAMTemplate_32.sv.func-sort-c.html
 create mode 100644 tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/CAMTemplate_32.sv.func.html
 create mode 100644 tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/CAMTemplate_32.sv.gcov.html
 create mode 100644 tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/CAMTemplate_33.sv.func-sort-c.html
 create mode 100644 tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/CAMTemplate_33.sv.func.html
 create mode 100644 tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/CAMTemplate_33.sv.gcov.html
 create mode 100644 tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/CAMTemplate_41.sv.func-sort-c.html
 create mode 100644 tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/CAMTemplate_41.sv.func.html
 create mode 100644 tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/CAMTemplate_41.sv.gcov.html
 create mode 100644 tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/CAMTemplate_43.sv.func-sort-c.html
 create mode 100644 tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/CAMTemplate_43.sv.func.html
 create mode 100644 tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/CAMTemplate_43.sv.gcov.html
 create mode 100644 tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/Composer.sv.func-sort-c.html
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diff --git a/tests/bpu_top/config.py b/tests/bpu_top/config.py
index e4e48d8..ad6d3bb 100644
--- a/tests/bpu_top/config.py
+++ b/tests/bpu_top/config.py
@@ -2,5 +2,5 @@ import os
 ROOT_PATH = os.path.dirname(os.path.abspath(__file__))+"/../../"
 TESTS_PATH = ROOT_PATH + "tests/"
 DUT_PATH = ROOT_PATH + "out/picker_out_BPUTop/"
+FTB_PATH = ROOT_PATH + "tests/bpu_top/env/"
 #os.sys.path.append(DUT_PATH)
-
diff --git a/tests/bpu_top/env/bpu_agent.py b/tests/bpu_top/env/bpu_agent.py
new file mode 100644
index 0000000..a10f9cc
--- /dev/null
+++ b/tests/bpu_top/env/bpu_agent.py
@@ -0,0 +1,514 @@
+#from mlvp import Bundle, Signals
+from mlvp import *
+import mlvp
+
+from config import *
+import os
+os.sys.path.append(TESTS_PATH)
+os.sys.path.append(DUT_PATH)
+
+from UT_Predictor import *
+import random
+
+ENV_PATH = os.path.dirname(os.path.abspath(__file__))+"/../"
+os.sys.path.append(ENV_PATH)
+
+from mlvp.agent import *
+from env.bpu_bundle import *
+
+###########################################################################################
+#################################################### Agent ################################
+###########################################################################################
+
+class SubPrediCtrlAgent(Agent):
+	#Self-define var
+	en_dict = {
+		'ubtb_en'	: 1,
+		'btb_en'	: 1,
+		'tage_en'	: 1,
+		'sc_en'		: 1,
+		'ras_en'	: 1
+	}
+
+	def __init__(self, bundle: SubPrediCtrlBundle):
+		super().__init__(bundle.step)
+		self.bundle = bundle
+
+	#Self-define func
+	@driver_method()
+	async def reset(self, step=1, reset_vector=0x1000):
+		self.bundle.set_all(0)
+		self.bundle.reset.value = 1
+		self.bundle.io_reset_vector.value = reset_vector
+		await self.bundle.step(step)
+		self.bundle.reset.value = 0
+		self.bundle.io_bpu_to_ftq_resp_ready.value = 1
+
+	@driver_method()
+	async def set_sub_predic_ctrl_en(self, en_dict: dict = en_dict):
+#	async def set_sub_predic_ctrl_en(self,dut, en_dict: dict):
+		print("set_sub_predic_ctrl_en Begin exec")
+#		mlvp.start_clock(dut)		
+
+		self.bundle.io_ctrl_ubtb_enable.value 	= en_dict['ubtb_en']
+		self.bundle.io_ctrl_btb_enable.value 	= en_dict['btb_en']
+		self.bundle.io_ctrl_tage_enable.value 	= en_dict['tage_en']
+		self.bundle.io_ctrl_sc_enable.value 	= en_dict['sc_en']
+		self.bundle.io_ctrl_ras_enable.value 	= en_dict['ras_en']
+		# why the clock is sync with DUT's clock
+		await self.bundle.step()
+
+## 2 Can't use monitor_method
+	@monitor_method()
+	async def mon_ubtb_enable(self):
+		if self.bundle.io_ctrl_ubtb_enable.value > 0:
+			print(self.bundle.io_ctrl_ubtb_enable.value)
+			return self.bundle.as_dict()
+
+## update_FTB_entry Signals
+class Ftq2BpuUpdateFtbEntryAgent(Agent):
+	#Self-define var
+	update_ftb_entry_dict = {
+		'ftb_entry_valid'	: 1,
+		'tailSlot_valid'	: 1,
+		'tailSlot_tarStat'	: 0b10,
+		'tailSlot_sharing'	: 1,
+		'tailSlot_offset'	: 0b0100,
+		'tailSlot_lower'	: 0x20,
+		'pftAddr'			: 0b1000,
+		'may_be_rvi_call'	: 1,
+		'isRet'				: 1,
+		'isJalr'			: 1,
+		'isCall'			: 1,
+		'carry'				: 1,
+		'always_taken_0'	: 1,
+		'always_taken_1'	: 1,
+
+		'brSlots_0_valid'	: 1,
+		'brSlots_0_tarStat' : 0b10,
+		'brSlots_0_sharing'	: 1,
+		'brSlots_0_offset'	: 0b0100,
+		'brSlots_0_lower'	: 0x200
+	}
+
+	def __init__(self,bundle: Ftq2BpuUpdateFtbEntryBundle):
+		super().__init__(bundle.step)
+		self.bundle = bundle
+	
+	@driver_method()
+	async def reset(self, step=1, reset_vector=0x1000):
+		self.bundle.set_all(0)
+		self.bundle.reset.value = 1
+		self.bundle.io_reset_vector.value = reset_vector
+		await self.bundle.step(step)
+		self.bundle.reset.value = 0
+		self.bundle.io_bpu_to_ftq_resp_ready.value = 1
+
+	@driver_method()
+	async def set_update_ftb_entry_value(self, update_pc = 0x1280, update_ftb_entry_dict: dict = update_ftb_entry_dict):
+		#demo update_ftb_entry_dict
+		self.bundle.io_ftq_to_bpu_update_valid.value 						= 1
+		self.bundle.io_ftq_to_bpu_update_bits_pc.value 						= update_pc
+
+		self.bundle.io_ftq_to_bpu_update_bits_ftb_entry_valid.value 			= update_ftb_entry_dict['ftb_entry_valid']
+		self.bundle.io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid.value	= update_ftb_entry_dict['tailSlot_valid']
+		self.bundle.io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset.value	= update_ftb_entry_dict['tailSlot_offset']
+		self.bundle.io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower.value	= update_ftb_entry_dict['tailSlot_lower']
+		self.bundle.io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat.value	= update_ftb_entry_dict['tailSlot_tarStat']
+		self.bundle.io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing.value	= update_ftb_entry_dict['tailSlot_sharing']
+
+		self.bundle.io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid.value	= update_ftb_entry_dict['brSlots_0_valid']
+		self.bundle.io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset.value	= update_ftb_entry_dict['brSlots_0_offset']
+		self.bundle.io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower.value	= update_ftb_entry_dict['brSlots_0_lower']
+		self.bundle.io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing.value	= update_ftb_entry_dict['brSlots_0_sharing']
+		self.bundle.io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat.value	= update_ftb_entry_dict['brSlots_0_tarStat']
+
+		self.bundle.io_ftq_to_bpu_update_bits_ftb_entry_pftAddr.value		= update_ftb_entry_dict['pftAddr']
+		self.bundle.io_ftq_to_bpu_update_bits_ftb_entry_carry.value			= update_ftb_entry_dict['carry']
+		self.bundle.io_ftq_to_bpu_update_bits_ftb_entry_isCall.value		= update_ftb_entry_dict['isCall']
+		self.bundle.io_ftq_to_bpu_update_bits_ftb_entry_isRet.value			= update_ftb_entry_dict['isRet']
+		self.bundle.io_ftq_to_bpu_update_bits_ftb_entry_isJalr.value		= update_ftb_entry_dict['isJalr']
+		self.bundle.io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call.value = update_ftb_entry_dict['may_be_rvi_call']
+		self.bundle.io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0.value= update_ftb_entry_dict['always_taken_0']
+		self.bundle.io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1.value= update_ftb_entry_dict['always_taken_1']
+		await self.bundle.step(1)
+		self.bundle.set_all(0)
+		self.bundle.io_bpu_to_ftq_resp_ready.value = 1
+
+	#@driver_method()
+	#async def set_update_valid_and_pc(self, update_valid = 1, update_bits_pc = 0x2000):
+	#	self.bundle.io_ftq_to_bpu_update_valid.value 	= update_valid
+	#	self.bundle.io_ftq_to_bpu_update_bits_pc.value 	= update_bits_pc
+	#	await self.bundle.step(1)
+	#	self.bundle.io_ftq_to_bpu_update_valid.value 	= 0 
+	#	self.bundle.io_ftq_to_bpu_update_bits_pc.value	= 0
+
+class Ftq2BpuUpdateOtherAgent(Agent):
+	## Varia
+	update_other_dict = {
+		'cfi_idx_valid'		: 1,
+		'cfi_idx_bits'		: 0b1000,
+		'br_taken_mask_0'	: 1,
+		'br_taken_mask_1'	: 1,
+		'jmp_taken'			: 1,
+		'mispred_mask_0'	: 1,
+		'mispred_mask_1'	: 1,
+		'mispred_mask_2'	: 1,
+		'old_entry'			: 1,
+		'meta'				: 1,
+		'full_target'		: 1
+	}
+	##__init__
+	def __init__(self,bundle: Ftq2BpuUpdateOtherBundle):
+		super().__init__(bundle.step)
+		self.bundle = bundle
+
+	@driver_method()
+	async def reset(self, step=1, reset_vector=0x1000):
+		self.bundle.set_all(0)
+		self.bundle.reset.value = 1
+		self.bundle.io_reset_vector.value = reset_vector
+		await self.bundle.step(step)
+		self.bundle.reset.value = 0
+		self.bundle.io_bpu_to_ftq_resp_ready.value = 1
+
+	@driver_method()
+	async def set_update_other_value(self,update_pc = 0x1280 ,update_other_dict: dict = update_other_dict ):
+		#demo update_ftb_entry_dict
+		self.bundle.io_ftq_to_bpu_update_valid.value 						= 1
+		self.bundle.io_ftq_to_bpu_update_bits_pc.value 						= update_pc
+	
+		self.bundle.io_ftq_to_bpu_update_bits_cfi_idx_valid.value	= update_other_dict['cfi_idx_valid']
+		self.bundle.io_ftq_to_bpu_update_bits_cfi_idx_bits.value	= update_other_dict['cfi_idx_bits']
+		self.bundle.io_ftq_to_bpu_update_bits_br_taken_mask_0.value	= update_other_dict['br_taken_mask_0']
+		self.bundle.io_ftq_to_bpu_update_bits_br_taken_mask_1.value	= update_other_dict['br_taken_mask_1']
+		self.bundle.io_ftq_to_bpu_update_bits_jmp_taken.value		= update_other_dict['jmp_taken']
+		self.bundle.io_ftq_to_bpu_update_bits_mispred_mask_0.value	= update_other_dict['mispred_mask_0']
+		self.bundle.io_ftq_to_bpu_update_bits_mispred_mask_1.value	= update_other_dict['mispred_mask_1']
+		self.bundle.io_ftq_to_bpu_update_bits_mispred_mask_2.value	= update_other_dict['mispred_mask_2']
+		self.bundle.io_ftq_to_bpu_update_bits_old_entry.value		= update_other_dict['old_entry']
+		self.bundle.io_ftq_to_bpu_update_bits_meta.value			= update_other_dict['meta']
+		self.bundle.io_ftq_to_bpu_update_bits_full_target.value		= update_other_dict['full_target']
+		await self.bundle.step(1)
+		self.bundle.set_all(0)
+		self.bundle.io_bpu_to_ftq_resp_ready.value = 1
+
+
+class Ftq2BpuUpdateFoldHistAgent(Agent): 
+	## Varia
+	update_fold_hist_dict = {
+		'folded_hist_1' 	: 0b1111,
+		'folded_hist_2' 	: 0b1111,
+		'folded_hist_3' 	: 0b1111,
+		'folded_hist_4' 	: 0b1111,
+		'folded_hist_5' 	: 0b1111,
+		'folded_hist_6' 	: 0b1111,
+		'folded_hist_7' 	: 0b1111,
+		'folded_hist_8' 	: 0b1111,
+		'folded_hist_9' 	: 0b1111,
+		'folded_hist_10' 	: 0b1011,
+		'folded_hist_11' 	: 0b1011,
+		'folded_hist_12' 	: 0b1011,
+		'folded_hist_13' 	: 0b1011,
+		'folded_hist_14' 	: 0b1011,
+		'folded_hist_15' 	: 0b1011,
+		'folded_hist_16' 	: 0b1011,
+		'folded_hist_17' 	: 0b1011
+	}
+	## Method
+	def __init__(self,bundle: Ftq2BpuUpdateFoldHistBundle):
+		super().__init__(bundle.step)
+		self.bundle = bundle
+	
+	@driver_method()
+	async def reset(self, step=1, reset_vector=0x1000):
+		self.bundle.set_all(0)
+		self.bundle.reset.value = 1
+		self.bundle.io_reset_vector.value = reset_vector
+		await self.bundle.step(step)
+		self.bundle.reset.value = 0
+		self.bundle.io_bpu_to_ftq_resp_ready.value = 1
+
+	@driver_method()
+	async def set_update_fold_hist_value(self, update_pc = 0x1280, hist_dict: dict = update_fold_hist_dict):
+		self.bundle.io_ftq_to_bpu_update_valid.value 						= 1
+		self.bundle.io_ftq_to_bpu_update_bits_pc.value 						= update_pc
+
+		self.bundle.io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist.value 	= hist_dict['folded_hist_17']
+		self.bundle.io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist.value 	= hist_dict['folded_hist_16']
+		self.bundle.io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist.value 	= hist_dict['folded_hist_15']
+		self.bundle.io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist.value 	= hist_dict['folded_hist_14']
+		self.bundle.io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist.value 	= hist_dict['folded_hist_13']
+		self.bundle.io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist.value 	= hist_dict['folded_hist_12']
+		self.bundle.io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist.value 	= hist_dict['folded_hist_11']
+		self.bundle.io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist.value 	= hist_dict['folded_hist_10']
+		self.bundle.io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist.value 	= hist_dict['folded_hist_9']
+		self.bundle.io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist.value 	= hist_dict['folded_hist_8']
+		self.bundle.io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist.value 	= hist_dict['folded_hist_7']
+		self.bundle.io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist.value 	= hist_dict['folded_hist_6']
+		self.bundle.io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist.value 	= hist_dict['folded_hist_5']
+		self.bundle.io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist.value 	= hist_dict['folded_hist_4']
+		self.bundle.io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist.value 	= hist_dict['folded_hist_3']
+		self.bundle.io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist.value 	= hist_dict['folded_hist_2']
+		self.bundle.io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist.value 	= hist_dict['folded_hist_1']
+		await self.bundle.step(1)
+		self.bundle.set_all(0)
+		self.bundle.io_bpu_to_ftq_resp_ready.value = 1
+	
+
+class Ftq2BpuRedirectOtherAgent(Agent): 
+	## Varia 
+	rediretc_ohter_dict = {
+		'level'					: 1,
+		'cfiUpdate_pc'			: 0x1280,
+		'cfiUpdate_pd_isRVC'	: 1,
+		'cfiUpdate_pd_isCall'	: 1,
+		'cfiUpdate_pd_isRet'	: 1,
+		'cfiUpdate_ssp'			: 1,
+		'cfiUpdate_sctr'		: 1,
+		'cfiUpdate_TOSW_flag'	: 1,
+		'cfiUpdate_TOSW_value'	: 1,
+		'cfiUpdate_TOSR_flag'	: 1,
+		'cfiUpdate_TOSR_value'	: 1,
+		'cfiUpdate_NOS_flag'	: 1,
+		'cfiUpdate_NOS_value'	: 1,
+
+		'cfiUpdate_lastBrNumOH'	: 1, 
+		'cfiUpdate_histPtr_flag': 1, 
+		'cfiUpdate_histPtr_value':1, 
+		'cfiUpdate_target'		: 1,
+		'cfiUpdate_taken'		: 1,
+		'cfiUpdate_shift'		: 1,
+		'cfiUpdate_addIntoHist'	: 1
+	}
+
+	## Method
+	def __init__(self,bundle: Ftq2BpuRedirectOtherBundle):
+		super().__init__(bundle.step)
+		self.bundle = bundle
+	
+	@driver_method()
+	async def reset(self, step=1, reset_vector=0x1000):
+		self.bundle.set_all(0)
+		self.bundle.reset.value = 1
+		self.bundle.io_reset_vector.value = reset_vector
+		await self.bundle.step(step)
+		self.bundle.reset.value = 0
+		self.bundle.io_bpu_to_ftq_resp_ready.value = 1
+
+	@driver_method()
+	async def set_redirect_other_value(self, rediretc_ohter_dict: dict = rediretc_ohter_dict):
+		self.bundle.io_ftq_to_bpu_redirect_valid.value			= 1
+
+		self.bundle.io_ftq_to_bpu_redirect_bits_level.value					= rediretc_ohter_dict['level']
+		self.bundle.io_ftq_to_bpu_redirect_bits_cfiUpdate_pc.value			= rediretc_ohter_dict['cfiUpdate_pc']
+		self.bundle.io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC.value	= rediretc_ohter_dict['cfiUpdate_pd_isRVC']
+		self.bundle.io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall.value	= rediretc_ohter_dict['cfiUpdate_pd_isCall']
+		self.bundle.io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet.value	= rediretc_ohter_dict['cfiUpdate_pd_isRet']
+		self.bundle.io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp.value			= rediretc_ohter_dict['cfiUpdate_ssp']
+		self.bundle.io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr.value		= rediretc_ohter_dict['cfiUpdate_sctr']
+		self.bundle.io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag.value	= rediretc_ohter_dict['cfiUpdate_TOSW_flag']
+		self.bundle.io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value.value	= rediretc_ohter_dict['cfiUpdate_TOSW_value']
+		self.bundle.io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag.value	= rediretc_ohter_dict['cfiUpdate_TOSR_flag']
+		self.bundle.io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value.value	= rediretc_ohter_dict['cfiUpdate_TOSR_value']
+		self.bundle.io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag.value	= rediretc_ohter_dict['cfiUpdate_NOS_flag']
+		self.bundle.io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value.value	= rediretc_ohter_dict['cfiUpdate_NOS_value']
+
+		self.bundle.io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH.value	= rediretc_ohter_dict['cfiUpdate_lastBrNumOH']
+		self.bundle.io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag.value= rediretc_ohter_dict['cfiUpdate_histPtr_flag']
+		self.bundle.io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value.value=rediretc_ohter_dict['cfiUpdate_histPtr_value']
+		self.bundle.io_ftq_to_bpu_redirect_bits_cfiUpdate_target.value		= rediretc_ohter_dict['cfiUpdate_target']
+		self.bundle.io_ftq_to_bpu_redirect_bits_cfiUpdate_taken.value		= rediretc_ohter_dict['cfiUpdate_taken']
+		self.bundle.io_ftq_to_bpu_redirect_bits_cfiUpdate_shift.value		= rediretc_ohter_dict['cfiUpdate_shift']
+		self.bundle.io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist.value	= rediretc_ohter_dict['cfiUpdate_addIntoHist']
+		await self.bundle.step(1)
+		self.bundle.set_all(0)
+		self.bundle.io_bpu_to_ftq_resp_ready.value = 1
+
+
+class Ftq2BpuRedirectFoldHistAgent(Agent): 
+	## Varia 
+	redirect_fold_hist_dict = {
+		'cfiUpdate_folded_hist_0'	: 0b100,
+		'cfiUpdate_folded_hist_1'	: 0b100,
+		'cfiUpdate_folded_hist_2'	: 0b100,
+		'cfiUpdate_folded_hist_3'	: 0b100,
+		'cfiUpdate_folded_hist_4'	: 0b100,
+		'cfiUpdate_folded_hist_5'	: 0b100,
+		'cfiUpdate_folded_hist_6'	: 0b100,
+		'cfiUpdate_folded_hist_7'	: 0b100,
+		'cfiUpdate_folded_hist_8'	: 0b100,
+		'cfiUpdate_folded_hist_9'	: 0b100,
+
+		'cfiUpdate_folded_hist_10': 0b100,
+		'cfiUpdate_folded_hist_11': 0b100,
+		'cfiUpdate_folded_hist_12': 0b100,
+		'cfiUpdate_folded_hist_13': 0b100,
+		'cfiUpdate_folded_hist_14': 0b100,
+		'cfiUpdate_folded_hist_15': 0b100,
+		'cfiUpdate_folded_hist_16': 0b100,
+		'cfiUpdate_folded_hist_17': 0b100
+	}
+
+	## Method
+	def __init__(self,bundle: Ftq2BpuRedirectFoldHistBundle):
+		super().__init__(bundle.step)
+		self.bundle = bundle
+	
+	@driver_method()
+	async def reset(self, step=1, reset_vector=0x1000):
+		self.bundle.set_all(0)
+		self.bundle.reset.value = 1
+		self.bundle.io_reset_vector.value = reset_vector
+		await self.bundle.step(step)
+		self.bundle.reset.value = 0
+		self.bundle.io_bpu_to_ftq_resp_ready.value = 1
+
+	@driver_method()
+	async def set_redirect_fold_hist_value(self, fold_hist_dict: dict = redirect_fold_hist_dict):
+		self.bundle.io_ftq_to_bpu_redirect_valid.value	= 1
+
+		self.bundle.io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist.value 	= fold_hist_dict['cfiUpdate_folded_hist_17']
+		self.bundle.io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist.value 	= fold_hist_dict['cfiUpdate_folded_hist_16']
+		self.bundle.io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist.value 	= fold_hist_dict['cfiUpdate_folded_hist_15']
+		self.bundle.io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist.value 	= fold_hist_dict['cfiUpdate_folded_hist_14']
+		self.bundle.io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist.value 	= fold_hist_dict['cfiUpdate_folded_hist_13']
+		self.bundle.io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist.value 	= fold_hist_dict['cfiUpdate_folded_hist_12']
+		self.bundle.io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist.value 	= fold_hist_dict['cfiUpdate_folded_hist_11']
+		self.bundle.io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist.value 	= fold_hist_dict['cfiUpdate_folded_hist_10']
+		self.bundle.io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist.value		= fold_hist_dict['cfiUpdate_folded_hist_9']
+		self.bundle.io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist.value		= fold_hist_dict['cfiUpdate_folded_hist_8']
+		self.bundle.io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist.value		= fold_hist_dict['cfiUpdate_folded_hist_7']
+		self.bundle.io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist.value		= fold_hist_dict['cfiUpdate_folded_hist_6']
+		self.bundle.io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist.value		= fold_hist_dict['cfiUpdate_folded_hist_5']
+		self.bundle.io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist.value		= fold_hist_dict['cfiUpdate_folded_hist_4']
+		self.bundle.io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist.value		= fold_hist_dict['cfiUpdate_folded_hist_3']
+		self.bundle.io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist.value		= fold_hist_dict['cfiUpdate_folded_hist_2']
+		self.bundle.io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist.value		= fold_hist_dict['cfiUpdate_folded_hist_1']
+		self.bundle.io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist.value		= fold_hist_dict['cfiUpdate_folded_hist_0']
+		await self.bundle.step(1)
+		self.bundle.set_all(0)
+		self.bundle.io_bpu_to_ftq_resp_ready.value = 1
+		
+
+class Ftq2BpuRedirectAfhobAgent(Agent): 
+	## Varia 
+	redirect_afhob_dict = {
+		'afhob_0_bits_0'	: 0b1,
+		'afhob_0_bits_1'	: 0b1,
+		'afhob_0_bits_2'	: 0b1,
+		'afhob_0_bits_3'	: 0b1,
+		'afhob_1_bits_0'	: 0b1,
+		'afhob_1_bits_1'	: 0b1,
+		'afhob_1_bits_2'	: 0b1,
+		'afhob_1_bits_3'	: 0b1,
+		'afhob_2_bits_0'	: 0b1,
+		'afhob_2_bits_1'	: 0b1,
+		'afhob_2_bits_2'	: 0b1,
+		'afhob_2_bits_3'	: 0b1,
+		'afhob_3_bits_0'	: 0b1,
+		'afhob_3_bits_1'	: 0b1,
+		'afhob_3_bits_2'	: 0b1,
+		'afhob_3_bits_3'	: 0b1,
+		'afhob_4_bits_0'	: 0b1,
+		'afhob_4_bits_1'	: 0b1,
+		'afhob_4_bits_2'	: 0b1,
+		'afhob_5_bits_0'	: 0b1,
+		'afhob_5_bits_1'	: 0b1,
+		'afhob_5_bits_2'	: 0b1,
+		'afhob_5_bits_3'	: 0b1
+	}
+
+	## Method
+	def __init__(self,bundle: Ftq2BpuRedirectAfhobBundle):
+		super().__init__(bundle.step)
+		self.bundle = bundle
+	
+	@driver_method()
+	async def reset(self, step=1, reset_vector=0x1000):
+		self.bundle.set_all(0)
+		self.bundle.reset.value = 1
+		self.bundle.io_reset_vector.value = reset_vector
+		await self.bundle.step(step)
+		self.bundle.reset.value = 0
+		self.bundle.io_bpu_to_ftq_resp_ready.value = 1
+
+	@driver_method()
+	async def set_redirect_afhob_value(self, afhob_dict: dict = redirect_afhob_dict):
+		self.bundle.io_ftq_to_bpu_redirect_valid.value	= 1
+
+		self.bundle.io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0.value	= afhob_dict['afhob_5_bits_0']
+		self.bundle.io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1.value	= afhob_dict['afhob_5_bits_1']
+		self.bundle.io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2.value	= afhob_dict['afhob_5_bits_2']
+		self.bundle.io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3.value	= afhob_dict['afhob_5_bits_3']
+		self.bundle.io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0.value	= afhob_dict['afhob_4_bits_0']
+		self.bundle.io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1.value	= afhob_dict['afhob_4_bits_1']
+		self.bundle.io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2.value	= afhob_dict['afhob_4_bits_2']
+		self.bundle.io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0.value	= afhob_dict['afhob_3_bits_0']
+		self.bundle.io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1.value	= afhob_dict['afhob_3_bits_1']
+		self.bundle.io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2.value	= afhob_dict['afhob_3_bits_2']
+		self.bundle.io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3.value	= afhob_dict['afhob_3_bits_3']
+		self.bundle.io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0.value	= afhob_dict['afhob_2_bits_0']
+		self.bundle.io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1.value	= afhob_dict['afhob_2_bits_1']
+		self.bundle.io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2.value	= afhob_dict['afhob_2_bits_2']
+		self.bundle.io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3.value	= afhob_dict['afhob_2_bits_3']
+		self.bundle.io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0.value	= afhob_dict['afhob_1_bits_0']
+		self.bundle.io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1.value	= afhob_dict['afhob_1_bits_1']
+		self.bundle.io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2.value	= afhob_dict['afhob_1_bits_2']
+		self.bundle.io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3.value	= afhob_dict['afhob_1_bits_3']
+		self.bundle.io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0.value	= afhob_dict['afhob_0_bits_0']
+		self.bundle.io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1.value	= afhob_dict['afhob_0_bits_1']
+		self.bundle.io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2.value	= afhob_dict['afhob_0_bits_2']
+		self.bundle.io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3.value	= afhob_dict['afhob_0_bits_3']
+		await self.bundle.step(1)
+		self.bundle.set_all(0)
+		self.bundle.io_bpu_to_ftq_resp_ready.value = 1
+
+
+################################  Only for agent_test#################0
+async def agent_test():
+	sub_predic_ctrl_bundle = SubPrediCtrlBundle()
+	dut: DUTPredictor = DUTPredictor()
+	sub_predic_ctrl_bundle.bind(dut)
+	
+	sub_predi_ctrl_agent = SubPrediCtrlAgent(sub_predic_ctrl_bundle)
+	
+	enable_dict = {
+		'ubtb_en' 	: 1,	
+		'btb_en'	: 1,
+		'tage_en'	: 1,
+		'sc_en'		: 1,
+		'ras_en'	: 1
+	}
+#	print(enable_dict)
+	
+## 1 Can't use driver_method
+	mlvp.run(sub_predi_ctrl_agent.set_sub_predic_ctrl_en(dut, enable_dict))
+	
+	spec_info_dict = {
+		'spec_info_folded_hist_hist_17_folded_hist' : 1,
+		'spec_info_folded_hist_hist_16_folded_hist' : 1,
+		'spec_info_folded_hist_hist_15_folded_hist' : 1,
+		'spec_info_folded_hist_hist_14_folded_hist' : 1,
+		'spec_info_folded_hist_hist_13_folded_hist' : 1,
+		'spec_info_folded_hist_hist_12_folded_hist' : 1,
+		'spec_info_folded_hist_hist_11_folded_hist' : 1,
+		'spec_info_folded_hist_hist_10_folded_hist' : 1,
+		'spec_info_folded_hist_hist_9_folded_hist'  : 1, 
+		'spec_info_folded_hist_hist_8_folded_hist'  : 1, 
+		'spec_info_folded_hist_hist_7_folded_hist'  : 1, 
+		'spec_info_folded_hist_hist_6_folded_hist'  : 1, 
+		'spec_info_folded_hist_hist_5_folded_hist'  : 1, 
+		'spec_info_folded_hist_hist_4_folded_hist'  : 1, 
+		'spec_info_folded_hist_hist_3_folded_hist'  : 1, 
+		'spec_info_folded_hist_hist_2_folded_hist'  : 1, 
+		'spec_info_folded_hist_hist_1_folded_hist'  : 1 
+	}
+
+	spec_info_dict['spec_info_folded_hist_hist_1_folded_hist'] = 2
+	print(spec_info_dict['spec_info_folded_hist_hist_1_folded_hist'])
+	
+
+if __name__ == "__main__":
+	print("bpu_agent exec!")
+#	mlvp.run(agent_test())
diff --git a/tests/bpu_top/env/bpu_bundle.py b/tests/bpu_top/env/bpu_bundle.py
new file mode 100644
index 0000000..7b55a74
--- /dev/null
+++ b/tests/bpu_top/env/bpu_bundle.py
@@ -0,0 +1,372 @@
+#from mlvp import Bundle, Signals
+from mlvp import *
+import mlvp
+
+from config import *
+import os
+os.sys.path.append(TESTS_PATH)
+os.sys.path.append(DUT_PATH)
+
+from UT_Predictor import *
+import random
+
+#Input Bundle
+class SubPrediCtrlBundle(Bundle): 
+	reset 					= Signal()
+	io_reset_vector 		= Signal()
+	io_bpu_to_ftq_resp_ready= Signal()
+
+	io_ctrl_ubtb_enable 	= Signal()
+	io_ctrl_btb_enable 		= Signal()
+	io_ctrl_tage_enable 	= Signal()
+	io_ctrl_sc_enable 		= Signal()
+	io_ctrl_ras_enable 		= Signal()
+
+
+class Ftq2BpuUpdateFtbEntryBundle(Bundle):
+	reset 					= Signal()
+	io_reset_vector 		= Signal()
+	io_bpu_to_ftq_resp_ready= Signal()
+
+	io_ftq_to_bpu_update_valid 								= Signal()
+	io_ftq_to_bpu_update_bits_pc 							= Signal()
+
+	io_ftq_to_bpu_update_bits_ftb_entry_valid 				= Signal()
+	io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset	= Signal()
+	io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower		= Signal()
+	io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat	= Signal()
+	io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing	= Signal()
+	io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid		= Signal()
+	io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset		= Signal()
+	io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower		= Signal()
+	io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat	= Signal()
+	io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing	= Signal()
+	io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid		= Signal()
+	io_ftq_to_bpu_update_bits_ftb_entry_pftAddr				= Signal()
+	io_ftq_to_bpu_update_bits_ftb_entry_carry				= Signal()
+	io_ftq_to_bpu_update_bits_ftb_entry_isCall				= Signal()
+	io_ftq_to_bpu_update_bits_ftb_entry_isRet				= Signal()
+	io_ftq_to_bpu_update_bits_ftb_entry_isJalr				= Signal()
+	io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call= Signal()
+	io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0		= Signal()
+	io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1		= Signal()
+
+class Ftq2BpuUpdateOtherBundle(Bundle):
+	reset 					= Signal()
+	io_reset_vector 		= Signal()
+	io_bpu_to_ftq_resp_ready= Signal()
+
+	io_ftq_to_bpu_update_valid 					= Signal()
+	io_ftq_to_bpu_update_bits_pc 				= Signal()
+
+	io_ftq_to_bpu_update_bits_cfi_idx_valid		= Signal()
+	io_ftq_to_bpu_update_bits_cfi_idx_bits		= Signal()
+	io_ftq_to_bpu_update_bits_br_taken_mask_0	= Signal()
+	io_ftq_to_bpu_update_bits_br_taken_mask_1	= Signal()
+	io_ftq_to_bpu_update_bits_jmp_taken			= Signal()
+	io_ftq_to_bpu_update_bits_mispred_mask_0	= Signal()
+	io_ftq_to_bpu_update_bits_mispred_mask_1	= Signal()
+	io_ftq_to_bpu_update_bits_mispred_mask_2	= Signal()
+	io_ftq_to_bpu_update_bits_old_entry			= Signal()
+	io_ftq_to_bpu_update_bits_meta				= Signal()
+	io_ftq_to_bpu_update_bits_full_target		= Signal()
+
+#Input: update signals
+class Ftq2BpuUpdateFoldHistBundle(Bundle):
+	reset 					= Signal()
+	io_reset_vector 		= Signal()
+	io_bpu_to_ftq_resp_ready= Signal()
+
+	io_ftq_to_bpu_update_valid 					= Signal()
+	io_ftq_to_bpu_update_bits_pc 				= Signal()
+
+	io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist = Signal()
+	io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist = Signal()
+	io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist = Signal()
+	io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist = Signal()
+	io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist = Signal()
+	io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist = Signal()
+	io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist = Signal()
+	io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist = Signal()
+	io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist 	= Signal()
+	io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist 	= Signal()
+	io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist 	= Signal()
+	io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist 	= Signal()
+	io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist 	= Signal()
+	io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist 	= Signal()
+	io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist 	= Signal()
+	io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist 	= Signal()
+	io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist 	= Signal()
+
+class Ftq2BpuRedirectOtherBundle(Bundle):
+	reset 						= Signal()
+	io_reset_vector 			= Signal()
+	io_bpu_to_ftq_resp_ready	= Signal()
+
+	io_ftq_to_bpu_redirect_valid					= Signal()
+	io_ftq_to_bpu_redirect_bits_level				= Signal()
+	io_ftq_to_bpu_redirect_bits_cfiUpdate_pc		= Signal()
+	io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC	= Signal()
+	io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall	= Signal()
+	io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet	= Signal()
+	io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp		= Signal()
+	io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr		= Signal()
+	io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag	= Signal()
+	io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value= Signal()
+	io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag	= Signal()
+	io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value= Signal()
+	io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag	= Signal()
+	io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value	= Signal()
+
+	io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH	= Signal()
+	io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag 	= Signal()
+	io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value	= Signal()
+	io_ftq_to_bpu_redirect_bits_cfiUpdate_target		= Signal()
+	io_ftq_to_bpu_redirect_bits_cfiUpdate_taken			= Signal()
+	io_ftq_to_bpu_redirect_bits_cfiUpdate_shift			= Signal()
+	io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist	= Signal()
+
+class Ftq2BpuRedirectFoldHistBundle(Bundle):
+	reset 						= Signal()
+	io_reset_vector 			= Signal()
+	io_bpu_to_ftq_resp_ready	= Signal()
+
+	io_ftq_to_bpu_redirect_valid	= Signal()
+
+	io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist 	= Signal()
+	io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist 	= Signal()
+	io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist 	= Signal()
+	io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist 	= Signal()
+	io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist 	= Signal()
+	io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist 	= Signal()
+	io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist 	= Signal()
+	io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist 	= Signal()
+	io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist	= Signal()
+	io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist	= Signal()
+	io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist	= Signal()
+	io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist	= Signal()
+	io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist	= Signal()
+	io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist	= Signal()
+	io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist	= Signal()
+	io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist	= Signal()
+	io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist	= Signal()
+	io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist	= Signal()
+	
+class Ftq2BpuRedirectAfhobBundle(Bundle):
+	reset 						= Signal()
+	io_reset_vector 			= Signal()
+	io_bpu_to_ftq_resp_ready	= Signal()
+
+	io_ftq_to_bpu_redirect_valid= Signal()
+
+	io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0	= Signal()
+	io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1	= Signal()
+	io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2	= Signal()
+	io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3	= Signal()
+	io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0	= Signal()
+	io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1	= Signal()
+	io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2	= Signal()
+	io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0	= Signal()
+	io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1	= Signal()
+	io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2	= Signal()
+	io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3	= Signal()
+	io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0	= Signal()
+	io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1	= Signal()
+	io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2	= Signal()
+	io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3	= Signal()
+	io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0	= Signal()
+	io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1	= Signal()
+	io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2	= Signal()
+	io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3	= Signal()
+	io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0	= Signal()
+	io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1	= Signal()
+	io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2	= Signal()
+	io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3	= Signal()
+
+
+
+
+################################################Output Ports #######################################
+class Bpu2FtqRespS1Bundle(Bundle):
+	io_bpu_to_ftq_resp_valid 								= Signal()
+	io_bpu_to_ftq_resp_bits_s1_pc_3 						= Signal()
+	io_bpu_to_ftq_resp_bits_s1_full_pred_3_br_taken_mask_0	= Signal()
+	io_bpu_to_ftq_resp_bits_s1_full_pred_3_br_taken_mask_1	= Signal()
+	io_bpu_to_ftq_resp_bits_s1_full_pred_3_slot_valids_0	= Signal()
+	io_bpu_to_ftq_resp_bits_s1_full_pred_3_slot_valids_1	= Signal()
+	io_bpu_to_ftq_resp_bits_s1_full_pred_3_targets_0		= Signal()
+	io_bpu_to_ftq_resp_bits_s1_full_pred_3_targets_1		= Signal()
+	io_bpu_to_ftq_resp_bits_s1_full_pred_3_offsets_0		= Signal()
+	io_bpu_to_ftq_resp_bits_s1_full_pred_3_offsets_1		= Signal()
+	io_bpu_to_ftq_resp_bits_s1_full_pred_3_fallThroughAddr	= Signal()
+	io_bpu_to_ftq_resp_bits_s1_full_pred_3_fallThroughErr	= Signal()
+	io_bpu_to_ftq_resp_bits_s1_full_pred_3_is_br_sharing	= Signal()
+	io_bpu_to_ftq_resp_bits_s1_full_pred_3_hit				= Signal()
+	
+class Bpu2FtqRespS2Bundle(Bundle):
+	io_bpu_to_ftq_resp_valid 					= Signal()
+	io_bpu_to_ftq_resp_bits_s2_pc_3				= Signal()
+	io_bpu_to_ftq_resp_bits_s2_valid_3 			= Signal()
+	io_bpu_to_ftq_resp_bits_s2_hasRedirect_3	= Signal()
+	io_bpu_to_ftq_resp_bits_s2_ftq_idx_flag		= Signal()
+	io_bpu_to_ftq_resp_bits_s2_ftq_idx_value	= Signal()
+	io_bpu_to_ftq_resp_bits_s2_full_pred_3_br_taken_mask_0	= Signal()
+	io_bpu_to_ftq_resp_bits_s2_full_pred_3_br_taken_mask_1	= Signal()
+	io_bpu_to_ftq_resp_bits_s2_full_pred_3_slot_valids_0 	= Signal()
+	io_bpu_to_ftq_resp_bits_s2_full_pred_3_slot_valids_1 	= Signal()
+	io_bpu_to_ftq_resp_bits_s2_full_pred_3_targets_0 		= Signal()
+	io_bpu_to_ftq_resp_bits_s2_full_pred_3_targets_1 		= Signal()
+	io_bpu_to_ftq_resp_bits_s2_full_pred_3_offsets_0 		= Signal()
+	io_bpu_to_ftq_resp_bits_s2_full_pred_3_offsets_1 		= Signal()
+	io_bpu_to_ftq_resp_bits_s2_full_pred_3_fallThroughAddr	= Signal()
+	io_bpu_to_ftq_resp_bits_s2_full_pred_3_fallThroughErr	= Signal()
+	io_bpu_to_ftq_resp_bits_s2_full_pred_3_is_br_sharing	= Signal()
+	io_bpu_to_ftq_resp_bits_s2_full_pred_3_hit				= Signal()
+	
+class Bpu2FtqRespS3Bundle(Bundle):
+	io_bpu_to_ftq_resp_bits_s3_pc_3							= Signal()
+	io_bpu_to_ftq_resp_bits_s3_valid_3						= Signal()
+	io_bpu_to_ftq_resp_bits_s3_hasRedirect_3 				= Signal()
+	io_bpu_to_ftq_resp_bits_s3_ftq_idx_flag					= Signal()
+	io_bpu_to_ftq_resp_bits_s3_ftq_idx_value				= Signal()
+
+	io_bpu_to_ftq_resp_bits_s3_full_pred_3_br_taken_mask_0	= Signal()
+	io_bpu_to_ftq_resp_bits_s3_full_pred_3_br_taken_mask_1	= Signal()
+	io_bpu_to_ftq_resp_bits_s3_full_pred_3_slot_valids_0 	= Signal()
+	io_bpu_to_ftq_resp_bits_s3_full_pred_3_slot_valids_1 	= Signal()
+	io_bpu_to_ftq_resp_bits_s3_full_pred_3_targets_0 		= Signal()
+	io_bpu_to_ftq_resp_bits_s3_full_pred_3_targets_1 		= Signal()
+	io_bpu_to_ftq_resp_bits_s3_full_pred_3_offsets_0 		= Signal()
+	io_bpu_to_ftq_resp_bits_s3_full_pred_3_offsets_1 		= Signal()
+	io_bpu_to_ftq_resp_bits_s3_full_pred_3_fallThroughAddr	= Signal()
+	io_bpu_to_ftq_resp_bits_s3_full_pred_3_fallThroughErr	= Signal()
+	io_bpu_to_ftq_resp_bits_s3_full_pred_3_is_br_sharing	= Signal()
+	io_bpu_to_ftq_resp_bits_s3_full_pred_3_hit				= Signal()
+
+class Bpu2FtqLastStageSpecInfoBundle(Bundle):
+	io_bpu_to_ftq_resp_bits_last_stage_meta	= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_17_folded_hist	= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_16_folded_hist	= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_15_folded_hist	= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_14_folded_hist	= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_13_folded_hist	= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_12_folded_hist	= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_11_folded_hist	= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_10_folded_hist	= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_9_folded_hist		= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_8_folded_hist		= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_7_folded_hist		= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_6_folded_hist		= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_5_folded_hist		= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_4_folded_hist		= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_3_folded_hist		= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_2_folded_hist		= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_1_folded_hist		= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_0_folded_hist		= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_5_bits_0				= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_5_bits_1				= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_5_bits_2				= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_5_bits_3				= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_4_bits_0				= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_4_bits_1				= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_4_bits_2				= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_4_bits_3				= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_3_bits_0				= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_3_bits_1				= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_3_bits_2				= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_3_bits_3				= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_2_bits_0				= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_2_bits_1				= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_2_bits_2				= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_2_bits_3				= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_1_bits_0				= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_1_bits_1				= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_1_bits_2				= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_1_bits_3				= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_0_bits_0				= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_0_bits_1				= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_0_bits_2				= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_0_bits_3				= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_spec_info_lastBrNumOH	= Signal() 
+	io_bpu_to_ftq_resp_bits_last_stage_spec_info_histPtr_flag	= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_spec_info_histPtr_value	= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_spec_info_ssp			= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_spec_info_sctr			= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_spec_info_TOSW_flag		= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_spec_info_TOSW_value		= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_spec_info_TOSR_flag		= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_spec_info_TOSR_value		= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_spec_info_NOS_flag		= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_spec_info_NOS_value		= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_spec_info_topAddr		= Signal()
+
+class Bpu2FtqLastStageSpecInfoBundle(Bundle):
+	io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_valid				= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_brSlots_0_offset	= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_brSlots_0_lower	= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_brSlots_0_tarStat	= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_brSlots_0_sharing	= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_brSlots_0_valid	= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_tailSlot_offset	= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_tailSlot_lower		= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_tailSlot_tarStat	= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_tailSlot_sharing	= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_tailSlot_valid		= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_pftAddr			= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_carry				= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_isCall				= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_isRet				= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_isJalr				= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_last_may_be_rvi_call = Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_always_taken_0		= Signal()
+	io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_always_taken_1		= Signal()
+
+
+
+async def set_sub_predic_ctrl_bundle(dut, sub_predic_ctrl_bundle: SubPrediCtrlBundle):
+	mlvp.start_clock(dut)
+
+	sub_predic_ctrl_bundle.io_ctrl_ubtb_enable.value = 1
+	print(sub_predic_ctrl_bundle.io_ctrl_ubtb_enable.value)
+	await sub_predic_ctrl_bundle.step()
+	print(sub_predic_ctrl_bundle.io_ctrl_ubtb_enable.value)
+
+
+
+if __name__ == "__main__":
+	mlvp.setup_logging(mlvp.INFO)
+
+	sub_predic_ctrl_bundle = SubPrediCtrlBundle.from_prefix()
+	dut: DUTPredictor = DUTPredictor()
+	sub_predic_ctrl_bundle.bind(dut)
+
+	sub_predic_ctrl_bundle.set_write_mode_as_imme()
+
+## 1 set value
+	sub_predic_ctrl_bundle.io_ctrl_ubtb_enable.value = 0
+#	sub_predic_ctrl_bundle.io_ctrl_ubtb_enable = 0
+	print("1xxx", sub_predic_ctrl_bundle.io_ctrl_ubtb_enable)
+
+## 2 access the signal by index
+	sub_predic_ctrl_bundle['io_ctrl_ubtb_enable'].value = 1
+	print(sub_predic_ctrl_bundle.io_ctrl_ubtb_enable)
+
+## 3 set value by set_all()
+	sub_predic_ctrl_bundle.set_all(1)	
+	print("set_all():",sub_predic_ctrl_bundle.io_ctrl_ubtb_enable)	# result is 0
+
+## 4 set value by assign
+	sub_predic_ctrl_bundle.assign({
+		'*'	: 0,
+		'io_ctrl_ubtb_enable' : 1
+	})
+	print("assign():",sub_predic_ctrl_bundle.io_ctrl_ubtb_enable)	# result is 0
+
+## 5 asyncio support
+	mlvp.run(set_sub_predic_ctrl_bundle(dut, sub_predic_ctrl_bundle))
+
+
+#	sub_predic_ctrl_bundle.io_ctrl_ubtb_enable = 1
+#	print(sub_predic_ctrl_bundle.io_ctrl_ubtb_enable)
+#	sub_predic_ctrl_bundle.io_ctrl_btb_enable = 1
+#	print(sub_predic_ctrl_bundle.io_ctrl_btb_enable)
diff --git a/tests/bpu_top/env/bpu_dut.py b/tests/bpu_top/env/bpu_dut.py
new file mode 100644
index 0000000..632fa32
--- /dev/null
+++ b/tests/bpu_top/env/bpu_dut.py
@@ -0,0 +1,27 @@
+import os
+CFG_PATH = os.path.dirname(os.path.abspath(__file__))+"/../"
+os.sys.path.append(CFG_PATH)
+from config import *
+os.sys.path.append(DUT_PATH)
+os.sys.path.append(TESTS_PATH)
+
+from UT_Predictor import *
+import random
+
+import mlvp
+import logging
+import mlvp.funcov as fc
+from mlvp.reporter import *
+
+import asyncio
+
+#do the sub-class extended the DUT
+class bpu_dut(DUTPredictor):
+	def __init__(self, *args, **kwargs):
+		super().__init__(*args, **kwargs)
+		self.InitClock("clock")
+		self.reset.value = 1
+		self.Step(2)
+		self.reset.value = 0
+		self.Step(2)
+
diff --git a/tests/bpu_top/env/bpu_env.py b/tests/bpu_top/env/bpu_env.py
new file mode 100644
index 0000000..8ca5673
--- /dev/null
+++ b/tests/bpu_top/env/bpu_env.py
@@ -0,0 +1,62 @@
+#from mlvp import Bundle, Signals
+from mlvp import *
+import mlvp
+from mlvp.env import *
+
+from config import *
+import os
+os.sys.path.append(TESTS_PATH)
+os.sys.path.append(DUT_PATH)
+
+from UT_Predictor import *
+import random
+
+ENV_PATH = os.path.dirname(os.path.abspath(__file__))+"/../"
+os.sys.path.append(ENV_PATH)
+
+from env.bpu_bundle import *
+from env.bpu_agent import *
+
+class BpuEnv(Env):
+	def __init__(self, SubPrediCtrlBundle, Ftq2BpuUpdateFtbEntryBundle,Ftq2BpuUpdateOtherBundle,
+			  	Ftq2BpuUpdateFoldHistBundle, Ftq2BpuRedirectOtherBundle, Ftq2BpuRedirectFoldHistBundle,
+				Ftq2BpuRedirectAfhobBundle):
+		super().__init__()
+
+		self.sub_predi_ctrl_agent	= SubPrediCtrlAgent(SubPrediCtrlBundle)
+		self.update_ftb_entry_agent = Ftq2BpuUpdateFtbEntryAgent(Ftq2BpuUpdateFtbEntryBundle) 
+		self.update_other_agent		= Ftq2BpuUpdateOtherAgent(Ftq2BpuUpdateOtherBundle)
+		self.update_fold_hist_agent	= Ftq2BpuUpdateFoldHistAgent(Ftq2BpuUpdateFoldHistBundle)
+		self.redirect_other_agent	= Ftq2BpuRedirectOtherAgent(Ftq2BpuRedirectOtherBundle)
+		self.redirect_fold_hist_agent	= Ftq2BpuRedirectFoldHistAgent(Ftq2BpuRedirectFoldHistBundle)
+		self.redirect_afhob_agent	= Ftq2BpuRedirectAfhobAgent(Ftq2BpuRedirectAfhobBundle)
+
+
+
+################################# Only for Test_ENV #####################
+#	async def test_env():
+#		sub_predic_ctrl_bundle 	= SubPrediCtrlBundle()
+#		spec_info_bundle 		= Ftq2BpuUpdateSpecInfoBundle()
+#	
+#		dut: DUTPredictor = DUTPredictor()
+#		sub_predic_ctrl_bundle.bind(dut)
+#		spec_info_bundle.bind(dut)
+#	
+#		bpu_env = BpuEnv(sub_predic_ctrl_bundle, spec_info_bundle)
+#		
+#		#the transaction
+#		enable_dict = {
+#			'ubtb_en' 	: 1,	
+#			'btb_en'	: 1,
+#			'tage_en'	: 1,
+#			'sc_en'		: 1,
+#			'ras_en'	: 1
+#		}
+#	
+#		await bpu_env.sub_predi_ctrl_agent.set_sub_predic_ctrl_en(dut, enable_dict)
+#	
+#		print("exec bottom!!!")
+
+
+#	if __name__ == "__main__":
+#		mlvp.run(test_env())
diff --git a/tests/bpu_top/env/config.py b/tests/bpu_top/env/config.py
new file mode 100644
index 0000000..5105e63
--- /dev/null
+++ b/tests/bpu_top/env/config.py
@@ -0,0 +1,6 @@
+import os
+ROOT_PATH = os.path.dirname(os.path.abspath(__file__))+"/../../../"
+TESTS_PATH = ROOT_PATH + "tests/"
+DUT_PATH = ROOT_PATH + "out/picker_out_BPUTop/"
+#FTB_PATH = ROOT_PATH + "tests/bpu_top/env/"
+#os.sys.path.append(DUT_PATH)
diff --git a/tests/bpu_top/reports/GLCC_BPU-TOP模块验证报告.pdf b/tests/bpu_top/reports/GLCC_BPU-TOP模块验证报告.pdf
new file mode 100644
index 0000000000000000000000000000000000000000..f92d671b175507ed1f3df298cf332da6922b37de
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diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/CAMTemplate.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/CAMTemplate.sv.func-sort-c.html
new file mode 100644
index 0000000..a23e411
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/CAMTemplate.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/CAMTemplate.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - CAMTemplate.sv<span style="font-size: 80%;"> (<a href="CAMTemplate.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">39</td>
+            <td class="headerCovTableEntry">39</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="CAMTemplate.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/CAMTemplate.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/CAMTemplate.sv.func.html
new file mode 100644
index 0000000..33f9236
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/CAMTemplate.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/CAMTemplate.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - CAMTemplate.sv<span style="font-size: 80%;"> (<a href="CAMTemplate.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">39</td>
+            <td class="headerCovTableEntry">39</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="CAMTemplate.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/CAMTemplate.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/CAMTemplate.sv.gcov.html
new file mode 100644
index 0000000..2ac4a15
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/CAMTemplate.sv.gcov.html
@@ -0,0 +1,212 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/CAMTemplate.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - CAMTemplate.sv<span style="font-size: 80%;"> (source / <a href="CAMTemplate.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">39</td>
+            <td class="headerCovTableEntry">39</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : module CAMTemplate(</a>
+<a name="59"><span class="lineNum">      59 </span><span class="lineCov">     127786 :   input        clock,</span></a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">        261 :   input  [8:0] io_r_req_0_idx,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">        539 :   output       io_r_resp_0_0,</span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">        466 :   output       io_r_resp_0_1,</span></a>
+<a name="63"><span class="lineNum">      63 </span><span class="lineCov">        490 :   output       io_r_resp_0_2,</span></a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">        455 :   output       io_r_resp_0_3,</span></a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">        493 :   output       io_r_resp_0_4,</span></a>
+<a name="66"><span class="lineNum">      66 </span><span class="lineCov">        472 :   output       io_r_resp_0_5,</span></a>
+<a name="67"><span class="lineNum">      67 </span><span class="lineCov">        439 :   output       io_r_resp_0_6,</span></a>
+<a name="68"><span class="lineNum">      68 </span><span class="lineCov">        473 :   output       io_r_resp_0_7,</span></a>
+<a name="69"><span class="lineNum">      69 </span><span class="lineCov">        612 :   input        io_w_valid,</span></a>
+<a name="70"><span class="lineNum">      70 </span><span class="lineCov">        261 :   input  [8:0] io_w_bits_data_idx,</span></a>
+<a name="71"><span class="lineNum">      71 </span><span class="lineCov">       2358 :   input  [2:0] io_w_bits_index</span></a>
+<a name="72"><span class="lineNum">      72 </span>            : );</a>
+<a name="73"><span class="lineNum">      73 </span>            : </a>
+<a name="74"><span class="lineNum">      74 </span><span class="lineCov">       4484 :   reg [8:0] array_0;</span></a>
+<a name="75"><span class="lineNum">      75 </span><span class="lineCov">       4158 :   reg [8:0] array_1;</span></a>
+<a name="76"><span class="lineNum">      76 </span><span class="lineCov">       4152 :   reg [8:0] array_2;</span></a>
+<a name="77"><span class="lineNum">      77 </span><span class="lineCov">       4135 :   reg [8:0] array_3;</span></a>
+<a name="78"><span class="lineNum">      78 </span><span class="lineCov">       4321 :   reg [8:0] array_4;</span></a>
+<a name="79"><span class="lineNum">      79 </span><span class="lineCov">       4222 :   reg [8:0] array_5;</span></a>
+<a name="80"><span class="lineNum">      80 </span><span class="lineCov">       4201 :   reg [8:0] array_6;</span></a>
+<a name="81"><span class="lineNum">      81 </span><span class="lineCov">       4284 :   reg [8:0] array_7;</span></a>
+<a name="82"><span class="lineNum">      82 </span><span class="lineCov">    4086208 :   always @(posedge clock) begin</span></a>
+<a name="83"><span class="lineNum">      83 </span><span class="lineCov">        152 :     if (io_w_valid &amp; io_w_bits_index == 3'h0)</span></a>
+<a name="84"><span class="lineNum">      84 </span><span class="lineCov">         76 :       array_0 &lt;= io_w_bits_data_idx;</span></a>
+<a name="85"><span class="lineNum">      85 </span><span class="lineCov">         22 :     if (io_w_valid &amp; io_w_bits_index == 3'h1)</span></a>
+<a name="86"><span class="lineNum">      86 </span><span class="lineCov">         11 :       array_1 &lt;= io_w_bits_data_idx;</span></a>
+<a name="87"><span class="lineNum">      87 </span><span class="lineCov">         14 :     if (io_w_valid &amp; io_w_bits_index == 3'h2)</span></a>
+<a name="88"><span class="lineNum">      88 </span><span class="lineCov">          7 :       array_2 &lt;= io_w_bits_data_idx;</span></a>
+<a name="89"><span class="lineNum">      89 </span><span class="lineCov">         10 :     if (io_w_valid &amp; io_w_bits_index == 3'h3)</span></a>
+<a name="90"><span class="lineNum">      90 </span><span class="lineCov">          5 :       array_3 &lt;= io_w_bits_data_idx;</span></a>
+<a name="91"><span class="lineNum">      91 </span><span class="lineCov">         30 :     if (io_w_valid &amp; io_w_bits_index == 3'h4)</span></a>
+<a name="92"><span class="lineNum">      92 </span><span class="lineCov">         15 :       array_4 &lt;= io_w_bits_data_idx;</span></a>
+<a name="93"><span class="lineNum">      93 </span><span class="lineCov">         18 :     if (io_w_valid &amp; io_w_bits_index == 3'h5)</span></a>
+<a name="94"><span class="lineNum">      94 </span><span class="lineCov">          9 :       array_5 &lt;= io_w_bits_data_idx;</span></a>
+<a name="95"><span class="lineNum">      95 </span><span class="lineCov">         10 :     if (io_w_valid &amp; io_w_bits_index == 3'h6)</span></a>
+<a name="96"><span class="lineNum">      96 </span><span class="lineCov">          5 :       array_6 &lt;= io_w_bits_data_idx;</span></a>
+<a name="97"><span class="lineNum">      97 </span><span class="lineCov">         20 :     if (io_w_valid &amp; (&amp;io_w_bits_index))</span></a>
+<a name="98"><span class="lineNum">      98 </span><span class="lineCov">         10 :       array_7 &lt;= io_w_bits_data_idx;</span></a>
+<a name="99"><span class="lineNum">      99 </span>            :   end // always @(posedge)</a>
+<a name="100"><span class="lineNum">     100 </span>            :   `ifdef ENABLE_INITIAL_REG_</a>
+<a name="101"><span class="lineNum">     101 </span>            :     `ifdef FIRRTL_BEFORE_INITIAL</a>
+<a name="102"><span class="lineNum">     102 </span>            :       `FIRRTL_BEFORE_INITIAL</a>
+<a name="103"><span class="lineNum">     103 </span>            :     `endif // FIRRTL_BEFORE_INITIAL</a>
+<a name="104"><span class="lineNum">     104 </span>            :     logic [31:0] _RANDOM[0:2];</a>
+<a name="105"><span class="lineNum">     105 </span><span class="lineCov">       1856 :     initial begin</span></a>
+<a name="106"><span class="lineNum">     106 </span>            :       `ifdef INIT_RANDOM_PROLOG_</a>
+<a name="107"><span class="lineNum">     107 </span>            :         `INIT_RANDOM_PROLOG_</a>
+<a name="108"><span class="lineNum">     108 </span>            :       `endif // INIT_RANDOM_PROLOG_</a>
+<a name="109"><span class="lineNum">     109 </span>            :       `ifdef RANDOMIZE_REG_INIT</a>
+<a name="110"><span class="lineNum">     110 </span>            :         for (logic [1:0] i = 2'h0; i &lt; 2'h3; i += 2'h1) begin</a>
+<a name="111"><span class="lineNum">     111 </span>            :           _RANDOM[i] = `RANDOM;</a>
+<a name="112"><span class="lineNum">     112 </span>            :         end</a>
+<a name="113"><span class="lineNum">     113 </span>            :         array_0 = _RANDOM[2'h0][8:0];</a>
+<a name="114"><span class="lineNum">     114 </span>            :         array_1 = _RANDOM[2'h0][17:9];</a>
+<a name="115"><span class="lineNum">     115 </span>            :         array_2 = _RANDOM[2'h0][26:18];</a>
+<a name="116"><span class="lineNum">     116 </span>            :         array_3 = {_RANDOM[2'h0][31:27], _RANDOM[2'h1][3:0]};</a>
+<a name="117"><span class="lineNum">     117 </span>            :         array_4 = _RANDOM[2'h1][12:4];</a>
+<a name="118"><span class="lineNum">     118 </span>            :         array_5 = _RANDOM[2'h1][21:13];</a>
+<a name="119"><span class="lineNum">     119 </span>            :         array_6 = _RANDOM[2'h1][30:22];</a>
+<a name="120"><span class="lineNum">     120 </span>            :         array_7 = {_RANDOM[2'h1][31], _RANDOM[2'h2][7:0]};</a>
+<a name="121"><span class="lineNum">     121 </span>            :       `endif // RANDOMIZE_REG_INIT</a>
+<a name="122"><span class="lineNum">     122 </span>            :     end // initial</a>
+<a name="123"><span class="lineNum">     123 </span>            :     `ifdef FIRRTL_AFTER_INITIAL</a>
+<a name="124"><span class="lineNum">     124 </span>            :       `FIRRTL_AFTER_INITIAL</a>
+<a name="125"><span class="lineNum">     125 </span>            :     `endif // FIRRTL_AFTER_INITIAL</a>
+<a name="126"><span class="lineNum">     126 </span>            :   `endif // ENABLE_INITIAL_REG_</a>
+<a name="127"><span class="lineNum">     127 </span>            :   assign io_r_resp_0_0 = io_r_req_0_idx == array_0;</a>
+<a name="128"><span class="lineNum">     128 </span>            :   assign io_r_resp_0_1 = io_r_req_0_idx == array_1;</a>
+<a name="129"><span class="lineNum">     129 </span>            :   assign io_r_resp_0_2 = io_r_req_0_idx == array_2;</a>
+<a name="130"><span class="lineNum">     130 </span>            :   assign io_r_resp_0_3 = io_r_req_0_idx == array_3;</a>
+<a name="131"><span class="lineNum">     131 </span>            :   assign io_r_resp_0_4 = io_r_req_0_idx == array_4;</a>
+<a name="132"><span class="lineNum">     132 </span>            :   assign io_r_resp_0_5 = io_r_req_0_idx == array_5;</a>
+<a name="133"><span class="lineNum">     133 </span>            :   assign io_r_resp_0_6 = io_r_req_0_idx == array_6;</a>
+<a name="134"><span class="lineNum">     134 </span>            :   assign io_r_resp_0_7 = io_r_req_0_idx == array_7;</a>
+<a name="135"><span class="lineNum">     135 </span>            : endmodule</a>
+<a name="136"><span class="lineNum">     136 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/CAMTemplate_32.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/CAMTemplate_32.sv.func-sort-c.html
new file mode 100644
index 0000000..32aa22d
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/CAMTemplate_32.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/CAMTemplate_32.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - CAMTemplate_32.sv<span style="font-size: 80%;"> (<a href="CAMTemplate_32.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">33</td>
+            <td class="headerCovTableEntry">39</td>
+            <td class="headerCovTableEntryMed">84.6 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="CAMTemplate_32.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/CAMTemplate_32.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/CAMTemplate_32.sv.func.html
new file mode 100644
index 0000000..ad1c51c
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/CAMTemplate_32.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/CAMTemplate_32.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - CAMTemplate_32.sv<span style="font-size: 80%;"> (<a href="CAMTemplate_32.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">33</td>
+            <td class="headerCovTableEntry">39</td>
+            <td class="headerCovTableEntryMed">84.6 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="CAMTemplate_32.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/CAMTemplate_32.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/CAMTemplate_32.sv.gcov.html
new file mode 100644
index 0000000..61c5c1d
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/CAMTemplate_32.sv.gcov.html
@@ -0,0 +1,212 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/CAMTemplate_32.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - CAMTemplate_32.sv<span style="font-size: 80%;"> (source / <a href="CAMTemplate_32.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">33</td>
+            <td class="headerCovTableEntry">39</td>
+            <td class="headerCovTableEntryMed">84.6 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : module CAMTemplate_32(</a>
+<a name="59"><span class="lineNum">      59 </span><span class="lineCov">     127786 :   input         clock,</span></a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">        189 :   input  [10:0] io_r_req_0_idx,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">         25 :   output        io_r_resp_0_0,</span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">         13 :   output        io_r_resp_0_1,</span></a>
+<a name="63"><span class="lineNum">      63 </span><span class="lineCov">         19 :   output        io_r_resp_0_2,</span></a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">         25 :   output        io_r_resp_0_3,</span></a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">         16 :   output        io_r_resp_0_4,</span></a>
+<a name="66"><span class="lineNum">      66 </span><span class="lineCov">         17 :   output        io_r_resp_0_5,</span></a>
+<a name="67"><span class="lineNum">      67 </span><span class="lineCov">         15 :   output        io_r_resp_0_6,</span></a>
+<a name="68"><span class="lineNum">      68 </span><span class="lineCov">         14 :   output        io_r_resp_0_7,</span></a>
+<a name="69"><span class="lineNum">      69 </span><span class="lineCov">         40 :   input         io_w_valid,</span></a>
+<a name="70"><span class="lineNum">      70 </span><span class="lineCov">        189 :   input  [10:0] io_w_bits_data_idx,</span></a>
+<a name="71"><span class="lineNum">      71 </span><span class="lineCov">         94 :   input  [2:0]  io_w_bits_index</span></a>
+<a name="72"><span class="lineNum">      72 </span>            : );</a>
+<a name="73"><span class="lineNum">      73 </span>            : </a>
+<a name="74"><span class="lineNum">      74 </span><span class="lineCov">        227 :   reg [10:0] array_0;</span></a>
+<a name="75"><span class="lineNum">      75 </span><span class="lineCov">        157 :   reg [10:0] array_1;</span></a>
+<a name="76"><span class="lineNum">      76 </span><span class="lineCov">        184 :   reg [10:0] array_2;</span></a>
+<a name="77"><span class="lineNum">      77 </span><span class="lineCov">        179 :   reg [10:0] array_3;</span></a>
+<a name="78"><span class="lineNum">      78 </span><span class="lineCov">        153 :   reg [10:0] array_4;</span></a>
+<a name="79"><span class="lineNum">      79 </span><span class="lineCov">        162 :   reg [10:0] array_5;</span></a>
+<a name="80"><span class="lineNum">      80 </span><span class="lineCov">        151 :   reg [10:0] array_6;</span></a>
+<a name="81"><span class="lineNum">      81 </span><span class="lineCov">        158 :   reg [10:0] array_7;</span></a>
+<a name="82"><span class="lineNum">      82 </span><span class="lineCov">     127694 :   always @(posedge clock) begin</span></a>
+<a name="83"><span class="lineNum">      83 </span><span class="lineCov">         28 :     if (io_w_valid &amp; io_w_bits_index == 3'h0)</span></a>
+<a name="84"><span class="lineNum">      84 </span><span class="lineCov">         14 :       array_0 &lt;= io_w_bits_data_idx;</span></a>
+<a name="85"><span class="lineNum">      85 </span><span class="lineCov">          2 :     if (io_w_valid &amp; io_w_bits_index == 3'h1)</span></a>
+<a name="86"><span class="lineNum">      86 </span><span class="lineCov">          1 :       array_1 &lt;= io_w_bits_data_idx;</span></a>
+<a name="87"><span class="lineNum">      87 </span><span class="lineCov">          8 :     if (io_w_valid &amp; io_w_bits_index == 3'h2)</span></a>
+<a name="88"><span class="lineNum">      88 </span><span class="lineCov">          4 :       array_2 &lt;= io_w_bits_data_idx;</span></a>
+<a name="89"><span class="lineNum">      89 </span><span class="lineCov">          6 :     if (io_w_valid &amp; io_w_bits_index == 3'h3)</span></a>
+<a name="90"><span class="lineNum">      90 </span><span class="lineCov">          3 :       array_3 &lt;= io_w_bits_data_idx;</span></a>
+<a name="91"><span class="lineNum">      91 </span><span class="lineNoCov">          0 :     if (io_w_valid &amp; io_w_bits_index == 3'h4)</span></a>
+<a name="92"><span class="lineNum">      92 </span><span class="lineNoCov">          0 :       array_4 &lt;= io_w_bits_data_idx;</span></a>
+<a name="93"><span class="lineNum">      93 </span><span class="lineCov">          4 :     if (io_w_valid &amp; io_w_bits_index == 3'h5)</span></a>
+<a name="94"><span class="lineNum">      94 </span><span class="lineCov">          2 :       array_5 &lt;= io_w_bits_data_idx;</span></a>
+<a name="95"><span class="lineNum">      95 </span><span class="lineNoCov">          0 :     if (io_w_valid &amp; io_w_bits_index == 3'h6)</span></a>
+<a name="96"><span class="lineNum">      96 </span><span class="lineNoCov">          0 :       array_6 &lt;= io_w_bits_data_idx;</span></a>
+<a name="97"><span class="lineNum">      97 </span><span class="lineNoCov">          0 :     if (io_w_valid &amp; (&amp;io_w_bits_index))</span></a>
+<a name="98"><span class="lineNum">      98 </span><span class="lineNoCov">          0 :       array_7 &lt;= io_w_bits_data_idx;</span></a>
+<a name="99"><span class="lineNum">      99 </span>            :   end // always @(posedge)</a>
+<a name="100"><span class="lineNum">     100 </span>            :   `ifdef ENABLE_INITIAL_REG_</a>
+<a name="101"><span class="lineNum">     101 </span>            :     `ifdef FIRRTL_BEFORE_INITIAL</a>
+<a name="102"><span class="lineNum">     102 </span>            :       `FIRRTL_BEFORE_INITIAL</a>
+<a name="103"><span class="lineNum">     103 </span>            :     `endif // FIRRTL_BEFORE_INITIAL</a>
+<a name="104"><span class="lineNum">     104 </span>            :     logic [31:0] _RANDOM[0:2];</a>
+<a name="105"><span class="lineNum">     105 </span><span class="lineCov">         58 :     initial begin</span></a>
+<a name="106"><span class="lineNum">     106 </span>            :       `ifdef INIT_RANDOM_PROLOG_</a>
+<a name="107"><span class="lineNum">     107 </span>            :         `INIT_RANDOM_PROLOG_</a>
+<a name="108"><span class="lineNum">     108 </span>            :       `endif // INIT_RANDOM_PROLOG_</a>
+<a name="109"><span class="lineNum">     109 </span>            :       `ifdef RANDOMIZE_REG_INIT</a>
+<a name="110"><span class="lineNum">     110 </span>            :         for (logic [1:0] i = 2'h0; i &lt; 2'h3; i += 2'h1) begin</a>
+<a name="111"><span class="lineNum">     111 </span>            :           _RANDOM[i] = `RANDOM;</a>
+<a name="112"><span class="lineNum">     112 </span>            :         end</a>
+<a name="113"><span class="lineNum">     113 </span>            :         array_0 = _RANDOM[2'h0][10:0];</a>
+<a name="114"><span class="lineNum">     114 </span>            :         array_1 = _RANDOM[2'h0][21:11];</a>
+<a name="115"><span class="lineNum">     115 </span>            :         array_2 = {_RANDOM[2'h0][31:22], _RANDOM[2'h1][0]};</a>
+<a name="116"><span class="lineNum">     116 </span>            :         array_3 = _RANDOM[2'h1][11:1];</a>
+<a name="117"><span class="lineNum">     117 </span>            :         array_4 = _RANDOM[2'h1][22:12];</a>
+<a name="118"><span class="lineNum">     118 </span>            :         array_5 = {_RANDOM[2'h1][31:23], _RANDOM[2'h2][1:0]};</a>
+<a name="119"><span class="lineNum">     119 </span>            :         array_6 = _RANDOM[2'h2][12:2];</a>
+<a name="120"><span class="lineNum">     120 </span>            :         array_7 = _RANDOM[2'h2][23:13];</a>
+<a name="121"><span class="lineNum">     121 </span>            :       `endif // RANDOMIZE_REG_INIT</a>
+<a name="122"><span class="lineNum">     122 </span>            :     end // initial</a>
+<a name="123"><span class="lineNum">     123 </span>            :     `ifdef FIRRTL_AFTER_INITIAL</a>
+<a name="124"><span class="lineNum">     124 </span>            :       `FIRRTL_AFTER_INITIAL</a>
+<a name="125"><span class="lineNum">     125 </span>            :     `endif // FIRRTL_AFTER_INITIAL</a>
+<a name="126"><span class="lineNum">     126 </span>            :   `endif // ENABLE_INITIAL_REG_</a>
+<a name="127"><span class="lineNum">     127 </span>            :   assign io_r_resp_0_0 = io_r_req_0_idx == array_0;</a>
+<a name="128"><span class="lineNum">     128 </span>            :   assign io_r_resp_0_1 = io_r_req_0_idx == array_1;</a>
+<a name="129"><span class="lineNum">     129 </span>            :   assign io_r_resp_0_2 = io_r_req_0_idx == array_2;</a>
+<a name="130"><span class="lineNum">     130 </span>            :   assign io_r_resp_0_3 = io_r_req_0_idx == array_3;</a>
+<a name="131"><span class="lineNum">     131 </span>            :   assign io_r_resp_0_4 = io_r_req_0_idx == array_4;</a>
+<a name="132"><span class="lineNum">     132 </span>            :   assign io_r_resp_0_5 = io_r_req_0_idx == array_5;</a>
+<a name="133"><span class="lineNum">     133 </span>            :   assign io_r_resp_0_6 = io_r_req_0_idx == array_6;</a>
+<a name="134"><span class="lineNum">     134 </span>            :   assign io_r_resp_0_7 = io_r_req_0_idx == array_7;</a>
+<a name="135"><span class="lineNum">     135 </span>            : endmodule</a>
+<a name="136"><span class="lineNum">     136 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/CAMTemplate_33.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/CAMTemplate_33.sv.func-sort-c.html
new file mode 100644
index 0000000..67544f2
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/CAMTemplate_33.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/CAMTemplate_33.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - CAMTemplate_33.sv<span style="font-size: 80%;"> (<a href="CAMTemplate_33.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">71</td>
+            <td class="headerCovTableEntry">71</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="CAMTemplate_33.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/CAMTemplate_33.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/CAMTemplate_33.sv.func.html
new file mode 100644
index 0000000..3a46665
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/CAMTemplate_33.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/CAMTemplate_33.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - CAMTemplate_33.sv<span style="font-size: 80%;"> (<a href="CAMTemplate_33.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">71</td>
+            <td class="headerCovTableEntry">71</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="CAMTemplate_33.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/CAMTemplate_33.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/CAMTemplate_33.sv.gcov.html
new file mode 100644
index 0000000..2813ae3
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/CAMTemplate_33.sv.gcov.html
@@ -0,0 +1,260 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/CAMTemplate_33.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - CAMTemplate_33.sv<span style="font-size: 80%;"> (source / <a href="CAMTemplate_33.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">71</td>
+            <td class="headerCovTableEntry">71</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : module CAMTemplate_33(</a>
+<a name="59"><span class="lineNum">      59 </span><span class="lineCov">     127786 :   input        clock,</span></a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">        131 :   input  [7:0] io_r_req_0_idx,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">        188 :   output       io_r_resp_0_0,</span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">        124 :   output       io_r_resp_0_1,</span></a>
+<a name="63"><span class="lineNum">      63 </span><span class="lineCov">        118 :   output       io_r_resp_0_2,</span></a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">        127 :   output       io_r_resp_0_3,</span></a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">        122 :   output       io_r_resp_0_4,</span></a>
+<a name="66"><span class="lineNum">      66 </span><span class="lineCov">        139 :   output       io_r_resp_0_5,</span></a>
+<a name="67"><span class="lineNum">      67 </span><span class="lineCov">        113 :   output       io_r_resp_0_6,</span></a>
+<a name="68"><span class="lineNum">      68 </span><span class="lineCov">        129 :   output       io_r_resp_0_7,</span></a>
+<a name="69"><span class="lineNum">      69 </span><span class="lineCov">        115 :   output       io_r_resp_0_8,</span></a>
+<a name="70"><span class="lineNum">      70 </span><span class="lineCov">        136 :   output       io_r_resp_0_9,</span></a>
+<a name="71"><span class="lineNum">      71 </span><span class="lineCov">        121 :   output       io_r_resp_0_10,</span></a>
+<a name="72"><span class="lineNum">      72 </span><span class="lineCov">        128 :   output       io_r_resp_0_11,</span></a>
+<a name="73"><span class="lineNum">      73 </span><span class="lineCov">        123 :   output       io_r_resp_0_12,</span></a>
+<a name="74"><span class="lineNum">      74 </span><span class="lineCov">        121 :   output       io_r_resp_0_13,</span></a>
+<a name="75"><span class="lineNum">      75 </span><span class="lineCov">        108 :   output       io_r_resp_0_14,</span></a>
+<a name="76"><span class="lineNum">      76 </span><span class="lineCov">        121 :   output       io_r_resp_0_15,</span></a>
+<a name="77"><span class="lineNum">      77 </span><span class="lineCov">        251 :   input        io_w_valid,</span></a>
+<a name="78"><span class="lineNum">      78 </span><span class="lineCov">        131 :   input  [7:0] io_w_bits_data_idx,</span></a>
+<a name="79"><span class="lineNum">      79 </span><span class="lineCov">        926 :   input  [3:0] io_w_bits_index</span></a>
+<a name="80"><span class="lineNum">      80 </span>            : );</a>
+<a name="81"><span class="lineNum">      81 </span>            : </a>
+<a name="82"><span class="lineNum">      82 </span><span class="lineCov">       1172 :   reg [7:0] array_0;</span></a>
+<a name="83"><span class="lineNum">      83 </span><span class="lineCov">        949 :   reg [7:0] array_1;</span></a>
+<a name="84"><span class="lineNum">      84 </span><span class="lineCov">        951 :   reg [7:0] array_2;</span></a>
+<a name="85"><span class="lineNum">      85 </span><span class="lineCov">        983 :   reg [7:0] array_3;</span></a>
+<a name="86"><span class="lineNum">      86 </span><span class="lineCov">        917 :   reg [7:0] array_4;</span></a>
+<a name="87"><span class="lineNum">      87 </span><span class="lineCov">        965 :   reg [7:0] array_5;</span></a>
+<a name="88"><span class="lineNum">      88 </span><span class="lineCov">        949 :   reg [7:0] array_6;</span></a>
+<a name="89"><span class="lineNum">      89 </span><span class="lineCov">        939 :   reg [7:0] array_7;</span></a>
+<a name="90"><span class="lineNum">      90 </span><span class="lineCov">        942 :   reg [7:0] array_8;</span></a>
+<a name="91"><span class="lineNum">      91 </span><span class="lineCov">        922 :   reg [7:0] array_9;</span></a>
+<a name="92"><span class="lineNum">      92 </span><span class="lineCov">        931 :   reg [7:0] array_10;</span></a>
+<a name="93"><span class="lineNum">      93 </span><span class="lineCov">        962 :   reg [7:0] array_11;</span></a>
+<a name="94"><span class="lineNum">      94 </span><span class="lineCov">        946 :   reg [7:0] array_12;</span></a>
+<a name="95"><span class="lineNum">      95 </span><span class="lineCov">        931 :   reg [7:0] array_13;</span></a>
+<a name="96"><span class="lineNum">      96 </span><span class="lineCov">        960 :   reg [7:0] array_14;</span></a>
+<a name="97"><span class="lineNum">      97 </span><span class="lineCov">        978 :   reg [7:0] array_15;</span></a>
+<a name="98"><span class="lineNum">      98 </span><span class="lineCov">    1021552 :   always @(posedge clock) begin</span></a>
+<a name="99"><span class="lineNum">      99 </span><span class="lineCov">        138 :     if (io_w_valid &amp; io_w_bits_index == 4'h0)</span></a>
+<a name="100"><span class="lineNum">     100 </span><span class="lineCov">         69 :       array_0 &lt;= io_w_bits_data_idx;</span></a>
+<a name="101"><span class="lineNum">     101 </span><span class="lineCov">         10 :     if (io_w_valid &amp; io_w_bits_index == 4'h1)</span></a>
+<a name="102"><span class="lineNum">     102 </span><span class="lineCov">          5 :       array_1 &lt;= io_w_bits_data_idx;</span></a>
+<a name="103"><span class="lineNum">     103 </span><span class="lineCov">          8 :     if (io_w_valid &amp; io_w_bits_index == 4'h2)</span></a>
+<a name="104"><span class="lineNum">     104 </span><span class="lineCov">          4 :       array_2 &lt;= io_w_bits_data_idx;</span></a>
+<a name="105"><span class="lineNum">     105 </span><span class="lineCov">         12 :     if (io_w_valid &amp; io_w_bits_index == 4'h3)</span></a>
+<a name="106"><span class="lineNum">     106 </span><span class="lineCov">          6 :       array_3 &lt;= io_w_bits_data_idx;</span></a>
+<a name="107"><span class="lineNum">     107 </span><span class="lineCov">         10 :     if (io_w_valid &amp; io_w_bits_index == 4'h4)</span></a>
+<a name="108"><span class="lineNum">     108 </span><span class="lineCov">          5 :       array_4 &lt;= io_w_bits_data_idx;</span></a>
+<a name="109"><span class="lineNum">     109 </span><span class="lineCov">         10 :     if (io_w_valid &amp; io_w_bits_index == 4'h5)</span></a>
+<a name="110"><span class="lineNum">     110 </span><span class="lineCov">          5 :       array_5 &lt;= io_w_bits_data_idx;</span></a>
+<a name="111"><span class="lineNum">     111 </span><span class="lineCov">          6 :     if (io_w_valid &amp; io_w_bits_index == 4'h6)</span></a>
+<a name="112"><span class="lineNum">     112 </span><span class="lineCov">          3 :       array_6 &lt;= io_w_bits_data_idx;</span></a>
+<a name="113"><span class="lineNum">     113 </span><span class="lineCov">          6 :     if (io_w_valid &amp; io_w_bits_index == 4'h7)</span></a>
+<a name="114"><span class="lineNum">     114 </span><span class="lineCov">          3 :       array_7 &lt;= io_w_bits_data_idx;</span></a>
+<a name="115"><span class="lineNum">     115 </span><span class="lineCov">          4 :     if (io_w_valid &amp; io_w_bits_index == 4'h8)</span></a>
+<a name="116"><span class="lineNum">     116 </span><span class="lineCov">          2 :       array_8 &lt;= io_w_bits_data_idx;</span></a>
+<a name="117"><span class="lineNum">     117 </span><span class="lineCov">          8 :     if (io_w_valid &amp; io_w_bits_index == 4'h9)</span></a>
+<a name="118"><span class="lineNum">     118 </span><span class="lineCov">          4 :       array_9 &lt;= io_w_bits_data_idx;</span></a>
+<a name="119"><span class="lineNum">     119 </span><span class="lineCov">          4 :     if (io_w_valid &amp; io_w_bits_index == 4'hA)</span></a>
+<a name="120"><span class="lineNum">     120 </span><span class="lineCov">          2 :       array_10 &lt;= io_w_bits_data_idx;</span></a>
+<a name="121"><span class="lineNum">     121 </span><span class="lineCov">         10 :     if (io_w_valid &amp; io_w_bits_index == 4'hB)</span></a>
+<a name="122"><span class="lineNum">     122 </span><span class="lineCov">          5 :       array_11 &lt;= io_w_bits_data_idx;</span></a>
+<a name="123"><span class="lineNum">     123 </span><span class="lineCov">          8 :     if (io_w_valid &amp; io_w_bits_index == 4'hC)</span></a>
+<a name="124"><span class="lineNum">     124 </span><span class="lineCov">          4 :       array_12 &lt;= io_w_bits_data_idx;</span></a>
+<a name="125"><span class="lineNum">     125 </span><span class="lineCov">          6 :     if (io_w_valid &amp; io_w_bits_index == 4'hD)</span></a>
+<a name="126"><span class="lineNum">     126 </span><span class="lineCov">          3 :       array_13 &lt;= io_w_bits_data_idx;</span></a>
+<a name="127"><span class="lineNum">     127 </span><span class="lineCov">          6 :     if (io_w_valid &amp; io_w_bits_index == 4'hE)</span></a>
+<a name="128"><span class="lineNum">     128 </span><span class="lineCov">          3 :       array_14 &lt;= io_w_bits_data_idx;</span></a>
+<a name="129"><span class="lineNum">     129 </span><span class="lineCov">          8 :     if (io_w_valid &amp; (&amp;io_w_bits_index))</span></a>
+<a name="130"><span class="lineNum">     130 </span><span class="lineCov">          4 :       array_15 &lt;= io_w_bits_data_idx;</span></a>
+<a name="131"><span class="lineNum">     131 </span>            :   end // always @(posedge)</a>
+<a name="132"><span class="lineNum">     132 </span>            :   `ifdef ENABLE_INITIAL_REG_</a>
+<a name="133"><span class="lineNum">     133 </span>            :     `ifdef FIRRTL_BEFORE_INITIAL</a>
+<a name="134"><span class="lineNum">     134 </span>            :       `FIRRTL_BEFORE_INITIAL</a>
+<a name="135"><span class="lineNum">     135 </span>            :     `endif // FIRRTL_BEFORE_INITIAL</a>
+<a name="136"><span class="lineNum">     136 </span>            :     logic [31:0] _RANDOM[0:3];</a>
+<a name="137"><span class="lineNum">     137 </span><span class="lineCov">        464 :     initial begin</span></a>
+<a name="138"><span class="lineNum">     138 </span>            :       `ifdef INIT_RANDOM_PROLOG_</a>
+<a name="139"><span class="lineNum">     139 </span>            :         `INIT_RANDOM_PROLOG_</a>
+<a name="140"><span class="lineNum">     140 </span>            :       `endif // INIT_RANDOM_PROLOG_</a>
+<a name="141"><span class="lineNum">     141 </span>            :       `ifdef RANDOMIZE_REG_INIT</a>
+<a name="142"><span class="lineNum">     142 </span>            :         for (logic [2:0] i = 3'h0; i &lt; 3'h4; i += 3'h1) begin</a>
+<a name="143"><span class="lineNum">     143 </span>            :           _RANDOM[i[1:0]] = `RANDOM;</a>
+<a name="144"><span class="lineNum">     144 </span>            :         end</a>
+<a name="145"><span class="lineNum">     145 </span>            :         array_0 = _RANDOM[2'h0][7:0];</a>
+<a name="146"><span class="lineNum">     146 </span>            :         array_1 = _RANDOM[2'h0][15:8];</a>
+<a name="147"><span class="lineNum">     147 </span>            :         array_2 = _RANDOM[2'h0][23:16];</a>
+<a name="148"><span class="lineNum">     148 </span>            :         array_3 = _RANDOM[2'h0][31:24];</a>
+<a name="149"><span class="lineNum">     149 </span>            :         array_4 = _RANDOM[2'h1][7:0];</a>
+<a name="150"><span class="lineNum">     150 </span>            :         array_5 = _RANDOM[2'h1][15:8];</a>
+<a name="151"><span class="lineNum">     151 </span>            :         array_6 = _RANDOM[2'h1][23:16];</a>
+<a name="152"><span class="lineNum">     152 </span>            :         array_7 = _RANDOM[2'h1][31:24];</a>
+<a name="153"><span class="lineNum">     153 </span>            :         array_8 = _RANDOM[2'h2][7:0];</a>
+<a name="154"><span class="lineNum">     154 </span>            :         array_9 = _RANDOM[2'h2][15:8];</a>
+<a name="155"><span class="lineNum">     155 </span>            :         array_10 = _RANDOM[2'h2][23:16];</a>
+<a name="156"><span class="lineNum">     156 </span>            :         array_11 = _RANDOM[2'h2][31:24];</a>
+<a name="157"><span class="lineNum">     157 </span>            :         array_12 = _RANDOM[2'h3][7:0];</a>
+<a name="158"><span class="lineNum">     158 </span>            :         array_13 = _RANDOM[2'h3][15:8];</a>
+<a name="159"><span class="lineNum">     159 </span>            :         array_14 = _RANDOM[2'h3][23:16];</a>
+<a name="160"><span class="lineNum">     160 </span>            :         array_15 = _RANDOM[2'h3][31:24];</a>
+<a name="161"><span class="lineNum">     161 </span>            :       `endif // RANDOMIZE_REG_INIT</a>
+<a name="162"><span class="lineNum">     162 </span>            :     end // initial</a>
+<a name="163"><span class="lineNum">     163 </span>            :     `ifdef FIRRTL_AFTER_INITIAL</a>
+<a name="164"><span class="lineNum">     164 </span>            :       `FIRRTL_AFTER_INITIAL</a>
+<a name="165"><span class="lineNum">     165 </span>            :     `endif // FIRRTL_AFTER_INITIAL</a>
+<a name="166"><span class="lineNum">     166 </span>            :   `endif // ENABLE_INITIAL_REG_</a>
+<a name="167"><span class="lineNum">     167 </span>            :   assign io_r_resp_0_0 = io_r_req_0_idx == array_0;</a>
+<a name="168"><span class="lineNum">     168 </span>            :   assign io_r_resp_0_1 = io_r_req_0_idx == array_1;</a>
+<a name="169"><span class="lineNum">     169 </span>            :   assign io_r_resp_0_2 = io_r_req_0_idx == array_2;</a>
+<a name="170"><span class="lineNum">     170 </span>            :   assign io_r_resp_0_3 = io_r_req_0_idx == array_3;</a>
+<a name="171"><span class="lineNum">     171 </span>            :   assign io_r_resp_0_4 = io_r_req_0_idx == array_4;</a>
+<a name="172"><span class="lineNum">     172 </span>            :   assign io_r_resp_0_5 = io_r_req_0_idx == array_5;</a>
+<a name="173"><span class="lineNum">     173 </span>            :   assign io_r_resp_0_6 = io_r_req_0_idx == array_6;</a>
+<a name="174"><span class="lineNum">     174 </span>            :   assign io_r_resp_0_7 = io_r_req_0_idx == array_7;</a>
+<a name="175"><span class="lineNum">     175 </span>            :   assign io_r_resp_0_8 = io_r_req_0_idx == array_8;</a>
+<a name="176"><span class="lineNum">     176 </span>            :   assign io_r_resp_0_9 = io_r_req_0_idx == array_9;</a>
+<a name="177"><span class="lineNum">     177 </span>            :   assign io_r_resp_0_10 = io_r_req_0_idx == array_10;</a>
+<a name="178"><span class="lineNum">     178 </span>            :   assign io_r_resp_0_11 = io_r_req_0_idx == array_11;</a>
+<a name="179"><span class="lineNum">     179 </span>            :   assign io_r_resp_0_12 = io_r_req_0_idx == array_12;</a>
+<a name="180"><span class="lineNum">     180 </span>            :   assign io_r_resp_0_13 = io_r_req_0_idx == array_13;</a>
+<a name="181"><span class="lineNum">     181 </span>            :   assign io_r_resp_0_14 = io_r_req_0_idx == array_14;</a>
+<a name="182"><span class="lineNum">     182 </span>            :   assign io_r_resp_0_15 = io_r_req_0_idx == array_15;</a>
+<a name="183"><span class="lineNum">     183 </span>            : endmodule</a>
+<a name="184"><span class="lineNum">     184 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/CAMTemplate_41.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/CAMTemplate_41.sv.func-sort-c.html
new file mode 100644
index 0000000..a01a269
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/CAMTemplate_41.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/CAMTemplate_41.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - CAMTemplate_41.sv<span style="font-size: 80%;"> (<a href="CAMTemplate_41.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">23</td>
+            <td class="headerCovTableEntry">23</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="CAMTemplate_41.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/CAMTemplate_41.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/CAMTemplate_41.sv.func.html
new file mode 100644
index 0000000..b25f60d
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/CAMTemplate_41.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/CAMTemplate_41.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - CAMTemplate_41.sv<span style="font-size: 80%;"> (<a href="CAMTemplate_41.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">23</td>
+            <td class="headerCovTableEntry">23</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="CAMTemplate_41.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/CAMTemplate_41.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/CAMTemplate_41.sv.gcov.html
new file mode 100644
index 0000000..09564a1
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/CAMTemplate_41.sv.gcov.html
@@ -0,0 +1,186 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/CAMTemplate_41.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - CAMTemplate_41.sv<span style="font-size: 80%;"> (source / <a href="CAMTemplate_41.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">23</td>
+            <td class="headerCovTableEntry">23</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : module CAMTemplate_41(</a>
+<a name="59"><span class="lineNum">      59 </span><span class="lineCov">     127786 :   input        clock,</span></a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">        105 :   input  [7:0] io_r_req_0_idx,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">         43 :   output       io_r_resp_0_0,</span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">         32 :   output       io_r_resp_0_1,</span></a>
+<a name="63"><span class="lineNum">      63 </span><span class="lineCov">         30 :   output       io_r_resp_0_2,</span></a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">         30 :   output       io_r_resp_0_3,</span></a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">         49 :   input        io_w_valid,</span></a>
+<a name="66"><span class="lineNum">      66 </span><span class="lineCov">        105 :   input  [7:0] io_w_bits_data_idx,</span></a>
+<a name="67"><span class="lineNum">      67 </span><span class="lineCov">        118 :   input  [1:0] io_w_bits_index</span></a>
+<a name="68"><span class="lineNum">      68 </span>            : );</a>
+<a name="69"><span class="lineNum">      69 </span>            : </a>
+<a name="70"><span class="lineNum">      70 </span><span class="lineCov">        286 :   reg [7:0] array_0;</span></a>
+<a name="71"><span class="lineNum">      71 </span><span class="lineCov">        233 :   reg [7:0] array_1;</span></a>
+<a name="72"><span class="lineNum">      72 </span><span class="lineCov">        252 :   reg [7:0] array_2;</span></a>
+<a name="73"><span class="lineNum">      73 </span><span class="lineCov">        242 :   reg [7:0] array_3;</span></a>
+<a name="74"><span class="lineNum">      74 </span><span class="lineCov">     255388 :   always @(posedge clock) begin</span></a>
+<a name="75"><span class="lineNum">      75 </span><span class="lineCov">         28 :     if (io_w_valid &amp; io_w_bits_index == 2'h0)</span></a>
+<a name="76"><span class="lineNum">      76 </span><span class="lineCov">         14 :       array_0 &lt;= io_w_bits_data_idx;</span></a>
+<a name="77"><span class="lineNum">      77 </span><span class="lineCov">          4 :     if (io_w_valid &amp; io_w_bits_index == 2'h1)</span></a>
+<a name="78"><span class="lineNum">      78 </span><span class="lineCov">          2 :       array_1 &lt;= io_w_bits_data_idx;</span></a>
+<a name="79"><span class="lineNum">      79 </span><span class="lineCov">          8 :     if (io_w_valid &amp; io_w_bits_index == 2'h2)</span></a>
+<a name="80"><span class="lineNum">      80 </span><span class="lineCov">          4 :       array_2 &lt;= io_w_bits_data_idx;</span></a>
+<a name="81"><span class="lineNum">      81 </span><span class="lineCov">          6 :     if (io_w_valid &amp; (&amp;io_w_bits_index))</span></a>
+<a name="82"><span class="lineNum">      82 </span><span class="lineCov">          3 :       array_3 &lt;= io_w_bits_data_idx;</span></a>
+<a name="83"><span class="lineNum">      83 </span>            :   end // always @(posedge)</a>
+<a name="84"><span class="lineNum">      84 </span>            :   `ifdef ENABLE_INITIAL_REG_</a>
+<a name="85"><span class="lineNum">      85 </span>            :     `ifdef FIRRTL_BEFORE_INITIAL</a>
+<a name="86"><span class="lineNum">      86 </span>            :       `FIRRTL_BEFORE_INITIAL</a>
+<a name="87"><span class="lineNum">      87 </span>            :     `endif // FIRRTL_BEFORE_INITIAL</a>
+<a name="88"><span class="lineNum">      88 </span>            :     logic [31:0] _RANDOM[0:0];</a>
+<a name="89"><span class="lineNum">      89 </span><span class="lineCov">        116 :     initial begin</span></a>
+<a name="90"><span class="lineNum">      90 </span>            :       `ifdef INIT_RANDOM_PROLOG_</a>
+<a name="91"><span class="lineNum">      91 </span>            :         `INIT_RANDOM_PROLOG_</a>
+<a name="92"><span class="lineNum">      92 </span>            :       `endif // INIT_RANDOM_PROLOG_</a>
+<a name="93"><span class="lineNum">      93 </span>            :       `ifdef RANDOMIZE_REG_INIT</a>
+<a name="94"><span class="lineNum">      94 </span>            :         _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;</a>
+<a name="95"><span class="lineNum">      95 </span>            :         array_0 = _RANDOM[/*Zero width*/ 1'b0][7:0];</a>
+<a name="96"><span class="lineNum">      96 </span>            :         array_1 = _RANDOM[/*Zero width*/ 1'b0][15:8];</a>
+<a name="97"><span class="lineNum">      97 </span>            :         array_2 = _RANDOM[/*Zero width*/ 1'b0][23:16];</a>
+<a name="98"><span class="lineNum">      98 </span>            :         array_3 = _RANDOM[/*Zero width*/ 1'b0][31:24];</a>
+<a name="99"><span class="lineNum">      99 </span>            :       `endif // RANDOMIZE_REG_INIT</a>
+<a name="100"><span class="lineNum">     100 </span>            :     end // initial</a>
+<a name="101"><span class="lineNum">     101 </span>            :     `ifdef FIRRTL_AFTER_INITIAL</a>
+<a name="102"><span class="lineNum">     102 </span>            :       `FIRRTL_AFTER_INITIAL</a>
+<a name="103"><span class="lineNum">     103 </span>            :     `endif // FIRRTL_AFTER_INITIAL</a>
+<a name="104"><span class="lineNum">     104 </span>            :   `endif // ENABLE_INITIAL_REG_</a>
+<a name="105"><span class="lineNum">     105 </span>            :   assign io_r_resp_0_0 = io_r_req_0_idx == array_0;</a>
+<a name="106"><span class="lineNum">     106 </span>            :   assign io_r_resp_0_1 = io_r_req_0_idx == array_1;</a>
+<a name="107"><span class="lineNum">     107 </span>            :   assign io_r_resp_0_2 = io_r_req_0_idx == array_2;</a>
+<a name="108"><span class="lineNum">     108 </span>            :   assign io_r_resp_0_3 = io_r_req_0_idx == array_3;</a>
+<a name="109"><span class="lineNum">     109 </span>            : endmodule</a>
+<a name="110"><span class="lineNum">     110 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/CAMTemplate_43.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/CAMTemplate_43.sv.func-sort-c.html
new file mode 100644
index 0000000..906ff81
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/CAMTemplate_43.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/CAMTemplate_43.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - CAMTemplate_43.sv<span style="font-size: 80%;"> (<a href="CAMTemplate_43.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">21</td>
+            <td class="headerCovTableEntry">23</td>
+            <td class="headerCovTableEntryHi">91.3 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="CAMTemplate_43.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/CAMTemplate_43.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/CAMTemplate_43.sv.func.html
new file mode 100644
index 0000000..86401c1
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/CAMTemplate_43.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/CAMTemplate_43.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - CAMTemplate_43.sv<span style="font-size: 80%;"> (<a href="CAMTemplate_43.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">21</td>
+            <td class="headerCovTableEntry">23</td>
+            <td class="headerCovTableEntryHi">91.3 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="CAMTemplate_43.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/CAMTemplate_43.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/CAMTemplate_43.sv.gcov.html
new file mode 100644
index 0000000..bd24408
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/CAMTemplate_43.sv.gcov.html
@@ -0,0 +1,188 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/CAMTemplate_43.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - CAMTemplate_43.sv<span style="font-size: 80%;"> (source / <a href="CAMTemplate_43.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">21</td>
+            <td class="headerCovTableEntry">23</td>
+            <td class="headerCovTableEntryHi">91.3 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : module CAMTemplate_43(</a>
+<a name="59"><span class="lineNum">      59 </span><span class="lineCov">     127786 :   input        clock,</span></a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">        125 :   input  [8:0] io_r_req_0_idx,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">         73 :   output       io_r_resp_0_0,</span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">         41 :   output       io_r_resp_0_1,</span></a>
+<a name="63"><span class="lineNum">      63 </span><span class="lineCov">         50 :   output       io_r_resp_0_2,</span></a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">         51 :   output       io_r_resp_0_3,</span></a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">         82 :   input        io_w_valid,</span></a>
+<a name="66"><span class="lineNum">      66 </span><span class="lineCov">        125 :   input  [8:0] io_w_bits_data_idx,</span></a>
+<a name="67"><span class="lineNum">      67 </span><span class="lineCov">        180 :   input  [1:0] io_w_bits_index</span></a>
+<a name="68"><span class="lineNum">      68 </span>            : );</a>
+<a name="69"><span class="lineNum">      69 </span>            : </a>
+<a name="70"><span class="lineNum">      70 </span><span class="lineCov">        509 :   reg [8:0] array_0;</span></a>
+<a name="71"><span class="lineNum">      71 </span><span class="lineCov">        392 :   reg [8:0] array_1;</span></a>
+<a name="72"><span class="lineNum">      72 </span><span class="lineCov">        440 :   reg [8:0] array_2;</span></a>
+<a name="73"><span class="lineNum">      73 </span><span class="lineCov">        407 :   reg [8:0] array_3;</span></a>
+<a name="74"><span class="lineNum">      74 </span><span class="lineCov">     383082 :   always @(posedge clock) begin</span></a>
+<a name="75"><span class="lineNum">      75 </span><span class="lineCov">         54 :     if (io_w_valid &amp; io_w_bits_index == 2'h0)</span></a>
+<a name="76"><span class="lineNum">      76 </span><span class="lineCov">         27 :       array_0 &lt;= io_w_bits_data_idx;</span></a>
+<a name="77"><span class="lineNum">      77 </span><span class="lineNoCov">          0 :     if (io_w_valid &amp; io_w_bits_index == 2'h1)</span></a>
+<a name="78"><span class="lineNum">      78 </span><span class="lineNoCov">          0 :       array_1 &lt;= io_w_bits_data_idx;</span></a>
+<a name="79"><span class="lineNum">      79 </span><span class="lineCov">         18 :     if (io_w_valid &amp; io_w_bits_index == 2'h2)</span></a>
+<a name="80"><span class="lineNum">      80 </span><span class="lineCov">          9 :       array_2 &lt;= io_w_bits_data_idx;</span></a>
+<a name="81"><span class="lineNum">      81 </span><span class="lineCov">          8 :     if (io_w_valid &amp; (&amp;io_w_bits_index))</span></a>
+<a name="82"><span class="lineNum">      82 </span><span class="lineCov">          4 :       array_3 &lt;= io_w_bits_data_idx;</span></a>
+<a name="83"><span class="lineNum">      83 </span>            :   end // always @(posedge)</a>
+<a name="84"><span class="lineNum">      84 </span>            :   `ifdef ENABLE_INITIAL_REG_</a>
+<a name="85"><span class="lineNum">      85 </span>            :     `ifdef FIRRTL_BEFORE_INITIAL</a>
+<a name="86"><span class="lineNum">      86 </span>            :       `FIRRTL_BEFORE_INITIAL</a>
+<a name="87"><span class="lineNum">      87 </span>            :     `endif // FIRRTL_BEFORE_INITIAL</a>
+<a name="88"><span class="lineNum">      88 </span>            :     logic [31:0] _RANDOM[0:1];</a>
+<a name="89"><span class="lineNum">      89 </span><span class="lineCov">        174 :     initial begin</span></a>
+<a name="90"><span class="lineNum">      90 </span>            :       `ifdef INIT_RANDOM_PROLOG_</a>
+<a name="91"><span class="lineNum">      91 </span>            :         `INIT_RANDOM_PROLOG_</a>
+<a name="92"><span class="lineNum">      92 </span>            :       `endif // INIT_RANDOM_PROLOG_</a>
+<a name="93"><span class="lineNum">      93 </span>            :       `ifdef RANDOMIZE_REG_INIT</a>
+<a name="94"><span class="lineNum">      94 </span>            :         for (logic [1:0] i = 2'h0; i &lt; 2'h2; i += 2'h1) begin</a>
+<a name="95"><span class="lineNum">      95 </span>            :           _RANDOM[i[0]] = `RANDOM;</a>
+<a name="96"><span class="lineNum">      96 </span>            :         end</a>
+<a name="97"><span class="lineNum">      97 </span>            :         array_0 = _RANDOM[1'h0][8:0];</a>
+<a name="98"><span class="lineNum">      98 </span>            :         array_1 = _RANDOM[1'h0][17:9];</a>
+<a name="99"><span class="lineNum">      99 </span>            :         array_2 = _RANDOM[1'h0][26:18];</a>
+<a name="100"><span class="lineNum">     100 </span>            :         array_3 = {_RANDOM[1'h0][31:27], _RANDOM[1'h1][3:0]};</a>
+<a name="101"><span class="lineNum">     101 </span>            :       `endif // RANDOMIZE_REG_INIT</a>
+<a name="102"><span class="lineNum">     102 </span>            :     end // initial</a>
+<a name="103"><span class="lineNum">     103 </span>            :     `ifdef FIRRTL_AFTER_INITIAL</a>
+<a name="104"><span class="lineNum">     104 </span>            :       `FIRRTL_AFTER_INITIAL</a>
+<a name="105"><span class="lineNum">     105 </span>            :     `endif // FIRRTL_AFTER_INITIAL</a>
+<a name="106"><span class="lineNum">     106 </span>            :   `endif // ENABLE_INITIAL_REG_</a>
+<a name="107"><span class="lineNum">     107 </span>            :   assign io_r_resp_0_0 = io_r_req_0_idx == array_0;</a>
+<a name="108"><span class="lineNum">     108 </span>            :   assign io_r_resp_0_1 = io_r_req_0_idx == array_1;</a>
+<a name="109"><span class="lineNum">     109 </span>            :   assign io_r_resp_0_2 = io_r_req_0_idx == array_2;</a>
+<a name="110"><span class="lineNum">     110 </span>            :   assign io_r_resp_0_3 = io_r_req_0_idx == array_3;</a>
+<a name="111"><span class="lineNum">     111 </span>            : endmodule</a>
+<a name="112"><span class="lineNum">     112 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/Composer.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/Composer.sv.func-sort-c.html
new file mode 100644
index 0000000..38bb6fa
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/Composer.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/Composer.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - Composer.sv<span style="font-size: 80%;"> (<a href="Composer.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">320</td>
+            <td class="headerCovTableEntry">320</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="Composer.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/Composer.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/Composer.sv.func.html
new file mode 100644
index 0000000..cc9796b
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/Composer.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/Composer.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - Composer.sv<span style="font-size: 80%;"> (<a href="Composer.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">320</td>
+            <td class="headerCovTableEntry">320</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="Composer.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/Composer.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/Composer.sv.gcov.html
new file mode 100644
index 0000000..5bcf4a5
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/Composer.sv.gcov.html
@@ -0,0 +1,2502 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/Composer.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - Composer.sv<span style="font-size: 80%;"> (source / <a href="Composer.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">320</td>
+            <td class="headerCovTableEntry">320</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : module Composer(</a>
+<a name="59"><span class="lineNum">      59 </span><span class="lineCov">     127786 :   input          clock,</span></a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">         62 :   input          reset,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">       1105 :   input  [35:0]  io_reset_vector,</span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">      10337 :   input  [40:0]  io_in_bits_s0_pc_0,</span></a>
+<a name="63"><span class="lineNum">      63 </span><span class="lineCov">      10224 :   input  [40:0]  io_in_bits_s0_pc_1,</span></a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">      10251 :   input  [40:0]  io_in_bits_s0_pc_2,</span></a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">      35066 :   input  [40:0]  io_in_bits_s0_pc_3,</span></a>
+<a name="66"><span class="lineNum">      66 </span><span class="lineCov">       1182 :   input  [10:0]  io_in_bits_folded_hist_1_hist_17_folded_hist,</span></a>
+<a name="67"><span class="lineNum">      67 </span><span class="lineCov">       1102 :   input  [10:0]  io_in_bits_folded_hist_1_hist_16_folded_hist,</span></a>
+<a name="68"><span class="lineNum">      68 </span><span class="lineCov">        828 :   input  [6:0]   io_in_bits_folded_hist_1_hist_15_folded_hist,</span></a>
+<a name="69"><span class="lineNum">      69 </span><span class="lineCov">        295 :   input  [7:0]   io_in_bits_folded_hist_1_hist_14_folded_hist,</span></a>
+<a name="70"><span class="lineNum">      70 </span><span class="lineCov">        844 :   input  [6:0]   io_in_bits_folded_hist_1_hist_9_folded_hist,</span></a>
+<a name="71"><span class="lineNum">      71 </span><span class="lineCov">        930 :   input  [7:0]   io_in_bits_folded_hist_1_hist_8_folded_hist,</span></a>
+<a name="72"><span class="lineNum">      72 </span><span class="lineCov">        760 :   input  [6:0]   io_in_bits_folded_hist_1_hist_7_folded_hist,</span></a>
+<a name="73"><span class="lineNum">      73 </span><span class="lineCov">        711 :   input  [6:0]   io_in_bits_folded_hist_1_hist_5_folded_hist,</span></a>
+<a name="74"><span class="lineNum">      74 </span><span class="lineCov">        300 :   input  [7:0]   io_in_bits_folded_hist_1_hist_4_folded_hist,</span></a>
+<a name="75"><span class="lineNum">      75 </span><span class="lineCov">        263 :   input  [7:0]   io_in_bits_folded_hist_1_hist_3_folded_hist,</span></a>
+<a name="76"><span class="lineNum">      76 </span><span class="lineCov">       1122 :   input  [10:0]  io_in_bits_folded_hist_1_hist_1_folded_hist,</span></a>
+<a name="77"><span class="lineNum">      77 </span><span class="lineCov">        564 :   input  [7:0]   io_in_bits_folded_hist_3_hist_14_folded_hist,</span></a>
+<a name="78"><span class="lineNum">      78 </span><span class="lineCov">        989 :   input  [8:0]   io_in_bits_folded_hist_3_hist_13_folded_hist,</span></a>
+<a name="79"><span class="lineNum">      79 </span><span class="lineCov">        474 :   input  [3:0]   io_in_bits_folded_hist_3_hist_12_folded_hist,</span></a>
+<a name="80"><span class="lineNum">      80 </span><span class="lineCov">        858 :   input  [7:0]   io_in_bits_folded_hist_3_hist_11_folded_hist,</span></a>
+<a name="81"><span class="lineNum">      81 </span><span class="lineCov">        998 :   input  [8:0]   io_in_bits_folded_hist_3_hist_10_folded_hist,</span></a>
+<a name="82"><span class="lineNum">      82 </span><span class="lineCov">        987 :   input  [8:0]   io_in_bits_folded_hist_3_hist_6_folded_hist,</span></a>
+<a name="83"><span class="lineNum">      83 </span><span class="lineCov">        602 :   input  [7:0]   io_in_bits_folded_hist_3_hist_4_folded_hist,</span></a>
+<a name="84"><span class="lineNum">      84 </span><span class="lineCov">        517 :   input  [7:0]   io_in_bits_folded_hist_3_hist_3_folded_hist,</span></a>
+<a name="85"><span class="lineNum">      85 </span><span class="lineCov">        811 :   input  [7:0]   io_in_bits_folded_hist_3_hist_2_folded_hist,</span></a>
+<a name="86"><span class="lineNum">      86 </span><span class="lineCov">       9878 :   output [40:0]  io_out_s1_pc_0,</span></a>
+<a name="87"><span class="lineNum">      87 </span><span class="lineCov">       9918 :   output [40:0]  io_out_s1_pc_1,</span></a>
+<a name="88"><span class="lineNum">      88 </span><span class="lineCov">       9857 :   output [40:0]  io_out_s1_pc_2,</span></a>
+<a name="89"><span class="lineNum">      89 </span><span class="lineCov">       9933 :   output [40:0]  io_out_s1_pc_3,</span></a>
+<a name="90"><span class="lineNum">      90 </span><span class="lineCov">         15 :   output         io_out_s1_full_pred_0_br_taken_mask_0,</span></a>
+<a name="91"><span class="lineNum">      91 </span><span class="lineCov">         17 :   output         io_out_s1_full_pred_0_br_taken_mask_1,</span></a>
+<a name="92"><span class="lineNum">      92 </span><span class="lineCov">         12 :   output         io_out_s1_full_pred_0_slot_valids_0,</span></a>
+<a name="93"><span class="lineNum">      93 </span><span class="lineCov">          9 :   output         io_out_s1_full_pred_0_slot_valids_1,</span></a>
+<a name="94"><span class="lineNum">      94 </span><span class="lineCov">        615 :   output [40:0]  io_out_s1_full_pred_0_targets_0,</span></a>
+<a name="95"><span class="lineNum">      95 </span><span class="lineCov">        574 :   output [40:0]  io_out_s1_full_pred_0_targets_1,</span></a>
+<a name="96"><span class="lineNum">      96 </span><span class="lineCov">         57 :   output [3:0]   io_out_s1_full_pred_0_offsets_0,</span></a>
+<a name="97"><span class="lineNum">      97 </span><span class="lineCov">         64 :   output [3:0]   io_out_s1_full_pred_0_offsets_1,</span></a>
+<a name="98"><span class="lineNum">      98 </span><span class="lineCov">        596 :   output [40:0]  io_out_s1_full_pred_0_fallThroughAddr,</span></a>
+<a name="99"><span class="lineNum">      99 </span><span class="lineCov">         14 :   output         io_out_s1_full_pred_0_is_br_sharing,</span></a>
+<a name="100"><span class="lineNum">     100 </span><span class="lineCov">         14 :   output         io_out_s1_full_pred_0_hit,</span></a>
+<a name="101"><span class="lineNum">     101 </span><span class="lineCov">         15 :   output         io_out_s1_full_pred_1_br_taken_mask_0,</span></a>
+<a name="102"><span class="lineNum">     102 </span><span class="lineCov">         17 :   output         io_out_s1_full_pred_1_br_taken_mask_1,</span></a>
+<a name="103"><span class="lineNum">     103 </span><span class="lineCov">         12 :   output         io_out_s1_full_pred_1_slot_valids_0,</span></a>
+<a name="104"><span class="lineNum">     104 </span><span class="lineCov">          9 :   output         io_out_s1_full_pred_1_slot_valids_1,</span></a>
+<a name="105"><span class="lineNum">     105 </span><span class="lineCov">        615 :   output [40:0]  io_out_s1_full_pred_1_targets_0,</span></a>
+<a name="106"><span class="lineNum">     106 </span><span class="lineCov">        574 :   output [40:0]  io_out_s1_full_pred_1_targets_1,</span></a>
+<a name="107"><span class="lineNum">     107 </span><span class="lineCov">         57 :   output [3:0]   io_out_s1_full_pred_1_offsets_0,</span></a>
+<a name="108"><span class="lineNum">     108 </span><span class="lineCov">         64 :   output [3:0]   io_out_s1_full_pred_1_offsets_1,</span></a>
+<a name="109"><span class="lineNum">     109 </span><span class="lineCov">        596 :   output [40:0]  io_out_s1_full_pred_1_fallThroughAddr,</span></a>
+<a name="110"><span class="lineNum">     110 </span><span class="lineCov">         14 :   output         io_out_s1_full_pred_1_is_br_sharing,</span></a>
+<a name="111"><span class="lineNum">     111 </span><span class="lineCov">         14 :   output         io_out_s1_full_pred_1_hit,</span></a>
+<a name="112"><span class="lineNum">     112 </span><span class="lineCov">         15 :   output         io_out_s1_full_pred_2_br_taken_mask_0,</span></a>
+<a name="113"><span class="lineNum">     113 </span><span class="lineCov">         17 :   output         io_out_s1_full_pred_2_br_taken_mask_1,</span></a>
+<a name="114"><span class="lineNum">     114 </span><span class="lineCov">         12 :   output         io_out_s1_full_pred_2_slot_valids_0,</span></a>
+<a name="115"><span class="lineNum">     115 </span><span class="lineCov">          9 :   output         io_out_s1_full_pred_2_slot_valids_1,</span></a>
+<a name="116"><span class="lineNum">     116 </span><span class="lineCov">        615 :   output [40:0]  io_out_s1_full_pred_2_targets_0,</span></a>
+<a name="117"><span class="lineNum">     117 </span><span class="lineCov">        574 :   output [40:0]  io_out_s1_full_pred_2_targets_1,</span></a>
+<a name="118"><span class="lineNum">     118 </span><span class="lineCov">         57 :   output [3:0]   io_out_s1_full_pred_2_offsets_0,</span></a>
+<a name="119"><span class="lineNum">     119 </span><span class="lineCov">         64 :   output [3:0]   io_out_s1_full_pred_2_offsets_1,</span></a>
+<a name="120"><span class="lineNum">     120 </span><span class="lineCov">        596 :   output [40:0]  io_out_s1_full_pred_2_fallThroughAddr,</span></a>
+<a name="121"><span class="lineNum">     121 </span><span class="lineCov">         14 :   output         io_out_s1_full_pred_2_is_br_sharing,</span></a>
+<a name="122"><span class="lineNum">     122 </span><span class="lineCov">         14 :   output         io_out_s1_full_pred_2_hit,</span></a>
+<a name="123"><span class="lineNum">     123 </span><span class="lineCov">         15 :   output         io_out_s1_full_pred_3_br_taken_mask_0,</span></a>
+<a name="124"><span class="lineNum">     124 </span><span class="lineCov">         17 :   output         io_out_s1_full_pred_3_br_taken_mask_1,</span></a>
+<a name="125"><span class="lineNum">     125 </span><span class="lineCov">         12 :   output         io_out_s1_full_pred_3_slot_valids_0,</span></a>
+<a name="126"><span class="lineNum">     126 </span><span class="lineCov">          9 :   output         io_out_s1_full_pred_3_slot_valids_1,</span></a>
+<a name="127"><span class="lineNum">     127 </span><span class="lineCov">        615 :   output [40:0]  io_out_s1_full_pred_3_targets_0,</span></a>
+<a name="128"><span class="lineNum">     128 </span><span class="lineCov">        574 :   output [40:0]  io_out_s1_full_pred_3_targets_1,</span></a>
+<a name="129"><span class="lineNum">     129 </span><span class="lineCov">         57 :   output [3:0]   io_out_s1_full_pred_3_offsets_0,</span></a>
+<a name="130"><span class="lineNum">     130 </span><span class="lineCov">         64 :   output [3:0]   io_out_s1_full_pred_3_offsets_1,</span></a>
+<a name="131"><span class="lineNum">     131 </span><span class="lineCov">        596 :   output [40:0]  io_out_s1_full_pred_3_fallThroughAddr,</span></a>
+<a name="132"><span class="lineNum">     132 </span><span class="lineCov">         10 :   output         io_out_s1_full_pred_3_fallThroughErr,</span></a>
+<a name="133"><span class="lineNum">     133 </span><span class="lineCov">         14 :   output         io_out_s1_full_pred_3_is_br_sharing,</span></a>
+<a name="134"><span class="lineNum">     134 </span><span class="lineCov">         14 :   output         io_out_s1_full_pred_3_hit,</span></a>
+<a name="135"><span class="lineNum">     135 </span><span class="lineCov">       9399 :   output [40:0]  io_out_s2_pc_0,</span></a>
+<a name="136"><span class="lineNum">     136 </span><span class="lineCov">       9353 :   output [40:0]  io_out_s2_pc_1,</span></a>
+<a name="137"><span class="lineNum">     137 </span><span class="lineCov">       9356 :   output [40:0]  io_out_s2_pc_2,</span></a>
+<a name="138"><span class="lineNum">     138 </span><span class="lineCov">       9388 :   output [40:0]  io_out_s2_pc_3,</span></a>
+<a name="139"><span class="lineNum">     139 </span><span class="lineCov">         79 :   output         io_out_s2_full_pred_0_br_taken_mask_0,</span></a>
+<a name="140"><span class="lineNum">     140 </span><span class="lineCov">         69 :   output         io_out_s2_full_pred_0_br_taken_mask_1,</span></a>
+<a name="141"><span class="lineNum">     141 </span><span class="lineCov">         31 :   output         io_out_s2_full_pred_0_slot_valids_0,</span></a>
+<a name="142"><span class="lineNum">     142 </span><span class="lineCov">         30 :   output         io_out_s2_full_pred_0_slot_valids_1,</span></a>
+<a name="143"><span class="lineNum">     143 </span><span class="lineCov">       1189 :   output [40:0]  io_out_s2_full_pred_0_targets_0,</span></a>
+<a name="144"><span class="lineNum">     144 </span><span class="lineCov">       1454 :   output [40:0]  io_out_s2_full_pred_0_targets_1,</span></a>
+<a name="145"><span class="lineNum">     145 </span><span class="lineCov">        116 :   output [3:0]   io_out_s2_full_pred_0_offsets_0,</span></a>
+<a name="146"><span class="lineNum">     146 </span><span class="lineCov">        107 :   output [3:0]   io_out_s2_full_pred_0_offsets_1,</span></a>
+<a name="147"><span class="lineNum">     147 </span><span class="lineCov">       9456 :   output [40:0]  io_out_s2_full_pred_0_fallThroughAddr,</span></a>
+<a name="148"><span class="lineNum">     148 </span><span class="lineCov">         31 :   output         io_out_s2_full_pred_0_is_br_sharing,</span></a>
+<a name="149"><span class="lineNum">     149 </span><span class="lineCov">         18 :   output         io_out_s2_full_pred_0_hit,</span></a>
+<a name="150"><span class="lineNum">     150 </span><span class="lineCov">         59 :   output         io_out_s2_full_pred_1_br_taken_mask_0,</span></a>
+<a name="151"><span class="lineNum">     151 </span><span class="lineCov">         71 :   output         io_out_s2_full_pred_1_br_taken_mask_1,</span></a>
+<a name="152"><span class="lineNum">     152 </span><span class="lineCov">         24 :   output         io_out_s2_full_pred_1_slot_valids_0,</span></a>
+<a name="153"><span class="lineNum">     153 </span><span class="lineCov">         24 :   output         io_out_s2_full_pred_1_slot_valids_1,</span></a>
+<a name="154"><span class="lineNum">     154 </span><span class="lineCov">       1278 :   output [40:0]  io_out_s2_full_pred_1_targets_0,</span></a>
+<a name="155"><span class="lineNum">     155 </span><span class="lineCov">       1345 :   output [40:0]  io_out_s2_full_pred_1_targets_1,</span></a>
+<a name="156"><span class="lineNum">     156 </span><span class="lineCov">        108 :   output [3:0]   io_out_s2_full_pred_1_offsets_0,</span></a>
+<a name="157"><span class="lineNum">     157 </span><span class="lineCov">        119 :   output [3:0]   io_out_s2_full_pred_1_offsets_1,</span></a>
+<a name="158"><span class="lineNum">     158 </span><span class="lineCov">       9458 :   output [40:0]  io_out_s2_full_pred_1_fallThroughAddr,</span></a>
+<a name="159"><span class="lineNum">     159 </span><span class="lineCov">         17 :   output         io_out_s2_full_pred_1_is_br_sharing,</span></a>
+<a name="160"><span class="lineNum">     160 </span><span class="lineCov">         25 :   output         io_out_s2_full_pred_1_hit,</span></a>
+<a name="161"><span class="lineNum">     161 </span><span class="lineCov">         72 :   output         io_out_s2_full_pred_2_br_taken_mask_0,</span></a>
+<a name="162"><span class="lineNum">     162 </span><span class="lineCov">         58 :   output         io_out_s2_full_pred_2_br_taken_mask_1,</span></a>
+<a name="163"><span class="lineNum">     163 </span><span class="lineCov">         31 :   output         io_out_s2_full_pred_2_slot_valids_0,</span></a>
+<a name="164"><span class="lineNum">     164 </span><span class="lineCov">         28 :   output         io_out_s2_full_pred_2_slot_valids_1,</span></a>
+<a name="165"><span class="lineNum">     165 </span><span class="lineCov">       1211 :   output [40:0]  io_out_s2_full_pred_2_targets_0,</span></a>
+<a name="166"><span class="lineNum">     166 </span><span class="lineCov">       1384 :   output [40:0]  io_out_s2_full_pred_2_targets_1,</span></a>
+<a name="167"><span class="lineNum">     167 </span><span class="lineCov">        114 :   output [3:0]   io_out_s2_full_pred_2_offsets_0,</span></a>
+<a name="168"><span class="lineNum">     168 </span><span class="lineCov">        120 :   output [3:0]   io_out_s2_full_pred_2_offsets_1,</span></a>
+<a name="169"><span class="lineNum">     169 </span><span class="lineCov">       9409 :   output [40:0]  io_out_s2_full_pred_2_fallThroughAddr,</span></a>
+<a name="170"><span class="lineNum">     170 </span><span class="lineCov">         23 :   output         io_out_s2_full_pred_2_is_br_sharing,</span></a>
+<a name="171"><span class="lineNum">     171 </span><span class="lineCov">         29 :   output         io_out_s2_full_pred_2_hit,</span></a>
+<a name="172"><span class="lineNum">     172 </span><span class="lineCov">         79 :   output         io_out_s2_full_pred_3_br_taken_mask_0,</span></a>
+<a name="173"><span class="lineNum">     173 </span><span class="lineCov">         76 :   output         io_out_s2_full_pred_3_br_taken_mask_1,</span></a>
+<a name="174"><span class="lineNum">     174 </span><span class="lineCov">         27 :   output         io_out_s2_full_pred_3_slot_valids_0,</span></a>
+<a name="175"><span class="lineNum">     175 </span><span class="lineCov">         30 :   output         io_out_s2_full_pred_3_slot_valids_1,</span></a>
+<a name="176"><span class="lineNum">     176 </span><span class="lineCov">       1252 :   output [40:0]  io_out_s2_full_pred_3_targets_0,</span></a>
+<a name="177"><span class="lineNum">     177 </span><span class="lineCov">       1433 :   output [40:0]  io_out_s2_full_pred_3_targets_1,</span></a>
+<a name="178"><span class="lineNum">     178 </span><span class="lineCov">        119 :   output [3:0]   io_out_s2_full_pred_3_offsets_0,</span></a>
+<a name="179"><span class="lineNum">     179 </span><span class="lineCov">        105 :   output [3:0]   io_out_s2_full_pred_3_offsets_1,</span></a>
+<a name="180"><span class="lineNum">     180 </span><span class="lineCov">       9476 :   output [40:0]  io_out_s2_full_pred_3_fallThroughAddr,</span></a>
+<a name="181"><span class="lineNum">     181 </span><span class="lineCov">         41 :   output         io_out_s2_full_pred_3_fallThroughErr,</span></a>
+<a name="182"><span class="lineNum">     182 </span><span class="lineCov">         22 :   output         io_out_s2_full_pred_3_is_br_sharing,</span></a>
+<a name="183"><span class="lineNum">     183 </span><span class="lineCov">         18 :   output         io_out_s2_full_pred_3_hit,</span></a>
+<a name="184"><span class="lineNum">     184 </span><span class="lineCov">       9337 :   output [40:0]  io_out_s3_pc_0,</span></a>
+<a name="185"><span class="lineNum">     185 </span><span class="lineCov">       9352 :   output [40:0]  io_out_s3_pc_1,</span></a>
+<a name="186"><span class="lineNum">     186 </span><span class="lineCov">       9331 :   output [40:0]  io_out_s3_pc_2,</span></a>
+<a name="187"><span class="lineNum">     187 </span><span class="lineCov">       9336 :   output [40:0]  io_out_s3_pc_3,</span></a>
+<a name="188"><span class="lineNum">     188 </span><span class="lineCov">         82 :   output         io_out_s3_full_pred_0_br_taken_mask_0,</span></a>
+<a name="189"><span class="lineNum">     189 </span><span class="lineCov">         70 :   output         io_out_s3_full_pred_0_br_taken_mask_1,</span></a>
+<a name="190"><span class="lineNum">     190 </span><span class="lineCov">         30 :   output         io_out_s3_full_pred_0_slot_valids_0,</span></a>
+<a name="191"><span class="lineNum">     191 </span><span class="lineCov">         33 :   output         io_out_s3_full_pred_0_slot_valids_1,</span></a>
+<a name="192"><span class="lineNum">     192 </span><span class="lineCov">       1241 :   output [40:0]  io_out_s3_full_pred_0_targets_0,</span></a>
+<a name="193"><span class="lineNum">     193 </span><span class="lineCov">       1451 :   output [40:0]  io_out_s3_full_pred_0_targets_1,</span></a>
+<a name="194"><span class="lineNum">     194 </span><span class="lineCov">       9423 :   output [40:0]  io_out_s3_full_pred_0_fallThroughAddr,</span></a>
+<a name="195"><span class="lineNum">     195 </span><span class="lineCov">         39 :   output         io_out_s3_full_pred_0_fallThroughErr,</span></a>
+<a name="196"><span class="lineNum">     196 </span><span class="lineCov">         26 :   output         io_out_s3_full_pred_0_is_br_sharing,</span></a>
+<a name="197"><span class="lineNum">     197 </span><span class="lineCov">         24 :   output         io_out_s3_full_pred_0_hit,</span></a>
+<a name="198"><span class="lineNum">     198 </span><span class="lineCov">         80 :   output         io_out_s3_full_pred_1_br_taken_mask_0,</span></a>
+<a name="199"><span class="lineNum">     199 </span><span class="lineCov">         75 :   output         io_out_s3_full_pred_1_br_taken_mask_1,</span></a>
+<a name="200"><span class="lineNum">     200 </span><span class="lineCov">         30 :   output         io_out_s3_full_pred_1_slot_valids_0,</span></a>
+<a name="201"><span class="lineNum">     201 </span><span class="lineCov">         39 :   output         io_out_s3_full_pred_1_slot_valids_1,</span></a>
+<a name="202"><span class="lineNum">     202 </span><span class="lineCov">       1262 :   output [40:0]  io_out_s3_full_pred_1_targets_0,</span></a>
+<a name="203"><span class="lineNum">     203 </span><span class="lineCov">       1497 :   output [40:0]  io_out_s3_full_pred_1_targets_1,</span></a>
+<a name="204"><span class="lineNum">     204 </span><span class="lineCov">       9377 :   output [40:0]  io_out_s3_full_pred_1_fallThroughAddr,</span></a>
+<a name="205"><span class="lineNum">     205 </span><span class="lineCov">         35 :   output         io_out_s3_full_pred_1_fallThroughErr,</span></a>
+<a name="206"><span class="lineNum">     206 </span><span class="lineCov">         24 :   output         io_out_s3_full_pred_1_is_br_sharing,</span></a>
+<a name="207"><span class="lineNum">     207 </span><span class="lineCov">         33 :   output         io_out_s3_full_pred_1_hit,</span></a>
+<a name="208"><span class="lineNum">     208 </span><span class="lineCov">         86 :   output         io_out_s3_full_pred_2_br_taken_mask_0,</span></a>
+<a name="209"><span class="lineNum">     209 </span><span class="lineCov">         70 :   output         io_out_s3_full_pred_2_br_taken_mask_1,</span></a>
+<a name="210"><span class="lineNum">     210 </span><span class="lineCov">         26 :   output         io_out_s3_full_pred_2_slot_valids_0,</span></a>
+<a name="211"><span class="lineNum">     211 </span><span class="lineCov">         30 :   output         io_out_s3_full_pred_2_slot_valids_1,</span></a>
+<a name="212"><span class="lineNum">     212 </span><span class="lineCov">       1286 :   output [40:0]  io_out_s3_full_pred_2_targets_0,</span></a>
+<a name="213"><span class="lineNum">     213 </span><span class="lineCov">       1563 :   output [40:0]  io_out_s3_full_pred_2_targets_1,</span></a>
+<a name="214"><span class="lineNum">     214 </span><span class="lineCov">       9424 :   output [40:0]  io_out_s3_full_pred_2_fallThroughAddr,</span></a>
+<a name="215"><span class="lineNum">     215 </span><span class="lineCov">         35 :   output         io_out_s3_full_pred_2_fallThroughErr,</span></a>
+<a name="216"><span class="lineNum">     216 </span><span class="lineCov">         21 :   output         io_out_s3_full_pred_2_is_br_sharing,</span></a>
+<a name="217"><span class="lineNum">     217 </span><span class="lineCov">         29 :   output         io_out_s3_full_pred_2_hit,</span></a>
+<a name="218"><span class="lineNum">     218 </span><span class="lineCov">         75 :   output         io_out_s3_full_pred_3_br_taken_mask_0,</span></a>
+<a name="219"><span class="lineNum">     219 </span><span class="lineCov">         76 :   output         io_out_s3_full_pred_3_br_taken_mask_1,</span></a>
+<a name="220"><span class="lineNum">     220 </span><span class="lineCov">         41 :   output         io_out_s3_full_pred_3_slot_valids_0,</span></a>
+<a name="221"><span class="lineNum">     221 </span><span class="lineCov">         42 :   output         io_out_s3_full_pred_3_slot_valids_1,</span></a>
+<a name="222"><span class="lineNum">     222 </span><span class="lineCov">       1231 :   output [40:0]  io_out_s3_full_pred_3_targets_0,</span></a>
+<a name="223"><span class="lineNum">     223 </span><span class="lineCov">       1446 :   output [40:0]  io_out_s3_full_pred_3_targets_1,</span></a>
+<a name="224"><span class="lineNum">     224 </span><span class="lineCov">        136 :   output [3:0]   io_out_s3_full_pred_3_offsets_0,</span></a>
+<a name="225"><span class="lineNum">     225 </span><span class="lineCov">        131 :   output [3:0]   io_out_s3_full_pred_3_offsets_1,</span></a>
+<a name="226"><span class="lineNum">     226 </span><span class="lineCov">       9391 :   output [40:0]  io_out_s3_full_pred_3_fallThroughAddr,</span></a>
+<a name="227"><span class="lineNum">     227 </span><span class="lineCov">         41 :   output         io_out_s3_full_pred_3_fallThroughErr,</span></a>
+<a name="228"><span class="lineNum">     228 </span><span class="lineCov">         30 :   output         io_out_s3_full_pred_3_is_br_sharing,</span></a>
+<a name="229"><span class="lineNum">     229 </span><span class="lineCov">         27 :   output         io_out_s3_full_pred_3_hit,</span></a>
+<a name="230"><span class="lineNum">     230 </span><span class="lineCov">      11660 :   output [222:0] io_out_last_stage_meta,</span></a>
+<a name="231"><span class="lineNum">     231 </span><span class="lineCov">        149 :   output [3:0]   io_out_last_stage_spec_info_ssp,</span></a>
+<a name="232"><span class="lineNum">     232 </span><span class="lineCov">         80 :   output [1:0]   io_out_last_stage_spec_info_sctr,</span></a>
+<a name="233"><span class="lineNum">     233 </span><span class="lineCov">         41 :   output         io_out_last_stage_spec_info_TOSW_flag,</span></a>
+<a name="234"><span class="lineNum">     234 </span><span class="lineCov">        183 :   output [4:0]   io_out_last_stage_spec_info_TOSW_value,</span></a>
+<a name="235"><span class="lineNum">     235 </span><span class="lineCov">         40 :   output         io_out_last_stage_spec_info_TOSR_flag,</span></a>
+<a name="236"><span class="lineNum">     236 </span><span class="lineCov">        214 :   output [4:0]   io_out_last_stage_spec_info_TOSR_value,</span></a>
+<a name="237"><span class="lineNum">     237 </span><span class="lineCov">         31 :   output         io_out_last_stage_spec_info_NOS_flag,</span></a>
+<a name="238"><span class="lineNum">     238 </span><span class="lineCov">        160 :   output [4:0]   io_out_last_stage_spec_info_NOS_value,</span></a>
+<a name="239"><span class="lineNum">     239 </span><span class="lineCov">       1348 :   output [40:0]  io_out_last_stage_spec_info_topAddr,</span></a>
+<a name="240"><span class="lineNum">     240 </span><span class="lineCov">         33 :   output         io_out_last_stage_ftb_entry_valid,</span></a>
+<a name="241"><span class="lineNum">     241 </span><span class="lineCov">        119 :   output [3:0]   io_out_last_stage_ftb_entry_brSlots_0_offset,</span></a>
+<a name="242"><span class="lineNum">     242 </span><span class="lineCov">        411 :   output [11:0]  io_out_last_stage_ftb_entry_brSlots_0_lower,</span></a>
+<a name="243"><span class="lineNum">     243 </span><span class="lineCov">         59 :   output [1:0]   io_out_last_stage_ftb_entry_brSlots_0_tarStat,</span></a>
+<a name="244"><span class="lineNum">     244 </span><span class="lineCov">         34 :   output         io_out_last_stage_ftb_entry_brSlots_0_sharing,</span></a>
+<a name="245"><span class="lineNum">     245 </span><span class="lineCov">         29 :   output         io_out_last_stage_ftb_entry_brSlots_0_valid,</span></a>
+<a name="246"><span class="lineNum">     246 </span><span class="lineCov">        125 :   output [3:0]   io_out_last_stage_ftb_entry_tailSlot_offset,</span></a>
+<a name="247"><span class="lineNum">     247 </span><span class="lineCov">        676 :   output [19:0]  io_out_last_stage_ftb_entry_tailSlot_lower,</span></a>
+<a name="248"><span class="lineNum">     248 </span><span class="lineCov">         70 :   output [1:0]   io_out_last_stage_ftb_entry_tailSlot_tarStat,</span></a>
+<a name="249"><span class="lineNum">     249 </span><span class="lineCov">         30 :   output         io_out_last_stage_ftb_entry_tailSlot_sharing,</span></a>
+<a name="250"><span class="lineNum">     250 </span><span class="lineCov">         31 :   output         io_out_last_stage_ftb_entry_tailSlot_valid,</span></a>
+<a name="251"><span class="lineNum">     251 </span><span class="lineCov">        140 :   output [3:0]   io_out_last_stage_ftb_entry_pftAddr,</span></a>
+<a name="252"><span class="lineNum">     252 </span><span class="lineCov">         33 :   output         io_out_last_stage_ftb_entry_carry,</span></a>
+<a name="253"><span class="lineNum">     253 </span><span class="lineCov">         35 :   output         io_out_last_stage_ftb_entry_isCall,</span></a>
+<a name="254"><span class="lineNum">     254 </span><span class="lineCov">         29 :   output         io_out_last_stage_ftb_entry_isRet,</span></a>
+<a name="255"><span class="lineNum">     255 </span><span class="lineCov">         40 :   output         io_out_last_stage_ftb_entry_isJalr,</span></a>
+<a name="256"><span class="lineNum">     256 </span><span class="lineCov">         36 :   output         io_out_last_stage_ftb_entry_last_may_be_rvi_call,</span></a>
+<a name="257"><span class="lineNum">     257 </span><span class="lineCov">         27 :   output         io_out_last_stage_ftb_entry_always_taken_0,</span></a>
+<a name="258"><span class="lineNum">     258 </span><span class="lineCov">         32 :   output         io_out_last_stage_ftb_entry_always_taken_1,</span></a>
+<a name="259"><span class="lineNum">     259 </span><span class="lineCov">         67 :   input          io_ctrl_ubtb_enable,</span></a>
+<a name="260"><span class="lineNum">     260 </span><span class="lineCov">         65 :   input          io_ctrl_btb_enable,</span></a>
+<a name="261"><span class="lineNum">     261 </span><span class="lineCov">         63 :   input          io_ctrl_tage_enable,</span></a>
+<a name="262"><span class="lineNum">     262 </span><span class="lineCov">         75 :   input          io_ctrl_sc_enable,</span></a>
+<a name="263"><span class="lineNum">     263 </span><span class="lineCov">         69 :   input          io_ctrl_ras_enable,</span></a>
+<a name="264"><span class="lineNum">     264 </span><span class="lineCov">         75 :   input          io_s0_fire_0,</span></a>
+<a name="265"><span class="lineNum">     265 </span><span class="lineCov">         76 :   input          io_s0_fire_1,</span></a>
+<a name="266"><span class="lineNum">     266 </span><span class="lineCov">         76 :   input          io_s0_fire_2,</span></a>
+<a name="267"><span class="lineNum">     267 </span><span class="lineCov">         73 :   input          io_s0_fire_3,</span></a>
+<a name="268"><span class="lineNum">     268 </span><span class="lineCov">        133 :   input          io_s1_fire_0,</span></a>
+<a name="269"><span class="lineNum">     269 </span><span class="lineCov">        131 :   input          io_s1_fire_1,</span></a>
+<a name="270"><span class="lineNum">     270 </span><span class="lineCov">        135 :   input          io_s1_fire_2,</span></a>
+<a name="271"><span class="lineNum">     271 </span><span class="lineCov">        133 :   input          io_s1_fire_3,</span></a>
+<a name="272"><span class="lineNum">     272 </span><span class="lineCov">        127 :   input          io_s2_fire_0,</span></a>
+<a name="273"><span class="lineNum">     273 </span><span class="lineCov">        127 :   input          io_s2_fire_1,</span></a>
+<a name="274"><span class="lineNum">     274 </span><span class="lineCov">        127 :   input          io_s2_fire_2,</span></a>
+<a name="275"><span class="lineNum">     275 </span><span class="lineCov">        127 :   input          io_s2_fire_3,</span></a>
+<a name="276"><span class="lineNum">     276 </span><span class="lineCov">        127 :   input          io_s3_fire_2,</span></a>
+<a name="277"><span class="lineNum">     277 </span><span class="lineCov">         20 :   input          io_s3_redirect_2,</span></a>
+<a name="278"><span class="lineNum">     278 </span><span class="lineCov">         78 :   output         io_s1_ready,</span></a>
+<a name="279"><span class="lineNum">     279 </span><span class="lineCov">        105 :   input          io_update_valid,</span></a>
+<a name="280"><span class="lineNum">     280 </span><span class="lineCov">       1143 :   input  [40:0]  io_update_bits_pc,</span></a>
+<a name="281"><span class="lineNum">     281 </span><span class="lineCov">        310 :   input  [10:0]  io_update_bits_spec_info_folded_hist_hist_17_folded_hist,</span></a>
+<a name="282"><span class="lineNum">     282 </span><span class="lineCov">        322 :   input  [10:0]  io_update_bits_spec_info_folded_hist_hist_16_folded_hist,</span></a>
+<a name="283"><span class="lineNum">     283 </span><span class="lineCov">        196 :   input  [6:0]   io_update_bits_spec_info_folded_hist_hist_15_folded_hist,</span></a>
+<a name="284"><span class="lineNum">     284 </span><span class="lineCov">        243 :   input  [7:0]   io_update_bits_spec_info_folded_hist_hist_14_folded_hist,</span></a>
+<a name="285"><span class="lineNum">     285 </span><span class="lineCov">        250 :   input  [8:0]   io_update_bits_spec_info_folded_hist_hist_13_folded_hist,</span></a>
+<a name="286"><span class="lineNum">     286 </span><span class="lineCov">        108 :   input  [3:0]   io_update_bits_spec_info_folded_hist_hist_12_folded_hist,</span></a>
+<a name="287"><span class="lineNum">     287 </span><span class="lineCov">        240 :   input  [7:0]   io_update_bits_spec_info_folded_hist_hist_11_folded_hist,</span></a>
+<a name="288"><span class="lineNum">     288 </span><span class="lineCov">        282 :   input  [8:0]   io_update_bits_spec_info_folded_hist_hist_10_folded_hist,</span></a>
+<a name="289"><span class="lineNum">     289 </span><span class="lineCov">        197 :   input  [6:0]   io_update_bits_spec_info_folded_hist_hist_9_folded_hist,</span></a>
+<a name="290"><span class="lineNum">     290 </span><span class="lineCov">        244 :   input  [7:0]   io_update_bits_spec_info_folded_hist_hist_8_folded_hist,</span></a>
+<a name="291"><span class="lineNum">     291 </span><span class="lineCov">        217 :   input  [6:0]   io_update_bits_spec_info_folded_hist_hist_7_folded_hist,</span></a>
+<a name="292"><span class="lineNum">     292 </span><span class="lineCov">        285 :   input  [8:0]   io_update_bits_spec_info_folded_hist_hist_6_folded_hist,</span></a>
+<a name="293"><span class="lineNum">     293 </span><span class="lineCov">        202 :   input  [6:0]   io_update_bits_spec_info_folded_hist_hist_5_folded_hist,</span></a>
+<a name="294"><span class="lineNum">     294 </span><span class="lineCov">        219 :   input  [7:0]   io_update_bits_spec_info_folded_hist_hist_4_folded_hist,</span></a>
+<a name="295"><span class="lineNum">     295 </span><span class="lineCov">        233 :   input  [7:0]   io_update_bits_spec_info_folded_hist_hist_3_folded_hist,</span></a>
+<a name="296"><span class="lineNum">     296 </span><span class="lineCov">        231 :   input  [7:0]   io_update_bits_spec_info_folded_hist_hist_2_folded_hist,</span></a>
+<a name="297"><span class="lineNum">     297 </span><span class="lineCov">        339 :   input  [10:0]  io_update_bits_spec_info_folded_hist_hist_1_folded_hist,</span></a>
+<a name="298"><span class="lineNum">     298 </span><span class="lineCov">         33 :   input          io_update_bits_ftb_entry_valid,</span></a>
+<a name="299"><span class="lineNum">     299 </span><span class="lineCov">        122 :   input  [3:0]   io_update_bits_ftb_entry_brSlots_0_offset,</span></a>
+<a name="300"><span class="lineNum">     300 </span><span class="lineCov">        337 :   input  [11:0]  io_update_bits_ftb_entry_brSlots_0_lower,</span></a>
+<a name="301"><span class="lineNum">     301 </span><span class="lineCov">         65 :   input  [1:0]   io_update_bits_ftb_entry_brSlots_0_tarStat,</span></a>
+<a name="302"><span class="lineNum">     302 </span><span class="lineCov">         33 :   input          io_update_bits_ftb_entry_brSlots_0_sharing,</span></a>
+<a name="303"><span class="lineNum">     303 </span><span class="lineCov">         35 :   input          io_update_bits_ftb_entry_brSlots_0_valid,</span></a>
+<a name="304"><span class="lineNum">     304 </span><span class="lineCov">        137 :   input  [3:0]   io_update_bits_ftb_entry_tailSlot_offset,</span></a>
+<a name="305"><span class="lineNum">     305 </span><span class="lineCov">        552 :   input  [19:0]  io_update_bits_ftb_entry_tailSlot_lower,</span></a>
+<a name="306"><span class="lineNum">     306 </span><span class="lineCov">         63 :   input  [1:0]   io_update_bits_ftb_entry_tailSlot_tarStat,</span></a>
+<a name="307"><span class="lineNum">     307 </span><span class="lineCov">         33 :   input          io_update_bits_ftb_entry_tailSlot_sharing,</span></a>
+<a name="308"><span class="lineNum">     308 </span><span class="lineCov">         28 :   input          io_update_bits_ftb_entry_tailSlot_valid,</span></a>
+<a name="309"><span class="lineNum">     309 </span><span class="lineCov">        152 :   input  [3:0]   io_update_bits_ftb_entry_pftAddr,</span></a>
+<a name="310"><span class="lineNum">     310 </span><span class="lineCov">         34 :   input          io_update_bits_ftb_entry_carry,</span></a>
+<a name="311"><span class="lineNum">     311 </span><span class="lineCov">         39 :   input          io_update_bits_ftb_entry_isCall,</span></a>
+<a name="312"><span class="lineNum">     312 </span><span class="lineCov">         36 :   input          io_update_bits_ftb_entry_isRet,</span></a>
+<a name="313"><span class="lineNum">     313 </span><span class="lineCov">         37 :   input          io_update_bits_ftb_entry_isJalr,</span></a>
+<a name="314"><span class="lineNum">     314 </span><span class="lineCov">         41 :   input          io_update_bits_ftb_entry_last_may_be_rvi_call,</span></a>
+<a name="315"><span class="lineNum">     315 </span><span class="lineCov">         32 :   input          io_update_bits_ftb_entry_always_taken_0,</span></a>
+<a name="316"><span class="lineNum">     316 </span><span class="lineCov">         33 :   input          io_update_bits_ftb_entry_always_taken_1,</span></a>
+<a name="317"><span class="lineNum">     317 </span><span class="lineCov">         22 :   input          io_update_bits_cfi_idx_valid,</span></a>
+<a name="318"><span class="lineNum">     318 </span><span class="lineCov">        155 :   input  [3:0]   io_update_bits_cfi_idx_bits,</span></a>
+<a name="319"><span class="lineNum">     319 </span><span class="lineCov">         24 :   input          io_update_bits_br_taken_mask_0,</span></a>
+<a name="320"><span class="lineNum">     320 </span><span class="lineCov">         40 :   input          io_update_bits_br_taken_mask_1,</span></a>
+<a name="321"><span class="lineNum">     321 </span><span class="lineCov">         40 :   input          io_update_bits_jmp_taken,</span></a>
+<a name="322"><span class="lineNum">     322 </span><span class="lineCov">         45 :   input          io_update_bits_mispred_mask_0,</span></a>
+<a name="323"><span class="lineNum">     323 </span><span class="lineCov">         30 :   input          io_update_bits_mispred_mask_1,</span></a>
+<a name="324"><span class="lineNum">     324 </span><span class="lineCov">         42 :   input          io_update_bits_mispred_mask_2,</span></a>
+<a name="325"><span class="lineNum">     325 </span><span class="lineCov">         46 :   input          io_update_bits_old_entry,</span></a>
+<a name="326"><span class="lineNum">     326 </span><span class="lineCov">       6212 :   input  [222:0] io_update_bits_meta,</span></a>
+<a name="327"><span class="lineNum">     327 </span><span class="lineCov">       1185 :   input  [40:0]  io_update_bits_full_target,</span></a>
+<a name="328"><span class="lineNum">     328 </span><span class="lineCov">         84 :   input          io_redirect_valid,</span></a>
+<a name="329"><span class="lineNum">     329 </span><span class="lineCov">         28 :   input          io_redirect_bits_level,</span></a>
+<a name="330"><span class="lineNum">     330 </span><span class="lineCov">       1207 :   input  [40:0]  io_redirect_bits_cfiUpdate_pc,</span></a>
+<a name="331"><span class="lineNum">     331 </span><span class="lineCov">         27 :   input          io_redirect_bits_cfiUpdate_pd_isRVC,</span></a>
+<a name="332"><span class="lineNum">     332 </span><span class="lineCov">         37 :   input          io_redirect_bits_cfiUpdate_pd_isCall,</span></a>
+<a name="333"><span class="lineNum">     333 </span><span class="lineCov">         37 :   input          io_redirect_bits_cfiUpdate_pd_isRet,</span></a>
+<a name="334"><span class="lineNum">     334 </span><span class="lineCov">        115 :   input  [3:0]   io_redirect_bits_cfiUpdate_ssp,</span></a>
+<a name="335"><span class="lineNum">     335 </span><span class="lineCov">         73 :   input  [1:0]   io_redirect_bits_cfiUpdate_sctr,</span></a>
+<a name="336"><span class="lineNum">     336 </span><span class="lineCov">         43 :   input          io_redirect_bits_cfiUpdate_TOSW_flag,</span></a>
+<a name="337"><span class="lineNum">     337 </span><span class="lineCov">        147 :   input  [4:0]   io_redirect_bits_cfiUpdate_TOSW_value,</span></a>
+<a name="338"><span class="lineNum">     338 </span><span class="lineCov">         42 :   input          io_redirect_bits_cfiUpdate_TOSR_flag,</span></a>
+<a name="339"><span class="lineNum">     339 </span><span class="lineCov">        138 :   input  [4:0]   io_redirect_bits_cfiUpdate_TOSR_value,</span></a>
+<a name="340"><span class="lineNum">     340 </span><span class="lineCov">         40 :   input          io_redirect_bits_cfiUpdate_NOS_flag,</span></a>
+<a name="341"><span class="lineNum">     341 </span><span class="lineCov">        150 :   input  [4:0]   io_redirect_bits_cfiUpdate_NOS_value,</span></a>
+<a name="342"><span class="lineNum">     342 </span><span class="lineCov">        301 :   output [5:0]   io_perf_0_value,</span></a>
+<a name="343"><span class="lineNum">     343 </span><span class="lineCov">        389 :   output [5:0]   io_perf_1_value,</span></a>
+<a name="344"><span class="lineNum">     344 </span><span class="lineCov">        341 :   output [5:0]   io_perf_2_value,</span></a>
+<a name="345"><span class="lineNum">     345 </span><span class="lineCov">        331 :   output [5:0]   io_perf_3_value,</span></a>
+<a name="346"><span class="lineNum">     346 </span><span class="lineCov">        308 :   output [5:0]   io_perf_4_value,</span></a>
+<a name="347"><span class="lineNum">     347 </span><span class="lineCov">        296 :   output [5:0]   io_perf_5_value,</span></a>
+<a name="348"><span class="lineNum">     348 </span><span class="lineCov">        352 :   output [5:0]   io_perf_6_value</span></a>
+<a name="349"><span class="lineNum">     349 </span>            : );</a>
+<a name="350"><span class="lineNum">     350 </span>            : </a>
+<a name="351"><span class="lineNum">     351 </span>            :   wire         _ras_io_ctrl_delay_io_out_ras_enable;</a>
+<a name="352"><span class="lineNum">     352 </span>            :   wire         _ftb_io_ctrl_delay_io_out_btb_enable;</a>
+<a name="353"><span class="lineNum">     353 </span>            :   wire         _tage_io_ctrl_delay_io_out_tage_enable;</a>
+<a name="354"><span class="lineNum">     354 </span>            :   wire         _tage_io_ctrl_delay_io_out_sc_enable;</a>
+<a name="355"><span class="lineNum">     355 </span>            :   wire         _ubtb_io_ctrl_delay_io_out_ubtb_enable;</a>
+<a name="356"><span class="lineNum">     356 </span>            :   wire         _ittage_io_out_s2_full_pred_0_br_taken_mask_0;</a>
+<a name="357"><span class="lineNum">     357 </span>            :   wire         _ittage_io_out_s2_full_pred_0_br_taken_mask_1;</a>
+<a name="358"><span class="lineNum">     358 </span>            :   wire         _ittage_io_out_s2_full_pred_0_slot_valids_0;</a>
+<a name="359"><span class="lineNum">     359 </span>            :   wire         _ittage_io_out_s2_full_pred_0_slot_valids_1;</a>
+<a name="360"><span class="lineNum">     360 </span>            :   wire [40:0]  _ittage_io_out_s2_full_pred_0_targets_0;</a>
+<a name="361"><span class="lineNum">     361 </span>            :   wire [40:0]  _ittage_io_out_s2_full_pred_0_targets_1;</a>
+<a name="362"><span class="lineNum">     362 </span>            :   wire [40:0]  _ittage_io_out_s2_full_pred_0_jalr_target;</a>
+<a name="363"><span class="lineNum">     363 </span>            :   wire [3:0]   _ittage_io_out_s2_full_pred_0_offsets_0;</a>
+<a name="364"><span class="lineNum">     364 </span>            :   wire [3:0]   _ittage_io_out_s2_full_pred_0_offsets_1;</a>
+<a name="365"><span class="lineNum">     365 </span>            :   wire [40:0]  _ittage_io_out_s2_full_pred_0_fallThroughAddr;</a>
+<a name="366"><span class="lineNum">     366 </span>            :   wire         _ittage_io_out_s2_full_pred_0_is_br_sharing;</a>
+<a name="367"><span class="lineNum">     367 </span>            :   wire         _ittage_io_out_s2_full_pred_0_hit;</a>
+<a name="368"><span class="lineNum">     368 </span>            :   wire         _ittage_io_out_s2_full_pred_1_br_taken_mask_0;</a>
+<a name="369"><span class="lineNum">     369 </span>            :   wire         _ittage_io_out_s2_full_pred_1_br_taken_mask_1;</a>
+<a name="370"><span class="lineNum">     370 </span>            :   wire         _ittage_io_out_s2_full_pred_1_slot_valids_0;</a>
+<a name="371"><span class="lineNum">     371 </span>            :   wire         _ittage_io_out_s2_full_pred_1_slot_valids_1;</a>
+<a name="372"><span class="lineNum">     372 </span>            :   wire [40:0]  _ittage_io_out_s2_full_pred_1_targets_0;</a>
+<a name="373"><span class="lineNum">     373 </span>            :   wire [40:0]  _ittage_io_out_s2_full_pred_1_targets_1;</a>
+<a name="374"><span class="lineNum">     374 </span>            :   wire [40:0]  _ittage_io_out_s2_full_pred_1_jalr_target;</a>
+<a name="375"><span class="lineNum">     375 </span>            :   wire [3:0]   _ittage_io_out_s2_full_pred_1_offsets_0;</a>
+<a name="376"><span class="lineNum">     376 </span>            :   wire [3:0]   _ittage_io_out_s2_full_pred_1_offsets_1;</a>
+<a name="377"><span class="lineNum">     377 </span>            :   wire [40:0]  _ittage_io_out_s2_full_pred_1_fallThroughAddr;</a>
+<a name="378"><span class="lineNum">     378 </span>            :   wire         _ittage_io_out_s2_full_pred_1_is_br_sharing;</a>
+<a name="379"><span class="lineNum">     379 </span>            :   wire         _ittage_io_out_s2_full_pred_1_hit;</a>
+<a name="380"><span class="lineNum">     380 </span>            :   wire         _ittage_io_out_s2_full_pred_2_br_taken_mask_0;</a>
+<a name="381"><span class="lineNum">     381 </span>            :   wire         _ittage_io_out_s2_full_pred_2_br_taken_mask_1;</a>
+<a name="382"><span class="lineNum">     382 </span>            :   wire         _ittage_io_out_s2_full_pred_2_slot_valids_0;</a>
+<a name="383"><span class="lineNum">     383 </span>            :   wire         _ittage_io_out_s2_full_pred_2_slot_valids_1;</a>
+<a name="384"><span class="lineNum">     384 </span>            :   wire [40:0]  _ittage_io_out_s2_full_pred_2_targets_0;</a>
+<a name="385"><span class="lineNum">     385 </span>            :   wire [40:0]  _ittage_io_out_s2_full_pred_2_targets_1;</a>
+<a name="386"><span class="lineNum">     386 </span>            :   wire [40:0]  _ittage_io_out_s2_full_pred_2_jalr_target;</a>
+<a name="387"><span class="lineNum">     387 </span>            :   wire [3:0]   _ittage_io_out_s2_full_pred_2_offsets_0;</a>
+<a name="388"><span class="lineNum">     388 </span>            :   wire [3:0]   _ittage_io_out_s2_full_pred_2_offsets_1;</a>
+<a name="389"><span class="lineNum">     389 </span>            :   wire [40:0]  _ittage_io_out_s2_full_pred_2_fallThroughAddr;</a>
+<a name="390"><span class="lineNum">     390 </span>            :   wire         _ittage_io_out_s2_full_pred_2_is_jalr;</a>
+<a name="391"><span class="lineNum">     391 </span>            :   wire         _ittage_io_out_s2_full_pred_2_is_call;</a>
+<a name="392"><span class="lineNum">     392 </span>            :   wire         _ittage_io_out_s2_full_pred_2_is_ret;</a>
+<a name="393"><span class="lineNum">     393 </span>            :   wire         _ittage_io_out_s2_full_pred_2_last_may_be_rvi_call;</a>
+<a name="394"><span class="lineNum">     394 </span>            :   wire         _ittage_io_out_s2_full_pred_2_is_br_sharing;</a>
+<a name="395"><span class="lineNum">     395 </span>            :   wire         _ittage_io_out_s2_full_pred_2_hit;</a>
+<a name="396"><span class="lineNum">     396 </span>            :   wire         _ittage_io_out_s2_full_pred_3_br_taken_mask_0;</a>
+<a name="397"><span class="lineNum">     397 </span>            :   wire         _ittage_io_out_s2_full_pred_3_br_taken_mask_1;</a>
+<a name="398"><span class="lineNum">     398 </span>            :   wire         _ittage_io_out_s2_full_pred_3_slot_valids_0;</a>
+<a name="399"><span class="lineNum">     399 </span>            :   wire         _ittage_io_out_s2_full_pred_3_slot_valids_1;</a>
+<a name="400"><span class="lineNum">     400 </span>            :   wire [40:0]  _ittage_io_out_s2_full_pred_3_targets_0;</a>
+<a name="401"><span class="lineNum">     401 </span>            :   wire [40:0]  _ittage_io_out_s2_full_pred_3_targets_1;</a>
+<a name="402"><span class="lineNum">     402 </span>            :   wire [40:0]  _ittage_io_out_s2_full_pred_3_jalr_target;</a>
+<a name="403"><span class="lineNum">     403 </span>            :   wire [3:0]   _ittage_io_out_s2_full_pred_3_offsets_0;</a>
+<a name="404"><span class="lineNum">     404 </span>            :   wire [3:0]   _ittage_io_out_s2_full_pred_3_offsets_1;</a>
+<a name="405"><span class="lineNum">     405 </span>            :   wire [40:0]  _ittage_io_out_s2_full_pred_3_fallThroughAddr;</a>
+<a name="406"><span class="lineNum">     406 </span>            :   wire         _ittage_io_out_s2_full_pred_3_fallThroughErr;</a>
+<a name="407"><span class="lineNum">     407 </span>            :   wire         _ittage_io_out_s2_full_pred_3_is_br_sharing;</a>
+<a name="408"><span class="lineNum">     408 </span>            :   wire         _ittage_io_out_s2_full_pred_3_hit;</a>
+<a name="409"><span class="lineNum">     409 </span>            :   wire         _ittage_io_out_s3_full_pred_0_br_taken_mask_0;</a>
+<a name="410"><span class="lineNum">     410 </span>            :   wire         _ittage_io_out_s3_full_pred_0_br_taken_mask_1;</a>
+<a name="411"><span class="lineNum">     411 </span>            :   wire         _ittage_io_out_s3_full_pred_0_slot_valids_0;</a>
+<a name="412"><span class="lineNum">     412 </span>            :   wire         _ittage_io_out_s3_full_pred_0_slot_valids_1;</a>
+<a name="413"><span class="lineNum">     413 </span>            :   wire [40:0]  _ittage_io_out_s3_full_pred_0_targets_0;</a>
+<a name="414"><span class="lineNum">     414 </span>            :   wire [40:0]  _ittage_io_out_s3_full_pred_0_targets_1;</a>
+<a name="415"><span class="lineNum">     415 </span>            :   wire [40:0]  _ittage_io_out_s3_full_pred_0_jalr_target;</a>
+<a name="416"><span class="lineNum">     416 </span>            :   wire [40:0]  _ittage_io_out_s3_full_pred_0_fallThroughAddr;</a>
+<a name="417"><span class="lineNum">     417 </span>            :   wire         _ittage_io_out_s3_full_pred_0_fallThroughErr;</a>
+<a name="418"><span class="lineNum">     418 </span>            :   wire         _ittage_io_out_s3_full_pred_0_is_br_sharing;</a>
+<a name="419"><span class="lineNum">     419 </span>            :   wire         _ittage_io_out_s3_full_pred_0_hit;</a>
+<a name="420"><span class="lineNum">     420 </span>            :   wire         _ittage_io_out_s3_full_pred_1_br_taken_mask_0;</a>
+<a name="421"><span class="lineNum">     421 </span>            :   wire         _ittage_io_out_s3_full_pred_1_br_taken_mask_1;</a>
+<a name="422"><span class="lineNum">     422 </span>            :   wire         _ittage_io_out_s3_full_pred_1_slot_valids_0;</a>
+<a name="423"><span class="lineNum">     423 </span>            :   wire         _ittage_io_out_s3_full_pred_1_slot_valids_1;</a>
+<a name="424"><span class="lineNum">     424 </span>            :   wire [40:0]  _ittage_io_out_s3_full_pred_1_targets_0;</a>
+<a name="425"><span class="lineNum">     425 </span>            :   wire [40:0]  _ittage_io_out_s3_full_pred_1_targets_1;</a>
+<a name="426"><span class="lineNum">     426 </span>            :   wire [40:0]  _ittage_io_out_s3_full_pred_1_jalr_target;</a>
+<a name="427"><span class="lineNum">     427 </span>            :   wire [40:0]  _ittage_io_out_s3_full_pred_1_fallThroughAddr;</a>
+<a name="428"><span class="lineNum">     428 </span>            :   wire         _ittage_io_out_s3_full_pred_1_fallThroughErr;</a>
+<a name="429"><span class="lineNum">     429 </span>            :   wire         _ittage_io_out_s3_full_pred_1_is_br_sharing;</a>
+<a name="430"><span class="lineNum">     430 </span>            :   wire         _ittage_io_out_s3_full_pred_1_hit;</a>
+<a name="431"><span class="lineNum">     431 </span>            :   wire         _ittage_io_out_s3_full_pred_2_br_taken_mask_0;</a>
+<a name="432"><span class="lineNum">     432 </span>            :   wire         _ittage_io_out_s3_full_pred_2_br_taken_mask_1;</a>
+<a name="433"><span class="lineNum">     433 </span>            :   wire         _ittage_io_out_s3_full_pred_2_slot_valids_0;</a>
+<a name="434"><span class="lineNum">     434 </span>            :   wire         _ittage_io_out_s3_full_pred_2_slot_valids_1;</a>
+<a name="435"><span class="lineNum">     435 </span>            :   wire [40:0]  _ittage_io_out_s3_full_pred_2_targets_0;</a>
+<a name="436"><span class="lineNum">     436 </span>            :   wire [40:0]  _ittage_io_out_s3_full_pred_2_targets_1;</a>
+<a name="437"><span class="lineNum">     437 </span>            :   wire [40:0]  _ittage_io_out_s3_full_pred_2_jalr_target;</a>
+<a name="438"><span class="lineNum">     438 </span>            :   wire [40:0]  _ittage_io_out_s3_full_pred_2_fallThroughAddr;</a>
+<a name="439"><span class="lineNum">     439 </span>            :   wire         _ittage_io_out_s3_full_pred_2_fallThroughErr;</a>
+<a name="440"><span class="lineNum">     440 </span>            :   wire         _ittage_io_out_s3_full_pred_2_is_jalr;</a>
+<a name="441"><span class="lineNum">     441 </span>            :   wire         _ittage_io_out_s3_full_pred_2_is_call;</a>
+<a name="442"><span class="lineNum">     442 </span>            :   wire         _ittage_io_out_s3_full_pred_2_is_ret;</a>
+<a name="443"><span class="lineNum">     443 </span>            :   wire         _ittage_io_out_s3_full_pred_2_is_br_sharing;</a>
+<a name="444"><span class="lineNum">     444 </span>            :   wire         _ittage_io_out_s3_full_pred_2_hit;</a>
+<a name="445"><span class="lineNum">     445 </span>            :   wire         _ittage_io_out_s3_full_pred_3_br_taken_mask_0;</a>
+<a name="446"><span class="lineNum">     446 </span>            :   wire         _ittage_io_out_s3_full_pred_3_br_taken_mask_1;</a>
+<a name="447"><span class="lineNum">     447 </span>            :   wire         _ittage_io_out_s3_full_pred_3_slot_valids_0;</a>
+<a name="448"><span class="lineNum">     448 </span>            :   wire         _ittage_io_out_s3_full_pred_3_slot_valids_1;</a>
+<a name="449"><span class="lineNum">     449 </span>            :   wire [40:0]  _ittage_io_out_s3_full_pred_3_targets_0;</a>
+<a name="450"><span class="lineNum">     450 </span>            :   wire [40:0]  _ittage_io_out_s3_full_pred_3_targets_1;</a>
+<a name="451"><span class="lineNum">     451 </span>            :   wire [40:0]  _ittage_io_out_s3_full_pred_3_jalr_target;</a>
+<a name="452"><span class="lineNum">     452 </span>            :   wire [3:0]   _ittage_io_out_s3_full_pred_3_offsets_0;</a>
+<a name="453"><span class="lineNum">     453 </span>            :   wire [3:0]   _ittage_io_out_s3_full_pred_3_offsets_1;</a>
+<a name="454"><span class="lineNum">     454 </span>            :   wire [40:0]  _ittage_io_out_s3_full_pred_3_fallThroughAddr;</a>
+<a name="455"><span class="lineNum">     455 </span>            :   wire         _ittage_io_out_s3_full_pred_3_fallThroughErr;</a>
+<a name="456"><span class="lineNum">     456 </span>            :   wire         _ittage_io_out_s3_full_pred_3_is_br_sharing;</a>
+<a name="457"><span class="lineNum">     457 </span>            :   wire         _ittage_io_out_s3_full_pred_3_hit;</a>
+<a name="458"><span class="lineNum">     458 </span>            :   wire [222:0] _ittage_io_out_last_stage_meta;</a>
+<a name="459"><span class="lineNum">     459 </span>            :   wire         _ittage_io_out_last_stage_ftb_entry_valid;</a>
+<a name="460"><span class="lineNum">     460 </span>            :   wire [3:0]   _ittage_io_out_last_stage_ftb_entry_brSlots_0_offset;</a>
+<a name="461"><span class="lineNum">     461 </span>            :   wire [11:0]  _ittage_io_out_last_stage_ftb_entry_brSlots_0_lower;</a>
+<a name="462"><span class="lineNum">     462 </span>            :   wire [1:0]   _ittage_io_out_last_stage_ftb_entry_brSlots_0_tarStat;</a>
+<a name="463"><span class="lineNum">     463 </span>            :   wire         _ittage_io_out_last_stage_ftb_entry_brSlots_0_sharing;</a>
+<a name="464"><span class="lineNum">     464 </span>            :   wire         _ittage_io_out_last_stage_ftb_entry_brSlots_0_valid;</a>
+<a name="465"><span class="lineNum">     465 </span>            :   wire [3:0]   _ittage_io_out_last_stage_ftb_entry_tailSlot_offset;</a>
+<a name="466"><span class="lineNum">     466 </span>            :   wire [19:0]  _ittage_io_out_last_stage_ftb_entry_tailSlot_lower;</a>
+<a name="467"><span class="lineNum">     467 </span>            :   wire [1:0]   _ittage_io_out_last_stage_ftb_entry_tailSlot_tarStat;</a>
+<a name="468"><span class="lineNum">     468 </span>            :   wire         _ittage_io_out_last_stage_ftb_entry_tailSlot_sharing;</a>
+<a name="469"><span class="lineNum">     469 </span>            :   wire         _ittage_io_out_last_stage_ftb_entry_tailSlot_valid;</a>
+<a name="470"><span class="lineNum">     470 </span>            :   wire [3:0]   _ittage_io_out_last_stage_ftb_entry_pftAddr;</a>
+<a name="471"><span class="lineNum">     471 </span>            :   wire         _ittage_io_out_last_stage_ftb_entry_carry;</a>
+<a name="472"><span class="lineNum">     472 </span>            :   wire         _ittage_io_out_last_stage_ftb_entry_isCall;</a>
+<a name="473"><span class="lineNum">     473 </span>            :   wire         _ittage_io_out_last_stage_ftb_entry_isRet;</a>
+<a name="474"><span class="lineNum">     474 </span>            :   wire         _ittage_io_out_last_stage_ftb_entry_isJalr;</a>
+<a name="475"><span class="lineNum">     475 </span>            :   wire         _ittage_io_out_last_stage_ftb_entry_last_may_be_rvi_call;</a>
+<a name="476"><span class="lineNum">     476 </span>            :   wire         _ittage_io_out_last_stage_ftb_entry_always_taken_0;</a>
+<a name="477"><span class="lineNum">     477 </span>            :   wire         _ittage_io_out_last_stage_ftb_entry_always_taken_1;</a>
+<a name="478"><span class="lineNum">     478 </span>            :   wire [222:0] _ras_io_out_last_stage_meta;</a>
+<a name="479"><span class="lineNum">     479 </span>            :   wire         _tage_io_out_s2_full_pred_0_br_taken_mask_0;</a>
+<a name="480"><span class="lineNum">     480 </span>            :   wire         _tage_io_out_s2_full_pred_0_br_taken_mask_1;</a>
+<a name="481"><span class="lineNum">     481 </span>            :   wire         _tage_io_out_s2_full_pred_1_br_taken_mask_0;</a>
+<a name="482"><span class="lineNum">     482 </span>            :   wire         _tage_io_out_s2_full_pred_1_br_taken_mask_1;</a>
+<a name="483"><span class="lineNum">     483 </span>            :   wire         _tage_io_out_s2_full_pred_2_br_taken_mask_0;</a>
+<a name="484"><span class="lineNum">     484 </span>            :   wire         _tage_io_out_s2_full_pred_2_br_taken_mask_1;</a>
+<a name="485"><span class="lineNum">     485 </span>            :   wire         _tage_io_out_s2_full_pred_3_br_taken_mask_0;</a>
+<a name="486"><span class="lineNum">     486 </span>            :   wire         _tage_io_out_s2_full_pred_3_br_taken_mask_1;</a>
+<a name="487"><span class="lineNum">     487 </span>            :   wire         _tage_io_out_s3_full_pred_0_br_taken_mask_0;</a>
+<a name="488"><span class="lineNum">     488 </span>            :   wire         _tage_io_out_s3_full_pred_0_br_taken_mask_1;</a>
+<a name="489"><span class="lineNum">     489 </span>            :   wire         _tage_io_out_s3_full_pred_1_br_taken_mask_0;</a>
+<a name="490"><span class="lineNum">     490 </span>            :   wire         _tage_io_out_s3_full_pred_1_br_taken_mask_1;</a>
+<a name="491"><span class="lineNum">     491 </span>            :   wire         _tage_io_out_s3_full_pred_2_br_taken_mask_0;</a>
+<a name="492"><span class="lineNum">     492 </span>            :   wire         _tage_io_out_s3_full_pred_2_br_taken_mask_1;</a>
+<a name="493"><span class="lineNum">     493 </span>            :   wire         _tage_io_out_s3_full_pred_3_br_taken_mask_0;</a>
+<a name="494"><span class="lineNum">     494 </span>            :   wire         _tage_io_out_s3_full_pred_3_br_taken_mask_1;</a>
+<a name="495"><span class="lineNum">     495 </span>            :   wire [222:0] _tage_io_out_last_stage_meta;</a>
+<a name="496"><span class="lineNum">     496 </span>            :   wire         _tage_io_s1_ready;</a>
+<a name="497"><span class="lineNum">     497 </span>            :   wire [5:0]   _tage_io_perf_0_value;</a>
+<a name="498"><span class="lineNum">     498 </span>            :   wire [5:0]   _tage_io_perf_1_value;</a>
+<a name="499"><span class="lineNum">     499 </span>            :   wire [5:0]   _tage_io_perf_2_value;</a>
+<a name="500"><span class="lineNum">     500 </span>            :   wire [222:0] _ubtb_io_out_last_stage_meta;</a>
+<a name="501"><span class="lineNum">     501 </span>            :   wire [5:0]   _ubtb_io_perf_0_value;</a>
+<a name="502"><span class="lineNum">     502 </span>            :   wire [5:0]   _ubtb_io_perf_1_value;</a>
+<a name="503"><span class="lineNum">     503 </span>            :   wire         _ftb_io_out_s2_full_pred_0_br_taken_mask_0;</a>
+<a name="504"><span class="lineNum">     504 </span>            :   wire         _ftb_io_out_s2_full_pred_0_br_taken_mask_1;</a>
+<a name="505"><span class="lineNum">     505 </span>            :   wire         _ftb_io_out_s2_full_pred_0_slot_valids_0;</a>
+<a name="506"><span class="lineNum">     506 </span>            :   wire         _ftb_io_out_s2_full_pred_0_slot_valids_1;</a>
+<a name="507"><span class="lineNum">     507 </span>            :   wire [40:0]  _ftb_io_out_s2_full_pred_0_targets_0;</a>
+<a name="508"><span class="lineNum">     508 </span>            :   wire [40:0]  _ftb_io_out_s2_full_pred_0_targets_1;</a>
+<a name="509"><span class="lineNum">     509 </span>            :   wire [40:0]  _ftb_io_out_s2_full_pred_0_jalr_target;</a>
+<a name="510"><span class="lineNum">     510 </span>            :   wire [3:0]   _ftb_io_out_s2_full_pred_0_offsets_0;</a>
+<a name="511"><span class="lineNum">     511 </span>            :   wire [3:0]   _ftb_io_out_s2_full_pred_0_offsets_1;</a>
+<a name="512"><span class="lineNum">     512 </span>            :   wire [40:0]  _ftb_io_out_s2_full_pred_0_fallThroughAddr;</a>
+<a name="513"><span class="lineNum">     513 </span>            :   wire         _ftb_io_out_s2_full_pred_0_is_br_sharing;</a>
+<a name="514"><span class="lineNum">     514 </span>            :   wire         _ftb_io_out_s2_full_pred_0_hit;</a>
+<a name="515"><span class="lineNum">     515 </span>            :   wire         _ftb_io_out_s2_full_pred_1_br_taken_mask_0;</a>
+<a name="516"><span class="lineNum">     516 </span>            :   wire         _ftb_io_out_s2_full_pred_1_br_taken_mask_1;</a>
+<a name="517"><span class="lineNum">     517 </span>            :   wire         _ftb_io_out_s2_full_pred_1_slot_valids_0;</a>
+<a name="518"><span class="lineNum">     518 </span>            :   wire         _ftb_io_out_s2_full_pred_1_slot_valids_1;</a>
+<a name="519"><span class="lineNum">     519 </span>            :   wire [40:0]  _ftb_io_out_s2_full_pred_1_targets_0;</a>
+<a name="520"><span class="lineNum">     520 </span>            :   wire [40:0]  _ftb_io_out_s2_full_pred_1_targets_1;</a>
+<a name="521"><span class="lineNum">     521 </span>            :   wire [40:0]  _ftb_io_out_s2_full_pred_1_jalr_target;</a>
+<a name="522"><span class="lineNum">     522 </span>            :   wire [3:0]   _ftb_io_out_s2_full_pred_1_offsets_0;</a>
+<a name="523"><span class="lineNum">     523 </span>            :   wire [3:0]   _ftb_io_out_s2_full_pred_1_offsets_1;</a>
+<a name="524"><span class="lineNum">     524 </span>            :   wire [40:0]  _ftb_io_out_s2_full_pred_1_fallThroughAddr;</a>
+<a name="525"><span class="lineNum">     525 </span>            :   wire         _ftb_io_out_s2_full_pred_1_is_br_sharing;</a>
+<a name="526"><span class="lineNum">     526 </span>            :   wire         _ftb_io_out_s2_full_pred_1_hit;</a>
+<a name="527"><span class="lineNum">     527 </span>            :   wire         _ftb_io_out_s2_full_pred_2_br_taken_mask_0;</a>
+<a name="528"><span class="lineNum">     528 </span>            :   wire         _ftb_io_out_s2_full_pred_2_br_taken_mask_1;</a>
+<a name="529"><span class="lineNum">     529 </span>            :   wire         _ftb_io_out_s2_full_pred_2_slot_valids_0;</a>
+<a name="530"><span class="lineNum">     530 </span>            :   wire         _ftb_io_out_s2_full_pred_2_slot_valids_1;</a>
+<a name="531"><span class="lineNum">     531 </span>            :   wire [40:0]  _ftb_io_out_s2_full_pred_2_targets_0;</a>
+<a name="532"><span class="lineNum">     532 </span>            :   wire [40:0]  _ftb_io_out_s2_full_pred_2_targets_1;</a>
+<a name="533"><span class="lineNum">     533 </span>            :   wire [40:0]  _ftb_io_out_s2_full_pred_2_jalr_target;</a>
+<a name="534"><span class="lineNum">     534 </span>            :   wire [3:0]   _ftb_io_out_s2_full_pred_2_offsets_0;</a>
+<a name="535"><span class="lineNum">     535 </span>            :   wire [3:0]   _ftb_io_out_s2_full_pred_2_offsets_1;</a>
+<a name="536"><span class="lineNum">     536 </span>            :   wire [40:0]  _ftb_io_out_s2_full_pred_2_fallThroughAddr;</a>
+<a name="537"><span class="lineNum">     537 </span>            :   wire         _ftb_io_out_s2_full_pred_2_is_jalr;</a>
+<a name="538"><span class="lineNum">     538 </span>            :   wire         _ftb_io_out_s2_full_pred_2_is_call;</a>
+<a name="539"><span class="lineNum">     539 </span>            :   wire         _ftb_io_out_s2_full_pred_2_is_ret;</a>
+<a name="540"><span class="lineNum">     540 </span>            :   wire         _ftb_io_out_s2_full_pred_2_last_may_be_rvi_call;</a>
+<a name="541"><span class="lineNum">     541 </span>            :   wire         _ftb_io_out_s2_full_pred_2_is_br_sharing;</a>
+<a name="542"><span class="lineNum">     542 </span>            :   wire         _ftb_io_out_s2_full_pred_2_hit;</a>
+<a name="543"><span class="lineNum">     543 </span>            :   wire         _ftb_io_out_s2_full_pred_3_br_taken_mask_0;</a>
+<a name="544"><span class="lineNum">     544 </span>            :   wire         _ftb_io_out_s2_full_pred_3_br_taken_mask_1;</a>
+<a name="545"><span class="lineNum">     545 </span>            :   wire         _ftb_io_out_s2_full_pred_3_slot_valids_0;</a>
+<a name="546"><span class="lineNum">     546 </span>            :   wire         _ftb_io_out_s2_full_pred_3_slot_valids_1;</a>
+<a name="547"><span class="lineNum">     547 </span>            :   wire [40:0]  _ftb_io_out_s2_full_pred_3_targets_0;</a>
+<a name="548"><span class="lineNum">     548 </span>            :   wire [40:0]  _ftb_io_out_s2_full_pred_3_targets_1;</a>
+<a name="549"><span class="lineNum">     549 </span>            :   wire [40:0]  _ftb_io_out_s2_full_pred_3_jalr_target;</a>
+<a name="550"><span class="lineNum">     550 </span>            :   wire [3:0]   _ftb_io_out_s2_full_pred_3_offsets_0;</a>
+<a name="551"><span class="lineNum">     551 </span>            :   wire [3:0]   _ftb_io_out_s2_full_pred_3_offsets_1;</a>
+<a name="552"><span class="lineNum">     552 </span>            :   wire [40:0]  _ftb_io_out_s2_full_pred_3_fallThroughAddr;</a>
+<a name="553"><span class="lineNum">     553 </span>            :   wire         _ftb_io_out_s2_full_pred_3_fallThroughErr;</a>
+<a name="554"><span class="lineNum">     554 </span>            :   wire         _ftb_io_out_s2_full_pred_3_is_br_sharing;</a>
+<a name="555"><span class="lineNum">     555 </span>            :   wire         _ftb_io_out_s2_full_pred_3_hit;</a>
+<a name="556"><span class="lineNum">     556 </span>            :   wire         _ftb_io_out_s3_full_pred_0_br_taken_mask_0;</a>
+<a name="557"><span class="lineNum">     557 </span>            :   wire         _ftb_io_out_s3_full_pred_0_br_taken_mask_1;</a>
+<a name="558"><span class="lineNum">     558 </span>            :   wire         _ftb_io_out_s3_full_pred_0_slot_valids_0;</a>
+<a name="559"><span class="lineNum">     559 </span>            :   wire         _ftb_io_out_s3_full_pred_0_slot_valids_1;</a>
+<a name="560"><span class="lineNum">     560 </span>            :   wire [40:0]  _ftb_io_out_s3_full_pred_0_targets_0;</a>
+<a name="561"><span class="lineNum">     561 </span>            :   wire [40:0]  _ftb_io_out_s3_full_pred_0_targets_1;</a>
+<a name="562"><span class="lineNum">     562 </span>            :   wire [40:0]  _ftb_io_out_s3_full_pred_0_jalr_target;</a>
+<a name="563"><span class="lineNum">     563 </span>            :   wire [40:0]  _ftb_io_out_s3_full_pred_0_fallThroughAddr;</a>
+<a name="564"><span class="lineNum">     564 </span>            :   wire         _ftb_io_out_s3_full_pred_0_fallThroughErr;</a>
+<a name="565"><span class="lineNum">     565 </span>            :   wire         _ftb_io_out_s3_full_pred_0_is_br_sharing;</a>
+<a name="566"><span class="lineNum">     566 </span>            :   wire         _ftb_io_out_s3_full_pred_0_hit;</a>
+<a name="567"><span class="lineNum">     567 </span>            :   wire         _ftb_io_out_s3_full_pred_1_br_taken_mask_0;</a>
+<a name="568"><span class="lineNum">     568 </span>            :   wire         _ftb_io_out_s3_full_pred_1_br_taken_mask_1;</a>
+<a name="569"><span class="lineNum">     569 </span>            :   wire         _ftb_io_out_s3_full_pred_1_slot_valids_0;</a>
+<a name="570"><span class="lineNum">     570 </span>            :   wire         _ftb_io_out_s3_full_pred_1_slot_valids_1;</a>
+<a name="571"><span class="lineNum">     571 </span>            :   wire [40:0]  _ftb_io_out_s3_full_pred_1_targets_0;</a>
+<a name="572"><span class="lineNum">     572 </span>            :   wire [40:0]  _ftb_io_out_s3_full_pred_1_targets_1;</a>
+<a name="573"><span class="lineNum">     573 </span>            :   wire [40:0]  _ftb_io_out_s3_full_pred_1_jalr_target;</a>
+<a name="574"><span class="lineNum">     574 </span>            :   wire [40:0]  _ftb_io_out_s3_full_pred_1_fallThroughAddr;</a>
+<a name="575"><span class="lineNum">     575 </span>            :   wire         _ftb_io_out_s3_full_pred_1_fallThroughErr;</a>
+<a name="576"><span class="lineNum">     576 </span>            :   wire         _ftb_io_out_s3_full_pred_1_is_br_sharing;</a>
+<a name="577"><span class="lineNum">     577 </span>            :   wire         _ftb_io_out_s3_full_pred_1_hit;</a>
+<a name="578"><span class="lineNum">     578 </span>            :   wire         _ftb_io_out_s3_full_pred_2_br_taken_mask_0;</a>
+<a name="579"><span class="lineNum">     579 </span>            :   wire         _ftb_io_out_s3_full_pred_2_br_taken_mask_1;</a>
+<a name="580"><span class="lineNum">     580 </span>            :   wire         _ftb_io_out_s3_full_pred_2_slot_valids_0;</a>
+<a name="581"><span class="lineNum">     581 </span>            :   wire         _ftb_io_out_s3_full_pred_2_slot_valids_1;</a>
+<a name="582"><span class="lineNum">     582 </span>            :   wire [40:0]  _ftb_io_out_s3_full_pred_2_targets_0;</a>
+<a name="583"><span class="lineNum">     583 </span>            :   wire [40:0]  _ftb_io_out_s3_full_pred_2_targets_1;</a>
+<a name="584"><span class="lineNum">     584 </span>            :   wire [40:0]  _ftb_io_out_s3_full_pred_2_jalr_target;</a>
+<a name="585"><span class="lineNum">     585 </span>            :   wire [40:0]  _ftb_io_out_s3_full_pred_2_fallThroughAddr;</a>
+<a name="586"><span class="lineNum">     586 </span>            :   wire         _ftb_io_out_s3_full_pred_2_fallThroughErr;</a>
+<a name="587"><span class="lineNum">     587 </span>            :   wire         _ftb_io_out_s3_full_pred_2_is_jalr;</a>
+<a name="588"><span class="lineNum">     588 </span>            :   wire         _ftb_io_out_s3_full_pred_2_is_call;</a>
+<a name="589"><span class="lineNum">     589 </span>            :   wire         _ftb_io_out_s3_full_pred_2_is_ret;</a>
+<a name="590"><span class="lineNum">     590 </span>            :   wire         _ftb_io_out_s3_full_pred_2_is_br_sharing;</a>
+<a name="591"><span class="lineNum">     591 </span>            :   wire         _ftb_io_out_s3_full_pred_2_hit;</a>
+<a name="592"><span class="lineNum">     592 </span>            :   wire         _ftb_io_out_s3_full_pred_3_br_taken_mask_0;</a>
+<a name="593"><span class="lineNum">     593 </span>            :   wire         _ftb_io_out_s3_full_pred_3_br_taken_mask_1;</a>
+<a name="594"><span class="lineNum">     594 </span>            :   wire         _ftb_io_out_s3_full_pred_3_slot_valids_0;</a>
+<a name="595"><span class="lineNum">     595 </span>            :   wire         _ftb_io_out_s3_full_pred_3_slot_valids_1;</a>
+<a name="596"><span class="lineNum">     596 </span>            :   wire [40:0]  _ftb_io_out_s3_full_pred_3_targets_0;</a>
+<a name="597"><span class="lineNum">     597 </span>            :   wire [40:0]  _ftb_io_out_s3_full_pred_3_targets_1;</a>
+<a name="598"><span class="lineNum">     598 </span>            :   wire [40:0]  _ftb_io_out_s3_full_pred_3_jalr_target;</a>
+<a name="599"><span class="lineNum">     599 </span>            :   wire [3:0]   _ftb_io_out_s3_full_pred_3_offsets_0;</a>
+<a name="600"><span class="lineNum">     600 </span>            :   wire [3:0]   _ftb_io_out_s3_full_pred_3_offsets_1;</a>
+<a name="601"><span class="lineNum">     601 </span>            :   wire [40:0]  _ftb_io_out_s3_full_pred_3_fallThroughAddr;</a>
+<a name="602"><span class="lineNum">     602 </span>            :   wire         _ftb_io_out_s3_full_pred_3_fallThroughErr;</a>
+<a name="603"><span class="lineNum">     603 </span>            :   wire         _ftb_io_out_s3_full_pred_3_is_br_sharing;</a>
+<a name="604"><span class="lineNum">     604 </span>            :   wire         _ftb_io_out_s3_full_pred_3_hit;</a>
+<a name="605"><span class="lineNum">     605 </span>            :   wire [222:0] _ftb_io_out_last_stage_meta;</a>
+<a name="606"><span class="lineNum">     606 </span>            :   wire         _ftb_io_out_last_stage_ftb_entry_valid;</a>
+<a name="607"><span class="lineNum">     607 </span>            :   wire [3:0]   _ftb_io_out_last_stage_ftb_entry_brSlots_0_offset;</a>
+<a name="608"><span class="lineNum">     608 </span>            :   wire [11:0]  _ftb_io_out_last_stage_ftb_entry_brSlots_0_lower;</a>
+<a name="609"><span class="lineNum">     609 </span>            :   wire [1:0]   _ftb_io_out_last_stage_ftb_entry_brSlots_0_tarStat;</a>
+<a name="610"><span class="lineNum">     610 </span>            :   wire         _ftb_io_out_last_stage_ftb_entry_brSlots_0_sharing;</a>
+<a name="611"><span class="lineNum">     611 </span>            :   wire         _ftb_io_out_last_stage_ftb_entry_brSlots_0_valid;</a>
+<a name="612"><span class="lineNum">     612 </span>            :   wire [3:0]   _ftb_io_out_last_stage_ftb_entry_tailSlot_offset;</a>
+<a name="613"><span class="lineNum">     613 </span>            :   wire [19:0]  _ftb_io_out_last_stage_ftb_entry_tailSlot_lower;</a>
+<a name="614"><span class="lineNum">     614 </span>            :   wire [1:0]   _ftb_io_out_last_stage_ftb_entry_tailSlot_tarStat;</a>
+<a name="615"><span class="lineNum">     615 </span>            :   wire         _ftb_io_out_last_stage_ftb_entry_tailSlot_sharing;</a>
+<a name="616"><span class="lineNum">     616 </span>            :   wire         _ftb_io_out_last_stage_ftb_entry_tailSlot_valid;</a>
+<a name="617"><span class="lineNum">     617 </span>            :   wire [3:0]   _ftb_io_out_last_stage_ftb_entry_pftAddr;</a>
+<a name="618"><span class="lineNum">     618 </span>            :   wire         _ftb_io_out_last_stage_ftb_entry_carry;</a>
+<a name="619"><span class="lineNum">     619 </span>            :   wire         _ftb_io_out_last_stage_ftb_entry_isCall;</a>
+<a name="620"><span class="lineNum">     620 </span>            :   wire         _ftb_io_out_last_stage_ftb_entry_isRet;</a>
+<a name="621"><span class="lineNum">     621 </span>            :   wire         _ftb_io_out_last_stage_ftb_entry_isJalr;</a>
+<a name="622"><span class="lineNum">     622 </span>            :   wire         _ftb_io_out_last_stage_ftb_entry_last_may_be_rvi_call;</a>
+<a name="623"><span class="lineNum">     623 </span>            :   wire         _ftb_io_out_last_stage_ftb_entry_always_taken_0;</a>
+<a name="624"><span class="lineNum">     624 </span>            :   wire         _ftb_io_out_last_stage_ftb_entry_always_taken_1;</a>
+<a name="625"><span class="lineNum">     625 </span>            :   wire         _ftb_io_s1_ready;</a>
+<a name="626"><span class="lineNum">     626 </span>            :   wire [5:0]   _ftb_io_perf_0_value;</a>
+<a name="627"><span class="lineNum">     627 </span>            :   wire [5:0]   _ftb_io_perf_1_value;</a>
+<a name="628"><span class="lineNum">     628 </span><span class="lineCov">        194 :   reg  [5:0]   io_perf_0_value_REG;</span></a>
+<a name="629"><span class="lineNum">     629 </span><span class="lineCov">        301 :   reg  [5:0]   io_perf_0_value_REG_1;</span></a>
+<a name="630"><span class="lineNum">     630 </span><span class="lineCov">        291 :   reg  [5:0]   io_perf_1_value_REG;</span></a>
+<a name="631"><span class="lineNum">     631 </span><span class="lineCov">        389 :   reg  [5:0]   io_perf_1_value_REG_1;</span></a>
+<a name="632"><span class="lineNum">     632 </span><span class="lineCov">        266 :   reg  [5:0]   io_perf_2_value_REG;</span></a>
+<a name="633"><span class="lineNum">     633 </span><span class="lineCov">        341 :   reg  [5:0]   io_perf_2_value_REG_1;</span></a>
+<a name="634"><span class="lineNum">     634 </span><span class="lineCov">        232 :   reg  [5:0]   io_perf_3_value_REG;</span></a>
+<a name="635"><span class="lineNum">     635 </span><span class="lineCov">        331 :   reg  [5:0]   io_perf_3_value_REG_1;</span></a>
+<a name="636"><span class="lineNum">     636 </span><span class="lineCov">        220 :   reg  [5:0]   io_perf_4_value_REG;</span></a>
+<a name="637"><span class="lineNum">     637 </span><span class="lineCov">        308 :   reg  [5:0]   io_perf_4_value_REG_1;</span></a>
+<a name="638"><span class="lineNum">     638 </span><span class="lineCov">        212 :   reg  [5:0]   io_perf_5_value_REG;</span></a>
+<a name="639"><span class="lineNum">     639 </span><span class="lineCov">        296 :   reg  [5:0]   io_perf_5_value_REG_1;</span></a>
+<a name="640"><span class="lineNum">     640 </span><span class="lineCov">        261 :   reg  [5:0]   io_perf_6_value_REG;</span></a>
+<a name="641"><span class="lineNum">     641 </span><span class="lineCov">        352 :   reg  [5:0]   io_perf_6_value_REG_1;</span></a>
+<a name="642"><span class="lineNum">     642 </span><span class="lineCov">     127694 :   always @(posedge clock) begin</span></a>
+<a name="643"><span class="lineNum">     643 </span><span class="lineCov">      63847 :     io_perf_0_value_REG &lt;= _ubtb_io_perf_0_value;</span></a>
+<a name="644"><span class="lineNum">     644 </span><span class="lineCov">      63847 :     io_perf_0_value_REG_1 &lt;= io_perf_0_value_REG;</span></a>
+<a name="645"><span class="lineNum">     645 </span><span class="lineCov">      63847 :     io_perf_1_value_REG &lt;= _ubtb_io_perf_1_value;</span></a>
+<a name="646"><span class="lineNum">     646 </span><span class="lineCov">      63847 :     io_perf_1_value_REG_1 &lt;= io_perf_1_value_REG;</span></a>
+<a name="647"><span class="lineNum">     647 </span><span class="lineCov">      63847 :     io_perf_2_value_REG &lt;= _tage_io_perf_0_value;</span></a>
+<a name="648"><span class="lineNum">     648 </span><span class="lineCov">      63847 :     io_perf_2_value_REG_1 &lt;= io_perf_2_value_REG;</span></a>
+<a name="649"><span class="lineNum">     649 </span><span class="lineCov">      63847 :     io_perf_3_value_REG &lt;= _tage_io_perf_1_value;</span></a>
+<a name="650"><span class="lineNum">     650 </span><span class="lineCov">      63847 :     io_perf_3_value_REG_1 &lt;= io_perf_3_value_REG;</span></a>
+<a name="651"><span class="lineNum">     651 </span><span class="lineCov">      63847 :     io_perf_4_value_REG &lt;= _tage_io_perf_2_value;</span></a>
+<a name="652"><span class="lineNum">     652 </span><span class="lineCov">      63847 :     io_perf_4_value_REG_1 &lt;= io_perf_4_value_REG;</span></a>
+<a name="653"><span class="lineNum">     653 </span><span class="lineCov">      63847 :     io_perf_5_value_REG &lt;= _ftb_io_perf_0_value;</span></a>
+<a name="654"><span class="lineNum">     654 </span><span class="lineCov">      63847 :     io_perf_5_value_REG_1 &lt;= io_perf_5_value_REG;</span></a>
+<a name="655"><span class="lineNum">     655 </span><span class="lineCov">      63847 :     io_perf_6_value_REG &lt;= _ftb_io_perf_1_value;</span></a>
+<a name="656"><span class="lineNum">     656 </span><span class="lineCov">      63847 :     io_perf_6_value_REG_1 &lt;= io_perf_6_value_REG;</span></a>
+<a name="657"><span class="lineNum">     657 </span>            :   end // always @(posedge)</a>
+<a name="658"><span class="lineNum">     658 </span>            :   `ifdef ENABLE_INITIAL_REG_</a>
+<a name="659"><span class="lineNum">     659 </span>            :     `ifdef FIRRTL_BEFORE_INITIAL</a>
+<a name="660"><span class="lineNum">     660 </span>            :       `FIRRTL_BEFORE_INITIAL</a>
+<a name="661"><span class="lineNum">     661 </span>            :     `endif // FIRRTL_BEFORE_INITIAL</a>
+<a name="662"><span class="lineNum">     662 </span>            :     logic [31:0] _RANDOM[0:18];</a>
+<a name="663"><span class="lineNum">     663 </span><span class="lineCov">         58 :     initial begin</span></a>
+<a name="664"><span class="lineNum">     664 </span>            :       `ifdef INIT_RANDOM_PROLOG_</a>
+<a name="665"><span class="lineNum">     665 </span>            :         `INIT_RANDOM_PROLOG_</a>
+<a name="666"><span class="lineNum">     666 </span>            :       `endif // INIT_RANDOM_PROLOG_</a>
+<a name="667"><span class="lineNum">     667 </span>            :       `ifdef RANDOMIZE_REG_INIT</a>
+<a name="668"><span class="lineNum">     668 </span>            :         for (logic [4:0] i = 5'h0; i &lt; 5'h13; i += 5'h1) begin</a>
+<a name="669"><span class="lineNum">     669 </span>            :           _RANDOM[i] = `RANDOM;</a>
+<a name="670"><span class="lineNum">     670 </span>            :         end</a>
+<a name="671"><span class="lineNum">     671 </span>            :         io_perf_0_value_REG = _RANDOM[5'hF][19:14];</a>
+<a name="672"><span class="lineNum">     672 </span>            :         io_perf_0_value_REG_1 = _RANDOM[5'hF][25:20];</a>
+<a name="673"><span class="lineNum">     673 </span>            :         io_perf_1_value_REG = _RANDOM[5'hF][31:26];</a>
+<a name="674"><span class="lineNum">     674 </span>            :         io_perf_1_value_REG_1 = _RANDOM[5'h10][5:0];</a>
+<a name="675"><span class="lineNum">     675 </span>            :         io_perf_2_value_REG = _RANDOM[5'h10][11:6];</a>
+<a name="676"><span class="lineNum">     676 </span>            :         io_perf_2_value_REG_1 = _RANDOM[5'h10][17:12];</a>
+<a name="677"><span class="lineNum">     677 </span>            :         io_perf_3_value_REG = _RANDOM[5'h10][23:18];</a>
+<a name="678"><span class="lineNum">     678 </span>            :         io_perf_3_value_REG_1 = _RANDOM[5'h10][29:24];</a>
+<a name="679"><span class="lineNum">     679 </span>            :         io_perf_4_value_REG = {_RANDOM[5'h10][31:30], _RANDOM[5'h11][3:0]};</a>
+<a name="680"><span class="lineNum">     680 </span>            :         io_perf_4_value_REG_1 = _RANDOM[5'h11][9:4];</a>
+<a name="681"><span class="lineNum">     681 </span>            :         io_perf_5_value_REG = _RANDOM[5'h11][15:10];</a>
+<a name="682"><span class="lineNum">     682 </span>            :         io_perf_5_value_REG_1 = _RANDOM[5'h11][21:16];</a>
+<a name="683"><span class="lineNum">     683 </span>            :         io_perf_6_value_REG = _RANDOM[5'h11][27:22];</a>
+<a name="684"><span class="lineNum">     684 </span>            :         io_perf_6_value_REG_1 = {_RANDOM[5'h11][31:28], _RANDOM[5'h12][1:0]};</a>
+<a name="685"><span class="lineNum">     685 </span>            :       `endif // RANDOMIZE_REG_INIT</a>
+<a name="686"><span class="lineNum">     686 </span>            :     end // initial</a>
+<a name="687"><span class="lineNum">     687 </span>            :     `ifdef FIRRTL_AFTER_INITIAL</a>
+<a name="688"><span class="lineNum">     688 </span>            :       `FIRRTL_AFTER_INITIAL</a>
+<a name="689"><span class="lineNum">     689 </span>            :     `endif // FIRRTL_AFTER_INITIAL</a>
+<a name="690"><span class="lineNum">     690 </span>            :   `endif // ENABLE_INITIAL_REG_</a>
+<a name="691"><span class="lineNum">     691 </span>            :   FTB ftb (</a>
+<a name="692"><span class="lineNum">     692 </span>            :     .clock                                               (clock),</a>
+<a name="693"><span class="lineNum">     693 </span>            :     .reset                                               (reset),</a>
+<a name="694"><span class="lineNum">     694 </span>            :     .io_reset_vector                                     (io_reset_vector),</a>
+<a name="695"><span class="lineNum">     695 </span>            :     .io_in_bits_s0_pc_0                                  (io_in_bits_s0_pc_0),</a>
+<a name="696"><span class="lineNum">     696 </span>            :     .io_in_bits_s0_pc_1                                  (io_in_bits_s0_pc_1),</a>
+<a name="697"><span class="lineNum">     697 </span>            :     .io_in_bits_s0_pc_2                                  (io_in_bits_s0_pc_2),</a>
+<a name="698"><span class="lineNum">     698 </span>            :     .io_in_bits_s0_pc_3                                  (io_in_bits_s0_pc_3),</a>
+<a name="699"><span class="lineNum">     699 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_0</a>
+<a name="700"><span class="lineNum">     700 </span>            :       (_tage_io_out_s2_full_pred_0_br_taken_mask_0),</a>
+<a name="701"><span class="lineNum">     701 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_1</a>
+<a name="702"><span class="lineNum">     702 </span>            :       (_tage_io_out_s2_full_pred_0_br_taken_mask_1),</a>
+<a name="703"><span class="lineNum">     703 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_0</a>
+<a name="704"><span class="lineNum">     704 </span>            :       (_tage_io_out_s2_full_pred_1_br_taken_mask_0),</a>
+<a name="705"><span class="lineNum">     705 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_1</a>
+<a name="706"><span class="lineNum">     706 </span>            :       (_tage_io_out_s2_full_pred_1_br_taken_mask_1),</a>
+<a name="707"><span class="lineNum">     707 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_0</a>
+<a name="708"><span class="lineNum">     708 </span>            :       (_tage_io_out_s2_full_pred_2_br_taken_mask_0),</a>
+<a name="709"><span class="lineNum">     709 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_1</a>
+<a name="710"><span class="lineNum">     710 </span>            :       (_tage_io_out_s2_full_pred_2_br_taken_mask_1),</a>
+<a name="711"><span class="lineNum">     711 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_0</a>
+<a name="712"><span class="lineNum">     712 </span>            :       (_tage_io_out_s2_full_pred_3_br_taken_mask_0),</a>
+<a name="713"><span class="lineNum">     713 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_1</a>
+<a name="714"><span class="lineNum">     714 </span>            :       (_tage_io_out_s2_full_pred_3_br_taken_mask_1),</a>
+<a name="715"><span class="lineNum">     715 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_0</a>
+<a name="716"><span class="lineNum">     716 </span>            :       (_tage_io_out_s3_full_pred_0_br_taken_mask_0),</a>
+<a name="717"><span class="lineNum">     717 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_1</a>
+<a name="718"><span class="lineNum">     718 </span>            :       (_tage_io_out_s3_full_pred_0_br_taken_mask_1),</a>
+<a name="719"><span class="lineNum">     719 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_0</a>
+<a name="720"><span class="lineNum">     720 </span>            :       (_tage_io_out_s3_full_pred_1_br_taken_mask_0),</a>
+<a name="721"><span class="lineNum">     721 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_1</a>
+<a name="722"><span class="lineNum">     722 </span>            :       (_tage_io_out_s3_full_pred_1_br_taken_mask_1),</a>
+<a name="723"><span class="lineNum">     723 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_0</a>
+<a name="724"><span class="lineNum">     724 </span>            :       (_tage_io_out_s3_full_pred_2_br_taken_mask_0),</a>
+<a name="725"><span class="lineNum">     725 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_1</a>
+<a name="726"><span class="lineNum">     726 </span>            :       (_tage_io_out_s3_full_pred_2_br_taken_mask_1),</a>
+<a name="727"><span class="lineNum">     727 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_0</a>
+<a name="728"><span class="lineNum">     728 </span>            :       (_tage_io_out_s3_full_pred_3_br_taken_mask_0),</a>
+<a name="729"><span class="lineNum">     729 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_1</a>
+<a name="730"><span class="lineNum">     730 </span>            :       (_tage_io_out_s3_full_pred_3_br_taken_mask_1),</a>
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+<a name="732"><span class="lineNum">     732 </span>            :       (_ftb_io_out_s2_full_pred_0_br_taken_mask_0),</a>
+<a name="733"><span class="lineNum">     733 </span>            :     .io_out_s2_full_pred_0_br_taken_mask_1</a>
+<a name="734"><span class="lineNum">     734 </span>            :       (_ftb_io_out_s2_full_pred_0_br_taken_mask_1),</a>
+<a name="735"><span class="lineNum">     735 </span>            :     .io_out_s2_full_pred_0_slot_valids_0</a>
+<a name="736"><span class="lineNum">     736 </span>            :       (_ftb_io_out_s2_full_pred_0_slot_valids_0),</a>
+<a name="737"><span class="lineNum">     737 </span>            :     .io_out_s2_full_pred_0_slot_valids_1</a>
+<a name="738"><span class="lineNum">     738 </span>            :       (_ftb_io_out_s2_full_pred_0_slot_valids_1),</a>
+<a name="739"><span class="lineNum">     739 </span>            :     .io_out_s2_full_pred_0_targets_0</a>
+<a name="740"><span class="lineNum">     740 </span>            :       (_ftb_io_out_s2_full_pred_0_targets_0),</a>
+<a name="741"><span class="lineNum">     741 </span>            :     .io_out_s2_full_pred_0_targets_1</a>
+<a name="742"><span class="lineNum">     742 </span>            :       (_ftb_io_out_s2_full_pred_0_targets_1),</a>
+<a name="743"><span class="lineNum">     743 </span>            :     .io_out_s2_full_pred_0_jalr_target</a>
+<a name="744"><span class="lineNum">     744 </span>            :       (_ftb_io_out_s2_full_pred_0_jalr_target),</a>
+<a name="745"><span class="lineNum">     745 </span>            :     .io_out_s2_full_pred_0_offsets_0</a>
+<a name="746"><span class="lineNum">     746 </span>            :       (_ftb_io_out_s2_full_pred_0_offsets_0),</a>
+<a name="747"><span class="lineNum">     747 </span>            :     .io_out_s2_full_pred_0_offsets_1</a>
+<a name="748"><span class="lineNum">     748 </span>            :       (_ftb_io_out_s2_full_pred_0_offsets_1),</a>
+<a name="749"><span class="lineNum">     749 </span>            :     .io_out_s2_full_pred_0_fallThroughAddr</a>
+<a name="750"><span class="lineNum">     750 </span>            :       (_ftb_io_out_s2_full_pred_0_fallThroughAddr),</a>
+<a name="751"><span class="lineNum">     751 </span>            :     .io_out_s2_full_pred_0_is_br_sharing</a>
+<a name="752"><span class="lineNum">     752 </span>            :       (_ftb_io_out_s2_full_pred_0_is_br_sharing),</a>
+<a name="753"><span class="lineNum">     753 </span>            :     .io_out_s2_full_pred_0_hit                           (_ftb_io_out_s2_full_pred_0_hit),</a>
+<a name="754"><span class="lineNum">     754 </span>            :     .io_out_s2_full_pred_1_br_taken_mask_0</a>
+<a name="755"><span class="lineNum">     755 </span>            :       (_ftb_io_out_s2_full_pred_1_br_taken_mask_0),</a>
+<a name="756"><span class="lineNum">     756 </span>            :     .io_out_s2_full_pred_1_br_taken_mask_1</a>
+<a name="757"><span class="lineNum">     757 </span>            :       (_ftb_io_out_s2_full_pred_1_br_taken_mask_1),</a>
+<a name="758"><span class="lineNum">     758 </span>            :     .io_out_s2_full_pred_1_slot_valids_0</a>
+<a name="759"><span class="lineNum">     759 </span>            :       (_ftb_io_out_s2_full_pred_1_slot_valids_0),</a>
+<a name="760"><span class="lineNum">     760 </span>            :     .io_out_s2_full_pred_1_slot_valids_1</a>
+<a name="761"><span class="lineNum">     761 </span>            :       (_ftb_io_out_s2_full_pred_1_slot_valids_1),</a>
+<a name="762"><span class="lineNum">     762 </span>            :     .io_out_s2_full_pred_1_targets_0</a>
+<a name="763"><span class="lineNum">     763 </span>            :       (_ftb_io_out_s2_full_pred_1_targets_0),</a>
+<a name="764"><span class="lineNum">     764 </span>            :     .io_out_s2_full_pred_1_targets_1</a>
+<a name="765"><span class="lineNum">     765 </span>            :       (_ftb_io_out_s2_full_pred_1_targets_1),</a>
+<a name="766"><span class="lineNum">     766 </span>            :     .io_out_s2_full_pred_1_jalr_target</a>
+<a name="767"><span class="lineNum">     767 </span>            :       (_ftb_io_out_s2_full_pred_1_jalr_target),</a>
+<a name="768"><span class="lineNum">     768 </span>            :     .io_out_s2_full_pred_1_offsets_0</a>
+<a name="769"><span class="lineNum">     769 </span>            :       (_ftb_io_out_s2_full_pred_1_offsets_0),</a>
+<a name="770"><span class="lineNum">     770 </span>            :     .io_out_s2_full_pred_1_offsets_1</a>
+<a name="771"><span class="lineNum">     771 </span>            :       (_ftb_io_out_s2_full_pred_1_offsets_1),</a>
+<a name="772"><span class="lineNum">     772 </span>            :     .io_out_s2_full_pred_1_fallThroughAddr</a>
+<a name="773"><span class="lineNum">     773 </span>            :       (_ftb_io_out_s2_full_pred_1_fallThroughAddr),</a>
+<a name="774"><span class="lineNum">     774 </span>            :     .io_out_s2_full_pred_1_is_br_sharing</a>
+<a name="775"><span class="lineNum">     775 </span>            :       (_ftb_io_out_s2_full_pred_1_is_br_sharing),</a>
+<a name="776"><span class="lineNum">     776 </span>            :     .io_out_s2_full_pred_1_hit                           (_ftb_io_out_s2_full_pred_1_hit),</a>
+<a name="777"><span class="lineNum">     777 </span>            :     .io_out_s2_full_pred_2_br_taken_mask_0</a>
+<a name="778"><span class="lineNum">     778 </span>            :       (_ftb_io_out_s2_full_pred_2_br_taken_mask_0),</a>
+<a name="779"><span class="lineNum">     779 </span>            :     .io_out_s2_full_pred_2_br_taken_mask_1</a>
+<a name="780"><span class="lineNum">     780 </span>            :       (_ftb_io_out_s2_full_pred_2_br_taken_mask_1),</a>
+<a name="781"><span class="lineNum">     781 </span>            :     .io_out_s2_full_pred_2_slot_valids_0</a>
+<a name="782"><span class="lineNum">     782 </span>            :       (_ftb_io_out_s2_full_pred_2_slot_valids_0),</a>
+<a name="783"><span class="lineNum">     783 </span>            :     .io_out_s2_full_pred_2_slot_valids_1</a>
+<a name="784"><span class="lineNum">     784 </span>            :       (_ftb_io_out_s2_full_pred_2_slot_valids_1),</a>
+<a name="785"><span class="lineNum">     785 </span>            :     .io_out_s2_full_pred_2_targets_0</a>
+<a name="786"><span class="lineNum">     786 </span>            :       (_ftb_io_out_s2_full_pred_2_targets_0),</a>
+<a name="787"><span class="lineNum">     787 </span>            :     .io_out_s2_full_pred_2_targets_1</a>
+<a name="788"><span class="lineNum">     788 </span>            :       (_ftb_io_out_s2_full_pred_2_targets_1),</a>
+<a name="789"><span class="lineNum">     789 </span>            :     .io_out_s2_full_pred_2_jalr_target</a>
+<a name="790"><span class="lineNum">     790 </span>            :       (_ftb_io_out_s2_full_pred_2_jalr_target),</a>
+<a name="791"><span class="lineNum">     791 </span>            :     .io_out_s2_full_pred_2_offsets_0</a>
+<a name="792"><span class="lineNum">     792 </span>            :       (_ftb_io_out_s2_full_pred_2_offsets_0),</a>
+<a name="793"><span class="lineNum">     793 </span>            :     .io_out_s2_full_pred_2_offsets_1</a>
+<a name="794"><span class="lineNum">     794 </span>            :       (_ftb_io_out_s2_full_pred_2_offsets_1),</a>
+<a name="795"><span class="lineNum">     795 </span>            :     .io_out_s2_full_pred_2_fallThroughAddr</a>
+<a name="796"><span class="lineNum">     796 </span>            :       (_ftb_io_out_s2_full_pred_2_fallThroughAddr),</a>
+<a name="797"><span class="lineNum">     797 </span>            :     .io_out_s2_full_pred_2_is_jalr</a>
+<a name="798"><span class="lineNum">     798 </span>            :       (_ftb_io_out_s2_full_pred_2_is_jalr),</a>
+<a name="799"><span class="lineNum">     799 </span>            :     .io_out_s2_full_pred_2_is_call</a>
+<a name="800"><span class="lineNum">     800 </span>            :       (_ftb_io_out_s2_full_pred_2_is_call),</a>
+<a name="801"><span class="lineNum">     801 </span>            :     .io_out_s2_full_pred_2_is_ret</a>
+<a name="802"><span class="lineNum">     802 </span>            :       (_ftb_io_out_s2_full_pred_2_is_ret),</a>
+<a name="803"><span class="lineNum">     803 </span>            :     .io_out_s2_full_pred_2_last_may_be_rvi_call</a>
+<a name="804"><span class="lineNum">     804 </span>            :       (_ftb_io_out_s2_full_pred_2_last_may_be_rvi_call),</a>
+<a name="805"><span class="lineNum">     805 </span>            :     .io_out_s2_full_pred_2_is_br_sharing</a>
+<a name="806"><span class="lineNum">     806 </span>            :       (_ftb_io_out_s2_full_pred_2_is_br_sharing),</a>
+<a name="807"><span class="lineNum">     807 </span>            :     .io_out_s2_full_pred_2_hit                           (_ftb_io_out_s2_full_pred_2_hit),</a>
+<a name="808"><span class="lineNum">     808 </span>            :     .io_out_s2_full_pred_3_br_taken_mask_0</a>
+<a name="809"><span class="lineNum">     809 </span>            :       (_ftb_io_out_s2_full_pred_3_br_taken_mask_0),</a>
+<a name="810"><span class="lineNum">     810 </span>            :     .io_out_s2_full_pred_3_br_taken_mask_1</a>
+<a name="811"><span class="lineNum">     811 </span>            :       (_ftb_io_out_s2_full_pred_3_br_taken_mask_1),</a>
+<a name="812"><span class="lineNum">     812 </span>            :     .io_out_s2_full_pred_3_slot_valids_0</a>
+<a name="813"><span class="lineNum">     813 </span>            :       (_ftb_io_out_s2_full_pred_3_slot_valids_0),</a>
+<a name="814"><span class="lineNum">     814 </span>            :     .io_out_s2_full_pred_3_slot_valids_1</a>
+<a name="815"><span class="lineNum">     815 </span>            :       (_ftb_io_out_s2_full_pred_3_slot_valids_1),</a>
+<a name="816"><span class="lineNum">     816 </span>            :     .io_out_s2_full_pred_3_targets_0</a>
+<a name="817"><span class="lineNum">     817 </span>            :       (_ftb_io_out_s2_full_pred_3_targets_0),</a>
+<a name="818"><span class="lineNum">     818 </span>            :     .io_out_s2_full_pred_3_targets_1</a>
+<a name="819"><span class="lineNum">     819 </span>            :       (_ftb_io_out_s2_full_pred_3_targets_1),</a>
+<a name="820"><span class="lineNum">     820 </span>            :     .io_out_s2_full_pred_3_jalr_target</a>
+<a name="821"><span class="lineNum">     821 </span>            :       (_ftb_io_out_s2_full_pred_3_jalr_target),</a>
+<a name="822"><span class="lineNum">     822 </span>            :     .io_out_s2_full_pred_3_offsets_0</a>
+<a name="823"><span class="lineNum">     823 </span>            :       (_ftb_io_out_s2_full_pred_3_offsets_0),</a>
+<a name="824"><span class="lineNum">     824 </span>            :     .io_out_s2_full_pred_3_offsets_1</a>
+<a name="825"><span class="lineNum">     825 </span>            :       (_ftb_io_out_s2_full_pred_3_offsets_1),</a>
+<a name="826"><span class="lineNum">     826 </span>            :     .io_out_s2_full_pred_3_fallThroughAddr</a>
+<a name="827"><span class="lineNum">     827 </span>            :       (_ftb_io_out_s2_full_pred_3_fallThroughAddr),</a>
+<a name="828"><span class="lineNum">     828 </span>            :     .io_out_s2_full_pred_3_fallThroughErr</a>
+<a name="829"><span class="lineNum">     829 </span>            :       (_ftb_io_out_s2_full_pred_3_fallThroughErr),</a>
+<a name="830"><span class="lineNum">     830 </span>            :     .io_out_s2_full_pred_3_is_br_sharing</a>
+<a name="831"><span class="lineNum">     831 </span>            :       (_ftb_io_out_s2_full_pred_3_is_br_sharing),</a>
+<a name="832"><span class="lineNum">     832 </span>            :     .io_out_s2_full_pred_3_hit                           (_ftb_io_out_s2_full_pred_3_hit),</a>
+<a name="833"><span class="lineNum">     833 </span>            :     .io_out_s3_full_pred_0_br_taken_mask_0</a>
+<a name="834"><span class="lineNum">     834 </span>            :       (_ftb_io_out_s3_full_pred_0_br_taken_mask_0),</a>
+<a name="835"><span class="lineNum">     835 </span>            :     .io_out_s3_full_pred_0_br_taken_mask_1</a>
+<a name="836"><span class="lineNum">     836 </span>            :       (_ftb_io_out_s3_full_pred_0_br_taken_mask_1),</a>
+<a name="837"><span class="lineNum">     837 </span>            :     .io_out_s3_full_pred_0_slot_valids_0</a>
+<a name="838"><span class="lineNum">     838 </span>            :       (_ftb_io_out_s3_full_pred_0_slot_valids_0),</a>
+<a name="839"><span class="lineNum">     839 </span>            :     .io_out_s3_full_pred_0_slot_valids_1</a>
+<a name="840"><span class="lineNum">     840 </span>            :       (_ftb_io_out_s3_full_pred_0_slot_valids_1),</a>
+<a name="841"><span class="lineNum">     841 </span>            :     .io_out_s3_full_pred_0_targets_0</a>
+<a name="842"><span class="lineNum">     842 </span>            :       (_ftb_io_out_s3_full_pred_0_targets_0),</a>
+<a name="843"><span class="lineNum">     843 </span>            :     .io_out_s3_full_pred_0_targets_1</a>
+<a name="844"><span class="lineNum">     844 </span>            :       (_ftb_io_out_s3_full_pred_0_targets_1),</a>
+<a name="845"><span class="lineNum">     845 </span>            :     .io_out_s3_full_pred_0_jalr_target</a>
+<a name="846"><span class="lineNum">     846 </span>            :       (_ftb_io_out_s3_full_pred_0_jalr_target),</a>
+<a name="847"><span class="lineNum">     847 </span>            :     .io_out_s3_full_pred_0_fallThroughAddr</a>
+<a name="848"><span class="lineNum">     848 </span>            :       (_ftb_io_out_s3_full_pred_0_fallThroughAddr),</a>
+<a name="849"><span class="lineNum">     849 </span>            :     .io_out_s3_full_pred_0_fallThroughErr</a>
+<a name="850"><span class="lineNum">     850 </span>            :       (_ftb_io_out_s3_full_pred_0_fallThroughErr),</a>
+<a name="851"><span class="lineNum">     851 </span>            :     .io_out_s3_full_pred_0_is_br_sharing</a>
+<a name="852"><span class="lineNum">     852 </span>            :       (_ftb_io_out_s3_full_pred_0_is_br_sharing),</a>
+<a name="853"><span class="lineNum">     853 </span>            :     .io_out_s3_full_pred_0_hit                           (_ftb_io_out_s3_full_pred_0_hit),</a>
+<a name="854"><span class="lineNum">     854 </span>            :     .io_out_s3_full_pred_1_br_taken_mask_0</a>
+<a name="855"><span class="lineNum">     855 </span>            :       (_ftb_io_out_s3_full_pred_1_br_taken_mask_0),</a>
+<a name="856"><span class="lineNum">     856 </span>            :     .io_out_s3_full_pred_1_br_taken_mask_1</a>
+<a name="857"><span class="lineNum">     857 </span>            :       (_ftb_io_out_s3_full_pred_1_br_taken_mask_1),</a>
+<a name="858"><span class="lineNum">     858 </span>            :     .io_out_s3_full_pred_1_slot_valids_0</a>
+<a name="859"><span class="lineNum">     859 </span>            :       (_ftb_io_out_s3_full_pred_1_slot_valids_0),</a>
+<a name="860"><span class="lineNum">     860 </span>            :     .io_out_s3_full_pred_1_slot_valids_1</a>
+<a name="861"><span class="lineNum">     861 </span>            :       (_ftb_io_out_s3_full_pred_1_slot_valids_1),</a>
+<a name="862"><span class="lineNum">     862 </span>            :     .io_out_s3_full_pred_1_targets_0</a>
+<a name="863"><span class="lineNum">     863 </span>            :       (_ftb_io_out_s3_full_pred_1_targets_0),</a>
+<a name="864"><span class="lineNum">     864 </span>            :     .io_out_s3_full_pred_1_targets_1</a>
+<a name="865"><span class="lineNum">     865 </span>            :       (_ftb_io_out_s3_full_pred_1_targets_1),</a>
+<a name="866"><span class="lineNum">     866 </span>            :     .io_out_s3_full_pred_1_jalr_target</a>
+<a name="867"><span class="lineNum">     867 </span>            :       (_ftb_io_out_s3_full_pred_1_jalr_target),</a>
+<a name="868"><span class="lineNum">     868 </span>            :     .io_out_s3_full_pred_1_fallThroughAddr</a>
+<a name="869"><span class="lineNum">     869 </span>            :       (_ftb_io_out_s3_full_pred_1_fallThroughAddr),</a>
+<a name="870"><span class="lineNum">     870 </span>            :     .io_out_s3_full_pred_1_fallThroughErr</a>
+<a name="871"><span class="lineNum">     871 </span>            :       (_ftb_io_out_s3_full_pred_1_fallThroughErr),</a>
+<a name="872"><span class="lineNum">     872 </span>            :     .io_out_s3_full_pred_1_is_br_sharing</a>
+<a name="873"><span class="lineNum">     873 </span>            :       (_ftb_io_out_s3_full_pred_1_is_br_sharing),</a>
+<a name="874"><span class="lineNum">     874 </span>            :     .io_out_s3_full_pred_1_hit                           (_ftb_io_out_s3_full_pred_1_hit),</a>
+<a name="875"><span class="lineNum">     875 </span>            :     .io_out_s3_full_pred_2_br_taken_mask_0</a>
+<a name="876"><span class="lineNum">     876 </span>            :       (_ftb_io_out_s3_full_pred_2_br_taken_mask_0),</a>
+<a name="877"><span class="lineNum">     877 </span>            :     .io_out_s3_full_pred_2_br_taken_mask_1</a>
+<a name="878"><span class="lineNum">     878 </span>            :       (_ftb_io_out_s3_full_pred_2_br_taken_mask_1),</a>
+<a name="879"><span class="lineNum">     879 </span>            :     .io_out_s3_full_pred_2_slot_valids_0</a>
+<a name="880"><span class="lineNum">     880 </span>            :       (_ftb_io_out_s3_full_pred_2_slot_valids_0),</a>
+<a name="881"><span class="lineNum">     881 </span>            :     .io_out_s3_full_pred_2_slot_valids_1</a>
+<a name="882"><span class="lineNum">     882 </span>            :       (_ftb_io_out_s3_full_pred_2_slot_valids_1),</a>
+<a name="883"><span class="lineNum">     883 </span>            :     .io_out_s3_full_pred_2_targets_0</a>
+<a name="884"><span class="lineNum">     884 </span>            :       (_ftb_io_out_s3_full_pred_2_targets_0),</a>
+<a name="885"><span class="lineNum">     885 </span>            :     .io_out_s3_full_pred_2_targets_1</a>
+<a name="886"><span class="lineNum">     886 </span>            :       (_ftb_io_out_s3_full_pred_2_targets_1),</a>
+<a name="887"><span class="lineNum">     887 </span>            :     .io_out_s3_full_pred_2_jalr_target</a>
+<a name="888"><span class="lineNum">     888 </span>            :       (_ftb_io_out_s3_full_pred_2_jalr_target),</a>
+<a name="889"><span class="lineNum">     889 </span>            :     .io_out_s3_full_pred_2_fallThroughAddr</a>
+<a name="890"><span class="lineNum">     890 </span>            :       (_ftb_io_out_s3_full_pred_2_fallThroughAddr),</a>
+<a name="891"><span class="lineNum">     891 </span>            :     .io_out_s3_full_pred_2_fallThroughErr</a>
+<a name="892"><span class="lineNum">     892 </span>            :       (_ftb_io_out_s3_full_pred_2_fallThroughErr),</a>
+<a name="893"><span class="lineNum">     893 </span>            :     .io_out_s3_full_pred_2_is_jalr</a>
+<a name="894"><span class="lineNum">     894 </span>            :       (_ftb_io_out_s3_full_pred_2_is_jalr),</a>
+<a name="895"><span class="lineNum">     895 </span>            :     .io_out_s3_full_pred_2_is_call</a>
+<a name="896"><span class="lineNum">     896 </span>            :       (_ftb_io_out_s3_full_pred_2_is_call),</a>
+<a name="897"><span class="lineNum">     897 </span>            :     .io_out_s3_full_pred_2_is_ret</a>
+<a name="898"><span class="lineNum">     898 </span>            :       (_ftb_io_out_s3_full_pred_2_is_ret),</a>
+<a name="899"><span class="lineNum">     899 </span>            :     .io_out_s3_full_pred_2_is_br_sharing</a>
+<a name="900"><span class="lineNum">     900 </span>            :       (_ftb_io_out_s3_full_pred_2_is_br_sharing),</a>
+<a name="901"><span class="lineNum">     901 </span>            :     .io_out_s3_full_pred_2_hit                           (_ftb_io_out_s3_full_pred_2_hit),</a>
+<a name="902"><span class="lineNum">     902 </span>            :     .io_out_s3_full_pred_3_br_taken_mask_0</a>
+<a name="903"><span class="lineNum">     903 </span>            :       (_ftb_io_out_s3_full_pred_3_br_taken_mask_0),</a>
+<a name="904"><span class="lineNum">     904 </span>            :     .io_out_s3_full_pred_3_br_taken_mask_1</a>
+<a name="905"><span class="lineNum">     905 </span>            :       (_ftb_io_out_s3_full_pred_3_br_taken_mask_1),</a>
+<a name="906"><span class="lineNum">     906 </span>            :     .io_out_s3_full_pred_3_slot_valids_0</a>
+<a name="907"><span class="lineNum">     907 </span>            :       (_ftb_io_out_s3_full_pred_3_slot_valids_0),</a>
+<a name="908"><span class="lineNum">     908 </span>            :     .io_out_s3_full_pred_3_slot_valids_1</a>
+<a name="909"><span class="lineNum">     909 </span>            :       (_ftb_io_out_s3_full_pred_3_slot_valids_1),</a>
+<a name="910"><span class="lineNum">     910 </span>            :     .io_out_s3_full_pred_3_targets_0</a>
+<a name="911"><span class="lineNum">     911 </span>            :       (_ftb_io_out_s3_full_pred_3_targets_0),</a>
+<a name="912"><span class="lineNum">     912 </span>            :     .io_out_s3_full_pred_3_targets_1</a>
+<a name="913"><span class="lineNum">     913 </span>            :       (_ftb_io_out_s3_full_pred_3_targets_1),</a>
+<a name="914"><span class="lineNum">     914 </span>            :     .io_out_s3_full_pred_3_jalr_target</a>
+<a name="915"><span class="lineNum">     915 </span>            :       (_ftb_io_out_s3_full_pred_3_jalr_target),</a>
+<a name="916"><span class="lineNum">     916 </span>            :     .io_out_s3_full_pred_3_offsets_0</a>
+<a name="917"><span class="lineNum">     917 </span>            :       (_ftb_io_out_s3_full_pred_3_offsets_0),</a>
+<a name="918"><span class="lineNum">     918 </span>            :     .io_out_s3_full_pred_3_offsets_1</a>
+<a name="919"><span class="lineNum">     919 </span>            :       (_ftb_io_out_s3_full_pred_3_offsets_1),</a>
+<a name="920"><span class="lineNum">     920 </span>            :     .io_out_s3_full_pred_3_fallThroughAddr</a>
+<a name="921"><span class="lineNum">     921 </span>            :       (_ftb_io_out_s3_full_pred_3_fallThroughAddr),</a>
+<a name="922"><span class="lineNum">     922 </span>            :     .io_out_s3_full_pred_3_fallThroughErr</a>
+<a name="923"><span class="lineNum">     923 </span>            :       (_ftb_io_out_s3_full_pred_3_fallThroughErr),</a>
+<a name="924"><span class="lineNum">     924 </span>            :     .io_out_s3_full_pred_3_is_br_sharing</a>
+<a name="925"><span class="lineNum">     925 </span>            :       (_ftb_io_out_s3_full_pred_3_is_br_sharing),</a>
+<a name="926"><span class="lineNum">     926 </span>            :     .io_out_s3_full_pred_3_hit                           (_ftb_io_out_s3_full_pred_3_hit),</a>
+<a name="927"><span class="lineNum">     927 </span>            :     .io_out_last_stage_meta                              (_ftb_io_out_last_stage_meta),</a>
+<a name="928"><span class="lineNum">     928 </span>            :     .io_out_last_stage_ftb_entry_valid</a>
+<a name="929"><span class="lineNum">     929 </span>            :       (_ftb_io_out_last_stage_ftb_entry_valid),</a>
+<a name="930"><span class="lineNum">     930 </span>            :     .io_out_last_stage_ftb_entry_brSlots_0_offset</a>
+<a name="931"><span class="lineNum">     931 </span>            :       (_ftb_io_out_last_stage_ftb_entry_brSlots_0_offset),</a>
+<a name="932"><span class="lineNum">     932 </span>            :     .io_out_last_stage_ftb_entry_brSlots_0_lower</a>
+<a name="933"><span class="lineNum">     933 </span>            :       (_ftb_io_out_last_stage_ftb_entry_brSlots_0_lower),</a>
+<a name="934"><span class="lineNum">     934 </span>            :     .io_out_last_stage_ftb_entry_brSlots_0_tarStat</a>
+<a name="935"><span class="lineNum">     935 </span>            :       (_ftb_io_out_last_stage_ftb_entry_brSlots_0_tarStat),</a>
+<a name="936"><span class="lineNum">     936 </span>            :     .io_out_last_stage_ftb_entry_brSlots_0_sharing</a>
+<a name="937"><span class="lineNum">     937 </span>            :       (_ftb_io_out_last_stage_ftb_entry_brSlots_0_sharing),</a>
+<a name="938"><span class="lineNum">     938 </span>            :     .io_out_last_stage_ftb_entry_brSlots_0_valid</a>
+<a name="939"><span class="lineNum">     939 </span>            :       (_ftb_io_out_last_stage_ftb_entry_brSlots_0_valid),</a>
+<a name="940"><span class="lineNum">     940 </span>            :     .io_out_last_stage_ftb_entry_tailSlot_offset</a>
+<a name="941"><span class="lineNum">     941 </span>            :       (_ftb_io_out_last_stage_ftb_entry_tailSlot_offset),</a>
+<a name="942"><span class="lineNum">     942 </span>            :     .io_out_last_stage_ftb_entry_tailSlot_lower</a>
+<a name="943"><span class="lineNum">     943 </span>            :       (_ftb_io_out_last_stage_ftb_entry_tailSlot_lower),</a>
+<a name="944"><span class="lineNum">     944 </span>            :     .io_out_last_stage_ftb_entry_tailSlot_tarStat</a>
+<a name="945"><span class="lineNum">     945 </span>            :       (_ftb_io_out_last_stage_ftb_entry_tailSlot_tarStat),</a>
+<a name="946"><span class="lineNum">     946 </span>            :     .io_out_last_stage_ftb_entry_tailSlot_sharing</a>
+<a name="947"><span class="lineNum">     947 </span>            :       (_ftb_io_out_last_stage_ftb_entry_tailSlot_sharing),</a>
+<a name="948"><span class="lineNum">     948 </span>            :     .io_out_last_stage_ftb_entry_tailSlot_valid</a>
+<a name="949"><span class="lineNum">     949 </span>            :       (_ftb_io_out_last_stage_ftb_entry_tailSlot_valid),</a>
+<a name="950"><span class="lineNum">     950 </span>            :     .io_out_last_stage_ftb_entry_pftAddr</a>
+<a name="951"><span class="lineNum">     951 </span>            :       (_ftb_io_out_last_stage_ftb_entry_pftAddr),</a>
+<a name="952"><span class="lineNum">     952 </span>            :     .io_out_last_stage_ftb_entry_carry</a>
+<a name="953"><span class="lineNum">     953 </span>            :       (_ftb_io_out_last_stage_ftb_entry_carry),</a>
+<a name="954"><span class="lineNum">     954 </span>            :     .io_out_last_stage_ftb_entry_isCall</a>
+<a name="955"><span class="lineNum">     955 </span>            :       (_ftb_io_out_last_stage_ftb_entry_isCall),</a>
+<a name="956"><span class="lineNum">     956 </span>            :     .io_out_last_stage_ftb_entry_isRet</a>
+<a name="957"><span class="lineNum">     957 </span>            :       (_ftb_io_out_last_stage_ftb_entry_isRet),</a>
+<a name="958"><span class="lineNum">     958 </span>            :     .io_out_last_stage_ftb_entry_isJalr</a>
+<a name="959"><span class="lineNum">     959 </span>            :       (_ftb_io_out_last_stage_ftb_entry_isJalr),</a>
+<a name="960"><span class="lineNum">     960 </span>            :     .io_out_last_stage_ftb_entry_last_may_be_rvi_call</a>
+<a name="961"><span class="lineNum">     961 </span>            :       (_ftb_io_out_last_stage_ftb_entry_last_may_be_rvi_call),</a>
+<a name="962"><span class="lineNum">     962 </span>            :     .io_out_last_stage_ftb_entry_always_taken_0</a>
+<a name="963"><span class="lineNum">     963 </span>            :       (_ftb_io_out_last_stage_ftb_entry_always_taken_0),</a>
+<a name="964"><span class="lineNum">     964 </span>            :     .io_out_last_stage_ftb_entry_always_taken_1</a>
+<a name="965"><span class="lineNum">     965 </span>            :       (_ftb_io_out_last_stage_ftb_entry_always_taken_1),</a>
+<a name="966"><span class="lineNum">     966 </span>            :     .io_ctrl_btb_enable</a>
+<a name="967"><span class="lineNum">     967 </span>            :       (_ftb_io_ctrl_delay_io_out_btb_enable),</a>
+<a name="968"><span class="lineNum">     968 </span>            :     .io_s0_fire_0                                        (io_s0_fire_0),</a>
+<a name="969"><span class="lineNum">     969 </span>            :     .io_s0_fire_1                                        (io_s0_fire_1),</a>
+<a name="970"><span class="lineNum">     970 </span>            :     .io_s0_fire_2                                        (io_s0_fire_2),</a>
+<a name="971"><span class="lineNum">     971 </span>            :     .io_s0_fire_3                                        (io_s0_fire_3),</a>
+<a name="972"><span class="lineNum">     972 </span>            :     .io_s1_fire_0                                        (io_s1_fire_0),</a>
+<a name="973"><span class="lineNum">     973 </span>            :     .io_s1_fire_1                                        (io_s1_fire_1),</a>
+<a name="974"><span class="lineNum">     974 </span>            :     .io_s1_fire_2                                        (io_s1_fire_2),</a>
+<a name="975"><span class="lineNum">     975 </span>            :     .io_s1_fire_3                                        (io_s1_fire_3),</a>
+<a name="976"><span class="lineNum">     976 </span>            :     .io_s2_fire_0                                        (io_s2_fire_0),</a>
+<a name="977"><span class="lineNum">     977 </span>            :     .io_s2_fire_1                                        (io_s2_fire_1),</a>
+<a name="978"><span class="lineNum">     978 </span>            :     .io_s2_fire_2                                        (io_s2_fire_2),</a>
+<a name="979"><span class="lineNum">     979 </span>            :     .io_s2_fire_3                                        (io_s2_fire_3),</a>
+<a name="980"><span class="lineNum">     980 </span>            :     .io_s1_ready                                         (_ftb_io_s1_ready),</a>
+<a name="981"><span class="lineNum">     981 </span>            :     .io_update_valid                                     (io_update_valid),</a>
+<a name="982"><span class="lineNum">     982 </span>            :     .io_update_bits_pc                                   (io_update_bits_pc),</a>
+<a name="983"><span class="lineNum">     983 </span>            :     .io_update_bits_ftb_entry_valid                      (io_update_bits_ftb_entry_valid),</a>
+<a name="984"><span class="lineNum">     984 </span>            :     .io_update_bits_ftb_entry_brSlots_0_offset</a>
+<a name="985"><span class="lineNum">     985 </span>            :       (io_update_bits_ftb_entry_brSlots_0_offset),</a>
+<a name="986"><span class="lineNum">     986 </span>            :     .io_update_bits_ftb_entry_brSlots_0_lower</a>
+<a name="987"><span class="lineNum">     987 </span>            :       (io_update_bits_ftb_entry_brSlots_0_lower),</a>
+<a name="988"><span class="lineNum">     988 </span>            :     .io_update_bits_ftb_entry_brSlots_0_tarStat</a>
+<a name="989"><span class="lineNum">     989 </span>            :       (io_update_bits_ftb_entry_brSlots_0_tarStat),</a>
+<a name="990"><span class="lineNum">     990 </span>            :     .io_update_bits_ftb_entry_brSlots_0_sharing</a>
+<a name="991"><span class="lineNum">     991 </span>            :       (io_update_bits_ftb_entry_brSlots_0_sharing),</a>
+<a name="992"><span class="lineNum">     992 </span>            :     .io_update_bits_ftb_entry_brSlots_0_valid</a>
+<a name="993"><span class="lineNum">     993 </span>            :       (io_update_bits_ftb_entry_brSlots_0_valid),</a>
+<a name="994"><span class="lineNum">     994 </span>            :     .io_update_bits_ftb_entry_tailSlot_offset</a>
+<a name="995"><span class="lineNum">     995 </span>            :       (io_update_bits_ftb_entry_tailSlot_offset),</a>
+<a name="996"><span class="lineNum">     996 </span>            :     .io_update_bits_ftb_entry_tailSlot_lower</a>
+<a name="997"><span class="lineNum">     997 </span>            :       (io_update_bits_ftb_entry_tailSlot_lower),</a>
+<a name="998"><span class="lineNum">     998 </span>            :     .io_update_bits_ftb_entry_tailSlot_tarStat</a>
+<a name="999"><span class="lineNum">     999 </span>            :       (io_update_bits_ftb_entry_tailSlot_tarStat),</a>
+<a name="1000"><span class="lineNum">    1000 </span>            :     .io_update_bits_ftb_entry_tailSlot_sharing</a>
+<a name="1001"><span class="lineNum">    1001 </span>            :       (io_update_bits_ftb_entry_tailSlot_sharing),</a>
+<a name="1002"><span class="lineNum">    1002 </span>            :     .io_update_bits_ftb_entry_tailSlot_valid</a>
+<a name="1003"><span class="lineNum">    1003 </span>            :       (io_update_bits_ftb_entry_tailSlot_valid),</a>
+<a name="1004"><span class="lineNum">    1004 </span>            :     .io_update_bits_ftb_entry_pftAddr</a>
+<a name="1005"><span class="lineNum">    1005 </span>            :       (io_update_bits_ftb_entry_pftAddr),</a>
+<a name="1006"><span class="lineNum">    1006 </span>            :     .io_update_bits_ftb_entry_carry                      (io_update_bits_ftb_entry_carry),</a>
+<a name="1007"><span class="lineNum">    1007 </span>            :     .io_update_bits_ftb_entry_isCall</a>
+<a name="1008"><span class="lineNum">    1008 </span>            :       (io_update_bits_ftb_entry_isCall),</a>
+<a name="1009"><span class="lineNum">    1009 </span>            :     .io_update_bits_ftb_entry_isRet                      (io_update_bits_ftb_entry_isRet),</a>
+<a name="1010"><span class="lineNum">    1010 </span>            :     .io_update_bits_ftb_entry_isJalr</a>
+<a name="1011"><span class="lineNum">    1011 </span>            :       (io_update_bits_ftb_entry_isJalr),</a>
+<a name="1012"><span class="lineNum">    1012 </span>            :     .io_update_bits_ftb_entry_last_may_be_rvi_call</a>
+<a name="1013"><span class="lineNum">    1013 </span>            :       (io_update_bits_ftb_entry_last_may_be_rvi_call),</a>
+<a name="1014"><span class="lineNum">    1014 </span>            :     .io_update_bits_ftb_entry_always_taken_0</a>
+<a name="1015"><span class="lineNum">    1015 </span>            :       (io_update_bits_ftb_entry_always_taken_0),</a>
+<a name="1016"><span class="lineNum">    1016 </span>            :     .io_update_bits_ftb_entry_always_taken_1</a>
+<a name="1017"><span class="lineNum">    1017 </span>            :       (io_update_bits_ftb_entry_always_taken_1),</a>
+<a name="1018"><span class="lineNum">    1018 </span>            :     .io_update_bits_old_entry                            (io_update_bits_old_entry),</a>
+<a name="1019"><span class="lineNum">    1019 </span>            :     .io_update_bits_meta</a>
+<a name="1020"><span class="lineNum">    1020 </span>            :       ({126'h0, io_update_bits_meta[222:126]}),</a>
+<a name="1021"><span class="lineNum">    1021 </span>            :     .io_perf_0_value                                     (_ftb_io_perf_0_value),</a>
+<a name="1022"><span class="lineNum">    1022 </span>            :     .io_perf_1_value                                     (_ftb_io_perf_1_value)</a>
+<a name="1023"><span class="lineNum">    1023 </span>            :   );</a>
+<a name="1024"><span class="lineNum">    1024 </span>            :   FauFTB ubtb (</a>
+<a name="1025"><span class="lineNum">    1025 </span>            :     .clock                                      (clock),</a>
+<a name="1026"><span class="lineNum">    1026 </span>            :     .reset                                      (reset),</a>
+<a name="1027"><span class="lineNum">    1027 </span>            :     .io_reset_vector                            (io_reset_vector),</a>
+<a name="1028"><span class="lineNum">    1028 </span>            :     .io_in_bits_s0_pc_0                         (io_in_bits_s0_pc_0),</a>
+<a name="1029"><span class="lineNum">    1029 </span>            :     .io_in_bits_s0_pc_1                         (io_in_bits_s0_pc_1),</a>
+<a name="1030"><span class="lineNum">    1030 </span>            :     .io_in_bits_s0_pc_2                         (io_in_bits_s0_pc_2),</a>
+<a name="1031"><span class="lineNum">    1031 </span>            :     .io_in_bits_s0_pc_3                         (io_in_bits_s0_pc_3),</a>
+<a name="1032"><span class="lineNum">    1032 </span>            :     .io_out_s1_pc_0                             (io_out_s1_pc_0),</a>
+<a name="1033"><span class="lineNum">    1033 </span>            :     .io_out_s1_pc_1                             (io_out_s1_pc_1),</a>
+<a name="1034"><span class="lineNum">    1034 </span>            :     .io_out_s1_pc_2                             (io_out_s1_pc_2),</a>
+<a name="1035"><span class="lineNum">    1035 </span>            :     .io_out_s1_pc_3                             (io_out_s1_pc_3),</a>
+<a name="1036"><span class="lineNum">    1036 </span>            :     .io_out_s1_full_pred_0_br_taken_mask_0      (io_out_s1_full_pred_0_br_taken_mask_0),</a>
+<a name="1037"><span class="lineNum">    1037 </span>            :     .io_out_s1_full_pred_0_br_taken_mask_1      (io_out_s1_full_pred_0_br_taken_mask_1),</a>
+<a name="1038"><span class="lineNum">    1038 </span>            :     .io_out_s1_full_pred_0_slot_valids_0        (io_out_s1_full_pred_0_slot_valids_0),</a>
+<a name="1039"><span class="lineNum">    1039 </span>            :     .io_out_s1_full_pred_0_slot_valids_1        (io_out_s1_full_pred_0_slot_valids_1),</a>
+<a name="1040"><span class="lineNum">    1040 </span>            :     .io_out_s1_full_pred_0_targets_0            (io_out_s1_full_pred_0_targets_0),</a>
+<a name="1041"><span class="lineNum">    1041 </span>            :     .io_out_s1_full_pred_0_targets_1            (io_out_s1_full_pred_0_targets_1),</a>
+<a name="1042"><span class="lineNum">    1042 </span>            :     .io_out_s1_full_pred_0_offsets_0            (io_out_s1_full_pred_0_offsets_0),</a>
+<a name="1043"><span class="lineNum">    1043 </span>            :     .io_out_s1_full_pred_0_offsets_1            (io_out_s1_full_pred_0_offsets_1),</a>
+<a name="1044"><span class="lineNum">    1044 </span>            :     .io_out_s1_full_pred_0_fallThroughAddr      (io_out_s1_full_pred_0_fallThroughAddr),</a>
+<a name="1045"><span class="lineNum">    1045 </span>            :     .io_out_s1_full_pred_0_is_br_sharing        (io_out_s1_full_pred_0_is_br_sharing),</a>
+<a name="1046"><span class="lineNum">    1046 </span>            :     .io_out_s1_full_pred_0_hit                  (io_out_s1_full_pred_0_hit),</a>
+<a name="1047"><span class="lineNum">    1047 </span>            :     .io_out_s1_full_pred_1_br_taken_mask_0      (io_out_s1_full_pred_1_br_taken_mask_0),</a>
+<a name="1048"><span class="lineNum">    1048 </span>            :     .io_out_s1_full_pred_1_br_taken_mask_1      (io_out_s1_full_pred_1_br_taken_mask_1),</a>
+<a name="1049"><span class="lineNum">    1049 </span>            :     .io_out_s1_full_pred_1_slot_valids_0        (io_out_s1_full_pred_1_slot_valids_0),</a>
+<a name="1050"><span class="lineNum">    1050 </span>            :     .io_out_s1_full_pred_1_slot_valids_1        (io_out_s1_full_pred_1_slot_valids_1),</a>
+<a name="1051"><span class="lineNum">    1051 </span>            :     .io_out_s1_full_pred_1_targets_0            (io_out_s1_full_pred_1_targets_0),</a>
+<a name="1052"><span class="lineNum">    1052 </span>            :     .io_out_s1_full_pred_1_targets_1            (io_out_s1_full_pred_1_targets_1),</a>
+<a name="1053"><span class="lineNum">    1053 </span>            :     .io_out_s1_full_pred_1_offsets_0            (io_out_s1_full_pred_1_offsets_0),</a>
+<a name="1054"><span class="lineNum">    1054 </span>            :     .io_out_s1_full_pred_1_offsets_1            (io_out_s1_full_pred_1_offsets_1),</a>
+<a name="1055"><span class="lineNum">    1055 </span>            :     .io_out_s1_full_pred_1_fallThroughAddr      (io_out_s1_full_pred_1_fallThroughAddr),</a>
+<a name="1056"><span class="lineNum">    1056 </span>            :     .io_out_s1_full_pred_1_is_br_sharing        (io_out_s1_full_pred_1_is_br_sharing),</a>
+<a name="1057"><span class="lineNum">    1057 </span>            :     .io_out_s1_full_pred_1_hit                  (io_out_s1_full_pred_1_hit),</a>
+<a name="1058"><span class="lineNum">    1058 </span>            :     .io_out_s1_full_pred_2_br_taken_mask_0      (io_out_s1_full_pred_2_br_taken_mask_0),</a>
+<a name="1059"><span class="lineNum">    1059 </span>            :     .io_out_s1_full_pred_2_br_taken_mask_1      (io_out_s1_full_pred_2_br_taken_mask_1),</a>
+<a name="1060"><span class="lineNum">    1060 </span>            :     .io_out_s1_full_pred_2_slot_valids_0        (io_out_s1_full_pred_2_slot_valids_0),</a>
+<a name="1061"><span class="lineNum">    1061 </span>            :     .io_out_s1_full_pred_2_slot_valids_1        (io_out_s1_full_pred_2_slot_valids_1),</a>
+<a name="1062"><span class="lineNum">    1062 </span>            :     .io_out_s1_full_pred_2_targets_0            (io_out_s1_full_pred_2_targets_0),</a>
+<a name="1063"><span class="lineNum">    1063 </span>            :     .io_out_s1_full_pred_2_targets_1            (io_out_s1_full_pred_2_targets_1),</a>
+<a name="1064"><span class="lineNum">    1064 </span>            :     .io_out_s1_full_pred_2_offsets_0            (io_out_s1_full_pred_2_offsets_0),</a>
+<a name="1065"><span class="lineNum">    1065 </span>            :     .io_out_s1_full_pred_2_offsets_1            (io_out_s1_full_pred_2_offsets_1),</a>
+<a name="1066"><span class="lineNum">    1066 </span>            :     .io_out_s1_full_pred_2_fallThroughAddr      (io_out_s1_full_pred_2_fallThroughAddr),</a>
+<a name="1067"><span class="lineNum">    1067 </span>            :     .io_out_s1_full_pred_2_is_br_sharing        (io_out_s1_full_pred_2_is_br_sharing),</a>
+<a name="1068"><span class="lineNum">    1068 </span>            :     .io_out_s1_full_pred_2_hit                  (io_out_s1_full_pred_2_hit),</a>
+<a name="1069"><span class="lineNum">    1069 </span>            :     .io_out_s1_full_pred_3_br_taken_mask_0      (io_out_s1_full_pred_3_br_taken_mask_0),</a>
+<a name="1070"><span class="lineNum">    1070 </span>            :     .io_out_s1_full_pred_3_br_taken_mask_1      (io_out_s1_full_pred_3_br_taken_mask_1),</a>
+<a name="1071"><span class="lineNum">    1071 </span>            :     .io_out_s1_full_pred_3_slot_valids_0        (io_out_s1_full_pred_3_slot_valids_0),</a>
+<a name="1072"><span class="lineNum">    1072 </span>            :     .io_out_s1_full_pred_3_slot_valids_1        (io_out_s1_full_pred_3_slot_valids_1),</a>
+<a name="1073"><span class="lineNum">    1073 </span>            :     .io_out_s1_full_pred_3_targets_0            (io_out_s1_full_pred_3_targets_0),</a>
+<a name="1074"><span class="lineNum">    1074 </span>            :     .io_out_s1_full_pred_3_targets_1            (io_out_s1_full_pred_3_targets_1),</a>
+<a name="1075"><span class="lineNum">    1075 </span>            :     .io_out_s1_full_pred_3_offsets_0            (io_out_s1_full_pred_3_offsets_0),</a>
+<a name="1076"><span class="lineNum">    1076 </span>            :     .io_out_s1_full_pred_3_offsets_1            (io_out_s1_full_pred_3_offsets_1),</a>
+<a name="1077"><span class="lineNum">    1077 </span>            :     .io_out_s1_full_pred_3_fallThroughAddr      (io_out_s1_full_pred_3_fallThroughAddr),</a>
+<a name="1078"><span class="lineNum">    1078 </span>            :     .io_out_s1_full_pred_3_fallThroughErr       (io_out_s1_full_pred_3_fallThroughErr),</a>
+<a name="1079"><span class="lineNum">    1079 </span>            :     .io_out_s1_full_pred_3_is_br_sharing        (io_out_s1_full_pred_3_is_br_sharing),</a>
+<a name="1080"><span class="lineNum">    1080 </span>            :     .io_out_s1_full_pred_3_hit                  (io_out_s1_full_pred_3_hit),</a>
+<a name="1081"><span class="lineNum">    1081 </span>            :     .io_out_last_stage_meta                     (_ubtb_io_out_last_stage_meta),</a>
+<a name="1082"><span class="lineNum">    1082 </span>            :     .io_ctrl_ubtb_enable                        (_ubtb_io_ctrl_delay_io_out_ubtb_enable),</a>
+<a name="1083"><span class="lineNum">    1083 </span>            :     .io_s0_fire_0                               (io_s0_fire_0),</a>
+<a name="1084"><span class="lineNum">    1084 </span>            :     .io_s0_fire_1                               (io_s0_fire_1),</a>
+<a name="1085"><span class="lineNum">    1085 </span>            :     .io_s0_fire_2                               (io_s0_fire_2),</a>
+<a name="1086"><span class="lineNum">    1086 </span>            :     .io_s0_fire_3                               (io_s0_fire_3),</a>
+<a name="1087"><span class="lineNum">    1087 </span>            :     .io_s1_fire_0                               (io_s1_fire_0),</a>
+<a name="1088"><span class="lineNum">    1088 </span>            :     .io_s2_fire_0                               (io_s2_fire_0),</a>
+<a name="1089"><span class="lineNum">    1089 </span>            :     .io_update_valid                            (io_update_valid),</a>
+<a name="1090"><span class="lineNum">    1090 </span>            :     .io_update_bits_pc                          (io_update_bits_pc),</a>
+<a name="1091"><span class="lineNum">    1091 </span>            :     .io_update_bits_ftb_entry_brSlots_0_offset</a>
+<a name="1092"><span class="lineNum">    1092 </span>            :       (io_update_bits_ftb_entry_brSlots_0_offset),</a>
+<a name="1093"><span class="lineNum">    1093 </span>            :     .io_update_bits_ftb_entry_brSlots_0_lower</a>
+<a name="1094"><span class="lineNum">    1094 </span>            :       (io_update_bits_ftb_entry_brSlots_0_lower),</a>
+<a name="1095"><span class="lineNum">    1095 </span>            :     .io_update_bits_ftb_entry_brSlots_0_tarStat</a>
+<a name="1096"><span class="lineNum">    1096 </span>            :       (io_update_bits_ftb_entry_brSlots_0_tarStat),</a>
+<a name="1097"><span class="lineNum">    1097 </span>            :     .io_update_bits_ftb_entry_brSlots_0_valid</a>
+<a name="1098"><span class="lineNum">    1098 </span>            :       (io_update_bits_ftb_entry_brSlots_0_valid),</a>
+<a name="1099"><span class="lineNum">    1099 </span>            :     .io_update_bits_ftb_entry_tailSlot_offset</a>
+<a name="1100"><span class="lineNum">    1100 </span>            :       (io_update_bits_ftb_entry_tailSlot_offset),</a>
+<a name="1101"><span class="lineNum">    1101 </span>            :     .io_update_bits_ftb_entry_tailSlot_lower    (io_update_bits_ftb_entry_tailSlot_lower),</a>
+<a name="1102"><span class="lineNum">    1102 </span>            :     .io_update_bits_ftb_entry_tailSlot_tarStat</a>
+<a name="1103"><span class="lineNum">    1103 </span>            :       (io_update_bits_ftb_entry_tailSlot_tarStat),</a>
+<a name="1104"><span class="lineNum">    1104 </span>            :     .io_update_bits_ftb_entry_tailSlot_sharing</a>
+<a name="1105"><span class="lineNum">    1105 </span>            :       (io_update_bits_ftb_entry_tailSlot_sharing),</a>
+<a name="1106"><span class="lineNum">    1106 </span>            :     .io_update_bits_ftb_entry_tailSlot_valid    (io_update_bits_ftb_entry_tailSlot_valid),</a>
+<a name="1107"><span class="lineNum">    1107 </span>            :     .io_update_bits_ftb_entry_pftAddr           (io_update_bits_ftb_entry_pftAddr),</a>
+<a name="1108"><span class="lineNum">    1108 </span>            :     .io_update_bits_ftb_entry_carry             (io_update_bits_ftb_entry_carry),</a>
+<a name="1109"><span class="lineNum">    1109 </span>            :     .io_update_bits_ftb_entry_always_taken_0    (io_update_bits_ftb_entry_always_taken_0),</a>
+<a name="1110"><span class="lineNum">    1110 </span>            :     .io_update_bits_ftb_entry_always_taken_1    (io_update_bits_ftb_entry_always_taken_1),</a>
+<a name="1111"><span class="lineNum">    1111 </span>            :     .io_update_bits_br_taken_mask_0             (io_update_bits_br_taken_mask_0),</a>
+<a name="1112"><span class="lineNum">    1112 </span>            :     .io_update_bits_br_taken_mask_1             (io_update_bits_br_taken_mask_1),</a>
+<a name="1113"><span class="lineNum">    1113 </span>            :     .io_update_bits_meta                        ({217'h0, io_update_bits_meta[222:217]}),</a>
+<a name="1114"><span class="lineNum">    1114 </span>            :     .io_perf_0_value                            (_ubtb_io_perf_0_value),</a>
+<a name="1115"><span class="lineNum">    1115 </span>            :     .io_perf_1_value                            (_ubtb_io_perf_1_value)</a>
+<a name="1116"><span class="lineNum">    1116 </span>            :   );</a>
+<a name="1117"><span class="lineNum">    1117 </span>            :   Tage_SC tage (</a>
+<a name="1118"><span class="lineNum">    1118 </span>            :     .clock                                                    (clock),</a>
+<a name="1119"><span class="lineNum">    1119 </span>            :     .reset                                                    (reset),</a>
+<a name="1120"><span class="lineNum">    1120 </span>            :     .io_reset_vector                                          (io_reset_vector),</a>
+<a name="1121"><span class="lineNum">    1121 </span>            :     .io_in_bits_s0_pc_0                                       (io_in_bits_s0_pc_0),</a>
+<a name="1122"><span class="lineNum">    1122 </span>            :     .io_in_bits_s0_pc_1                                       (io_in_bits_s0_pc_1),</a>
+<a name="1123"><span class="lineNum">    1123 </span>            :     .io_in_bits_s0_pc_3                                       (io_in_bits_s0_pc_3),</a>
+<a name="1124"><span class="lineNum">    1124 </span>            :     .io_in_bits_folded_hist_1_hist_17_folded_hist</a>
+<a name="1125"><span class="lineNum">    1125 </span>            :       (io_in_bits_folded_hist_1_hist_17_folded_hist),</a>
+<a name="1126"><span class="lineNum">    1126 </span>            :     .io_in_bits_folded_hist_1_hist_16_folded_hist</a>
+<a name="1127"><span class="lineNum">    1127 </span>            :       (io_in_bits_folded_hist_1_hist_16_folded_hist),</a>
+<a name="1128"><span class="lineNum">    1128 </span>            :     .io_in_bits_folded_hist_1_hist_15_folded_hist</a>
+<a name="1129"><span class="lineNum">    1129 </span>            :       (io_in_bits_folded_hist_1_hist_15_folded_hist),</a>
+<a name="1130"><span class="lineNum">    1130 </span>            :     .io_in_bits_folded_hist_1_hist_14_folded_hist</a>
+<a name="1131"><span class="lineNum">    1131 </span>            :       (io_in_bits_folded_hist_1_hist_14_folded_hist),</a>
+<a name="1132"><span class="lineNum">    1132 </span>            :     .io_in_bits_folded_hist_1_hist_9_folded_hist</a>
+<a name="1133"><span class="lineNum">    1133 </span>            :       (io_in_bits_folded_hist_1_hist_9_folded_hist),</a>
+<a name="1134"><span class="lineNum">    1134 </span>            :     .io_in_bits_folded_hist_1_hist_8_folded_hist</a>
+<a name="1135"><span class="lineNum">    1135 </span>            :       (io_in_bits_folded_hist_1_hist_8_folded_hist),</a>
+<a name="1136"><span class="lineNum">    1136 </span>            :     .io_in_bits_folded_hist_1_hist_7_folded_hist</a>
+<a name="1137"><span class="lineNum">    1137 </span>            :       (io_in_bits_folded_hist_1_hist_7_folded_hist),</a>
+<a name="1138"><span class="lineNum">    1138 </span>            :     .io_in_bits_folded_hist_1_hist_5_folded_hist</a>
+<a name="1139"><span class="lineNum">    1139 </span>            :       (io_in_bits_folded_hist_1_hist_5_folded_hist),</a>
+<a name="1140"><span class="lineNum">    1140 </span>            :     .io_in_bits_folded_hist_1_hist_4_folded_hist</a>
+<a name="1141"><span class="lineNum">    1141 </span>            :       (io_in_bits_folded_hist_1_hist_4_folded_hist),</a>
+<a name="1142"><span class="lineNum">    1142 </span>            :     .io_in_bits_folded_hist_1_hist_3_folded_hist</a>
+<a name="1143"><span class="lineNum">    1143 </span>            :       (io_in_bits_folded_hist_1_hist_3_folded_hist),</a>
+<a name="1144"><span class="lineNum">    1144 </span>            :     .io_in_bits_folded_hist_1_hist_1_folded_hist</a>
+<a name="1145"><span class="lineNum">    1145 </span>            :       (io_in_bits_folded_hist_1_hist_1_folded_hist),</a>
+<a name="1146"><span class="lineNum">    1146 </span>            :     .io_in_bits_folded_hist_3_hist_12_folded_hist</a>
+<a name="1147"><span class="lineNum">    1147 </span>            :       (io_in_bits_folded_hist_3_hist_12_folded_hist),</a>
+<a name="1148"><span class="lineNum">    1148 </span>            :     .io_in_bits_folded_hist_3_hist_11_folded_hist</a>
+<a name="1149"><span class="lineNum">    1149 </span>            :       (io_in_bits_folded_hist_3_hist_11_folded_hist),</a>
+<a name="1150"><span class="lineNum">    1150 </span>            :     .io_in_bits_folded_hist_3_hist_2_folded_hist</a>
+<a name="1151"><span class="lineNum">    1151 </span>            :       (io_in_bits_folded_hist_3_hist_2_folded_hist),</a>
+<a name="1152"><span class="lineNum">    1152 </span>            :     .io_out_s2_full_pred_0_br_taken_mask_0</a>
+<a name="1153"><span class="lineNum">    1153 </span>            :       (_tage_io_out_s2_full_pred_0_br_taken_mask_0),</a>
+<a name="1154"><span class="lineNum">    1154 </span>            :     .io_out_s2_full_pred_0_br_taken_mask_1</a>
+<a name="1155"><span class="lineNum">    1155 </span>            :       (_tage_io_out_s2_full_pred_0_br_taken_mask_1),</a>
+<a name="1156"><span class="lineNum">    1156 </span>            :     .io_out_s2_full_pred_1_br_taken_mask_0</a>
+<a name="1157"><span class="lineNum">    1157 </span>            :       (_tage_io_out_s2_full_pred_1_br_taken_mask_0),</a>
+<a name="1158"><span class="lineNum">    1158 </span>            :     .io_out_s2_full_pred_1_br_taken_mask_1</a>
+<a name="1159"><span class="lineNum">    1159 </span>            :       (_tage_io_out_s2_full_pred_1_br_taken_mask_1),</a>
+<a name="1160"><span class="lineNum">    1160 </span>            :     .io_out_s2_full_pred_2_br_taken_mask_0</a>
+<a name="1161"><span class="lineNum">    1161 </span>            :       (_tage_io_out_s2_full_pred_2_br_taken_mask_0),</a>
+<a name="1162"><span class="lineNum">    1162 </span>            :     .io_out_s2_full_pred_2_br_taken_mask_1</a>
+<a name="1163"><span class="lineNum">    1163 </span>            :       (_tage_io_out_s2_full_pred_2_br_taken_mask_1),</a>
+<a name="1164"><span class="lineNum">    1164 </span>            :     .io_out_s2_full_pred_3_br_taken_mask_0</a>
+<a name="1165"><span class="lineNum">    1165 </span>            :       (_tage_io_out_s2_full_pred_3_br_taken_mask_0),</a>
+<a name="1166"><span class="lineNum">    1166 </span>            :     .io_out_s2_full_pred_3_br_taken_mask_1</a>
+<a name="1167"><span class="lineNum">    1167 </span>            :       (_tage_io_out_s2_full_pred_3_br_taken_mask_1),</a>
+<a name="1168"><span class="lineNum">    1168 </span>            :     .io_out_s3_full_pred_0_br_taken_mask_0</a>
+<a name="1169"><span class="lineNum">    1169 </span>            :       (_tage_io_out_s3_full_pred_0_br_taken_mask_0),</a>
+<a name="1170"><span class="lineNum">    1170 </span>            :     .io_out_s3_full_pred_0_br_taken_mask_1</a>
+<a name="1171"><span class="lineNum">    1171 </span>            :       (_tage_io_out_s3_full_pred_0_br_taken_mask_1),</a>
+<a name="1172"><span class="lineNum">    1172 </span>            :     .io_out_s3_full_pred_1_br_taken_mask_0</a>
+<a name="1173"><span class="lineNum">    1173 </span>            :       (_tage_io_out_s3_full_pred_1_br_taken_mask_0),</a>
+<a name="1174"><span class="lineNum">    1174 </span>            :     .io_out_s3_full_pred_1_br_taken_mask_1</a>
+<a name="1175"><span class="lineNum">    1175 </span>            :       (_tage_io_out_s3_full_pred_1_br_taken_mask_1),</a>
+<a name="1176"><span class="lineNum">    1176 </span>            :     .io_out_s3_full_pred_2_br_taken_mask_0</a>
+<a name="1177"><span class="lineNum">    1177 </span>            :       (_tage_io_out_s3_full_pred_2_br_taken_mask_0),</a>
+<a name="1178"><span class="lineNum">    1178 </span>            :     .io_out_s3_full_pred_2_br_taken_mask_1</a>
+<a name="1179"><span class="lineNum">    1179 </span>            :       (_tage_io_out_s3_full_pred_2_br_taken_mask_1),</a>
+<a name="1180"><span class="lineNum">    1180 </span>            :     .io_out_s3_full_pred_3_br_taken_mask_0</a>
+<a name="1181"><span class="lineNum">    1181 </span>            :       (_tage_io_out_s3_full_pred_3_br_taken_mask_0),</a>
+<a name="1182"><span class="lineNum">    1182 </span>            :     .io_out_s3_full_pred_3_br_taken_mask_1</a>
+<a name="1183"><span class="lineNum">    1183 </span>            :       (_tage_io_out_s3_full_pred_3_br_taken_mask_1),</a>
+<a name="1184"><span class="lineNum">    1184 </span>            :     .io_out_last_stage_meta</a>
+<a name="1185"><span class="lineNum">    1185 </span>            :       (_tage_io_out_last_stage_meta),</a>
+<a name="1186"><span class="lineNum">    1186 </span>            :     .io_ctrl_tage_enable</a>
+<a name="1187"><span class="lineNum">    1187 </span>            :       (_tage_io_ctrl_delay_io_out_tage_enable),</a>
+<a name="1188"><span class="lineNum">    1188 </span>            :     .io_ctrl_sc_enable</a>
+<a name="1189"><span class="lineNum">    1189 </span>            :       (_tage_io_ctrl_delay_io_out_sc_enable),</a>
+<a name="1190"><span class="lineNum">    1190 </span>            :     .io_s0_fire_0                                             (io_s0_fire_0),</a>
+<a name="1191"><span class="lineNum">    1191 </span>            :     .io_s0_fire_1                                             (io_s0_fire_1),</a>
+<a name="1192"><span class="lineNum">    1192 </span>            :     .io_s0_fire_3                                             (io_s0_fire_3),</a>
+<a name="1193"><span class="lineNum">    1193 </span>            :     .io_s1_fire_0                                             (io_s1_fire_0),</a>
+<a name="1194"><span class="lineNum">    1194 </span>            :     .io_s1_fire_1                                             (io_s1_fire_1),</a>
+<a name="1195"><span class="lineNum">    1195 </span>            :     .io_s1_fire_2                                             (io_s1_fire_2),</a>
+<a name="1196"><span class="lineNum">    1196 </span>            :     .io_s1_fire_3                                             (io_s1_fire_3),</a>
+<a name="1197"><span class="lineNum">    1197 </span>            :     .io_s2_fire_0                                             (io_s2_fire_0),</a>
+<a name="1198"><span class="lineNum">    1198 </span>            :     .io_s2_fire_1                                             (io_s2_fire_1),</a>
+<a name="1199"><span class="lineNum">    1199 </span>            :     .io_s2_fire_2                                             (io_s2_fire_2),</a>
+<a name="1200"><span class="lineNum">    1200 </span>            :     .io_s2_fire_3                                             (io_s2_fire_3),</a>
+<a name="1201"><span class="lineNum">    1201 </span>            :     .io_s1_ready                                              (_tage_io_s1_ready),</a>
+<a name="1202"><span class="lineNum">    1202 </span>            :     .io_update_valid                                          (io_update_valid),</a>
+<a name="1203"><span class="lineNum">    1203 </span>            :     .io_update_bits_pc                                        (io_update_bits_pc),</a>
+<a name="1204"><span class="lineNum">    1204 </span>            :     .io_update_bits_spec_info_folded_hist_hist_17_folded_hist</a>
+<a name="1205"><span class="lineNum">    1205 </span>            :       (io_update_bits_spec_info_folded_hist_hist_17_folded_hist),</a>
+<a name="1206"><span class="lineNum">    1206 </span>            :     .io_update_bits_spec_info_folded_hist_hist_16_folded_hist</a>
+<a name="1207"><span class="lineNum">    1207 </span>            :       (io_update_bits_spec_info_folded_hist_hist_16_folded_hist),</a>
+<a name="1208"><span class="lineNum">    1208 </span>            :     .io_update_bits_spec_info_folded_hist_hist_15_folded_hist</a>
+<a name="1209"><span class="lineNum">    1209 </span>            :       (io_update_bits_spec_info_folded_hist_hist_15_folded_hist),</a>
+<a name="1210"><span class="lineNum">    1210 </span>            :     .io_update_bits_spec_info_folded_hist_hist_14_folded_hist</a>
+<a name="1211"><span class="lineNum">    1211 </span>            :       (io_update_bits_spec_info_folded_hist_hist_14_folded_hist),</a>
+<a name="1212"><span class="lineNum">    1212 </span>            :     .io_update_bits_spec_info_folded_hist_hist_12_folded_hist</a>
+<a name="1213"><span class="lineNum">    1213 </span>            :       (io_update_bits_spec_info_folded_hist_hist_12_folded_hist),</a>
+<a name="1214"><span class="lineNum">    1214 </span>            :     .io_update_bits_spec_info_folded_hist_hist_11_folded_hist</a>
+<a name="1215"><span class="lineNum">    1215 </span>            :       (io_update_bits_spec_info_folded_hist_hist_11_folded_hist),</a>
+<a name="1216"><span class="lineNum">    1216 </span>            :     .io_update_bits_spec_info_folded_hist_hist_9_folded_hist</a>
+<a name="1217"><span class="lineNum">    1217 </span>            :       (io_update_bits_spec_info_folded_hist_hist_9_folded_hist),</a>
+<a name="1218"><span class="lineNum">    1218 </span>            :     .io_update_bits_spec_info_folded_hist_hist_8_folded_hist</a>
+<a name="1219"><span class="lineNum">    1219 </span>            :       (io_update_bits_spec_info_folded_hist_hist_8_folded_hist),</a>
+<a name="1220"><span class="lineNum">    1220 </span>            :     .io_update_bits_spec_info_folded_hist_hist_7_folded_hist</a>
+<a name="1221"><span class="lineNum">    1221 </span>            :       (io_update_bits_spec_info_folded_hist_hist_7_folded_hist),</a>
+<a name="1222"><span class="lineNum">    1222 </span>            :     .io_update_bits_spec_info_folded_hist_hist_5_folded_hist</a>
+<a name="1223"><span class="lineNum">    1223 </span>            :       (io_update_bits_spec_info_folded_hist_hist_5_folded_hist),</a>
+<a name="1224"><span class="lineNum">    1224 </span>            :     .io_update_bits_spec_info_folded_hist_hist_4_folded_hist</a>
+<a name="1225"><span class="lineNum">    1225 </span>            :       (io_update_bits_spec_info_folded_hist_hist_4_folded_hist),</a>
+<a name="1226"><span class="lineNum">    1226 </span>            :     .io_update_bits_spec_info_folded_hist_hist_3_folded_hist</a>
+<a name="1227"><span class="lineNum">    1227 </span>            :       (io_update_bits_spec_info_folded_hist_hist_3_folded_hist),</a>
+<a name="1228"><span class="lineNum">    1228 </span>            :     .io_update_bits_spec_info_folded_hist_hist_2_folded_hist</a>
+<a name="1229"><span class="lineNum">    1229 </span>            :       (io_update_bits_spec_info_folded_hist_hist_2_folded_hist),</a>
+<a name="1230"><span class="lineNum">    1230 </span>            :     .io_update_bits_spec_info_folded_hist_hist_1_folded_hist</a>
+<a name="1231"><span class="lineNum">    1231 </span>            :       (io_update_bits_spec_info_folded_hist_hist_1_folded_hist),</a>
+<a name="1232"><span class="lineNum">    1232 </span>            :     .io_update_bits_ftb_entry_brSlots_0_valid</a>
+<a name="1233"><span class="lineNum">    1233 </span>            :       (io_update_bits_ftb_entry_brSlots_0_valid),</a>
+<a name="1234"><span class="lineNum">    1234 </span>            :     .io_update_bits_ftb_entry_tailSlot_sharing</a>
+<a name="1235"><span class="lineNum">    1235 </span>            :       (io_update_bits_ftb_entry_tailSlot_sharing),</a>
+<a name="1236"><span class="lineNum">    1236 </span>            :     .io_update_bits_ftb_entry_tailSlot_valid</a>
+<a name="1237"><span class="lineNum">    1237 </span>            :       (io_update_bits_ftb_entry_tailSlot_valid),</a>
+<a name="1238"><span class="lineNum">    1238 </span>            :     .io_update_bits_ftb_entry_always_taken_0</a>
+<a name="1239"><span class="lineNum">    1239 </span>            :       (io_update_bits_ftb_entry_always_taken_0),</a>
+<a name="1240"><span class="lineNum">    1240 </span>            :     .io_update_bits_ftb_entry_always_taken_1</a>
+<a name="1241"><span class="lineNum">    1241 </span>            :       (io_update_bits_ftb_entry_always_taken_1),</a>
+<a name="1242"><span class="lineNum">    1242 </span>            :     .io_update_bits_br_taken_mask_0</a>
+<a name="1243"><span class="lineNum">    1243 </span>            :       (io_update_bits_br_taken_mask_0),</a>
+<a name="1244"><span class="lineNum">    1244 </span>            :     .io_update_bits_br_taken_mask_1</a>
+<a name="1245"><span class="lineNum">    1245 </span>            :       (io_update_bits_br_taken_mask_1),</a>
+<a name="1246"><span class="lineNum">    1246 </span>            :     .io_update_bits_mispred_mask_0</a>
+<a name="1247"><span class="lineNum">    1247 </span>            :       (io_update_bits_mispred_mask_0),</a>
+<a name="1248"><span class="lineNum">    1248 </span>            :     .io_update_bits_mispred_mask_1</a>
+<a name="1249"><span class="lineNum">    1249 </span>            :       (io_update_bits_mispred_mask_1),</a>
+<a name="1250"><span class="lineNum">    1250 </span>            :     .io_update_bits_meta</a>
+<a name="1251"><span class="lineNum">    1251 </span>            :       ({129'h0, io_update_bits_meta[222:129]}),</a>
+<a name="1252"><span class="lineNum">    1252 </span>            :     .io_perf_0_value                                          (_tage_io_perf_0_value),</a>
+<a name="1253"><span class="lineNum">    1253 </span>            :     .io_perf_1_value                                          (_tage_io_perf_1_value),</a>
+<a name="1254"><span class="lineNum">    1254 </span>            :     .io_perf_2_value                                          (_tage_io_perf_2_value)</a>
+<a name="1255"><span class="lineNum">    1255 </span>            :   );</a>
+<a name="1256"><span class="lineNum">    1256 </span>            :   RAS ras (</a>
+<a name="1257"><span class="lineNum">    1257 </span>            :     .clock                                                          (clock),</a>
+<a name="1258"><span class="lineNum">    1258 </span>            :     .reset                                                          (reset),</a>
+<a name="1259"><span class="lineNum">    1259 </span>            :     .io_reset_vector                                                (io_reset_vector),</a>
+<a name="1260"><span class="lineNum">    1260 </span>            :     .io_in_bits_s0_pc_0                                             (io_in_bits_s0_pc_0),</a>
+<a name="1261"><span class="lineNum">    1261 </span>            :     .io_in_bits_s0_pc_1                                             (io_in_bits_s0_pc_1),</a>
+<a name="1262"><span class="lineNum">    1262 </span>            :     .io_in_bits_s0_pc_2                                             (io_in_bits_s0_pc_2),</a>
+<a name="1263"><span class="lineNum">    1263 </span>            :     .io_in_bits_s0_pc_3                                             (io_in_bits_s0_pc_3),</a>
+<a name="1264"><span class="lineNum">    1264 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_0</a>
+<a name="1265"><span class="lineNum">    1265 </span>            :       (_ittage_io_out_s2_full_pred_0_br_taken_mask_0),</a>
+<a name="1266"><span class="lineNum">    1266 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_1</a>
+<a name="1267"><span class="lineNum">    1267 </span>            :       (_ittage_io_out_s2_full_pred_0_br_taken_mask_1),</a>
+<a name="1268"><span class="lineNum">    1268 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_0</a>
+<a name="1269"><span class="lineNum">    1269 </span>            :       (_ittage_io_out_s2_full_pred_0_slot_valids_0),</a>
+<a name="1270"><span class="lineNum">    1270 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_1</a>
+<a name="1271"><span class="lineNum">    1271 </span>            :       (_ittage_io_out_s2_full_pred_0_slot_valids_1),</a>
+<a name="1272"><span class="lineNum">    1272 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_0_targets_0</a>
+<a name="1273"><span class="lineNum">    1273 </span>            :       (_ittage_io_out_s2_full_pred_0_targets_0),</a>
+<a name="1274"><span class="lineNum">    1274 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_0_targets_1</a>
+<a name="1275"><span class="lineNum">    1275 </span>            :       (_ittage_io_out_s2_full_pred_0_targets_1),</a>
+<a name="1276"><span class="lineNum">    1276 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_0_jalr_target</a>
+<a name="1277"><span class="lineNum">    1277 </span>            :       (_ittage_io_out_s2_full_pred_0_jalr_target),</a>
+<a name="1278"><span class="lineNum">    1278 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_0_offsets_0</a>
+<a name="1279"><span class="lineNum">    1279 </span>            :       (_ittage_io_out_s2_full_pred_0_offsets_0),</a>
+<a name="1280"><span class="lineNum">    1280 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_0_offsets_1</a>
+<a name="1281"><span class="lineNum">    1281 </span>            :       (_ittage_io_out_s2_full_pred_0_offsets_1),</a>
+<a name="1282"><span class="lineNum">    1282 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_0_fallThroughAddr</a>
+<a name="1283"><span class="lineNum">    1283 </span>            :       (_ittage_io_out_s2_full_pred_0_fallThroughAddr),</a>
+<a name="1284"><span class="lineNum">    1284 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_0_is_br_sharing</a>
+<a name="1285"><span class="lineNum">    1285 </span>            :       (_ittage_io_out_s2_full_pred_0_is_br_sharing),</a>
+<a name="1286"><span class="lineNum">    1286 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_0_hit</a>
+<a name="1287"><span class="lineNum">    1287 </span>            :       (_ittage_io_out_s2_full_pred_0_hit),</a>
+<a name="1288"><span class="lineNum">    1288 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_0</a>
+<a name="1289"><span class="lineNum">    1289 </span>            :       (_ittage_io_out_s2_full_pred_1_br_taken_mask_0),</a>
+<a name="1290"><span class="lineNum">    1290 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_1</a>
+<a name="1291"><span class="lineNum">    1291 </span>            :       (_ittage_io_out_s2_full_pred_1_br_taken_mask_1),</a>
+<a name="1292"><span class="lineNum">    1292 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_0</a>
+<a name="1293"><span class="lineNum">    1293 </span>            :       (_ittage_io_out_s2_full_pred_1_slot_valids_0),</a>
+<a name="1294"><span class="lineNum">    1294 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_1</a>
+<a name="1295"><span class="lineNum">    1295 </span>            :       (_ittage_io_out_s2_full_pred_1_slot_valids_1),</a>
+<a name="1296"><span class="lineNum">    1296 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_1_targets_0</a>
+<a name="1297"><span class="lineNum">    1297 </span>            :       (_ittage_io_out_s2_full_pred_1_targets_0),</a>
+<a name="1298"><span class="lineNum">    1298 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_1_targets_1</a>
+<a name="1299"><span class="lineNum">    1299 </span>            :       (_ittage_io_out_s2_full_pred_1_targets_1),</a>
+<a name="1300"><span class="lineNum">    1300 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_1_jalr_target</a>
+<a name="1301"><span class="lineNum">    1301 </span>            :       (_ittage_io_out_s2_full_pred_1_jalr_target),</a>
+<a name="1302"><span class="lineNum">    1302 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_1_offsets_0</a>
+<a name="1303"><span class="lineNum">    1303 </span>            :       (_ittage_io_out_s2_full_pred_1_offsets_0),</a>
+<a name="1304"><span class="lineNum">    1304 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_1_offsets_1</a>
+<a name="1305"><span class="lineNum">    1305 </span>            :       (_ittage_io_out_s2_full_pred_1_offsets_1),</a>
+<a name="1306"><span class="lineNum">    1306 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_1_fallThroughAddr</a>
+<a name="1307"><span class="lineNum">    1307 </span>            :       (_ittage_io_out_s2_full_pred_1_fallThroughAddr),</a>
+<a name="1308"><span class="lineNum">    1308 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_1_is_br_sharing</a>
+<a name="1309"><span class="lineNum">    1309 </span>            :       (_ittage_io_out_s2_full_pred_1_is_br_sharing),</a>
+<a name="1310"><span class="lineNum">    1310 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_1_hit</a>
+<a name="1311"><span class="lineNum">    1311 </span>            :       (_ittage_io_out_s2_full_pred_1_hit),</a>
+<a name="1312"><span class="lineNum">    1312 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_0</a>
+<a name="1313"><span class="lineNum">    1313 </span>            :       (_ittage_io_out_s2_full_pred_2_br_taken_mask_0),</a>
+<a name="1314"><span class="lineNum">    1314 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_1</a>
+<a name="1315"><span class="lineNum">    1315 </span>            :       (_ittage_io_out_s2_full_pred_2_br_taken_mask_1),</a>
+<a name="1316"><span class="lineNum">    1316 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_0</a>
+<a name="1317"><span class="lineNum">    1317 </span>            :       (_ittage_io_out_s2_full_pred_2_slot_valids_0),</a>
+<a name="1318"><span class="lineNum">    1318 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_1</a>
+<a name="1319"><span class="lineNum">    1319 </span>            :       (_ittage_io_out_s2_full_pred_2_slot_valids_1),</a>
+<a name="1320"><span class="lineNum">    1320 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_2_targets_0</a>
+<a name="1321"><span class="lineNum">    1321 </span>            :       (_ittage_io_out_s2_full_pred_2_targets_0),</a>
+<a name="1322"><span class="lineNum">    1322 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_2_targets_1</a>
+<a name="1323"><span class="lineNum">    1323 </span>            :       (_ittage_io_out_s2_full_pred_2_targets_1),</a>
+<a name="1324"><span class="lineNum">    1324 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_2_jalr_target</a>
+<a name="1325"><span class="lineNum">    1325 </span>            :       (_ittage_io_out_s2_full_pred_2_jalr_target),</a>
+<a name="1326"><span class="lineNum">    1326 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_2_offsets_0</a>
+<a name="1327"><span class="lineNum">    1327 </span>            :       (_ittage_io_out_s2_full_pred_2_offsets_0),</a>
+<a name="1328"><span class="lineNum">    1328 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_2_offsets_1</a>
+<a name="1329"><span class="lineNum">    1329 </span>            :       (_ittage_io_out_s2_full_pred_2_offsets_1),</a>
+<a name="1330"><span class="lineNum">    1330 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_2_fallThroughAddr</a>
+<a name="1331"><span class="lineNum">    1331 </span>            :       (_ittage_io_out_s2_full_pred_2_fallThroughAddr),</a>
+<a name="1332"><span class="lineNum">    1332 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_2_is_jalr</a>
+<a name="1333"><span class="lineNum">    1333 </span>            :       (_ittage_io_out_s2_full_pred_2_is_jalr),</a>
+<a name="1334"><span class="lineNum">    1334 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_2_is_call</a>
+<a name="1335"><span class="lineNum">    1335 </span>            :       (_ittage_io_out_s2_full_pred_2_is_call),</a>
+<a name="1336"><span class="lineNum">    1336 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_2_is_ret</a>
+<a name="1337"><span class="lineNum">    1337 </span>            :       (_ittage_io_out_s2_full_pred_2_is_ret),</a>
+<a name="1338"><span class="lineNum">    1338 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_2_last_may_be_rvi_call</a>
+<a name="1339"><span class="lineNum">    1339 </span>            :       (_ittage_io_out_s2_full_pred_2_last_may_be_rvi_call),</a>
+<a name="1340"><span class="lineNum">    1340 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing</a>
+<a name="1341"><span class="lineNum">    1341 </span>            :       (_ittage_io_out_s2_full_pred_2_is_br_sharing),</a>
+<a name="1342"><span class="lineNum">    1342 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_2_hit</a>
+<a name="1343"><span class="lineNum">    1343 </span>            :       (_ittage_io_out_s2_full_pred_2_hit),</a>
+<a name="1344"><span class="lineNum">    1344 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_0</a>
+<a name="1345"><span class="lineNum">    1345 </span>            :       (_ittage_io_out_s2_full_pred_3_br_taken_mask_0),</a>
+<a name="1346"><span class="lineNum">    1346 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_1</a>
+<a name="1347"><span class="lineNum">    1347 </span>            :       (_ittage_io_out_s2_full_pred_3_br_taken_mask_1),</a>
+<a name="1348"><span class="lineNum">    1348 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_0</a>
+<a name="1349"><span class="lineNum">    1349 </span>            :       (_ittage_io_out_s2_full_pred_3_slot_valids_0),</a>
+<a name="1350"><span class="lineNum">    1350 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_1</a>
+<a name="1351"><span class="lineNum">    1351 </span>            :       (_ittage_io_out_s2_full_pred_3_slot_valids_1),</a>
+<a name="1352"><span class="lineNum">    1352 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_3_targets_0</a>
+<a name="1353"><span class="lineNum">    1353 </span>            :       (_ittage_io_out_s2_full_pred_3_targets_0),</a>
+<a name="1354"><span class="lineNum">    1354 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_3_targets_1</a>
+<a name="1355"><span class="lineNum">    1355 </span>            :       (_ittage_io_out_s2_full_pred_3_targets_1),</a>
+<a name="1356"><span class="lineNum">    1356 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_3_jalr_target</a>
+<a name="1357"><span class="lineNum">    1357 </span>            :       (_ittage_io_out_s2_full_pred_3_jalr_target),</a>
+<a name="1358"><span class="lineNum">    1358 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_3_offsets_0</a>
+<a name="1359"><span class="lineNum">    1359 </span>            :       (_ittage_io_out_s2_full_pred_3_offsets_0),</a>
+<a name="1360"><span class="lineNum">    1360 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_3_offsets_1</a>
+<a name="1361"><span class="lineNum">    1361 </span>            :       (_ittage_io_out_s2_full_pred_3_offsets_1),</a>
+<a name="1362"><span class="lineNum">    1362 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_3_fallThroughAddr</a>
+<a name="1363"><span class="lineNum">    1363 </span>            :       (_ittage_io_out_s2_full_pred_3_fallThroughAddr),</a>
+<a name="1364"><span class="lineNum">    1364 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_3_fallThroughErr</a>
+<a name="1365"><span class="lineNum">    1365 </span>            :       (_ittage_io_out_s2_full_pred_3_fallThroughErr),</a>
+<a name="1366"><span class="lineNum">    1366 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_3_is_br_sharing</a>
+<a name="1367"><span class="lineNum">    1367 </span>            :       (_ittage_io_out_s2_full_pred_3_is_br_sharing),</a>
+<a name="1368"><span class="lineNum">    1368 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_3_hit</a>
+<a name="1369"><span class="lineNum">    1369 </span>            :       (_ittage_io_out_s2_full_pred_3_hit),</a>
+<a name="1370"><span class="lineNum">    1370 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_0</a>
+<a name="1371"><span class="lineNum">    1371 </span>            :       (_ittage_io_out_s3_full_pred_0_br_taken_mask_0),</a>
+<a name="1372"><span class="lineNum">    1372 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_1</a>
+<a name="1373"><span class="lineNum">    1373 </span>            :       (_ittage_io_out_s3_full_pred_0_br_taken_mask_1),</a>
+<a name="1374"><span class="lineNum">    1374 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_0</a>
+<a name="1375"><span class="lineNum">    1375 </span>            :       (_ittage_io_out_s3_full_pred_0_slot_valids_0),</a>
+<a name="1376"><span class="lineNum">    1376 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_1</a>
+<a name="1377"><span class="lineNum">    1377 </span>            :       (_ittage_io_out_s3_full_pred_0_slot_valids_1),</a>
+<a name="1378"><span class="lineNum">    1378 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_0_targets_0</a>
+<a name="1379"><span class="lineNum">    1379 </span>            :       (_ittage_io_out_s3_full_pred_0_targets_0),</a>
+<a name="1380"><span class="lineNum">    1380 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_0_targets_1</a>
+<a name="1381"><span class="lineNum">    1381 </span>            :       (_ittage_io_out_s3_full_pred_0_targets_1),</a>
+<a name="1382"><span class="lineNum">    1382 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_0_jalr_target</a>
+<a name="1383"><span class="lineNum">    1383 </span>            :       (_ittage_io_out_s3_full_pred_0_jalr_target),</a>
+<a name="1384"><span class="lineNum">    1384 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_0_fallThroughAddr</a>
+<a name="1385"><span class="lineNum">    1385 </span>            :       (_ittage_io_out_s3_full_pred_0_fallThroughAddr),</a>
+<a name="1386"><span class="lineNum">    1386 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_0_fallThroughErr</a>
+<a name="1387"><span class="lineNum">    1387 </span>            :       (_ittage_io_out_s3_full_pred_0_fallThroughErr),</a>
+<a name="1388"><span class="lineNum">    1388 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_0_is_br_sharing</a>
+<a name="1389"><span class="lineNum">    1389 </span>            :       (_ittage_io_out_s3_full_pred_0_is_br_sharing),</a>
+<a name="1390"><span class="lineNum">    1390 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_0_hit</a>
+<a name="1391"><span class="lineNum">    1391 </span>            :       (_ittage_io_out_s3_full_pred_0_hit),</a>
+<a name="1392"><span class="lineNum">    1392 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_0</a>
+<a name="1393"><span class="lineNum">    1393 </span>            :       (_ittage_io_out_s3_full_pred_1_br_taken_mask_0),</a>
+<a name="1394"><span class="lineNum">    1394 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_1</a>
+<a name="1395"><span class="lineNum">    1395 </span>            :       (_ittage_io_out_s3_full_pred_1_br_taken_mask_1),</a>
+<a name="1396"><span class="lineNum">    1396 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_0</a>
+<a name="1397"><span class="lineNum">    1397 </span>            :       (_ittage_io_out_s3_full_pred_1_slot_valids_0),</a>
+<a name="1398"><span class="lineNum">    1398 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_1</a>
+<a name="1399"><span class="lineNum">    1399 </span>            :       (_ittage_io_out_s3_full_pred_1_slot_valids_1),</a>
+<a name="1400"><span class="lineNum">    1400 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_1_targets_0</a>
+<a name="1401"><span class="lineNum">    1401 </span>            :       (_ittage_io_out_s3_full_pred_1_targets_0),</a>
+<a name="1402"><span class="lineNum">    1402 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_1_targets_1</a>
+<a name="1403"><span class="lineNum">    1403 </span>            :       (_ittage_io_out_s3_full_pred_1_targets_1),</a>
+<a name="1404"><span class="lineNum">    1404 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_1_jalr_target</a>
+<a name="1405"><span class="lineNum">    1405 </span>            :       (_ittage_io_out_s3_full_pred_1_jalr_target),</a>
+<a name="1406"><span class="lineNum">    1406 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_1_fallThroughAddr</a>
+<a name="1407"><span class="lineNum">    1407 </span>            :       (_ittage_io_out_s3_full_pred_1_fallThroughAddr),</a>
+<a name="1408"><span class="lineNum">    1408 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_1_fallThroughErr</a>
+<a name="1409"><span class="lineNum">    1409 </span>            :       (_ittage_io_out_s3_full_pred_1_fallThroughErr),</a>
+<a name="1410"><span class="lineNum">    1410 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_1_is_br_sharing</a>
+<a name="1411"><span class="lineNum">    1411 </span>            :       (_ittage_io_out_s3_full_pred_1_is_br_sharing),</a>
+<a name="1412"><span class="lineNum">    1412 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_1_hit</a>
+<a name="1413"><span class="lineNum">    1413 </span>            :       (_ittage_io_out_s3_full_pred_1_hit),</a>
+<a name="1414"><span class="lineNum">    1414 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_0</a>
+<a name="1415"><span class="lineNum">    1415 </span>            :       (_ittage_io_out_s3_full_pred_2_br_taken_mask_0),</a>
+<a name="1416"><span class="lineNum">    1416 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_1</a>
+<a name="1417"><span class="lineNum">    1417 </span>            :       (_ittage_io_out_s3_full_pred_2_br_taken_mask_1),</a>
+<a name="1418"><span class="lineNum">    1418 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_0</a>
+<a name="1419"><span class="lineNum">    1419 </span>            :       (_ittage_io_out_s3_full_pred_2_slot_valids_0),</a>
+<a name="1420"><span class="lineNum">    1420 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_1</a>
+<a name="1421"><span class="lineNum">    1421 </span>            :       (_ittage_io_out_s3_full_pred_2_slot_valids_1),</a>
+<a name="1422"><span class="lineNum">    1422 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_2_targets_0</a>
+<a name="1423"><span class="lineNum">    1423 </span>            :       (_ittage_io_out_s3_full_pred_2_targets_0),</a>
+<a name="1424"><span class="lineNum">    1424 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_2_targets_1</a>
+<a name="1425"><span class="lineNum">    1425 </span>            :       (_ittage_io_out_s3_full_pred_2_targets_1),</a>
+<a name="1426"><span class="lineNum">    1426 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_2_jalr_target</a>
+<a name="1427"><span class="lineNum">    1427 </span>            :       (_ittage_io_out_s3_full_pred_2_jalr_target),</a>
+<a name="1428"><span class="lineNum">    1428 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_2_fallThroughAddr</a>
+<a name="1429"><span class="lineNum">    1429 </span>            :       (_ittage_io_out_s3_full_pred_2_fallThroughAddr),</a>
+<a name="1430"><span class="lineNum">    1430 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_2_fallThroughErr</a>
+<a name="1431"><span class="lineNum">    1431 </span>            :       (_ittage_io_out_s3_full_pred_2_fallThroughErr),</a>
+<a name="1432"><span class="lineNum">    1432 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_2_is_jalr</a>
+<a name="1433"><span class="lineNum">    1433 </span>            :       (_ittage_io_out_s3_full_pred_2_is_jalr),</a>
+<a name="1434"><span class="lineNum">    1434 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_2_is_call</a>
+<a name="1435"><span class="lineNum">    1435 </span>            :       (_ittage_io_out_s3_full_pred_2_is_call),</a>
+<a name="1436"><span class="lineNum">    1436 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_2_is_ret</a>
+<a name="1437"><span class="lineNum">    1437 </span>            :       (_ittage_io_out_s3_full_pred_2_is_ret),</a>
+<a name="1438"><span class="lineNum">    1438 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing</a>
+<a name="1439"><span class="lineNum">    1439 </span>            :       (_ittage_io_out_s3_full_pred_2_is_br_sharing),</a>
+<a name="1440"><span class="lineNum">    1440 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_2_hit</a>
+<a name="1441"><span class="lineNum">    1441 </span>            :       (_ittage_io_out_s3_full_pred_2_hit),</a>
+<a name="1442"><span class="lineNum">    1442 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_0</a>
+<a name="1443"><span class="lineNum">    1443 </span>            :       (_ittage_io_out_s3_full_pred_3_br_taken_mask_0),</a>
+<a name="1444"><span class="lineNum">    1444 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_1</a>
+<a name="1445"><span class="lineNum">    1445 </span>            :       (_ittage_io_out_s3_full_pred_3_br_taken_mask_1),</a>
+<a name="1446"><span class="lineNum">    1446 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_0</a>
+<a name="1447"><span class="lineNum">    1447 </span>            :       (_ittage_io_out_s3_full_pred_3_slot_valids_0),</a>
+<a name="1448"><span class="lineNum">    1448 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_1</a>
+<a name="1449"><span class="lineNum">    1449 </span>            :       (_ittage_io_out_s3_full_pred_3_slot_valids_1),</a>
+<a name="1450"><span class="lineNum">    1450 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_3_targets_0</a>
+<a name="1451"><span class="lineNum">    1451 </span>            :       (_ittage_io_out_s3_full_pred_3_targets_0),</a>
+<a name="1452"><span class="lineNum">    1452 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_3_targets_1</a>
+<a name="1453"><span class="lineNum">    1453 </span>            :       (_ittage_io_out_s3_full_pred_3_targets_1),</a>
+<a name="1454"><span class="lineNum">    1454 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_3_jalr_target</a>
+<a name="1455"><span class="lineNum">    1455 </span>            :       (_ittage_io_out_s3_full_pred_3_jalr_target),</a>
+<a name="1456"><span class="lineNum">    1456 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_3_offsets_0</a>
+<a name="1457"><span class="lineNum">    1457 </span>            :       (_ittage_io_out_s3_full_pred_3_offsets_0),</a>
+<a name="1458"><span class="lineNum">    1458 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_3_offsets_1</a>
+<a name="1459"><span class="lineNum">    1459 </span>            :       (_ittage_io_out_s3_full_pred_3_offsets_1),</a>
+<a name="1460"><span class="lineNum">    1460 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_3_fallThroughAddr</a>
+<a name="1461"><span class="lineNum">    1461 </span>            :       (_ittage_io_out_s3_full_pred_3_fallThroughAddr),</a>
+<a name="1462"><span class="lineNum">    1462 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_3_fallThroughErr</a>
+<a name="1463"><span class="lineNum">    1463 </span>            :       (_ittage_io_out_s3_full_pred_3_fallThroughErr),</a>
+<a name="1464"><span class="lineNum">    1464 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_3_is_br_sharing</a>
+<a name="1465"><span class="lineNum">    1465 </span>            :       (_ittage_io_out_s3_full_pred_3_is_br_sharing),</a>
+<a name="1466"><span class="lineNum">    1466 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_3_hit</a>
+<a name="1467"><span class="lineNum">    1467 </span>            :       (_ittage_io_out_s3_full_pred_3_hit),</a>
+<a name="1468"><span class="lineNum">    1468 </span>            :     .io_in_bits_resp_in_0_last_stage_ftb_entry_valid</a>
+<a name="1469"><span class="lineNum">    1469 </span>            :       (_ittage_io_out_last_stage_ftb_entry_valid),</a>
+<a name="1470"><span class="lineNum">    1470 </span>            :     .io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_offset</a>
+<a name="1471"><span class="lineNum">    1471 </span>            :       (_ittage_io_out_last_stage_ftb_entry_brSlots_0_offset),</a>
+<a name="1472"><span class="lineNum">    1472 </span>            :     .io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_lower</a>
+<a name="1473"><span class="lineNum">    1473 </span>            :       (_ittage_io_out_last_stage_ftb_entry_brSlots_0_lower),</a>
+<a name="1474"><span class="lineNum">    1474 </span>            :     .io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_tarStat</a>
+<a name="1475"><span class="lineNum">    1475 </span>            :       (_ittage_io_out_last_stage_ftb_entry_brSlots_0_tarStat),</a>
+<a name="1476"><span class="lineNum">    1476 </span>            :     .io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_sharing</a>
+<a name="1477"><span class="lineNum">    1477 </span>            :       (_ittage_io_out_last_stage_ftb_entry_brSlots_0_sharing),</a>
+<a name="1478"><span class="lineNum">    1478 </span>            :     .io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_valid</a>
+<a name="1479"><span class="lineNum">    1479 </span>            :       (_ittage_io_out_last_stage_ftb_entry_brSlots_0_valid),</a>
+<a name="1480"><span class="lineNum">    1480 </span>            :     .io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_offset</a>
+<a name="1481"><span class="lineNum">    1481 </span>            :       (_ittage_io_out_last_stage_ftb_entry_tailSlot_offset),</a>
+<a name="1482"><span class="lineNum">    1482 </span>            :     .io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_lower</a>
+<a name="1483"><span class="lineNum">    1483 </span>            :       (_ittage_io_out_last_stage_ftb_entry_tailSlot_lower),</a>
+<a name="1484"><span class="lineNum">    1484 </span>            :     .io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_tarStat</a>
+<a name="1485"><span class="lineNum">    1485 </span>            :       (_ittage_io_out_last_stage_ftb_entry_tailSlot_tarStat),</a>
+<a name="1486"><span class="lineNum">    1486 </span>            :     .io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_sharing</a>
+<a name="1487"><span class="lineNum">    1487 </span>            :       (_ittage_io_out_last_stage_ftb_entry_tailSlot_sharing),</a>
+<a name="1488"><span class="lineNum">    1488 </span>            :     .io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_valid</a>
+<a name="1489"><span class="lineNum">    1489 </span>            :       (_ittage_io_out_last_stage_ftb_entry_tailSlot_valid),</a>
+<a name="1490"><span class="lineNum">    1490 </span>            :     .io_in_bits_resp_in_0_last_stage_ftb_entry_pftAddr</a>
+<a name="1491"><span class="lineNum">    1491 </span>            :       (_ittage_io_out_last_stage_ftb_entry_pftAddr),</a>
+<a name="1492"><span class="lineNum">    1492 </span>            :     .io_in_bits_resp_in_0_last_stage_ftb_entry_carry</a>
+<a name="1493"><span class="lineNum">    1493 </span>            :       (_ittage_io_out_last_stage_ftb_entry_carry),</a>
+<a name="1494"><span class="lineNum">    1494 </span>            :     .io_in_bits_resp_in_0_last_stage_ftb_entry_isCall</a>
+<a name="1495"><span class="lineNum">    1495 </span>            :       (_ittage_io_out_last_stage_ftb_entry_isCall),</a>
+<a name="1496"><span class="lineNum">    1496 </span>            :     .io_in_bits_resp_in_0_last_stage_ftb_entry_isRet</a>
+<a name="1497"><span class="lineNum">    1497 </span>            :       (_ittage_io_out_last_stage_ftb_entry_isRet),</a>
+<a name="1498"><span class="lineNum">    1498 </span>            :     .io_in_bits_resp_in_0_last_stage_ftb_entry_isJalr</a>
+<a name="1499"><span class="lineNum">    1499 </span>            :       (_ittage_io_out_last_stage_ftb_entry_isJalr),</a>
+<a name="1500"><span class="lineNum">    1500 </span>            :     .io_in_bits_resp_in_0_last_stage_ftb_entry_last_may_be_rvi_call</a>
+<a name="1501"><span class="lineNum">    1501 </span>            :       (_ittage_io_out_last_stage_ftb_entry_last_may_be_rvi_call),</a>
+<a name="1502"><span class="lineNum">    1502 </span>            :     .io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_0</a>
+<a name="1503"><span class="lineNum">    1503 </span>            :       (_ittage_io_out_last_stage_ftb_entry_always_taken_0),</a>
+<a name="1504"><span class="lineNum">    1504 </span>            :     .io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_1</a>
+<a name="1505"><span class="lineNum">    1505 </span>            :       (_ittage_io_out_last_stage_ftb_entry_always_taken_1),</a>
+<a name="1506"><span class="lineNum">    1506 </span>            :     .io_out_s2_pc_0                                                 (io_out_s2_pc_0),</a>
+<a name="1507"><span class="lineNum">    1507 </span>            :     .io_out_s2_pc_1                                                 (io_out_s2_pc_1),</a>
+<a name="1508"><span class="lineNum">    1508 </span>            :     .io_out_s2_pc_2                                                 (io_out_s2_pc_2),</a>
+<a name="1509"><span class="lineNum">    1509 </span>            :     .io_out_s2_pc_3                                                 (io_out_s2_pc_3),</a>
+<a name="1510"><span class="lineNum">    1510 </span>            :     .io_out_s2_full_pred_0_br_taken_mask_0</a>
+<a name="1511"><span class="lineNum">    1511 </span>            :       (io_out_s2_full_pred_0_br_taken_mask_0),</a>
+<a name="1512"><span class="lineNum">    1512 </span>            :     .io_out_s2_full_pred_0_br_taken_mask_1</a>
+<a name="1513"><span class="lineNum">    1513 </span>            :       (io_out_s2_full_pred_0_br_taken_mask_1),</a>
+<a name="1514"><span class="lineNum">    1514 </span>            :     .io_out_s2_full_pred_0_slot_valids_0</a>
+<a name="1515"><span class="lineNum">    1515 </span>            :       (io_out_s2_full_pred_0_slot_valids_0),</a>
+<a name="1516"><span class="lineNum">    1516 </span>            :     .io_out_s2_full_pred_0_slot_valids_1</a>
+<a name="1517"><span class="lineNum">    1517 </span>            :       (io_out_s2_full_pred_0_slot_valids_1),</a>
+<a name="1518"><span class="lineNum">    1518 </span>            :     .io_out_s2_full_pred_0_targets_0</a>
+<a name="1519"><span class="lineNum">    1519 </span>            :       (io_out_s2_full_pred_0_targets_0),</a>
+<a name="1520"><span class="lineNum">    1520 </span>            :     .io_out_s2_full_pred_0_targets_1</a>
+<a name="1521"><span class="lineNum">    1521 </span>            :       (io_out_s2_full_pred_0_targets_1),</a>
+<a name="1522"><span class="lineNum">    1522 </span>            :     .io_out_s2_full_pred_0_offsets_0</a>
+<a name="1523"><span class="lineNum">    1523 </span>            :       (io_out_s2_full_pred_0_offsets_0),</a>
+<a name="1524"><span class="lineNum">    1524 </span>            :     .io_out_s2_full_pred_0_offsets_1</a>
+<a name="1525"><span class="lineNum">    1525 </span>            :       (io_out_s2_full_pred_0_offsets_1),</a>
+<a name="1526"><span class="lineNum">    1526 </span>            :     .io_out_s2_full_pred_0_fallThroughAddr</a>
+<a name="1527"><span class="lineNum">    1527 </span>            :       (io_out_s2_full_pred_0_fallThroughAddr),</a>
+<a name="1528"><span class="lineNum">    1528 </span>            :     .io_out_s2_full_pred_0_is_br_sharing</a>
+<a name="1529"><span class="lineNum">    1529 </span>            :       (io_out_s2_full_pred_0_is_br_sharing),</a>
+<a name="1530"><span class="lineNum">    1530 </span>            :     .io_out_s2_full_pred_0_hit</a>
+<a name="1531"><span class="lineNum">    1531 </span>            :       (io_out_s2_full_pred_0_hit),</a>
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+<a name="1533"><span class="lineNum">    1533 </span>            :       (io_out_s2_full_pred_1_br_taken_mask_0),</a>
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+<a name="1535"><span class="lineNum">    1535 </span>            :       (io_out_s2_full_pred_1_br_taken_mask_1),</a>
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+<a name="1544"><span class="lineNum">    1544 </span>            :     .io_out_s2_full_pred_1_offsets_0</a>
+<a name="1545"><span class="lineNum">    1545 </span>            :       (io_out_s2_full_pred_1_offsets_0),</a>
+<a name="1546"><span class="lineNum">    1546 </span>            :     .io_out_s2_full_pred_1_offsets_1</a>
+<a name="1547"><span class="lineNum">    1547 </span>            :       (io_out_s2_full_pred_1_offsets_1),</a>
+<a name="1548"><span class="lineNum">    1548 </span>            :     .io_out_s2_full_pred_1_fallThroughAddr</a>
+<a name="1549"><span class="lineNum">    1549 </span>            :       (io_out_s2_full_pred_1_fallThroughAddr),</a>
+<a name="1550"><span class="lineNum">    1550 </span>            :     .io_out_s2_full_pred_1_is_br_sharing</a>
+<a name="1551"><span class="lineNum">    1551 </span>            :       (io_out_s2_full_pred_1_is_br_sharing),</a>
+<a name="1552"><span class="lineNum">    1552 </span>            :     .io_out_s2_full_pred_1_hit</a>
+<a name="1553"><span class="lineNum">    1553 </span>            :       (io_out_s2_full_pred_1_hit),</a>
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+<a name="1555"><span class="lineNum">    1555 </span>            :       (io_out_s2_full_pred_2_br_taken_mask_0),</a>
+<a name="1556"><span class="lineNum">    1556 </span>            :     .io_out_s2_full_pred_2_br_taken_mask_1</a>
+<a name="1557"><span class="lineNum">    1557 </span>            :       (io_out_s2_full_pred_2_br_taken_mask_1),</a>
+<a name="1558"><span class="lineNum">    1558 </span>            :     .io_out_s2_full_pred_2_slot_valids_0</a>
+<a name="1559"><span class="lineNum">    1559 </span>            :       (io_out_s2_full_pred_2_slot_valids_0),</a>
+<a name="1560"><span class="lineNum">    1560 </span>            :     .io_out_s2_full_pred_2_slot_valids_1</a>
+<a name="1561"><span class="lineNum">    1561 </span>            :       (io_out_s2_full_pred_2_slot_valids_1),</a>
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+<a name="1564"><span class="lineNum">    1564 </span>            :     .io_out_s2_full_pred_2_targets_1</a>
+<a name="1565"><span class="lineNum">    1565 </span>            :       (io_out_s2_full_pred_2_targets_1),</a>
+<a name="1566"><span class="lineNum">    1566 </span>            :     .io_out_s2_full_pred_2_offsets_0</a>
+<a name="1567"><span class="lineNum">    1567 </span>            :       (io_out_s2_full_pred_2_offsets_0),</a>
+<a name="1568"><span class="lineNum">    1568 </span>            :     .io_out_s2_full_pred_2_offsets_1</a>
+<a name="1569"><span class="lineNum">    1569 </span>            :       (io_out_s2_full_pred_2_offsets_1),</a>
+<a name="1570"><span class="lineNum">    1570 </span>            :     .io_out_s2_full_pred_2_fallThroughAddr</a>
+<a name="1571"><span class="lineNum">    1571 </span>            :       (io_out_s2_full_pred_2_fallThroughAddr),</a>
+<a name="1572"><span class="lineNum">    1572 </span>            :     .io_out_s2_full_pred_2_is_br_sharing</a>
+<a name="1573"><span class="lineNum">    1573 </span>            :       (io_out_s2_full_pred_2_is_br_sharing),</a>
+<a name="1574"><span class="lineNum">    1574 </span>            :     .io_out_s2_full_pred_2_hit</a>
+<a name="1575"><span class="lineNum">    1575 </span>            :       (io_out_s2_full_pred_2_hit),</a>
+<a name="1576"><span class="lineNum">    1576 </span>            :     .io_out_s2_full_pred_3_br_taken_mask_0</a>
+<a name="1577"><span class="lineNum">    1577 </span>            :       (io_out_s2_full_pred_3_br_taken_mask_0),</a>
+<a name="1578"><span class="lineNum">    1578 </span>            :     .io_out_s2_full_pred_3_br_taken_mask_1</a>
+<a name="1579"><span class="lineNum">    1579 </span>            :       (io_out_s2_full_pred_3_br_taken_mask_1),</a>
+<a name="1580"><span class="lineNum">    1580 </span>            :     .io_out_s2_full_pred_3_slot_valids_0</a>
+<a name="1581"><span class="lineNum">    1581 </span>            :       (io_out_s2_full_pred_3_slot_valids_0),</a>
+<a name="1582"><span class="lineNum">    1582 </span>            :     .io_out_s2_full_pred_3_slot_valids_1</a>
+<a name="1583"><span class="lineNum">    1583 </span>            :       (io_out_s2_full_pred_3_slot_valids_1),</a>
+<a name="1584"><span class="lineNum">    1584 </span>            :     .io_out_s2_full_pred_3_targets_0</a>
+<a name="1585"><span class="lineNum">    1585 </span>            :       (io_out_s2_full_pred_3_targets_0),</a>
+<a name="1586"><span class="lineNum">    1586 </span>            :     .io_out_s2_full_pred_3_targets_1</a>
+<a name="1587"><span class="lineNum">    1587 </span>            :       (io_out_s2_full_pred_3_targets_1),</a>
+<a name="1588"><span class="lineNum">    1588 </span>            :     .io_out_s2_full_pred_3_offsets_0</a>
+<a name="1589"><span class="lineNum">    1589 </span>            :       (io_out_s2_full_pred_3_offsets_0),</a>
+<a name="1590"><span class="lineNum">    1590 </span>            :     .io_out_s2_full_pred_3_offsets_1</a>
+<a name="1591"><span class="lineNum">    1591 </span>            :       (io_out_s2_full_pred_3_offsets_1),</a>
+<a name="1592"><span class="lineNum">    1592 </span>            :     .io_out_s2_full_pred_3_fallThroughAddr</a>
+<a name="1593"><span class="lineNum">    1593 </span>            :       (io_out_s2_full_pred_3_fallThroughAddr),</a>
+<a name="1594"><span class="lineNum">    1594 </span>            :     .io_out_s2_full_pred_3_fallThroughErr</a>
+<a name="1595"><span class="lineNum">    1595 </span>            :       (io_out_s2_full_pred_3_fallThroughErr),</a>
+<a name="1596"><span class="lineNum">    1596 </span>            :     .io_out_s2_full_pred_3_is_br_sharing</a>
+<a name="1597"><span class="lineNum">    1597 </span>            :       (io_out_s2_full_pred_3_is_br_sharing),</a>
+<a name="1598"><span class="lineNum">    1598 </span>            :     .io_out_s2_full_pred_3_hit</a>
+<a name="1599"><span class="lineNum">    1599 </span>            :       (io_out_s2_full_pred_3_hit),</a>
+<a name="1600"><span class="lineNum">    1600 </span>            :     .io_out_s3_pc_0                                                 (io_out_s3_pc_0),</a>
+<a name="1601"><span class="lineNum">    1601 </span>            :     .io_out_s3_pc_1                                                 (io_out_s3_pc_1),</a>
+<a name="1602"><span class="lineNum">    1602 </span>            :     .io_out_s3_pc_2                                                 (io_out_s3_pc_2),</a>
+<a name="1603"><span class="lineNum">    1603 </span>            :     .io_out_s3_pc_3                                                 (io_out_s3_pc_3),</a>
+<a name="1604"><span class="lineNum">    1604 </span>            :     .io_out_s3_full_pred_0_br_taken_mask_0</a>
+<a name="1605"><span class="lineNum">    1605 </span>            :       (io_out_s3_full_pred_0_br_taken_mask_0),</a>
+<a name="1606"><span class="lineNum">    1606 </span>            :     .io_out_s3_full_pred_0_br_taken_mask_1</a>
+<a name="1607"><span class="lineNum">    1607 </span>            :       (io_out_s3_full_pred_0_br_taken_mask_1),</a>
+<a name="1608"><span class="lineNum">    1608 </span>            :     .io_out_s3_full_pred_0_slot_valids_0</a>
+<a name="1609"><span class="lineNum">    1609 </span>            :       (io_out_s3_full_pred_0_slot_valids_0),</a>
+<a name="1610"><span class="lineNum">    1610 </span>            :     .io_out_s3_full_pred_0_slot_valids_1</a>
+<a name="1611"><span class="lineNum">    1611 </span>            :       (io_out_s3_full_pred_0_slot_valids_1),</a>
+<a name="1612"><span class="lineNum">    1612 </span>            :     .io_out_s3_full_pred_0_targets_0</a>
+<a name="1613"><span class="lineNum">    1613 </span>            :       (io_out_s3_full_pred_0_targets_0),</a>
+<a name="1614"><span class="lineNum">    1614 </span>            :     .io_out_s3_full_pred_0_targets_1</a>
+<a name="1615"><span class="lineNum">    1615 </span>            :       (io_out_s3_full_pred_0_targets_1),</a>
+<a name="1616"><span class="lineNum">    1616 </span>            :     .io_out_s3_full_pred_0_fallThroughAddr</a>
+<a name="1617"><span class="lineNum">    1617 </span>            :       (io_out_s3_full_pred_0_fallThroughAddr),</a>
+<a name="1618"><span class="lineNum">    1618 </span>            :     .io_out_s3_full_pred_0_fallThroughErr</a>
+<a name="1619"><span class="lineNum">    1619 </span>            :       (io_out_s3_full_pred_0_fallThroughErr),</a>
+<a name="1620"><span class="lineNum">    1620 </span>            :     .io_out_s3_full_pred_0_is_br_sharing</a>
+<a name="1621"><span class="lineNum">    1621 </span>            :       (io_out_s3_full_pred_0_is_br_sharing),</a>
+<a name="1622"><span class="lineNum">    1622 </span>            :     .io_out_s3_full_pred_0_hit</a>
+<a name="1623"><span class="lineNum">    1623 </span>            :       (io_out_s3_full_pred_0_hit),</a>
+<a name="1624"><span class="lineNum">    1624 </span>            :     .io_out_s3_full_pred_1_br_taken_mask_0</a>
+<a name="1625"><span class="lineNum">    1625 </span>            :       (io_out_s3_full_pred_1_br_taken_mask_0),</a>
+<a name="1626"><span class="lineNum">    1626 </span>            :     .io_out_s3_full_pred_1_br_taken_mask_1</a>
+<a name="1627"><span class="lineNum">    1627 </span>            :       (io_out_s3_full_pred_1_br_taken_mask_1),</a>
+<a name="1628"><span class="lineNum">    1628 </span>            :     .io_out_s3_full_pred_1_slot_valids_0</a>
+<a name="1629"><span class="lineNum">    1629 </span>            :       (io_out_s3_full_pred_1_slot_valids_0),</a>
+<a name="1630"><span class="lineNum">    1630 </span>            :     .io_out_s3_full_pred_1_slot_valids_1</a>
+<a name="1631"><span class="lineNum">    1631 </span>            :       (io_out_s3_full_pred_1_slot_valids_1),</a>
+<a name="1632"><span class="lineNum">    1632 </span>            :     .io_out_s3_full_pred_1_targets_0</a>
+<a name="1633"><span class="lineNum">    1633 </span>            :       (io_out_s3_full_pred_1_targets_0),</a>
+<a name="1634"><span class="lineNum">    1634 </span>            :     .io_out_s3_full_pred_1_targets_1</a>
+<a name="1635"><span class="lineNum">    1635 </span>            :       (io_out_s3_full_pred_1_targets_1),</a>
+<a name="1636"><span class="lineNum">    1636 </span>            :     .io_out_s3_full_pred_1_fallThroughAddr</a>
+<a name="1637"><span class="lineNum">    1637 </span>            :       (io_out_s3_full_pred_1_fallThroughAddr),</a>
+<a name="1638"><span class="lineNum">    1638 </span>            :     .io_out_s3_full_pred_1_fallThroughErr</a>
+<a name="1639"><span class="lineNum">    1639 </span>            :       (io_out_s3_full_pred_1_fallThroughErr),</a>
+<a name="1640"><span class="lineNum">    1640 </span>            :     .io_out_s3_full_pred_1_is_br_sharing</a>
+<a name="1641"><span class="lineNum">    1641 </span>            :       (io_out_s3_full_pred_1_is_br_sharing),</a>
+<a name="1642"><span class="lineNum">    1642 </span>            :     .io_out_s3_full_pred_1_hit</a>
+<a name="1643"><span class="lineNum">    1643 </span>            :       (io_out_s3_full_pred_1_hit),</a>
+<a name="1644"><span class="lineNum">    1644 </span>            :     .io_out_s3_full_pred_2_br_taken_mask_0</a>
+<a name="1645"><span class="lineNum">    1645 </span>            :       (io_out_s3_full_pred_2_br_taken_mask_0),</a>
+<a name="1646"><span class="lineNum">    1646 </span>            :     .io_out_s3_full_pred_2_br_taken_mask_1</a>
+<a name="1647"><span class="lineNum">    1647 </span>            :       (io_out_s3_full_pred_2_br_taken_mask_1),</a>
+<a name="1648"><span class="lineNum">    1648 </span>            :     .io_out_s3_full_pred_2_slot_valids_0</a>
+<a name="1649"><span class="lineNum">    1649 </span>            :       (io_out_s3_full_pred_2_slot_valids_0),</a>
+<a name="1650"><span class="lineNum">    1650 </span>            :     .io_out_s3_full_pred_2_slot_valids_1</a>
+<a name="1651"><span class="lineNum">    1651 </span>            :       (io_out_s3_full_pred_2_slot_valids_1),</a>
+<a name="1652"><span class="lineNum">    1652 </span>            :     .io_out_s3_full_pred_2_targets_0</a>
+<a name="1653"><span class="lineNum">    1653 </span>            :       (io_out_s3_full_pred_2_targets_0),</a>
+<a name="1654"><span class="lineNum">    1654 </span>            :     .io_out_s3_full_pred_2_targets_1</a>
+<a name="1655"><span class="lineNum">    1655 </span>            :       (io_out_s3_full_pred_2_targets_1),</a>
+<a name="1656"><span class="lineNum">    1656 </span>            :     .io_out_s3_full_pred_2_fallThroughAddr</a>
+<a name="1657"><span class="lineNum">    1657 </span>            :       (io_out_s3_full_pred_2_fallThroughAddr),</a>
+<a name="1658"><span class="lineNum">    1658 </span>            :     .io_out_s3_full_pred_2_fallThroughErr</a>
+<a name="1659"><span class="lineNum">    1659 </span>            :       (io_out_s3_full_pred_2_fallThroughErr),</a>
+<a name="1660"><span class="lineNum">    1660 </span>            :     .io_out_s3_full_pred_2_is_br_sharing</a>
+<a name="1661"><span class="lineNum">    1661 </span>            :       (io_out_s3_full_pred_2_is_br_sharing),</a>
+<a name="1662"><span class="lineNum">    1662 </span>            :     .io_out_s3_full_pred_2_hit</a>
+<a name="1663"><span class="lineNum">    1663 </span>            :       (io_out_s3_full_pred_2_hit),</a>
+<a name="1664"><span class="lineNum">    1664 </span>            :     .io_out_s3_full_pred_3_br_taken_mask_0</a>
+<a name="1665"><span class="lineNum">    1665 </span>            :       (io_out_s3_full_pred_3_br_taken_mask_0),</a>
+<a name="1666"><span class="lineNum">    1666 </span>            :     .io_out_s3_full_pred_3_br_taken_mask_1</a>
+<a name="1667"><span class="lineNum">    1667 </span>            :       (io_out_s3_full_pred_3_br_taken_mask_1),</a>
+<a name="1668"><span class="lineNum">    1668 </span>            :     .io_out_s3_full_pred_3_slot_valids_0</a>
+<a name="1669"><span class="lineNum">    1669 </span>            :       (io_out_s3_full_pred_3_slot_valids_0),</a>
+<a name="1670"><span class="lineNum">    1670 </span>            :     .io_out_s3_full_pred_3_slot_valids_1</a>
+<a name="1671"><span class="lineNum">    1671 </span>            :       (io_out_s3_full_pred_3_slot_valids_1),</a>
+<a name="1672"><span class="lineNum">    1672 </span>            :     .io_out_s3_full_pred_3_targets_0</a>
+<a name="1673"><span class="lineNum">    1673 </span>            :       (io_out_s3_full_pred_3_targets_0),</a>
+<a name="1674"><span class="lineNum">    1674 </span>            :     .io_out_s3_full_pred_3_targets_1</a>
+<a name="1675"><span class="lineNum">    1675 </span>            :       (io_out_s3_full_pred_3_targets_1),</a>
+<a name="1676"><span class="lineNum">    1676 </span>            :     .io_out_s3_full_pred_3_offsets_0</a>
+<a name="1677"><span class="lineNum">    1677 </span>            :       (io_out_s3_full_pred_3_offsets_0),</a>
+<a name="1678"><span class="lineNum">    1678 </span>            :     .io_out_s3_full_pred_3_offsets_1</a>
+<a name="1679"><span class="lineNum">    1679 </span>            :       (io_out_s3_full_pred_3_offsets_1),</a>
+<a name="1680"><span class="lineNum">    1680 </span>            :     .io_out_s3_full_pred_3_fallThroughAddr</a>
+<a name="1681"><span class="lineNum">    1681 </span>            :       (io_out_s3_full_pred_3_fallThroughAddr),</a>
+<a name="1682"><span class="lineNum">    1682 </span>            :     .io_out_s3_full_pred_3_fallThroughErr</a>
+<a name="1683"><span class="lineNum">    1683 </span>            :       (io_out_s3_full_pred_3_fallThroughErr),</a>
+<a name="1684"><span class="lineNum">    1684 </span>            :     .io_out_s3_full_pred_3_is_br_sharing</a>
+<a name="1685"><span class="lineNum">    1685 </span>            :       (io_out_s3_full_pred_3_is_br_sharing),</a>
+<a name="1686"><span class="lineNum">    1686 </span>            :     .io_out_s3_full_pred_3_hit</a>
+<a name="1687"><span class="lineNum">    1687 </span>            :       (io_out_s3_full_pred_3_hit),</a>
+<a name="1688"><span class="lineNum">    1688 </span>            :     .io_out_last_stage_meta</a>
+<a name="1689"><span class="lineNum">    1689 </span>            :       (_ras_io_out_last_stage_meta),</a>
+<a name="1690"><span class="lineNum">    1690 </span>            :     .io_out_last_stage_spec_info_ssp</a>
+<a name="1691"><span class="lineNum">    1691 </span>            :       (io_out_last_stage_spec_info_ssp),</a>
+<a name="1692"><span class="lineNum">    1692 </span>            :     .io_out_last_stage_spec_info_sctr</a>
+<a name="1693"><span class="lineNum">    1693 </span>            :       (io_out_last_stage_spec_info_sctr),</a>
+<a name="1694"><span class="lineNum">    1694 </span>            :     .io_out_last_stage_spec_info_TOSW_flag</a>
+<a name="1695"><span class="lineNum">    1695 </span>            :       (io_out_last_stage_spec_info_TOSW_flag),</a>
+<a name="1696"><span class="lineNum">    1696 </span>            :     .io_out_last_stage_spec_info_TOSW_value</a>
+<a name="1697"><span class="lineNum">    1697 </span>            :       (io_out_last_stage_spec_info_TOSW_value),</a>
+<a name="1698"><span class="lineNum">    1698 </span>            :     .io_out_last_stage_spec_info_TOSR_flag</a>
+<a name="1699"><span class="lineNum">    1699 </span>            :       (io_out_last_stage_spec_info_TOSR_flag),</a>
+<a name="1700"><span class="lineNum">    1700 </span>            :     .io_out_last_stage_spec_info_TOSR_value</a>
+<a name="1701"><span class="lineNum">    1701 </span>            :       (io_out_last_stage_spec_info_TOSR_value),</a>
+<a name="1702"><span class="lineNum">    1702 </span>            :     .io_out_last_stage_spec_info_NOS_flag</a>
+<a name="1703"><span class="lineNum">    1703 </span>            :       (io_out_last_stage_spec_info_NOS_flag),</a>
+<a name="1704"><span class="lineNum">    1704 </span>            :     .io_out_last_stage_spec_info_NOS_value</a>
+<a name="1705"><span class="lineNum">    1705 </span>            :       (io_out_last_stage_spec_info_NOS_value),</a>
+<a name="1706"><span class="lineNum">    1706 </span>            :     .io_out_last_stage_spec_info_topAddr</a>
+<a name="1707"><span class="lineNum">    1707 </span>            :       (io_out_last_stage_spec_info_topAddr),</a>
+<a name="1708"><span class="lineNum">    1708 </span>            :     .io_out_last_stage_ftb_entry_valid</a>
+<a name="1709"><span class="lineNum">    1709 </span>            :       (io_out_last_stage_ftb_entry_valid),</a>
+<a name="1710"><span class="lineNum">    1710 </span>            :     .io_out_last_stage_ftb_entry_brSlots_0_offset</a>
+<a name="1711"><span class="lineNum">    1711 </span>            :       (io_out_last_stage_ftb_entry_brSlots_0_offset),</a>
+<a name="1712"><span class="lineNum">    1712 </span>            :     .io_out_last_stage_ftb_entry_brSlots_0_lower</a>
+<a name="1713"><span class="lineNum">    1713 </span>            :       (io_out_last_stage_ftb_entry_brSlots_0_lower),</a>
+<a name="1714"><span class="lineNum">    1714 </span>            :     .io_out_last_stage_ftb_entry_brSlots_0_tarStat</a>
+<a name="1715"><span class="lineNum">    1715 </span>            :       (io_out_last_stage_ftb_entry_brSlots_0_tarStat),</a>
+<a name="1716"><span class="lineNum">    1716 </span>            :     .io_out_last_stage_ftb_entry_brSlots_0_sharing</a>
+<a name="1717"><span class="lineNum">    1717 </span>            :       (io_out_last_stage_ftb_entry_brSlots_0_sharing),</a>
+<a name="1718"><span class="lineNum">    1718 </span>            :     .io_out_last_stage_ftb_entry_brSlots_0_valid</a>
+<a name="1719"><span class="lineNum">    1719 </span>            :       (io_out_last_stage_ftb_entry_brSlots_0_valid),</a>
+<a name="1720"><span class="lineNum">    1720 </span>            :     .io_out_last_stage_ftb_entry_tailSlot_offset</a>
+<a name="1721"><span class="lineNum">    1721 </span>            :       (io_out_last_stage_ftb_entry_tailSlot_offset),</a>
+<a name="1722"><span class="lineNum">    1722 </span>            :     .io_out_last_stage_ftb_entry_tailSlot_lower</a>
+<a name="1723"><span class="lineNum">    1723 </span>            :       (io_out_last_stage_ftb_entry_tailSlot_lower),</a>
+<a name="1724"><span class="lineNum">    1724 </span>            :     .io_out_last_stage_ftb_entry_tailSlot_tarStat</a>
+<a name="1725"><span class="lineNum">    1725 </span>            :       (io_out_last_stage_ftb_entry_tailSlot_tarStat),</a>
+<a name="1726"><span class="lineNum">    1726 </span>            :     .io_out_last_stage_ftb_entry_tailSlot_sharing</a>
+<a name="1727"><span class="lineNum">    1727 </span>            :       (io_out_last_stage_ftb_entry_tailSlot_sharing),</a>
+<a name="1728"><span class="lineNum">    1728 </span>            :     .io_out_last_stage_ftb_entry_tailSlot_valid</a>
+<a name="1729"><span class="lineNum">    1729 </span>            :       (io_out_last_stage_ftb_entry_tailSlot_valid),</a>
+<a name="1730"><span class="lineNum">    1730 </span>            :     .io_out_last_stage_ftb_entry_pftAddr</a>
+<a name="1731"><span class="lineNum">    1731 </span>            :       (io_out_last_stage_ftb_entry_pftAddr),</a>
+<a name="1732"><span class="lineNum">    1732 </span>            :     .io_out_last_stage_ftb_entry_carry</a>
+<a name="1733"><span class="lineNum">    1733 </span>            :       (io_out_last_stage_ftb_entry_carry),</a>
+<a name="1734"><span class="lineNum">    1734 </span>            :     .io_out_last_stage_ftb_entry_isCall</a>
+<a name="1735"><span class="lineNum">    1735 </span>            :       (io_out_last_stage_ftb_entry_isCall),</a>
+<a name="1736"><span class="lineNum">    1736 </span>            :     .io_out_last_stage_ftb_entry_isRet</a>
+<a name="1737"><span class="lineNum">    1737 </span>            :       (io_out_last_stage_ftb_entry_isRet),</a>
+<a name="1738"><span class="lineNum">    1738 </span>            :     .io_out_last_stage_ftb_entry_isJalr</a>
+<a name="1739"><span class="lineNum">    1739 </span>            :       (io_out_last_stage_ftb_entry_isJalr),</a>
+<a name="1740"><span class="lineNum">    1740 </span>            :     .io_out_last_stage_ftb_entry_last_may_be_rvi_call</a>
+<a name="1741"><span class="lineNum">    1741 </span>            :       (io_out_last_stage_ftb_entry_last_may_be_rvi_call),</a>
+<a name="1742"><span class="lineNum">    1742 </span>            :     .io_out_last_stage_ftb_entry_always_taken_0</a>
+<a name="1743"><span class="lineNum">    1743 </span>            :       (io_out_last_stage_ftb_entry_always_taken_0),</a>
+<a name="1744"><span class="lineNum">    1744 </span>            :     .io_out_last_stage_ftb_entry_always_taken_1</a>
+<a name="1745"><span class="lineNum">    1745 </span>            :       (io_out_last_stage_ftb_entry_always_taken_1),</a>
+<a name="1746"><span class="lineNum">    1746 </span>            :     .io_ctrl_ras_enable</a>
+<a name="1747"><span class="lineNum">    1747 </span>            :       (_ras_io_ctrl_delay_io_out_ras_enable),</a>
+<a name="1748"><span class="lineNum">    1748 </span>            :     .io_s0_fire_0                                                   (io_s0_fire_0),</a>
+<a name="1749"><span class="lineNum">    1749 </span>            :     .io_s0_fire_1                                                   (io_s0_fire_1),</a>
+<a name="1750"><span class="lineNum">    1750 </span>            :     .io_s0_fire_2                                                   (io_s0_fire_2),</a>
+<a name="1751"><span class="lineNum">    1751 </span>            :     .io_s0_fire_3                                                   (io_s0_fire_3),</a>
+<a name="1752"><span class="lineNum">    1752 </span>            :     .io_s1_fire_0                                                   (io_s1_fire_0),</a>
+<a name="1753"><span class="lineNum">    1753 </span>            :     .io_s1_fire_1                                                   (io_s1_fire_1),</a>
+<a name="1754"><span class="lineNum">    1754 </span>            :     .io_s1_fire_2                                                   (io_s1_fire_2),</a>
+<a name="1755"><span class="lineNum">    1755 </span>            :     .io_s1_fire_3                                                   (io_s1_fire_3),</a>
+<a name="1756"><span class="lineNum">    1756 </span>            :     .io_s2_fire_0                                                   (io_s2_fire_0),</a>
+<a name="1757"><span class="lineNum">    1757 </span>            :     .io_s2_fire_1                                                   (io_s2_fire_1),</a>
+<a name="1758"><span class="lineNum">    1758 </span>            :     .io_s2_fire_2                                                   (io_s2_fire_2),</a>
+<a name="1759"><span class="lineNum">    1759 </span>            :     .io_s2_fire_3                                                   (io_s2_fire_3),</a>
+<a name="1760"><span class="lineNum">    1760 </span>            :     .io_s3_fire_2                                                   (io_s3_fire_2),</a>
+<a name="1761"><span class="lineNum">    1761 </span>            :     .io_s3_redirect_2                                               (io_s3_redirect_2),</a>
+<a name="1762"><span class="lineNum">    1762 </span>            :     .io_update_valid                                                (io_update_valid),</a>
+<a name="1763"><span class="lineNum">    1763 </span>            :     .io_update_bits_ftb_entry_tailSlot_offset</a>
+<a name="1764"><span class="lineNum">    1764 </span>            :       (io_update_bits_ftb_entry_tailSlot_offset),</a>
+<a name="1765"><span class="lineNum">    1765 </span>            :     .io_update_bits_ftb_entry_tailSlot_valid</a>
+<a name="1766"><span class="lineNum">    1766 </span>            :       (io_update_bits_ftb_entry_tailSlot_valid),</a>
+<a name="1767"><span class="lineNum">    1767 </span>            :     .io_update_bits_ftb_entry_isCall</a>
+<a name="1768"><span class="lineNum">    1768 </span>            :       (io_update_bits_ftb_entry_isCall),</a>
+<a name="1769"><span class="lineNum">    1769 </span>            :     .io_update_bits_ftb_entry_isRet</a>
+<a name="1770"><span class="lineNum">    1770 </span>            :       (io_update_bits_ftb_entry_isRet),</a>
+<a name="1771"><span class="lineNum">    1771 </span>            :     .io_update_bits_cfi_idx_valid</a>
+<a name="1772"><span class="lineNum">    1772 </span>            :       (io_update_bits_cfi_idx_valid),</a>
+<a name="1773"><span class="lineNum">    1773 </span>            :     .io_update_bits_cfi_idx_bits</a>
+<a name="1774"><span class="lineNum">    1774 </span>            :       (io_update_bits_cfi_idx_bits),</a>
+<a name="1775"><span class="lineNum">    1775 </span>            :     .io_update_bits_jmp_taken</a>
+<a name="1776"><span class="lineNum">    1776 </span>            :       (io_update_bits_jmp_taken),</a>
+<a name="1777"><span class="lineNum">    1777 </span>            :     .io_update_bits_meta                                            (io_update_bits_meta),</a>
+<a name="1778"><span class="lineNum">    1778 </span>            :     .io_redirect_valid                                              (io_redirect_valid),</a>
+<a name="1779"><span class="lineNum">    1779 </span>            :     .io_redirect_bits_level</a>
+<a name="1780"><span class="lineNum">    1780 </span>            :       (io_redirect_bits_level),</a>
+<a name="1781"><span class="lineNum">    1781 </span>            :     .io_redirect_bits_cfiUpdate_pc</a>
+<a name="1782"><span class="lineNum">    1782 </span>            :       (io_redirect_bits_cfiUpdate_pc),</a>
+<a name="1783"><span class="lineNum">    1783 </span>            :     .io_redirect_bits_cfiUpdate_pd_isRVC</a>
+<a name="1784"><span class="lineNum">    1784 </span>            :       (io_redirect_bits_cfiUpdate_pd_isRVC),</a>
+<a name="1785"><span class="lineNum">    1785 </span>            :     .io_redirect_bits_cfiUpdate_pd_isCall</a>
+<a name="1786"><span class="lineNum">    1786 </span>            :       (io_redirect_bits_cfiUpdate_pd_isCall),</a>
+<a name="1787"><span class="lineNum">    1787 </span>            :     .io_redirect_bits_cfiUpdate_pd_isRet</a>
+<a name="1788"><span class="lineNum">    1788 </span>            :       (io_redirect_bits_cfiUpdate_pd_isRet),</a>
+<a name="1789"><span class="lineNum">    1789 </span>            :     .io_redirect_bits_cfiUpdate_ssp</a>
+<a name="1790"><span class="lineNum">    1790 </span>            :       (io_redirect_bits_cfiUpdate_ssp),</a>
+<a name="1791"><span class="lineNum">    1791 </span>            :     .io_redirect_bits_cfiUpdate_sctr</a>
+<a name="1792"><span class="lineNum">    1792 </span>            :       (io_redirect_bits_cfiUpdate_sctr),</a>
+<a name="1793"><span class="lineNum">    1793 </span>            :     .io_redirect_bits_cfiUpdate_TOSW_flag</a>
+<a name="1794"><span class="lineNum">    1794 </span>            :       (io_redirect_bits_cfiUpdate_TOSW_flag),</a>
+<a name="1795"><span class="lineNum">    1795 </span>            :     .io_redirect_bits_cfiUpdate_TOSW_value</a>
+<a name="1796"><span class="lineNum">    1796 </span>            :       (io_redirect_bits_cfiUpdate_TOSW_value),</a>
+<a name="1797"><span class="lineNum">    1797 </span>            :     .io_redirect_bits_cfiUpdate_TOSR_flag</a>
+<a name="1798"><span class="lineNum">    1798 </span>            :       (io_redirect_bits_cfiUpdate_TOSR_flag),</a>
+<a name="1799"><span class="lineNum">    1799 </span>            :     .io_redirect_bits_cfiUpdate_TOSR_value</a>
+<a name="1800"><span class="lineNum">    1800 </span>            :       (io_redirect_bits_cfiUpdate_TOSR_value),</a>
+<a name="1801"><span class="lineNum">    1801 </span>            :     .io_redirect_bits_cfiUpdate_NOS_flag</a>
+<a name="1802"><span class="lineNum">    1802 </span>            :       (io_redirect_bits_cfiUpdate_NOS_flag),</a>
+<a name="1803"><span class="lineNum">    1803 </span>            :     .io_redirect_bits_cfiUpdate_NOS_value</a>
+<a name="1804"><span class="lineNum">    1804 </span>            :       (io_redirect_bits_cfiUpdate_NOS_value)</a>
+<a name="1805"><span class="lineNum">    1805 </span>            :   );</a>
+<a name="1806"><span class="lineNum">    1806 </span>            :   ITTage ittage (</a>
+<a name="1807"><span class="lineNum">    1807 </span>            :     .clock                                                          (clock),</a>
+<a name="1808"><span class="lineNum">    1808 </span>            :     .reset                                                          (reset),</a>
+<a name="1809"><span class="lineNum">    1809 </span>            :     .io_in_bits_s0_pc_3                                             (io_in_bits_s0_pc_3),</a>
+<a name="1810"><span class="lineNum">    1810 </span>            :     .io_in_bits_folded_hist_3_hist_14_folded_hist</a>
+<a name="1811"><span class="lineNum">    1811 </span>            :       (io_in_bits_folded_hist_3_hist_14_folded_hist),</a>
+<a name="1812"><span class="lineNum">    1812 </span>            :     .io_in_bits_folded_hist_3_hist_13_folded_hist</a>
+<a name="1813"><span class="lineNum">    1813 </span>            :       (io_in_bits_folded_hist_3_hist_13_folded_hist),</a>
+<a name="1814"><span class="lineNum">    1814 </span>            :     .io_in_bits_folded_hist_3_hist_12_folded_hist</a>
+<a name="1815"><span class="lineNum">    1815 </span>            :       (io_in_bits_folded_hist_3_hist_12_folded_hist),</a>
+<a name="1816"><span class="lineNum">    1816 </span>            :     .io_in_bits_folded_hist_3_hist_10_folded_hist</a>
+<a name="1817"><span class="lineNum">    1817 </span>            :       (io_in_bits_folded_hist_3_hist_10_folded_hist),</a>
+<a name="1818"><span class="lineNum">    1818 </span>            :     .io_in_bits_folded_hist_3_hist_6_folded_hist</a>
+<a name="1819"><span class="lineNum">    1819 </span>            :       (io_in_bits_folded_hist_3_hist_6_folded_hist),</a>
+<a name="1820"><span class="lineNum">    1820 </span>            :     .io_in_bits_folded_hist_3_hist_4_folded_hist</a>
+<a name="1821"><span class="lineNum">    1821 </span>            :       (io_in_bits_folded_hist_3_hist_4_folded_hist),</a>
+<a name="1822"><span class="lineNum">    1822 </span>            :     .io_in_bits_folded_hist_3_hist_3_folded_hist</a>
+<a name="1823"><span class="lineNum">    1823 </span>            :       (io_in_bits_folded_hist_3_hist_3_folded_hist),</a>
+<a name="1824"><span class="lineNum">    1824 </span>            :     .io_in_bits_folded_hist_3_hist_2_folded_hist</a>
+<a name="1825"><span class="lineNum">    1825 </span>            :       (io_in_bits_folded_hist_3_hist_2_folded_hist),</a>
+<a name="1826"><span class="lineNum">    1826 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_0</a>
+<a name="1827"><span class="lineNum">    1827 </span>            :       (_ftb_io_out_s2_full_pred_0_br_taken_mask_0),</a>
+<a name="1828"><span class="lineNum">    1828 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_1</a>
+<a name="1829"><span class="lineNum">    1829 </span>            :       (_ftb_io_out_s2_full_pred_0_br_taken_mask_1),</a>
+<a name="1830"><span class="lineNum">    1830 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_0</a>
+<a name="1831"><span class="lineNum">    1831 </span>            :       (_ftb_io_out_s2_full_pred_0_slot_valids_0),</a>
+<a name="1832"><span class="lineNum">    1832 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_1</a>
+<a name="1833"><span class="lineNum">    1833 </span>            :       (_ftb_io_out_s2_full_pred_0_slot_valids_1),</a>
+<a name="1834"><span class="lineNum">    1834 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_0_targets_0</a>
+<a name="1835"><span class="lineNum">    1835 </span>            :       (_ftb_io_out_s2_full_pred_0_targets_0),</a>
+<a name="1836"><span class="lineNum">    1836 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_0_targets_1</a>
+<a name="1837"><span class="lineNum">    1837 </span>            :       (_ftb_io_out_s2_full_pred_0_targets_1),</a>
+<a name="1838"><span class="lineNum">    1838 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_0_jalr_target</a>
+<a name="1839"><span class="lineNum">    1839 </span>            :       (_ftb_io_out_s2_full_pred_0_jalr_target),</a>
+<a name="1840"><span class="lineNum">    1840 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_0_offsets_0</a>
+<a name="1841"><span class="lineNum">    1841 </span>            :       (_ftb_io_out_s2_full_pred_0_offsets_0),</a>
+<a name="1842"><span class="lineNum">    1842 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_0_offsets_1</a>
+<a name="1843"><span class="lineNum">    1843 </span>            :       (_ftb_io_out_s2_full_pred_0_offsets_1),</a>
+<a name="1844"><span class="lineNum">    1844 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_0_fallThroughAddr</a>
+<a name="1845"><span class="lineNum">    1845 </span>            :       (_ftb_io_out_s2_full_pred_0_fallThroughAddr),</a>
+<a name="1846"><span class="lineNum">    1846 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_0_is_br_sharing</a>
+<a name="1847"><span class="lineNum">    1847 </span>            :       (_ftb_io_out_s2_full_pred_0_is_br_sharing),</a>
+<a name="1848"><span class="lineNum">    1848 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_0_hit</a>
+<a name="1849"><span class="lineNum">    1849 </span>            :       (_ftb_io_out_s2_full_pred_0_hit),</a>
+<a name="1850"><span class="lineNum">    1850 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_0</a>
+<a name="1851"><span class="lineNum">    1851 </span>            :       (_ftb_io_out_s2_full_pred_1_br_taken_mask_0),</a>
+<a name="1852"><span class="lineNum">    1852 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_1</a>
+<a name="1853"><span class="lineNum">    1853 </span>            :       (_ftb_io_out_s2_full_pred_1_br_taken_mask_1),</a>
+<a name="1854"><span class="lineNum">    1854 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_0</a>
+<a name="1855"><span class="lineNum">    1855 </span>            :       (_ftb_io_out_s2_full_pred_1_slot_valids_0),</a>
+<a name="1856"><span class="lineNum">    1856 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_1</a>
+<a name="1857"><span class="lineNum">    1857 </span>            :       (_ftb_io_out_s2_full_pred_1_slot_valids_1),</a>
+<a name="1858"><span class="lineNum">    1858 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_1_targets_0</a>
+<a name="1859"><span class="lineNum">    1859 </span>            :       (_ftb_io_out_s2_full_pred_1_targets_0),</a>
+<a name="1860"><span class="lineNum">    1860 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_1_targets_1</a>
+<a name="1861"><span class="lineNum">    1861 </span>            :       (_ftb_io_out_s2_full_pred_1_targets_1),</a>
+<a name="1862"><span class="lineNum">    1862 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_1_jalr_target</a>
+<a name="1863"><span class="lineNum">    1863 </span>            :       (_ftb_io_out_s2_full_pred_1_jalr_target),</a>
+<a name="1864"><span class="lineNum">    1864 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_1_offsets_0</a>
+<a name="1865"><span class="lineNum">    1865 </span>            :       (_ftb_io_out_s2_full_pred_1_offsets_0),</a>
+<a name="1866"><span class="lineNum">    1866 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_1_offsets_1</a>
+<a name="1867"><span class="lineNum">    1867 </span>            :       (_ftb_io_out_s2_full_pred_1_offsets_1),</a>
+<a name="1868"><span class="lineNum">    1868 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_1_fallThroughAddr</a>
+<a name="1869"><span class="lineNum">    1869 </span>            :       (_ftb_io_out_s2_full_pred_1_fallThroughAddr),</a>
+<a name="1870"><span class="lineNum">    1870 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_1_is_br_sharing</a>
+<a name="1871"><span class="lineNum">    1871 </span>            :       (_ftb_io_out_s2_full_pred_1_is_br_sharing),</a>
+<a name="1872"><span class="lineNum">    1872 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_1_hit</a>
+<a name="1873"><span class="lineNum">    1873 </span>            :       (_ftb_io_out_s2_full_pred_1_hit),</a>
+<a name="1874"><span class="lineNum">    1874 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_0</a>
+<a name="1875"><span class="lineNum">    1875 </span>            :       (_ftb_io_out_s2_full_pred_2_br_taken_mask_0),</a>
+<a name="1876"><span class="lineNum">    1876 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_1</a>
+<a name="1877"><span class="lineNum">    1877 </span>            :       (_ftb_io_out_s2_full_pred_2_br_taken_mask_1),</a>
+<a name="1878"><span class="lineNum">    1878 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_0</a>
+<a name="1879"><span class="lineNum">    1879 </span>            :       (_ftb_io_out_s2_full_pred_2_slot_valids_0),</a>
+<a name="1880"><span class="lineNum">    1880 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_1</a>
+<a name="1881"><span class="lineNum">    1881 </span>            :       (_ftb_io_out_s2_full_pred_2_slot_valids_1),</a>
+<a name="1882"><span class="lineNum">    1882 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_2_targets_0</a>
+<a name="1883"><span class="lineNum">    1883 </span>            :       (_ftb_io_out_s2_full_pred_2_targets_0),</a>
+<a name="1884"><span class="lineNum">    1884 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_2_targets_1</a>
+<a name="1885"><span class="lineNum">    1885 </span>            :       (_ftb_io_out_s2_full_pred_2_targets_1),</a>
+<a name="1886"><span class="lineNum">    1886 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_2_jalr_target</a>
+<a name="1887"><span class="lineNum">    1887 </span>            :       (_ftb_io_out_s2_full_pred_2_jalr_target),</a>
+<a name="1888"><span class="lineNum">    1888 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_2_offsets_0</a>
+<a name="1889"><span class="lineNum">    1889 </span>            :       (_ftb_io_out_s2_full_pred_2_offsets_0),</a>
+<a name="1890"><span class="lineNum">    1890 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_2_offsets_1</a>
+<a name="1891"><span class="lineNum">    1891 </span>            :       (_ftb_io_out_s2_full_pred_2_offsets_1),</a>
+<a name="1892"><span class="lineNum">    1892 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_2_fallThroughAddr</a>
+<a name="1893"><span class="lineNum">    1893 </span>            :       (_ftb_io_out_s2_full_pred_2_fallThroughAddr),</a>
+<a name="1894"><span class="lineNum">    1894 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_2_is_jalr</a>
+<a name="1895"><span class="lineNum">    1895 </span>            :       (_ftb_io_out_s2_full_pred_2_is_jalr),</a>
+<a name="1896"><span class="lineNum">    1896 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_2_is_call</a>
+<a name="1897"><span class="lineNum">    1897 </span>            :       (_ftb_io_out_s2_full_pred_2_is_call),</a>
+<a name="1898"><span class="lineNum">    1898 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_2_is_ret</a>
+<a name="1899"><span class="lineNum">    1899 </span>            :       (_ftb_io_out_s2_full_pred_2_is_ret),</a>
+<a name="1900"><span class="lineNum">    1900 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_2_last_may_be_rvi_call</a>
+<a name="1901"><span class="lineNum">    1901 </span>            :       (_ftb_io_out_s2_full_pred_2_last_may_be_rvi_call),</a>
+<a name="1902"><span class="lineNum">    1902 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing</a>
+<a name="1903"><span class="lineNum">    1903 </span>            :       (_ftb_io_out_s2_full_pred_2_is_br_sharing),</a>
+<a name="1904"><span class="lineNum">    1904 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_2_hit</a>
+<a name="1905"><span class="lineNum">    1905 </span>            :       (_ftb_io_out_s2_full_pred_2_hit),</a>
+<a name="1906"><span class="lineNum">    1906 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_0</a>
+<a name="1907"><span class="lineNum">    1907 </span>            :       (_ftb_io_out_s2_full_pred_3_br_taken_mask_0),</a>
+<a name="1908"><span class="lineNum">    1908 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_1</a>
+<a name="1909"><span class="lineNum">    1909 </span>            :       (_ftb_io_out_s2_full_pred_3_br_taken_mask_1),</a>
+<a name="1910"><span class="lineNum">    1910 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_0</a>
+<a name="1911"><span class="lineNum">    1911 </span>            :       (_ftb_io_out_s2_full_pred_3_slot_valids_0),</a>
+<a name="1912"><span class="lineNum">    1912 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_1</a>
+<a name="1913"><span class="lineNum">    1913 </span>            :       (_ftb_io_out_s2_full_pred_3_slot_valids_1),</a>
+<a name="1914"><span class="lineNum">    1914 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_3_targets_0</a>
+<a name="1915"><span class="lineNum">    1915 </span>            :       (_ftb_io_out_s2_full_pred_3_targets_0),</a>
+<a name="1916"><span class="lineNum">    1916 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_3_targets_1</a>
+<a name="1917"><span class="lineNum">    1917 </span>            :       (_ftb_io_out_s2_full_pred_3_targets_1),</a>
+<a name="1918"><span class="lineNum">    1918 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_3_jalr_target</a>
+<a name="1919"><span class="lineNum">    1919 </span>            :       (_ftb_io_out_s2_full_pred_3_jalr_target),</a>
+<a name="1920"><span class="lineNum">    1920 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_3_offsets_0</a>
+<a name="1921"><span class="lineNum">    1921 </span>            :       (_ftb_io_out_s2_full_pred_3_offsets_0),</a>
+<a name="1922"><span class="lineNum">    1922 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_3_offsets_1</a>
+<a name="1923"><span class="lineNum">    1923 </span>            :       (_ftb_io_out_s2_full_pred_3_offsets_1),</a>
+<a name="1924"><span class="lineNum">    1924 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_3_fallThroughAddr</a>
+<a name="1925"><span class="lineNum">    1925 </span>            :       (_ftb_io_out_s2_full_pred_3_fallThroughAddr),</a>
+<a name="1926"><span class="lineNum">    1926 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_3_fallThroughErr</a>
+<a name="1927"><span class="lineNum">    1927 </span>            :       (_ftb_io_out_s2_full_pred_3_fallThroughErr),</a>
+<a name="1928"><span class="lineNum">    1928 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_3_is_br_sharing</a>
+<a name="1929"><span class="lineNum">    1929 </span>            :       (_ftb_io_out_s2_full_pred_3_is_br_sharing),</a>
+<a name="1930"><span class="lineNum">    1930 </span>            :     .io_in_bits_resp_in_0_s2_full_pred_3_hit</a>
+<a name="1931"><span class="lineNum">    1931 </span>            :       (_ftb_io_out_s2_full_pred_3_hit),</a>
+<a name="1932"><span class="lineNum">    1932 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_0</a>
+<a name="1933"><span class="lineNum">    1933 </span>            :       (_ftb_io_out_s3_full_pred_0_br_taken_mask_0),</a>
+<a name="1934"><span class="lineNum">    1934 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_1</a>
+<a name="1935"><span class="lineNum">    1935 </span>            :       (_ftb_io_out_s3_full_pred_0_br_taken_mask_1),</a>
+<a name="1936"><span class="lineNum">    1936 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_0</a>
+<a name="1937"><span class="lineNum">    1937 </span>            :       (_ftb_io_out_s3_full_pred_0_slot_valids_0),</a>
+<a name="1938"><span class="lineNum">    1938 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_1</a>
+<a name="1939"><span class="lineNum">    1939 </span>            :       (_ftb_io_out_s3_full_pred_0_slot_valids_1),</a>
+<a name="1940"><span class="lineNum">    1940 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_0_targets_0</a>
+<a name="1941"><span class="lineNum">    1941 </span>            :       (_ftb_io_out_s3_full_pred_0_targets_0),</a>
+<a name="1942"><span class="lineNum">    1942 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_0_targets_1</a>
+<a name="1943"><span class="lineNum">    1943 </span>            :       (_ftb_io_out_s3_full_pred_0_targets_1),</a>
+<a name="1944"><span class="lineNum">    1944 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_0_jalr_target</a>
+<a name="1945"><span class="lineNum">    1945 </span>            :       (_ftb_io_out_s3_full_pred_0_jalr_target),</a>
+<a name="1946"><span class="lineNum">    1946 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_0_fallThroughAddr</a>
+<a name="1947"><span class="lineNum">    1947 </span>            :       (_ftb_io_out_s3_full_pred_0_fallThroughAddr),</a>
+<a name="1948"><span class="lineNum">    1948 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_0_fallThroughErr</a>
+<a name="1949"><span class="lineNum">    1949 </span>            :       (_ftb_io_out_s3_full_pred_0_fallThroughErr),</a>
+<a name="1950"><span class="lineNum">    1950 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_0_is_br_sharing</a>
+<a name="1951"><span class="lineNum">    1951 </span>            :       (_ftb_io_out_s3_full_pred_0_is_br_sharing),</a>
+<a name="1952"><span class="lineNum">    1952 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_0_hit</a>
+<a name="1953"><span class="lineNum">    1953 </span>            :       (_ftb_io_out_s3_full_pred_0_hit),</a>
+<a name="1954"><span class="lineNum">    1954 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_0</a>
+<a name="1955"><span class="lineNum">    1955 </span>            :       (_ftb_io_out_s3_full_pred_1_br_taken_mask_0),</a>
+<a name="1956"><span class="lineNum">    1956 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_1</a>
+<a name="1957"><span class="lineNum">    1957 </span>            :       (_ftb_io_out_s3_full_pred_1_br_taken_mask_1),</a>
+<a name="1958"><span class="lineNum">    1958 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_0</a>
+<a name="1959"><span class="lineNum">    1959 </span>            :       (_ftb_io_out_s3_full_pred_1_slot_valids_0),</a>
+<a name="1960"><span class="lineNum">    1960 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_1</a>
+<a name="1961"><span class="lineNum">    1961 </span>            :       (_ftb_io_out_s3_full_pred_1_slot_valids_1),</a>
+<a name="1962"><span class="lineNum">    1962 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_1_targets_0</a>
+<a name="1963"><span class="lineNum">    1963 </span>            :       (_ftb_io_out_s3_full_pred_1_targets_0),</a>
+<a name="1964"><span class="lineNum">    1964 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_1_targets_1</a>
+<a name="1965"><span class="lineNum">    1965 </span>            :       (_ftb_io_out_s3_full_pred_1_targets_1),</a>
+<a name="1966"><span class="lineNum">    1966 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_1_jalr_target</a>
+<a name="1967"><span class="lineNum">    1967 </span>            :       (_ftb_io_out_s3_full_pred_1_jalr_target),</a>
+<a name="1968"><span class="lineNum">    1968 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_1_fallThroughAddr</a>
+<a name="1969"><span class="lineNum">    1969 </span>            :       (_ftb_io_out_s3_full_pred_1_fallThroughAddr),</a>
+<a name="1970"><span class="lineNum">    1970 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_1_fallThroughErr</a>
+<a name="1971"><span class="lineNum">    1971 </span>            :       (_ftb_io_out_s3_full_pred_1_fallThroughErr),</a>
+<a name="1972"><span class="lineNum">    1972 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_1_is_br_sharing</a>
+<a name="1973"><span class="lineNum">    1973 </span>            :       (_ftb_io_out_s3_full_pred_1_is_br_sharing),</a>
+<a name="1974"><span class="lineNum">    1974 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_1_hit</a>
+<a name="1975"><span class="lineNum">    1975 </span>            :       (_ftb_io_out_s3_full_pred_1_hit),</a>
+<a name="1976"><span class="lineNum">    1976 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_0</a>
+<a name="1977"><span class="lineNum">    1977 </span>            :       (_ftb_io_out_s3_full_pred_2_br_taken_mask_0),</a>
+<a name="1978"><span class="lineNum">    1978 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_1</a>
+<a name="1979"><span class="lineNum">    1979 </span>            :       (_ftb_io_out_s3_full_pred_2_br_taken_mask_1),</a>
+<a name="1980"><span class="lineNum">    1980 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_0</a>
+<a name="1981"><span class="lineNum">    1981 </span>            :       (_ftb_io_out_s3_full_pred_2_slot_valids_0),</a>
+<a name="1982"><span class="lineNum">    1982 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_1</a>
+<a name="1983"><span class="lineNum">    1983 </span>            :       (_ftb_io_out_s3_full_pred_2_slot_valids_1),</a>
+<a name="1984"><span class="lineNum">    1984 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_2_targets_0</a>
+<a name="1985"><span class="lineNum">    1985 </span>            :       (_ftb_io_out_s3_full_pred_2_targets_0),</a>
+<a name="1986"><span class="lineNum">    1986 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_2_targets_1</a>
+<a name="1987"><span class="lineNum">    1987 </span>            :       (_ftb_io_out_s3_full_pred_2_targets_1),</a>
+<a name="1988"><span class="lineNum">    1988 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_2_jalr_target</a>
+<a name="1989"><span class="lineNum">    1989 </span>            :       (_ftb_io_out_s3_full_pred_2_jalr_target),</a>
+<a name="1990"><span class="lineNum">    1990 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_2_fallThroughAddr</a>
+<a name="1991"><span class="lineNum">    1991 </span>            :       (_ftb_io_out_s3_full_pred_2_fallThroughAddr),</a>
+<a name="1992"><span class="lineNum">    1992 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_2_fallThroughErr</a>
+<a name="1993"><span class="lineNum">    1993 </span>            :       (_ftb_io_out_s3_full_pred_2_fallThroughErr),</a>
+<a name="1994"><span class="lineNum">    1994 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_2_is_jalr</a>
+<a name="1995"><span class="lineNum">    1995 </span>            :       (_ftb_io_out_s3_full_pred_2_is_jalr),</a>
+<a name="1996"><span class="lineNum">    1996 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_2_is_call</a>
+<a name="1997"><span class="lineNum">    1997 </span>            :       (_ftb_io_out_s3_full_pred_2_is_call),</a>
+<a name="1998"><span class="lineNum">    1998 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_2_is_ret</a>
+<a name="1999"><span class="lineNum">    1999 </span>            :       (_ftb_io_out_s3_full_pred_2_is_ret),</a>
+<a name="2000"><span class="lineNum">    2000 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing</a>
+<a name="2001"><span class="lineNum">    2001 </span>            :       (_ftb_io_out_s3_full_pred_2_is_br_sharing),</a>
+<a name="2002"><span class="lineNum">    2002 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_2_hit</a>
+<a name="2003"><span class="lineNum">    2003 </span>            :       (_ftb_io_out_s3_full_pred_2_hit),</a>
+<a name="2004"><span class="lineNum">    2004 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_0</a>
+<a name="2005"><span class="lineNum">    2005 </span>            :       (_ftb_io_out_s3_full_pred_3_br_taken_mask_0),</a>
+<a name="2006"><span class="lineNum">    2006 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_1</a>
+<a name="2007"><span class="lineNum">    2007 </span>            :       (_ftb_io_out_s3_full_pred_3_br_taken_mask_1),</a>
+<a name="2008"><span class="lineNum">    2008 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_0</a>
+<a name="2009"><span class="lineNum">    2009 </span>            :       (_ftb_io_out_s3_full_pred_3_slot_valids_0),</a>
+<a name="2010"><span class="lineNum">    2010 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_1</a>
+<a name="2011"><span class="lineNum">    2011 </span>            :       (_ftb_io_out_s3_full_pred_3_slot_valids_1),</a>
+<a name="2012"><span class="lineNum">    2012 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_3_targets_0</a>
+<a name="2013"><span class="lineNum">    2013 </span>            :       (_ftb_io_out_s3_full_pred_3_targets_0),</a>
+<a name="2014"><span class="lineNum">    2014 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_3_targets_1</a>
+<a name="2015"><span class="lineNum">    2015 </span>            :       (_ftb_io_out_s3_full_pred_3_targets_1),</a>
+<a name="2016"><span class="lineNum">    2016 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_3_jalr_target</a>
+<a name="2017"><span class="lineNum">    2017 </span>            :       (_ftb_io_out_s3_full_pred_3_jalr_target),</a>
+<a name="2018"><span class="lineNum">    2018 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_3_offsets_0</a>
+<a name="2019"><span class="lineNum">    2019 </span>            :       (_ftb_io_out_s3_full_pred_3_offsets_0),</a>
+<a name="2020"><span class="lineNum">    2020 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_3_offsets_1</a>
+<a name="2021"><span class="lineNum">    2021 </span>            :       (_ftb_io_out_s3_full_pred_3_offsets_1),</a>
+<a name="2022"><span class="lineNum">    2022 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_3_fallThroughAddr</a>
+<a name="2023"><span class="lineNum">    2023 </span>            :       (_ftb_io_out_s3_full_pred_3_fallThroughAddr),</a>
+<a name="2024"><span class="lineNum">    2024 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_3_fallThroughErr</a>
+<a name="2025"><span class="lineNum">    2025 </span>            :       (_ftb_io_out_s3_full_pred_3_fallThroughErr),</a>
+<a name="2026"><span class="lineNum">    2026 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_3_is_br_sharing</a>
+<a name="2027"><span class="lineNum">    2027 </span>            :       (_ftb_io_out_s3_full_pred_3_is_br_sharing),</a>
+<a name="2028"><span class="lineNum">    2028 </span>            :     .io_in_bits_resp_in_0_s3_full_pred_3_hit</a>
+<a name="2029"><span class="lineNum">    2029 </span>            :       (_ftb_io_out_s3_full_pred_3_hit),</a>
+<a name="2030"><span class="lineNum">    2030 </span>            :     .io_in_bits_resp_in_0_last_stage_ftb_entry_valid</a>
+<a name="2031"><span class="lineNum">    2031 </span>            :       (_ftb_io_out_last_stage_ftb_entry_valid),</a>
+<a name="2032"><span class="lineNum">    2032 </span>            :     .io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_offset</a>
+<a name="2033"><span class="lineNum">    2033 </span>            :       (_ftb_io_out_last_stage_ftb_entry_brSlots_0_offset),</a>
+<a name="2034"><span class="lineNum">    2034 </span>            :     .io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_lower</a>
+<a name="2035"><span class="lineNum">    2035 </span>            :       (_ftb_io_out_last_stage_ftb_entry_brSlots_0_lower),</a>
+<a name="2036"><span class="lineNum">    2036 </span>            :     .io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_tarStat</a>
+<a name="2037"><span class="lineNum">    2037 </span>            :       (_ftb_io_out_last_stage_ftb_entry_brSlots_0_tarStat),</a>
+<a name="2038"><span class="lineNum">    2038 </span>            :     .io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_sharing</a>
+<a name="2039"><span class="lineNum">    2039 </span>            :       (_ftb_io_out_last_stage_ftb_entry_brSlots_0_sharing),</a>
+<a name="2040"><span class="lineNum">    2040 </span>            :     .io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_valid</a>
+<a name="2041"><span class="lineNum">    2041 </span>            :       (_ftb_io_out_last_stage_ftb_entry_brSlots_0_valid),</a>
+<a name="2042"><span class="lineNum">    2042 </span>            :     .io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_offset</a>
+<a name="2043"><span class="lineNum">    2043 </span>            :       (_ftb_io_out_last_stage_ftb_entry_tailSlot_offset),</a>
+<a name="2044"><span class="lineNum">    2044 </span>            :     .io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_lower</a>
+<a name="2045"><span class="lineNum">    2045 </span>            :       (_ftb_io_out_last_stage_ftb_entry_tailSlot_lower),</a>
+<a name="2046"><span class="lineNum">    2046 </span>            :     .io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_tarStat</a>
+<a name="2047"><span class="lineNum">    2047 </span>            :       (_ftb_io_out_last_stage_ftb_entry_tailSlot_tarStat),</a>
+<a name="2048"><span class="lineNum">    2048 </span>            :     .io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_sharing</a>
+<a name="2049"><span class="lineNum">    2049 </span>            :       (_ftb_io_out_last_stage_ftb_entry_tailSlot_sharing),</a>
+<a name="2050"><span class="lineNum">    2050 </span>            :     .io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_valid</a>
+<a name="2051"><span class="lineNum">    2051 </span>            :       (_ftb_io_out_last_stage_ftb_entry_tailSlot_valid),</a>
+<a name="2052"><span class="lineNum">    2052 </span>            :     .io_in_bits_resp_in_0_last_stage_ftb_entry_pftAddr</a>
+<a name="2053"><span class="lineNum">    2053 </span>            :       (_ftb_io_out_last_stage_ftb_entry_pftAddr),</a>
+<a name="2054"><span class="lineNum">    2054 </span>            :     .io_in_bits_resp_in_0_last_stage_ftb_entry_carry</a>
+<a name="2055"><span class="lineNum">    2055 </span>            :       (_ftb_io_out_last_stage_ftb_entry_carry),</a>
+<a name="2056"><span class="lineNum">    2056 </span>            :     .io_in_bits_resp_in_0_last_stage_ftb_entry_isCall</a>
+<a name="2057"><span class="lineNum">    2057 </span>            :       (_ftb_io_out_last_stage_ftb_entry_isCall),</a>
+<a name="2058"><span class="lineNum">    2058 </span>            :     .io_in_bits_resp_in_0_last_stage_ftb_entry_isRet</a>
+<a name="2059"><span class="lineNum">    2059 </span>            :       (_ftb_io_out_last_stage_ftb_entry_isRet),</a>
+<a name="2060"><span class="lineNum">    2060 </span>            :     .io_in_bits_resp_in_0_last_stage_ftb_entry_isJalr</a>
+<a name="2061"><span class="lineNum">    2061 </span>            :       (_ftb_io_out_last_stage_ftb_entry_isJalr),</a>
+<a name="2062"><span class="lineNum">    2062 </span>            :     .io_in_bits_resp_in_0_last_stage_ftb_entry_last_may_be_rvi_call</a>
+<a name="2063"><span class="lineNum">    2063 </span>            :       (_ftb_io_out_last_stage_ftb_entry_last_may_be_rvi_call),</a>
+<a name="2064"><span class="lineNum">    2064 </span>            :     .io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_0</a>
+<a name="2065"><span class="lineNum">    2065 </span>            :       (_ftb_io_out_last_stage_ftb_entry_always_taken_0),</a>
+<a name="2066"><span class="lineNum">    2066 </span>            :     .io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_1</a>
+<a name="2067"><span class="lineNum">    2067 </span>            :       (_ftb_io_out_last_stage_ftb_entry_always_taken_1),</a>
+<a name="2068"><span class="lineNum">    2068 </span>            :     .io_out_s2_full_pred_0_br_taken_mask_0</a>
+<a name="2069"><span class="lineNum">    2069 </span>            :       (_ittage_io_out_s2_full_pred_0_br_taken_mask_0),</a>
+<a name="2070"><span class="lineNum">    2070 </span>            :     .io_out_s2_full_pred_0_br_taken_mask_1</a>
+<a name="2071"><span class="lineNum">    2071 </span>            :       (_ittage_io_out_s2_full_pred_0_br_taken_mask_1),</a>
+<a name="2072"><span class="lineNum">    2072 </span>            :     .io_out_s2_full_pred_0_slot_valids_0</a>
+<a name="2073"><span class="lineNum">    2073 </span>            :       (_ittage_io_out_s2_full_pred_0_slot_valids_0),</a>
+<a name="2074"><span class="lineNum">    2074 </span>            :     .io_out_s2_full_pred_0_slot_valids_1</a>
+<a name="2075"><span class="lineNum">    2075 </span>            :       (_ittage_io_out_s2_full_pred_0_slot_valids_1),</a>
+<a name="2076"><span class="lineNum">    2076 </span>            :     .io_out_s2_full_pred_0_targets_0</a>
+<a name="2077"><span class="lineNum">    2077 </span>            :       (_ittage_io_out_s2_full_pred_0_targets_0),</a>
+<a name="2078"><span class="lineNum">    2078 </span>            :     .io_out_s2_full_pred_0_targets_1</a>
+<a name="2079"><span class="lineNum">    2079 </span>            :       (_ittage_io_out_s2_full_pred_0_targets_1),</a>
+<a name="2080"><span class="lineNum">    2080 </span>            :     .io_out_s2_full_pred_0_jalr_target</a>
+<a name="2081"><span class="lineNum">    2081 </span>            :       (_ittage_io_out_s2_full_pred_0_jalr_target),</a>
+<a name="2082"><span class="lineNum">    2082 </span>            :     .io_out_s2_full_pred_0_offsets_0</a>
+<a name="2083"><span class="lineNum">    2083 </span>            :       (_ittage_io_out_s2_full_pred_0_offsets_0),</a>
+<a name="2084"><span class="lineNum">    2084 </span>            :     .io_out_s2_full_pred_0_offsets_1</a>
+<a name="2085"><span class="lineNum">    2085 </span>            :       (_ittage_io_out_s2_full_pred_0_offsets_1),</a>
+<a name="2086"><span class="lineNum">    2086 </span>            :     .io_out_s2_full_pred_0_fallThroughAddr</a>
+<a name="2087"><span class="lineNum">    2087 </span>            :       (_ittage_io_out_s2_full_pred_0_fallThroughAddr),</a>
+<a name="2088"><span class="lineNum">    2088 </span>            :     .io_out_s2_full_pred_0_is_br_sharing</a>
+<a name="2089"><span class="lineNum">    2089 </span>            :       (_ittage_io_out_s2_full_pred_0_is_br_sharing),</a>
+<a name="2090"><span class="lineNum">    2090 </span>            :     .io_out_s2_full_pred_0_hit</a>
+<a name="2091"><span class="lineNum">    2091 </span>            :       (_ittage_io_out_s2_full_pred_0_hit),</a>
+<a name="2092"><span class="lineNum">    2092 </span>            :     .io_out_s2_full_pred_1_br_taken_mask_0</a>
+<a name="2093"><span class="lineNum">    2093 </span>            :       (_ittage_io_out_s2_full_pred_1_br_taken_mask_0),</a>
+<a name="2094"><span class="lineNum">    2094 </span>            :     .io_out_s2_full_pred_1_br_taken_mask_1</a>
+<a name="2095"><span class="lineNum">    2095 </span>            :       (_ittage_io_out_s2_full_pred_1_br_taken_mask_1),</a>
+<a name="2096"><span class="lineNum">    2096 </span>            :     .io_out_s2_full_pred_1_slot_valids_0</a>
+<a name="2097"><span class="lineNum">    2097 </span>            :       (_ittage_io_out_s2_full_pred_1_slot_valids_0),</a>
+<a name="2098"><span class="lineNum">    2098 </span>            :     .io_out_s2_full_pred_1_slot_valids_1</a>
+<a name="2099"><span class="lineNum">    2099 </span>            :       (_ittage_io_out_s2_full_pred_1_slot_valids_1),</a>
+<a name="2100"><span class="lineNum">    2100 </span>            :     .io_out_s2_full_pred_1_targets_0</a>
+<a name="2101"><span class="lineNum">    2101 </span>            :       (_ittage_io_out_s2_full_pred_1_targets_0),</a>
+<a name="2102"><span class="lineNum">    2102 </span>            :     .io_out_s2_full_pred_1_targets_1</a>
+<a name="2103"><span class="lineNum">    2103 </span>            :       (_ittage_io_out_s2_full_pred_1_targets_1),</a>
+<a name="2104"><span class="lineNum">    2104 </span>            :     .io_out_s2_full_pred_1_jalr_target</a>
+<a name="2105"><span class="lineNum">    2105 </span>            :       (_ittage_io_out_s2_full_pred_1_jalr_target),</a>
+<a name="2106"><span class="lineNum">    2106 </span>            :     .io_out_s2_full_pred_1_offsets_0</a>
+<a name="2107"><span class="lineNum">    2107 </span>            :       (_ittage_io_out_s2_full_pred_1_offsets_0),</a>
+<a name="2108"><span class="lineNum">    2108 </span>            :     .io_out_s2_full_pred_1_offsets_1</a>
+<a name="2109"><span class="lineNum">    2109 </span>            :       (_ittage_io_out_s2_full_pred_1_offsets_1),</a>
+<a name="2110"><span class="lineNum">    2110 </span>            :     .io_out_s2_full_pred_1_fallThroughAddr</a>
+<a name="2111"><span class="lineNum">    2111 </span>            :       (_ittage_io_out_s2_full_pred_1_fallThroughAddr),</a>
+<a name="2112"><span class="lineNum">    2112 </span>            :     .io_out_s2_full_pred_1_is_br_sharing</a>
+<a name="2113"><span class="lineNum">    2113 </span>            :       (_ittage_io_out_s2_full_pred_1_is_br_sharing),</a>
+<a name="2114"><span class="lineNum">    2114 </span>            :     .io_out_s2_full_pred_1_hit</a>
+<a name="2115"><span class="lineNum">    2115 </span>            :       (_ittage_io_out_s2_full_pred_1_hit),</a>
+<a name="2116"><span class="lineNum">    2116 </span>            :     .io_out_s2_full_pred_2_br_taken_mask_0</a>
+<a name="2117"><span class="lineNum">    2117 </span>            :       (_ittage_io_out_s2_full_pred_2_br_taken_mask_0),</a>
+<a name="2118"><span class="lineNum">    2118 </span>            :     .io_out_s2_full_pred_2_br_taken_mask_1</a>
+<a name="2119"><span class="lineNum">    2119 </span>            :       (_ittage_io_out_s2_full_pred_2_br_taken_mask_1),</a>
+<a name="2120"><span class="lineNum">    2120 </span>            :     .io_out_s2_full_pred_2_slot_valids_0</a>
+<a name="2121"><span class="lineNum">    2121 </span>            :       (_ittage_io_out_s2_full_pred_2_slot_valids_0),</a>
+<a name="2122"><span class="lineNum">    2122 </span>            :     .io_out_s2_full_pred_2_slot_valids_1</a>
+<a name="2123"><span class="lineNum">    2123 </span>            :       (_ittage_io_out_s2_full_pred_2_slot_valids_1),</a>
+<a name="2124"><span class="lineNum">    2124 </span>            :     .io_out_s2_full_pred_2_targets_0</a>
+<a name="2125"><span class="lineNum">    2125 </span>            :       (_ittage_io_out_s2_full_pred_2_targets_0),</a>
+<a name="2126"><span class="lineNum">    2126 </span>            :     .io_out_s2_full_pred_2_targets_1</a>
+<a name="2127"><span class="lineNum">    2127 </span>            :       (_ittage_io_out_s2_full_pred_2_targets_1),</a>
+<a name="2128"><span class="lineNum">    2128 </span>            :     .io_out_s2_full_pred_2_jalr_target</a>
+<a name="2129"><span class="lineNum">    2129 </span>            :       (_ittage_io_out_s2_full_pred_2_jalr_target),</a>
+<a name="2130"><span class="lineNum">    2130 </span>            :     .io_out_s2_full_pred_2_offsets_0</a>
+<a name="2131"><span class="lineNum">    2131 </span>            :       (_ittage_io_out_s2_full_pred_2_offsets_0),</a>
+<a name="2132"><span class="lineNum">    2132 </span>            :     .io_out_s2_full_pred_2_offsets_1</a>
+<a name="2133"><span class="lineNum">    2133 </span>            :       (_ittage_io_out_s2_full_pred_2_offsets_1),</a>
+<a name="2134"><span class="lineNum">    2134 </span>            :     .io_out_s2_full_pred_2_fallThroughAddr</a>
+<a name="2135"><span class="lineNum">    2135 </span>            :       (_ittage_io_out_s2_full_pred_2_fallThroughAddr),</a>
+<a name="2136"><span class="lineNum">    2136 </span>            :     .io_out_s2_full_pred_2_is_jalr</a>
+<a name="2137"><span class="lineNum">    2137 </span>            :       (_ittage_io_out_s2_full_pred_2_is_jalr),</a>
+<a name="2138"><span class="lineNum">    2138 </span>            :     .io_out_s2_full_pred_2_is_call</a>
+<a name="2139"><span class="lineNum">    2139 </span>            :       (_ittage_io_out_s2_full_pred_2_is_call),</a>
+<a name="2140"><span class="lineNum">    2140 </span>            :     .io_out_s2_full_pred_2_is_ret</a>
+<a name="2141"><span class="lineNum">    2141 </span>            :       (_ittage_io_out_s2_full_pred_2_is_ret),</a>
+<a name="2142"><span class="lineNum">    2142 </span>            :     .io_out_s2_full_pred_2_last_may_be_rvi_call</a>
+<a name="2143"><span class="lineNum">    2143 </span>            :       (_ittage_io_out_s2_full_pred_2_last_may_be_rvi_call),</a>
+<a name="2144"><span class="lineNum">    2144 </span>            :     .io_out_s2_full_pred_2_is_br_sharing</a>
+<a name="2145"><span class="lineNum">    2145 </span>            :       (_ittage_io_out_s2_full_pred_2_is_br_sharing),</a>
+<a name="2146"><span class="lineNum">    2146 </span>            :     .io_out_s2_full_pred_2_hit</a>
+<a name="2147"><span class="lineNum">    2147 </span>            :       (_ittage_io_out_s2_full_pred_2_hit),</a>
+<a name="2148"><span class="lineNum">    2148 </span>            :     .io_out_s2_full_pred_3_br_taken_mask_0</a>
+<a name="2149"><span class="lineNum">    2149 </span>            :       (_ittage_io_out_s2_full_pred_3_br_taken_mask_0),</a>
+<a name="2150"><span class="lineNum">    2150 </span>            :     .io_out_s2_full_pred_3_br_taken_mask_1</a>
+<a name="2151"><span class="lineNum">    2151 </span>            :       (_ittage_io_out_s2_full_pred_3_br_taken_mask_1),</a>
+<a name="2152"><span class="lineNum">    2152 </span>            :     .io_out_s2_full_pred_3_slot_valids_0</a>
+<a name="2153"><span class="lineNum">    2153 </span>            :       (_ittage_io_out_s2_full_pred_3_slot_valids_0),</a>
+<a name="2154"><span class="lineNum">    2154 </span>            :     .io_out_s2_full_pred_3_slot_valids_1</a>
+<a name="2155"><span class="lineNum">    2155 </span>            :       (_ittage_io_out_s2_full_pred_3_slot_valids_1),</a>
+<a name="2156"><span class="lineNum">    2156 </span>            :     .io_out_s2_full_pred_3_targets_0</a>
+<a name="2157"><span class="lineNum">    2157 </span>            :       (_ittage_io_out_s2_full_pred_3_targets_0),</a>
+<a name="2158"><span class="lineNum">    2158 </span>            :     .io_out_s2_full_pred_3_targets_1</a>
+<a name="2159"><span class="lineNum">    2159 </span>            :       (_ittage_io_out_s2_full_pred_3_targets_1),</a>
+<a name="2160"><span class="lineNum">    2160 </span>            :     .io_out_s2_full_pred_3_jalr_target</a>
+<a name="2161"><span class="lineNum">    2161 </span>            :       (_ittage_io_out_s2_full_pred_3_jalr_target),</a>
+<a name="2162"><span class="lineNum">    2162 </span>            :     .io_out_s2_full_pred_3_offsets_0</a>
+<a name="2163"><span class="lineNum">    2163 </span>            :       (_ittage_io_out_s2_full_pred_3_offsets_0),</a>
+<a name="2164"><span class="lineNum">    2164 </span>            :     .io_out_s2_full_pred_3_offsets_1</a>
+<a name="2165"><span class="lineNum">    2165 </span>            :       (_ittage_io_out_s2_full_pred_3_offsets_1),</a>
+<a name="2166"><span class="lineNum">    2166 </span>            :     .io_out_s2_full_pred_3_fallThroughAddr</a>
+<a name="2167"><span class="lineNum">    2167 </span>            :       (_ittage_io_out_s2_full_pred_3_fallThroughAddr),</a>
+<a name="2168"><span class="lineNum">    2168 </span>            :     .io_out_s2_full_pred_3_fallThroughErr</a>
+<a name="2169"><span class="lineNum">    2169 </span>            :       (_ittage_io_out_s2_full_pred_3_fallThroughErr),</a>
+<a name="2170"><span class="lineNum">    2170 </span>            :     .io_out_s2_full_pred_3_is_br_sharing</a>
+<a name="2171"><span class="lineNum">    2171 </span>            :       (_ittage_io_out_s2_full_pred_3_is_br_sharing),</a>
+<a name="2172"><span class="lineNum">    2172 </span>            :     .io_out_s2_full_pred_3_hit</a>
+<a name="2173"><span class="lineNum">    2173 </span>            :       (_ittage_io_out_s2_full_pred_3_hit),</a>
+<a name="2174"><span class="lineNum">    2174 </span>            :     .io_out_s3_full_pred_0_br_taken_mask_0</a>
+<a name="2175"><span class="lineNum">    2175 </span>            :       (_ittage_io_out_s3_full_pred_0_br_taken_mask_0),</a>
+<a name="2176"><span class="lineNum">    2176 </span>            :     .io_out_s3_full_pred_0_br_taken_mask_1</a>
+<a name="2177"><span class="lineNum">    2177 </span>            :       (_ittage_io_out_s3_full_pred_0_br_taken_mask_1),</a>
+<a name="2178"><span class="lineNum">    2178 </span>            :     .io_out_s3_full_pred_0_slot_valids_0</a>
+<a name="2179"><span class="lineNum">    2179 </span>            :       (_ittage_io_out_s3_full_pred_0_slot_valids_0),</a>
+<a name="2180"><span class="lineNum">    2180 </span>            :     .io_out_s3_full_pred_0_slot_valids_1</a>
+<a name="2181"><span class="lineNum">    2181 </span>            :       (_ittage_io_out_s3_full_pred_0_slot_valids_1),</a>
+<a name="2182"><span class="lineNum">    2182 </span>            :     .io_out_s3_full_pred_0_targets_0</a>
+<a name="2183"><span class="lineNum">    2183 </span>            :       (_ittage_io_out_s3_full_pred_0_targets_0),</a>
+<a name="2184"><span class="lineNum">    2184 </span>            :     .io_out_s3_full_pred_0_targets_1</a>
+<a name="2185"><span class="lineNum">    2185 </span>            :       (_ittage_io_out_s3_full_pred_0_targets_1),</a>
+<a name="2186"><span class="lineNum">    2186 </span>            :     .io_out_s3_full_pred_0_jalr_target</a>
+<a name="2187"><span class="lineNum">    2187 </span>            :       (_ittage_io_out_s3_full_pred_0_jalr_target),</a>
+<a name="2188"><span class="lineNum">    2188 </span>            :     .io_out_s3_full_pred_0_fallThroughAddr</a>
+<a name="2189"><span class="lineNum">    2189 </span>            :       (_ittage_io_out_s3_full_pred_0_fallThroughAddr),</a>
+<a name="2190"><span class="lineNum">    2190 </span>            :     .io_out_s3_full_pred_0_fallThroughErr</a>
+<a name="2191"><span class="lineNum">    2191 </span>            :       (_ittage_io_out_s3_full_pred_0_fallThroughErr),</a>
+<a name="2192"><span class="lineNum">    2192 </span>            :     .io_out_s3_full_pred_0_is_br_sharing</a>
+<a name="2193"><span class="lineNum">    2193 </span>            :       (_ittage_io_out_s3_full_pred_0_is_br_sharing),</a>
+<a name="2194"><span class="lineNum">    2194 </span>            :     .io_out_s3_full_pred_0_hit</a>
+<a name="2195"><span class="lineNum">    2195 </span>            :       (_ittage_io_out_s3_full_pred_0_hit),</a>
+<a name="2196"><span class="lineNum">    2196 </span>            :     .io_out_s3_full_pred_1_br_taken_mask_0</a>
+<a name="2197"><span class="lineNum">    2197 </span>            :       (_ittage_io_out_s3_full_pred_1_br_taken_mask_0),</a>
+<a name="2198"><span class="lineNum">    2198 </span>            :     .io_out_s3_full_pred_1_br_taken_mask_1</a>
+<a name="2199"><span class="lineNum">    2199 </span>            :       (_ittage_io_out_s3_full_pred_1_br_taken_mask_1),</a>
+<a name="2200"><span class="lineNum">    2200 </span>            :     .io_out_s3_full_pred_1_slot_valids_0</a>
+<a name="2201"><span class="lineNum">    2201 </span>            :       (_ittage_io_out_s3_full_pred_1_slot_valids_0),</a>
+<a name="2202"><span class="lineNum">    2202 </span>            :     .io_out_s3_full_pred_1_slot_valids_1</a>
+<a name="2203"><span class="lineNum">    2203 </span>            :       (_ittage_io_out_s3_full_pred_1_slot_valids_1),</a>
+<a name="2204"><span class="lineNum">    2204 </span>            :     .io_out_s3_full_pred_1_targets_0</a>
+<a name="2205"><span class="lineNum">    2205 </span>            :       (_ittage_io_out_s3_full_pred_1_targets_0),</a>
+<a name="2206"><span class="lineNum">    2206 </span>            :     .io_out_s3_full_pred_1_targets_1</a>
+<a name="2207"><span class="lineNum">    2207 </span>            :       (_ittage_io_out_s3_full_pred_1_targets_1),</a>
+<a name="2208"><span class="lineNum">    2208 </span>            :     .io_out_s3_full_pred_1_jalr_target</a>
+<a name="2209"><span class="lineNum">    2209 </span>            :       (_ittage_io_out_s3_full_pred_1_jalr_target),</a>
+<a name="2210"><span class="lineNum">    2210 </span>            :     .io_out_s3_full_pred_1_fallThroughAddr</a>
+<a name="2211"><span class="lineNum">    2211 </span>            :       (_ittage_io_out_s3_full_pred_1_fallThroughAddr),</a>
+<a name="2212"><span class="lineNum">    2212 </span>            :     .io_out_s3_full_pred_1_fallThroughErr</a>
+<a name="2213"><span class="lineNum">    2213 </span>            :       (_ittage_io_out_s3_full_pred_1_fallThroughErr),</a>
+<a name="2214"><span class="lineNum">    2214 </span>            :     .io_out_s3_full_pred_1_is_br_sharing</a>
+<a name="2215"><span class="lineNum">    2215 </span>            :       (_ittage_io_out_s3_full_pred_1_is_br_sharing),</a>
+<a name="2216"><span class="lineNum">    2216 </span>            :     .io_out_s3_full_pred_1_hit</a>
+<a name="2217"><span class="lineNum">    2217 </span>            :       (_ittage_io_out_s3_full_pred_1_hit),</a>
+<a name="2218"><span class="lineNum">    2218 </span>            :     .io_out_s3_full_pred_2_br_taken_mask_0</a>
+<a name="2219"><span class="lineNum">    2219 </span>            :       (_ittage_io_out_s3_full_pred_2_br_taken_mask_0),</a>
+<a name="2220"><span class="lineNum">    2220 </span>            :     .io_out_s3_full_pred_2_br_taken_mask_1</a>
+<a name="2221"><span class="lineNum">    2221 </span>            :       (_ittage_io_out_s3_full_pred_2_br_taken_mask_1),</a>
+<a name="2222"><span class="lineNum">    2222 </span>            :     .io_out_s3_full_pred_2_slot_valids_0</a>
+<a name="2223"><span class="lineNum">    2223 </span>            :       (_ittage_io_out_s3_full_pred_2_slot_valids_0),</a>
+<a name="2224"><span class="lineNum">    2224 </span>            :     .io_out_s3_full_pred_2_slot_valids_1</a>
+<a name="2225"><span class="lineNum">    2225 </span>            :       (_ittage_io_out_s3_full_pred_2_slot_valids_1),</a>
+<a name="2226"><span class="lineNum">    2226 </span>            :     .io_out_s3_full_pred_2_targets_0</a>
+<a name="2227"><span class="lineNum">    2227 </span>            :       (_ittage_io_out_s3_full_pred_2_targets_0),</a>
+<a name="2228"><span class="lineNum">    2228 </span>            :     .io_out_s3_full_pred_2_targets_1</a>
+<a name="2229"><span class="lineNum">    2229 </span>            :       (_ittage_io_out_s3_full_pred_2_targets_1),</a>
+<a name="2230"><span class="lineNum">    2230 </span>            :     .io_out_s3_full_pred_2_jalr_target</a>
+<a name="2231"><span class="lineNum">    2231 </span>            :       (_ittage_io_out_s3_full_pred_2_jalr_target),</a>
+<a name="2232"><span class="lineNum">    2232 </span>            :     .io_out_s3_full_pred_2_fallThroughAddr</a>
+<a name="2233"><span class="lineNum">    2233 </span>            :       (_ittage_io_out_s3_full_pred_2_fallThroughAddr),</a>
+<a name="2234"><span class="lineNum">    2234 </span>            :     .io_out_s3_full_pred_2_fallThroughErr</a>
+<a name="2235"><span class="lineNum">    2235 </span>            :       (_ittage_io_out_s3_full_pred_2_fallThroughErr),</a>
+<a name="2236"><span class="lineNum">    2236 </span>            :     .io_out_s3_full_pred_2_is_jalr</a>
+<a name="2237"><span class="lineNum">    2237 </span>            :       (_ittage_io_out_s3_full_pred_2_is_jalr),</a>
+<a name="2238"><span class="lineNum">    2238 </span>            :     .io_out_s3_full_pred_2_is_call</a>
+<a name="2239"><span class="lineNum">    2239 </span>            :       (_ittage_io_out_s3_full_pred_2_is_call),</a>
+<a name="2240"><span class="lineNum">    2240 </span>            :     .io_out_s3_full_pred_2_is_ret</a>
+<a name="2241"><span class="lineNum">    2241 </span>            :       (_ittage_io_out_s3_full_pred_2_is_ret),</a>
+<a name="2242"><span class="lineNum">    2242 </span>            :     .io_out_s3_full_pred_2_is_br_sharing</a>
+<a name="2243"><span class="lineNum">    2243 </span>            :       (_ittage_io_out_s3_full_pred_2_is_br_sharing),</a>
+<a name="2244"><span class="lineNum">    2244 </span>            :     .io_out_s3_full_pred_2_hit</a>
+<a name="2245"><span class="lineNum">    2245 </span>            :       (_ittage_io_out_s3_full_pred_2_hit),</a>
+<a name="2246"><span class="lineNum">    2246 </span>            :     .io_out_s3_full_pred_3_br_taken_mask_0</a>
+<a name="2247"><span class="lineNum">    2247 </span>            :       (_ittage_io_out_s3_full_pred_3_br_taken_mask_0),</a>
+<a name="2248"><span class="lineNum">    2248 </span>            :     .io_out_s3_full_pred_3_br_taken_mask_1</a>
+<a name="2249"><span class="lineNum">    2249 </span>            :       (_ittage_io_out_s3_full_pred_3_br_taken_mask_1),</a>
+<a name="2250"><span class="lineNum">    2250 </span>            :     .io_out_s3_full_pred_3_slot_valids_0</a>
+<a name="2251"><span class="lineNum">    2251 </span>            :       (_ittage_io_out_s3_full_pred_3_slot_valids_0),</a>
+<a name="2252"><span class="lineNum">    2252 </span>            :     .io_out_s3_full_pred_3_slot_valids_1</a>
+<a name="2253"><span class="lineNum">    2253 </span>            :       (_ittage_io_out_s3_full_pred_3_slot_valids_1),</a>
+<a name="2254"><span class="lineNum">    2254 </span>            :     .io_out_s3_full_pred_3_targets_0</a>
+<a name="2255"><span class="lineNum">    2255 </span>            :       (_ittage_io_out_s3_full_pred_3_targets_0),</a>
+<a name="2256"><span class="lineNum">    2256 </span>            :     .io_out_s3_full_pred_3_targets_1</a>
+<a name="2257"><span class="lineNum">    2257 </span>            :       (_ittage_io_out_s3_full_pred_3_targets_1),</a>
+<a name="2258"><span class="lineNum">    2258 </span>            :     .io_out_s3_full_pred_3_jalr_target</a>
+<a name="2259"><span class="lineNum">    2259 </span>            :       (_ittage_io_out_s3_full_pred_3_jalr_target),</a>
+<a name="2260"><span class="lineNum">    2260 </span>            :     .io_out_s3_full_pred_3_offsets_0</a>
+<a name="2261"><span class="lineNum">    2261 </span>            :       (_ittage_io_out_s3_full_pred_3_offsets_0),</a>
+<a name="2262"><span class="lineNum">    2262 </span>            :     .io_out_s3_full_pred_3_offsets_1</a>
+<a name="2263"><span class="lineNum">    2263 </span>            :       (_ittage_io_out_s3_full_pred_3_offsets_1),</a>
+<a name="2264"><span class="lineNum">    2264 </span>            :     .io_out_s3_full_pred_3_fallThroughAddr</a>
+<a name="2265"><span class="lineNum">    2265 </span>            :       (_ittage_io_out_s3_full_pred_3_fallThroughAddr),</a>
+<a name="2266"><span class="lineNum">    2266 </span>            :     .io_out_s3_full_pred_3_fallThroughErr</a>
+<a name="2267"><span class="lineNum">    2267 </span>            :       (_ittage_io_out_s3_full_pred_3_fallThroughErr),</a>
+<a name="2268"><span class="lineNum">    2268 </span>            :     .io_out_s3_full_pred_3_is_br_sharing</a>
+<a name="2269"><span class="lineNum">    2269 </span>            :       (_ittage_io_out_s3_full_pred_3_is_br_sharing),</a>
+<a name="2270"><span class="lineNum">    2270 </span>            :     .io_out_s3_full_pred_3_hit</a>
+<a name="2271"><span class="lineNum">    2271 </span>            :       (_ittage_io_out_s3_full_pred_3_hit),</a>
+<a name="2272"><span class="lineNum">    2272 </span>            :     .io_out_last_stage_meta</a>
+<a name="2273"><span class="lineNum">    2273 </span>            :       (_ittage_io_out_last_stage_meta),</a>
+<a name="2274"><span class="lineNum">    2274 </span>            :     .io_out_last_stage_ftb_entry_valid</a>
+<a name="2275"><span class="lineNum">    2275 </span>            :       (_ittage_io_out_last_stage_ftb_entry_valid),</a>
+<a name="2276"><span class="lineNum">    2276 </span>            :     .io_out_last_stage_ftb_entry_brSlots_0_offset</a>
+<a name="2277"><span class="lineNum">    2277 </span>            :       (_ittage_io_out_last_stage_ftb_entry_brSlots_0_offset),</a>
+<a name="2278"><span class="lineNum">    2278 </span>            :     .io_out_last_stage_ftb_entry_brSlots_0_lower</a>
+<a name="2279"><span class="lineNum">    2279 </span>            :       (_ittage_io_out_last_stage_ftb_entry_brSlots_0_lower),</a>
+<a name="2280"><span class="lineNum">    2280 </span>            :     .io_out_last_stage_ftb_entry_brSlots_0_tarStat</a>
+<a name="2281"><span class="lineNum">    2281 </span>            :       (_ittage_io_out_last_stage_ftb_entry_brSlots_0_tarStat),</a>
+<a name="2282"><span class="lineNum">    2282 </span>            :     .io_out_last_stage_ftb_entry_brSlots_0_sharing</a>
+<a name="2283"><span class="lineNum">    2283 </span>            :       (_ittage_io_out_last_stage_ftb_entry_brSlots_0_sharing),</a>
+<a name="2284"><span class="lineNum">    2284 </span>            :     .io_out_last_stage_ftb_entry_brSlots_0_valid</a>
+<a name="2285"><span class="lineNum">    2285 </span>            :       (_ittage_io_out_last_stage_ftb_entry_brSlots_0_valid),</a>
+<a name="2286"><span class="lineNum">    2286 </span>            :     .io_out_last_stage_ftb_entry_tailSlot_offset</a>
+<a name="2287"><span class="lineNum">    2287 </span>            :       (_ittage_io_out_last_stage_ftb_entry_tailSlot_offset),</a>
+<a name="2288"><span class="lineNum">    2288 </span>            :     .io_out_last_stage_ftb_entry_tailSlot_lower</a>
+<a name="2289"><span class="lineNum">    2289 </span>            :       (_ittage_io_out_last_stage_ftb_entry_tailSlot_lower),</a>
+<a name="2290"><span class="lineNum">    2290 </span>            :     .io_out_last_stage_ftb_entry_tailSlot_tarStat</a>
+<a name="2291"><span class="lineNum">    2291 </span>            :       (_ittage_io_out_last_stage_ftb_entry_tailSlot_tarStat),</a>
+<a name="2292"><span class="lineNum">    2292 </span>            :     .io_out_last_stage_ftb_entry_tailSlot_sharing</a>
+<a name="2293"><span class="lineNum">    2293 </span>            :       (_ittage_io_out_last_stage_ftb_entry_tailSlot_sharing),</a>
+<a name="2294"><span class="lineNum">    2294 </span>            :     .io_out_last_stage_ftb_entry_tailSlot_valid</a>
+<a name="2295"><span class="lineNum">    2295 </span>            :       (_ittage_io_out_last_stage_ftb_entry_tailSlot_valid),</a>
+<a name="2296"><span class="lineNum">    2296 </span>            :     .io_out_last_stage_ftb_entry_pftAddr</a>
+<a name="2297"><span class="lineNum">    2297 </span>            :       (_ittage_io_out_last_stage_ftb_entry_pftAddr),</a>
+<a name="2298"><span class="lineNum">    2298 </span>            :     .io_out_last_stage_ftb_entry_carry</a>
+<a name="2299"><span class="lineNum">    2299 </span>            :       (_ittage_io_out_last_stage_ftb_entry_carry),</a>
+<a name="2300"><span class="lineNum">    2300 </span>            :     .io_out_last_stage_ftb_entry_isCall</a>
+<a name="2301"><span class="lineNum">    2301 </span>            :       (_ittage_io_out_last_stage_ftb_entry_isCall),</a>
+<a name="2302"><span class="lineNum">    2302 </span>            :     .io_out_last_stage_ftb_entry_isRet</a>
+<a name="2303"><span class="lineNum">    2303 </span>            :       (_ittage_io_out_last_stage_ftb_entry_isRet),</a>
+<a name="2304"><span class="lineNum">    2304 </span>            :     .io_out_last_stage_ftb_entry_isJalr</a>
+<a name="2305"><span class="lineNum">    2305 </span>            :       (_ittage_io_out_last_stage_ftb_entry_isJalr),</a>
+<a name="2306"><span class="lineNum">    2306 </span>            :     .io_out_last_stage_ftb_entry_last_may_be_rvi_call</a>
+<a name="2307"><span class="lineNum">    2307 </span>            :       (_ittage_io_out_last_stage_ftb_entry_last_may_be_rvi_call),</a>
+<a name="2308"><span class="lineNum">    2308 </span>            :     .io_out_last_stage_ftb_entry_always_taken_0</a>
+<a name="2309"><span class="lineNum">    2309 </span>            :       (_ittage_io_out_last_stage_ftb_entry_always_taken_0),</a>
+<a name="2310"><span class="lineNum">    2310 </span>            :     .io_out_last_stage_ftb_entry_always_taken_1</a>
+<a name="2311"><span class="lineNum">    2311 </span>            :       (_ittage_io_out_last_stage_ftb_entry_always_taken_1),</a>
+<a name="2312"><span class="lineNum">    2312 </span>            :     .io_s0_fire_3                                                   (io_s0_fire_3),</a>
+<a name="2313"><span class="lineNum">    2313 </span>            :     .io_s1_fire_3                                                   (io_s1_fire_3),</a>
+<a name="2314"><span class="lineNum">    2314 </span>            :     .io_s2_fire_0                                                   (io_s2_fire_0),</a>
+<a name="2315"><span class="lineNum">    2315 </span>            :     .io_s2_fire_1                                                   (io_s2_fire_1),</a>
+<a name="2316"><span class="lineNum">    2316 </span>            :     .io_s2_fire_2                                                   (io_s2_fire_2),</a>
+<a name="2317"><span class="lineNum">    2317 </span>            :     .io_s2_fire_3                                                   (io_s2_fire_3),</a>
+<a name="2318"><span class="lineNum">    2318 </span>            :     .io_update_valid                                                (io_update_valid),</a>
+<a name="2319"><span class="lineNum">    2319 </span>            :     .io_update_bits_pc                                              (io_update_bits_pc),</a>
+<a name="2320"><span class="lineNum">    2320 </span>            :     .io_update_bits_spec_info_folded_hist_hist_14_folded_hist</a>
+<a name="2321"><span class="lineNum">    2321 </span>            :       (io_update_bits_spec_info_folded_hist_hist_14_folded_hist),</a>
+<a name="2322"><span class="lineNum">    2322 </span>            :     .io_update_bits_spec_info_folded_hist_hist_13_folded_hist</a>
+<a name="2323"><span class="lineNum">    2323 </span>            :       (io_update_bits_spec_info_folded_hist_hist_13_folded_hist),</a>
+<a name="2324"><span class="lineNum">    2324 </span>            :     .io_update_bits_spec_info_folded_hist_hist_12_folded_hist</a>
+<a name="2325"><span class="lineNum">    2325 </span>            :       (io_update_bits_spec_info_folded_hist_hist_12_folded_hist),</a>
+<a name="2326"><span class="lineNum">    2326 </span>            :     .io_update_bits_spec_info_folded_hist_hist_10_folded_hist</a>
+<a name="2327"><span class="lineNum">    2327 </span>            :       (io_update_bits_spec_info_folded_hist_hist_10_folded_hist),</a>
+<a name="2328"><span class="lineNum">    2328 </span>            :     .io_update_bits_spec_info_folded_hist_hist_6_folded_hist</a>
+<a name="2329"><span class="lineNum">    2329 </span>            :       (io_update_bits_spec_info_folded_hist_hist_6_folded_hist),</a>
+<a name="2330"><span class="lineNum">    2330 </span>            :     .io_update_bits_spec_info_folded_hist_hist_4_folded_hist</a>
+<a name="2331"><span class="lineNum">    2331 </span>            :       (io_update_bits_spec_info_folded_hist_hist_4_folded_hist),</a>
+<a name="2332"><span class="lineNum">    2332 </span>            :     .io_update_bits_spec_info_folded_hist_hist_3_folded_hist</a>
+<a name="2333"><span class="lineNum">    2333 </span>            :       (io_update_bits_spec_info_folded_hist_hist_3_folded_hist),</a>
+<a name="2334"><span class="lineNum">    2334 </span>            :     .io_update_bits_spec_info_folded_hist_hist_2_folded_hist</a>
+<a name="2335"><span class="lineNum">    2335 </span>            :       (io_update_bits_spec_info_folded_hist_hist_2_folded_hist),</a>
+<a name="2336"><span class="lineNum">    2336 </span>            :     .io_update_bits_ftb_entry_tailSlot_offset</a>
+<a name="2337"><span class="lineNum">    2337 </span>            :       (io_update_bits_ftb_entry_tailSlot_offset),</a>
+<a name="2338"><span class="lineNum">    2338 </span>            :     .io_update_bits_ftb_entry_tailSlot_sharing</a>
+<a name="2339"><span class="lineNum">    2339 </span>            :       (io_update_bits_ftb_entry_tailSlot_sharing),</a>
+<a name="2340"><span class="lineNum">    2340 </span>            :     .io_update_bits_ftb_entry_tailSlot_valid</a>
+<a name="2341"><span class="lineNum">    2341 </span>            :       (io_update_bits_ftb_entry_tailSlot_valid),</a>
+<a name="2342"><span class="lineNum">    2342 </span>            :     .io_update_bits_ftb_entry_isRet</a>
+<a name="2343"><span class="lineNum">    2343 </span>            :       (io_update_bits_ftb_entry_isRet),</a>
+<a name="2344"><span class="lineNum">    2344 </span>            :     .io_update_bits_ftb_entry_isJalr</a>
+<a name="2345"><span class="lineNum">    2345 </span>            :       (io_update_bits_ftb_entry_isJalr),</a>
+<a name="2346"><span class="lineNum">    2346 </span>            :     .io_update_bits_cfi_idx_valid</a>
+<a name="2347"><span class="lineNum">    2347 </span>            :       (io_update_bits_cfi_idx_valid),</a>
+<a name="2348"><span class="lineNum">    2348 </span>            :     .io_update_bits_cfi_idx_bits</a>
+<a name="2349"><span class="lineNum">    2349 </span>            :       (io_update_bits_cfi_idx_bits),</a>
+<a name="2350"><span class="lineNum">    2350 </span>            :     .io_update_bits_jmp_taken</a>
+<a name="2351"><span class="lineNum">    2351 </span>            :       (io_update_bits_jmp_taken),</a>
+<a name="2352"><span class="lineNum">    2352 </span>            :     .io_update_bits_mispred_mask_2</a>
+<a name="2353"><span class="lineNum">    2353 </span>            :       (io_update_bits_mispred_mask_2),</a>
+<a name="2354"><span class="lineNum">    2354 </span>            :     .io_update_bits_meta</a>
+<a name="2355"><span class="lineNum">    2355 </span>            :       ({25'h0, io_update_bits_meta[222:25]}),</a>
+<a name="2356"><span class="lineNum">    2356 </span>            :     .io_update_bits_full_target</a>
+<a name="2357"><span class="lineNum">    2357 </span>            :       (io_update_bits_full_target)</a>
+<a name="2358"><span class="lineNum">    2358 </span>            :   );</a>
+<a name="2359"><span class="lineNum">    2359 </span>            :   DelayN_1 ubtb_io_ctrl_delay (</a>
+<a name="2360"><span class="lineNum">    2360 </span>            :     .clock              (clock),</a>
+<a name="2361"><span class="lineNum">    2361 </span>            :     .io_in_ubtb_enable  (io_ctrl_ubtb_enable),</a>
+<a name="2362"><span class="lineNum">    2362 </span>            :     .io_in_btb_enable   (io_ctrl_btb_enable),</a>
+<a name="2363"><span class="lineNum">    2363 </span>            :     .io_in_tage_enable  (io_ctrl_tage_enable),</a>
+<a name="2364"><span class="lineNum">    2364 </span>            :     .io_in_sc_enable    (io_ctrl_sc_enable),</a>
+<a name="2365"><span class="lineNum">    2365 </span>            :     .io_in_ras_enable   (io_ctrl_ras_enable),</a>
+<a name="2366"><span class="lineNum">    2366 </span>            :     .io_out_ubtb_enable (_ubtb_io_ctrl_delay_io_out_ubtb_enable),</a>
+<a name="2367"><span class="lineNum">    2367 </span>            :     .io_out_btb_enable  (/* unused */),</a>
+<a name="2368"><span class="lineNum">    2368 </span>            :     .io_out_tage_enable (/* unused */),</a>
+<a name="2369"><span class="lineNum">    2369 </span>            :     .io_out_sc_enable   (/* unused */),</a>
+<a name="2370"><span class="lineNum">    2370 </span>            :     .io_out_ras_enable  (/* unused */)</a>
+<a name="2371"><span class="lineNum">    2371 </span>            :   );</a>
+<a name="2372"><span class="lineNum">    2372 </span>            :   DelayN_1 tage_io_ctrl_delay (</a>
+<a name="2373"><span class="lineNum">    2373 </span>            :     .clock              (clock),</a>
+<a name="2374"><span class="lineNum">    2374 </span>            :     .io_in_ubtb_enable  (io_ctrl_ubtb_enable),</a>
+<a name="2375"><span class="lineNum">    2375 </span>            :     .io_in_btb_enable   (io_ctrl_btb_enable),</a>
+<a name="2376"><span class="lineNum">    2376 </span>            :     .io_in_tage_enable  (io_ctrl_tage_enable),</a>
+<a name="2377"><span class="lineNum">    2377 </span>            :     .io_in_sc_enable    (io_ctrl_sc_enable),</a>
+<a name="2378"><span class="lineNum">    2378 </span>            :     .io_in_ras_enable   (io_ctrl_ras_enable),</a>
+<a name="2379"><span class="lineNum">    2379 </span>            :     .io_out_ubtb_enable (/* unused */),</a>
+<a name="2380"><span class="lineNum">    2380 </span>            :     .io_out_btb_enable  (/* unused */),</a>
+<a name="2381"><span class="lineNum">    2381 </span>            :     .io_out_tage_enable (_tage_io_ctrl_delay_io_out_tage_enable),</a>
+<a name="2382"><span class="lineNum">    2382 </span>            :     .io_out_sc_enable   (_tage_io_ctrl_delay_io_out_sc_enable),</a>
+<a name="2383"><span class="lineNum">    2383 </span>            :     .io_out_ras_enable  (/* unused */)</a>
+<a name="2384"><span class="lineNum">    2384 </span>            :   );</a>
+<a name="2385"><span class="lineNum">    2385 </span>            :   DelayN_1 ftb_io_ctrl_delay (</a>
+<a name="2386"><span class="lineNum">    2386 </span>            :     .clock              (clock),</a>
+<a name="2387"><span class="lineNum">    2387 </span>            :     .io_in_ubtb_enable  (io_ctrl_ubtb_enable),</a>
+<a name="2388"><span class="lineNum">    2388 </span>            :     .io_in_btb_enable   (io_ctrl_btb_enable),</a>
+<a name="2389"><span class="lineNum">    2389 </span>            :     .io_in_tage_enable  (io_ctrl_tage_enable),</a>
+<a name="2390"><span class="lineNum">    2390 </span>            :     .io_in_sc_enable    (io_ctrl_sc_enable),</a>
+<a name="2391"><span class="lineNum">    2391 </span>            :     .io_in_ras_enable   (io_ctrl_ras_enable),</a>
+<a name="2392"><span class="lineNum">    2392 </span>            :     .io_out_ubtb_enable (/* unused */),</a>
+<a name="2393"><span class="lineNum">    2393 </span>            :     .io_out_btb_enable  (_ftb_io_ctrl_delay_io_out_btb_enable),</a>
+<a name="2394"><span class="lineNum">    2394 </span>            :     .io_out_tage_enable (/* unused */),</a>
+<a name="2395"><span class="lineNum">    2395 </span>            :     .io_out_sc_enable   (/* unused */),</a>
+<a name="2396"><span class="lineNum">    2396 </span>            :     .io_out_ras_enable  (/* unused */)</a>
+<a name="2397"><span class="lineNum">    2397 </span>            :   );</a>
+<a name="2398"><span class="lineNum">    2398 </span>            :   DelayN_1 ras_io_ctrl_delay (</a>
+<a name="2399"><span class="lineNum">    2399 </span>            :     .clock              (clock),</a>
+<a name="2400"><span class="lineNum">    2400 </span>            :     .io_in_ubtb_enable  (io_ctrl_ubtb_enable),</a>
+<a name="2401"><span class="lineNum">    2401 </span>            :     .io_in_btb_enable   (io_ctrl_btb_enable),</a>
+<a name="2402"><span class="lineNum">    2402 </span>            :     .io_in_tage_enable  (io_ctrl_tage_enable),</a>
+<a name="2403"><span class="lineNum">    2403 </span>            :     .io_in_sc_enable    (io_ctrl_sc_enable),</a>
+<a name="2404"><span class="lineNum">    2404 </span>            :     .io_in_ras_enable   (io_ctrl_ras_enable),</a>
+<a name="2405"><span class="lineNum">    2405 </span>            :     .io_out_ubtb_enable (/* unused */),</a>
+<a name="2406"><span class="lineNum">    2406 </span>            :     .io_out_btb_enable  (/* unused */),</a>
+<a name="2407"><span class="lineNum">    2407 </span>            :     .io_out_tage_enable (/* unused */),</a>
+<a name="2408"><span class="lineNum">    2408 </span>            :     .io_out_sc_enable   (/* unused */),</a>
+<a name="2409"><span class="lineNum">    2409 </span>            :     .io_out_ras_enable  (_ras_io_ctrl_delay_io_out_ras_enable)</a>
+<a name="2410"><span class="lineNum">    2410 </span>            :   );</a>
+<a name="2411"><span class="lineNum">    2411 </span>            :   assign io_out_last_stage_meta =</a>
+<a name="2412"><span class="lineNum">    2412 </span>            :     {_ubtb_io_out_last_stage_meta[5:0],</a>
+<a name="2413"><span class="lineNum">    2413 </span>            :      _tage_io_out_last_stage_meta[87:0],</a>
+<a name="2414"><span class="lineNum">    2414 </span>            :      _ftb_io_out_last_stage_meta[2:0],</a>
+<a name="2415"><span class="lineNum">    2415 </span>            :      _ittage_io_out_last_stage_meta[100:0],</a>
+<a name="2416"><span class="lineNum">    2416 </span>            :      _ras_io_out_last_stage_meta[24:0]};</a>
+<a name="2417"><span class="lineNum">    2417 </span>            :   assign io_s1_ready = _tage_io_s1_ready &amp; _ftb_io_s1_ready;</a>
+<a name="2418"><span class="lineNum">    2418 </span>            :   assign io_perf_0_value = io_perf_0_value_REG_1;</a>
+<a name="2419"><span class="lineNum">    2419 </span>            :   assign io_perf_1_value = io_perf_1_value_REG_1;</a>
+<a name="2420"><span class="lineNum">    2420 </span>            :   assign io_perf_2_value = io_perf_2_value_REG_1;</a>
+<a name="2421"><span class="lineNum">    2421 </span>            :   assign io_perf_3_value = io_perf_3_value_REG_1;</a>
+<a name="2422"><span class="lineNum">    2422 </span>            :   assign io_perf_4_value = io_perf_4_value_REG_1;</a>
+<a name="2423"><span class="lineNum">    2423 </span>            :   assign io_perf_5_value = io_perf_5_value_REG_1;</a>
+<a name="2424"><span class="lineNum">    2424 </span>            :   assign io_perf_6_value = io_perf_6_value_REG_1;</a>
+<a name="2425"><span class="lineNum">    2425 </span>            : endmodule</a>
+<a name="2426"><span class="lineNum">    2426 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/DelayNWithValid.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/DelayNWithValid.sv.func-sort-c.html
new file mode 100644
index 0000000..01f3541
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/DelayNWithValid.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/DelayNWithValid.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - DelayNWithValid.sv<span style="font-size: 80%;"> (<a href="DelayNWithValid.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">20</td>
+            <td class="headerCovTableEntry">20</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="DelayNWithValid.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/DelayNWithValid.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/DelayNWithValid.sv.func.html
new file mode 100644
index 0000000..a9d7178
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/DelayNWithValid.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/DelayNWithValid.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - DelayNWithValid.sv<span style="font-size: 80%;"> (<a href="DelayNWithValid.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">20</td>
+            <td class="headerCovTableEntry">20</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="DelayNWithValid.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/DelayNWithValid.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/DelayNWithValid.sv.gcov.html
new file mode 100644
index 0000000..0d0f615
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/DelayNWithValid.sv.gcov.html
@@ -0,0 +1,183 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/DelayNWithValid.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - DelayNWithValid.sv<span style="font-size: 80%;"> (source / <a href="DelayNWithValid.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">20</td>
+            <td class="headerCovTableEntry">20</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : module DelayNWithValid(</a>
+<a name="59"><span class="lineNum">      59 </span><span class="lineCov">     127786 :   input         clock,</span></a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">         62 :   input         reset,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">       1143 :   input  [40:0] io_in_bits,</span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">         57 :   input         io_in_valid,</span></a>
+<a name="63"><span class="lineNum">      63 </span><span class="lineCov">       1057 :   output [40:0] io_out_bits</span></a>
+<a name="64"><span class="lineNum">      64 </span>            : );</a>
+<a name="65"><span class="lineNum">      65 </span>            : </a>
+<a name="66"><span class="lineNum">      66 </span><span class="lineCov">         58 :   reg        valid_REG;</span></a>
+<a name="67"><span class="lineNum">      67 </span><span class="lineCov">        968 :   reg [40:0] data;</span></a>
+<a name="68"><span class="lineNum">      68 </span><span class="lineCov">       1057 :   reg [40:0] res_bits;</span></a>
+<a name="69"><span class="lineNum">      69 </span><span class="lineCov">     127730 :   always @(posedge clock or posedge reset) begin</span></a>
+<a name="70"><span class="lineNum">      70 </span><span class="lineCov">        272 :     if (reset)</span></a>
+<a name="71"><span class="lineNum">      71 </span><span class="lineCov">        136 :       valid_REG &lt;= 1'h0;</span></a>
+<a name="72"><span class="lineNum">      72 </span>            :     else</a>
+<a name="73"><span class="lineNum">      73 </span><span class="lineCov">      63729 :       valid_REG &lt;= io_in_valid;</span></a>
+<a name="74"><span class="lineNum">      74 </span>            :   end // always @(posedge, posedge)</a>
+<a name="75"><span class="lineNum">      75 </span><span class="lineCov">     127694 :   always @(posedge clock) begin</span></a>
+<a name="76"><span class="lineNum">      76 </span><span class="lineCov">         44 :     if (io_in_valid)</span></a>
+<a name="77"><span class="lineNum">      77 </span><span class="lineCov">         22 :       data &lt;= io_in_bits;</span></a>
+<a name="78"><span class="lineNum">      78 </span><span class="lineCov">         50 :     if (valid_REG)</span></a>
+<a name="79"><span class="lineNum">      79 </span><span class="lineCov">         25 :       res_bits &lt;= data;</span></a>
+<a name="80"><span class="lineNum">      80 </span>            :   end // always @(posedge)</a>
+<a name="81"><span class="lineNum">      81 </span>            :   `ifdef ENABLE_INITIAL_REG_</a>
+<a name="82"><span class="lineNum">      82 </span>            :     `ifdef FIRRTL_BEFORE_INITIAL</a>
+<a name="83"><span class="lineNum">      83 </span>            :       `FIRRTL_BEFORE_INITIAL</a>
+<a name="84"><span class="lineNum">      84 </span>            :     `endif // FIRRTL_BEFORE_INITIAL</a>
+<a name="85"><span class="lineNum">      85 </span>            :     logic [31:0] _RANDOM[0:2];</a>
+<a name="86"><span class="lineNum">      86 </span><span class="lineCov">         58 :     initial begin</span></a>
+<a name="87"><span class="lineNum">      87 </span>            :       `ifdef INIT_RANDOM_PROLOG_</a>
+<a name="88"><span class="lineNum">      88 </span>            :         `INIT_RANDOM_PROLOG_</a>
+<a name="89"><span class="lineNum">      89 </span>            :       `endif // INIT_RANDOM_PROLOG_</a>
+<a name="90"><span class="lineNum">      90 </span>            :       `ifdef RANDOMIZE_REG_INIT</a>
+<a name="91"><span class="lineNum">      91 </span>            :         for (logic [1:0] i = 2'h0; i &lt; 2'h3; i += 2'h1) begin</a>
+<a name="92"><span class="lineNum">      92 </span>            :           _RANDOM[i] = `RANDOM;</a>
+<a name="93"><span class="lineNum">      93 </span>            :         end</a>
+<a name="94"><span class="lineNum">      94 </span>            :         valid_REG = _RANDOM[2'h0][0];</a>
+<a name="95"><span class="lineNum">      95 </span>            :         data = {_RANDOM[2'h0][31:1], _RANDOM[2'h1][9:0]};</a>
+<a name="96"><span class="lineNum">      96 </span>            :         res_bits = {_RANDOM[2'h1][31:11], _RANDOM[2'h2][19:0]};</a>
+<a name="97"><span class="lineNum">      97 </span>            :       `endif // RANDOMIZE_REG_INIT</a>
+<a name="98"><span class="lineNum">      98 </span><span class="lineCov">         17 :       if (reset)</span></a>
+<a name="99"><span class="lineNum">      99 </span><span class="lineCov">         12 :         valid_REG = 1'h0;</span></a>
+<a name="100"><span class="lineNum">     100 </span>            :     end // initial</a>
+<a name="101"><span class="lineNum">     101 </span>            :     `ifdef FIRRTL_AFTER_INITIAL</a>
+<a name="102"><span class="lineNum">     102 </span>            :       `FIRRTL_AFTER_INITIAL</a>
+<a name="103"><span class="lineNum">     103 </span>            :     `endif // FIRRTL_AFTER_INITIAL</a>
+<a name="104"><span class="lineNum">     104 </span>            :   `endif // ENABLE_INITIAL_REG_</a>
+<a name="105"><span class="lineNum">     105 </span>            :   assign io_out_bits = res_bits;</a>
+<a name="106"><span class="lineNum">     106 </span>            : endmodule</a>
+<a name="107"><span class="lineNum">     107 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/DelayNWithValid_1.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/DelayNWithValid_1.sv.func-sort-c.html
new file mode 100644
index 0000000..8715af3
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/DelayNWithValid_1.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/DelayNWithValid_1.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - DelayNWithValid_1.sv<span style="font-size: 80%;"> (<a href="DelayNWithValid_1.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">128</td>
+            <td class="headerCovTableEntry">128</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="DelayNWithValid_1.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/DelayNWithValid_1.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/DelayNWithValid_1.sv.func.html
new file mode 100644
index 0000000..317c34a
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/DelayNWithValid_1.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/DelayNWithValid_1.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - DelayNWithValid_1.sv<span style="font-size: 80%;"> (<a href="DelayNWithValid_1.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">128</td>
+            <td class="headerCovTableEntry">128</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="DelayNWithValid_1.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/DelayNWithValid_1.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/DelayNWithValid_1.sv.gcov.html
new file mode 100644
index 0000000..59f2b0b
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/DelayNWithValid_1.sv.gcov.html
@@ -0,0 +1,347 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/DelayNWithValid_1.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - DelayNWithValid_1.sv<span style="font-size: 80%;"> (source / <a href="DelayNWithValid_1.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">128</td>
+            <td class="headerCovTableEntry">128</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : module DelayNWithValid_1(</a>
+<a name="59"><span class="lineNum">      59 </span><span class="lineCov">     127786 :   input         clock,</span></a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">         62 :   input         reset,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">         33 :   input         io_in_bits_valid,</span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">        122 :   input  [3:0]  io_in_bits_brSlots_0_offset,</span></a>
+<a name="63"><span class="lineNum">      63 </span><span class="lineCov">        337 :   input  [11:0] io_in_bits_brSlots_0_lower,</span></a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">         65 :   input  [1:0]  io_in_bits_brSlots_0_tarStat,</span></a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">         33 :   input         io_in_bits_brSlots_0_sharing,</span></a>
+<a name="66"><span class="lineNum">      66 </span><span class="lineCov">         35 :   input         io_in_bits_brSlots_0_valid,</span></a>
+<a name="67"><span class="lineNum">      67 </span><span class="lineCov">        137 :   input  [3:0]  io_in_bits_tailSlot_offset,</span></a>
+<a name="68"><span class="lineNum">      68 </span><span class="lineCov">        552 :   input  [19:0] io_in_bits_tailSlot_lower,</span></a>
+<a name="69"><span class="lineNum">      69 </span><span class="lineCov">         63 :   input  [1:0]  io_in_bits_tailSlot_tarStat,</span></a>
+<a name="70"><span class="lineNum">      70 </span><span class="lineCov">         33 :   input         io_in_bits_tailSlot_sharing,</span></a>
+<a name="71"><span class="lineNum">      71 </span><span class="lineCov">         28 :   input         io_in_bits_tailSlot_valid,</span></a>
+<a name="72"><span class="lineNum">      72 </span><span class="lineCov">        152 :   input  [3:0]  io_in_bits_pftAddr,</span></a>
+<a name="73"><span class="lineNum">      73 </span><span class="lineCov">         34 :   input         io_in_bits_carry,</span></a>
+<a name="74"><span class="lineNum">      74 </span><span class="lineCov">         39 :   input         io_in_bits_isCall,</span></a>
+<a name="75"><span class="lineNum">      75 </span><span class="lineCov">         36 :   input         io_in_bits_isRet,</span></a>
+<a name="76"><span class="lineNum">      76 </span><span class="lineCov">         37 :   input         io_in_bits_isJalr,</span></a>
+<a name="77"><span class="lineNum">      77 </span><span class="lineCov">         41 :   input         io_in_bits_last_may_be_rvi_call,</span></a>
+<a name="78"><span class="lineNum">      78 </span><span class="lineCov">         32 :   input         io_in_bits_always_taken_0,</span></a>
+<a name="79"><span class="lineNum">      79 </span><span class="lineCov">         33 :   input         io_in_bits_always_taken_1,</span></a>
+<a name="80"><span class="lineNum">      80 </span><span class="lineCov">         57 :   input         io_in_valid,</span></a>
+<a name="81"><span class="lineNum">      81 </span><span class="lineCov">         27 :   output        io_out_bits_valid,</span></a>
+<a name="82"><span class="lineNum">      82 </span><span class="lineCov">         90 :   output [3:0]  io_out_bits_brSlots_0_offset,</span></a>
+<a name="83"><span class="lineNum">      83 </span><span class="lineCov">        291 :   output [11:0] io_out_bits_brSlots_0_lower,</span></a>
+<a name="84"><span class="lineNum">      84 </span><span class="lineCov">         53 :   output [1:0]  io_out_bits_brSlots_0_tarStat,</span></a>
+<a name="85"><span class="lineNum">      85 </span><span class="lineCov">         26 :   output        io_out_bits_brSlots_0_sharing,</span></a>
+<a name="86"><span class="lineNum">      86 </span><span class="lineCov">         25 :   output        io_out_bits_brSlots_0_valid,</span></a>
+<a name="87"><span class="lineNum">      87 </span><span class="lineCov">         97 :   output [3:0]  io_out_bits_tailSlot_offset,</span></a>
+<a name="88"><span class="lineNum">      88 </span><span class="lineCov">        508 :   output [19:0] io_out_bits_tailSlot_lower,</span></a>
+<a name="89"><span class="lineNum">      89 </span><span class="lineCov">         42 :   output [1:0]  io_out_bits_tailSlot_tarStat,</span></a>
+<a name="90"><span class="lineNum">      90 </span><span class="lineCov">         24 :   output        io_out_bits_tailSlot_sharing,</span></a>
+<a name="91"><span class="lineNum">      91 </span><span class="lineCov">         21 :   output        io_out_bits_tailSlot_valid,</span></a>
+<a name="92"><span class="lineNum">      92 </span><span class="lineCov">        101 :   output [3:0]  io_out_bits_pftAddr,</span></a>
+<a name="93"><span class="lineNum">      93 </span><span class="lineCov">         31 :   output        io_out_bits_carry,</span></a>
+<a name="94"><span class="lineNum">      94 </span><span class="lineCov">         25 :   output        io_out_bits_isCall,</span></a>
+<a name="95"><span class="lineNum">      95 </span><span class="lineCov">         21 :   output        io_out_bits_isRet,</span></a>
+<a name="96"><span class="lineNum">      96 </span><span class="lineCov">         25 :   output        io_out_bits_isJalr,</span></a>
+<a name="97"><span class="lineNum">      97 </span><span class="lineCov">         24 :   output        io_out_bits_last_may_be_rvi_call,</span></a>
+<a name="98"><span class="lineNum">      98 </span><span class="lineCov">         21 :   output        io_out_bits_always_taken_0,</span></a>
+<a name="99"><span class="lineNum">      99 </span><span class="lineCov">         26 :   output        io_out_bits_always_taken_1</span></a>
+<a name="100"><span class="lineNum">     100 </span>            : );</a>
+<a name="101"><span class="lineNum">     101 </span>            : </a>
+<a name="102"><span class="lineNum">     102 </span><span class="lineCov">         59 :   reg        valid_REG;</span></a>
+<a name="103"><span class="lineNum">     103 </span><span class="lineCov">         30 :   reg        data_valid;</span></a>
+<a name="104"><span class="lineNum">     104 </span><span class="lineCov">         91 :   reg [3:0]  data_brSlots_0_offset;</span></a>
+<a name="105"><span class="lineNum">     105 </span><span class="lineCov">        294 :   reg [11:0] data_brSlots_0_lower;</span></a>
+<a name="106"><span class="lineNum">     106 </span><span class="lineCov">         48 :   reg [1:0]  data_brSlots_0_tarStat;</span></a>
+<a name="107"><span class="lineNum">     107 </span><span class="lineCov">         21 :   reg        data_brSlots_0_sharing;</span></a>
+<a name="108"><span class="lineNum">     108 </span><span class="lineCov">         27 :   reg        data_brSlots_0_valid;</span></a>
+<a name="109"><span class="lineNum">     109 </span><span class="lineCov">        100 :   reg [3:0]  data_tailSlot_offset;</span></a>
+<a name="110"><span class="lineNum">     110 </span><span class="lineCov">        470 :   reg [19:0] data_tailSlot_lower;</span></a>
+<a name="111"><span class="lineNum">     111 </span><span class="lineCov">         43 :   reg [1:0]  data_tailSlot_tarStat;</span></a>
+<a name="112"><span class="lineNum">     112 </span><span class="lineCov">         20 :   reg        data_tailSlot_sharing;</span></a>
+<a name="113"><span class="lineNum">     113 </span><span class="lineCov">         26 :   reg        data_tailSlot_valid;</span></a>
+<a name="114"><span class="lineNum">     114 </span><span class="lineCov">         87 :   reg [3:0]  data_pftAddr;</span></a>
+<a name="115"><span class="lineNum">     115 </span><span class="lineCov">         24 :   reg        data_carry;</span></a>
+<a name="116"><span class="lineNum">     116 </span><span class="lineCov">         25 :   reg        data_isCall;</span></a>
+<a name="117"><span class="lineNum">     117 </span><span class="lineCov">         13 :   reg        data_isRet;</span></a>
+<a name="118"><span class="lineNum">     118 </span><span class="lineCov">         24 :   reg        data_isJalr;</span></a>
+<a name="119"><span class="lineNum">     119 </span><span class="lineCov">         23 :   reg        data_last_may_be_rvi_call;</span></a>
+<a name="120"><span class="lineNum">     120 </span><span class="lineCov">         22 :   reg        data_always_taken_0;</span></a>
+<a name="121"><span class="lineNum">     121 </span><span class="lineCov">         24 :   reg        data_always_taken_1;</span></a>
+<a name="122"><span class="lineNum">     122 </span><span class="lineCov">         27 :   reg        res_bits_valid;</span></a>
+<a name="123"><span class="lineNum">     123 </span><span class="lineCov">         90 :   reg [3:0]  res_bits_brSlots_0_offset;</span></a>
+<a name="124"><span class="lineNum">     124 </span><span class="lineCov">        291 :   reg [11:0] res_bits_brSlots_0_lower;</span></a>
+<a name="125"><span class="lineNum">     125 </span><span class="lineCov">         53 :   reg [1:0]  res_bits_brSlots_0_tarStat;</span></a>
+<a name="126"><span class="lineNum">     126 </span><span class="lineCov">         26 :   reg        res_bits_brSlots_0_sharing;</span></a>
+<a name="127"><span class="lineNum">     127 </span><span class="lineCov">         25 :   reg        res_bits_brSlots_0_valid;</span></a>
+<a name="128"><span class="lineNum">     128 </span><span class="lineCov">         97 :   reg [3:0]  res_bits_tailSlot_offset;</span></a>
+<a name="129"><span class="lineNum">     129 </span><span class="lineCov">        508 :   reg [19:0] res_bits_tailSlot_lower;</span></a>
+<a name="130"><span class="lineNum">     130 </span><span class="lineCov">         42 :   reg [1:0]  res_bits_tailSlot_tarStat;</span></a>
+<a name="131"><span class="lineNum">     131 </span><span class="lineCov">         24 :   reg        res_bits_tailSlot_sharing;</span></a>
+<a name="132"><span class="lineNum">     132 </span><span class="lineCov">         21 :   reg        res_bits_tailSlot_valid;</span></a>
+<a name="133"><span class="lineNum">     133 </span><span class="lineCov">        101 :   reg [3:0]  res_bits_pftAddr;</span></a>
+<a name="134"><span class="lineNum">     134 </span><span class="lineCov">         31 :   reg        res_bits_carry;</span></a>
+<a name="135"><span class="lineNum">     135 </span><span class="lineCov">         25 :   reg        res_bits_isCall;</span></a>
+<a name="136"><span class="lineNum">     136 </span><span class="lineCov">         21 :   reg        res_bits_isRet;</span></a>
+<a name="137"><span class="lineNum">     137 </span><span class="lineCov">         25 :   reg        res_bits_isJalr;</span></a>
+<a name="138"><span class="lineNum">     138 </span><span class="lineCov">         24 :   reg        res_bits_last_may_be_rvi_call;</span></a>
+<a name="139"><span class="lineNum">     139 </span><span class="lineCov">         21 :   reg        res_bits_always_taken_0;</span></a>
+<a name="140"><span class="lineNum">     140 </span><span class="lineCov">         26 :   reg        res_bits_always_taken_1;</span></a>
+<a name="141"><span class="lineNum">     141 </span><span class="lineCov">     127730 :   always @(posedge clock or posedge reset) begin</span></a>
+<a name="142"><span class="lineNum">     142 </span><span class="lineCov">        272 :     if (reset)</span></a>
+<a name="143"><span class="lineNum">     143 </span><span class="lineCov">        136 :       valid_REG &lt;= 1'h0;</span></a>
+<a name="144"><span class="lineNum">     144 </span>            :     else</a>
+<a name="145"><span class="lineNum">     145 </span><span class="lineCov">      63729 :       valid_REG &lt;= io_in_valid;</span></a>
+<a name="146"><span class="lineNum">     146 </span>            :   end // always @(posedge, posedge)</a>
+<a name="147"><span class="lineNum">     147 </span><span class="lineCov">     127694 :   always @(posedge clock) begin</span></a>
+<a name="148"><span class="lineNum">     148 </span><span class="lineCov">         44 :     if (io_in_valid) begin</span></a>
+<a name="149"><span class="lineNum">     149 </span><span class="lineCov">         22 :       data_valid &lt;= io_in_bits_valid;</span></a>
+<a name="150"><span class="lineNum">     150 </span><span class="lineCov">         22 :       data_brSlots_0_offset &lt;= io_in_bits_brSlots_0_offset;</span></a>
+<a name="151"><span class="lineNum">     151 </span><span class="lineCov">         22 :       data_brSlots_0_lower &lt;= io_in_bits_brSlots_0_lower;</span></a>
+<a name="152"><span class="lineNum">     152 </span><span class="lineCov">         22 :       data_brSlots_0_tarStat &lt;= io_in_bits_brSlots_0_tarStat;</span></a>
+<a name="153"><span class="lineNum">     153 </span><span class="lineCov">         22 :       data_brSlots_0_sharing &lt;= io_in_bits_brSlots_0_sharing;</span></a>
+<a name="154"><span class="lineNum">     154 </span><span class="lineCov">         22 :       data_brSlots_0_valid &lt;= io_in_bits_brSlots_0_valid;</span></a>
+<a name="155"><span class="lineNum">     155 </span><span class="lineCov">         22 :       data_tailSlot_offset &lt;= io_in_bits_tailSlot_offset;</span></a>
+<a name="156"><span class="lineNum">     156 </span><span class="lineCov">         22 :       data_tailSlot_lower &lt;= io_in_bits_tailSlot_lower;</span></a>
+<a name="157"><span class="lineNum">     157 </span><span class="lineCov">         22 :       data_tailSlot_tarStat &lt;= io_in_bits_tailSlot_tarStat;</span></a>
+<a name="158"><span class="lineNum">     158 </span><span class="lineCov">         22 :       data_tailSlot_sharing &lt;= io_in_bits_tailSlot_sharing;</span></a>
+<a name="159"><span class="lineNum">     159 </span><span class="lineCov">         22 :       data_tailSlot_valid &lt;= io_in_bits_tailSlot_valid;</span></a>
+<a name="160"><span class="lineNum">     160 </span><span class="lineCov">         22 :       data_pftAddr &lt;= io_in_bits_pftAddr;</span></a>
+<a name="161"><span class="lineNum">     161 </span><span class="lineCov">         22 :       data_carry &lt;= io_in_bits_carry;</span></a>
+<a name="162"><span class="lineNum">     162 </span><span class="lineCov">         22 :       data_isCall &lt;= io_in_bits_isCall;</span></a>
+<a name="163"><span class="lineNum">     163 </span><span class="lineCov">         22 :       data_isRet &lt;= io_in_bits_isRet;</span></a>
+<a name="164"><span class="lineNum">     164 </span><span class="lineCov">         22 :       data_isJalr &lt;= io_in_bits_isJalr;</span></a>
+<a name="165"><span class="lineNum">     165 </span><span class="lineCov">         22 :       data_last_may_be_rvi_call &lt;= io_in_bits_last_may_be_rvi_call;</span></a>
+<a name="166"><span class="lineNum">     166 </span><span class="lineCov">         22 :       data_always_taken_0 &lt;= io_in_bits_always_taken_0;</span></a>
+<a name="167"><span class="lineNum">     167 </span><span class="lineCov">         22 :       data_always_taken_1 &lt;= io_in_bits_always_taken_1;</span></a>
+<a name="168"><span class="lineNum">     168 </span>            :     end</a>
+<a name="169"><span class="lineNum">     169 </span><span class="lineCov">         50 :     if (valid_REG) begin</span></a>
+<a name="170"><span class="lineNum">     170 </span><span class="lineCov">         25 :       res_bits_valid &lt;= data_valid;</span></a>
+<a name="171"><span class="lineNum">     171 </span><span class="lineCov">         25 :       res_bits_brSlots_0_offset &lt;= data_brSlots_0_offset;</span></a>
+<a name="172"><span class="lineNum">     172 </span><span class="lineCov">         25 :       res_bits_brSlots_0_lower &lt;= data_brSlots_0_lower;</span></a>
+<a name="173"><span class="lineNum">     173 </span><span class="lineCov">         25 :       res_bits_brSlots_0_tarStat &lt;= data_brSlots_0_tarStat;</span></a>
+<a name="174"><span class="lineNum">     174 </span><span class="lineCov">         25 :       res_bits_brSlots_0_sharing &lt;= data_brSlots_0_sharing;</span></a>
+<a name="175"><span class="lineNum">     175 </span><span class="lineCov">         25 :       res_bits_brSlots_0_valid &lt;= data_brSlots_0_valid;</span></a>
+<a name="176"><span class="lineNum">     176 </span><span class="lineCov">         25 :       res_bits_tailSlot_offset &lt;= data_tailSlot_offset;</span></a>
+<a name="177"><span class="lineNum">     177 </span><span class="lineCov">         25 :       res_bits_tailSlot_lower &lt;= data_tailSlot_lower;</span></a>
+<a name="178"><span class="lineNum">     178 </span><span class="lineCov">         25 :       res_bits_tailSlot_tarStat &lt;= data_tailSlot_tarStat;</span></a>
+<a name="179"><span class="lineNum">     179 </span><span class="lineCov">         25 :       res_bits_tailSlot_sharing &lt;= data_tailSlot_sharing;</span></a>
+<a name="180"><span class="lineNum">     180 </span><span class="lineCov">         25 :       res_bits_tailSlot_valid &lt;= data_tailSlot_valid;</span></a>
+<a name="181"><span class="lineNum">     181 </span><span class="lineCov">         25 :       res_bits_pftAddr &lt;= data_pftAddr;</span></a>
+<a name="182"><span class="lineNum">     182 </span><span class="lineCov">         25 :       res_bits_carry &lt;= data_carry;</span></a>
+<a name="183"><span class="lineNum">     183 </span><span class="lineCov">         25 :       res_bits_isCall &lt;= data_isCall;</span></a>
+<a name="184"><span class="lineNum">     184 </span><span class="lineCov">         25 :       res_bits_isRet &lt;= data_isRet;</span></a>
+<a name="185"><span class="lineNum">     185 </span><span class="lineCov">         25 :       res_bits_isJalr &lt;= data_isJalr;</span></a>
+<a name="186"><span class="lineNum">     186 </span><span class="lineCov">         25 :       res_bits_last_may_be_rvi_call &lt;= data_last_may_be_rvi_call;</span></a>
+<a name="187"><span class="lineNum">     187 </span><span class="lineCov">         25 :       res_bits_always_taken_0 &lt;= data_always_taken_0;</span></a>
+<a name="188"><span class="lineNum">     188 </span><span class="lineCov">         25 :       res_bits_always_taken_1 &lt;= data_always_taken_1;</span></a>
+<a name="189"><span class="lineNum">     189 </span>            :     end</a>
+<a name="190"><span class="lineNum">     190 </span>            :   end // always @(posedge)</a>
+<a name="191"><span class="lineNum">     191 </span>            :   `ifdef ENABLE_INITIAL_REG_</a>
+<a name="192"><span class="lineNum">     192 </span>            :     `ifdef FIRRTL_BEFORE_INITIAL</a>
+<a name="193"><span class="lineNum">     193 </span>            :       `FIRRTL_BEFORE_INITIAL</a>
+<a name="194"><span class="lineNum">     194 </span>            :     `endif // FIRRTL_BEFORE_INITIAL</a>
+<a name="195"><span class="lineNum">     195 </span>            :     logic [31:0] _RANDOM[0:3];</a>
+<a name="196"><span class="lineNum">     196 </span><span class="lineCov">         58 :     initial begin</span></a>
+<a name="197"><span class="lineNum">     197 </span>            :       `ifdef INIT_RANDOM_PROLOG_</a>
+<a name="198"><span class="lineNum">     198 </span>            :         `INIT_RANDOM_PROLOG_</a>
+<a name="199"><span class="lineNum">     199 </span>            :       `endif // INIT_RANDOM_PROLOG_</a>
+<a name="200"><span class="lineNum">     200 </span>            :       `ifdef RANDOMIZE_REG_INIT</a>
+<a name="201"><span class="lineNum">     201 </span>            :         for (logic [2:0] i = 3'h0; i &lt; 3'h4; i += 3'h1) begin</a>
+<a name="202"><span class="lineNum">     202 </span>            :           _RANDOM[i[1:0]] = `RANDOM;</a>
+<a name="203"><span class="lineNum">     203 </span>            :         end</a>
+<a name="204"><span class="lineNum">     204 </span>            :         valid_REG = _RANDOM[2'h0][0];</a>
+<a name="205"><span class="lineNum">     205 </span>            :         data_valid = _RANDOM[2'h0][1];</a>
+<a name="206"><span class="lineNum">     206 </span>            :         data_brSlots_0_offset = _RANDOM[2'h0][5:2];</a>
+<a name="207"><span class="lineNum">     207 </span>            :         data_brSlots_0_lower = _RANDOM[2'h0][17:6];</a>
+<a name="208"><span class="lineNum">     208 </span>            :         data_brSlots_0_tarStat = _RANDOM[2'h0][19:18];</a>
+<a name="209"><span class="lineNum">     209 </span>            :         data_brSlots_0_sharing = _RANDOM[2'h0][20];</a>
+<a name="210"><span class="lineNum">     210 </span>            :         data_brSlots_0_valid = _RANDOM[2'h0][21];</a>
+<a name="211"><span class="lineNum">     211 </span>            :         data_tailSlot_offset = _RANDOM[2'h0][25:22];</a>
+<a name="212"><span class="lineNum">     212 </span>            :         data_tailSlot_lower = {_RANDOM[2'h0][31:26], _RANDOM[2'h1][13:0]};</a>
+<a name="213"><span class="lineNum">     213 </span>            :         data_tailSlot_tarStat = _RANDOM[2'h1][15:14];</a>
+<a name="214"><span class="lineNum">     214 </span>            :         data_tailSlot_sharing = _RANDOM[2'h1][16];</a>
+<a name="215"><span class="lineNum">     215 </span>            :         data_tailSlot_valid = _RANDOM[2'h1][17];</a>
+<a name="216"><span class="lineNum">     216 </span>            :         data_pftAddr = _RANDOM[2'h1][21:18];</a>
+<a name="217"><span class="lineNum">     217 </span>            :         data_carry = _RANDOM[2'h1][22];</a>
+<a name="218"><span class="lineNum">     218 </span>            :         data_isCall = _RANDOM[2'h1][23];</a>
+<a name="219"><span class="lineNum">     219 </span>            :         data_isRet = _RANDOM[2'h1][24];</a>
+<a name="220"><span class="lineNum">     220 </span>            :         data_isJalr = _RANDOM[2'h1][25];</a>
+<a name="221"><span class="lineNum">     221 </span>            :         data_last_may_be_rvi_call = _RANDOM[2'h1][26];</a>
+<a name="222"><span class="lineNum">     222 </span>            :         data_always_taken_0 = _RANDOM[2'h1][27];</a>
+<a name="223"><span class="lineNum">     223 </span>            :         data_always_taken_1 = _RANDOM[2'h1][28];</a>
+<a name="224"><span class="lineNum">     224 </span>            :         res_bits_valid = _RANDOM[2'h1][30];</a>
+<a name="225"><span class="lineNum">     225 </span>            :         res_bits_brSlots_0_offset = {_RANDOM[2'h1][31], _RANDOM[2'h2][2:0]};</a>
+<a name="226"><span class="lineNum">     226 </span>            :         res_bits_brSlots_0_lower = _RANDOM[2'h2][14:3];</a>
+<a name="227"><span class="lineNum">     227 </span>            :         res_bits_brSlots_0_tarStat = _RANDOM[2'h2][16:15];</a>
+<a name="228"><span class="lineNum">     228 </span>            :         res_bits_brSlots_0_sharing = _RANDOM[2'h2][17];</a>
+<a name="229"><span class="lineNum">     229 </span>            :         res_bits_brSlots_0_valid = _RANDOM[2'h2][18];</a>
+<a name="230"><span class="lineNum">     230 </span>            :         res_bits_tailSlot_offset = _RANDOM[2'h2][22:19];</a>
+<a name="231"><span class="lineNum">     231 </span>            :         res_bits_tailSlot_lower = {_RANDOM[2'h2][31:23], _RANDOM[2'h3][10:0]};</a>
+<a name="232"><span class="lineNum">     232 </span>            :         res_bits_tailSlot_tarStat = _RANDOM[2'h3][12:11];</a>
+<a name="233"><span class="lineNum">     233 </span>            :         res_bits_tailSlot_sharing = _RANDOM[2'h3][13];</a>
+<a name="234"><span class="lineNum">     234 </span>            :         res_bits_tailSlot_valid = _RANDOM[2'h3][14];</a>
+<a name="235"><span class="lineNum">     235 </span>            :         res_bits_pftAddr = _RANDOM[2'h3][18:15];</a>
+<a name="236"><span class="lineNum">     236 </span>            :         res_bits_carry = _RANDOM[2'h3][19];</a>
+<a name="237"><span class="lineNum">     237 </span>            :         res_bits_isCall = _RANDOM[2'h3][20];</a>
+<a name="238"><span class="lineNum">     238 </span>            :         res_bits_isRet = _RANDOM[2'h3][21];</a>
+<a name="239"><span class="lineNum">     239 </span>            :         res_bits_isJalr = _RANDOM[2'h3][22];</a>
+<a name="240"><span class="lineNum">     240 </span>            :         res_bits_last_may_be_rvi_call = _RANDOM[2'h3][23];</a>
+<a name="241"><span class="lineNum">     241 </span>            :         res_bits_always_taken_0 = _RANDOM[2'h3][24];</a>
+<a name="242"><span class="lineNum">     242 </span>            :         res_bits_always_taken_1 = _RANDOM[2'h3][25];</a>
+<a name="243"><span class="lineNum">     243 </span>            :       `endif // RANDOMIZE_REG_INIT</a>
+<a name="244"><span class="lineNum">     244 </span><span class="lineCov">         17 :       if (reset)</span></a>
+<a name="245"><span class="lineNum">     245 </span><span class="lineCov">         12 :         valid_REG = 1'h0;</span></a>
+<a name="246"><span class="lineNum">     246 </span>            :     end // initial</a>
+<a name="247"><span class="lineNum">     247 </span>            :     `ifdef FIRRTL_AFTER_INITIAL</a>
+<a name="248"><span class="lineNum">     248 </span>            :       `FIRRTL_AFTER_INITIAL</a>
+<a name="249"><span class="lineNum">     249 </span>            :     `endif // FIRRTL_AFTER_INITIAL</a>
+<a name="250"><span class="lineNum">     250 </span>            :   `endif // ENABLE_INITIAL_REG_</a>
+<a name="251"><span class="lineNum">     251 </span>            :   assign io_out_bits_valid = res_bits_valid;</a>
+<a name="252"><span class="lineNum">     252 </span>            :   assign io_out_bits_brSlots_0_offset = res_bits_brSlots_0_offset;</a>
+<a name="253"><span class="lineNum">     253 </span>            :   assign io_out_bits_brSlots_0_lower = res_bits_brSlots_0_lower;</a>
+<a name="254"><span class="lineNum">     254 </span>            :   assign io_out_bits_brSlots_0_tarStat = res_bits_brSlots_0_tarStat;</a>
+<a name="255"><span class="lineNum">     255 </span>            :   assign io_out_bits_brSlots_0_sharing = res_bits_brSlots_0_sharing;</a>
+<a name="256"><span class="lineNum">     256 </span>            :   assign io_out_bits_brSlots_0_valid = res_bits_brSlots_0_valid;</a>
+<a name="257"><span class="lineNum">     257 </span>            :   assign io_out_bits_tailSlot_offset = res_bits_tailSlot_offset;</a>
+<a name="258"><span class="lineNum">     258 </span>            :   assign io_out_bits_tailSlot_lower = res_bits_tailSlot_lower;</a>
+<a name="259"><span class="lineNum">     259 </span>            :   assign io_out_bits_tailSlot_tarStat = res_bits_tailSlot_tarStat;</a>
+<a name="260"><span class="lineNum">     260 </span>            :   assign io_out_bits_tailSlot_sharing = res_bits_tailSlot_sharing;</a>
+<a name="261"><span class="lineNum">     261 </span>            :   assign io_out_bits_tailSlot_valid = res_bits_tailSlot_valid;</a>
+<a name="262"><span class="lineNum">     262 </span>            :   assign io_out_bits_pftAddr = res_bits_pftAddr;</a>
+<a name="263"><span class="lineNum">     263 </span>            :   assign io_out_bits_carry = res_bits_carry;</a>
+<a name="264"><span class="lineNum">     264 </span>            :   assign io_out_bits_isCall = res_bits_isCall;</a>
+<a name="265"><span class="lineNum">     265 </span>            :   assign io_out_bits_isRet = res_bits_isRet;</a>
+<a name="266"><span class="lineNum">     266 </span>            :   assign io_out_bits_isJalr = res_bits_isJalr;</a>
+<a name="267"><span class="lineNum">     267 </span>            :   assign io_out_bits_last_may_be_rvi_call = res_bits_last_may_be_rvi_call;</a>
+<a name="268"><span class="lineNum">     268 </span>            :   assign io_out_bits_always_taken_0 = res_bits_always_taken_0;</a>
+<a name="269"><span class="lineNum">     269 </span>            :   assign io_out_bits_always_taken_1 = res_bits_always_taken_1;</a>
+<a name="270"><span class="lineNum">     270 </span>            : endmodule</a>
+<a name="271"><span class="lineNum">     271 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/DelayN_1.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/DelayN_1.sv.func-sort-c.html
new file mode 100644
index 0000000..ccba7de
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/DelayN_1.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/DelayN_1.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - DelayN_1.sv<span style="font-size: 80%;"> (<a href="DelayN_1.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">23</td>
+            <td class="headerCovTableEntry">23</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="DelayN_1.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/DelayN_1.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/DelayN_1.sv.func.html
new file mode 100644
index 0000000..a8ae44d
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/DelayN_1.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/DelayN_1.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - DelayN_1.sv<span style="font-size: 80%;"> (<a href="DelayN_1.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">23</td>
+            <td class="headerCovTableEntry">23</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="DelayN_1.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/DelayN_1.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/DelayN_1.sv.gcov.html
new file mode 100644
index 0000000..f97fc63
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/DelayN_1.sv.gcov.html
@@ -0,0 +1,188 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/DelayN_1.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - DelayN_1.sv<span style="font-size: 80%;"> (source / <a href="DelayN_1.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">23</td>
+            <td class="headerCovTableEntry">23</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : module DelayN_1(</a>
+<a name="59"><span class="lineNum">      59 </span><span class="lineCov">     638930 :   input  clock,</span></a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">        325 :   input  io_in_ubtb_enable,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">        315 :   input  io_in_btb_enable,</span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">        307 :   input  io_in_tage_enable,</span></a>
+<a name="63"><span class="lineNum">      63 </span><span class="lineCov">        356 :   input  io_in_sc_enable,</span></a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">        328 :   input  io_in_ras_enable,</span></a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">        386 :   output io_out_ubtb_enable,</span></a>
+<a name="66"><span class="lineNum">      66 </span><span class="lineCov">        398 :   output io_out_btb_enable,</span></a>
+<a name="67"><span class="lineNum">      67 </span><span class="lineCov">        378 :   output io_out_tage_enable,</span></a>
+<a name="68"><span class="lineNum">      68 </span><span class="lineCov">        422 :   output io_out_sc_enable,</span></a>
+<a name="69"><span class="lineNum">      69 </span><span class="lineCov">        412 :   output io_out_ras_enable</span></a>
+<a name="70"><span class="lineNum">      70 </span>            : );</a>
+<a name="71"><span class="lineNum">      71 </span>            : </a>
+<a name="72"><span class="lineNum">      72 </span><span class="lineCov">        386 :   reg REG_ubtb_enable;</span></a>
+<a name="73"><span class="lineNum">      73 </span><span class="lineCov">        398 :   reg REG_btb_enable;</span></a>
+<a name="74"><span class="lineNum">      74 </span><span class="lineCov">        378 :   reg REG_tage_enable;</span></a>
+<a name="75"><span class="lineNum">      75 </span><span class="lineCov">        422 :   reg REG_sc_enable;</span></a>
+<a name="76"><span class="lineNum">      76 </span><span class="lineCov">        412 :   reg REG_ras_enable;</span></a>
+<a name="77"><span class="lineNum">      77 </span><span class="lineCov">     638470 :   always @(posedge clock) begin</span></a>
+<a name="78"><span class="lineNum">      78 </span><span class="lineCov">     319235 :     REG_ubtb_enable &lt;= io_in_ubtb_enable;</span></a>
+<a name="79"><span class="lineNum">      79 </span><span class="lineCov">     319235 :     REG_btb_enable &lt;= io_in_btb_enable;</span></a>
+<a name="80"><span class="lineNum">      80 </span><span class="lineCov">     319235 :     REG_tage_enable &lt;= io_in_tage_enable;</span></a>
+<a name="81"><span class="lineNum">      81 </span><span class="lineCov">     319235 :     REG_sc_enable &lt;= io_in_sc_enable;</span></a>
+<a name="82"><span class="lineNum">      82 </span><span class="lineCov">     319235 :     REG_ras_enable &lt;= io_in_ras_enable;</span></a>
+<a name="83"><span class="lineNum">      83 </span>            :   end // always @(posedge)</a>
+<a name="84"><span class="lineNum">      84 </span>            :   `ifdef ENABLE_INITIAL_REG_</a>
+<a name="85"><span class="lineNum">      85 </span>            :     `ifdef FIRRTL_BEFORE_INITIAL</a>
+<a name="86"><span class="lineNum">      86 </span>            :       `FIRRTL_BEFORE_INITIAL</a>
+<a name="87"><span class="lineNum">      87 </span>            :     `endif // FIRRTL_BEFORE_INITIAL</a>
+<a name="88"><span class="lineNum">      88 </span>            :     logic [31:0] _RANDOM[0:0];</a>
+<a name="89"><span class="lineNum">      89 </span><span class="lineCov">        290 :     initial begin</span></a>
+<a name="90"><span class="lineNum">      90 </span>            :       `ifdef INIT_RANDOM_PROLOG_</a>
+<a name="91"><span class="lineNum">      91 </span>            :         `INIT_RANDOM_PROLOG_</a>
+<a name="92"><span class="lineNum">      92 </span>            :       `endif // INIT_RANDOM_PROLOG_</a>
+<a name="93"><span class="lineNum">      93 </span>            :       `ifdef RANDOMIZE_REG_INIT</a>
+<a name="94"><span class="lineNum">      94 </span>            :         _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;</a>
+<a name="95"><span class="lineNum">      95 </span>            :         REG_ubtb_enable = _RANDOM[/*Zero width*/ 1'b0][0];</a>
+<a name="96"><span class="lineNum">      96 </span>            :         REG_btb_enable = _RANDOM[/*Zero width*/ 1'b0][1];</a>
+<a name="97"><span class="lineNum">      97 </span>            :         REG_tage_enable = _RANDOM[/*Zero width*/ 1'b0][3];</a>
+<a name="98"><span class="lineNum">      98 </span>            :         REG_sc_enable = _RANDOM[/*Zero width*/ 1'b0][4];</a>
+<a name="99"><span class="lineNum">      99 </span>            :         REG_ras_enable = _RANDOM[/*Zero width*/ 1'b0][5];</a>
+<a name="100"><span class="lineNum">     100 </span>            :       `endif // RANDOMIZE_REG_INIT</a>
+<a name="101"><span class="lineNum">     101 </span>            :     end // initial</a>
+<a name="102"><span class="lineNum">     102 </span>            :     `ifdef FIRRTL_AFTER_INITIAL</a>
+<a name="103"><span class="lineNum">     103 </span>            :       `FIRRTL_AFTER_INITIAL</a>
+<a name="104"><span class="lineNum">     104 </span>            :     `endif // FIRRTL_AFTER_INITIAL</a>
+<a name="105"><span class="lineNum">     105 </span>            :   `endif // ENABLE_INITIAL_REG_</a>
+<a name="106"><span class="lineNum">     106 </span>            :   assign io_out_ubtb_enable = REG_ubtb_enable;</a>
+<a name="107"><span class="lineNum">     107 </span>            :   assign io_out_btb_enable = REG_btb_enable;</a>
+<a name="108"><span class="lineNum">     108 </span>            :   assign io_out_tage_enable = REG_tage_enable;</a>
+<a name="109"><span class="lineNum">     109 </span>            :   assign io_out_sc_enable = REG_sc_enable;</a>
+<a name="110"><span class="lineNum">     110 </span>            :   assign io_out_ras_enable = REG_ras_enable;</a>
+<a name="111"><span class="lineNum">     111 </span>            : endmodule</a>
+<a name="112"><span class="lineNum">     112 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/DelayN_2.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/DelayN_2.sv.func-sort-c.html
new file mode 100644
index 0000000..0031439
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/DelayN_2.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/DelayN_2.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - DelayN_2.sv<span style="font-size: 80%;"> (<a href="DelayN_2.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">15</td>
+            <td class="headerCovTableEntry">15</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="DelayN_2.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/DelayN_2.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/DelayN_2.sv.func.html
new file mode 100644
index 0000000..c6ec7b6
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/DelayN_2.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/DelayN_2.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - DelayN_2.sv<span style="font-size: 80%;"> (<a href="DelayN_2.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">15</td>
+            <td class="headerCovTableEntry">15</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="DelayN_2.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/DelayN_2.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/DelayN_2.sv.gcov.html
new file mode 100644
index 0000000..36b80d1
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/DelayN_2.sv.gcov.html
@@ -0,0 +1,178 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/DelayN_2.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - DelayN_2.sv<span style="font-size: 80%;"> (source / <a href="DelayN_2.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">15</td>
+            <td class="headerCovTableEntry">15</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : module DelayN_2(</a>
+<a name="59"><span class="lineNum">      59 </span><span class="lineCov">     127786 :   input         clock,</span></a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">       1105 :   input  [35:0] io_in,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">      18419 :   output [35:0] io_out</span></a>
+<a name="62"><span class="lineNum">      62 </span>            : );</a>
+<a name="63"><span class="lineNum">      63 </span>            : </a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">       8059 :   reg [35:0] REG;</span></a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">      10571 :   reg [35:0] REG_1;</span></a>
+<a name="66"><span class="lineNum">      66 </span><span class="lineCov">      13265 :   reg [35:0] REG_2;</span></a>
+<a name="67"><span class="lineNum">      67 </span><span class="lineCov">      15817 :   reg [35:0] REG_3;</span></a>
+<a name="68"><span class="lineNum">      68 </span><span class="lineCov">      18419 :   reg [35:0] REG_4;</span></a>
+<a name="69"><span class="lineNum">      69 </span><span class="lineCov">     638470 :   always @(posedge clock) begin</span></a>
+<a name="70"><span class="lineNum">      70 </span><span class="lineCov">     319235 :     REG &lt;= io_in;</span></a>
+<a name="71"><span class="lineNum">      71 </span><span class="lineCov">     319235 :     REG_1 &lt;= REG;</span></a>
+<a name="72"><span class="lineNum">      72 </span><span class="lineCov">     319235 :     REG_2 &lt;= REG_1;</span></a>
+<a name="73"><span class="lineNum">      73 </span><span class="lineCov">     319235 :     REG_3 &lt;= REG_2;</span></a>
+<a name="74"><span class="lineNum">      74 </span><span class="lineCov">     319235 :     REG_4 &lt;= REG_3;</span></a>
+<a name="75"><span class="lineNum">      75 </span>            :   end // always @(posedge)</a>
+<a name="76"><span class="lineNum">      76 </span>            :   `ifdef ENABLE_INITIAL_REG_</a>
+<a name="77"><span class="lineNum">      77 </span>            :     `ifdef FIRRTL_BEFORE_INITIAL</a>
+<a name="78"><span class="lineNum">      78 </span>            :       `FIRRTL_BEFORE_INITIAL</a>
+<a name="79"><span class="lineNum">      79 </span>            :     `endif // FIRRTL_BEFORE_INITIAL</a>
+<a name="80"><span class="lineNum">      80 </span>            :     logic [31:0] _RANDOM[0:5];</a>
+<a name="81"><span class="lineNum">      81 </span><span class="lineCov">        290 :     initial begin</span></a>
+<a name="82"><span class="lineNum">      82 </span>            :       `ifdef INIT_RANDOM_PROLOG_</a>
+<a name="83"><span class="lineNum">      83 </span>            :         `INIT_RANDOM_PROLOG_</a>
+<a name="84"><span class="lineNum">      84 </span>            :       `endif // INIT_RANDOM_PROLOG_</a>
+<a name="85"><span class="lineNum">      85 </span>            :       `ifdef RANDOMIZE_REG_INIT</a>
+<a name="86"><span class="lineNum">      86 </span>            :         for (logic [2:0] i = 3'h0; i &lt; 3'h6; i += 3'h1) begin</a>
+<a name="87"><span class="lineNum">      87 </span>            :           _RANDOM[i] = `RANDOM;</a>
+<a name="88"><span class="lineNum">      88 </span>            :         end</a>
+<a name="89"><span class="lineNum">      89 </span>            :         REG = {_RANDOM[3'h0], _RANDOM[3'h1][3:0]};</a>
+<a name="90"><span class="lineNum">      90 </span>            :         REG_1 = {_RANDOM[3'h1][31:4], _RANDOM[3'h2][7:0]};</a>
+<a name="91"><span class="lineNum">      91 </span>            :         REG_2 = {_RANDOM[3'h2][31:8], _RANDOM[3'h3][11:0]};</a>
+<a name="92"><span class="lineNum">      92 </span>            :         REG_3 = {_RANDOM[3'h3][31:12], _RANDOM[3'h4][15:0]};</a>
+<a name="93"><span class="lineNum">      93 </span>            :         REG_4 = {_RANDOM[3'h4][31:16], _RANDOM[3'h5][19:0]};</a>
+<a name="94"><span class="lineNum">      94 </span>            :       `endif // RANDOMIZE_REG_INIT</a>
+<a name="95"><span class="lineNum">      95 </span>            :     end // initial</a>
+<a name="96"><span class="lineNum">      96 </span>            :     `ifdef FIRRTL_AFTER_INITIAL</a>
+<a name="97"><span class="lineNum">      97 </span>            :       `FIRRTL_AFTER_INITIAL</a>
+<a name="98"><span class="lineNum">      98 </span>            :     `endif // FIRRTL_AFTER_INITIAL</a>
+<a name="99"><span class="lineNum">      99 </span>            :   `endif // ENABLE_INITIAL_REG_</a>
+<a name="100"><span class="lineNum">     100 </span>            :   assign io_out = REG_4;</a>
+<a name="101"><span class="lineNum">     101 </span>            : endmodule</a>
+<a name="102"><span class="lineNum">     102 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/DelayN_4.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/DelayN_4.sv.func-sort-c.html
new file mode 100644
index 0000000..5642ca0
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/DelayN_4.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/DelayN_4.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - DelayN_4.sv<span style="font-size: 80%;"> (<a href="DelayN_4.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">9</td>
+            <td class="headerCovTableEntry">9</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="DelayN_4.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/DelayN_4.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/DelayN_4.sv.func.html
new file mode 100644
index 0000000..359188a
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/DelayN_4.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/DelayN_4.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - DelayN_4.sv<span style="font-size: 80%;"> (<a href="DelayN_4.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">9</td>
+            <td class="headerCovTableEntry">9</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="DelayN_4.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/DelayN_4.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/DelayN_4.sv.gcov.html
new file mode 100644
index 0000000..ef0c657
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/DelayN_4.sv.gcov.html
@@ -0,0 +1,167 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/DelayN_4.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - DelayN_4.sv<span style="font-size: 80%;"> (source / <a href="DelayN_4.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">9</td>
+            <td class="headerCovTableEntry">9</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : module DelayN_4(</a>
+<a name="59"><span class="lineNum">      59 </span><span class="lineCov">     127786 :   input  clock,</span></a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">         50 :   input  io_in,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">         72 :   output io_out</span></a>
+<a name="62"><span class="lineNum">      62 </span>            : );</a>
+<a name="63"><span class="lineNum">      63 </span>            : </a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">         60 :   reg REG;</span></a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">         72 :   reg REG_1;</span></a>
+<a name="66"><span class="lineNum">      66 </span><span class="lineCov">     127694 :   always @(posedge clock) begin</span></a>
+<a name="67"><span class="lineNum">      67 </span><span class="lineCov">      63847 :     REG &lt;= io_in;</span></a>
+<a name="68"><span class="lineNum">      68 </span><span class="lineCov">      63847 :     REG_1 &lt;= REG;</span></a>
+<a name="69"><span class="lineNum">      69 </span>            :   end // always @(posedge)</a>
+<a name="70"><span class="lineNum">      70 </span>            :   `ifdef ENABLE_INITIAL_REG_</a>
+<a name="71"><span class="lineNum">      71 </span>            :     `ifdef FIRRTL_BEFORE_INITIAL</a>
+<a name="72"><span class="lineNum">      72 </span>            :       `FIRRTL_BEFORE_INITIAL</a>
+<a name="73"><span class="lineNum">      73 </span>            :     `endif // FIRRTL_BEFORE_INITIAL</a>
+<a name="74"><span class="lineNum">      74 </span>            :     logic [31:0] _RANDOM[0:0];</a>
+<a name="75"><span class="lineNum">      75 </span><span class="lineCov">         58 :     initial begin</span></a>
+<a name="76"><span class="lineNum">      76 </span>            :       `ifdef INIT_RANDOM_PROLOG_</a>
+<a name="77"><span class="lineNum">      77 </span>            :         `INIT_RANDOM_PROLOG_</a>
+<a name="78"><span class="lineNum">      78 </span>            :       `endif // INIT_RANDOM_PROLOG_</a>
+<a name="79"><span class="lineNum">      79 </span>            :       `ifdef RANDOMIZE_REG_INIT</a>
+<a name="80"><span class="lineNum">      80 </span>            :         _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;</a>
+<a name="81"><span class="lineNum">      81 </span>            :         REG = _RANDOM[/*Zero width*/ 1'b0][0];</a>
+<a name="82"><span class="lineNum">      82 </span>            :         REG_1 = _RANDOM[/*Zero width*/ 1'b0][1];</a>
+<a name="83"><span class="lineNum">      83 </span>            :       `endif // RANDOMIZE_REG_INIT</a>
+<a name="84"><span class="lineNum">      84 </span>            :     end // initial</a>
+<a name="85"><span class="lineNum">      85 </span>            :     `ifdef FIRRTL_AFTER_INITIAL</a>
+<a name="86"><span class="lineNum">      86 </span>            :       `FIRRTL_AFTER_INITIAL</a>
+<a name="87"><span class="lineNum">      87 </span>            :     `endif // FIRRTL_AFTER_INITIAL</a>
+<a name="88"><span class="lineNum">      88 </span>            :   `endif // ENABLE_INITIAL_REG_</a>
+<a name="89"><span class="lineNum">      89 </span>            :   assign io_out = REG_1;</a>
+<a name="90"><span class="lineNum">      90 </span>            : endmodule</a>
+<a name="91"><span class="lineNum">      91 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FTB.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FTB.sv.func-sort-c.html
new file mode 100644
index 0000000..212dca5
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FTB.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/FTB.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - FTB.sv<span style="font-size: 80%;"> (<a href="FTB.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">703</td>
+            <td class="headerCovTableEntry">703</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="FTB.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FTB.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FTB.sv.func.html
new file mode 100644
index 0000000..566d0da
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FTB.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/FTB.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - FTB.sv<span style="font-size: 80%;"> (<a href="FTB.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">703</td>
+            <td class="headerCovTableEntry">703</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="FTB.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FTB.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FTB.sv.gcov.html
new file mode 100644
index 0000000..ee97a79
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FTB.sv.gcov.html
@@ -0,0 +1,1732 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/FTB.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - FTB.sv<span style="font-size: 80%;"> (source / <a href="FTB.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">703</td>
+            <td class="headerCovTableEntry">703</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : module FTB(</a>
+<a name="59"><span class="lineNum">      59 </span><span class="lineCov">     127786 :   input          clock,</span></a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">         62 :   input          reset,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">       1105 : </span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">      10337 :   input  [35:0]  io_reset_vector,</span></a>
+<a name="63"><span class="lineNum">      63 </span><span class="lineCov">      10224 : </span></a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">      10251 :   input  [40:0]  io_in_bits_s0_pc_0,</span></a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">      35066 :   input  [40:0]  io_in_bits_s0_pc_1,</span></a>
+<a name="66"><span class="lineNum">      66 </span><span class="lineCov">         75 :   input  [40:0]  io_in_bits_s0_pc_2,</span></a>
+<a name="67"><span class="lineNum">      67 </span><span class="lineCov">         68 :   input  [40:0]  io_in_bits_s0_pc_3,</span></a>
+<a name="68"><span class="lineNum">      68 </span><span class="lineCov">         61 :   input          io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_0,</span></a>
+<a name="69"><span class="lineNum">      69 </span><span class="lineCov">         64 :   input          io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_1,</span></a>
+<a name="70"><span class="lineNum">      70 </span><span class="lineCov">         64 :   input          io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_0,</span></a>
+<a name="71"><span class="lineNum">      71 </span><span class="lineCov">         55 :   input          io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_1,</span></a>
+<a name="72"><span class="lineNum">      72 </span><span class="lineCov">         75 :   input          io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_0,</span></a>
+<a name="73"><span class="lineNum">      73 </span><span class="lineCov">         67 :   input          io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_1,</span></a>
+<a name="74"><span class="lineNum">      74 </span><span class="lineCov">         75 :   input          io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_0,</span></a>
+<a name="75"><span class="lineNum">      75 </span><span class="lineCov">         64 :   input          io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_1,</span></a>
+<a name="76"><span class="lineNum">      76 </span><span class="lineCov">         82 :   input          io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_0,</span></a>
+<a name="77"><span class="lineNum">      77 </span><span class="lineCov">         62 :   input          io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_1,</span></a>
+<a name="78"><span class="lineNum">      78 </span><span class="lineCov">         84 :   input          io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_0,</span></a>
+<a name="79"><span class="lineNum">      79 </span><span class="lineCov">         66 :   input          io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_1,</span></a>
+<a name="80"><span class="lineNum">      80 </span><span class="lineCov">         70 :   input          io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_0,</span></a>
+<a name="81"><span class="lineNum">      81 </span><span class="lineCov">         69 :   input          io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_1,</span></a>
+<a name="82"><span class="lineNum">      82 </span><span class="lineCov">         79 :   input          io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_0,</span></a>
+<a name="83"><span class="lineNum">      83 </span><span class="lineCov">         69 :   input          io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_1,</span></a>
+<a name="84"><span class="lineNum">      84 </span><span class="lineCov">         31 : </span></a>
+<a name="85"><span class="lineNum">      85 </span><span class="lineCov">         30 :   output         io_out_s2_full_pred_0_br_taken_mask_0,</span></a>
+<a name="86"><span class="lineNum">      86 </span><span class="lineCov">       1189 :   output         io_out_s2_full_pred_0_br_taken_mask_1,</span></a>
+<a name="87"><span class="lineNum">      87 </span><span class="lineCov">       1202 :   output         io_out_s2_full_pred_0_slot_valids_0,</span></a>
+<a name="88"><span class="lineNum">      88 </span><span class="lineCov">       1202 :   output         io_out_s2_full_pred_0_slot_valids_1,</span></a>
+<a name="89"><span class="lineNum">      89 </span><span class="lineCov">        116 :   output [40:0]  io_out_s2_full_pred_0_targets_0,</span></a>
+<a name="90"><span class="lineNum">      90 </span><span class="lineCov">        107 :   output [40:0]  io_out_s2_full_pred_0_targets_1,</span></a>
+<a name="91"><span class="lineNum">      91 </span><span class="lineCov">       9456 :   output [40:0]  io_out_s2_full_pred_0_jalr_target,</span></a>
+<a name="92"><span class="lineNum">      92 </span><span class="lineCov">         31 :   output [3:0]   io_out_s2_full_pred_0_offsets_0,</span></a>
+<a name="93"><span class="lineNum">      93 </span><span class="lineCov">         18 :   output [3:0]   io_out_s2_full_pred_0_offsets_1,</span></a>
+<a name="94"><span class="lineNum">      94 </span><span class="lineCov">         59 :   output [40:0]  io_out_s2_full_pred_0_fallThroughAddr,</span></a>
+<a name="95"><span class="lineNum">      95 </span><span class="lineCov">         71 :   output         io_out_s2_full_pred_0_is_br_sharing,</span></a>
+<a name="96"><span class="lineNum">      96 </span><span class="lineCov">         24 :   output         io_out_s2_full_pred_0_hit,</span></a>
+<a name="97"><span class="lineNum">      97 </span><span class="lineCov">         24 :   output         io_out_s2_full_pred_1_br_taken_mask_0,</span></a>
+<a name="98"><span class="lineNum">      98 </span><span class="lineCov">       1278 :   output         io_out_s2_full_pred_1_br_taken_mask_1,</span></a>
+<a name="99"><span class="lineNum">      99 </span><span class="lineCov">       1114 :   output         io_out_s2_full_pred_1_slot_valids_0,</span></a>
+<a name="100"><span class="lineNum">     100 </span><span class="lineCov">       1114 :   output         io_out_s2_full_pred_1_slot_valids_1,</span></a>
+<a name="101"><span class="lineNum">     101 </span><span class="lineCov">        108 :   output [40:0]  io_out_s2_full_pred_1_targets_0,</span></a>
+<a name="102"><span class="lineNum">     102 </span><span class="lineCov">        119 :   output [40:0]  io_out_s2_full_pred_1_targets_1,</span></a>
+<a name="103"><span class="lineNum">     103 </span><span class="lineCov">       9458 :   output [40:0]  io_out_s2_full_pred_1_jalr_target,</span></a>
+<a name="104"><span class="lineNum">     104 </span><span class="lineCov">         17 :   output [3:0]   io_out_s2_full_pred_1_offsets_0,</span></a>
+<a name="105"><span class="lineNum">     105 </span><span class="lineCov">         25 :   output [3:0]   io_out_s2_full_pred_1_offsets_1,</span></a>
+<a name="106"><span class="lineNum">     106 </span><span class="lineCov">         72 :   output [40:0]  io_out_s2_full_pred_1_fallThroughAddr,</span></a>
+<a name="107"><span class="lineNum">     107 </span><span class="lineCov">         58 :   output         io_out_s2_full_pred_1_is_br_sharing,</span></a>
+<a name="108"><span class="lineNum">     108 </span><span class="lineCov">         31 :   output         io_out_s2_full_pred_1_hit,</span></a>
+<a name="109"><span class="lineNum">     109 </span><span class="lineCov">         28 :   output         io_out_s2_full_pred_2_br_taken_mask_0,</span></a>
+<a name="110"><span class="lineNum">     110 </span><span class="lineCov">       1211 :   output         io_out_s2_full_pred_2_br_taken_mask_1,</span></a>
+<a name="111"><span class="lineNum">     111 </span><span class="lineCov">       1198 :   output         io_out_s2_full_pred_2_slot_valids_0,</span></a>
+<a name="112"><span class="lineNum">     112 </span><span class="lineCov">       1198 :   output         io_out_s2_full_pred_2_slot_valids_1,</span></a>
+<a name="113"><span class="lineNum">     113 </span><span class="lineCov">        114 :   output [40:0]  io_out_s2_full_pred_2_targets_0,</span></a>
+<a name="114"><span class="lineNum">     114 </span><span class="lineCov">        120 :   output [40:0]  io_out_s2_full_pred_2_targets_1,</span></a>
+<a name="115"><span class="lineNum">     115 </span><span class="lineCov">       9409 :   output [40:0]  io_out_s2_full_pred_2_jalr_target,</span></a>
+<a name="116"><span class="lineNum">     116 </span><span class="lineCov">         23 :   output [3:0]   io_out_s2_full_pred_2_offsets_0,</span></a>
+<a name="117"><span class="lineNum">     117 </span><span class="lineCov">         21 :   output [3:0]   io_out_s2_full_pred_2_offsets_1,</span></a>
+<a name="118"><span class="lineNum">     118 </span><span class="lineCov">         26 :   output [40:0]  io_out_s2_full_pred_2_fallThroughAddr,</span></a>
+<a name="119"><span class="lineNum">     119 </span><span class="lineCov">         25 :   output         io_out_s2_full_pred_2_is_jalr,</span></a>
+<a name="120"><span class="lineNum">     120 </span><span class="lineCov">         23 :   output         io_out_s2_full_pred_2_is_call,</span></a>
+<a name="121"><span class="lineNum">     121 </span><span class="lineCov">         29 :   output         io_out_s2_full_pred_2_is_ret,</span></a>
+<a name="122"><span class="lineNum">     122 </span><span class="lineCov">         79 :   output         io_out_s2_full_pred_2_last_may_be_rvi_call,</span></a>
+<a name="123"><span class="lineNum">     123 </span><span class="lineCov">         76 :   output         io_out_s2_full_pred_2_is_br_sharing,</span></a>
+<a name="124"><span class="lineNum">     124 </span><span class="lineCov">         27 :   output         io_out_s2_full_pred_2_hit,</span></a>
+<a name="125"><span class="lineNum">     125 </span><span class="lineCov">         30 :   output         io_out_s2_full_pred_3_br_taken_mask_0,</span></a>
+<a name="126"><span class="lineNum">     126 </span><span class="lineCov">       1252 :   output         io_out_s2_full_pred_3_br_taken_mask_1,</span></a>
+<a name="127"><span class="lineNum">     127 </span><span class="lineCov">       1179 :   output         io_out_s2_full_pred_3_slot_valids_0,</span></a>
+<a name="128"><span class="lineNum">     128 </span><span class="lineCov">       1179 :   output         io_out_s2_full_pred_3_slot_valids_1,</span></a>
+<a name="129"><span class="lineNum">     129 </span><span class="lineCov">        119 :   output [40:0]  io_out_s2_full_pred_3_targets_0,</span></a>
+<a name="130"><span class="lineNum">     130 </span><span class="lineCov">        105 :   output [40:0]  io_out_s2_full_pred_3_targets_1,</span></a>
+<a name="131"><span class="lineNum">     131 </span><span class="lineCov">       9476 :   output [40:0]  io_out_s2_full_pred_3_jalr_target,</span></a>
+<a name="132"><span class="lineNum">     132 </span><span class="lineCov">         33 :   output [3:0]   io_out_s2_full_pred_3_offsets_0,</span></a>
+<a name="133"><span class="lineNum">     133 </span><span class="lineCov">         22 :   output [3:0]   io_out_s2_full_pred_3_offsets_1,</span></a>
+<a name="134"><span class="lineNum">     134 </span><span class="lineCov">         18 :   output [40:0]  io_out_s2_full_pred_3_fallThroughAddr,</span></a>
+<a name="135"><span class="lineNum">     135 </span><span class="lineCov">         82 :   output         io_out_s2_full_pred_3_fallThroughErr,</span></a>
+<a name="136"><span class="lineNum">     136 </span><span class="lineCov">         70 :   output         io_out_s2_full_pred_3_is_br_sharing,</span></a>
+<a name="137"><span class="lineNum">     137 </span><span class="lineCov">         30 :   output         io_out_s2_full_pred_3_hit,</span></a>
+<a name="138"><span class="lineNum">     138 </span><span class="lineCov">         33 :   output         io_out_s3_full_pred_0_br_taken_mask_0,</span></a>
+<a name="139"><span class="lineNum">     139 </span><span class="lineCov">       1241 :   output         io_out_s3_full_pred_0_br_taken_mask_1,</span></a>
+<a name="140"><span class="lineNum">     140 </span><span class="lineCov">       1247 :   output         io_out_s3_full_pred_0_slot_valids_0,</span></a>
+<a name="141"><span class="lineNum">     141 </span><span class="lineCov">       1247 :   output         io_out_s3_full_pred_0_slot_valids_1,</span></a>
+<a name="142"><span class="lineNum">     142 </span><span class="lineCov">       9423 :   output [40:0]  io_out_s3_full_pred_0_targets_0,</span></a>
+<a name="143"><span class="lineNum">     143 </span><span class="lineCov">         39 :   output [40:0]  io_out_s3_full_pred_0_targets_1,</span></a>
+<a name="144"><span class="lineNum">     144 </span><span class="lineCov">         26 :   output [40:0]  io_out_s3_full_pred_0_jalr_target,</span></a>
+<a name="145"><span class="lineNum">     145 </span><span class="lineCov">         24 :   output [40:0]  io_out_s3_full_pred_0_fallThroughAddr,</span></a>
+<a name="146"><span class="lineNum">     146 </span><span class="lineCov">         80 :   output         io_out_s3_full_pred_0_fallThroughErr,</span></a>
+<a name="147"><span class="lineNum">     147 </span><span class="lineCov">         75 :   output         io_out_s3_full_pred_0_is_br_sharing,</span></a>
+<a name="148"><span class="lineNum">     148 </span><span class="lineCov">         30 :   output         io_out_s3_full_pred_0_hit,</span></a>
+<a name="149"><span class="lineNum">     149 </span><span class="lineCov">         39 :   output         io_out_s3_full_pred_1_br_taken_mask_0,</span></a>
+<a name="150"><span class="lineNum">     150 </span><span class="lineCov">       1262 :   output         io_out_s3_full_pred_1_br_taken_mask_1,</span></a>
+<a name="151"><span class="lineNum">     151 </span><span class="lineCov">       1289 :   output         io_out_s3_full_pred_1_slot_valids_0,</span></a>
+<a name="152"><span class="lineNum">     152 </span><span class="lineCov">       1289 :   output         io_out_s3_full_pred_1_slot_valids_1,</span></a>
+<a name="153"><span class="lineNum">     153 </span><span class="lineCov">       9377 :   output [40:0]  io_out_s3_full_pred_1_targets_0,</span></a>
+<a name="154"><span class="lineNum">     154 </span><span class="lineCov">         35 :   output [40:0]  io_out_s3_full_pred_1_targets_1,</span></a>
+<a name="155"><span class="lineNum">     155 </span><span class="lineCov">         24 :   output [40:0]  io_out_s3_full_pred_1_jalr_target,</span></a>
+<a name="156"><span class="lineNum">     156 </span><span class="lineCov">         33 :   output [40:0]  io_out_s3_full_pred_1_fallThroughAddr,</span></a>
+<a name="157"><span class="lineNum">     157 </span><span class="lineCov">         86 :   output         io_out_s3_full_pred_1_fallThroughErr,</span></a>
+<a name="158"><span class="lineNum">     158 </span><span class="lineCov">         70 :   output         io_out_s3_full_pred_1_is_br_sharing,</span></a>
+<a name="159"><span class="lineNum">     159 </span><span class="lineCov">         26 :   output         io_out_s3_full_pred_1_hit,</span></a>
+<a name="160"><span class="lineNum">     160 </span><span class="lineCov">         30 :   output         io_out_s3_full_pred_2_br_taken_mask_0,</span></a>
+<a name="161"><span class="lineNum">     161 </span><span class="lineCov">       1286 :   output         io_out_s3_full_pred_2_br_taken_mask_1,</span></a>
+<a name="162"><span class="lineNum">     162 </span><span class="lineCov">       1331 :   output         io_out_s3_full_pred_2_slot_valids_0,</span></a>
+<a name="163"><span class="lineNum">     163 </span><span class="lineCov">       1331 :   output         io_out_s3_full_pred_2_slot_valids_1,</span></a>
+<a name="164"><span class="lineNum">     164 </span><span class="lineCov">       9424 :   output [40:0]  io_out_s3_full_pred_2_targets_0,</span></a>
+<a name="165"><span class="lineNum">     165 </span><span class="lineCov">         35 :   output [40:0]  io_out_s3_full_pred_2_targets_1,</span></a>
+<a name="166"><span class="lineNum">     166 </span><span class="lineCov">         23 :   output [40:0]  io_out_s3_full_pred_2_jalr_target,</span></a>
+<a name="167"><span class="lineNum">     167 </span><span class="lineCov">         23 :   output [40:0]  io_out_s3_full_pred_2_fallThroughAddr,</span></a>
+<a name="168"><span class="lineNum">     168 </span><span class="lineCov">         24 :   output         io_out_s3_full_pred_2_fallThroughErr,</span></a>
+<a name="169"><span class="lineNum">     169 </span><span class="lineCov">         21 :   output         io_out_s3_full_pred_2_is_jalr,</span></a>
+<a name="170"><span class="lineNum">     170 </span><span class="lineCov">         29 :   output         io_out_s3_full_pred_2_is_call,</span></a>
+<a name="171"><span class="lineNum">     171 </span><span class="lineCov">         75 :   output         io_out_s3_full_pred_2_is_ret,</span></a>
+<a name="172"><span class="lineNum">     172 </span><span class="lineCov">         76 :   output         io_out_s3_full_pred_2_is_br_sharing,</span></a>
+<a name="173"><span class="lineNum">     173 </span><span class="lineCov">         41 :   output         io_out_s3_full_pred_2_hit,</span></a>
+<a name="174"><span class="lineNum">     174 </span><span class="lineCov">         42 :   output         io_out_s3_full_pred_3_br_taken_mask_0,</span></a>
+<a name="175"><span class="lineNum">     175 </span><span class="lineCov">       1231 :   output         io_out_s3_full_pred_3_br_taken_mask_1,</span></a>
+<a name="176"><span class="lineNum">     176 </span><span class="lineCov">       1247 :   output         io_out_s3_full_pred_3_slot_valids_0,</span></a>
+<a name="177"><span class="lineNum">     177 </span><span class="lineCov">       1247 :   output         io_out_s3_full_pred_3_slot_valids_1,</span></a>
+<a name="178"><span class="lineNum">     178 </span><span class="lineCov">        128 :   output [40:0]  io_out_s3_full_pred_3_targets_0,</span></a>
+<a name="179"><span class="lineNum">     179 </span><span class="lineCov">        137 :   output [40:0]  io_out_s3_full_pred_3_targets_1,</span></a>
+<a name="180"><span class="lineNum">     180 </span><span class="lineCov">       9391 :   output [40:0]  io_out_s3_full_pred_3_jalr_target,</span></a>
+<a name="181"><span class="lineNum">     181 </span><span class="lineCov">         41 :   output [3:0]   io_out_s3_full_pred_3_offsets_0,</span></a>
+<a name="182"><span class="lineNum">     182 </span><span class="lineCov">         30 :   output [3:0]   io_out_s3_full_pred_3_offsets_1,</span></a>
+<a name="183"><span class="lineNum">     183 </span><span class="lineCov">         27 :   output [40:0]  io_out_s3_full_pred_3_fallThroughAddr,</span></a>
+<a name="184"><span class="lineNum">     184 </span><span class="lineCov">       3313 :   output         io_out_s3_full_pred_3_fallThroughErr,</span></a>
+<a name="185"><span class="lineNum">     185 </span><span class="lineCov">         29 :   output         io_out_s3_full_pred_3_is_br_sharing,</span></a>
+<a name="186"><span class="lineNum">     186 </span><span class="lineCov">        126 :   output         io_out_s3_full_pred_3_hit,</span></a>
+<a name="187"><span class="lineNum">     187 </span><span class="lineCov">        409 :   output [222:0] io_out_last_stage_meta,</span></a>
+<a name="188"><span class="lineNum">     188 </span><span class="lineCov">         65 :   output         io_out_last_stage_ftb_entry_valid,</span></a>
+<a name="189"><span class="lineNum">     189 </span><span class="lineCov">         32 :   output [3:0]   io_out_last_stage_ftb_entry_brSlots_0_offset,</span></a>
+<a name="190"><span class="lineNum">     190 </span><span class="lineCov">         30 :   output [11:0]  io_out_last_stage_ftb_entry_brSlots_0_lower,</span></a>
+<a name="191"><span class="lineNum">     191 </span><span class="lineCov">        116 :   output [1:0]   io_out_last_stage_ftb_entry_brSlots_0_tarStat,</span></a>
+<a name="192"><span class="lineNum">     192 </span><span class="lineCov">        705 :   output         io_out_last_stage_ftb_entry_brSlots_0_sharing,</span></a>
+<a name="193"><span class="lineNum">     193 </span><span class="lineCov">         65 :   output         io_out_last_stage_ftb_entry_brSlots_0_valid,</span></a>
+<a name="194"><span class="lineNum">     194 </span><span class="lineCov">         37 :   output [3:0]   io_out_last_stage_ftb_entry_tailSlot_offset,</span></a>
+<a name="195"><span class="lineNum">     195 </span><span class="lineCov">         33 :   output [19:0]  io_out_last_stage_ftb_entry_tailSlot_lower,</span></a>
+<a name="196"><span class="lineNum">     196 </span><span class="lineCov">        142 :   output [1:0]   io_out_last_stage_ftb_entry_tailSlot_tarStat,</span></a>
+<a name="197"><span class="lineNum">     197 </span><span class="lineCov">         35 :   output         io_out_last_stage_ftb_entry_tailSlot_sharing,</span></a>
+<a name="198"><span class="lineNum">     198 </span><span class="lineCov">         34 :   output         io_out_last_stage_ftb_entry_tailSlot_valid,</span></a>
+<a name="199"><span class="lineNum">     199 </span><span class="lineCov">         33 :   output [3:0]   io_out_last_stage_ftb_entry_pftAddr,</span></a>
+<a name="200"><span class="lineNum">     200 </span><span class="lineCov">         36 :   output         io_out_last_stage_ftb_entry_carry,</span></a>
+<a name="201"><span class="lineNum">     201 </span><span class="lineCov">         31 :   output         io_out_last_stage_ftb_entry_isCall,</span></a>
+<a name="202"><span class="lineNum">     202 </span><span class="lineCov">         27 :   output         io_out_last_stage_ftb_entry_isRet,</span></a>
+<a name="203"><span class="lineNum">     203 </span><span class="lineCov">         33 :   output         io_out_last_stage_ftb_entry_isJalr,</span></a>
+<a name="204"><span class="lineNum">     204 </span><span class="lineCov">         86 :   output         io_out_last_stage_ftb_entry_last_may_be_rvi_call,</span></a>
+<a name="205"><span class="lineNum">     205 </span><span class="lineCov">         75 :   output         io_out_last_stage_ftb_entry_always_taken_0,</span></a>
+<a name="206"><span class="lineNum">     206 </span><span class="lineCov">         76 :   output         io_out_last_stage_ftb_entry_always_taken_1,</span></a>
+<a name="207"><span class="lineNum">     207 </span><span class="lineCov">         76 : </span></a>
+<a name="208"><span class="lineNum">     208 </span><span class="lineCov">         73 : </span></a>
+<a name="209"><span class="lineNum">     209 </span><span class="lineCov">        133 :   input          io_ctrl_btb_enable,</span></a>
+<a name="210"><span class="lineNum">     210 </span><span class="lineCov">        131 :   input          io_s0_fire_0,</span></a>
+<a name="211"><span class="lineNum">     211 </span><span class="lineCov">        135 :   input          io_s0_fire_1,</span></a>
+<a name="212"><span class="lineNum">     212 </span><span class="lineCov">        133 :   input          io_s0_fire_2,</span></a>
+<a name="213"><span class="lineNum">     213 </span><span class="lineCov">        127 :   input          io_s0_fire_3,</span></a>
+<a name="214"><span class="lineNum">     214 </span><span class="lineCov">        127 :   input          io_s1_fire_0,</span></a>
+<a name="215"><span class="lineNum">     215 </span><span class="lineCov">        127 :   input          io_s1_fire_1,</span></a>
+<a name="216"><span class="lineNum">     216 </span><span class="lineCov">        127 :   input          io_s1_fire_2,</span></a>
+<a name="217"><span class="lineNum">     217 </span><span class="lineCov">         88 :   input          io_s1_fire_3,</span></a>
+<a name="218"><span class="lineNum">     218 </span><span class="lineCov">        105 :   input          io_s2_fire_0,</span></a>
+<a name="219"><span class="lineNum">     219 </span><span class="lineCov">       1143 :   input          io_s2_fire_1,</span></a>
+<a name="220"><span class="lineNum">     220 </span><span class="lineCov">         33 :   input          io_s2_fire_2,</span></a>
+<a name="221"><span class="lineNum">     221 </span><span class="lineCov">        122 :   input          io_s2_fire_3,</span></a>
+<a name="222"><span class="lineNum">     222 </span><span class="lineCov">        337 :   output         io_s1_ready,</span></a>
+<a name="223"><span class="lineNum">     223 </span><span class="lineCov">         65 : </span></a>
+<a name="224"><span class="lineNum">     224 </span><span class="lineCov">         33 :   input          io_update_valid,</span></a>
+<a name="225"><span class="lineNum">     225 </span><span class="lineCov">         35 :   input  [40:0]  io_update_bits_pc,</span></a>
+<a name="226"><span class="lineNum">     226 </span><span class="lineCov">        137 :   input          io_update_bits_ftb_entry_valid,</span></a>
+<a name="227"><span class="lineNum">     227 </span><span class="lineCov">        552 :   input  [3:0]   io_update_bits_ftb_entry_brSlots_0_offset,</span></a>
+<a name="228"><span class="lineNum">     228 </span><span class="lineCov">         63 :   input  [11:0]  io_update_bits_ftb_entry_brSlots_0_lower,</span></a>
+<a name="229"><span class="lineNum">     229 </span><span class="lineCov">         33 :   input  [1:0]   io_update_bits_ftb_entry_brSlots_0_tarStat,</span></a>
+<a name="230"><span class="lineNum">     230 </span><span class="lineCov">         28 :   input          io_update_bits_ftb_entry_brSlots_0_sharing,</span></a>
+<a name="231"><span class="lineNum">     231 </span><span class="lineCov">        152 :   input          io_update_bits_ftb_entry_brSlots_0_valid,</span></a>
+<a name="232"><span class="lineNum">     232 </span><span class="lineCov">         34 :   input  [3:0]   io_update_bits_ftb_entry_tailSlot_offset,</span></a>
+<a name="233"><span class="lineNum">     233 </span><span class="lineCov">         39 :   input  [19:0]  io_update_bits_ftb_entry_tailSlot_lower,</span></a>
+<a name="234"><span class="lineNum">     234 </span><span class="lineCov">         36 :   input  [1:0]   io_update_bits_ftb_entry_tailSlot_tarStat,</span></a>
+<a name="235"><span class="lineNum">     235 </span><span class="lineCov">         37 :   input          io_update_bits_ftb_entry_tailSlot_sharing,</span></a>
+<a name="236"><span class="lineNum">     236 </span><span class="lineCov">         41 :   input          io_update_bits_ftb_entry_tailSlot_valid,</span></a>
+<a name="237"><span class="lineNum">     237 </span><span class="lineCov">         32 :   input  [3:0]   io_update_bits_ftb_entry_pftAddr,</span></a>
+<a name="238"><span class="lineNum">     238 </span><span class="lineCov">         33 :   input          io_update_bits_ftb_entry_carry,</span></a>
+<a name="239"><span class="lineNum">     239 </span><span class="lineCov">         46 :   input          io_update_bits_ftb_entry_isCall,</span></a>
+<a name="240"><span class="lineNum">     240 </span><span class="lineCov">       4526 :   input          io_update_bits_ftb_entry_isRet,</span></a>
+<a name="241"><span class="lineNum">     241 </span><span class="lineCov">        129 :   input          io_update_bits_ftb_entry_isJalr,</span></a>
+<a name="242"><span class="lineNum">     242 </span><span class="lineCov">        190 :   input          io_update_bits_ftb_entry_last_may_be_rvi_call,</span></a>
+<a name="243"><span class="lineNum">     243 </span>            :   input          io_update_bits_ftb_entry_always_taken_0,</a>
+<a name="244"><span class="lineNum">     244 </span>            :   input          io_update_bits_ftb_entry_always_taken_1,</a>
+<a name="245"><span class="lineNum">     245 </span>            :   input          io_update_bits_old_entry,</a>
+<a name="246"><span class="lineNum">     246 </span>            :   input  [222:0] io_update_bits_meta,</a>
+<a name="247"><span class="lineNum">     247 </span>            :   output [5:0]   io_perf_0_value,</a>
+<a name="248"><span class="lineNum">     248 </span>            :   output [5:0]   io_perf_1_value</a>
+<a name="249"><span class="lineNum">     249 </span>            : );</a>
+<a name="250"><span class="lineNum">     250 </span>            : </a>
+<a name="251"><span class="lineNum">     251 </span>            :   wire        _write_valid_delay_io_out;</a>
+<a name="252"><span class="lineNum">     252 </span>            :   wire        _delay2_entry_pipMod_io_out_bits_valid;</a>
+<a name="253"><span class="lineNum">     253 </span>            :   wire [3:0]  _delay2_entry_pipMod_io_out_bits_brSlots_0_offset;</a>
+<a name="254"><span class="lineNum">     254 </span>            :   wire [11:0] _delay2_entry_pipMod_io_out_bits_brSlots_0_lower;</a>
+<a name="255"><span class="lineNum">     255 </span>            :   wire [1:0]  _delay2_entry_pipMod_io_out_bits_brSlots_0_tarStat;</a>
+<a name="256"><span class="lineNum">     256 </span>            :   wire        _delay2_entry_pipMod_io_out_bits_brSlots_0_sharing;</a>
+<a name="257"><span class="lineNum">     257 </span>            :   wire        _delay2_entry_pipMod_io_out_bits_brSlots_0_valid;</a>
+<a name="258"><span class="lineNum">     258 </span>            :   wire [3:0]  _delay2_entry_pipMod_io_out_bits_tailSlot_offset;</a>
+<a name="259"><span class="lineNum">     259 </span>            :   wire [19:0] _delay2_entry_pipMod_io_out_bits_tailSlot_lower;</a>
+<a name="260"><span class="lineNum">     260 </span>            :   wire [1:0]  _delay2_entry_pipMod_io_out_bits_tailSlot_tarStat;</a>
+<a name="261"><span class="lineNum">     261 </span>            :   wire        _delay2_entry_pipMod_io_out_bits_tailSlot_sharing;</a>
+<a name="262"><span class="lineNum">     262 </span>            :   wire        _delay2_entry_pipMod_io_out_bits_tailSlot_valid;</a>
+<a name="263"><span class="lineNum">     263 </span>            :   wire [3:0]  _delay2_entry_pipMod_io_out_bits_pftAddr;</a>
+<a name="264"><span class="lineNum">     264 </span>            :   wire        _delay2_entry_pipMod_io_out_bits_carry;</a>
+<a name="265"><span class="lineNum">     265 </span>            :   wire        _delay2_entry_pipMod_io_out_bits_isCall;</a>
+<a name="266"><span class="lineNum">     266 </span>            :   wire        _delay2_entry_pipMod_io_out_bits_isRet;</a>
+<a name="267"><span class="lineNum">     267 </span>            :   wire        _delay2_entry_pipMod_io_out_bits_isJalr;</a>
+<a name="268"><span class="lineNum">     268 </span>            :   wire        _delay2_entry_pipMod_io_out_bits_last_may_be_rvi_call;</a>
+<a name="269"><span class="lineNum">     269 </span>            :   wire        _delay2_entry_pipMod_io_out_bits_always_taken_0;</a>
+<a name="270"><span class="lineNum">     270 </span>            :   wire        _delay2_entry_pipMod_io_out_bits_always_taken_1;</a>
+<a name="271"><span class="lineNum">     271 </span>            :   wire [40:0] _delay2_pc_pipMod_io_out_bits;</a>
+<a name="272"><span class="lineNum">     272 </span>            :   wire        _ftbBank_io_req_pc_ready;</a>
+<a name="273"><span class="lineNum">     273 </span>            :   wire        _ftbBank_io_read_resp_valid;</a>
+<a name="274"><span class="lineNum">     274 </span>            :   wire [3:0]  _ftbBank_io_read_resp_brSlots_0_offset;</a>
+<a name="275"><span class="lineNum">     275 </span>            :   wire [11:0] _ftbBank_io_read_resp_brSlots_0_lower;</a>
+<a name="276"><span class="lineNum">     276 </span>            :   wire [1:0]  _ftbBank_io_read_resp_brSlots_0_tarStat;</a>
+<a name="277"><span class="lineNum">     277 </span>            :   wire        _ftbBank_io_read_resp_brSlots_0_sharing;</a>
+<a name="278"><span class="lineNum">     278 </span>            :   wire        _ftbBank_io_read_resp_brSlots_0_valid;</a>
+<a name="279"><span class="lineNum">     279 </span>            :   wire [3:0]  _ftbBank_io_read_resp_tailSlot_offset;</a>
+<a name="280"><span class="lineNum">     280 </span>            :   wire [19:0] _ftbBank_io_read_resp_tailSlot_lower;</a>
+<a name="281"><span class="lineNum">     281 </span>            :   wire [1:0]  _ftbBank_io_read_resp_tailSlot_tarStat;</a>
+<a name="282"><span class="lineNum">     282 </span>            :   wire        _ftbBank_io_read_resp_tailSlot_sharing;</a>
+<a name="283"><span class="lineNum">     283 </span>            :   wire        _ftbBank_io_read_resp_tailSlot_valid;</a>
+<a name="284"><span class="lineNum">     284 </span>            :   wire [3:0]  _ftbBank_io_read_resp_pftAddr;</a>
+<a name="285"><span class="lineNum">     285 </span>            :   wire        _ftbBank_io_read_resp_carry;</a>
+<a name="286"><span class="lineNum">     286 </span>            :   wire        _ftbBank_io_read_resp_isCall;</a>
+<a name="287"><span class="lineNum">     287 </span>            :   wire        _ftbBank_io_read_resp_isRet;</a>
+<a name="288"><span class="lineNum">     288 </span>            :   wire        _ftbBank_io_read_resp_isJalr;</a>
+<a name="289"><span class="lineNum">     289 </span>            :   wire        _ftbBank_io_read_resp_last_may_be_rvi_call;</a>
+<a name="290"><span class="lineNum">     290 </span>            :   wire        _ftbBank_io_read_resp_always_taken_0;</a>
+<a name="291"><span class="lineNum">     291 </span><span class="lineCov">       9933 :   wire        _ftbBank_io_read_resp_always_taken_1;</span></a>
+<a name="292"><span class="lineNum">     292 </span><span class="lineCov">       9916 :   wire        _ftbBank_io_read_hits_valid;</span></a>
+<a name="293"><span class="lineNum">     293 </span><span class="lineCov">       9909 :   wire [1:0]  _ftbBank_io_read_hits_bits;</span></a>
+<a name="294"><span class="lineNum">     294 </span><span class="lineCov">       9952 :   wire        _ftbBank_io_update_hits_valid;</span></a>
+<a name="295"><span class="lineNum">     295 </span><span class="lineCov">       9396 :   wire [1:0]  _ftbBank_io_update_hits_bits;</span></a>
+<a name="296"><span class="lineNum">     296 </span><span class="lineCov">       9392 :   wire [35:0] _reset_vector_delay_io_out;</span></a>
+<a name="297"><span class="lineNum">     297 </span><span class="lineCov">       9346 :   reg  [40:0] s1_pc_dup_0;</span></a>
+<a name="298"><span class="lineNum">     298 </span><span class="lineCov">       9373 :   reg  [40:0] s1_pc_dup_1;</span></a>
+<a name="299"><span class="lineNum">     299 </span><span class="lineCov">       9364 :   reg  [40:0] s1_pc_dup_2;</span></a>
+<a name="300"><span class="lineNum">     300 </span><span class="lineCov">       9352 :   reg  [40:0] s1_pc_dup_3;</span></a>
+<a name="301"><span class="lineNum">     301 </span><span class="lineCov">       9331 :   reg  [40:0] s2_pc_dup_0;</span></a>
+<a name="302"><span class="lineNum">     302 </span><span class="lineCov">       9345 :   reg  [40:0] s2_pc_dup_1;</span></a>
+<a name="303"><span class="lineNum">     303 </span><span class="lineCov">         77 :   reg  [40:0] s2_pc_dup_2;</span></a>
+<a name="304"><span class="lineNum">     304 </span><span class="lineCov">         91 :   reg  [40:0] s2_pc_dup_3;</span></a>
+<a name="305"><span class="lineNum">     305 </span><span class="lineCov">         25 :   reg  [40:0] s3_pc_dup_0;</span></a>
+<a name="306"><span class="lineNum">     306 </span><span class="lineCov">        116 :   reg  [40:0] s3_pc_dup_1;</span></a>
+<a name="307"><span class="lineNum">     307 </span><span class="lineCov">        349 :   reg  [40:0] s3_pc_dup_2;</span></a>
+<a name="308"><span class="lineNum">     308 </span><span class="lineCov">         61 :   reg  [40:0] s3_pc_dup_3;</span></a>
+<a name="309"><span class="lineNum">     309 </span><span class="lineCov">         31 :   reg         REG;</span></a>
+<a name="310"><span class="lineNum">     310 </span><span class="lineCov">         31 :   reg         REG_1;</span></a>
+<a name="311"><span class="lineNum">     311 </span><span class="lineCov">        107 :   reg         s2_ftb_entry_dup_0_valid;</span></a>
+<a name="312"><span class="lineNum">     312 </span><span class="lineCov">        564 :   reg  [3:0]  s2_ftb_entry_dup_0_brSlots_0_offset;</span></a>
+<a name="313"><span class="lineNum">     313 </span><span class="lineCov">         62 :   reg  [11:0] s2_ftb_entry_dup_0_brSlots_0_lower;</span></a>
+<a name="314"><span class="lineNum">     314 </span><span class="lineCov">         31 :   reg  [1:0]  s2_ftb_entry_dup_0_brSlots_0_tarStat;</span></a>
+<a name="315"><span class="lineNum">     315 </span><span class="lineCov">         30 :   reg         s2_ftb_entry_dup_0_brSlots_0_sharing;</span></a>
+<a name="316"><span class="lineNum">     316 </span><span class="lineCov">        120 :   reg         s2_ftb_entry_dup_0_brSlots_0_valid;</span></a>
+<a name="317"><span class="lineNum">     317 </span><span class="lineCov">         21 :   reg  [3:0]  s2_ftb_entry_dup_0_tailSlot_offset;</span></a>
+<a name="318"><span class="lineNum">     318 </span><span class="lineCov">         28 :   reg  [19:0] s2_ftb_entry_dup_0_tailSlot_lower;</span></a>
+<a name="319"><span class="lineNum">     319 </span><span class="lineCov">         30 :   reg  [1:0]  s2_ftb_entry_dup_0_tailSlot_tarStat;</span></a>
+<a name="320"><span class="lineNum">     320 </span><span class="lineCov">         32 :   reg         s2_ftb_entry_dup_0_tailSlot_sharing;</span></a>
+<a name="321"><span class="lineNum">     321 </span><span class="lineCov">         34 :   reg         s2_ftb_entry_dup_0_tailSlot_valid;</span></a>
+<a name="322"><span class="lineNum">     322 </span><span class="lineCov">         33 :   reg  [3:0]  s2_ftb_entry_dup_0_pftAddr;</span></a>
+<a name="323"><span class="lineNum">     323 </span><span class="lineCov">         23 :   reg         s2_ftb_entry_dup_0_carry;</span></a>
+<a name="324"><span class="lineNum">     324 </span><span class="lineCov">        108 :   reg         s2_ftb_entry_dup_0_isCall;</span></a>
+<a name="325"><span class="lineNum">     325 </span><span class="lineCov">        324 :   reg         s2_ftb_entry_dup_0_isRet;</span></a>
+<a name="326"><span class="lineNum">     326 </span><span class="lineCov">         58 :   reg         s2_ftb_entry_dup_0_isJalr;</span></a>
+<a name="327"><span class="lineNum">     327 </span><span class="lineCov">         24 :   reg         s2_ftb_entry_dup_0_last_may_be_rvi_call;</span></a>
+<a name="328"><span class="lineNum">     328 </span><span class="lineCov">        119 :   reg         s2_ftb_entry_dup_0_always_taken_0;</span></a>
+<a name="329"><span class="lineNum">     329 </span><span class="lineCov">        561 :   reg         s2_ftb_entry_dup_0_always_taken_1;</span></a>
+<a name="330"><span class="lineNum">     330 </span><span class="lineCov">         54 :   reg  [3:0]  s2_ftb_entry_dup_1_brSlots_0_offset;</span></a>
+<a name="331"><span class="lineNum">     331 </span><span class="lineCov">         31 :   reg  [11:0] s2_ftb_entry_dup_1_brSlots_0_lower;</span></a>
+<a name="332"><span class="lineNum">     332 </span><span class="lineCov">         24 :   reg  [1:0]  s2_ftb_entry_dup_1_brSlots_0_tarStat;</span></a>
+<a name="333"><span class="lineNum">     333 </span><span class="lineCov">        118 :   reg         s2_ftb_entry_dup_1_brSlots_0_valid;</span></a>
+<a name="334"><span class="lineNum">     334 </span><span class="lineCov">         27 :   reg  [3:0]  s2_ftb_entry_dup_1_tailSlot_offset;</span></a>
+<a name="335"><span class="lineNum">     335 </span><span class="lineCov">         27 :   reg  [19:0] s2_ftb_entry_dup_1_tailSlot_lower;</span></a>
+<a name="336"><span class="lineNum">     336 </span><span class="lineCov">         30 :   reg  [1:0]  s2_ftb_entry_dup_1_tailSlot_tarStat;</span></a>
+<a name="337"><span class="lineNum">     337 </span><span class="lineCov">        114 :   reg         s2_ftb_entry_dup_1_tailSlot_sharing;</span></a>
+<a name="338"><span class="lineNum">     338 </span><span class="lineCov">        357 :   reg         s2_ftb_entry_dup_1_tailSlot_valid;</span></a>
+<a name="339"><span class="lineNum">     339 </span><span class="lineCov">         53 :   reg  [3:0]  s2_ftb_entry_dup_1_pftAddr;</span></a>
+<a name="340"><span class="lineNum">     340 </span><span class="lineCov">         31 :   reg         s2_ftb_entry_dup_1_carry;</span></a>
+<a name="341"><span class="lineNum">     341 </span><span class="lineCov">        120 :   reg         s2_ftb_entry_dup_1_always_taken_0;</span></a>
+<a name="342"><span class="lineNum">     342 </span><span class="lineCov">        574 :   reg         s2_ftb_entry_dup_1_always_taken_1;</span></a>
+<a name="343"><span class="lineNum">     343 </span><span class="lineCov">         55 :   reg  [3:0]  s2_ftb_entry_dup_2_brSlots_0_offset;</span></a>
+<a name="344"><span class="lineNum">     344 </span><span class="lineCov">         22 :   reg  [11:0] s2_ftb_entry_dup_2_brSlots_0_lower;</span></a>
+<a name="345"><span class="lineNum">     345 </span><span class="lineCov">         28 :   reg  [1:0]  s2_ftb_entry_dup_2_brSlots_0_tarStat;</span></a>
+<a name="346"><span class="lineNum">     346 </span><span class="lineCov">        127 :   reg         s2_ftb_entry_dup_2_brSlots_0_valid;</span></a>
+<a name="347"><span class="lineNum">     347 </span><span class="lineCov">         33 :   reg  [3:0]  s2_ftb_entry_dup_2_tailSlot_offset;</span></a>
+<a name="348"><span class="lineNum">     348 </span><span class="lineCov">         30 :   reg  [19:0] s2_ftb_entry_dup_2_tailSlot_lower;</span></a>
+<a name="349"><span class="lineNum">     349 </span><span class="lineCov">         39 :   reg  [1:0]  s2_ftb_entry_dup_2_tailSlot_tarStat;</span></a>
+<a name="350"><span class="lineNum">     350 </span><span class="lineCov">         21 :   reg         s2_ftb_entry_dup_2_tailSlot_sharing;</span></a>
+<a name="351"><span class="lineNum">     351 </span><span class="lineCov">         25 :   reg         s2_ftb_entry_dup_2_tailSlot_valid;</span></a>
+<a name="352"><span class="lineNum">     352 </span><span class="lineCov">         27 :   reg  [3:0]  s2_ftb_entry_dup_2_pftAddr;</span></a>
+<a name="353"><span class="lineNum">     353 </span><span class="lineCov">         26 :   reg         s2_ftb_entry_dup_2_carry;</span></a>
+<a name="354"><span class="lineNum">     354 </span><span class="lineCov">        119 :   reg         s2_ftb_entry_dup_2_isCall;</span></a>
+<a name="355"><span class="lineNum">     355 </span><span class="lineCov">        367 :   reg         s2_ftb_entry_dup_2_isRet;</span></a>
+<a name="356"><span class="lineNum">     356 </span><span class="lineCov">         52 :   reg         s2_ftb_entry_dup_2_isJalr;</span></a>
+<a name="357"><span class="lineNum">     357 </span><span class="lineCov">         27 :   reg         s2_ftb_entry_dup_2_last_may_be_rvi_call;</span></a>
+<a name="358"><span class="lineNum">     358 </span><span class="lineCov">        105 :   reg         s2_ftb_entry_dup_2_always_taken_0;</span></a>
+<a name="359"><span class="lineNum">     359 </span><span class="lineCov">        602 :   reg         s2_ftb_entry_dup_2_always_taken_1;</span></a>
+<a name="360"><span class="lineNum">     360 </span><span class="lineCov">         59 :   reg  [3:0]  s2_ftb_entry_dup_3_brSlots_0_offset;</span></a>
+<a name="361"><span class="lineNum">     361 </span><span class="lineCov">         31 :   reg  [11:0] s2_ftb_entry_dup_3_brSlots_0_lower;</span></a>
+<a name="362"><span class="lineNum">     362 </span><span class="lineCov">         30 :   reg  [1:0]  s2_ftb_entry_dup_3_brSlots_0_tarStat;</span></a>
+<a name="363"><span class="lineNum">     363 </span><span class="lineCov">        120 :   reg         s2_ftb_entry_dup_3_brSlots_0_valid;</span></a>
+<a name="364"><span class="lineNum">     364 </span><span class="lineCov">         32 :   reg  [3:0]  s2_ftb_entry_dup_3_tailSlot_offset;</span></a>
+<a name="365"><span class="lineNum">     365 </span><span class="lineCov">         25 :   reg  [19:0] s2_ftb_entry_dup_3_tailSlot_lower;</span></a>
+<a name="366"><span class="lineNum">     366 </span><span class="lineCov">         32 :   reg  [1:0]  s2_ftb_entry_dup_3_tailSlot_tarStat;</span></a>
+<a name="367"><span class="lineNum">     367 </span><span class="lineCov">         29 :   reg         s2_ftb_entry_dup_3_tailSlot_sharing;</span></a>
+<a name="368"><span class="lineNum">     368 </span><span class="lineCov">        126 :   reg         s2_ftb_entry_dup_3_tailSlot_valid;</span></a>
+<a name="369"><span class="lineNum">     369 </span><span class="lineCov">        409 :   reg  [3:0]  s2_ftb_entry_dup_3_pftAddr;</span></a>
+<a name="370"><span class="lineNum">     370 </span><span class="lineCov">         65 :   reg         s2_ftb_entry_dup_3_carry;</span></a>
+<a name="371"><span class="lineNum">     371 </span><span class="lineCov">         32 :   reg         s2_ftb_entry_dup_3_always_taken_0;</span></a>
+<a name="372"><span class="lineNum">     372 </span><span class="lineCov">         30 :   reg         s2_ftb_entry_dup_3_always_taken_1;</span></a>
+<a name="373"><span class="lineNum">     373 </span><span class="lineCov">        116 :   reg         s3_ftb_entry_dup_0_valid;</span></a>
+<a name="374"><span class="lineNum">     374 </span><span class="lineCov">        705 :   reg  [3:0]  s3_ftb_entry_dup_0_brSlots_0_offset;</span></a>
+<a name="375"><span class="lineNum">     375 </span><span class="lineCov">         65 :   reg  [11:0] s3_ftb_entry_dup_0_brSlots_0_lower;</span></a>
+<a name="376"><span class="lineNum">     376 </span><span class="lineCov">         37 :   reg  [1:0]  s3_ftb_entry_dup_0_brSlots_0_tarStat;</span></a>
+<a name="377"><span class="lineNum">     377 </span><span class="lineCov">         33 :   reg         s3_ftb_entry_dup_0_brSlots_0_sharing;</span></a>
+<a name="378"><span class="lineNum">     378 </span><span class="lineCov">        142 :   reg         s3_ftb_entry_dup_0_brSlots_0_valid;</span></a>
+<a name="379"><span class="lineNum">     379 </span><span class="lineCov">         35 :   reg  [3:0]  s3_ftb_entry_dup_0_tailSlot_offset;</span></a>
+<a name="380"><span class="lineNum">     380 </span><span class="lineCov">         34 :   reg  [19:0] s3_ftb_entry_dup_0_tailSlot_lower;</span></a>
+<a name="381"><span class="lineNum">     381 </span><span class="lineCov">         33 :   reg  [1:0]  s3_ftb_entry_dup_0_tailSlot_tarStat;</span></a>
+<a name="382"><span class="lineNum">     382 </span><span class="lineCov">         36 :   reg         s3_ftb_entry_dup_0_tailSlot_sharing;</span></a>
+<a name="383"><span class="lineNum">     383 </span><span class="lineCov">         31 :   reg         s3_ftb_entry_dup_0_tailSlot_valid;</span></a>
+<a name="384"><span class="lineNum">     384 </span><span class="lineCov">         27 :   reg  [3:0]  s3_ftb_entry_dup_0_pftAddr;</span></a>
+<a name="385"><span class="lineNum">     385 </span><span class="lineCov">         33 :   reg         s3_ftb_entry_dup_0_carry;</span></a>
+<a name="386"><span class="lineNum">     386 </span><span class="lineCov">        388 :   reg         s3_ftb_entry_dup_0_isCall;</span></a>
+<a name="387"><span class="lineNum">     387 </span><span class="lineCov">         64 :   reg         s3_ftb_entry_dup_0_isRet;</span></a>
+<a name="388"><span class="lineNum">     388 </span><span class="lineCov">         30 :   reg         s3_ftb_entry_dup_0_isJalr;</span></a>
+<a name="389"><span class="lineNum">     389 </span><span class="lineCov">        632 :   reg         s3_ftb_entry_dup_0_last_may_be_rvi_call;</span></a>
+<a name="390"><span class="lineNum">     390 </span><span class="lineCov">         63 :   reg         s3_ftb_entry_dup_0_always_taken_0;</span></a>
+<a name="391"><span class="lineNum">     391 </span><span class="lineCov">         31 :   reg         s3_ftb_entry_dup_0_always_taken_1;</span></a>
+<a name="392"><span class="lineNum">     392 </span><span class="lineCov">         39 :   reg  [11:0] s3_ftb_entry_dup_1_brSlots_0_lower;</span></a>
+<a name="393"><span class="lineNum">     393 </span><span class="lineCov">        142 :   reg  [1:0]  s3_ftb_entry_dup_1_brSlots_0_tarStat;</span></a>
+<a name="394"><span class="lineNum">     394 </span><span class="lineCov">         33 :   reg         s3_ftb_entry_dup_1_brSlots_0_valid;</span></a>
+<a name="395"><span class="lineNum">     395 </span><span class="lineCov">         26 :   reg  [19:0] s3_ftb_entry_dup_1_tailSlot_lower;</span></a>
+<a name="396"><span class="lineNum">     396 </span><span class="lineCov">         37 :   reg  [1:0]  s3_ftb_entry_dup_1_tailSlot_tarStat;</span></a>
+<a name="397"><span class="lineNum">     397 </span><span class="lineCov">        379 :   reg         s3_ftb_entry_dup_1_tailSlot_sharing;</span></a>
+<a name="398"><span class="lineNum">     398 </span><span class="lineCov">         65 :   reg         s3_ftb_entry_dup_1_tailSlot_valid;</span></a>
+<a name="399"><span class="lineNum">     399 </span><span class="lineCov">         26 :   reg  [3:0]  s3_ftb_entry_dup_1_pftAddr;</span></a>
+<a name="400"><span class="lineNum">     400 </span><span class="lineCov">        670 :   reg         s3_ftb_entry_dup_1_carry;</span></a>
+<a name="401"><span class="lineNum">     401 </span><span class="lineCov">         66 :   reg         s3_ftb_entry_dup_1_always_taken_0;</span></a>
+<a name="402"><span class="lineNum">     402 </span><span class="lineCov">         24 :   reg         s3_ftb_entry_dup_1_always_taken_1;</span></a>
+<a name="403"><span class="lineNum">     403 </span><span class="lineCov">         30 :   reg  [11:0] s3_ftb_entry_dup_2_brSlots_0_lower;</span></a>
+<a name="404"><span class="lineNum">     404 </span><span class="lineCov">        142 :   reg  [1:0]  s3_ftb_entry_dup_2_brSlots_0_tarStat;</span></a>
+<a name="405"><span class="lineNum">     405 </span><span class="lineCov">         38 :   reg         s3_ftb_entry_dup_2_brSlots_0_valid;</span></a>
+<a name="406"><span class="lineNum">     406 </span><span class="lineCov">         27 :   reg  [19:0] s3_ftb_entry_dup_2_tailSlot_lower;</span></a>
+<a name="407"><span class="lineNum">     407 </span><span class="lineCov">         28 :   reg  [1:0]  s3_ftb_entry_dup_2_tailSlot_tarStat;</span></a>
+<a name="408"><span class="lineNum">     408 </span><span class="lineCov">         38 :   reg         s3_ftb_entry_dup_2_tailSlot_sharing;</span></a>
+<a name="409"><span class="lineNum">     409 </span><span class="lineCov">         33 :   reg         s3_ftb_entry_dup_2_tailSlot_valid;</span></a>
+<a name="410"><span class="lineNum">     410 </span><span class="lineCov">         29 :   reg  [3:0]  s3_ftb_entry_dup_2_pftAddr;</span></a>
+<a name="411"><span class="lineNum">     411 </span><span class="lineCov">        128 :   reg         s3_ftb_entry_dup_2_carry;</span></a>
+<a name="412"><span class="lineNum">     412 </span><span class="lineCov">        385 :   reg         s3_ftb_entry_dup_2_isCall;</span></a>
+<a name="413"><span class="lineNum">     413 </span><span class="lineCov">         73 :   reg         s3_ftb_entry_dup_2_isRet;</span></a>
+<a name="414"><span class="lineNum">     414 </span><span class="lineCov">         41 :   reg         s3_ftb_entry_dup_2_isJalr;</span></a>
+<a name="415"><span class="lineNum">     415 </span><span class="lineCov">        137 :   reg         s3_ftb_entry_dup_2_always_taken_0;</span></a>
+<a name="416"><span class="lineNum">     416 </span><span class="lineCov">        624 :   reg         s3_ftb_entry_dup_2_always_taken_1;</span></a>
+<a name="417"><span class="lineNum">     417 </span><span class="lineCov">         68 :   reg  [3:0]  s3_ftb_entry_dup_3_brSlots_0_offset;</span></a>
+<a name="418"><span class="lineNum">     418 </span><span class="lineCov">         37 :   reg  [11:0] s3_ftb_entry_dup_3_brSlots_0_lower;</span></a>
+<a name="419"><span class="lineNum">     419 </span><span class="lineCov">         42 :   reg  [1:0]  s3_ftb_entry_dup_3_brSlots_0_tarStat;</span></a>
+<a name="420"><span class="lineNum">     420 </span><span class="lineCov">        126 :   reg         s3_ftb_entry_dup_3_brSlots_0_valid;</span></a>
+<a name="421"><span class="lineNum">     421 </span><span class="lineCov">         34 :   reg  [3:0]  s3_ftb_entry_dup_3_tailSlot_offset;</span></a>
+<a name="422"><span class="lineNum">     422 </span><span class="lineCov">         34 :   reg  [19:0] s3_ftb_entry_dup_3_tailSlot_lower;</span></a>
+<a name="423"><span class="lineNum">     423 </span><span class="lineCov">         36 :   reg  [1:0]  s3_ftb_entry_dup_3_tailSlot_tarStat;</span></a>
+<a name="424"><span class="lineNum">     424 </span><span class="lineCov">         15 :   reg         s3_ftb_entry_dup_3_tailSlot_sharing;</span></a>
+<a name="425"><span class="lineNum">     425 </span><span class="lineCov">         18 :   reg         s3_ftb_entry_dup_3_tailSlot_valid;</span></a>
+<a name="426"><span class="lineNum">     426 </span><span class="lineCov">         25 :   reg  [3:0]  s3_ftb_entry_dup_3_pftAddr;</span></a>
+<a name="427"><span class="lineNum">     427 </span><span class="lineCov">         29 :   reg         s3_ftb_entry_dup_3_carry;</span></a>
+<a name="428"><span class="lineNum">     428 </span><span class="lineCov">         18 :   reg         s3_ftb_entry_dup_3_always_taken_0;</span></a>
+<a name="429"><span class="lineNum">     429 </span><span class="lineCov">         24 :   reg         s3_ftb_entry_dup_3_always_taken_1;</span></a>
+<a name="430"><span class="lineNum">     430 </span><span class="lineCov">         33 :   wire        s1_hit = _ftbBank_io_read_hits_valid &amp; io_ctrl_btb_enable;</span></a>
+<a name="431"><span class="lineNum">     431 </span><span class="lineCov">         29 :   reg         s2_hit_dup_0;</span></a>
+<a name="432"><span class="lineNum">     432 </span><span class="lineCov">         27 :   reg         s2_hit_dup_1;</span></a>
+<a name="433"><span class="lineNum">     433 </span><span class="lineCov">        903 :   reg         s2_hit_dup_2;</span></a>
+<a name="434"><span class="lineNum">     434 </span><span class="lineCov">        874 :   reg         s2_hit_dup_3;</span></a>
+<a name="435"><span class="lineNum">     435 </span><span class="lineCov">       1216 :   reg         s3_hit_dup_0;</span></a>
+<a name="436"><span class="lineNum">     436 </span><span class="lineCov">        935 :   reg         s3_hit_dup_1;</span></a>
+<a name="437"><span class="lineNum">     437 </span><span class="lineCov">        921 :   reg         s3_hit_dup_2;</span></a>
+<a name="438"><span class="lineNum">     438 </span><span class="lineCov">       1200 :   reg         s3_hit_dup_3;</span></a>
+<a name="439"><span class="lineNum">     439 </span>            :   reg  [27:0] higher_r;</a>
+<a name="440"><span class="lineNum">     440 </span>            :   reg  [27:0] higher_plus_one_r;</a>
+<a name="441"><span class="lineNum">     441 </span>            :   reg  [27:0] higher_minus_one_r;</a>
+<a name="442"><span class="lineNum">     442 </span><span class="lineCov">        630 :   reg  [27:0] higher_r_1;</span></a>
+<a name="443"><span class="lineNum">     443 </span><span class="lineCov">        657 :   reg  [27:0] higher_plus_one_r_1;</span></a>
+<a name="444"><span class="lineNum">     444 </span><span class="lineCov">        622 :   reg  [27:0] higher_minus_one_r_1;</span></a>
+<a name="445"><span class="lineNum">     445 </span><span class="lineCov">       1202 :   wire        _target_T_18 = s2_ftb_entry_dup_0_tailSlot_tarStat == 2'h1;</span></a>
+<a name="446"><span class="lineNum">     446 </span>            :   wire        _target_T_19 = s2_ftb_entry_dup_0_tailSlot_tarStat == 2'h2;</a>
+<a name="447"><span class="lineNum">     447 </span>            :   wire        _target_T_20 = s2_ftb_entry_dup_0_tailSlot_tarStat == 2'h0;</a>
+<a name="448"><span class="lineNum">     448 </span>            :   reg  [19:0] higher_r_2;</a>
+<a name="449"><span class="lineNum">     449 </span>            :   reg  [19:0] higher_plus_one_r_2;</a>
+<a name="450"><span class="lineNum">     450 </span>            :   reg  [19:0] higher_minus_one_r_2;</a>
+<a name="451"><span class="lineNum">     451 </span>            :   wire [40:0] io_out_s2_full_pred_0_targets_1_0 =</a>
+<a name="452"><span class="lineNum">     452 </span>            :     {s2_ftb_entry_dup_0_tailSlot_sharing</a>
+<a name="453"><span class="lineNum">     453 </span>            :        ? {(_target_T_18 ? higher_plus_one_r_1 : 28'h0)</a>
+<a name="454"><span class="lineNum">     454 </span>            :             | (_target_T_19 ? higher_minus_one_r_1 : 28'h0)</a>
+<a name="455"><span class="lineNum">     455 </span>            :             | (_target_T_20 ? higher_r_1 : 28'h0),</a>
+<a name="456"><span class="lineNum">     456 </span><span class="lineCov">         28 :           s2_ftb_entry_dup_0_tailSlot_lower[11:0]}</span></a>
+<a name="457"><span class="lineNum">     457 </span><span class="lineCov">        913 :        : {(_target_T_18 ? higher_plus_one_r_2 : 20'h0)</span></a>
+<a name="458"><span class="lineNum">     458 </span><span class="lineCov">        913 :             | (_target_T_19 ? higher_minus_one_r_2 : 20'h0)</span></a>
+<a name="459"><span class="lineNum">     459 </span><span class="lineCov">       1213 :             | (_target_T_20 ? higher_r_2 : 20'h0),</span></a>
+<a name="460"><span class="lineNum">     460 </span><span class="lineCov">        935 :           s2_ftb_entry_dup_0_tailSlot_lower},</span></a>
+<a name="461"><span class="lineNum">     461 </span><span class="lineCov">        937 :      1'h0};</span></a>
+<a name="462"><span class="lineNum">     462 </span><span class="lineCov">       1221 :   reg         io_out_s2_full_pred_0_fallThroughAddr_stashed_carry;</span></a>
+<a name="463"><span class="lineNum">     463 </span>            :   reg  [27:0] higher_r_3;</a>
+<a name="464"><span class="lineNum">     464 </span>            :   reg  [27:0] higher_plus_one_r_3;</a>
+<a name="465"><span class="lineNum">     465 </span>            :   reg  [27:0] higher_minus_one_r_3;</a>
+<a name="466"><span class="lineNum">     466 </span><span class="lineCov">        638 :   reg  [27:0] higher_r_4;</span></a>
+<a name="467"><span class="lineNum">     467 </span><span class="lineCov">        617 :   reg  [27:0] higher_plus_one_r_4;</span></a>
+<a name="468"><span class="lineNum">     468 </span><span class="lineCov">        648 :   reg  [27:0] higher_minus_one_r_4;</span></a>
+<a name="469"><span class="lineNum">     469 </span><span class="lineCov">       1114 :   wire        _target_T_45 = s2_ftb_entry_dup_1_tailSlot_tarStat == 2'h1;</span></a>
+<a name="470"><span class="lineNum">     470 </span>            :   wire        _target_T_46 = s2_ftb_entry_dup_1_tailSlot_tarStat == 2'h2;</a>
+<a name="471"><span class="lineNum">     471 </span>            :   wire        _target_T_47 = s2_ftb_entry_dup_1_tailSlot_tarStat == 2'h0;</a>
+<a name="472"><span class="lineNum">     472 </span>            :   reg  [19:0] higher_r_5;</a>
+<a name="473"><span class="lineNum">     473 </span>            :   reg  [19:0] higher_plus_one_r_5;</a>
+<a name="474"><span class="lineNum">     474 </span>            :   reg  [19:0] higher_minus_one_r_5;</a>
+<a name="475"><span class="lineNum">     475 </span>            :   wire [40:0] io_out_s2_full_pred_1_targets_1_0 =</a>
+<a name="476"><span class="lineNum">     476 </span>            :     {s2_ftb_entry_dup_1_tailSlot_sharing</a>
+<a name="477"><span class="lineNum">     477 </span>            :        ? {(_target_T_45 ? higher_plus_one_r_4 : 28'h0)</a>
+<a name="478"><span class="lineNum">     478 </span>            :             | (_target_T_46 ? higher_minus_one_r_4 : 28'h0)</a>
+<a name="479"><span class="lineNum">     479 </span>            :             | (_target_T_47 ? higher_r_4 : 28'h0),</a>
+<a name="480"><span class="lineNum">     480 </span><span class="lineCov">         31 :           s2_ftb_entry_dup_1_tailSlot_lower[11:0]}</span></a>
+<a name="481"><span class="lineNum">     481 </span><span class="lineCov">        916 :        : {(_target_T_45 ? higher_plus_one_r_5 : 20'h0)</span></a>
+<a name="482"><span class="lineNum">     482 </span><span class="lineCov">        927 :             | (_target_T_46 ? higher_minus_one_r_5 : 20'h0)</span></a>
+<a name="483"><span class="lineNum">     483 </span><span class="lineCov">       1229 :             | (_target_T_47 ? higher_r_5 : 20'h0),</span></a>
+<a name="484"><span class="lineNum">     484 </span><span class="lineCov">        906 :           s2_ftb_entry_dup_1_tailSlot_lower},</span></a>
+<a name="485"><span class="lineNum">     485 </span><span class="lineCov">        940 :      1'h0};</span></a>
+<a name="486"><span class="lineNum">     486 </span><span class="lineCov">       1237 :   reg         io_out_s2_full_pred_1_fallThroughAddr_stashed_carry;</span></a>
+<a name="487"><span class="lineNum">     487 </span>            :   reg  [27:0] higher_r_6;</a>
+<a name="488"><span class="lineNum">     488 </span>            :   reg  [27:0] higher_plus_one_r_6;</a>
+<a name="489"><span class="lineNum">     489 </span>            :   reg  [27:0] higher_minus_one_r_6;</a>
+<a name="490"><span class="lineNum">     490 </span><span class="lineCov">        620 :   reg  [27:0] higher_r_7;</span></a>
+<a name="491"><span class="lineNum">     491 </span><span class="lineCov">        635 :   reg  [27:0] higher_plus_one_r_7;</span></a>
+<a name="492"><span class="lineNum">     492 </span><span class="lineCov">        632 :   reg  [27:0] higher_minus_one_r_7;</span></a>
+<a name="493"><span class="lineNum">     493 </span><span class="lineCov">       1198 :   wire        _target_T_72 = s2_ftb_entry_dup_2_tailSlot_tarStat == 2'h1;</span></a>
+<a name="494"><span class="lineNum">     494 </span>            :   wire        _target_T_73 = s2_ftb_entry_dup_2_tailSlot_tarStat == 2'h2;</a>
+<a name="495"><span class="lineNum">     495 </span>            :   wire        _target_T_74 = s2_ftb_entry_dup_2_tailSlot_tarStat == 2'h0;</a>
+<a name="496"><span class="lineNum">     496 </span>            :   reg  [19:0] higher_r_8;</a>
+<a name="497"><span class="lineNum">     497 </span>            :   reg  [19:0] higher_plus_one_r_8;</a>
+<a name="498"><span class="lineNum">     498 </span>            :   reg  [19:0] higher_minus_one_r_8;</a>
+<a name="499"><span class="lineNum">     499 </span>            :   wire [40:0] io_out_s2_full_pred_2_targets_1_0 =</a>
+<a name="500"><span class="lineNum">     500 </span>            :     {s2_ftb_entry_dup_2_tailSlot_sharing</a>
+<a name="501"><span class="lineNum">     501 </span>            :        ? {(_target_T_72 ? higher_plus_one_r_7 : 28'h0)</a>
+<a name="502"><span class="lineNum">     502 </span>            :             | (_target_T_73 ? higher_minus_one_r_7 : 28'h0)</a>
+<a name="503"><span class="lineNum">     503 </span>            :             | (_target_T_74 ? higher_r_7 : 28'h0),</a>
+<a name="504"><span class="lineNum">     504 </span><span class="lineCov">         36 :           s2_ftb_entry_dup_2_tailSlot_lower[11:0]}</span></a>
+<a name="505"><span class="lineNum">     505 </span><span class="lineCov">        885 :        : {(_target_T_72 ? higher_plus_one_r_8 : 20'h0)</span></a>
+<a name="506"><span class="lineNum">     506 </span><span class="lineCov">        946 :             | (_target_T_73 ? higher_minus_one_r_8 : 20'h0)</span></a>
+<a name="507"><span class="lineNum">     507 </span><span class="lineCov">       1185 :             | (_target_T_74 ? higher_r_8 : 20'h0),</span></a>
+<a name="508"><span class="lineNum">     508 </span><span class="lineCov">        900 :           s2_ftb_entry_dup_2_tailSlot_lower},</span></a>
+<a name="509"><span class="lineNum">     509 </span><span class="lineCov">        929 :      1'h0};</span></a>
+<a name="510"><span class="lineNum">     510 </span><span class="lineCov">       1232 :   reg         io_out_s2_full_pred_2_fallThroughAddr_stashed_carry;</span></a>
+<a name="511"><span class="lineNum">     511 </span>            :   reg  [27:0] higher_r_9;</a>
+<a name="512"><span class="lineNum">     512 </span>            :   reg  [27:0] higher_plus_one_r_9;</a>
+<a name="513"><span class="lineNum">     513 </span>            :   reg  [27:0] higher_minus_one_r_9;</a>
+<a name="514"><span class="lineNum">     514 </span><span class="lineCov">        619 :   reg  [27:0] higher_r_10;</span></a>
+<a name="515"><span class="lineNum">     515 </span><span class="lineCov">        609 :   reg  [27:0] higher_plus_one_r_10;</span></a>
+<a name="516"><span class="lineNum">     516 </span><span class="lineCov">        589 :   reg  [27:0] higher_minus_one_r_10;</span></a>
+<a name="517"><span class="lineNum">     517 </span><span class="lineCov">       1179 :   wire        _target_T_99 = s2_ftb_entry_dup_3_tailSlot_tarStat == 2'h1;</span></a>
+<a name="518"><span class="lineNum">     518 </span>            :   wire        _target_T_100 = s2_ftb_entry_dup_3_tailSlot_tarStat == 2'h2;</a>
+<a name="519"><span class="lineNum">     519 </span>            :   wire        _target_T_101 = s2_ftb_entry_dup_3_tailSlot_tarStat == 2'h0;</a>
+<a name="520"><span class="lineNum">     520 </span>            :   reg  [19:0] higher_r_11;</a>
+<a name="521"><span class="lineNum">     521 </span>            :   reg  [19:0] higher_plus_one_r_11;</a>
+<a name="522"><span class="lineNum">     522 </span>            :   reg  [19:0] higher_minus_one_r_11;</a>
+<a name="523"><span class="lineNum">     523 </span>            :   wire [40:0] io_out_s2_full_pred_3_targets_1_0 =</a>
+<a name="524"><span class="lineNum">     524 </span>            :     {s2_ftb_entry_dup_3_tailSlot_sharing</a>
+<a name="525"><span class="lineNum">     525 </span>            :        ? {(_target_T_99 ? higher_plus_one_r_10 : 28'h0)</a>
+<a name="526"><span class="lineNum">     526 </span>            :             | (_target_T_100 ? higher_minus_one_r_10 : 28'h0)</a>
+<a name="527"><span class="lineNum">     527 </span>            :             | (_target_T_101 ? higher_r_10 : 28'h0),</a>
+<a name="528"><span class="lineNum">     528 </span><span class="lineCov">         33 :           s2_ftb_entry_dup_3_tailSlot_lower[11:0]}</span></a>
+<a name="529"><span class="lineNum">     529 </span>            :        : {(_target_T_99 ? higher_plus_one_r_11 : 20'h0)</a>
+<a name="530"><span class="lineNum">     530 </span><span class="lineCov">         31 :             | (_target_T_100 ? higher_minus_one_r_11 : 20'h0)</span></a>
+<a name="531"><span class="lineNum">     531 </span><span class="lineCov">        934 :             | (_target_T_101 ? higher_r_11 : 20'h0),</span></a>
+<a name="532"><span class="lineNum">     532 </span><span class="lineCov">        964 :           s2_ftb_entry_dup_3_tailSlot_lower},</span></a>
+<a name="533"><span class="lineNum">     533 </span><span class="lineCov">       1245 :      1'h0};</span></a>
+<a name="534"><span class="lineNum">     534 </span><span class="lineCov">        912 :   wire        io_out_s2_full_pred_3_fallThroughErr_0 =</span></a>
+<a name="535"><span class="lineNum">     535 </span><span class="lineCov">        975 :     {1'h0, s2_pc_dup_3[4:1]} &gt;= {s2_ftb_entry_dup_3_carry, s2_ftb_entry_dup_3_pftAddr};</span></a>
+<a name="536"><span class="lineNum">     536 </span><span class="lineCov">       1270 :   reg         io_out_s2_full_pred_3_fallThroughAddr_stashed_carry;</span></a>
+<a name="537"><span class="lineNum">     537 </span>            :   reg  [27:0] higher_r_12;</a>
+<a name="538"><span class="lineNum">     538 </span>            :   reg  [27:0] higher_plus_one_r_12;</a>
+<a name="539"><span class="lineNum">     539 </span>            :   reg  [27:0] higher_minus_one_r_12;</a>
+<a name="540"><span class="lineNum">     540 </span><span class="lineCov">        633 :   reg  [27:0] higher_r_13;</span></a>
+<a name="541"><span class="lineNum">     541 </span><span class="lineCov">        652 :   reg  [27:0] higher_plus_one_r_13;</span></a>
+<a name="542"><span class="lineNum">     542 </span><span class="lineCov">        664 :   reg  [27:0] higher_minus_one_r_13;</span></a>
+<a name="543"><span class="lineNum">     543 </span><span class="lineCov">       1247 :   wire        _target_T_126 = s3_ftb_entry_dup_0_tailSlot_tarStat == 2'h1;</span></a>
+<a name="544"><span class="lineNum">     544 </span>            :   wire        _target_T_127 = s3_ftb_entry_dup_0_tailSlot_tarStat == 2'h2;</a>
+<a name="545"><span class="lineNum">     545 </span>            :   wire        _target_T_128 = s3_ftb_entry_dup_0_tailSlot_tarStat == 2'h0;</a>
+<a name="546"><span class="lineNum">     546 </span>            :   reg  [19:0] higher_r_14;</a>
+<a name="547"><span class="lineNum">     547 </span>            :   reg  [19:0] higher_plus_one_r_14;</a>
+<a name="548"><span class="lineNum">     548 </span>            :   reg  [19:0] higher_minus_one_r_14;</a>
+<a name="549"><span class="lineNum">     549 </span>            :   wire [40:0] io_out_s3_full_pred_0_targets_1_0 =</a>
+<a name="550"><span class="lineNum">     550 </span>            :     {s3_ftb_entry_dup_0_tailSlot_sharing</a>
+<a name="551"><span class="lineNum">     551 </span>            :        ? {(_target_T_126 ? higher_plus_one_r_13 : 28'h0)</a>
+<a name="552"><span class="lineNum">     552 </span>            :             | (_target_T_127 ? higher_minus_one_r_13 : 28'h0)</a>
+<a name="553"><span class="lineNum">     553 </span>            :             | (_target_T_128 ? higher_r_13 : 28'h0),</a>
+<a name="554"><span class="lineNum">     554 </span><span class="lineCov">         39 :           s3_ftb_entry_dup_0_tailSlot_lower[11:0]}</span></a>
+<a name="555"><span class="lineNum">     555 </span>            :        : {(_target_T_126 ? higher_plus_one_r_14 : 20'h0)</a>
+<a name="556"><span class="lineNum">     556 </span><span class="lineCov">        935 :             | (_target_T_127 ? higher_minus_one_r_14 : 20'h0)</span></a>
+<a name="557"><span class="lineNum">     557 </span><span class="lineCov">        918 :             | (_target_T_128 ? higher_r_14 : 20'h0),</span></a>
+<a name="558"><span class="lineNum">     558 </span><span class="lineCov">       1240 :           s3_ftb_entry_dup_0_tailSlot_lower},</span></a>
+<a name="559"><span class="lineNum">     559 </span><span class="lineCov">        924 :      1'h0};</span></a>
+<a name="560"><span class="lineNum">     560 </span><span class="lineCov">        937 :   wire        io_out_s3_full_pred_0_fallThroughErr_0 =</span></a>
+<a name="561"><span class="lineNum">     561 </span><span class="lineCov">       1268 :     {1'h0, s3_pc_dup_0[4:1]} &gt;= {s3_ftb_entry_dup_0_carry, s3_ftb_entry_dup_0_pftAddr};</span></a>
+<a name="562"><span class="lineNum">     562 </span>            :   reg  [27:0] higher_r_15;</a>
+<a name="563"><span class="lineNum">     563 </span>            :   reg  [27:0] higher_plus_one_r_15;</a>
+<a name="564"><span class="lineNum">     564 </span>            :   reg  [27:0] higher_minus_one_r_15;</a>
+<a name="565"><span class="lineNum">     565 </span><span class="lineCov">        622 :   reg  [27:0] higher_r_16;</span></a>
+<a name="566"><span class="lineNum">     566 </span><span class="lineCov">        660 :   reg  [27:0] higher_plus_one_r_16;</span></a>
+<a name="567"><span class="lineNum">     567 </span><span class="lineCov">        670 :   reg  [27:0] higher_minus_one_r_16;</span></a>
+<a name="568"><span class="lineNum">     568 </span><span class="lineCov">       1289 :   wire        _target_T_153 = s3_ftb_entry_dup_1_tailSlot_tarStat == 2'h1;</span></a>
+<a name="569"><span class="lineNum">     569 </span>            :   wire        _target_T_154 = s3_ftb_entry_dup_1_tailSlot_tarStat == 2'h2;</a>
+<a name="570"><span class="lineNum">     570 </span>            :   wire        _target_T_155 = s3_ftb_entry_dup_1_tailSlot_tarStat == 2'h0;</a>
+<a name="571"><span class="lineNum">     571 </span>            :   reg  [19:0] higher_r_17;</a>
+<a name="572"><span class="lineNum">     572 </span>            :   reg  [19:0] higher_plus_one_r_17;</a>
+<a name="573"><span class="lineNum">     573 </span>            :   reg  [19:0] higher_minus_one_r_17;</a>
+<a name="574"><span class="lineNum">     574 </span>            :   wire [40:0] io_out_s3_full_pred_1_targets_1_0 =</a>
+<a name="575"><span class="lineNum">     575 </span>            :     {s3_ftb_entry_dup_1_tailSlot_sharing</a>
+<a name="576"><span class="lineNum">     576 </span>            :        ? {(_target_T_153 ? higher_plus_one_r_16 : 28'h0)</a>
+<a name="577"><span class="lineNum">     577 </span>            :             | (_target_T_154 ? higher_minus_one_r_16 : 28'h0)</a>
+<a name="578"><span class="lineNum">     578 </span>            :             | (_target_T_155 ? higher_r_16 : 28'h0),</a>
+<a name="579"><span class="lineNum">     579 </span><span class="lineCov">         35 :           s3_ftb_entry_dup_1_tailSlot_lower[11:0]}</span></a>
+<a name="580"><span class="lineNum">     580 </span>            :        : {(_target_T_153 ? higher_plus_one_r_17 : 20'h0)</a>
+<a name="581"><span class="lineNum">     581 </span><span class="lineCov">        941 :             | (_target_T_154 ? higher_minus_one_r_17 : 20'h0)</span></a>
+<a name="582"><span class="lineNum">     582 </span><span class="lineCov">        943 :             | (_target_T_155 ? higher_r_17 : 20'h0),</span></a>
+<a name="583"><span class="lineNum">     583 </span><span class="lineCov">       1281 :           s3_ftb_entry_dup_1_tailSlot_lower},</span></a>
+<a name="584"><span class="lineNum">     584 </span><span class="lineCov">        945 :      1'h0};</span></a>
+<a name="585"><span class="lineNum">     585 </span><span class="lineCov">        954 :   wire        io_out_s3_full_pred_1_fallThroughErr_0 =</span></a>
+<a name="586"><span class="lineNum">     586 </span><span class="lineCov">       1233 :     {1'h0, s3_pc_dup_1[4:1]} &gt;= {s3_ftb_entry_dup_1_carry, s3_ftb_entry_dup_1_pftAddr};</span></a>
+<a name="587"><span class="lineNum">     587 </span>            :   reg  [27:0] higher_r_18;</a>
+<a name="588"><span class="lineNum">     588 </span>            :   reg  [27:0] higher_plus_one_r_18;</a>
+<a name="589"><span class="lineNum">     589 </span>            :   reg  [27:0] higher_minus_one_r_18;</a>
+<a name="590"><span class="lineNum">     590 </span><span class="lineCov">        632 :   reg  [27:0] higher_r_19;</span></a>
+<a name="591"><span class="lineNum">     591 </span><span class="lineCov">        631 :   reg  [27:0] higher_plus_one_r_19;</span></a>
+<a name="592"><span class="lineNum">     592 </span><span class="lineCov">        629 :   reg  [27:0] higher_minus_one_r_19;</span></a>
+<a name="593"><span class="lineNum">     593 </span><span class="lineCov">       1331 :   wire        _target_T_180 = s3_ftb_entry_dup_2_tailSlot_tarStat == 2'h1;</span></a>
+<a name="594"><span class="lineNum">     594 </span>            :   wire        _target_T_181 = s3_ftb_entry_dup_2_tailSlot_tarStat == 2'h2;</a>
+<a name="595"><span class="lineNum">     595 </span>            :   wire        _target_T_182 = s3_ftb_entry_dup_2_tailSlot_tarStat == 2'h0;</a>
+<a name="596"><span class="lineNum">     596 </span>            :   reg  [19:0] higher_r_20;</a>
+<a name="597"><span class="lineNum">     597 </span>            :   reg  [19:0] higher_plus_one_r_20;</a>
+<a name="598"><span class="lineNum">     598 </span>            :   reg  [19:0] higher_minus_one_r_20;</a>
+<a name="599"><span class="lineNum">     599 </span>            :   wire [40:0] io_out_s3_full_pred_2_targets_1_0 =</a>
+<a name="600"><span class="lineNum">     600 </span>            :     {s3_ftb_entry_dup_2_tailSlot_sharing</a>
+<a name="601"><span class="lineNum">     601 </span>            :        ? {(_target_T_180 ? higher_plus_one_r_19 : 28'h0)</a>
+<a name="602"><span class="lineNum">     602 </span>            :             | (_target_T_181 ? higher_minus_one_r_19 : 28'h0)</a>
+<a name="603"><span class="lineNum">     603 </span>            :             | (_target_T_182 ? higher_r_19 : 28'h0),</a>
+<a name="604"><span class="lineNum">     604 </span><span class="lineCov">         35 :           s3_ftb_entry_dup_2_tailSlot_lower[11:0]}</span></a>
+<a name="605"><span class="lineNum">     605 </span>            :        : {(_target_T_180 ? higher_plus_one_r_20 : 20'h0)</a>
+<a name="606"><span class="lineNum">     606 </span><span class="lineCov">        948 :             | (_target_T_181 ? higher_minus_one_r_20 : 20'h0)</span></a>
+<a name="607"><span class="lineNum">     607 </span><span class="lineCov">        971 :             | (_target_T_182 ? higher_r_20 : 20'h0),</span></a>
+<a name="608"><span class="lineNum">     608 </span><span class="lineCov">       1271 :           s3_ftb_entry_dup_2_tailSlot_lower},</span></a>
+<a name="609"><span class="lineNum">     609 </span><span class="lineCov">        950 :      1'h0};</span></a>
+<a name="610"><span class="lineNum">     610 </span><span class="lineCov">        945 :   wire        io_out_s3_full_pred_2_fallThroughErr_0 =</span></a>
+<a name="611"><span class="lineNum">     611 </span><span class="lineCov">       1268 :     {1'h0, s3_pc_dup_2[4:1]} &gt;= {s3_ftb_entry_dup_2_carry, s3_ftb_entry_dup_2_pftAddr};</span></a>
+<a name="612"><span class="lineNum">     612 </span>            :   reg  [27:0] higher_r_21;</a>
+<a name="613"><span class="lineNum">     613 </span>            :   reg  [27:0] higher_plus_one_r_21;</a>
+<a name="614"><span class="lineNum">     614 </span>            :   reg  [27:0] higher_minus_one_r_21;</a>
+<a name="615"><span class="lineNum">     615 </span><span class="lineCov">        678 :   reg  [27:0] higher_r_22;</span></a>
+<a name="616"><span class="lineNum">     616 </span><span class="lineCov">        644 :   reg  [27:0] higher_plus_one_r_22;</span></a>
+<a name="617"><span class="lineNum">     617 </span><span class="lineCov">        684 :   reg  [27:0] higher_minus_one_r_22;</span></a>
+<a name="618"><span class="lineNum">     618 </span><span class="lineCov">       1247 :   wire        _target_T_207 = s3_ftb_entry_dup_3_tailSlot_tarStat == 2'h1;</span></a>
+<a name="619"><span class="lineNum">     619 </span>            :   wire        _target_T_208 = s3_ftb_entry_dup_3_tailSlot_tarStat == 2'h2;</a>
+<a name="620"><span class="lineNum">     620 </span>            :   wire        _target_T_209 = s3_ftb_entry_dup_3_tailSlot_tarStat == 2'h0;</a>
+<a name="621"><span class="lineNum">     621 </span>            :   reg  [19:0] higher_r_23;</a>
+<a name="622"><span class="lineNum">     622 </span>            :   reg  [19:0] higher_plus_one_r_23;</a>
+<a name="623"><span class="lineNum">     623 </span>            :   reg  [19:0] higher_minus_one_r_23;</a>
+<a name="624"><span class="lineNum">     624 </span>            :   wire [40:0] io_out_s3_full_pred_3_targets_1_0 =</a>
+<a name="625"><span class="lineNum">     625 </span>            :     {s3_ftb_entry_dup_3_tailSlot_sharing</a>
+<a name="626"><span class="lineNum">     626 </span>            :        ? {(_target_T_207 ? higher_plus_one_r_22 : 28'h0)</a>
+<a name="627"><span class="lineNum">     627 </span>            :             | (_target_T_208 ? higher_minus_one_r_22 : 28'h0)</a>
+<a name="628"><span class="lineNum">     628 </span>            :             | (_target_T_209 ? higher_r_22 : 28'h0),</a>
+<a name="629"><span class="lineNum">     629 </span><span class="lineCov">         41 :           s3_ftb_entry_dup_3_tailSlot_lower[11:0]}</span></a>
+<a name="630"><span class="lineNum">     630 </span>            :        : {(_target_T_207 ? higher_plus_one_r_23 : 20'h0)</a>
+<a name="631"><span class="lineNum">     631 </span><span class="lineCov">        104 :             | (_target_T_208 ? higher_minus_one_r_23 : 20'h0)</span></a>
+<a name="632"><span class="lineNum">     632 </span><span class="lineCov">        107 :             | (_target_T_209 ? higher_r_23 : 20'h0),</span></a>
+<a name="633"><span class="lineNum">     633 </span><span class="lineCov">         57 :           s3_ftb_entry_dup_3_tailSlot_lower},</span></a>
+<a name="634"><span class="lineNum">     634 </span><span class="lineCov">         27 :      1'h0};</span></a>
+<a name="635"><span class="lineNum">     635 </span><span class="lineCov">         49 :   wire        io_out_s3_full_pred_3_fallThroughErr_0 =</span></a>
+<a name="636"><span class="lineNum">     636 </span><span class="lineCov">         62 :     {1'h0, s3_pc_dup_3[4:1]} &gt;= {s3_ftb_entry_dup_3_carry, s3_ftb_entry_dup_3_pftAddr};</span></a>
+<a name="637"><span class="lineNum">     637 </span>            :   reg  [2:0]  io_out_last_stage_meta_r;</a>
+<a name="638"><span class="lineNum">     638 </span>            :   reg  [2:0]  io_out_last_stage_meta_r_1;</a>
+<a name="639"><span class="lineNum">     639 </span><span class="lineCov">         55 :   wire        u_valid = io_update_valid &amp; ~io_update_bits_old_entry;</span></a>
+<a name="640"><span class="lineNum">     640 </span><span class="lineCov">         37 :   wire        update_now = u_valid &amp; io_update_bits_meta[0];</span></a>
+<a name="641"><span class="lineNum">     641 </span><span class="lineCov">         41 :   wire        update_need_read = u_valid &amp; ~(io_update_bits_meta[0]);</span></a>
+<a name="642"><span class="lineNum">     642 </span><span class="lineCov">         52 :   reg         io_s1_ready_REG;</span></a>
+<a name="643"><span class="lineNum">     643 </span><span class="lineCov">        110 :   wire [40:0] _ftbBank_io_update_pc_T =</span></a>
+<a name="644"><span class="lineNum">     644 </span><span class="lineCov">        117 :     update_now ? io_update_bits_pc : _delay2_pc_pipMod_io_out_bits;</span></a>
+<a name="645"><span class="lineNum">     645 </span>            :   reg  [1:0]  ftbBank_io_update_write_way_REG;</a>
+<a name="646"><span class="lineNum">     646 </span><span class="lineCov">     127694 :   reg         ftbBank_io_update_write_alloc_REG;</span></a>
+<a name="647"><span class="lineNum">     647 </span><span class="lineCov">        102 :   reg         io_perf_0_value_REG;</span></a>
+<a name="648"><span class="lineNum">     648 </span><span class="lineCov">         51 :   reg         io_perf_0_value_REG_1;</span></a>
+<a name="649"><span class="lineNum">     649 </span><span class="lineCov">         51 :   reg         io_perf_1_value_REG;</span></a>
+<a name="650"><span class="lineNum">     650 </span><span class="lineCov">         51 :   reg         io_perf_1_value_REG_1;</span></a>
+<a name="651"><span class="lineNum">     651 </span><span class="lineCov">         51 :   wire [40:0] _GEN = {5'h0, _reset_vector_delay_io_out};</span></a>
+<a name="652"><span class="lineNum">     652 </span>            :   always @(posedge clock) begin</a>
+<a name="653"><span class="lineNum">     653 </span><span class="lineCov">      63796 :     if (REG_1) begin</span></a>
+<a name="654"><span class="lineNum">     654 </span><span class="lineCov">       8350 :       s1_pc_dup_0 &lt;= _GEN;</span></a>
+<a name="655"><span class="lineNum">     655 </span><span class="lineCov">       4175 :       s1_pc_dup_1 &lt;= _GEN;</span></a>
+<a name="656"><span class="lineNum">     656 </span><span class="lineCov">       8350 :       s1_pc_dup_2 &lt;= _GEN;</span></a>
+<a name="657"><span class="lineNum">     657 </span><span class="lineCov">       4175 :       s1_pc_dup_3 &lt;= _GEN;</span></a>
+<a name="658"><span class="lineNum">     658 </span><span class="lineCov">       8350 :     end</span></a>
+<a name="659"><span class="lineNum">     659 </span><span class="lineCov">       4175 :     else begin</span></a>
+<a name="660"><span class="lineNum">     660 </span><span class="lineCov">       8350 :       if (io_s0_fire_0)</span></a>
+<a name="661"><span class="lineNum">     661 </span><span class="lineCov">       4175 :         s1_pc_dup_0 &lt;= io_in_bits_s0_pc_0;</span></a>
+<a name="662"><span class="lineNum">     662 </span>            :       if (io_s0_fire_1)</a>
+<a name="663"><span class="lineNum">     663 </span><span class="lineCov">       8252 :         s1_pc_dup_1 &lt;= io_in_bits_s0_pc_1;</span></a>
+<a name="664"><span class="lineNum">     664 </span><span class="lineCov">       4126 :       if (io_s0_fire_2)</span></a>
+<a name="665"><span class="lineNum">     665 </span><span class="lineCov">       4126 :         s1_pc_dup_2 &lt;= io_in_bits_s0_pc_2;</span></a>
+<a name="666"><span class="lineNum">     666 </span><span class="lineCov">       4126 :       if (io_s0_fire_3)</span></a>
+<a name="667"><span class="lineNum">     667 </span><span class="lineCov">       4126 :         s1_pc_dup_3 &lt;= io_in_bits_s0_pc_3;</span></a>
+<a name="668"><span class="lineNum">     668 </span><span class="lineCov">       4126 :     end</span></a>
+<a name="669"><span class="lineNum">     669 </span><span class="lineCov">       4126 : </span></a>
+<a name="670"><span class="lineNum">     670 </span><span class="lineCov">       4126 :     if (io_s1_fire_0) begin</span></a>
+<a name="671"><span class="lineNum">     671 </span><span class="lineCov">       4126 :       s2_pc_dup_0 &lt;= s1_pc_dup_0;</span></a>
+<a name="672"><span class="lineNum">     672 </span><span class="lineCov">       4126 :       s2_ftb_entry_dup_0_valid &lt;= _ftbBank_io_read_resp_valid;</span></a>
+<a name="673"><span class="lineNum">     673 </span><span class="lineCov">       4126 :       s2_ftb_entry_dup_0_brSlots_0_offset &lt;= _ftbBank_io_read_resp_brSlots_0_offset;</span></a>
+<a name="674"><span class="lineNum">     674 </span><span class="lineCov">       4126 :       s2_ftb_entry_dup_0_brSlots_0_lower &lt;= _ftbBank_io_read_resp_brSlots_0_lower;</span></a>
+<a name="675"><span class="lineNum">     675 </span><span class="lineCov">       4126 :       s2_ftb_entry_dup_0_brSlots_0_tarStat &lt;= _ftbBank_io_read_resp_brSlots_0_tarStat;</span></a>
+<a name="676"><span class="lineNum">     676 </span><span class="lineCov">       4126 :       s2_ftb_entry_dup_0_brSlots_0_sharing &lt;= _ftbBank_io_read_resp_brSlots_0_sharing;</span></a>
+<a name="677"><span class="lineNum">     677 </span><span class="lineCov">       4126 :       s2_ftb_entry_dup_0_brSlots_0_valid &lt;= _ftbBank_io_read_resp_brSlots_0_valid;</span></a>
+<a name="678"><span class="lineNum">     678 </span><span class="lineCov">       4126 :       s2_ftb_entry_dup_0_tailSlot_offset &lt;= _ftbBank_io_read_resp_tailSlot_offset;</span></a>
+<a name="679"><span class="lineNum">     679 </span><span class="lineCov">       4126 :       s2_ftb_entry_dup_0_tailSlot_lower &lt;= _ftbBank_io_read_resp_tailSlot_lower;</span></a>
+<a name="680"><span class="lineNum">     680 </span><span class="lineCov">       4126 :       s2_ftb_entry_dup_0_tailSlot_tarStat &lt;= _ftbBank_io_read_resp_tailSlot_tarStat;</span></a>
+<a name="681"><span class="lineNum">     681 </span><span class="lineCov">       4126 :       s2_ftb_entry_dup_0_tailSlot_sharing &lt;= _ftbBank_io_read_resp_tailSlot_sharing;</span></a>
+<a name="682"><span class="lineNum">     682 </span><span class="lineCov">       4126 :       s2_ftb_entry_dup_0_tailSlot_valid &lt;= _ftbBank_io_read_resp_tailSlot_valid;</span></a>
+<a name="683"><span class="lineNum">     683 </span><span class="lineCov">       4126 :       s2_ftb_entry_dup_0_pftAddr &lt;= _ftbBank_io_read_resp_pftAddr;</span></a>
+<a name="684"><span class="lineNum">     684 </span><span class="lineCov">       4126 :       s2_ftb_entry_dup_0_carry &lt;= _ftbBank_io_read_resp_carry;</span></a>
+<a name="685"><span class="lineNum">     685 </span><span class="lineCov">       4126 :       s2_ftb_entry_dup_0_isCall &lt;= _ftbBank_io_read_resp_isCall;</span></a>
+<a name="686"><span class="lineNum">     686 </span><span class="lineCov">       4126 :       s2_ftb_entry_dup_0_isRet &lt;= _ftbBank_io_read_resp_isRet;</span></a>
+<a name="687"><span class="lineNum">     687 </span><span class="lineCov">       4126 :       s2_ftb_entry_dup_0_isJalr &lt;= _ftbBank_io_read_resp_isJalr;</span></a>
+<a name="688"><span class="lineNum">     688 </span><span class="lineCov">       4126 :       s2_ftb_entry_dup_0_last_may_be_rvi_call &lt;=</span></a>
+<a name="689"><span class="lineNum">     689 </span><span class="lineCov">       4126 :         _ftbBank_io_read_resp_last_may_be_rvi_call;</span></a>
+<a name="690"><span class="lineNum">     690 </span><span class="lineCov">       4126 :       s2_ftb_entry_dup_0_always_taken_0 &lt;= _ftbBank_io_read_resp_always_taken_0;</span></a>
+<a name="691"><span class="lineNum">     691 </span><span class="lineCov">       4126 :       s2_ftb_entry_dup_0_always_taken_1 &lt;= _ftbBank_io_read_resp_always_taken_1;</span></a>
+<a name="692"><span class="lineNum">     692 </span><span class="lineCov">       4126 :       higher_r &lt;= s1_pc_dup_0[40:13];</span></a>
+<a name="693"><span class="lineNum">     693 </span><span class="lineCov">       4126 :       higher_plus_one_r &lt;= 28'(s1_pc_dup_0[40:13] + 28'h1);</span></a>
+<a name="694"><span class="lineNum">     694 </span><span class="lineCov">       4126 :       higher_minus_one_r &lt;= 28'(s1_pc_dup_0[40:13] - 28'h1);</span></a>
+<a name="695"><span class="lineNum">     695 </span><span class="lineCov">       4126 :       higher_r_1 &lt;= s1_pc_dup_0[40:13];</span></a>
+<a name="696"><span class="lineNum">     696 </span>            :       higher_plus_one_r_1 &lt;= 28'(s1_pc_dup_0[40:13] + 28'h1);</a>
+<a name="697"><span class="lineNum">     697 </span><span class="lineCov">       8252 :       higher_minus_one_r_1 &lt;= 28'(s1_pc_dup_0[40:13] - 28'h1);</span></a>
+<a name="698"><span class="lineNum">     698 </span><span class="lineCov">       4126 :       higher_r_2 &lt;= s1_pc_dup_0[40:21];</span></a>
+<a name="699"><span class="lineNum">     699 </span><span class="lineCov">       4126 :       higher_plus_one_r_2 &lt;= 20'(s1_pc_dup_0[40:21] + 20'h1);</span></a>
+<a name="700"><span class="lineNum">     700 </span><span class="lineCov">       4126 :       higher_minus_one_r_2 &lt;= 20'(s1_pc_dup_0[40:21] - 20'h1);</span></a>
+<a name="701"><span class="lineNum">     701 </span><span class="lineCov">       4126 :       io_out_s2_full_pred_0_fallThroughAddr_stashed_carry &lt;= _ftbBank_io_read_resp_carry;</span></a>
+<a name="702"><span class="lineNum">     702 </span><span class="lineCov">       4126 :       io_out_last_stage_meta_r &lt;= {_ftbBank_io_read_hits_bits, s1_hit};</span></a>
+<a name="703"><span class="lineNum">     703 </span><span class="lineCov">       4126 :     end</span></a>
+<a name="704"><span class="lineNum">     704 </span><span class="lineCov">       4126 :     if (io_s1_fire_1) begin</span></a>
+<a name="705"><span class="lineNum">     705 </span><span class="lineCov">       4126 :       s2_pc_dup_1 &lt;= s1_pc_dup_1;</span></a>
+<a name="706"><span class="lineNum">     706 </span><span class="lineCov">       4126 :       s2_ftb_entry_dup_1_brSlots_0_offset &lt;= _ftbBank_io_read_resp_brSlots_0_offset;</span></a>
+<a name="707"><span class="lineNum">     707 </span><span class="lineCov">       4126 :       s2_ftb_entry_dup_1_brSlots_0_lower &lt;= _ftbBank_io_read_resp_brSlots_0_lower;</span></a>
+<a name="708"><span class="lineNum">     708 </span><span class="lineCov">       4126 :       s2_ftb_entry_dup_1_brSlots_0_tarStat &lt;= _ftbBank_io_read_resp_brSlots_0_tarStat;</span></a>
+<a name="709"><span class="lineNum">     709 </span><span class="lineCov">       4126 :       s2_ftb_entry_dup_1_brSlots_0_valid &lt;= _ftbBank_io_read_resp_brSlots_0_valid;</span></a>
+<a name="710"><span class="lineNum">     710 </span><span class="lineCov">       4126 :       s2_ftb_entry_dup_1_tailSlot_offset &lt;= _ftbBank_io_read_resp_tailSlot_offset;</span></a>
+<a name="711"><span class="lineNum">     711 </span><span class="lineCov">       4126 :       s2_ftb_entry_dup_1_tailSlot_lower &lt;= _ftbBank_io_read_resp_tailSlot_lower;</span></a>
+<a name="712"><span class="lineNum">     712 </span><span class="lineCov">       4126 :       s2_ftb_entry_dup_1_tailSlot_tarStat &lt;= _ftbBank_io_read_resp_tailSlot_tarStat;</span></a>
+<a name="713"><span class="lineNum">     713 </span><span class="lineCov">       4126 :       s2_ftb_entry_dup_1_tailSlot_sharing &lt;= _ftbBank_io_read_resp_tailSlot_sharing;</span></a>
+<a name="714"><span class="lineNum">     714 </span><span class="lineCov">       4126 :       s2_ftb_entry_dup_1_tailSlot_valid &lt;= _ftbBank_io_read_resp_tailSlot_valid;</span></a>
+<a name="715"><span class="lineNum">     715 </span><span class="lineCov">       4126 :       s2_ftb_entry_dup_1_pftAddr &lt;= _ftbBank_io_read_resp_pftAddr;</span></a>
+<a name="716"><span class="lineNum">     716 </span><span class="lineCov">       4126 :       s2_ftb_entry_dup_1_carry &lt;= _ftbBank_io_read_resp_carry;</span></a>
+<a name="717"><span class="lineNum">     717 </span><span class="lineCov">       4126 :       s2_ftb_entry_dup_1_always_taken_0 &lt;= _ftbBank_io_read_resp_always_taken_0;</span></a>
+<a name="718"><span class="lineNum">     718 </span><span class="lineCov">       4126 :       s2_ftb_entry_dup_1_always_taken_1 &lt;= _ftbBank_io_read_resp_always_taken_1;</span></a>
+<a name="719"><span class="lineNum">     719 </span><span class="lineCov">       4126 :       higher_r_3 &lt;= s1_pc_dup_1[40:13];</span></a>
+<a name="720"><span class="lineNum">     720 </span><span class="lineCov">       4126 :       higher_plus_one_r_3 &lt;= 28'(s1_pc_dup_1[40:13] + 28'h1);</span></a>
+<a name="721"><span class="lineNum">     721 </span><span class="lineCov">       4126 :       higher_minus_one_r_3 &lt;= 28'(s1_pc_dup_1[40:13] - 28'h1);</span></a>
+<a name="722"><span class="lineNum">     722 </span>            :       higher_r_4 &lt;= s1_pc_dup_1[40:13];</a>
+<a name="723"><span class="lineNum">     723 </span><span class="lineCov">       8252 :       higher_plus_one_r_4 &lt;= 28'(s1_pc_dup_1[40:13] + 28'h1);</span></a>
+<a name="724"><span class="lineNum">     724 </span><span class="lineCov">       4126 :       higher_minus_one_r_4 &lt;= 28'(s1_pc_dup_1[40:13] - 28'h1);</span></a>
+<a name="725"><span class="lineNum">     725 </span><span class="lineCov">       4126 :       higher_r_5 &lt;= s1_pc_dup_1[40:21];</span></a>
+<a name="726"><span class="lineNum">     726 </span><span class="lineCov">       4126 :       higher_plus_one_r_5 &lt;= 20'(s1_pc_dup_1[40:21] + 20'h1);</span></a>
+<a name="727"><span class="lineNum">     727 </span><span class="lineCov">       4126 :       higher_minus_one_r_5 &lt;= 20'(s1_pc_dup_1[40:21] - 20'h1);</span></a>
+<a name="728"><span class="lineNum">     728 </span><span class="lineCov">       4126 :       io_out_s2_full_pred_1_fallThroughAddr_stashed_carry &lt;= _ftbBank_io_read_resp_carry;</span></a>
+<a name="729"><span class="lineNum">     729 </span><span class="lineCov">       4126 :     end</span></a>
+<a name="730"><span class="lineNum">     730 </span><span class="lineCov">       4126 :     if (io_s1_fire_2) begin</span></a>
+<a name="731"><span class="lineNum">     731 </span><span class="lineCov">       4126 :       s2_pc_dup_2 &lt;= s1_pc_dup_2;</span></a>
+<a name="732"><span class="lineNum">     732 </span><span class="lineCov">       4126 :       s2_ftb_entry_dup_2_brSlots_0_offset &lt;= _ftbBank_io_read_resp_brSlots_0_offset;</span></a>
+<a name="733"><span class="lineNum">     733 </span><span class="lineCov">       4126 :       s2_ftb_entry_dup_2_brSlots_0_lower &lt;= _ftbBank_io_read_resp_brSlots_0_lower;</span></a>
+<a name="734"><span class="lineNum">     734 </span><span class="lineCov">       4126 :       s2_ftb_entry_dup_2_brSlots_0_tarStat &lt;= _ftbBank_io_read_resp_brSlots_0_tarStat;</span></a>
+<a name="735"><span class="lineNum">     735 </span><span class="lineCov">       4126 :       s2_ftb_entry_dup_2_brSlots_0_valid &lt;= _ftbBank_io_read_resp_brSlots_0_valid;</span></a>
+<a name="736"><span class="lineNum">     736 </span><span class="lineCov">       4126 :       s2_ftb_entry_dup_2_tailSlot_offset &lt;= _ftbBank_io_read_resp_tailSlot_offset;</span></a>
+<a name="737"><span class="lineNum">     737 </span><span class="lineCov">       4126 :       s2_ftb_entry_dup_2_tailSlot_lower &lt;= _ftbBank_io_read_resp_tailSlot_lower;</span></a>
+<a name="738"><span class="lineNum">     738 </span><span class="lineCov">       4126 :       s2_ftb_entry_dup_2_tailSlot_tarStat &lt;= _ftbBank_io_read_resp_tailSlot_tarStat;</span></a>
+<a name="739"><span class="lineNum">     739 </span><span class="lineCov">       4126 :       s2_ftb_entry_dup_2_tailSlot_sharing &lt;= _ftbBank_io_read_resp_tailSlot_sharing;</span></a>
+<a name="740"><span class="lineNum">     740 </span><span class="lineCov">       4126 :       s2_ftb_entry_dup_2_tailSlot_valid &lt;= _ftbBank_io_read_resp_tailSlot_valid;</span></a>
+<a name="741"><span class="lineNum">     741 </span><span class="lineCov">       4126 :       s2_ftb_entry_dup_2_pftAddr &lt;= _ftbBank_io_read_resp_pftAddr;</span></a>
+<a name="742"><span class="lineNum">     742 </span><span class="lineCov">       4126 :       s2_ftb_entry_dup_2_carry &lt;= _ftbBank_io_read_resp_carry;</span></a>
+<a name="743"><span class="lineNum">     743 </span><span class="lineCov">       4126 :       s2_ftb_entry_dup_2_isCall &lt;= _ftbBank_io_read_resp_isCall;</span></a>
+<a name="744"><span class="lineNum">     744 </span><span class="lineCov">       4126 :       s2_ftb_entry_dup_2_isRet &lt;= _ftbBank_io_read_resp_isRet;</span></a>
+<a name="745"><span class="lineNum">     745 </span><span class="lineCov">       4126 :       s2_ftb_entry_dup_2_isJalr &lt;= _ftbBank_io_read_resp_isJalr;</span></a>
+<a name="746"><span class="lineNum">     746 </span><span class="lineCov">       4126 :       s2_ftb_entry_dup_2_last_may_be_rvi_call &lt;=</span></a>
+<a name="747"><span class="lineNum">     747 </span><span class="lineCov">       4126 :         _ftbBank_io_read_resp_last_may_be_rvi_call;</span></a>
+<a name="748"><span class="lineNum">     748 </span><span class="lineCov">       4126 :       s2_ftb_entry_dup_2_always_taken_0 &lt;= _ftbBank_io_read_resp_always_taken_0;</span></a>
+<a name="749"><span class="lineNum">     749 </span><span class="lineCov">       4126 :       s2_ftb_entry_dup_2_always_taken_1 &lt;= _ftbBank_io_read_resp_always_taken_1;</span></a>
+<a name="750"><span class="lineNum">     750 </span><span class="lineCov">       4126 :       higher_r_6 &lt;= s1_pc_dup_2[40:13];</span></a>
+<a name="751"><span class="lineNum">     751 </span><span class="lineCov">       4126 :       higher_plus_one_r_6 &lt;= 28'(s1_pc_dup_2[40:13] + 28'h1);</span></a>
+<a name="752"><span class="lineNum">     752 </span><span class="lineCov">       4126 :       higher_minus_one_r_6 &lt;= 28'(s1_pc_dup_2[40:13] - 28'h1);</span></a>
+<a name="753"><span class="lineNum">     753 </span>            :       higher_r_7 &lt;= s1_pc_dup_2[40:13];</a>
+<a name="754"><span class="lineNum">     754 </span><span class="lineCov">       8252 :       higher_plus_one_r_7 &lt;= 28'(s1_pc_dup_2[40:13] + 28'h1);</span></a>
+<a name="755"><span class="lineNum">     755 </span><span class="lineCov">       4126 :       higher_minus_one_r_7 &lt;= 28'(s1_pc_dup_2[40:13] - 28'h1);</span></a>
+<a name="756"><span class="lineNum">     756 </span><span class="lineCov">       4126 :       higher_r_8 &lt;= s1_pc_dup_2[40:21];</span></a>
+<a name="757"><span class="lineNum">     757 </span><span class="lineCov">       4126 :       higher_plus_one_r_8 &lt;= 20'(s1_pc_dup_2[40:21] + 20'h1);</span></a>
+<a name="758"><span class="lineNum">     758 </span><span class="lineCov">       4126 :       higher_minus_one_r_8 &lt;= 20'(s1_pc_dup_2[40:21] - 20'h1);</span></a>
+<a name="759"><span class="lineNum">     759 </span><span class="lineCov">       4126 :       io_out_s2_full_pred_2_fallThroughAddr_stashed_carry &lt;= _ftbBank_io_read_resp_carry;</span></a>
+<a name="760"><span class="lineNum">     760 </span><span class="lineCov">       4126 :     end</span></a>
+<a name="761"><span class="lineNum">     761 </span><span class="lineCov">       4126 :     if (io_s1_fire_3) begin</span></a>
+<a name="762"><span class="lineNum">     762 </span><span class="lineCov">       4126 :       s2_pc_dup_3 &lt;= s1_pc_dup_3;</span></a>
+<a name="763"><span class="lineNum">     763 </span><span class="lineCov">       4126 :       s2_ftb_entry_dup_3_brSlots_0_offset &lt;= _ftbBank_io_read_resp_brSlots_0_offset;</span></a>
+<a name="764"><span class="lineNum">     764 </span><span class="lineCov">       4126 :       s2_ftb_entry_dup_3_brSlots_0_lower &lt;= _ftbBank_io_read_resp_brSlots_0_lower;</span></a>
+<a name="765"><span class="lineNum">     765 </span><span class="lineCov">       4126 :       s2_ftb_entry_dup_3_brSlots_0_tarStat &lt;= _ftbBank_io_read_resp_brSlots_0_tarStat;</span></a>
+<a name="766"><span class="lineNum">     766 </span><span class="lineCov">       4126 :       s2_ftb_entry_dup_3_brSlots_0_valid &lt;= _ftbBank_io_read_resp_brSlots_0_valid;</span></a>
+<a name="767"><span class="lineNum">     767 </span><span class="lineCov">       4126 :       s2_ftb_entry_dup_3_tailSlot_offset &lt;= _ftbBank_io_read_resp_tailSlot_offset;</span></a>
+<a name="768"><span class="lineNum">     768 </span><span class="lineCov">       4126 :       s2_ftb_entry_dup_3_tailSlot_lower &lt;= _ftbBank_io_read_resp_tailSlot_lower;</span></a>
+<a name="769"><span class="lineNum">     769 </span><span class="lineCov">       4126 :       s2_ftb_entry_dup_3_tailSlot_tarStat &lt;= _ftbBank_io_read_resp_tailSlot_tarStat;</span></a>
+<a name="770"><span class="lineNum">     770 </span><span class="lineCov">       4126 :       s2_ftb_entry_dup_3_tailSlot_sharing &lt;= _ftbBank_io_read_resp_tailSlot_sharing;</span></a>
+<a name="771"><span class="lineNum">     771 </span><span class="lineCov">       4126 :       s2_ftb_entry_dup_3_tailSlot_valid &lt;= _ftbBank_io_read_resp_tailSlot_valid;</span></a>
+<a name="772"><span class="lineNum">     772 </span><span class="lineCov">       4126 :       s2_ftb_entry_dup_3_pftAddr &lt;= _ftbBank_io_read_resp_pftAddr;</span></a>
+<a name="773"><span class="lineNum">     773 </span><span class="lineCov">       4126 :       s2_ftb_entry_dup_3_carry &lt;= _ftbBank_io_read_resp_carry;</span></a>
+<a name="774"><span class="lineNum">     774 </span><span class="lineCov">       4126 :       s2_ftb_entry_dup_3_always_taken_0 &lt;= _ftbBank_io_read_resp_always_taken_0;</span></a>
+<a name="775"><span class="lineNum">     775 </span><span class="lineCov">       4126 :       s2_ftb_entry_dup_3_always_taken_1 &lt;= _ftbBank_io_read_resp_always_taken_1;</span></a>
+<a name="776"><span class="lineNum">     776 </span><span class="lineCov">       4126 :       higher_r_9 &lt;= s1_pc_dup_3[40:13];</span></a>
+<a name="777"><span class="lineNum">     777 </span><span class="lineCov">       4126 :       higher_plus_one_r_9 &lt;= 28'(s1_pc_dup_3[40:13] + 28'h1);</span></a>
+<a name="778"><span class="lineNum">     778 </span><span class="lineCov">       4126 :       higher_minus_one_r_9 &lt;= 28'(s1_pc_dup_3[40:13] - 28'h1);</span></a>
+<a name="779"><span class="lineNum">     779 </span>            :       higher_r_10 &lt;= s1_pc_dup_3[40:13];</a>
+<a name="780"><span class="lineNum">     780 </span><span class="lineCov">       8150 :       higher_plus_one_r_10 &lt;= 28'(s1_pc_dup_3[40:13] + 28'h1);</span></a>
+<a name="781"><span class="lineNum">     781 </span><span class="lineCov">       4075 :       higher_minus_one_r_10 &lt;= 28'(s1_pc_dup_3[40:13] - 28'h1);</span></a>
+<a name="782"><span class="lineNum">     782 </span><span class="lineCov">       4075 :       higher_r_11 &lt;= s1_pc_dup_3[40:21];</span></a>
+<a name="783"><span class="lineNum">     783 </span><span class="lineCov">       4075 :       higher_plus_one_r_11 &lt;= 20'(s1_pc_dup_3[40:21] + 20'h1);</span></a>
+<a name="784"><span class="lineNum">     784 </span><span class="lineCov">       4075 :       higher_minus_one_r_11 &lt;= 20'(s1_pc_dup_3[40:21] - 20'h1);</span></a>
+<a name="785"><span class="lineNum">     785 </span><span class="lineCov">       4075 :       io_out_s2_full_pred_3_fallThroughAddr_stashed_carry &lt;= _ftbBank_io_read_resp_carry;</span></a>
+<a name="786"><span class="lineNum">     786 </span><span class="lineCov">       4075 :     end</span></a>
+<a name="787"><span class="lineNum">     787 </span><span class="lineCov">       4075 : </span></a>
+<a name="788"><span class="lineNum">     788 </span><span class="lineCov">       4075 :     if (io_s2_fire_0) begin</span></a>
+<a name="789"><span class="lineNum">     789 </span><span class="lineCov">       4075 :       s3_pc_dup_0 &lt;= s2_pc_dup_0;</span></a>
+<a name="790"><span class="lineNum">     790 </span><span class="lineCov">       4075 :       s3_ftb_entry_dup_0_valid &lt;= s2_ftb_entry_dup_0_valid;</span></a>
+<a name="791"><span class="lineNum">     791 </span><span class="lineCov">       4075 :       s3_ftb_entry_dup_0_brSlots_0_offset &lt;= s2_ftb_entry_dup_0_brSlots_0_offset;</span></a>
+<a name="792"><span class="lineNum">     792 </span><span class="lineCov">       4075 :       s3_ftb_entry_dup_0_brSlots_0_lower &lt;= s2_ftb_entry_dup_0_brSlots_0_lower;</span></a>
+<a name="793"><span class="lineNum">     793 </span><span class="lineCov">       4075 :       s3_ftb_entry_dup_0_brSlots_0_tarStat &lt;= s2_ftb_entry_dup_0_brSlots_0_tarStat;</span></a>
+<a name="794"><span class="lineNum">     794 </span><span class="lineCov">       4075 :       s3_ftb_entry_dup_0_brSlots_0_sharing &lt;= s2_ftb_entry_dup_0_brSlots_0_sharing;</span></a>
+<a name="795"><span class="lineNum">     795 </span><span class="lineCov">       4075 :       s3_ftb_entry_dup_0_brSlots_0_valid &lt;= s2_ftb_entry_dup_0_brSlots_0_valid;</span></a>
+<a name="796"><span class="lineNum">     796 </span><span class="lineCov">       4075 :       s3_ftb_entry_dup_0_tailSlot_offset &lt;= s2_ftb_entry_dup_0_tailSlot_offset;</span></a>
+<a name="797"><span class="lineNum">     797 </span><span class="lineCov">       4075 :       s3_ftb_entry_dup_0_tailSlot_lower &lt;= s2_ftb_entry_dup_0_tailSlot_lower;</span></a>
+<a name="798"><span class="lineNum">     798 </span><span class="lineCov">       4075 :       s3_ftb_entry_dup_0_tailSlot_tarStat &lt;= s2_ftb_entry_dup_0_tailSlot_tarStat;</span></a>
+<a name="799"><span class="lineNum">     799 </span><span class="lineCov">       4075 :       s3_ftb_entry_dup_0_tailSlot_sharing &lt;= s2_ftb_entry_dup_0_tailSlot_sharing;</span></a>
+<a name="800"><span class="lineNum">     800 </span><span class="lineCov">       4075 :       s3_ftb_entry_dup_0_tailSlot_valid &lt;= s2_ftb_entry_dup_0_tailSlot_valid;</span></a>
+<a name="801"><span class="lineNum">     801 </span><span class="lineCov">       4075 :       s3_ftb_entry_dup_0_pftAddr &lt;= s2_ftb_entry_dup_0_pftAddr;</span></a>
+<a name="802"><span class="lineNum">     802 </span><span class="lineCov">       4075 :       s3_ftb_entry_dup_0_carry &lt;= s2_ftb_entry_dup_0_carry;</span></a>
+<a name="803"><span class="lineNum">     803 </span><span class="lineCov">       4075 :       s3_ftb_entry_dup_0_isCall &lt;= s2_ftb_entry_dup_0_isCall;</span></a>
+<a name="804"><span class="lineNum">     804 </span><span class="lineCov">       4075 :       s3_ftb_entry_dup_0_isRet &lt;= s2_ftb_entry_dup_0_isRet;</span></a>
+<a name="805"><span class="lineNum">     805 </span><span class="lineCov">       4075 :       s3_ftb_entry_dup_0_isJalr &lt;= s2_ftb_entry_dup_0_isJalr;</span></a>
+<a name="806"><span class="lineNum">     806 </span><span class="lineCov">       4075 :       s3_ftb_entry_dup_0_last_may_be_rvi_call &lt;= s2_ftb_entry_dup_0_last_may_be_rvi_call;</span></a>
+<a name="807"><span class="lineNum">     807 </span><span class="lineCov">       4075 :       s3_ftb_entry_dup_0_always_taken_0 &lt;= s2_ftb_entry_dup_0_always_taken_0;</span></a>
+<a name="808"><span class="lineNum">     808 </span><span class="lineCov">       4075 :       s3_ftb_entry_dup_0_always_taken_1 &lt;= s2_ftb_entry_dup_0_always_taken_1;</span></a>
+<a name="809"><span class="lineNum">     809 </span><span class="lineCov">       4075 :       higher_r_12 &lt;= s2_pc_dup_0[40:13];</span></a>
+<a name="810"><span class="lineNum">     810 </span><span class="lineCov">       4075 :       higher_plus_one_r_12 &lt;= 28'(s2_pc_dup_0[40:13] + 28'h1);</span></a>
+<a name="811"><span class="lineNum">     811 </span>            :       higher_minus_one_r_12 &lt;= 28'(s2_pc_dup_0[40:13] - 28'h1);</a>
+<a name="812"><span class="lineNum">     812 </span><span class="lineCov">       8150 :       higher_r_13 &lt;= s2_pc_dup_0[40:13];</span></a>
+<a name="813"><span class="lineNum">     813 </span><span class="lineCov">       4075 :       higher_plus_one_r_13 &lt;= 28'(s2_pc_dup_0[40:13] + 28'h1);</span></a>
+<a name="814"><span class="lineNum">     814 </span><span class="lineCov">       4075 :       higher_minus_one_r_13 &lt;= 28'(s2_pc_dup_0[40:13] - 28'h1);</span></a>
+<a name="815"><span class="lineNum">     815 </span><span class="lineCov">       4075 :       higher_r_14 &lt;= s2_pc_dup_0[40:21];</span></a>
+<a name="816"><span class="lineNum">     816 </span><span class="lineCov">       4075 :       higher_plus_one_r_14 &lt;= 20'(s2_pc_dup_0[40:21] + 20'h1);</span></a>
+<a name="817"><span class="lineNum">     817 </span><span class="lineCov">       4075 :       higher_minus_one_r_14 &lt;= 20'(s2_pc_dup_0[40:21] - 20'h1);</span></a>
+<a name="818"><span class="lineNum">     818 </span><span class="lineCov">       4075 :       io_out_last_stage_meta_r_1 &lt;= io_out_last_stage_meta_r;</span></a>
+<a name="819"><span class="lineNum">     819 </span><span class="lineCov">       4075 :     end</span></a>
+<a name="820"><span class="lineNum">     820 </span><span class="lineCov">       4075 :     if (io_s2_fire_1) begin</span></a>
+<a name="821"><span class="lineNum">     821 </span><span class="lineCov">       4075 :       s3_pc_dup_1 &lt;= s2_pc_dup_1;</span></a>
+<a name="822"><span class="lineNum">     822 </span><span class="lineCov">       4075 :       s3_ftb_entry_dup_1_brSlots_0_lower &lt;= s2_ftb_entry_dup_1_brSlots_0_lower;</span></a>
+<a name="823"><span class="lineNum">     823 </span><span class="lineCov">       4075 :       s3_ftb_entry_dup_1_brSlots_0_tarStat &lt;= s2_ftb_entry_dup_1_brSlots_0_tarStat;</span></a>
+<a name="824"><span class="lineNum">     824 </span><span class="lineCov">       4075 :       s3_ftb_entry_dup_1_brSlots_0_valid &lt;= s2_ftb_entry_dup_1_brSlots_0_valid;</span></a>
+<a name="825"><span class="lineNum">     825 </span><span class="lineCov">       4075 :       s3_ftb_entry_dup_1_tailSlot_lower &lt;= s2_ftb_entry_dup_1_tailSlot_lower;</span></a>
+<a name="826"><span class="lineNum">     826 </span><span class="lineCov">       4075 :       s3_ftb_entry_dup_1_tailSlot_tarStat &lt;= s2_ftb_entry_dup_1_tailSlot_tarStat;</span></a>
+<a name="827"><span class="lineNum">     827 </span><span class="lineCov">       4075 :       s3_ftb_entry_dup_1_tailSlot_sharing &lt;= s2_ftb_entry_dup_1_tailSlot_sharing;</span></a>
+<a name="828"><span class="lineNum">     828 </span><span class="lineCov">       4075 :       s3_ftb_entry_dup_1_tailSlot_valid &lt;= s2_ftb_entry_dup_1_tailSlot_valid;</span></a>
+<a name="829"><span class="lineNum">     829 </span><span class="lineCov">       4075 :       s3_ftb_entry_dup_1_pftAddr &lt;= s2_ftb_entry_dup_1_pftAddr;</span></a>
+<a name="830"><span class="lineNum">     830 </span><span class="lineCov">       4075 :       s3_ftb_entry_dup_1_carry &lt;= s2_ftb_entry_dup_1_carry;</span></a>
+<a name="831"><span class="lineNum">     831 </span><span class="lineCov">       4075 :       s3_ftb_entry_dup_1_always_taken_0 &lt;= s2_ftb_entry_dup_1_always_taken_0;</span></a>
+<a name="832"><span class="lineNum">     832 </span><span class="lineCov">       4075 :       s3_ftb_entry_dup_1_always_taken_1 &lt;= s2_ftb_entry_dup_1_always_taken_1;</span></a>
+<a name="833"><span class="lineNum">     833 </span><span class="lineCov">       4075 :       higher_r_15 &lt;= s2_pc_dup_1[40:13];</span></a>
+<a name="834"><span class="lineNum">     834 </span>            :       higher_plus_one_r_15 &lt;= 28'(s2_pc_dup_1[40:13] + 28'h1);</a>
+<a name="835"><span class="lineNum">     835 </span><span class="lineCov">       8150 :       higher_minus_one_r_15 &lt;= 28'(s2_pc_dup_1[40:13] - 28'h1);</span></a>
+<a name="836"><span class="lineNum">     836 </span><span class="lineCov">       4075 :       higher_r_16 &lt;= s2_pc_dup_1[40:13];</span></a>
+<a name="837"><span class="lineNum">     837 </span><span class="lineCov">       4075 :       higher_plus_one_r_16 &lt;= 28'(s2_pc_dup_1[40:13] + 28'h1);</span></a>
+<a name="838"><span class="lineNum">     838 </span><span class="lineCov">       4075 :       higher_minus_one_r_16 &lt;= 28'(s2_pc_dup_1[40:13] - 28'h1);</span></a>
+<a name="839"><span class="lineNum">     839 </span><span class="lineCov">       4075 :       higher_r_17 &lt;= s2_pc_dup_1[40:21];</span></a>
+<a name="840"><span class="lineNum">     840 </span><span class="lineCov">       4075 :       higher_plus_one_r_17 &lt;= 20'(s2_pc_dup_1[40:21] + 20'h1);</span></a>
+<a name="841"><span class="lineNum">     841 </span><span class="lineCov">       4075 :       higher_minus_one_r_17 &lt;= 20'(s2_pc_dup_1[40:21] - 20'h1);</span></a>
+<a name="842"><span class="lineNum">     842 </span><span class="lineCov">       4075 :     end</span></a>
+<a name="843"><span class="lineNum">     843 </span><span class="lineCov">       4075 :     if (io_s2_fire_2) begin</span></a>
+<a name="844"><span class="lineNum">     844 </span><span class="lineCov">       4075 :       s3_pc_dup_2 &lt;= s2_pc_dup_2;</span></a>
+<a name="845"><span class="lineNum">     845 </span><span class="lineCov">       4075 :       s3_ftb_entry_dup_2_brSlots_0_lower &lt;= s2_ftb_entry_dup_2_brSlots_0_lower;</span></a>
+<a name="846"><span class="lineNum">     846 </span><span class="lineCov">       4075 :       s3_ftb_entry_dup_2_brSlots_0_tarStat &lt;= s2_ftb_entry_dup_2_brSlots_0_tarStat;</span></a>
+<a name="847"><span class="lineNum">     847 </span><span class="lineCov">       4075 :       s3_ftb_entry_dup_2_brSlots_0_valid &lt;= s2_ftb_entry_dup_2_brSlots_0_valid;</span></a>
+<a name="848"><span class="lineNum">     848 </span><span class="lineCov">       4075 :       s3_ftb_entry_dup_2_tailSlot_lower &lt;= s2_ftb_entry_dup_2_tailSlot_lower;</span></a>
+<a name="849"><span class="lineNum">     849 </span><span class="lineCov">       4075 :       s3_ftb_entry_dup_2_tailSlot_tarStat &lt;= s2_ftb_entry_dup_2_tailSlot_tarStat;</span></a>
+<a name="850"><span class="lineNum">     850 </span><span class="lineCov">       4075 :       s3_ftb_entry_dup_2_tailSlot_sharing &lt;= s2_ftb_entry_dup_2_tailSlot_sharing;</span></a>
+<a name="851"><span class="lineNum">     851 </span><span class="lineCov">       4075 :       s3_ftb_entry_dup_2_tailSlot_valid &lt;= s2_ftb_entry_dup_2_tailSlot_valid;</span></a>
+<a name="852"><span class="lineNum">     852 </span><span class="lineCov">       4075 :       s3_ftb_entry_dup_2_pftAddr &lt;= s2_ftb_entry_dup_2_pftAddr;</span></a>
+<a name="853"><span class="lineNum">     853 </span><span class="lineCov">       4075 :       s3_ftb_entry_dup_2_carry &lt;= s2_ftb_entry_dup_2_carry;</span></a>
+<a name="854"><span class="lineNum">     854 </span><span class="lineCov">       4075 :       s3_ftb_entry_dup_2_isCall &lt;= s2_ftb_entry_dup_2_isCall;</span></a>
+<a name="855"><span class="lineNum">     855 </span><span class="lineCov">       4075 :       s3_ftb_entry_dup_2_isRet &lt;= s2_ftb_entry_dup_2_isRet;</span></a>
+<a name="856"><span class="lineNum">     856 </span><span class="lineCov">       4075 :       s3_ftb_entry_dup_2_isJalr &lt;= s2_ftb_entry_dup_2_isJalr;</span></a>
+<a name="857"><span class="lineNum">     857 </span><span class="lineCov">       4075 :       s3_ftb_entry_dup_2_always_taken_0 &lt;= s2_ftb_entry_dup_2_always_taken_0;</span></a>
+<a name="858"><span class="lineNum">     858 </span><span class="lineCov">       4075 :       s3_ftb_entry_dup_2_always_taken_1 &lt;= s2_ftb_entry_dup_2_always_taken_1;</span></a>
+<a name="859"><span class="lineNum">     859 </span><span class="lineCov">       4075 :       higher_r_18 &lt;= s2_pc_dup_2[40:13];</span></a>
+<a name="860"><span class="lineNum">     860 </span>            :       higher_plus_one_r_18 &lt;= 28'(s2_pc_dup_2[40:13] + 28'h1);</a>
+<a name="861"><span class="lineNum">     861 </span><span class="lineCov">       8150 :       higher_minus_one_r_18 &lt;= 28'(s2_pc_dup_2[40:13] - 28'h1);</span></a>
+<a name="862"><span class="lineNum">     862 </span><span class="lineCov">       4075 :       higher_r_19 &lt;= s2_pc_dup_2[40:13];</span></a>
+<a name="863"><span class="lineNum">     863 </span><span class="lineCov">       4075 :       higher_plus_one_r_19 &lt;= 28'(s2_pc_dup_2[40:13] + 28'h1);</span></a>
+<a name="864"><span class="lineNum">     864 </span><span class="lineCov">       4075 :       higher_minus_one_r_19 &lt;= 28'(s2_pc_dup_2[40:13] - 28'h1);</span></a>
+<a name="865"><span class="lineNum">     865 </span><span class="lineCov">       4075 :       higher_r_20 &lt;= s2_pc_dup_2[40:21];</span></a>
+<a name="866"><span class="lineNum">     866 </span><span class="lineCov">       4075 :       higher_plus_one_r_20 &lt;= 20'(s2_pc_dup_2[40:21] + 20'h1);</span></a>
+<a name="867"><span class="lineNum">     867 </span><span class="lineCov">       4075 :       higher_minus_one_r_20 &lt;= 20'(s2_pc_dup_2[40:21] - 20'h1);</span></a>
+<a name="868"><span class="lineNum">     868 </span><span class="lineCov">       4075 :     end</span></a>
+<a name="869"><span class="lineNum">     869 </span><span class="lineCov">       4075 :     if (io_s2_fire_3) begin</span></a>
+<a name="870"><span class="lineNum">     870 </span><span class="lineCov">       4075 :       s3_pc_dup_3 &lt;= s2_pc_dup_3;</span></a>
+<a name="871"><span class="lineNum">     871 </span><span class="lineCov">       4075 :       s3_ftb_entry_dup_3_brSlots_0_offset &lt;= s2_ftb_entry_dup_3_brSlots_0_offset;</span></a>
+<a name="872"><span class="lineNum">     872 </span><span class="lineCov">       4075 :       s3_ftb_entry_dup_3_brSlots_0_lower &lt;= s2_ftb_entry_dup_3_brSlots_0_lower;</span></a>
+<a name="873"><span class="lineNum">     873 </span><span class="lineCov">       4075 :       s3_ftb_entry_dup_3_brSlots_0_tarStat &lt;= s2_ftb_entry_dup_3_brSlots_0_tarStat;</span></a>
+<a name="874"><span class="lineNum">     874 </span><span class="lineCov">       4075 :       s3_ftb_entry_dup_3_brSlots_0_valid &lt;= s2_ftb_entry_dup_3_brSlots_0_valid;</span></a>
+<a name="875"><span class="lineNum">     875 </span><span class="lineCov">       4075 :       s3_ftb_entry_dup_3_tailSlot_offset &lt;= s2_ftb_entry_dup_3_tailSlot_offset;</span></a>
+<a name="876"><span class="lineNum">     876 </span><span class="lineCov">       4075 :       s3_ftb_entry_dup_3_tailSlot_lower &lt;= s2_ftb_entry_dup_3_tailSlot_lower;</span></a>
+<a name="877"><span class="lineNum">     877 </span><span class="lineCov">       4075 :       s3_ftb_entry_dup_3_tailSlot_tarStat &lt;= s2_ftb_entry_dup_3_tailSlot_tarStat;</span></a>
+<a name="878"><span class="lineNum">     878 </span><span class="lineCov">       4075 :       s3_ftb_entry_dup_3_tailSlot_sharing &lt;= s2_ftb_entry_dup_3_tailSlot_sharing;</span></a>
+<a name="879"><span class="lineNum">     879 </span><span class="lineCov">       4075 :       s3_ftb_entry_dup_3_tailSlot_valid &lt;= s2_ftb_entry_dup_3_tailSlot_valid;</span></a>
+<a name="880"><span class="lineNum">     880 </span><span class="lineCov">       4075 :       s3_ftb_entry_dup_3_pftAddr &lt;= s2_ftb_entry_dup_3_pftAddr;</span></a>
+<a name="881"><span class="lineNum">     881 </span><span class="lineCov">       4075 :       s3_ftb_entry_dup_3_carry &lt;= s2_ftb_entry_dup_3_carry;</span></a>
+<a name="882"><span class="lineNum">     882 </span><span class="lineCov">       4075 :       s3_ftb_entry_dup_3_always_taken_0 &lt;= s2_ftb_entry_dup_3_always_taken_0;</span></a>
+<a name="883"><span class="lineNum">     883 </span><span class="lineCov">       4075 :       s3_ftb_entry_dup_3_always_taken_1 &lt;= s2_ftb_entry_dup_3_always_taken_1;</span></a>
+<a name="884"><span class="lineNum">     884 </span><span class="lineCov">       4075 :       higher_r_21 &lt;= s2_pc_dup_3[40:13];</span></a>
+<a name="885"><span class="lineNum">     885 </span>            :       higher_plus_one_r_21 &lt;= 28'(s2_pc_dup_3[40:13] + 28'h1);</a>
+<a name="886"><span class="lineNum">     886 </span><span class="lineCov">      63847 :       higher_minus_one_r_21 &lt;= 28'(s2_pc_dup_3[40:13] - 28'h1);</span></a>
+<a name="887"><span class="lineNum">     887 </span><span class="lineCov">      63847 :       higher_r_22 &lt;= s2_pc_dup_3[40:13];</span></a>
+<a name="888"><span class="lineNum">     888 </span><span class="lineCov">      63847 :       higher_plus_one_r_22 &lt;= 28'(s2_pc_dup_3[40:13] + 28'h1);</span></a>
+<a name="889"><span class="lineNum">     889 </span><span class="lineCov">      63847 :       higher_minus_one_r_22 &lt;= 28'(s2_pc_dup_3[40:13] - 28'h1);</span></a>
+<a name="890"><span class="lineNum">     890 </span><span class="lineCov">      63847 :       higher_r_23 &lt;= s2_pc_dup_3[40:21];</span></a>
+<a name="891"><span class="lineNum">     891 </span><span class="lineCov">      63847 :       higher_plus_one_r_23 &lt;= 20'(s2_pc_dup_3[40:21] + 20'h1);</span></a>
+<a name="892"><span class="lineNum">     892 </span><span class="lineCov">      63847 :       higher_minus_one_r_23 &lt;= 20'(s2_pc_dup_3[40:21] - 20'h1);</span></a>
+<a name="893"><span class="lineNum">     893 </span><span class="lineCov">      63847 :     end</span></a>
+<a name="894"><span class="lineNum">     894 </span><span class="lineCov">      63847 : </span></a>
+<a name="895"><span class="lineNum">     895 </span>            :     REG &lt;= reset;</a>
+<a name="896"><span class="lineNum">     896 </span><span class="lineCov">     127730 :     REG_1 &lt;= REG &amp; ~reset;       //for get the pulse </span></a>
+<a name="897"><span class="lineNum">     897 </span><span class="lineCov">        272 : </span></a>
+<a name="898"><span class="lineNum">     898 </span><span class="lineCov">        136 :     io_s1_ready_REG &lt;= update_need_read;</span></a>
+<a name="899"><span class="lineNum">     899 </span><span class="lineCov">        136 :     ftbBank_io_update_write_way_REG &lt;= _ftbBank_io_update_hits_bits;</span></a>
+<a name="900"><span class="lineNum">     900 </span><span class="lineCov">        136 :     ftbBank_io_update_write_alloc_REG &lt;= ~_ftbBank_io_update_hits_valid;</span></a>
+<a name="901"><span class="lineNum">     901 </span><span class="lineCov">        136 :     io_perf_0_value_REG &lt;= io_update_valid &amp; io_update_bits_meta[0];</span></a>
+<a name="902"><span class="lineNum">     902 </span><span class="lineCov">        136 :     io_perf_0_value_REG_1 &lt;= io_perf_0_value_REG;</span></a>
+<a name="903"><span class="lineNum">     903 </span><span class="lineCov">        136 :     io_perf_1_value_REG &lt;= io_update_valid &amp; ~(io_update_bits_meta[0]);</span></a>
+<a name="904"><span class="lineNum">     904 </span><span class="lineCov">        136 :     io_perf_1_value_REG_1 &lt;= io_perf_1_value_REG;</span></a>
+<a name="905"><span class="lineNum">     905 </span><span class="lineCov">        136 :   end // always @(posedge)</span></a>
+<a name="906"><span class="lineNum">     906 </span>            :   always @(posedge clock or posedge reset) begin</a>
+<a name="907"><span class="lineNum">     907 </span><span class="lineCov">      63729 :     if (reset) begin</span></a>
+<a name="908"><span class="lineNum">     908 </span><span class="lineCov">       8252 :       s2_hit_dup_0 &lt;= 1'h0;</span></a>
+<a name="909"><span class="lineNum">     909 </span><span class="lineCov">       4126 :       s2_hit_dup_1 &lt;= 1'h0;</span></a>
+<a name="910"><span class="lineNum">     910 </span><span class="lineCov">       8252 :       s2_hit_dup_2 &lt;= 1'h0;</span></a>
+<a name="911"><span class="lineNum">     911 </span><span class="lineCov">       4126 :       s2_hit_dup_3 &lt;= 1'h0;</span></a>
+<a name="912"><span class="lineNum">     912 </span><span class="lineCov">       8252 :       s3_hit_dup_0 &lt;= 1'h0;</span></a>
+<a name="913"><span class="lineNum">     913 </span><span class="lineCov">       4126 :       s3_hit_dup_1 &lt;= 1'h0;</span></a>
+<a name="914"><span class="lineNum">     914 </span><span class="lineCov">       8252 :       s3_hit_dup_2 &lt;= 1'h0;</span></a>
+<a name="915"><span class="lineNum">     915 </span><span class="lineCov">       4126 :       s3_hit_dup_3 &lt;= 1'h0;</span></a>
+<a name="916"><span class="lineNum">     916 </span><span class="lineCov">       8150 :     end</span></a>
+<a name="917"><span class="lineNum">     917 </span><span class="lineCov">       4075 :     else begin</span></a>
+<a name="918"><span class="lineNum">     918 </span><span class="lineCov">       8150 :       if (io_s1_fire_0)</span></a>
+<a name="919"><span class="lineNum">     919 </span><span class="lineCov">       4075 :         s2_hit_dup_0 &lt;= s1_hit;</span></a>
+<a name="920"><span class="lineNum">     920 </span><span class="lineCov">       8150 :       if (io_s1_fire_1)</span></a>
+<a name="921"><span class="lineNum">     921 </span><span class="lineCov">       4075 :         s2_hit_dup_1 &lt;= s1_hit;</span></a>
+<a name="922"><span class="lineNum">     922 </span><span class="lineCov">       8150 :       if (io_s1_fire_2)</span></a>
+<a name="923"><span class="lineNum">     923 </span><span class="lineCov">       4075 :         s2_hit_dup_2 &lt;= s1_hit;</span></a>
+<a name="924"><span class="lineNum">     924 </span>            :       if (io_s1_fire_3)</a>
+<a name="925"><span class="lineNum">     925 </span>            :         s2_hit_dup_3 &lt;= s1_hit;</a>
+<a name="926"><span class="lineNum">     926 </span>            :       if (io_s2_fire_0)</a>
+<a name="927"><span class="lineNum">     927 </span>            :         s3_hit_dup_0 &lt;= s2_hit_dup_0;</a>
+<a name="928"><span class="lineNum">     928 </span>            :       if (io_s2_fire_1)</a>
+<a name="929"><span class="lineNum">     929 </span>            :         s3_hit_dup_1 &lt;= s2_hit_dup_1;</a>
+<a name="930"><span class="lineNum">     930 </span>            :       if (io_s2_fire_2)</a>
+<a name="931"><span class="lineNum">     931 </span><span class="lineCov">         58 :         s3_hit_dup_2 &lt;= s2_hit_dup_2;</span></a>
+<a name="932"><span class="lineNum">     932 </span>            :       if (io_s2_fire_3)</a>
+<a name="933"><span class="lineNum">     933 </span>            :         s3_hit_dup_3 &lt;= s2_hit_dup_3;</a>
+<a name="934"><span class="lineNum">     934 </span>            :     end</a>
+<a name="935"><span class="lineNum">     935 </span>            :   end // always @(posedge, posedge)</a>
+<a name="936"><span class="lineNum">     936 </span>            :   `ifdef ENABLE_INITIAL_REG_</a>
+<a name="937"><span class="lineNum">     937 </span>            :     `ifdef FIRRTL_BEFORE_INITIAL</a>
+<a name="938"><span class="lineNum">     938 </span>            :       `FIRRTL_BEFORE_INITIAL</a>
+<a name="939"><span class="lineNum">     939 </span>            :     `endif // FIRRTL_BEFORE_INITIAL</a>
+<a name="940"><span class="lineNum">     940 </span>            :     logic [31:0] _RANDOM[0:90];</a>
+<a name="941"><span class="lineNum">     941 </span>            :     initial begin</a>
+<a name="942"><span class="lineNum">     942 </span>            :       `ifdef INIT_RANDOM_PROLOG_</a>
+<a name="943"><span class="lineNum">     943 </span>            :         `INIT_RANDOM_PROLOG_</a>
+<a name="944"><span class="lineNum">     944 </span>            :       `endif // INIT_RANDOM_PROLOG_</a>
+<a name="945"><span class="lineNum">     945 </span>            :       `ifdef RANDOMIZE_REG_INIT</a>
+<a name="946"><span class="lineNum">     946 </span>            :         for (logic [6:0] i = 7'h0; i &lt; 7'h5B; i += 7'h1) begin</a>
+<a name="947"><span class="lineNum">     947 </span>            :           _RANDOM[i] = `RANDOM;</a>
+<a name="948"><span class="lineNum">     948 </span>            :         end</a>
+<a name="949"><span class="lineNum">     949 </span>            :         s1_pc_dup_0 = {_RANDOM[7'h0], _RANDOM[7'h1][8:0]};</a>
+<a name="950"><span class="lineNum">     950 </span>            :         s1_pc_dup_1 = {_RANDOM[7'h1][31:9], _RANDOM[7'h2][17:0]};</a>
+<a name="951"><span class="lineNum">     951 </span>            :         s1_pc_dup_2 = {_RANDOM[7'h2][31:18], _RANDOM[7'h3][26:0]};</a>
+<a name="952"><span class="lineNum">     952 </span>            :         s1_pc_dup_3 = {_RANDOM[7'h3][31:27], _RANDOM[7'h4], _RANDOM[7'h5][3:0]};</a>
+<a name="953"><span class="lineNum">     953 </span>            :         s2_pc_dup_0 = {_RANDOM[7'h5][31:4], _RANDOM[7'h6][12:0]};</a>
+<a name="954"><span class="lineNum">     954 </span>            :         s2_pc_dup_1 = {_RANDOM[7'h6][31:13], _RANDOM[7'h7][21:0]};</a>
+<a name="955"><span class="lineNum">     955 </span>            :         s2_pc_dup_2 = {_RANDOM[7'h7][31:22], _RANDOM[7'h8][30:0]};</a>
+<a name="956"><span class="lineNum">     956 </span>            :         s2_pc_dup_3 = {_RANDOM[7'h8][31], _RANDOM[7'h9], _RANDOM[7'hA][7:0]};</a>
+<a name="957"><span class="lineNum">     957 </span>            :         s3_pc_dup_0 = {_RANDOM[7'hA][31:8], _RANDOM[7'hB][16:0]};</a>
+<a name="958"><span class="lineNum">     958 </span>            :         s3_pc_dup_1 = {_RANDOM[7'hB][31:17], _RANDOM[7'hC][25:0]};</a>
+<a name="959"><span class="lineNum">     959 </span>            :         s3_pc_dup_2 = {_RANDOM[7'hC][31:26], _RANDOM[7'hD], _RANDOM[7'hE][2:0]};</a>
+<a name="960"><span class="lineNum">     960 </span>            :         s3_pc_dup_3 = {_RANDOM[7'hE][31:3], _RANDOM[7'hF][11:0]};</a>
+<a name="961"><span class="lineNum">     961 </span>            :         REG = _RANDOM[7'hF][12];</a>
+<a name="962"><span class="lineNum">     962 </span>            :         REG_1 = _RANDOM[7'hF][13];</a>
+<a name="963"><span class="lineNum">     963 </span>            :         s2_ftb_entry_dup_0_valid = _RANDOM[7'hF][15];</a>
+<a name="964"><span class="lineNum">     964 </span>            :         s2_ftb_entry_dup_0_brSlots_0_offset = _RANDOM[7'hF][19:16];</a>
+<a name="965"><span class="lineNum">     965 </span>            :         s2_ftb_entry_dup_0_brSlots_0_lower = _RANDOM[7'hF][31:20];</a>
+<a name="966"><span class="lineNum">     966 </span>            :         s2_ftb_entry_dup_0_brSlots_0_tarStat = _RANDOM[7'h10][1:0];</a>
+<a name="967"><span class="lineNum">     967 </span>            :         s2_ftb_entry_dup_0_brSlots_0_sharing = _RANDOM[7'h10][2];</a>
+<a name="968"><span class="lineNum">     968 </span>            :         s2_ftb_entry_dup_0_brSlots_0_valid = _RANDOM[7'h10][3];</a>
+<a name="969"><span class="lineNum">     969 </span>            :         s2_ftb_entry_dup_0_tailSlot_offset = _RANDOM[7'h10][7:4];</a>
+<a name="970"><span class="lineNum">     970 </span>            :         s2_ftb_entry_dup_0_tailSlot_lower = _RANDOM[7'h10][27:8];</a>
+<a name="971"><span class="lineNum">     971 </span>            :         s2_ftb_entry_dup_0_tailSlot_tarStat = _RANDOM[7'h10][29:28];</a>
+<a name="972"><span class="lineNum">     972 </span>            :         s2_ftb_entry_dup_0_tailSlot_sharing = _RANDOM[7'h10][30];</a>
+<a name="973"><span class="lineNum">     973 </span>            :         s2_ftb_entry_dup_0_tailSlot_valid = _RANDOM[7'h10][31];</a>
+<a name="974"><span class="lineNum">     974 </span>            :         s2_ftb_entry_dup_0_pftAddr = _RANDOM[7'h11][3:0];</a>
+<a name="975"><span class="lineNum">     975 </span>            :         s2_ftb_entry_dup_0_carry = _RANDOM[7'h11][4];</a>
+<a name="976"><span class="lineNum">     976 </span>            :         s2_ftb_entry_dup_0_isCall = _RANDOM[7'h11][5];</a>
+<a name="977"><span class="lineNum">     977 </span>            :         s2_ftb_entry_dup_0_isRet = _RANDOM[7'h11][6];</a>
+<a name="978"><span class="lineNum">     978 </span>            :         s2_ftb_entry_dup_0_isJalr = _RANDOM[7'h11][7];</a>
+<a name="979"><span class="lineNum">     979 </span>            :         s2_ftb_entry_dup_0_last_may_be_rvi_call = _RANDOM[7'h11][8];</a>
+<a name="980"><span class="lineNum">     980 </span>            :         s2_ftb_entry_dup_0_always_taken_0 = _RANDOM[7'h11][9];</a>
+<a name="981"><span class="lineNum">     981 </span>            :         s2_ftb_entry_dup_0_always_taken_1 = _RANDOM[7'h11][10];</a>
+<a name="982"><span class="lineNum">     982 </span>            :         s2_ftb_entry_dup_1_brSlots_0_offset = _RANDOM[7'h11][15:12];</a>
+<a name="983"><span class="lineNum">     983 </span>            :         s2_ftb_entry_dup_1_brSlots_0_lower = _RANDOM[7'h11][27:16];</a>
+<a name="984"><span class="lineNum">     984 </span>            :         s2_ftb_entry_dup_1_brSlots_0_tarStat = _RANDOM[7'h11][29:28];</a>
+<a name="985"><span class="lineNum">     985 </span>            :         s2_ftb_entry_dup_1_brSlots_0_valid = _RANDOM[7'h11][31];</a>
+<a name="986"><span class="lineNum">     986 </span>            :         s2_ftb_entry_dup_1_tailSlot_offset = _RANDOM[7'h12][3:0];</a>
+<a name="987"><span class="lineNum">     987 </span>            :         s2_ftb_entry_dup_1_tailSlot_lower = _RANDOM[7'h12][23:4];</a>
+<a name="988"><span class="lineNum">     988 </span>            :         s2_ftb_entry_dup_1_tailSlot_tarStat = _RANDOM[7'h12][25:24];</a>
+<a name="989"><span class="lineNum">     989 </span>            :         s2_ftb_entry_dup_1_tailSlot_sharing = _RANDOM[7'h12][26];</a>
+<a name="990"><span class="lineNum">     990 </span>            :         s2_ftb_entry_dup_1_tailSlot_valid = _RANDOM[7'h12][27];</a>
+<a name="991"><span class="lineNum">     991 </span>            :         s2_ftb_entry_dup_1_pftAddr = _RANDOM[7'h12][31:28];</a>
+<a name="992"><span class="lineNum">     992 </span>            :         s2_ftb_entry_dup_1_carry = _RANDOM[7'h13][0];</a>
+<a name="993"><span class="lineNum">     993 </span>            :         s2_ftb_entry_dup_1_always_taken_0 = _RANDOM[7'h13][5];</a>
+<a name="994"><span class="lineNum">     994 </span>            :         s2_ftb_entry_dup_1_always_taken_1 = _RANDOM[7'h13][6];</a>
+<a name="995"><span class="lineNum">     995 </span>            :         s2_ftb_entry_dup_2_brSlots_0_offset = _RANDOM[7'h13][11:8];</a>
+<a name="996"><span class="lineNum">     996 </span>            :         s2_ftb_entry_dup_2_brSlots_0_lower = _RANDOM[7'h13][23:12];</a>
+<a name="997"><span class="lineNum">     997 </span>            :         s2_ftb_entry_dup_2_brSlots_0_tarStat = _RANDOM[7'h13][25:24];</a>
+<a name="998"><span class="lineNum">     998 </span>            :         s2_ftb_entry_dup_2_brSlots_0_valid = _RANDOM[7'h13][27];</a>
+<a name="999"><span class="lineNum">     999 </span>            :         s2_ftb_entry_dup_2_tailSlot_offset = _RANDOM[7'h13][31:28];</a>
+<a name="1000"><span class="lineNum">    1000 </span>            :         s2_ftb_entry_dup_2_tailSlot_lower = _RANDOM[7'h14][19:0];</a>
+<a name="1001"><span class="lineNum">    1001 </span>            :         s2_ftb_entry_dup_2_tailSlot_tarStat = _RANDOM[7'h14][21:20];</a>
+<a name="1002"><span class="lineNum">    1002 </span>            :         s2_ftb_entry_dup_2_tailSlot_sharing = _RANDOM[7'h14][22];</a>
+<a name="1003"><span class="lineNum">    1003 </span>            :         s2_ftb_entry_dup_2_tailSlot_valid = _RANDOM[7'h14][23];</a>
+<a name="1004"><span class="lineNum">    1004 </span>            :         s2_ftb_entry_dup_2_pftAddr = _RANDOM[7'h14][27:24];</a>
+<a name="1005"><span class="lineNum">    1005 </span>            :         s2_ftb_entry_dup_2_carry = _RANDOM[7'h14][28];</a>
+<a name="1006"><span class="lineNum">    1006 </span>            :         s2_ftb_entry_dup_2_isCall = _RANDOM[7'h14][29];</a>
+<a name="1007"><span class="lineNum">    1007 </span>            :         s2_ftb_entry_dup_2_isRet = _RANDOM[7'h14][30];</a>
+<a name="1008"><span class="lineNum">    1008 </span>            :         s2_ftb_entry_dup_2_isJalr = _RANDOM[7'h14][31];</a>
+<a name="1009"><span class="lineNum">    1009 </span>            :         s2_ftb_entry_dup_2_last_may_be_rvi_call = _RANDOM[7'h15][0];</a>
+<a name="1010"><span class="lineNum">    1010 </span>            :         s2_ftb_entry_dup_2_always_taken_0 = _RANDOM[7'h15][1];</a>
+<a name="1011"><span class="lineNum">    1011 </span>            :         s2_ftb_entry_dup_2_always_taken_1 = _RANDOM[7'h15][2];</a>
+<a name="1012"><span class="lineNum">    1012 </span>            :         s2_ftb_entry_dup_3_brSlots_0_offset = _RANDOM[7'h15][7:4];</a>
+<a name="1013"><span class="lineNum">    1013 </span>            :         s2_ftb_entry_dup_3_brSlots_0_lower = _RANDOM[7'h15][19:8];</a>
+<a name="1014"><span class="lineNum">    1014 </span>            :         s2_ftb_entry_dup_3_brSlots_0_tarStat = _RANDOM[7'h15][21:20];</a>
+<a name="1015"><span class="lineNum">    1015 </span>            :         s2_ftb_entry_dup_3_brSlots_0_valid = _RANDOM[7'h15][23];</a>
+<a name="1016"><span class="lineNum">    1016 </span>            :         s2_ftb_entry_dup_3_tailSlot_offset = _RANDOM[7'h15][27:24];</a>
+<a name="1017"><span class="lineNum">    1017 </span>            :         s2_ftb_entry_dup_3_tailSlot_lower = {_RANDOM[7'h15][31:28], _RANDOM[7'h16][15:0]};</a>
+<a name="1018"><span class="lineNum">    1018 </span>            :         s2_ftb_entry_dup_3_tailSlot_tarStat = _RANDOM[7'h16][17:16];</a>
+<a name="1019"><span class="lineNum">    1019 </span>            :         s2_ftb_entry_dup_3_tailSlot_sharing = _RANDOM[7'h16][18];</a>
+<a name="1020"><span class="lineNum">    1020 </span>            :         s2_ftb_entry_dup_3_tailSlot_valid = _RANDOM[7'h16][19];</a>
+<a name="1021"><span class="lineNum">    1021 </span>            :         s2_ftb_entry_dup_3_pftAddr = _RANDOM[7'h16][23:20];</a>
+<a name="1022"><span class="lineNum">    1022 </span>            :         s2_ftb_entry_dup_3_carry = _RANDOM[7'h16][24];</a>
+<a name="1023"><span class="lineNum">    1023 </span>            :         s2_ftb_entry_dup_3_always_taken_0 = _RANDOM[7'h16][29];</a>
+<a name="1024"><span class="lineNum">    1024 </span>            :         s2_ftb_entry_dup_3_always_taken_1 = _RANDOM[7'h16][30];</a>
+<a name="1025"><span class="lineNum">    1025 </span>            :         s3_ftb_entry_dup_0_valid = _RANDOM[7'h16][31];</a>
+<a name="1026"><span class="lineNum">    1026 </span>            :         s3_ftb_entry_dup_0_brSlots_0_offset = _RANDOM[7'h17][3:0];</a>
+<a name="1027"><span class="lineNum">    1027 </span>            :         s3_ftb_entry_dup_0_brSlots_0_lower = _RANDOM[7'h17][15:4];</a>
+<a name="1028"><span class="lineNum">    1028 </span>            :         s3_ftb_entry_dup_0_brSlots_0_tarStat = _RANDOM[7'h17][17:16];</a>
+<a name="1029"><span class="lineNum">    1029 </span>            :         s3_ftb_entry_dup_0_brSlots_0_sharing = _RANDOM[7'h17][18];</a>
+<a name="1030"><span class="lineNum">    1030 </span>            :         s3_ftb_entry_dup_0_brSlots_0_valid = _RANDOM[7'h17][19];</a>
+<a name="1031"><span class="lineNum">    1031 </span>            :         s3_ftb_entry_dup_0_tailSlot_offset = _RANDOM[7'h17][23:20];</a>
+<a name="1032"><span class="lineNum">    1032 </span>            :         s3_ftb_entry_dup_0_tailSlot_lower = {_RANDOM[7'h17][31:24], _RANDOM[7'h18][11:0]};</a>
+<a name="1033"><span class="lineNum">    1033 </span>            :         s3_ftb_entry_dup_0_tailSlot_tarStat = _RANDOM[7'h18][13:12];</a>
+<a name="1034"><span class="lineNum">    1034 </span>            :         s3_ftb_entry_dup_0_tailSlot_sharing = _RANDOM[7'h18][14];</a>
+<a name="1035"><span class="lineNum">    1035 </span>            :         s3_ftb_entry_dup_0_tailSlot_valid = _RANDOM[7'h18][15];</a>
+<a name="1036"><span class="lineNum">    1036 </span>            :         s3_ftb_entry_dup_0_pftAddr = _RANDOM[7'h18][19:16];</a>
+<a name="1037"><span class="lineNum">    1037 </span>            :         s3_ftb_entry_dup_0_carry = _RANDOM[7'h18][20];</a>
+<a name="1038"><span class="lineNum">    1038 </span>            :         s3_ftb_entry_dup_0_isCall = _RANDOM[7'h18][21];</a>
+<a name="1039"><span class="lineNum">    1039 </span>            :         s3_ftb_entry_dup_0_isRet = _RANDOM[7'h18][22];</a>
+<a name="1040"><span class="lineNum">    1040 </span>            :         s3_ftb_entry_dup_0_isJalr = _RANDOM[7'h18][23];</a>
+<a name="1041"><span class="lineNum">    1041 </span>            :         s3_ftb_entry_dup_0_last_may_be_rvi_call = _RANDOM[7'h18][24];</a>
+<a name="1042"><span class="lineNum">    1042 </span>            :         s3_ftb_entry_dup_0_always_taken_0 = _RANDOM[7'h18][25];</a>
+<a name="1043"><span class="lineNum">    1043 </span>            :         s3_ftb_entry_dup_0_always_taken_1 = _RANDOM[7'h18][26];</a>
+<a name="1044"><span class="lineNum">    1044 </span>            :         s3_ftb_entry_dup_1_brSlots_0_lower = _RANDOM[7'h19][11:0];</a>
+<a name="1045"><span class="lineNum">    1045 </span>            :         s3_ftb_entry_dup_1_brSlots_0_tarStat = _RANDOM[7'h19][13:12];</a>
+<a name="1046"><span class="lineNum">    1046 </span>            :         s3_ftb_entry_dup_1_brSlots_0_valid = _RANDOM[7'h19][15];</a>
+<a name="1047"><span class="lineNum">    1047 </span>            :         s3_ftb_entry_dup_1_tailSlot_lower = {_RANDOM[7'h19][31:20], _RANDOM[7'h1A][7:0]};</a>
+<a name="1048"><span class="lineNum">    1048 </span>            :         s3_ftb_entry_dup_1_tailSlot_tarStat = _RANDOM[7'h1A][9:8];</a>
+<a name="1049"><span class="lineNum">    1049 </span>            :         s3_ftb_entry_dup_1_tailSlot_sharing = _RANDOM[7'h1A][10];</a>
+<a name="1050"><span class="lineNum">    1050 </span>            :         s3_ftb_entry_dup_1_tailSlot_valid = _RANDOM[7'h1A][11];</a>
+<a name="1051"><span class="lineNum">    1051 </span>            :         s3_ftb_entry_dup_1_pftAddr = _RANDOM[7'h1A][15:12];</a>
+<a name="1052"><span class="lineNum">    1052 </span>            :         s3_ftb_entry_dup_1_carry = _RANDOM[7'h1A][16];</a>
+<a name="1053"><span class="lineNum">    1053 </span>            :         s3_ftb_entry_dup_1_always_taken_0 = _RANDOM[7'h1A][21];</a>
+<a name="1054"><span class="lineNum">    1054 </span>            :         s3_ftb_entry_dup_1_always_taken_1 = _RANDOM[7'h1A][22];</a>
+<a name="1055"><span class="lineNum">    1055 </span>            :         s3_ftb_entry_dup_2_brSlots_0_lower = {_RANDOM[7'h1A][31:28], _RANDOM[7'h1B][7:0]};</a>
+<a name="1056"><span class="lineNum">    1056 </span>            :         s3_ftb_entry_dup_2_brSlots_0_tarStat = _RANDOM[7'h1B][9:8];</a>
+<a name="1057"><span class="lineNum">    1057 </span>            :         s3_ftb_entry_dup_2_brSlots_0_valid = _RANDOM[7'h1B][11];</a>
+<a name="1058"><span class="lineNum">    1058 </span>            :         s3_ftb_entry_dup_2_tailSlot_lower = {_RANDOM[7'h1B][31:16], _RANDOM[7'h1C][3:0]};</a>
+<a name="1059"><span class="lineNum">    1059 </span>            :         s3_ftb_entry_dup_2_tailSlot_tarStat = _RANDOM[7'h1C][5:4];</a>
+<a name="1060"><span class="lineNum">    1060 </span>            :         s3_ftb_entry_dup_2_tailSlot_sharing = _RANDOM[7'h1C][6];</a>
+<a name="1061"><span class="lineNum">    1061 </span>            :         s3_ftb_entry_dup_2_tailSlot_valid = _RANDOM[7'h1C][7];</a>
+<a name="1062"><span class="lineNum">    1062 </span>            :         s3_ftb_entry_dup_2_pftAddr = _RANDOM[7'h1C][11:8];</a>
+<a name="1063"><span class="lineNum">    1063 </span>            :         s3_ftb_entry_dup_2_carry = _RANDOM[7'h1C][12];</a>
+<a name="1064"><span class="lineNum">    1064 </span>            :         s3_ftb_entry_dup_2_isCall = _RANDOM[7'h1C][13];</a>
+<a name="1065"><span class="lineNum">    1065 </span>            :         s3_ftb_entry_dup_2_isRet = _RANDOM[7'h1C][14];</a>
+<a name="1066"><span class="lineNum">    1066 </span>            :         s3_ftb_entry_dup_2_isJalr = _RANDOM[7'h1C][15];</a>
+<a name="1067"><span class="lineNum">    1067 </span>            :         s3_ftb_entry_dup_2_always_taken_0 = _RANDOM[7'h1C][17];</a>
+<a name="1068"><span class="lineNum">    1068 </span>            :         s3_ftb_entry_dup_2_always_taken_1 = _RANDOM[7'h1C][18];</a>
+<a name="1069"><span class="lineNum">    1069 </span>            :         s3_ftb_entry_dup_3_brSlots_0_offset = _RANDOM[7'h1C][23:20];</a>
+<a name="1070"><span class="lineNum">    1070 </span>            :         s3_ftb_entry_dup_3_brSlots_0_lower = {_RANDOM[7'h1C][31:24], _RANDOM[7'h1D][3:0]};</a>
+<a name="1071"><span class="lineNum">    1071 </span>            :         s3_ftb_entry_dup_3_brSlots_0_tarStat = _RANDOM[7'h1D][5:4];</a>
+<a name="1072"><span class="lineNum">    1072 </span>            :         s3_ftb_entry_dup_3_brSlots_0_valid = _RANDOM[7'h1D][7];</a>
+<a name="1073"><span class="lineNum">    1073 </span>            :         s3_ftb_entry_dup_3_tailSlot_offset = _RANDOM[7'h1D][11:8];</a>
+<a name="1074"><span class="lineNum">    1074 </span>            :         s3_ftb_entry_dup_3_tailSlot_lower = _RANDOM[7'h1D][31:12];</a>
+<a name="1075"><span class="lineNum">    1075 </span>            :         s3_ftb_entry_dup_3_tailSlot_tarStat = _RANDOM[7'h1E][1:0];</a>
+<a name="1076"><span class="lineNum">    1076 </span>            :         s3_ftb_entry_dup_3_tailSlot_sharing = _RANDOM[7'h1E][2];</a>
+<a name="1077"><span class="lineNum">    1077 </span>            :         s3_ftb_entry_dup_3_tailSlot_valid = _RANDOM[7'h1E][3];</a>
+<a name="1078"><span class="lineNum">    1078 </span>            :         s3_ftb_entry_dup_3_pftAddr = _RANDOM[7'h1E][7:4];</a>
+<a name="1079"><span class="lineNum">    1079 </span>            :         s3_ftb_entry_dup_3_carry = _RANDOM[7'h1E][8];</a>
+<a name="1080"><span class="lineNum">    1080 </span>            :         s3_ftb_entry_dup_3_always_taken_0 = _RANDOM[7'h1E][13];</a>
+<a name="1081"><span class="lineNum">    1081 </span>            :         s3_ftb_entry_dup_3_always_taken_1 = _RANDOM[7'h1E][14];</a>
+<a name="1082"><span class="lineNum">    1082 </span>            :         s2_hit_dup_0 = _RANDOM[7'h1E][15];</a>
+<a name="1083"><span class="lineNum">    1083 </span>            :         s2_hit_dup_1 = _RANDOM[7'h1E][16];</a>
+<a name="1084"><span class="lineNum">    1084 </span>            :         s2_hit_dup_2 = _RANDOM[7'h1E][17];</a>
+<a name="1085"><span class="lineNum">    1085 </span>            :         s2_hit_dup_3 = _RANDOM[7'h1E][18];</a>
+<a name="1086"><span class="lineNum">    1086 </span>            :         s3_hit_dup_0 = _RANDOM[7'h1E][19];</a>
+<a name="1087"><span class="lineNum">    1087 </span>            :         s3_hit_dup_1 = _RANDOM[7'h1E][20];</a>
+<a name="1088"><span class="lineNum">    1088 </span>            :         s3_hit_dup_2 = _RANDOM[7'h1E][21];</a>
+<a name="1089"><span class="lineNum">    1089 </span>            :         s3_hit_dup_3 = _RANDOM[7'h1E][22];</a>
+<a name="1090"><span class="lineNum">    1090 </span>            :         higher_r = {_RANDOM[7'h1E][31:23], _RANDOM[7'h1F][18:0]};</a>
+<a name="1091"><span class="lineNum">    1091 </span>            :         higher_plus_one_r = {_RANDOM[7'h1F][31:19], _RANDOM[7'h20][14:0]};</a>
+<a name="1092"><span class="lineNum">    1092 </span>            :         higher_minus_one_r = {_RANDOM[7'h20][31:15], _RANDOM[7'h21][10:0]};</a>
+<a name="1093"><span class="lineNum">    1093 </span>            :         higher_r_1 = {_RANDOM[7'h21][31:11], _RANDOM[7'h22][6:0]};</a>
+<a name="1094"><span class="lineNum">    1094 </span>            :         higher_plus_one_r_1 = {_RANDOM[7'h22][31:7], _RANDOM[7'h23][2:0]};</a>
+<a name="1095"><span class="lineNum">    1095 </span>            :         higher_minus_one_r_1 = _RANDOM[7'h23][30:3];</a>
+<a name="1096"><span class="lineNum">    1096 </span>            :         higher_r_2 = {_RANDOM[7'h23][31], _RANDOM[7'h24][18:0]};</a>
+<a name="1097"><span class="lineNum">    1097 </span>            :         higher_plus_one_r_2 = {_RANDOM[7'h24][31:19], _RANDOM[7'h25][6:0]};</a>
+<a name="1098"><span class="lineNum">    1098 </span>            :         higher_minus_one_r_2 = _RANDOM[7'h25][26:7];</a>
+<a name="1099"><span class="lineNum">    1099 </span>            :         io_out_s2_full_pred_0_fallThroughAddr_stashed_carry = _RANDOM[7'h25][27];</a>
+<a name="1100"><span class="lineNum">    1100 </span>            :         higher_r_3 = {_RANDOM[7'h25][31:28], _RANDOM[7'h26][23:0]};</a>
+<a name="1101"><span class="lineNum">    1101 </span>            :         higher_plus_one_r_3 = {_RANDOM[7'h26][31:24], _RANDOM[7'h27][19:0]};</a>
+<a name="1102"><span class="lineNum">    1102 </span>            :         higher_minus_one_r_3 = {_RANDOM[7'h27][31:20], _RANDOM[7'h28][15:0]};</a>
+<a name="1103"><span class="lineNum">    1103 </span>            :         higher_r_4 = {_RANDOM[7'h28][31:16], _RANDOM[7'h29][11:0]};</a>
+<a name="1104"><span class="lineNum">    1104 </span>            :         higher_plus_one_r_4 = {_RANDOM[7'h29][31:12], _RANDOM[7'h2A][7:0]};</a>
+<a name="1105"><span class="lineNum">    1105 </span>            :         higher_minus_one_r_4 = {_RANDOM[7'h2A][31:8], _RANDOM[7'h2B][3:0]};</a>
+<a name="1106"><span class="lineNum">    1106 </span>            :         higher_r_5 = _RANDOM[7'h2B][23:4];</a>
+<a name="1107"><span class="lineNum">    1107 </span>            :         higher_plus_one_r_5 = {_RANDOM[7'h2B][31:24], _RANDOM[7'h2C][11:0]};</a>
+<a name="1108"><span class="lineNum">    1108 </span>            :         higher_minus_one_r_5 = _RANDOM[7'h2C][31:12];</a>
+<a name="1109"><span class="lineNum">    1109 </span>            :         io_out_s2_full_pred_1_fallThroughAddr_stashed_carry = _RANDOM[7'h2D][0];</a>
+<a name="1110"><span class="lineNum">    1110 </span>            :         higher_r_6 = _RANDOM[7'h2D][28:1];</a>
+<a name="1111"><span class="lineNum">    1111 </span>            :         higher_plus_one_r_6 = {_RANDOM[7'h2D][31:29], _RANDOM[7'h2E][24:0]};</a>
+<a name="1112"><span class="lineNum">    1112 </span>            :         higher_minus_one_r_6 = {_RANDOM[7'h2E][31:25], _RANDOM[7'h2F][20:0]};</a>
+<a name="1113"><span class="lineNum">    1113 </span>            :         higher_r_7 = {_RANDOM[7'h2F][31:21], _RANDOM[7'h30][16:0]};</a>
+<a name="1114"><span class="lineNum">    1114 </span>            :         higher_plus_one_r_7 = {_RANDOM[7'h30][31:17], _RANDOM[7'h31][12:0]};</a>
+<a name="1115"><span class="lineNum">    1115 </span>            :         higher_minus_one_r_7 = {_RANDOM[7'h31][31:13], _RANDOM[7'h32][8:0]};</a>
+<a name="1116"><span class="lineNum">    1116 </span>            :         higher_r_8 = _RANDOM[7'h32][28:9];</a>
+<a name="1117"><span class="lineNum">    1117 </span>            :         higher_plus_one_r_8 = {_RANDOM[7'h32][31:29], _RANDOM[7'h33][16:0]};</a>
+<a name="1118"><span class="lineNum">    1118 </span>            :         higher_minus_one_r_8 = {_RANDOM[7'h33][31:17], _RANDOM[7'h34][4:0]};</a>
+<a name="1119"><span class="lineNum">    1119 </span>            :         io_out_s2_full_pred_2_fallThroughAddr_stashed_carry = _RANDOM[7'h34][5];</a>
+<a name="1120"><span class="lineNum">    1120 </span>            :         higher_r_9 = {_RANDOM[7'h34][31:6], _RANDOM[7'h35][1:0]};</a>
+<a name="1121"><span class="lineNum">    1121 </span>            :         higher_plus_one_r_9 = _RANDOM[7'h35][29:2];</a>
+<a name="1122"><span class="lineNum">    1122 </span>            :         higher_minus_one_r_9 = {_RANDOM[7'h35][31:30], _RANDOM[7'h36][25:0]};</a>
+<a name="1123"><span class="lineNum">    1123 </span>            :         higher_r_10 = {_RANDOM[7'h36][31:26], _RANDOM[7'h37][21:0]};</a>
+<a name="1124"><span class="lineNum">    1124 </span>            :         higher_plus_one_r_10 = {_RANDOM[7'h37][31:22], _RANDOM[7'h38][17:0]};</a>
+<a name="1125"><span class="lineNum">    1125 </span>            :         higher_minus_one_r_10 = {_RANDOM[7'h38][31:18], _RANDOM[7'h39][13:0]};</a>
+<a name="1126"><span class="lineNum">    1126 </span>            :         higher_r_11 = {_RANDOM[7'h39][31:14], _RANDOM[7'h3A][1:0]};</a>
+<a name="1127"><span class="lineNum">    1127 </span>            :         higher_plus_one_r_11 = _RANDOM[7'h3A][21:2];</a>
+<a name="1128"><span class="lineNum">    1128 </span>            :         higher_minus_one_r_11 = {_RANDOM[7'h3A][31:22], _RANDOM[7'h3B][9:0]};</a>
+<a name="1129"><span class="lineNum">    1129 </span>            :         io_out_s2_full_pred_3_fallThroughAddr_stashed_carry = _RANDOM[7'h3B][10];</a>
+<a name="1130"><span class="lineNum">    1130 </span>            :         higher_r_12 = {_RANDOM[7'h3B][31:11], _RANDOM[7'h3C][6:0]};</a>
+<a name="1131"><span class="lineNum">    1131 </span>            :         higher_plus_one_r_12 = {_RANDOM[7'h3C][31:7], _RANDOM[7'h3D][2:0]};</a>
+<a name="1132"><span class="lineNum">    1132 </span>            :         higher_minus_one_r_12 = _RANDOM[7'h3D][30:3];</a>
+<a name="1133"><span class="lineNum">    1133 </span>            :         higher_r_13 = {_RANDOM[7'h3D][31], _RANDOM[7'h3E][26:0]};</a>
+<a name="1134"><span class="lineNum">    1134 </span>            :         higher_plus_one_r_13 = {_RANDOM[7'h3E][31:27], _RANDOM[7'h3F][22:0]};</a>
+<a name="1135"><span class="lineNum">    1135 </span>            :         higher_minus_one_r_13 = {_RANDOM[7'h3F][31:23], _RANDOM[7'h40][18:0]};</a>
+<a name="1136"><span class="lineNum">    1136 </span>            :         higher_r_14 = {_RANDOM[7'h40][31:19], _RANDOM[7'h41][6:0]};</a>
+<a name="1137"><span class="lineNum">    1137 </span>            :         higher_plus_one_r_14 = _RANDOM[7'h41][26:7];</a>
+<a name="1138"><span class="lineNum">    1138 </span>            :         higher_minus_one_r_14 = {_RANDOM[7'h41][31:27], _RANDOM[7'h42][14:0]};</a>
+<a name="1139"><span class="lineNum">    1139 </span>            :         higher_r_15 = {_RANDOM[7'h42][31:15], _RANDOM[7'h43][10:0]};</a>
+<a name="1140"><span class="lineNum">    1140 </span>            :         higher_plus_one_r_15 = {_RANDOM[7'h43][31:11], _RANDOM[7'h44][6:0]};</a>
+<a name="1141"><span class="lineNum">    1141 </span>            :         higher_minus_one_r_15 = {_RANDOM[7'h44][31:7], _RANDOM[7'h45][2:0]};</a>
+<a name="1142"><span class="lineNum">    1142 </span>            :         higher_r_16 = _RANDOM[7'h45][30:3];</a>
+<a name="1143"><span class="lineNum">    1143 </span>            :         higher_plus_one_r_16 = {_RANDOM[7'h45][31], _RANDOM[7'h46][26:0]};</a>
+<a name="1144"><span class="lineNum">    1144 </span>            :         higher_minus_one_r_16 = {_RANDOM[7'h46][31:27], _RANDOM[7'h47][22:0]};</a>
+<a name="1145"><span class="lineNum">    1145 </span>            :         higher_r_17 = {_RANDOM[7'h47][31:23], _RANDOM[7'h48][10:0]};</a>
+<a name="1146"><span class="lineNum">    1146 </span>            :         higher_plus_one_r_17 = _RANDOM[7'h48][30:11];</a>
+<a name="1147"><span class="lineNum">    1147 </span>            :         higher_minus_one_r_17 = {_RANDOM[7'h48][31], _RANDOM[7'h49][18:0]};</a>
+<a name="1148"><span class="lineNum">    1148 </span>            :         higher_r_18 = {_RANDOM[7'h49][31:19], _RANDOM[7'h4A][14:0]};</a>
+<a name="1149"><span class="lineNum">    1149 </span>            :         higher_plus_one_r_18 = {_RANDOM[7'h4A][31:15], _RANDOM[7'h4B][10:0]};</a>
+<a name="1150"><span class="lineNum">    1150 </span>            :         higher_minus_one_r_18 = {_RANDOM[7'h4B][31:11], _RANDOM[7'h4C][6:0]};</a>
+<a name="1151"><span class="lineNum">    1151 </span>            :         higher_r_19 = {_RANDOM[7'h4C][31:7], _RANDOM[7'h4D][2:0]};</a>
+<a name="1152"><span class="lineNum">    1152 </span>            :         higher_plus_one_r_19 = _RANDOM[7'h4D][30:3];</a>
+<a name="1153"><span class="lineNum">    1153 </span>            :         higher_minus_one_r_19 = {_RANDOM[7'h4D][31], _RANDOM[7'h4E][26:0]};</a>
+<a name="1154"><span class="lineNum">    1154 </span>            :         higher_r_20 = {_RANDOM[7'h4E][31:27], _RANDOM[7'h4F][14:0]};</a>
+<a name="1155"><span class="lineNum">    1155 </span>            :         higher_plus_one_r_20 = {_RANDOM[7'h4F][31:15], _RANDOM[7'h50][2:0]};</a>
+<a name="1156"><span class="lineNum">    1156 </span>            :         higher_minus_one_r_20 = _RANDOM[7'h50][22:3];</a>
+<a name="1157"><span class="lineNum">    1157 </span>            :         higher_r_21 = {_RANDOM[7'h50][31:23], _RANDOM[7'h51][18:0]};</a>
+<a name="1158"><span class="lineNum">    1158 </span>            :         higher_plus_one_r_21 = {_RANDOM[7'h51][31:19], _RANDOM[7'h52][14:0]};</a>
+<a name="1159"><span class="lineNum">    1159 </span>            :         higher_minus_one_r_21 = {_RANDOM[7'h52][31:15], _RANDOM[7'h53][10:0]};</a>
+<a name="1160"><span class="lineNum">    1160 </span>            :         higher_r_22 = {_RANDOM[7'h53][31:11], _RANDOM[7'h54][6:0]};</a>
+<a name="1161"><span class="lineNum">    1161 </span>            :         higher_plus_one_r_22 = {_RANDOM[7'h54][31:7], _RANDOM[7'h55][2:0]};</a>
+<a name="1162"><span class="lineNum">    1162 </span>            :         higher_minus_one_r_22 = _RANDOM[7'h55][30:3];</a>
+<a name="1163"><span class="lineNum">    1163 </span>            :         higher_r_23 = {_RANDOM[7'h55][31], _RANDOM[7'h56][18:0]};</a>
+<a name="1164"><span class="lineNum">    1164 </span>            :         higher_plus_one_r_23 = {_RANDOM[7'h56][31:19], _RANDOM[7'h57][6:0]};</a>
+<a name="1165"><span class="lineNum">    1165 </span>            :         higher_minus_one_r_23 = _RANDOM[7'h57][26:7];</a>
+<a name="1166"><span class="lineNum">    1166 </span><span class="lineCov">         17 :         io_out_last_stage_meta_r = _RANDOM[7'h59][29:27];</span></a>
+<a name="1167"><span class="lineNum">    1167 </span><span class="lineCov">         12 :         io_out_last_stage_meta_r_1 = {_RANDOM[7'h59][31:30], _RANDOM[7'h5A][0]};</span></a>
+<a name="1168"><span class="lineNum">    1168 </span><span class="lineCov">         12 :         io_s1_ready_REG = _RANDOM[7'h5A][1];</span></a>
+<a name="1169"><span class="lineNum">    1169 </span><span class="lineCov">         12 :         ftbBank_io_update_write_way_REG = _RANDOM[7'h5A][3:2];</span></a>
+<a name="1170"><span class="lineNum">    1170 </span><span class="lineCov">         12 :         ftbBank_io_update_write_alloc_REG = _RANDOM[7'h5A][4];</span></a>
+<a name="1171"><span class="lineNum">    1171 </span><span class="lineCov">         12 :         io_perf_0_value_REG = _RANDOM[7'h5A][7];</span></a>
+<a name="1172"><span class="lineNum">    1172 </span><span class="lineCov">         12 :         io_perf_0_value_REG_1 = _RANDOM[7'h5A][8];</span></a>
+<a name="1173"><span class="lineNum">    1173 </span><span class="lineCov">         12 :         io_perf_1_value_REG = _RANDOM[7'h5A][9];</span></a>
+<a name="1174"><span class="lineNum">    1174 </span><span class="lineCov">         12 :         io_perf_1_value_REG_1 = _RANDOM[7'h5A][10];</span></a>
+<a name="1175"><span class="lineNum">    1175 </span>            :       `endif // RANDOMIZE_REG_INIT</a>
+<a name="1176"><span class="lineNum">    1176 </span>            :       if (reset) begin</a>
+<a name="1177"><span class="lineNum">    1177 </span>            :         s2_hit_dup_0 = 1'h0;</a>
+<a name="1178"><span class="lineNum">    1178 </span>            :         s2_hit_dup_1 = 1'h0;</a>
+<a name="1179"><span class="lineNum">    1179 </span>            :         s2_hit_dup_2 = 1'h0;</a>
+<a name="1180"><span class="lineNum">    1180 </span>            :         s2_hit_dup_3 = 1'h0;</a>
+<a name="1181"><span class="lineNum">    1181 </span>            :         s3_hit_dup_0 = 1'h0;</a>
+<a name="1182"><span class="lineNum">    1182 </span>            :         s3_hit_dup_1 = 1'h0;</a>
+<a name="1183"><span class="lineNum">    1183 </span>            :         s3_hit_dup_2 = 1'h0;</a>
+<a name="1184"><span class="lineNum">    1184 </span>            :         s3_hit_dup_3 = 1'h0;</a>
+<a name="1185"><span class="lineNum">    1185 </span>            :       end</a>
+<a name="1186"><span class="lineNum">    1186 </span>            :     end // initial</a>
+<a name="1187"><span class="lineNum">    1187 </span>            :     `ifdef FIRRTL_AFTER_INITIAL</a>
+<a name="1188"><span class="lineNum">    1188 </span>            :       `FIRRTL_AFTER_INITIAL</a>
+<a name="1189"><span class="lineNum">    1189 </span>            :     `endif // FIRRTL_AFTER_INITIAL</a>
+<a name="1190"><span class="lineNum">    1190 </span>            :   `endif // ENABLE_INITIAL_REG_</a>
+<a name="1191"><span class="lineNum">    1191 </span>            :   DelayN_2 reset_vector_delay (</a>
+<a name="1192"><span class="lineNum">    1192 </span>            :     .clock  (clock),</a>
+<a name="1193"><span class="lineNum">    1193 </span>            :     .io_in  (io_reset_vector),</a>
+<a name="1194"><span class="lineNum">    1194 </span>            :     .io_out (_reset_vector_delay_io_out)</a>
+<a name="1195"><span class="lineNum">    1195 </span>            :   );</a>
+<a name="1196"><span class="lineNum">    1196 </span>            : </a>
+<a name="1197"><span class="lineNum">    1197 </span>            : </a>
+<a name="1198"><span class="lineNum">    1198 </span>            :   FTBBank ftbBank (</a>
+<a name="1199"><span class="lineNum">    1199 </span>            :     .clock                                                (clock),</a>
+<a name="1200"><span class="lineNum">    1200 </span>            :     .reset                                                (reset),</a>
+<a name="1201"><span class="lineNum">    1201 </span>            :     .io_s1_fire                                           (io_s1_fire_0),</a>
+<a name="1202"><span class="lineNum">    1202 </span>            :     .io_req_pc_ready                                      (_ftbBank_io_req_pc_ready),</a>
+<a name="1203"><span class="lineNum">    1203 </span>            :     .io_req_pc_valid                                      (io_s0_fire_0),</a>
+<a name="1204"><span class="lineNum">    1204 </span>            :     .io_req_pc_bits                                       (io_in_bits_s0_pc_0),</a>
+<a name="1205"><span class="lineNum">    1205 </span>            :     .io_read_resp_valid                                   (_ftbBank_io_read_resp_valid),</a>
+<a name="1206"><span class="lineNum">    1206 </span>            :     .io_read_resp_brSlots_0_offset</a>
+<a name="1207"><span class="lineNum">    1207 </span>            :       (_ftbBank_io_read_resp_brSlots_0_offset),</a>
+<a name="1208"><span class="lineNum">    1208 </span>            :     .io_read_resp_brSlots_0_lower</a>
+<a name="1209"><span class="lineNum">    1209 </span>            :       (_ftbBank_io_read_resp_brSlots_0_lower),</a>
+<a name="1210"><span class="lineNum">    1210 </span>            :     .io_read_resp_brSlots_0_tarStat</a>
+<a name="1211"><span class="lineNum">    1211 </span>            :       (_ftbBank_io_read_resp_brSlots_0_tarStat),</a>
+<a name="1212"><span class="lineNum">    1212 </span>            :     .io_read_resp_brSlots_0_sharing</a>
+<a name="1213"><span class="lineNum">    1213 </span>            :       (_ftbBank_io_read_resp_brSlots_0_sharing),</a>
+<a name="1214"><span class="lineNum">    1214 </span>            :     .io_read_resp_brSlots_0_valid</a>
+<a name="1215"><span class="lineNum">    1215 </span>            :       (_ftbBank_io_read_resp_brSlots_0_valid),</a>
+<a name="1216"><span class="lineNum">    1216 </span>            :     .io_read_resp_tailSlot_offset</a>
+<a name="1217"><span class="lineNum">    1217 </span>            :       (_ftbBank_io_read_resp_tailSlot_offset),</a>
+<a name="1218"><span class="lineNum">    1218 </span>            :     .io_read_resp_tailSlot_lower</a>
+<a name="1219"><span class="lineNum">    1219 </span>            :       (_ftbBank_io_read_resp_tailSlot_lower),</a>
+<a name="1220"><span class="lineNum">    1220 </span>            :     .io_read_resp_tailSlot_tarStat</a>
+<a name="1221"><span class="lineNum">    1221 </span>            :       (_ftbBank_io_read_resp_tailSlot_tarStat),</a>
+<a name="1222"><span class="lineNum">    1222 </span>            :     .io_read_resp_tailSlot_sharing</a>
+<a name="1223"><span class="lineNum">    1223 </span>            :       (_ftbBank_io_read_resp_tailSlot_sharing),</a>
+<a name="1224"><span class="lineNum">    1224 </span>            :     .io_read_resp_tailSlot_valid</a>
+<a name="1225"><span class="lineNum">    1225 </span>            :       (_ftbBank_io_read_resp_tailSlot_valid),</a>
+<a name="1226"><span class="lineNum">    1226 </span>            :     .io_read_resp_pftAddr                                 (_ftbBank_io_read_resp_pftAddr),</a>
+<a name="1227"><span class="lineNum">    1227 </span>            :     .io_read_resp_carry                                   (_ftbBank_io_read_resp_carry),</a>
+<a name="1228"><span class="lineNum">    1228 </span>            :     .io_read_resp_isCall                                  (_ftbBank_io_read_resp_isCall),</a>
+<a name="1229"><span class="lineNum">    1229 </span>            :     .io_read_resp_isRet                                   (_ftbBank_io_read_resp_isRet),</a>
+<a name="1230"><span class="lineNum">    1230 </span>            :     .io_read_resp_isJalr                                  (_ftbBank_io_read_resp_isJalr),</a>
+<a name="1231"><span class="lineNum">    1231 </span>            :     .io_read_resp_last_may_be_rvi_call</a>
+<a name="1232"><span class="lineNum">    1232 </span>            :       (_ftbBank_io_read_resp_last_may_be_rvi_call),</a>
+<a name="1233"><span class="lineNum">    1233 </span>            :     .io_read_resp_always_taken_0</a>
+<a name="1234"><span class="lineNum">    1234 </span>            :       (_ftbBank_io_read_resp_always_taken_0),</a>
+<a name="1235"><span class="lineNum">    1235 </span>            :     .io_read_resp_always_taken_1</a>
+<a name="1236"><span class="lineNum">    1236 </span>            :       (_ftbBank_io_read_resp_always_taken_1),</a>
+<a name="1237"><span class="lineNum">    1237 </span>            :     .io_read_hits_valid                                   (_ftbBank_io_read_hits_valid),</a>
+<a name="1238"><span class="lineNum">    1238 </span>            :     .io_read_hits_bits                                    (_ftbBank_io_read_hits_bits),</a>
+<a name="1239"><span class="lineNum">    1239 </span>            :     .io_u_req_pc_valid                                    (update_need_read),</a>
+<a name="1240"><span class="lineNum">    1240 </span>            :     .io_u_req_pc_bits                                     (io_update_bits_pc),</a>
+<a name="1241"><span class="lineNum">    1241 </span>            :     .io_update_hits_valid                                 (_ftbBank_io_update_hits_valid),</a>
+<a name="1242"><span class="lineNum">    1242 </span>            :     .io_update_hits_bits                                  (_ftbBank_io_update_hits_bits),</a>
+<a name="1243"><span class="lineNum">    1243 </span>            :     .io_update_access</a>
+<a name="1244"><span class="lineNum">    1244 </span>            :       (u_valid &amp; ~(io_update_bits_meta[0])),</a>
+<a name="1245"><span class="lineNum">    1245 </span>            :     .io_update_pc                                         (_ftbBank_io_update_pc_T),</a>
+<a name="1246"><span class="lineNum">    1246 </span>            :     .io_update_write_data_valid</a>
+<a name="1247"><span class="lineNum">    1247 </span>            :       (update_now | _write_valid_delay_io_out),</a>
+<a name="1248"><span class="lineNum">    1248 </span>            :     .io_update_write_data_bits_entry_valid</a>
+<a name="1249"><span class="lineNum">    1249 </span>            :       (update_now</a>
+<a name="1250"><span class="lineNum">    1250 </span>            :          ? io_update_bits_ftb_entry_valid</a>
+<a name="1251"><span class="lineNum">    1251 </span>            :          : _delay2_entry_pipMod_io_out_bits_valid),</a>
+<a name="1252"><span class="lineNum">    1252 </span>            :     .io_update_write_data_bits_entry_brSlots_0_offset</a>
+<a name="1253"><span class="lineNum">    1253 </span>            :       (update_now</a>
+<a name="1254"><span class="lineNum">    1254 </span>            :          ? io_update_bits_ftb_entry_brSlots_0_offset</a>
+<a name="1255"><span class="lineNum">    1255 </span>            :          : _delay2_entry_pipMod_io_out_bits_brSlots_0_offset),</a>
+<a name="1256"><span class="lineNum">    1256 </span>            :     .io_update_write_data_bits_entry_brSlots_0_lower</a>
+<a name="1257"><span class="lineNum">    1257 </span>            :       (update_now</a>
+<a name="1258"><span class="lineNum">    1258 </span>            :          ? io_update_bits_ftb_entry_brSlots_0_lower</a>
+<a name="1259"><span class="lineNum">    1259 </span>            :          : _delay2_entry_pipMod_io_out_bits_brSlots_0_lower),</a>
+<a name="1260"><span class="lineNum">    1260 </span>            :     .io_update_write_data_bits_entry_brSlots_0_tarStat</a>
+<a name="1261"><span class="lineNum">    1261 </span>            :       (update_now</a>
+<a name="1262"><span class="lineNum">    1262 </span>            :          ? io_update_bits_ftb_entry_brSlots_0_tarStat</a>
+<a name="1263"><span class="lineNum">    1263 </span>            :          : _delay2_entry_pipMod_io_out_bits_brSlots_0_tarStat),</a>
+<a name="1264"><span class="lineNum">    1264 </span>            :     .io_update_write_data_bits_entry_brSlots_0_sharing</a>
+<a name="1265"><span class="lineNum">    1265 </span>            :       (update_now</a>
+<a name="1266"><span class="lineNum">    1266 </span>            :          ? io_update_bits_ftb_entry_brSlots_0_sharing</a>
+<a name="1267"><span class="lineNum">    1267 </span>            :          : _delay2_entry_pipMod_io_out_bits_brSlots_0_sharing),</a>
+<a name="1268"><span class="lineNum">    1268 </span>            :     .io_update_write_data_bits_entry_brSlots_0_valid</a>
+<a name="1269"><span class="lineNum">    1269 </span>            :       (update_now</a>
+<a name="1270"><span class="lineNum">    1270 </span>            :          ? io_update_bits_ftb_entry_brSlots_0_valid</a>
+<a name="1271"><span class="lineNum">    1271 </span>            :          : _delay2_entry_pipMod_io_out_bits_brSlots_0_valid),</a>
+<a name="1272"><span class="lineNum">    1272 </span>            :     .io_update_write_data_bits_entry_tailSlot_offset</a>
+<a name="1273"><span class="lineNum">    1273 </span>            :       (update_now</a>
+<a name="1274"><span class="lineNum">    1274 </span>            :          ? io_update_bits_ftb_entry_tailSlot_offset</a>
+<a name="1275"><span class="lineNum">    1275 </span>            :          : _delay2_entry_pipMod_io_out_bits_tailSlot_offset),</a>
+<a name="1276"><span class="lineNum">    1276 </span>            :     .io_update_write_data_bits_entry_tailSlot_lower</a>
+<a name="1277"><span class="lineNum">    1277 </span>            :       (update_now</a>
+<a name="1278"><span class="lineNum">    1278 </span>            :          ? io_update_bits_ftb_entry_tailSlot_lower</a>
+<a name="1279"><span class="lineNum">    1279 </span>            :          : _delay2_entry_pipMod_io_out_bits_tailSlot_lower),</a>
+<a name="1280"><span class="lineNum">    1280 </span>            :     .io_update_write_data_bits_entry_tailSlot_tarStat</a>
+<a name="1281"><span class="lineNum">    1281 </span>            :       (update_now</a>
+<a name="1282"><span class="lineNum">    1282 </span>            :          ? io_update_bits_ftb_entry_tailSlot_tarStat</a>
+<a name="1283"><span class="lineNum">    1283 </span>            :          : _delay2_entry_pipMod_io_out_bits_tailSlot_tarStat),</a>
+<a name="1284"><span class="lineNum">    1284 </span>            :     .io_update_write_data_bits_entry_tailSlot_sharing</a>
+<a name="1285"><span class="lineNum">    1285 </span>            :       (update_now</a>
+<a name="1286"><span class="lineNum">    1286 </span>            :          ? io_update_bits_ftb_entry_tailSlot_sharing</a>
+<a name="1287"><span class="lineNum">    1287 </span>            :          : _delay2_entry_pipMod_io_out_bits_tailSlot_sharing),</a>
+<a name="1288"><span class="lineNum">    1288 </span>            :     .io_update_write_data_bits_entry_tailSlot_valid</a>
+<a name="1289"><span class="lineNum">    1289 </span>            :       (update_now</a>
+<a name="1290"><span class="lineNum">    1290 </span>            :          ? io_update_bits_ftb_entry_tailSlot_valid</a>
+<a name="1291"><span class="lineNum">    1291 </span>            :          : _delay2_entry_pipMod_io_out_bits_tailSlot_valid),</a>
+<a name="1292"><span class="lineNum">    1292 </span>            :     .io_update_write_data_bits_entry_pftAddr</a>
+<a name="1293"><span class="lineNum">    1293 </span>            :       (update_now</a>
+<a name="1294"><span class="lineNum">    1294 </span>            :          ? io_update_bits_ftb_entry_pftAddr</a>
+<a name="1295"><span class="lineNum">    1295 </span>            :          : _delay2_entry_pipMod_io_out_bits_pftAddr),</a>
+<a name="1296"><span class="lineNum">    1296 </span>            :     .io_update_write_data_bits_entry_carry</a>
+<a name="1297"><span class="lineNum">    1297 </span>            :       (update_now</a>
+<a name="1298"><span class="lineNum">    1298 </span>            :          ? io_update_bits_ftb_entry_carry</a>
+<a name="1299"><span class="lineNum">    1299 </span>            :          : _delay2_entry_pipMod_io_out_bits_carry),</a>
+<a name="1300"><span class="lineNum">    1300 </span>            :     .io_update_write_data_bits_entry_isCall</a>
+<a name="1301"><span class="lineNum">    1301 </span>            :       (update_now</a>
+<a name="1302"><span class="lineNum">    1302 </span>            :          ? io_update_bits_ftb_entry_isCall</a>
+<a name="1303"><span class="lineNum">    1303 </span>            :          : _delay2_entry_pipMod_io_out_bits_isCall),</a>
+<a name="1304"><span class="lineNum">    1304 </span>            :     .io_update_write_data_bits_entry_isRet</a>
+<a name="1305"><span class="lineNum">    1305 </span>            :       (update_now</a>
+<a name="1306"><span class="lineNum">    1306 </span>            :          ? io_update_bits_ftb_entry_isRet</a>
+<a name="1307"><span class="lineNum">    1307 </span>            :          : _delay2_entry_pipMod_io_out_bits_isRet),</a>
+<a name="1308"><span class="lineNum">    1308 </span>            :     .io_update_write_data_bits_entry_isJalr</a>
+<a name="1309"><span class="lineNum">    1309 </span>            :       (update_now</a>
+<a name="1310"><span class="lineNum">    1310 </span>            :          ? io_update_bits_ftb_entry_isJalr</a>
+<a name="1311"><span class="lineNum">    1311 </span>            :          : _delay2_entry_pipMod_io_out_bits_isJalr),</a>
+<a name="1312"><span class="lineNum">    1312 </span>            :     .io_update_write_data_bits_entry_last_may_be_rvi_call</a>
+<a name="1313"><span class="lineNum">    1313 </span>            :       (update_now</a>
+<a name="1314"><span class="lineNum">    1314 </span>            :          ? io_update_bits_ftb_entry_last_may_be_rvi_call</a>
+<a name="1315"><span class="lineNum">    1315 </span>            :          : _delay2_entry_pipMod_io_out_bits_last_may_be_rvi_call),</a>
+<a name="1316"><span class="lineNum">    1316 </span>            :     .io_update_write_data_bits_entry_always_taken_0</a>
+<a name="1317"><span class="lineNum">    1317 </span>            :       (update_now</a>
+<a name="1318"><span class="lineNum">    1318 </span>            :          ? io_update_bits_ftb_entry_always_taken_0</a>
+<a name="1319"><span class="lineNum">    1319 </span>            :          : _delay2_entry_pipMod_io_out_bits_always_taken_0),</a>
+<a name="1320"><span class="lineNum">    1320 </span>            :     .io_update_write_data_bits_entry_always_taken_1</a>
+<a name="1321"><span class="lineNum">    1321 </span>            :       (update_now</a>
+<a name="1322"><span class="lineNum">    1322 </span>            :          ? io_update_bits_ftb_entry_always_taken_1</a>
+<a name="1323"><span class="lineNum">    1323 </span>            :          : _delay2_entry_pipMod_io_out_bits_always_taken_1),</a>
+<a name="1324"><span class="lineNum">    1324 </span>            :     .io_update_write_data_bits_tag</a>
+<a name="1325"><span class="lineNum">    1325 </span>            :       (_ftbBank_io_update_pc_T[29:10]),</a>
+<a name="1326"><span class="lineNum">    1326 </span>            :     .io_update_write_way</a>
+<a name="1327"><span class="lineNum">    1327 </span>            :       (update_now ? io_update_bits_meta[2:1] : ftbBank_io_update_write_way_REG),</a>
+<a name="1328"><span class="lineNum">    1328 </span>            :     .io_update_write_alloc</a>
+<a name="1329"><span class="lineNum">    1329 </span>            :       (~update_now &amp; ftbBank_io_update_write_alloc_REG)</a>
+<a name="1330"><span class="lineNum">    1330 </span>            :   );</a>
+<a name="1331"><span class="lineNum">    1331 </span>            :   DelayNWithValid delay2_pc_pipMod (</a>
+<a name="1332"><span class="lineNum">    1332 </span>            :     .clock       (clock),</a>
+<a name="1333"><span class="lineNum">    1333 </span>            :     .reset       (reset),</a>
+<a name="1334"><span class="lineNum">    1334 </span>            :     .io_in_bits  (io_update_bits_pc),</a>
+<a name="1335"><span class="lineNum">    1335 </span>            :     .io_in_valid (u_valid),</a>
+<a name="1336"><span class="lineNum">    1336 </span>            :     .io_out_bits (_delay2_pc_pipMod_io_out_bits)</a>
+<a name="1337"><span class="lineNum">    1337 </span>            :   );</a>
+<a name="1338"><span class="lineNum">    1338 </span>            :   DelayNWithValid_1 delay2_entry_pipMod (</a>
+<a name="1339"><span class="lineNum">    1339 </span>            :     .clock                            (clock),</a>
+<a name="1340"><span class="lineNum">    1340 </span>            :     .reset                            (reset),</a>
+<a name="1341"><span class="lineNum">    1341 </span>            :     .io_in_bits_valid                 (io_update_bits_ftb_entry_valid),</a>
+<a name="1342"><span class="lineNum">    1342 </span>            :     .io_in_bits_brSlots_0_offset      (io_update_bits_ftb_entry_brSlots_0_offset),</a>
+<a name="1343"><span class="lineNum">    1343 </span>            :     .io_in_bits_brSlots_0_lower       (io_update_bits_ftb_entry_brSlots_0_lower),</a>
+<a name="1344"><span class="lineNum">    1344 </span>            :     .io_in_bits_brSlots_0_tarStat     (io_update_bits_ftb_entry_brSlots_0_tarStat),</a>
+<a name="1345"><span class="lineNum">    1345 </span>            :     .io_in_bits_brSlots_0_sharing     (io_update_bits_ftb_entry_brSlots_0_sharing),</a>
+<a name="1346"><span class="lineNum">    1346 </span>            :     .io_in_bits_brSlots_0_valid       (io_update_bits_ftb_entry_brSlots_0_valid),</a>
+<a name="1347"><span class="lineNum">    1347 </span>            :     .io_in_bits_tailSlot_offset       (io_update_bits_ftb_entry_tailSlot_offset),</a>
+<a name="1348"><span class="lineNum">    1348 </span>            :     .io_in_bits_tailSlot_lower        (io_update_bits_ftb_entry_tailSlot_lower),</a>
+<a name="1349"><span class="lineNum">    1349 </span>            :     .io_in_bits_tailSlot_tarStat      (io_update_bits_ftb_entry_tailSlot_tarStat),</a>
+<a name="1350"><span class="lineNum">    1350 </span>            :     .io_in_bits_tailSlot_sharing      (io_update_bits_ftb_entry_tailSlot_sharing),</a>
+<a name="1351"><span class="lineNum">    1351 </span>            :     .io_in_bits_tailSlot_valid        (io_update_bits_ftb_entry_tailSlot_valid),</a>
+<a name="1352"><span class="lineNum">    1352 </span>            :     .io_in_bits_pftAddr               (io_update_bits_ftb_entry_pftAddr),</a>
+<a name="1353"><span class="lineNum">    1353 </span>            :     .io_in_bits_carry                 (io_update_bits_ftb_entry_carry),</a>
+<a name="1354"><span class="lineNum">    1354 </span>            :     .io_in_bits_isCall                (io_update_bits_ftb_entry_isCall),</a>
+<a name="1355"><span class="lineNum">    1355 </span>            :     .io_in_bits_isRet                 (io_update_bits_ftb_entry_isRet),</a>
+<a name="1356"><span class="lineNum">    1356 </span>            :     .io_in_bits_isJalr                (io_update_bits_ftb_entry_isJalr),</a>
+<a name="1357"><span class="lineNum">    1357 </span>            :     .io_in_bits_last_may_be_rvi_call  (io_update_bits_ftb_entry_last_may_be_rvi_call),</a>
+<a name="1358"><span class="lineNum">    1358 </span>            :     .io_in_bits_always_taken_0        (io_update_bits_ftb_entry_always_taken_0),</a>
+<a name="1359"><span class="lineNum">    1359 </span>            :     .io_in_bits_always_taken_1        (io_update_bits_ftb_entry_always_taken_1),</a>
+<a name="1360"><span class="lineNum">    1360 </span>            :     .io_in_valid                      (u_valid),</a>
+<a name="1361"><span class="lineNum">    1361 </span>            :     .io_out_bits_valid                (_delay2_entry_pipMod_io_out_bits_valid),</a>
+<a name="1362"><span class="lineNum">    1362 </span>            :     .io_out_bits_brSlots_0_offset     (_delay2_entry_pipMod_io_out_bits_brSlots_0_offset),</a>
+<a name="1363"><span class="lineNum">    1363 </span>            :     .io_out_bits_brSlots_0_lower      (_delay2_entry_pipMod_io_out_bits_brSlots_0_lower),</a>
+<a name="1364"><span class="lineNum">    1364 </span>            :     .io_out_bits_brSlots_0_tarStat</a>
+<a name="1365"><span class="lineNum">    1365 </span>            :       (_delay2_entry_pipMod_io_out_bits_brSlots_0_tarStat),</a>
+<a name="1366"><span class="lineNum">    1366 </span>            :     .io_out_bits_brSlots_0_sharing</a>
+<a name="1367"><span class="lineNum">    1367 </span>            :       (_delay2_entry_pipMod_io_out_bits_brSlots_0_sharing),</a>
+<a name="1368"><span class="lineNum">    1368 </span>            :     .io_out_bits_brSlots_0_valid      (_delay2_entry_pipMod_io_out_bits_brSlots_0_valid),</a>
+<a name="1369"><span class="lineNum">    1369 </span>            :     .io_out_bits_tailSlot_offset      (_delay2_entry_pipMod_io_out_bits_tailSlot_offset),</a>
+<a name="1370"><span class="lineNum">    1370 </span>            :     .io_out_bits_tailSlot_lower       (_delay2_entry_pipMod_io_out_bits_tailSlot_lower),</a>
+<a name="1371"><span class="lineNum">    1371 </span>            :     .io_out_bits_tailSlot_tarStat     (_delay2_entry_pipMod_io_out_bits_tailSlot_tarStat),</a>
+<a name="1372"><span class="lineNum">    1372 </span>            :     .io_out_bits_tailSlot_sharing     (_delay2_entry_pipMod_io_out_bits_tailSlot_sharing),</a>
+<a name="1373"><span class="lineNum">    1373 </span>            :     .io_out_bits_tailSlot_valid       (_delay2_entry_pipMod_io_out_bits_tailSlot_valid),</a>
+<a name="1374"><span class="lineNum">    1374 </span>            :     .io_out_bits_pftAddr              (_delay2_entry_pipMod_io_out_bits_pftAddr),</a>
+<a name="1375"><span class="lineNum">    1375 </span>            :     .io_out_bits_carry                (_delay2_entry_pipMod_io_out_bits_carry),</a>
+<a name="1376"><span class="lineNum">    1376 </span>            :     .io_out_bits_isCall               (_delay2_entry_pipMod_io_out_bits_isCall),</a>
+<a name="1377"><span class="lineNum">    1377 </span>            :     .io_out_bits_isRet                (_delay2_entry_pipMod_io_out_bits_isRet),</a>
+<a name="1378"><span class="lineNum">    1378 </span>            :     .io_out_bits_isJalr               (_delay2_entry_pipMod_io_out_bits_isJalr),</a>
+<a name="1379"><span class="lineNum">    1379 </span>            :     .io_out_bits_last_may_be_rvi_call</a>
+<a name="1380"><span class="lineNum">    1380 </span>            :       (_delay2_entry_pipMod_io_out_bits_last_may_be_rvi_call),</a>
+<a name="1381"><span class="lineNum">    1381 </span>            :     .io_out_bits_always_taken_0       (_delay2_entry_pipMod_io_out_bits_always_taken_0),</a>
+<a name="1382"><span class="lineNum">    1382 </span>            :     .io_out_bits_always_taken_1       (_delay2_entry_pipMod_io_out_bits_always_taken_1)</a>
+<a name="1383"><span class="lineNum">    1383 </span>            :   );</a>
+<a name="1384"><span class="lineNum">    1384 </span>            :   DelayN_4 write_valid_delay (</a>
+<a name="1385"><span class="lineNum">    1385 </span>            :     .clock  (clock),</a>
+<a name="1386"><span class="lineNum">    1386 </span>            :     .io_in  (u_valid &amp; ~(io_update_bits_meta[0])),</a>
+<a name="1387"><span class="lineNum">    1387 </span>            :     .io_out (_write_valid_delay_io_out)</a>
+<a name="1388"><span class="lineNum">    1388 </span>            :   );</a>
+<a name="1389"><span class="lineNum">    1389 </span>            :   assign io_out_s2_full_pred_0_br_taken_mask_0 =</a>
+<a name="1390"><span class="lineNum">    1390 </span>            :     io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_0 | s2_hit_dup_0</a>
+<a name="1391"><span class="lineNum">    1391 </span>            :     &amp; s2_ftb_entry_dup_0_always_taken_0;</a>
+<a name="1392"><span class="lineNum">    1392 </span>            :   assign io_out_s2_full_pred_0_br_taken_mask_1 =</a>
+<a name="1393"><span class="lineNum">    1393 </span>            :     io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_1 | s2_hit_dup_0</a>
+<a name="1394"><span class="lineNum">    1394 </span>            :     &amp; s2_ftb_entry_dup_0_always_taken_1;</a>
+<a name="1395"><span class="lineNum">    1395 </span>            :   assign io_out_s2_full_pred_0_slot_valids_0 = s2_ftb_entry_dup_0_brSlots_0_valid;</a>
+<a name="1396"><span class="lineNum">    1396 </span>            :   assign io_out_s2_full_pred_0_slot_valids_1 = s2_ftb_entry_dup_0_tailSlot_valid;</a>
+<a name="1397"><span class="lineNum">    1397 </span>            :   assign io_out_s2_full_pred_0_targets_0 =</a>
+<a name="1398"><span class="lineNum">    1398 </span>            :     {(s2_ftb_entry_dup_0_brSlots_0_tarStat == 2'h1 ? higher_plus_one_r : 28'h0)</a>
+<a name="1399"><span class="lineNum">    1399 </span>            :        | (s2_ftb_entry_dup_0_brSlots_0_tarStat == 2'h2 ? higher_minus_one_r : 28'h0)</a>
+<a name="1400"><span class="lineNum">    1400 </span>            :        | (s2_ftb_entry_dup_0_brSlots_0_tarStat == 2'h0 ? higher_r : 28'h0),</a>
+<a name="1401"><span class="lineNum">    1401 </span>            :      s2_ftb_entry_dup_0_brSlots_0_lower,</a>
+<a name="1402"><span class="lineNum">    1402 </span>            :      1'h0};</a>
+<a name="1403"><span class="lineNum">    1403 </span>            :   assign io_out_s2_full_pred_0_targets_1 = io_out_s2_full_pred_0_targets_1_0;</a>
+<a name="1404"><span class="lineNum">    1404 </span>            :   assign io_out_s2_full_pred_0_jalr_target = io_out_s2_full_pred_0_targets_1_0;</a>
+<a name="1405"><span class="lineNum">    1405 </span>            :   assign io_out_s2_full_pred_0_offsets_0 = s2_ftb_entry_dup_0_brSlots_0_offset;</a>
+<a name="1406"><span class="lineNum">    1406 </span>            :   assign io_out_s2_full_pred_0_offsets_1 = s2_ftb_entry_dup_0_tailSlot_offset;</a>
+<a name="1407"><span class="lineNum">    1407 </span>            :   assign io_out_s2_full_pred_0_fallThroughAddr =</a>
+<a name="1408"><span class="lineNum">    1408 </span>            :     {1'h0, s2_pc_dup_0[4:1]} &gt;= {s2_ftb_entry_dup_0_carry, s2_ftb_entry_dup_0_pftAddr}</a>
+<a name="1409"><span class="lineNum">    1409 </span>            :       ? 41'(s2_pc_dup_0 + 41'h20)</a>
+<a name="1410"><span class="lineNum">    1410 </span>            :       : {io_out_s2_full_pred_0_fallThroughAddr_stashed_carry</a>
+<a name="1411"><span class="lineNum">    1411 </span>            :            ? 36'(s2_pc_dup_0[40:5] + 36'h1)</a>
+<a name="1412"><span class="lineNum">    1412 </span>            :            : s2_pc_dup_0[40:5],</a>
+<a name="1413"><span class="lineNum">    1413 </span>            :          s2_ftb_entry_dup_0_pftAddr,</a>
+<a name="1414"><span class="lineNum">    1414 </span>            :          1'h0};</a>
+<a name="1415"><span class="lineNum">    1415 </span>            :   assign io_out_s2_full_pred_0_is_br_sharing =</a>
+<a name="1416"><span class="lineNum">    1416 </span>            :     s2_ftb_entry_dup_0_tailSlot_valid &amp; s2_ftb_entry_dup_0_tailSlot_sharing;</a>
+<a name="1417"><span class="lineNum">    1417 </span>            :   assign io_out_s2_full_pred_0_hit = s2_hit_dup_0;</a>
+<a name="1418"><span class="lineNum">    1418 </span>            :   assign io_out_s2_full_pred_1_br_taken_mask_0 =</a>
+<a name="1419"><span class="lineNum">    1419 </span>            :     io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_0 | s2_hit_dup_1</a>
+<a name="1420"><span class="lineNum">    1420 </span>            :     &amp; s2_ftb_entry_dup_1_always_taken_0;</a>
+<a name="1421"><span class="lineNum">    1421 </span>            :   assign io_out_s2_full_pred_1_br_taken_mask_1 =</a>
+<a name="1422"><span class="lineNum">    1422 </span>            :     io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_1 | s2_hit_dup_1</a>
+<a name="1423"><span class="lineNum">    1423 </span>            :     &amp; s2_ftb_entry_dup_1_always_taken_1;</a>
+<a name="1424"><span class="lineNum">    1424 </span>            :   assign io_out_s2_full_pred_1_slot_valids_0 = s2_ftb_entry_dup_1_brSlots_0_valid;</a>
+<a name="1425"><span class="lineNum">    1425 </span>            :   assign io_out_s2_full_pred_1_slot_valids_1 = s2_ftb_entry_dup_1_tailSlot_valid;</a>
+<a name="1426"><span class="lineNum">    1426 </span>            :   assign io_out_s2_full_pred_1_targets_0 =</a>
+<a name="1427"><span class="lineNum">    1427 </span>            :     {(s2_ftb_entry_dup_1_brSlots_0_tarStat == 2'h1 ? higher_plus_one_r_3 : 28'h0)</a>
+<a name="1428"><span class="lineNum">    1428 </span>            :        | (s2_ftb_entry_dup_1_brSlots_0_tarStat == 2'h2 ? higher_minus_one_r_3 : 28'h0)</a>
+<a name="1429"><span class="lineNum">    1429 </span>            :        | (s2_ftb_entry_dup_1_brSlots_0_tarStat == 2'h0 ? higher_r_3 : 28'h0),</a>
+<a name="1430"><span class="lineNum">    1430 </span>            :      s2_ftb_entry_dup_1_brSlots_0_lower,</a>
+<a name="1431"><span class="lineNum">    1431 </span>            :      1'h0};</a>
+<a name="1432"><span class="lineNum">    1432 </span>            :   assign io_out_s2_full_pred_1_targets_1 = io_out_s2_full_pred_1_targets_1_0;</a>
+<a name="1433"><span class="lineNum">    1433 </span>            :   assign io_out_s2_full_pred_1_jalr_target = io_out_s2_full_pred_1_targets_1_0;</a>
+<a name="1434"><span class="lineNum">    1434 </span>            :   assign io_out_s2_full_pred_1_offsets_0 = s2_ftb_entry_dup_1_brSlots_0_offset;</a>
+<a name="1435"><span class="lineNum">    1435 </span>            :   assign io_out_s2_full_pred_1_offsets_1 = s2_ftb_entry_dup_1_tailSlot_offset;</a>
+<a name="1436"><span class="lineNum">    1436 </span>            :   assign io_out_s2_full_pred_1_fallThroughAddr =</a>
+<a name="1437"><span class="lineNum">    1437 </span>            :     {1'h0, s2_pc_dup_1[4:1]} &gt;= {s2_ftb_entry_dup_1_carry, s2_ftb_entry_dup_1_pftAddr}</a>
+<a name="1438"><span class="lineNum">    1438 </span>            :       ? 41'(s2_pc_dup_1 + 41'h20)</a>
+<a name="1439"><span class="lineNum">    1439 </span>            :       : {io_out_s2_full_pred_1_fallThroughAddr_stashed_carry</a>
+<a name="1440"><span class="lineNum">    1440 </span>            :            ? 36'(s2_pc_dup_1[40:5] + 36'h1)</a>
+<a name="1441"><span class="lineNum">    1441 </span>            :            : s2_pc_dup_1[40:5],</a>
+<a name="1442"><span class="lineNum">    1442 </span>            :          s2_ftb_entry_dup_1_pftAddr,</a>
+<a name="1443"><span class="lineNum">    1443 </span>            :          1'h0};</a>
+<a name="1444"><span class="lineNum">    1444 </span>            :   assign io_out_s2_full_pred_1_is_br_sharing =</a>
+<a name="1445"><span class="lineNum">    1445 </span>            :     s2_ftb_entry_dup_1_tailSlot_valid &amp; s2_ftb_entry_dup_1_tailSlot_sharing;</a>
+<a name="1446"><span class="lineNum">    1446 </span>            :   assign io_out_s2_full_pred_1_hit = s2_hit_dup_1;</a>
+<a name="1447"><span class="lineNum">    1447 </span>            :   assign io_out_s2_full_pred_2_br_taken_mask_0 =</a>
+<a name="1448"><span class="lineNum">    1448 </span>            :     io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_0 | s2_hit_dup_2</a>
+<a name="1449"><span class="lineNum">    1449 </span>            :     &amp; s2_ftb_entry_dup_2_always_taken_0;</a>
+<a name="1450"><span class="lineNum">    1450 </span>            :   assign io_out_s2_full_pred_2_br_taken_mask_1 =</a>
+<a name="1451"><span class="lineNum">    1451 </span>            :     io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_1 | s2_hit_dup_2</a>
+<a name="1452"><span class="lineNum">    1452 </span>            :     &amp; s2_ftb_entry_dup_2_always_taken_1;</a>
+<a name="1453"><span class="lineNum">    1453 </span>            :   assign io_out_s2_full_pred_2_slot_valids_0 = s2_ftb_entry_dup_2_brSlots_0_valid;</a>
+<a name="1454"><span class="lineNum">    1454 </span>            :   assign io_out_s2_full_pred_2_slot_valids_1 = s2_ftb_entry_dup_2_tailSlot_valid;</a>
+<a name="1455"><span class="lineNum">    1455 </span>            :   assign io_out_s2_full_pred_2_targets_0 =</a>
+<a name="1456"><span class="lineNum">    1456 </span>            :     {(s2_ftb_entry_dup_2_brSlots_0_tarStat == 2'h1 ? higher_plus_one_r_6 : 28'h0)</a>
+<a name="1457"><span class="lineNum">    1457 </span>            :        | (s2_ftb_entry_dup_2_brSlots_0_tarStat == 2'h2 ? higher_minus_one_r_6 : 28'h0)</a>
+<a name="1458"><span class="lineNum">    1458 </span>            :        | (s2_ftb_entry_dup_2_brSlots_0_tarStat == 2'h0 ? higher_r_6 : 28'h0),</a>
+<a name="1459"><span class="lineNum">    1459 </span>            :      s2_ftb_entry_dup_2_brSlots_0_lower,</a>
+<a name="1460"><span class="lineNum">    1460 </span>            :      1'h0};</a>
+<a name="1461"><span class="lineNum">    1461 </span>            :   assign io_out_s2_full_pred_2_targets_1 = io_out_s2_full_pred_2_targets_1_0;</a>
+<a name="1462"><span class="lineNum">    1462 </span>            :   assign io_out_s2_full_pred_2_jalr_target = io_out_s2_full_pred_2_targets_1_0;</a>
+<a name="1463"><span class="lineNum">    1463 </span>            :   assign io_out_s2_full_pred_2_offsets_0 = s2_ftb_entry_dup_2_brSlots_0_offset;</a>
+<a name="1464"><span class="lineNum">    1464 </span>            :   assign io_out_s2_full_pred_2_offsets_1 = s2_ftb_entry_dup_2_tailSlot_offset;</a>
+<a name="1465"><span class="lineNum">    1465 </span>            :   assign io_out_s2_full_pred_2_fallThroughAddr =</a>
+<a name="1466"><span class="lineNum">    1466 </span>            :     {1'h0, s2_pc_dup_2[4:1]} &gt;= {s2_ftb_entry_dup_2_carry, s2_ftb_entry_dup_2_pftAddr}</a>
+<a name="1467"><span class="lineNum">    1467 </span>            :       ? 41'(s2_pc_dup_2 + 41'h20)</a>
+<a name="1468"><span class="lineNum">    1468 </span>            :       : {io_out_s2_full_pred_2_fallThroughAddr_stashed_carry</a>
+<a name="1469"><span class="lineNum">    1469 </span>            :            ? 36'(s2_pc_dup_2[40:5] + 36'h1)</a>
+<a name="1470"><span class="lineNum">    1470 </span>            :            : s2_pc_dup_2[40:5],</a>
+<a name="1471"><span class="lineNum">    1471 </span>            :          s2_ftb_entry_dup_2_pftAddr,</a>
+<a name="1472"><span class="lineNum">    1472 </span>            :          1'h0};</a>
+<a name="1473"><span class="lineNum">    1473 </span>            :   assign io_out_s2_full_pred_2_is_jalr =</a>
+<a name="1474"><span class="lineNum">    1474 </span>            :     s2_ftb_entry_dup_2_tailSlot_valid &amp; s2_ftb_entry_dup_2_isJalr;</a>
+<a name="1475"><span class="lineNum">    1475 </span>            :   assign io_out_s2_full_pred_2_is_call =</a>
+<a name="1476"><span class="lineNum">    1476 </span>            :     s2_ftb_entry_dup_2_tailSlot_valid &amp; s2_ftb_entry_dup_2_isCall;</a>
+<a name="1477"><span class="lineNum">    1477 </span>            :   assign io_out_s2_full_pred_2_is_ret =</a>
+<a name="1478"><span class="lineNum">    1478 </span>            :     s2_ftb_entry_dup_2_tailSlot_valid &amp; s2_ftb_entry_dup_2_isRet;</a>
+<a name="1479"><span class="lineNum">    1479 </span>            :   assign io_out_s2_full_pred_2_last_may_be_rvi_call =</a>
+<a name="1480"><span class="lineNum">    1480 </span>            :     s2_ftb_entry_dup_2_last_may_be_rvi_call;</a>
+<a name="1481"><span class="lineNum">    1481 </span>            :   assign io_out_s2_full_pred_2_is_br_sharing =</a>
+<a name="1482"><span class="lineNum">    1482 </span>            :     s2_ftb_entry_dup_2_tailSlot_valid &amp; s2_ftb_entry_dup_2_tailSlot_sharing;</a>
+<a name="1483"><span class="lineNum">    1483 </span>            :   assign io_out_s2_full_pred_2_hit = s2_hit_dup_2;</a>
+<a name="1484"><span class="lineNum">    1484 </span>            :   assign io_out_s2_full_pred_3_br_taken_mask_0 =</a>
+<a name="1485"><span class="lineNum">    1485 </span>            :     io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_0 | s2_hit_dup_3</a>
+<a name="1486"><span class="lineNum">    1486 </span>            :     &amp; s2_ftb_entry_dup_3_always_taken_0;</a>
+<a name="1487"><span class="lineNum">    1487 </span>            :   assign io_out_s2_full_pred_3_br_taken_mask_1 =</a>
+<a name="1488"><span class="lineNum">    1488 </span>            :     io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_1 | s2_hit_dup_3</a>
+<a name="1489"><span class="lineNum">    1489 </span>            :     &amp; s2_ftb_entry_dup_3_always_taken_1;</a>
+<a name="1490"><span class="lineNum">    1490 </span>            :   assign io_out_s2_full_pred_3_slot_valids_0 = s2_ftb_entry_dup_3_brSlots_0_valid;</a>
+<a name="1491"><span class="lineNum">    1491 </span>            :   assign io_out_s2_full_pred_3_slot_valids_1 = s2_ftb_entry_dup_3_tailSlot_valid;</a>
+<a name="1492"><span class="lineNum">    1492 </span>            :   assign io_out_s2_full_pred_3_targets_0 =</a>
+<a name="1493"><span class="lineNum">    1493 </span>            :     {(s2_ftb_entry_dup_3_brSlots_0_tarStat == 2'h1 ? higher_plus_one_r_9 : 28'h0)</a>
+<a name="1494"><span class="lineNum">    1494 </span>            :        | (s2_ftb_entry_dup_3_brSlots_0_tarStat == 2'h2 ? higher_minus_one_r_9 : 28'h0)</a>
+<a name="1495"><span class="lineNum">    1495 </span>            :        | (s2_ftb_entry_dup_3_brSlots_0_tarStat == 2'h0 ? higher_r_9 : 28'h0),</a>
+<a name="1496"><span class="lineNum">    1496 </span>            :      s2_ftb_entry_dup_3_brSlots_0_lower,</a>
+<a name="1497"><span class="lineNum">    1497 </span>            :      1'h0};</a>
+<a name="1498"><span class="lineNum">    1498 </span>            :   assign io_out_s2_full_pred_3_targets_1 = io_out_s2_full_pred_3_targets_1_0;</a>
+<a name="1499"><span class="lineNum">    1499 </span>            :   assign io_out_s2_full_pred_3_jalr_target = io_out_s2_full_pred_3_targets_1_0;</a>
+<a name="1500"><span class="lineNum">    1500 </span>            :   assign io_out_s2_full_pred_3_offsets_0 = s2_ftb_entry_dup_3_brSlots_0_offset;</a>
+<a name="1501"><span class="lineNum">    1501 </span>            :   assign io_out_s2_full_pred_3_offsets_1 = s2_ftb_entry_dup_3_tailSlot_offset;</a>
+<a name="1502"><span class="lineNum">    1502 </span>            :   assign io_out_s2_full_pred_3_fallThroughAddr =</a>
+<a name="1503"><span class="lineNum">    1503 </span>            :     io_out_s2_full_pred_3_fallThroughErr_0</a>
+<a name="1504"><span class="lineNum">    1504 </span>            :       ? 41'(s2_pc_dup_3 + 41'h20)</a>
+<a name="1505"><span class="lineNum">    1505 </span>            :       : {io_out_s2_full_pred_3_fallThroughAddr_stashed_carry</a>
+<a name="1506"><span class="lineNum">    1506 </span>            :            ? 36'(s2_pc_dup_3[40:5] + 36'h1)</a>
+<a name="1507"><span class="lineNum">    1507 </span>            :            : s2_pc_dup_3[40:5],</a>
+<a name="1508"><span class="lineNum">    1508 </span>            :          s2_ftb_entry_dup_3_pftAddr,</a>
+<a name="1509"><span class="lineNum">    1509 </span>            :          1'h0};</a>
+<a name="1510"><span class="lineNum">    1510 </span>            :   assign io_out_s2_full_pred_3_fallThroughErr = io_out_s2_full_pred_3_fallThroughErr_0;</a>
+<a name="1511"><span class="lineNum">    1511 </span>            :   assign io_out_s2_full_pred_3_is_br_sharing =</a>
+<a name="1512"><span class="lineNum">    1512 </span>            :     s2_ftb_entry_dup_3_tailSlot_valid &amp; s2_ftb_entry_dup_3_tailSlot_sharing;</a>
+<a name="1513"><span class="lineNum">    1513 </span>            :   assign io_out_s2_full_pred_3_hit = s2_hit_dup_3;</a>
+<a name="1514"><span class="lineNum">    1514 </span>            :   assign io_out_s3_full_pred_0_br_taken_mask_0 =</a>
+<a name="1515"><span class="lineNum">    1515 </span>            :     io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_0 | s3_hit_dup_0</a>
+<a name="1516"><span class="lineNum">    1516 </span>            :     &amp; s3_ftb_entry_dup_0_always_taken_0;</a>
+<a name="1517"><span class="lineNum">    1517 </span>            :   assign io_out_s3_full_pred_0_br_taken_mask_1 =</a>
+<a name="1518"><span class="lineNum">    1518 </span>            :     io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_1 | s3_hit_dup_0</a>
+<a name="1519"><span class="lineNum">    1519 </span>            :     &amp; s3_ftb_entry_dup_0_always_taken_1;</a>
+<a name="1520"><span class="lineNum">    1520 </span>            :   assign io_out_s3_full_pred_0_slot_valids_0 = s3_ftb_entry_dup_0_brSlots_0_valid;</a>
+<a name="1521"><span class="lineNum">    1521 </span>            :   assign io_out_s3_full_pred_0_slot_valids_1 = s3_ftb_entry_dup_0_tailSlot_valid;</a>
+<a name="1522"><span class="lineNum">    1522 </span>            :   assign io_out_s3_full_pred_0_targets_0 =</a>
+<a name="1523"><span class="lineNum">    1523 </span>            :     {(s3_ftb_entry_dup_0_brSlots_0_tarStat == 2'h1 ? higher_plus_one_r_12 : 28'h0)</a>
+<a name="1524"><span class="lineNum">    1524 </span>            :        | (s3_ftb_entry_dup_0_brSlots_0_tarStat == 2'h2 ? higher_minus_one_r_12 : 28'h0)</a>
+<a name="1525"><span class="lineNum">    1525 </span>            :        | (s3_ftb_entry_dup_0_brSlots_0_tarStat == 2'h0 ? higher_r_12 : 28'h0),</a>
+<a name="1526"><span class="lineNum">    1526 </span>            :      s3_ftb_entry_dup_0_brSlots_0_lower,</a>
+<a name="1527"><span class="lineNum">    1527 </span>            :      1'h0};</a>
+<a name="1528"><span class="lineNum">    1528 </span>            :   assign io_out_s3_full_pred_0_targets_1 = io_out_s3_full_pred_0_targets_1_0;</a>
+<a name="1529"><span class="lineNum">    1529 </span>            :   assign io_out_s3_full_pred_0_jalr_target = io_out_s3_full_pred_0_targets_1_0;</a>
+<a name="1530"><span class="lineNum">    1530 </span>            :   assign io_out_s3_full_pred_0_fallThroughAddr =</a>
+<a name="1531"><span class="lineNum">    1531 </span>            :     io_out_s3_full_pred_0_fallThroughErr_0</a>
+<a name="1532"><span class="lineNum">    1532 </span>            :       ? 41'(s3_pc_dup_0 + 41'h20)</a>
+<a name="1533"><span class="lineNum">    1533 </span>            :       : {s3_ftb_entry_dup_0_carry ? 36'(s3_pc_dup_0[40:5] + 36'h1) : s3_pc_dup_0[40:5],</a>
+<a name="1534"><span class="lineNum">    1534 </span>            :          s3_ftb_entry_dup_0_pftAddr,</a>
+<a name="1535"><span class="lineNum">    1535 </span>            :          1'h0};</a>
+<a name="1536"><span class="lineNum">    1536 </span>            :   assign io_out_s3_full_pred_0_fallThroughErr = io_out_s3_full_pred_0_fallThroughErr_0;</a>
+<a name="1537"><span class="lineNum">    1537 </span>            :   assign io_out_s3_full_pred_0_is_br_sharing =</a>
+<a name="1538"><span class="lineNum">    1538 </span>            :     s3_ftb_entry_dup_0_tailSlot_valid &amp; s3_ftb_entry_dup_0_tailSlot_sharing;</a>
+<a name="1539"><span class="lineNum">    1539 </span>            :   assign io_out_s3_full_pred_0_hit = s3_hit_dup_0;</a>
+<a name="1540"><span class="lineNum">    1540 </span>            :   assign io_out_s3_full_pred_1_br_taken_mask_0 =</a>
+<a name="1541"><span class="lineNum">    1541 </span>            :     io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_0 | s3_hit_dup_1</a>
+<a name="1542"><span class="lineNum">    1542 </span>            :     &amp; s3_ftb_entry_dup_1_always_taken_0;</a>
+<a name="1543"><span class="lineNum">    1543 </span>            :   assign io_out_s3_full_pred_1_br_taken_mask_1 =</a>
+<a name="1544"><span class="lineNum">    1544 </span>            :     io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_1 | s3_hit_dup_1</a>
+<a name="1545"><span class="lineNum">    1545 </span>            :     &amp; s3_ftb_entry_dup_1_always_taken_1;</a>
+<a name="1546"><span class="lineNum">    1546 </span>            :   assign io_out_s3_full_pred_1_slot_valids_0 = s3_ftb_entry_dup_1_brSlots_0_valid;</a>
+<a name="1547"><span class="lineNum">    1547 </span>            :   assign io_out_s3_full_pred_1_slot_valids_1 = s3_ftb_entry_dup_1_tailSlot_valid;</a>
+<a name="1548"><span class="lineNum">    1548 </span>            :   assign io_out_s3_full_pred_1_targets_0 =</a>
+<a name="1549"><span class="lineNum">    1549 </span>            :     {(s3_ftb_entry_dup_1_brSlots_0_tarStat == 2'h1 ? higher_plus_one_r_15 : 28'h0)</a>
+<a name="1550"><span class="lineNum">    1550 </span>            :        | (s3_ftb_entry_dup_1_brSlots_0_tarStat == 2'h2 ? higher_minus_one_r_15 : 28'h0)</a>
+<a name="1551"><span class="lineNum">    1551 </span>            :        | (s3_ftb_entry_dup_1_brSlots_0_tarStat == 2'h0 ? higher_r_15 : 28'h0),</a>
+<a name="1552"><span class="lineNum">    1552 </span>            :      s3_ftb_entry_dup_1_brSlots_0_lower,</a>
+<a name="1553"><span class="lineNum">    1553 </span>            :      1'h0};</a>
+<a name="1554"><span class="lineNum">    1554 </span>            :   assign io_out_s3_full_pred_1_targets_1 = io_out_s3_full_pred_1_targets_1_0;</a>
+<a name="1555"><span class="lineNum">    1555 </span>            :   assign io_out_s3_full_pred_1_jalr_target = io_out_s3_full_pred_1_targets_1_0;</a>
+<a name="1556"><span class="lineNum">    1556 </span>            :   assign io_out_s3_full_pred_1_fallThroughAddr =</a>
+<a name="1557"><span class="lineNum">    1557 </span>            :     io_out_s3_full_pred_1_fallThroughErr_0</a>
+<a name="1558"><span class="lineNum">    1558 </span>            :       ? 41'(s3_pc_dup_1 + 41'h20)</a>
+<a name="1559"><span class="lineNum">    1559 </span>            :       : {s3_ftb_entry_dup_1_carry ? 36'(s3_pc_dup_1[40:5] + 36'h1) : s3_pc_dup_1[40:5],</a>
+<a name="1560"><span class="lineNum">    1560 </span>            :          s3_ftb_entry_dup_1_pftAddr,</a>
+<a name="1561"><span class="lineNum">    1561 </span>            :          1'h0};</a>
+<a name="1562"><span class="lineNum">    1562 </span>            :   assign io_out_s3_full_pred_1_fallThroughErr = io_out_s3_full_pred_1_fallThroughErr_0;</a>
+<a name="1563"><span class="lineNum">    1563 </span>            :   assign io_out_s3_full_pred_1_is_br_sharing =</a>
+<a name="1564"><span class="lineNum">    1564 </span>            :     s3_ftb_entry_dup_1_tailSlot_valid &amp; s3_ftb_entry_dup_1_tailSlot_sharing;</a>
+<a name="1565"><span class="lineNum">    1565 </span>            :   assign io_out_s3_full_pred_1_hit = s3_hit_dup_1;</a>
+<a name="1566"><span class="lineNum">    1566 </span>            :   assign io_out_s3_full_pred_2_br_taken_mask_0 =</a>
+<a name="1567"><span class="lineNum">    1567 </span>            :     io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_0 | s3_hit_dup_2</a>
+<a name="1568"><span class="lineNum">    1568 </span>            :     &amp; s3_ftb_entry_dup_2_always_taken_0;</a>
+<a name="1569"><span class="lineNum">    1569 </span>            :   assign io_out_s3_full_pred_2_br_taken_mask_1 =</a>
+<a name="1570"><span class="lineNum">    1570 </span>            :     io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_1 | s3_hit_dup_2</a>
+<a name="1571"><span class="lineNum">    1571 </span>            :     &amp; s3_ftb_entry_dup_2_always_taken_1;</a>
+<a name="1572"><span class="lineNum">    1572 </span>            :   assign io_out_s3_full_pred_2_slot_valids_0 = s3_ftb_entry_dup_2_brSlots_0_valid;</a>
+<a name="1573"><span class="lineNum">    1573 </span>            :   assign io_out_s3_full_pred_2_slot_valids_1 = s3_ftb_entry_dup_2_tailSlot_valid;</a>
+<a name="1574"><span class="lineNum">    1574 </span>            :   assign io_out_s3_full_pred_2_targets_0 =</a>
+<a name="1575"><span class="lineNum">    1575 </span>            :     {(s3_ftb_entry_dup_2_brSlots_0_tarStat == 2'h1 ? higher_plus_one_r_18 : 28'h0)</a>
+<a name="1576"><span class="lineNum">    1576 </span>            :        | (s3_ftb_entry_dup_2_brSlots_0_tarStat == 2'h2 ? higher_minus_one_r_18 : 28'h0)</a>
+<a name="1577"><span class="lineNum">    1577 </span>            :        | (s3_ftb_entry_dup_2_brSlots_0_tarStat == 2'h0 ? higher_r_18 : 28'h0),</a>
+<a name="1578"><span class="lineNum">    1578 </span>            :      s3_ftb_entry_dup_2_brSlots_0_lower,</a>
+<a name="1579"><span class="lineNum">    1579 </span>            :      1'h0};</a>
+<a name="1580"><span class="lineNum">    1580 </span>            :   assign io_out_s3_full_pred_2_targets_1 = io_out_s3_full_pred_2_targets_1_0;</a>
+<a name="1581"><span class="lineNum">    1581 </span>            :   assign io_out_s3_full_pred_2_jalr_target = io_out_s3_full_pred_2_targets_1_0;</a>
+<a name="1582"><span class="lineNum">    1582 </span>            :   assign io_out_s3_full_pred_2_fallThroughAddr =</a>
+<a name="1583"><span class="lineNum">    1583 </span>            :     io_out_s3_full_pred_2_fallThroughErr_0</a>
+<a name="1584"><span class="lineNum">    1584 </span>            :       ? 41'(s3_pc_dup_2 + 41'h20)</a>
+<a name="1585"><span class="lineNum">    1585 </span>            :       : {s3_ftb_entry_dup_2_carry ? 36'(s3_pc_dup_2[40:5] + 36'h1) : s3_pc_dup_2[40:5],</a>
+<a name="1586"><span class="lineNum">    1586 </span>            :          s3_ftb_entry_dup_2_pftAddr,</a>
+<a name="1587"><span class="lineNum">    1587 </span>            :          1'h0};</a>
+<a name="1588"><span class="lineNum">    1588 </span>            :   assign io_out_s3_full_pred_2_fallThroughErr = io_out_s3_full_pred_2_fallThroughErr_0;</a>
+<a name="1589"><span class="lineNum">    1589 </span>            :   assign io_out_s3_full_pred_2_is_jalr =</a>
+<a name="1590"><span class="lineNum">    1590 </span>            :     s3_ftb_entry_dup_2_tailSlot_valid &amp; s3_ftb_entry_dup_2_isJalr;</a>
+<a name="1591"><span class="lineNum">    1591 </span>            :   assign io_out_s3_full_pred_2_is_call =</a>
+<a name="1592"><span class="lineNum">    1592 </span>            :     s3_ftb_entry_dup_2_tailSlot_valid &amp; s3_ftb_entry_dup_2_isCall;</a>
+<a name="1593"><span class="lineNum">    1593 </span>            :   assign io_out_s3_full_pred_2_is_ret =</a>
+<a name="1594"><span class="lineNum">    1594 </span>            :     s3_ftb_entry_dup_2_tailSlot_valid &amp; s3_ftb_entry_dup_2_isRet;</a>
+<a name="1595"><span class="lineNum">    1595 </span>            :   assign io_out_s3_full_pred_2_is_br_sharing =</a>
+<a name="1596"><span class="lineNum">    1596 </span>            :     s3_ftb_entry_dup_2_tailSlot_valid &amp; s3_ftb_entry_dup_2_tailSlot_sharing;</a>
+<a name="1597"><span class="lineNum">    1597 </span>            :   assign io_out_s3_full_pred_2_hit = s3_hit_dup_2;</a>
+<a name="1598"><span class="lineNum">    1598 </span>            :   assign io_out_s3_full_pred_3_br_taken_mask_0 =</a>
+<a name="1599"><span class="lineNum">    1599 </span>            :     io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_0 | s3_hit_dup_3</a>
+<a name="1600"><span class="lineNum">    1600 </span>            :     &amp; s3_ftb_entry_dup_3_always_taken_0;</a>
+<a name="1601"><span class="lineNum">    1601 </span>            :   assign io_out_s3_full_pred_3_br_taken_mask_1 =</a>
+<a name="1602"><span class="lineNum">    1602 </span>            :     io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_1 | s3_hit_dup_3</a>
+<a name="1603"><span class="lineNum">    1603 </span>            :     &amp; s3_ftb_entry_dup_3_always_taken_1;</a>
+<a name="1604"><span class="lineNum">    1604 </span>            :   assign io_out_s3_full_pred_3_slot_valids_0 = s3_ftb_entry_dup_3_brSlots_0_valid;</a>
+<a name="1605"><span class="lineNum">    1605 </span>            :   assign io_out_s3_full_pred_3_slot_valids_1 = s3_ftb_entry_dup_3_tailSlot_valid;</a>
+<a name="1606"><span class="lineNum">    1606 </span>            :   assign io_out_s3_full_pred_3_targets_0 =</a>
+<a name="1607"><span class="lineNum">    1607 </span>            :     {(s3_ftb_entry_dup_3_brSlots_0_tarStat == 2'h1 ? higher_plus_one_r_21 : 28'h0)</a>
+<a name="1608"><span class="lineNum">    1608 </span>            :        | (s3_ftb_entry_dup_3_brSlots_0_tarStat == 2'h2 ? higher_minus_one_r_21 : 28'h0)</a>
+<a name="1609"><span class="lineNum">    1609 </span>            :        | (s3_ftb_entry_dup_3_brSlots_0_tarStat == 2'h0 ? higher_r_21 : 28'h0),</a>
+<a name="1610"><span class="lineNum">    1610 </span>            :      s3_ftb_entry_dup_3_brSlots_0_lower,</a>
+<a name="1611"><span class="lineNum">    1611 </span>            :      1'h0};</a>
+<a name="1612"><span class="lineNum">    1612 </span>            :   assign io_out_s3_full_pred_3_targets_1 = io_out_s3_full_pred_3_targets_1_0;</a>
+<a name="1613"><span class="lineNum">    1613 </span>            :   assign io_out_s3_full_pred_3_jalr_target = io_out_s3_full_pred_3_targets_1_0;</a>
+<a name="1614"><span class="lineNum">    1614 </span>            :   assign io_out_s3_full_pred_3_offsets_0 = s3_ftb_entry_dup_3_brSlots_0_offset;</a>
+<a name="1615"><span class="lineNum">    1615 </span>            :   assign io_out_s3_full_pred_3_offsets_1 = s3_ftb_entry_dup_3_tailSlot_offset;</a>
+<a name="1616"><span class="lineNum">    1616 </span>            :   assign io_out_s3_full_pred_3_fallThroughAddr =</a>
+<a name="1617"><span class="lineNum">    1617 </span>            :     io_out_s3_full_pred_3_fallThroughErr_0</a>
+<a name="1618"><span class="lineNum">    1618 </span>            :       ? 41'(s3_pc_dup_3 + 41'h20)</a>
+<a name="1619"><span class="lineNum">    1619 </span>            :       : {s3_ftb_entry_dup_3_carry ? 36'(s3_pc_dup_3[40:5] + 36'h1) : s3_pc_dup_3[40:5],</a>
+<a name="1620"><span class="lineNum">    1620 </span>            :          s3_ftb_entry_dup_3_pftAddr,</a>
+<a name="1621"><span class="lineNum">    1621 </span>            :          1'h0};</a>
+<a name="1622"><span class="lineNum">    1622 </span>            :   assign io_out_s3_full_pred_3_fallThroughErr = io_out_s3_full_pred_3_fallThroughErr_0;</a>
+<a name="1623"><span class="lineNum">    1623 </span>            :   assign io_out_s3_full_pred_3_is_br_sharing =</a>
+<a name="1624"><span class="lineNum">    1624 </span>            :     s3_ftb_entry_dup_3_tailSlot_valid &amp; s3_ftb_entry_dup_3_tailSlot_sharing;</a>
+<a name="1625"><span class="lineNum">    1625 </span>            :   assign io_out_s3_full_pred_3_hit = s3_hit_dup_3;</a>
+<a name="1626"><span class="lineNum">    1626 </span>            :   assign io_out_last_stage_meta = {220'h0, io_out_last_stage_meta_r_1};</a>
+<a name="1627"><span class="lineNum">    1627 </span>            :   assign io_out_last_stage_ftb_entry_valid = s3_ftb_entry_dup_0_valid;</a>
+<a name="1628"><span class="lineNum">    1628 </span>            :   assign io_out_last_stage_ftb_entry_brSlots_0_offset =</a>
+<a name="1629"><span class="lineNum">    1629 </span>            :     s3_ftb_entry_dup_0_brSlots_0_offset;</a>
+<a name="1630"><span class="lineNum">    1630 </span>            :   assign io_out_last_stage_ftb_entry_brSlots_0_lower = s3_ftb_entry_dup_0_brSlots_0_lower;</a>
+<a name="1631"><span class="lineNum">    1631 </span>            :   assign io_out_last_stage_ftb_entry_brSlots_0_tarStat =</a>
+<a name="1632"><span class="lineNum">    1632 </span>            :     s3_ftb_entry_dup_0_brSlots_0_tarStat;</a>
+<a name="1633"><span class="lineNum">    1633 </span>            :   assign io_out_last_stage_ftb_entry_brSlots_0_sharing =</a>
+<a name="1634"><span class="lineNum">    1634 </span>            :     s3_ftb_entry_dup_0_brSlots_0_sharing;</a>
+<a name="1635"><span class="lineNum">    1635 </span>            :   assign io_out_last_stage_ftb_entry_brSlots_0_valid = s3_ftb_entry_dup_0_brSlots_0_valid;</a>
+<a name="1636"><span class="lineNum">    1636 </span>            :   assign io_out_last_stage_ftb_entry_tailSlot_offset = s3_ftb_entry_dup_0_tailSlot_offset;</a>
+<a name="1637"><span class="lineNum">    1637 </span>            :   assign io_out_last_stage_ftb_entry_tailSlot_lower = s3_ftb_entry_dup_0_tailSlot_lower;</a>
+<a name="1638"><span class="lineNum">    1638 </span>            :   assign io_out_last_stage_ftb_entry_tailSlot_tarStat =</a>
+<a name="1639"><span class="lineNum">    1639 </span>            :     s3_ftb_entry_dup_0_tailSlot_tarStat;</a>
+<a name="1640"><span class="lineNum">    1640 </span>            :   assign io_out_last_stage_ftb_entry_tailSlot_sharing =</a>
+<a name="1641"><span class="lineNum">    1641 </span>            :     s3_ftb_entry_dup_0_tailSlot_sharing;</a>
+<a name="1642"><span class="lineNum">    1642 </span>            :   assign io_out_last_stage_ftb_entry_tailSlot_valid = s3_ftb_entry_dup_0_tailSlot_valid;</a>
+<a name="1643"><span class="lineNum">    1643 </span>            :   assign io_out_last_stage_ftb_entry_pftAddr = s3_ftb_entry_dup_0_pftAddr;</a>
+<a name="1644"><span class="lineNum">    1644 </span>            :   assign io_out_last_stage_ftb_entry_carry = s3_ftb_entry_dup_0_carry;</a>
+<a name="1645"><span class="lineNum">    1645 </span>            :   assign io_out_last_stage_ftb_entry_isCall = s3_ftb_entry_dup_0_isCall;</a>
+<a name="1646"><span class="lineNum">    1646 </span>            :   assign io_out_last_stage_ftb_entry_isRet = s3_ftb_entry_dup_0_isRet;</a>
+<a name="1647"><span class="lineNum">    1647 </span>            :   assign io_out_last_stage_ftb_entry_isJalr = s3_ftb_entry_dup_0_isJalr;</a>
+<a name="1648"><span class="lineNum">    1648 </span>            :   assign io_out_last_stage_ftb_entry_last_may_be_rvi_call =</a>
+<a name="1649"><span class="lineNum">    1649 </span>            :     s3_ftb_entry_dup_0_last_may_be_rvi_call;</a>
+<a name="1650"><span class="lineNum">    1650 </span>            :   assign io_out_last_stage_ftb_entry_always_taken_0 = s3_ftb_entry_dup_0_always_taken_0;</a>
+<a name="1651"><span class="lineNum">    1651 </span>            :   assign io_out_last_stage_ftb_entry_always_taken_1 = s3_ftb_entry_dup_0_always_taken_1;</a>
+<a name="1652"><span class="lineNum">    1652 </span>            :   assign io_s1_ready = _ftbBank_io_req_pc_ready &amp; ~update_need_read &amp; ~io_s1_ready_REG;</a>
+<a name="1653"><span class="lineNum">    1653 </span>            :   assign io_perf_0_value = {5'h0, io_perf_0_value_REG_1};</a>
+<a name="1654"><span class="lineNum">    1654 </span>            :   assign io_perf_1_value = {5'h0, io_perf_1_value_REG_1};</a>
+<a name="1655"><span class="lineNum">    1655 </span>            : endmodule</a>
+<a name="1656"><span class="lineNum">    1656 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FTBBank.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FTBBank.sv.func-sort-c.html
new file mode 100644
index 0000000..d0080e5
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FTBBank.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/FTBBank.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - FTBBank.sv<span style="font-size: 80%;"> (<a href="FTBBank.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">1935</td>
+            <td class="headerCovTableEntry">4420</td>
+            <td class="headerCovTableEntryLo">43.8 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="FTBBank.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FTBBank.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FTBBank.sv.func.html
new file mode 100644
index 0000000..e7841bb
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FTBBank.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/FTBBank.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - FTBBank.sv<span style="font-size: 80%;"> (<a href="FTBBank.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">1935</td>
+            <td class="headerCovTableEntry">4420</td>
+            <td class="headerCovTableEntryLo">43.8 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="FTBBank.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FTBBank.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FTBBank.sv.gcov.html
new file mode 100644
index 0000000..b06fde6
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FTBBank.sv.gcov.html
@@ -0,0 +1,6446 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/FTBBank.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - FTBBank.sv<span style="font-size: 80%;"> (source / <a href="FTBBank.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">1935</td>
+            <td class="headerCovTableEntry">4420</td>
+            <td class="headerCovTableEntryLo">43.8 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : module FTBBank(</a>
+<a name="59"><span class="lineNum">      59 </span><span class="lineCov">     127786 :   input         clock,</span></a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">         62 :   input         reset,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">        133 :   input         io_s1_fire,</span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">         90 : </span></a>
+<a name="63"><span class="lineNum">      63 </span><span class="lineCov">         75 :   output        io_req_pc_ready,</span></a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">      10337 :   input         io_req_pc_valid,</span></a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">         16 :   input  [40:0] io_req_pc_bits,</span></a>
+<a name="66"><span class="lineNum">      66 </span><span class="lineCov">         55 :   output        io_read_resp_valid,</span></a>
+<a name="67"><span class="lineNum">      67 </span><span class="lineCov">        166 :   output [3:0]  io_read_resp_brSlots_0_offset,</span></a>
+<a name="68"><span class="lineNum">      68 </span><span class="lineCov">         31 :   output [11:0] io_read_resp_brSlots_0_lower,</span></a>
+<a name="69"><span class="lineNum">      69 </span><span class="lineCov">         14 :   output [1:0]  io_read_resp_brSlots_0_tarStat,</span></a>
+<a name="70"><span class="lineNum">      70 </span><span class="lineCov">         12 :   output        io_read_resp_brSlots_0_sharing,</span></a>
+<a name="71"><span class="lineNum">      71 </span><span class="lineCov">         57 :   output        io_read_resp_brSlots_0_valid,</span></a>
+<a name="72"><span class="lineNum">      72 </span><span class="lineCov">        311 :   output [3:0]  io_read_resp_tailSlot_offset,</span></a>
+<a name="73"><span class="lineNum">      73 </span><span class="lineCov">         30 :   output [19:0] io_read_resp_tailSlot_lower,</span></a>
+<a name="74"><span class="lineNum">      74 </span><span class="lineCov">         14 :   output [1:0]  io_read_resp_tailSlot_tarStat,</span></a>
+<a name="75"><span class="lineNum">      75 </span><span class="lineCov">         16 :   output        io_read_resp_tailSlot_sharing,</span></a>
+<a name="76"><span class="lineNum">      76 </span><span class="lineCov">         61 :   output        io_read_resp_tailSlot_valid,</span></a>
+<a name="77"><span class="lineNum">      77 </span><span class="lineCov">         12 :   output [3:0]  io_read_resp_pftAddr,</span></a>
+<a name="78"><span class="lineNum">      78 </span><span class="lineCov">         18 :   output        io_read_resp_carry,</span></a>
+<a name="79"><span class="lineNum">      79 </span><span class="lineCov">         10 :   output        io_read_resp_isCall,</span></a>
+<a name="80"><span class="lineNum">      80 </span><span class="lineCov">         10 :   output        io_read_resp_isRet,</span></a>
+<a name="81"><span class="lineNum">      81 </span><span class="lineCov">         15 :   output        io_read_resp_isJalr,</span></a>
+<a name="82"><span class="lineNum">      82 </span><span class="lineCov">         13 :   output        io_read_resp_last_may_be_rvi_call,</span></a>
+<a name="83"><span class="lineNum">      83 </span><span class="lineCov">         19 :   output        io_read_resp_always_taken_0,</span></a>
+<a name="84"><span class="lineNum">      84 </span><span class="lineCov">         19 :   output        io_read_resp_always_taken_1,</span></a>
+<a name="85"><span class="lineNum">      85 </span><span class="lineCov">         30 :   output        io_read_hits_valid,</span></a>
+<a name="86"><span class="lineNum">      86 </span><span class="lineCov">         49 :   output [1:0]  io_read_hits_bits,</span></a>
+<a name="87"><span class="lineNum">      87 </span><span class="lineCov">       1143 :   input         io_u_req_pc_valid,</span></a>
+<a name="88"><span class="lineNum">      88 </span><span class="lineCov">         24 :   input  [40:0] io_u_req_pc_bits,</span></a>
+<a name="89"><span class="lineNum">      89 </span><span class="lineCov">         29 :   output        io_update_hits_valid,</span></a>
+<a name="90"><span class="lineNum">      90 </span><span class="lineCov">         48 :   output [1:0]  io_update_hits_bits,</span></a>
+<a name="91"><span class="lineNum">      91 </span><span class="lineCov">       1167 :   input         io_update_access,</span></a>
+<a name="92"><span class="lineNum">      92 </span><span class="lineCov">         78 :   input  [40:0] io_update_pc,</span></a>
+<a name="93"><span class="lineNum">      93 </span><span class="lineCov">         27 :   input         io_update_write_data_valid,</span></a>
+<a name="94"><span class="lineNum">      94 </span><span class="lineCov">        110 :   input         io_update_write_data_bits_entry_valid,</span></a>
+<a name="95"><span class="lineNum">      95 </span><span class="lineCov">        363 :   input  [3:0]  io_update_write_data_bits_entry_brSlots_0_offset,</span></a>
+<a name="96"><span class="lineNum">      96 </span><span class="lineCov">         49 :   input  [11:0] io_update_write_data_bits_entry_brSlots_0_lower,</span></a>
+<a name="97"><span class="lineNum">      97 </span><span class="lineCov">         28 :   input  [1:0]  io_update_write_data_bits_entry_brSlots_0_tarStat,</span></a>
+<a name="98"><span class="lineNum">      98 </span><span class="lineCov">         30 :   input         io_update_write_data_bits_entry_brSlots_0_sharing,</span></a>
+<a name="99"><span class="lineNum">      99 </span><span class="lineCov">        107 :   input         io_update_write_data_bits_entry_brSlots_0_valid,</span></a>
+<a name="100"><span class="lineNum">     100 </span><span class="lineCov">        576 :   input  [3:0]  io_update_write_data_bits_entry_tailSlot_offset,</span></a>
+<a name="101"><span class="lineNum">     101 </span><span class="lineCov">         54 :   input  [19:0] io_update_write_data_bits_entry_tailSlot_lower,</span></a>
+<a name="102"><span class="lineNum">     102 </span><span class="lineCov">         32 :   input  [1:0]  io_update_write_data_bits_entry_tailSlot_tarStat,</span></a>
+<a name="103"><span class="lineNum">     103 </span><span class="lineCov">         31 :   input         io_update_write_data_bits_entry_tailSlot_sharing,</span></a>
+<a name="104"><span class="lineNum">     104 </span><span class="lineCov">        118 :   input         io_update_write_data_bits_entry_tailSlot_valid,</span></a>
+<a name="105"><span class="lineNum">     105 </span><span class="lineCov">         25 :   input  [3:0]  io_update_write_data_bits_entry_pftAddr,</span></a>
+<a name="106"><span class="lineNum">     106 </span><span class="lineCov">         31 :   input         io_update_write_data_bits_entry_carry,</span></a>
+<a name="107"><span class="lineNum">     107 </span><span class="lineCov">         26 :   input         io_update_write_data_bits_entry_isCall,</span></a>
+<a name="108"><span class="lineNum">     108 </span><span class="lineCov">         24 :   input         io_update_write_data_bits_entry_isRet,</span></a>
+<a name="109"><span class="lineNum">     109 </span><span class="lineCov">         28 :   input         io_update_write_data_bits_entry_isJalr,</span></a>
+<a name="110"><span class="lineNum">     110 </span><span class="lineCov">         28 :   input         io_update_write_data_bits_entry_last_may_be_rvi_call,</span></a>
+<a name="111"><span class="lineNum">     111 </span><span class="lineCov">         31 :   input         io_update_write_data_bits_entry_always_taken_0,</span></a>
+<a name="112"><span class="lineNum">     112 </span><span class="lineCov">        566 :   input         io_update_write_data_bits_entry_always_taken_1,</span></a>
+<a name="113"><span class="lineNum">     113 </span><span class="lineCov">         62 :   input  [19:0] io_update_write_data_bits_tag,</span></a>
+<a name="114"><span class="lineNum">     114 </span><span class="lineCov">         41 :   input  [1:0]  io_update_write_way,</span></a>
+<a name="115"><span class="lineNum">     115 </span>            :   input         io_update_write_alloc</a>
+<a name="116"><span class="lineNum">     116 </span>            : );</a>
+<a name="117"><span class="lineNum">     117 </span>            : </a>
+<a name="118"><span class="lineNum">     118 </span>            :   wire              _ftb_io_r_resp_data_0_entry_valid;</a>
+<a name="119"><span class="lineNum">     119 </span>            :   wire [3:0]        _ftb_io_r_resp_data_0_entry_brSlots_0_offset;</a>
+<a name="120"><span class="lineNum">     120 </span>            :   wire [11:0]       _ftb_io_r_resp_data_0_entry_brSlots_0_lower;</a>
+<a name="121"><span class="lineNum">     121 </span>            :   wire [1:0]        _ftb_io_r_resp_data_0_entry_brSlots_0_tarStat;</a>
+<a name="122"><span class="lineNum">     122 </span>            :   wire              _ftb_io_r_resp_data_0_entry_brSlots_0_sharing;</a>
+<a name="123"><span class="lineNum">     123 </span>            :   wire              _ftb_io_r_resp_data_0_entry_brSlots_0_valid;</a>
+<a name="124"><span class="lineNum">     124 </span>            :   wire [3:0]        _ftb_io_r_resp_data_0_entry_tailSlot_offset;</a>
+<a name="125"><span class="lineNum">     125 </span>            :   wire [19:0]       _ftb_io_r_resp_data_0_entry_tailSlot_lower;</a>
+<a name="126"><span class="lineNum">     126 </span>            :   wire [1:0]        _ftb_io_r_resp_data_0_entry_tailSlot_tarStat;</a>
+<a name="127"><span class="lineNum">     127 </span>            :   wire              _ftb_io_r_resp_data_0_entry_tailSlot_sharing;</a>
+<a name="128"><span class="lineNum">     128 </span>            :   wire              _ftb_io_r_resp_data_0_entry_tailSlot_valid;</a>
+<a name="129"><span class="lineNum">     129 </span>            :   wire [3:0]        _ftb_io_r_resp_data_0_entry_pftAddr;</a>
+<a name="130"><span class="lineNum">     130 </span>            :   wire              _ftb_io_r_resp_data_0_entry_carry;</a>
+<a name="131"><span class="lineNum">     131 </span>            :   wire              _ftb_io_r_resp_data_0_entry_isCall;</a>
+<a name="132"><span class="lineNum">     132 </span>            :   wire              _ftb_io_r_resp_data_0_entry_isRet;</a>
+<a name="133"><span class="lineNum">     133 </span>            :   wire              _ftb_io_r_resp_data_0_entry_isJalr;</a>
+<a name="134"><span class="lineNum">     134 </span>            :   wire              _ftb_io_r_resp_data_0_entry_last_may_be_rvi_call;</a>
+<a name="135"><span class="lineNum">     135 </span>            :   wire              _ftb_io_r_resp_data_0_entry_always_taken_0;</a>
+<a name="136"><span class="lineNum">     136 </span>            :   wire              _ftb_io_r_resp_data_0_entry_always_taken_1;</a>
+<a name="137"><span class="lineNum">     137 </span>            :   wire [19:0]       _ftb_io_r_resp_data_0_tag;</a>
+<a name="138"><span class="lineNum">     138 </span>            :   wire              _ftb_io_r_resp_data_1_entry_valid;</a>
+<a name="139"><span class="lineNum">     139 </span>            :   wire [3:0]        _ftb_io_r_resp_data_1_entry_brSlots_0_offset;</a>
+<a name="140"><span class="lineNum">     140 </span>            :   wire [11:0]       _ftb_io_r_resp_data_1_entry_brSlots_0_lower;</a>
+<a name="141"><span class="lineNum">     141 </span>            :   wire [1:0]        _ftb_io_r_resp_data_1_entry_brSlots_0_tarStat;</a>
+<a name="142"><span class="lineNum">     142 </span>            :   wire              _ftb_io_r_resp_data_1_entry_brSlots_0_sharing;</a>
+<a name="143"><span class="lineNum">     143 </span>            :   wire              _ftb_io_r_resp_data_1_entry_brSlots_0_valid;</a>
+<a name="144"><span class="lineNum">     144 </span>            :   wire [3:0]        _ftb_io_r_resp_data_1_entry_tailSlot_offset;</a>
+<a name="145"><span class="lineNum">     145 </span>            :   wire [19:0]       _ftb_io_r_resp_data_1_entry_tailSlot_lower;</a>
+<a name="146"><span class="lineNum">     146 </span>            :   wire [1:0]        _ftb_io_r_resp_data_1_entry_tailSlot_tarStat;</a>
+<a name="147"><span class="lineNum">     147 </span>            :   wire              _ftb_io_r_resp_data_1_entry_tailSlot_sharing;</a>
+<a name="148"><span class="lineNum">     148 </span>            :   wire              _ftb_io_r_resp_data_1_entry_tailSlot_valid;</a>
+<a name="149"><span class="lineNum">     149 </span>            :   wire [3:0]        _ftb_io_r_resp_data_1_entry_pftAddr;</a>
+<a name="150"><span class="lineNum">     150 </span>            :   wire              _ftb_io_r_resp_data_1_entry_carry;</a>
+<a name="151"><span class="lineNum">     151 </span>            :   wire              _ftb_io_r_resp_data_1_entry_isCall;</a>
+<a name="152"><span class="lineNum">     152 </span>            :   wire              _ftb_io_r_resp_data_1_entry_isRet;</a>
+<a name="153"><span class="lineNum">     153 </span>            :   wire              _ftb_io_r_resp_data_1_entry_isJalr;</a>
+<a name="154"><span class="lineNum">     154 </span>            :   wire              _ftb_io_r_resp_data_1_entry_last_may_be_rvi_call;</a>
+<a name="155"><span class="lineNum">     155 </span>            :   wire              _ftb_io_r_resp_data_1_entry_always_taken_0;</a>
+<a name="156"><span class="lineNum">     156 </span>            :   wire              _ftb_io_r_resp_data_1_entry_always_taken_1;</a>
+<a name="157"><span class="lineNum">     157 </span>            :   wire [19:0]       _ftb_io_r_resp_data_1_tag;</a>
+<a name="158"><span class="lineNum">     158 </span>            :   wire              _ftb_io_r_resp_data_2_entry_valid;</a>
+<a name="159"><span class="lineNum">     159 </span>            :   wire [3:0]        _ftb_io_r_resp_data_2_entry_brSlots_0_offset;</a>
+<a name="160"><span class="lineNum">     160 </span>            :   wire [11:0]       _ftb_io_r_resp_data_2_entry_brSlots_0_lower;</a>
+<a name="161"><span class="lineNum">     161 </span>            :   wire [1:0]        _ftb_io_r_resp_data_2_entry_brSlots_0_tarStat;</a>
+<a name="162"><span class="lineNum">     162 </span>            :   wire              _ftb_io_r_resp_data_2_entry_brSlots_0_sharing;</a>
+<a name="163"><span class="lineNum">     163 </span>            :   wire              _ftb_io_r_resp_data_2_entry_brSlots_0_valid;</a>
+<a name="164"><span class="lineNum">     164 </span>            :   wire [3:0]        _ftb_io_r_resp_data_2_entry_tailSlot_offset;</a>
+<a name="165"><span class="lineNum">     165 </span>            :   wire [19:0]       _ftb_io_r_resp_data_2_entry_tailSlot_lower;</a>
+<a name="166"><span class="lineNum">     166 </span>            :   wire [1:0]        _ftb_io_r_resp_data_2_entry_tailSlot_tarStat;</a>
+<a name="167"><span class="lineNum">     167 </span>            :   wire              _ftb_io_r_resp_data_2_entry_tailSlot_sharing;</a>
+<a name="168"><span class="lineNum">     168 </span>            :   wire              _ftb_io_r_resp_data_2_entry_tailSlot_valid;</a>
+<a name="169"><span class="lineNum">     169 </span>            :   wire [3:0]        _ftb_io_r_resp_data_2_entry_pftAddr;</a>
+<a name="170"><span class="lineNum">     170 </span>            :   wire              _ftb_io_r_resp_data_2_entry_carry;</a>
+<a name="171"><span class="lineNum">     171 </span>            :   wire              _ftb_io_r_resp_data_2_entry_isCall;</a>
+<a name="172"><span class="lineNum">     172 </span>            :   wire              _ftb_io_r_resp_data_2_entry_isRet;</a>
+<a name="173"><span class="lineNum">     173 </span>            :   wire              _ftb_io_r_resp_data_2_entry_isJalr;</a>
+<a name="174"><span class="lineNum">     174 </span>            :   wire              _ftb_io_r_resp_data_2_entry_last_may_be_rvi_call;</a>
+<a name="175"><span class="lineNum">     175 </span>            :   wire              _ftb_io_r_resp_data_2_entry_always_taken_0;</a>
+<a name="176"><span class="lineNum">     176 </span>            :   wire              _ftb_io_r_resp_data_2_entry_always_taken_1;</a>
+<a name="177"><span class="lineNum">     177 </span>            :   wire [19:0]       _ftb_io_r_resp_data_2_tag;</a>
+<a name="178"><span class="lineNum">     178 </span>            :   wire              _ftb_io_r_resp_data_3_entry_valid;</a>
+<a name="179"><span class="lineNum">     179 </span>            :   wire [3:0]        _ftb_io_r_resp_data_3_entry_brSlots_0_offset;</a>
+<a name="180"><span class="lineNum">     180 </span>            :   wire [11:0]       _ftb_io_r_resp_data_3_entry_brSlots_0_lower;</a>
+<a name="181"><span class="lineNum">     181 </span>            :   wire [1:0]        _ftb_io_r_resp_data_3_entry_brSlots_0_tarStat;</a>
+<a name="182"><span class="lineNum">     182 </span>            :   wire              _ftb_io_r_resp_data_3_entry_brSlots_0_sharing;</a>
+<a name="183"><span class="lineNum">     183 </span>            :   wire              _ftb_io_r_resp_data_3_entry_brSlots_0_valid;</a>
+<a name="184"><span class="lineNum">     184 </span>            :   wire [3:0]        _ftb_io_r_resp_data_3_entry_tailSlot_offset;</a>
+<a name="185"><span class="lineNum">     185 </span>            :   wire [19:0]       _ftb_io_r_resp_data_3_entry_tailSlot_lower;</a>
+<a name="186"><span class="lineNum">     186 </span>            :   wire [1:0]        _ftb_io_r_resp_data_3_entry_tailSlot_tarStat;</a>
+<a name="187"><span class="lineNum">     187 </span>            :   wire              _ftb_io_r_resp_data_3_entry_tailSlot_sharing;</a>
+<a name="188"><span class="lineNum">     188 </span>            :   wire              _ftb_io_r_resp_data_3_entry_tailSlot_valid;</a>
+<a name="189"><span class="lineNum">     189 </span>            :   wire [3:0]        _ftb_io_r_resp_data_3_entry_pftAddr;</a>
+<a name="190"><span class="lineNum">     190 </span>            :   wire              _ftb_io_r_resp_data_3_entry_carry;</a>
+<a name="191"><span class="lineNum">     191 </span>            :   wire              _ftb_io_r_resp_data_3_entry_isCall;</a>
+<a name="192"><span class="lineNum">     192 </span>            :   wire              _ftb_io_r_resp_data_3_entry_isRet;</a>
+<a name="193"><span class="lineNum">     193 </span>            :   wire              _ftb_io_r_resp_data_3_entry_isJalr;</a>
+<a name="194"><span class="lineNum">     194 </span>            :   wire              _ftb_io_r_resp_data_3_entry_last_may_be_rvi_call;</a>
+<a name="195"><span class="lineNum">     195 </span>            :   wire              _ftb_io_r_resp_data_3_entry_always_taken_0;</a>
+<a name="196"><span class="lineNum">     196 </span>            :   wire              _ftb_io_r_resp_data_3_entry_always_taken_1;</a>
+<a name="197"><span class="lineNum">     197 </span><span class="lineCov">         90 :   wire [19:0]       _ftb_io_r_resp_data_3_tag;</span></a>
+<a name="198"><span class="lineNum">     198 </span><span class="lineCov">         51 :   reg               pred_rdata_REG;</span></a>
+<a name="199"><span class="lineNum">     199 </span><span class="lineCov">        157 :   reg               pred_rdata_hold_data_0_entry_valid;</span></a>
+<a name="200"><span class="lineNum">     200 </span><span class="lineCov">        433 :   reg  [3:0]        pred_rdata_hold_data_0_entry_brSlots_0_offset;</span></a>
+<a name="201"><span class="lineNum">     201 </span><span class="lineCov">         89 :   reg  [11:0]       pred_rdata_hold_data_0_entry_brSlots_0_lower;</span></a>
+<a name="202"><span class="lineNum">     202 </span><span class="lineCov">         51 :   reg  [1:0]        pred_rdata_hold_data_0_entry_brSlots_0_tarStat;</span></a>
+<a name="203"><span class="lineNum">     203 </span><span class="lineCov">         55 :   reg               pred_rdata_hold_data_0_entry_brSlots_0_sharing;</span></a>
+<a name="204"><span class="lineNum">     204 </span><span class="lineCov">        232 :   reg               pred_rdata_hold_data_0_entry_brSlots_0_valid;</span></a>
+<a name="205"><span class="lineNum">     205 </span><span class="lineCov">        766 :   reg  [3:0]        pred_rdata_hold_data_0_entry_tailSlot_offset;</span></a>
+<a name="206"><span class="lineNum">     206 </span><span class="lineCov">        116 :   reg  [19:0]       pred_rdata_hold_data_0_entry_tailSlot_lower;</span></a>
+<a name="207"><span class="lineNum">     207 </span><span class="lineCov">         51 :   reg  [1:0]        pred_rdata_hold_data_0_entry_tailSlot_tarStat;</span></a>
+<a name="208"><span class="lineNum">     208 </span><span class="lineCov">         63 :   reg               pred_rdata_hold_data_0_entry_tailSlot_sharing;</span></a>
+<a name="209"><span class="lineNum">     209 </span><span class="lineCov">        218 :   reg               pred_rdata_hold_data_0_entry_tailSlot_valid;</span></a>
+<a name="210"><span class="lineNum">     210 </span><span class="lineCov">         57 :   reg  [3:0]        pred_rdata_hold_data_0_entry_pftAddr;</span></a>
+<a name="211"><span class="lineNum">     211 </span><span class="lineCov">         57 :   reg               pred_rdata_hold_data_0_entry_carry;</span></a>
+<a name="212"><span class="lineNum">     212 </span><span class="lineCov">         58 :   reg               pred_rdata_hold_data_0_entry_isCall;</span></a>
+<a name="213"><span class="lineNum">     213 </span><span class="lineCov">         54 :   reg               pred_rdata_hold_data_0_entry_isRet;</span></a>
+<a name="214"><span class="lineNum">     214 </span><span class="lineCov">         54 :   reg               pred_rdata_hold_data_0_entry_isJalr;</span></a>
+<a name="215"><span class="lineNum">     215 </span><span class="lineCov">         55 :   reg               pred_rdata_hold_data_0_entry_last_may_be_rvi_call;</span></a>
+<a name="216"><span class="lineNum">     216 </span><span class="lineCov">         53 :   reg               pred_rdata_hold_data_0_entry_always_taken_0;</span></a>
+<a name="217"><span class="lineNum">     217 </span><span class="lineCov">        764 :   reg               pred_rdata_hold_data_0_entry_always_taken_1;</span></a>
+<a name="218"><span class="lineNum">     218 </span><span class="lineCov">         35 :   reg  [19:0]       pred_rdata_hold_data_0_tag;</span></a>
+<a name="219"><span class="lineNum">     219 </span><span class="lineCov">        139 :   reg               pred_rdata_hold_data_1_entry_valid;</span></a>
+<a name="220"><span class="lineNum">     220 </span><span class="lineCov">        456 :   reg  [3:0]        pred_rdata_hold_data_1_entry_brSlots_0_offset;</span></a>
+<a name="221"><span class="lineNum">     221 </span><span class="lineCov">         65 :   reg  [11:0]       pred_rdata_hold_data_1_entry_brSlots_0_lower;</span></a>
+<a name="222"><span class="lineNum">     222 </span><span class="lineCov">         38 :   reg  [1:0]        pred_rdata_hold_data_1_entry_brSlots_0_tarStat;</span></a>
+<a name="223"><span class="lineNum">     223 </span><span class="lineCov">         35 :   reg               pred_rdata_hold_data_1_entry_brSlots_0_sharing;</span></a>
+<a name="224"><span class="lineNum">     224 </span><span class="lineCov">        146 :   reg               pred_rdata_hold_data_1_entry_brSlots_0_valid;</span></a>
+<a name="225"><span class="lineNum">     225 </span><span class="lineCov">        729 :   reg  [3:0]        pred_rdata_hold_data_1_entry_tailSlot_offset;</span></a>
+<a name="226"><span class="lineNum">     226 </span><span class="lineCov">         70 :   reg  [19:0]       pred_rdata_hold_data_1_entry_tailSlot_lower;</span></a>
+<a name="227"><span class="lineNum">     227 </span><span class="lineCov">         29 :   reg  [1:0]        pred_rdata_hold_data_1_entry_tailSlot_tarStat;</span></a>
+<a name="228"><span class="lineNum">     228 </span><span class="lineCov">         35 :   reg               pred_rdata_hold_data_1_entry_tailSlot_sharing;</span></a>
+<a name="229"><span class="lineNum">     229 </span><span class="lineCov">        142 :   reg               pred_rdata_hold_data_1_entry_tailSlot_valid;</span></a>
+<a name="230"><span class="lineNum">     230 </span><span class="lineCov">         34 :   reg  [3:0]        pred_rdata_hold_data_1_entry_pftAddr;</span></a>
+<a name="231"><span class="lineNum">     231 </span><span class="lineCov">         30 :   reg               pred_rdata_hold_data_1_entry_carry;</span></a>
+<a name="232"><span class="lineNum">     232 </span><span class="lineCov">         40 :   reg               pred_rdata_hold_data_1_entry_isCall;</span></a>
+<a name="233"><span class="lineNum">     233 </span><span class="lineCov">         36 :   reg               pred_rdata_hold_data_1_entry_isRet;</span></a>
+<a name="234"><span class="lineNum">     234 </span><span class="lineCov">         44 :   reg               pred_rdata_hold_data_1_entry_isJalr;</span></a>
+<a name="235"><span class="lineNum">     235 </span><span class="lineCov">         34 :   reg               pred_rdata_hold_data_1_entry_last_may_be_rvi_call;</span></a>
+<a name="236"><span class="lineNum">     236 </span><span class="lineCov">         38 :   reg               pred_rdata_hold_data_1_entry_always_taken_0;</span></a>
+<a name="237"><span class="lineNum">     237 </span><span class="lineCov">        717 :   reg               pred_rdata_hold_data_1_entry_always_taken_1;</span></a>
+<a name="238"><span class="lineNum">     238 </span><span class="lineCov">         24 :   reg  [19:0]       pred_rdata_hold_data_1_tag;</span></a>
+<a name="239"><span class="lineNum">     239 </span><span class="lineCov">        152 :   reg               pred_rdata_hold_data_2_entry_valid;</span></a>
+<a name="240"><span class="lineNum">     240 </span><span class="lineCov">        411 :   reg  [3:0]        pred_rdata_hold_data_2_entry_brSlots_0_offset;</span></a>
+<a name="241"><span class="lineNum">     241 </span><span class="lineCov">         71 :   reg  [11:0]       pred_rdata_hold_data_2_entry_brSlots_0_lower;</span></a>
+<a name="242"><span class="lineNum">     242 </span><span class="lineCov">         38 :   reg  [1:0]        pred_rdata_hold_data_2_entry_brSlots_0_tarStat;</span></a>
+<a name="243"><span class="lineNum">     243 </span><span class="lineCov">         40 :   reg               pred_rdata_hold_data_2_entry_brSlots_0_sharing;</span></a>
+<a name="244"><span class="lineNum">     244 </span><span class="lineCov">        155 :   reg               pred_rdata_hold_data_2_entry_brSlots_0_valid;</span></a>
+<a name="245"><span class="lineNum">     245 </span><span class="lineCov">        703 :   reg  [3:0]        pred_rdata_hold_data_2_entry_tailSlot_offset;</span></a>
+<a name="246"><span class="lineNum">     246 </span><span class="lineCov">         69 :   reg  [19:0]       pred_rdata_hold_data_2_entry_tailSlot_lower;</span></a>
+<a name="247"><span class="lineNum">     247 </span><span class="lineCov">         38 :   reg  [1:0]        pred_rdata_hold_data_2_entry_tailSlot_tarStat;</span></a>
+<a name="248"><span class="lineNum">     248 </span><span class="lineCov">         33 :   reg               pred_rdata_hold_data_2_entry_tailSlot_sharing;</span></a>
+<a name="249"><span class="lineNum">     249 </span><span class="lineCov">        134 :   reg               pred_rdata_hold_data_2_entry_tailSlot_valid;</span></a>
+<a name="250"><span class="lineNum">     250 </span><span class="lineCov">         29 :   reg  [3:0]        pred_rdata_hold_data_2_entry_pftAddr;</span></a>
+<a name="251"><span class="lineNum">     251 </span><span class="lineCov">         36 :   reg               pred_rdata_hold_data_2_entry_carry;</span></a>
+<a name="252"><span class="lineNum">     252 </span><span class="lineCov">         39 :   reg               pred_rdata_hold_data_2_entry_isCall;</span></a>
+<a name="253"><span class="lineNum">     253 </span><span class="lineCov">         34 :   reg               pred_rdata_hold_data_2_entry_isRet;</span></a>
+<a name="254"><span class="lineNum">     254 </span><span class="lineCov">         30 :   reg               pred_rdata_hold_data_2_entry_isJalr;</span></a>
+<a name="255"><span class="lineNum">     255 </span><span class="lineCov">         37 :   reg               pred_rdata_hold_data_2_entry_last_may_be_rvi_call;</span></a>
+<a name="256"><span class="lineNum">     256 </span><span class="lineCov">         32 :   reg               pred_rdata_hold_data_2_entry_always_taken_0;</span></a>
+<a name="257"><span class="lineNum">     257 </span><span class="lineCov">        727 :   reg               pred_rdata_hold_data_2_entry_always_taken_1;</span></a>
+<a name="258"><span class="lineNum">     258 </span><span class="lineCov">         35 :   reg  [19:0]       pred_rdata_hold_data_2_tag;</span></a>
+<a name="259"><span class="lineNum">     259 </span><span class="lineCov">        150 :   reg               pred_rdata_hold_data_3_entry_valid;</span></a>
+<a name="260"><span class="lineNum">     260 </span><span class="lineCov">        415 :   reg  [3:0]        pred_rdata_hold_data_3_entry_brSlots_0_offset;</span></a>
+<a name="261"><span class="lineNum">     261 </span><span class="lineCov">         68 :   reg  [11:0]       pred_rdata_hold_data_3_entry_brSlots_0_lower;</span></a>
+<a name="262"><span class="lineNum">     262 </span><span class="lineCov">         36 :   reg  [1:0]        pred_rdata_hold_data_3_entry_brSlots_0_tarStat;</span></a>
+<a name="263"><span class="lineNum">     263 </span><span class="lineCov">         27 :   reg               pred_rdata_hold_data_3_entry_brSlots_0_sharing;</span></a>
+<a name="264"><span class="lineNum">     264 </span><span class="lineCov">        151 :   reg               pred_rdata_hold_data_3_entry_brSlots_0_valid;</span></a>
+<a name="265"><span class="lineNum">     265 </span><span class="lineCov">        745 :   reg  [3:0]        pred_rdata_hold_data_3_entry_tailSlot_offset;</span></a>
+<a name="266"><span class="lineNum">     266 </span><span class="lineCov">         74 :   reg  [19:0]       pred_rdata_hold_data_3_entry_tailSlot_lower;</span></a>
+<a name="267"><span class="lineNum">     267 </span><span class="lineCov">         32 :   reg  [1:0]        pred_rdata_hold_data_3_entry_tailSlot_tarStat;</span></a>
+<a name="268"><span class="lineNum">     268 </span><span class="lineCov">         36 :   reg               pred_rdata_hold_data_3_entry_tailSlot_sharing;</span></a>
+<a name="269"><span class="lineNum">     269 </span><span class="lineCov">        136 :   reg               pred_rdata_hold_data_3_entry_tailSlot_valid;</span></a>
+<a name="270"><span class="lineNum">     270 </span><span class="lineCov">         28 :   reg  [3:0]        pred_rdata_hold_data_3_entry_pftAddr;</span></a>
+<a name="271"><span class="lineNum">     271 </span><span class="lineCov">         36 :   reg               pred_rdata_hold_data_3_entry_carry;</span></a>
+<a name="272"><span class="lineNum">     272 </span><span class="lineCov">         40 :   reg               pred_rdata_hold_data_3_entry_isCall;</span></a>
+<a name="273"><span class="lineNum">     273 </span><span class="lineCov">         37 :   reg               pred_rdata_hold_data_3_entry_isRet;</span></a>
+<a name="274"><span class="lineNum">     274 </span><span class="lineCov">         28 :   reg               pred_rdata_hold_data_3_entry_isJalr;</span></a>
+<a name="275"><span class="lineNum">     275 </span><span class="lineCov">         43 :   reg               pred_rdata_hold_data_3_entry_last_may_be_rvi_call;</span></a>
+<a name="276"><span class="lineNum">     276 </span><span class="lineCov">         37 :   reg               pred_rdata_hold_data_3_entry_always_taken_0;</span></a>
+<a name="277"><span class="lineNum">     277 </span><span class="lineCov">        722 :   reg               pred_rdata_hold_data_3_entry_always_taken_1;</span></a>
+<a name="278"><span class="lineNum">     278 </span><span class="lineCov">         42 :   reg  [19:0]       pred_rdata_hold_data_3_tag;</span></a>
+<a name="279"><span class="lineNum">     279 </span>            :   wire              pred_rdata_0_entry_valid =</a>
+<a name="280"><span class="lineNum">     280 </span>            :     pred_rdata_REG</a>
+<a name="281"><span class="lineNum">     281 </span>            :       ? _ftb_io_r_resp_data_0_entry_valid</a>
+<a name="282"><span class="lineNum">     282 </span><span class="lineCov">         30 :       : pred_rdata_hold_data_0_entry_valid;</span></a>
+<a name="283"><span class="lineNum">     283 </span>            :   wire              pred_rdata_1_entry_valid =</a>
+<a name="284"><span class="lineNum">     284 </span>            :     pred_rdata_REG</a>
+<a name="285"><span class="lineNum">     285 </span>            :       ? _ftb_io_r_resp_data_1_entry_valid</a>
+<a name="286"><span class="lineNum">     286 </span><span class="lineCov">         23 :       : pred_rdata_hold_data_1_entry_valid;</span></a>
+<a name="287"><span class="lineNum">     287 </span>            :   wire              pred_rdata_2_entry_valid =</a>
+<a name="288"><span class="lineNum">     288 </span>            :     pred_rdata_REG</a>
+<a name="289"><span class="lineNum">     289 </span>            :       ? _ftb_io_r_resp_data_2_entry_valid</a>
+<a name="290"><span class="lineNum">     290 </span><span class="lineCov">         30 :       : pred_rdata_hold_data_2_entry_valid;</span></a>
+<a name="291"><span class="lineNum">     291 </span>            :   wire              pred_rdata_3_entry_valid =</a>
+<a name="292"><span class="lineNum">     292 </span>            :     pred_rdata_REG</a>
+<a name="293"><span class="lineNum">     293 </span>            :       ? _ftb_io_r_resp_data_3_entry_valid</a>
+<a name="294"><span class="lineNum">     294 </span><span class="lineCov">        763 :       : pred_rdata_hold_data_3_entry_valid;</span></a>
+<a name="295"><span class="lineNum">     295 </span><span class="lineCov">       8237 :   reg  [19:0]       req_tag;</span></a>
+<a name="296"><span class="lineNum">     296 </span><span class="lineCov">        431 :   reg  [8:0]        req_idx;</span></a>
+<a name="297"><span class="lineNum">     297 </span><span class="lineCov">         15 :   reg  [19:0]       u_req_tag;</span></a>
+<a name="298"><span class="lineNum">     298 </span>            :   wire              total_hits_0 =</a>
+<a name="299"><span class="lineNum">     299 </span>            :     (pred_rdata_REG ? _ftb_io_r_resp_data_0_tag : pred_rdata_hold_data_0_tag) == req_tag</a>
+<a name="300"><span class="lineNum">     300 </span><span class="lineCov">         11 :     &amp; pred_rdata_0_entry_valid &amp; io_s1_fire;</span></a>
+<a name="301"><span class="lineNum">     301 </span>            :   wire              total_hits_1 =</a>
+<a name="302"><span class="lineNum">     302 </span>            :     (pred_rdata_REG ? _ftb_io_r_resp_data_1_tag : pred_rdata_hold_data_1_tag) == req_tag</a>
+<a name="303"><span class="lineNum">     303 </span><span class="lineCov">         17 :     &amp; pred_rdata_1_entry_valid &amp; io_s1_fire;</span></a>
+<a name="304"><span class="lineNum">     304 </span>            :   wire              total_hits_2 =</a>
+<a name="305"><span class="lineNum">     305 </span>            :     (pred_rdata_REG ? _ftb_io_r_resp_data_2_tag : pred_rdata_hold_data_2_tag) == req_tag</a>
+<a name="306"><span class="lineNum">     306 </span><span class="lineCov">         10 :     &amp; pred_rdata_2_entry_valid &amp; io_s1_fire;</span></a>
+<a name="307"><span class="lineNum">     307 </span>            :   wire              total_hits_3 =</a>
+<a name="308"><span class="lineNum">     308 </span>            :     (pred_rdata_REG ? _ftb_io_r_resp_data_3_tag : pred_rdata_hold_data_3_tag) == req_tag</a>
+<a name="309"><span class="lineNum">     309 </span><span class="lineCov">         19 :     &amp; pred_rdata_3_entry_valid &amp; io_s1_fire;</span></a>
+<a name="310"><span class="lineNum">     310 </span><span class="lineCov">         30 :   wire              hit = total_hits_0 | total_hits_1 | total_hits_2 | total_hits_3;</span></a>
+<a name="311"><span class="lineNum">     311 </span>            :   wire [1:0]        hit_way =</a>
+<a name="312"><span class="lineNum">     312 </span><span class="lineCov">         61 :     {|{total_hits_3, total_hits_2}, total_hits_3 | total_hits_1};</span></a>
+<a name="313"><span class="lineNum">     313 </span><span class="lineCov">         66 :   reg               u_total_hits_REG;</span></a>
+<a name="314"><span class="lineNum">     314 </span><span class="lineCov">         15 :   reg               u_total_hits_REG_1;</span></a>
+<a name="315"><span class="lineNum">     315 </span>            :   wire              u_total_hits_1 =</a>
+<a name="316"><span class="lineNum">     316 </span>            :     _ftb_io_r_resp_data_1_tag == u_req_tag &amp; _ftb_io_r_resp_data_1_entry_valid</a>
+<a name="317"><span class="lineNum">     317 </span><span class="lineCov">         61 :     &amp; u_total_hits_REG_1;</span></a>
+<a name="318"><span class="lineNum">     318 </span><span class="lineCov">         18 :   reg               u_total_hits_REG_2;</span></a>
+<a name="319"><span class="lineNum">     319 </span>            :   wire              u_total_hits_2 =</a>
+<a name="320"><span class="lineNum">     320 </span>            :     _ftb_io_r_resp_data_2_tag == u_req_tag &amp; _ftb_io_r_resp_data_2_entry_valid</a>
+<a name="321"><span class="lineNum">     321 </span><span class="lineCov">         63 :     &amp; u_total_hits_REG_2;</span></a>
+<a name="322"><span class="lineNum">     322 </span><span class="lineCov">         17 :   reg               u_total_hits_REG_3;</span></a>
+<a name="323"><span class="lineNum">     323 </span>            :   wire              u_total_hits_3 =</a>
+<a name="324"><span class="lineNum">     324 </span>            :     _ftb_io_r_resp_data_3_tag == u_req_tag &amp; _ftb_io_r_resp_data_3_entry_valid</a>
+<a name="325"><span class="lineNum">     325 </span><span class="lineCov">         75 :     &amp; u_total_hits_REG_3;</span></a>
+<a name="326"><span class="lineNum">     326 </span><span class="lineCov">         67 :   reg  [2:0]        state_vec_0;</span></a>
+<a name="327"><span class="lineNum">     327 </span><span class="lineCov">         68 :   reg  [2:0]        state_vec_1;</span></a>
+<a name="328"><span class="lineNum">     328 </span><span class="lineCov">         70 :   reg  [2:0]        state_vec_2;</span></a>
+<a name="329"><span class="lineNum">     329 </span><span class="lineCov">         76 :   reg  [2:0]        state_vec_3;</span></a>
+<a name="330"><span class="lineNum">     330 </span><span class="lineCov">         72 :   reg  [2:0]        state_vec_4;</span></a>
+<a name="331"><span class="lineNum">     331 </span><span class="lineCov">         82 :   reg  [2:0]        state_vec_5;</span></a>
+<a name="332"><span class="lineNum">     332 </span><span class="lineCov">         67 :   reg  [2:0]        state_vec_6;</span></a>
+<a name="333"><span class="lineNum">     333 </span><span class="lineCov">         75 :   reg  [2:0]        state_vec_7;</span></a>
+<a name="334"><span class="lineNum">     334 </span><span class="lineCov">         75 :   reg  [2:0]        state_vec_8;</span></a>
+<a name="335"><span class="lineNum">     335 </span><span class="lineCov">         70 :   reg  [2:0]        state_vec_9;</span></a>
+<a name="336"><span class="lineNum">     336 </span><span class="lineCov">         75 :   reg  [2:0]        state_vec_10;</span></a>
+<a name="337"><span class="lineNum">     337 </span><span class="lineCov">         78 :   reg  [2:0]        state_vec_11;</span></a>
+<a name="338"><span class="lineNum">     338 </span><span class="lineCov">         62 :   reg  [2:0]        state_vec_12;</span></a>
+<a name="339"><span class="lineNum">     339 </span><span class="lineCov">         64 :   reg  [2:0]        state_vec_13;</span></a>
+<a name="340"><span class="lineNum">     340 </span><span class="lineCov">         57 :   reg  [2:0]        state_vec_14;</span></a>
+<a name="341"><span class="lineNum">     341 </span><span class="lineCov">         77 :   reg  [2:0]        state_vec_15;</span></a>
+<a name="342"><span class="lineNum">     342 </span><span class="lineCov">         69 :   reg  [2:0]        state_vec_16;</span></a>
+<a name="343"><span class="lineNum">     343 </span><span class="lineCov">         58 :   reg  [2:0]        state_vec_17;</span></a>
+<a name="344"><span class="lineNum">     344 </span><span class="lineCov">         63 :   reg  [2:0]        state_vec_18;</span></a>
+<a name="345"><span class="lineNum">     345 </span><span class="lineCov">         76 :   reg  [2:0]        state_vec_19;</span></a>
+<a name="346"><span class="lineNum">     346 </span><span class="lineCov">         78 :   reg  [2:0]        state_vec_20;</span></a>
+<a name="347"><span class="lineNum">     347 </span><span class="lineCov">         69 :   reg  [2:0]        state_vec_21;</span></a>
+<a name="348"><span class="lineNum">     348 </span><span class="lineCov">         66 :   reg  [2:0]        state_vec_22;</span></a>
+<a name="349"><span class="lineNum">     349 </span><span class="lineCov">         69 :   reg  [2:0]        state_vec_23;</span></a>
+<a name="350"><span class="lineNum">     350 </span><span class="lineCov">         67 :   reg  [2:0]        state_vec_24;</span></a>
+<a name="351"><span class="lineNum">     351 </span><span class="lineCov">         79 :   reg  [2:0]        state_vec_25;</span></a>
+<a name="352"><span class="lineNum">     352 </span><span class="lineCov">         61 :   reg  [2:0]        state_vec_26;</span></a>
+<a name="353"><span class="lineNum">     353 </span><span class="lineCov">         74 :   reg  [2:0]        state_vec_27;</span></a>
+<a name="354"><span class="lineNum">     354 </span><span class="lineCov">         66 :   reg  [2:0]        state_vec_28;</span></a>
+<a name="355"><span class="lineNum">     355 </span><span class="lineCov">         68 :   reg  [2:0]        state_vec_29;</span></a>
+<a name="356"><span class="lineNum">     356 </span><span class="lineCov">         71 :   reg  [2:0]        state_vec_30;</span></a>
+<a name="357"><span class="lineNum">     357 </span><span class="lineCov">         74 :   reg  [2:0]        state_vec_31;</span></a>
+<a name="358"><span class="lineNum">     358 </span><span class="lineCov">         73 :   reg  [2:0]        state_vec_32;</span></a>
+<a name="359"><span class="lineNum">     359 </span><span class="lineCov">         73 :   reg  [2:0]        state_vec_33;</span></a>
+<a name="360"><span class="lineNum">     360 </span><span class="lineCov">         70 :   reg  [2:0]        state_vec_34;</span></a>
+<a name="361"><span class="lineNum">     361 </span><span class="lineCov">         71 :   reg  [2:0]        state_vec_35;</span></a>
+<a name="362"><span class="lineNum">     362 </span><span class="lineCov">         70 :   reg  [2:0]        state_vec_36;</span></a>
+<a name="363"><span class="lineNum">     363 </span><span class="lineCov">         69 :   reg  [2:0]        state_vec_37;</span></a>
+<a name="364"><span class="lineNum">     364 </span><span class="lineCov">         66 :   reg  [2:0]        state_vec_38;</span></a>
+<a name="365"><span class="lineNum">     365 </span><span class="lineCov">         68 :   reg  [2:0]        state_vec_39;</span></a>
+<a name="366"><span class="lineNum">     366 </span><span class="lineCov">         66 :   reg  [2:0]        state_vec_40;</span></a>
+<a name="367"><span class="lineNum">     367 </span><span class="lineCov">         68 :   reg  [2:0]        state_vec_41;</span></a>
+<a name="368"><span class="lineNum">     368 </span><span class="lineCov">         70 :   reg  [2:0]        state_vec_42;</span></a>
+<a name="369"><span class="lineNum">     369 </span><span class="lineCov">         68 :   reg  [2:0]        state_vec_43;</span></a>
+<a name="370"><span class="lineNum">     370 </span><span class="lineCov">         78 :   reg  [2:0]        state_vec_44;</span></a>
+<a name="371"><span class="lineNum">     371 </span><span class="lineCov">         69 :   reg  [2:0]        state_vec_45;</span></a>
+<a name="372"><span class="lineNum">     372 </span><span class="lineCov">         75 :   reg  [2:0]        state_vec_46;</span></a>
+<a name="373"><span class="lineNum">     373 </span><span class="lineCov">         63 :   reg  [2:0]        state_vec_47;</span></a>
+<a name="374"><span class="lineNum">     374 </span><span class="lineCov">         71 :   reg  [2:0]        state_vec_48;</span></a>
+<a name="375"><span class="lineNum">     375 </span><span class="lineCov">         67 :   reg  [2:0]        state_vec_49;</span></a>
+<a name="376"><span class="lineNum">     376 </span><span class="lineCov">         65 :   reg  [2:0]        state_vec_50;</span></a>
+<a name="377"><span class="lineNum">     377 </span><span class="lineCov">         75 :   reg  [2:0]        state_vec_51;</span></a>
+<a name="378"><span class="lineNum">     378 </span><span class="lineCov">         75 :   reg  [2:0]        state_vec_52;</span></a>
+<a name="379"><span class="lineNum">     379 </span><span class="lineCov">         70 :   reg  [2:0]        state_vec_53;</span></a>
+<a name="380"><span class="lineNum">     380 </span><span class="lineCov">         60 :   reg  [2:0]        state_vec_54;</span></a>
+<a name="381"><span class="lineNum">     381 </span><span class="lineCov">         63 :   reg  [2:0]        state_vec_55;</span></a>
+<a name="382"><span class="lineNum">     382 </span><span class="lineCov">         69 :   reg  [2:0]        state_vec_56;</span></a>
+<a name="383"><span class="lineNum">     383 </span><span class="lineCov">         69 :   reg  [2:0]        state_vec_57;</span></a>
+<a name="384"><span class="lineNum">     384 </span><span class="lineCov">         81 :   reg  [2:0]        state_vec_58;</span></a>
+<a name="385"><span class="lineNum">     385 </span><span class="lineCov">         63 :   reg  [2:0]        state_vec_59;</span></a>
+<a name="386"><span class="lineNum">     386 </span><span class="lineCov">         60 :   reg  [2:0]        state_vec_60;</span></a>
+<a name="387"><span class="lineNum">     387 </span><span class="lineCov">         77 :   reg  [2:0]        state_vec_61;</span></a>
+<a name="388"><span class="lineNum">     388 </span><span class="lineCov">         71 :   reg  [2:0]        state_vec_62;</span></a>
+<a name="389"><span class="lineNum">     389 </span><span class="lineCov">         86 :   reg  [2:0]        state_vec_63;</span></a>
+<a name="390"><span class="lineNum">     390 </span><span class="lineCov">         67 :   reg  [2:0]        state_vec_64;</span></a>
+<a name="391"><span class="lineNum">     391 </span><span class="lineCov">         72 :   reg  [2:0]        state_vec_65;</span></a>
+<a name="392"><span class="lineNum">     392 </span><span class="lineCov">         68 :   reg  [2:0]        state_vec_66;</span></a>
+<a name="393"><span class="lineNum">     393 </span><span class="lineCov">         68 :   reg  [2:0]        state_vec_67;</span></a>
+<a name="394"><span class="lineNum">     394 </span><span class="lineCov">         71 :   reg  [2:0]        state_vec_68;</span></a>
+<a name="395"><span class="lineNum">     395 </span><span class="lineCov">         60 :   reg  [2:0]        state_vec_69;</span></a>
+<a name="396"><span class="lineNum">     396 </span><span class="lineCov">         72 :   reg  [2:0]        state_vec_70;</span></a>
+<a name="397"><span class="lineNum">     397 </span><span class="lineCov">         70 :   reg  [2:0]        state_vec_71;</span></a>
+<a name="398"><span class="lineNum">     398 </span><span class="lineCov">         71 :   reg  [2:0]        state_vec_72;</span></a>
+<a name="399"><span class="lineNum">     399 </span><span class="lineCov">         72 :   reg  [2:0]        state_vec_73;</span></a>
+<a name="400"><span class="lineNum">     400 </span><span class="lineCov">         78 :   reg  [2:0]        state_vec_74;</span></a>
+<a name="401"><span class="lineNum">     401 </span><span class="lineCov">         66 :   reg  [2:0]        state_vec_75;</span></a>
+<a name="402"><span class="lineNum">     402 </span><span class="lineCov">         66 :   reg  [2:0]        state_vec_76;</span></a>
+<a name="403"><span class="lineNum">     403 </span><span class="lineCov">         64 :   reg  [2:0]        state_vec_77;</span></a>
+<a name="404"><span class="lineNum">     404 </span><span class="lineCov">         73 :   reg  [2:0]        state_vec_78;</span></a>
+<a name="405"><span class="lineNum">     405 </span><span class="lineCov">         83 :   reg  [2:0]        state_vec_79;</span></a>
+<a name="406"><span class="lineNum">     406 </span><span class="lineCov">         76 :   reg  [2:0]        state_vec_80;</span></a>
+<a name="407"><span class="lineNum">     407 </span><span class="lineCov">         75 :   reg  [2:0]        state_vec_81;</span></a>
+<a name="408"><span class="lineNum">     408 </span><span class="lineCov">         71 :   reg  [2:0]        state_vec_82;</span></a>
+<a name="409"><span class="lineNum">     409 </span><span class="lineCov">         66 :   reg  [2:0]        state_vec_83;</span></a>
+<a name="410"><span class="lineNum">     410 </span><span class="lineCov">         74 :   reg  [2:0]        state_vec_84;</span></a>
+<a name="411"><span class="lineNum">     411 </span><span class="lineCov">         80 :   reg  [2:0]        state_vec_85;</span></a>
+<a name="412"><span class="lineNum">     412 </span><span class="lineCov">         74 :   reg  [2:0]        state_vec_86;</span></a>
+<a name="413"><span class="lineNum">     413 </span><span class="lineCov">         77 :   reg  [2:0]        state_vec_87;</span></a>
+<a name="414"><span class="lineNum">     414 </span><span class="lineCov">         66 :   reg  [2:0]        state_vec_88;</span></a>
+<a name="415"><span class="lineNum">     415 </span><span class="lineCov">         59 :   reg  [2:0]        state_vec_89;</span></a>
+<a name="416"><span class="lineNum">     416 </span><span class="lineCov">         64 :   reg  [2:0]        state_vec_90;</span></a>
+<a name="417"><span class="lineNum">     417 </span><span class="lineCov">         58 :   reg  [2:0]        state_vec_91;</span></a>
+<a name="418"><span class="lineNum">     418 </span><span class="lineCov">         65 :   reg  [2:0]        state_vec_92;</span></a>
+<a name="419"><span class="lineNum">     419 </span><span class="lineCov">         71 :   reg  [2:0]        state_vec_93;</span></a>
+<a name="420"><span class="lineNum">     420 </span><span class="lineCov">         73 :   reg  [2:0]        state_vec_94;</span></a>
+<a name="421"><span class="lineNum">     421 </span><span class="lineCov">         70 :   reg  [2:0]        state_vec_95;</span></a>
+<a name="422"><span class="lineNum">     422 </span><span class="lineCov">         73 :   reg  [2:0]        state_vec_96;</span></a>
+<a name="423"><span class="lineNum">     423 </span><span class="lineCov">         70 :   reg  [2:0]        state_vec_97;</span></a>
+<a name="424"><span class="lineNum">     424 </span><span class="lineCov">         70 :   reg  [2:0]        state_vec_98;</span></a>
+<a name="425"><span class="lineNum">     425 </span><span class="lineCov">         68 :   reg  [2:0]        state_vec_99;</span></a>
+<a name="426"><span class="lineNum">     426 </span><span class="lineCov">         66 :   reg  [2:0]        state_vec_100;</span></a>
+<a name="427"><span class="lineNum">     427 </span><span class="lineCov">         70 :   reg  [2:0]        state_vec_101;</span></a>
+<a name="428"><span class="lineNum">     428 </span><span class="lineCov">         64 :   reg  [2:0]        state_vec_102;</span></a>
+<a name="429"><span class="lineNum">     429 </span><span class="lineCov">         74 :   reg  [2:0]        state_vec_103;</span></a>
+<a name="430"><span class="lineNum">     430 </span><span class="lineCov">         79 :   reg  [2:0]        state_vec_104;</span></a>
+<a name="431"><span class="lineNum">     431 </span><span class="lineCov">         74 :   reg  [2:0]        state_vec_105;</span></a>
+<a name="432"><span class="lineNum">     432 </span><span class="lineCov">         77 :   reg  [2:0]        state_vec_106;</span></a>
+<a name="433"><span class="lineNum">     433 </span><span class="lineCov">         59 :   reg  [2:0]        state_vec_107;</span></a>
+<a name="434"><span class="lineNum">     434 </span><span class="lineCov">         62 :   reg  [2:0]        state_vec_108;</span></a>
+<a name="435"><span class="lineNum">     435 </span><span class="lineCov">         67 :   reg  [2:0]        state_vec_109;</span></a>
+<a name="436"><span class="lineNum">     436 </span><span class="lineCov">         57 :   reg  [2:0]        state_vec_110;</span></a>
+<a name="437"><span class="lineNum">     437 </span><span class="lineCov">         71 :   reg  [2:0]        state_vec_111;</span></a>
+<a name="438"><span class="lineNum">     438 </span><span class="lineCov">         56 :   reg  [2:0]        state_vec_112;</span></a>
+<a name="439"><span class="lineNum">     439 </span><span class="lineCov">         74 :   reg  [2:0]        state_vec_113;</span></a>
+<a name="440"><span class="lineNum">     440 </span><span class="lineCov">         66 :   reg  [2:0]        state_vec_114;</span></a>
+<a name="441"><span class="lineNum">     441 </span><span class="lineCov">         74 :   reg  [2:0]        state_vec_115;</span></a>
+<a name="442"><span class="lineNum">     442 </span><span class="lineCov">         81 :   reg  [2:0]        state_vec_116;</span></a>
+<a name="443"><span class="lineNum">     443 </span><span class="lineCov">         72 :   reg  [2:0]        state_vec_117;</span></a>
+<a name="444"><span class="lineNum">     444 </span><span class="lineCov">         71 :   reg  [2:0]        state_vec_118;</span></a>
+<a name="445"><span class="lineNum">     445 </span><span class="lineCov">         70 :   reg  [2:0]        state_vec_119;</span></a>
+<a name="446"><span class="lineNum">     446 </span><span class="lineCov">         59 :   reg  [2:0]        state_vec_120;</span></a>
+<a name="447"><span class="lineNum">     447 </span><span class="lineCov">         66 :   reg  [2:0]        state_vec_121;</span></a>
+<a name="448"><span class="lineNum">     448 </span><span class="lineCov">         71 :   reg  [2:0]        state_vec_122;</span></a>
+<a name="449"><span class="lineNum">     449 </span><span class="lineCov">         65 :   reg  [2:0]        state_vec_123;</span></a>
+<a name="450"><span class="lineNum">     450 </span><span class="lineCov">         68 :   reg  [2:0]        state_vec_124;</span></a>
+<a name="451"><span class="lineNum">     451 </span><span class="lineCov">         74 :   reg  [2:0]        state_vec_125;</span></a>
+<a name="452"><span class="lineNum">     452 </span><span class="lineCov">         67 :   reg  [2:0]        state_vec_126;</span></a>
+<a name="453"><span class="lineNum">     453 </span><span class="lineCov">         73 :   reg  [2:0]        state_vec_127;</span></a>
+<a name="454"><span class="lineNum">     454 </span><span class="lineCov">         74 :   reg  [2:0]        state_vec_128;</span></a>
+<a name="455"><span class="lineNum">     455 </span><span class="lineCov">         61 :   reg  [2:0]        state_vec_129;</span></a>
+<a name="456"><span class="lineNum">     456 </span><span class="lineCov">         63 :   reg  [2:0]        state_vec_130;</span></a>
+<a name="457"><span class="lineNum">     457 </span><span class="lineCov">         73 :   reg  [2:0]        state_vec_131;</span></a>
+<a name="458"><span class="lineNum">     458 </span><span class="lineCov">         62 :   reg  [2:0]        state_vec_132;</span></a>
+<a name="459"><span class="lineNum">     459 </span><span class="lineCov">         70 :   reg  [2:0]        state_vec_133;</span></a>
+<a name="460"><span class="lineNum">     460 </span><span class="lineCov">         81 :   reg  [2:0]        state_vec_134;</span></a>
+<a name="461"><span class="lineNum">     461 </span><span class="lineCov">         64 :   reg  [2:0]        state_vec_135;</span></a>
+<a name="462"><span class="lineNum">     462 </span><span class="lineCov">         71 :   reg  [2:0]        state_vec_136;</span></a>
+<a name="463"><span class="lineNum">     463 </span><span class="lineCov">         62 :   reg  [2:0]        state_vec_137;</span></a>
+<a name="464"><span class="lineNum">     464 </span><span class="lineCov">         64 :   reg  [2:0]        state_vec_138;</span></a>
+<a name="465"><span class="lineNum">     465 </span><span class="lineCov">         73 :   reg  [2:0]        state_vec_139;</span></a>
+<a name="466"><span class="lineNum">     466 </span><span class="lineCov">         68 :   reg  [2:0]        state_vec_140;</span></a>
+<a name="467"><span class="lineNum">     467 </span><span class="lineCov">         76 :   reg  [2:0]        state_vec_141;</span></a>
+<a name="468"><span class="lineNum">     468 </span><span class="lineCov">         69 :   reg  [2:0]        state_vec_142;</span></a>
+<a name="469"><span class="lineNum">     469 </span><span class="lineCov">         67 :   reg  [2:0]        state_vec_143;</span></a>
+<a name="470"><span class="lineNum">     470 </span><span class="lineCov">         69 :   reg  [2:0]        state_vec_144;</span></a>
+<a name="471"><span class="lineNum">     471 </span><span class="lineCov">         69 :   reg  [2:0]        state_vec_145;</span></a>
+<a name="472"><span class="lineNum">     472 </span><span class="lineCov">         70 :   reg  [2:0]        state_vec_146;</span></a>
+<a name="473"><span class="lineNum">     473 </span><span class="lineCov">         65 :   reg  [2:0]        state_vec_147;</span></a>
+<a name="474"><span class="lineNum">     474 </span><span class="lineCov">         69 :   reg  [2:0]        state_vec_148;</span></a>
+<a name="475"><span class="lineNum">     475 </span><span class="lineCov">         73 :   reg  [2:0]        state_vec_149;</span></a>
+<a name="476"><span class="lineNum">     476 </span><span class="lineCov">         60 :   reg  [2:0]        state_vec_150;</span></a>
+<a name="477"><span class="lineNum">     477 </span><span class="lineCov">         62 :   reg  [2:0]        state_vec_151;</span></a>
+<a name="478"><span class="lineNum">     478 </span><span class="lineCov">         56 :   reg  [2:0]        state_vec_152;</span></a>
+<a name="479"><span class="lineNum">     479 </span><span class="lineCov">         78 :   reg  [2:0]        state_vec_153;</span></a>
+<a name="480"><span class="lineNum">     480 </span><span class="lineCov">         78 :   reg  [2:0]        state_vec_154;</span></a>
+<a name="481"><span class="lineNum">     481 </span><span class="lineCov">         63 :   reg  [2:0]        state_vec_155;</span></a>
+<a name="482"><span class="lineNum">     482 </span><span class="lineCov">         65 :   reg  [2:0]        state_vec_156;</span></a>
+<a name="483"><span class="lineNum">     483 </span><span class="lineCov">         72 :   reg  [2:0]        state_vec_157;</span></a>
+<a name="484"><span class="lineNum">     484 </span><span class="lineCov">         68 :   reg  [2:0]        state_vec_158;</span></a>
+<a name="485"><span class="lineNum">     485 </span><span class="lineCov">         62 :   reg  [2:0]        state_vec_159;</span></a>
+<a name="486"><span class="lineNum">     486 </span><span class="lineCov">         69 :   reg  [2:0]        state_vec_160;</span></a>
+<a name="487"><span class="lineNum">     487 </span><span class="lineCov">         69 :   reg  [2:0]        state_vec_161;</span></a>
+<a name="488"><span class="lineNum">     488 </span><span class="lineCov">         68 :   reg  [2:0]        state_vec_162;</span></a>
+<a name="489"><span class="lineNum">     489 </span><span class="lineCov">         64 :   reg  [2:0]        state_vec_163;</span></a>
+<a name="490"><span class="lineNum">     490 </span><span class="lineCov">         72 :   reg  [2:0]        state_vec_164;</span></a>
+<a name="491"><span class="lineNum">     491 </span><span class="lineCov">         75 :   reg  [2:0]        state_vec_165;</span></a>
+<a name="492"><span class="lineNum">     492 </span><span class="lineCov">         76 :   reg  [2:0]        state_vec_166;</span></a>
+<a name="493"><span class="lineNum">     493 </span><span class="lineCov">         65 :   reg  [2:0]        state_vec_167;</span></a>
+<a name="494"><span class="lineNum">     494 </span><span class="lineCov">         60 :   reg  [2:0]        state_vec_168;</span></a>
+<a name="495"><span class="lineNum">     495 </span><span class="lineCov">         68 :   reg  [2:0]        state_vec_169;</span></a>
+<a name="496"><span class="lineNum">     496 </span><span class="lineCov">         70 :   reg  [2:0]        state_vec_170;</span></a>
+<a name="497"><span class="lineNum">     497 </span><span class="lineCov">         73 :   reg  [2:0]        state_vec_171;</span></a>
+<a name="498"><span class="lineNum">     498 </span><span class="lineCov">         70 :   reg  [2:0]        state_vec_172;</span></a>
+<a name="499"><span class="lineNum">     499 </span><span class="lineCov">         73 :   reg  [2:0]        state_vec_173;</span></a>
+<a name="500"><span class="lineNum">     500 </span><span class="lineCov">         70 :   reg  [2:0]        state_vec_174;</span></a>
+<a name="501"><span class="lineNum">     501 </span><span class="lineCov">         65 :   reg  [2:0]        state_vec_175;</span></a>
+<a name="502"><span class="lineNum">     502 </span><span class="lineCov">         75 :   reg  [2:0]        state_vec_176;</span></a>
+<a name="503"><span class="lineNum">     503 </span><span class="lineCov">         67 :   reg  [2:0]        state_vec_177;</span></a>
+<a name="504"><span class="lineNum">     504 </span><span class="lineCov">         72 :   reg  [2:0]        state_vec_178;</span></a>
+<a name="505"><span class="lineNum">     505 </span><span class="lineCov">         67 :   reg  [2:0]        state_vec_179;</span></a>
+<a name="506"><span class="lineNum">     506 </span><span class="lineCov">         66 :   reg  [2:0]        state_vec_180;</span></a>
+<a name="507"><span class="lineNum">     507 </span><span class="lineCov">         64 :   reg  [2:0]        state_vec_181;</span></a>
+<a name="508"><span class="lineNum">     508 </span><span class="lineCov">         73 :   reg  [2:0]        state_vec_182;</span></a>
+<a name="509"><span class="lineNum">     509 </span><span class="lineCov">         80 :   reg  [2:0]        state_vec_183;</span></a>
+<a name="510"><span class="lineNum">     510 </span><span class="lineCov">         73 :   reg  [2:0]        state_vec_184;</span></a>
+<a name="511"><span class="lineNum">     511 </span><span class="lineCov">         74 :   reg  [2:0]        state_vec_185;</span></a>
+<a name="512"><span class="lineNum">     512 </span><span class="lineCov">         64 :   reg  [2:0]        state_vec_186;</span></a>
+<a name="513"><span class="lineNum">     513 </span><span class="lineCov">         63 :   reg  [2:0]        state_vec_187;</span></a>
+<a name="514"><span class="lineNum">     514 </span><span class="lineCov">         78 :   reg  [2:0]        state_vec_188;</span></a>
+<a name="515"><span class="lineNum">     515 </span><span class="lineCov">         71 :   reg  [2:0]        state_vec_189;</span></a>
+<a name="516"><span class="lineNum">     516 </span><span class="lineCov">         62 :   reg  [2:0]        state_vec_190;</span></a>
+<a name="517"><span class="lineNum">     517 </span><span class="lineCov">         68 :   reg  [2:0]        state_vec_191;</span></a>
+<a name="518"><span class="lineNum">     518 </span><span class="lineCov">         71 :   reg  [2:0]        state_vec_192;</span></a>
+<a name="519"><span class="lineNum">     519 </span><span class="lineCov">         64 :   reg  [2:0]        state_vec_193;</span></a>
+<a name="520"><span class="lineNum">     520 </span><span class="lineCov">         74 :   reg  [2:0]        state_vec_194;</span></a>
+<a name="521"><span class="lineNum">     521 </span><span class="lineCov">         79 :   reg  [2:0]        state_vec_195;</span></a>
+<a name="522"><span class="lineNum">     522 </span><span class="lineCov">         71 :   reg  [2:0]        state_vec_196;</span></a>
+<a name="523"><span class="lineNum">     523 </span><span class="lineCov">         64 :   reg  [2:0]        state_vec_197;</span></a>
+<a name="524"><span class="lineNum">     524 </span><span class="lineCov">         68 :   reg  [2:0]        state_vec_198;</span></a>
+<a name="525"><span class="lineNum">     525 </span><span class="lineCov">         65 :   reg  [2:0]        state_vec_199;</span></a>
+<a name="526"><span class="lineNum">     526 </span><span class="lineCov">         68 :   reg  [2:0]        state_vec_200;</span></a>
+<a name="527"><span class="lineNum">     527 </span><span class="lineCov">         72 :   reg  [2:0]        state_vec_201;</span></a>
+<a name="528"><span class="lineNum">     528 </span><span class="lineCov">         68 :   reg  [2:0]        state_vec_202;</span></a>
+<a name="529"><span class="lineNum">     529 </span><span class="lineCov">         57 :   reg  [2:0]        state_vec_203;</span></a>
+<a name="530"><span class="lineNum">     530 </span><span class="lineCov">         73 :   reg  [2:0]        state_vec_204;</span></a>
+<a name="531"><span class="lineNum">     531 </span><span class="lineCov">         60 :   reg  [2:0]        state_vec_205;</span></a>
+<a name="532"><span class="lineNum">     532 </span><span class="lineCov">         65 :   reg  [2:0]        state_vec_206;</span></a>
+<a name="533"><span class="lineNum">     533 </span><span class="lineCov">         72 :   reg  [2:0]        state_vec_207;</span></a>
+<a name="534"><span class="lineNum">     534 </span><span class="lineCov">         69 :   reg  [2:0]        state_vec_208;</span></a>
+<a name="535"><span class="lineNum">     535 </span><span class="lineCov">         78 :   reg  [2:0]        state_vec_209;</span></a>
+<a name="536"><span class="lineNum">     536 </span><span class="lineCov">         75 :   reg  [2:0]        state_vec_210;</span></a>
+<a name="537"><span class="lineNum">     537 </span><span class="lineCov">         67 :   reg  [2:0]        state_vec_211;</span></a>
+<a name="538"><span class="lineNum">     538 </span><span class="lineCov">         69 :   reg  [2:0]        state_vec_212;</span></a>
+<a name="539"><span class="lineNum">     539 </span><span class="lineCov">         69 :   reg  [2:0]        state_vec_213;</span></a>
+<a name="540"><span class="lineNum">     540 </span><span class="lineCov">         70 :   reg  [2:0]        state_vec_214;</span></a>
+<a name="541"><span class="lineNum">     541 </span><span class="lineCov">         63 :   reg  [2:0]        state_vec_215;</span></a>
+<a name="542"><span class="lineNum">     542 </span><span class="lineCov">         74 :   reg  [2:0]        state_vec_216;</span></a>
+<a name="543"><span class="lineNum">     543 </span><span class="lineCov">         71 :   reg  [2:0]        state_vec_217;</span></a>
+<a name="544"><span class="lineNum">     544 </span><span class="lineCov">         68 :   reg  [2:0]        state_vec_218;</span></a>
+<a name="545"><span class="lineNum">     545 </span><span class="lineCov">         62 :   reg  [2:0]        state_vec_219;</span></a>
+<a name="546"><span class="lineNum">     546 </span><span class="lineCov">         70 :   reg  [2:0]        state_vec_220;</span></a>
+<a name="547"><span class="lineNum">     547 </span><span class="lineCov">         68 :   reg  [2:0]        state_vec_221;</span></a>
+<a name="548"><span class="lineNum">     548 </span><span class="lineCov">         66 :   reg  [2:0]        state_vec_222;</span></a>
+<a name="549"><span class="lineNum">     549 </span><span class="lineCov">         67 :   reg  [2:0]        state_vec_223;</span></a>
+<a name="550"><span class="lineNum">     550 </span><span class="lineCov">         66 :   reg  [2:0]        state_vec_224;</span></a>
+<a name="551"><span class="lineNum">     551 </span><span class="lineCov">         63 :   reg  [2:0]        state_vec_225;</span></a>
+<a name="552"><span class="lineNum">     552 </span><span class="lineCov">         65 :   reg  [2:0]        state_vec_226;</span></a>
+<a name="553"><span class="lineNum">     553 </span><span class="lineCov">         67 :   reg  [2:0]        state_vec_227;</span></a>
+<a name="554"><span class="lineNum">     554 </span><span class="lineCov">         66 :   reg  [2:0]        state_vec_228;</span></a>
+<a name="555"><span class="lineNum">     555 </span><span class="lineCov">         59 :   reg  [2:0]        state_vec_229;</span></a>
+<a name="556"><span class="lineNum">     556 </span><span class="lineCov">         63 :   reg  [2:0]        state_vec_230;</span></a>
+<a name="557"><span class="lineNum">     557 </span><span class="lineCov">         60 :   reg  [2:0]        state_vec_231;</span></a>
+<a name="558"><span class="lineNum">     558 </span><span class="lineCov">         71 :   reg  [2:0]        state_vec_232;</span></a>
+<a name="559"><span class="lineNum">     559 </span><span class="lineCov">         72 :   reg  [2:0]        state_vec_233;</span></a>
+<a name="560"><span class="lineNum">     560 </span><span class="lineCov">         75 :   reg  [2:0]        state_vec_234;</span></a>
+<a name="561"><span class="lineNum">     561 </span><span class="lineCov">         65 :   reg  [2:0]        state_vec_235;</span></a>
+<a name="562"><span class="lineNum">     562 </span><span class="lineCov">         71 :   reg  [2:0]        state_vec_236;</span></a>
+<a name="563"><span class="lineNum">     563 </span><span class="lineCov">         68 :   reg  [2:0]        state_vec_237;</span></a>
+<a name="564"><span class="lineNum">     564 </span><span class="lineCov">         78 :   reg  [2:0]        state_vec_238;</span></a>
+<a name="565"><span class="lineNum">     565 </span><span class="lineCov">         66 :   reg  [2:0]        state_vec_239;</span></a>
+<a name="566"><span class="lineNum">     566 </span><span class="lineCov">         74 :   reg  [2:0]        state_vec_240;</span></a>
+<a name="567"><span class="lineNum">     567 </span><span class="lineCov">         65 :   reg  [2:0]        state_vec_241;</span></a>
+<a name="568"><span class="lineNum">     568 </span><span class="lineCov">         67 :   reg  [2:0]        state_vec_242;</span></a>
+<a name="569"><span class="lineNum">     569 </span><span class="lineCov">         74 :   reg  [2:0]        state_vec_243;</span></a>
+<a name="570"><span class="lineNum">     570 </span><span class="lineCov">         68 :   reg  [2:0]        state_vec_244;</span></a>
+<a name="571"><span class="lineNum">     571 </span><span class="lineCov">         75 :   reg  [2:0]        state_vec_245;</span></a>
+<a name="572"><span class="lineNum">     572 </span><span class="lineCov">         64 :   reg  [2:0]        state_vec_246;</span></a>
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+<a name="621"><span class="lineNum">     621 </span><span class="lineCov">         67 :   reg  [2:0]        state_vec_295;</span></a>
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+<a name="623"><span class="lineNum">     623 </span><span class="lineCov">         75 :   reg  [2:0]        state_vec_297;</span></a>
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+<a name="627"><span class="lineNum">     627 </span><span class="lineCov">         81 :   reg  [2:0]        state_vec_301;</span></a>
+<a name="628"><span class="lineNum">     628 </span><span class="lineCov">         70 :   reg  [2:0]        state_vec_302;</span></a>
+<a name="629"><span class="lineNum">     629 </span><span class="lineCov">         74 :   reg  [2:0]        state_vec_303;</span></a>
+<a name="630"><span class="lineNum">     630 </span><span class="lineCov">         71 :   reg  [2:0]        state_vec_304;</span></a>
+<a name="631"><span class="lineNum">     631 </span><span class="lineCov">         70 :   reg  [2:0]        state_vec_305;</span></a>
+<a name="632"><span class="lineNum">     632 </span><span class="lineCov">         74 :   reg  [2:0]        state_vec_306;</span></a>
+<a name="633"><span class="lineNum">     633 </span><span class="lineCov">         66 :   reg  [2:0]        state_vec_307;</span></a>
+<a name="634"><span class="lineNum">     634 </span><span class="lineCov">         71 :   reg  [2:0]        state_vec_308;</span></a>
+<a name="635"><span class="lineNum">     635 </span><span class="lineCov">         63 :   reg  [2:0]        state_vec_309;</span></a>
+<a name="636"><span class="lineNum">     636 </span><span class="lineCov">         56 :   reg  [2:0]        state_vec_310;</span></a>
+<a name="637"><span class="lineNum">     637 </span><span class="lineCov">         71 :   reg  [2:0]        state_vec_311;</span></a>
+<a name="638"><span class="lineNum">     638 </span><span class="lineCov">         63 :   reg  [2:0]        state_vec_312;</span></a>
+<a name="639"><span class="lineNum">     639 </span><span class="lineCov">         66 :   reg  [2:0]        state_vec_313;</span></a>
+<a name="640"><span class="lineNum">     640 </span><span class="lineCov">         71 :   reg  [2:0]        state_vec_314;</span></a>
+<a name="641"><span class="lineNum">     641 </span><span class="lineCov">         72 :   reg  [2:0]        state_vec_315;</span></a>
+<a name="642"><span class="lineNum">     642 </span><span class="lineCov">         84 :   reg  [2:0]        state_vec_316;</span></a>
+<a name="643"><span class="lineNum">     643 </span><span class="lineCov">         69 :   reg  [2:0]        state_vec_317;</span></a>
+<a name="644"><span class="lineNum">     644 </span><span class="lineCov">         65 :   reg  [2:0]        state_vec_318;</span></a>
+<a name="645"><span class="lineNum">     645 </span><span class="lineCov">         70 :   reg  [2:0]        state_vec_319;</span></a>
+<a name="646"><span class="lineNum">     646 </span><span class="lineCov">         78 :   reg  [2:0]        state_vec_320;</span></a>
+<a name="647"><span class="lineNum">     647 </span><span class="lineCov">         72 :   reg  [2:0]        state_vec_321;</span></a>
+<a name="648"><span class="lineNum">     648 </span><span class="lineCov">         63 :   reg  [2:0]        state_vec_322;</span></a>
+<a name="649"><span class="lineNum">     649 </span><span class="lineCov">         62 :   reg  [2:0]        state_vec_323;</span></a>
+<a name="650"><span class="lineNum">     650 </span><span class="lineCov">         81 :   reg  [2:0]        state_vec_324;</span></a>
+<a name="651"><span class="lineNum">     651 </span><span class="lineCov">         62 :   reg  [2:0]        state_vec_325;</span></a>
+<a name="652"><span class="lineNum">     652 </span><span class="lineCov">         70 :   reg  [2:0]        state_vec_326;</span></a>
+<a name="653"><span class="lineNum">     653 </span><span class="lineCov">         74 :   reg  [2:0]        state_vec_327;</span></a>
+<a name="654"><span class="lineNum">     654 </span><span class="lineCov">         72 :   reg  [2:0]        state_vec_328;</span></a>
+<a name="655"><span class="lineNum">     655 </span><span class="lineCov">         73 :   reg  [2:0]        state_vec_329;</span></a>
+<a name="656"><span class="lineNum">     656 </span><span class="lineCov">         66 :   reg  [2:0]        state_vec_330;</span></a>
+<a name="657"><span class="lineNum">     657 </span><span class="lineCov">         67 :   reg  [2:0]        state_vec_331;</span></a>
+<a name="658"><span class="lineNum">     658 </span><span class="lineCov">         74 :   reg  [2:0]        state_vec_332;</span></a>
+<a name="659"><span class="lineNum">     659 </span><span class="lineCov">         69 :   reg  [2:0]        state_vec_333;</span></a>
+<a name="660"><span class="lineNum">     660 </span><span class="lineCov">         65 :   reg  [2:0]        state_vec_334;</span></a>
+<a name="661"><span class="lineNum">     661 </span><span class="lineCov">         68 :   reg  [2:0]        state_vec_335;</span></a>
+<a name="662"><span class="lineNum">     662 </span><span class="lineCov">         74 :   reg  [2:0]        state_vec_336;</span></a>
+<a name="663"><span class="lineNum">     663 </span><span class="lineCov">         62 :   reg  [2:0]        state_vec_337;</span></a>
+<a name="664"><span class="lineNum">     664 </span><span class="lineCov">         74 :   reg  [2:0]        state_vec_338;</span></a>
+<a name="665"><span class="lineNum">     665 </span><span class="lineCov">         68 :   reg  [2:0]        state_vec_339;</span></a>
+<a name="666"><span class="lineNum">     666 </span><span class="lineCov">         68 :   reg  [2:0]        state_vec_340;</span></a>
+<a name="667"><span class="lineNum">     667 </span><span class="lineCov">         60 :   reg  [2:0]        state_vec_341;</span></a>
+<a name="668"><span class="lineNum">     668 </span><span class="lineCov">         76 :   reg  [2:0]        state_vec_342;</span></a>
+<a name="669"><span class="lineNum">     669 </span><span class="lineCov">         61 :   reg  [2:0]        state_vec_343;</span></a>
+<a name="670"><span class="lineNum">     670 </span><span class="lineCov">         70 :   reg  [2:0]        state_vec_344;</span></a>
+<a name="671"><span class="lineNum">     671 </span><span class="lineCov">         66 :   reg  [2:0]        state_vec_345;</span></a>
+<a name="672"><span class="lineNum">     672 </span><span class="lineCov">         74 :   reg  [2:0]        state_vec_346;</span></a>
+<a name="673"><span class="lineNum">     673 </span><span class="lineCov">         68 :   reg  [2:0]        state_vec_347;</span></a>
+<a name="674"><span class="lineNum">     674 </span><span class="lineCov">         68 :   reg  [2:0]        state_vec_348;</span></a>
+<a name="675"><span class="lineNum">     675 </span><span class="lineCov">         73 :   reg  [2:0]        state_vec_349;</span></a>
+<a name="676"><span class="lineNum">     676 </span><span class="lineCov">         62 :   reg  [2:0]        state_vec_350;</span></a>
+<a name="677"><span class="lineNum">     677 </span><span class="lineCov">         65 :   reg  [2:0]        state_vec_351;</span></a>
+<a name="678"><span class="lineNum">     678 </span><span class="lineCov">         74 :   reg  [2:0]        state_vec_352;</span></a>
+<a name="679"><span class="lineNum">     679 </span><span class="lineCov">         69 :   reg  [2:0]        state_vec_353;</span></a>
+<a name="680"><span class="lineNum">     680 </span><span class="lineCov">         67 :   reg  [2:0]        state_vec_354;</span></a>
+<a name="681"><span class="lineNum">     681 </span><span class="lineCov">         61 :   reg  [2:0]        state_vec_355;</span></a>
+<a name="682"><span class="lineNum">     682 </span><span class="lineCov">         60 :   reg  [2:0]        state_vec_356;</span></a>
+<a name="683"><span class="lineNum">     683 </span><span class="lineCov">         72 :   reg  [2:0]        state_vec_357;</span></a>
+<a name="684"><span class="lineNum">     684 </span><span class="lineCov">         75 :   reg  [2:0]        state_vec_358;</span></a>
+<a name="685"><span class="lineNum">     685 </span><span class="lineCov">         65 :   reg  [2:0]        state_vec_359;</span></a>
+<a name="686"><span class="lineNum">     686 </span><span class="lineCov">         61 :   reg  [2:0]        state_vec_360;</span></a>
+<a name="687"><span class="lineNum">     687 </span><span class="lineCov">         74 :   reg  [2:0]        state_vec_361;</span></a>
+<a name="688"><span class="lineNum">     688 </span><span class="lineCov">         54 :   reg  [2:0]        state_vec_362;</span></a>
+<a name="689"><span class="lineNum">     689 </span><span class="lineCov">         61 :   reg  [2:0]        state_vec_363;</span></a>
+<a name="690"><span class="lineNum">     690 </span><span class="lineCov">         59 :   reg  [2:0]        state_vec_364;</span></a>
+<a name="691"><span class="lineNum">     691 </span><span class="lineCov">         62 :   reg  [2:0]        state_vec_365;</span></a>
+<a name="692"><span class="lineNum">     692 </span><span class="lineCov">         69 :   reg  [2:0]        state_vec_366;</span></a>
+<a name="693"><span class="lineNum">     693 </span><span class="lineCov">         73 :   reg  [2:0]        state_vec_367;</span></a>
+<a name="694"><span class="lineNum">     694 </span><span class="lineCov">         68 :   reg  [2:0]        state_vec_368;</span></a>
+<a name="695"><span class="lineNum">     695 </span><span class="lineCov">         74 :   reg  [2:0]        state_vec_369;</span></a>
+<a name="696"><span class="lineNum">     696 </span><span class="lineCov">         72 :   reg  [2:0]        state_vec_370;</span></a>
+<a name="697"><span class="lineNum">     697 </span><span class="lineCov">         82 :   reg  [2:0]        state_vec_371;</span></a>
+<a name="698"><span class="lineNum">     698 </span><span class="lineCov">         73 :   reg  [2:0]        state_vec_372;</span></a>
+<a name="699"><span class="lineNum">     699 </span><span class="lineCov">         70 :   reg  [2:0]        state_vec_373;</span></a>
+<a name="700"><span class="lineNum">     700 </span><span class="lineCov">         70 :   reg  [2:0]        state_vec_374;</span></a>
+<a name="701"><span class="lineNum">     701 </span><span class="lineCov">         59 :   reg  [2:0]        state_vec_375;</span></a>
+<a name="702"><span class="lineNum">     702 </span><span class="lineCov">         58 :   reg  [2:0]        state_vec_376;</span></a>
+<a name="703"><span class="lineNum">     703 </span><span class="lineCov">         67 :   reg  [2:0]        state_vec_377;</span></a>
+<a name="704"><span class="lineNum">     704 </span><span class="lineCov">         72 :   reg  [2:0]        state_vec_378;</span></a>
+<a name="705"><span class="lineNum">     705 </span><span class="lineCov">         72 :   reg  [2:0]        state_vec_379;</span></a>
+<a name="706"><span class="lineNum">     706 </span><span class="lineCov">         68 :   reg  [2:0]        state_vec_380;</span></a>
+<a name="707"><span class="lineNum">     707 </span><span class="lineCov">         62 :   reg  [2:0]        state_vec_381;</span></a>
+<a name="708"><span class="lineNum">     708 </span><span class="lineCov">         61 :   reg  [2:0]        state_vec_382;</span></a>
+<a name="709"><span class="lineNum">     709 </span><span class="lineCov">         71 :   reg  [2:0]        state_vec_383;</span></a>
+<a name="710"><span class="lineNum">     710 </span><span class="lineCov">         70 :   reg  [2:0]        state_vec_384;</span></a>
+<a name="711"><span class="lineNum">     711 </span><span class="lineCov">         81 :   reg  [2:0]        state_vec_385;</span></a>
+<a name="712"><span class="lineNum">     712 </span><span class="lineCov">         82 :   reg  [2:0]        state_vec_386;</span></a>
+<a name="713"><span class="lineNum">     713 </span><span class="lineCov">         80 :   reg  [2:0]        state_vec_387;</span></a>
+<a name="714"><span class="lineNum">     714 </span><span class="lineCov">         76 :   reg  [2:0]        state_vec_388;</span></a>
+<a name="715"><span class="lineNum">     715 </span><span class="lineCov">         67 :   reg  [2:0]        state_vec_389;</span></a>
+<a name="716"><span class="lineNum">     716 </span><span class="lineCov">         72 :   reg  [2:0]        state_vec_390;</span></a>
+<a name="717"><span class="lineNum">     717 </span><span class="lineCov">         65 :   reg  [2:0]        state_vec_391;</span></a>
+<a name="718"><span class="lineNum">     718 </span><span class="lineCov">         67 :   reg  [2:0]        state_vec_392;</span></a>
+<a name="719"><span class="lineNum">     719 </span><span class="lineCov">         68 :   reg  [2:0]        state_vec_393;</span></a>
+<a name="720"><span class="lineNum">     720 </span><span class="lineCov">         66 :   reg  [2:0]        state_vec_394;</span></a>
+<a name="721"><span class="lineNum">     721 </span><span class="lineCov">         69 :   reg  [2:0]        state_vec_395;</span></a>
+<a name="722"><span class="lineNum">     722 </span><span class="lineCov">         65 :   reg  [2:0]        state_vec_396;</span></a>
+<a name="723"><span class="lineNum">     723 </span><span class="lineCov">         82 :   reg  [2:0]        state_vec_397;</span></a>
+<a name="724"><span class="lineNum">     724 </span><span class="lineCov">         55 :   reg  [2:0]        state_vec_398;</span></a>
+<a name="725"><span class="lineNum">     725 </span><span class="lineCov">         70 :   reg  [2:0]        state_vec_399;</span></a>
+<a name="726"><span class="lineNum">     726 </span><span class="lineCov">         70 :   reg  [2:0]        state_vec_400;</span></a>
+<a name="727"><span class="lineNum">     727 </span><span class="lineCov">         72 :   reg  [2:0]        state_vec_401;</span></a>
+<a name="728"><span class="lineNum">     728 </span><span class="lineCov">         72 :   reg  [2:0]        state_vec_402;</span></a>
+<a name="729"><span class="lineNum">     729 </span><span class="lineCov">         71 :   reg  [2:0]        state_vec_403;</span></a>
+<a name="730"><span class="lineNum">     730 </span><span class="lineCov">         75 :   reg  [2:0]        state_vec_404;</span></a>
+<a name="731"><span class="lineNum">     731 </span><span class="lineCov">         76 :   reg  [2:0]        state_vec_405;</span></a>
+<a name="732"><span class="lineNum">     732 </span><span class="lineCov">         60 :   reg  [2:0]        state_vec_406;</span></a>
+<a name="733"><span class="lineNum">     733 </span><span class="lineCov">         62 :   reg  [2:0]        state_vec_407;</span></a>
+<a name="734"><span class="lineNum">     734 </span><span class="lineCov">         81 :   reg  [2:0]        state_vec_408;</span></a>
+<a name="735"><span class="lineNum">     735 </span><span class="lineCov">         72 :   reg  [2:0]        state_vec_409;</span></a>
+<a name="736"><span class="lineNum">     736 </span><span class="lineCov">         73 :   reg  [2:0]        state_vec_410;</span></a>
+<a name="737"><span class="lineNum">     737 </span><span class="lineCov">         66 :   reg  [2:0]        state_vec_411;</span></a>
+<a name="738"><span class="lineNum">     738 </span><span class="lineCov">         74 :   reg  [2:0]        state_vec_412;</span></a>
+<a name="739"><span class="lineNum">     739 </span><span class="lineCov">         70 :   reg  [2:0]        state_vec_413;</span></a>
+<a name="740"><span class="lineNum">     740 </span><span class="lineCov">         81 :   reg  [2:0]        state_vec_414;</span></a>
+<a name="741"><span class="lineNum">     741 </span><span class="lineCov">         77 :   reg  [2:0]        state_vec_415;</span></a>
+<a name="742"><span class="lineNum">     742 </span><span class="lineCov">         81 :   reg  [2:0]        state_vec_416;</span></a>
+<a name="743"><span class="lineNum">     743 </span><span class="lineCov">         58 :   reg  [2:0]        state_vec_417;</span></a>
+<a name="744"><span class="lineNum">     744 </span><span class="lineCov">         68 :   reg  [2:0]        state_vec_418;</span></a>
+<a name="745"><span class="lineNum">     745 </span><span class="lineCov">         74 :   reg  [2:0]        state_vec_419;</span></a>
+<a name="746"><span class="lineNum">     746 </span><span class="lineCov">         69 :   reg  [2:0]        state_vec_420;</span></a>
+<a name="747"><span class="lineNum">     747 </span><span class="lineCov">         75 :   reg  [2:0]        state_vec_421;</span></a>
+<a name="748"><span class="lineNum">     748 </span><span class="lineCov">         64 :   reg  [2:0]        state_vec_422;</span></a>
+<a name="749"><span class="lineNum">     749 </span><span class="lineCov">         70 :   reg  [2:0]        state_vec_423;</span></a>
+<a name="750"><span class="lineNum">     750 </span><span class="lineCov">         66 :   reg  [2:0]        state_vec_424;</span></a>
+<a name="751"><span class="lineNum">     751 </span><span class="lineCov">         73 :   reg  [2:0]        state_vec_425;</span></a>
+<a name="752"><span class="lineNum">     752 </span><span class="lineCov">         73 :   reg  [2:0]        state_vec_426;</span></a>
+<a name="753"><span class="lineNum">     753 </span><span class="lineCov">         76 :   reg  [2:0]        state_vec_427;</span></a>
+<a name="754"><span class="lineNum">     754 </span><span class="lineCov">         67 :   reg  [2:0]        state_vec_428;</span></a>
+<a name="755"><span class="lineNum">     755 </span><span class="lineCov">         60 :   reg  [2:0]        state_vec_429;</span></a>
+<a name="756"><span class="lineNum">     756 </span><span class="lineCov">         77 :   reg  [2:0]        state_vec_430;</span></a>
+<a name="757"><span class="lineNum">     757 </span><span class="lineCov">         68 :   reg  [2:0]        state_vec_431;</span></a>
+<a name="758"><span class="lineNum">     758 </span><span class="lineCov">         73 :   reg  [2:0]        state_vec_432;</span></a>
+<a name="759"><span class="lineNum">     759 </span><span class="lineCov">         59 :   reg  [2:0]        state_vec_433;</span></a>
+<a name="760"><span class="lineNum">     760 </span><span class="lineCov">         72 :   reg  [2:0]        state_vec_434;</span></a>
+<a name="761"><span class="lineNum">     761 </span><span class="lineCov">         66 :   reg  [2:0]        state_vec_435;</span></a>
+<a name="762"><span class="lineNum">     762 </span><span class="lineCov">         75 :   reg  [2:0]        state_vec_436;</span></a>
+<a name="763"><span class="lineNum">     763 </span><span class="lineCov">         77 :   reg  [2:0]        state_vec_437;</span></a>
+<a name="764"><span class="lineNum">     764 </span><span class="lineCov">         69 :   reg  [2:0]        state_vec_438;</span></a>
+<a name="765"><span class="lineNum">     765 </span><span class="lineCov">         68 :   reg  [2:0]        state_vec_439;</span></a>
+<a name="766"><span class="lineNum">     766 </span><span class="lineCov">         73 :   reg  [2:0]        state_vec_440;</span></a>
+<a name="767"><span class="lineNum">     767 </span><span class="lineCov">         72 :   reg  [2:0]        state_vec_441;</span></a>
+<a name="768"><span class="lineNum">     768 </span><span class="lineCov">         67 :   reg  [2:0]        state_vec_442;</span></a>
+<a name="769"><span class="lineNum">     769 </span><span class="lineCov">         63 :   reg  [2:0]        state_vec_443;</span></a>
+<a name="770"><span class="lineNum">     770 </span><span class="lineCov">         65 :   reg  [2:0]        state_vec_444;</span></a>
+<a name="771"><span class="lineNum">     771 </span><span class="lineCov">         73 :   reg  [2:0]        state_vec_445;</span></a>
+<a name="772"><span class="lineNum">     772 </span><span class="lineCov">         73 :   reg  [2:0]        state_vec_446;</span></a>
+<a name="773"><span class="lineNum">     773 </span><span class="lineCov">         75 :   reg  [2:0]        state_vec_447;</span></a>
+<a name="774"><span class="lineNum">     774 </span><span class="lineCov">         72 :   reg  [2:0]        state_vec_448;</span></a>
+<a name="775"><span class="lineNum">     775 </span><span class="lineCov">         62 :   reg  [2:0]        state_vec_449;</span></a>
+<a name="776"><span class="lineNum">     776 </span><span class="lineCov">         65 :   reg  [2:0]        state_vec_450;</span></a>
+<a name="777"><span class="lineNum">     777 </span><span class="lineCov">         75 :   reg  [2:0]        state_vec_451;</span></a>
+<a name="778"><span class="lineNum">     778 </span><span class="lineCov">         64 :   reg  [2:0]        state_vec_452;</span></a>
+<a name="779"><span class="lineNum">     779 </span><span class="lineCov">         68 :   reg  [2:0]        state_vec_453;</span></a>
+<a name="780"><span class="lineNum">     780 </span><span class="lineCov">         73 :   reg  [2:0]        state_vec_454;</span></a>
+<a name="781"><span class="lineNum">     781 </span><span class="lineCov">         73 :   reg  [2:0]        state_vec_455;</span></a>
+<a name="782"><span class="lineNum">     782 </span><span class="lineCov">         69 :   reg  [2:0]        state_vec_456;</span></a>
+<a name="783"><span class="lineNum">     783 </span><span class="lineCov">         82 :   reg  [2:0]        state_vec_457;</span></a>
+<a name="784"><span class="lineNum">     784 </span><span class="lineCov">         71 :   reg  [2:0]        state_vec_458;</span></a>
+<a name="785"><span class="lineNum">     785 </span><span class="lineCov">         69 :   reg  [2:0]        state_vec_459;</span></a>
+<a name="786"><span class="lineNum">     786 </span><span class="lineCov">         71 :   reg  [2:0]        state_vec_460;</span></a>
+<a name="787"><span class="lineNum">     787 </span><span class="lineCov">         66 :   reg  [2:0]        state_vec_461;</span></a>
+<a name="788"><span class="lineNum">     788 </span><span class="lineCov">         72 :   reg  [2:0]        state_vec_462;</span></a>
+<a name="789"><span class="lineNum">     789 </span><span class="lineCov">         61 :   reg  [2:0]        state_vec_463;</span></a>
+<a name="790"><span class="lineNum">     790 </span><span class="lineCov">         71 :   reg  [2:0]        state_vec_464;</span></a>
+<a name="791"><span class="lineNum">     791 </span><span class="lineCov">         68 :   reg  [2:0]        state_vec_465;</span></a>
+<a name="792"><span class="lineNum">     792 </span><span class="lineCov">         68 :   reg  [2:0]        state_vec_466;</span></a>
+<a name="793"><span class="lineNum">     793 </span><span class="lineCov">         81 :   reg  [2:0]        state_vec_467;</span></a>
+<a name="794"><span class="lineNum">     794 </span><span class="lineCov">         65 :   reg  [2:0]        state_vec_468;</span></a>
+<a name="795"><span class="lineNum">     795 </span><span class="lineCov">         69 :   reg  [2:0]        state_vec_469;</span></a>
+<a name="796"><span class="lineNum">     796 </span><span class="lineCov">         75 :   reg  [2:0]        state_vec_470;</span></a>
+<a name="797"><span class="lineNum">     797 </span><span class="lineCov">         73 :   reg  [2:0]        state_vec_471;</span></a>
+<a name="798"><span class="lineNum">     798 </span><span class="lineCov">         68 :   reg  [2:0]        state_vec_472;</span></a>
+<a name="799"><span class="lineNum">     799 </span><span class="lineCov">         73 :   reg  [2:0]        state_vec_473;</span></a>
+<a name="800"><span class="lineNum">     800 </span><span class="lineCov">         75 :   reg  [2:0]        state_vec_474;</span></a>
+<a name="801"><span class="lineNum">     801 </span><span class="lineCov">         64 :   reg  [2:0]        state_vec_475;</span></a>
+<a name="802"><span class="lineNum">     802 </span><span class="lineCov">         66 :   reg  [2:0]        state_vec_476;</span></a>
+<a name="803"><span class="lineNum">     803 </span><span class="lineCov">         72 :   reg  [2:0]        state_vec_477;</span></a>
+<a name="804"><span class="lineNum">     804 </span><span class="lineCov">         62 :   reg  [2:0]        state_vec_478;</span></a>
+<a name="805"><span class="lineNum">     805 </span><span class="lineCov">         62 :   reg  [2:0]        state_vec_479;</span></a>
+<a name="806"><span class="lineNum">     806 </span><span class="lineCov">         84 :   reg  [2:0]        state_vec_480;</span></a>
+<a name="807"><span class="lineNum">     807 </span><span class="lineCov">         84 :   reg  [2:0]        state_vec_481;</span></a>
+<a name="808"><span class="lineNum">     808 </span><span class="lineCov">         77 :   reg  [2:0]        state_vec_482;</span></a>
+<a name="809"><span class="lineNum">     809 </span><span class="lineCov">         72 :   reg  [2:0]        state_vec_483;</span></a>
+<a name="810"><span class="lineNum">     810 </span><span class="lineCov">         71 :   reg  [2:0]        state_vec_484;</span></a>
+<a name="811"><span class="lineNum">     811 </span><span class="lineCov">         66 :   reg  [2:0]        state_vec_485;</span></a>
+<a name="812"><span class="lineNum">     812 </span><span class="lineCov">         72 :   reg  [2:0]        state_vec_486;</span></a>
+<a name="813"><span class="lineNum">     813 </span><span class="lineCov">         78 :   reg  [2:0]        state_vec_487;</span></a>
+<a name="814"><span class="lineNum">     814 </span><span class="lineCov">         70 :   reg  [2:0]        state_vec_488;</span></a>
+<a name="815"><span class="lineNum">     815 </span><span class="lineCov">         66 :   reg  [2:0]        state_vec_489;</span></a>
+<a name="816"><span class="lineNum">     816 </span><span class="lineCov">         60 :   reg  [2:0]        state_vec_490;</span></a>
+<a name="817"><span class="lineNum">     817 </span><span class="lineCov">         71 :   reg  [2:0]        state_vec_491;</span></a>
+<a name="818"><span class="lineNum">     818 </span><span class="lineCov">         68 :   reg  [2:0]        state_vec_492;</span></a>
+<a name="819"><span class="lineNum">     819 </span><span class="lineCov">         68 :   reg  [2:0]        state_vec_493;</span></a>
+<a name="820"><span class="lineNum">     820 </span><span class="lineCov">         67 :   reg  [2:0]        state_vec_494;</span></a>
+<a name="821"><span class="lineNum">     821 </span><span class="lineCov">         67 :   reg  [2:0]        state_vec_495;</span></a>
+<a name="822"><span class="lineNum">     822 </span><span class="lineCov">         65 :   reg  [2:0]        state_vec_496;</span></a>
+<a name="823"><span class="lineNum">     823 </span><span class="lineCov">         61 :   reg  [2:0]        state_vec_497;</span></a>
+<a name="824"><span class="lineNum">     824 </span><span class="lineCov">         67 :   reg  [2:0]        state_vec_498;</span></a>
+<a name="825"><span class="lineNum">     825 </span><span class="lineCov">         62 :   reg  [2:0]        state_vec_499;</span></a>
+<a name="826"><span class="lineNum">     826 </span><span class="lineCov">         69 :   reg  [2:0]        state_vec_500;</span></a>
+<a name="827"><span class="lineNum">     827 </span><span class="lineCov">         72 :   reg  [2:0]        state_vec_501;</span></a>
+<a name="828"><span class="lineNum">     828 </span><span class="lineCov">         72 :   reg  [2:0]        state_vec_502;</span></a>
+<a name="829"><span class="lineNum">     829 </span><span class="lineCov">         63 :   reg  [2:0]        state_vec_503;</span></a>
+<a name="830"><span class="lineNum">     830 </span><span class="lineCov">         75 :   reg  [2:0]        state_vec_504;</span></a>
+<a name="831"><span class="lineNum">     831 </span><span class="lineCov">         71 :   reg  [2:0]        state_vec_505;</span></a>
+<a name="832"><span class="lineNum">     832 </span><span class="lineCov">         68 :   reg  [2:0]        state_vec_506;</span></a>
+<a name="833"><span class="lineNum">     833 </span><span class="lineCov">         65 :   reg  [2:0]        state_vec_507;</span></a>
+<a name="834"><span class="lineNum">     834 </span><span class="lineCov">         66 :   reg  [2:0]        state_vec_508;</span></a>
+<a name="835"><span class="lineNum">     835 </span><span class="lineCov">         75 :   reg  [2:0]        state_vec_509;</span></a>
+<a name="836"><span class="lineNum">     836 </span><span class="lineCov">         61 :   reg  [2:0]        state_vec_510;</span></a>
+<a name="837"><span class="lineNum">     837 </span><span class="lineCov">       8297 :   reg  [2:0]        state_vec_511;</span></a>
+<a name="838"><span class="lineNum">     838 </span><span class="lineCov">         29 :   reg  [8:0]        touch_set_0_REG;</span></a>
+<a name="839"><span class="lineNum">     839 </span><span class="lineCov">         66 :   reg               touch_way_0_valid_REG;</span></a>
+<a name="840"><span class="lineNum">     840 </span><span class="lineCov">         88 :   reg  [1:0]        touch_way_0_bits_REG;</span></a>
+<a name="841"><span class="lineNum">     841 </span><span class="lineCov">         40 :   reg               allocWriteWay_REG_0;</span></a>
+<a name="842"><span class="lineNum">     842 </span><span class="lineCov">         41 :   reg               allocWriteWay_REG_1;</span></a>
+<a name="843"><span class="lineNum">     843 </span><span class="lineCov">         52 :   reg               allocWriteWay_REG_2;</span></a>
+<a name="844"><span class="lineNum">     844 </span>            :   reg               allocWriteWay_REG_3;</a>
+<a name="845"><span class="lineNum">     845 </span>            :   wire [511:0][2:0] _GEN =</a>
+<a name="846"><span class="lineNum">     846 </span>            :     {{state_vec_511},</a>
+<a name="847"><span class="lineNum">     847 </span>            :      {state_vec_510},</a>
+<a name="848"><span class="lineNum">     848 </span>            :      {state_vec_509},</a>
+<a name="849"><span class="lineNum">     849 </span>            :      {state_vec_508},</a>
+<a name="850"><span class="lineNum">     850 </span>            :      {state_vec_507},</a>
+<a name="851"><span class="lineNum">     851 </span>            :      {state_vec_506},</a>
+<a name="852"><span class="lineNum">     852 </span>            :      {state_vec_505},</a>
+<a name="853"><span class="lineNum">     853 </span>            :      {state_vec_504},</a>
+<a name="854"><span class="lineNum">     854 </span>            :      {state_vec_503},</a>
+<a name="855"><span class="lineNum">     855 </span>            :      {state_vec_502},</a>
+<a name="856"><span class="lineNum">     856 </span>            :      {state_vec_501},</a>
+<a name="857"><span class="lineNum">     857 </span>            :      {state_vec_500},</a>
+<a name="858"><span class="lineNum">     858 </span>            :      {state_vec_499},</a>
+<a name="859"><span class="lineNum">     859 </span>            :      {state_vec_498},</a>
+<a name="860"><span class="lineNum">     860 </span>            :      {state_vec_497},</a>
+<a name="861"><span class="lineNum">     861 </span>            :      {state_vec_496},</a>
+<a name="862"><span class="lineNum">     862 </span>            :      {state_vec_495},</a>
+<a name="863"><span class="lineNum">     863 </span>            :      {state_vec_494},</a>
+<a name="864"><span class="lineNum">     864 </span>            :      {state_vec_493},</a>
+<a name="865"><span class="lineNum">     865 </span>            :      {state_vec_492},</a>
+<a name="866"><span class="lineNum">     866 </span>            :      {state_vec_491},</a>
+<a name="867"><span class="lineNum">     867 </span>            :      {state_vec_490},</a>
+<a name="868"><span class="lineNum">     868 </span>            :      {state_vec_489},</a>
+<a name="869"><span class="lineNum">     869 </span>            :      {state_vec_488},</a>
+<a name="870"><span class="lineNum">     870 </span>            :      {state_vec_487},</a>
+<a name="871"><span class="lineNum">     871 </span>            :      {state_vec_486},</a>
+<a name="872"><span class="lineNum">     872 </span>            :      {state_vec_485},</a>
+<a name="873"><span class="lineNum">     873 </span>            :      {state_vec_484},</a>
+<a name="874"><span class="lineNum">     874 </span>            :      {state_vec_483},</a>
+<a name="875"><span class="lineNum">     875 </span>            :      {state_vec_482},</a>
+<a name="876"><span class="lineNum">     876 </span>            :      {state_vec_481},</a>
+<a name="877"><span class="lineNum">     877 </span>            :      {state_vec_480},</a>
+<a name="878"><span class="lineNum">     878 </span>            :      {state_vec_479},</a>
+<a name="879"><span class="lineNum">     879 </span>            :      {state_vec_478},</a>
+<a name="880"><span class="lineNum">     880 </span>            :      {state_vec_477},</a>
+<a name="881"><span class="lineNum">     881 </span>            :      {state_vec_476},</a>
+<a name="882"><span class="lineNum">     882 </span>            :      {state_vec_475},</a>
+<a name="883"><span class="lineNum">     883 </span>            :      {state_vec_474},</a>
+<a name="884"><span class="lineNum">     884 </span>            :      {state_vec_473},</a>
+<a name="885"><span class="lineNum">     885 </span>            :      {state_vec_472},</a>
+<a name="886"><span class="lineNum">     886 </span>            :      {state_vec_471},</a>
+<a name="887"><span class="lineNum">     887 </span>            :      {state_vec_470},</a>
+<a name="888"><span class="lineNum">     888 </span>            :      {state_vec_469},</a>
+<a name="889"><span class="lineNum">     889 </span>            :      {state_vec_468},</a>
+<a name="890"><span class="lineNum">     890 </span>            :      {state_vec_467},</a>
+<a name="891"><span class="lineNum">     891 </span>            :      {state_vec_466},</a>
+<a name="892"><span class="lineNum">     892 </span>            :      {state_vec_465},</a>
+<a name="893"><span class="lineNum">     893 </span>            :      {state_vec_464},</a>
+<a name="894"><span class="lineNum">     894 </span>            :      {state_vec_463},</a>
+<a name="895"><span class="lineNum">     895 </span>            :      {state_vec_462},</a>
+<a name="896"><span class="lineNum">     896 </span>            :      {state_vec_461},</a>
+<a name="897"><span class="lineNum">     897 </span>            :      {state_vec_460},</a>
+<a name="898"><span class="lineNum">     898 </span>            :      {state_vec_459},</a>
+<a name="899"><span class="lineNum">     899 </span>            :      {state_vec_458},</a>
+<a name="900"><span class="lineNum">     900 </span>            :      {state_vec_457},</a>
+<a name="901"><span class="lineNum">     901 </span>            :      {state_vec_456},</a>
+<a name="902"><span class="lineNum">     902 </span>            :      {state_vec_455},</a>
+<a name="903"><span class="lineNum">     903 </span>            :      {state_vec_454},</a>
+<a name="904"><span class="lineNum">     904 </span>            :      {state_vec_453},</a>
+<a name="905"><span class="lineNum">     905 </span>            :      {state_vec_452},</a>
+<a name="906"><span class="lineNum">     906 </span>            :      {state_vec_451},</a>
+<a name="907"><span class="lineNum">     907 </span>            :      {state_vec_450},</a>
+<a name="908"><span class="lineNum">     908 </span>            :      {state_vec_449},</a>
+<a name="909"><span class="lineNum">     909 </span>            :      {state_vec_448},</a>
+<a name="910"><span class="lineNum">     910 </span>            :      {state_vec_447},</a>
+<a name="911"><span class="lineNum">     911 </span>            :      {state_vec_446},</a>
+<a name="912"><span class="lineNum">     912 </span>            :      {state_vec_445},</a>
+<a name="913"><span class="lineNum">     913 </span>            :      {state_vec_444},</a>
+<a name="914"><span class="lineNum">     914 </span>            :      {state_vec_443},</a>
+<a name="915"><span class="lineNum">     915 </span>            :      {state_vec_442},</a>
+<a name="916"><span class="lineNum">     916 </span>            :      {state_vec_441},</a>
+<a name="917"><span class="lineNum">     917 </span>            :      {state_vec_440},</a>
+<a name="918"><span class="lineNum">     918 </span>            :      {state_vec_439},</a>
+<a name="919"><span class="lineNum">     919 </span>            :      {state_vec_438},</a>
+<a name="920"><span class="lineNum">     920 </span>            :      {state_vec_437},</a>
+<a name="921"><span class="lineNum">     921 </span>            :      {state_vec_436},</a>
+<a name="922"><span class="lineNum">     922 </span>            :      {state_vec_435},</a>
+<a name="923"><span class="lineNum">     923 </span>            :      {state_vec_434},</a>
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+<a name="1160"><span class="lineNum">    1160 </span>            :      {state_vec_197},</a>
+<a name="1161"><span class="lineNum">    1161 </span>            :      {state_vec_196},</a>
+<a name="1162"><span class="lineNum">    1162 </span>            :      {state_vec_195},</a>
+<a name="1163"><span class="lineNum">    1163 </span>            :      {state_vec_194},</a>
+<a name="1164"><span class="lineNum">    1164 </span>            :      {state_vec_193},</a>
+<a name="1165"><span class="lineNum">    1165 </span>            :      {state_vec_192},</a>
+<a name="1166"><span class="lineNum">    1166 </span>            :      {state_vec_191},</a>
+<a name="1167"><span class="lineNum">    1167 </span>            :      {state_vec_190},</a>
+<a name="1168"><span class="lineNum">    1168 </span>            :      {state_vec_189},</a>
+<a name="1169"><span class="lineNum">    1169 </span>            :      {state_vec_188},</a>
+<a name="1170"><span class="lineNum">    1170 </span>            :      {state_vec_187},</a>
+<a name="1171"><span class="lineNum">    1171 </span>            :      {state_vec_186},</a>
+<a name="1172"><span class="lineNum">    1172 </span>            :      {state_vec_185},</a>
+<a name="1173"><span class="lineNum">    1173 </span>            :      {state_vec_184},</a>
+<a name="1174"><span class="lineNum">    1174 </span>            :      {state_vec_183},</a>
+<a name="1175"><span class="lineNum">    1175 </span>            :      {state_vec_182},</a>
+<a name="1176"><span class="lineNum">    1176 </span>            :      {state_vec_181},</a>
+<a name="1177"><span class="lineNum">    1177 </span>            :      {state_vec_180},</a>
+<a name="1178"><span class="lineNum">    1178 </span>            :      {state_vec_179},</a>
+<a name="1179"><span class="lineNum">    1179 </span>            :      {state_vec_178},</a>
+<a name="1180"><span class="lineNum">    1180 </span>            :      {state_vec_177},</a>
+<a name="1181"><span class="lineNum">    1181 </span>            :      {state_vec_176},</a>
+<a name="1182"><span class="lineNum">    1182 </span>            :      {state_vec_175},</a>
+<a name="1183"><span class="lineNum">    1183 </span>            :      {state_vec_174},</a>
+<a name="1184"><span class="lineNum">    1184 </span>            :      {state_vec_173},</a>
+<a name="1185"><span class="lineNum">    1185 </span>            :      {state_vec_172},</a>
+<a name="1186"><span class="lineNum">    1186 </span>            :      {state_vec_171},</a>
+<a name="1187"><span class="lineNum">    1187 </span>            :      {state_vec_170},</a>
+<a name="1188"><span class="lineNum">    1188 </span>            :      {state_vec_169},</a>
+<a name="1189"><span class="lineNum">    1189 </span>            :      {state_vec_168},</a>
+<a name="1190"><span class="lineNum">    1190 </span>            :      {state_vec_167},</a>
+<a name="1191"><span class="lineNum">    1191 </span>            :      {state_vec_166},</a>
+<a name="1192"><span class="lineNum">    1192 </span>            :      {state_vec_165},</a>
+<a name="1193"><span class="lineNum">    1193 </span>            :      {state_vec_164},</a>
+<a name="1194"><span class="lineNum">    1194 </span>            :      {state_vec_163},</a>
+<a name="1195"><span class="lineNum">    1195 </span>            :      {state_vec_162},</a>
+<a name="1196"><span class="lineNum">    1196 </span>            :      {state_vec_161},</a>
+<a name="1197"><span class="lineNum">    1197 </span>            :      {state_vec_160},</a>
+<a name="1198"><span class="lineNum">    1198 </span>            :      {state_vec_159},</a>
+<a name="1199"><span class="lineNum">    1199 </span>            :      {state_vec_158},</a>
+<a name="1200"><span class="lineNum">    1200 </span>            :      {state_vec_157},</a>
+<a name="1201"><span class="lineNum">    1201 </span>            :      {state_vec_156},</a>
+<a name="1202"><span class="lineNum">    1202 </span>            :      {state_vec_155},</a>
+<a name="1203"><span class="lineNum">    1203 </span>            :      {state_vec_154},</a>
+<a name="1204"><span class="lineNum">    1204 </span>            :      {state_vec_153},</a>
+<a name="1205"><span class="lineNum">    1205 </span>            :      {state_vec_152},</a>
+<a name="1206"><span class="lineNum">    1206 </span>            :      {state_vec_151},</a>
+<a name="1207"><span class="lineNum">    1207 </span>            :      {state_vec_150},</a>
+<a name="1208"><span class="lineNum">    1208 </span>            :      {state_vec_149},</a>
+<a name="1209"><span class="lineNum">    1209 </span>            :      {state_vec_148},</a>
+<a name="1210"><span class="lineNum">    1210 </span>            :      {state_vec_147},</a>
+<a name="1211"><span class="lineNum">    1211 </span>            :      {state_vec_146},</a>
+<a name="1212"><span class="lineNum">    1212 </span>            :      {state_vec_145},</a>
+<a name="1213"><span class="lineNum">    1213 </span>            :      {state_vec_144},</a>
+<a name="1214"><span class="lineNum">    1214 </span>            :      {state_vec_143},</a>
+<a name="1215"><span class="lineNum">    1215 </span>            :      {state_vec_142},</a>
+<a name="1216"><span class="lineNum">    1216 </span>            :      {state_vec_141},</a>
+<a name="1217"><span class="lineNum">    1217 </span>            :      {state_vec_140},</a>
+<a name="1218"><span class="lineNum">    1218 </span>            :      {state_vec_139},</a>
+<a name="1219"><span class="lineNum">    1219 </span>            :      {state_vec_138},</a>
+<a name="1220"><span class="lineNum">    1220 </span>            :      {state_vec_137},</a>
+<a name="1221"><span class="lineNum">    1221 </span>            :      {state_vec_136},</a>
+<a name="1222"><span class="lineNum">    1222 </span>            :      {state_vec_135},</a>
+<a name="1223"><span class="lineNum">    1223 </span>            :      {state_vec_134},</a>
+<a name="1224"><span class="lineNum">    1224 </span>            :      {state_vec_133},</a>
+<a name="1225"><span class="lineNum">    1225 </span>            :      {state_vec_132},</a>
+<a name="1226"><span class="lineNum">    1226 </span>            :      {state_vec_131},</a>
+<a name="1227"><span class="lineNum">    1227 </span>            :      {state_vec_130},</a>
+<a name="1228"><span class="lineNum">    1228 </span>            :      {state_vec_129},</a>
+<a name="1229"><span class="lineNum">    1229 </span>            :      {state_vec_128},</a>
+<a name="1230"><span class="lineNum">    1230 </span>            :      {state_vec_127},</a>
+<a name="1231"><span class="lineNum">    1231 </span>            :      {state_vec_126},</a>
+<a name="1232"><span class="lineNum">    1232 </span>            :      {state_vec_125},</a>
+<a name="1233"><span class="lineNum">    1233 </span>            :      {state_vec_124},</a>
+<a name="1234"><span class="lineNum">    1234 </span>            :      {state_vec_123},</a>
+<a name="1235"><span class="lineNum">    1235 </span>            :      {state_vec_122},</a>
+<a name="1236"><span class="lineNum">    1236 </span>            :      {state_vec_121},</a>
+<a name="1237"><span class="lineNum">    1237 </span>            :      {state_vec_120},</a>
+<a name="1238"><span class="lineNum">    1238 </span>            :      {state_vec_119},</a>
+<a name="1239"><span class="lineNum">    1239 </span>            :      {state_vec_118},</a>
+<a name="1240"><span class="lineNum">    1240 </span>            :      {state_vec_117},</a>
+<a name="1241"><span class="lineNum">    1241 </span>            :      {state_vec_116},</a>
+<a name="1242"><span class="lineNum">    1242 </span>            :      {state_vec_115},</a>
+<a name="1243"><span class="lineNum">    1243 </span>            :      {state_vec_114},</a>
+<a name="1244"><span class="lineNum">    1244 </span>            :      {state_vec_113},</a>
+<a name="1245"><span class="lineNum">    1245 </span>            :      {state_vec_112},</a>
+<a name="1246"><span class="lineNum">    1246 </span>            :      {state_vec_111},</a>
+<a name="1247"><span class="lineNum">    1247 </span>            :      {state_vec_110},</a>
+<a name="1248"><span class="lineNum">    1248 </span>            :      {state_vec_109},</a>
+<a name="1249"><span class="lineNum">    1249 </span>            :      {state_vec_108},</a>
+<a name="1250"><span class="lineNum">    1250 </span>            :      {state_vec_107},</a>
+<a name="1251"><span class="lineNum">    1251 </span>            :      {state_vec_106},</a>
+<a name="1252"><span class="lineNum">    1252 </span>            :      {state_vec_105},</a>
+<a name="1253"><span class="lineNum">    1253 </span>            :      {state_vec_104},</a>
+<a name="1254"><span class="lineNum">    1254 </span>            :      {state_vec_103},</a>
+<a name="1255"><span class="lineNum">    1255 </span>            :      {state_vec_102},</a>
+<a name="1256"><span class="lineNum">    1256 </span>            :      {state_vec_101},</a>
+<a name="1257"><span class="lineNum">    1257 </span>            :      {state_vec_100},</a>
+<a name="1258"><span class="lineNum">    1258 </span>            :      {state_vec_99},</a>
+<a name="1259"><span class="lineNum">    1259 </span>            :      {state_vec_98},</a>
+<a name="1260"><span class="lineNum">    1260 </span>            :      {state_vec_97},</a>
+<a name="1261"><span class="lineNum">    1261 </span>            :      {state_vec_96},</a>
+<a name="1262"><span class="lineNum">    1262 </span>            :      {state_vec_95},</a>
+<a name="1263"><span class="lineNum">    1263 </span>            :      {state_vec_94},</a>
+<a name="1264"><span class="lineNum">    1264 </span>            :      {state_vec_93},</a>
+<a name="1265"><span class="lineNum">    1265 </span>            :      {state_vec_92},</a>
+<a name="1266"><span class="lineNum">    1266 </span>            :      {state_vec_91},</a>
+<a name="1267"><span class="lineNum">    1267 </span>            :      {state_vec_90},</a>
+<a name="1268"><span class="lineNum">    1268 </span>            :      {state_vec_89},</a>
+<a name="1269"><span class="lineNum">    1269 </span>            :      {state_vec_88},</a>
+<a name="1270"><span class="lineNum">    1270 </span>            :      {state_vec_87},</a>
+<a name="1271"><span class="lineNum">    1271 </span>            :      {state_vec_86},</a>
+<a name="1272"><span class="lineNum">    1272 </span>            :      {state_vec_85},</a>
+<a name="1273"><span class="lineNum">    1273 </span>            :      {state_vec_84},</a>
+<a name="1274"><span class="lineNum">    1274 </span>            :      {state_vec_83},</a>
+<a name="1275"><span class="lineNum">    1275 </span>            :      {state_vec_82},</a>
+<a name="1276"><span class="lineNum">    1276 </span>            :      {state_vec_81},</a>
+<a name="1277"><span class="lineNum">    1277 </span>            :      {state_vec_80},</a>
+<a name="1278"><span class="lineNum">    1278 </span>            :      {state_vec_79},</a>
+<a name="1279"><span class="lineNum">    1279 </span>            :      {state_vec_78},</a>
+<a name="1280"><span class="lineNum">    1280 </span>            :      {state_vec_77},</a>
+<a name="1281"><span class="lineNum">    1281 </span>            :      {state_vec_76},</a>
+<a name="1282"><span class="lineNum">    1282 </span>            :      {state_vec_75},</a>
+<a name="1283"><span class="lineNum">    1283 </span>            :      {state_vec_74},</a>
+<a name="1284"><span class="lineNum">    1284 </span>            :      {state_vec_73},</a>
+<a name="1285"><span class="lineNum">    1285 </span>            :      {state_vec_72},</a>
+<a name="1286"><span class="lineNum">    1286 </span>            :      {state_vec_71},</a>
+<a name="1287"><span class="lineNum">    1287 </span>            :      {state_vec_70},</a>
+<a name="1288"><span class="lineNum">    1288 </span>            :      {state_vec_69},</a>
+<a name="1289"><span class="lineNum">    1289 </span>            :      {state_vec_68},</a>
+<a name="1290"><span class="lineNum">    1290 </span>            :      {state_vec_67},</a>
+<a name="1291"><span class="lineNum">    1291 </span>            :      {state_vec_66},</a>
+<a name="1292"><span class="lineNum">    1292 </span>            :      {state_vec_65},</a>
+<a name="1293"><span class="lineNum">    1293 </span>            :      {state_vec_64},</a>
+<a name="1294"><span class="lineNum">    1294 </span>            :      {state_vec_63},</a>
+<a name="1295"><span class="lineNum">    1295 </span>            :      {state_vec_62},</a>
+<a name="1296"><span class="lineNum">    1296 </span>            :      {state_vec_61},</a>
+<a name="1297"><span class="lineNum">    1297 </span>            :      {state_vec_60},</a>
+<a name="1298"><span class="lineNum">    1298 </span>            :      {state_vec_59},</a>
+<a name="1299"><span class="lineNum">    1299 </span>            :      {state_vec_58},</a>
+<a name="1300"><span class="lineNum">    1300 </span>            :      {state_vec_57},</a>
+<a name="1301"><span class="lineNum">    1301 </span>            :      {state_vec_56},</a>
+<a name="1302"><span class="lineNum">    1302 </span>            :      {state_vec_55},</a>
+<a name="1303"><span class="lineNum">    1303 </span>            :      {state_vec_54},</a>
+<a name="1304"><span class="lineNum">    1304 </span>            :      {state_vec_53},</a>
+<a name="1305"><span class="lineNum">    1305 </span>            :      {state_vec_52},</a>
+<a name="1306"><span class="lineNum">    1306 </span>            :      {state_vec_51},</a>
+<a name="1307"><span class="lineNum">    1307 </span>            :      {state_vec_50},</a>
+<a name="1308"><span class="lineNum">    1308 </span>            :      {state_vec_49},</a>
+<a name="1309"><span class="lineNum">    1309 </span>            :      {state_vec_48},</a>
+<a name="1310"><span class="lineNum">    1310 </span>            :      {state_vec_47},</a>
+<a name="1311"><span class="lineNum">    1311 </span>            :      {state_vec_46},</a>
+<a name="1312"><span class="lineNum">    1312 </span>            :      {state_vec_45},</a>
+<a name="1313"><span class="lineNum">    1313 </span>            :      {state_vec_44},</a>
+<a name="1314"><span class="lineNum">    1314 </span>            :      {state_vec_43},</a>
+<a name="1315"><span class="lineNum">    1315 </span>            :      {state_vec_42},</a>
+<a name="1316"><span class="lineNum">    1316 </span>            :      {state_vec_41},</a>
+<a name="1317"><span class="lineNum">    1317 </span>            :      {state_vec_40},</a>
+<a name="1318"><span class="lineNum">    1318 </span>            :      {state_vec_39},</a>
+<a name="1319"><span class="lineNum">    1319 </span>            :      {state_vec_38},</a>
+<a name="1320"><span class="lineNum">    1320 </span>            :      {state_vec_37},</a>
+<a name="1321"><span class="lineNum">    1321 </span>            :      {state_vec_36},</a>
+<a name="1322"><span class="lineNum">    1322 </span>            :      {state_vec_35},</a>
+<a name="1323"><span class="lineNum">    1323 </span>            :      {state_vec_34},</a>
+<a name="1324"><span class="lineNum">    1324 </span>            :      {state_vec_33},</a>
+<a name="1325"><span class="lineNum">    1325 </span>            :      {state_vec_32},</a>
+<a name="1326"><span class="lineNum">    1326 </span>            :      {state_vec_31},</a>
+<a name="1327"><span class="lineNum">    1327 </span>            :      {state_vec_30},</a>
+<a name="1328"><span class="lineNum">    1328 </span>            :      {state_vec_29},</a>
+<a name="1329"><span class="lineNum">    1329 </span>            :      {state_vec_28},</a>
+<a name="1330"><span class="lineNum">    1330 </span>            :      {state_vec_27},</a>
+<a name="1331"><span class="lineNum">    1331 </span>            :      {state_vec_26},</a>
+<a name="1332"><span class="lineNum">    1332 </span>            :      {state_vec_25},</a>
+<a name="1333"><span class="lineNum">    1333 </span>            :      {state_vec_24},</a>
+<a name="1334"><span class="lineNum">    1334 </span>            :      {state_vec_23},</a>
+<a name="1335"><span class="lineNum">    1335 </span>            :      {state_vec_22},</a>
+<a name="1336"><span class="lineNum">    1336 </span>            :      {state_vec_21},</a>
+<a name="1337"><span class="lineNum">    1337 </span>            :      {state_vec_20},</a>
+<a name="1338"><span class="lineNum">    1338 </span>            :      {state_vec_19},</a>
+<a name="1339"><span class="lineNum">    1339 </span>            :      {state_vec_18},</a>
+<a name="1340"><span class="lineNum">    1340 </span>            :      {state_vec_17},</a>
+<a name="1341"><span class="lineNum">    1341 </span>            :      {state_vec_16},</a>
+<a name="1342"><span class="lineNum">    1342 </span>            :      {state_vec_15},</a>
+<a name="1343"><span class="lineNum">    1343 </span>            :      {state_vec_14},</a>
+<a name="1344"><span class="lineNum">    1344 </span>            :      {state_vec_13},</a>
+<a name="1345"><span class="lineNum">    1345 </span>            :      {state_vec_12},</a>
+<a name="1346"><span class="lineNum">    1346 </span>            :      {state_vec_11},</a>
+<a name="1347"><span class="lineNum">    1347 </span>            :      {state_vec_10},</a>
+<a name="1348"><span class="lineNum">    1348 </span>            :      {state_vec_9},</a>
+<a name="1349"><span class="lineNum">    1349 </span>            :      {state_vec_8},</a>
+<a name="1350"><span class="lineNum">    1350 </span>            :      {state_vec_7},</a>
+<a name="1351"><span class="lineNum">    1351 </span>            :      {state_vec_6},</a>
+<a name="1352"><span class="lineNum">    1352 </span>            :      {state_vec_5},</a>
+<a name="1353"><span class="lineNum">    1353 </span>            :      {state_vec_4},</a>
+<a name="1354"><span class="lineNum">    1354 </span>            :      {state_vec_3},</a>
+<a name="1355"><span class="lineNum">    1355 </span>            :      {state_vec_2},</a>
+<a name="1356"><span class="lineNum">    1356 </span>            :      {state_vec_1},</a>
+<a name="1357"><span class="lineNum">    1357 </span>            :      {state_vec_0}};</a>
+<a name="1358"><span class="lineNum">    1358 </span>            :   wire [2:0]        _GEN_0 = _GEN[io_update_pc[9:1]];</a>
+<a name="1359"><span class="lineNum">    1359 </span>            :   wire [2:0]        _allocWriteWay_w_T_4 =</a>
+<a name="1360"><span class="lineNum">    1360 </span><span class="lineCov">        127 :     ~{allocWriteWay_REG_2, allocWriteWay_REG_1, allocWriteWay_REG_0};</span></a>
+<a name="1361"><span class="lineNum">    1361 </span>            :   wire [1:0]        u_way =</a>
+<a name="1362"><span class="lineNum">    1362 </span>            :     io_update_write_alloc</a>
+<a name="1363"><span class="lineNum">    1363 </span>            :       ? ((&amp;{allocWriteWay_REG_3,</a>
+<a name="1364"><span class="lineNum">    1364 </span>            :             allocWriteWay_REG_2,</a>
+<a name="1365"><span class="lineNum">    1365 </span>            :             allocWriteWay_REG_1,</a>
+<a name="1366"><span class="lineNum">    1366 </span>            :             allocWriteWay_REG_0})</a>
+<a name="1367"><span class="lineNum">    1367 </span>            :            ? {_GEN_0[2], _GEN_0[2] ? _GEN_0[1] : _GEN_0[0]}</a>
+<a name="1368"><span class="lineNum">    1368 </span>            :            : _allocWriteWay_w_T_4[0]</a>
+<a name="1369"><span class="lineNum">    1369 </span>            :                ? 2'h0</a>
+<a name="1370"><span class="lineNum">    1370 </span>            :                : _allocWriteWay_w_T_4[1] ? 2'h1 : {1'h1, ~(_allocWriteWay_w_T_4[2])})</a>
+<a name="1371"><span class="lineNum">    1371 </span><span class="lineCov">     127694 :       : io_update_write_way;</span></a>
+<a name="1372"><span class="lineNum">    1372 </span><span class="lineCov">      63847 :   always @(posedge clock) begin</span></a>
+<a name="1373"><span class="lineNum">    1373 </span><span class="lineCov">       8320 :     pred_rdata_REG &lt;= io_req_pc_valid &amp; ~io_update_access;</span></a>
+<a name="1374"><span class="lineNum">    1374 </span><span class="lineCov">       4160 :     if (pred_rdata_REG) begin</span></a>
+<a name="1375"><span class="lineNum">    1375 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_0_entry_valid &lt;= _ftb_io_r_resp_data_0_entry_valid;</span></a>
+<a name="1376"><span class="lineNum">    1376 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_0_entry_brSlots_0_offset &lt;=</span></a>
+<a name="1377"><span class="lineNum">    1377 </span><span class="lineCov">       4160 :         _ftb_io_r_resp_data_0_entry_brSlots_0_offset;</span></a>
+<a name="1378"><span class="lineNum">    1378 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_0_entry_brSlots_0_lower &lt;=</span></a>
+<a name="1379"><span class="lineNum">    1379 </span><span class="lineCov">       4160 :         _ftb_io_r_resp_data_0_entry_brSlots_0_lower;</span></a>
+<a name="1380"><span class="lineNum">    1380 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_0_entry_brSlots_0_tarStat &lt;=</span></a>
+<a name="1381"><span class="lineNum">    1381 </span><span class="lineCov">       4160 :         _ftb_io_r_resp_data_0_entry_brSlots_0_tarStat;</span></a>
+<a name="1382"><span class="lineNum">    1382 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_0_entry_brSlots_0_sharing &lt;=</span></a>
+<a name="1383"><span class="lineNum">    1383 </span><span class="lineCov">       4160 :         _ftb_io_r_resp_data_0_entry_brSlots_0_sharing;</span></a>
+<a name="1384"><span class="lineNum">    1384 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_0_entry_brSlots_0_valid &lt;=</span></a>
+<a name="1385"><span class="lineNum">    1385 </span><span class="lineCov">       4160 :         _ftb_io_r_resp_data_0_entry_brSlots_0_valid;</span></a>
+<a name="1386"><span class="lineNum">    1386 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_0_entry_tailSlot_offset &lt;=</span></a>
+<a name="1387"><span class="lineNum">    1387 </span><span class="lineCov">       4160 :         _ftb_io_r_resp_data_0_entry_tailSlot_offset;</span></a>
+<a name="1388"><span class="lineNum">    1388 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_0_entry_tailSlot_lower &lt;=</span></a>
+<a name="1389"><span class="lineNum">    1389 </span><span class="lineCov">       4160 :         _ftb_io_r_resp_data_0_entry_tailSlot_lower;</span></a>
+<a name="1390"><span class="lineNum">    1390 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_0_entry_tailSlot_tarStat &lt;=</span></a>
+<a name="1391"><span class="lineNum">    1391 </span><span class="lineCov">       4160 :         _ftb_io_r_resp_data_0_entry_tailSlot_tarStat;</span></a>
+<a name="1392"><span class="lineNum">    1392 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_0_entry_tailSlot_sharing &lt;=</span></a>
+<a name="1393"><span class="lineNum">    1393 </span><span class="lineCov">       4160 :         _ftb_io_r_resp_data_0_entry_tailSlot_sharing;</span></a>
+<a name="1394"><span class="lineNum">    1394 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_0_entry_tailSlot_valid &lt;=</span></a>
+<a name="1395"><span class="lineNum">    1395 </span><span class="lineCov">       4160 :         _ftb_io_r_resp_data_0_entry_tailSlot_valid;</span></a>
+<a name="1396"><span class="lineNum">    1396 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_0_entry_pftAddr &lt;= _ftb_io_r_resp_data_0_entry_pftAddr;</span></a>
+<a name="1397"><span class="lineNum">    1397 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_0_entry_carry &lt;= _ftb_io_r_resp_data_0_entry_carry;</span></a>
+<a name="1398"><span class="lineNum">    1398 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_0_entry_isCall &lt;= _ftb_io_r_resp_data_0_entry_isCall;</span></a>
+<a name="1399"><span class="lineNum">    1399 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_0_entry_isRet &lt;= _ftb_io_r_resp_data_0_entry_isRet;</span></a>
+<a name="1400"><span class="lineNum">    1400 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_0_entry_isJalr &lt;= _ftb_io_r_resp_data_0_entry_isJalr;</span></a>
+<a name="1401"><span class="lineNum">    1401 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_0_entry_last_may_be_rvi_call &lt;=</span></a>
+<a name="1402"><span class="lineNum">    1402 </span><span class="lineCov">       4160 :         _ftb_io_r_resp_data_0_entry_last_may_be_rvi_call;</span></a>
+<a name="1403"><span class="lineNum">    1403 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_0_entry_always_taken_0 &lt;=</span></a>
+<a name="1404"><span class="lineNum">    1404 </span><span class="lineCov">       4160 :         _ftb_io_r_resp_data_0_entry_always_taken_0;</span></a>
+<a name="1405"><span class="lineNum">    1405 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_0_entry_always_taken_1 &lt;=</span></a>
+<a name="1406"><span class="lineNum">    1406 </span><span class="lineCov">       4160 :         _ftb_io_r_resp_data_0_entry_always_taken_1;</span></a>
+<a name="1407"><span class="lineNum">    1407 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_0_tag &lt;= _ftb_io_r_resp_data_0_tag;</span></a>
+<a name="1408"><span class="lineNum">    1408 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_1_entry_valid &lt;= _ftb_io_r_resp_data_1_entry_valid;</span></a>
+<a name="1409"><span class="lineNum">    1409 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_1_entry_brSlots_0_offset &lt;=</span></a>
+<a name="1410"><span class="lineNum">    1410 </span><span class="lineCov">       4160 :         _ftb_io_r_resp_data_1_entry_brSlots_0_offset;</span></a>
+<a name="1411"><span class="lineNum">    1411 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_1_entry_brSlots_0_lower &lt;=</span></a>
+<a name="1412"><span class="lineNum">    1412 </span><span class="lineCov">       4160 :         _ftb_io_r_resp_data_1_entry_brSlots_0_lower;</span></a>
+<a name="1413"><span class="lineNum">    1413 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_1_entry_brSlots_0_tarStat &lt;=</span></a>
+<a name="1414"><span class="lineNum">    1414 </span><span class="lineCov">       4160 :         _ftb_io_r_resp_data_1_entry_brSlots_0_tarStat;</span></a>
+<a name="1415"><span class="lineNum">    1415 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_1_entry_brSlots_0_sharing &lt;=</span></a>
+<a name="1416"><span class="lineNum">    1416 </span><span class="lineCov">       4160 :         _ftb_io_r_resp_data_1_entry_brSlots_0_sharing;</span></a>
+<a name="1417"><span class="lineNum">    1417 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_1_entry_brSlots_0_valid &lt;=</span></a>
+<a name="1418"><span class="lineNum">    1418 </span><span class="lineCov">       4160 :         _ftb_io_r_resp_data_1_entry_brSlots_0_valid;</span></a>
+<a name="1419"><span class="lineNum">    1419 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_1_entry_tailSlot_offset &lt;=</span></a>
+<a name="1420"><span class="lineNum">    1420 </span><span class="lineCov">       4160 :         _ftb_io_r_resp_data_1_entry_tailSlot_offset;</span></a>
+<a name="1421"><span class="lineNum">    1421 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_1_entry_tailSlot_lower &lt;=</span></a>
+<a name="1422"><span class="lineNum">    1422 </span><span class="lineCov">       4160 :         _ftb_io_r_resp_data_1_entry_tailSlot_lower;</span></a>
+<a name="1423"><span class="lineNum">    1423 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_1_entry_tailSlot_tarStat &lt;=</span></a>
+<a name="1424"><span class="lineNum">    1424 </span><span class="lineCov">       4160 :         _ftb_io_r_resp_data_1_entry_tailSlot_tarStat;</span></a>
+<a name="1425"><span class="lineNum">    1425 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_1_entry_tailSlot_sharing &lt;=</span></a>
+<a name="1426"><span class="lineNum">    1426 </span><span class="lineCov">       4160 :         _ftb_io_r_resp_data_1_entry_tailSlot_sharing;</span></a>
+<a name="1427"><span class="lineNum">    1427 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_1_entry_tailSlot_valid &lt;=</span></a>
+<a name="1428"><span class="lineNum">    1428 </span><span class="lineCov">       4160 :         _ftb_io_r_resp_data_1_entry_tailSlot_valid;</span></a>
+<a name="1429"><span class="lineNum">    1429 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_1_entry_pftAddr &lt;= _ftb_io_r_resp_data_1_entry_pftAddr;</span></a>
+<a name="1430"><span class="lineNum">    1430 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_1_entry_carry &lt;= _ftb_io_r_resp_data_1_entry_carry;</span></a>
+<a name="1431"><span class="lineNum">    1431 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_1_entry_isCall &lt;= _ftb_io_r_resp_data_1_entry_isCall;</span></a>
+<a name="1432"><span class="lineNum">    1432 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_1_entry_isRet &lt;= _ftb_io_r_resp_data_1_entry_isRet;</span></a>
+<a name="1433"><span class="lineNum">    1433 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_1_entry_isJalr &lt;= _ftb_io_r_resp_data_1_entry_isJalr;</span></a>
+<a name="1434"><span class="lineNum">    1434 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_1_entry_last_may_be_rvi_call &lt;=</span></a>
+<a name="1435"><span class="lineNum">    1435 </span><span class="lineCov">       4160 :         _ftb_io_r_resp_data_1_entry_last_may_be_rvi_call;</span></a>
+<a name="1436"><span class="lineNum">    1436 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_1_entry_always_taken_0 &lt;=</span></a>
+<a name="1437"><span class="lineNum">    1437 </span><span class="lineCov">       4160 :         _ftb_io_r_resp_data_1_entry_always_taken_0;</span></a>
+<a name="1438"><span class="lineNum">    1438 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_1_entry_always_taken_1 &lt;=</span></a>
+<a name="1439"><span class="lineNum">    1439 </span><span class="lineCov">       4160 :         _ftb_io_r_resp_data_1_entry_always_taken_1;</span></a>
+<a name="1440"><span class="lineNum">    1440 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_1_tag &lt;= _ftb_io_r_resp_data_1_tag;</span></a>
+<a name="1441"><span class="lineNum">    1441 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_2_entry_valid &lt;= _ftb_io_r_resp_data_2_entry_valid;</span></a>
+<a name="1442"><span class="lineNum">    1442 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_2_entry_brSlots_0_offset &lt;=</span></a>
+<a name="1443"><span class="lineNum">    1443 </span><span class="lineCov">       4160 :         _ftb_io_r_resp_data_2_entry_brSlots_0_offset;</span></a>
+<a name="1444"><span class="lineNum">    1444 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_2_entry_brSlots_0_lower &lt;=</span></a>
+<a name="1445"><span class="lineNum">    1445 </span><span class="lineCov">       4160 :         _ftb_io_r_resp_data_2_entry_brSlots_0_lower;</span></a>
+<a name="1446"><span class="lineNum">    1446 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_2_entry_brSlots_0_tarStat &lt;=</span></a>
+<a name="1447"><span class="lineNum">    1447 </span><span class="lineCov">       4160 :         _ftb_io_r_resp_data_2_entry_brSlots_0_tarStat;</span></a>
+<a name="1448"><span class="lineNum">    1448 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_2_entry_brSlots_0_sharing &lt;=</span></a>
+<a name="1449"><span class="lineNum">    1449 </span><span class="lineCov">       4160 :         _ftb_io_r_resp_data_2_entry_brSlots_0_sharing;</span></a>
+<a name="1450"><span class="lineNum">    1450 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_2_entry_brSlots_0_valid &lt;=</span></a>
+<a name="1451"><span class="lineNum">    1451 </span><span class="lineCov">       4160 :         _ftb_io_r_resp_data_2_entry_brSlots_0_valid;</span></a>
+<a name="1452"><span class="lineNum">    1452 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_2_entry_tailSlot_offset &lt;=</span></a>
+<a name="1453"><span class="lineNum">    1453 </span><span class="lineCov">       4160 :         _ftb_io_r_resp_data_2_entry_tailSlot_offset;</span></a>
+<a name="1454"><span class="lineNum">    1454 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_2_entry_tailSlot_lower &lt;=</span></a>
+<a name="1455"><span class="lineNum">    1455 </span><span class="lineCov">       4160 :         _ftb_io_r_resp_data_2_entry_tailSlot_lower;</span></a>
+<a name="1456"><span class="lineNum">    1456 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_2_entry_tailSlot_tarStat &lt;=</span></a>
+<a name="1457"><span class="lineNum">    1457 </span><span class="lineCov">       4160 :         _ftb_io_r_resp_data_2_entry_tailSlot_tarStat;</span></a>
+<a name="1458"><span class="lineNum">    1458 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_2_entry_tailSlot_sharing &lt;=</span></a>
+<a name="1459"><span class="lineNum">    1459 </span><span class="lineCov">       4160 :         _ftb_io_r_resp_data_2_entry_tailSlot_sharing;</span></a>
+<a name="1460"><span class="lineNum">    1460 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_2_entry_tailSlot_valid &lt;=</span></a>
+<a name="1461"><span class="lineNum">    1461 </span><span class="lineCov">       4160 :         _ftb_io_r_resp_data_2_entry_tailSlot_valid;</span></a>
+<a name="1462"><span class="lineNum">    1462 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_2_entry_pftAddr &lt;= _ftb_io_r_resp_data_2_entry_pftAddr;</span></a>
+<a name="1463"><span class="lineNum">    1463 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_2_entry_carry &lt;= _ftb_io_r_resp_data_2_entry_carry;</span></a>
+<a name="1464"><span class="lineNum">    1464 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_2_entry_isCall &lt;= _ftb_io_r_resp_data_2_entry_isCall;</span></a>
+<a name="1465"><span class="lineNum">    1465 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_2_entry_isRet &lt;= _ftb_io_r_resp_data_2_entry_isRet;</span></a>
+<a name="1466"><span class="lineNum">    1466 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_2_entry_isJalr &lt;= _ftb_io_r_resp_data_2_entry_isJalr;</span></a>
+<a name="1467"><span class="lineNum">    1467 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_2_entry_last_may_be_rvi_call &lt;=</span></a>
+<a name="1468"><span class="lineNum">    1468 </span><span class="lineCov">       4160 :         _ftb_io_r_resp_data_2_entry_last_may_be_rvi_call;</span></a>
+<a name="1469"><span class="lineNum">    1469 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_2_entry_always_taken_0 &lt;=</span></a>
+<a name="1470"><span class="lineNum">    1470 </span><span class="lineCov">       4160 :         _ftb_io_r_resp_data_2_entry_always_taken_0;</span></a>
+<a name="1471"><span class="lineNum">    1471 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_2_entry_always_taken_1 &lt;=</span></a>
+<a name="1472"><span class="lineNum">    1472 </span><span class="lineCov">       4160 :         _ftb_io_r_resp_data_2_entry_always_taken_1;</span></a>
+<a name="1473"><span class="lineNum">    1473 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_2_tag &lt;= _ftb_io_r_resp_data_2_tag;</span></a>
+<a name="1474"><span class="lineNum">    1474 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_3_entry_valid &lt;= _ftb_io_r_resp_data_3_entry_valid;</span></a>
+<a name="1475"><span class="lineNum">    1475 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_3_entry_brSlots_0_offset &lt;=</span></a>
+<a name="1476"><span class="lineNum">    1476 </span><span class="lineCov">       4160 :         _ftb_io_r_resp_data_3_entry_brSlots_0_offset;</span></a>
+<a name="1477"><span class="lineNum">    1477 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_3_entry_brSlots_0_lower &lt;=</span></a>
+<a name="1478"><span class="lineNum">    1478 </span><span class="lineCov">       4160 :         _ftb_io_r_resp_data_3_entry_brSlots_0_lower;</span></a>
+<a name="1479"><span class="lineNum">    1479 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_3_entry_brSlots_0_tarStat &lt;=</span></a>
+<a name="1480"><span class="lineNum">    1480 </span><span class="lineCov">       4160 :         _ftb_io_r_resp_data_3_entry_brSlots_0_tarStat;</span></a>
+<a name="1481"><span class="lineNum">    1481 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_3_entry_brSlots_0_sharing &lt;=</span></a>
+<a name="1482"><span class="lineNum">    1482 </span><span class="lineCov">       4160 :         _ftb_io_r_resp_data_3_entry_brSlots_0_sharing;</span></a>
+<a name="1483"><span class="lineNum">    1483 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_3_entry_brSlots_0_valid &lt;=</span></a>
+<a name="1484"><span class="lineNum">    1484 </span><span class="lineCov">       4160 :         _ftb_io_r_resp_data_3_entry_brSlots_0_valid;</span></a>
+<a name="1485"><span class="lineNum">    1485 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_3_entry_tailSlot_offset &lt;=</span></a>
+<a name="1486"><span class="lineNum">    1486 </span><span class="lineCov">       4160 :         _ftb_io_r_resp_data_3_entry_tailSlot_offset;</span></a>
+<a name="1487"><span class="lineNum">    1487 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_3_entry_tailSlot_lower &lt;=</span></a>
+<a name="1488"><span class="lineNum">    1488 </span><span class="lineCov">       4160 :         _ftb_io_r_resp_data_3_entry_tailSlot_lower;</span></a>
+<a name="1489"><span class="lineNum">    1489 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_3_entry_tailSlot_tarStat &lt;=</span></a>
+<a name="1490"><span class="lineNum">    1490 </span><span class="lineCov">       4160 :         _ftb_io_r_resp_data_3_entry_tailSlot_tarStat;</span></a>
+<a name="1491"><span class="lineNum">    1491 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_3_entry_tailSlot_sharing &lt;=</span></a>
+<a name="1492"><span class="lineNum">    1492 </span><span class="lineCov">       4160 :         _ftb_io_r_resp_data_3_entry_tailSlot_sharing;</span></a>
+<a name="1493"><span class="lineNum">    1493 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_3_entry_tailSlot_valid &lt;=</span></a>
+<a name="1494"><span class="lineNum">    1494 </span><span class="lineCov">       4160 :         _ftb_io_r_resp_data_3_entry_tailSlot_valid;</span></a>
+<a name="1495"><span class="lineNum">    1495 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_3_entry_pftAddr &lt;= _ftb_io_r_resp_data_3_entry_pftAddr;</span></a>
+<a name="1496"><span class="lineNum">    1496 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_3_entry_carry &lt;= _ftb_io_r_resp_data_3_entry_carry;</span></a>
+<a name="1497"><span class="lineNum">    1497 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_3_entry_isCall &lt;= _ftb_io_r_resp_data_3_entry_isCall;</span></a>
+<a name="1498"><span class="lineNum">    1498 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_3_entry_isRet &lt;= _ftb_io_r_resp_data_3_entry_isRet;</span></a>
+<a name="1499"><span class="lineNum">    1499 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_3_entry_isJalr &lt;= _ftb_io_r_resp_data_3_entry_isJalr;</span></a>
+<a name="1500"><span class="lineNum">    1500 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_3_entry_last_may_be_rvi_call &lt;=</span></a>
+<a name="1501"><span class="lineNum">    1501 </span><span class="lineCov">       4160 :         _ftb_io_r_resp_data_3_entry_last_may_be_rvi_call;</span></a>
+<a name="1502"><span class="lineNum">    1502 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_3_entry_always_taken_0 &lt;=</span></a>
+<a name="1503"><span class="lineNum">    1503 </span><span class="lineCov">       4160 :         _ftb_io_r_resp_data_3_entry_always_taken_0;</span></a>
+<a name="1504"><span class="lineNum">    1504 </span><span class="lineCov">       4160 :       pred_rdata_hold_data_3_entry_always_taken_1 &lt;=</span></a>
+<a name="1505"><span class="lineNum">    1505 </span><span class="lineCov">       4160 :         _ftb_io_r_resp_data_3_entry_always_taken_1;</span></a>
+<a name="1506"><span class="lineNum">    1506 </span>            :       pred_rdata_hold_data_3_tag &lt;= _ftb_io_r_resp_data_3_tag;</a>
+<a name="1507"><span class="lineNum">    1507 </span><span class="lineCov">       8350 :     end</span></a>
+<a name="1508"><span class="lineNum">    1508 </span><span class="lineCov">       4175 :     if (io_req_pc_valid) begin</span></a>
+<a name="1509"><span class="lineNum">    1509 </span><span class="lineCov">       4175 :       req_tag &lt;= io_req_pc_bits[29:10];</span></a>
+<a name="1510"><span class="lineNum">    1510 </span>            :       req_idx &lt;= io_req_pc_bits[9:1];</a>
+<a name="1511"><span class="lineNum">    1511 </span><span class="lineCov">         38 :     end</span></a>
+<a name="1512"><span class="lineNum">    1512 </span><span class="lineCov">         19 :     if (io_u_req_pc_valid)</span></a>
+<a name="1513"><span class="lineNum">    1513 </span><span class="lineCov">      63847 :       u_req_tag &lt;= io_u_req_pc_bits[29:10];</span></a>
+<a name="1514"><span class="lineNum">    1514 </span><span class="lineCov">      63847 :     u_total_hits_REG &lt;= io_update_access;</span></a>
+<a name="1515"><span class="lineNum">    1515 </span><span class="lineCov">      63847 :     u_total_hits_REG_1 &lt;= io_update_access;</span></a>
+<a name="1516"><span class="lineNum">    1516 </span><span class="lineCov">      63847 :     u_total_hits_REG_2 &lt;= io_update_access;</span></a>
+<a name="1517"><span class="lineNum">    1517 </span><span class="lineCov">      63847 :     u_total_hits_REG_3 &lt;= io_update_access;</span></a>
+<a name="1518"><span class="lineNum">    1518 </span><span class="lineCov">      63847 :     touch_set_0_REG &lt;= req_idx;</span></a>
+<a name="1519"><span class="lineNum">    1519 </span><span class="lineCov">      63847 :     touch_way_0_valid_REG &lt;= hit;</span></a>
+<a name="1520"><span class="lineNum">    1520 </span><span class="lineCov">      63847 :     touch_way_0_bits_REG &lt;= hit_way;</span></a>
+<a name="1521"><span class="lineNum">    1521 </span><span class="lineCov">      63847 :     allocWriteWay_REG_0 &lt;= _ftb_io_r_resp_data_0_entry_valid;</span></a>
+<a name="1522"><span class="lineNum">    1522 </span><span class="lineCov">      63847 :     allocWriteWay_REG_1 &lt;= _ftb_io_r_resp_data_1_entry_valid;</span></a>
+<a name="1523"><span class="lineNum">    1523 </span><span class="lineCov">      63847 :     allocWriteWay_REG_2 &lt;= _ftb_io_r_resp_data_2_entry_valid;</span></a>
+<a name="1524"><span class="lineNum">    1524 </span>            :     allocWriteWay_REG_3 &lt;= _ftb_io_r_resp_data_3_entry_valid;</a>
+<a name="1525"><span class="lineNum">    1525 </span><span class="lineCov">       8514 :   end // always @(posedge)</span></a>
+<a name="1526"><span class="lineNum">    1526 </span>            :   wire [8:0]        touch_set_0 =</a>
+<a name="1527"><span class="lineNum">    1527 </span><span class="lineCov">         77 :     io_update_write_data_valid ? io_update_pc[9:1] : touch_set_0_REG;</span></a>
+<a name="1528"><span class="lineNum">    1528 </span>            :   wire              touch_way_0_valid =</a>
+<a name="1529"><span class="lineNum">    1529 </span><span class="lineCov">         71 :     io_update_write_data_valid | touch_way_0_valid_REG;</span></a>
+<a name="1530"><span class="lineNum">    1530 </span>            :   wire [1:0]        touch_way_0_bits =</a>
+<a name="1531"><span class="lineNum">    1531 </span><span class="lineCov">     127730 :     io_update_write_data_valid ? u_way : touch_way_0_bits_REG;</span></a>
+<a name="1532"><span class="lineNum">    1532 </span><span class="lineCov">        272 :   always @(posedge clock or posedge reset) begin</span></a>
+<a name="1533"><span class="lineNum">    1533 </span><span class="lineCov">        136 :     if (reset) begin</span></a>
+<a name="1534"><span class="lineNum">    1534 </span><span class="lineCov">        136 :       state_vec_0 &lt;= 3'h0;</span></a>
+<a name="1535"><span class="lineNum">    1535 </span><span class="lineCov">        136 :       state_vec_1 &lt;= 3'h0;</span></a>
+<a name="1536"><span class="lineNum">    1536 </span><span class="lineCov">        136 :       state_vec_2 &lt;= 3'h0;</span></a>
+<a name="1537"><span class="lineNum">    1537 </span><span class="lineCov">        136 :       state_vec_3 &lt;= 3'h0;</span></a>
+<a name="1538"><span class="lineNum">    1538 </span><span class="lineCov">        136 :       state_vec_4 &lt;= 3'h0;</span></a>
+<a name="1539"><span class="lineNum">    1539 </span><span class="lineCov">        136 :       state_vec_5 &lt;= 3'h0;</span></a>
+<a name="1540"><span class="lineNum">    1540 </span><span class="lineCov">        136 :       state_vec_6 &lt;= 3'h0;</span></a>
+<a name="1541"><span class="lineNum">    1541 </span><span class="lineCov">        136 :       state_vec_7 &lt;= 3'h0;</span></a>
+<a name="1542"><span class="lineNum">    1542 </span><span class="lineCov">        136 :       state_vec_8 &lt;= 3'h0;</span></a>
+<a name="1543"><span class="lineNum">    1543 </span><span class="lineCov">        136 :       state_vec_9 &lt;= 3'h0;</span></a>
+<a name="1544"><span class="lineNum">    1544 </span><span class="lineCov">        136 :       state_vec_10 &lt;= 3'h0;</span></a>
+<a name="1545"><span class="lineNum">    1545 </span><span class="lineCov">        136 :       state_vec_11 &lt;= 3'h0;</span></a>
+<a name="1546"><span class="lineNum">    1546 </span><span class="lineCov">        136 :       state_vec_12 &lt;= 3'h0;</span></a>
+<a name="1547"><span class="lineNum">    1547 </span><span class="lineCov">        136 :       state_vec_13 &lt;= 3'h0;</span></a>
+<a name="1548"><span class="lineNum">    1548 </span><span class="lineCov">        136 :       state_vec_14 &lt;= 3'h0;</span></a>
+<a name="1549"><span class="lineNum">    1549 </span><span class="lineCov">        136 :       state_vec_15 &lt;= 3'h0;</span></a>
+<a name="1550"><span class="lineNum">    1550 </span><span class="lineCov">        136 :       state_vec_16 &lt;= 3'h0;</span></a>
+<a name="1551"><span class="lineNum">    1551 </span><span class="lineCov">        136 :       state_vec_17 &lt;= 3'h0;</span></a>
+<a name="1552"><span class="lineNum">    1552 </span><span class="lineCov">        136 :       state_vec_18 &lt;= 3'h0;</span></a>
+<a name="1553"><span class="lineNum">    1553 </span><span class="lineCov">        136 :       state_vec_19 &lt;= 3'h0;</span></a>
+<a name="1554"><span class="lineNum">    1554 </span><span class="lineCov">        136 :       state_vec_20 &lt;= 3'h0;</span></a>
+<a name="1555"><span class="lineNum">    1555 </span><span class="lineCov">        136 :       state_vec_21 &lt;= 3'h0;</span></a>
+<a name="1556"><span class="lineNum">    1556 </span><span class="lineCov">        136 :       state_vec_22 &lt;= 3'h0;</span></a>
+<a name="1557"><span class="lineNum">    1557 </span><span class="lineCov">        136 :       state_vec_23 &lt;= 3'h0;</span></a>
+<a name="1558"><span class="lineNum">    1558 </span><span class="lineCov">        136 :       state_vec_24 &lt;= 3'h0;</span></a>
+<a name="1559"><span class="lineNum">    1559 </span><span class="lineCov">        136 :       state_vec_25 &lt;= 3'h0;</span></a>
+<a name="1560"><span class="lineNum">    1560 </span><span class="lineCov">        136 :       state_vec_26 &lt;= 3'h0;</span></a>
+<a name="1561"><span class="lineNum">    1561 </span><span class="lineCov">        136 :       state_vec_27 &lt;= 3'h0;</span></a>
+<a name="1562"><span class="lineNum">    1562 </span><span class="lineCov">        136 :       state_vec_28 &lt;= 3'h0;</span></a>
+<a name="1563"><span class="lineNum">    1563 </span><span class="lineCov">        136 :       state_vec_29 &lt;= 3'h0;</span></a>
+<a name="1564"><span class="lineNum">    1564 </span><span class="lineCov">        136 :       state_vec_30 &lt;= 3'h0;</span></a>
+<a name="1565"><span class="lineNum">    1565 </span><span class="lineCov">        136 :       state_vec_31 &lt;= 3'h0;</span></a>
+<a name="1566"><span class="lineNum">    1566 </span><span class="lineCov">        136 :       state_vec_32 &lt;= 3'h0;</span></a>
+<a name="1567"><span class="lineNum">    1567 </span><span class="lineCov">        136 :       state_vec_33 &lt;= 3'h0;</span></a>
+<a name="1568"><span class="lineNum">    1568 </span><span class="lineCov">        136 :       state_vec_34 &lt;= 3'h0;</span></a>
+<a name="1569"><span class="lineNum">    1569 </span><span class="lineCov">        136 :       state_vec_35 &lt;= 3'h0;</span></a>
+<a name="1570"><span class="lineNum">    1570 </span><span class="lineCov">        136 :       state_vec_36 &lt;= 3'h0;</span></a>
+<a name="1571"><span class="lineNum">    1571 </span><span class="lineCov">        136 :       state_vec_37 &lt;= 3'h0;</span></a>
+<a name="1572"><span class="lineNum">    1572 </span><span class="lineCov">        136 :       state_vec_38 &lt;= 3'h0;</span></a>
+<a name="1573"><span class="lineNum">    1573 </span><span class="lineCov">        136 :       state_vec_39 &lt;= 3'h0;</span></a>
+<a name="1574"><span class="lineNum">    1574 </span><span class="lineCov">        136 :       state_vec_40 &lt;= 3'h0;</span></a>
+<a name="1575"><span class="lineNum">    1575 </span><span class="lineCov">        136 :       state_vec_41 &lt;= 3'h0;</span></a>
+<a name="1576"><span class="lineNum">    1576 </span><span class="lineCov">        136 :       state_vec_42 &lt;= 3'h0;</span></a>
+<a name="1577"><span class="lineNum">    1577 </span><span class="lineCov">        136 :       state_vec_43 &lt;= 3'h0;</span></a>
+<a name="1578"><span class="lineNum">    1578 </span><span class="lineCov">        136 :       state_vec_44 &lt;= 3'h0;</span></a>
+<a name="1579"><span class="lineNum">    1579 </span><span class="lineCov">        136 :       state_vec_45 &lt;= 3'h0;</span></a>
+<a name="1580"><span class="lineNum">    1580 </span><span class="lineCov">        136 :       state_vec_46 &lt;= 3'h0;</span></a>
+<a name="1581"><span class="lineNum">    1581 </span><span class="lineCov">        136 :       state_vec_47 &lt;= 3'h0;</span></a>
+<a name="1582"><span class="lineNum">    1582 </span><span class="lineCov">        136 :       state_vec_48 &lt;= 3'h0;</span></a>
+<a name="1583"><span class="lineNum">    1583 </span><span class="lineCov">        136 :       state_vec_49 &lt;= 3'h0;</span></a>
+<a name="1584"><span class="lineNum">    1584 </span><span class="lineCov">        136 :       state_vec_50 &lt;= 3'h0;</span></a>
+<a name="1585"><span class="lineNum">    1585 </span><span class="lineCov">        136 :       state_vec_51 &lt;= 3'h0;</span></a>
+<a name="1586"><span class="lineNum">    1586 </span><span class="lineCov">        136 :       state_vec_52 &lt;= 3'h0;</span></a>
+<a name="1587"><span class="lineNum">    1587 </span><span class="lineCov">        136 :       state_vec_53 &lt;= 3'h0;</span></a>
+<a name="1588"><span class="lineNum">    1588 </span><span class="lineCov">        136 :       state_vec_54 &lt;= 3'h0;</span></a>
+<a name="1589"><span class="lineNum">    1589 </span><span class="lineCov">        136 :       state_vec_55 &lt;= 3'h0;</span></a>
+<a name="1590"><span class="lineNum">    1590 </span><span class="lineCov">        136 :       state_vec_56 &lt;= 3'h0;</span></a>
+<a name="1591"><span class="lineNum">    1591 </span><span class="lineCov">        136 :       state_vec_57 &lt;= 3'h0;</span></a>
+<a name="1592"><span class="lineNum">    1592 </span><span class="lineCov">        136 :       state_vec_58 &lt;= 3'h0;</span></a>
+<a name="1593"><span class="lineNum">    1593 </span><span class="lineCov">        136 :       state_vec_59 &lt;= 3'h0;</span></a>
+<a name="1594"><span class="lineNum">    1594 </span><span class="lineCov">        136 :       state_vec_60 &lt;= 3'h0;</span></a>
+<a name="1595"><span class="lineNum">    1595 </span><span class="lineCov">        136 :       state_vec_61 &lt;= 3'h0;</span></a>
+<a name="1596"><span class="lineNum">    1596 </span><span class="lineCov">        136 :       state_vec_62 &lt;= 3'h0;</span></a>
+<a name="1597"><span class="lineNum">    1597 </span><span class="lineCov">        136 :       state_vec_63 &lt;= 3'h0;</span></a>
+<a name="1598"><span class="lineNum">    1598 </span><span class="lineCov">        136 :       state_vec_64 &lt;= 3'h0;</span></a>
+<a name="1599"><span class="lineNum">    1599 </span><span class="lineCov">        136 :       state_vec_65 &lt;= 3'h0;</span></a>
+<a name="1600"><span class="lineNum">    1600 </span><span class="lineCov">        136 :       state_vec_66 &lt;= 3'h0;</span></a>
+<a name="1601"><span class="lineNum">    1601 </span><span class="lineCov">        136 :       state_vec_67 &lt;= 3'h0;</span></a>
+<a name="1602"><span class="lineNum">    1602 </span><span class="lineCov">        136 :       state_vec_68 &lt;= 3'h0;</span></a>
+<a name="1603"><span class="lineNum">    1603 </span><span class="lineCov">        136 :       state_vec_69 &lt;= 3'h0;</span></a>
+<a name="1604"><span class="lineNum">    1604 </span><span class="lineCov">        136 :       state_vec_70 &lt;= 3'h0;</span></a>
+<a name="1605"><span class="lineNum">    1605 </span><span class="lineCov">        136 :       state_vec_71 &lt;= 3'h0;</span></a>
+<a name="1606"><span class="lineNum">    1606 </span><span class="lineCov">        136 :       state_vec_72 &lt;= 3'h0;</span></a>
+<a name="1607"><span class="lineNum">    1607 </span><span class="lineCov">        136 :       state_vec_73 &lt;= 3'h0;</span></a>
+<a name="1608"><span class="lineNum">    1608 </span><span class="lineCov">        136 :       state_vec_74 &lt;= 3'h0;</span></a>
+<a name="1609"><span class="lineNum">    1609 </span><span class="lineCov">        136 :       state_vec_75 &lt;= 3'h0;</span></a>
+<a name="1610"><span class="lineNum">    1610 </span><span class="lineCov">        136 :       state_vec_76 &lt;= 3'h0;</span></a>
+<a name="1611"><span class="lineNum">    1611 </span><span class="lineCov">        136 :       state_vec_77 &lt;= 3'h0;</span></a>
+<a name="1612"><span class="lineNum">    1612 </span><span class="lineCov">        136 :       state_vec_78 &lt;= 3'h0;</span></a>
+<a name="1613"><span class="lineNum">    1613 </span><span class="lineCov">        136 :       state_vec_79 &lt;= 3'h0;</span></a>
+<a name="1614"><span class="lineNum">    1614 </span><span class="lineCov">        136 :       state_vec_80 &lt;= 3'h0;</span></a>
+<a name="1615"><span class="lineNum">    1615 </span><span class="lineCov">        136 :       state_vec_81 &lt;= 3'h0;</span></a>
+<a name="1616"><span class="lineNum">    1616 </span><span class="lineCov">        136 :       state_vec_82 &lt;= 3'h0;</span></a>
+<a name="1617"><span class="lineNum">    1617 </span><span class="lineCov">        136 :       state_vec_83 &lt;= 3'h0;</span></a>
+<a name="1618"><span class="lineNum">    1618 </span><span class="lineCov">        136 :       state_vec_84 &lt;= 3'h0;</span></a>
+<a name="1619"><span class="lineNum">    1619 </span><span class="lineCov">        136 :       state_vec_85 &lt;= 3'h0;</span></a>
+<a name="1620"><span class="lineNum">    1620 </span><span class="lineCov">        136 :       state_vec_86 &lt;= 3'h0;</span></a>
+<a name="1621"><span class="lineNum">    1621 </span><span class="lineCov">        136 :       state_vec_87 &lt;= 3'h0;</span></a>
+<a name="1622"><span class="lineNum">    1622 </span><span class="lineCov">        136 :       state_vec_88 &lt;= 3'h0;</span></a>
+<a name="1623"><span class="lineNum">    1623 </span><span class="lineCov">        136 :       state_vec_89 &lt;= 3'h0;</span></a>
+<a name="1624"><span class="lineNum">    1624 </span><span class="lineCov">        136 :       state_vec_90 &lt;= 3'h0;</span></a>
+<a name="1625"><span class="lineNum">    1625 </span><span class="lineCov">        136 :       state_vec_91 &lt;= 3'h0;</span></a>
+<a name="1626"><span class="lineNum">    1626 </span><span class="lineCov">        136 :       state_vec_92 &lt;= 3'h0;</span></a>
+<a name="1627"><span class="lineNum">    1627 </span><span class="lineCov">        136 :       state_vec_93 &lt;= 3'h0;</span></a>
+<a name="1628"><span class="lineNum">    1628 </span><span class="lineCov">        136 :       state_vec_94 &lt;= 3'h0;</span></a>
+<a name="1629"><span class="lineNum">    1629 </span><span class="lineCov">        136 :       state_vec_95 &lt;= 3'h0;</span></a>
+<a name="1630"><span class="lineNum">    1630 </span><span class="lineCov">        136 :       state_vec_96 &lt;= 3'h0;</span></a>
+<a name="1631"><span class="lineNum">    1631 </span><span class="lineCov">        136 :       state_vec_97 &lt;= 3'h0;</span></a>
+<a name="1632"><span class="lineNum">    1632 </span><span class="lineCov">        136 :       state_vec_98 &lt;= 3'h0;</span></a>
+<a name="1633"><span class="lineNum">    1633 </span><span class="lineCov">        136 :       state_vec_99 &lt;= 3'h0;</span></a>
+<a name="1634"><span class="lineNum">    1634 </span><span class="lineCov">        136 :       state_vec_100 &lt;= 3'h0;</span></a>
+<a name="1635"><span class="lineNum">    1635 </span><span class="lineCov">        136 :       state_vec_101 &lt;= 3'h0;</span></a>
+<a name="1636"><span class="lineNum">    1636 </span><span class="lineCov">        136 :       state_vec_102 &lt;= 3'h0;</span></a>
+<a name="1637"><span class="lineNum">    1637 </span><span class="lineCov">        136 :       state_vec_103 &lt;= 3'h0;</span></a>
+<a name="1638"><span class="lineNum">    1638 </span><span class="lineCov">        136 :       state_vec_104 &lt;= 3'h0;</span></a>
+<a name="1639"><span class="lineNum">    1639 </span><span class="lineCov">        136 :       state_vec_105 &lt;= 3'h0;</span></a>
+<a name="1640"><span class="lineNum">    1640 </span><span class="lineCov">        136 :       state_vec_106 &lt;= 3'h0;</span></a>
+<a name="1641"><span class="lineNum">    1641 </span><span class="lineCov">        136 :       state_vec_107 &lt;= 3'h0;</span></a>
+<a name="1642"><span class="lineNum">    1642 </span><span class="lineCov">        136 :       state_vec_108 &lt;= 3'h0;</span></a>
+<a name="1643"><span class="lineNum">    1643 </span><span class="lineCov">        136 :       state_vec_109 &lt;= 3'h0;</span></a>
+<a name="1644"><span class="lineNum">    1644 </span><span class="lineCov">        136 :       state_vec_110 &lt;= 3'h0;</span></a>
+<a name="1645"><span class="lineNum">    1645 </span><span class="lineCov">        136 :       state_vec_111 &lt;= 3'h0;</span></a>
+<a name="1646"><span class="lineNum">    1646 </span><span class="lineCov">        136 :       state_vec_112 &lt;= 3'h0;</span></a>
+<a name="1647"><span class="lineNum">    1647 </span><span class="lineCov">        136 :       state_vec_113 &lt;= 3'h0;</span></a>
+<a name="1648"><span class="lineNum">    1648 </span><span class="lineCov">        136 :       state_vec_114 &lt;= 3'h0;</span></a>
+<a name="1649"><span class="lineNum">    1649 </span><span class="lineCov">        136 :       state_vec_115 &lt;= 3'h0;</span></a>
+<a name="1650"><span class="lineNum">    1650 </span><span class="lineCov">        136 :       state_vec_116 &lt;= 3'h0;</span></a>
+<a name="1651"><span class="lineNum">    1651 </span><span class="lineCov">        136 :       state_vec_117 &lt;= 3'h0;</span></a>
+<a name="1652"><span class="lineNum">    1652 </span><span class="lineCov">        136 :       state_vec_118 &lt;= 3'h0;</span></a>
+<a name="1653"><span class="lineNum">    1653 </span><span class="lineCov">        136 :       state_vec_119 &lt;= 3'h0;</span></a>
+<a name="1654"><span class="lineNum">    1654 </span><span class="lineCov">        136 :       state_vec_120 &lt;= 3'h0;</span></a>
+<a name="1655"><span class="lineNum">    1655 </span><span class="lineCov">        136 :       state_vec_121 &lt;= 3'h0;</span></a>
+<a name="1656"><span class="lineNum">    1656 </span><span class="lineCov">        136 :       state_vec_122 &lt;= 3'h0;</span></a>
+<a name="1657"><span class="lineNum">    1657 </span><span class="lineCov">        136 :       state_vec_123 &lt;= 3'h0;</span></a>
+<a name="1658"><span class="lineNum">    1658 </span><span class="lineCov">        136 :       state_vec_124 &lt;= 3'h0;</span></a>
+<a name="1659"><span class="lineNum">    1659 </span><span class="lineCov">        136 :       state_vec_125 &lt;= 3'h0;</span></a>
+<a name="1660"><span class="lineNum">    1660 </span><span class="lineCov">        136 :       state_vec_126 &lt;= 3'h0;</span></a>
+<a name="1661"><span class="lineNum">    1661 </span><span class="lineCov">        136 :       state_vec_127 &lt;= 3'h0;</span></a>
+<a name="1662"><span class="lineNum">    1662 </span><span class="lineCov">        136 :       state_vec_128 &lt;= 3'h0;</span></a>
+<a name="1663"><span class="lineNum">    1663 </span><span class="lineCov">        136 :       state_vec_129 &lt;= 3'h0;</span></a>
+<a name="1664"><span class="lineNum">    1664 </span><span class="lineCov">        136 :       state_vec_130 &lt;= 3'h0;</span></a>
+<a name="1665"><span class="lineNum">    1665 </span><span class="lineCov">        136 :       state_vec_131 &lt;= 3'h0;</span></a>
+<a name="1666"><span class="lineNum">    1666 </span><span class="lineCov">        136 :       state_vec_132 &lt;= 3'h0;</span></a>
+<a name="1667"><span class="lineNum">    1667 </span><span class="lineCov">        136 :       state_vec_133 &lt;= 3'h0;</span></a>
+<a name="1668"><span class="lineNum">    1668 </span><span class="lineCov">        136 :       state_vec_134 &lt;= 3'h0;</span></a>
+<a name="1669"><span class="lineNum">    1669 </span><span class="lineCov">        136 :       state_vec_135 &lt;= 3'h0;</span></a>
+<a name="1670"><span class="lineNum">    1670 </span><span class="lineCov">        136 :       state_vec_136 &lt;= 3'h0;</span></a>
+<a name="1671"><span class="lineNum">    1671 </span><span class="lineCov">        136 :       state_vec_137 &lt;= 3'h0;</span></a>
+<a name="1672"><span class="lineNum">    1672 </span><span class="lineCov">        136 :       state_vec_138 &lt;= 3'h0;</span></a>
+<a name="1673"><span class="lineNum">    1673 </span><span class="lineCov">        136 :       state_vec_139 &lt;= 3'h0;</span></a>
+<a name="1674"><span class="lineNum">    1674 </span><span class="lineCov">        136 :       state_vec_140 &lt;= 3'h0;</span></a>
+<a name="1675"><span class="lineNum">    1675 </span><span class="lineCov">        136 :       state_vec_141 &lt;= 3'h0;</span></a>
+<a name="1676"><span class="lineNum">    1676 </span><span class="lineCov">        136 :       state_vec_142 &lt;= 3'h0;</span></a>
+<a name="1677"><span class="lineNum">    1677 </span><span class="lineCov">        136 :       state_vec_143 &lt;= 3'h0;</span></a>
+<a name="1678"><span class="lineNum">    1678 </span><span class="lineCov">        136 :       state_vec_144 &lt;= 3'h0;</span></a>
+<a name="1679"><span class="lineNum">    1679 </span><span class="lineCov">        136 :       state_vec_145 &lt;= 3'h0;</span></a>
+<a name="1680"><span class="lineNum">    1680 </span><span class="lineCov">        136 :       state_vec_146 &lt;= 3'h0;</span></a>
+<a name="1681"><span class="lineNum">    1681 </span><span class="lineCov">        136 :       state_vec_147 &lt;= 3'h0;</span></a>
+<a name="1682"><span class="lineNum">    1682 </span><span class="lineCov">        136 :       state_vec_148 &lt;= 3'h0;</span></a>
+<a name="1683"><span class="lineNum">    1683 </span><span class="lineCov">        136 :       state_vec_149 &lt;= 3'h0;</span></a>
+<a name="1684"><span class="lineNum">    1684 </span><span class="lineCov">        136 :       state_vec_150 &lt;= 3'h0;</span></a>
+<a name="1685"><span class="lineNum">    1685 </span><span class="lineCov">        136 :       state_vec_151 &lt;= 3'h0;</span></a>
+<a name="1686"><span class="lineNum">    1686 </span><span class="lineCov">        136 :       state_vec_152 &lt;= 3'h0;</span></a>
+<a name="1687"><span class="lineNum">    1687 </span><span class="lineCov">        136 :       state_vec_153 &lt;= 3'h0;</span></a>
+<a name="1688"><span class="lineNum">    1688 </span><span class="lineCov">        136 :       state_vec_154 &lt;= 3'h0;</span></a>
+<a name="1689"><span class="lineNum">    1689 </span><span class="lineCov">        136 :       state_vec_155 &lt;= 3'h0;</span></a>
+<a name="1690"><span class="lineNum">    1690 </span><span class="lineCov">        136 :       state_vec_156 &lt;= 3'h0;</span></a>
+<a name="1691"><span class="lineNum">    1691 </span><span class="lineCov">        136 :       state_vec_157 &lt;= 3'h0;</span></a>
+<a name="1692"><span class="lineNum">    1692 </span><span class="lineCov">        136 :       state_vec_158 &lt;= 3'h0;</span></a>
+<a name="1693"><span class="lineNum">    1693 </span><span class="lineCov">        136 :       state_vec_159 &lt;= 3'h0;</span></a>
+<a name="1694"><span class="lineNum">    1694 </span><span class="lineCov">        136 :       state_vec_160 &lt;= 3'h0;</span></a>
+<a name="1695"><span class="lineNum">    1695 </span><span class="lineCov">        136 :       state_vec_161 &lt;= 3'h0;</span></a>
+<a name="1696"><span class="lineNum">    1696 </span><span class="lineCov">        136 :       state_vec_162 &lt;= 3'h0;</span></a>
+<a name="1697"><span class="lineNum">    1697 </span><span class="lineCov">        136 :       state_vec_163 &lt;= 3'h0;</span></a>
+<a name="1698"><span class="lineNum">    1698 </span><span class="lineCov">        136 :       state_vec_164 &lt;= 3'h0;</span></a>
+<a name="1699"><span class="lineNum">    1699 </span><span class="lineCov">        136 :       state_vec_165 &lt;= 3'h0;</span></a>
+<a name="1700"><span class="lineNum">    1700 </span><span class="lineCov">        136 :       state_vec_166 &lt;= 3'h0;</span></a>
+<a name="1701"><span class="lineNum">    1701 </span><span class="lineCov">        136 :       state_vec_167 &lt;= 3'h0;</span></a>
+<a name="1702"><span class="lineNum">    1702 </span><span class="lineCov">        136 :       state_vec_168 &lt;= 3'h0;</span></a>
+<a name="1703"><span class="lineNum">    1703 </span><span class="lineCov">        136 :       state_vec_169 &lt;= 3'h0;</span></a>
+<a name="1704"><span class="lineNum">    1704 </span><span class="lineCov">        136 :       state_vec_170 &lt;= 3'h0;</span></a>
+<a name="1705"><span class="lineNum">    1705 </span><span class="lineCov">        136 :       state_vec_171 &lt;= 3'h0;</span></a>
+<a name="1706"><span class="lineNum">    1706 </span><span class="lineCov">        136 :       state_vec_172 &lt;= 3'h0;</span></a>
+<a name="1707"><span class="lineNum">    1707 </span><span class="lineCov">        136 :       state_vec_173 &lt;= 3'h0;</span></a>
+<a name="1708"><span class="lineNum">    1708 </span><span class="lineCov">        136 :       state_vec_174 &lt;= 3'h0;</span></a>
+<a name="1709"><span class="lineNum">    1709 </span><span class="lineCov">        136 :       state_vec_175 &lt;= 3'h0;</span></a>
+<a name="1710"><span class="lineNum">    1710 </span><span class="lineCov">        136 :       state_vec_176 &lt;= 3'h0;</span></a>
+<a name="1711"><span class="lineNum">    1711 </span><span class="lineCov">        136 :       state_vec_177 &lt;= 3'h0;</span></a>
+<a name="1712"><span class="lineNum">    1712 </span><span class="lineCov">        136 :       state_vec_178 &lt;= 3'h0;</span></a>
+<a name="1713"><span class="lineNum">    1713 </span><span class="lineCov">        136 :       state_vec_179 &lt;= 3'h0;</span></a>
+<a name="1714"><span class="lineNum">    1714 </span><span class="lineCov">        136 :       state_vec_180 &lt;= 3'h0;</span></a>
+<a name="1715"><span class="lineNum">    1715 </span><span class="lineCov">        136 :       state_vec_181 &lt;= 3'h0;</span></a>
+<a name="1716"><span class="lineNum">    1716 </span><span class="lineCov">        136 :       state_vec_182 &lt;= 3'h0;</span></a>
+<a name="1717"><span class="lineNum">    1717 </span><span class="lineCov">        136 :       state_vec_183 &lt;= 3'h0;</span></a>
+<a name="1718"><span class="lineNum">    1718 </span><span class="lineCov">        136 :       state_vec_184 &lt;= 3'h0;</span></a>
+<a name="1719"><span class="lineNum">    1719 </span><span class="lineCov">        136 :       state_vec_185 &lt;= 3'h0;</span></a>
+<a name="1720"><span class="lineNum">    1720 </span><span class="lineCov">        136 :       state_vec_186 &lt;= 3'h0;</span></a>
+<a name="1721"><span class="lineNum">    1721 </span><span class="lineCov">        136 :       state_vec_187 &lt;= 3'h0;</span></a>
+<a name="1722"><span class="lineNum">    1722 </span><span class="lineCov">        136 :       state_vec_188 &lt;= 3'h0;</span></a>
+<a name="1723"><span class="lineNum">    1723 </span><span class="lineCov">        136 :       state_vec_189 &lt;= 3'h0;</span></a>
+<a name="1724"><span class="lineNum">    1724 </span><span class="lineCov">        136 :       state_vec_190 &lt;= 3'h0;</span></a>
+<a name="1725"><span class="lineNum">    1725 </span><span class="lineCov">        136 :       state_vec_191 &lt;= 3'h0;</span></a>
+<a name="1726"><span class="lineNum">    1726 </span><span class="lineCov">        136 :       state_vec_192 &lt;= 3'h0;</span></a>
+<a name="1727"><span class="lineNum">    1727 </span><span class="lineCov">        136 :       state_vec_193 &lt;= 3'h0;</span></a>
+<a name="1728"><span class="lineNum">    1728 </span><span class="lineCov">        136 :       state_vec_194 &lt;= 3'h0;</span></a>
+<a name="1729"><span class="lineNum">    1729 </span><span class="lineCov">        136 :       state_vec_195 &lt;= 3'h0;</span></a>
+<a name="1730"><span class="lineNum">    1730 </span><span class="lineCov">        136 :       state_vec_196 &lt;= 3'h0;</span></a>
+<a name="1731"><span class="lineNum">    1731 </span><span class="lineCov">        136 :       state_vec_197 &lt;= 3'h0;</span></a>
+<a name="1732"><span class="lineNum">    1732 </span><span class="lineCov">        136 :       state_vec_198 &lt;= 3'h0;</span></a>
+<a name="1733"><span class="lineNum">    1733 </span><span class="lineCov">        136 :       state_vec_199 &lt;= 3'h0;</span></a>
+<a name="1734"><span class="lineNum">    1734 </span><span class="lineCov">        136 :       state_vec_200 &lt;= 3'h0;</span></a>
+<a name="1735"><span class="lineNum">    1735 </span><span class="lineCov">        136 :       state_vec_201 &lt;= 3'h0;</span></a>
+<a name="1736"><span class="lineNum">    1736 </span><span class="lineCov">        136 :       state_vec_202 &lt;= 3'h0;</span></a>
+<a name="1737"><span class="lineNum">    1737 </span><span class="lineCov">        136 :       state_vec_203 &lt;= 3'h0;</span></a>
+<a name="1738"><span class="lineNum">    1738 </span><span class="lineCov">        136 :       state_vec_204 &lt;= 3'h0;</span></a>
+<a name="1739"><span class="lineNum">    1739 </span><span class="lineCov">        136 :       state_vec_205 &lt;= 3'h0;</span></a>
+<a name="1740"><span class="lineNum">    1740 </span><span class="lineCov">        136 :       state_vec_206 &lt;= 3'h0;</span></a>
+<a name="1741"><span class="lineNum">    1741 </span><span class="lineCov">        136 :       state_vec_207 &lt;= 3'h0;</span></a>
+<a name="1742"><span class="lineNum">    1742 </span><span class="lineCov">        136 :       state_vec_208 &lt;= 3'h0;</span></a>
+<a name="1743"><span class="lineNum">    1743 </span><span class="lineCov">        136 :       state_vec_209 &lt;= 3'h0;</span></a>
+<a name="1744"><span class="lineNum">    1744 </span><span class="lineCov">        136 :       state_vec_210 &lt;= 3'h0;</span></a>
+<a name="1745"><span class="lineNum">    1745 </span><span class="lineCov">        136 :       state_vec_211 &lt;= 3'h0;</span></a>
+<a name="1746"><span class="lineNum">    1746 </span><span class="lineCov">        136 :       state_vec_212 &lt;= 3'h0;</span></a>
+<a name="1747"><span class="lineNum">    1747 </span><span class="lineCov">        136 :       state_vec_213 &lt;= 3'h0;</span></a>
+<a name="1748"><span class="lineNum">    1748 </span><span class="lineCov">        136 :       state_vec_214 &lt;= 3'h0;</span></a>
+<a name="1749"><span class="lineNum">    1749 </span><span class="lineCov">        136 :       state_vec_215 &lt;= 3'h0;</span></a>
+<a name="1750"><span class="lineNum">    1750 </span><span class="lineCov">        136 :       state_vec_216 &lt;= 3'h0;</span></a>
+<a name="1751"><span class="lineNum">    1751 </span><span class="lineCov">        136 :       state_vec_217 &lt;= 3'h0;</span></a>
+<a name="1752"><span class="lineNum">    1752 </span><span class="lineCov">        136 :       state_vec_218 &lt;= 3'h0;</span></a>
+<a name="1753"><span class="lineNum">    1753 </span><span class="lineCov">        136 :       state_vec_219 &lt;= 3'h0;</span></a>
+<a name="1754"><span class="lineNum">    1754 </span><span class="lineCov">        136 :       state_vec_220 &lt;= 3'h0;</span></a>
+<a name="1755"><span class="lineNum">    1755 </span><span class="lineCov">        136 :       state_vec_221 &lt;= 3'h0;</span></a>
+<a name="1756"><span class="lineNum">    1756 </span><span class="lineCov">        136 :       state_vec_222 &lt;= 3'h0;</span></a>
+<a name="1757"><span class="lineNum">    1757 </span><span class="lineCov">        136 :       state_vec_223 &lt;= 3'h0;</span></a>
+<a name="1758"><span class="lineNum">    1758 </span><span class="lineCov">        136 :       state_vec_224 &lt;= 3'h0;</span></a>
+<a name="1759"><span class="lineNum">    1759 </span><span class="lineCov">        136 :       state_vec_225 &lt;= 3'h0;</span></a>
+<a name="1760"><span class="lineNum">    1760 </span><span class="lineCov">        136 :       state_vec_226 &lt;= 3'h0;</span></a>
+<a name="1761"><span class="lineNum">    1761 </span><span class="lineCov">        136 :       state_vec_227 &lt;= 3'h0;</span></a>
+<a name="1762"><span class="lineNum">    1762 </span><span class="lineCov">        136 :       state_vec_228 &lt;= 3'h0;</span></a>
+<a name="1763"><span class="lineNum">    1763 </span><span class="lineCov">        136 :       state_vec_229 &lt;= 3'h0;</span></a>
+<a name="1764"><span class="lineNum">    1764 </span><span class="lineCov">        136 :       state_vec_230 &lt;= 3'h0;</span></a>
+<a name="1765"><span class="lineNum">    1765 </span><span class="lineCov">        136 :       state_vec_231 &lt;= 3'h0;</span></a>
+<a name="1766"><span class="lineNum">    1766 </span><span class="lineCov">        136 :       state_vec_232 &lt;= 3'h0;</span></a>
+<a name="1767"><span class="lineNum">    1767 </span><span class="lineCov">        136 :       state_vec_233 &lt;= 3'h0;</span></a>
+<a name="1768"><span class="lineNum">    1768 </span><span class="lineCov">        136 :       state_vec_234 &lt;= 3'h0;</span></a>
+<a name="1769"><span class="lineNum">    1769 </span><span class="lineCov">        136 :       state_vec_235 &lt;= 3'h0;</span></a>
+<a name="1770"><span class="lineNum">    1770 </span><span class="lineCov">        136 :       state_vec_236 &lt;= 3'h0;</span></a>
+<a name="1771"><span class="lineNum">    1771 </span><span class="lineCov">        136 :       state_vec_237 &lt;= 3'h0;</span></a>
+<a name="1772"><span class="lineNum">    1772 </span><span class="lineCov">        136 :       state_vec_238 &lt;= 3'h0;</span></a>
+<a name="1773"><span class="lineNum">    1773 </span><span class="lineCov">        136 :       state_vec_239 &lt;= 3'h0;</span></a>
+<a name="1774"><span class="lineNum">    1774 </span><span class="lineCov">        136 :       state_vec_240 &lt;= 3'h0;</span></a>
+<a name="1775"><span class="lineNum">    1775 </span><span class="lineCov">        136 :       state_vec_241 &lt;= 3'h0;</span></a>
+<a name="1776"><span class="lineNum">    1776 </span><span class="lineCov">        136 :       state_vec_242 &lt;= 3'h0;</span></a>
+<a name="1777"><span class="lineNum">    1777 </span><span class="lineCov">        136 :       state_vec_243 &lt;= 3'h0;</span></a>
+<a name="1778"><span class="lineNum">    1778 </span><span class="lineCov">        136 :       state_vec_244 &lt;= 3'h0;</span></a>
+<a name="1779"><span class="lineNum">    1779 </span><span class="lineCov">        136 :       state_vec_245 &lt;= 3'h0;</span></a>
+<a name="1780"><span class="lineNum">    1780 </span><span class="lineCov">        136 :       state_vec_246 &lt;= 3'h0;</span></a>
+<a name="1781"><span class="lineNum">    1781 </span><span class="lineCov">        136 :       state_vec_247 &lt;= 3'h0;</span></a>
+<a name="1782"><span class="lineNum">    1782 </span><span class="lineCov">        136 :       state_vec_248 &lt;= 3'h0;</span></a>
+<a name="1783"><span class="lineNum">    1783 </span><span class="lineCov">        136 :       state_vec_249 &lt;= 3'h0;</span></a>
+<a name="1784"><span class="lineNum">    1784 </span><span class="lineCov">        136 :       state_vec_250 &lt;= 3'h0;</span></a>
+<a name="1785"><span class="lineNum">    1785 </span><span class="lineCov">        136 :       state_vec_251 &lt;= 3'h0;</span></a>
+<a name="1786"><span class="lineNum">    1786 </span><span class="lineCov">        136 :       state_vec_252 &lt;= 3'h0;</span></a>
+<a name="1787"><span class="lineNum">    1787 </span><span class="lineCov">        136 :       state_vec_253 &lt;= 3'h0;</span></a>
+<a name="1788"><span class="lineNum">    1788 </span><span class="lineCov">        136 :       state_vec_254 &lt;= 3'h0;</span></a>
+<a name="1789"><span class="lineNum">    1789 </span><span class="lineCov">        136 :       state_vec_255 &lt;= 3'h0;</span></a>
+<a name="1790"><span class="lineNum">    1790 </span><span class="lineCov">        136 :       state_vec_256 &lt;= 3'h0;</span></a>
+<a name="1791"><span class="lineNum">    1791 </span><span class="lineCov">        136 :       state_vec_257 &lt;= 3'h0;</span></a>
+<a name="1792"><span class="lineNum">    1792 </span><span class="lineCov">        136 :       state_vec_258 &lt;= 3'h0;</span></a>
+<a name="1793"><span class="lineNum">    1793 </span><span class="lineCov">        136 :       state_vec_259 &lt;= 3'h0;</span></a>
+<a name="1794"><span class="lineNum">    1794 </span><span class="lineCov">        136 :       state_vec_260 &lt;= 3'h0;</span></a>
+<a name="1795"><span class="lineNum">    1795 </span><span class="lineCov">        136 :       state_vec_261 &lt;= 3'h0;</span></a>
+<a name="1796"><span class="lineNum">    1796 </span><span class="lineCov">        136 :       state_vec_262 &lt;= 3'h0;</span></a>
+<a name="1797"><span class="lineNum">    1797 </span><span class="lineCov">        136 :       state_vec_263 &lt;= 3'h0;</span></a>
+<a name="1798"><span class="lineNum">    1798 </span><span class="lineCov">        136 :       state_vec_264 &lt;= 3'h0;</span></a>
+<a name="1799"><span class="lineNum">    1799 </span><span class="lineCov">        136 :       state_vec_265 &lt;= 3'h0;</span></a>
+<a name="1800"><span class="lineNum">    1800 </span><span class="lineCov">        136 :       state_vec_266 &lt;= 3'h0;</span></a>
+<a name="1801"><span class="lineNum">    1801 </span><span class="lineCov">        136 :       state_vec_267 &lt;= 3'h0;</span></a>
+<a name="1802"><span class="lineNum">    1802 </span><span class="lineCov">        136 :       state_vec_268 &lt;= 3'h0;</span></a>
+<a name="1803"><span class="lineNum">    1803 </span><span class="lineCov">        136 :       state_vec_269 &lt;= 3'h0;</span></a>
+<a name="1804"><span class="lineNum">    1804 </span><span class="lineCov">        136 :       state_vec_270 &lt;= 3'h0;</span></a>
+<a name="1805"><span class="lineNum">    1805 </span><span class="lineCov">        136 :       state_vec_271 &lt;= 3'h0;</span></a>
+<a name="1806"><span class="lineNum">    1806 </span><span class="lineCov">        136 :       state_vec_272 &lt;= 3'h0;</span></a>
+<a name="1807"><span class="lineNum">    1807 </span><span class="lineCov">        136 :       state_vec_273 &lt;= 3'h0;</span></a>
+<a name="1808"><span class="lineNum">    1808 </span><span class="lineCov">        136 :       state_vec_274 &lt;= 3'h0;</span></a>
+<a name="1809"><span class="lineNum">    1809 </span><span class="lineCov">        136 :       state_vec_275 &lt;= 3'h0;</span></a>
+<a name="1810"><span class="lineNum">    1810 </span><span class="lineCov">        136 :       state_vec_276 &lt;= 3'h0;</span></a>
+<a name="1811"><span class="lineNum">    1811 </span><span class="lineCov">        136 :       state_vec_277 &lt;= 3'h0;</span></a>
+<a name="1812"><span class="lineNum">    1812 </span><span class="lineCov">        136 :       state_vec_278 &lt;= 3'h0;</span></a>
+<a name="1813"><span class="lineNum">    1813 </span><span class="lineCov">        136 :       state_vec_279 &lt;= 3'h0;</span></a>
+<a name="1814"><span class="lineNum">    1814 </span><span class="lineCov">        136 :       state_vec_280 &lt;= 3'h0;</span></a>
+<a name="1815"><span class="lineNum">    1815 </span><span class="lineCov">        136 :       state_vec_281 &lt;= 3'h0;</span></a>
+<a name="1816"><span class="lineNum">    1816 </span><span class="lineCov">        136 :       state_vec_282 &lt;= 3'h0;</span></a>
+<a name="1817"><span class="lineNum">    1817 </span><span class="lineCov">        136 :       state_vec_283 &lt;= 3'h0;</span></a>
+<a name="1818"><span class="lineNum">    1818 </span><span class="lineCov">        136 :       state_vec_284 &lt;= 3'h0;</span></a>
+<a name="1819"><span class="lineNum">    1819 </span><span class="lineCov">        136 :       state_vec_285 &lt;= 3'h0;</span></a>
+<a name="1820"><span class="lineNum">    1820 </span><span class="lineCov">        136 :       state_vec_286 &lt;= 3'h0;</span></a>
+<a name="1821"><span class="lineNum">    1821 </span><span class="lineCov">        136 :       state_vec_287 &lt;= 3'h0;</span></a>
+<a name="1822"><span class="lineNum">    1822 </span><span class="lineCov">        136 :       state_vec_288 &lt;= 3'h0;</span></a>
+<a name="1823"><span class="lineNum">    1823 </span><span class="lineCov">        136 :       state_vec_289 &lt;= 3'h0;</span></a>
+<a name="1824"><span class="lineNum">    1824 </span><span class="lineCov">        136 :       state_vec_290 &lt;= 3'h0;</span></a>
+<a name="1825"><span class="lineNum">    1825 </span><span class="lineCov">        136 :       state_vec_291 &lt;= 3'h0;</span></a>
+<a name="1826"><span class="lineNum">    1826 </span><span class="lineCov">        136 :       state_vec_292 &lt;= 3'h0;</span></a>
+<a name="1827"><span class="lineNum">    1827 </span><span class="lineCov">        136 :       state_vec_293 &lt;= 3'h0;</span></a>
+<a name="1828"><span class="lineNum">    1828 </span><span class="lineCov">        136 :       state_vec_294 &lt;= 3'h0;</span></a>
+<a name="1829"><span class="lineNum">    1829 </span><span class="lineCov">        136 :       state_vec_295 &lt;= 3'h0;</span></a>
+<a name="1830"><span class="lineNum">    1830 </span><span class="lineCov">        136 :       state_vec_296 &lt;= 3'h0;</span></a>
+<a name="1831"><span class="lineNum">    1831 </span><span class="lineCov">        136 :       state_vec_297 &lt;= 3'h0;</span></a>
+<a name="1832"><span class="lineNum">    1832 </span><span class="lineCov">        136 :       state_vec_298 &lt;= 3'h0;</span></a>
+<a name="1833"><span class="lineNum">    1833 </span><span class="lineCov">        136 :       state_vec_299 &lt;= 3'h0;</span></a>
+<a name="1834"><span class="lineNum">    1834 </span><span class="lineCov">        136 :       state_vec_300 &lt;= 3'h0;</span></a>
+<a name="1835"><span class="lineNum">    1835 </span><span class="lineCov">        136 :       state_vec_301 &lt;= 3'h0;</span></a>
+<a name="1836"><span class="lineNum">    1836 </span><span class="lineCov">        136 :       state_vec_302 &lt;= 3'h0;</span></a>
+<a name="1837"><span class="lineNum">    1837 </span><span class="lineCov">        136 :       state_vec_303 &lt;= 3'h0;</span></a>
+<a name="1838"><span class="lineNum">    1838 </span><span class="lineCov">        136 :       state_vec_304 &lt;= 3'h0;</span></a>
+<a name="1839"><span class="lineNum">    1839 </span><span class="lineCov">        136 :       state_vec_305 &lt;= 3'h0;</span></a>
+<a name="1840"><span class="lineNum">    1840 </span><span class="lineCov">        136 :       state_vec_306 &lt;= 3'h0;</span></a>
+<a name="1841"><span class="lineNum">    1841 </span><span class="lineCov">        136 :       state_vec_307 &lt;= 3'h0;</span></a>
+<a name="1842"><span class="lineNum">    1842 </span><span class="lineCov">        136 :       state_vec_308 &lt;= 3'h0;</span></a>
+<a name="1843"><span class="lineNum">    1843 </span><span class="lineCov">        136 :       state_vec_309 &lt;= 3'h0;</span></a>
+<a name="1844"><span class="lineNum">    1844 </span><span class="lineCov">        136 :       state_vec_310 &lt;= 3'h0;</span></a>
+<a name="1845"><span class="lineNum">    1845 </span><span class="lineCov">        136 :       state_vec_311 &lt;= 3'h0;</span></a>
+<a name="1846"><span class="lineNum">    1846 </span><span class="lineCov">        136 :       state_vec_312 &lt;= 3'h0;</span></a>
+<a name="1847"><span class="lineNum">    1847 </span><span class="lineCov">        136 :       state_vec_313 &lt;= 3'h0;</span></a>
+<a name="1848"><span class="lineNum">    1848 </span><span class="lineCov">        136 :       state_vec_314 &lt;= 3'h0;</span></a>
+<a name="1849"><span class="lineNum">    1849 </span><span class="lineCov">        136 :       state_vec_315 &lt;= 3'h0;</span></a>
+<a name="1850"><span class="lineNum">    1850 </span><span class="lineCov">        136 :       state_vec_316 &lt;= 3'h0;</span></a>
+<a name="1851"><span class="lineNum">    1851 </span><span class="lineCov">        136 :       state_vec_317 &lt;= 3'h0;</span></a>
+<a name="1852"><span class="lineNum">    1852 </span><span class="lineCov">        136 :       state_vec_318 &lt;= 3'h0;</span></a>
+<a name="1853"><span class="lineNum">    1853 </span><span class="lineCov">        136 :       state_vec_319 &lt;= 3'h0;</span></a>
+<a name="1854"><span class="lineNum">    1854 </span><span class="lineCov">        136 :       state_vec_320 &lt;= 3'h0;</span></a>
+<a name="1855"><span class="lineNum">    1855 </span><span class="lineCov">        136 :       state_vec_321 &lt;= 3'h0;</span></a>
+<a name="1856"><span class="lineNum">    1856 </span><span class="lineCov">        136 :       state_vec_322 &lt;= 3'h0;</span></a>
+<a name="1857"><span class="lineNum">    1857 </span><span class="lineCov">        136 :       state_vec_323 &lt;= 3'h0;</span></a>
+<a name="1858"><span class="lineNum">    1858 </span><span class="lineCov">        136 :       state_vec_324 &lt;= 3'h0;</span></a>
+<a name="1859"><span class="lineNum">    1859 </span><span class="lineCov">        136 :       state_vec_325 &lt;= 3'h0;</span></a>
+<a name="1860"><span class="lineNum">    1860 </span><span class="lineCov">        136 :       state_vec_326 &lt;= 3'h0;</span></a>
+<a name="1861"><span class="lineNum">    1861 </span><span class="lineCov">        136 :       state_vec_327 &lt;= 3'h0;</span></a>
+<a name="1862"><span class="lineNum">    1862 </span><span class="lineCov">        136 :       state_vec_328 &lt;= 3'h0;</span></a>
+<a name="1863"><span class="lineNum">    1863 </span><span class="lineCov">        136 :       state_vec_329 &lt;= 3'h0;</span></a>
+<a name="1864"><span class="lineNum">    1864 </span><span class="lineCov">        136 :       state_vec_330 &lt;= 3'h0;</span></a>
+<a name="1865"><span class="lineNum">    1865 </span><span class="lineCov">        136 :       state_vec_331 &lt;= 3'h0;</span></a>
+<a name="1866"><span class="lineNum">    1866 </span><span class="lineCov">        136 :       state_vec_332 &lt;= 3'h0;</span></a>
+<a name="1867"><span class="lineNum">    1867 </span><span class="lineCov">        136 :       state_vec_333 &lt;= 3'h0;</span></a>
+<a name="1868"><span class="lineNum">    1868 </span><span class="lineCov">        136 :       state_vec_334 &lt;= 3'h0;</span></a>
+<a name="1869"><span class="lineNum">    1869 </span><span class="lineCov">        136 :       state_vec_335 &lt;= 3'h0;</span></a>
+<a name="1870"><span class="lineNum">    1870 </span><span class="lineCov">        136 :       state_vec_336 &lt;= 3'h0;</span></a>
+<a name="1871"><span class="lineNum">    1871 </span><span class="lineCov">        136 :       state_vec_337 &lt;= 3'h0;</span></a>
+<a name="1872"><span class="lineNum">    1872 </span><span class="lineCov">        136 :       state_vec_338 &lt;= 3'h0;</span></a>
+<a name="1873"><span class="lineNum">    1873 </span><span class="lineCov">        136 :       state_vec_339 &lt;= 3'h0;</span></a>
+<a name="1874"><span class="lineNum">    1874 </span><span class="lineCov">        136 :       state_vec_340 &lt;= 3'h0;</span></a>
+<a name="1875"><span class="lineNum">    1875 </span><span class="lineCov">        136 :       state_vec_341 &lt;= 3'h0;</span></a>
+<a name="1876"><span class="lineNum">    1876 </span><span class="lineCov">        136 :       state_vec_342 &lt;= 3'h0;</span></a>
+<a name="1877"><span class="lineNum">    1877 </span><span class="lineCov">        136 :       state_vec_343 &lt;= 3'h0;</span></a>
+<a name="1878"><span class="lineNum">    1878 </span><span class="lineCov">        136 :       state_vec_344 &lt;= 3'h0;</span></a>
+<a name="1879"><span class="lineNum">    1879 </span><span class="lineCov">        136 :       state_vec_345 &lt;= 3'h0;</span></a>
+<a name="1880"><span class="lineNum">    1880 </span><span class="lineCov">        136 :       state_vec_346 &lt;= 3'h0;</span></a>
+<a name="1881"><span class="lineNum">    1881 </span><span class="lineCov">        136 :       state_vec_347 &lt;= 3'h0;</span></a>
+<a name="1882"><span class="lineNum">    1882 </span><span class="lineCov">        136 :       state_vec_348 &lt;= 3'h0;</span></a>
+<a name="1883"><span class="lineNum">    1883 </span><span class="lineCov">        136 :       state_vec_349 &lt;= 3'h0;</span></a>
+<a name="1884"><span class="lineNum">    1884 </span><span class="lineCov">        136 :       state_vec_350 &lt;= 3'h0;</span></a>
+<a name="1885"><span class="lineNum">    1885 </span><span class="lineCov">        136 :       state_vec_351 &lt;= 3'h0;</span></a>
+<a name="1886"><span class="lineNum">    1886 </span><span class="lineCov">        136 :       state_vec_352 &lt;= 3'h0;</span></a>
+<a name="1887"><span class="lineNum">    1887 </span><span class="lineCov">        136 :       state_vec_353 &lt;= 3'h0;</span></a>
+<a name="1888"><span class="lineNum">    1888 </span><span class="lineCov">        136 :       state_vec_354 &lt;= 3'h0;</span></a>
+<a name="1889"><span class="lineNum">    1889 </span><span class="lineCov">        136 :       state_vec_355 &lt;= 3'h0;</span></a>
+<a name="1890"><span class="lineNum">    1890 </span><span class="lineCov">        136 :       state_vec_356 &lt;= 3'h0;</span></a>
+<a name="1891"><span class="lineNum">    1891 </span><span class="lineCov">        136 :       state_vec_357 &lt;= 3'h0;</span></a>
+<a name="1892"><span class="lineNum">    1892 </span><span class="lineCov">        136 :       state_vec_358 &lt;= 3'h0;</span></a>
+<a name="1893"><span class="lineNum">    1893 </span><span class="lineCov">        136 :       state_vec_359 &lt;= 3'h0;</span></a>
+<a name="1894"><span class="lineNum">    1894 </span><span class="lineCov">        136 :       state_vec_360 &lt;= 3'h0;</span></a>
+<a name="1895"><span class="lineNum">    1895 </span><span class="lineCov">        136 :       state_vec_361 &lt;= 3'h0;</span></a>
+<a name="1896"><span class="lineNum">    1896 </span><span class="lineCov">        136 :       state_vec_362 &lt;= 3'h0;</span></a>
+<a name="1897"><span class="lineNum">    1897 </span><span class="lineCov">        136 :       state_vec_363 &lt;= 3'h0;</span></a>
+<a name="1898"><span class="lineNum">    1898 </span><span class="lineCov">        136 :       state_vec_364 &lt;= 3'h0;</span></a>
+<a name="1899"><span class="lineNum">    1899 </span><span class="lineCov">        136 :       state_vec_365 &lt;= 3'h0;</span></a>
+<a name="1900"><span class="lineNum">    1900 </span><span class="lineCov">        136 :       state_vec_366 &lt;= 3'h0;</span></a>
+<a name="1901"><span class="lineNum">    1901 </span><span class="lineCov">        136 :       state_vec_367 &lt;= 3'h0;</span></a>
+<a name="1902"><span class="lineNum">    1902 </span><span class="lineCov">        136 :       state_vec_368 &lt;= 3'h0;</span></a>
+<a name="1903"><span class="lineNum">    1903 </span><span class="lineCov">        136 :       state_vec_369 &lt;= 3'h0;</span></a>
+<a name="1904"><span class="lineNum">    1904 </span><span class="lineCov">        136 :       state_vec_370 &lt;= 3'h0;</span></a>
+<a name="1905"><span class="lineNum">    1905 </span><span class="lineCov">        136 :       state_vec_371 &lt;= 3'h0;</span></a>
+<a name="1906"><span class="lineNum">    1906 </span><span class="lineCov">        136 :       state_vec_372 &lt;= 3'h0;</span></a>
+<a name="1907"><span class="lineNum">    1907 </span><span class="lineCov">        136 :       state_vec_373 &lt;= 3'h0;</span></a>
+<a name="1908"><span class="lineNum">    1908 </span><span class="lineCov">        136 :       state_vec_374 &lt;= 3'h0;</span></a>
+<a name="1909"><span class="lineNum">    1909 </span><span class="lineCov">        136 :       state_vec_375 &lt;= 3'h0;</span></a>
+<a name="1910"><span class="lineNum">    1910 </span><span class="lineCov">        136 :       state_vec_376 &lt;= 3'h0;</span></a>
+<a name="1911"><span class="lineNum">    1911 </span><span class="lineCov">        136 :       state_vec_377 &lt;= 3'h0;</span></a>
+<a name="1912"><span class="lineNum">    1912 </span><span class="lineCov">        136 :       state_vec_378 &lt;= 3'h0;</span></a>
+<a name="1913"><span class="lineNum">    1913 </span><span class="lineCov">        136 :       state_vec_379 &lt;= 3'h0;</span></a>
+<a name="1914"><span class="lineNum">    1914 </span><span class="lineCov">        136 :       state_vec_380 &lt;= 3'h0;</span></a>
+<a name="1915"><span class="lineNum">    1915 </span><span class="lineCov">        136 :       state_vec_381 &lt;= 3'h0;</span></a>
+<a name="1916"><span class="lineNum">    1916 </span><span class="lineCov">        136 :       state_vec_382 &lt;= 3'h0;</span></a>
+<a name="1917"><span class="lineNum">    1917 </span><span class="lineCov">        136 :       state_vec_383 &lt;= 3'h0;</span></a>
+<a name="1918"><span class="lineNum">    1918 </span><span class="lineCov">        136 :       state_vec_384 &lt;= 3'h0;</span></a>
+<a name="1919"><span class="lineNum">    1919 </span><span class="lineCov">        136 :       state_vec_385 &lt;= 3'h0;</span></a>
+<a name="1920"><span class="lineNum">    1920 </span><span class="lineCov">        136 :       state_vec_386 &lt;= 3'h0;</span></a>
+<a name="1921"><span class="lineNum">    1921 </span><span class="lineCov">        136 :       state_vec_387 &lt;= 3'h0;</span></a>
+<a name="1922"><span class="lineNum">    1922 </span><span class="lineCov">        136 :       state_vec_388 &lt;= 3'h0;</span></a>
+<a name="1923"><span class="lineNum">    1923 </span><span class="lineCov">        136 :       state_vec_389 &lt;= 3'h0;</span></a>
+<a name="1924"><span class="lineNum">    1924 </span><span class="lineCov">        136 :       state_vec_390 &lt;= 3'h0;</span></a>
+<a name="1925"><span class="lineNum">    1925 </span><span class="lineCov">        136 :       state_vec_391 &lt;= 3'h0;</span></a>
+<a name="1926"><span class="lineNum">    1926 </span><span class="lineCov">        136 :       state_vec_392 &lt;= 3'h0;</span></a>
+<a name="1927"><span class="lineNum">    1927 </span><span class="lineCov">        136 :       state_vec_393 &lt;= 3'h0;</span></a>
+<a name="1928"><span class="lineNum">    1928 </span><span class="lineCov">        136 :       state_vec_394 &lt;= 3'h0;</span></a>
+<a name="1929"><span class="lineNum">    1929 </span><span class="lineCov">        136 :       state_vec_395 &lt;= 3'h0;</span></a>
+<a name="1930"><span class="lineNum">    1930 </span><span class="lineCov">        136 :       state_vec_396 &lt;= 3'h0;</span></a>
+<a name="1931"><span class="lineNum">    1931 </span><span class="lineCov">        136 :       state_vec_397 &lt;= 3'h0;</span></a>
+<a name="1932"><span class="lineNum">    1932 </span><span class="lineCov">        136 :       state_vec_398 &lt;= 3'h0;</span></a>
+<a name="1933"><span class="lineNum">    1933 </span><span class="lineCov">        136 :       state_vec_399 &lt;= 3'h0;</span></a>
+<a name="1934"><span class="lineNum">    1934 </span><span class="lineCov">        136 :       state_vec_400 &lt;= 3'h0;</span></a>
+<a name="1935"><span class="lineNum">    1935 </span><span class="lineCov">        136 :       state_vec_401 &lt;= 3'h0;</span></a>
+<a name="1936"><span class="lineNum">    1936 </span><span class="lineCov">        136 :       state_vec_402 &lt;= 3'h0;</span></a>
+<a name="1937"><span class="lineNum">    1937 </span><span class="lineCov">        136 :       state_vec_403 &lt;= 3'h0;</span></a>
+<a name="1938"><span class="lineNum">    1938 </span><span class="lineCov">        136 :       state_vec_404 &lt;= 3'h0;</span></a>
+<a name="1939"><span class="lineNum">    1939 </span><span class="lineCov">        136 :       state_vec_405 &lt;= 3'h0;</span></a>
+<a name="1940"><span class="lineNum">    1940 </span><span class="lineCov">        136 :       state_vec_406 &lt;= 3'h0;</span></a>
+<a name="1941"><span class="lineNum">    1941 </span><span class="lineCov">        136 :       state_vec_407 &lt;= 3'h0;</span></a>
+<a name="1942"><span class="lineNum">    1942 </span><span class="lineCov">        136 :       state_vec_408 &lt;= 3'h0;</span></a>
+<a name="1943"><span class="lineNum">    1943 </span><span class="lineCov">        136 :       state_vec_409 &lt;= 3'h0;</span></a>
+<a name="1944"><span class="lineNum">    1944 </span><span class="lineCov">        136 :       state_vec_410 &lt;= 3'h0;</span></a>
+<a name="1945"><span class="lineNum">    1945 </span><span class="lineCov">        136 :       state_vec_411 &lt;= 3'h0;</span></a>
+<a name="1946"><span class="lineNum">    1946 </span><span class="lineCov">        136 :       state_vec_412 &lt;= 3'h0;</span></a>
+<a name="1947"><span class="lineNum">    1947 </span><span class="lineCov">        136 :       state_vec_413 &lt;= 3'h0;</span></a>
+<a name="1948"><span class="lineNum">    1948 </span><span class="lineCov">        136 :       state_vec_414 &lt;= 3'h0;</span></a>
+<a name="1949"><span class="lineNum">    1949 </span><span class="lineCov">        136 :       state_vec_415 &lt;= 3'h0;</span></a>
+<a name="1950"><span class="lineNum">    1950 </span><span class="lineCov">        136 :       state_vec_416 &lt;= 3'h0;</span></a>
+<a name="1951"><span class="lineNum">    1951 </span><span class="lineCov">        136 :       state_vec_417 &lt;= 3'h0;</span></a>
+<a name="1952"><span class="lineNum">    1952 </span><span class="lineCov">        136 :       state_vec_418 &lt;= 3'h0;</span></a>
+<a name="1953"><span class="lineNum">    1953 </span><span class="lineCov">        136 :       state_vec_419 &lt;= 3'h0;</span></a>
+<a name="1954"><span class="lineNum">    1954 </span><span class="lineCov">        136 :       state_vec_420 &lt;= 3'h0;</span></a>
+<a name="1955"><span class="lineNum">    1955 </span><span class="lineCov">        136 :       state_vec_421 &lt;= 3'h0;</span></a>
+<a name="1956"><span class="lineNum">    1956 </span><span class="lineCov">        136 :       state_vec_422 &lt;= 3'h0;</span></a>
+<a name="1957"><span class="lineNum">    1957 </span><span class="lineCov">        136 :       state_vec_423 &lt;= 3'h0;</span></a>
+<a name="1958"><span class="lineNum">    1958 </span><span class="lineCov">        136 :       state_vec_424 &lt;= 3'h0;</span></a>
+<a name="1959"><span class="lineNum">    1959 </span><span class="lineCov">        136 :       state_vec_425 &lt;= 3'h0;</span></a>
+<a name="1960"><span class="lineNum">    1960 </span><span class="lineCov">        136 :       state_vec_426 &lt;= 3'h0;</span></a>
+<a name="1961"><span class="lineNum">    1961 </span><span class="lineCov">        136 :       state_vec_427 &lt;= 3'h0;</span></a>
+<a name="1962"><span class="lineNum">    1962 </span><span class="lineCov">        136 :       state_vec_428 &lt;= 3'h0;</span></a>
+<a name="1963"><span class="lineNum">    1963 </span><span class="lineCov">        136 :       state_vec_429 &lt;= 3'h0;</span></a>
+<a name="1964"><span class="lineNum">    1964 </span><span class="lineCov">        136 :       state_vec_430 &lt;= 3'h0;</span></a>
+<a name="1965"><span class="lineNum">    1965 </span><span class="lineCov">        136 :       state_vec_431 &lt;= 3'h0;</span></a>
+<a name="1966"><span class="lineNum">    1966 </span><span class="lineCov">        136 :       state_vec_432 &lt;= 3'h0;</span></a>
+<a name="1967"><span class="lineNum">    1967 </span><span class="lineCov">        136 :       state_vec_433 &lt;= 3'h0;</span></a>
+<a name="1968"><span class="lineNum">    1968 </span><span class="lineCov">        136 :       state_vec_434 &lt;= 3'h0;</span></a>
+<a name="1969"><span class="lineNum">    1969 </span><span class="lineCov">        136 :       state_vec_435 &lt;= 3'h0;</span></a>
+<a name="1970"><span class="lineNum">    1970 </span><span class="lineCov">        136 :       state_vec_436 &lt;= 3'h0;</span></a>
+<a name="1971"><span class="lineNum">    1971 </span><span class="lineCov">        136 :       state_vec_437 &lt;= 3'h0;</span></a>
+<a name="1972"><span class="lineNum">    1972 </span><span class="lineCov">        136 :       state_vec_438 &lt;= 3'h0;</span></a>
+<a name="1973"><span class="lineNum">    1973 </span><span class="lineCov">        136 :       state_vec_439 &lt;= 3'h0;</span></a>
+<a name="1974"><span class="lineNum">    1974 </span><span class="lineCov">        136 :       state_vec_440 &lt;= 3'h0;</span></a>
+<a name="1975"><span class="lineNum">    1975 </span><span class="lineCov">        136 :       state_vec_441 &lt;= 3'h0;</span></a>
+<a name="1976"><span class="lineNum">    1976 </span><span class="lineCov">        136 :       state_vec_442 &lt;= 3'h0;</span></a>
+<a name="1977"><span class="lineNum">    1977 </span><span class="lineCov">        136 :       state_vec_443 &lt;= 3'h0;</span></a>
+<a name="1978"><span class="lineNum">    1978 </span><span class="lineCov">        136 :       state_vec_444 &lt;= 3'h0;</span></a>
+<a name="1979"><span class="lineNum">    1979 </span><span class="lineCov">        136 :       state_vec_445 &lt;= 3'h0;</span></a>
+<a name="1980"><span class="lineNum">    1980 </span><span class="lineCov">        136 :       state_vec_446 &lt;= 3'h0;</span></a>
+<a name="1981"><span class="lineNum">    1981 </span><span class="lineCov">        136 :       state_vec_447 &lt;= 3'h0;</span></a>
+<a name="1982"><span class="lineNum">    1982 </span><span class="lineCov">        136 :       state_vec_448 &lt;= 3'h0;</span></a>
+<a name="1983"><span class="lineNum">    1983 </span><span class="lineCov">        136 :       state_vec_449 &lt;= 3'h0;</span></a>
+<a name="1984"><span class="lineNum">    1984 </span><span class="lineCov">        136 :       state_vec_450 &lt;= 3'h0;</span></a>
+<a name="1985"><span class="lineNum">    1985 </span><span class="lineCov">        136 :       state_vec_451 &lt;= 3'h0;</span></a>
+<a name="1986"><span class="lineNum">    1986 </span><span class="lineCov">        136 :       state_vec_452 &lt;= 3'h0;</span></a>
+<a name="1987"><span class="lineNum">    1987 </span><span class="lineCov">        136 :       state_vec_453 &lt;= 3'h0;</span></a>
+<a name="1988"><span class="lineNum">    1988 </span><span class="lineCov">        136 :       state_vec_454 &lt;= 3'h0;</span></a>
+<a name="1989"><span class="lineNum">    1989 </span><span class="lineCov">        136 :       state_vec_455 &lt;= 3'h0;</span></a>
+<a name="1990"><span class="lineNum">    1990 </span><span class="lineCov">        136 :       state_vec_456 &lt;= 3'h0;</span></a>
+<a name="1991"><span class="lineNum">    1991 </span><span class="lineCov">        136 :       state_vec_457 &lt;= 3'h0;</span></a>
+<a name="1992"><span class="lineNum">    1992 </span><span class="lineCov">        136 :       state_vec_458 &lt;= 3'h0;</span></a>
+<a name="1993"><span class="lineNum">    1993 </span><span class="lineCov">        136 :       state_vec_459 &lt;= 3'h0;</span></a>
+<a name="1994"><span class="lineNum">    1994 </span><span class="lineCov">        136 :       state_vec_460 &lt;= 3'h0;</span></a>
+<a name="1995"><span class="lineNum">    1995 </span><span class="lineCov">        136 :       state_vec_461 &lt;= 3'h0;</span></a>
+<a name="1996"><span class="lineNum">    1996 </span><span class="lineCov">        136 :       state_vec_462 &lt;= 3'h0;</span></a>
+<a name="1997"><span class="lineNum">    1997 </span><span class="lineCov">        136 :       state_vec_463 &lt;= 3'h0;</span></a>
+<a name="1998"><span class="lineNum">    1998 </span><span class="lineCov">        136 :       state_vec_464 &lt;= 3'h0;</span></a>
+<a name="1999"><span class="lineNum">    1999 </span><span class="lineCov">        136 :       state_vec_465 &lt;= 3'h0;</span></a>
+<a name="2000"><span class="lineNum">    2000 </span><span class="lineCov">        136 :       state_vec_466 &lt;= 3'h0;</span></a>
+<a name="2001"><span class="lineNum">    2001 </span><span class="lineCov">        136 :       state_vec_467 &lt;= 3'h0;</span></a>
+<a name="2002"><span class="lineNum">    2002 </span><span class="lineCov">        136 :       state_vec_468 &lt;= 3'h0;</span></a>
+<a name="2003"><span class="lineNum">    2003 </span><span class="lineCov">        136 :       state_vec_469 &lt;= 3'h0;</span></a>
+<a name="2004"><span class="lineNum">    2004 </span><span class="lineCov">        136 :       state_vec_470 &lt;= 3'h0;</span></a>
+<a name="2005"><span class="lineNum">    2005 </span><span class="lineCov">        136 :       state_vec_471 &lt;= 3'h0;</span></a>
+<a name="2006"><span class="lineNum">    2006 </span><span class="lineCov">        136 :       state_vec_472 &lt;= 3'h0;</span></a>
+<a name="2007"><span class="lineNum">    2007 </span><span class="lineCov">        136 :       state_vec_473 &lt;= 3'h0;</span></a>
+<a name="2008"><span class="lineNum">    2008 </span><span class="lineCov">        136 :       state_vec_474 &lt;= 3'h0;</span></a>
+<a name="2009"><span class="lineNum">    2009 </span><span class="lineCov">        136 :       state_vec_475 &lt;= 3'h0;</span></a>
+<a name="2010"><span class="lineNum">    2010 </span><span class="lineCov">        136 :       state_vec_476 &lt;= 3'h0;</span></a>
+<a name="2011"><span class="lineNum">    2011 </span><span class="lineCov">        136 :       state_vec_477 &lt;= 3'h0;</span></a>
+<a name="2012"><span class="lineNum">    2012 </span><span class="lineCov">        136 :       state_vec_478 &lt;= 3'h0;</span></a>
+<a name="2013"><span class="lineNum">    2013 </span><span class="lineCov">        136 :       state_vec_479 &lt;= 3'h0;</span></a>
+<a name="2014"><span class="lineNum">    2014 </span><span class="lineCov">        136 :       state_vec_480 &lt;= 3'h0;</span></a>
+<a name="2015"><span class="lineNum">    2015 </span><span class="lineCov">        136 :       state_vec_481 &lt;= 3'h0;</span></a>
+<a name="2016"><span class="lineNum">    2016 </span><span class="lineCov">        136 :       state_vec_482 &lt;= 3'h0;</span></a>
+<a name="2017"><span class="lineNum">    2017 </span><span class="lineCov">        136 :       state_vec_483 &lt;= 3'h0;</span></a>
+<a name="2018"><span class="lineNum">    2018 </span><span class="lineCov">        136 :       state_vec_484 &lt;= 3'h0;</span></a>
+<a name="2019"><span class="lineNum">    2019 </span><span class="lineCov">        136 :       state_vec_485 &lt;= 3'h0;</span></a>
+<a name="2020"><span class="lineNum">    2020 </span><span class="lineCov">        136 :       state_vec_486 &lt;= 3'h0;</span></a>
+<a name="2021"><span class="lineNum">    2021 </span><span class="lineCov">        136 :       state_vec_487 &lt;= 3'h0;</span></a>
+<a name="2022"><span class="lineNum">    2022 </span><span class="lineCov">        136 :       state_vec_488 &lt;= 3'h0;</span></a>
+<a name="2023"><span class="lineNum">    2023 </span><span class="lineCov">        136 :       state_vec_489 &lt;= 3'h0;</span></a>
+<a name="2024"><span class="lineNum">    2024 </span><span class="lineCov">        136 :       state_vec_490 &lt;= 3'h0;</span></a>
+<a name="2025"><span class="lineNum">    2025 </span><span class="lineCov">        136 :       state_vec_491 &lt;= 3'h0;</span></a>
+<a name="2026"><span class="lineNum">    2026 </span><span class="lineCov">        136 :       state_vec_492 &lt;= 3'h0;</span></a>
+<a name="2027"><span class="lineNum">    2027 </span><span class="lineCov">        136 :       state_vec_493 &lt;= 3'h0;</span></a>
+<a name="2028"><span class="lineNum">    2028 </span><span class="lineCov">        136 :       state_vec_494 &lt;= 3'h0;</span></a>
+<a name="2029"><span class="lineNum">    2029 </span><span class="lineCov">        136 :       state_vec_495 &lt;= 3'h0;</span></a>
+<a name="2030"><span class="lineNum">    2030 </span><span class="lineCov">        136 :       state_vec_496 &lt;= 3'h0;</span></a>
+<a name="2031"><span class="lineNum">    2031 </span><span class="lineCov">        136 :       state_vec_497 &lt;= 3'h0;</span></a>
+<a name="2032"><span class="lineNum">    2032 </span><span class="lineCov">        136 :       state_vec_498 &lt;= 3'h0;</span></a>
+<a name="2033"><span class="lineNum">    2033 </span><span class="lineCov">        136 :       state_vec_499 &lt;= 3'h0;</span></a>
+<a name="2034"><span class="lineNum">    2034 </span><span class="lineCov">        136 :       state_vec_500 &lt;= 3'h0;</span></a>
+<a name="2035"><span class="lineNum">    2035 </span><span class="lineCov">        136 :       state_vec_501 &lt;= 3'h0;</span></a>
+<a name="2036"><span class="lineNum">    2036 </span><span class="lineCov">        136 :       state_vec_502 &lt;= 3'h0;</span></a>
+<a name="2037"><span class="lineNum">    2037 </span><span class="lineCov">        136 :       state_vec_503 &lt;= 3'h0;</span></a>
+<a name="2038"><span class="lineNum">    2038 </span><span class="lineCov">        136 :       state_vec_504 &lt;= 3'h0;</span></a>
+<a name="2039"><span class="lineNum">    2039 </span><span class="lineCov">        136 :       state_vec_505 &lt;= 3'h0;</span></a>
+<a name="2040"><span class="lineNum">    2040 </span><span class="lineCov">        136 :       state_vec_506 &lt;= 3'h0;</span></a>
+<a name="2041"><span class="lineNum">    2041 </span><span class="lineCov">        136 :       state_vec_507 &lt;= 3'h0;</span></a>
+<a name="2042"><span class="lineNum">    2042 </span><span class="lineCov">        136 :       state_vec_508 &lt;= 3'h0;</span></a>
+<a name="2043"><span class="lineNum">    2043 </span><span class="lineCov">        136 :       state_vec_509 &lt;= 3'h0;</span></a>
+<a name="2044"><span class="lineNum">    2044 </span><span class="lineCov">        136 :       state_vec_510 &lt;= 3'h0;</span></a>
+<a name="2045"><span class="lineNum">    2045 </span>            :       state_vec_511 &lt;= 3'h0;</a>
+<a name="2046"><span class="lineNum">    2046 </span><span class="lineCov">      63729 :     end</span></a>
+<a name="2047"><span class="lineNum">    2047 </span><span class="lineNoCov">          0 :     else begin</span></a>
+<a name="2048"><span class="lineNum">    2048 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h0)</span></a>
+<a name="2049"><span class="lineNum">    2049 </span><span class="lineNoCov">          0 :         state_vec_0 &lt;=</span></a>
+<a name="2050"><span class="lineNum">    2050 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2051"><span class="lineNum">    2051 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_0[1],</span></a>
+<a name="2052"><span class="lineNum">    2052 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_0[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2053"><span class="lineNum">    2053 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1)</span></a>
+<a name="2054"><span class="lineNum">    2054 </span><span class="lineNoCov">          0 :         state_vec_1 &lt;=</span></a>
+<a name="2055"><span class="lineNum">    2055 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2056"><span class="lineNum">    2056 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_1[1],</span></a>
+<a name="2057"><span class="lineNum">    2057 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_1[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2058"><span class="lineNum">    2058 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h2)</span></a>
+<a name="2059"><span class="lineNum">    2059 </span><span class="lineNoCov">          0 :         state_vec_2 &lt;=</span></a>
+<a name="2060"><span class="lineNum">    2060 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2061"><span class="lineNum">    2061 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_2[1],</span></a>
+<a name="2062"><span class="lineNum">    2062 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_2[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2063"><span class="lineNum">    2063 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h3)</span></a>
+<a name="2064"><span class="lineNum">    2064 </span><span class="lineNoCov">          0 :         state_vec_3 &lt;=</span></a>
+<a name="2065"><span class="lineNum">    2065 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2066"><span class="lineNum">    2066 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_3[1],</span></a>
+<a name="2067"><span class="lineNum">    2067 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_3[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2068"><span class="lineNum">    2068 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h4)</span></a>
+<a name="2069"><span class="lineNum">    2069 </span><span class="lineNoCov">          0 :         state_vec_4 &lt;=</span></a>
+<a name="2070"><span class="lineNum">    2070 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2071"><span class="lineNum">    2071 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_4[1],</span></a>
+<a name="2072"><span class="lineNum">    2072 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_4[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2073"><span class="lineNum">    2073 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h5)</span></a>
+<a name="2074"><span class="lineNum">    2074 </span><span class="lineNoCov">          0 :         state_vec_5 &lt;=</span></a>
+<a name="2075"><span class="lineNum">    2075 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2076"><span class="lineNum">    2076 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_5[1],</span></a>
+<a name="2077"><span class="lineNum">    2077 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_5[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2078"><span class="lineNum">    2078 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h6)</span></a>
+<a name="2079"><span class="lineNum">    2079 </span><span class="lineNoCov">          0 :         state_vec_6 &lt;=</span></a>
+<a name="2080"><span class="lineNum">    2080 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2081"><span class="lineNum">    2081 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_6[1],</span></a>
+<a name="2082"><span class="lineNum">    2082 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_6[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2083"><span class="lineNum">    2083 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h7)</span></a>
+<a name="2084"><span class="lineNum">    2084 </span><span class="lineNoCov">          0 :         state_vec_7 &lt;=</span></a>
+<a name="2085"><span class="lineNum">    2085 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2086"><span class="lineNum">    2086 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_7[1],</span></a>
+<a name="2087"><span class="lineNum">    2087 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_7[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2088"><span class="lineNum">    2088 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h8)</span></a>
+<a name="2089"><span class="lineNum">    2089 </span><span class="lineNoCov">          0 :         state_vec_8 &lt;=</span></a>
+<a name="2090"><span class="lineNum">    2090 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2091"><span class="lineNum">    2091 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_8[1],</span></a>
+<a name="2092"><span class="lineNum">    2092 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_8[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2093"><span class="lineNum">    2093 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h9)</span></a>
+<a name="2094"><span class="lineNum">    2094 </span><span class="lineNoCov">          0 :         state_vec_9 &lt;=</span></a>
+<a name="2095"><span class="lineNum">    2095 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2096"><span class="lineNum">    2096 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_9[1],</span></a>
+<a name="2097"><span class="lineNum">    2097 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_9[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2098"><span class="lineNum">    2098 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hA)</span></a>
+<a name="2099"><span class="lineNum">    2099 </span><span class="lineNoCov">          0 :         state_vec_10 &lt;=</span></a>
+<a name="2100"><span class="lineNum">    2100 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2101"><span class="lineNum">    2101 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_10[1],</span></a>
+<a name="2102"><span class="lineNum">    2102 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_10[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2103"><span class="lineNum">    2103 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hB)</span></a>
+<a name="2104"><span class="lineNum">    2104 </span><span class="lineNoCov">          0 :         state_vec_11 &lt;=</span></a>
+<a name="2105"><span class="lineNum">    2105 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2106"><span class="lineNum">    2106 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_11[1],</span></a>
+<a name="2107"><span class="lineNum">    2107 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_11[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2108"><span class="lineNum">    2108 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hC)</span></a>
+<a name="2109"><span class="lineNum">    2109 </span><span class="lineNoCov">          0 :         state_vec_12 &lt;=</span></a>
+<a name="2110"><span class="lineNum">    2110 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2111"><span class="lineNum">    2111 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_12[1],</span></a>
+<a name="2112"><span class="lineNum">    2112 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_12[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2113"><span class="lineNum">    2113 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hD)</span></a>
+<a name="2114"><span class="lineNum">    2114 </span><span class="lineNoCov">          0 :         state_vec_13 &lt;=</span></a>
+<a name="2115"><span class="lineNum">    2115 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2116"><span class="lineNum">    2116 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_13[1],</span></a>
+<a name="2117"><span class="lineNum">    2117 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_13[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2118"><span class="lineNum">    2118 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hE)</span></a>
+<a name="2119"><span class="lineNum">    2119 </span><span class="lineNoCov">          0 :         state_vec_14 &lt;=</span></a>
+<a name="2120"><span class="lineNum">    2120 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2121"><span class="lineNum">    2121 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_14[1],</span></a>
+<a name="2122"><span class="lineNum">    2122 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_14[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2123"><span class="lineNum">    2123 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hF)</span></a>
+<a name="2124"><span class="lineNum">    2124 </span><span class="lineNoCov">          0 :         state_vec_15 &lt;=</span></a>
+<a name="2125"><span class="lineNum">    2125 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2126"><span class="lineNum">    2126 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_15[1],</span></a>
+<a name="2127"><span class="lineNum">    2127 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_15[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2128"><span class="lineNum">    2128 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h10)</span></a>
+<a name="2129"><span class="lineNum">    2129 </span><span class="lineNoCov">          0 :         state_vec_16 &lt;=</span></a>
+<a name="2130"><span class="lineNum">    2130 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2131"><span class="lineNum">    2131 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_16[1],</span></a>
+<a name="2132"><span class="lineNum">    2132 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_16[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2133"><span class="lineNum">    2133 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h11)</span></a>
+<a name="2134"><span class="lineNum">    2134 </span><span class="lineNoCov">          0 :         state_vec_17 &lt;=</span></a>
+<a name="2135"><span class="lineNum">    2135 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2136"><span class="lineNum">    2136 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_17[1],</span></a>
+<a name="2137"><span class="lineNum">    2137 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_17[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2138"><span class="lineNum">    2138 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h12)</span></a>
+<a name="2139"><span class="lineNum">    2139 </span><span class="lineNoCov">          0 :         state_vec_18 &lt;=</span></a>
+<a name="2140"><span class="lineNum">    2140 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2141"><span class="lineNum">    2141 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_18[1],</span></a>
+<a name="2142"><span class="lineNum">    2142 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_18[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2143"><span class="lineNum">    2143 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h13)</span></a>
+<a name="2144"><span class="lineNum">    2144 </span><span class="lineNoCov">          0 :         state_vec_19 &lt;=</span></a>
+<a name="2145"><span class="lineNum">    2145 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2146"><span class="lineNum">    2146 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_19[1],</span></a>
+<a name="2147"><span class="lineNum">    2147 </span><span class="lineCov">          4 :            touch_way_0_bits[1] ? state_vec_19[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2148"><span class="lineNum">    2148 </span><span class="lineCov">          2 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h14)</span></a>
+<a name="2149"><span class="lineNum">    2149 </span><span class="lineCov">          2 :         state_vec_20 &lt;=</span></a>
+<a name="2150"><span class="lineNum">    2150 </span><span class="lineCov">          2 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2151"><span class="lineNum">    2151 </span><span class="lineCov">          2 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_20[1],</span></a>
+<a name="2152"><span class="lineNum">    2152 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_20[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2153"><span class="lineNum">    2153 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h15)</span></a>
+<a name="2154"><span class="lineNum">    2154 </span><span class="lineNoCov">          0 :         state_vec_21 &lt;=</span></a>
+<a name="2155"><span class="lineNum">    2155 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2156"><span class="lineNum">    2156 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_21[1],</span></a>
+<a name="2157"><span class="lineNum">    2157 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_21[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2158"><span class="lineNum">    2158 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h16)</span></a>
+<a name="2159"><span class="lineNum">    2159 </span><span class="lineNoCov">          0 :         state_vec_22 &lt;=</span></a>
+<a name="2160"><span class="lineNum">    2160 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2161"><span class="lineNum">    2161 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_22[1],</span></a>
+<a name="2162"><span class="lineNum">    2162 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_22[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2163"><span class="lineNum">    2163 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h17)</span></a>
+<a name="2164"><span class="lineNum">    2164 </span><span class="lineNoCov">          0 :         state_vec_23 &lt;=</span></a>
+<a name="2165"><span class="lineNum">    2165 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2166"><span class="lineNum">    2166 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_23[1],</span></a>
+<a name="2167"><span class="lineNum">    2167 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_23[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2168"><span class="lineNum">    2168 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h18)</span></a>
+<a name="2169"><span class="lineNum">    2169 </span><span class="lineNoCov">          0 :         state_vec_24 &lt;=</span></a>
+<a name="2170"><span class="lineNum">    2170 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2171"><span class="lineNum">    2171 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_24[1],</span></a>
+<a name="2172"><span class="lineNum">    2172 </span><span class="lineCov">          2 :            touch_way_0_bits[1] ? state_vec_24[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2173"><span class="lineNum">    2173 </span><span class="lineCov">          1 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h19)</span></a>
+<a name="2174"><span class="lineNum">    2174 </span><span class="lineCov">          1 :         state_vec_25 &lt;=</span></a>
+<a name="2175"><span class="lineNum">    2175 </span><span class="lineCov">          1 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2176"><span class="lineNum">    2176 </span><span class="lineCov">          1 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_25[1],</span></a>
+<a name="2177"><span class="lineNum">    2177 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_25[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2178"><span class="lineNum">    2178 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1A)</span></a>
+<a name="2179"><span class="lineNum">    2179 </span><span class="lineNoCov">          0 :         state_vec_26 &lt;=</span></a>
+<a name="2180"><span class="lineNum">    2180 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2181"><span class="lineNum">    2181 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_26[1],</span></a>
+<a name="2182"><span class="lineNum">    2182 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_26[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2183"><span class="lineNum">    2183 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1B)</span></a>
+<a name="2184"><span class="lineNum">    2184 </span><span class="lineNoCov">          0 :         state_vec_27 &lt;=</span></a>
+<a name="2185"><span class="lineNum">    2185 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2186"><span class="lineNum">    2186 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_27[1],</span></a>
+<a name="2187"><span class="lineNum">    2187 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_27[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2188"><span class="lineNum">    2188 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1C)</span></a>
+<a name="2189"><span class="lineNum">    2189 </span><span class="lineNoCov">          0 :         state_vec_28 &lt;=</span></a>
+<a name="2190"><span class="lineNum">    2190 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2191"><span class="lineNum">    2191 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_28[1],</span></a>
+<a name="2192"><span class="lineNum">    2192 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_28[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2193"><span class="lineNum">    2193 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1D)</span></a>
+<a name="2194"><span class="lineNum">    2194 </span><span class="lineNoCov">          0 :         state_vec_29 &lt;=</span></a>
+<a name="2195"><span class="lineNum">    2195 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2196"><span class="lineNum">    2196 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_29[1],</span></a>
+<a name="2197"><span class="lineNum">    2197 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_29[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2198"><span class="lineNum">    2198 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1E)</span></a>
+<a name="2199"><span class="lineNum">    2199 </span><span class="lineNoCov">          0 :         state_vec_30 &lt;=</span></a>
+<a name="2200"><span class="lineNum">    2200 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2201"><span class="lineNum">    2201 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_30[1],</span></a>
+<a name="2202"><span class="lineNum">    2202 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_30[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2203"><span class="lineNum">    2203 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1F)</span></a>
+<a name="2204"><span class="lineNum">    2204 </span><span class="lineNoCov">          0 :         state_vec_31 &lt;=</span></a>
+<a name="2205"><span class="lineNum">    2205 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2206"><span class="lineNum">    2206 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_31[1],</span></a>
+<a name="2207"><span class="lineNum">    2207 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_31[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2208"><span class="lineNum">    2208 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h20)</span></a>
+<a name="2209"><span class="lineNum">    2209 </span><span class="lineNoCov">          0 :         state_vec_32 &lt;=</span></a>
+<a name="2210"><span class="lineNum">    2210 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2211"><span class="lineNum">    2211 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_32[1],</span></a>
+<a name="2212"><span class="lineNum">    2212 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_32[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2213"><span class="lineNum">    2213 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h21)</span></a>
+<a name="2214"><span class="lineNum">    2214 </span><span class="lineNoCov">          0 :         state_vec_33 &lt;=</span></a>
+<a name="2215"><span class="lineNum">    2215 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2216"><span class="lineNum">    2216 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_33[1],</span></a>
+<a name="2217"><span class="lineNum">    2217 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_33[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2218"><span class="lineNum">    2218 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h22)</span></a>
+<a name="2219"><span class="lineNum">    2219 </span><span class="lineNoCov">          0 :         state_vec_34 &lt;=</span></a>
+<a name="2220"><span class="lineNum">    2220 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2221"><span class="lineNum">    2221 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_34[1],</span></a>
+<a name="2222"><span class="lineNum">    2222 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_34[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2223"><span class="lineNum">    2223 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h23)</span></a>
+<a name="2224"><span class="lineNum">    2224 </span><span class="lineNoCov">          0 :         state_vec_35 &lt;=</span></a>
+<a name="2225"><span class="lineNum">    2225 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2226"><span class="lineNum">    2226 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_35[1],</span></a>
+<a name="2227"><span class="lineNum">    2227 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_35[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2228"><span class="lineNum">    2228 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h24)</span></a>
+<a name="2229"><span class="lineNum">    2229 </span><span class="lineNoCov">          0 :         state_vec_36 &lt;=</span></a>
+<a name="2230"><span class="lineNum">    2230 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2231"><span class="lineNum">    2231 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_36[1],</span></a>
+<a name="2232"><span class="lineNum">    2232 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_36[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2233"><span class="lineNum">    2233 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h25)</span></a>
+<a name="2234"><span class="lineNum">    2234 </span><span class="lineNoCov">          0 :         state_vec_37 &lt;=</span></a>
+<a name="2235"><span class="lineNum">    2235 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2236"><span class="lineNum">    2236 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_37[1],</span></a>
+<a name="2237"><span class="lineNum">    2237 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_37[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2238"><span class="lineNum">    2238 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h26)</span></a>
+<a name="2239"><span class="lineNum">    2239 </span><span class="lineNoCov">          0 :         state_vec_38 &lt;=</span></a>
+<a name="2240"><span class="lineNum">    2240 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2241"><span class="lineNum">    2241 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_38[1],</span></a>
+<a name="2242"><span class="lineNum">    2242 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_38[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2243"><span class="lineNum">    2243 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h27)</span></a>
+<a name="2244"><span class="lineNum">    2244 </span><span class="lineNoCov">          0 :         state_vec_39 &lt;=</span></a>
+<a name="2245"><span class="lineNum">    2245 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2246"><span class="lineNum">    2246 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_39[1],</span></a>
+<a name="2247"><span class="lineNum">    2247 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_39[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2248"><span class="lineNum">    2248 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h28)</span></a>
+<a name="2249"><span class="lineNum">    2249 </span><span class="lineNoCov">          0 :         state_vec_40 &lt;=</span></a>
+<a name="2250"><span class="lineNum">    2250 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2251"><span class="lineNum">    2251 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_40[1],</span></a>
+<a name="2252"><span class="lineNum">    2252 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_40[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2253"><span class="lineNum">    2253 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h29)</span></a>
+<a name="2254"><span class="lineNum">    2254 </span><span class="lineNoCov">          0 :         state_vec_41 &lt;=</span></a>
+<a name="2255"><span class="lineNum">    2255 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2256"><span class="lineNum">    2256 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_41[1],</span></a>
+<a name="2257"><span class="lineNum">    2257 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_41[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2258"><span class="lineNum">    2258 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h2A)</span></a>
+<a name="2259"><span class="lineNum">    2259 </span><span class="lineNoCov">          0 :         state_vec_42 &lt;=</span></a>
+<a name="2260"><span class="lineNum">    2260 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2261"><span class="lineNum">    2261 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_42[1],</span></a>
+<a name="2262"><span class="lineNum">    2262 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_42[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2263"><span class="lineNum">    2263 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h2B)</span></a>
+<a name="2264"><span class="lineNum">    2264 </span><span class="lineNoCov">          0 :         state_vec_43 &lt;=</span></a>
+<a name="2265"><span class="lineNum">    2265 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2266"><span class="lineNum">    2266 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_43[1],</span></a>
+<a name="2267"><span class="lineNum">    2267 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_43[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2268"><span class="lineNum">    2268 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h2C)</span></a>
+<a name="2269"><span class="lineNum">    2269 </span><span class="lineNoCov">          0 :         state_vec_44 &lt;=</span></a>
+<a name="2270"><span class="lineNum">    2270 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2271"><span class="lineNum">    2271 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_44[1],</span></a>
+<a name="2272"><span class="lineNum">    2272 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_44[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2273"><span class="lineNum">    2273 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h2D)</span></a>
+<a name="2274"><span class="lineNum">    2274 </span><span class="lineNoCov">          0 :         state_vec_45 &lt;=</span></a>
+<a name="2275"><span class="lineNum">    2275 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2276"><span class="lineNum">    2276 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_45[1],</span></a>
+<a name="2277"><span class="lineNum">    2277 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_45[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2278"><span class="lineNum">    2278 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h2E)</span></a>
+<a name="2279"><span class="lineNum">    2279 </span><span class="lineNoCov">          0 :         state_vec_46 &lt;=</span></a>
+<a name="2280"><span class="lineNum">    2280 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2281"><span class="lineNum">    2281 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_46[1],</span></a>
+<a name="2282"><span class="lineNum">    2282 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_46[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2283"><span class="lineNum">    2283 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h2F)</span></a>
+<a name="2284"><span class="lineNum">    2284 </span><span class="lineNoCov">          0 :         state_vec_47 &lt;=</span></a>
+<a name="2285"><span class="lineNum">    2285 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2286"><span class="lineNum">    2286 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_47[1],</span></a>
+<a name="2287"><span class="lineNum">    2287 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_47[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2288"><span class="lineNum">    2288 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h30)</span></a>
+<a name="2289"><span class="lineNum">    2289 </span><span class="lineNoCov">          0 :         state_vec_48 &lt;=</span></a>
+<a name="2290"><span class="lineNum">    2290 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2291"><span class="lineNum">    2291 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_48[1],</span></a>
+<a name="2292"><span class="lineNum">    2292 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_48[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2293"><span class="lineNum">    2293 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h31)</span></a>
+<a name="2294"><span class="lineNum">    2294 </span><span class="lineNoCov">          0 :         state_vec_49 &lt;=</span></a>
+<a name="2295"><span class="lineNum">    2295 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2296"><span class="lineNum">    2296 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_49[1],</span></a>
+<a name="2297"><span class="lineNum">    2297 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_49[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2298"><span class="lineNum">    2298 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h32)</span></a>
+<a name="2299"><span class="lineNum">    2299 </span><span class="lineNoCov">          0 :         state_vec_50 &lt;=</span></a>
+<a name="2300"><span class="lineNum">    2300 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2301"><span class="lineNum">    2301 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_50[1],</span></a>
+<a name="2302"><span class="lineNum">    2302 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_50[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2303"><span class="lineNum">    2303 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h33)</span></a>
+<a name="2304"><span class="lineNum">    2304 </span><span class="lineNoCov">          0 :         state_vec_51 &lt;=</span></a>
+<a name="2305"><span class="lineNum">    2305 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2306"><span class="lineNum">    2306 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_51[1],</span></a>
+<a name="2307"><span class="lineNum">    2307 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_51[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2308"><span class="lineNum">    2308 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h34)</span></a>
+<a name="2309"><span class="lineNum">    2309 </span><span class="lineNoCov">          0 :         state_vec_52 &lt;=</span></a>
+<a name="2310"><span class="lineNum">    2310 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2311"><span class="lineNum">    2311 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_52[1],</span></a>
+<a name="2312"><span class="lineNum">    2312 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_52[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2313"><span class="lineNum">    2313 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h35)</span></a>
+<a name="2314"><span class="lineNum">    2314 </span><span class="lineNoCov">          0 :         state_vec_53 &lt;=</span></a>
+<a name="2315"><span class="lineNum">    2315 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2316"><span class="lineNum">    2316 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_53[1],</span></a>
+<a name="2317"><span class="lineNum">    2317 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_53[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2318"><span class="lineNum">    2318 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h36)</span></a>
+<a name="2319"><span class="lineNum">    2319 </span><span class="lineNoCov">          0 :         state_vec_54 &lt;=</span></a>
+<a name="2320"><span class="lineNum">    2320 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2321"><span class="lineNum">    2321 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_54[1],</span></a>
+<a name="2322"><span class="lineNum">    2322 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_54[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2323"><span class="lineNum">    2323 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h37)</span></a>
+<a name="2324"><span class="lineNum">    2324 </span><span class="lineNoCov">          0 :         state_vec_55 &lt;=</span></a>
+<a name="2325"><span class="lineNum">    2325 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2326"><span class="lineNum">    2326 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_55[1],</span></a>
+<a name="2327"><span class="lineNum">    2327 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_55[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2328"><span class="lineNum">    2328 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h38)</span></a>
+<a name="2329"><span class="lineNum">    2329 </span><span class="lineNoCov">          0 :         state_vec_56 &lt;=</span></a>
+<a name="2330"><span class="lineNum">    2330 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2331"><span class="lineNum">    2331 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_56[1],</span></a>
+<a name="2332"><span class="lineNum">    2332 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_56[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2333"><span class="lineNum">    2333 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h39)</span></a>
+<a name="2334"><span class="lineNum">    2334 </span><span class="lineNoCov">          0 :         state_vec_57 &lt;=</span></a>
+<a name="2335"><span class="lineNum">    2335 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2336"><span class="lineNum">    2336 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_57[1],</span></a>
+<a name="2337"><span class="lineNum">    2337 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_57[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2338"><span class="lineNum">    2338 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h3A)</span></a>
+<a name="2339"><span class="lineNum">    2339 </span><span class="lineNoCov">          0 :         state_vec_58 &lt;=</span></a>
+<a name="2340"><span class="lineNum">    2340 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2341"><span class="lineNum">    2341 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_58[1],</span></a>
+<a name="2342"><span class="lineNum">    2342 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_58[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2343"><span class="lineNum">    2343 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h3B)</span></a>
+<a name="2344"><span class="lineNum">    2344 </span><span class="lineNoCov">          0 :         state_vec_59 &lt;=</span></a>
+<a name="2345"><span class="lineNum">    2345 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2346"><span class="lineNum">    2346 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_59[1],</span></a>
+<a name="2347"><span class="lineNum">    2347 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_59[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2348"><span class="lineNum">    2348 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h3C)</span></a>
+<a name="2349"><span class="lineNum">    2349 </span><span class="lineNoCov">          0 :         state_vec_60 &lt;=</span></a>
+<a name="2350"><span class="lineNum">    2350 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2351"><span class="lineNum">    2351 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_60[1],</span></a>
+<a name="2352"><span class="lineNum">    2352 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_60[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2353"><span class="lineNum">    2353 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h3D)</span></a>
+<a name="2354"><span class="lineNum">    2354 </span><span class="lineNoCov">          0 :         state_vec_61 &lt;=</span></a>
+<a name="2355"><span class="lineNum">    2355 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2356"><span class="lineNum">    2356 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_61[1],</span></a>
+<a name="2357"><span class="lineNum">    2357 </span><span class="lineCov">          2 :            touch_way_0_bits[1] ? state_vec_61[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2358"><span class="lineNum">    2358 </span><span class="lineCov">          1 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h3E)</span></a>
+<a name="2359"><span class="lineNum">    2359 </span><span class="lineCov">          1 :         state_vec_62 &lt;=</span></a>
+<a name="2360"><span class="lineNum">    2360 </span><span class="lineCov">          1 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2361"><span class="lineNum">    2361 </span><span class="lineCov">          1 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_62[1],</span></a>
+<a name="2362"><span class="lineNum">    2362 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_62[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2363"><span class="lineNum">    2363 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h3F)</span></a>
+<a name="2364"><span class="lineNum">    2364 </span><span class="lineNoCov">          0 :         state_vec_63 &lt;=</span></a>
+<a name="2365"><span class="lineNum">    2365 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2366"><span class="lineNum">    2366 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_63[1],</span></a>
+<a name="2367"><span class="lineNum">    2367 </span><span class="lineCov">         16 :            touch_way_0_bits[1] ? state_vec_63[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2368"><span class="lineNum">    2368 </span><span class="lineCov">          8 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h40)</span></a>
+<a name="2369"><span class="lineNum">    2369 </span><span class="lineCov">          8 :         state_vec_64 &lt;=</span></a>
+<a name="2370"><span class="lineNum">    2370 </span><span class="lineCov">          8 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2371"><span class="lineNum">    2371 </span><span class="lineCov">          8 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_64[1],</span></a>
+<a name="2372"><span class="lineNum">    2372 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_64[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2373"><span class="lineNum">    2373 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h41)</span></a>
+<a name="2374"><span class="lineNum">    2374 </span><span class="lineNoCov">          0 :         state_vec_65 &lt;=</span></a>
+<a name="2375"><span class="lineNum">    2375 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2376"><span class="lineNum">    2376 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_65[1],</span></a>
+<a name="2377"><span class="lineNum">    2377 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_65[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2378"><span class="lineNum">    2378 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h42)</span></a>
+<a name="2379"><span class="lineNum">    2379 </span><span class="lineNoCov">          0 :         state_vec_66 &lt;=</span></a>
+<a name="2380"><span class="lineNum">    2380 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2381"><span class="lineNum">    2381 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_66[1],</span></a>
+<a name="2382"><span class="lineNum">    2382 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_66[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2383"><span class="lineNum">    2383 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h43)</span></a>
+<a name="2384"><span class="lineNum">    2384 </span><span class="lineNoCov">          0 :         state_vec_67 &lt;=</span></a>
+<a name="2385"><span class="lineNum">    2385 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2386"><span class="lineNum">    2386 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_67[1],</span></a>
+<a name="2387"><span class="lineNum">    2387 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_67[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2388"><span class="lineNum">    2388 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h44)</span></a>
+<a name="2389"><span class="lineNum">    2389 </span><span class="lineNoCov">          0 :         state_vec_68 &lt;=</span></a>
+<a name="2390"><span class="lineNum">    2390 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2391"><span class="lineNum">    2391 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_68[1],</span></a>
+<a name="2392"><span class="lineNum">    2392 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_68[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2393"><span class="lineNum">    2393 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h45)</span></a>
+<a name="2394"><span class="lineNum">    2394 </span><span class="lineNoCov">          0 :         state_vec_69 &lt;=</span></a>
+<a name="2395"><span class="lineNum">    2395 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2396"><span class="lineNum">    2396 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_69[1],</span></a>
+<a name="2397"><span class="lineNum">    2397 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_69[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2398"><span class="lineNum">    2398 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h46)</span></a>
+<a name="2399"><span class="lineNum">    2399 </span><span class="lineNoCov">          0 :         state_vec_70 &lt;=</span></a>
+<a name="2400"><span class="lineNum">    2400 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2401"><span class="lineNum">    2401 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_70[1],</span></a>
+<a name="2402"><span class="lineNum">    2402 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_70[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2403"><span class="lineNum">    2403 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h47)</span></a>
+<a name="2404"><span class="lineNum">    2404 </span><span class="lineNoCov">          0 :         state_vec_71 &lt;=</span></a>
+<a name="2405"><span class="lineNum">    2405 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2406"><span class="lineNum">    2406 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_71[1],</span></a>
+<a name="2407"><span class="lineNum">    2407 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_71[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2408"><span class="lineNum">    2408 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h48)</span></a>
+<a name="2409"><span class="lineNum">    2409 </span><span class="lineNoCov">          0 :         state_vec_72 &lt;=</span></a>
+<a name="2410"><span class="lineNum">    2410 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2411"><span class="lineNum">    2411 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_72[1],</span></a>
+<a name="2412"><span class="lineNum">    2412 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_72[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2413"><span class="lineNum">    2413 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h49)</span></a>
+<a name="2414"><span class="lineNum">    2414 </span><span class="lineNoCov">          0 :         state_vec_73 &lt;=</span></a>
+<a name="2415"><span class="lineNum">    2415 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2416"><span class="lineNum">    2416 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_73[1],</span></a>
+<a name="2417"><span class="lineNum">    2417 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_73[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2418"><span class="lineNum">    2418 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h4A)</span></a>
+<a name="2419"><span class="lineNum">    2419 </span><span class="lineNoCov">          0 :         state_vec_74 &lt;=</span></a>
+<a name="2420"><span class="lineNum">    2420 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2421"><span class="lineNum">    2421 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_74[1],</span></a>
+<a name="2422"><span class="lineNum">    2422 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_74[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2423"><span class="lineNum">    2423 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h4B)</span></a>
+<a name="2424"><span class="lineNum">    2424 </span><span class="lineNoCov">          0 :         state_vec_75 &lt;=</span></a>
+<a name="2425"><span class="lineNum">    2425 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2426"><span class="lineNum">    2426 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_75[1],</span></a>
+<a name="2427"><span class="lineNum">    2427 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_75[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2428"><span class="lineNum">    2428 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h4C)</span></a>
+<a name="2429"><span class="lineNum">    2429 </span><span class="lineNoCov">          0 :         state_vec_76 &lt;=</span></a>
+<a name="2430"><span class="lineNum">    2430 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2431"><span class="lineNum">    2431 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_76[1],</span></a>
+<a name="2432"><span class="lineNum">    2432 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_76[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2433"><span class="lineNum">    2433 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h4D)</span></a>
+<a name="2434"><span class="lineNum">    2434 </span><span class="lineNoCov">          0 :         state_vec_77 &lt;=</span></a>
+<a name="2435"><span class="lineNum">    2435 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2436"><span class="lineNum">    2436 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_77[1],</span></a>
+<a name="2437"><span class="lineNum">    2437 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_77[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2438"><span class="lineNum">    2438 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h4E)</span></a>
+<a name="2439"><span class="lineNum">    2439 </span><span class="lineNoCov">          0 :         state_vec_78 &lt;=</span></a>
+<a name="2440"><span class="lineNum">    2440 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2441"><span class="lineNum">    2441 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_78[1],</span></a>
+<a name="2442"><span class="lineNum">    2442 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_78[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2443"><span class="lineNum">    2443 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h4F)</span></a>
+<a name="2444"><span class="lineNum">    2444 </span><span class="lineNoCov">          0 :         state_vec_79 &lt;=</span></a>
+<a name="2445"><span class="lineNum">    2445 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2446"><span class="lineNum">    2446 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_79[1],</span></a>
+<a name="2447"><span class="lineNum">    2447 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_79[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2448"><span class="lineNum">    2448 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h50)</span></a>
+<a name="2449"><span class="lineNum">    2449 </span><span class="lineNoCov">          0 :         state_vec_80 &lt;=</span></a>
+<a name="2450"><span class="lineNum">    2450 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2451"><span class="lineNum">    2451 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_80[1],</span></a>
+<a name="2452"><span class="lineNum">    2452 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_80[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2453"><span class="lineNum">    2453 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h51)</span></a>
+<a name="2454"><span class="lineNum">    2454 </span><span class="lineNoCov">          0 :         state_vec_81 &lt;=</span></a>
+<a name="2455"><span class="lineNum">    2455 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2456"><span class="lineNum">    2456 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_81[1],</span></a>
+<a name="2457"><span class="lineNum">    2457 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_81[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2458"><span class="lineNum">    2458 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h52)</span></a>
+<a name="2459"><span class="lineNum">    2459 </span><span class="lineNoCov">          0 :         state_vec_82 &lt;=</span></a>
+<a name="2460"><span class="lineNum">    2460 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2461"><span class="lineNum">    2461 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_82[1],</span></a>
+<a name="2462"><span class="lineNum">    2462 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_82[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2463"><span class="lineNum">    2463 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h53)</span></a>
+<a name="2464"><span class="lineNum">    2464 </span><span class="lineNoCov">          0 :         state_vec_83 &lt;=</span></a>
+<a name="2465"><span class="lineNum">    2465 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2466"><span class="lineNum">    2466 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_83[1],</span></a>
+<a name="2467"><span class="lineNum">    2467 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_83[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2468"><span class="lineNum">    2468 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h54)</span></a>
+<a name="2469"><span class="lineNum">    2469 </span><span class="lineNoCov">          0 :         state_vec_84 &lt;=</span></a>
+<a name="2470"><span class="lineNum">    2470 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2471"><span class="lineNum">    2471 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_84[1],</span></a>
+<a name="2472"><span class="lineNum">    2472 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_84[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2473"><span class="lineNum">    2473 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h55)</span></a>
+<a name="2474"><span class="lineNum">    2474 </span><span class="lineNoCov">          0 :         state_vec_85 &lt;=</span></a>
+<a name="2475"><span class="lineNum">    2475 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2476"><span class="lineNum">    2476 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_85[1],</span></a>
+<a name="2477"><span class="lineNum">    2477 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_85[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2478"><span class="lineNum">    2478 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h56)</span></a>
+<a name="2479"><span class="lineNum">    2479 </span><span class="lineNoCov">          0 :         state_vec_86 &lt;=</span></a>
+<a name="2480"><span class="lineNum">    2480 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2481"><span class="lineNum">    2481 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_86[1],</span></a>
+<a name="2482"><span class="lineNum">    2482 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_86[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2483"><span class="lineNum">    2483 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h57)</span></a>
+<a name="2484"><span class="lineNum">    2484 </span><span class="lineNoCov">          0 :         state_vec_87 &lt;=</span></a>
+<a name="2485"><span class="lineNum">    2485 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2486"><span class="lineNum">    2486 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_87[1],</span></a>
+<a name="2487"><span class="lineNum">    2487 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_87[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2488"><span class="lineNum">    2488 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h58)</span></a>
+<a name="2489"><span class="lineNum">    2489 </span><span class="lineNoCov">          0 :         state_vec_88 &lt;=</span></a>
+<a name="2490"><span class="lineNum">    2490 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2491"><span class="lineNum">    2491 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_88[1],</span></a>
+<a name="2492"><span class="lineNum">    2492 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_88[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2493"><span class="lineNum">    2493 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h59)</span></a>
+<a name="2494"><span class="lineNum">    2494 </span><span class="lineNoCov">          0 :         state_vec_89 &lt;=</span></a>
+<a name="2495"><span class="lineNum">    2495 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2496"><span class="lineNum">    2496 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_89[1],</span></a>
+<a name="2497"><span class="lineNum">    2497 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_89[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2498"><span class="lineNum">    2498 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h5A)</span></a>
+<a name="2499"><span class="lineNum">    2499 </span><span class="lineNoCov">          0 :         state_vec_90 &lt;=</span></a>
+<a name="2500"><span class="lineNum">    2500 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2501"><span class="lineNum">    2501 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_90[1],</span></a>
+<a name="2502"><span class="lineNum">    2502 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_90[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2503"><span class="lineNum">    2503 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h5B)</span></a>
+<a name="2504"><span class="lineNum">    2504 </span><span class="lineNoCov">          0 :         state_vec_91 &lt;=</span></a>
+<a name="2505"><span class="lineNum">    2505 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2506"><span class="lineNum">    2506 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_91[1],</span></a>
+<a name="2507"><span class="lineNum">    2507 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_91[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2508"><span class="lineNum">    2508 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h5C)</span></a>
+<a name="2509"><span class="lineNum">    2509 </span><span class="lineNoCov">          0 :         state_vec_92 &lt;=</span></a>
+<a name="2510"><span class="lineNum">    2510 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2511"><span class="lineNum">    2511 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_92[1],</span></a>
+<a name="2512"><span class="lineNum">    2512 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_92[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2513"><span class="lineNum">    2513 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h5D)</span></a>
+<a name="2514"><span class="lineNum">    2514 </span><span class="lineNoCov">          0 :         state_vec_93 &lt;=</span></a>
+<a name="2515"><span class="lineNum">    2515 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2516"><span class="lineNum">    2516 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_93[1],</span></a>
+<a name="2517"><span class="lineNum">    2517 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_93[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2518"><span class="lineNum">    2518 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h5E)</span></a>
+<a name="2519"><span class="lineNum">    2519 </span><span class="lineNoCov">          0 :         state_vec_94 &lt;=</span></a>
+<a name="2520"><span class="lineNum">    2520 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2521"><span class="lineNum">    2521 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_94[1],</span></a>
+<a name="2522"><span class="lineNum">    2522 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_94[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2523"><span class="lineNum">    2523 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h5F)</span></a>
+<a name="2524"><span class="lineNum">    2524 </span><span class="lineNoCov">          0 :         state_vec_95 &lt;=</span></a>
+<a name="2525"><span class="lineNum">    2525 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2526"><span class="lineNum">    2526 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_95[1],</span></a>
+<a name="2527"><span class="lineNum">    2527 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_95[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2528"><span class="lineNum">    2528 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h60)</span></a>
+<a name="2529"><span class="lineNum">    2529 </span><span class="lineNoCov">          0 :         state_vec_96 &lt;=</span></a>
+<a name="2530"><span class="lineNum">    2530 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2531"><span class="lineNum">    2531 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_96[1],</span></a>
+<a name="2532"><span class="lineNum">    2532 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_96[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2533"><span class="lineNum">    2533 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h61)</span></a>
+<a name="2534"><span class="lineNum">    2534 </span><span class="lineNoCov">          0 :         state_vec_97 &lt;=</span></a>
+<a name="2535"><span class="lineNum">    2535 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2536"><span class="lineNum">    2536 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_97[1],</span></a>
+<a name="2537"><span class="lineNum">    2537 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_97[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2538"><span class="lineNum">    2538 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h62)</span></a>
+<a name="2539"><span class="lineNum">    2539 </span><span class="lineNoCov">          0 :         state_vec_98 &lt;=</span></a>
+<a name="2540"><span class="lineNum">    2540 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2541"><span class="lineNum">    2541 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_98[1],</span></a>
+<a name="2542"><span class="lineNum">    2542 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_98[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2543"><span class="lineNum">    2543 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h63)</span></a>
+<a name="2544"><span class="lineNum">    2544 </span><span class="lineNoCov">          0 :         state_vec_99 &lt;=</span></a>
+<a name="2545"><span class="lineNum">    2545 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2546"><span class="lineNum">    2546 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_99[1],</span></a>
+<a name="2547"><span class="lineNum">    2547 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_99[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2548"><span class="lineNum">    2548 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h64)</span></a>
+<a name="2549"><span class="lineNum">    2549 </span><span class="lineNoCov">          0 :         state_vec_100 &lt;=</span></a>
+<a name="2550"><span class="lineNum">    2550 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2551"><span class="lineNum">    2551 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_100[1],</span></a>
+<a name="2552"><span class="lineNum">    2552 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_100[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2553"><span class="lineNum">    2553 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h65)</span></a>
+<a name="2554"><span class="lineNum">    2554 </span><span class="lineNoCov">          0 :         state_vec_101 &lt;=</span></a>
+<a name="2555"><span class="lineNum">    2555 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2556"><span class="lineNum">    2556 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_101[1],</span></a>
+<a name="2557"><span class="lineNum">    2557 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_101[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2558"><span class="lineNum">    2558 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h66)</span></a>
+<a name="2559"><span class="lineNum">    2559 </span><span class="lineNoCov">          0 :         state_vec_102 &lt;=</span></a>
+<a name="2560"><span class="lineNum">    2560 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2561"><span class="lineNum">    2561 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_102[1],</span></a>
+<a name="2562"><span class="lineNum">    2562 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_102[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2563"><span class="lineNum">    2563 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h67)</span></a>
+<a name="2564"><span class="lineNum">    2564 </span><span class="lineNoCov">          0 :         state_vec_103 &lt;=</span></a>
+<a name="2565"><span class="lineNum">    2565 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2566"><span class="lineNum">    2566 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_103[1],</span></a>
+<a name="2567"><span class="lineNum">    2567 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_103[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2568"><span class="lineNum">    2568 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h68)</span></a>
+<a name="2569"><span class="lineNum">    2569 </span><span class="lineNoCov">          0 :         state_vec_104 &lt;=</span></a>
+<a name="2570"><span class="lineNum">    2570 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2571"><span class="lineNum">    2571 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_104[1],</span></a>
+<a name="2572"><span class="lineNum">    2572 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_104[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2573"><span class="lineNum">    2573 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h69)</span></a>
+<a name="2574"><span class="lineNum">    2574 </span><span class="lineNoCov">          0 :         state_vec_105 &lt;=</span></a>
+<a name="2575"><span class="lineNum">    2575 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2576"><span class="lineNum">    2576 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_105[1],</span></a>
+<a name="2577"><span class="lineNum">    2577 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_105[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2578"><span class="lineNum">    2578 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h6A)</span></a>
+<a name="2579"><span class="lineNum">    2579 </span><span class="lineNoCov">          0 :         state_vec_106 &lt;=</span></a>
+<a name="2580"><span class="lineNum">    2580 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2581"><span class="lineNum">    2581 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_106[1],</span></a>
+<a name="2582"><span class="lineNum">    2582 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_106[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2583"><span class="lineNum">    2583 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h6B)</span></a>
+<a name="2584"><span class="lineNum">    2584 </span><span class="lineNoCov">          0 :         state_vec_107 &lt;=</span></a>
+<a name="2585"><span class="lineNum">    2585 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2586"><span class="lineNum">    2586 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_107[1],</span></a>
+<a name="2587"><span class="lineNum">    2587 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_107[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2588"><span class="lineNum">    2588 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h6C)</span></a>
+<a name="2589"><span class="lineNum">    2589 </span><span class="lineNoCov">          0 :         state_vec_108 &lt;=</span></a>
+<a name="2590"><span class="lineNum">    2590 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2591"><span class="lineNum">    2591 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_108[1],</span></a>
+<a name="2592"><span class="lineNum">    2592 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_108[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2593"><span class="lineNum">    2593 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h6D)</span></a>
+<a name="2594"><span class="lineNum">    2594 </span><span class="lineNoCov">          0 :         state_vec_109 &lt;=</span></a>
+<a name="2595"><span class="lineNum">    2595 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2596"><span class="lineNum">    2596 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_109[1],</span></a>
+<a name="2597"><span class="lineNum">    2597 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_109[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2598"><span class="lineNum">    2598 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h6E)</span></a>
+<a name="2599"><span class="lineNum">    2599 </span><span class="lineNoCov">          0 :         state_vec_110 &lt;=</span></a>
+<a name="2600"><span class="lineNum">    2600 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2601"><span class="lineNum">    2601 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_110[1],</span></a>
+<a name="2602"><span class="lineNum">    2602 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_110[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2603"><span class="lineNum">    2603 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h6F)</span></a>
+<a name="2604"><span class="lineNum">    2604 </span><span class="lineNoCov">          0 :         state_vec_111 &lt;=</span></a>
+<a name="2605"><span class="lineNum">    2605 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2606"><span class="lineNum">    2606 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_111[1],</span></a>
+<a name="2607"><span class="lineNum">    2607 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_111[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2608"><span class="lineNum">    2608 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h70)</span></a>
+<a name="2609"><span class="lineNum">    2609 </span><span class="lineNoCov">          0 :         state_vec_112 &lt;=</span></a>
+<a name="2610"><span class="lineNum">    2610 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2611"><span class="lineNum">    2611 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_112[1],</span></a>
+<a name="2612"><span class="lineNum">    2612 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_112[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2613"><span class="lineNum">    2613 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h71)</span></a>
+<a name="2614"><span class="lineNum">    2614 </span><span class="lineNoCov">          0 :         state_vec_113 &lt;=</span></a>
+<a name="2615"><span class="lineNum">    2615 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2616"><span class="lineNum">    2616 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_113[1],</span></a>
+<a name="2617"><span class="lineNum">    2617 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_113[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2618"><span class="lineNum">    2618 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h72)</span></a>
+<a name="2619"><span class="lineNum">    2619 </span><span class="lineNoCov">          0 :         state_vec_114 &lt;=</span></a>
+<a name="2620"><span class="lineNum">    2620 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2621"><span class="lineNum">    2621 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_114[1],</span></a>
+<a name="2622"><span class="lineNum">    2622 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_114[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2623"><span class="lineNum">    2623 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h73)</span></a>
+<a name="2624"><span class="lineNum">    2624 </span><span class="lineNoCov">          0 :         state_vec_115 &lt;=</span></a>
+<a name="2625"><span class="lineNum">    2625 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2626"><span class="lineNum">    2626 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_115[1],</span></a>
+<a name="2627"><span class="lineNum">    2627 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_115[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2628"><span class="lineNum">    2628 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h74)</span></a>
+<a name="2629"><span class="lineNum">    2629 </span><span class="lineNoCov">          0 :         state_vec_116 &lt;=</span></a>
+<a name="2630"><span class="lineNum">    2630 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2631"><span class="lineNum">    2631 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_116[1],</span></a>
+<a name="2632"><span class="lineNum">    2632 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_116[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2633"><span class="lineNum">    2633 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h75)</span></a>
+<a name="2634"><span class="lineNum">    2634 </span><span class="lineNoCov">          0 :         state_vec_117 &lt;=</span></a>
+<a name="2635"><span class="lineNum">    2635 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2636"><span class="lineNum">    2636 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_117[1],</span></a>
+<a name="2637"><span class="lineNum">    2637 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_117[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2638"><span class="lineNum">    2638 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h76)</span></a>
+<a name="2639"><span class="lineNum">    2639 </span><span class="lineNoCov">          0 :         state_vec_118 &lt;=</span></a>
+<a name="2640"><span class="lineNum">    2640 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2641"><span class="lineNum">    2641 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_118[1],</span></a>
+<a name="2642"><span class="lineNum">    2642 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_118[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2643"><span class="lineNum">    2643 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h77)</span></a>
+<a name="2644"><span class="lineNum">    2644 </span><span class="lineNoCov">          0 :         state_vec_119 &lt;=</span></a>
+<a name="2645"><span class="lineNum">    2645 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2646"><span class="lineNum">    2646 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_119[1],</span></a>
+<a name="2647"><span class="lineNum">    2647 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_119[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2648"><span class="lineNum">    2648 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h78)</span></a>
+<a name="2649"><span class="lineNum">    2649 </span><span class="lineNoCov">          0 :         state_vec_120 &lt;=</span></a>
+<a name="2650"><span class="lineNum">    2650 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2651"><span class="lineNum">    2651 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_120[1],</span></a>
+<a name="2652"><span class="lineNum">    2652 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_120[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2653"><span class="lineNum">    2653 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h79)</span></a>
+<a name="2654"><span class="lineNum">    2654 </span><span class="lineNoCov">          0 :         state_vec_121 &lt;=</span></a>
+<a name="2655"><span class="lineNum">    2655 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2656"><span class="lineNum">    2656 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_121[1],</span></a>
+<a name="2657"><span class="lineNum">    2657 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_121[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2658"><span class="lineNum">    2658 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h7A)</span></a>
+<a name="2659"><span class="lineNum">    2659 </span><span class="lineNoCov">          0 :         state_vec_122 &lt;=</span></a>
+<a name="2660"><span class="lineNum">    2660 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2661"><span class="lineNum">    2661 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_122[1],</span></a>
+<a name="2662"><span class="lineNum">    2662 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_122[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2663"><span class="lineNum">    2663 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h7B)</span></a>
+<a name="2664"><span class="lineNum">    2664 </span><span class="lineNoCov">          0 :         state_vec_123 &lt;=</span></a>
+<a name="2665"><span class="lineNum">    2665 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2666"><span class="lineNum">    2666 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_123[1],</span></a>
+<a name="2667"><span class="lineNum">    2667 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_123[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2668"><span class="lineNum">    2668 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h7C)</span></a>
+<a name="2669"><span class="lineNum">    2669 </span><span class="lineNoCov">          0 :         state_vec_124 &lt;=</span></a>
+<a name="2670"><span class="lineNum">    2670 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2671"><span class="lineNum">    2671 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_124[1],</span></a>
+<a name="2672"><span class="lineNum">    2672 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_124[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2673"><span class="lineNum">    2673 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h7D)</span></a>
+<a name="2674"><span class="lineNum">    2674 </span><span class="lineNoCov">          0 :         state_vec_125 &lt;=</span></a>
+<a name="2675"><span class="lineNum">    2675 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2676"><span class="lineNum">    2676 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_125[1],</span></a>
+<a name="2677"><span class="lineNum">    2677 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_125[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2678"><span class="lineNum">    2678 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h7E)</span></a>
+<a name="2679"><span class="lineNum">    2679 </span><span class="lineNoCov">          0 :         state_vec_126 &lt;=</span></a>
+<a name="2680"><span class="lineNum">    2680 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2681"><span class="lineNum">    2681 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_126[1],</span></a>
+<a name="2682"><span class="lineNum">    2682 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_126[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2683"><span class="lineNum">    2683 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h7F)</span></a>
+<a name="2684"><span class="lineNum">    2684 </span><span class="lineNoCov">          0 :         state_vec_127 &lt;=</span></a>
+<a name="2685"><span class="lineNum">    2685 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2686"><span class="lineNum">    2686 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_127[1],</span></a>
+<a name="2687"><span class="lineNum">    2687 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_127[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2688"><span class="lineNum">    2688 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h80)</span></a>
+<a name="2689"><span class="lineNum">    2689 </span><span class="lineNoCov">          0 :         state_vec_128 &lt;=</span></a>
+<a name="2690"><span class="lineNum">    2690 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2691"><span class="lineNum">    2691 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_128[1],</span></a>
+<a name="2692"><span class="lineNum">    2692 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_128[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2693"><span class="lineNum">    2693 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h81)</span></a>
+<a name="2694"><span class="lineNum">    2694 </span><span class="lineNoCov">          0 :         state_vec_129 &lt;=</span></a>
+<a name="2695"><span class="lineNum">    2695 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2696"><span class="lineNum">    2696 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_129[1],</span></a>
+<a name="2697"><span class="lineNum">    2697 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_129[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2698"><span class="lineNum">    2698 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h82)</span></a>
+<a name="2699"><span class="lineNum">    2699 </span><span class="lineNoCov">          0 :         state_vec_130 &lt;=</span></a>
+<a name="2700"><span class="lineNum">    2700 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2701"><span class="lineNum">    2701 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_130[1],</span></a>
+<a name="2702"><span class="lineNum">    2702 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_130[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2703"><span class="lineNum">    2703 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h83)</span></a>
+<a name="2704"><span class="lineNum">    2704 </span><span class="lineNoCov">          0 :         state_vec_131 &lt;=</span></a>
+<a name="2705"><span class="lineNum">    2705 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2706"><span class="lineNum">    2706 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_131[1],</span></a>
+<a name="2707"><span class="lineNum">    2707 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_131[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2708"><span class="lineNum">    2708 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h84)</span></a>
+<a name="2709"><span class="lineNum">    2709 </span><span class="lineNoCov">          0 :         state_vec_132 &lt;=</span></a>
+<a name="2710"><span class="lineNum">    2710 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2711"><span class="lineNum">    2711 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_132[1],</span></a>
+<a name="2712"><span class="lineNum">    2712 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_132[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2713"><span class="lineNum">    2713 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h85)</span></a>
+<a name="2714"><span class="lineNum">    2714 </span><span class="lineNoCov">          0 :         state_vec_133 &lt;=</span></a>
+<a name="2715"><span class="lineNum">    2715 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2716"><span class="lineNum">    2716 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_133[1],</span></a>
+<a name="2717"><span class="lineNum">    2717 </span><span class="lineCov">          2 :            touch_way_0_bits[1] ? state_vec_133[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2718"><span class="lineNum">    2718 </span><span class="lineCov">          1 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h86)</span></a>
+<a name="2719"><span class="lineNum">    2719 </span><span class="lineCov">          1 :         state_vec_134 &lt;=</span></a>
+<a name="2720"><span class="lineNum">    2720 </span><span class="lineCov">          1 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2721"><span class="lineNum">    2721 </span><span class="lineCov">          1 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_134[1],</span></a>
+<a name="2722"><span class="lineNum">    2722 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_134[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2723"><span class="lineNum">    2723 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h87)</span></a>
+<a name="2724"><span class="lineNum">    2724 </span><span class="lineNoCov">          0 :         state_vec_135 &lt;=</span></a>
+<a name="2725"><span class="lineNum">    2725 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2726"><span class="lineNum">    2726 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_135[1],</span></a>
+<a name="2727"><span class="lineNum">    2727 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_135[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2728"><span class="lineNum">    2728 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h88)</span></a>
+<a name="2729"><span class="lineNum">    2729 </span><span class="lineNoCov">          0 :         state_vec_136 &lt;=</span></a>
+<a name="2730"><span class="lineNum">    2730 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2731"><span class="lineNum">    2731 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_136[1],</span></a>
+<a name="2732"><span class="lineNum">    2732 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_136[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2733"><span class="lineNum">    2733 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h89)</span></a>
+<a name="2734"><span class="lineNum">    2734 </span><span class="lineNoCov">          0 :         state_vec_137 &lt;=</span></a>
+<a name="2735"><span class="lineNum">    2735 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2736"><span class="lineNum">    2736 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_137[1],</span></a>
+<a name="2737"><span class="lineNum">    2737 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_137[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2738"><span class="lineNum">    2738 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h8A)</span></a>
+<a name="2739"><span class="lineNum">    2739 </span><span class="lineNoCov">          0 :         state_vec_138 &lt;=</span></a>
+<a name="2740"><span class="lineNum">    2740 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2741"><span class="lineNum">    2741 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_138[1],</span></a>
+<a name="2742"><span class="lineNum">    2742 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_138[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2743"><span class="lineNum">    2743 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h8B)</span></a>
+<a name="2744"><span class="lineNum">    2744 </span><span class="lineNoCov">          0 :         state_vec_139 &lt;=</span></a>
+<a name="2745"><span class="lineNum">    2745 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2746"><span class="lineNum">    2746 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_139[1],</span></a>
+<a name="2747"><span class="lineNum">    2747 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_139[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2748"><span class="lineNum">    2748 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h8C)</span></a>
+<a name="2749"><span class="lineNum">    2749 </span><span class="lineNoCov">          0 :         state_vec_140 &lt;=</span></a>
+<a name="2750"><span class="lineNum">    2750 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2751"><span class="lineNum">    2751 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_140[1],</span></a>
+<a name="2752"><span class="lineNum">    2752 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_140[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2753"><span class="lineNum">    2753 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h8D)</span></a>
+<a name="2754"><span class="lineNum">    2754 </span><span class="lineNoCov">          0 :         state_vec_141 &lt;=</span></a>
+<a name="2755"><span class="lineNum">    2755 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2756"><span class="lineNum">    2756 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_141[1],</span></a>
+<a name="2757"><span class="lineNum">    2757 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_141[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2758"><span class="lineNum">    2758 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h8E)</span></a>
+<a name="2759"><span class="lineNum">    2759 </span><span class="lineNoCov">          0 :         state_vec_142 &lt;=</span></a>
+<a name="2760"><span class="lineNum">    2760 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2761"><span class="lineNum">    2761 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_142[1],</span></a>
+<a name="2762"><span class="lineNum">    2762 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_142[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2763"><span class="lineNum">    2763 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h8F)</span></a>
+<a name="2764"><span class="lineNum">    2764 </span><span class="lineNoCov">          0 :         state_vec_143 &lt;=</span></a>
+<a name="2765"><span class="lineNum">    2765 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2766"><span class="lineNum">    2766 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_143[1],</span></a>
+<a name="2767"><span class="lineNum">    2767 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_143[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2768"><span class="lineNum">    2768 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h90)</span></a>
+<a name="2769"><span class="lineNum">    2769 </span><span class="lineNoCov">          0 :         state_vec_144 &lt;=</span></a>
+<a name="2770"><span class="lineNum">    2770 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2771"><span class="lineNum">    2771 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_144[1],</span></a>
+<a name="2772"><span class="lineNum">    2772 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_144[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2773"><span class="lineNum">    2773 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h91)</span></a>
+<a name="2774"><span class="lineNum">    2774 </span><span class="lineNoCov">          0 :         state_vec_145 &lt;=</span></a>
+<a name="2775"><span class="lineNum">    2775 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2776"><span class="lineNum">    2776 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_145[1],</span></a>
+<a name="2777"><span class="lineNum">    2777 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_145[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2778"><span class="lineNum">    2778 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h92)</span></a>
+<a name="2779"><span class="lineNum">    2779 </span><span class="lineNoCov">          0 :         state_vec_146 &lt;=</span></a>
+<a name="2780"><span class="lineNum">    2780 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2781"><span class="lineNum">    2781 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_146[1],</span></a>
+<a name="2782"><span class="lineNum">    2782 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_146[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2783"><span class="lineNum">    2783 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h93)</span></a>
+<a name="2784"><span class="lineNum">    2784 </span><span class="lineNoCov">          0 :         state_vec_147 &lt;=</span></a>
+<a name="2785"><span class="lineNum">    2785 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2786"><span class="lineNum">    2786 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_147[1],</span></a>
+<a name="2787"><span class="lineNum">    2787 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_147[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2788"><span class="lineNum">    2788 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h94)</span></a>
+<a name="2789"><span class="lineNum">    2789 </span><span class="lineNoCov">          0 :         state_vec_148 &lt;=</span></a>
+<a name="2790"><span class="lineNum">    2790 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2791"><span class="lineNum">    2791 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_148[1],</span></a>
+<a name="2792"><span class="lineNum">    2792 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_148[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2793"><span class="lineNum">    2793 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h95)</span></a>
+<a name="2794"><span class="lineNum">    2794 </span><span class="lineNoCov">          0 :         state_vec_149 &lt;=</span></a>
+<a name="2795"><span class="lineNum">    2795 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2796"><span class="lineNum">    2796 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_149[1],</span></a>
+<a name="2797"><span class="lineNum">    2797 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_149[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2798"><span class="lineNum">    2798 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h96)</span></a>
+<a name="2799"><span class="lineNum">    2799 </span><span class="lineNoCov">          0 :         state_vec_150 &lt;=</span></a>
+<a name="2800"><span class="lineNum">    2800 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2801"><span class="lineNum">    2801 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_150[1],</span></a>
+<a name="2802"><span class="lineNum">    2802 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_150[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2803"><span class="lineNum">    2803 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h97)</span></a>
+<a name="2804"><span class="lineNum">    2804 </span><span class="lineNoCov">          0 :         state_vec_151 &lt;=</span></a>
+<a name="2805"><span class="lineNum">    2805 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2806"><span class="lineNum">    2806 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_151[1],</span></a>
+<a name="2807"><span class="lineNum">    2807 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_151[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2808"><span class="lineNum">    2808 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h98)</span></a>
+<a name="2809"><span class="lineNum">    2809 </span><span class="lineNoCov">          0 :         state_vec_152 &lt;=</span></a>
+<a name="2810"><span class="lineNum">    2810 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2811"><span class="lineNum">    2811 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_152[1],</span></a>
+<a name="2812"><span class="lineNum">    2812 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_152[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2813"><span class="lineNum">    2813 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h99)</span></a>
+<a name="2814"><span class="lineNum">    2814 </span><span class="lineNoCov">          0 :         state_vec_153 &lt;=</span></a>
+<a name="2815"><span class="lineNum">    2815 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2816"><span class="lineNum">    2816 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_153[1],</span></a>
+<a name="2817"><span class="lineNum">    2817 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_153[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2818"><span class="lineNum">    2818 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h9A)</span></a>
+<a name="2819"><span class="lineNum">    2819 </span><span class="lineNoCov">          0 :         state_vec_154 &lt;=</span></a>
+<a name="2820"><span class="lineNum">    2820 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2821"><span class="lineNum">    2821 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_154[1],</span></a>
+<a name="2822"><span class="lineNum">    2822 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_154[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2823"><span class="lineNum">    2823 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h9B)</span></a>
+<a name="2824"><span class="lineNum">    2824 </span><span class="lineNoCov">          0 :         state_vec_155 &lt;=</span></a>
+<a name="2825"><span class="lineNum">    2825 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2826"><span class="lineNum">    2826 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_155[1],</span></a>
+<a name="2827"><span class="lineNum">    2827 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_155[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2828"><span class="lineNum">    2828 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h9C)</span></a>
+<a name="2829"><span class="lineNum">    2829 </span><span class="lineNoCov">          0 :         state_vec_156 &lt;=</span></a>
+<a name="2830"><span class="lineNum">    2830 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2831"><span class="lineNum">    2831 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_156[1],</span></a>
+<a name="2832"><span class="lineNum">    2832 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_156[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2833"><span class="lineNum">    2833 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h9D)</span></a>
+<a name="2834"><span class="lineNum">    2834 </span><span class="lineNoCov">          0 :         state_vec_157 &lt;=</span></a>
+<a name="2835"><span class="lineNum">    2835 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2836"><span class="lineNum">    2836 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_157[1],</span></a>
+<a name="2837"><span class="lineNum">    2837 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_157[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2838"><span class="lineNum">    2838 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h9E)</span></a>
+<a name="2839"><span class="lineNum">    2839 </span><span class="lineNoCov">          0 :         state_vec_158 &lt;=</span></a>
+<a name="2840"><span class="lineNum">    2840 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2841"><span class="lineNum">    2841 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_158[1],</span></a>
+<a name="2842"><span class="lineNum">    2842 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_158[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2843"><span class="lineNum">    2843 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h9F)</span></a>
+<a name="2844"><span class="lineNum">    2844 </span><span class="lineNoCov">          0 :         state_vec_159 &lt;=</span></a>
+<a name="2845"><span class="lineNum">    2845 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2846"><span class="lineNum">    2846 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_159[1],</span></a>
+<a name="2847"><span class="lineNum">    2847 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_159[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2848"><span class="lineNum">    2848 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hA0)</span></a>
+<a name="2849"><span class="lineNum">    2849 </span><span class="lineNoCov">          0 :         state_vec_160 &lt;=</span></a>
+<a name="2850"><span class="lineNum">    2850 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2851"><span class="lineNum">    2851 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_160[1],</span></a>
+<a name="2852"><span class="lineNum">    2852 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_160[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2853"><span class="lineNum">    2853 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hA1)</span></a>
+<a name="2854"><span class="lineNum">    2854 </span><span class="lineNoCov">          0 :         state_vec_161 &lt;=</span></a>
+<a name="2855"><span class="lineNum">    2855 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2856"><span class="lineNum">    2856 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_161[1],</span></a>
+<a name="2857"><span class="lineNum">    2857 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_161[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2858"><span class="lineNum">    2858 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hA2)</span></a>
+<a name="2859"><span class="lineNum">    2859 </span><span class="lineNoCov">          0 :         state_vec_162 &lt;=</span></a>
+<a name="2860"><span class="lineNum">    2860 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2861"><span class="lineNum">    2861 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_162[1],</span></a>
+<a name="2862"><span class="lineNum">    2862 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_162[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2863"><span class="lineNum">    2863 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hA3)</span></a>
+<a name="2864"><span class="lineNum">    2864 </span><span class="lineNoCov">          0 :         state_vec_163 &lt;=</span></a>
+<a name="2865"><span class="lineNum">    2865 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2866"><span class="lineNum">    2866 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_163[1],</span></a>
+<a name="2867"><span class="lineNum">    2867 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_163[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2868"><span class="lineNum">    2868 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hA4)</span></a>
+<a name="2869"><span class="lineNum">    2869 </span><span class="lineNoCov">          0 :         state_vec_164 &lt;=</span></a>
+<a name="2870"><span class="lineNum">    2870 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2871"><span class="lineNum">    2871 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_164[1],</span></a>
+<a name="2872"><span class="lineNum">    2872 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_164[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2873"><span class="lineNum">    2873 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hA5)</span></a>
+<a name="2874"><span class="lineNum">    2874 </span><span class="lineNoCov">          0 :         state_vec_165 &lt;=</span></a>
+<a name="2875"><span class="lineNum">    2875 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2876"><span class="lineNum">    2876 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_165[1],</span></a>
+<a name="2877"><span class="lineNum">    2877 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_165[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2878"><span class="lineNum">    2878 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hA6)</span></a>
+<a name="2879"><span class="lineNum">    2879 </span><span class="lineNoCov">          0 :         state_vec_166 &lt;=</span></a>
+<a name="2880"><span class="lineNum">    2880 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2881"><span class="lineNum">    2881 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_166[1],</span></a>
+<a name="2882"><span class="lineNum">    2882 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_166[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2883"><span class="lineNum">    2883 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hA7)</span></a>
+<a name="2884"><span class="lineNum">    2884 </span><span class="lineNoCov">          0 :         state_vec_167 &lt;=</span></a>
+<a name="2885"><span class="lineNum">    2885 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2886"><span class="lineNum">    2886 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_167[1],</span></a>
+<a name="2887"><span class="lineNum">    2887 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_167[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2888"><span class="lineNum">    2888 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hA8)</span></a>
+<a name="2889"><span class="lineNum">    2889 </span><span class="lineNoCov">          0 :         state_vec_168 &lt;=</span></a>
+<a name="2890"><span class="lineNum">    2890 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2891"><span class="lineNum">    2891 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_168[1],</span></a>
+<a name="2892"><span class="lineNum">    2892 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_168[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2893"><span class="lineNum">    2893 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hA9)</span></a>
+<a name="2894"><span class="lineNum">    2894 </span><span class="lineNoCov">          0 :         state_vec_169 &lt;=</span></a>
+<a name="2895"><span class="lineNum">    2895 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2896"><span class="lineNum">    2896 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_169[1],</span></a>
+<a name="2897"><span class="lineNum">    2897 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_169[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2898"><span class="lineNum">    2898 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hAA)</span></a>
+<a name="2899"><span class="lineNum">    2899 </span><span class="lineNoCov">          0 :         state_vec_170 &lt;=</span></a>
+<a name="2900"><span class="lineNum">    2900 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2901"><span class="lineNum">    2901 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_170[1],</span></a>
+<a name="2902"><span class="lineNum">    2902 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_170[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2903"><span class="lineNum">    2903 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hAB)</span></a>
+<a name="2904"><span class="lineNum">    2904 </span><span class="lineNoCov">          0 :         state_vec_171 &lt;=</span></a>
+<a name="2905"><span class="lineNum">    2905 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2906"><span class="lineNum">    2906 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_171[1],</span></a>
+<a name="2907"><span class="lineNum">    2907 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_171[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2908"><span class="lineNum">    2908 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hAC)</span></a>
+<a name="2909"><span class="lineNum">    2909 </span><span class="lineNoCov">          0 :         state_vec_172 &lt;=</span></a>
+<a name="2910"><span class="lineNum">    2910 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2911"><span class="lineNum">    2911 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_172[1],</span></a>
+<a name="2912"><span class="lineNum">    2912 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_172[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2913"><span class="lineNum">    2913 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hAD)</span></a>
+<a name="2914"><span class="lineNum">    2914 </span><span class="lineNoCov">          0 :         state_vec_173 &lt;=</span></a>
+<a name="2915"><span class="lineNum">    2915 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2916"><span class="lineNum">    2916 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_173[1],</span></a>
+<a name="2917"><span class="lineNum">    2917 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_173[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2918"><span class="lineNum">    2918 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hAE)</span></a>
+<a name="2919"><span class="lineNum">    2919 </span><span class="lineNoCov">          0 :         state_vec_174 &lt;=</span></a>
+<a name="2920"><span class="lineNum">    2920 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2921"><span class="lineNum">    2921 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_174[1],</span></a>
+<a name="2922"><span class="lineNum">    2922 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_174[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2923"><span class="lineNum">    2923 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hAF)</span></a>
+<a name="2924"><span class="lineNum">    2924 </span><span class="lineNoCov">          0 :         state_vec_175 &lt;=</span></a>
+<a name="2925"><span class="lineNum">    2925 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2926"><span class="lineNum">    2926 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_175[1],</span></a>
+<a name="2927"><span class="lineNum">    2927 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_175[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2928"><span class="lineNum">    2928 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hB0)</span></a>
+<a name="2929"><span class="lineNum">    2929 </span><span class="lineNoCov">          0 :         state_vec_176 &lt;=</span></a>
+<a name="2930"><span class="lineNum">    2930 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2931"><span class="lineNum">    2931 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_176[1],</span></a>
+<a name="2932"><span class="lineNum">    2932 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_176[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2933"><span class="lineNum">    2933 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hB1)</span></a>
+<a name="2934"><span class="lineNum">    2934 </span><span class="lineNoCov">          0 :         state_vec_177 &lt;=</span></a>
+<a name="2935"><span class="lineNum">    2935 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2936"><span class="lineNum">    2936 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_177[1],</span></a>
+<a name="2937"><span class="lineNum">    2937 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_177[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2938"><span class="lineNum">    2938 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hB2)</span></a>
+<a name="2939"><span class="lineNum">    2939 </span><span class="lineNoCov">          0 :         state_vec_178 &lt;=</span></a>
+<a name="2940"><span class="lineNum">    2940 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2941"><span class="lineNum">    2941 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_178[1],</span></a>
+<a name="2942"><span class="lineNum">    2942 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_178[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2943"><span class="lineNum">    2943 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hB3)</span></a>
+<a name="2944"><span class="lineNum">    2944 </span><span class="lineNoCov">          0 :         state_vec_179 &lt;=</span></a>
+<a name="2945"><span class="lineNum">    2945 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2946"><span class="lineNum">    2946 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_179[1],</span></a>
+<a name="2947"><span class="lineNum">    2947 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_179[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2948"><span class="lineNum">    2948 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hB4)</span></a>
+<a name="2949"><span class="lineNum">    2949 </span><span class="lineNoCov">          0 :         state_vec_180 &lt;=</span></a>
+<a name="2950"><span class="lineNum">    2950 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2951"><span class="lineNum">    2951 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_180[1],</span></a>
+<a name="2952"><span class="lineNum">    2952 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_180[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2953"><span class="lineNum">    2953 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hB5)</span></a>
+<a name="2954"><span class="lineNum">    2954 </span><span class="lineNoCov">          0 :         state_vec_181 &lt;=</span></a>
+<a name="2955"><span class="lineNum">    2955 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2956"><span class="lineNum">    2956 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_181[1],</span></a>
+<a name="2957"><span class="lineNum">    2957 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_181[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2958"><span class="lineNum">    2958 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hB6)</span></a>
+<a name="2959"><span class="lineNum">    2959 </span><span class="lineNoCov">          0 :         state_vec_182 &lt;=</span></a>
+<a name="2960"><span class="lineNum">    2960 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2961"><span class="lineNum">    2961 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_182[1],</span></a>
+<a name="2962"><span class="lineNum">    2962 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_182[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2963"><span class="lineNum">    2963 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hB7)</span></a>
+<a name="2964"><span class="lineNum">    2964 </span><span class="lineNoCov">          0 :         state_vec_183 &lt;=</span></a>
+<a name="2965"><span class="lineNum">    2965 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2966"><span class="lineNum">    2966 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_183[1],</span></a>
+<a name="2967"><span class="lineNum">    2967 </span><span class="lineCov">          2 :            touch_way_0_bits[1] ? state_vec_183[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2968"><span class="lineNum">    2968 </span><span class="lineCov">          1 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hB8)</span></a>
+<a name="2969"><span class="lineNum">    2969 </span><span class="lineCov">          1 :         state_vec_184 &lt;=</span></a>
+<a name="2970"><span class="lineNum">    2970 </span><span class="lineCov">          1 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2971"><span class="lineNum">    2971 </span><span class="lineCov">          1 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_184[1],</span></a>
+<a name="2972"><span class="lineNum">    2972 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_184[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2973"><span class="lineNum">    2973 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hB9)</span></a>
+<a name="2974"><span class="lineNum">    2974 </span><span class="lineNoCov">          0 :         state_vec_185 &lt;=</span></a>
+<a name="2975"><span class="lineNum">    2975 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2976"><span class="lineNum">    2976 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_185[1],</span></a>
+<a name="2977"><span class="lineNum">    2977 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_185[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2978"><span class="lineNum">    2978 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hBA)</span></a>
+<a name="2979"><span class="lineNum">    2979 </span><span class="lineNoCov">          0 :         state_vec_186 &lt;=</span></a>
+<a name="2980"><span class="lineNum">    2980 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2981"><span class="lineNum">    2981 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_186[1],</span></a>
+<a name="2982"><span class="lineNum">    2982 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_186[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2983"><span class="lineNum">    2983 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hBB)</span></a>
+<a name="2984"><span class="lineNum">    2984 </span><span class="lineNoCov">          0 :         state_vec_187 &lt;=</span></a>
+<a name="2985"><span class="lineNum">    2985 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2986"><span class="lineNum">    2986 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_187[1],</span></a>
+<a name="2987"><span class="lineNum">    2987 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_187[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2988"><span class="lineNum">    2988 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hBC)</span></a>
+<a name="2989"><span class="lineNum">    2989 </span><span class="lineNoCov">          0 :         state_vec_188 &lt;=</span></a>
+<a name="2990"><span class="lineNum">    2990 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2991"><span class="lineNum">    2991 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_188[1],</span></a>
+<a name="2992"><span class="lineNum">    2992 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_188[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2993"><span class="lineNum">    2993 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hBD)</span></a>
+<a name="2994"><span class="lineNum">    2994 </span><span class="lineNoCov">          0 :         state_vec_189 &lt;=</span></a>
+<a name="2995"><span class="lineNum">    2995 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="2996"><span class="lineNum">    2996 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_189[1],</span></a>
+<a name="2997"><span class="lineNum">    2997 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_189[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="2998"><span class="lineNum">    2998 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hBE)</span></a>
+<a name="2999"><span class="lineNum">    2999 </span><span class="lineNoCov">          0 :         state_vec_190 &lt;=</span></a>
+<a name="3000"><span class="lineNum">    3000 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3001"><span class="lineNum">    3001 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_190[1],</span></a>
+<a name="3002"><span class="lineNum">    3002 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_190[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3003"><span class="lineNum">    3003 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hBF)</span></a>
+<a name="3004"><span class="lineNum">    3004 </span><span class="lineNoCov">          0 :         state_vec_191 &lt;=</span></a>
+<a name="3005"><span class="lineNum">    3005 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3006"><span class="lineNum">    3006 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_191[1],</span></a>
+<a name="3007"><span class="lineNum">    3007 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_191[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3008"><span class="lineNum">    3008 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hC0)</span></a>
+<a name="3009"><span class="lineNum">    3009 </span><span class="lineNoCov">          0 :         state_vec_192 &lt;=</span></a>
+<a name="3010"><span class="lineNum">    3010 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3011"><span class="lineNum">    3011 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_192[1],</span></a>
+<a name="3012"><span class="lineNum">    3012 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_192[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3013"><span class="lineNum">    3013 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hC1)</span></a>
+<a name="3014"><span class="lineNum">    3014 </span><span class="lineNoCov">          0 :         state_vec_193 &lt;=</span></a>
+<a name="3015"><span class="lineNum">    3015 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3016"><span class="lineNum">    3016 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_193[1],</span></a>
+<a name="3017"><span class="lineNum">    3017 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_193[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3018"><span class="lineNum">    3018 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hC2)</span></a>
+<a name="3019"><span class="lineNum">    3019 </span><span class="lineNoCov">          0 :         state_vec_194 &lt;=</span></a>
+<a name="3020"><span class="lineNum">    3020 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3021"><span class="lineNum">    3021 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_194[1],</span></a>
+<a name="3022"><span class="lineNum">    3022 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_194[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3023"><span class="lineNum">    3023 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hC3)</span></a>
+<a name="3024"><span class="lineNum">    3024 </span><span class="lineNoCov">          0 :         state_vec_195 &lt;=</span></a>
+<a name="3025"><span class="lineNum">    3025 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3026"><span class="lineNum">    3026 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_195[1],</span></a>
+<a name="3027"><span class="lineNum">    3027 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_195[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3028"><span class="lineNum">    3028 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hC4)</span></a>
+<a name="3029"><span class="lineNum">    3029 </span><span class="lineNoCov">          0 :         state_vec_196 &lt;=</span></a>
+<a name="3030"><span class="lineNum">    3030 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3031"><span class="lineNum">    3031 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_196[1],</span></a>
+<a name="3032"><span class="lineNum">    3032 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_196[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3033"><span class="lineNum">    3033 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hC5)</span></a>
+<a name="3034"><span class="lineNum">    3034 </span><span class="lineNoCov">          0 :         state_vec_197 &lt;=</span></a>
+<a name="3035"><span class="lineNum">    3035 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3036"><span class="lineNum">    3036 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_197[1],</span></a>
+<a name="3037"><span class="lineNum">    3037 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_197[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3038"><span class="lineNum">    3038 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hC6)</span></a>
+<a name="3039"><span class="lineNum">    3039 </span><span class="lineNoCov">          0 :         state_vec_198 &lt;=</span></a>
+<a name="3040"><span class="lineNum">    3040 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3041"><span class="lineNum">    3041 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_198[1],</span></a>
+<a name="3042"><span class="lineNum">    3042 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_198[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3043"><span class="lineNum">    3043 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hC7)</span></a>
+<a name="3044"><span class="lineNum">    3044 </span><span class="lineNoCov">          0 :         state_vec_199 &lt;=</span></a>
+<a name="3045"><span class="lineNum">    3045 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3046"><span class="lineNum">    3046 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_199[1],</span></a>
+<a name="3047"><span class="lineNum">    3047 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_199[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3048"><span class="lineNum">    3048 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hC8)</span></a>
+<a name="3049"><span class="lineNum">    3049 </span><span class="lineNoCov">          0 :         state_vec_200 &lt;=</span></a>
+<a name="3050"><span class="lineNum">    3050 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3051"><span class="lineNum">    3051 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_200[1],</span></a>
+<a name="3052"><span class="lineNum">    3052 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_200[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3053"><span class="lineNum">    3053 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hC9)</span></a>
+<a name="3054"><span class="lineNum">    3054 </span><span class="lineNoCov">          0 :         state_vec_201 &lt;=</span></a>
+<a name="3055"><span class="lineNum">    3055 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3056"><span class="lineNum">    3056 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_201[1],</span></a>
+<a name="3057"><span class="lineNum">    3057 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_201[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3058"><span class="lineNum">    3058 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hCA)</span></a>
+<a name="3059"><span class="lineNum">    3059 </span><span class="lineNoCov">          0 :         state_vec_202 &lt;=</span></a>
+<a name="3060"><span class="lineNum">    3060 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3061"><span class="lineNum">    3061 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_202[1],</span></a>
+<a name="3062"><span class="lineNum">    3062 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_202[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3063"><span class="lineNum">    3063 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hCB)</span></a>
+<a name="3064"><span class="lineNum">    3064 </span><span class="lineNoCov">          0 :         state_vec_203 &lt;=</span></a>
+<a name="3065"><span class="lineNum">    3065 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3066"><span class="lineNum">    3066 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_203[1],</span></a>
+<a name="3067"><span class="lineNum">    3067 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_203[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3068"><span class="lineNum">    3068 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hCC)</span></a>
+<a name="3069"><span class="lineNum">    3069 </span><span class="lineNoCov">          0 :         state_vec_204 &lt;=</span></a>
+<a name="3070"><span class="lineNum">    3070 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3071"><span class="lineNum">    3071 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_204[1],</span></a>
+<a name="3072"><span class="lineNum">    3072 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_204[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3073"><span class="lineNum">    3073 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hCD)</span></a>
+<a name="3074"><span class="lineNum">    3074 </span><span class="lineNoCov">          0 :         state_vec_205 &lt;=</span></a>
+<a name="3075"><span class="lineNum">    3075 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3076"><span class="lineNum">    3076 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_205[1],</span></a>
+<a name="3077"><span class="lineNum">    3077 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_205[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3078"><span class="lineNum">    3078 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hCE)</span></a>
+<a name="3079"><span class="lineNum">    3079 </span><span class="lineNoCov">          0 :         state_vec_206 &lt;=</span></a>
+<a name="3080"><span class="lineNum">    3080 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3081"><span class="lineNum">    3081 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_206[1],</span></a>
+<a name="3082"><span class="lineNum">    3082 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_206[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3083"><span class="lineNum">    3083 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hCF)</span></a>
+<a name="3084"><span class="lineNum">    3084 </span><span class="lineNoCov">          0 :         state_vec_207 &lt;=</span></a>
+<a name="3085"><span class="lineNum">    3085 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3086"><span class="lineNum">    3086 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_207[1],</span></a>
+<a name="3087"><span class="lineNum">    3087 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_207[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3088"><span class="lineNum">    3088 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hD0)</span></a>
+<a name="3089"><span class="lineNum">    3089 </span><span class="lineNoCov">          0 :         state_vec_208 &lt;=</span></a>
+<a name="3090"><span class="lineNum">    3090 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3091"><span class="lineNum">    3091 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_208[1],</span></a>
+<a name="3092"><span class="lineNum">    3092 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_208[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3093"><span class="lineNum">    3093 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hD1)</span></a>
+<a name="3094"><span class="lineNum">    3094 </span><span class="lineNoCov">          0 :         state_vec_209 &lt;=</span></a>
+<a name="3095"><span class="lineNum">    3095 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3096"><span class="lineNum">    3096 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_209[1],</span></a>
+<a name="3097"><span class="lineNum">    3097 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_209[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3098"><span class="lineNum">    3098 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hD2)</span></a>
+<a name="3099"><span class="lineNum">    3099 </span><span class="lineNoCov">          0 :         state_vec_210 &lt;=</span></a>
+<a name="3100"><span class="lineNum">    3100 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3101"><span class="lineNum">    3101 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_210[1],</span></a>
+<a name="3102"><span class="lineNum">    3102 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_210[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3103"><span class="lineNum">    3103 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hD3)</span></a>
+<a name="3104"><span class="lineNum">    3104 </span><span class="lineNoCov">          0 :         state_vec_211 &lt;=</span></a>
+<a name="3105"><span class="lineNum">    3105 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3106"><span class="lineNum">    3106 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_211[1],</span></a>
+<a name="3107"><span class="lineNum">    3107 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_211[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3108"><span class="lineNum">    3108 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hD4)</span></a>
+<a name="3109"><span class="lineNum">    3109 </span><span class="lineNoCov">          0 :         state_vec_212 &lt;=</span></a>
+<a name="3110"><span class="lineNum">    3110 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3111"><span class="lineNum">    3111 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_212[1],</span></a>
+<a name="3112"><span class="lineNum">    3112 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_212[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3113"><span class="lineNum">    3113 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hD5)</span></a>
+<a name="3114"><span class="lineNum">    3114 </span><span class="lineNoCov">          0 :         state_vec_213 &lt;=</span></a>
+<a name="3115"><span class="lineNum">    3115 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3116"><span class="lineNum">    3116 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_213[1],</span></a>
+<a name="3117"><span class="lineNum">    3117 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_213[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3118"><span class="lineNum">    3118 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hD6)</span></a>
+<a name="3119"><span class="lineNum">    3119 </span><span class="lineNoCov">          0 :         state_vec_214 &lt;=</span></a>
+<a name="3120"><span class="lineNum">    3120 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3121"><span class="lineNum">    3121 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_214[1],</span></a>
+<a name="3122"><span class="lineNum">    3122 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_214[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3123"><span class="lineNum">    3123 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hD7)</span></a>
+<a name="3124"><span class="lineNum">    3124 </span><span class="lineNoCov">          0 :         state_vec_215 &lt;=</span></a>
+<a name="3125"><span class="lineNum">    3125 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3126"><span class="lineNum">    3126 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_215[1],</span></a>
+<a name="3127"><span class="lineNum">    3127 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_215[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3128"><span class="lineNum">    3128 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hD8)</span></a>
+<a name="3129"><span class="lineNum">    3129 </span><span class="lineNoCov">          0 :         state_vec_216 &lt;=</span></a>
+<a name="3130"><span class="lineNum">    3130 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3131"><span class="lineNum">    3131 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_216[1],</span></a>
+<a name="3132"><span class="lineNum">    3132 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_216[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3133"><span class="lineNum">    3133 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hD9)</span></a>
+<a name="3134"><span class="lineNum">    3134 </span><span class="lineNoCov">          0 :         state_vec_217 &lt;=</span></a>
+<a name="3135"><span class="lineNum">    3135 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3136"><span class="lineNum">    3136 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_217[1],</span></a>
+<a name="3137"><span class="lineNum">    3137 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_217[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3138"><span class="lineNum">    3138 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hDA)</span></a>
+<a name="3139"><span class="lineNum">    3139 </span><span class="lineNoCov">          0 :         state_vec_218 &lt;=</span></a>
+<a name="3140"><span class="lineNum">    3140 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3141"><span class="lineNum">    3141 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_218[1],</span></a>
+<a name="3142"><span class="lineNum">    3142 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_218[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3143"><span class="lineNum">    3143 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hDB)</span></a>
+<a name="3144"><span class="lineNum">    3144 </span><span class="lineNoCov">          0 :         state_vec_219 &lt;=</span></a>
+<a name="3145"><span class="lineNum">    3145 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3146"><span class="lineNum">    3146 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_219[1],</span></a>
+<a name="3147"><span class="lineNum">    3147 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_219[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3148"><span class="lineNum">    3148 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hDC)</span></a>
+<a name="3149"><span class="lineNum">    3149 </span><span class="lineNoCov">          0 :         state_vec_220 &lt;=</span></a>
+<a name="3150"><span class="lineNum">    3150 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3151"><span class="lineNum">    3151 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_220[1],</span></a>
+<a name="3152"><span class="lineNum">    3152 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_220[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3153"><span class="lineNum">    3153 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hDD)</span></a>
+<a name="3154"><span class="lineNum">    3154 </span><span class="lineNoCov">          0 :         state_vec_221 &lt;=</span></a>
+<a name="3155"><span class="lineNum">    3155 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3156"><span class="lineNum">    3156 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_221[1],</span></a>
+<a name="3157"><span class="lineNum">    3157 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_221[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3158"><span class="lineNum">    3158 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hDE)</span></a>
+<a name="3159"><span class="lineNum">    3159 </span><span class="lineNoCov">          0 :         state_vec_222 &lt;=</span></a>
+<a name="3160"><span class="lineNum">    3160 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3161"><span class="lineNum">    3161 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_222[1],</span></a>
+<a name="3162"><span class="lineNum">    3162 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_222[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3163"><span class="lineNum">    3163 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hDF)</span></a>
+<a name="3164"><span class="lineNum">    3164 </span><span class="lineNoCov">          0 :         state_vec_223 &lt;=</span></a>
+<a name="3165"><span class="lineNum">    3165 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3166"><span class="lineNum">    3166 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_223[1],</span></a>
+<a name="3167"><span class="lineNum">    3167 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_223[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3168"><span class="lineNum">    3168 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hE0)</span></a>
+<a name="3169"><span class="lineNum">    3169 </span><span class="lineNoCov">          0 :         state_vec_224 &lt;=</span></a>
+<a name="3170"><span class="lineNum">    3170 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3171"><span class="lineNum">    3171 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_224[1],</span></a>
+<a name="3172"><span class="lineNum">    3172 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_224[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3173"><span class="lineNum">    3173 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hE1)</span></a>
+<a name="3174"><span class="lineNum">    3174 </span><span class="lineNoCov">          0 :         state_vec_225 &lt;=</span></a>
+<a name="3175"><span class="lineNum">    3175 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3176"><span class="lineNum">    3176 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_225[1],</span></a>
+<a name="3177"><span class="lineNum">    3177 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_225[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3178"><span class="lineNum">    3178 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hE2)</span></a>
+<a name="3179"><span class="lineNum">    3179 </span><span class="lineNoCov">          0 :         state_vec_226 &lt;=</span></a>
+<a name="3180"><span class="lineNum">    3180 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3181"><span class="lineNum">    3181 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_226[1],</span></a>
+<a name="3182"><span class="lineNum">    3182 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_226[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3183"><span class="lineNum">    3183 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hE3)</span></a>
+<a name="3184"><span class="lineNum">    3184 </span><span class="lineNoCov">          0 :         state_vec_227 &lt;=</span></a>
+<a name="3185"><span class="lineNum">    3185 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3186"><span class="lineNum">    3186 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_227[1],</span></a>
+<a name="3187"><span class="lineNum">    3187 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_227[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3188"><span class="lineNum">    3188 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hE4)</span></a>
+<a name="3189"><span class="lineNum">    3189 </span><span class="lineNoCov">          0 :         state_vec_228 &lt;=</span></a>
+<a name="3190"><span class="lineNum">    3190 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3191"><span class="lineNum">    3191 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_228[1],</span></a>
+<a name="3192"><span class="lineNum">    3192 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_228[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3193"><span class="lineNum">    3193 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hE5)</span></a>
+<a name="3194"><span class="lineNum">    3194 </span><span class="lineNoCov">          0 :         state_vec_229 &lt;=</span></a>
+<a name="3195"><span class="lineNum">    3195 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3196"><span class="lineNum">    3196 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_229[1],</span></a>
+<a name="3197"><span class="lineNum">    3197 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_229[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3198"><span class="lineNum">    3198 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hE6)</span></a>
+<a name="3199"><span class="lineNum">    3199 </span><span class="lineNoCov">          0 :         state_vec_230 &lt;=</span></a>
+<a name="3200"><span class="lineNum">    3200 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3201"><span class="lineNum">    3201 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_230[1],</span></a>
+<a name="3202"><span class="lineNum">    3202 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_230[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3203"><span class="lineNum">    3203 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hE7)</span></a>
+<a name="3204"><span class="lineNum">    3204 </span><span class="lineNoCov">          0 :         state_vec_231 &lt;=</span></a>
+<a name="3205"><span class="lineNum">    3205 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3206"><span class="lineNum">    3206 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_231[1],</span></a>
+<a name="3207"><span class="lineNum">    3207 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_231[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3208"><span class="lineNum">    3208 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hE8)</span></a>
+<a name="3209"><span class="lineNum">    3209 </span><span class="lineNoCov">          0 :         state_vec_232 &lt;=</span></a>
+<a name="3210"><span class="lineNum">    3210 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3211"><span class="lineNum">    3211 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_232[1],</span></a>
+<a name="3212"><span class="lineNum">    3212 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_232[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3213"><span class="lineNum">    3213 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hE9)</span></a>
+<a name="3214"><span class="lineNum">    3214 </span><span class="lineNoCov">          0 :         state_vec_233 &lt;=</span></a>
+<a name="3215"><span class="lineNum">    3215 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3216"><span class="lineNum">    3216 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_233[1],</span></a>
+<a name="3217"><span class="lineNum">    3217 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_233[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3218"><span class="lineNum">    3218 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hEA)</span></a>
+<a name="3219"><span class="lineNum">    3219 </span><span class="lineNoCov">          0 :         state_vec_234 &lt;=</span></a>
+<a name="3220"><span class="lineNum">    3220 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3221"><span class="lineNum">    3221 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_234[1],</span></a>
+<a name="3222"><span class="lineNum">    3222 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_234[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3223"><span class="lineNum">    3223 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hEB)</span></a>
+<a name="3224"><span class="lineNum">    3224 </span><span class="lineNoCov">          0 :         state_vec_235 &lt;=</span></a>
+<a name="3225"><span class="lineNum">    3225 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3226"><span class="lineNum">    3226 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_235[1],</span></a>
+<a name="3227"><span class="lineNum">    3227 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_235[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3228"><span class="lineNum">    3228 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hEC)</span></a>
+<a name="3229"><span class="lineNum">    3229 </span><span class="lineNoCov">          0 :         state_vec_236 &lt;=</span></a>
+<a name="3230"><span class="lineNum">    3230 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3231"><span class="lineNum">    3231 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_236[1],</span></a>
+<a name="3232"><span class="lineNum">    3232 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_236[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3233"><span class="lineNum">    3233 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hED)</span></a>
+<a name="3234"><span class="lineNum">    3234 </span><span class="lineNoCov">          0 :         state_vec_237 &lt;=</span></a>
+<a name="3235"><span class="lineNum">    3235 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3236"><span class="lineNum">    3236 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_237[1],</span></a>
+<a name="3237"><span class="lineNum">    3237 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_237[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3238"><span class="lineNum">    3238 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hEE)</span></a>
+<a name="3239"><span class="lineNum">    3239 </span><span class="lineNoCov">          0 :         state_vec_238 &lt;=</span></a>
+<a name="3240"><span class="lineNum">    3240 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3241"><span class="lineNum">    3241 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_238[1],</span></a>
+<a name="3242"><span class="lineNum">    3242 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_238[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3243"><span class="lineNum">    3243 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hEF)</span></a>
+<a name="3244"><span class="lineNum">    3244 </span><span class="lineNoCov">          0 :         state_vec_239 &lt;=</span></a>
+<a name="3245"><span class="lineNum">    3245 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3246"><span class="lineNum">    3246 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_239[1],</span></a>
+<a name="3247"><span class="lineNum">    3247 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_239[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3248"><span class="lineNum">    3248 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hF0)</span></a>
+<a name="3249"><span class="lineNum">    3249 </span><span class="lineNoCov">          0 :         state_vec_240 &lt;=</span></a>
+<a name="3250"><span class="lineNum">    3250 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3251"><span class="lineNum">    3251 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_240[1],</span></a>
+<a name="3252"><span class="lineNum">    3252 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_240[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3253"><span class="lineNum">    3253 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hF1)</span></a>
+<a name="3254"><span class="lineNum">    3254 </span><span class="lineNoCov">          0 :         state_vec_241 &lt;=</span></a>
+<a name="3255"><span class="lineNum">    3255 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3256"><span class="lineNum">    3256 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_241[1],</span></a>
+<a name="3257"><span class="lineNum">    3257 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_241[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3258"><span class="lineNum">    3258 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hF2)</span></a>
+<a name="3259"><span class="lineNum">    3259 </span><span class="lineNoCov">          0 :         state_vec_242 &lt;=</span></a>
+<a name="3260"><span class="lineNum">    3260 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3261"><span class="lineNum">    3261 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_242[1],</span></a>
+<a name="3262"><span class="lineNum">    3262 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_242[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3263"><span class="lineNum">    3263 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hF3)</span></a>
+<a name="3264"><span class="lineNum">    3264 </span><span class="lineNoCov">          0 :         state_vec_243 &lt;=</span></a>
+<a name="3265"><span class="lineNum">    3265 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3266"><span class="lineNum">    3266 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_243[1],</span></a>
+<a name="3267"><span class="lineNum">    3267 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_243[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3268"><span class="lineNum">    3268 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hF4)</span></a>
+<a name="3269"><span class="lineNum">    3269 </span><span class="lineNoCov">          0 :         state_vec_244 &lt;=</span></a>
+<a name="3270"><span class="lineNum">    3270 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3271"><span class="lineNum">    3271 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_244[1],</span></a>
+<a name="3272"><span class="lineNum">    3272 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_244[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3273"><span class="lineNum">    3273 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hF5)</span></a>
+<a name="3274"><span class="lineNum">    3274 </span><span class="lineNoCov">          0 :         state_vec_245 &lt;=</span></a>
+<a name="3275"><span class="lineNum">    3275 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3276"><span class="lineNum">    3276 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_245[1],</span></a>
+<a name="3277"><span class="lineNum">    3277 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_245[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3278"><span class="lineNum">    3278 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hF6)</span></a>
+<a name="3279"><span class="lineNum">    3279 </span><span class="lineNoCov">          0 :         state_vec_246 &lt;=</span></a>
+<a name="3280"><span class="lineNum">    3280 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3281"><span class="lineNum">    3281 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_246[1],</span></a>
+<a name="3282"><span class="lineNum">    3282 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_246[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3283"><span class="lineNum">    3283 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hF7)</span></a>
+<a name="3284"><span class="lineNum">    3284 </span><span class="lineNoCov">          0 :         state_vec_247 &lt;=</span></a>
+<a name="3285"><span class="lineNum">    3285 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3286"><span class="lineNum">    3286 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_247[1],</span></a>
+<a name="3287"><span class="lineNum">    3287 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_247[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3288"><span class="lineNum">    3288 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hF8)</span></a>
+<a name="3289"><span class="lineNum">    3289 </span><span class="lineNoCov">          0 :         state_vec_248 &lt;=</span></a>
+<a name="3290"><span class="lineNum">    3290 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3291"><span class="lineNum">    3291 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_248[1],</span></a>
+<a name="3292"><span class="lineNum">    3292 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_248[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3293"><span class="lineNum">    3293 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hF9)</span></a>
+<a name="3294"><span class="lineNum">    3294 </span><span class="lineNoCov">          0 :         state_vec_249 &lt;=</span></a>
+<a name="3295"><span class="lineNum">    3295 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3296"><span class="lineNum">    3296 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_249[1],</span></a>
+<a name="3297"><span class="lineNum">    3297 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_249[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3298"><span class="lineNum">    3298 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hFA)</span></a>
+<a name="3299"><span class="lineNum">    3299 </span><span class="lineNoCov">          0 :         state_vec_250 &lt;=</span></a>
+<a name="3300"><span class="lineNum">    3300 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3301"><span class="lineNum">    3301 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_250[1],</span></a>
+<a name="3302"><span class="lineNum">    3302 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_250[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3303"><span class="lineNum">    3303 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hFB)</span></a>
+<a name="3304"><span class="lineNum">    3304 </span><span class="lineNoCov">          0 :         state_vec_251 &lt;=</span></a>
+<a name="3305"><span class="lineNum">    3305 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3306"><span class="lineNum">    3306 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_251[1],</span></a>
+<a name="3307"><span class="lineNum">    3307 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_251[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3308"><span class="lineNum">    3308 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hFC)</span></a>
+<a name="3309"><span class="lineNum">    3309 </span><span class="lineNoCov">          0 :         state_vec_252 &lt;=</span></a>
+<a name="3310"><span class="lineNum">    3310 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3311"><span class="lineNum">    3311 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_252[1],</span></a>
+<a name="3312"><span class="lineNum">    3312 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_252[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3313"><span class="lineNum">    3313 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hFD)</span></a>
+<a name="3314"><span class="lineNum">    3314 </span><span class="lineNoCov">          0 :         state_vec_253 &lt;=</span></a>
+<a name="3315"><span class="lineNum">    3315 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3316"><span class="lineNum">    3316 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_253[1],</span></a>
+<a name="3317"><span class="lineNum">    3317 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_253[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3318"><span class="lineNum">    3318 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hFE)</span></a>
+<a name="3319"><span class="lineNum">    3319 </span><span class="lineNoCov">          0 :         state_vec_254 &lt;=</span></a>
+<a name="3320"><span class="lineNum">    3320 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3321"><span class="lineNum">    3321 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_254[1],</span></a>
+<a name="3322"><span class="lineNum">    3322 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_254[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3323"><span class="lineNum">    3323 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'hFF)</span></a>
+<a name="3324"><span class="lineNum">    3324 </span><span class="lineNoCov">          0 :         state_vec_255 &lt;=</span></a>
+<a name="3325"><span class="lineNum">    3325 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3326"><span class="lineNum">    3326 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_255[1],</span></a>
+<a name="3327"><span class="lineNum">    3327 </span><span class="lineCov">          2 :            touch_way_0_bits[1] ? state_vec_255[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3328"><span class="lineNum">    3328 </span><span class="lineCov">          1 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h100)</span></a>
+<a name="3329"><span class="lineNum">    3329 </span><span class="lineCov">          1 :         state_vec_256 &lt;=</span></a>
+<a name="3330"><span class="lineNum">    3330 </span><span class="lineCov">          1 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3331"><span class="lineNum">    3331 </span><span class="lineCov">          1 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_256[1],</span></a>
+<a name="3332"><span class="lineNum">    3332 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_256[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3333"><span class="lineNum">    3333 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h101)</span></a>
+<a name="3334"><span class="lineNum">    3334 </span><span class="lineNoCov">          0 :         state_vec_257 &lt;=</span></a>
+<a name="3335"><span class="lineNum">    3335 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3336"><span class="lineNum">    3336 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_257[1],</span></a>
+<a name="3337"><span class="lineNum">    3337 </span><span class="lineCov">          2 :            touch_way_0_bits[1] ? state_vec_257[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3338"><span class="lineNum">    3338 </span><span class="lineCov">          1 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h102)</span></a>
+<a name="3339"><span class="lineNum">    3339 </span><span class="lineCov">          1 :         state_vec_258 &lt;=</span></a>
+<a name="3340"><span class="lineNum">    3340 </span><span class="lineCov">          1 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3341"><span class="lineNum">    3341 </span><span class="lineCov">          1 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_258[1],</span></a>
+<a name="3342"><span class="lineNum">    3342 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_258[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3343"><span class="lineNum">    3343 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h103)</span></a>
+<a name="3344"><span class="lineNum">    3344 </span><span class="lineNoCov">          0 :         state_vec_259 &lt;=</span></a>
+<a name="3345"><span class="lineNum">    3345 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3346"><span class="lineNum">    3346 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_259[1],</span></a>
+<a name="3347"><span class="lineNum">    3347 </span><span class="lineCov">          2 :            touch_way_0_bits[1] ? state_vec_259[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3348"><span class="lineNum">    3348 </span><span class="lineCov">          1 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h104)</span></a>
+<a name="3349"><span class="lineNum">    3349 </span><span class="lineCov">          1 :         state_vec_260 &lt;=</span></a>
+<a name="3350"><span class="lineNum">    3350 </span><span class="lineCov">          1 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3351"><span class="lineNum">    3351 </span><span class="lineCov">          1 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_260[1],</span></a>
+<a name="3352"><span class="lineNum">    3352 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_260[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3353"><span class="lineNum">    3353 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h105)</span></a>
+<a name="3354"><span class="lineNum">    3354 </span><span class="lineNoCov">          0 :         state_vec_261 &lt;=</span></a>
+<a name="3355"><span class="lineNum">    3355 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3356"><span class="lineNum">    3356 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_261[1],</span></a>
+<a name="3357"><span class="lineNum">    3357 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_261[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3358"><span class="lineNum">    3358 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h106)</span></a>
+<a name="3359"><span class="lineNum">    3359 </span><span class="lineNoCov">          0 :         state_vec_262 &lt;=</span></a>
+<a name="3360"><span class="lineNum">    3360 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3361"><span class="lineNum">    3361 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_262[1],</span></a>
+<a name="3362"><span class="lineNum">    3362 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_262[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3363"><span class="lineNum">    3363 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h107)</span></a>
+<a name="3364"><span class="lineNum">    3364 </span><span class="lineNoCov">          0 :         state_vec_263 &lt;=</span></a>
+<a name="3365"><span class="lineNum">    3365 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3366"><span class="lineNum">    3366 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_263[1],</span></a>
+<a name="3367"><span class="lineNum">    3367 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_263[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3368"><span class="lineNum">    3368 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h108)</span></a>
+<a name="3369"><span class="lineNum">    3369 </span><span class="lineNoCov">          0 :         state_vec_264 &lt;=</span></a>
+<a name="3370"><span class="lineNum">    3370 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3371"><span class="lineNum">    3371 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_264[1],</span></a>
+<a name="3372"><span class="lineNum">    3372 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_264[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3373"><span class="lineNum">    3373 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h109)</span></a>
+<a name="3374"><span class="lineNum">    3374 </span><span class="lineNoCov">          0 :         state_vec_265 &lt;=</span></a>
+<a name="3375"><span class="lineNum">    3375 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3376"><span class="lineNum">    3376 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_265[1],</span></a>
+<a name="3377"><span class="lineNum">    3377 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_265[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3378"><span class="lineNum">    3378 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h10A)</span></a>
+<a name="3379"><span class="lineNum">    3379 </span><span class="lineNoCov">          0 :         state_vec_266 &lt;=</span></a>
+<a name="3380"><span class="lineNum">    3380 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3381"><span class="lineNum">    3381 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_266[1],</span></a>
+<a name="3382"><span class="lineNum">    3382 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_266[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3383"><span class="lineNum">    3383 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h10B)</span></a>
+<a name="3384"><span class="lineNum">    3384 </span><span class="lineNoCov">          0 :         state_vec_267 &lt;=</span></a>
+<a name="3385"><span class="lineNum">    3385 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3386"><span class="lineNum">    3386 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_267[1],</span></a>
+<a name="3387"><span class="lineNum">    3387 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_267[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3388"><span class="lineNum">    3388 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h10C)</span></a>
+<a name="3389"><span class="lineNum">    3389 </span><span class="lineNoCov">          0 :         state_vec_268 &lt;=</span></a>
+<a name="3390"><span class="lineNum">    3390 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3391"><span class="lineNum">    3391 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_268[1],</span></a>
+<a name="3392"><span class="lineNum">    3392 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_268[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3393"><span class="lineNum">    3393 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h10D)</span></a>
+<a name="3394"><span class="lineNum">    3394 </span><span class="lineNoCov">          0 :         state_vec_269 &lt;=</span></a>
+<a name="3395"><span class="lineNum">    3395 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3396"><span class="lineNum">    3396 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_269[1],</span></a>
+<a name="3397"><span class="lineNum">    3397 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_269[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3398"><span class="lineNum">    3398 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h10E)</span></a>
+<a name="3399"><span class="lineNum">    3399 </span><span class="lineNoCov">          0 :         state_vec_270 &lt;=</span></a>
+<a name="3400"><span class="lineNum">    3400 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3401"><span class="lineNum">    3401 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_270[1],</span></a>
+<a name="3402"><span class="lineNum">    3402 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_270[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3403"><span class="lineNum">    3403 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h10F)</span></a>
+<a name="3404"><span class="lineNum">    3404 </span><span class="lineNoCov">          0 :         state_vec_271 &lt;=</span></a>
+<a name="3405"><span class="lineNum">    3405 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3406"><span class="lineNum">    3406 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_271[1],</span></a>
+<a name="3407"><span class="lineNum">    3407 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_271[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3408"><span class="lineNum">    3408 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h110)</span></a>
+<a name="3409"><span class="lineNum">    3409 </span><span class="lineNoCov">          0 :         state_vec_272 &lt;=</span></a>
+<a name="3410"><span class="lineNum">    3410 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3411"><span class="lineNum">    3411 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_272[1],</span></a>
+<a name="3412"><span class="lineNum">    3412 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_272[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3413"><span class="lineNum">    3413 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h111)</span></a>
+<a name="3414"><span class="lineNum">    3414 </span><span class="lineNoCov">          0 :         state_vec_273 &lt;=</span></a>
+<a name="3415"><span class="lineNum">    3415 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3416"><span class="lineNum">    3416 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_273[1],</span></a>
+<a name="3417"><span class="lineNum">    3417 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_273[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3418"><span class="lineNum">    3418 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h112)</span></a>
+<a name="3419"><span class="lineNum">    3419 </span><span class="lineNoCov">          0 :         state_vec_274 &lt;=</span></a>
+<a name="3420"><span class="lineNum">    3420 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3421"><span class="lineNum">    3421 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_274[1],</span></a>
+<a name="3422"><span class="lineNum">    3422 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_274[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3423"><span class="lineNum">    3423 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h113)</span></a>
+<a name="3424"><span class="lineNum">    3424 </span><span class="lineNoCov">          0 :         state_vec_275 &lt;=</span></a>
+<a name="3425"><span class="lineNum">    3425 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3426"><span class="lineNum">    3426 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_275[1],</span></a>
+<a name="3427"><span class="lineNum">    3427 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_275[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3428"><span class="lineNum">    3428 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h114)</span></a>
+<a name="3429"><span class="lineNum">    3429 </span><span class="lineNoCov">          0 :         state_vec_276 &lt;=</span></a>
+<a name="3430"><span class="lineNum">    3430 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3431"><span class="lineNum">    3431 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_276[1],</span></a>
+<a name="3432"><span class="lineNum">    3432 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_276[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3433"><span class="lineNum">    3433 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h115)</span></a>
+<a name="3434"><span class="lineNum">    3434 </span><span class="lineNoCov">          0 :         state_vec_277 &lt;=</span></a>
+<a name="3435"><span class="lineNum">    3435 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3436"><span class="lineNum">    3436 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_277[1],</span></a>
+<a name="3437"><span class="lineNum">    3437 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_277[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3438"><span class="lineNum">    3438 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h116)</span></a>
+<a name="3439"><span class="lineNum">    3439 </span><span class="lineNoCov">          0 :         state_vec_278 &lt;=</span></a>
+<a name="3440"><span class="lineNum">    3440 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3441"><span class="lineNum">    3441 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_278[1],</span></a>
+<a name="3442"><span class="lineNum">    3442 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_278[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3443"><span class="lineNum">    3443 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h117)</span></a>
+<a name="3444"><span class="lineNum">    3444 </span><span class="lineNoCov">          0 :         state_vec_279 &lt;=</span></a>
+<a name="3445"><span class="lineNum">    3445 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3446"><span class="lineNum">    3446 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_279[1],</span></a>
+<a name="3447"><span class="lineNum">    3447 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_279[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3448"><span class="lineNum">    3448 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h118)</span></a>
+<a name="3449"><span class="lineNum">    3449 </span><span class="lineNoCov">          0 :         state_vec_280 &lt;=</span></a>
+<a name="3450"><span class="lineNum">    3450 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3451"><span class="lineNum">    3451 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_280[1],</span></a>
+<a name="3452"><span class="lineNum">    3452 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_280[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3453"><span class="lineNum">    3453 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h119)</span></a>
+<a name="3454"><span class="lineNum">    3454 </span><span class="lineNoCov">          0 :         state_vec_281 &lt;=</span></a>
+<a name="3455"><span class="lineNum">    3455 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3456"><span class="lineNum">    3456 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_281[1],</span></a>
+<a name="3457"><span class="lineNum">    3457 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_281[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3458"><span class="lineNum">    3458 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h11A)</span></a>
+<a name="3459"><span class="lineNum">    3459 </span><span class="lineNoCov">          0 :         state_vec_282 &lt;=</span></a>
+<a name="3460"><span class="lineNum">    3460 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3461"><span class="lineNum">    3461 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_282[1],</span></a>
+<a name="3462"><span class="lineNum">    3462 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_282[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3463"><span class="lineNum">    3463 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h11B)</span></a>
+<a name="3464"><span class="lineNum">    3464 </span><span class="lineNoCov">          0 :         state_vec_283 &lt;=</span></a>
+<a name="3465"><span class="lineNum">    3465 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3466"><span class="lineNum">    3466 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_283[1],</span></a>
+<a name="3467"><span class="lineNum">    3467 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_283[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3468"><span class="lineNum">    3468 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h11C)</span></a>
+<a name="3469"><span class="lineNum">    3469 </span><span class="lineNoCov">          0 :         state_vec_284 &lt;=</span></a>
+<a name="3470"><span class="lineNum">    3470 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3471"><span class="lineNum">    3471 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_284[1],</span></a>
+<a name="3472"><span class="lineNum">    3472 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_284[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3473"><span class="lineNum">    3473 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h11D)</span></a>
+<a name="3474"><span class="lineNum">    3474 </span><span class="lineNoCov">          0 :         state_vec_285 &lt;=</span></a>
+<a name="3475"><span class="lineNum">    3475 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3476"><span class="lineNum">    3476 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_285[1],</span></a>
+<a name="3477"><span class="lineNum">    3477 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_285[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3478"><span class="lineNum">    3478 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h11E)</span></a>
+<a name="3479"><span class="lineNum">    3479 </span><span class="lineNoCov">          0 :         state_vec_286 &lt;=</span></a>
+<a name="3480"><span class="lineNum">    3480 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3481"><span class="lineNum">    3481 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_286[1],</span></a>
+<a name="3482"><span class="lineNum">    3482 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_286[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3483"><span class="lineNum">    3483 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h11F)</span></a>
+<a name="3484"><span class="lineNum">    3484 </span><span class="lineNoCov">          0 :         state_vec_287 &lt;=</span></a>
+<a name="3485"><span class="lineNum">    3485 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3486"><span class="lineNum">    3486 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_287[1],</span></a>
+<a name="3487"><span class="lineNum">    3487 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_287[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3488"><span class="lineNum">    3488 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h120)</span></a>
+<a name="3489"><span class="lineNum">    3489 </span><span class="lineNoCov">          0 :         state_vec_288 &lt;=</span></a>
+<a name="3490"><span class="lineNum">    3490 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3491"><span class="lineNum">    3491 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_288[1],</span></a>
+<a name="3492"><span class="lineNum">    3492 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_288[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3493"><span class="lineNum">    3493 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h121)</span></a>
+<a name="3494"><span class="lineNum">    3494 </span><span class="lineNoCov">          0 :         state_vec_289 &lt;=</span></a>
+<a name="3495"><span class="lineNum">    3495 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3496"><span class="lineNum">    3496 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_289[1],</span></a>
+<a name="3497"><span class="lineNum">    3497 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_289[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3498"><span class="lineNum">    3498 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h122)</span></a>
+<a name="3499"><span class="lineNum">    3499 </span><span class="lineNoCov">          0 :         state_vec_290 &lt;=</span></a>
+<a name="3500"><span class="lineNum">    3500 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3501"><span class="lineNum">    3501 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_290[1],</span></a>
+<a name="3502"><span class="lineNum">    3502 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_290[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3503"><span class="lineNum">    3503 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h123)</span></a>
+<a name="3504"><span class="lineNum">    3504 </span><span class="lineNoCov">          0 :         state_vec_291 &lt;=</span></a>
+<a name="3505"><span class="lineNum">    3505 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3506"><span class="lineNum">    3506 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_291[1],</span></a>
+<a name="3507"><span class="lineNum">    3507 </span><span class="lineCov">         10 :            touch_way_0_bits[1] ? state_vec_291[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3508"><span class="lineNum">    3508 </span><span class="lineCov">          5 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h124)</span></a>
+<a name="3509"><span class="lineNum">    3509 </span><span class="lineCov">          5 :         state_vec_292 &lt;=</span></a>
+<a name="3510"><span class="lineNum">    3510 </span><span class="lineCov">          5 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3511"><span class="lineNum">    3511 </span><span class="lineCov">          5 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_292[1],</span></a>
+<a name="3512"><span class="lineNum">    3512 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_292[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3513"><span class="lineNum">    3513 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h125)</span></a>
+<a name="3514"><span class="lineNum">    3514 </span><span class="lineNoCov">          0 :         state_vec_293 &lt;=</span></a>
+<a name="3515"><span class="lineNum">    3515 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3516"><span class="lineNum">    3516 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_293[1],</span></a>
+<a name="3517"><span class="lineNum">    3517 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_293[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3518"><span class="lineNum">    3518 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h126)</span></a>
+<a name="3519"><span class="lineNum">    3519 </span><span class="lineNoCov">          0 :         state_vec_294 &lt;=</span></a>
+<a name="3520"><span class="lineNum">    3520 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3521"><span class="lineNum">    3521 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_294[1],</span></a>
+<a name="3522"><span class="lineNum">    3522 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_294[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3523"><span class="lineNum">    3523 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h127)</span></a>
+<a name="3524"><span class="lineNum">    3524 </span><span class="lineNoCov">          0 :         state_vec_295 &lt;=</span></a>
+<a name="3525"><span class="lineNum">    3525 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3526"><span class="lineNum">    3526 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_295[1],</span></a>
+<a name="3527"><span class="lineNum">    3527 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_295[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3528"><span class="lineNum">    3528 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h128)</span></a>
+<a name="3529"><span class="lineNum">    3529 </span><span class="lineNoCov">          0 :         state_vec_296 &lt;=</span></a>
+<a name="3530"><span class="lineNum">    3530 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3531"><span class="lineNum">    3531 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_296[1],</span></a>
+<a name="3532"><span class="lineNum">    3532 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_296[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3533"><span class="lineNum">    3533 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h129)</span></a>
+<a name="3534"><span class="lineNum">    3534 </span><span class="lineNoCov">          0 :         state_vec_297 &lt;=</span></a>
+<a name="3535"><span class="lineNum">    3535 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3536"><span class="lineNum">    3536 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_297[1],</span></a>
+<a name="3537"><span class="lineNum">    3537 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_297[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3538"><span class="lineNum">    3538 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h12A)</span></a>
+<a name="3539"><span class="lineNum">    3539 </span><span class="lineNoCov">          0 :         state_vec_298 &lt;=</span></a>
+<a name="3540"><span class="lineNum">    3540 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3541"><span class="lineNum">    3541 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_298[1],</span></a>
+<a name="3542"><span class="lineNum">    3542 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_298[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3543"><span class="lineNum">    3543 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h12B)</span></a>
+<a name="3544"><span class="lineNum">    3544 </span><span class="lineNoCov">          0 :         state_vec_299 &lt;=</span></a>
+<a name="3545"><span class="lineNum">    3545 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3546"><span class="lineNum">    3546 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_299[1],</span></a>
+<a name="3547"><span class="lineNum">    3547 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_299[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3548"><span class="lineNum">    3548 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h12C)</span></a>
+<a name="3549"><span class="lineNum">    3549 </span><span class="lineNoCov">          0 :         state_vec_300 &lt;=</span></a>
+<a name="3550"><span class="lineNum">    3550 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3551"><span class="lineNum">    3551 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_300[1],</span></a>
+<a name="3552"><span class="lineNum">    3552 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_300[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3553"><span class="lineNum">    3553 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h12D)</span></a>
+<a name="3554"><span class="lineNum">    3554 </span><span class="lineNoCov">          0 :         state_vec_301 &lt;=</span></a>
+<a name="3555"><span class="lineNum">    3555 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3556"><span class="lineNum">    3556 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_301[1],</span></a>
+<a name="3557"><span class="lineNum">    3557 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_301[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3558"><span class="lineNum">    3558 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h12E)</span></a>
+<a name="3559"><span class="lineNum">    3559 </span><span class="lineNoCov">          0 :         state_vec_302 &lt;=</span></a>
+<a name="3560"><span class="lineNum">    3560 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3561"><span class="lineNum">    3561 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_302[1],</span></a>
+<a name="3562"><span class="lineNum">    3562 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_302[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3563"><span class="lineNum">    3563 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h12F)</span></a>
+<a name="3564"><span class="lineNum">    3564 </span><span class="lineNoCov">          0 :         state_vec_303 &lt;=</span></a>
+<a name="3565"><span class="lineNum">    3565 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3566"><span class="lineNum">    3566 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_303[1],</span></a>
+<a name="3567"><span class="lineNum">    3567 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_303[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3568"><span class="lineNum">    3568 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h130)</span></a>
+<a name="3569"><span class="lineNum">    3569 </span><span class="lineNoCov">          0 :         state_vec_304 &lt;=</span></a>
+<a name="3570"><span class="lineNum">    3570 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3571"><span class="lineNum">    3571 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_304[1],</span></a>
+<a name="3572"><span class="lineNum">    3572 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_304[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3573"><span class="lineNum">    3573 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h131)</span></a>
+<a name="3574"><span class="lineNum">    3574 </span><span class="lineNoCov">          0 :         state_vec_305 &lt;=</span></a>
+<a name="3575"><span class="lineNum">    3575 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3576"><span class="lineNum">    3576 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_305[1],</span></a>
+<a name="3577"><span class="lineNum">    3577 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_305[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3578"><span class="lineNum">    3578 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h132)</span></a>
+<a name="3579"><span class="lineNum">    3579 </span><span class="lineNoCov">          0 :         state_vec_306 &lt;=</span></a>
+<a name="3580"><span class="lineNum">    3580 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3581"><span class="lineNum">    3581 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_306[1],</span></a>
+<a name="3582"><span class="lineNum">    3582 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_306[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3583"><span class="lineNum">    3583 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h133)</span></a>
+<a name="3584"><span class="lineNum">    3584 </span><span class="lineNoCov">          0 :         state_vec_307 &lt;=</span></a>
+<a name="3585"><span class="lineNum">    3585 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3586"><span class="lineNum">    3586 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_307[1],</span></a>
+<a name="3587"><span class="lineNum">    3587 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_307[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3588"><span class="lineNum">    3588 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h134)</span></a>
+<a name="3589"><span class="lineNum">    3589 </span><span class="lineNoCov">          0 :         state_vec_308 &lt;=</span></a>
+<a name="3590"><span class="lineNum">    3590 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3591"><span class="lineNum">    3591 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_308[1],</span></a>
+<a name="3592"><span class="lineNum">    3592 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_308[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3593"><span class="lineNum">    3593 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h135)</span></a>
+<a name="3594"><span class="lineNum">    3594 </span><span class="lineNoCov">          0 :         state_vec_309 &lt;=</span></a>
+<a name="3595"><span class="lineNum">    3595 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3596"><span class="lineNum">    3596 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_309[1],</span></a>
+<a name="3597"><span class="lineNum">    3597 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_309[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3598"><span class="lineNum">    3598 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h136)</span></a>
+<a name="3599"><span class="lineNum">    3599 </span><span class="lineNoCov">          0 :         state_vec_310 &lt;=</span></a>
+<a name="3600"><span class="lineNum">    3600 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3601"><span class="lineNum">    3601 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_310[1],</span></a>
+<a name="3602"><span class="lineNum">    3602 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_310[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3603"><span class="lineNum">    3603 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h137)</span></a>
+<a name="3604"><span class="lineNum">    3604 </span><span class="lineNoCov">          0 :         state_vec_311 &lt;=</span></a>
+<a name="3605"><span class="lineNum">    3605 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3606"><span class="lineNum">    3606 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_311[1],</span></a>
+<a name="3607"><span class="lineNum">    3607 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_311[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3608"><span class="lineNum">    3608 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h138)</span></a>
+<a name="3609"><span class="lineNum">    3609 </span><span class="lineNoCov">          0 :         state_vec_312 &lt;=</span></a>
+<a name="3610"><span class="lineNum">    3610 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3611"><span class="lineNum">    3611 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_312[1],</span></a>
+<a name="3612"><span class="lineNum">    3612 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_312[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3613"><span class="lineNum">    3613 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h139)</span></a>
+<a name="3614"><span class="lineNum">    3614 </span><span class="lineNoCov">          0 :         state_vec_313 &lt;=</span></a>
+<a name="3615"><span class="lineNum">    3615 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3616"><span class="lineNum">    3616 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_313[1],</span></a>
+<a name="3617"><span class="lineNum">    3617 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_313[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3618"><span class="lineNum">    3618 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h13A)</span></a>
+<a name="3619"><span class="lineNum">    3619 </span><span class="lineNoCov">          0 :         state_vec_314 &lt;=</span></a>
+<a name="3620"><span class="lineNum">    3620 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3621"><span class="lineNum">    3621 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_314[1],</span></a>
+<a name="3622"><span class="lineNum">    3622 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_314[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3623"><span class="lineNum">    3623 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h13B)</span></a>
+<a name="3624"><span class="lineNum">    3624 </span><span class="lineNoCov">          0 :         state_vec_315 &lt;=</span></a>
+<a name="3625"><span class="lineNum">    3625 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3626"><span class="lineNum">    3626 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_315[1],</span></a>
+<a name="3627"><span class="lineNum">    3627 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_315[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3628"><span class="lineNum">    3628 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h13C)</span></a>
+<a name="3629"><span class="lineNum">    3629 </span><span class="lineNoCov">          0 :         state_vec_316 &lt;=</span></a>
+<a name="3630"><span class="lineNum">    3630 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3631"><span class="lineNum">    3631 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_316[1],</span></a>
+<a name="3632"><span class="lineNum">    3632 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_316[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3633"><span class="lineNum">    3633 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h13D)</span></a>
+<a name="3634"><span class="lineNum">    3634 </span><span class="lineNoCov">          0 :         state_vec_317 &lt;=</span></a>
+<a name="3635"><span class="lineNum">    3635 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3636"><span class="lineNum">    3636 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_317[1],</span></a>
+<a name="3637"><span class="lineNum">    3637 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_317[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3638"><span class="lineNum">    3638 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h13E)</span></a>
+<a name="3639"><span class="lineNum">    3639 </span><span class="lineNoCov">          0 :         state_vec_318 &lt;=</span></a>
+<a name="3640"><span class="lineNum">    3640 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3641"><span class="lineNum">    3641 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_318[1],</span></a>
+<a name="3642"><span class="lineNum">    3642 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_318[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3643"><span class="lineNum">    3643 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h13F)</span></a>
+<a name="3644"><span class="lineNum">    3644 </span><span class="lineNoCov">          0 :         state_vec_319 &lt;=</span></a>
+<a name="3645"><span class="lineNum">    3645 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3646"><span class="lineNum">    3646 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_319[1],</span></a>
+<a name="3647"><span class="lineNum">    3647 </span><span class="lineCov">          2 :            touch_way_0_bits[1] ? state_vec_319[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3648"><span class="lineNum">    3648 </span><span class="lineCov">          1 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h140)</span></a>
+<a name="3649"><span class="lineNum">    3649 </span><span class="lineCov">          1 :         state_vec_320 &lt;=</span></a>
+<a name="3650"><span class="lineNum">    3650 </span><span class="lineCov">          1 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3651"><span class="lineNum">    3651 </span><span class="lineCov">          1 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_320[1],</span></a>
+<a name="3652"><span class="lineNum">    3652 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_320[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3653"><span class="lineNum">    3653 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h141)</span></a>
+<a name="3654"><span class="lineNum">    3654 </span><span class="lineNoCov">          0 :         state_vec_321 &lt;=</span></a>
+<a name="3655"><span class="lineNum">    3655 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3656"><span class="lineNum">    3656 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_321[1],</span></a>
+<a name="3657"><span class="lineNum">    3657 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_321[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3658"><span class="lineNum">    3658 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h142)</span></a>
+<a name="3659"><span class="lineNum">    3659 </span><span class="lineNoCov">          0 :         state_vec_322 &lt;=</span></a>
+<a name="3660"><span class="lineNum">    3660 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3661"><span class="lineNum">    3661 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_322[1],</span></a>
+<a name="3662"><span class="lineNum">    3662 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_322[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3663"><span class="lineNum">    3663 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h143)</span></a>
+<a name="3664"><span class="lineNum">    3664 </span><span class="lineNoCov">          0 :         state_vec_323 &lt;=</span></a>
+<a name="3665"><span class="lineNum">    3665 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3666"><span class="lineNum">    3666 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_323[1],</span></a>
+<a name="3667"><span class="lineNum">    3667 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_323[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3668"><span class="lineNum">    3668 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h144)</span></a>
+<a name="3669"><span class="lineNum">    3669 </span><span class="lineNoCov">          0 :         state_vec_324 &lt;=</span></a>
+<a name="3670"><span class="lineNum">    3670 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3671"><span class="lineNum">    3671 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_324[1],</span></a>
+<a name="3672"><span class="lineNum">    3672 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_324[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3673"><span class="lineNum">    3673 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h145)</span></a>
+<a name="3674"><span class="lineNum">    3674 </span><span class="lineNoCov">          0 :         state_vec_325 &lt;=</span></a>
+<a name="3675"><span class="lineNum">    3675 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3676"><span class="lineNum">    3676 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_325[1],</span></a>
+<a name="3677"><span class="lineNum">    3677 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_325[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3678"><span class="lineNum">    3678 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h146)</span></a>
+<a name="3679"><span class="lineNum">    3679 </span><span class="lineNoCov">          0 :         state_vec_326 &lt;=</span></a>
+<a name="3680"><span class="lineNum">    3680 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3681"><span class="lineNum">    3681 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_326[1],</span></a>
+<a name="3682"><span class="lineNum">    3682 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_326[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3683"><span class="lineNum">    3683 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h147)</span></a>
+<a name="3684"><span class="lineNum">    3684 </span><span class="lineNoCov">          0 :         state_vec_327 &lt;=</span></a>
+<a name="3685"><span class="lineNum">    3685 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3686"><span class="lineNum">    3686 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_327[1],</span></a>
+<a name="3687"><span class="lineNum">    3687 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_327[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3688"><span class="lineNum">    3688 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h148)</span></a>
+<a name="3689"><span class="lineNum">    3689 </span><span class="lineNoCov">          0 :         state_vec_328 &lt;=</span></a>
+<a name="3690"><span class="lineNum">    3690 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3691"><span class="lineNum">    3691 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_328[1],</span></a>
+<a name="3692"><span class="lineNum">    3692 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_328[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3693"><span class="lineNum">    3693 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h149)</span></a>
+<a name="3694"><span class="lineNum">    3694 </span><span class="lineNoCov">          0 :         state_vec_329 &lt;=</span></a>
+<a name="3695"><span class="lineNum">    3695 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3696"><span class="lineNum">    3696 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_329[1],</span></a>
+<a name="3697"><span class="lineNum">    3697 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_329[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3698"><span class="lineNum">    3698 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h14A)</span></a>
+<a name="3699"><span class="lineNum">    3699 </span><span class="lineNoCov">          0 :         state_vec_330 &lt;=</span></a>
+<a name="3700"><span class="lineNum">    3700 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3701"><span class="lineNum">    3701 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_330[1],</span></a>
+<a name="3702"><span class="lineNum">    3702 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_330[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3703"><span class="lineNum">    3703 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h14B)</span></a>
+<a name="3704"><span class="lineNum">    3704 </span><span class="lineNoCov">          0 :         state_vec_331 &lt;=</span></a>
+<a name="3705"><span class="lineNum">    3705 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3706"><span class="lineNum">    3706 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_331[1],</span></a>
+<a name="3707"><span class="lineNum">    3707 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_331[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3708"><span class="lineNum">    3708 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h14C)</span></a>
+<a name="3709"><span class="lineNum">    3709 </span><span class="lineNoCov">          0 :         state_vec_332 &lt;=</span></a>
+<a name="3710"><span class="lineNum">    3710 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3711"><span class="lineNum">    3711 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_332[1],</span></a>
+<a name="3712"><span class="lineNum">    3712 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_332[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3713"><span class="lineNum">    3713 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h14D)</span></a>
+<a name="3714"><span class="lineNum">    3714 </span><span class="lineNoCov">          0 :         state_vec_333 &lt;=</span></a>
+<a name="3715"><span class="lineNum">    3715 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3716"><span class="lineNum">    3716 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_333[1],</span></a>
+<a name="3717"><span class="lineNum">    3717 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_333[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3718"><span class="lineNum">    3718 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h14E)</span></a>
+<a name="3719"><span class="lineNum">    3719 </span><span class="lineNoCov">          0 :         state_vec_334 &lt;=</span></a>
+<a name="3720"><span class="lineNum">    3720 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3721"><span class="lineNum">    3721 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_334[1],</span></a>
+<a name="3722"><span class="lineNum">    3722 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_334[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3723"><span class="lineNum">    3723 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h14F)</span></a>
+<a name="3724"><span class="lineNum">    3724 </span><span class="lineNoCov">          0 :         state_vec_335 &lt;=</span></a>
+<a name="3725"><span class="lineNum">    3725 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3726"><span class="lineNum">    3726 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_335[1],</span></a>
+<a name="3727"><span class="lineNum">    3727 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_335[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3728"><span class="lineNum">    3728 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h150)</span></a>
+<a name="3729"><span class="lineNum">    3729 </span><span class="lineNoCov">          0 :         state_vec_336 &lt;=</span></a>
+<a name="3730"><span class="lineNum">    3730 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3731"><span class="lineNum">    3731 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_336[1],</span></a>
+<a name="3732"><span class="lineNum">    3732 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_336[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3733"><span class="lineNum">    3733 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h151)</span></a>
+<a name="3734"><span class="lineNum">    3734 </span><span class="lineNoCov">          0 :         state_vec_337 &lt;=</span></a>
+<a name="3735"><span class="lineNum">    3735 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3736"><span class="lineNum">    3736 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_337[1],</span></a>
+<a name="3737"><span class="lineNum">    3737 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_337[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3738"><span class="lineNum">    3738 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h152)</span></a>
+<a name="3739"><span class="lineNum">    3739 </span><span class="lineNoCov">          0 :         state_vec_338 &lt;=</span></a>
+<a name="3740"><span class="lineNum">    3740 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3741"><span class="lineNum">    3741 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_338[1],</span></a>
+<a name="3742"><span class="lineNum">    3742 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_338[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3743"><span class="lineNum">    3743 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h153)</span></a>
+<a name="3744"><span class="lineNum">    3744 </span><span class="lineNoCov">          0 :         state_vec_339 &lt;=</span></a>
+<a name="3745"><span class="lineNum">    3745 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3746"><span class="lineNum">    3746 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_339[1],</span></a>
+<a name="3747"><span class="lineNum">    3747 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_339[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3748"><span class="lineNum">    3748 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h154)</span></a>
+<a name="3749"><span class="lineNum">    3749 </span><span class="lineNoCov">          0 :         state_vec_340 &lt;=</span></a>
+<a name="3750"><span class="lineNum">    3750 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3751"><span class="lineNum">    3751 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_340[1],</span></a>
+<a name="3752"><span class="lineNum">    3752 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_340[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3753"><span class="lineNum">    3753 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h155)</span></a>
+<a name="3754"><span class="lineNum">    3754 </span><span class="lineNoCov">          0 :         state_vec_341 &lt;=</span></a>
+<a name="3755"><span class="lineNum">    3755 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3756"><span class="lineNum">    3756 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_341[1],</span></a>
+<a name="3757"><span class="lineNum">    3757 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_341[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3758"><span class="lineNum">    3758 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h156)</span></a>
+<a name="3759"><span class="lineNum">    3759 </span><span class="lineNoCov">          0 :         state_vec_342 &lt;=</span></a>
+<a name="3760"><span class="lineNum">    3760 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3761"><span class="lineNum">    3761 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_342[1],</span></a>
+<a name="3762"><span class="lineNum">    3762 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_342[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3763"><span class="lineNum">    3763 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h157)</span></a>
+<a name="3764"><span class="lineNum">    3764 </span><span class="lineNoCov">          0 :         state_vec_343 &lt;=</span></a>
+<a name="3765"><span class="lineNum">    3765 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3766"><span class="lineNum">    3766 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_343[1],</span></a>
+<a name="3767"><span class="lineNum">    3767 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_343[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3768"><span class="lineNum">    3768 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h158)</span></a>
+<a name="3769"><span class="lineNum">    3769 </span><span class="lineNoCov">          0 :         state_vec_344 &lt;=</span></a>
+<a name="3770"><span class="lineNum">    3770 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3771"><span class="lineNum">    3771 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_344[1],</span></a>
+<a name="3772"><span class="lineNum">    3772 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_344[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3773"><span class="lineNum">    3773 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h159)</span></a>
+<a name="3774"><span class="lineNum">    3774 </span><span class="lineNoCov">          0 :         state_vec_345 &lt;=</span></a>
+<a name="3775"><span class="lineNum">    3775 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3776"><span class="lineNum">    3776 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_345[1],</span></a>
+<a name="3777"><span class="lineNum">    3777 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_345[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3778"><span class="lineNum">    3778 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h15A)</span></a>
+<a name="3779"><span class="lineNum">    3779 </span><span class="lineNoCov">          0 :         state_vec_346 &lt;=</span></a>
+<a name="3780"><span class="lineNum">    3780 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3781"><span class="lineNum">    3781 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_346[1],</span></a>
+<a name="3782"><span class="lineNum">    3782 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_346[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3783"><span class="lineNum">    3783 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h15B)</span></a>
+<a name="3784"><span class="lineNum">    3784 </span><span class="lineNoCov">          0 :         state_vec_347 &lt;=</span></a>
+<a name="3785"><span class="lineNum">    3785 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3786"><span class="lineNum">    3786 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_347[1],</span></a>
+<a name="3787"><span class="lineNum">    3787 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_347[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3788"><span class="lineNum">    3788 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h15C)</span></a>
+<a name="3789"><span class="lineNum">    3789 </span><span class="lineNoCov">          0 :         state_vec_348 &lt;=</span></a>
+<a name="3790"><span class="lineNum">    3790 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3791"><span class="lineNum">    3791 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_348[1],</span></a>
+<a name="3792"><span class="lineNum">    3792 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_348[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3793"><span class="lineNum">    3793 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h15D)</span></a>
+<a name="3794"><span class="lineNum">    3794 </span><span class="lineNoCov">          0 :         state_vec_349 &lt;=</span></a>
+<a name="3795"><span class="lineNum">    3795 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3796"><span class="lineNum">    3796 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_349[1],</span></a>
+<a name="3797"><span class="lineNum">    3797 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_349[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3798"><span class="lineNum">    3798 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h15E)</span></a>
+<a name="3799"><span class="lineNum">    3799 </span><span class="lineNoCov">          0 :         state_vec_350 &lt;=</span></a>
+<a name="3800"><span class="lineNum">    3800 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3801"><span class="lineNum">    3801 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_350[1],</span></a>
+<a name="3802"><span class="lineNum">    3802 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_350[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3803"><span class="lineNum">    3803 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h15F)</span></a>
+<a name="3804"><span class="lineNum">    3804 </span><span class="lineNoCov">          0 :         state_vec_351 &lt;=</span></a>
+<a name="3805"><span class="lineNum">    3805 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3806"><span class="lineNum">    3806 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_351[1],</span></a>
+<a name="3807"><span class="lineNum">    3807 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_351[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3808"><span class="lineNum">    3808 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h160)</span></a>
+<a name="3809"><span class="lineNum">    3809 </span><span class="lineNoCov">          0 :         state_vec_352 &lt;=</span></a>
+<a name="3810"><span class="lineNum">    3810 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3811"><span class="lineNum">    3811 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_352[1],</span></a>
+<a name="3812"><span class="lineNum">    3812 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_352[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3813"><span class="lineNum">    3813 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h161)</span></a>
+<a name="3814"><span class="lineNum">    3814 </span><span class="lineNoCov">          0 :         state_vec_353 &lt;=</span></a>
+<a name="3815"><span class="lineNum">    3815 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3816"><span class="lineNum">    3816 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_353[1],</span></a>
+<a name="3817"><span class="lineNum">    3817 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_353[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3818"><span class="lineNum">    3818 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h162)</span></a>
+<a name="3819"><span class="lineNum">    3819 </span><span class="lineNoCov">          0 :         state_vec_354 &lt;=</span></a>
+<a name="3820"><span class="lineNum">    3820 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3821"><span class="lineNum">    3821 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_354[1],</span></a>
+<a name="3822"><span class="lineNum">    3822 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_354[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3823"><span class="lineNum">    3823 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h163)</span></a>
+<a name="3824"><span class="lineNum">    3824 </span><span class="lineNoCov">          0 :         state_vec_355 &lt;=</span></a>
+<a name="3825"><span class="lineNum">    3825 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3826"><span class="lineNum">    3826 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_355[1],</span></a>
+<a name="3827"><span class="lineNum">    3827 </span><span class="lineCov">          2 :            touch_way_0_bits[1] ? state_vec_355[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3828"><span class="lineNum">    3828 </span><span class="lineCov">          1 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h164)</span></a>
+<a name="3829"><span class="lineNum">    3829 </span><span class="lineCov">          1 :         state_vec_356 &lt;=</span></a>
+<a name="3830"><span class="lineNum">    3830 </span><span class="lineCov">          1 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3831"><span class="lineNum">    3831 </span><span class="lineCov">          1 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_356[1],</span></a>
+<a name="3832"><span class="lineNum">    3832 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_356[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3833"><span class="lineNum">    3833 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h165)</span></a>
+<a name="3834"><span class="lineNum">    3834 </span><span class="lineNoCov">          0 :         state_vec_357 &lt;=</span></a>
+<a name="3835"><span class="lineNum">    3835 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3836"><span class="lineNum">    3836 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_357[1],</span></a>
+<a name="3837"><span class="lineNum">    3837 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_357[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3838"><span class="lineNum">    3838 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h166)</span></a>
+<a name="3839"><span class="lineNum">    3839 </span><span class="lineNoCov">          0 :         state_vec_358 &lt;=</span></a>
+<a name="3840"><span class="lineNum">    3840 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3841"><span class="lineNum">    3841 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_358[1],</span></a>
+<a name="3842"><span class="lineNum">    3842 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_358[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3843"><span class="lineNum">    3843 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h167)</span></a>
+<a name="3844"><span class="lineNum">    3844 </span><span class="lineNoCov">          0 :         state_vec_359 &lt;=</span></a>
+<a name="3845"><span class="lineNum">    3845 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3846"><span class="lineNum">    3846 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_359[1],</span></a>
+<a name="3847"><span class="lineNum">    3847 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_359[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3848"><span class="lineNum">    3848 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h168)</span></a>
+<a name="3849"><span class="lineNum">    3849 </span><span class="lineNoCov">          0 :         state_vec_360 &lt;=</span></a>
+<a name="3850"><span class="lineNum">    3850 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3851"><span class="lineNum">    3851 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_360[1],</span></a>
+<a name="3852"><span class="lineNum">    3852 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_360[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3853"><span class="lineNum">    3853 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h169)</span></a>
+<a name="3854"><span class="lineNum">    3854 </span><span class="lineNoCov">          0 :         state_vec_361 &lt;=</span></a>
+<a name="3855"><span class="lineNum">    3855 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3856"><span class="lineNum">    3856 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_361[1],</span></a>
+<a name="3857"><span class="lineNum">    3857 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_361[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3858"><span class="lineNum">    3858 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h16A)</span></a>
+<a name="3859"><span class="lineNum">    3859 </span><span class="lineNoCov">          0 :         state_vec_362 &lt;=</span></a>
+<a name="3860"><span class="lineNum">    3860 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3861"><span class="lineNum">    3861 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_362[1],</span></a>
+<a name="3862"><span class="lineNum">    3862 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_362[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3863"><span class="lineNum">    3863 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h16B)</span></a>
+<a name="3864"><span class="lineNum">    3864 </span><span class="lineNoCov">          0 :         state_vec_363 &lt;=</span></a>
+<a name="3865"><span class="lineNum">    3865 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3866"><span class="lineNum">    3866 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_363[1],</span></a>
+<a name="3867"><span class="lineNum">    3867 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_363[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3868"><span class="lineNum">    3868 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h16C)</span></a>
+<a name="3869"><span class="lineNum">    3869 </span><span class="lineNoCov">          0 :         state_vec_364 &lt;=</span></a>
+<a name="3870"><span class="lineNum">    3870 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3871"><span class="lineNum">    3871 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_364[1],</span></a>
+<a name="3872"><span class="lineNum">    3872 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_364[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3873"><span class="lineNum">    3873 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h16D)</span></a>
+<a name="3874"><span class="lineNum">    3874 </span><span class="lineNoCov">          0 :         state_vec_365 &lt;=</span></a>
+<a name="3875"><span class="lineNum">    3875 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3876"><span class="lineNum">    3876 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_365[1],</span></a>
+<a name="3877"><span class="lineNum">    3877 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_365[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3878"><span class="lineNum">    3878 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h16E)</span></a>
+<a name="3879"><span class="lineNum">    3879 </span><span class="lineNoCov">          0 :         state_vec_366 &lt;=</span></a>
+<a name="3880"><span class="lineNum">    3880 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3881"><span class="lineNum">    3881 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_366[1],</span></a>
+<a name="3882"><span class="lineNum">    3882 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_366[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3883"><span class="lineNum">    3883 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h16F)</span></a>
+<a name="3884"><span class="lineNum">    3884 </span><span class="lineNoCov">          0 :         state_vec_367 &lt;=</span></a>
+<a name="3885"><span class="lineNum">    3885 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3886"><span class="lineNum">    3886 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_367[1],</span></a>
+<a name="3887"><span class="lineNum">    3887 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_367[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3888"><span class="lineNum">    3888 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h170)</span></a>
+<a name="3889"><span class="lineNum">    3889 </span><span class="lineNoCov">          0 :         state_vec_368 &lt;=</span></a>
+<a name="3890"><span class="lineNum">    3890 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3891"><span class="lineNum">    3891 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_368[1],</span></a>
+<a name="3892"><span class="lineNum">    3892 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_368[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3893"><span class="lineNum">    3893 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h171)</span></a>
+<a name="3894"><span class="lineNum">    3894 </span><span class="lineNoCov">          0 :         state_vec_369 &lt;=</span></a>
+<a name="3895"><span class="lineNum">    3895 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3896"><span class="lineNum">    3896 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_369[1],</span></a>
+<a name="3897"><span class="lineNum">    3897 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_369[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3898"><span class="lineNum">    3898 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h172)</span></a>
+<a name="3899"><span class="lineNum">    3899 </span><span class="lineNoCov">          0 :         state_vec_370 &lt;=</span></a>
+<a name="3900"><span class="lineNum">    3900 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3901"><span class="lineNum">    3901 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_370[1],</span></a>
+<a name="3902"><span class="lineNum">    3902 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_370[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3903"><span class="lineNum">    3903 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h173)</span></a>
+<a name="3904"><span class="lineNum">    3904 </span><span class="lineNoCov">          0 :         state_vec_371 &lt;=</span></a>
+<a name="3905"><span class="lineNum">    3905 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3906"><span class="lineNum">    3906 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_371[1],</span></a>
+<a name="3907"><span class="lineNum">    3907 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_371[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3908"><span class="lineNum">    3908 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h174)</span></a>
+<a name="3909"><span class="lineNum">    3909 </span><span class="lineNoCov">          0 :         state_vec_372 &lt;=</span></a>
+<a name="3910"><span class="lineNum">    3910 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3911"><span class="lineNum">    3911 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_372[1],</span></a>
+<a name="3912"><span class="lineNum">    3912 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_372[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3913"><span class="lineNum">    3913 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h175)</span></a>
+<a name="3914"><span class="lineNum">    3914 </span><span class="lineNoCov">          0 :         state_vec_373 &lt;=</span></a>
+<a name="3915"><span class="lineNum">    3915 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3916"><span class="lineNum">    3916 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_373[1],</span></a>
+<a name="3917"><span class="lineNum">    3917 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_373[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3918"><span class="lineNum">    3918 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h176)</span></a>
+<a name="3919"><span class="lineNum">    3919 </span><span class="lineNoCov">          0 :         state_vec_374 &lt;=</span></a>
+<a name="3920"><span class="lineNum">    3920 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3921"><span class="lineNum">    3921 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_374[1],</span></a>
+<a name="3922"><span class="lineNum">    3922 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_374[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3923"><span class="lineNum">    3923 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h177)</span></a>
+<a name="3924"><span class="lineNum">    3924 </span><span class="lineNoCov">          0 :         state_vec_375 &lt;=</span></a>
+<a name="3925"><span class="lineNum">    3925 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3926"><span class="lineNum">    3926 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_375[1],</span></a>
+<a name="3927"><span class="lineNum">    3927 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_375[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3928"><span class="lineNum">    3928 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h178)</span></a>
+<a name="3929"><span class="lineNum">    3929 </span><span class="lineNoCov">          0 :         state_vec_376 &lt;=</span></a>
+<a name="3930"><span class="lineNum">    3930 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3931"><span class="lineNum">    3931 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_376[1],</span></a>
+<a name="3932"><span class="lineNum">    3932 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_376[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3933"><span class="lineNum">    3933 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h179)</span></a>
+<a name="3934"><span class="lineNum">    3934 </span><span class="lineNoCov">          0 :         state_vec_377 &lt;=</span></a>
+<a name="3935"><span class="lineNum">    3935 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3936"><span class="lineNum">    3936 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_377[1],</span></a>
+<a name="3937"><span class="lineNum">    3937 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_377[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3938"><span class="lineNum">    3938 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h17A)</span></a>
+<a name="3939"><span class="lineNum">    3939 </span><span class="lineNoCov">          0 :         state_vec_378 &lt;=</span></a>
+<a name="3940"><span class="lineNum">    3940 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3941"><span class="lineNum">    3941 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_378[1],</span></a>
+<a name="3942"><span class="lineNum">    3942 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_378[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3943"><span class="lineNum">    3943 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h17B)</span></a>
+<a name="3944"><span class="lineNum">    3944 </span><span class="lineNoCov">          0 :         state_vec_379 &lt;=</span></a>
+<a name="3945"><span class="lineNum">    3945 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3946"><span class="lineNum">    3946 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_379[1],</span></a>
+<a name="3947"><span class="lineNum">    3947 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_379[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3948"><span class="lineNum">    3948 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h17C)</span></a>
+<a name="3949"><span class="lineNum">    3949 </span><span class="lineNoCov">          0 :         state_vec_380 &lt;=</span></a>
+<a name="3950"><span class="lineNum">    3950 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3951"><span class="lineNum">    3951 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_380[1],</span></a>
+<a name="3952"><span class="lineNum">    3952 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_380[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3953"><span class="lineNum">    3953 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h17D)</span></a>
+<a name="3954"><span class="lineNum">    3954 </span><span class="lineNoCov">          0 :         state_vec_381 &lt;=</span></a>
+<a name="3955"><span class="lineNum">    3955 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3956"><span class="lineNum">    3956 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_381[1],</span></a>
+<a name="3957"><span class="lineNum">    3957 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_381[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3958"><span class="lineNum">    3958 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h17E)</span></a>
+<a name="3959"><span class="lineNum">    3959 </span><span class="lineNoCov">          0 :         state_vec_382 &lt;=</span></a>
+<a name="3960"><span class="lineNum">    3960 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3961"><span class="lineNum">    3961 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_382[1],</span></a>
+<a name="3962"><span class="lineNum">    3962 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_382[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3963"><span class="lineNum">    3963 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h17F)</span></a>
+<a name="3964"><span class="lineNum">    3964 </span><span class="lineNoCov">          0 :         state_vec_383 &lt;=</span></a>
+<a name="3965"><span class="lineNum">    3965 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3966"><span class="lineNum">    3966 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_383[1],</span></a>
+<a name="3967"><span class="lineNum">    3967 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_383[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3968"><span class="lineNum">    3968 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h180)</span></a>
+<a name="3969"><span class="lineNum">    3969 </span><span class="lineNoCov">          0 :         state_vec_384 &lt;=</span></a>
+<a name="3970"><span class="lineNum">    3970 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3971"><span class="lineNum">    3971 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_384[1],</span></a>
+<a name="3972"><span class="lineNum">    3972 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_384[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3973"><span class="lineNum">    3973 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h181)</span></a>
+<a name="3974"><span class="lineNum">    3974 </span><span class="lineNoCov">          0 :         state_vec_385 &lt;=</span></a>
+<a name="3975"><span class="lineNum">    3975 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3976"><span class="lineNum">    3976 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_385[1],</span></a>
+<a name="3977"><span class="lineNum">    3977 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_385[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3978"><span class="lineNum">    3978 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h182)</span></a>
+<a name="3979"><span class="lineNum">    3979 </span><span class="lineNoCov">          0 :         state_vec_386 &lt;=</span></a>
+<a name="3980"><span class="lineNum">    3980 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3981"><span class="lineNum">    3981 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_386[1],</span></a>
+<a name="3982"><span class="lineNum">    3982 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_386[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3983"><span class="lineNum">    3983 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h183)</span></a>
+<a name="3984"><span class="lineNum">    3984 </span><span class="lineNoCov">          0 :         state_vec_387 &lt;=</span></a>
+<a name="3985"><span class="lineNum">    3985 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3986"><span class="lineNum">    3986 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_387[1],</span></a>
+<a name="3987"><span class="lineNum">    3987 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_387[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3988"><span class="lineNum">    3988 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h184)</span></a>
+<a name="3989"><span class="lineNum">    3989 </span><span class="lineNoCov">          0 :         state_vec_388 &lt;=</span></a>
+<a name="3990"><span class="lineNum">    3990 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3991"><span class="lineNum">    3991 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_388[1],</span></a>
+<a name="3992"><span class="lineNum">    3992 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_388[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3993"><span class="lineNum">    3993 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h185)</span></a>
+<a name="3994"><span class="lineNum">    3994 </span><span class="lineNoCov">          0 :         state_vec_389 &lt;=</span></a>
+<a name="3995"><span class="lineNum">    3995 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="3996"><span class="lineNum">    3996 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_389[1],</span></a>
+<a name="3997"><span class="lineNum">    3997 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_389[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="3998"><span class="lineNum">    3998 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h186)</span></a>
+<a name="3999"><span class="lineNum">    3999 </span><span class="lineNoCov">          0 :         state_vec_390 &lt;=</span></a>
+<a name="4000"><span class="lineNum">    4000 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4001"><span class="lineNum">    4001 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_390[1],</span></a>
+<a name="4002"><span class="lineNum">    4002 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_390[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4003"><span class="lineNum">    4003 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h187)</span></a>
+<a name="4004"><span class="lineNum">    4004 </span><span class="lineNoCov">          0 :         state_vec_391 &lt;=</span></a>
+<a name="4005"><span class="lineNum">    4005 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4006"><span class="lineNum">    4006 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_391[1],</span></a>
+<a name="4007"><span class="lineNum">    4007 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_391[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4008"><span class="lineNum">    4008 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h188)</span></a>
+<a name="4009"><span class="lineNum">    4009 </span><span class="lineNoCov">          0 :         state_vec_392 &lt;=</span></a>
+<a name="4010"><span class="lineNum">    4010 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4011"><span class="lineNum">    4011 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_392[1],</span></a>
+<a name="4012"><span class="lineNum">    4012 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_392[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4013"><span class="lineNum">    4013 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h189)</span></a>
+<a name="4014"><span class="lineNum">    4014 </span><span class="lineNoCov">          0 :         state_vec_393 &lt;=</span></a>
+<a name="4015"><span class="lineNum">    4015 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4016"><span class="lineNum">    4016 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_393[1],</span></a>
+<a name="4017"><span class="lineNum">    4017 </span><span class="lineCov">          2 :            touch_way_0_bits[1] ? state_vec_393[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4018"><span class="lineNum">    4018 </span><span class="lineCov">          1 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h18A)</span></a>
+<a name="4019"><span class="lineNum">    4019 </span><span class="lineCov">          1 :         state_vec_394 &lt;=</span></a>
+<a name="4020"><span class="lineNum">    4020 </span><span class="lineCov">          1 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4021"><span class="lineNum">    4021 </span><span class="lineCov">          1 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_394[1],</span></a>
+<a name="4022"><span class="lineNum">    4022 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_394[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4023"><span class="lineNum">    4023 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h18B)</span></a>
+<a name="4024"><span class="lineNum">    4024 </span><span class="lineNoCov">          0 :         state_vec_395 &lt;=</span></a>
+<a name="4025"><span class="lineNum">    4025 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4026"><span class="lineNum">    4026 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_395[1],</span></a>
+<a name="4027"><span class="lineNum">    4027 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_395[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4028"><span class="lineNum">    4028 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h18C)</span></a>
+<a name="4029"><span class="lineNum">    4029 </span><span class="lineNoCov">          0 :         state_vec_396 &lt;=</span></a>
+<a name="4030"><span class="lineNum">    4030 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4031"><span class="lineNum">    4031 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_396[1],</span></a>
+<a name="4032"><span class="lineNum">    4032 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_396[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4033"><span class="lineNum">    4033 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h18D)</span></a>
+<a name="4034"><span class="lineNum">    4034 </span><span class="lineNoCov">          0 :         state_vec_397 &lt;=</span></a>
+<a name="4035"><span class="lineNum">    4035 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4036"><span class="lineNum">    4036 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_397[1],</span></a>
+<a name="4037"><span class="lineNum">    4037 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_397[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4038"><span class="lineNum">    4038 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h18E)</span></a>
+<a name="4039"><span class="lineNum">    4039 </span><span class="lineNoCov">          0 :         state_vec_398 &lt;=</span></a>
+<a name="4040"><span class="lineNum">    4040 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4041"><span class="lineNum">    4041 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_398[1],</span></a>
+<a name="4042"><span class="lineNum">    4042 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_398[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4043"><span class="lineNum">    4043 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h18F)</span></a>
+<a name="4044"><span class="lineNum">    4044 </span><span class="lineNoCov">          0 :         state_vec_399 &lt;=</span></a>
+<a name="4045"><span class="lineNum">    4045 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4046"><span class="lineNum">    4046 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_399[1],</span></a>
+<a name="4047"><span class="lineNum">    4047 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_399[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4048"><span class="lineNum">    4048 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h190)</span></a>
+<a name="4049"><span class="lineNum">    4049 </span><span class="lineNoCov">          0 :         state_vec_400 &lt;=</span></a>
+<a name="4050"><span class="lineNum">    4050 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4051"><span class="lineNum">    4051 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_400[1],</span></a>
+<a name="4052"><span class="lineNum">    4052 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_400[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4053"><span class="lineNum">    4053 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h191)</span></a>
+<a name="4054"><span class="lineNum">    4054 </span><span class="lineNoCov">          0 :         state_vec_401 &lt;=</span></a>
+<a name="4055"><span class="lineNum">    4055 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4056"><span class="lineNum">    4056 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_401[1],</span></a>
+<a name="4057"><span class="lineNum">    4057 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_401[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4058"><span class="lineNum">    4058 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h192)</span></a>
+<a name="4059"><span class="lineNum">    4059 </span><span class="lineNoCov">          0 :         state_vec_402 &lt;=</span></a>
+<a name="4060"><span class="lineNum">    4060 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4061"><span class="lineNum">    4061 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_402[1],</span></a>
+<a name="4062"><span class="lineNum">    4062 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_402[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4063"><span class="lineNum">    4063 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h193)</span></a>
+<a name="4064"><span class="lineNum">    4064 </span><span class="lineNoCov">          0 :         state_vec_403 &lt;=</span></a>
+<a name="4065"><span class="lineNum">    4065 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4066"><span class="lineNum">    4066 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_403[1],</span></a>
+<a name="4067"><span class="lineNum">    4067 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_403[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4068"><span class="lineNum">    4068 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h194)</span></a>
+<a name="4069"><span class="lineNum">    4069 </span><span class="lineNoCov">          0 :         state_vec_404 &lt;=</span></a>
+<a name="4070"><span class="lineNum">    4070 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4071"><span class="lineNum">    4071 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_404[1],</span></a>
+<a name="4072"><span class="lineNum">    4072 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_404[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4073"><span class="lineNum">    4073 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h195)</span></a>
+<a name="4074"><span class="lineNum">    4074 </span><span class="lineNoCov">          0 :         state_vec_405 &lt;=</span></a>
+<a name="4075"><span class="lineNum">    4075 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4076"><span class="lineNum">    4076 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_405[1],</span></a>
+<a name="4077"><span class="lineNum">    4077 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_405[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4078"><span class="lineNum">    4078 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h196)</span></a>
+<a name="4079"><span class="lineNum">    4079 </span><span class="lineNoCov">          0 :         state_vec_406 &lt;=</span></a>
+<a name="4080"><span class="lineNum">    4080 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4081"><span class="lineNum">    4081 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_406[1],</span></a>
+<a name="4082"><span class="lineNum">    4082 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_406[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4083"><span class="lineNum">    4083 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h197)</span></a>
+<a name="4084"><span class="lineNum">    4084 </span><span class="lineNoCov">          0 :         state_vec_407 &lt;=</span></a>
+<a name="4085"><span class="lineNum">    4085 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4086"><span class="lineNum">    4086 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_407[1],</span></a>
+<a name="4087"><span class="lineNum">    4087 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_407[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4088"><span class="lineNum">    4088 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h198)</span></a>
+<a name="4089"><span class="lineNum">    4089 </span><span class="lineNoCov">          0 :         state_vec_408 &lt;=</span></a>
+<a name="4090"><span class="lineNum">    4090 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4091"><span class="lineNum">    4091 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_408[1],</span></a>
+<a name="4092"><span class="lineNum">    4092 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_408[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4093"><span class="lineNum">    4093 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h199)</span></a>
+<a name="4094"><span class="lineNum">    4094 </span><span class="lineNoCov">          0 :         state_vec_409 &lt;=</span></a>
+<a name="4095"><span class="lineNum">    4095 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4096"><span class="lineNum">    4096 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_409[1],</span></a>
+<a name="4097"><span class="lineNum">    4097 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_409[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4098"><span class="lineNum">    4098 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h19A)</span></a>
+<a name="4099"><span class="lineNum">    4099 </span><span class="lineNoCov">          0 :         state_vec_410 &lt;=</span></a>
+<a name="4100"><span class="lineNum">    4100 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4101"><span class="lineNum">    4101 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_410[1],</span></a>
+<a name="4102"><span class="lineNum">    4102 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_410[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4103"><span class="lineNum">    4103 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h19B)</span></a>
+<a name="4104"><span class="lineNum">    4104 </span><span class="lineNoCov">          0 :         state_vec_411 &lt;=</span></a>
+<a name="4105"><span class="lineNum">    4105 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4106"><span class="lineNum">    4106 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_411[1],</span></a>
+<a name="4107"><span class="lineNum">    4107 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_411[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4108"><span class="lineNum">    4108 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h19C)</span></a>
+<a name="4109"><span class="lineNum">    4109 </span><span class="lineNoCov">          0 :         state_vec_412 &lt;=</span></a>
+<a name="4110"><span class="lineNum">    4110 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4111"><span class="lineNum">    4111 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_412[1],</span></a>
+<a name="4112"><span class="lineNum">    4112 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_412[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4113"><span class="lineNum">    4113 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h19D)</span></a>
+<a name="4114"><span class="lineNum">    4114 </span><span class="lineNoCov">          0 :         state_vec_413 &lt;=</span></a>
+<a name="4115"><span class="lineNum">    4115 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4116"><span class="lineNum">    4116 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_413[1],</span></a>
+<a name="4117"><span class="lineNum">    4117 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_413[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4118"><span class="lineNum">    4118 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h19E)</span></a>
+<a name="4119"><span class="lineNum">    4119 </span><span class="lineNoCov">          0 :         state_vec_414 &lt;=</span></a>
+<a name="4120"><span class="lineNum">    4120 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4121"><span class="lineNum">    4121 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_414[1],</span></a>
+<a name="4122"><span class="lineNum">    4122 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_414[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4123"><span class="lineNum">    4123 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h19F)</span></a>
+<a name="4124"><span class="lineNum">    4124 </span><span class="lineNoCov">          0 :         state_vec_415 &lt;=</span></a>
+<a name="4125"><span class="lineNum">    4125 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4126"><span class="lineNum">    4126 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_415[1],</span></a>
+<a name="4127"><span class="lineNum">    4127 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_415[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4128"><span class="lineNum">    4128 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1A0)</span></a>
+<a name="4129"><span class="lineNum">    4129 </span><span class="lineNoCov">          0 :         state_vec_416 &lt;=</span></a>
+<a name="4130"><span class="lineNum">    4130 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4131"><span class="lineNum">    4131 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_416[1],</span></a>
+<a name="4132"><span class="lineNum">    4132 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_416[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4133"><span class="lineNum">    4133 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1A1)</span></a>
+<a name="4134"><span class="lineNum">    4134 </span><span class="lineNoCov">          0 :         state_vec_417 &lt;=</span></a>
+<a name="4135"><span class="lineNum">    4135 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4136"><span class="lineNum">    4136 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_417[1],</span></a>
+<a name="4137"><span class="lineNum">    4137 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_417[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4138"><span class="lineNum">    4138 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1A2)</span></a>
+<a name="4139"><span class="lineNum">    4139 </span><span class="lineNoCov">          0 :         state_vec_418 &lt;=</span></a>
+<a name="4140"><span class="lineNum">    4140 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4141"><span class="lineNum">    4141 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_418[1],</span></a>
+<a name="4142"><span class="lineNum">    4142 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_418[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4143"><span class="lineNum">    4143 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1A3)</span></a>
+<a name="4144"><span class="lineNum">    4144 </span><span class="lineNoCov">          0 :         state_vec_419 &lt;=</span></a>
+<a name="4145"><span class="lineNum">    4145 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4146"><span class="lineNum">    4146 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_419[1],</span></a>
+<a name="4147"><span class="lineNum">    4147 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_419[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4148"><span class="lineNum">    4148 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1A4)</span></a>
+<a name="4149"><span class="lineNum">    4149 </span><span class="lineNoCov">          0 :         state_vec_420 &lt;=</span></a>
+<a name="4150"><span class="lineNum">    4150 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4151"><span class="lineNum">    4151 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_420[1],</span></a>
+<a name="4152"><span class="lineNum">    4152 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_420[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4153"><span class="lineNum">    4153 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1A5)</span></a>
+<a name="4154"><span class="lineNum">    4154 </span><span class="lineNoCov">          0 :         state_vec_421 &lt;=</span></a>
+<a name="4155"><span class="lineNum">    4155 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4156"><span class="lineNum">    4156 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_421[1],</span></a>
+<a name="4157"><span class="lineNum">    4157 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_421[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4158"><span class="lineNum">    4158 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1A6)</span></a>
+<a name="4159"><span class="lineNum">    4159 </span><span class="lineNoCov">          0 :         state_vec_422 &lt;=</span></a>
+<a name="4160"><span class="lineNum">    4160 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4161"><span class="lineNum">    4161 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_422[1],</span></a>
+<a name="4162"><span class="lineNum">    4162 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_422[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4163"><span class="lineNum">    4163 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1A7)</span></a>
+<a name="4164"><span class="lineNum">    4164 </span><span class="lineNoCov">          0 :         state_vec_423 &lt;=</span></a>
+<a name="4165"><span class="lineNum">    4165 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4166"><span class="lineNum">    4166 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_423[1],</span></a>
+<a name="4167"><span class="lineNum">    4167 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_423[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4168"><span class="lineNum">    4168 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1A8)</span></a>
+<a name="4169"><span class="lineNum">    4169 </span><span class="lineNoCov">          0 :         state_vec_424 &lt;=</span></a>
+<a name="4170"><span class="lineNum">    4170 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4171"><span class="lineNum">    4171 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_424[1],</span></a>
+<a name="4172"><span class="lineNum">    4172 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_424[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4173"><span class="lineNum">    4173 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1A9)</span></a>
+<a name="4174"><span class="lineNum">    4174 </span><span class="lineNoCov">          0 :         state_vec_425 &lt;=</span></a>
+<a name="4175"><span class="lineNum">    4175 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4176"><span class="lineNum">    4176 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_425[1],</span></a>
+<a name="4177"><span class="lineNum">    4177 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_425[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4178"><span class="lineNum">    4178 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1AA)</span></a>
+<a name="4179"><span class="lineNum">    4179 </span><span class="lineNoCov">          0 :         state_vec_426 &lt;=</span></a>
+<a name="4180"><span class="lineNum">    4180 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4181"><span class="lineNum">    4181 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_426[1],</span></a>
+<a name="4182"><span class="lineNum">    4182 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_426[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4183"><span class="lineNum">    4183 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1AB)</span></a>
+<a name="4184"><span class="lineNum">    4184 </span><span class="lineNoCov">          0 :         state_vec_427 &lt;=</span></a>
+<a name="4185"><span class="lineNum">    4185 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4186"><span class="lineNum">    4186 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_427[1],</span></a>
+<a name="4187"><span class="lineNum">    4187 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_427[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4188"><span class="lineNum">    4188 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1AC)</span></a>
+<a name="4189"><span class="lineNum">    4189 </span><span class="lineNoCov">          0 :         state_vec_428 &lt;=</span></a>
+<a name="4190"><span class="lineNum">    4190 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4191"><span class="lineNum">    4191 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_428[1],</span></a>
+<a name="4192"><span class="lineNum">    4192 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_428[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4193"><span class="lineNum">    4193 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1AD)</span></a>
+<a name="4194"><span class="lineNum">    4194 </span><span class="lineNoCov">          0 :         state_vec_429 &lt;=</span></a>
+<a name="4195"><span class="lineNum">    4195 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4196"><span class="lineNum">    4196 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_429[1],</span></a>
+<a name="4197"><span class="lineNum">    4197 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_429[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4198"><span class="lineNum">    4198 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1AE)</span></a>
+<a name="4199"><span class="lineNum">    4199 </span><span class="lineNoCov">          0 :         state_vec_430 &lt;=</span></a>
+<a name="4200"><span class="lineNum">    4200 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4201"><span class="lineNum">    4201 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_430[1],</span></a>
+<a name="4202"><span class="lineNum">    4202 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_430[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4203"><span class="lineNum">    4203 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1AF)</span></a>
+<a name="4204"><span class="lineNum">    4204 </span><span class="lineNoCov">          0 :         state_vec_431 &lt;=</span></a>
+<a name="4205"><span class="lineNum">    4205 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4206"><span class="lineNum">    4206 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_431[1],</span></a>
+<a name="4207"><span class="lineNum">    4207 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_431[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4208"><span class="lineNum">    4208 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1B0)</span></a>
+<a name="4209"><span class="lineNum">    4209 </span><span class="lineNoCov">          0 :         state_vec_432 &lt;=</span></a>
+<a name="4210"><span class="lineNum">    4210 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4211"><span class="lineNum">    4211 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_432[1],</span></a>
+<a name="4212"><span class="lineNum">    4212 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_432[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4213"><span class="lineNum">    4213 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1B1)</span></a>
+<a name="4214"><span class="lineNum">    4214 </span><span class="lineNoCov">          0 :         state_vec_433 &lt;=</span></a>
+<a name="4215"><span class="lineNum">    4215 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4216"><span class="lineNum">    4216 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_433[1],</span></a>
+<a name="4217"><span class="lineNum">    4217 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_433[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4218"><span class="lineNum">    4218 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1B2)</span></a>
+<a name="4219"><span class="lineNum">    4219 </span><span class="lineNoCov">          0 :         state_vec_434 &lt;=</span></a>
+<a name="4220"><span class="lineNum">    4220 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4221"><span class="lineNum">    4221 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_434[1],</span></a>
+<a name="4222"><span class="lineNum">    4222 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_434[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4223"><span class="lineNum">    4223 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1B3)</span></a>
+<a name="4224"><span class="lineNum">    4224 </span><span class="lineNoCov">          0 :         state_vec_435 &lt;=</span></a>
+<a name="4225"><span class="lineNum">    4225 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4226"><span class="lineNum">    4226 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_435[1],</span></a>
+<a name="4227"><span class="lineNum">    4227 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_435[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4228"><span class="lineNum">    4228 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1B4)</span></a>
+<a name="4229"><span class="lineNum">    4229 </span><span class="lineNoCov">          0 :         state_vec_436 &lt;=</span></a>
+<a name="4230"><span class="lineNum">    4230 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4231"><span class="lineNum">    4231 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_436[1],</span></a>
+<a name="4232"><span class="lineNum">    4232 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_436[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4233"><span class="lineNum">    4233 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1B5)</span></a>
+<a name="4234"><span class="lineNum">    4234 </span><span class="lineNoCov">          0 :         state_vec_437 &lt;=</span></a>
+<a name="4235"><span class="lineNum">    4235 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4236"><span class="lineNum">    4236 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_437[1],</span></a>
+<a name="4237"><span class="lineNum">    4237 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_437[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4238"><span class="lineNum">    4238 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1B6)</span></a>
+<a name="4239"><span class="lineNum">    4239 </span><span class="lineNoCov">          0 :         state_vec_438 &lt;=</span></a>
+<a name="4240"><span class="lineNum">    4240 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4241"><span class="lineNum">    4241 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_438[1],</span></a>
+<a name="4242"><span class="lineNum">    4242 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_438[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4243"><span class="lineNum">    4243 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1B7)</span></a>
+<a name="4244"><span class="lineNum">    4244 </span><span class="lineNoCov">          0 :         state_vec_439 &lt;=</span></a>
+<a name="4245"><span class="lineNum">    4245 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4246"><span class="lineNum">    4246 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_439[1],</span></a>
+<a name="4247"><span class="lineNum">    4247 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_439[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4248"><span class="lineNum">    4248 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1B8)</span></a>
+<a name="4249"><span class="lineNum">    4249 </span><span class="lineNoCov">          0 :         state_vec_440 &lt;=</span></a>
+<a name="4250"><span class="lineNum">    4250 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4251"><span class="lineNum">    4251 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_440[1],</span></a>
+<a name="4252"><span class="lineNum">    4252 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_440[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4253"><span class="lineNum">    4253 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1B9)</span></a>
+<a name="4254"><span class="lineNum">    4254 </span><span class="lineNoCov">          0 :         state_vec_441 &lt;=</span></a>
+<a name="4255"><span class="lineNum">    4255 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4256"><span class="lineNum">    4256 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_441[1],</span></a>
+<a name="4257"><span class="lineNum">    4257 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_441[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4258"><span class="lineNum">    4258 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1BA)</span></a>
+<a name="4259"><span class="lineNum">    4259 </span><span class="lineNoCov">          0 :         state_vec_442 &lt;=</span></a>
+<a name="4260"><span class="lineNum">    4260 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4261"><span class="lineNum">    4261 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_442[1],</span></a>
+<a name="4262"><span class="lineNum">    4262 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_442[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4263"><span class="lineNum">    4263 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1BB)</span></a>
+<a name="4264"><span class="lineNum">    4264 </span><span class="lineNoCov">          0 :         state_vec_443 &lt;=</span></a>
+<a name="4265"><span class="lineNum">    4265 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4266"><span class="lineNum">    4266 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_443[1],</span></a>
+<a name="4267"><span class="lineNum">    4267 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_443[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4268"><span class="lineNum">    4268 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1BC)</span></a>
+<a name="4269"><span class="lineNum">    4269 </span><span class="lineNoCov">          0 :         state_vec_444 &lt;=</span></a>
+<a name="4270"><span class="lineNum">    4270 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4271"><span class="lineNum">    4271 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_444[1],</span></a>
+<a name="4272"><span class="lineNum">    4272 </span><span class="lineCov">          2 :            touch_way_0_bits[1] ? state_vec_444[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4273"><span class="lineNum">    4273 </span><span class="lineCov">          1 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1BD)</span></a>
+<a name="4274"><span class="lineNum">    4274 </span><span class="lineCov">          1 :         state_vec_445 &lt;=</span></a>
+<a name="4275"><span class="lineNum">    4275 </span><span class="lineCov">          1 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4276"><span class="lineNum">    4276 </span><span class="lineCov">          1 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_445[1],</span></a>
+<a name="4277"><span class="lineNum">    4277 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_445[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4278"><span class="lineNum">    4278 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1BE)</span></a>
+<a name="4279"><span class="lineNum">    4279 </span><span class="lineNoCov">          0 :         state_vec_446 &lt;=</span></a>
+<a name="4280"><span class="lineNum">    4280 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4281"><span class="lineNum">    4281 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_446[1],</span></a>
+<a name="4282"><span class="lineNum">    4282 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_446[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4283"><span class="lineNum">    4283 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1BF)</span></a>
+<a name="4284"><span class="lineNum">    4284 </span><span class="lineNoCov">          0 :         state_vec_447 &lt;=</span></a>
+<a name="4285"><span class="lineNum">    4285 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4286"><span class="lineNum">    4286 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_447[1],</span></a>
+<a name="4287"><span class="lineNum">    4287 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_447[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4288"><span class="lineNum">    4288 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1C0)</span></a>
+<a name="4289"><span class="lineNum">    4289 </span><span class="lineNoCov">          0 :         state_vec_448 &lt;=</span></a>
+<a name="4290"><span class="lineNum">    4290 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4291"><span class="lineNum">    4291 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_448[1],</span></a>
+<a name="4292"><span class="lineNum">    4292 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_448[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4293"><span class="lineNum">    4293 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1C1)</span></a>
+<a name="4294"><span class="lineNum">    4294 </span><span class="lineNoCov">          0 :         state_vec_449 &lt;=</span></a>
+<a name="4295"><span class="lineNum">    4295 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4296"><span class="lineNum">    4296 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_449[1],</span></a>
+<a name="4297"><span class="lineNum">    4297 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_449[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4298"><span class="lineNum">    4298 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1C2)</span></a>
+<a name="4299"><span class="lineNum">    4299 </span><span class="lineNoCov">          0 :         state_vec_450 &lt;=</span></a>
+<a name="4300"><span class="lineNum">    4300 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4301"><span class="lineNum">    4301 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_450[1],</span></a>
+<a name="4302"><span class="lineNum">    4302 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_450[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4303"><span class="lineNum">    4303 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1C3)</span></a>
+<a name="4304"><span class="lineNum">    4304 </span><span class="lineNoCov">          0 :         state_vec_451 &lt;=</span></a>
+<a name="4305"><span class="lineNum">    4305 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4306"><span class="lineNum">    4306 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_451[1],</span></a>
+<a name="4307"><span class="lineNum">    4307 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_451[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4308"><span class="lineNum">    4308 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1C4)</span></a>
+<a name="4309"><span class="lineNum">    4309 </span><span class="lineNoCov">          0 :         state_vec_452 &lt;=</span></a>
+<a name="4310"><span class="lineNum">    4310 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4311"><span class="lineNum">    4311 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_452[1],</span></a>
+<a name="4312"><span class="lineNum">    4312 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_452[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4313"><span class="lineNum">    4313 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1C5)</span></a>
+<a name="4314"><span class="lineNum">    4314 </span><span class="lineNoCov">          0 :         state_vec_453 &lt;=</span></a>
+<a name="4315"><span class="lineNum">    4315 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4316"><span class="lineNum">    4316 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_453[1],</span></a>
+<a name="4317"><span class="lineNum">    4317 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_453[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4318"><span class="lineNum">    4318 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1C6)</span></a>
+<a name="4319"><span class="lineNum">    4319 </span><span class="lineNoCov">          0 :         state_vec_454 &lt;=</span></a>
+<a name="4320"><span class="lineNum">    4320 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4321"><span class="lineNum">    4321 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_454[1],</span></a>
+<a name="4322"><span class="lineNum">    4322 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_454[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4323"><span class="lineNum">    4323 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1C7)</span></a>
+<a name="4324"><span class="lineNum">    4324 </span><span class="lineNoCov">          0 :         state_vec_455 &lt;=</span></a>
+<a name="4325"><span class="lineNum">    4325 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4326"><span class="lineNum">    4326 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_455[1],</span></a>
+<a name="4327"><span class="lineNum">    4327 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_455[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4328"><span class="lineNum">    4328 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1C8)</span></a>
+<a name="4329"><span class="lineNum">    4329 </span><span class="lineNoCov">          0 :         state_vec_456 &lt;=</span></a>
+<a name="4330"><span class="lineNum">    4330 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4331"><span class="lineNum">    4331 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_456[1],</span></a>
+<a name="4332"><span class="lineNum">    4332 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_456[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4333"><span class="lineNum">    4333 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1C9)</span></a>
+<a name="4334"><span class="lineNum">    4334 </span><span class="lineNoCov">          0 :         state_vec_457 &lt;=</span></a>
+<a name="4335"><span class="lineNum">    4335 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4336"><span class="lineNum">    4336 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_457[1],</span></a>
+<a name="4337"><span class="lineNum">    4337 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_457[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4338"><span class="lineNum">    4338 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1CA)</span></a>
+<a name="4339"><span class="lineNum">    4339 </span><span class="lineNoCov">          0 :         state_vec_458 &lt;=</span></a>
+<a name="4340"><span class="lineNum">    4340 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4341"><span class="lineNum">    4341 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_458[1],</span></a>
+<a name="4342"><span class="lineNum">    4342 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_458[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4343"><span class="lineNum">    4343 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1CB)</span></a>
+<a name="4344"><span class="lineNum">    4344 </span><span class="lineNoCov">          0 :         state_vec_459 &lt;=</span></a>
+<a name="4345"><span class="lineNum">    4345 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4346"><span class="lineNum">    4346 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_459[1],</span></a>
+<a name="4347"><span class="lineNum">    4347 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_459[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4348"><span class="lineNum">    4348 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1CC)</span></a>
+<a name="4349"><span class="lineNum">    4349 </span><span class="lineNoCov">          0 :         state_vec_460 &lt;=</span></a>
+<a name="4350"><span class="lineNum">    4350 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4351"><span class="lineNum">    4351 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_460[1],</span></a>
+<a name="4352"><span class="lineNum">    4352 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_460[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4353"><span class="lineNum">    4353 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1CD)</span></a>
+<a name="4354"><span class="lineNum">    4354 </span><span class="lineNoCov">          0 :         state_vec_461 &lt;=</span></a>
+<a name="4355"><span class="lineNum">    4355 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4356"><span class="lineNum">    4356 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_461[1],</span></a>
+<a name="4357"><span class="lineNum">    4357 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_461[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4358"><span class="lineNum">    4358 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1CE)</span></a>
+<a name="4359"><span class="lineNum">    4359 </span><span class="lineNoCov">          0 :         state_vec_462 &lt;=</span></a>
+<a name="4360"><span class="lineNum">    4360 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4361"><span class="lineNum">    4361 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_462[1],</span></a>
+<a name="4362"><span class="lineNum">    4362 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_462[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4363"><span class="lineNum">    4363 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1CF)</span></a>
+<a name="4364"><span class="lineNum">    4364 </span><span class="lineNoCov">          0 :         state_vec_463 &lt;=</span></a>
+<a name="4365"><span class="lineNum">    4365 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4366"><span class="lineNum">    4366 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_463[1],</span></a>
+<a name="4367"><span class="lineNum">    4367 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_463[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4368"><span class="lineNum">    4368 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1D0)</span></a>
+<a name="4369"><span class="lineNum">    4369 </span><span class="lineNoCov">          0 :         state_vec_464 &lt;=</span></a>
+<a name="4370"><span class="lineNum">    4370 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4371"><span class="lineNum">    4371 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_464[1],</span></a>
+<a name="4372"><span class="lineNum">    4372 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_464[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4373"><span class="lineNum">    4373 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1D1)</span></a>
+<a name="4374"><span class="lineNum">    4374 </span><span class="lineNoCov">          0 :         state_vec_465 &lt;=</span></a>
+<a name="4375"><span class="lineNum">    4375 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4376"><span class="lineNum">    4376 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_465[1],</span></a>
+<a name="4377"><span class="lineNum">    4377 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_465[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4378"><span class="lineNum">    4378 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1D2)</span></a>
+<a name="4379"><span class="lineNum">    4379 </span><span class="lineNoCov">          0 :         state_vec_466 &lt;=</span></a>
+<a name="4380"><span class="lineNum">    4380 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4381"><span class="lineNum">    4381 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_466[1],</span></a>
+<a name="4382"><span class="lineNum">    4382 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_466[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4383"><span class="lineNum">    4383 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1D3)</span></a>
+<a name="4384"><span class="lineNum">    4384 </span><span class="lineNoCov">          0 :         state_vec_467 &lt;=</span></a>
+<a name="4385"><span class="lineNum">    4385 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4386"><span class="lineNum">    4386 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_467[1],</span></a>
+<a name="4387"><span class="lineNum">    4387 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_467[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4388"><span class="lineNum">    4388 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1D4)</span></a>
+<a name="4389"><span class="lineNum">    4389 </span><span class="lineNoCov">          0 :         state_vec_468 &lt;=</span></a>
+<a name="4390"><span class="lineNum">    4390 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4391"><span class="lineNum">    4391 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_468[1],</span></a>
+<a name="4392"><span class="lineNum">    4392 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_468[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4393"><span class="lineNum">    4393 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1D5)</span></a>
+<a name="4394"><span class="lineNum">    4394 </span><span class="lineNoCov">          0 :         state_vec_469 &lt;=</span></a>
+<a name="4395"><span class="lineNum">    4395 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4396"><span class="lineNum">    4396 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_469[1],</span></a>
+<a name="4397"><span class="lineNum">    4397 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_469[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4398"><span class="lineNum">    4398 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1D6)</span></a>
+<a name="4399"><span class="lineNum">    4399 </span><span class="lineNoCov">          0 :         state_vec_470 &lt;=</span></a>
+<a name="4400"><span class="lineNum">    4400 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4401"><span class="lineNum">    4401 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_470[1],</span></a>
+<a name="4402"><span class="lineNum">    4402 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_470[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4403"><span class="lineNum">    4403 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1D7)</span></a>
+<a name="4404"><span class="lineNum">    4404 </span><span class="lineNoCov">          0 :         state_vec_471 &lt;=</span></a>
+<a name="4405"><span class="lineNum">    4405 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4406"><span class="lineNum">    4406 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_471[1],</span></a>
+<a name="4407"><span class="lineNum">    4407 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_471[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4408"><span class="lineNum">    4408 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1D8)</span></a>
+<a name="4409"><span class="lineNum">    4409 </span><span class="lineNoCov">          0 :         state_vec_472 &lt;=</span></a>
+<a name="4410"><span class="lineNum">    4410 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4411"><span class="lineNum">    4411 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_472[1],</span></a>
+<a name="4412"><span class="lineNum">    4412 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_472[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4413"><span class="lineNum">    4413 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1D9)</span></a>
+<a name="4414"><span class="lineNum">    4414 </span><span class="lineNoCov">          0 :         state_vec_473 &lt;=</span></a>
+<a name="4415"><span class="lineNum">    4415 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4416"><span class="lineNum">    4416 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_473[1],</span></a>
+<a name="4417"><span class="lineNum">    4417 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_473[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4418"><span class="lineNum">    4418 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1DA)</span></a>
+<a name="4419"><span class="lineNum">    4419 </span><span class="lineNoCov">          0 :         state_vec_474 &lt;=</span></a>
+<a name="4420"><span class="lineNum">    4420 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4421"><span class="lineNum">    4421 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_474[1],</span></a>
+<a name="4422"><span class="lineNum">    4422 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_474[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4423"><span class="lineNum">    4423 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1DB)</span></a>
+<a name="4424"><span class="lineNum">    4424 </span><span class="lineNoCov">          0 :         state_vec_475 &lt;=</span></a>
+<a name="4425"><span class="lineNum">    4425 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4426"><span class="lineNum">    4426 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_475[1],</span></a>
+<a name="4427"><span class="lineNum">    4427 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_475[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4428"><span class="lineNum">    4428 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1DC)</span></a>
+<a name="4429"><span class="lineNum">    4429 </span><span class="lineNoCov">          0 :         state_vec_476 &lt;=</span></a>
+<a name="4430"><span class="lineNum">    4430 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4431"><span class="lineNum">    4431 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_476[1],</span></a>
+<a name="4432"><span class="lineNum">    4432 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_476[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4433"><span class="lineNum">    4433 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1DD)</span></a>
+<a name="4434"><span class="lineNum">    4434 </span><span class="lineNoCov">          0 :         state_vec_477 &lt;=</span></a>
+<a name="4435"><span class="lineNum">    4435 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4436"><span class="lineNum">    4436 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_477[1],</span></a>
+<a name="4437"><span class="lineNum">    4437 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_477[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4438"><span class="lineNum">    4438 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1DE)</span></a>
+<a name="4439"><span class="lineNum">    4439 </span><span class="lineNoCov">          0 :         state_vec_478 &lt;=</span></a>
+<a name="4440"><span class="lineNum">    4440 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4441"><span class="lineNum">    4441 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_478[1],</span></a>
+<a name="4442"><span class="lineNum">    4442 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_478[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4443"><span class="lineNum">    4443 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1DF)</span></a>
+<a name="4444"><span class="lineNum">    4444 </span><span class="lineNoCov">          0 :         state_vec_479 &lt;=</span></a>
+<a name="4445"><span class="lineNum">    4445 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4446"><span class="lineNum">    4446 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_479[1],</span></a>
+<a name="4447"><span class="lineNum">    4447 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_479[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4448"><span class="lineNum">    4448 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1E0)</span></a>
+<a name="4449"><span class="lineNum">    4449 </span><span class="lineNoCov">          0 :         state_vec_480 &lt;=</span></a>
+<a name="4450"><span class="lineNum">    4450 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4451"><span class="lineNum">    4451 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_480[1],</span></a>
+<a name="4452"><span class="lineNum">    4452 </span><span class="lineCov">          2 :            touch_way_0_bits[1] ? state_vec_480[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4453"><span class="lineNum">    4453 </span><span class="lineCov">          1 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1E1)</span></a>
+<a name="4454"><span class="lineNum">    4454 </span><span class="lineCov">          1 :         state_vec_481 &lt;=</span></a>
+<a name="4455"><span class="lineNum">    4455 </span><span class="lineCov">          1 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4456"><span class="lineNum">    4456 </span><span class="lineCov">          1 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_481[1],</span></a>
+<a name="4457"><span class="lineNum">    4457 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_481[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4458"><span class="lineNum">    4458 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1E2)</span></a>
+<a name="4459"><span class="lineNum">    4459 </span><span class="lineNoCov">          0 :         state_vec_482 &lt;=</span></a>
+<a name="4460"><span class="lineNum">    4460 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4461"><span class="lineNum">    4461 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_482[1],</span></a>
+<a name="4462"><span class="lineNum">    4462 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_482[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4463"><span class="lineNum">    4463 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1E3)</span></a>
+<a name="4464"><span class="lineNum">    4464 </span><span class="lineNoCov">          0 :         state_vec_483 &lt;=</span></a>
+<a name="4465"><span class="lineNum">    4465 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4466"><span class="lineNum">    4466 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_483[1],</span></a>
+<a name="4467"><span class="lineNum">    4467 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_483[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4468"><span class="lineNum">    4468 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1E4)</span></a>
+<a name="4469"><span class="lineNum">    4469 </span><span class="lineNoCov">          0 :         state_vec_484 &lt;=</span></a>
+<a name="4470"><span class="lineNum">    4470 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4471"><span class="lineNum">    4471 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_484[1],</span></a>
+<a name="4472"><span class="lineNum">    4472 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_484[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4473"><span class="lineNum">    4473 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1E5)</span></a>
+<a name="4474"><span class="lineNum">    4474 </span><span class="lineNoCov">          0 :         state_vec_485 &lt;=</span></a>
+<a name="4475"><span class="lineNum">    4475 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4476"><span class="lineNum">    4476 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_485[1],</span></a>
+<a name="4477"><span class="lineNum">    4477 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_485[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4478"><span class="lineNum">    4478 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1E6)</span></a>
+<a name="4479"><span class="lineNum">    4479 </span><span class="lineNoCov">          0 :         state_vec_486 &lt;=</span></a>
+<a name="4480"><span class="lineNum">    4480 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4481"><span class="lineNum">    4481 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_486[1],</span></a>
+<a name="4482"><span class="lineNum">    4482 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_486[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4483"><span class="lineNum">    4483 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1E7)</span></a>
+<a name="4484"><span class="lineNum">    4484 </span><span class="lineNoCov">          0 :         state_vec_487 &lt;=</span></a>
+<a name="4485"><span class="lineNum">    4485 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4486"><span class="lineNum">    4486 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_487[1],</span></a>
+<a name="4487"><span class="lineNum">    4487 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_487[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4488"><span class="lineNum">    4488 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1E8)</span></a>
+<a name="4489"><span class="lineNum">    4489 </span><span class="lineNoCov">          0 :         state_vec_488 &lt;=</span></a>
+<a name="4490"><span class="lineNum">    4490 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4491"><span class="lineNum">    4491 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_488[1],</span></a>
+<a name="4492"><span class="lineNum">    4492 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_488[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4493"><span class="lineNum">    4493 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1E9)</span></a>
+<a name="4494"><span class="lineNum">    4494 </span><span class="lineNoCov">          0 :         state_vec_489 &lt;=</span></a>
+<a name="4495"><span class="lineNum">    4495 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4496"><span class="lineNum">    4496 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_489[1],</span></a>
+<a name="4497"><span class="lineNum">    4497 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_489[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4498"><span class="lineNum">    4498 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1EA)</span></a>
+<a name="4499"><span class="lineNum">    4499 </span><span class="lineNoCov">          0 :         state_vec_490 &lt;=</span></a>
+<a name="4500"><span class="lineNum">    4500 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4501"><span class="lineNum">    4501 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_490[1],</span></a>
+<a name="4502"><span class="lineNum">    4502 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_490[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4503"><span class="lineNum">    4503 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1EB)</span></a>
+<a name="4504"><span class="lineNum">    4504 </span><span class="lineNoCov">          0 :         state_vec_491 &lt;=</span></a>
+<a name="4505"><span class="lineNum">    4505 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4506"><span class="lineNum">    4506 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_491[1],</span></a>
+<a name="4507"><span class="lineNum">    4507 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_491[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4508"><span class="lineNum">    4508 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1EC)</span></a>
+<a name="4509"><span class="lineNum">    4509 </span><span class="lineNoCov">          0 :         state_vec_492 &lt;=</span></a>
+<a name="4510"><span class="lineNum">    4510 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4511"><span class="lineNum">    4511 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_492[1],</span></a>
+<a name="4512"><span class="lineNum">    4512 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_492[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4513"><span class="lineNum">    4513 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1ED)</span></a>
+<a name="4514"><span class="lineNum">    4514 </span><span class="lineNoCov">          0 :         state_vec_493 &lt;=</span></a>
+<a name="4515"><span class="lineNum">    4515 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4516"><span class="lineNum">    4516 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_493[1],</span></a>
+<a name="4517"><span class="lineNum">    4517 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_493[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4518"><span class="lineNum">    4518 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1EE)</span></a>
+<a name="4519"><span class="lineNum">    4519 </span><span class="lineNoCov">          0 :         state_vec_494 &lt;=</span></a>
+<a name="4520"><span class="lineNum">    4520 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4521"><span class="lineNum">    4521 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_494[1],</span></a>
+<a name="4522"><span class="lineNum">    4522 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_494[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4523"><span class="lineNum">    4523 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1EF)</span></a>
+<a name="4524"><span class="lineNum">    4524 </span><span class="lineNoCov">          0 :         state_vec_495 &lt;=</span></a>
+<a name="4525"><span class="lineNum">    4525 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4526"><span class="lineNum">    4526 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_495[1],</span></a>
+<a name="4527"><span class="lineNum">    4527 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_495[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4528"><span class="lineNum">    4528 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1F0)</span></a>
+<a name="4529"><span class="lineNum">    4529 </span><span class="lineNoCov">          0 :         state_vec_496 &lt;=</span></a>
+<a name="4530"><span class="lineNum">    4530 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4531"><span class="lineNum">    4531 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_496[1],</span></a>
+<a name="4532"><span class="lineNum">    4532 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_496[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4533"><span class="lineNum">    4533 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1F1)</span></a>
+<a name="4534"><span class="lineNum">    4534 </span><span class="lineNoCov">          0 :         state_vec_497 &lt;=</span></a>
+<a name="4535"><span class="lineNum">    4535 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4536"><span class="lineNum">    4536 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_497[1],</span></a>
+<a name="4537"><span class="lineNum">    4537 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_497[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4538"><span class="lineNum">    4538 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1F2)</span></a>
+<a name="4539"><span class="lineNum">    4539 </span><span class="lineNoCov">          0 :         state_vec_498 &lt;=</span></a>
+<a name="4540"><span class="lineNum">    4540 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4541"><span class="lineNum">    4541 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_498[1],</span></a>
+<a name="4542"><span class="lineNum">    4542 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_498[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4543"><span class="lineNum">    4543 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1F3)</span></a>
+<a name="4544"><span class="lineNum">    4544 </span><span class="lineNoCov">          0 :         state_vec_499 &lt;=</span></a>
+<a name="4545"><span class="lineNum">    4545 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4546"><span class="lineNum">    4546 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_499[1],</span></a>
+<a name="4547"><span class="lineNum">    4547 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_499[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4548"><span class="lineNum">    4548 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1F4)</span></a>
+<a name="4549"><span class="lineNum">    4549 </span><span class="lineNoCov">          0 :         state_vec_500 &lt;=</span></a>
+<a name="4550"><span class="lineNum">    4550 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4551"><span class="lineNum">    4551 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_500[1],</span></a>
+<a name="4552"><span class="lineNum">    4552 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_500[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4553"><span class="lineNum">    4553 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1F5)</span></a>
+<a name="4554"><span class="lineNum">    4554 </span><span class="lineNoCov">          0 :         state_vec_501 &lt;=</span></a>
+<a name="4555"><span class="lineNum">    4555 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4556"><span class="lineNum">    4556 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_501[1],</span></a>
+<a name="4557"><span class="lineNum">    4557 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_501[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4558"><span class="lineNum">    4558 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1F6)</span></a>
+<a name="4559"><span class="lineNum">    4559 </span><span class="lineNoCov">          0 :         state_vec_502 &lt;=</span></a>
+<a name="4560"><span class="lineNum">    4560 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4561"><span class="lineNum">    4561 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_502[1],</span></a>
+<a name="4562"><span class="lineNum">    4562 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_502[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4563"><span class="lineNum">    4563 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1F7)</span></a>
+<a name="4564"><span class="lineNum">    4564 </span><span class="lineNoCov">          0 :         state_vec_503 &lt;=</span></a>
+<a name="4565"><span class="lineNum">    4565 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4566"><span class="lineNum">    4566 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_503[1],</span></a>
+<a name="4567"><span class="lineNum">    4567 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_503[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4568"><span class="lineNum">    4568 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1F8)</span></a>
+<a name="4569"><span class="lineNum">    4569 </span><span class="lineNoCov">          0 :         state_vec_504 &lt;=</span></a>
+<a name="4570"><span class="lineNum">    4570 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4571"><span class="lineNum">    4571 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_504[1],</span></a>
+<a name="4572"><span class="lineNum">    4572 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_504[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4573"><span class="lineNum">    4573 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1F9)</span></a>
+<a name="4574"><span class="lineNum">    4574 </span><span class="lineNoCov">          0 :         state_vec_505 &lt;=</span></a>
+<a name="4575"><span class="lineNum">    4575 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4576"><span class="lineNum">    4576 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_505[1],</span></a>
+<a name="4577"><span class="lineNum">    4577 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_505[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4578"><span class="lineNum">    4578 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1FA)</span></a>
+<a name="4579"><span class="lineNum">    4579 </span><span class="lineNoCov">          0 :         state_vec_506 &lt;=</span></a>
+<a name="4580"><span class="lineNum">    4580 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4581"><span class="lineNum">    4581 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_506[1],</span></a>
+<a name="4582"><span class="lineNum">    4582 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_506[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4583"><span class="lineNum">    4583 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1FB)</span></a>
+<a name="4584"><span class="lineNum">    4584 </span><span class="lineNoCov">          0 :         state_vec_507 &lt;=</span></a>
+<a name="4585"><span class="lineNum">    4585 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4586"><span class="lineNum">    4586 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_507[1],</span></a>
+<a name="4587"><span class="lineNum">    4587 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_507[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4588"><span class="lineNum">    4588 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1FC)</span></a>
+<a name="4589"><span class="lineNum">    4589 </span><span class="lineNoCov">          0 :         state_vec_508 &lt;=</span></a>
+<a name="4590"><span class="lineNum">    4590 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4591"><span class="lineNum">    4591 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_508[1],</span></a>
+<a name="4592"><span class="lineNum">    4592 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_508[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4593"><span class="lineNum">    4593 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1FD)</span></a>
+<a name="4594"><span class="lineNum">    4594 </span><span class="lineNoCov">          0 :         state_vec_509 &lt;=</span></a>
+<a name="4595"><span class="lineNum">    4595 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4596"><span class="lineNum">    4596 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_509[1],</span></a>
+<a name="4597"><span class="lineNum">    4597 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_509[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4598"><span class="lineNum">    4598 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; touch_set_0 == 9'h1FE)</span></a>
+<a name="4599"><span class="lineNum">    4599 </span><span class="lineNoCov">          0 :         state_vec_510 &lt;=</span></a>
+<a name="4600"><span class="lineNum">    4600 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4601"><span class="lineNum">    4601 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_510[1],</span></a>
+<a name="4602"><span class="lineNum">    4602 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? state_vec_510[0] : ~(touch_way_0_bits[0])};</span></a>
+<a name="4603"><span class="lineNum">    4603 </span><span class="lineNoCov">          0 :       if (touch_way_0_valid &amp; (&amp;touch_set_0))</span></a>
+<a name="4604"><span class="lineNum">    4604 </span><span class="lineNoCov">          0 :         state_vec_511 &lt;=</span></a>
+<a name="4605"><span class="lineNum">    4605 </span><span class="lineNoCov">          0 :           {~(touch_way_0_bits[1]),</span></a>
+<a name="4606"><span class="lineNum">    4606 </span><span class="lineNoCov">          0 :            touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_511[1],</span></a>
+<a name="4607"><span class="lineNum">    4607 </span>            :            touch_way_0_bits[1] ? state_vec_511[0] : ~(touch_way_0_bits[0])};</a>
+<a name="4608"><span class="lineNum">    4608 </span>            :     end</a>
+<a name="4609"><span class="lineNum">    4609 </span>            :   end // always @(posedge, posedge)</a>
+<a name="4610"><span class="lineNum">    4610 </span>            :   `ifdef ENABLE_INITIAL_REG_</a>
+<a name="4611"><span class="lineNum">    4611 </span>            :     `ifdef FIRRTL_BEFORE_INITIAL</a>
+<a name="4612"><span class="lineNum">    4612 </span>            :       `FIRRTL_BEFORE_INITIAL</a>
+<a name="4613"><span class="lineNum">    4613 </span>            :     `endif // FIRRTL_BEFORE_INITIAL</a>
+<a name="4614"><span class="lineNum">    4614 </span><span class="lineCov">         58 :     logic [31:0] _RANDOM[0:60];</span></a>
+<a name="4615"><span class="lineNum">    4615 </span>            :     initial begin</a>
+<a name="4616"><span class="lineNum">    4616 </span>            :       `ifdef INIT_RANDOM_PROLOG_</a>
+<a name="4617"><span class="lineNum">    4617 </span>            :         `INIT_RANDOM_PROLOG_</a>
+<a name="4618"><span class="lineNum">    4618 </span>            :       `endif // INIT_RANDOM_PROLOG_</a>
+<a name="4619"><span class="lineNum">    4619 </span>            :       `ifdef RANDOMIZE_REG_INIT</a>
+<a name="4620"><span class="lineNum">    4620 </span>            :         for (logic [5:0] i = 6'h0; i &lt; 6'h3D; i += 6'h1) begin</a>
+<a name="4621"><span class="lineNum">    4621 </span>            :           _RANDOM[i] = `RANDOM;</a>
+<a name="4622"><span class="lineNum">    4622 </span>            :         end</a>
+<a name="4623"><span class="lineNum">    4623 </span>            :         pred_rdata_REG = _RANDOM[6'h0][0];</a>
+<a name="4624"><span class="lineNum">    4624 </span>            :         pred_rdata_hold_data_0_entry_valid = _RANDOM[6'h0][1];</a>
+<a name="4625"><span class="lineNum">    4625 </span>            :         pred_rdata_hold_data_0_entry_brSlots_0_offset = _RANDOM[6'h0][5:2];</a>
+<a name="4626"><span class="lineNum">    4626 </span>            :         pred_rdata_hold_data_0_entry_brSlots_0_lower = _RANDOM[6'h0][17:6];</a>
+<a name="4627"><span class="lineNum">    4627 </span>            :         pred_rdata_hold_data_0_entry_brSlots_0_tarStat = _RANDOM[6'h0][19:18];</a>
+<a name="4628"><span class="lineNum">    4628 </span>            :         pred_rdata_hold_data_0_entry_brSlots_0_sharing = _RANDOM[6'h0][20];</a>
+<a name="4629"><span class="lineNum">    4629 </span>            :         pred_rdata_hold_data_0_entry_brSlots_0_valid = _RANDOM[6'h0][21];</a>
+<a name="4630"><span class="lineNum">    4630 </span>            :         pred_rdata_hold_data_0_entry_tailSlot_offset = _RANDOM[6'h0][25:22];</a>
+<a name="4631"><span class="lineNum">    4631 </span>            :         pred_rdata_hold_data_0_entry_tailSlot_lower =</a>
+<a name="4632"><span class="lineNum">    4632 </span>            :           {_RANDOM[6'h0][31:26], _RANDOM[6'h1][13:0]};</a>
+<a name="4633"><span class="lineNum">    4633 </span>            :         pred_rdata_hold_data_0_entry_tailSlot_tarStat = _RANDOM[6'h1][15:14];</a>
+<a name="4634"><span class="lineNum">    4634 </span>            :         pred_rdata_hold_data_0_entry_tailSlot_sharing = _RANDOM[6'h1][16];</a>
+<a name="4635"><span class="lineNum">    4635 </span>            :         pred_rdata_hold_data_0_entry_tailSlot_valid = _RANDOM[6'h1][17];</a>
+<a name="4636"><span class="lineNum">    4636 </span>            :         pred_rdata_hold_data_0_entry_pftAddr = _RANDOM[6'h1][21:18];</a>
+<a name="4637"><span class="lineNum">    4637 </span>            :         pred_rdata_hold_data_0_entry_carry = _RANDOM[6'h1][22];</a>
+<a name="4638"><span class="lineNum">    4638 </span>            :         pred_rdata_hold_data_0_entry_isCall = _RANDOM[6'h1][23];</a>
+<a name="4639"><span class="lineNum">    4639 </span>            :         pred_rdata_hold_data_0_entry_isRet = _RANDOM[6'h1][24];</a>
+<a name="4640"><span class="lineNum">    4640 </span>            :         pred_rdata_hold_data_0_entry_isJalr = _RANDOM[6'h1][25];</a>
+<a name="4641"><span class="lineNum">    4641 </span>            :         pred_rdata_hold_data_0_entry_last_may_be_rvi_call = _RANDOM[6'h1][26];</a>
+<a name="4642"><span class="lineNum">    4642 </span>            :         pred_rdata_hold_data_0_entry_always_taken_0 = _RANDOM[6'h1][27];</a>
+<a name="4643"><span class="lineNum">    4643 </span>            :         pred_rdata_hold_data_0_entry_always_taken_1 = _RANDOM[6'h1][28];</a>
+<a name="4644"><span class="lineNum">    4644 </span>            :         pred_rdata_hold_data_0_tag = {_RANDOM[6'h1][31:29], _RANDOM[6'h2][16:0]};</a>
+<a name="4645"><span class="lineNum">    4645 </span>            :         pred_rdata_hold_data_1_entry_valid = _RANDOM[6'h2][17];</a>
+<a name="4646"><span class="lineNum">    4646 </span>            :         pred_rdata_hold_data_1_entry_brSlots_0_offset = _RANDOM[6'h2][21:18];</a>
+<a name="4647"><span class="lineNum">    4647 </span>            :         pred_rdata_hold_data_1_entry_brSlots_0_lower =</a>
+<a name="4648"><span class="lineNum">    4648 </span>            :           {_RANDOM[6'h2][31:22], _RANDOM[6'h3][1:0]};</a>
+<a name="4649"><span class="lineNum">    4649 </span>            :         pred_rdata_hold_data_1_entry_brSlots_0_tarStat = _RANDOM[6'h3][3:2];</a>
+<a name="4650"><span class="lineNum">    4650 </span>            :         pred_rdata_hold_data_1_entry_brSlots_0_sharing = _RANDOM[6'h3][4];</a>
+<a name="4651"><span class="lineNum">    4651 </span>            :         pred_rdata_hold_data_1_entry_brSlots_0_valid = _RANDOM[6'h3][5];</a>
+<a name="4652"><span class="lineNum">    4652 </span>            :         pred_rdata_hold_data_1_entry_tailSlot_offset = _RANDOM[6'h3][9:6];</a>
+<a name="4653"><span class="lineNum">    4653 </span>            :         pred_rdata_hold_data_1_entry_tailSlot_lower = _RANDOM[6'h3][29:10];</a>
+<a name="4654"><span class="lineNum">    4654 </span>            :         pred_rdata_hold_data_1_entry_tailSlot_tarStat = _RANDOM[6'h3][31:30];</a>
+<a name="4655"><span class="lineNum">    4655 </span>            :         pred_rdata_hold_data_1_entry_tailSlot_sharing = _RANDOM[6'h4][0];</a>
+<a name="4656"><span class="lineNum">    4656 </span>            :         pred_rdata_hold_data_1_entry_tailSlot_valid = _RANDOM[6'h4][1];</a>
+<a name="4657"><span class="lineNum">    4657 </span>            :         pred_rdata_hold_data_1_entry_pftAddr = _RANDOM[6'h4][5:2];</a>
+<a name="4658"><span class="lineNum">    4658 </span>            :         pred_rdata_hold_data_1_entry_carry = _RANDOM[6'h4][6];</a>
+<a name="4659"><span class="lineNum">    4659 </span>            :         pred_rdata_hold_data_1_entry_isCall = _RANDOM[6'h4][7];</a>
+<a name="4660"><span class="lineNum">    4660 </span>            :         pred_rdata_hold_data_1_entry_isRet = _RANDOM[6'h4][8];</a>
+<a name="4661"><span class="lineNum">    4661 </span>            :         pred_rdata_hold_data_1_entry_isJalr = _RANDOM[6'h4][9];</a>
+<a name="4662"><span class="lineNum">    4662 </span>            :         pred_rdata_hold_data_1_entry_last_may_be_rvi_call = _RANDOM[6'h4][10];</a>
+<a name="4663"><span class="lineNum">    4663 </span>            :         pred_rdata_hold_data_1_entry_always_taken_0 = _RANDOM[6'h4][11];</a>
+<a name="4664"><span class="lineNum">    4664 </span>            :         pred_rdata_hold_data_1_entry_always_taken_1 = _RANDOM[6'h4][12];</a>
+<a name="4665"><span class="lineNum">    4665 </span>            :         pred_rdata_hold_data_1_tag = {_RANDOM[6'h4][31:13], _RANDOM[6'h5][0]};</a>
+<a name="4666"><span class="lineNum">    4666 </span>            :         pred_rdata_hold_data_2_entry_valid = _RANDOM[6'h5][1];</a>
+<a name="4667"><span class="lineNum">    4667 </span>            :         pred_rdata_hold_data_2_entry_brSlots_0_offset = _RANDOM[6'h5][5:2];</a>
+<a name="4668"><span class="lineNum">    4668 </span>            :         pred_rdata_hold_data_2_entry_brSlots_0_lower = _RANDOM[6'h5][17:6];</a>
+<a name="4669"><span class="lineNum">    4669 </span>            :         pred_rdata_hold_data_2_entry_brSlots_0_tarStat = _RANDOM[6'h5][19:18];</a>
+<a name="4670"><span class="lineNum">    4670 </span>            :         pred_rdata_hold_data_2_entry_brSlots_0_sharing = _RANDOM[6'h5][20];</a>
+<a name="4671"><span class="lineNum">    4671 </span>            :         pred_rdata_hold_data_2_entry_brSlots_0_valid = _RANDOM[6'h5][21];</a>
+<a name="4672"><span class="lineNum">    4672 </span>            :         pred_rdata_hold_data_2_entry_tailSlot_offset = _RANDOM[6'h5][25:22];</a>
+<a name="4673"><span class="lineNum">    4673 </span>            :         pred_rdata_hold_data_2_entry_tailSlot_lower =</a>
+<a name="4674"><span class="lineNum">    4674 </span>            :           {_RANDOM[6'h5][31:26], _RANDOM[6'h6][13:0]};</a>
+<a name="4675"><span class="lineNum">    4675 </span>            :         pred_rdata_hold_data_2_entry_tailSlot_tarStat = _RANDOM[6'h6][15:14];</a>
+<a name="4676"><span class="lineNum">    4676 </span>            :         pred_rdata_hold_data_2_entry_tailSlot_sharing = _RANDOM[6'h6][16];</a>
+<a name="4677"><span class="lineNum">    4677 </span>            :         pred_rdata_hold_data_2_entry_tailSlot_valid = _RANDOM[6'h6][17];</a>
+<a name="4678"><span class="lineNum">    4678 </span>            :         pred_rdata_hold_data_2_entry_pftAddr = _RANDOM[6'h6][21:18];</a>
+<a name="4679"><span class="lineNum">    4679 </span>            :         pred_rdata_hold_data_2_entry_carry = _RANDOM[6'h6][22];</a>
+<a name="4680"><span class="lineNum">    4680 </span>            :         pred_rdata_hold_data_2_entry_isCall = _RANDOM[6'h6][23];</a>
+<a name="4681"><span class="lineNum">    4681 </span>            :         pred_rdata_hold_data_2_entry_isRet = _RANDOM[6'h6][24];</a>
+<a name="4682"><span class="lineNum">    4682 </span>            :         pred_rdata_hold_data_2_entry_isJalr = _RANDOM[6'h6][25];</a>
+<a name="4683"><span class="lineNum">    4683 </span>            :         pred_rdata_hold_data_2_entry_last_may_be_rvi_call = _RANDOM[6'h6][26];</a>
+<a name="4684"><span class="lineNum">    4684 </span>            :         pred_rdata_hold_data_2_entry_always_taken_0 = _RANDOM[6'h6][27];</a>
+<a name="4685"><span class="lineNum">    4685 </span>            :         pred_rdata_hold_data_2_entry_always_taken_1 = _RANDOM[6'h6][28];</a>
+<a name="4686"><span class="lineNum">    4686 </span>            :         pred_rdata_hold_data_2_tag = {_RANDOM[6'h6][31:29], _RANDOM[6'h7][16:0]};</a>
+<a name="4687"><span class="lineNum">    4687 </span>            :         pred_rdata_hold_data_3_entry_valid = _RANDOM[6'h7][17];</a>
+<a name="4688"><span class="lineNum">    4688 </span>            :         pred_rdata_hold_data_3_entry_brSlots_0_offset = _RANDOM[6'h7][21:18];</a>
+<a name="4689"><span class="lineNum">    4689 </span>            :         pred_rdata_hold_data_3_entry_brSlots_0_lower =</a>
+<a name="4690"><span class="lineNum">    4690 </span>            :           {_RANDOM[6'h7][31:22], _RANDOM[6'h8][1:0]};</a>
+<a name="4691"><span class="lineNum">    4691 </span>            :         pred_rdata_hold_data_3_entry_brSlots_0_tarStat = _RANDOM[6'h8][3:2];</a>
+<a name="4692"><span class="lineNum">    4692 </span>            :         pred_rdata_hold_data_3_entry_brSlots_0_sharing = _RANDOM[6'h8][4];</a>
+<a name="4693"><span class="lineNum">    4693 </span>            :         pred_rdata_hold_data_3_entry_brSlots_0_valid = _RANDOM[6'h8][5];</a>
+<a name="4694"><span class="lineNum">    4694 </span>            :         pred_rdata_hold_data_3_entry_tailSlot_offset = _RANDOM[6'h8][9:6];</a>
+<a name="4695"><span class="lineNum">    4695 </span>            :         pred_rdata_hold_data_3_entry_tailSlot_lower = _RANDOM[6'h8][29:10];</a>
+<a name="4696"><span class="lineNum">    4696 </span>            :         pred_rdata_hold_data_3_entry_tailSlot_tarStat = _RANDOM[6'h8][31:30];</a>
+<a name="4697"><span class="lineNum">    4697 </span>            :         pred_rdata_hold_data_3_entry_tailSlot_sharing = _RANDOM[6'h9][0];</a>
+<a name="4698"><span class="lineNum">    4698 </span>            :         pred_rdata_hold_data_3_entry_tailSlot_valid = _RANDOM[6'h9][1];</a>
+<a name="4699"><span class="lineNum">    4699 </span>            :         pred_rdata_hold_data_3_entry_pftAddr = _RANDOM[6'h9][5:2];</a>
+<a name="4700"><span class="lineNum">    4700 </span>            :         pred_rdata_hold_data_3_entry_carry = _RANDOM[6'h9][6];</a>
+<a name="4701"><span class="lineNum">    4701 </span>            :         pred_rdata_hold_data_3_entry_isCall = _RANDOM[6'h9][7];</a>
+<a name="4702"><span class="lineNum">    4702 </span>            :         pred_rdata_hold_data_3_entry_isRet = _RANDOM[6'h9][8];</a>
+<a name="4703"><span class="lineNum">    4703 </span>            :         pred_rdata_hold_data_3_entry_isJalr = _RANDOM[6'h9][9];</a>
+<a name="4704"><span class="lineNum">    4704 </span>            :         pred_rdata_hold_data_3_entry_last_may_be_rvi_call = _RANDOM[6'h9][10];</a>
+<a name="4705"><span class="lineNum">    4705 </span>            :         pred_rdata_hold_data_3_entry_always_taken_0 = _RANDOM[6'h9][11];</a>
+<a name="4706"><span class="lineNum">    4706 </span>            :         pred_rdata_hold_data_3_entry_always_taken_1 = _RANDOM[6'h9][12];</a>
+<a name="4707"><span class="lineNum">    4707 </span>            :         pred_rdata_hold_data_3_tag = {_RANDOM[6'h9][31:13], _RANDOM[6'hA][0]};</a>
+<a name="4708"><span class="lineNum">    4708 </span>            :         req_tag = _RANDOM[6'hA][20:1];</a>
+<a name="4709"><span class="lineNum">    4709 </span>            :         req_idx = _RANDOM[6'hA][29:21];</a>
+<a name="4710"><span class="lineNum">    4710 </span>            :         u_req_tag = {_RANDOM[6'hA][31:30], _RANDOM[6'hB][17:0]};</a>
+<a name="4711"><span class="lineNum">    4711 </span>            :         u_total_hits_REG = _RANDOM[6'hB][18];</a>
+<a name="4712"><span class="lineNum">    4712 </span>            :         u_total_hits_REG_1 = _RANDOM[6'hB][19];</a>
+<a name="4713"><span class="lineNum">    4713 </span>            :         u_total_hits_REG_2 = _RANDOM[6'hB][20];</a>
+<a name="4714"><span class="lineNum">    4714 </span>            :         u_total_hits_REG_3 = _RANDOM[6'hB][21];</a>
+<a name="4715"><span class="lineNum">    4715 </span>            :         state_vec_0 = _RANDOM[6'hB][27:25];</a>
+<a name="4716"><span class="lineNum">    4716 </span>            :         state_vec_1 = _RANDOM[6'hB][30:28];</a>
+<a name="4717"><span class="lineNum">    4717 </span>            :         state_vec_2 = {_RANDOM[6'hB][31], _RANDOM[6'hC][1:0]};</a>
+<a name="4718"><span class="lineNum">    4718 </span>            :         state_vec_3 = _RANDOM[6'hC][4:2];</a>
+<a name="4719"><span class="lineNum">    4719 </span>            :         state_vec_4 = _RANDOM[6'hC][7:5];</a>
+<a name="4720"><span class="lineNum">    4720 </span>            :         state_vec_5 = _RANDOM[6'hC][10:8];</a>
+<a name="4721"><span class="lineNum">    4721 </span>            :         state_vec_6 = _RANDOM[6'hC][13:11];</a>
+<a name="4722"><span class="lineNum">    4722 </span>            :         state_vec_7 = _RANDOM[6'hC][16:14];</a>
+<a name="4723"><span class="lineNum">    4723 </span>            :         state_vec_8 = _RANDOM[6'hC][19:17];</a>
+<a name="4724"><span class="lineNum">    4724 </span>            :         state_vec_9 = _RANDOM[6'hC][22:20];</a>
+<a name="4725"><span class="lineNum">    4725 </span>            :         state_vec_10 = _RANDOM[6'hC][25:23];</a>
+<a name="4726"><span class="lineNum">    4726 </span>            :         state_vec_11 = _RANDOM[6'hC][28:26];</a>
+<a name="4727"><span class="lineNum">    4727 </span>            :         state_vec_12 = _RANDOM[6'hC][31:29];</a>
+<a name="4728"><span class="lineNum">    4728 </span>            :         state_vec_13 = _RANDOM[6'hD][2:0];</a>
+<a name="4729"><span class="lineNum">    4729 </span>            :         state_vec_14 = _RANDOM[6'hD][5:3];</a>
+<a name="4730"><span class="lineNum">    4730 </span>            :         state_vec_15 = _RANDOM[6'hD][8:6];</a>
+<a name="4731"><span class="lineNum">    4731 </span>            :         state_vec_16 = _RANDOM[6'hD][11:9];</a>
+<a name="4732"><span class="lineNum">    4732 </span>            :         state_vec_17 = _RANDOM[6'hD][14:12];</a>
+<a name="4733"><span class="lineNum">    4733 </span>            :         state_vec_18 = _RANDOM[6'hD][17:15];</a>
+<a name="4734"><span class="lineNum">    4734 </span>            :         state_vec_19 = _RANDOM[6'hD][20:18];</a>
+<a name="4735"><span class="lineNum">    4735 </span>            :         state_vec_20 = _RANDOM[6'hD][23:21];</a>
+<a name="4736"><span class="lineNum">    4736 </span>            :         state_vec_21 = _RANDOM[6'hD][26:24];</a>
+<a name="4737"><span class="lineNum">    4737 </span>            :         state_vec_22 = _RANDOM[6'hD][29:27];</a>
+<a name="4738"><span class="lineNum">    4738 </span>            :         state_vec_23 = {_RANDOM[6'hD][31:30], _RANDOM[6'hE][0]};</a>
+<a name="4739"><span class="lineNum">    4739 </span>            :         state_vec_24 = _RANDOM[6'hE][3:1];</a>
+<a name="4740"><span class="lineNum">    4740 </span>            :         state_vec_25 = _RANDOM[6'hE][6:4];</a>
+<a name="4741"><span class="lineNum">    4741 </span>            :         state_vec_26 = _RANDOM[6'hE][9:7];</a>
+<a name="4742"><span class="lineNum">    4742 </span>            :         state_vec_27 = _RANDOM[6'hE][12:10];</a>
+<a name="4743"><span class="lineNum">    4743 </span>            :         state_vec_28 = _RANDOM[6'hE][15:13];</a>
+<a name="4744"><span class="lineNum">    4744 </span>            :         state_vec_29 = _RANDOM[6'hE][18:16];</a>
+<a name="4745"><span class="lineNum">    4745 </span>            :         state_vec_30 = _RANDOM[6'hE][21:19];</a>
+<a name="4746"><span class="lineNum">    4746 </span>            :         state_vec_31 = _RANDOM[6'hE][24:22];</a>
+<a name="4747"><span class="lineNum">    4747 </span>            :         state_vec_32 = _RANDOM[6'hE][27:25];</a>
+<a name="4748"><span class="lineNum">    4748 </span>            :         state_vec_33 = _RANDOM[6'hE][30:28];</a>
+<a name="4749"><span class="lineNum">    4749 </span>            :         state_vec_34 = {_RANDOM[6'hE][31], _RANDOM[6'hF][1:0]};</a>
+<a name="4750"><span class="lineNum">    4750 </span>            :         state_vec_35 = _RANDOM[6'hF][4:2];</a>
+<a name="4751"><span class="lineNum">    4751 </span>            :         state_vec_36 = _RANDOM[6'hF][7:5];</a>
+<a name="4752"><span class="lineNum">    4752 </span>            :         state_vec_37 = _RANDOM[6'hF][10:8];</a>
+<a name="4753"><span class="lineNum">    4753 </span>            :         state_vec_38 = _RANDOM[6'hF][13:11];</a>
+<a name="4754"><span class="lineNum">    4754 </span>            :         state_vec_39 = _RANDOM[6'hF][16:14];</a>
+<a name="4755"><span class="lineNum">    4755 </span>            :         state_vec_40 = _RANDOM[6'hF][19:17];</a>
+<a name="4756"><span class="lineNum">    4756 </span>            :         state_vec_41 = _RANDOM[6'hF][22:20];</a>
+<a name="4757"><span class="lineNum">    4757 </span>            :         state_vec_42 = _RANDOM[6'hF][25:23];</a>
+<a name="4758"><span class="lineNum">    4758 </span>            :         state_vec_43 = _RANDOM[6'hF][28:26];</a>
+<a name="4759"><span class="lineNum">    4759 </span>            :         state_vec_44 = _RANDOM[6'hF][31:29];</a>
+<a name="4760"><span class="lineNum">    4760 </span>            :         state_vec_45 = _RANDOM[6'h10][2:0];</a>
+<a name="4761"><span class="lineNum">    4761 </span>            :         state_vec_46 = _RANDOM[6'h10][5:3];</a>
+<a name="4762"><span class="lineNum">    4762 </span>            :         state_vec_47 = _RANDOM[6'h10][8:6];</a>
+<a name="4763"><span class="lineNum">    4763 </span>            :         state_vec_48 = _RANDOM[6'h10][11:9];</a>
+<a name="4764"><span class="lineNum">    4764 </span>            :         state_vec_49 = _RANDOM[6'h10][14:12];</a>
+<a name="4765"><span class="lineNum">    4765 </span>            :         state_vec_50 = _RANDOM[6'h10][17:15];</a>
+<a name="4766"><span class="lineNum">    4766 </span>            :         state_vec_51 = _RANDOM[6'h10][20:18];</a>
+<a name="4767"><span class="lineNum">    4767 </span>            :         state_vec_52 = _RANDOM[6'h10][23:21];</a>
+<a name="4768"><span class="lineNum">    4768 </span>            :         state_vec_53 = _RANDOM[6'h10][26:24];</a>
+<a name="4769"><span class="lineNum">    4769 </span>            :         state_vec_54 = _RANDOM[6'h10][29:27];</a>
+<a name="4770"><span class="lineNum">    4770 </span>            :         state_vec_55 = {_RANDOM[6'h10][31:30], _RANDOM[6'h11][0]};</a>
+<a name="4771"><span class="lineNum">    4771 </span>            :         state_vec_56 = _RANDOM[6'h11][3:1];</a>
+<a name="4772"><span class="lineNum">    4772 </span>            :         state_vec_57 = _RANDOM[6'h11][6:4];</a>
+<a name="4773"><span class="lineNum">    4773 </span>            :         state_vec_58 = _RANDOM[6'h11][9:7];</a>
+<a name="4774"><span class="lineNum">    4774 </span>            :         state_vec_59 = _RANDOM[6'h11][12:10];</a>
+<a name="4775"><span class="lineNum">    4775 </span>            :         state_vec_60 = _RANDOM[6'h11][15:13];</a>
+<a name="4776"><span class="lineNum">    4776 </span>            :         state_vec_61 = _RANDOM[6'h11][18:16];</a>
+<a name="4777"><span class="lineNum">    4777 </span>            :         state_vec_62 = _RANDOM[6'h11][21:19];</a>
+<a name="4778"><span class="lineNum">    4778 </span>            :         state_vec_63 = _RANDOM[6'h11][24:22];</a>
+<a name="4779"><span class="lineNum">    4779 </span>            :         state_vec_64 = _RANDOM[6'h11][27:25];</a>
+<a name="4780"><span class="lineNum">    4780 </span>            :         state_vec_65 = _RANDOM[6'h11][30:28];</a>
+<a name="4781"><span class="lineNum">    4781 </span>            :         state_vec_66 = {_RANDOM[6'h11][31], _RANDOM[6'h12][1:0]};</a>
+<a name="4782"><span class="lineNum">    4782 </span>            :         state_vec_67 = _RANDOM[6'h12][4:2];</a>
+<a name="4783"><span class="lineNum">    4783 </span>            :         state_vec_68 = _RANDOM[6'h12][7:5];</a>
+<a name="4784"><span class="lineNum">    4784 </span>            :         state_vec_69 = _RANDOM[6'h12][10:8];</a>
+<a name="4785"><span class="lineNum">    4785 </span>            :         state_vec_70 = _RANDOM[6'h12][13:11];</a>
+<a name="4786"><span class="lineNum">    4786 </span>            :         state_vec_71 = _RANDOM[6'h12][16:14];</a>
+<a name="4787"><span class="lineNum">    4787 </span>            :         state_vec_72 = _RANDOM[6'h12][19:17];</a>
+<a name="4788"><span class="lineNum">    4788 </span>            :         state_vec_73 = _RANDOM[6'h12][22:20];</a>
+<a name="4789"><span class="lineNum">    4789 </span>            :         state_vec_74 = _RANDOM[6'h12][25:23];</a>
+<a name="4790"><span class="lineNum">    4790 </span>            :         state_vec_75 = _RANDOM[6'h12][28:26];</a>
+<a name="4791"><span class="lineNum">    4791 </span>            :         state_vec_76 = _RANDOM[6'h12][31:29];</a>
+<a name="4792"><span class="lineNum">    4792 </span>            :         state_vec_77 = _RANDOM[6'h13][2:0];</a>
+<a name="4793"><span class="lineNum">    4793 </span>            :         state_vec_78 = _RANDOM[6'h13][5:3];</a>
+<a name="4794"><span class="lineNum">    4794 </span>            :         state_vec_79 = _RANDOM[6'h13][8:6];</a>
+<a name="4795"><span class="lineNum">    4795 </span>            :         state_vec_80 = _RANDOM[6'h13][11:9];</a>
+<a name="4796"><span class="lineNum">    4796 </span>            :         state_vec_81 = _RANDOM[6'h13][14:12];</a>
+<a name="4797"><span class="lineNum">    4797 </span>            :         state_vec_82 = _RANDOM[6'h13][17:15];</a>
+<a name="4798"><span class="lineNum">    4798 </span>            :         state_vec_83 = _RANDOM[6'h13][20:18];</a>
+<a name="4799"><span class="lineNum">    4799 </span>            :         state_vec_84 = _RANDOM[6'h13][23:21];</a>
+<a name="4800"><span class="lineNum">    4800 </span>            :         state_vec_85 = _RANDOM[6'h13][26:24];</a>
+<a name="4801"><span class="lineNum">    4801 </span>            :         state_vec_86 = _RANDOM[6'h13][29:27];</a>
+<a name="4802"><span class="lineNum">    4802 </span>            :         state_vec_87 = {_RANDOM[6'h13][31:30], _RANDOM[6'h14][0]};</a>
+<a name="4803"><span class="lineNum">    4803 </span>            :         state_vec_88 = _RANDOM[6'h14][3:1];</a>
+<a name="4804"><span class="lineNum">    4804 </span>            :         state_vec_89 = _RANDOM[6'h14][6:4];</a>
+<a name="4805"><span class="lineNum">    4805 </span>            :         state_vec_90 = _RANDOM[6'h14][9:7];</a>
+<a name="4806"><span class="lineNum">    4806 </span>            :         state_vec_91 = _RANDOM[6'h14][12:10];</a>
+<a name="4807"><span class="lineNum">    4807 </span>            :         state_vec_92 = _RANDOM[6'h14][15:13];</a>
+<a name="4808"><span class="lineNum">    4808 </span>            :         state_vec_93 = _RANDOM[6'h14][18:16];</a>
+<a name="4809"><span class="lineNum">    4809 </span>            :         state_vec_94 = _RANDOM[6'h14][21:19];</a>
+<a name="4810"><span class="lineNum">    4810 </span>            :         state_vec_95 = _RANDOM[6'h14][24:22];</a>
+<a name="4811"><span class="lineNum">    4811 </span>            :         state_vec_96 = _RANDOM[6'h14][27:25];</a>
+<a name="4812"><span class="lineNum">    4812 </span>            :         state_vec_97 = _RANDOM[6'h14][30:28];</a>
+<a name="4813"><span class="lineNum">    4813 </span>            :         state_vec_98 = {_RANDOM[6'h14][31], _RANDOM[6'h15][1:0]};</a>
+<a name="4814"><span class="lineNum">    4814 </span>            :         state_vec_99 = _RANDOM[6'h15][4:2];</a>
+<a name="4815"><span class="lineNum">    4815 </span>            :         state_vec_100 = _RANDOM[6'h15][7:5];</a>
+<a name="4816"><span class="lineNum">    4816 </span>            :         state_vec_101 = _RANDOM[6'h15][10:8];</a>
+<a name="4817"><span class="lineNum">    4817 </span>            :         state_vec_102 = _RANDOM[6'h15][13:11];</a>
+<a name="4818"><span class="lineNum">    4818 </span>            :         state_vec_103 = _RANDOM[6'h15][16:14];</a>
+<a name="4819"><span class="lineNum">    4819 </span>            :         state_vec_104 = _RANDOM[6'h15][19:17];</a>
+<a name="4820"><span class="lineNum">    4820 </span>            :         state_vec_105 = _RANDOM[6'h15][22:20];</a>
+<a name="4821"><span class="lineNum">    4821 </span>            :         state_vec_106 = _RANDOM[6'h15][25:23];</a>
+<a name="4822"><span class="lineNum">    4822 </span>            :         state_vec_107 = _RANDOM[6'h15][28:26];</a>
+<a name="4823"><span class="lineNum">    4823 </span>            :         state_vec_108 = _RANDOM[6'h15][31:29];</a>
+<a name="4824"><span class="lineNum">    4824 </span>            :         state_vec_109 = _RANDOM[6'h16][2:0];</a>
+<a name="4825"><span class="lineNum">    4825 </span>            :         state_vec_110 = _RANDOM[6'h16][5:3];</a>
+<a name="4826"><span class="lineNum">    4826 </span>            :         state_vec_111 = _RANDOM[6'h16][8:6];</a>
+<a name="4827"><span class="lineNum">    4827 </span>            :         state_vec_112 = _RANDOM[6'h16][11:9];</a>
+<a name="4828"><span class="lineNum">    4828 </span>            :         state_vec_113 = _RANDOM[6'h16][14:12];</a>
+<a name="4829"><span class="lineNum">    4829 </span>            :         state_vec_114 = _RANDOM[6'h16][17:15];</a>
+<a name="4830"><span class="lineNum">    4830 </span>            :         state_vec_115 = _RANDOM[6'h16][20:18];</a>
+<a name="4831"><span class="lineNum">    4831 </span>            :         state_vec_116 = _RANDOM[6'h16][23:21];</a>
+<a name="4832"><span class="lineNum">    4832 </span>            :         state_vec_117 = _RANDOM[6'h16][26:24];</a>
+<a name="4833"><span class="lineNum">    4833 </span>            :         state_vec_118 = _RANDOM[6'h16][29:27];</a>
+<a name="4834"><span class="lineNum">    4834 </span>            :         state_vec_119 = {_RANDOM[6'h16][31:30], _RANDOM[6'h17][0]};</a>
+<a name="4835"><span class="lineNum">    4835 </span>            :         state_vec_120 = _RANDOM[6'h17][3:1];</a>
+<a name="4836"><span class="lineNum">    4836 </span>            :         state_vec_121 = _RANDOM[6'h17][6:4];</a>
+<a name="4837"><span class="lineNum">    4837 </span>            :         state_vec_122 = _RANDOM[6'h17][9:7];</a>
+<a name="4838"><span class="lineNum">    4838 </span>            :         state_vec_123 = _RANDOM[6'h17][12:10];</a>
+<a name="4839"><span class="lineNum">    4839 </span>            :         state_vec_124 = _RANDOM[6'h17][15:13];</a>
+<a name="4840"><span class="lineNum">    4840 </span>            :         state_vec_125 = _RANDOM[6'h17][18:16];</a>
+<a name="4841"><span class="lineNum">    4841 </span>            :         state_vec_126 = _RANDOM[6'h17][21:19];</a>
+<a name="4842"><span class="lineNum">    4842 </span>            :         state_vec_127 = _RANDOM[6'h17][24:22];</a>
+<a name="4843"><span class="lineNum">    4843 </span>            :         state_vec_128 = _RANDOM[6'h17][27:25];</a>
+<a name="4844"><span class="lineNum">    4844 </span>            :         state_vec_129 = _RANDOM[6'h17][30:28];</a>
+<a name="4845"><span class="lineNum">    4845 </span>            :         state_vec_130 = {_RANDOM[6'h17][31], _RANDOM[6'h18][1:0]};</a>
+<a name="4846"><span class="lineNum">    4846 </span>            :         state_vec_131 = _RANDOM[6'h18][4:2];</a>
+<a name="4847"><span class="lineNum">    4847 </span>            :         state_vec_132 = _RANDOM[6'h18][7:5];</a>
+<a name="4848"><span class="lineNum">    4848 </span>            :         state_vec_133 = _RANDOM[6'h18][10:8];</a>
+<a name="4849"><span class="lineNum">    4849 </span>            :         state_vec_134 = _RANDOM[6'h18][13:11];</a>
+<a name="4850"><span class="lineNum">    4850 </span>            :         state_vec_135 = _RANDOM[6'h18][16:14];</a>
+<a name="4851"><span class="lineNum">    4851 </span>            :         state_vec_136 = _RANDOM[6'h18][19:17];</a>
+<a name="4852"><span class="lineNum">    4852 </span>            :         state_vec_137 = _RANDOM[6'h18][22:20];</a>
+<a name="4853"><span class="lineNum">    4853 </span>            :         state_vec_138 = _RANDOM[6'h18][25:23];</a>
+<a name="4854"><span class="lineNum">    4854 </span>            :         state_vec_139 = _RANDOM[6'h18][28:26];</a>
+<a name="4855"><span class="lineNum">    4855 </span>            :         state_vec_140 = _RANDOM[6'h18][31:29];</a>
+<a name="4856"><span class="lineNum">    4856 </span>            :         state_vec_141 = _RANDOM[6'h19][2:0];</a>
+<a name="4857"><span class="lineNum">    4857 </span>            :         state_vec_142 = _RANDOM[6'h19][5:3];</a>
+<a name="4858"><span class="lineNum">    4858 </span>            :         state_vec_143 = _RANDOM[6'h19][8:6];</a>
+<a name="4859"><span class="lineNum">    4859 </span>            :         state_vec_144 = _RANDOM[6'h19][11:9];</a>
+<a name="4860"><span class="lineNum">    4860 </span>            :         state_vec_145 = _RANDOM[6'h19][14:12];</a>
+<a name="4861"><span class="lineNum">    4861 </span>            :         state_vec_146 = _RANDOM[6'h19][17:15];</a>
+<a name="4862"><span class="lineNum">    4862 </span>            :         state_vec_147 = _RANDOM[6'h19][20:18];</a>
+<a name="4863"><span class="lineNum">    4863 </span>            :         state_vec_148 = _RANDOM[6'h19][23:21];</a>
+<a name="4864"><span class="lineNum">    4864 </span>            :         state_vec_149 = _RANDOM[6'h19][26:24];</a>
+<a name="4865"><span class="lineNum">    4865 </span>            :         state_vec_150 = _RANDOM[6'h19][29:27];</a>
+<a name="4866"><span class="lineNum">    4866 </span>            :         state_vec_151 = {_RANDOM[6'h19][31:30], _RANDOM[6'h1A][0]};</a>
+<a name="4867"><span class="lineNum">    4867 </span>            :         state_vec_152 = _RANDOM[6'h1A][3:1];</a>
+<a name="4868"><span class="lineNum">    4868 </span>            :         state_vec_153 = _RANDOM[6'h1A][6:4];</a>
+<a name="4869"><span class="lineNum">    4869 </span>            :         state_vec_154 = _RANDOM[6'h1A][9:7];</a>
+<a name="4870"><span class="lineNum">    4870 </span>            :         state_vec_155 = _RANDOM[6'h1A][12:10];</a>
+<a name="4871"><span class="lineNum">    4871 </span>            :         state_vec_156 = _RANDOM[6'h1A][15:13];</a>
+<a name="4872"><span class="lineNum">    4872 </span>            :         state_vec_157 = _RANDOM[6'h1A][18:16];</a>
+<a name="4873"><span class="lineNum">    4873 </span>            :         state_vec_158 = _RANDOM[6'h1A][21:19];</a>
+<a name="4874"><span class="lineNum">    4874 </span>            :         state_vec_159 = _RANDOM[6'h1A][24:22];</a>
+<a name="4875"><span class="lineNum">    4875 </span>            :         state_vec_160 = _RANDOM[6'h1A][27:25];</a>
+<a name="4876"><span class="lineNum">    4876 </span>            :         state_vec_161 = _RANDOM[6'h1A][30:28];</a>
+<a name="4877"><span class="lineNum">    4877 </span>            :         state_vec_162 = {_RANDOM[6'h1A][31], _RANDOM[6'h1B][1:0]};</a>
+<a name="4878"><span class="lineNum">    4878 </span>            :         state_vec_163 = _RANDOM[6'h1B][4:2];</a>
+<a name="4879"><span class="lineNum">    4879 </span>            :         state_vec_164 = _RANDOM[6'h1B][7:5];</a>
+<a name="4880"><span class="lineNum">    4880 </span>            :         state_vec_165 = _RANDOM[6'h1B][10:8];</a>
+<a name="4881"><span class="lineNum">    4881 </span>            :         state_vec_166 = _RANDOM[6'h1B][13:11];</a>
+<a name="4882"><span class="lineNum">    4882 </span>            :         state_vec_167 = _RANDOM[6'h1B][16:14];</a>
+<a name="4883"><span class="lineNum">    4883 </span>            :         state_vec_168 = _RANDOM[6'h1B][19:17];</a>
+<a name="4884"><span class="lineNum">    4884 </span>            :         state_vec_169 = _RANDOM[6'h1B][22:20];</a>
+<a name="4885"><span class="lineNum">    4885 </span>            :         state_vec_170 = _RANDOM[6'h1B][25:23];</a>
+<a name="4886"><span class="lineNum">    4886 </span>            :         state_vec_171 = _RANDOM[6'h1B][28:26];</a>
+<a name="4887"><span class="lineNum">    4887 </span>            :         state_vec_172 = _RANDOM[6'h1B][31:29];</a>
+<a name="4888"><span class="lineNum">    4888 </span>            :         state_vec_173 = _RANDOM[6'h1C][2:0];</a>
+<a name="4889"><span class="lineNum">    4889 </span>            :         state_vec_174 = _RANDOM[6'h1C][5:3];</a>
+<a name="4890"><span class="lineNum">    4890 </span>            :         state_vec_175 = _RANDOM[6'h1C][8:6];</a>
+<a name="4891"><span class="lineNum">    4891 </span>            :         state_vec_176 = _RANDOM[6'h1C][11:9];</a>
+<a name="4892"><span class="lineNum">    4892 </span>            :         state_vec_177 = _RANDOM[6'h1C][14:12];</a>
+<a name="4893"><span class="lineNum">    4893 </span>            :         state_vec_178 = _RANDOM[6'h1C][17:15];</a>
+<a name="4894"><span class="lineNum">    4894 </span>            :         state_vec_179 = _RANDOM[6'h1C][20:18];</a>
+<a name="4895"><span class="lineNum">    4895 </span>            :         state_vec_180 = _RANDOM[6'h1C][23:21];</a>
+<a name="4896"><span class="lineNum">    4896 </span>            :         state_vec_181 = _RANDOM[6'h1C][26:24];</a>
+<a name="4897"><span class="lineNum">    4897 </span>            :         state_vec_182 = _RANDOM[6'h1C][29:27];</a>
+<a name="4898"><span class="lineNum">    4898 </span>            :         state_vec_183 = {_RANDOM[6'h1C][31:30], _RANDOM[6'h1D][0]};</a>
+<a name="4899"><span class="lineNum">    4899 </span>            :         state_vec_184 = _RANDOM[6'h1D][3:1];</a>
+<a name="4900"><span class="lineNum">    4900 </span>            :         state_vec_185 = _RANDOM[6'h1D][6:4];</a>
+<a name="4901"><span class="lineNum">    4901 </span>            :         state_vec_186 = _RANDOM[6'h1D][9:7];</a>
+<a name="4902"><span class="lineNum">    4902 </span>            :         state_vec_187 = _RANDOM[6'h1D][12:10];</a>
+<a name="4903"><span class="lineNum">    4903 </span>            :         state_vec_188 = _RANDOM[6'h1D][15:13];</a>
+<a name="4904"><span class="lineNum">    4904 </span>            :         state_vec_189 = _RANDOM[6'h1D][18:16];</a>
+<a name="4905"><span class="lineNum">    4905 </span>            :         state_vec_190 = _RANDOM[6'h1D][21:19];</a>
+<a name="4906"><span class="lineNum">    4906 </span>            :         state_vec_191 = _RANDOM[6'h1D][24:22];</a>
+<a name="4907"><span class="lineNum">    4907 </span>            :         state_vec_192 = _RANDOM[6'h1D][27:25];</a>
+<a name="4908"><span class="lineNum">    4908 </span>            :         state_vec_193 = _RANDOM[6'h1D][30:28];</a>
+<a name="4909"><span class="lineNum">    4909 </span>            :         state_vec_194 = {_RANDOM[6'h1D][31], _RANDOM[6'h1E][1:0]};</a>
+<a name="4910"><span class="lineNum">    4910 </span>            :         state_vec_195 = _RANDOM[6'h1E][4:2];</a>
+<a name="4911"><span class="lineNum">    4911 </span>            :         state_vec_196 = _RANDOM[6'h1E][7:5];</a>
+<a name="4912"><span class="lineNum">    4912 </span>            :         state_vec_197 = _RANDOM[6'h1E][10:8];</a>
+<a name="4913"><span class="lineNum">    4913 </span>            :         state_vec_198 = _RANDOM[6'h1E][13:11];</a>
+<a name="4914"><span class="lineNum">    4914 </span>            :         state_vec_199 = _RANDOM[6'h1E][16:14];</a>
+<a name="4915"><span class="lineNum">    4915 </span>            :         state_vec_200 = _RANDOM[6'h1E][19:17];</a>
+<a name="4916"><span class="lineNum">    4916 </span>            :         state_vec_201 = _RANDOM[6'h1E][22:20];</a>
+<a name="4917"><span class="lineNum">    4917 </span>            :         state_vec_202 = _RANDOM[6'h1E][25:23];</a>
+<a name="4918"><span class="lineNum">    4918 </span>            :         state_vec_203 = _RANDOM[6'h1E][28:26];</a>
+<a name="4919"><span class="lineNum">    4919 </span>            :         state_vec_204 = _RANDOM[6'h1E][31:29];</a>
+<a name="4920"><span class="lineNum">    4920 </span>            :         state_vec_205 = _RANDOM[6'h1F][2:0];</a>
+<a name="4921"><span class="lineNum">    4921 </span>            :         state_vec_206 = _RANDOM[6'h1F][5:3];</a>
+<a name="4922"><span class="lineNum">    4922 </span>            :         state_vec_207 = _RANDOM[6'h1F][8:6];</a>
+<a name="4923"><span class="lineNum">    4923 </span>            :         state_vec_208 = _RANDOM[6'h1F][11:9];</a>
+<a name="4924"><span class="lineNum">    4924 </span>            :         state_vec_209 = _RANDOM[6'h1F][14:12];</a>
+<a name="4925"><span class="lineNum">    4925 </span>            :         state_vec_210 = _RANDOM[6'h1F][17:15];</a>
+<a name="4926"><span class="lineNum">    4926 </span>            :         state_vec_211 = _RANDOM[6'h1F][20:18];</a>
+<a name="4927"><span class="lineNum">    4927 </span>            :         state_vec_212 = _RANDOM[6'h1F][23:21];</a>
+<a name="4928"><span class="lineNum">    4928 </span>            :         state_vec_213 = _RANDOM[6'h1F][26:24];</a>
+<a name="4929"><span class="lineNum">    4929 </span>            :         state_vec_214 = _RANDOM[6'h1F][29:27];</a>
+<a name="4930"><span class="lineNum">    4930 </span>            :         state_vec_215 = {_RANDOM[6'h1F][31:30], _RANDOM[6'h20][0]};</a>
+<a name="4931"><span class="lineNum">    4931 </span>            :         state_vec_216 = _RANDOM[6'h20][3:1];</a>
+<a name="4932"><span class="lineNum">    4932 </span>            :         state_vec_217 = _RANDOM[6'h20][6:4];</a>
+<a name="4933"><span class="lineNum">    4933 </span>            :         state_vec_218 = _RANDOM[6'h20][9:7];</a>
+<a name="4934"><span class="lineNum">    4934 </span>            :         state_vec_219 = _RANDOM[6'h20][12:10];</a>
+<a name="4935"><span class="lineNum">    4935 </span>            :         state_vec_220 = _RANDOM[6'h20][15:13];</a>
+<a name="4936"><span class="lineNum">    4936 </span>            :         state_vec_221 = _RANDOM[6'h20][18:16];</a>
+<a name="4937"><span class="lineNum">    4937 </span>            :         state_vec_222 = _RANDOM[6'h20][21:19];</a>
+<a name="4938"><span class="lineNum">    4938 </span>            :         state_vec_223 = _RANDOM[6'h20][24:22];</a>
+<a name="4939"><span class="lineNum">    4939 </span>            :         state_vec_224 = _RANDOM[6'h20][27:25];</a>
+<a name="4940"><span class="lineNum">    4940 </span>            :         state_vec_225 = _RANDOM[6'h20][30:28];</a>
+<a name="4941"><span class="lineNum">    4941 </span>            :         state_vec_226 = {_RANDOM[6'h20][31], _RANDOM[6'h21][1:0]};</a>
+<a name="4942"><span class="lineNum">    4942 </span>            :         state_vec_227 = _RANDOM[6'h21][4:2];</a>
+<a name="4943"><span class="lineNum">    4943 </span>            :         state_vec_228 = _RANDOM[6'h21][7:5];</a>
+<a name="4944"><span class="lineNum">    4944 </span>            :         state_vec_229 = _RANDOM[6'h21][10:8];</a>
+<a name="4945"><span class="lineNum">    4945 </span>            :         state_vec_230 = _RANDOM[6'h21][13:11];</a>
+<a name="4946"><span class="lineNum">    4946 </span>            :         state_vec_231 = _RANDOM[6'h21][16:14];</a>
+<a name="4947"><span class="lineNum">    4947 </span>            :         state_vec_232 = _RANDOM[6'h21][19:17];</a>
+<a name="4948"><span class="lineNum">    4948 </span>            :         state_vec_233 = _RANDOM[6'h21][22:20];</a>
+<a name="4949"><span class="lineNum">    4949 </span>            :         state_vec_234 = _RANDOM[6'h21][25:23];</a>
+<a name="4950"><span class="lineNum">    4950 </span>            :         state_vec_235 = _RANDOM[6'h21][28:26];</a>
+<a name="4951"><span class="lineNum">    4951 </span>            :         state_vec_236 = _RANDOM[6'h21][31:29];</a>
+<a name="4952"><span class="lineNum">    4952 </span>            :         state_vec_237 = _RANDOM[6'h22][2:0];</a>
+<a name="4953"><span class="lineNum">    4953 </span>            :         state_vec_238 = _RANDOM[6'h22][5:3];</a>
+<a name="4954"><span class="lineNum">    4954 </span>            :         state_vec_239 = _RANDOM[6'h22][8:6];</a>
+<a name="4955"><span class="lineNum">    4955 </span>            :         state_vec_240 = _RANDOM[6'h22][11:9];</a>
+<a name="4956"><span class="lineNum">    4956 </span>            :         state_vec_241 = _RANDOM[6'h22][14:12];</a>
+<a name="4957"><span class="lineNum">    4957 </span>            :         state_vec_242 = _RANDOM[6'h22][17:15];</a>
+<a name="4958"><span class="lineNum">    4958 </span>            :         state_vec_243 = _RANDOM[6'h22][20:18];</a>
+<a name="4959"><span class="lineNum">    4959 </span>            :         state_vec_244 = _RANDOM[6'h22][23:21];</a>
+<a name="4960"><span class="lineNum">    4960 </span>            :         state_vec_245 = _RANDOM[6'h22][26:24];</a>
+<a name="4961"><span class="lineNum">    4961 </span>            :         state_vec_246 = _RANDOM[6'h22][29:27];</a>
+<a name="4962"><span class="lineNum">    4962 </span>            :         state_vec_247 = {_RANDOM[6'h22][31:30], _RANDOM[6'h23][0]};</a>
+<a name="4963"><span class="lineNum">    4963 </span>            :         state_vec_248 = _RANDOM[6'h23][3:1];</a>
+<a name="4964"><span class="lineNum">    4964 </span>            :         state_vec_249 = _RANDOM[6'h23][6:4];</a>
+<a name="4965"><span class="lineNum">    4965 </span>            :         state_vec_250 = _RANDOM[6'h23][9:7];</a>
+<a name="4966"><span class="lineNum">    4966 </span>            :         state_vec_251 = _RANDOM[6'h23][12:10];</a>
+<a name="4967"><span class="lineNum">    4967 </span>            :         state_vec_252 = _RANDOM[6'h23][15:13];</a>
+<a name="4968"><span class="lineNum">    4968 </span>            :         state_vec_253 = _RANDOM[6'h23][18:16];</a>
+<a name="4969"><span class="lineNum">    4969 </span>            :         state_vec_254 = _RANDOM[6'h23][21:19];</a>
+<a name="4970"><span class="lineNum">    4970 </span>            :         state_vec_255 = _RANDOM[6'h23][24:22];</a>
+<a name="4971"><span class="lineNum">    4971 </span>            :         state_vec_256 = _RANDOM[6'h23][27:25];</a>
+<a name="4972"><span class="lineNum">    4972 </span>            :         state_vec_257 = _RANDOM[6'h23][30:28];</a>
+<a name="4973"><span class="lineNum">    4973 </span>            :         state_vec_258 = {_RANDOM[6'h23][31], _RANDOM[6'h24][1:0]};</a>
+<a name="4974"><span class="lineNum">    4974 </span>            :         state_vec_259 = _RANDOM[6'h24][4:2];</a>
+<a name="4975"><span class="lineNum">    4975 </span>            :         state_vec_260 = _RANDOM[6'h24][7:5];</a>
+<a name="4976"><span class="lineNum">    4976 </span>            :         state_vec_261 = _RANDOM[6'h24][10:8];</a>
+<a name="4977"><span class="lineNum">    4977 </span>            :         state_vec_262 = _RANDOM[6'h24][13:11];</a>
+<a name="4978"><span class="lineNum">    4978 </span>            :         state_vec_263 = _RANDOM[6'h24][16:14];</a>
+<a name="4979"><span class="lineNum">    4979 </span>            :         state_vec_264 = _RANDOM[6'h24][19:17];</a>
+<a name="4980"><span class="lineNum">    4980 </span>            :         state_vec_265 = _RANDOM[6'h24][22:20];</a>
+<a name="4981"><span class="lineNum">    4981 </span>            :         state_vec_266 = _RANDOM[6'h24][25:23];</a>
+<a name="4982"><span class="lineNum">    4982 </span>            :         state_vec_267 = _RANDOM[6'h24][28:26];</a>
+<a name="4983"><span class="lineNum">    4983 </span>            :         state_vec_268 = _RANDOM[6'h24][31:29];</a>
+<a name="4984"><span class="lineNum">    4984 </span>            :         state_vec_269 = _RANDOM[6'h25][2:0];</a>
+<a name="4985"><span class="lineNum">    4985 </span>            :         state_vec_270 = _RANDOM[6'h25][5:3];</a>
+<a name="4986"><span class="lineNum">    4986 </span>            :         state_vec_271 = _RANDOM[6'h25][8:6];</a>
+<a name="4987"><span class="lineNum">    4987 </span>            :         state_vec_272 = _RANDOM[6'h25][11:9];</a>
+<a name="4988"><span class="lineNum">    4988 </span>            :         state_vec_273 = _RANDOM[6'h25][14:12];</a>
+<a name="4989"><span class="lineNum">    4989 </span>            :         state_vec_274 = _RANDOM[6'h25][17:15];</a>
+<a name="4990"><span class="lineNum">    4990 </span>            :         state_vec_275 = _RANDOM[6'h25][20:18];</a>
+<a name="4991"><span class="lineNum">    4991 </span>            :         state_vec_276 = _RANDOM[6'h25][23:21];</a>
+<a name="4992"><span class="lineNum">    4992 </span>            :         state_vec_277 = _RANDOM[6'h25][26:24];</a>
+<a name="4993"><span class="lineNum">    4993 </span>            :         state_vec_278 = _RANDOM[6'h25][29:27];</a>
+<a name="4994"><span class="lineNum">    4994 </span>            :         state_vec_279 = {_RANDOM[6'h25][31:30], _RANDOM[6'h26][0]};</a>
+<a name="4995"><span class="lineNum">    4995 </span>            :         state_vec_280 = _RANDOM[6'h26][3:1];</a>
+<a name="4996"><span class="lineNum">    4996 </span>            :         state_vec_281 = _RANDOM[6'h26][6:4];</a>
+<a name="4997"><span class="lineNum">    4997 </span>            :         state_vec_282 = _RANDOM[6'h26][9:7];</a>
+<a name="4998"><span class="lineNum">    4998 </span>            :         state_vec_283 = _RANDOM[6'h26][12:10];</a>
+<a name="4999"><span class="lineNum">    4999 </span>            :         state_vec_284 = _RANDOM[6'h26][15:13];</a>
+<a name="5000"><span class="lineNum">    5000 </span>            :         state_vec_285 = _RANDOM[6'h26][18:16];</a>
+<a name="5001"><span class="lineNum">    5001 </span>            :         state_vec_286 = _RANDOM[6'h26][21:19];</a>
+<a name="5002"><span class="lineNum">    5002 </span>            :         state_vec_287 = _RANDOM[6'h26][24:22];</a>
+<a name="5003"><span class="lineNum">    5003 </span>            :         state_vec_288 = _RANDOM[6'h26][27:25];</a>
+<a name="5004"><span class="lineNum">    5004 </span>            :         state_vec_289 = _RANDOM[6'h26][30:28];</a>
+<a name="5005"><span class="lineNum">    5005 </span>            :         state_vec_290 = {_RANDOM[6'h26][31], _RANDOM[6'h27][1:0]};</a>
+<a name="5006"><span class="lineNum">    5006 </span>            :         state_vec_291 = _RANDOM[6'h27][4:2];</a>
+<a name="5007"><span class="lineNum">    5007 </span>            :         state_vec_292 = _RANDOM[6'h27][7:5];</a>
+<a name="5008"><span class="lineNum">    5008 </span>            :         state_vec_293 = _RANDOM[6'h27][10:8];</a>
+<a name="5009"><span class="lineNum">    5009 </span>            :         state_vec_294 = _RANDOM[6'h27][13:11];</a>
+<a name="5010"><span class="lineNum">    5010 </span>            :         state_vec_295 = _RANDOM[6'h27][16:14];</a>
+<a name="5011"><span class="lineNum">    5011 </span>            :         state_vec_296 = _RANDOM[6'h27][19:17];</a>
+<a name="5012"><span class="lineNum">    5012 </span>            :         state_vec_297 = _RANDOM[6'h27][22:20];</a>
+<a name="5013"><span class="lineNum">    5013 </span>            :         state_vec_298 = _RANDOM[6'h27][25:23];</a>
+<a name="5014"><span class="lineNum">    5014 </span>            :         state_vec_299 = _RANDOM[6'h27][28:26];</a>
+<a name="5015"><span class="lineNum">    5015 </span>            :         state_vec_300 = _RANDOM[6'h27][31:29];</a>
+<a name="5016"><span class="lineNum">    5016 </span>            :         state_vec_301 = _RANDOM[6'h28][2:0];</a>
+<a name="5017"><span class="lineNum">    5017 </span>            :         state_vec_302 = _RANDOM[6'h28][5:3];</a>
+<a name="5018"><span class="lineNum">    5018 </span>            :         state_vec_303 = _RANDOM[6'h28][8:6];</a>
+<a name="5019"><span class="lineNum">    5019 </span>            :         state_vec_304 = _RANDOM[6'h28][11:9];</a>
+<a name="5020"><span class="lineNum">    5020 </span>            :         state_vec_305 = _RANDOM[6'h28][14:12];</a>
+<a name="5021"><span class="lineNum">    5021 </span>            :         state_vec_306 = _RANDOM[6'h28][17:15];</a>
+<a name="5022"><span class="lineNum">    5022 </span>            :         state_vec_307 = _RANDOM[6'h28][20:18];</a>
+<a name="5023"><span class="lineNum">    5023 </span>            :         state_vec_308 = _RANDOM[6'h28][23:21];</a>
+<a name="5024"><span class="lineNum">    5024 </span>            :         state_vec_309 = _RANDOM[6'h28][26:24];</a>
+<a name="5025"><span class="lineNum">    5025 </span>            :         state_vec_310 = _RANDOM[6'h28][29:27];</a>
+<a name="5026"><span class="lineNum">    5026 </span>            :         state_vec_311 = {_RANDOM[6'h28][31:30], _RANDOM[6'h29][0]};</a>
+<a name="5027"><span class="lineNum">    5027 </span>            :         state_vec_312 = _RANDOM[6'h29][3:1];</a>
+<a name="5028"><span class="lineNum">    5028 </span>            :         state_vec_313 = _RANDOM[6'h29][6:4];</a>
+<a name="5029"><span class="lineNum">    5029 </span>            :         state_vec_314 = _RANDOM[6'h29][9:7];</a>
+<a name="5030"><span class="lineNum">    5030 </span>            :         state_vec_315 = _RANDOM[6'h29][12:10];</a>
+<a name="5031"><span class="lineNum">    5031 </span>            :         state_vec_316 = _RANDOM[6'h29][15:13];</a>
+<a name="5032"><span class="lineNum">    5032 </span>            :         state_vec_317 = _RANDOM[6'h29][18:16];</a>
+<a name="5033"><span class="lineNum">    5033 </span>            :         state_vec_318 = _RANDOM[6'h29][21:19];</a>
+<a name="5034"><span class="lineNum">    5034 </span>            :         state_vec_319 = _RANDOM[6'h29][24:22];</a>
+<a name="5035"><span class="lineNum">    5035 </span>            :         state_vec_320 = _RANDOM[6'h29][27:25];</a>
+<a name="5036"><span class="lineNum">    5036 </span>            :         state_vec_321 = _RANDOM[6'h29][30:28];</a>
+<a name="5037"><span class="lineNum">    5037 </span>            :         state_vec_322 = {_RANDOM[6'h29][31], _RANDOM[6'h2A][1:0]};</a>
+<a name="5038"><span class="lineNum">    5038 </span>            :         state_vec_323 = _RANDOM[6'h2A][4:2];</a>
+<a name="5039"><span class="lineNum">    5039 </span>            :         state_vec_324 = _RANDOM[6'h2A][7:5];</a>
+<a name="5040"><span class="lineNum">    5040 </span>            :         state_vec_325 = _RANDOM[6'h2A][10:8];</a>
+<a name="5041"><span class="lineNum">    5041 </span>            :         state_vec_326 = _RANDOM[6'h2A][13:11];</a>
+<a name="5042"><span class="lineNum">    5042 </span>            :         state_vec_327 = _RANDOM[6'h2A][16:14];</a>
+<a name="5043"><span class="lineNum">    5043 </span>            :         state_vec_328 = _RANDOM[6'h2A][19:17];</a>
+<a name="5044"><span class="lineNum">    5044 </span>            :         state_vec_329 = _RANDOM[6'h2A][22:20];</a>
+<a name="5045"><span class="lineNum">    5045 </span>            :         state_vec_330 = _RANDOM[6'h2A][25:23];</a>
+<a name="5046"><span class="lineNum">    5046 </span>            :         state_vec_331 = _RANDOM[6'h2A][28:26];</a>
+<a name="5047"><span class="lineNum">    5047 </span>            :         state_vec_332 = _RANDOM[6'h2A][31:29];</a>
+<a name="5048"><span class="lineNum">    5048 </span>            :         state_vec_333 = _RANDOM[6'h2B][2:0];</a>
+<a name="5049"><span class="lineNum">    5049 </span>            :         state_vec_334 = _RANDOM[6'h2B][5:3];</a>
+<a name="5050"><span class="lineNum">    5050 </span>            :         state_vec_335 = _RANDOM[6'h2B][8:6];</a>
+<a name="5051"><span class="lineNum">    5051 </span>            :         state_vec_336 = _RANDOM[6'h2B][11:9];</a>
+<a name="5052"><span class="lineNum">    5052 </span>            :         state_vec_337 = _RANDOM[6'h2B][14:12];</a>
+<a name="5053"><span class="lineNum">    5053 </span>            :         state_vec_338 = _RANDOM[6'h2B][17:15];</a>
+<a name="5054"><span class="lineNum">    5054 </span>            :         state_vec_339 = _RANDOM[6'h2B][20:18];</a>
+<a name="5055"><span class="lineNum">    5055 </span>            :         state_vec_340 = _RANDOM[6'h2B][23:21];</a>
+<a name="5056"><span class="lineNum">    5056 </span>            :         state_vec_341 = _RANDOM[6'h2B][26:24];</a>
+<a name="5057"><span class="lineNum">    5057 </span>            :         state_vec_342 = _RANDOM[6'h2B][29:27];</a>
+<a name="5058"><span class="lineNum">    5058 </span>            :         state_vec_343 = {_RANDOM[6'h2B][31:30], _RANDOM[6'h2C][0]};</a>
+<a name="5059"><span class="lineNum">    5059 </span>            :         state_vec_344 = _RANDOM[6'h2C][3:1];</a>
+<a name="5060"><span class="lineNum">    5060 </span>            :         state_vec_345 = _RANDOM[6'h2C][6:4];</a>
+<a name="5061"><span class="lineNum">    5061 </span>            :         state_vec_346 = _RANDOM[6'h2C][9:7];</a>
+<a name="5062"><span class="lineNum">    5062 </span>            :         state_vec_347 = _RANDOM[6'h2C][12:10];</a>
+<a name="5063"><span class="lineNum">    5063 </span>            :         state_vec_348 = _RANDOM[6'h2C][15:13];</a>
+<a name="5064"><span class="lineNum">    5064 </span>            :         state_vec_349 = _RANDOM[6'h2C][18:16];</a>
+<a name="5065"><span class="lineNum">    5065 </span>            :         state_vec_350 = _RANDOM[6'h2C][21:19];</a>
+<a name="5066"><span class="lineNum">    5066 </span>            :         state_vec_351 = _RANDOM[6'h2C][24:22];</a>
+<a name="5067"><span class="lineNum">    5067 </span>            :         state_vec_352 = _RANDOM[6'h2C][27:25];</a>
+<a name="5068"><span class="lineNum">    5068 </span>            :         state_vec_353 = _RANDOM[6'h2C][30:28];</a>
+<a name="5069"><span class="lineNum">    5069 </span>            :         state_vec_354 = {_RANDOM[6'h2C][31], _RANDOM[6'h2D][1:0]};</a>
+<a name="5070"><span class="lineNum">    5070 </span>            :         state_vec_355 = _RANDOM[6'h2D][4:2];</a>
+<a name="5071"><span class="lineNum">    5071 </span>            :         state_vec_356 = _RANDOM[6'h2D][7:5];</a>
+<a name="5072"><span class="lineNum">    5072 </span>            :         state_vec_357 = _RANDOM[6'h2D][10:8];</a>
+<a name="5073"><span class="lineNum">    5073 </span>            :         state_vec_358 = _RANDOM[6'h2D][13:11];</a>
+<a name="5074"><span class="lineNum">    5074 </span>            :         state_vec_359 = _RANDOM[6'h2D][16:14];</a>
+<a name="5075"><span class="lineNum">    5075 </span>            :         state_vec_360 = _RANDOM[6'h2D][19:17];</a>
+<a name="5076"><span class="lineNum">    5076 </span>            :         state_vec_361 = _RANDOM[6'h2D][22:20];</a>
+<a name="5077"><span class="lineNum">    5077 </span>            :         state_vec_362 = _RANDOM[6'h2D][25:23];</a>
+<a name="5078"><span class="lineNum">    5078 </span>            :         state_vec_363 = _RANDOM[6'h2D][28:26];</a>
+<a name="5079"><span class="lineNum">    5079 </span>            :         state_vec_364 = _RANDOM[6'h2D][31:29];</a>
+<a name="5080"><span class="lineNum">    5080 </span>            :         state_vec_365 = _RANDOM[6'h2E][2:0];</a>
+<a name="5081"><span class="lineNum">    5081 </span>            :         state_vec_366 = _RANDOM[6'h2E][5:3];</a>
+<a name="5082"><span class="lineNum">    5082 </span>            :         state_vec_367 = _RANDOM[6'h2E][8:6];</a>
+<a name="5083"><span class="lineNum">    5083 </span>            :         state_vec_368 = _RANDOM[6'h2E][11:9];</a>
+<a name="5084"><span class="lineNum">    5084 </span>            :         state_vec_369 = _RANDOM[6'h2E][14:12];</a>
+<a name="5085"><span class="lineNum">    5085 </span>            :         state_vec_370 = _RANDOM[6'h2E][17:15];</a>
+<a name="5086"><span class="lineNum">    5086 </span>            :         state_vec_371 = _RANDOM[6'h2E][20:18];</a>
+<a name="5087"><span class="lineNum">    5087 </span>            :         state_vec_372 = _RANDOM[6'h2E][23:21];</a>
+<a name="5088"><span class="lineNum">    5088 </span>            :         state_vec_373 = _RANDOM[6'h2E][26:24];</a>
+<a name="5089"><span class="lineNum">    5089 </span>            :         state_vec_374 = _RANDOM[6'h2E][29:27];</a>
+<a name="5090"><span class="lineNum">    5090 </span>            :         state_vec_375 = {_RANDOM[6'h2E][31:30], _RANDOM[6'h2F][0]};</a>
+<a name="5091"><span class="lineNum">    5091 </span>            :         state_vec_376 = _RANDOM[6'h2F][3:1];</a>
+<a name="5092"><span class="lineNum">    5092 </span>            :         state_vec_377 = _RANDOM[6'h2F][6:4];</a>
+<a name="5093"><span class="lineNum">    5093 </span>            :         state_vec_378 = _RANDOM[6'h2F][9:7];</a>
+<a name="5094"><span class="lineNum">    5094 </span>            :         state_vec_379 = _RANDOM[6'h2F][12:10];</a>
+<a name="5095"><span class="lineNum">    5095 </span>            :         state_vec_380 = _RANDOM[6'h2F][15:13];</a>
+<a name="5096"><span class="lineNum">    5096 </span>            :         state_vec_381 = _RANDOM[6'h2F][18:16];</a>
+<a name="5097"><span class="lineNum">    5097 </span>            :         state_vec_382 = _RANDOM[6'h2F][21:19];</a>
+<a name="5098"><span class="lineNum">    5098 </span>            :         state_vec_383 = _RANDOM[6'h2F][24:22];</a>
+<a name="5099"><span class="lineNum">    5099 </span>            :         state_vec_384 = _RANDOM[6'h2F][27:25];</a>
+<a name="5100"><span class="lineNum">    5100 </span>            :         state_vec_385 = _RANDOM[6'h2F][30:28];</a>
+<a name="5101"><span class="lineNum">    5101 </span>            :         state_vec_386 = {_RANDOM[6'h2F][31], _RANDOM[6'h30][1:0]};</a>
+<a name="5102"><span class="lineNum">    5102 </span>            :         state_vec_387 = _RANDOM[6'h30][4:2];</a>
+<a name="5103"><span class="lineNum">    5103 </span>            :         state_vec_388 = _RANDOM[6'h30][7:5];</a>
+<a name="5104"><span class="lineNum">    5104 </span>            :         state_vec_389 = _RANDOM[6'h30][10:8];</a>
+<a name="5105"><span class="lineNum">    5105 </span>            :         state_vec_390 = _RANDOM[6'h30][13:11];</a>
+<a name="5106"><span class="lineNum">    5106 </span>            :         state_vec_391 = _RANDOM[6'h30][16:14];</a>
+<a name="5107"><span class="lineNum">    5107 </span>            :         state_vec_392 = _RANDOM[6'h30][19:17];</a>
+<a name="5108"><span class="lineNum">    5108 </span>            :         state_vec_393 = _RANDOM[6'h30][22:20];</a>
+<a name="5109"><span class="lineNum">    5109 </span>            :         state_vec_394 = _RANDOM[6'h30][25:23];</a>
+<a name="5110"><span class="lineNum">    5110 </span>            :         state_vec_395 = _RANDOM[6'h30][28:26];</a>
+<a name="5111"><span class="lineNum">    5111 </span>            :         state_vec_396 = _RANDOM[6'h30][31:29];</a>
+<a name="5112"><span class="lineNum">    5112 </span>            :         state_vec_397 = _RANDOM[6'h31][2:0];</a>
+<a name="5113"><span class="lineNum">    5113 </span>            :         state_vec_398 = _RANDOM[6'h31][5:3];</a>
+<a name="5114"><span class="lineNum">    5114 </span>            :         state_vec_399 = _RANDOM[6'h31][8:6];</a>
+<a name="5115"><span class="lineNum">    5115 </span>            :         state_vec_400 = _RANDOM[6'h31][11:9];</a>
+<a name="5116"><span class="lineNum">    5116 </span>            :         state_vec_401 = _RANDOM[6'h31][14:12];</a>
+<a name="5117"><span class="lineNum">    5117 </span>            :         state_vec_402 = _RANDOM[6'h31][17:15];</a>
+<a name="5118"><span class="lineNum">    5118 </span>            :         state_vec_403 = _RANDOM[6'h31][20:18];</a>
+<a name="5119"><span class="lineNum">    5119 </span>            :         state_vec_404 = _RANDOM[6'h31][23:21];</a>
+<a name="5120"><span class="lineNum">    5120 </span>            :         state_vec_405 = _RANDOM[6'h31][26:24];</a>
+<a name="5121"><span class="lineNum">    5121 </span>            :         state_vec_406 = _RANDOM[6'h31][29:27];</a>
+<a name="5122"><span class="lineNum">    5122 </span>            :         state_vec_407 = {_RANDOM[6'h31][31:30], _RANDOM[6'h32][0]};</a>
+<a name="5123"><span class="lineNum">    5123 </span>            :         state_vec_408 = _RANDOM[6'h32][3:1];</a>
+<a name="5124"><span class="lineNum">    5124 </span>            :         state_vec_409 = _RANDOM[6'h32][6:4];</a>
+<a name="5125"><span class="lineNum">    5125 </span>            :         state_vec_410 = _RANDOM[6'h32][9:7];</a>
+<a name="5126"><span class="lineNum">    5126 </span>            :         state_vec_411 = _RANDOM[6'h32][12:10];</a>
+<a name="5127"><span class="lineNum">    5127 </span>            :         state_vec_412 = _RANDOM[6'h32][15:13];</a>
+<a name="5128"><span class="lineNum">    5128 </span>            :         state_vec_413 = _RANDOM[6'h32][18:16];</a>
+<a name="5129"><span class="lineNum">    5129 </span>            :         state_vec_414 = _RANDOM[6'h32][21:19];</a>
+<a name="5130"><span class="lineNum">    5130 </span>            :         state_vec_415 = _RANDOM[6'h32][24:22];</a>
+<a name="5131"><span class="lineNum">    5131 </span>            :         state_vec_416 = _RANDOM[6'h32][27:25];</a>
+<a name="5132"><span class="lineNum">    5132 </span>            :         state_vec_417 = _RANDOM[6'h32][30:28];</a>
+<a name="5133"><span class="lineNum">    5133 </span>            :         state_vec_418 = {_RANDOM[6'h32][31], _RANDOM[6'h33][1:0]};</a>
+<a name="5134"><span class="lineNum">    5134 </span>            :         state_vec_419 = _RANDOM[6'h33][4:2];</a>
+<a name="5135"><span class="lineNum">    5135 </span>            :         state_vec_420 = _RANDOM[6'h33][7:5];</a>
+<a name="5136"><span class="lineNum">    5136 </span>            :         state_vec_421 = _RANDOM[6'h33][10:8];</a>
+<a name="5137"><span class="lineNum">    5137 </span>            :         state_vec_422 = _RANDOM[6'h33][13:11];</a>
+<a name="5138"><span class="lineNum">    5138 </span>            :         state_vec_423 = _RANDOM[6'h33][16:14];</a>
+<a name="5139"><span class="lineNum">    5139 </span>            :         state_vec_424 = _RANDOM[6'h33][19:17];</a>
+<a name="5140"><span class="lineNum">    5140 </span>            :         state_vec_425 = _RANDOM[6'h33][22:20];</a>
+<a name="5141"><span class="lineNum">    5141 </span>            :         state_vec_426 = _RANDOM[6'h33][25:23];</a>
+<a name="5142"><span class="lineNum">    5142 </span>            :         state_vec_427 = _RANDOM[6'h33][28:26];</a>
+<a name="5143"><span class="lineNum">    5143 </span>            :         state_vec_428 = _RANDOM[6'h33][31:29];</a>
+<a name="5144"><span class="lineNum">    5144 </span>            :         state_vec_429 = _RANDOM[6'h34][2:0];</a>
+<a name="5145"><span class="lineNum">    5145 </span>            :         state_vec_430 = _RANDOM[6'h34][5:3];</a>
+<a name="5146"><span class="lineNum">    5146 </span>            :         state_vec_431 = _RANDOM[6'h34][8:6];</a>
+<a name="5147"><span class="lineNum">    5147 </span>            :         state_vec_432 = _RANDOM[6'h34][11:9];</a>
+<a name="5148"><span class="lineNum">    5148 </span>            :         state_vec_433 = _RANDOM[6'h34][14:12];</a>
+<a name="5149"><span class="lineNum">    5149 </span>            :         state_vec_434 = _RANDOM[6'h34][17:15];</a>
+<a name="5150"><span class="lineNum">    5150 </span>            :         state_vec_435 = _RANDOM[6'h34][20:18];</a>
+<a name="5151"><span class="lineNum">    5151 </span>            :         state_vec_436 = _RANDOM[6'h34][23:21];</a>
+<a name="5152"><span class="lineNum">    5152 </span>            :         state_vec_437 = _RANDOM[6'h34][26:24];</a>
+<a name="5153"><span class="lineNum">    5153 </span>            :         state_vec_438 = _RANDOM[6'h34][29:27];</a>
+<a name="5154"><span class="lineNum">    5154 </span>            :         state_vec_439 = {_RANDOM[6'h34][31:30], _RANDOM[6'h35][0]};</a>
+<a name="5155"><span class="lineNum">    5155 </span>            :         state_vec_440 = _RANDOM[6'h35][3:1];</a>
+<a name="5156"><span class="lineNum">    5156 </span>            :         state_vec_441 = _RANDOM[6'h35][6:4];</a>
+<a name="5157"><span class="lineNum">    5157 </span>            :         state_vec_442 = _RANDOM[6'h35][9:7];</a>
+<a name="5158"><span class="lineNum">    5158 </span>            :         state_vec_443 = _RANDOM[6'h35][12:10];</a>
+<a name="5159"><span class="lineNum">    5159 </span>            :         state_vec_444 = _RANDOM[6'h35][15:13];</a>
+<a name="5160"><span class="lineNum">    5160 </span>            :         state_vec_445 = _RANDOM[6'h35][18:16];</a>
+<a name="5161"><span class="lineNum">    5161 </span>            :         state_vec_446 = _RANDOM[6'h35][21:19];</a>
+<a name="5162"><span class="lineNum">    5162 </span>            :         state_vec_447 = _RANDOM[6'h35][24:22];</a>
+<a name="5163"><span class="lineNum">    5163 </span>            :         state_vec_448 = _RANDOM[6'h35][27:25];</a>
+<a name="5164"><span class="lineNum">    5164 </span>            :         state_vec_449 = _RANDOM[6'h35][30:28];</a>
+<a name="5165"><span class="lineNum">    5165 </span>            :         state_vec_450 = {_RANDOM[6'h35][31], _RANDOM[6'h36][1:0]};</a>
+<a name="5166"><span class="lineNum">    5166 </span>            :         state_vec_451 = _RANDOM[6'h36][4:2];</a>
+<a name="5167"><span class="lineNum">    5167 </span>            :         state_vec_452 = _RANDOM[6'h36][7:5];</a>
+<a name="5168"><span class="lineNum">    5168 </span>            :         state_vec_453 = _RANDOM[6'h36][10:8];</a>
+<a name="5169"><span class="lineNum">    5169 </span>            :         state_vec_454 = _RANDOM[6'h36][13:11];</a>
+<a name="5170"><span class="lineNum">    5170 </span>            :         state_vec_455 = _RANDOM[6'h36][16:14];</a>
+<a name="5171"><span class="lineNum">    5171 </span>            :         state_vec_456 = _RANDOM[6'h36][19:17];</a>
+<a name="5172"><span class="lineNum">    5172 </span>            :         state_vec_457 = _RANDOM[6'h36][22:20];</a>
+<a name="5173"><span class="lineNum">    5173 </span>            :         state_vec_458 = _RANDOM[6'h36][25:23];</a>
+<a name="5174"><span class="lineNum">    5174 </span>            :         state_vec_459 = _RANDOM[6'h36][28:26];</a>
+<a name="5175"><span class="lineNum">    5175 </span>            :         state_vec_460 = _RANDOM[6'h36][31:29];</a>
+<a name="5176"><span class="lineNum">    5176 </span>            :         state_vec_461 = _RANDOM[6'h37][2:0];</a>
+<a name="5177"><span class="lineNum">    5177 </span>            :         state_vec_462 = _RANDOM[6'h37][5:3];</a>
+<a name="5178"><span class="lineNum">    5178 </span>            :         state_vec_463 = _RANDOM[6'h37][8:6];</a>
+<a name="5179"><span class="lineNum">    5179 </span>            :         state_vec_464 = _RANDOM[6'h37][11:9];</a>
+<a name="5180"><span class="lineNum">    5180 </span>            :         state_vec_465 = _RANDOM[6'h37][14:12];</a>
+<a name="5181"><span class="lineNum">    5181 </span>            :         state_vec_466 = _RANDOM[6'h37][17:15];</a>
+<a name="5182"><span class="lineNum">    5182 </span>            :         state_vec_467 = _RANDOM[6'h37][20:18];</a>
+<a name="5183"><span class="lineNum">    5183 </span>            :         state_vec_468 = _RANDOM[6'h37][23:21];</a>
+<a name="5184"><span class="lineNum">    5184 </span>            :         state_vec_469 = _RANDOM[6'h37][26:24];</a>
+<a name="5185"><span class="lineNum">    5185 </span>            :         state_vec_470 = _RANDOM[6'h37][29:27];</a>
+<a name="5186"><span class="lineNum">    5186 </span>            :         state_vec_471 = {_RANDOM[6'h37][31:30], _RANDOM[6'h38][0]};</a>
+<a name="5187"><span class="lineNum">    5187 </span>            :         state_vec_472 = _RANDOM[6'h38][3:1];</a>
+<a name="5188"><span class="lineNum">    5188 </span>            :         state_vec_473 = _RANDOM[6'h38][6:4];</a>
+<a name="5189"><span class="lineNum">    5189 </span>            :         state_vec_474 = _RANDOM[6'h38][9:7];</a>
+<a name="5190"><span class="lineNum">    5190 </span>            :         state_vec_475 = _RANDOM[6'h38][12:10];</a>
+<a name="5191"><span class="lineNum">    5191 </span>            :         state_vec_476 = _RANDOM[6'h38][15:13];</a>
+<a name="5192"><span class="lineNum">    5192 </span>            :         state_vec_477 = _RANDOM[6'h38][18:16];</a>
+<a name="5193"><span class="lineNum">    5193 </span>            :         state_vec_478 = _RANDOM[6'h38][21:19];</a>
+<a name="5194"><span class="lineNum">    5194 </span>            :         state_vec_479 = _RANDOM[6'h38][24:22];</a>
+<a name="5195"><span class="lineNum">    5195 </span>            :         state_vec_480 = _RANDOM[6'h38][27:25];</a>
+<a name="5196"><span class="lineNum">    5196 </span>            :         state_vec_481 = _RANDOM[6'h38][30:28];</a>
+<a name="5197"><span class="lineNum">    5197 </span>            :         state_vec_482 = {_RANDOM[6'h38][31], _RANDOM[6'h39][1:0]};</a>
+<a name="5198"><span class="lineNum">    5198 </span>            :         state_vec_483 = _RANDOM[6'h39][4:2];</a>
+<a name="5199"><span class="lineNum">    5199 </span>            :         state_vec_484 = _RANDOM[6'h39][7:5];</a>
+<a name="5200"><span class="lineNum">    5200 </span>            :         state_vec_485 = _RANDOM[6'h39][10:8];</a>
+<a name="5201"><span class="lineNum">    5201 </span>            :         state_vec_486 = _RANDOM[6'h39][13:11];</a>
+<a name="5202"><span class="lineNum">    5202 </span>            :         state_vec_487 = _RANDOM[6'h39][16:14];</a>
+<a name="5203"><span class="lineNum">    5203 </span>            :         state_vec_488 = _RANDOM[6'h39][19:17];</a>
+<a name="5204"><span class="lineNum">    5204 </span>            :         state_vec_489 = _RANDOM[6'h39][22:20];</a>
+<a name="5205"><span class="lineNum">    5205 </span>            :         state_vec_490 = _RANDOM[6'h39][25:23];</a>
+<a name="5206"><span class="lineNum">    5206 </span>            :         state_vec_491 = _RANDOM[6'h39][28:26];</a>
+<a name="5207"><span class="lineNum">    5207 </span>            :         state_vec_492 = _RANDOM[6'h39][31:29];</a>
+<a name="5208"><span class="lineNum">    5208 </span>            :         state_vec_493 = _RANDOM[6'h3A][2:0];</a>
+<a name="5209"><span class="lineNum">    5209 </span>            :         state_vec_494 = _RANDOM[6'h3A][5:3];</a>
+<a name="5210"><span class="lineNum">    5210 </span>            :         state_vec_495 = _RANDOM[6'h3A][8:6];</a>
+<a name="5211"><span class="lineNum">    5211 </span>            :         state_vec_496 = _RANDOM[6'h3A][11:9];</a>
+<a name="5212"><span class="lineNum">    5212 </span>            :         state_vec_497 = _RANDOM[6'h3A][14:12];</a>
+<a name="5213"><span class="lineNum">    5213 </span>            :         state_vec_498 = _RANDOM[6'h3A][17:15];</a>
+<a name="5214"><span class="lineNum">    5214 </span>            :         state_vec_499 = _RANDOM[6'h3A][20:18];</a>
+<a name="5215"><span class="lineNum">    5215 </span>            :         state_vec_500 = _RANDOM[6'h3A][23:21];</a>
+<a name="5216"><span class="lineNum">    5216 </span>            :         state_vec_501 = _RANDOM[6'h3A][26:24];</a>
+<a name="5217"><span class="lineNum">    5217 </span>            :         state_vec_502 = _RANDOM[6'h3A][29:27];</a>
+<a name="5218"><span class="lineNum">    5218 </span>            :         state_vec_503 = {_RANDOM[6'h3A][31:30], _RANDOM[6'h3B][0]};</a>
+<a name="5219"><span class="lineNum">    5219 </span>            :         state_vec_504 = _RANDOM[6'h3B][3:1];</a>
+<a name="5220"><span class="lineNum">    5220 </span>            :         state_vec_505 = _RANDOM[6'h3B][6:4];</a>
+<a name="5221"><span class="lineNum">    5221 </span>            :         state_vec_506 = _RANDOM[6'h3B][9:7];</a>
+<a name="5222"><span class="lineNum">    5222 </span>            :         state_vec_507 = _RANDOM[6'h3B][12:10];</a>
+<a name="5223"><span class="lineNum">    5223 </span>            :         state_vec_508 = _RANDOM[6'h3B][15:13];</a>
+<a name="5224"><span class="lineNum">    5224 </span>            :         state_vec_509 = _RANDOM[6'h3B][18:16];</a>
+<a name="5225"><span class="lineNum">    5225 </span>            :         state_vec_510 = _RANDOM[6'h3B][21:19];</a>
+<a name="5226"><span class="lineNum">    5226 </span>            :         state_vec_511 = _RANDOM[6'h3B][24:22];</a>
+<a name="5227"><span class="lineNum">    5227 </span>            :         touch_set_0_REG = {_RANDOM[6'h3B][31:25], _RANDOM[6'h3C][1:0]};</a>
+<a name="5228"><span class="lineNum">    5228 </span>            :         touch_way_0_valid_REG = _RANDOM[6'h3C][2];</a>
+<a name="5229"><span class="lineNum">    5229 </span>            :         touch_way_0_bits_REG = _RANDOM[6'h3C][4:3];</a>
+<a name="5230"><span class="lineNum">    5230 </span>            :         allocWriteWay_REG_0 = _RANDOM[6'h3C][5];</a>
+<a name="5231"><span class="lineNum">    5231 </span>            :         allocWriteWay_REG_1 = _RANDOM[6'h3C][6];</a>
+<a name="5232"><span class="lineNum">    5232 </span>            :         allocWriteWay_REG_2 = _RANDOM[6'h3C][7];</a>
+<a name="5233"><span class="lineNum">    5233 </span>            :         allocWriteWay_REG_3 = _RANDOM[6'h3C][8];</a>
+<a name="5234"><span class="lineNum">    5234 </span><span class="lineCov">         17 :       `endif // RANDOMIZE_REG_INIT</span></a>
+<a name="5235"><span class="lineNum">    5235 </span><span class="lineCov">         12 :       if (reset) begin</span></a>
+<a name="5236"><span class="lineNum">    5236 </span><span class="lineCov">         12 :         state_vec_0 = 3'h0;</span></a>
+<a name="5237"><span class="lineNum">    5237 </span><span class="lineCov">         12 :         state_vec_1 = 3'h0;</span></a>
+<a name="5238"><span class="lineNum">    5238 </span><span class="lineCov">         12 :         state_vec_2 = 3'h0;</span></a>
+<a name="5239"><span class="lineNum">    5239 </span><span class="lineCov">         12 :         state_vec_3 = 3'h0;</span></a>
+<a name="5240"><span class="lineNum">    5240 </span><span class="lineCov">         12 :         state_vec_4 = 3'h0;</span></a>
+<a name="5241"><span class="lineNum">    5241 </span><span class="lineCov">         12 :         state_vec_5 = 3'h0;</span></a>
+<a name="5242"><span class="lineNum">    5242 </span><span class="lineCov">         12 :         state_vec_6 = 3'h0;</span></a>
+<a name="5243"><span class="lineNum">    5243 </span><span class="lineCov">         12 :         state_vec_7 = 3'h0;</span></a>
+<a name="5244"><span class="lineNum">    5244 </span><span class="lineCov">         12 :         state_vec_8 = 3'h0;</span></a>
+<a name="5245"><span class="lineNum">    5245 </span><span class="lineCov">         12 :         state_vec_9 = 3'h0;</span></a>
+<a name="5246"><span class="lineNum">    5246 </span><span class="lineCov">         12 :         state_vec_10 = 3'h0;</span></a>
+<a name="5247"><span class="lineNum">    5247 </span><span class="lineCov">         12 :         state_vec_11 = 3'h0;</span></a>
+<a name="5248"><span class="lineNum">    5248 </span><span class="lineCov">         12 :         state_vec_12 = 3'h0;</span></a>
+<a name="5249"><span class="lineNum">    5249 </span><span class="lineCov">         12 :         state_vec_13 = 3'h0;</span></a>
+<a name="5250"><span class="lineNum">    5250 </span><span class="lineCov">         12 :         state_vec_14 = 3'h0;</span></a>
+<a name="5251"><span class="lineNum">    5251 </span><span class="lineCov">         12 :         state_vec_15 = 3'h0;</span></a>
+<a name="5252"><span class="lineNum">    5252 </span><span class="lineCov">         12 :         state_vec_16 = 3'h0;</span></a>
+<a name="5253"><span class="lineNum">    5253 </span><span class="lineCov">         12 :         state_vec_17 = 3'h0;</span></a>
+<a name="5254"><span class="lineNum">    5254 </span><span class="lineCov">         12 :         state_vec_18 = 3'h0;</span></a>
+<a name="5255"><span class="lineNum">    5255 </span><span class="lineCov">         12 :         state_vec_19 = 3'h0;</span></a>
+<a name="5256"><span class="lineNum">    5256 </span><span class="lineCov">         12 :         state_vec_20 = 3'h0;</span></a>
+<a name="5257"><span class="lineNum">    5257 </span><span class="lineCov">         12 :         state_vec_21 = 3'h0;</span></a>
+<a name="5258"><span class="lineNum">    5258 </span><span class="lineCov">         12 :         state_vec_22 = 3'h0;</span></a>
+<a name="5259"><span class="lineNum">    5259 </span><span class="lineCov">         12 :         state_vec_23 = 3'h0;</span></a>
+<a name="5260"><span class="lineNum">    5260 </span><span class="lineCov">         12 :         state_vec_24 = 3'h0;</span></a>
+<a name="5261"><span class="lineNum">    5261 </span><span class="lineCov">         12 :         state_vec_25 = 3'h0;</span></a>
+<a name="5262"><span class="lineNum">    5262 </span><span class="lineCov">         12 :         state_vec_26 = 3'h0;</span></a>
+<a name="5263"><span class="lineNum">    5263 </span><span class="lineCov">         12 :         state_vec_27 = 3'h0;</span></a>
+<a name="5264"><span class="lineNum">    5264 </span><span class="lineCov">         12 :         state_vec_28 = 3'h0;</span></a>
+<a name="5265"><span class="lineNum">    5265 </span><span class="lineCov">         12 :         state_vec_29 = 3'h0;</span></a>
+<a name="5266"><span class="lineNum">    5266 </span><span class="lineCov">         12 :         state_vec_30 = 3'h0;</span></a>
+<a name="5267"><span class="lineNum">    5267 </span><span class="lineCov">         12 :         state_vec_31 = 3'h0;</span></a>
+<a name="5268"><span class="lineNum">    5268 </span><span class="lineCov">         12 :         state_vec_32 = 3'h0;</span></a>
+<a name="5269"><span class="lineNum">    5269 </span><span class="lineCov">         12 :         state_vec_33 = 3'h0;</span></a>
+<a name="5270"><span class="lineNum">    5270 </span><span class="lineCov">         12 :         state_vec_34 = 3'h0;</span></a>
+<a name="5271"><span class="lineNum">    5271 </span><span class="lineCov">         12 :         state_vec_35 = 3'h0;</span></a>
+<a name="5272"><span class="lineNum">    5272 </span><span class="lineCov">         12 :         state_vec_36 = 3'h0;</span></a>
+<a name="5273"><span class="lineNum">    5273 </span><span class="lineCov">         12 :         state_vec_37 = 3'h0;</span></a>
+<a name="5274"><span class="lineNum">    5274 </span><span class="lineCov">         12 :         state_vec_38 = 3'h0;</span></a>
+<a name="5275"><span class="lineNum">    5275 </span><span class="lineCov">         12 :         state_vec_39 = 3'h0;</span></a>
+<a name="5276"><span class="lineNum">    5276 </span><span class="lineCov">         12 :         state_vec_40 = 3'h0;</span></a>
+<a name="5277"><span class="lineNum">    5277 </span><span class="lineCov">         12 :         state_vec_41 = 3'h0;</span></a>
+<a name="5278"><span class="lineNum">    5278 </span><span class="lineCov">         12 :         state_vec_42 = 3'h0;</span></a>
+<a name="5279"><span class="lineNum">    5279 </span><span class="lineCov">         12 :         state_vec_43 = 3'h0;</span></a>
+<a name="5280"><span class="lineNum">    5280 </span><span class="lineCov">         12 :         state_vec_44 = 3'h0;</span></a>
+<a name="5281"><span class="lineNum">    5281 </span><span class="lineCov">         12 :         state_vec_45 = 3'h0;</span></a>
+<a name="5282"><span class="lineNum">    5282 </span><span class="lineCov">         12 :         state_vec_46 = 3'h0;</span></a>
+<a name="5283"><span class="lineNum">    5283 </span><span class="lineCov">         12 :         state_vec_47 = 3'h0;</span></a>
+<a name="5284"><span class="lineNum">    5284 </span><span class="lineCov">         12 :         state_vec_48 = 3'h0;</span></a>
+<a name="5285"><span class="lineNum">    5285 </span><span class="lineCov">         12 :         state_vec_49 = 3'h0;</span></a>
+<a name="5286"><span class="lineNum">    5286 </span><span class="lineCov">         12 :         state_vec_50 = 3'h0;</span></a>
+<a name="5287"><span class="lineNum">    5287 </span><span class="lineCov">         12 :         state_vec_51 = 3'h0;</span></a>
+<a name="5288"><span class="lineNum">    5288 </span><span class="lineCov">         12 :         state_vec_52 = 3'h0;</span></a>
+<a name="5289"><span class="lineNum">    5289 </span><span class="lineCov">         12 :         state_vec_53 = 3'h0;</span></a>
+<a name="5290"><span class="lineNum">    5290 </span><span class="lineCov">         12 :         state_vec_54 = 3'h0;</span></a>
+<a name="5291"><span class="lineNum">    5291 </span><span class="lineCov">         12 :         state_vec_55 = 3'h0;</span></a>
+<a name="5292"><span class="lineNum">    5292 </span><span class="lineCov">         12 :         state_vec_56 = 3'h0;</span></a>
+<a name="5293"><span class="lineNum">    5293 </span><span class="lineCov">         12 :         state_vec_57 = 3'h0;</span></a>
+<a name="5294"><span class="lineNum">    5294 </span><span class="lineCov">         12 :         state_vec_58 = 3'h0;</span></a>
+<a name="5295"><span class="lineNum">    5295 </span><span class="lineCov">         12 :         state_vec_59 = 3'h0;</span></a>
+<a name="5296"><span class="lineNum">    5296 </span><span class="lineCov">         12 :         state_vec_60 = 3'h0;</span></a>
+<a name="5297"><span class="lineNum">    5297 </span><span class="lineCov">         12 :         state_vec_61 = 3'h0;</span></a>
+<a name="5298"><span class="lineNum">    5298 </span><span class="lineCov">         12 :         state_vec_62 = 3'h0;</span></a>
+<a name="5299"><span class="lineNum">    5299 </span><span class="lineCov">         12 :         state_vec_63 = 3'h0;</span></a>
+<a name="5300"><span class="lineNum">    5300 </span><span class="lineCov">         12 :         state_vec_64 = 3'h0;</span></a>
+<a name="5301"><span class="lineNum">    5301 </span><span class="lineCov">         12 :         state_vec_65 = 3'h0;</span></a>
+<a name="5302"><span class="lineNum">    5302 </span><span class="lineCov">         12 :         state_vec_66 = 3'h0;</span></a>
+<a name="5303"><span class="lineNum">    5303 </span><span class="lineCov">         12 :         state_vec_67 = 3'h0;</span></a>
+<a name="5304"><span class="lineNum">    5304 </span><span class="lineCov">         12 :         state_vec_68 = 3'h0;</span></a>
+<a name="5305"><span class="lineNum">    5305 </span><span class="lineCov">         12 :         state_vec_69 = 3'h0;</span></a>
+<a name="5306"><span class="lineNum">    5306 </span><span class="lineCov">         12 :         state_vec_70 = 3'h0;</span></a>
+<a name="5307"><span class="lineNum">    5307 </span><span class="lineCov">         12 :         state_vec_71 = 3'h0;</span></a>
+<a name="5308"><span class="lineNum">    5308 </span><span class="lineCov">         12 :         state_vec_72 = 3'h0;</span></a>
+<a name="5309"><span class="lineNum">    5309 </span><span class="lineCov">         12 :         state_vec_73 = 3'h0;</span></a>
+<a name="5310"><span class="lineNum">    5310 </span><span class="lineCov">         12 :         state_vec_74 = 3'h0;</span></a>
+<a name="5311"><span class="lineNum">    5311 </span><span class="lineCov">         12 :         state_vec_75 = 3'h0;</span></a>
+<a name="5312"><span class="lineNum">    5312 </span><span class="lineCov">         12 :         state_vec_76 = 3'h0;</span></a>
+<a name="5313"><span class="lineNum">    5313 </span><span class="lineCov">         12 :         state_vec_77 = 3'h0;</span></a>
+<a name="5314"><span class="lineNum">    5314 </span><span class="lineCov">         12 :         state_vec_78 = 3'h0;</span></a>
+<a name="5315"><span class="lineNum">    5315 </span><span class="lineCov">         12 :         state_vec_79 = 3'h0;</span></a>
+<a name="5316"><span class="lineNum">    5316 </span><span class="lineCov">         12 :         state_vec_80 = 3'h0;</span></a>
+<a name="5317"><span class="lineNum">    5317 </span><span class="lineCov">         12 :         state_vec_81 = 3'h0;</span></a>
+<a name="5318"><span class="lineNum">    5318 </span><span class="lineCov">         12 :         state_vec_82 = 3'h0;</span></a>
+<a name="5319"><span class="lineNum">    5319 </span><span class="lineCov">         12 :         state_vec_83 = 3'h0;</span></a>
+<a name="5320"><span class="lineNum">    5320 </span><span class="lineCov">         12 :         state_vec_84 = 3'h0;</span></a>
+<a name="5321"><span class="lineNum">    5321 </span><span class="lineCov">         12 :         state_vec_85 = 3'h0;</span></a>
+<a name="5322"><span class="lineNum">    5322 </span><span class="lineCov">         12 :         state_vec_86 = 3'h0;</span></a>
+<a name="5323"><span class="lineNum">    5323 </span><span class="lineCov">         12 :         state_vec_87 = 3'h0;</span></a>
+<a name="5324"><span class="lineNum">    5324 </span><span class="lineCov">         12 :         state_vec_88 = 3'h0;</span></a>
+<a name="5325"><span class="lineNum">    5325 </span><span class="lineCov">         12 :         state_vec_89 = 3'h0;</span></a>
+<a name="5326"><span class="lineNum">    5326 </span><span class="lineCov">         12 :         state_vec_90 = 3'h0;</span></a>
+<a name="5327"><span class="lineNum">    5327 </span><span class="lineCov">         12 :         state_vec_91 = 3'h0;</span></a>
+<a name="5328"><span class="lineNum">    5328 </span><span class="lineCov">         12 :         state_vec_92 = 3'h0;</span></a>
+<a name="5329"><span class="lineNum">    5329 </span><span class="lineCov">         12 :         state_vec_93 = 3'h0;</span></a>
+<a name="5330"><span class="lineNum">    5330 </span><span class="lineCov">         12 :         state_vec_94 = 3'h0;</span></a>
+<a name="5331"><span class="lineNum">    5331 </span><span class="lineCov">         12 :         state_vec_95 = 3'h0;</span></a>
+<a name="5332"><span class="lineNum">    5332 </span><span class="lineCov">         12 :         state_vec_96 = 3'h0;</span></a>
+<a name="5333"><span class="lineNum">    5333 </span><span class="lineCov">         12 :         state_vec_97 = 3'h0;</span></a>
+<a name="5334"><span class="lineNum">    5334 </span><span class="lineCov">         12 :         state_vec_98 = 3'h0;</span></a>
+<a name="5335"><span class="lineNum">    5335 </span><span class="lineCov">         12 :         state_vec_99 = 3'h0;</span></a>
+<a name="5336"><span class="lineNum">    5336 </span><span class="lineCov">         12 :         state_vec_100 = 3'h0;</span></a>
+<a name="5337"><span class="lineNum">    5337 </span><span class="lineCov">         12 :         state_vec_101 = 3'h0;</span></a>
+<a name="5338"><span class="lineNum">    5338 </span><span class="lineCov">         12 :         state_vec_102 = 3'h0;</span></a>
+<a name="5339"><span class="lineNum">    5339 </span><span class="lineCov">         12 :         state_vec_103 = 3'h0;</span></a>
+<a name="5340"><span class="lineNum">    5340 </span><span class="lineCov">         12 :         state_vec_104 = 3'h0;</span></a>
+<a name="5341"><span class="lineNum">    5341 </span><span class="lineCov">         12 :         state_vec_105 = 3'h0;</span></a>
+<a name="5342"><span class="lineNum">    5342 </span><span class="lineCov">         12 :         state_vec_106 = 3'h0;</span></a>
+<a name="5343"><span class="lineNum">    5343 </span><span class="lineCov">         12 :         state_vec_107 = 3'h0;</span></a>
+<a name="5344"><span class="lineNum">    5344 </span><span class="lineCov">         12 :         state_vec_108 = 3'h0;</span></a>
+<a name="5345"><span class="lineNum">    5345 </span><span class="lineCov">         12 :         state_vec_109 = 3'h0;</span></a>
+<a name="5346"><span class="lineNum">    5346 </span><span class="lineCov">         12 :         state_vec_110 = 3'h0;</span></a>
+<a name="5347"><span class="lineNum">    5347 </span><span class="lineCov">         12 :         state_vec_111 = 3'h0;</span></a>
+<a name="5348"><span class="lineNum">    5348 </span><span class="lineCov">         12 :         state_vec_112 = 3'h0;</span></a>
+<a name="5349"><span class="lineNum">    5349 </span><span class="lineCov">         12 :         state_vec_113 = 3'h0;</span></a>
+<a name="5350"><span class="lineNum">    5350 </span><span class="lineCov">         12 :         state_vec_114 = 3'h0;</span></a>
+<a name="5351"><span class="lineNum">    5351 </span><span class="lineCov">         12 :         state_vec_115 = 3'h0;</span></a>
+<a name="5352"><span class="lineNum">    5352 </span><span class="lineCov">         12 :         state_vec_116 = 3'h0;</span></a>
+<a name="5353"><span class="lineNum">    5353 </span><span class="lineCov">         12 :         state_vec_117 = 3'h0;</span></a>
+<a name="5354"><span class="lineNum">    5354 </span><span class="lineCov">         12 :         state_vec_118 = 3'h0;</span></a>
+<a name="5355"><span class="lineNum">    5355 </span><span class="lineCov">         12 :         state_vec_119 = 3'h0;</span></a>
+<a name="5356"><span class="lineNum">    5356 </span><span class="lineCov">         12 :         state_vec_120 = 3'h0;</span></a>
+<a name="5357"><span class="lineNum">    5357 </span><span class="lineCov">         12 :         state_vec_121 = 3'h0;</span></a>
+<a name="5358"><span class="lineNum">    5358 </span><span class="lineCov">         12 :         state_vec_122 = 3'h0;</span></a>
+<a name="5359"><span class="lineNum">    5359 </span><span class="lineCov">         12 :         state_vec_123 = 3'h0;</span></a>
+<a name="5360"><span class="lineNum">    5360 </span><span class="lineCov">         12 :         state_vec_124 = 3'h0;</span></a>
+<a name="5361"><span class="lineNum">    5361 </span><span class="lineCov">         12 :         state_vec_125 = 3'h0;</span></a>
+<a name="5362"><span class="lineNum">    5362 </span><span class="lineCov">         12 :         state_vec_126 = 3'h0;</span></a>
+<a name="5363"><span class="lineNum">    5363 </span><span class="lineCov">         12 :         state_vec_127 = 3'h0;</span></a>
+<a name="5364"><span class="lineNum">    5364 </span><span class="lineCov">         12 :         state_vec_128 = 3'h0;</span></a>
+<a name="5365"><span class="lineNum">    5365 </span><span class="lineCov">         12 :         state_vec_129 = 3'h0;</span></a>
+<a name="5366"><span class="lineNum">    5366 </span><span class="lineCov">         12 :         state_vec_130 = 3'h0;</span></a>
+<a name="5367"><span class="lineNum">    5367 </span><span class="lineCov">         12 :         state_vec_131 = 3'h0;</span></a>
+<a name="5368"><span class="lineNum">    5368 </span><span class="lineCov">         12 :         state_vec_132 = 3'h0;</span></a>
+<a name="5369"><span class="lineNum">    5369 </span><span class="lineCov">         12 :         state_vec_133 = 3'h0;</span></a>
+<a name="5370"><span class="lineNum">    5370 </span><span class="lineCov">         12 :         state_vec_134 = 3'h0;</span></a>
+<a name="5371"><span class="lineNum">    5371 </span><span class="lineCov">         12 :         state_vec_135 = 3'h0;</span></a>
+<a name="5372"><span class="lineNum">    5372 </span><span class="lineCov">         12 :         state_vec_136 = 3'h0;</span></a>
+<a name="5373"><span class="lineNum">    5373 </span><span class="lineCov">         12 :         state_vec_137 = 3'h0;</span></a>
+<a name="5374"><span class="lineNum">    5374 </span><span class="lineCov">         12 :         state_vec_138 = 3'h0;</span></a>
+<a name="5375"><span class="lineNum">    5375 </span><span class="lineCov">         12 :         state_vec_139 = 3'h0;</span></a>
+<a name="5376"><span class="lineNum">    5376 </span><span class="lineCov">         12 :         state_vec_140 = 3'h0;</span></a>
+<a name="5377"><span class="lineNum">    5377 </span><span class="lineCov">         12 :         state_vec_141 = 3'h0;</span></a>
+<a name="5378"><span class="lineNum">    5378 </span><span class="lineCov">         12 :         state_vec_142 = 3'h0;</span></a>
+<a name="5379"><span class="lineNum">    5379 </span><span class="lineCov">         12 :         state_vec_143 = 3'h0;</span></a>
+<a name="5380"><span class="lineNum">    5380 </span><span class="lineCov">         12 :         state_vec_144 = 3'h0;</span></a>
+<a name="5381"><span class="lineNum">    5381 </span><span class="lineCov">         12 :         state_vec_145 = 3'h0;</span></a>
+<a name="5382"><span class="lineNum">    5382 </span><span class="lineCov">         12 :         state_vec_146 = 3'h0;</span></a>
+<a name="5383"><span class="lineNum">    5383 </span><span class="lineCov">         12 :         state_vec_147 = 3'h0;</span></a>
+<a name="5384"><span class="lineNum">    5384 </span><span class="lineCov">         12 :         state_vec_148 = 3'h0;</span></a>
+<a name="5385"><span class="lineNum">    5385 </span><span class="lineCov">         12 :         state_vec_149 = 3'h0;</span></a>
+<a name="5386"><span class="lineNum">    5386 </span><span class="lineCov">         12 :         state_vec_150 = 3'h0;</span></a>
+<a name="5387"><span class="lineNum">    5387 </span><span class="lineCov">         12 :         state_vec_151 = 3'h0;</span></a>
+<a name="5388"><span class="lineNum">    5388 </span><span class="lineCov">         12 :         state_vec_152 = 3'h0;</span></a>
+<a name="5389"><span class="lineNum">    5389 </span><span class="lineCov">         12 :         state_vec_153 = 3'h0;</span></a>
+<a name="5390"><span class="lineNum">    5390 </span><span class="lineCov">         12 :         state_vec_154 = 3'h0;</span></a>
+<a name="5391"><span class="lineNum">    5391 </span><span class="lineCov">         12 :         state_vec_155 = 3'h0;</span></a>
+<a name="5392"><span class="lineNum">    5392 </span><span class="lineCov">         12 :         state_vec_156 = 3'h0;</span></a>
+<a name="5393"><span class="lineNum">    5393 </span><span class="lineCov">         12 :         state_vec_157 = 3'h0;</span></a>
+<a name="5394"><span class="lineNum">    5394 </span><span class="lineCov">         12 :         state_vec_158 = 3'h0;</span></a>
+<a name="5395"><span class="lineNum">    5395 </span><span class="lineCov">         12 :         state_vec_159 = 3'h0;</span></a>
+<a name="5396"><span class="lineNum">    5396 </span><span class="lineCov">         12 :         state_vec_160 = 3'h0;</span></a>
+<a name="5397"><span class="lineNum">    5397 </span><span class="lineCov">         12 :         state_vec_161 = 3'h0;</span></a>
+<a name="5398"><span class="lineNum">    5398 </span><span class="lineCov">         12 :         state_vec_162 = 3'h0;</span></a>
+<a name="5399"><span class="lineNum">    5399 </span><span class="lineCov">         12 :         state_vec_163 = 3'h0;</span></a>
+<a name="5400"><span class="lineNum">    5400 </span><span class="lineCov">         12 :         state_vec_164 = 3'h0;</span></a>
+<a name="5401"><span class="lineNum">    5401 </span><span class="lineCov">         12 :         state_vec_165 = 3'h0;</span></a>
+<a name="5402"><span class="lineNum">    5402 </span><span class="lineCov">         12 :         state_vec_166 = 3'h0;</span></a>
+<a name="5403"><span class="lineNum">    5403 </span><span class="lineCov">         12 :         state_vec_167 = 3'h0;</span></a>
+<a name="5404"><span class="lineNum">    5404 </span><span class="lineCov">         12 :         state_vec_168 = 3'h0;</span></a>
+<a name="5405"><span class="lineNum">    5405 </span><span class="lineCov">         12 :         state_vec_169 = 3'h0;</span></a>
+<a name="5406"><span class="lineNum">    5406 </span><span class="lineCov">         12 :         state_vec_170 = 3'h0;</span></a>
+<a name="5407"><span class="lineNum">    5407 </span><span class="lineCov">         12 :         state_vec_171 = 3'h0;</span></a>
+<a name="5408"><span class="lineNum">    5408 </span><span class="lineCov">         12 :         state_vec_172 = 3'h0;</span></a>
+<a name="5409"><span class="lineNum">    5409 </span><span class="lineCov">         12 :         state_vec_173 = 3'h0;</span></a>
+<a name="5410"><span class="lineNum">    5410 </span><span class="lineCov">         12 :         state_vec_174 = 3'h0;</span></a>
+<a name="5411"><span class="lineNum">    5411 </span><span class="lineCov">         12 :         state_vec_175 = 3'h0;</span></a>
+<a name="5412"><span class="lineNum">    5412 </span><span class="lineCov">         12 :         state_vec_176 = 3'h0;</span></a>
+<a name="5413"><span class="lineNum">    5413 </span><span class="lineCov">         12 :         state_vec_177 = 3'h0;</span></a>
+<a name="5414"><span class="lineNum">    5414 </span><span class="lineCov">         12 :         state_vec_178 = 3'h0;</span></a>
+<a name="5415"><span class="lineNum">    5415 </span><span class="lineCov">         12 :         state_vec_179 = 3'h0;</span></a>
+<a name="5416"><span class="lineNum">    5416 </span><span class="lineCov">         12 :         state_vec_180 = 3'h0;</span></a>
+<a name="5417"><span class="lineNum">    5417 </span><span class="lineCov">         12 :         state_vec_181 = 3'h0;</span></a>
+<a name="5418"><span class="lineNum">    5418 </span><span class="lineCov">         12 :         state_vec_182 = 3'h0;</span></a>
+<a name="5419"><span class="lineNum">    5419 </span><span class="lineCov">         12 :         state_vec_183 = 3'h0;</span></a>
+<a name="5420"><span class="lineNum">    5420 </span><span class="lineCov">         12 :         state_vec_184 = 3'h0;</span></a>
+<a name="5421"><span class="lineNum">    5421 </span><span class="lineCov">         12 :         state_vec_185 = 3'h0;</span></a>
+<a name="5422"><span class="lineNum">    5422 </span><span class="lineCov">         12 :         state_vec_186 = 3'h0;</span></a>
+<a name="5423"><span class="lineNum">    5423 </span><span class="lineCov">         12 :         state_vec_187 = 3'h0;</span></a>
+<a name="5424"><span class="lineNum">    5424 </span><span class="lineCov">         12 :         state_vec_188 = 3'h0;</span></a>
+<a name="5425"><span class="lineNum">    5425 </span><span class="lineCov">         12 :         state_vec_189 = 3'h0;</span></a>
+<a name="5426"><span class="lineNum">    5426 </span><span class="lineCov">         12 :         state_vec_190 = 3'h0;</span></a>
+<a name="5427"><span class="lineNum">    5427 </span><span class="lineCov">         12 :         state_vec_191 = 3'h0;</span></a>
+<a name="5428"><span class="lineNum">    5428 </span><span class="lineCov">         12 :         state_vec_192 = 3'h0;</span></a>
+<a name="5429"><span class="lineNum">    5429 </span><span class="lineCov">         12 :         state_vec_193 = 3'h0;</span></a>
+<a name="5430"><span class="lineNum">    5430 </span><span class="lineCov">         12 :         state_vec_194 = 3'h0;</span></a>
+<a name="5431"><span class="lineNum">    5431 </span><span class="lineCov">         12 :         state_vec_195 = 3'h0;</span></a>
+<a name="5432"><span class="lineNum">    5432 </span><span class="lineCov">         12 :         state_vec_196 = 3'h0;</span></a>
+<a name="5433"><span class="lineNum">    5433 </span><span class="lineCov">         12 :         state_vec_197 = 3'h0;</span></a>
+<a name="5434"><span class="lineNum">    5434 </span><span class="lineCov">         12 :         state_vec_198 = 3'h0;</span></a>
+<a name="5435"><span class="lineNum">    5435 </span><span class="lineCov">         12 :         state_vec_199 = 3'h0;</span></a>
+<a name="5436"><span class="lineNum">    5436 </span><span class="lineCov">         12 :         state_vec_200 = 3'h0;</span></a>
+<a name="5437"><span class="lineNum">    5437 </span><span class="lineCov">         12 :         state_vec_201 = 3'h0;</span></a>
+<a name="5438"><span class="lineNum">    5438 </span><span class="lineCov">         12 :         state_vec_202 = 3'h0;</span></a>
+<a name="5439"><span class="lineNum">    5439 </span><span class="lineCov">         12 :         state_vec_203 = 3'h0;</span></a>
+<a name="5440"><span class="lineNum">    5440 </span><span class="lineCov">         12 :         state_vec_204 = 3'h0;</span></a>
+<a name="5441"><span class="lineNum">    5441 </span><span class="lineCov">         12 :         state_vec_205 = 3'h0;</span></a>
+<a name="5442"><span class="lineNum">    5442 </span><span class="lineCov">         12 :         state_vec_206 = 3'h0;</span></a>
+<a name="5443"><span class="lineNum">    5443 </span><span class="lineCov">         12 :         state_vec_207 = 3'h0;</span></a>
+<a name="5444"><span class="lineNum">    5444 </span><span class="lineCov">         12 :         state_vec_208 = 3'h0;</span></a>
+<a name="5445"><span class="lineNum">    5445 </span><span class="lineCov">         12 :         state_vec_209 = 3'h0;</span></a>
+<a name="5446"><span class="lineNum">    5446 </span><span class="lineCov">         12 :         state_vec_210 = 3'h0;</span></a>
+<a name="5447"><span class="lineNum">    5447 </span><span class="lineCov">         12 :         state_vec_211 = 3'h0;</span></a>
+<a name="5448"><span class="lineNum">    5448 </span><span class="lineCov">         12 :         state_vec_212 = 3'h0;</span></a>
+<a name="5449"><span class="lineNum">    5449 </span><span class="lineCov">         12 :         state_vec_213 = 3'h0;</span></a>
+<a name="5450"><span class="lineNum">    5450 </span><span class="lineCov">         12 :         state_vec_214 = 3'h0;</span></a>
+<a name="5451"><span class="lineNum">    5451 </span><span class="lineCov">         12 :         state_vec_215 = 3'h0;</span></a>
+<a name="5452"><span class="lineNum">    5452 </span><span class="lineCov">         12 :         state_vec_216 = 3'h0;</span></a>
+<a name="5453"><span class="lineNum">    5453 </span><span class="lineCov">         12 :         state_vec_217 = 3'h0;</span></a>
+<a name="5454"><span class="lineNum">    5454 </span><span class="lineCov">         12 :         state_vec_218 = 3'h0;</span></a>
+<a name="5455"><span class="lineNum">    5455 </span><span class="lineCov">         12 :         state_vec_219 = 3'h0;</span></a>
+<a name="5456"><span class="lineNum">    5456 </span><span class="lineCov">         12 :         state_vec_220 = 3'h0;</span></a>
+<a name="5457"><span class="lineNum">    5457 </span><span class="lineCov">         12 :         state_vec_221 = 3'h0;</span></a>
+<a name="5458"><span class="lineNum">    5458 </span><span class="lineCov">         12 :         state_vec_222 = 3'h0;</span></a>
+<a name="5459"><span class="lineNum">    5459 </span><span class="lineCov">         12 :         state_vec_223 = 3'h0;</span></a>
+<a name="5460"><span class="lineNum">    5460 </span><span class="lineCov">         12 :         state_vec_224 = 3'h0;</span></a>
+<a name="5461"><span class="lineNum">    5461 </span><span class="lineCov">         12 :         state_vec_225 = 3'h0;</span></a>
+<a name="5462"><span class="lineNum">    5462 </span><span class="lineCov">         12 :         state_vec_226 = 3'h0;</span></a>
+<a name="5463"><span class="lineNum">    5463 </span><span class="lineCov">         12 :         state_vec_227 = 3'h0;</span></a>
+<a name="5464"><span class="lineNum">    5464 </span><span class="lineCov">         12 :         state_vec_228 = 3'h0;</span></a>
+<a name="5465"><span class="lineNum">    5465 </span><span class="lineCov">         12 :         state_vec_229 = 3'h0;</span></a>
+<a name="5466"><span class="lineNum">    5466 </span><span class="lineCov">         12 :         state_vec_230 = 3'h0;</span></a>
+<a name="5467"><span class="lineNum">    5467 </span><span class="lineCov">         12 :         state_vec_231 = 3'h0;</span></a>
+<a name="5468"><span class="lineNum">    5468 </span><span class="lineCov">         12 :         state_vec_232 = 3'h0;</span></a>
+<a name="5469"><span class="lineNum">    5469 </span><span class="lineCov">         12 :         state_vec_233 = 3'h0;</span></a>
+<a name="5470"><span class="lineNum">    5470 </span><span class="lineCov">         12 :         state_vec_234 = 3'h0;</span></a>
+<a name="5471"><span class="lineNum">    5471 </span><span class="lineCov">         12 :         state_vec_235 = 3'h0;</span></a>
+<a name="5472"><span class="lineNum">    5472 </span><span class="lineCov">         12 :         state_vec_236 = 3'h0;</span></a>
+<a name="5473"><span class="lineNum">    5473 </span><span class="lineCov">         12 :         state_vec_237 = 3'h0;</span></a>
+<a name="5474"><span class="lineNum">    5474 </span><span class="lineCov">         12 :         state_vec_238 = 3'h0;</span></a>
+<a name="5475"><span class="lineNum">    5475 </span><span class="lineCov">         12 :         state_vec_239 = 3'h0;</span></a>
+<a name="5476"><span class="lineNum">    5476 </span><span class="lineCov">         12 :         state_vec_240 = 3'h0;</span></a>
+<a name="5477"><span class="lineNum">    5477 </span><span class="lineCov">         12 :         state_vec_241 = 3'h0;</span></a>
+<a name="5478"><span class="lineNum">    5478 </span><span class="lineCov">         12 :         state_vec_242 = 3'h0;</span></a>
+<a name="5479"><span class="lineNum">    5479 </span><span class="lineCov">         12 :         state_vec_243 = 3'h0;</span></a>
+<a name="5480"><span class="lineNum">    5480 </span><span class="lineCov">         12 :         state_vec_244 = 3'h0;</span></a>
+<a name="5481"><span class="lineNum">    5481 </span><span class="lineCov">         12 :         state_vec_245 = 3'h0;</span></a>
+<a name="5482"><span class="lineNum">    5482 </span><span class="lineCov">         12 :         state_vec_246 = 3'h0;</span></a>
+<a name="5483"><span class="lineNum">    5483 </span><span class="lineCov">         12 :         state_vec_247 = 3'h0;</span></a>
+<a name="5484"><span class="lineNum">    5484 </span><span class="lineCov">         12 :         state_vec_248 = 3'h0;</span></a>
+<a name="5485"><span class="lineNum">    5485 </span><span class="lineCov">         12 :         state_vec_249 = 3'h0;</span></a>
+<a name="5486"><span class="lineNum">    5486 </span><span class="lineCov">         12 :         state_vec_250 = 3'h0;</span></a>
+<a name="5487"><span class="lineNum">    5487 </span><span class="lineCov">         12 :         state_vec_251 = 3'h0;</span></a>
+<a name="5488"><span class="lineNum">    5488 </span><span class="lineCov">         12 :         state_vec_252 = 3'h0;</span></a>
+<a name="5489"><span class="lineNum">    5489 </span><span class="lineCov">         12 :         state_vec_253 = 3'h0;</span></a>
+<a name="5490"><span class="lineNum">    5490 </span><span class="lineCov">         12 :         state_vec_254 = 3'h0;</span></a>
+<a name="5491"><span class="lineNum">    5491 </span><span class="lineCov">         12 :         state_vec_255 = 3'h0;</span></a>
+<a name="5492"><span class="lineNum">    5492 </span><span class="lineCov">         12 :         state_vec_256 = 3'h0;</span></a>
+<a name="5493"><span class="lineNum">    5493 </span><span class="lineCov">         12 :         state_vec_257 = 3'h0;</span></a>
+<a name="5494"><span class="lineNum">    5494 </span><span class="lineCov">         12 :         state_vec_258 = 3'h0;</span></a>
+<a name="5495"><span class="lineNum">    5495 </span><span class="lineCov">         12 :         state_vec_259 = 3'h0;</span></a>
+<a name="5496"><span class="lineNum">    5496 </span><span class="lineCov">         12 :         state_vec_260 = 3'h0;</span></a>
+<a name="5497"><span class="lineNum">    5497 </span><span class="lineCov">         12 :         state_vec_261 = 3'h0;</span></a>
+<a name="5498"><span class="lineNum">    5498 </span><span class="lineCov">         12 :         state_vec_262 = 3'h0;</span></a>
+<a name="5499"><span class="lineNum">    5499 </span><span class="lineCov">         12 :         state_vec_263 = 3'h0;</span></a>
+<a name="5500"><span class="lineNum">    5500 </span><span class="lineCov">         12 :         state_vec_264 = 3'h0;</span></a>
+<a name="5501"><span class="lineNum">    5501 </span><span class="lineCov">         12 :         state_vec_265 = 3'h0;</span></a>
+<a name="5502"><span class="lineNum">    5502 </span><span class="lineCov">         12 :         state_vec_266 = 3'h0;</span></a>
+<a name="5503"><span class="lineNum">    5503 </span><span class="lineCov">         12 :         state_vec_267 = 3'h0;</span></a>
+<a name="5504"><span class="lineNum">    5504 </span><span class="lineCov">         12 :         state_vec_268 = 3'h0;</span></a>
+<a name="5505"><span class="lineNum">    5505 </span><span class="lineCov">         12 :         state_vec_269 = 3'h0;</span></a>
+<a name="5506"><span class="lineNum">    5506 </span><span class="lineCov">         12 :         state_vec_270 = 3'h0;</span></a>
+<a name="5507"><span class="lineNum">    5507 </span><span class="lineCov">         12 :         state_vec_271 = 3'h0;</span></a>
+<a name="5508"><span class="lineNum">    5508 </span><span class="lineCov">         12 :         state_vec_272 = 3'h0;</span></a>
+<a name="5509"><span class="lineNum">    5509 </span><span class="lineCov">         12 :         state_vec_273 = 3'h0;</span></a>
+<a name="5510"><span class="lineNum">    5510 </span><span class="lineCov">         12 :         state_vec_274 = 3'h0;</span></a>
+<a name="5511"><span class="lineNum">    5511 </span><span class="lineCov">         12 :         state_vec_275 = 3'h0;</span></a>
+<a name="5512"><span class="lineNum">    5512 </span><span class="lineCov">         12 :         state_vec_276 = 3'h0;</span></a>
+<a name="5513"><span class="lineNum">    5513 </span><span class="lineCov">         12 :         state_vec_277 = 3'h0;</span></a>
+<a name="5514"><span class="lineNum">    5514 </span><span class="lineCov">         12 :         state_vec_278 = 3'h0;</span></a>
+<a name="5515"><span class="lineNum">    5515 </span><span class="lineCov">         12 :         state_vec_279 = 3'h0;</span></a>
+<a name="5516"><span class="lineNum">    5516 </span><span class="lineCov">         12 :         state_vec_280 = 3'h0;</span></a>
+<a name="5517"><span class="lineNum">    5517 </span><span class="lineCov">         12 :         state_vec_281 = 3'h0;</span></a>
+<a name="5518"><span class="lineNum">    5518 </span><span class="lineCov">         12 :         state_vec_282 = 3'h0;</span></a>
+<a name="5519"><span class="lineNum">    5519 </span><span class="lineCov">         12 :         state_vec_283 = 3'h0;</span></a>
+<a name="5520"><span class="lineNum">    5520 </span><span class="lineCov">         12 :         state_vec_284 = 3'h0;</span></a>
+<a name="5521"><span class="lineNum">    5521 </span><span class="lineCov">         12 :         state_vec_285 = 3'h0;</span></a>
+<a name="5522"><span class="lineNum">    5522 </span><span class="lineCov">         12 :         state_vec_286 = 3'h0;</span></a>
+<a name="5523"><span class="lineNum">    5523 </span><span class="lineCov">         12 :         state_vec_287 = 3'h0;</span></a>
+<a name="5524"><span class="lineNum">    5524 </span><span class="lineCov">         12 :         state_vec_288 = 3'h0;</span></a>
+<a name="5525"><span class="lineNum">    5525 </span><span class="lineCov">         12 :         state_vec_289 = 3'h0;</span></a>
+<a name="5526"><span class="lineNum">    5526 </span><span class="lineCov">         12 :         state_vec_290 = 3'h0;</span></a>
+<a name="5527"><span class="lineNum">    5527 </span><span class="lineCov">         12 :         state_vec_291 = 3'h0;</span></a>
+<a name="5528"><span class="lineNum">    5528 </span><span class="lineCov">         12 :         state_vec_292 = 3'h0;</span></a>
+<a name="5529"><span class="lineNum">    5529 </span><span class="lineCov">         12 :         state_vec_293 = 3'h0;</span></a>
+<a name="5530"><span class="lineNum">    5530 </span><span class="lineCov">         12 :         state_vec_294 = 3'h0;</span></a>
+<a name="5531"><span class="lineNum">    5531 </span><span class="lineCov">         12 :         state_vec_295 = 3'h0;</span></a>
+<a name="5532"><span class="lineNum">    5532 </span><span class="lineCov">         12 :         state_vec_296 = 3'h0;</span></a>
+<a name="5533"><span class="lineNum">    5533 </span><span class="lineCov">         12 :         state_vec_297 = 3'h0;</span></a>
+<a name="5534"><span class="lineNum">    5534 </span><span class="lineCov">         12 :         state_vec_298 = 3'h0;</span></a>
+<a name="5535"><span class="lineNum">    5535 </span><span class="lineCov">         12 :         state_vec_299 = 3'h0;</span></a>
+<a name="5536"><span class="lineNum">    5536 </span><span class="lineCov">         12 :         state_vec_300 = 3'h0;</span></a>
+<a name="5537"><span class="lineNum">    5537 </span><span class="lineCov">         12 :         state_vec_301 = 3'h0;</span></a>
+<a name="5538"><span class="lineNum">    5538 </span><span class="lineCov">         12 :         state_vec_302 = 3'h0;</span></a>
+<a name="5539"><span class="lineNum">    5539 </span><span class="lineCov">         12 :         state_vec_303 = 3'h0;</span></a>
+<a name="5540"><span class="lineNum">    5540 </span><span class="lineCov">         12 :         state_vec_304 = 3'h0;</span></a>
+<a name="5541"><span class="lineNum">    5541 </span><span class="lineCov">         12 :         state_vec_305 = 3'h0;</span></a>
+<a name="5542"><span class="lineNum">    5542 </span><span class="lineCov">         12 :         state_vec_306 = 3'h0;</span></a>
+<a name="5543"><span class="lineNum">    5543 </span><span class="lineCov">         12 :         state_vec_307 = 3'h0;</span></a>
+<a name="5544"><span class="lineNum">    5544 </span><span class="lineCov">         12 :         state_vec_308 = 3'h0;</span></a>
+<a name="5545"><span class="lineNum">    5545 </span><span class="lineCov">         12 :         state_vec_309 = 3'h0;</span></a>
+<a name="5546"><span class="lineNum">    5546 </span><span class="lineCov">         12 :         state_vec_310 = 3'h0;</span></a>
+<a name="5547"><span class="lineNum">    5547 </span><span class="lineCov">         12 :         state_vec_311 = 3'h0;</span></a>
+<a name="5548"><span class="lineNum">    5548 </span><span class="lineCov">         12 :         state_vec_312 = 3'h0;</span></a>
+<a name="5549"><span class="lineNum">    5549 </span><span class="lineCov">         12 :         state_vec_313 = 3'h0;</span></a>
+<a name="5550"><span class="lineNum">    5550 </span><span class="lineCov">         12 :         state_vec_314 = 3'h0;</span></a>
+<a name="5551"><span class="lineNum">    5551 </span><span class="lineCov">         12 :         state_vec_315 = 3'h0;</span></a>
+<a name="5552"><span class="lineNum">    5552 </span><span class="lineCov">         12 :         state_vec_316 = 3'h0;</span></a>
+<a name="5553"><span class="lineNum">    5553 </span><span class="lineCov">         12 :         state_vec_317 = 3'h0;</span></a>
+<a name="5554"><span class="lineNum">    5554 </span><span class="lineCov">         12 :         state_vec_318 = 3'h0;</span></a>
+<a name="5555"><span class="lineNum">    5555 </span><span class="lineCov">         12 :         state_vec_319 = 3'h0;</span></a>
+<a name="5556"><span class="lineNum">    5556 </span><span class="lineCov">         12 :         state_vec_320 = 3'h0;</span></a>
+<a name="5557"><span class="lineNum">    5557 </span><span class="lineCov">         12 :         state_vec_321 = 3'h0;</span></a>
+<a name="5558"><span class="lineNum">    5558 </span><span class="lineCov">         12 :         state_vec_322 = 3'h0;</span></a>
+<a name="5559"><span class="lineNum">    5559 </span><span class="lineCov">         12 :         state_vec_323 = 3'h0;</span></a>
+<a name="5560"><span class="lineNum">    5560 </span><span class="lineCov">         12 :         state_vec_324 = 3'h0;</span></a>
+<a name="5561"><span class="lineNum">    5561 </span><span class="lineCov">         12 :         state_vec_325 = 3'h0;</span></a>
+<a name="5562"><span class="lineNum">    5562 </span><span class="lineCov">         12 :         state_vec_326 = 3'h0;</span></a>
+<a name="5563"><span class="lineNum">    5563 </span><span class="lineCov">         12 :         state_vec_327 = 3'h0;</span></a>
+<a name="5564"><span class="lineNum">    5564 </span><span class="lineCov">         12 :         state_vec_328 = 3'h0;</span></a>
+<a name="5565"><span class="lineNum">    5565 </span><span class="lineCov">         12 :         state_vec_329 = 3'h0;</span></a>
+<a name="5566"><span class="lineNum">    5566 </span><span class="lineCov">         12 :         state_vec_330 = 3'h0;</span></a>
+<a name="5567"><span class="lineNum">    5567 </span><span class="lineCov">         12 :         state_vec_331 = 3'h0;</span></a>
+<a name="5568"><span class="lineNum">    5568 </span><span class="lineCov">         12 :         state_vec_332 = 3'h0;</span></a>
+<a name="5569"><span class="lineNum">    5569 </span><span class="lineCov">         12 :         state_vec_333 = 3'h0;</span></a>
+<a name="5570"><span class="lineNum">    5570 </span><span class="lineCov">         12 :         state_vec_334 = 3'h0;</span></a>
+<a name="5571"><span class="lineNum">    5571 </span><span class="lineCov">         12 :         state_vec_335 = 3'h0;</span></a>
+<a name="5572"><span class="lineNum">    5572 </span><span class="lineCov">         12 :         state_vec_336 = 3'h0;</span></a>
+<a name="5573"><span class="lineNum">    5573 </span><span class="lineCov">         12 :         state_vec_337 = 3'h0;</span></a>
+<a name="5574"><span class="lineNum">    5574 </span><span class="lineCov">         12 :         state_vec_338 = 3'h0;</span></a>
+<a name="5575"><span class="lineNum">    5575 </span><span class="lineCov">         12 :         state_vec_339 = 3'h0;</span></a>
+<a name="5576"><span class="lineNum">    5576 </span><span class="lineCov">         12 :         state_vec_340 = 3'h0;</span></a>
+<a name="5577"><span class="lineNum">    5577 </span><span class="lineCov">         12 :         state_vec_341 = 3'h0;</span></a>
+<a name="5578"><span class="lineNum">    5578 </span><span class="lineCov">         12 :         state_vec_342 = 3'h0;</span></a>
+<a name="5579"><span class="lineNum">    5579 </span><span class="lineCov">         12 :         state_vec_343 = 3'h0;</span></a>
+<a name="5580"><span class="lineNum">    5580 </span><span class="lineCov">         12 :         state_vec_344 = 3'h0;</span></a>
+<a name="5581"><span class="lineNum">    5581 </span><span class="lineCov">         12 :         state_vec_345 = 3'h0;</span></a>
+<a name="5582"><span class="lineNum">    5582 </span><span class="lineCov">         12 :         state_vec_346 = 3'h0;</span></a>
+<a name="5583"><span class="lineNum">    5583 </span><span class="lineCov">         12 :         state_vec_347 = 3'h0;</span></a>
+<a name="5584"><span class="lineNum">    5584 </span><span class="lineCov">         12 :         state_vec_348 = 3'h0;</span></a>
+<a name="5585"><span class="lineNum">    5585 </span><span class="lineCov">         12 :         state_vec_349 = 3'h0;</span></a>
+<a name="5586"><span class="lineNum">    5586 </span><span class="lineCov">         12 :         state_vec_350 = 3'h0;</span></a>
+<a name="5587"><span class="lineNum">    5587 </span><span class="lineCov">         12 :         state_vec_351 = 3'h0;</span></a>
+<a name="5588"><span class="lineNum">    5588 </span><span class="lineCov">         12 :         state_vec_352 = 3'h0;</span></a>
+<a name="5589"><span class="lineNum">    5589 </span><span class="lineCov">         12 :         state_vec_353 = 3'h0;</span></a>
+<a name="5590"><span class="lineNum">    5590 </span><span class="lineCov">         12 :         state_vec_354 = 3'h0;</span></a>
+<a name="5591"><span class="lineNum">    5591 </span><span class="lineCov">         12 :         state_vec_355 = 3'h0;</span></a>
+<a name="5592"><span class="lineNum">    5592 </span><span class="lineCov">         12 :         state_vec_356 = 3'h0;</span></a>
+<a name="5593"><span class="lineNum">    5593 </span><span class="lineCov">         12 :         state_vec_357 = 3'h0;</span></a>
+<a name="5594"><span class="lineNum">    5594 </span><span class="lineCov">         12 :         state_vec_358 = 3'h0;</span></a>
+<a name="5595"><span class="lineNum">    5595 </span><span class="lineCov">         12 :         state_vec_359 = 3'h0;</span></a>
+<a name="5596"><span class="lineNum">    5596 </span><span class="lineCov">         12 :         state_vec_360 = 3'h0;</span></a>
+<a name="5597"><span class="lineNum">    5597 </span><span class="lineCov">         12 :         state_vec_361 = 3'h0;</span></a>
+<a name="5598"><span class="lineNum">    5598 </span><span class="lineCov">         12 :         state_vec_362 = 3'h0;</span></a>
+<a name="5599"><span class="lineNum">    5599 </span><span class="lineCov">         12 :         state_vec_363 = 3'h0;</span></a>
+<a name="5600"><span class="lineNum">    5600 </span><span class="lineCov">         12 :         state_vec_364 = 3'h0;</span></a>
+<a name="5601"><span class="lineNum">    5601 </span><span class="lineCov">         12 :         state_vec_365 = 3'h0;</span></a>
+<a name="5602"><span class="lineNum">    5602 </span><span class="lineCov">         12 :         state_vec_366 = 3'h0;</span></a>
+<a name="5603"><span class="lineNum">    5603 </span><span class="lineCov">         12 :         state_vec_367 = 3'h0;</span></a>
+<a name="5604"><span class="lineNum">    5604 </span><span class="lineCov">         12 :         state_vec_368 = 3'h0;</span></a>
+<a name="5605"><span class="lineNum">    5605 </span><span class="lineCov">         12 :         state_vec_369 = 3'h0;</span></a>
+<a name="5606"><span class="lineNum">    5606 </span><span class="lineCov">         12 :         state_vec_370 = 3'h0;</span></a>
+<a name="5607"><span class="lineNum">    5607 </span><span class="lineCov">         12 :         state_vec_371 = 3'h0;</span></a>
+<a name="5608"><span class="lineNum">    5608 </span><span class="lineCov">         12 :         state_vec_372 = 3'h0;</span></a>
+<a name="5609"><span class="lineNum">    5609 </span><span class="lineCov">         12 :         state_vec_373 = 3'h0;</span></a>
+<a name="5610"><span class="lineNum">    5610 </span><span class="lineCov">         12 :         state_vec_374 = 3'h0;</span></a>
+<a name="5611"><span class="lineNum">    5611 </span><span class="lineCov">         12 :         state_vec_375 = 3'h0;</span></a>
+<a name="5612"><span class="lineNum">    5612 </span><span class="lineCov">         12 :         state_vec_376 = 3'h0;</span></a>
+<a name="5613"><span class="lineNum">    5613 </span><span class="lineCov">         12 :         state_vec_377 = 3'h0;</span></a>
+<a name="5614"><span class="lineNum">    5614 </span><span class="lineCov">         12 :         state_vec_378 = 3'h0;</span></a>
+<a name="5615"><span class="lineNum">    5615 </span><span class="lineCov">         12 :         state_vec_379 = 3'h0;</span></a>
+<a name="5616"><span class="lineNum">    5616 </span><span class="lineCov">         12 :         state_vec_380 = 3'h0;</span></a>
+<a name="5617"><span class="lineNum">    5617 </span><span class="lineCov">         12 :         state_vec_381 = 3'h0;</span></a>
+<a name="5618"><span class="lineNum">    5618 </span><span class="lineCov">         12 :         state_vec_382 = 3'h0;</span></a>
+<a name="5619"><span class="lineNum">    5619 </span><span class="lineCov">         12 :         state_vec_383 = 3'h0;</span></a>
+<a name="5620"><span class="lineNum">    5620 </span><span class="lineCov">         12 :         state_vec_384 = 3'h0;</span></a>
+<a name="5621"><span class="lineNum">    5621 </span><span class="lineCov">         12 :         state_vec_385 = 3'h0;</span></a>
+<a name="5622"><span class="lineNum">    5622 </span><span class="lineCov">         12 :         state_vec_386 = 3'h0;</span></a>
+<a name="5623"><span class="lineNum">    5623 </span><span class="lineCov">         12 :         state_vec_387 = 3'h0;</span></a>
+<a name="5624"><span class="lineNum">    5624 </span><span class="lineCov">         12 :         state_vec_388 = 3'h0;</span></a>
+<a name="5625"><span class="lineNum">    5625 </span><span class="lineCov">         12 :         state_vec_389 = 3'h0;</span></a>
+<a name="5626"><span class="lineNum">    5626 </span><span class="lineCov">         12 :         state_vec_390 = 3'h0;</span></a>
+<a name="5627"><span class="lineNum">    5627 </span><span class="lineCov">         12 :         state_vec_391 = 3'h0;</span></a>
+<a name="5628"><span class="lineNum">    5628 </span><span class="lineCov">         12 :         state_vec_392 = 3'h0;</span></a>
+<a name="5629"><span class="lineNum">    5629 </span><span class="lineCov">         12 :         state_vec_393 = 3'h0;</span></a>
+<a name="5630"><span class="lineNum">    5630 </span><span class="lineCov">         12 :         state_vec_394 = 3'h0;</span></a>
+<a name="5631"><span class="lineNum">    5631 </span><span class="lineCov">         12 :         state_vec_395 = 3'h0;</span></a>
+<a name="5632"><span class="lineNum">    5632 </span><span class="lineCov">         12 :         state_vec_396 = 3'h0;</span></a>
+<a name="5633"><span class="lineNum">    5633 </span><span class="lineCov">         12 :         state_vec_397 = 3'h0;</span></a>
+<a name="5634"><span class="lineNum">    5634 </span><span class="lineCov">         12 :         state_vec_398 = 3'h0;</span></a>
+<a name="5635"><span class="lineNum">    5635 </span><span class="lineCov">         12 :         state_vec_399 = 3'h0;</span></a>
+<a name="5636"><span class="lineNum">    5636 </span><span class="lineCov">         12 :         state_vec_400 = 3'h0;</span></a>
+<a name="5637"><span class="lineNum">    5637 </span><span class="lineCov">         12 :         state_vec_401 = 3'h0;</span></a>
+<a name="5638"><span class="lineNum">    5638 </span><span class="lineCov">         12 :         state_vec_402 = 3'h0;</span></a>
+<a name="5639"><span class="lineNum">    5639 </span><span class="lineCov">         12 :         state_vec_403 = 3'h0;</span></a>
+<a name="5640"><span class="lineNum">    5640 </span><span class="lineCov">         12 :         state_vec_404 = 3'h0;</span></a>
+<a name="5641"><span class="lineNum">    5641 </span><span class="lineCov">         12 :         state_vec_405 = 3'h0;</span></a>
+<a name="5642"><span class="lineNum">    5642 </span><span class="lineCov">         12 :         state_vec_406 = 3'h0;</span></a>
+<a name="5643"><span class="lineNum">    5643 </span><span class="lineCov">         12 :         state_vec_407 = 3'h0;</span></a>
+<a name="5644"><span class="lineNum">    5644 </span><span class="lineCov">         12 :         state_vec_408 = 3'h0;</span></a>
+<a name="5645"><span class="lineNum">    5645 </span><span class="lineCov">         12 :         state_vec_409 = 3'h0;</span></a>
+<a name="5646"><span class="lineNum">    5646 </span><span class="lineCov">         12 :         state_vec_410 = 3'h0;</span></a>
+<a name="5647"><span class="lineNum">    5647 </span><span class="lineCov">         12 :         state_vec_411 = 3'h0;</span></a>
+<a name="5648"><span class="lineNum">    5648 </span><span class="lineCov">         12 :         state_vec_412 = 3'h0;</span></a>
+<a name="5649"><span class="lineNum">    5649 </span><span class="lineCov">         12 :         state_vec_413 = 3'h0;</span></a>
+<a name="5650"><span class="lineNum">    5650 </span><span class="lineCov">         12 :         state_vec_414 = 3'h0;</span></a>
+<a name="5651"><span class="lineNum">    5651 </span><span class="lineCov">         12 :         state_vec_415 = 3'h0;</span></a>
+<a name="5652"><span class="lineNum">    5652 </span><span class="lineCov">         12 :         state_vec_416 = 3'h0;</span></a>
+<a name="5653"><span class="lineNum">    5653 </span><span class="lineCov">         12 :         state_vec_417 = 3'h0;</span></a>
+<a name="5654"><span class="lineNum">    5654 </span><span class="lineCov">         12 :         state_vec_418 = 3'h0;</span></a>
+<a name="5655"><span class="lineNum">    5655 </span><span class="lineCov">         12 :         state_vec_419 = 3'h0;</span></a>
+<a name="5656"><span class="lineNum">    5656 </span><span class="lineCov">         12 :         state_vec_420 = 3'h0;</span></a>
+<a name="5657"><span class="lineNum">    5657 </span><span class="lineCov">         12 :         state_vec_421 = 3'h0;</span></a>
+<a name="5658"><span class="lineNum">    5658 </span><span class="lineCov">         12 :         state_vec_422 = 3'h0;</span></a>
+<a name="5659"><span class="lineNum">    5659 </span><span class="lineCov">         12 :         state_vec_423 = 3'h0;</span></a>
+<a name="5660"><span class="lineNum">    5660 </span><span class="lineCov">         12 :         state_vec_424 = 3'h0;</span></a>
+<a name="5661"><span class="lineNum">    5661 </span><span class="lineCov">         12 :         state_vec_425 = 3'h0;</span></a>
+<a name="5662"><span class="lineNum">    5662 </span><span class="lineCov">         12 :         state_vec_426 = 3'h0;</span></a>
+<a name="5663"><span class="lineNum">    5663 </span><span class="lineCov">         12 :         state_vec_427 = 3'h0;</span></a>
+<a name="5664"><span class="lineNum">    5664 </span><span class="lineCov">         12 :         state_vec_428 = 3'h0;</span></a>
+<a name="5665"><span class="lineNum">    5665 </span><span class="lineCov">         12 :         state_vec_429 = 3'h0;</span></a>
+<a name="5666"><span class="lineNum">    5666 </span><span class="lineCov">         12 :         state_vec_430 = 3'h0;</span></a>
+<a name="5667"><span class="lineNum">    5667 </span><span class="lineCov">         12 :         state_vec_431 = 3'h0;</span></a>
+<a name="5668"><span class="lineNum">    5668 </span><span class="lineCov">         12 :         state_vec_432 = 3'h0;</span></a>
+<a name="5669"><span class="lineNum">    5669 </span><span class="lineCov">         12 :         state_vec_433 = 3'h0;</span></a>
+<a name="5670"><span class="lineNum">    5670 </span><span class="lineCov">         12 :         state_vec_434 = 3'h0;</span></a>
+<a name="5671"><span class="lineNum">    5671 </span><span class="lineCov">         12 :         state_vec_435 = 3'h0;</span></a>
+<a name="5672"><span class="lineNum">    5672 </span><span class="lineCov">         12 :         state_vec_436 = 3'h0;</span></a>
+<a name="5673"><span class="lineNum">    5673 </span><span class="lineCov">         12 :         state_vec_437 = 3'h0;</span></a>
+<a name="5674"><span class="lineNum">    5674 </span><span class="lineCov">         12 :         state_vec_438 = 3'h0;</span></a>
+<a name="5675"><span class="lineNum">    5675 </span><span class="lineCov">         12 :         state_vec_439 = 3'h0;</span></a>
+<a name="5676"><span class="lineNum">    5676 </span><span class="lineCov">         12 :         state_vec_440 = 3'h0;</span></a>
+<a name="5677"><span class="lineNum">    5677 </span><span class="lineCov">         12 :         state_vec_441 = 3'h0;</span></a>
+<a name="5678"><span class="lineNum">    5678 </span><span class="lineCov">         12 :         state_vec_442 = 3'h0;</span></a>
+<a name="5679"><span class="lineNum">    5679 </span><span class="lineCov">         12 :         state_vec_443 = 3'h0;</span></a>
+<a name="5680"><span class="lineNum">    5680 </span><span class="lineCov">         12 :         state_vec_444 = 3'h0;</span></a>
+<a name="5681"><span class="lineNum">    5681 </span><span class="lineCov">         12 :         state_vec_445 = 3'h0;</span></a>
+<a name="5682"><span class="lineNum">    5682 </span><span class="lineCov">         12 :         state_vec_446 = 3'h0;</span></a>
+<a name="5683"><span class="lineNum">    5683 </span><span class="lineCov">         12 :         state_vec_447 = 3'h0;</span></a>
+<a name="5684"><span class="lineNum">    5684 </span><span class="lineCov">         12 :         state_vec_448 = 3'h0;</span></a>
+<a name="5685"><span class="lineNum">    5685 </span><span class="lineCov">         12 :         state_vec_449 = 3'h0;</span></a>
+<a name="5686"><span class="lineNum">    5686 </span><span class="lineCov">         12 :         state_vec_450 = 3'h0;</span></a>
+<a name="5687"><span class="lineNum">    5687 </span><span class="lineCov">         12 :         state_vec_451 = 3'h0;</span></a>
+<a name="5688"><span class="lineNum">    5688 </span><span class="lineCov">         12 :         state_vec_452 = 3'h0;</span></a>
+<a name="5689"><span class="lineNum">    5689 </span><span class="lineCov">         12 :         state_vec_453 = 3'h0;</span></a>
+<a name="5690"><span class="lineNum">    5690 </span><span class="lineCov">         12 :         state_vec_454 = 3'h0;</span></a>
+<a name="5691"><span class="lineNum">    5691 </span><span class="lineCov">         12 :         state_vec_455 = 3'h0;</span></a>
+<a name="5692"><span class="lineNum">    5692 </span><span class="lineCov">         12 :         state_vec_456 = 3'h0;</span></a>
+<a name="5693"><span class="lineNum">    5693 </span><span class="lineCov">         12 :         state_vec_457 = 3'h0;</span></a>
+<a name="5694"><span class="lineNum">    5694 </span><span class="lineCov">         12 :         state_vec_458 = 3'h0;</span></a>
+<a name="5695"><span class="lineNum">    5695 </span><span class="lineCov">         12 :         state_vec_459 = 3'h0;</span></a>
+<a name="5696"><span class="lineNum">    5696 </span><span class="lineCov">         12 :         state_vec_460 = 3'h0;</span></a>
+<a name="5697"><span class="lineNum">    5697 </span><span class="lineCov">         12 :         state_vec_461 = 3'h0;</span></a>
+<a name="5698"><span class="lineNum">    5698 </span><span class="lineCov">         12 :         state_vec_462 = 3'h0;</span></a>
+<a name="5699"><span class="lineNum">    5699 </span><span class="lineCov">         12 :         state_vec_463 = 3'h0;</span></a>
+<a name="5700"><span class="lineNum">    5700 </span><span class="lineCov">         12 :         state_vec_464 = 3'h0;</span></a>
+<a name="5701"><span class="lineNum">    5701 </span><span class="lineCov">         12 :         state_vec_465 = 3'h0;</span></a>
+<a name="5702"><span class="lineNum">    5702 </span><span class="lineCov">         12 :         state_vec_466 = 3'h0;</span></a>
+<a name="5703"><span class="lineNum">    5703 </span><span class="lineCov">         12 :         state_vec_467 = 3'h0;</span></a>
+<a name="5704"><span class="lineNum">    5704 </span><span class="lineCov">         12 :         state_vec_468 = 3'h0;</span></a>
+<a name="5705"><span class="lineNum">    5705 </span><span class="lineCov">         12 :         state_vec_469 = 3'h0;</span></a>
+<a name="5706"><span class="lineNum">    5706 </span><span class="lineCov">         12 :         state_vec_470 = 3'h0;</span></a>
+<a name="5707"><span class="lineNum">    5707 </span><span class="lineCov">         12 :         state_vec_471 = 3'h0;</span></a>
+<a name="5708"><span class="lineNum">    5708 </span><span class="lineCov">         12 :         state_vec_472 = 3'h0;</span></a>
+<a name="5709"><span class="lineNum">    5709 </span><span class="lineCov">         12 :         state_vec_473 = 3'h0;</span></a>
+<a name="5710"><span class="lineNum">    5710 </span><span class="lineCov">         12 :         state_vec_474 = 3'h0;</span></a>
+<a name="5711"><span class="lineNum">    5711 </span><span class="lineCov">         12 :         state_vec_475 = 3'h0;</span></a>
+<a name="5712"><span class="lineNum">    5712 </span><span class="lineCov">         12 :         state_vec_476 = 3'h0;</span></a>
+<a name="5713"><span class="lineNum">    5713 </span><span class="lineCov">         12 :         state_vec_477 = 3'h0;</span></a>
+<a name="5714"><span class="lineNum">    5714 </span><span class="lineCov">         12 :         state_vec_478 = 3'h0;</span></a>
+<a name="5715"><span class="lineNum">    5715 </span><span class="lineCov">         12 :         state_vec_479 = 3'h0;</span></a>
+<a name="5716"><span class="lineNum">    5716 </span><span class="lineCov">         12 :         state_vec_480 = 3'h0;</span></a>
+<a name="5717"><span class="lineNum">    5717 </span><span class="lineCov">         12 :         state_vec_481 = 3'h0;</span></a>
+<a name="5718"><span class="lineNum">    5718 </span><span class="lineCov">         12 :         state_vec_482 = 3'h0;</span></a>
+<a name="5719"><span class="lineNum">    5719 </span><span class="lineCov">         12 :         state_vec_483 = 3'h0;</span></a>
+<a name="5720"><span class="lineNum">    5720 </span><span class="lineCov">         12 :         state_vec_484 = 3'h0;</span></a>
+<a name="5721"><span class="lineNum">    5721 </span><span class="lineCov">         12 :         state_vec_485 = 3'h0;</span></a>
+<a name="5722"><span class="lineNum">    5722 </span><span class="lineCov">         12 :         state_vec_486 = 3'h0;</span></a>
+<a name="5723"><span class="lineNum">    5723 </span><span class="lineCov">         12 :         state_vec_487 = 3'h0;</span></a>
+<a name="5724"><span class="lineNum">    5724 </span><span class="lineCov">         12 :         state_vec_488 = 3'h0;</span></a>
+<a name="5725"><span class="lineNum">    5725 </span><span class="lineCov">         12 :         state_vec_489 = 3'h0;</span></a>
+<a name="5726"><span class="lineNum">    5726 </span><span class="lineCov">         12 :         state_vec_490 = 3'h0;</span></a>
+<a name="5727"><span class="lineNum">    5727 </span><span class="lineCov">         12 :         state_vec_491 = 3'h0;</span></a>
+<a name="5728"><span class="lineNum">    5728 </span><span class="lineCov">         12 :         state_vec_492 = 3'h0;</span></a>
+<a name="5729"><span class="lineNum">    5729 </span><span class="lineCov">         12 :         state_vec_493 = 3'h0;</span></a>
+<a name="5730"><span class="lineNum">    5730 </span><span class="lineCov">         12 :         state_vec_494 = 3'h0;</span></a>
+<a name="5731"><span class="lineNum">    5731 </span><span class="lineCov">         12 :         state_vec_495 = 3'h0;</span></a>
+<a name="5732"><span class="lineNum">    5732 </span><span class="lineCov">         12 :         state_vec_496 = 3'h0;</span></a>
+<a name="5733"><span class="lineNum">    5733 </span><span class="lineCov">         12 :         state_vec_497 = 3'h0;</span></a>
+<a name="5734"><span class="lineNum">    5734 </span><span class="lineCov">         12 :         state_vec_498 = 3'h0;</span></a>
+<a name="5735"><span class="lineNum">    5735 </span><span class="lineCov">         12 :         state_vec_499 = 3'h0;</span></a>
+<a name="5736"><span class="lineNum">    5736 </span><span class="lineCov">         12 :         state_vec_500 = 3'h0;</span></a>
+<a name="5737"><span class="lineNum">    5737 </span><span class="lineCov">         12 :         state_vec_501 = 3'h0;</span></a>
+<a name="5738"><span class="lineNum">    5738 </span><span class="lineCov">         12 :         state_vec_502 = 3'h0;</span></a>
+<a name="5739"><span class="lineNum">    5739 </span><span class="lineCov">         12 :         state_vec_503 = 3'h0;</span></a>
+<a name="5740"><span class="lineNum">    5740 </span><span class="lineCov">         12 :         state_vec_504 = 3'h0;</span></a>
+<a name="5741"><span class="lineNum">    5741 </span><span class="lineCov">         12 :         state_vec_505 = 3'h0;</span></a>
+<a name="5742"><span class="lineNum">    5742 </span><span class="lineCov">         12 :         state_vec_506 = 3'h0;</span></a>
+<a name="5743"><span class="lineNum">    5743 </span><span class="lineCov">         12 :         state_vec_507 = 3'h0;</span></a>
+<a name="5744"><span class="lineNum">    5744 </span><span class="lineCov">         12 :         state_vec_508 = 3'h0;</span></a>
+<a name="5745"><span class="lineNum">    5745 </span><span class="lineCov">         12 :         state_vec_509 = 3'h0;</span></a>
+<a name="5746"><span class="lineNum">    5746 </span><span class="lineCov">         12 :         state_vec_510 = 3'h0;</span></a>
+<a name="5747"><span class="lineNum">    5747 </span>            :         state_vec_511 = 3'h0;</a>
+<a name="5748"><span class="lineNum">    5748 </span>            :       end</a>
+<a name="5749"><span class="lineNum">    5749 </span>            :     end // initial</a>
+<a name="5750"><span class="lineNum">    5750 </span>            :     `ifdef FIRRTL_AFTER_INITIAL</a>
+<a name="5751"><span class="lineNum">    5751 </span>            :       `FIRRTL_AFTER_INITIAL</a>
+<a name="5752"><span class="lineNum">    5752 </span>            :     `endif // FIRRTL_AFTER_INITIAL</a>
+<a name="5753"><span class="lineNum">    5753 </span>            :   `endif // ENABLE_INITIAL_REG_</a>
+<a name="5754"><span class="lineNum">    5754 </span>            :   SRAMTemplate_13 ftb (</a>
+<a name="5755"><span class="lineNum">    5755 </span>            :     .clock                                           (clock),</a>
+<a name="5756"><span class="lineNum">    5756 </span>            :     .reset                                           (reset),</a>
+<a name="5757"><span class="lineNum">    5757 </span>            :     .io_r_req_ready                                  (io_req_pc_ready),</a>
+<a name="5758"><span class="lineNum">    5758 </span>            :     .io_r_req_valid</a>
+<a name="5759"><span class="lineNum">    5759 </span>            :       (io_req_pc_valid | io_u_req_pc_valid),</a>
+<a name="5760"><span class="lineNum">    5760 </span>            :     .io_r_req_bits_setIdx</a>
+<a name="5761"><span class="lineNum">    5761 </span>            :       (io_u_req_pc_valid ? io_u_req_pc_bits[9:1] : io_req_pc_bits[9:1]),</a>
+<a name="5762"><span class="lineNum">    5762 </span>            :     .io_r_resp_data_0_entry_valid                    (_ftb_io_r_resp_data_0_entry_valid),</a>
+<a name="5763"><span class="lineNum">    5763 </span>            :     .io_r_resp_data_0_entry_brSlots_0_offset</a>
+<a name="5764"><span class="lineNum">    5764 </span>            :       (_ftb_io_r_resp_data_0_entry_brSlots_0_offset),</a>
+<a name="5765"><span class="lineNum">    5765 </span>            :     .io_r_resp_data_0_entry_brSlots_0_lower</a>
+<a name="5766"><span class="lineNum">    5766 </span>            :       (_ftb_io_r_resp_data_0_entry_brSlots_0_lower),</a>
+<a name="5767"><span class="lineNum">    5767 </span>            :     .io_r_resp_data_0_entry_brSlots_0_tarStat</a>
+<a name="5768"><span class="lineNum">    5768 </span>            :       (_ftb_io_r_resp_data_0_entry_brSlots_0_tarStat),</a>
+<a name="5769"><span class="lineNum">    5769 </span>            :     .io_r_resp_data_0_entry_brSlots_0_sharing</a>
+<a name="5770"><span class="lineNum">    5770 </span>            :       (_ftb_io_r_resp_data_0_entry_brSlots_0_sharing),</a>
+<a name="5771"><span class="lineNum">    5771 </span>            :     .io_r_resp_data_0_entry_brSlots_0_valid</a>
+<a name="5772"><span class="lineNum">    5772 </span>            :       (_ftb_io_r_resp_data_0_entry_brSlots_0_valid),</a>
+<a name="5773"><span class="lineNum">    5773 </span>            :     .io_r_resp_data_0_entry_tailSlot_offset</a>
+<a name="5774"><span class="lineNum">    5774 </span>            :       (_ftb_io_r_resp_data_0_entry_tailSlot_offset),</a>
+<a name="5775"><span class="lineNum">    5775 </span>            :     .io_r_resp_data_0_entry_tailSlot_lower</a>
+<a name="5776"><span class="lineNum">    5776 </span>            :       (_ftb_io_r_resp_data_0_entry_tailSlot_lower),</a>
+<a name="5777"><span class="lineNum">    5777 </span>            :     .io_r_resp_data_0_entry_tailSlot_tarStat</a>
+<a name="5778"><span class="lineNum">    5778 </span>            :       (_ftb_io_r_resp_data_0_entry_tailSlot_tarStat),</a>
+<a name="5779"><span class="lineNum">    5779 </span>            :     .io_r_resp_data_0_entry_tailSlot_sharing</a>
+<a name="5780"><span class="lineNum">    5780 </span>            :       (_ftb_io_r_resp_data_0_entry_tailSlot_sharing),</a>
+<a name="5781"><span class="lineNum">    5781 </span>            :     .io_r_resp_data_0_entry_tailSlot_valid</a>
+<a name="5782"><span class="lineNum">    5782 </span>            :       (_ftb_io_r_resp_data_0_entry_tailSlot_valid),</a>
+<a name="5783"><span class="lineNum">    5783 </span>            :     .io_r_resp_data_0_entry_pftAddr</a>
+<a name="5784"><span class="lineNum">    5784 </span>            :       (_ftb_io_r_resp_data_0_entry_pftAddr),</a>
+<a name="5785"><span class="lineNum">    5785 </span>            :     .io_r_resp_data_0_entry_carry                    (_ftb_io_r_resp_data_0_entry_carry),</a>
+<a name="5786"><span class="lineNum">    5786 </span>            :     .io_r_resp_data_0_entry_isCall                   (_ftb_io_r_resp_data_0_entry_isCall),</a>
+<a name="5787"><span class="lineNum">    5787 </span>            :     .io_r_resp_data_0_entry_isRet                    (_ftb_io_r_resp_data_0_entry_isRet),</a>
+<a name="5788"><span class="lineNum">    5788 </span>            :     .io_r_resp_data_0_entry_isJalr                   (_ftb_io_r_resp_data_0_entry_isJalr),</a>
+<a name="5789"><span class="lineNum">    5789 </span>            :     .io_r_resp_data_0_entry_last_may_be_rvi_call</a>
+<a name="5790"><span class="lineNum">    5790 </span>            :       (_ftb_io_r_resp_data_0_entry_last_may_be_rvi_call),</a>
+<a name="5791"><span class="lineNum">    5791 </span>            :     .io_r_resp_data_0_entry_always_taken_0</a>
+<a name="5792"><span class="lineNum">    5792 </span>            :       (_ftb_io_r_resp_data_0_entry_always_taken_0),</a>
+<a name="5793"><span class="lineNum">    5793 </span>            :     .io_r_resp_data_0_entry_always_taken_1</a>
+<a name="5794"><span class="lineNum">    5794 </span>            :       (_ftb_io_r_resp_data_0_entry_always_taken_1),</a>
+<a name="5795"><span class="lineNum">    5795 </span>            :     .io_r_resp_data_0_tag                            (_ftb_io_r_resp_data_0_tag),</a>
+<a name="5796"><span class="lineNum">    5796 </span>            :     .io_r_resp_data_1_entry_valid                    (_ftb_io_r_resp_data_1_entry_valid),</a>
+<a name="5797"><span class="lineNum">    5797 </span>            :     .io_r_resp_data_1_entry_brSlots_0_offset</a>
+<a name="5798"><span class="lineNum">    5798 </span>            :       (_ftb_io_r_resp_data_1_entry_brSlots_0_offset),</a>
+<a name="5799"><span class="lineNum">    5799 </span>            :     .io_r_resp_data_1_entry_brSlots_0_lower</a>
+<a name="5800"><span class="lineNum">    5800 </span>            :       (_ftb_io_r_resp_data_1_entry_brSlots_0_lower),</a>
+<a name="5801"><span class="lineNum">    5801 </span>            :     .io_r_resp_data_1_entry_brSlots_0_tarStat</a>
+<a name="5802"><span class="lineNum">    5802 </span>            :       (_ftb_io_r_resp_data_1_entry_brSlots_0_tarStat),</a>
+<a name="5803"><span class="lineNum">    5803 </span>            :     .io_r_resp_data_1_entry_brSlots_0_sharing</a>
+<a name="5804"><span class="lineNum">    5804 </span>            :       (_ftb_io_r_resp_data_1_entry_brSlots_0_sharing),</a>
+<a name="5805"><span class="lineNum">    5805 </span>            :     .io_r_resp_data_1_entry_brSlots_0_valid</a>
+<a name="5806"><span class="lineNum">    5806 </span>            :       (_ftb_io_r_resp_data_1_entry_brSlots_0_valid),</a>
+<a name="5807"><span class="lineNum">    5807 </span>            :     .io_r_resp_data_1_entry_tailSlot_offset</a>
+<a name="5808"><span class="lineNum">    5808 </span>            :       (_ftb_io_r_resp_data_1_entry_tailSlot_offset),</a>
+<a name="5809"><span class="lineNum">    5809 </span>            :     .io_r_resp_data_1_entry_tailSlot_lower</a>
+<a name="5810"><span class="lineNum">    5810 </span>            :       (_ftb_io_r_resp_data_1_entry_tailSlot_lower),</a>
+<a name="5811"><span class="lineNum">    5811 </span>            :     .io_r_resp_data_1_entry_tailSlot_tarStat</a>
+<a name="5812"><span class="lineNum">    5812 </span>            :       (_ftb_io_r_resp_data_1_entry_tailSlot_tarStat),</a>
+<a name="5813"><span class="lineNum">    5813 </span>            :     .io_r_resp_data_1_entry_tailSlot_sharing</a>
+<a name="5814"><span class="lineNum">    5814 </span>            :       (_ftb_io_r_resp_data_1_entry_tailSlot_sharing),</a>
+<a name="5815"><span class="lineNum">    5815 </span>            :     .io_r_resp_data_1_entry_tailSlot_valid</a>
+<a name="5816"><span class="lineNum">    5816 </span>            :       (_ftb_io_r_resp_data_1_entry_tailSlot_valid),</a>
+<a name="5817"><span class="lineNum">    5817 </span>            :     .io_r_resp_data_1_entry_pftAddr</a>
+<a name="5818"><span class="lineNum">    5818 </span>            :       (_ftb_io_r_resp_data_1_entry_pftAddr),</a>
+<a name="5819"><span class="lineNum">    5819 </span>            :     .io_r_resp_data_1_entry_carry                    (_ftb_io_r_resp_data_1_entry_carry),</a>
+<a name="5820"><span class="lineNum">    5820 </span>            :     .io_r_resp_data_1_entry_isCall                   (_ftb_io_r_resp_data_1_entry_isCall),</a>
+<a name="5821"><span class="lineNum">    5821 </span>            :     .io_r_resp_data_1_entry_isRet                    (_ftb_io_r_resp_data_1_entry_isRet),</a>
+<a name="5822"><span class="lineNum">    5822 </span>            :     .io_r_resp_data_1_entry_isJalr                   (_ftb_io_r_resp_data_1_entry_isJalr),</a>
+<a name="5823"><span class="lineNum">    5823 </span>            :     .io_r_resp_data_1_entry_last_may_be_rvi_call</a>
+<a name="5824"><span class="lineNum">    5824 </span>            :       (_ftb_io_r_resp_data_1_entry_last_may_be_rvi_call),</a>
+<a name="5825"><span class="lineNum">    5825 </span>            :     .io_r_resp_data_1_entry_always_taken_0</a>
+<a name="5826"><span class="lineNum">    5826 </span>            :       (_ftb_io_r_resp_data_1_entry_always_taken_0),</a>
+<a name="5827"><span class="lineNum">    5827 </span>            :     .io_r_resp_data_1_entry_always_taken_1</a>
+<a name="5828"><span class="lineNum">    5828 </span>            :       (_ftb_io_r_resp_data_1_entry_always_taken_1),</a>
+<a name="5829"><span class="lineNum">    5829 </span>            :     .io_r_resp_data_1_tag                            (_ftb_io_r_resp_data_1_tag),</a>
+<a name="5830"><span class="lineNum">    5830 </span>            :     .io_r_resp_data_2_entry_valid                    (_ftb_io_r_resp_data_2_entry_valid),</a>
+<a name="5831"><span class="lineNum">    5831 </span>            :     .io_r_resp_data_2_entry_brSlots_0_offset</a>
+<a name="5832"><span class="lineNum">    5832 </span>            :       (_ftb_io_r_resp_data_2_entry_brSlots_0_offset),</a>
+<a name="5833"><span class="lineNum">    5833 </span>            :     .io_r_resp_data_2_entry_brSlots_0_lower</a>
+<a name="5834"><span class="lineNum">    5834 </span>            :       (_ftb_io_r_resp_data_2_entry_brSlots_0_lower),</a>
+<a name="5835"><span class="lineNum">    5835 </span>            :     .io_r_resp_data_2_entry_brSlots_0_tarStat</a>
+<a name="5836"><span class="lineNum">    5836 </span>            :       (_ftb_io_r_resp_data_2_entry_brSlots_0_tarStat),</a>
+<a name="5837"><span class="lineNum">    5837 </span>            :     .io_r_resp_data_2_entry_brSlots_0_sharing</a>
+<a name="5838"><span class="lineNum">    5838 </span>            :       (_ftb_io_r_resp_data_2_entry_brSlots_0_sharing),</a>
+<a name="5839"><span class="lineNum">    5839 </span>            :     .io_r_resp_data_2_entry_brSlots_0_valid</a>
+<a name="5840"><span class="lineNum">    5840 </span>            :       (_ftb_io_r_resp_data_2_entry_brSlots_0_valid),</a>
+<a name="5841"><span class="lineNum">    5841 </span>            :     .io_r_resp_data_2_entry_tailSlot_offset</a>
+<a name="5842"><span class="lineNum">    5842 </span>            :       (_ftb_io_r_resp_data_2_entry_tailSlot_offset),</a>
+<a name="5843"><span class="lineNum">    5843 </span>            :     .io_r_resp_data_2_entry_tailSlot_lower</a>
+<a name="5844"><span class="lineNum">    5844 </span>            :       (_ftb_io_r_resp_data_2_entry_tailSlot_lower),</a>
+<a name="5845"><span class="lineNum">    5845 </span>            :     .io_r_resp_data_2_entry_tailSlot_tarStat</a>
+<a name="5846"><span class="lineNum">    5846 </span>            :       (_ftb_io_r_resp_data_2_entry_tailSlot_tarStat),</a>
+<a name="5847"><span class="lineNum">    5847 </span>            :     .io_r_resp_data_2_entry_tailSlot_sharing</a>
+<a name="5848"><span class="lineNum">    5848 </span>            :       (_ftb_io_r_resp_data_2_entry_tailSlot_sharing),</a>
+<a name="5849"><span class="lineNum">    5849 </span>            :     .io_r_resp_data_2_entry_tailSlot_valid</a>
+<a name="5850"><span class="lineNum">    5850 </span>            :       (_ftb_io_r_resp_data_2_entry_tailSlot_valid),</a>
+<a name="5851"><span class="lineNum">    5851 </span>            :     .io_r_resp_data_2_entry_pftAddr</a>
+<a name="5852"><span class="lineNum">    5852 </span>            :       (_ftb_io_r_resp_data_2_entry_pftAddr),</a>
+<a name="5853"><span class="lineNum">    5853 </span>            :     .io_r_resp_data_2_entry_carry                    (_ftb_io_r_resp_data_2_entry_carry),</a>
+<a name="5854"><span class="lineNum">    5854 </span>            :     .io_r_resp_data_2_entry_isCall                   (_ftb_io_r_resp_data_2_entry_isCall),</a>
+<a name="5855"><span class="lineNum">    5855 </span>            :     .io_r_resp_data_2_entry_isRet                    (_ftb_io_r_resp_data_2_entry_isRet),</a>
+<a name="5856"><span class="lineNum">    5856 </span>            :     .io_r_resp_data_2_entry_isJalr                   (_ftb_io_r_resp_data_2_entry_isJalr),</a>
+<a name="5857"><span class="lineNum">    5857 </span>            :     .io_r_resp_data_2_entry_last_may_be_rvi_call</a>
+<a name="5858"><span class="lineNum">    5858 </span>            :       (_ftb_io_r_resp_data_2_entry_last_may_be_rvi_call),</a>
+<a name="5859"><span class="lineNum">    5859 </span>            :     .io_r_resp_data_2_entry_always_taken_0</a>
+<a name="5860"><span class="lineNum">    5860 </span>            :       (_ftb_io_r_resp_data_2_entry_always_taken_0),</a>
+<a name="5861"><span class="lineNum">    5861 </span>            :     .io_r_resp_data_2_entry_always_taken_1</a>
+<a name="5862"><span class="lineNum">    5862 </span>            :       (_ftb_io_r_resp_data_2_entry_always_taken_1),</a>
+<a name="5863"><span class="lineNum">    5863 </span>            :     .io_r_resp_data_2_tag                            (_ftb_io_r_resp_data_2_tag),</a>
+<a name="5864"><span class="lineNum">    5864 </span>            :     .io_r_resp_data_3_entry_valid                    (_ftb_io_r_resp_data_3_entry_valid),</a>
+<a name="5865"><span class="lineNum">    5865 </span>            :     .io_r_resp_data_3_entry_brSlots_0_offset</a>
+<a name="5866"><span class="lineNum">    5866 </span>            :       (_ftb_io_r_resp_data_3_entry_brSlots_0_offset),</a>
+<a name="5867"><span class="lineNum">    5867 </span>            :     .io_r_resp_data_3_entry_brSlots_0_lower</a>
+<a name="5868"><span class="lineNum">    5868 </span>            :       (_ftb_io_r_resp_data_3_entry_brSlots_0_lower),</a>
+<a name="5869"><span class="lineNum">    5869 </span>            :     .io_r_resp_data_3_entry_brSlots_0_tarStat</a>
+<a name="5870"><span class="lineNum">    5870 </span>            :       (_ftb_io_r_resp_data_3_entry_brSlots_0_tarStat),</a>
+<a name="5871"><span class="lineNum">    5871 </span>            :     .io_r_resp_data_3_entry_brSlots_0_sharing</a>
+<a name="5872"><span class="lineNum">    5872 </span>            :       (_ftb_io_r_resp_data_3_entry_brSlots_0_sharing),</a>
+<a name="5873"><span class="lineNum">    5873 </span>            :     .io_r_resp_data_3_entry_brSlots_0_valid</a>
+<a name="5874"><span class="lineNum">    5874 </span>            :       (_ftb_io_r_resp_data_3_entry_brSlots_0_valid),</a>
+<a name="5875"><span class="lineNum">    5875 </span>            :     .io_r_resp_data_3_entry_tailSlot_offset</a>
+<a name="5876"><span class="lineNum">    5876 </span>            :       (_ftb_io_r_resp_data_3_entry_tailSlot_offset),</a>
+<a name="5877"><span class="lineNum">    5877 </span>            :     .io_r_resp_data_3_entry_tailSlot_lower</a>
+<a name="5878"><span class="lineNum">    5878 </span>            :       (_ftb_io_r_resp_data_3_entry_tailSlot_lower),</a>
+<a name="5879"><span class="lineNum">    5879 </span>            :     .io_r_resp_data_3_entry_tailSlot_tarStat</a>
+<a name="5880"><span class="lineNum">    5880 </span>            :       (_ftb_io_r_resp_data_3_entry_tailSlot_tarStat),</a>
+<a name="5881"><span class="lineNum">    5881 </span>            :     .io_r_resp_data_3_entry_tailSlot_sharing</a>
+<a name="5882"><span class="lineNum">    5882 </span>            :       (_ftb_io_r_resp_data_3_entry_tailSlot_sharing),</a>
+<a name="5883"><span class="lineNum">    5883 </span>            :     .io_r_resp_data_3_entry_tailSlot_valid</a>
+<a name="5884"><span class="lineNum">    5884 </span>            :       (_ftb_io_r_resp_data_3_entry_tailSlot_valid),</a>
+<a name="5885"><span class="lineNum">    5885 </span>            :     .io_r_resp_data_3_entry_pftAddr</a>
+<a name="5886"><span class="lineNum">    5886 </span>            :       (_ftb_io_r_resp_data_3_entry_pftAddr),</a>
+<a name="5887"><span class="lineNum">    5887 </span>            :     .io_r_resp_data_3_entry_carry                    (_ftb_io_r_resp_data_3_entry_carry),</a>
+<a name="5888"><span class="lineNum">    5888 </span>            :     .io_r_resp_data_3_entry_isCall                   (_ftb_io_r_resp_data_3_entry_isCall),</a>
+<a name="5889"><span class="lineNum">    5889 </span>            :     .io_r_resp_data_3_entry_isRet                    (_ftb_io_r_resp_data_3_entry_isRet),</a>
+<a name="5890"><span class="lineNum">    5890 </span>            :     .io_r_resp_data_3_entry_isJalr                   (_ftb_io_r_resp_data_3_entry_isJalr),</a>
+<a name="5891"><span class="lineNum">    5891 </span>            :     .io_r_resp_data_3_entry_last_may_be_rvi_call</a>
+<a name="5892"><span class="lineNum">    5892 </span>            :       (_ftb_io_r_resp_data_3_entry_last_may_be_rvi_call),</a>
+<a name="5893"><span class="lineNum">    5893 </span>            :     .io_r_resp_data_3_entry_always_taken_0</a>
+<a name="5894"><span class="lineNum">    5894 </span>            :       (_ftb_io_r_resp_data_3_entry_always_taken_0),</a>
+<a name="5895"><span class="lineNum">    5895 </span>            :     .io_r_resp_data_3_entry_always_taken_1</a>
+<a name="5896"><span class="lineNum">    5896 </span>            :       (_ftb_io_r_resp_data_3_entry_always_taken_1),</a>
+<a name="5897"><span class="lineNum">    5897 </span>            :     .io_r_resp_data_3_tag                            (_ftb_io_r_resp_data_3_tag),</a>
+<a name="5898"><span class="lineNum">    5898 </span>            :     .io_w_req_valid                                  (io_update_write_data_valid),</a>
+<a name="5899"><span class="lineNum">    5899 </span>            :     .io_w_req_bits_setIdx                            (io_update_pc[9:1]),</a>
+<a name="5900"><span class="lineNum">    5900 </span>            :     .io_w_req_bits_data_0_entry_valid</a>
+<a name="5901"><span class="lineNum">    5901 </span>            :       (io_update_write_data_bits_entry_valid),</a>
+<a name="5902"><span class="lineNum">    5902 </span>            :     .io_w_req_bits_data_0_entry_brSlots_0_offset</a>
+<a name="5903"><span class="lineNum">    5903 </span>            :       (io_update_write_data_bits_entry_brSlots_0_offset),</a>
+<a name="5904"><span class="lineNum">    5904 </span>            :     .io_w_req_bits_data_0_entry_brSlots_0_lower</a>
+<a name="5905"><span class="lineNum">    5905 </span>            :       (io_update_write_data_bits_entry_brSlots_0_lower),</a>
+<a name="5906"><span class="lineNum">    5906 </span>            :     .io_w_req_bits_data_0_entry_brSlots_0_tarStat</a>
+<a name="5907"><span class="lineNum">    5907 </span>            :       (io_update_write_data_bits_entry_brSlots_0_tarStat),</a>
+<a name="5908"><span class="lineNum">    5908 </span>            :     .io_w_req_bits_data_0_entry_brSlots_0_sharing</a>
+<a name="5909"><span class="lineNum">    5909 </span>            :       (io_update_write_data_bits_entry_brSlots_0_sharing),</a>
+<a name="5910"><span class="lineNum">    5910 </span>            :     .io_w_req_bits_data_0_entry_brSlots_0_valid</a>
+<a name="5911"><span class="lineNum">    5911 </span>            :       (io_update_write_data_bits_entry_brSlots_0_valid),</a>
+<a name="5912"><span class="lineNum">    5912 </span>            :     .io_w_req_bits_data_0_entry_tailSlot_offset</a>
+<a name="5913"><span class="lineNum">    5913 </span>            :       (io_update_write_data_bits_entry_tailSlot_offset),</a>
+<a name="5914"><span class="lineNum">    5914 </span>            :     .io_w_req_bits_data_0_entry_tailSlot_lower</a>
+<a name="5915"><span class="lineNum">    5915 </span>            :       (io_update_write_data_bits_entry_tailSlot_lower),</a>
+<a name="5916"><span class="lineNum">    5916 </span>            :     .io_w_req_bits_data_0_entry_tailSlot_tarStat</a>
+<a name="5917"><span class="lineNum">    5917 </span>            :       (io_update_write_data_bits_entry_tailSlot_tarStat),</a>
+<a name="5918"><span class="lineNum">    5918 </span>            :     .io_w_req_bits_data_0_entry_tailSlot_sharing</a>
+<a name="5919"><span class="lineNum">    5919 </span>            :       (io_update_write_data_bits_entry_tailSlot_sharing),</a>
+<a name="5920"><span class="lineNum">    5920 </span>            :     .io_w_req_bits_data_0_entry_tailSlot_valid</a>
+<a name="5921"><span class="lineNum">    5921 </span>            :       (io_update_write_data_bits_entry_tailSlot_valid),</a>
+<a name="5922"><span class="lineNum">    5922 </span>            :     .io_w_req_bits_data_0_entry_pftAddr</a>
+<a name="5923"><span class="lineNum">    5923 </span>            :       (io_update_write_data_bits_entry_pftAddr),</a>
+<a name="5924"><span class="lineNum">    5924 </span>            :     .io_w_req_bits_data_0_entry_carry</a>
+<a name="5925"><span class="lineNum">    5925 </span>            :       (io_update_write_data_bits_entry_carry),</a>
+<a name="5926"><span class="lineNum">    5926 </span>            :     .io_w_req_bits_data_0_entry_isCall</a>
+<a name="5927"><span class="lineNum">    5927 </span>            :       (io_update_write_data_bits_entry_isCall),</a>
+<a name="5928"><span class="lineNum">    5928 </span>            :     .io_w_req_bits_data_0_entry_isRet</a>
+<a name="5929"><span class="lineNum">    5929 </span>            :       (io_update_write_data_bits_entry_isRet),</a>
+<a name="5930"><span class="lineNum">    5930 </span>            :     .io_w_req_bits_data_0_entry_isJalr</a>
+<a name="5931"><span class="lineNum">    5931 </span>            :       (io_update_write_data_bits_entry_isJalr),</a>
+<a name="5932"><span class="lineNum">    5932 </span>            :     .io_w_req_bits_data_0_entry_last_may_be_rvi_call</a>
+<a name="5933"><span class="lineNum">    5933 </span>            :       (io_update_write_data_bits_entry_last_may_be_rvi_call),</a>
+<a name="5934"><span class="lineNum">    5934 </span>            :     .io_w_req_bits_data_0_entry_always_taken_0</a>
+<a name="5935"><span class="lineNum">    5935 </span>            :       (io_update_write_data_bits_entry_always_taken_0),</a>
+<a name="5936"><span class="lineNum">    5936 </span>            :     .io_w_req_bits_data_0_entry_always_taken_1</a>
+<a name="5937"><span class="lineNum">    5937 </span>            :       (io_update_write_data_bits_entry_always_taken_1),</a>
+<a name="5938"><span class="lineNum">    5938 </span>            :     .io_w_req_bits_data_0_tag                        (io_update_write_data_bits_tag),</a>
+<a name="5939"><span class="lineNum">    5939 </span>            :     .io_w_req_bits_data_1_entry_valid</a>
+<a name="5940"><span class="lineNum">    5940 </span>            :       (io_update_write_data_bits_entry_valid),</a>
+<a name="5941"><span class="lineNum">    5941 </span>            :     .io_w_req_bits_data_1_entry_brSlots_0_offset</a>
+<a name="5942"><span class="lineNum">    5942 </span>            :       (io_update_write_data_bits_entry_brSlots_0_offset),</a>
+<a name="5943"><span class="lineNum">    5943 </span>            :     .io_w_req_bits_data_1_entry_brSlots_0_lower</a>
+<a name="5944"><span class="lineNum">    5944 </span>            :       (io_update_write_data_bits_entry_brSlots_0_lower),</a>
+<a name="5945"><span class="lineNum">    5945 </span>            :     .io_w_req_bits_data_1_entry_brSlots_0_tarStat</a>
+<a name="5946"><span class="lineNum">    5946 </span>            :       (io_update_write_data_bits_entry_brSlots_0_tarStat),</a>
+<a name="5947"><span class="lineNum">    5947 </span>            :     .io_w_req_bits_data_1_entry_brSlots_0_sharing</a>
+<a name="5948"><span class="lineNum">    5948 </span>            :       (io_update_write_data_bits_entry_brSlots_0_sharing),</a>
+<a name="5949"><span class="lineNum">    5949 </span>            :     .io_w_req_bits_data_1_entry_brSlots_0_valid</a>
+<a name="5950"><span class="lineNum">    5950 </span>            :       (io_update_write_data_bits_entry_brSlots_0_valid),</a>
+<a name="5951"><span class="lineNum">    5951 </span>            :     .io_w_req_bits_data_1_entry_tailSlot_offset</a>
+<a name="5952"><span class="lineNum">    5952 </span>            :       (io_update_write_data_bits_entry_tailSlot_offset),</a>
+<a name="5953"><span class="lineNum">    5953 </span>            :     .io_w_req_bits_data_1_entry_tailSlot_lower</a>
+<a name="5954"><span class="lineNum">    5954 </span>            :       (io_update_write_data_bits_entry_tailSlot_lower),</a>
+<a name="5955"><span class="lineNum">    5955 </span>            :     .io_w_req_bits_data_1_entry_tailSlot_tarStat</a>
+<a name="5956"><span class="lineNum">    5956 </span>            :       (io_update_write_data_bits_entry_tailSlot_tarStat),</a>
+<a name="5957"><span class="lineNum">    5957 </span>            :     .io_w_req_bits_data_1_entry_tailSlot_sharing</a>
+<a name="5958"><span class="lineNum">    5958 </span>            :       (io_update_write_data_bits_entry_tailSlot_sharing),</a>
+<a name="5959"><span class="lineNum">    5959 </span>            :     .io_w_req_bits_data_1_entry_tailSlot_valid</a>
+<a name="5960"><span class="lineNum">    5960 </span>            :       (io_update_write_data_bits_entry_tailSlot_valid),</a>
+<a name="5961"><span class="lineNum">    5961 </span>            :     .io_w_req_bits_data_1_entry_pftAddr</a>
+<a name="5962"><span class="lineNum">    5962 </span>            :       (io_update_write_data_bits_entry_pftAddr),</a>
+<a name="5963"><span class="lineNum">    5963 </span>            :     .io_w_req_bits_data_1_entry_carry</a>
+<a name="5964"><span class="lineNum">    5964 </span>            :       (io_update_write_data_bits_entry_carry),</a>
+<a name="5965"><span class="lineNum">    5965 </span>            :     .io_w_req_bits_data_1_entry_isCall</a>
+<a name="5966"><span class="lineNum">    5966 </span>            :       (io_update_write_data_bits_entry_isCall),</a>
+<a name="5967"><span class="lineNum">    5967 </span>            :     .io_w_req_bits_data_1_entry_isRet</a>
+<a name="5968"><span class="lineNum">    5968 </span>            :       (io_update_write_data_bits_entry_isRet),</a>
+<a name="5969"><span class="lineNum">    5969 </span>            :     .io_w_req_bits_data_1_entry_isJalr</a>
+<a name="5970"><span class="lineNum">    5970 </span>            :       (io_update_write_data_bits_entry_isJalr),</a>
+<a name="5971"><span class="lineNum">    5971 </span>            :     .io_w_req_bits_data_1_entry_last_may_be_rvi_call</a>
+<a name="5972"><span class="lineNum">    5972 </span>            :       (io_update_write_data_bits_entry_last_may_be_rvi_call),</a>
+<a name="5973"><span class="lineNum">    5973 </span>            :     .io_w_req_bits_data_1_entry_always_taken_0</a>
+<a name="5974"><span class="lineNum">    5974 </span>            :       (io_update_write_data_bits_entry_always_taken_0),</a>
+<a name="5975"><span class="lineNum">    5975 </span>            :     .io_w_req_bits_data_1_entry_always_taken_1</a>
+<a name="5976"><span class="lineNum">    5976 </span>            :       (io_update_write_data_bits_entry_always_taken_1),</a>
+<a name="5977"><span class="lineNum">    5977 </span>            :     .io_w_req_bits_data_1_tag                        (io_update_write_data_bits_tag),</a>
+<a name="5978"><span class="lineNum">    5978 </span>            :     .io_w_req_bits_data_2_entry_valid</a>
+<a name="5979"><span class="lineNum">    5979 </span>            :       (io_update_write_data_bits_entry_valid),</a>
+<a name="5980"><span class="lineNum">    5980 </span>            :     .io_w_req_bits_data_2_entry_brSlots_0_offset</a>
+<a name="5981"><span class="lineNum">    5981 </span>            :       (io_update_write_data_bits_entry_brSlots_0_offset),</a>
+<a name="5982"><span class="lineNum">    5982 </span>            :     .io_w_req_bits_data_2_entry_brSlots_0_lower</a>
+<a name="5983"><span class="lineNum">    5983 </span>            :       (io_update_write_data_bits_entry_brSlots_0_lower),</a>
+<a name="5984"><span class="lineNum">    5984 </span>            :     .io_w_req_bits_data_2_entry_brSlots_0_tarStat</a>
+<a name="5985"><span class="lineNum">    5985 </span>            :       (io_update_write_data_bits_entry_brSlots_0_tarStat),</a>
+<a name="5986"><span class="lineNum">    5986 </span>            :     .io_w_req_bits_data_2_entry_brSlots_0_sharing</a>
+<a name="5987"><span class="lineNum">    5987 </span>            :       (io_update_write_data_bits_entry_brSlots_0_sharing),</a>
+<a name="5988"><span class="lineNum">    5988 </span>            :     .io_w_req_bits_data_2_entry_brSlots_0_valid</a>
+<a name="5989"><span class="lineNum">    5989 </span>            :       (io_update_write_data_bits_entry_brSlots_0_valid),</a>
+<a name="5990"><span class="lineNum">    5990 </span>            :     .io_w_req_bits_data_2_entry_tailSlot_offset</a>
+<a name="5991"><span class="lineNum">    5991 </span>            :       (io_update_write_data_bits_entry_tailSlot_offset),</a>
+<a name="5992"><span class="lineNum">    5992 </span>            :     .io_w_req_bits_data_2_entry_tailSlot_lower</a>
+<a name="5993"><span class="lineNum">    5993 </span>            :       (io_update_write_data_bits_entry_tailSlot_lower),</a>
+<a name="5994"><span class="lineNum">    5994 </span>            :     .io_w_req_bits_data_2_entry_tailSlot_tarStat</a>
+<a name="5995"><span class="lineNum">    5995 </span>            :       (io_update_write_data_bits_entry_tailSlot_tarStat),</a>
+<a name="5996"><span class="lineNum">    5996 </span>            :     .io_w_req_bits_data_2_entry_tailSlot_sharing</a>
+<a name="5997"><span class="lineNum">    5997 </span>            :       (io_update_write_data_bits_entry_tailSlot_sharing),</a>
+<a name="5998"><span class="lineNum">    5998 </span>            :     .io_w_req_bits_data_2_entry_tailSlot_valid</a>
+<a name="5999"><span class="lineNum">    5999 </span>            :       (io_update_write_data_bits_entry_tailSlot_valid),</a>
+<a name="6000"><span class="lineNum">    6000 </span>            :     .io_w_req_bits_data_2_entry_pftAddr</a>
+<a name="6001"><span class="lineNum">    6001 </span>            :       (io_update_write_data_bits_entry_pftAddr),</a>
+<a name="6002"><span class="lineNum">    6002 </span>            :     .io_w_req_bits_data_2_entry_carry</a>
+<a name="6003"><span class="lineNum">    6003 </span>            :       (io_update_write_data_bits_entry_carry),</a>
+<a name="6004"><span class="lineNum">    6004 </span>            :     .io_w_req_bits_data_2_entry_isCall</a>
+<a name="6005"><span class="lineNum">    6005 </span>            :       (io_update_write_data_bits_entry_isCall),</a>
+<a name="6006"><span class="lineNum">    6006 </span>            :     .io_w_req_bits_data_2_entry_isRet</a>
+<a name="6007"><span class="lineNum">    6007 </span>            :       (io_update_write_data_bits_entry_isRet),</a>
+<a name="6008"><span class="lineNum">    6008 </span>            :     .io_w_req_bits_data_2_entry_isJalr</a>
+<a name="6009"><span class="lineNum">    6009 </span>            :       (io_update_write_data_bits_entry_isJalr),</a>
+<a name="6010"><span class="lineNum">    6010 </span>            :     .io_w_req_bits_data_2_entry_last_may_be_rvi_call</a>
+<a name="6011"><span class="lineNum">    6011 </span>            :       (io_update_write_data_bits_entry_last_may_be_rvi_call),</a>
+<a name="6012"><span class="lineNum">    6012 </span>            :     .io_w_req_bits_data_2_entry_always_taken_0</a>
+<a name="6013"><span class="lineNum">    6013 </span>            :       (io_update_write_data_bits_entry_always_taken_0),</a>
+<a name="6014"><span class="lineNum">    6014 </span>            :     .io_w_req_bits_data_2_entry_always_taken_1</a>
+<a name="6015"><span class="lineNum">    6015 </span>            :       (io_update_write_data_bits_entry_always_taken_1),</a>
+<a name="6016"><span class="lineNum">    6016 </span>            :     .io_w_req_bits_data_2_tag                        (io_update_write_data_bits_tag),</a>
+<a name="6017"><span class="lineNum">    6017 </span>            :     .io_w_req_bits_data_3_entry_valid</a>
+<a name="6018"><span class="lineNum">    6018 </span>            :       (io_update_write_data_bits_entry_valid),</a>
+<a name="6019"><span class="lineNum">    6019 </span>            :     .io_w_req_bits_data_3_entry_brSlots_0_offset</a>
+<a name="6020"><span class="lineNum">    6020 </span>            :       (io_update_write_data_bits_entry_brSlots_0_offset),</a>
+<a name="6021"><span class="lineNum">    6021 </span>            :     .io_w_req_bits_data_3_entry_brSlots_0_lower</a>
+<a name="6022"><span class="lineNum">    6022 </span>            :       (io_update_write_data_bits_entry_brSlots_0_lower),</a>
+<a name="6023"><span class="lineNum">    6023 </span>            :     .io_w_req_bits_data_3_entry_brSlots_0_tarStat</a>
+<a name="6024"><span class="lineNum">    6024 </span>            :       (io_update_write_data_bits_entry_brSlots_0_tarStat),</a>
+<a name="6025"><span class="lineNum">    6025 </span>            :     .io_w_req_bits_data_3_entry_brSlots_0_sharing</a>
+<a name="6026"><span class="lineNum">    6026 </span>            :       (io_update_write_data_bits_entry_brSlots_0_sharing),</a>
+<a name="6027"><span class="lineNum">    6027 </span>            :     .io_w_req_bits_data_3_entry_brSlots_0_valid</a>
+<a name="6028"><span class="lineNum">    6028 </span>            :       (io_update_write_data_bits_entry_brSlots_0_valid),</a>
+<a name="6029"><span class="lineNum">    6029 </span>            :     .io_w_req_bits_data_3_entry_tailSlot_offset</a>
+<a name="6030"><span class="lineNum">    6030 </span>            :       (io_update_write_data_bits_entry_tailSlot_offset),</a>
+<a name="6031"><span class="lineNum">    6031 </span>            :     .io_w_req_bits_data_3_entry_tailSlot_lower</a>
+<a name="6032"><span class="lineNum">    6032 </span>            :       (io_update_write_data_bits_entry_tailSlot_lower),</a>
+<a name="6033"><span class="lineNum">    6033 </span>            :     .io_w_req_bits_data_3_entry_tailSlot_tarStat</a>
+<a name="6034"><span class="lineNum">    6034 </span>            :       (io_update_write_data_bits_entry_tailSlot_tarStat),</a>
+<a name="6035"><span class="lineNum">    6035 </span>            :     .io_w_req_bits_data_3_entry_tailSlot_sharing</a>
+<a name="6036"><span class="lineNum">    6036 </span>            :       (io_update_write_data_bits_entry_tailSlot_sharing),</a>
+<a name="6037"><span class="lineNum">    6037 </span>            :     .io_w_req_bits_data_3_entry_tailSlot_valid</a>
+<a name="6038"><span class="lineNum">    6038 </span>            :       (io_update_write_data_bits_entry_tailSlot_valid),</a>
+<a name="6039"><span class="lineNum">    6039 </span>            :     .io_w_req_bits_data_3_entry_pftAddr</a>
+<a name="6040"><span class="lineNum">    6040 </span>            :       (io_update_write_data_bits_entry_pftAddr),</a>
+<a name="6041"><span class="lineNum">    6041 </span>            :     .io_w_req_bits_data_3_entry_carry</a>
+<a name="6042"><span class="lineNum">    6042 </span>            :       (io_update_write_data_bits_entry_carry),</a>
+<a name="6043"><span class="lineNum">    6043 </span>            :     .io_w_req_bits_data_3_entry_isCall</a>
+<a name="6044"><span class="lineNum">    6044 </span>            :       (io_update_write_data_bits_entry_isCall),</a>
+<a name="6045"><span class="lineNum">    6045 </span>            :     .io_w_req_bits_data_3_entry_isRet</a>
+<a name="6046"><span class="lineNum">    6046 </span>            :       (io_update_write_data_bits_entry_isRet),</a>
+<a name="6047"><span class="lineNum">    6047 </span>            :     .io_w_req_bits_data_3_entry_isJalr</a>
+<a name="6048"><span class="lineNum">    6048 </span>            :       (io_update_write_data_bits_entry_isJalr),</a>
+<a name="6049"><span class="lineNum">    6049 </span>            :     .io_w_req_bits_data_3_entry_last_may_be_rvi_call</a>
+<a name="6050"><span class="lineNum">    6050 </span>            :       (io_update_write_data_bits_entry_last_may_be_rvi_call),</a>
+<a name="6051"><span class="lineNum">    6051 </span>            :     .io_w_req_bits_data_3_entry_always_taken_0</a>
+<a name="6052"><span class="lineNum">    6052 </span>            :       (io_update_write_data_bits_entry_always_taken_0),</a>
+<a name="6053"><span class="lineNum">    6053 </span>            :     .io_w_req_bits_data_3_entry_always_taken_1</a>
+<a name="6054"><span class="lineNum">    6054 </span>            :       (io_update_write_data_bits_entry_always_taken_1),</a>
+<a name="6055"><span class="lineNum">    6055 </span>            :     .io_w_req_bits_data_3_tag                        (io_update_write_data_bits_tag),</a>
+<a name="6056"><span class="lineNum">    6056 </span>            :     .io_w_req_bits_waymask                           (4'h1 &lt;&lt; u_way)</a>
+<a name="6057"><span class="lineNum">    6057 </span>            :   );</a>
+<a name="6058"><span class="lineNum">    6058 </span>            :   assign io_read_resp_valid =</a>
+<a name="6059"><span class="lineNum">    6059 </span>            :     total_hits_0 &amp; pred_rdata_0_entry_valid | total_hits_1 &amp; pred_rdata_1_entry_valid</a>
+<a name="6060"><span class="lineNum">    6060 </span>            :     | total_hits_2 &amp; pred_rdata_2_entry_valid | total_hits_3 &amp; pred_rdata_3_entry_valid;</a>
+<a name="6061"><span class="lineNum">    6061 </span>            :   assign io_read_resp_brSlots_0_offset =</a>
+<a name="6062"><span class="lineNum">    6062 </span>            :     (total_hits_0</a>
+<a name="6063"><span class="lineNum">    6063 </span>            :        ? (pred_rdata_REG</a>
+<a name="6064"><span class="lineNum">    6064 </span>            :             ? _ftb_io_r_resp_data_0_entry_brSlots_0_offset</a>
+<a name="6065"><span class="lineNum">    6065 </span>            :             : pred_rdata_hold_data_0_entry_brSlots_0_offset)</a>
+<a name="6066"><span class="lineNum">    6066 </span>            :        : 4'h0)</a>
+<a name="6067"><span class="lineNum">    6067 </span>            :     | (total_hits_1</a>
+<a name="6068"><span class="lineNum">    6068 </span>            :          ? (pred_rdata_REG</a>
+<a name="6069"><span class="lineNum">    6069 </span>            :               ? _ftb_io_r_resp_data_1_entry_brSlots_0_offset</a>
+<a name="6070"><span class="lineNum">    6070 </span>            :               : pred_rdata_hold_data_1_entry_brSlots_0_offset)</a>
+<a name="6071"><span class="lineNum">    6071 </span>            :          : 4'h0)</a>
+<a name="6072"><span class="lineNum">    6072 </span>            :     | (total_hits_2</a>
+<a name="6073"><span class="lineNum">    6073 </span>            :          ? (pred_rdata_REG</a>
+<a name="6074"><span class="lineNum">    6074 </span>            :               ? _ftb_io_r_resp_data_2_entry_brSlots_0_offset</a>
+<a name="6075"><span class="lineNum">    6075 </span>            :               : pred_rdata_hold_data_2_entry_brSlots_0_offset)</a>
+<a name="6076"><span class="lineNum">    6076 </span>            :          : 4'h0)</a>
+<a name="6077"><span class="lineNum">    6077 </span>            :     | (total_hits_3</a>
+<a name="6078"><span class="lineNum">    6078 </span>            :          ? (pred_rdata_REG</a>
+<a name="6079"><span class="lineNum">    6079 </span>            :               ? _ftb_io_r_resp_data_3_entry_brSlots_0_offset</a>
+<a name="6080"><span class="lineNum">    6080 </span>            :               : pred_rdata_hold_data_3_entry_brSlots_0_offset)</a>
+<a name="6081"><span class="lineNum">    6081 </span>            :          : 4'h0);</a>
+<a name="6082"><span class="lineNum">    6082 </span>            :   assign io_read_resp_brSlots_0_lower =</a>
+<a name="6083"><span class="lineNum">    6083 </span>            :     (total_hits_0</a>
+<a name="6084"><span class="lineNum">    6084 </span>            :        ? (pred_rdata_REG</a>
+<a name="6085"><span class="lineNum">    6085 </span>            :             ? _ftb_io_r_resp_data_0_entry_brSlots_0_lower</a>
+<a name="6086"><span class="lineNum">    6086 </span>            :             : pred_rdata_hold_data_0_entry_brSlots_0_lower)</a>
+<a name="6087"><span class="lineNum">    6087 </span>            :        : 12'h0)</a>
+<a name="6088"><span class="lineNum">    6088 </span>            :     | (total_hits_1</a>
+<a name="6089"><span class="lineNum">    6089 </span>            :          ? (pred_rdata_REG</a>
+<a name="6090"><span class="lineNum">    6090 </span>            :               ? _ftb_io_r_resp_data_1_entry_brSlots_0_lower</a>
+<a name="6091"><span class="lineNum">    6091 </span>            :               : pred_rdata_hold_data_1_entry_brSlots_0_lower)</a>
+<a name="6092"><span class="lineNum">    6092 </span>            :          : 12'h0)</a>
+<a name="6093"><span class="lineNum">    6093 </span>            :     | (total_hits_2</a>
+<a name="6094"><span class="lineNum">    6094 </span>            :          ? (pred_rdata_REG</a>
+<a name="6095"><span class="lineNum">    6095 </span>            :               ? _ftb_io_r_resp_data_2_entry_brSlots_0_lower</a>
+<a name="6096"><span class="lineNum">    6096 </span>            :               : pred_rdata_hold_data_2_entry_brSlots_0_lower)</a>
+<a name="6097"><span class="lineNum">    6097 </span>            :          : 12'h0)</a>
+<a name="6098"><span class="lineNum">    6098 </span>            :     | (total_hits_3</a>
+<a name="6099"><span class="lineNum">    6099 </span>            :          ? (pred_rdata_REG</a>
+<a name="6100"><span class="lineNum">    6100 </span>            :               ? _ftb_io_r_resp_data_3_entry_brSlots_0_lower</a>
+<a name="6101"><span class="lineNum">    6101 </span>            :               : pred_rdata_hold_data_3_entry_brSlots_0_lower)</a>
+<a name="6102"><span class="lineNum">    6102 </span>            :          : 12'h0);</a>
+<a name="6103"><span class="lineNum">    6103 </span>            :   assign io_read_resp_brSlots_0_tarStat =</a>
+<a name="6104"><span class="lineNum">    6104 </span>            :     (total_hits_0</a>
+<a name="6105"><span class="lineNum">    6105 </span>            :        ? (pred_rdata_REG</a>
+<a name="6106"><span class="lineNum">    6106 </span>            :             ? _ftb_io_r_resp_data_0_entry_brSlots_0_tarStat</a>
+<a name="6107"><span class="lineNum">    6107 </span>            :             : pred_rdata_hold_data_0_entry_brSlots_0_tarStat)</a>
+<a name="6108"><span class="lineNum">    6108 </span>            :        : 2'h0)</a>
+<a name="6109"><span class="lineNum">    6109 </span>            :     | (total_hits_1</a>
+<a name="6110"><span class="lineNum">    6110 </span>            :          ? (pred_rdata_REG</a>
+<a name="6111"><span class="lineNum">    6111 </span>            :               ? _ftb_io_r_resp_data_1_entry_brSlots_0_tarStat</a>
+<a name="6112"><span class="lineNum">    6112 </span>            :               : pred_rdata_hold_data_1_entry_brSlots_0_tarStat)</a>
+<a name="6113"><span class="lineNum">    6113 </span>            :          : 2'h0)</a>
+<a name="6114"><span class="lineNum">    6114 </span>            :     | (total_hits_2</a>
+<a name="6115"><span class="lineNum">    6115 </span>            :          ? (pred_rdata_REG</a>
+<a name="6116"><span class="lineNum">    6116 </span>            :               ? _ftb_io_r_resp_data_2_entry_brSlots_0_tarStat</a>
+<a name="6117"><span class="lineNum">    6117 </span>            :               : pred_rdata_hold_data_2_entry_brSlots_0_tarStat)</a>
+<a name="6118"><span class="lineNum">    6118 </span>            :          : 2'h0)</a>
+<a name="6119"><span class="lineNum">    6119 </span>            :     | (total_hits_3</a>
+<a name="6120"><span class="lineNum">    6120 </span>            :          ? (pred_rdata_REG</a>
+<a name="6121"><span class="lineNum">    6121 </span>            :               ? _ftb_io_r_resp_data_3_entry_brSlots_0_tarStat</a>
+<a name="6122"><span class="lineNum">    6122 </span>            :               : pred_rdata_hold_data_3_entry_brSlots_0_tarStat)</a>
+<a name="6123"><span class="lineNum">    6123 </span>            :          : 2'h0);</a>
+<a name="6124"><span class="lineNum">    6124 </span>            :   assign io_read_resp_brSlots_0_sharing =</a>
+<a name="6125"><span class="lineNum">    6125 </span>            :     total_hits_0</a>
+<a name="6126"><span class="lineNum">    6126 </span>            :     &amp; (pred_rdata_REG</a>
+<a name="6127"><span class="lineNum">    6127 </span>            :          ? _ftb_io_r_resp_data_0_entry_brSlots_0_sharing</a>
+<a name="6128"><span class="lineNum">    6128 </span>            :          : pred_rdata_hold_data_0_entry_brSlots_0_sharing) | total_hits_1</a>
+<a name="6129"><span class="lineNum">    6129 </span>            :     &amp; (pred_rdata_REG</a>
+<a name="6130"><span class="lineNum">    6130 </span>            :          ? _ftb_io_r_resp_data_1_entry_brSlots_0_sharing</a>
+<a name="6131"><span class="lineNum">    6131 </span>            :          : pred_rdata_hold_data_1_entry_brSlots_0_sharing) | total_hits_2</a>
+<a name="6132"><span class="lineNum">    6132 </span>            :     &amp; (pred_rdata_REG</a>
+<a name="6133"><span class="lineNum">    6133 </span>            :          ? _ftb_io_r_resp_data_2_entry_brSlots_0_sharing</a>
+<a name="6134"><span class="lineNum">    6134 </span>            :          : pred_rdata_hold_data_2_entry_brSlots_0_sharing) | total_hits_3</a>
+<a name="6135"><span class="lineNum">    6135 </span>            :     &amp; (pred_rdata_REG</a>
+<a name="6136"><span class="lineNum">    6136 </span>            :          ? _ftb_io_r_resp_data_3_entry_brSlots_0_sharing</a>
+<a name="6137"><span class="lineNum">    6137 </span>            :          : pred_rdata_hold_data_3_entry_brSlots_0_sharing);</a>
+<a name="6138"><span class="lineNum">    6138 </span>            :   assign io_read_resp_brSlots_0_valid =</a>
+<a name="6139"><span class="lineNum">    6139 </span>            :     total_hits_0</a>
+<a name="6140"><span class="lineNum">    6140 </span>            :     &amp; (pred_rdata_REG</a>
+<a name="6141"><span class="lineNum">    6141 </span>            :          ? _ftb_io_r_resp_data_0_entry_brSlots_0_valid</a>
+<a name="6142"><span class="lineNum">    6142 </span>            :          : pred_rdata_hold_data_0_entry_brSlots_0_valid) | total_hits_1</a>
+<a name="6143"><span class="lineNum">    6143 </span>            :     &amp; (pred_rdata_REG</a>
+<a name="6144"><span class="lineNum">    6144 </span>            :          ? _ftb_io_r_resp_data_1_entry_brSlots_0_valid</a>
+<a name="6145"><span class="lineNum">    6145 </span>            :          : pred_rdata_hold_data_1_entry_brSlots_0_valid) | total_hits_2</a>
+<a name="6146"><span class="lineNum">    6146 </span>            :     &amp; (pred_rdata_REG</a>
+<a name="6147"><span class="lineNum">    6147 </span>            :          ? _ftb_io_r_resp_data_2_entry_brSlots_0_valid</a>
+<a name="6148"><span class="lineNum">    6148 </span>            :          : pred_rdata_hold_data_2_entry_brSlots_0_valid) | total_hits_3</a>
+<a name="6149"><span class="lineNum">    6149 </span>            :     &amp; (pred_rdata_REG</a>
+<a name="6150"><span class="lineNum">    6150 </span>            :          ? _ftb_io_r_resp_data_3_entry_brSlots_0_valid</a>
+<a name="6151"><span class="lineNum">    6151 </span>            :          : pred_rdata_hold_data_3_entry_brSlots_0_valid);</a>
+<a name="6152"><span class="lineNum">    6152 </span>            :   assign io_read_resp_tailSlot_offset =</a>
+<a name="6153"><span class="lineNum">    6153 </span>            :     (total_hits_0</a>
+<a name="6154"><span class="lineNum">    6154 </span>            :        ? (pred_rdata_REG</a>
+<a name="6155"><span class="lineNum">    6155 </span>            :             ? _ftb_io_r_resp_data_0_entry_tailSlot_offset</a>
+<a name="6156"><span class="lineNum">    6156 </span>            :             : pred_rdata_hold_data_0_entry_tailSlot_offset)</a>
+<a name="6157"><span class="lineNum">    6157 </span>            :        : 4'h0)</a>
+<a name="6158"><span class="lineNum">    6158 </span>            :     | (total_hits_1</a>
+<a name="6159"><span class="lineNum">    6159 </span>            :          ? (pred_rdata_REG</a>
+<a name="6160"><span class="lineNum">    6160 </span>            :               ? _ftb_io_r_resp_data_1_entry_tailSlot_offset</a>
+<a name="6161"><span class="lineNum">    6161 </span>            :               : pred_rdata_hold_data_1_entry_tailSlot_offset)</a>
+<a name="6162"><span class="lineNum">    6162 </span>            :          : 4'h0)</a>
+<a name="6163"><span class="lineNum">    6163 </span>            :     | (total_hits_2</a>
+<a name="6164"><span class="lineNum">    6164 </span>            :          ? (pred_rdata_REG</a>
+<a name="6165"><span class="lineNum">    6165 </span>            :               ? _ftb_io_r_resp_data_2_entry_tailSlot_offset</a>
+<a name="6166"><span class="lineNum">    6166 </span>            :               : pred_rdata_hold_data_2_entry_tailSlot_offset)</a>
+<a name="6167"><span class="lineNum">    6167 </span>            :          : 4'h0)</a>
+<a name="6168"><span class="lineNum">    6168 </span>            :     | (total_hits_3</a>
+<a name="6169"><span class="lineNum">    6169 </span>            :          ? (pred_rdata_REG</a>
+<a name="6170"><span class="lineNum">    6170 </span>            :               ? _ftb_io_r_resp_data_3_entry_tailSlot_offset</a>
+<a name="6171"><span class="lineNum">    6171 </span>            :               : pred_rdata_hold_data_3_entry_tailSlot_offset)</a>
+<a name="6172"><span class="lineNum">    6172 </span>            :          : 4'h0);</a>
+<a name="6173"><span class="lineNum">    6173 </span>            :   assign io_read_resp_tailSlot_lower =</a>
+<a name="6174"><span class="lineNum">    6174 </span>            :     (total_hits_0</a>
+<a name="6175"><span class="lineNum">    6175 </span>            :        ? (pred_rdata_REG</a>
+<a name="6176"><span class="lineNum">    6176 </span>            :             ? _ftb_io_r_resp_data_0_entry_tailSlot_lower</a>
+<a name="6177"><span class="lineNum">    6177 </span>            :             : pred_rdata_hold_data_0_entry_tailSlot_lower)</a>
+<a name="6178"><span class="lineNum">    6178 </span>            :        : 20'h0)</a>
+<a name="6179"><span class="lineNum">    6179 </span>            :     | (total_hits_1</a>
+<a name="6180"><span class="lineNum">    6180 </span>            :          ? (pred_rdata_REG</a>
+<a name="6181"><span class="lineNum">    6181 </span>            :               ? _ftb_io_r_resp_data_1_entry_tailSlot_lower</a>
+<a name="6182"><span class="lineNum">    6182 </span>            :               : pred_rdata_hold_data_1_entry_tailSlot_lower)</a>
+<a name="6183"><span class="lineNum">    6183 </span>            :          : 20'h0)</a>
+<a name="6184"><span class="lineNum">    6184 </span>            :     | (total_hits_2</a>
+<a name="6185"><span class="lineNum">    6185 </span>            :          ? (pred_rdata_REG</a>
+<a name="6186"><span class="lineNum">    6186 </span>            :               ? _ftb_io_r_resp_data_2_entry_tailSlot_lower</a>
+<a name="6187"><span class="lineNum">    6187 </span>            :               : pred_rdata_hold_data_2_entry_tailSlot_lower)</a>
+<a name="6188"><span class="lineNum">    6188 </span>            :          : 20'h0)</a>
+<a name="6189"><span class="lineNum">    6189 </span>            :     | (total_hits_3</a>
+<a name="6190"><span class="lineNum">    6190 </span>            :          ? (pred_rdata_REG</a>
+<a name="6191"><span class="lineNum">    6191 </span>            :               ? _ftb_io_r_resp_data_3_entry_tailSlot_lower</a>
+<a name="6192"><span class="lineNum">    6192 </span>            :               : pred_rdata_hold_data_3_entry_tailSlot_lower)</a>
+<a name="6193"><span class="lineNum">    6193 </span>            :          : 20'h0);</a>
+<a name="6194"><span class="lineNum">    6194 </span>            :   assign io_read_resp_tailSlot_tarStat =</a>
+<a name="6195"><span class="lineNum">    6195 </span>            :     (total_hits_0</a>
+<a name="6196"><span class="lineNum">    6196 </span>            :        ? (pred_rdata_REG</a>
+<a name="6197"><span class="lineNum">    6197 </span>            :             ? _ftb_io_r_resp_data_0_entry_tailSlot_tarStat</a>
+<a name="6198"><span class="lineNum">    6198 </span>            :             : pred_rdata_hold_data_0_entry_tailSlot_tarStat)</a>
+<a name="6199"><span class="lineNum">    6199 </span>            :        : 2'h0)</a>
+<a name="6200"><span class="lineNum">    6200 </span>            :     | (total_hits_1</a>
+<a name="6201"><span class="lineNum">    6201 </span>            :          ? (pred_rdata_REG</a>
+<a name="6202"><span class="lineNum">    6202 </span>            :               ? _ftb_io_r_resp_data_1_entry_tailSlot_tarStat</a>
+<a name="6203"><span class="lineNum">    6203 </span>            :               : pred_rdata_hold_data_1_entry_tailSlot_tarStat)</a>
+<a name="6204"><span class="lineNum">    6204 </span>            :          : 2'h0)</a>
+<a name="6205"><span class="lineNum">    6205 </span>            :     | (total_hits_2</a>
+<a name="6206"><span class="lineNum">    6206 </span>            :          ? (pred_rdata_REG</a>
+<a name="6207"><span class="lineNum">    6207 </span>            :               ? _ftb_io_r_resp_data_2_entry_tailSlot_tarStat</a>
+<a name="6208"><span class="lineNum">    6208 </span>            :               : pred_rdata_hold_data_2_entry_tailSlot_tarStat)</a>
+<a name="6209"><span class="lineNum">    6209 </span>            :          : 2'h0)</a>
+<a name="6210"><span class="lineNum">    6210 </span>            :     | (total_hits_3</a>
+<a name="6211"><span class="lineNum">    6211 </span>            :          ? (pred_rdata_REG</a>
+<a name="6212"><span class="lineNum">    6212 </span>            :               ? _ftb_io_r_resp_data_3_entry_tailSlot_tarStat</a>
+<a name="6213"><span class="lineNum">    6213 </span>            :               : pred_rdata_hold_data_3_entry_tailSlot_tarStat)</a>
+<a name="6214"><span class="lineNum">    6214 </span>            :          : 2'h0);</a>
+<a name="6215"><span class="lineNum">    6215 </span>            :   assign io_read_resp_tailSlot_sharing =</a>
+<a name="6216"><span class="lineNum">    6216 </span>            :     total_hits_0</a>
+<a name="6217"><span class="lineNum">    6217 </span>            :     &amp; (pred_rdata_REG</a>
+<a name="6218"><span class="lineNum">    6218 </span>            :          ? _ftb_io_r_resp_data_0_entry_tailSlot_sharing</a>
+<a name="6219"><span class="lineNum">    6219 </span>            :          : pred_rdata_hold_data_0_entry_tailSlot_sharing) | total_hits_1</a>
+<a name="6220"><span class="lineNum">    6220 </span>            :     &amp; (pred_rdata_REG</a>
+<a name="6221"><span class="lineNum">    6221 </span>            :          ? _ftb_io_r_resp_data_1_entry_tailSlot_sharing</a>
+<a name="6222"><span class="lineNum">    6222 </span>            :          : pred_rdata_hold_data_1_entry_tailSlot_sharing) | total_hits_2</a>
+<a name="6223"><span class="lineNum">    6223 </span>            :     &amp; (pred_rdata_REG</a>
+<a name="6224"><span class="lineNum">    6224 </span>            :          ? _ftb_io_r_resp_data_2_entry_tailSlot_sharing</a>
+<a name="6225"><span class="lineNum">    6225 </span>            :          : pred_rdata_hold_data_2_entry_tailSlot_sharing) | total_hits_3</a>
+<a name="6226"><span class="lineNum">    6226 </span>            :     &amp; (pred_rdata_REG</a>
+<a name="6227"><span class="lineNum">    6227 </span>            :          ? _ftb_io_r_resp_data_3_entry_tailSlot_sharing</a>
+<a name="6228"><span class="lineNum">    6228 </span>            :          : pred_rdata_hold_data_3_entry_tailSlot_sharing);</a>
+<a name="6229"><span class="lineNum">    6229 </span>            :   assign io_read_resp_tailSlot_valid =</a>
+<a name="6230"><span class="lineNum">    6230 </span>            :     total_hits_0</a>
+<a name="6231"><span class="lineNum">    6231 </span>            :     &amp; (pred_rdata_REG</a>
+<a name="6232"><span class="lineNum">    6232 </span>            :          ? _ftb_io_r_resp_data_0_entry_tailSlot_valid</a>
+<a name="6233"><span class="lineNum">    6233 </span>            :          : pred_rdata_hold_data_0_entry_tailSlot_valid) | total_hits_1</a>
+<a name="6234"><span class="lineNum">    6234 </span>            :     &amp; (pred_rdata_REG</a>
+<a name="6235"><span class="lineNum">    6235 </span>            :          ? _ftb_io_r_resp_data_1_entry_tailSlot_valid</a>
+<a name="6236"><span class="lineNum">    6236 </span>            :          : pred_rdata_hold_data_1_entry_tailSlot_valid) | total_hits_2</a>
+<a name="6237"><span class="lineNum">    6237 </span>            :     &amp; (pred_rdata_REG</a>
+<a name="6238"><span class="lineNum">    6238 </span>            :          ? _ftb_io_r_resp_data_2_entry_tailSlot_valid</a>
+<a name="6239"><span class="lineNum">    6239 </span>            :          : pred_rdata_hold_data_2_entry_tailSlot_valid) | total_hits_3</a>
+<a name="6240"><span class="lineNum">    6240 </span>            :     &amp; (pred_rdata_REG</a>
+<a name="6241"><span class="lineNum">    6241 </span>            :          ? _ftb_io_r_resp_data_3_entry_tailSlot_valid</a>
+<a name="6242"><span class="lineNum">    6242 </span>            :          : pred_rdata_hold_data_3_entry_tailSlot_valid);</a>
+<a name="6243"><span class="lineNum">    6243 </span>            :   assign io_read_resp_pftAddr =</a>
+<a name="6244"><span class="lineNum">    6244 </span>            :     (total_hits_0</a>
+<a name="6245"><span class="lineNum">    6245 </span>            :        ? (pred_rdata_REG</a>
+<a name="6246"><span class="lineNum">    6246 </span>            :             ? _ftb_io_r_resp_data_0_entry_pftAddr</a>
+<a name="6247"><span class="lineNum">    6247 </span>            :             : pred_rdata_hold_data_0_entry_pftAddr)</a>
+<a name="6248"><span class="lineNum">    6248 </span>            :        : 4'h0)</a>
+<a name="6249"><span class="lineNum">    6249 </span>            :     | (total_hits_1</a>
+<a name="6250"><span class="lineNum">    6250 </span>            :          ? (pred_rdata_REG</a>
+<a name="6251"><span class="lineNum">    6251 </span>            :               ? _ftb_io_r_resp_data_1_entry_pftAddr</a>
+<a name="6252"><span class="lineNum">    6252 </span>            :               : pred_rdata_hold_data_1_entry_pftAddr)</a>
+<a name="6253"><span class="lineNum">    6253 </span>            :          : 4'h0)</a>
+<a name="6254"><span class="lineNum">    6254 </span>            :     | (total_hits_2</a>
+<a name="6255"><span class="lineNum">    6255 </span>            :          ? (pred_rdata_REG</a>
+<a name="6256"><span class="lineNum">    6256 </span>            :               ? _ftb_io_r_resp_data_2_entry_pftAddr</a>
+<a name="6257"><span class="lineNum">    6257 </span>            :               : pred_rdata_hold_data_2_entry_pftAddr)</a>
+<a name="6258"><span class="lineNum">    6258 </span>            :          : 4'h0)</a>
+<a name="6259"><span class="lineNum">    6259 </span>            :     | (total_hits_3</a>
+<a name="6260"><span class="lineNum">    6260 </span>            :          ? (pred_rdata_REG</a>
+<a name="6261"><span class="lineNum">    6261 </span>            :               ? _ftb_io_r_resp_data_3_entry_pftAddr</a>
+<a name="6262"><span class="lineNum">    6262 </span>            :               : pred_rdata_hold_data_3_entry_pftAddr)</a>
+<a name="6263"><span class="lineNum">    6263 </span>            :          : 4'h0);</a>
+<a name="6264"><span class="lineNum">    6264 </span>            :   assign io_read_resp_carry =</a>
+<a name="6265"><span class="lineNum">    6265 </span>            :     total_hits_0</a>
+<a name="6266"><span class="lineNum">    6266 </span>            :     &amp; (pred_rdata_REG</a>
+<a name="6267"><span class="lineNum">    6267 </span>            :          ? _ftb_io_r_resp_data_0_entry_carry</a>
+<a name="6268"><span class="lineNum">    6268 </span>            :          : pred_rdata_hold_data_0_entry_carry) | total_hits_1</a>
+<a name="6269"><span class="lineNum">    6269 </span>            :     &amp; (pred_rdata_REG</a>
+<a name="6270"><span class="lineNum">    6270 </span>            :          ? _ftb_io_r_resp_data_1_entry_carry</a>
+<a name="6271"><span class="lineNum">    6271 </span>            :          : pred_rdata_hold_data_1_entry_carry) | total_hits_2</a>
+<a name="6272"><span class="lineNum">    6272 </span>            :     &amp; (pred_rdata_REG</a>
+<a name="6273"><span class="lineNum">    6273 </span>            :          ? _ftb_io_r_resp_data_2_entry_carry</a>
+<a name="6274"><span class="lineNum">    6274 </span>            :          : pred_rdata_hold_data_2_entry_carry) | total_hits_3</a>
+<a name="6275"><span class="lineNum">    6275 </span>            :     &amp; (pred_rdata_REG</a>
+<a name="6276"><span class="lineNum">    6276 </span>            :          ? _ftb_io_r_resp_data_3_entry_carry</a>
+<a name="6277"><span class="lineNum">    6277 </span>            :          : pred_rdata_hold_data_3_entry_carry);</a>
+<a name="6278"><span class="lineNum">    6278 </span>            :   assign io_read_resp_isCall =</a>
+<a name="6279"><span class="lineNum">    6279 </span>            :     total_hits_0</a>
+<a name="6280"><span class="lineNum">    6280 </span>            :     &amp; (pred_rdata_REG</a>
+<a name="6281"><span class="lineNum">    6281 </span>            :          ? _ftb_io_r_resp_data_0_entry_isCall</a>
+<a name="6282"><span class="lineNum">    6282 </span>            :          : pred_rdata_hold_data_0_entry_isCall) | total_hits_1</a>
+<a name="6283"><span class="lineNum">    6283 </span>            :     &amp; (pred_rdata_REG</a>
+<a name="6284"><span class="lineNum">    6284 </span>            :          ? _ftb_io_r_resp_data_1_entry_isCall</a>
+<a name="6285"><span class="lineNum">    6285 </span>            :          : pred_rdata_hold_data_1_entry_isCall) | total_hits_2</a>
+<a name="6286"><span class="lineNum">    6286 </span>            :     &amp; (pred_rdata_REG</a>
+<a name="6287"><span class="lineNum">    6287 </span>            :          ? _ftb_io_r_resp_data_2_entry_isCall</a>
+<a name="6288"><span class="lineNum">    6288 </span>            :          : pred_rdata_hold_data_2_entry_isCall) | total_hits_3</a>
+<a name="6289"><span class="lineNum">    6289 </span>            :     &amp; (pred_rdata_REG</a>
+<a name="6290"><span class="lineNum">    6290 </span>            :          ? _ftb_io_r_resp_data_3_entry_isCall</a>
+<a name="6291"><span class="lineNum">    6291 </span>            :          : pred_rdata_hold_data_3_entry_isCall);</a>
+<a name="6292"><span class="lineNum">    6292 </span>            :   assign io_read_resp_isRet =</a>
+<a name="6293"><span class="lineNum">    6293 </span>            :     total_hits_0</a>
+<a name="6294"><span class="lineNum">    6294 </span>            :     &amp; (pred_rdata_REG</a>
+<a name="6295"><span class="lineNum">    6295 </span>            :          ? _ftb_io_r_resp_data_0_entry_isRet</a>
+<a name="6296"><span class="lineNum">    6296 </span>            :          : pred_rdata_hold_data_0_entry_isRet) | total_hits_1</a>
+<a name="6297"><span class="lineNum">    6297 </span>            :     &amp; (pred_rdata_REG</a>
+<a name="6298"><span class="lineNum">    6298 </span>            :          ? _ftb_io_r_resp_data_1_entry_isRet</a>
+<a name="6299"><span class="lineNum">    6299 </span>            :          : pred_rdata_hold_data_1_entry_isRet) | total_hits_2</a>
+<a name="6300"><span class="lineNum">    6300 </span>            :     &amp; (pred_rdata_REG</a>
+<a name="6301"><span class="lineNum">    6301 </span>            :          ? _ftb_io_r_resp_data_2_entry_isRet</a>
+<a name="6302"><span class="lineNum">    6302 </span>            :          : pred_rdata_hold_data_2_entry_isRet) | total_hits_3</a>
+<a name="6303"><span class="lineNum">    6303 </span>            :     &amp; (pred_rdata_REG</a>
+<a name="6304"><span class="lineNum">    6304 </span>            :          ? _ftb_io_r_resp_data_3_entry_isRet</a>
+<a name="6305"><span class="lineNum">    6305 </span>            :          : pred_rdata_hold_data_3_entry_isRet);</a>
+<a name="6306"><span class="lineNum">    6306 </span>            :   assign io_read_resp_isJalr =</a>
+<a name="6307"><span class="lineNum">    6307 </span>            :     total_hits_0</a>
+<a name="6308"><span class="lineNum">    6308 </span>            :     &amp; (pred_rdata_REG</a>
+<a name="6309"><span class="lineNum">    6309 </span>            :          ? _ftb_io_r_resp_data_0_entry_isJalr</a>
+<a name="6310"><span class="lineNum">    6310 </span>            :          : pred_rdata_hold_data_0_entry_isJalr) | total_hits_1</a>
+<a name="6311"><span class="lineNum">    6311 </span>            :     &amp; (pred_rdata_REG</a>
+<a name="6312"><span class="lineNum">    6312 </span>            :          ? _ftb_io_r_resp_data_1_entry_isJalr</a>
+<a name="6313"><span class="lineNum">    6313 </span>            :          : pred_rdata_hold_data_1_entry_isJalr) | total_hits_2</a>
+<a name="6314"><span class="lineNum">    6314 </span>            :     &amp; (pred_rdata_REG</a>
+<a name="6315"><span class="lineNum">    6315 </span>            :          ? _ftb_io_r_resp_data_2_entry_isJalr</a>
+<a name="6316"><span class="lineNum">    6316 </span>            :          : pred_rdata_hold_data_2_entry_isJalr) | total_hits_3</a>
+<a name="6317"><span class="lineNum">    6317 </span>            :     &amp; (pred_rdata_REG</a>
+<a name="6318"><span class="lineNum">    6318 </span>            :          ? _ftb_io_r_resp_data_3_entry_isJalr</a>
+<a name="6319"><span class="lineNum">    6319 </span>            :          : pred_rdata_hold_data_3_entry_isJalr);</a>
+<a name="6320"><span class="lineNum">    6320 </span>            :   assign io_read_resp_last_may_be_rvi_call =</a>
+<a name="6321"><span class="lineNum">    6321 </span>            :     total_hits_0</a>
+<a name="6322"><span class="lineNum">    6322 </span>            :     &amp; (pred_rdata_REG</a>
+<a name="6323"><span class="lineNum">    6323 </span>            :          ? _ftb_io_r_resp_data_0_entry_last_may_be_rvi_call</a>
+<a name="6324"><span class="lineNum">    6324 </span>            :          : pred_rdata_hold_data_0_entry_last_may_be_rvi_call) | total_hits_1</a>
+<a name="6325"><span class="lineNum">    6325 </span>            :     &amp; (pred_rdata_REG</a>
+<a name="6326"><span class="lineNum">    6326 </span>            :          ? _ftb_io_r_resp_data_1_entry_last_may_be_rvi_call</a>
+<a name="6327"><span class="lineNum">    6327 </span>            :          : pred_rdata_hold_data_1_entry_last_may_be_rvi_call) | total_hits_2</a>
+<a name="6328"><span class="lineNum">    6328 </span>            :     &amp; (pred_rdata_REG</a>
+<a name="6329"><span class="lineNum">    6329 </span>            :          ? _ftb_io_r_resp_data_2_entry_last_may_be_rvi_call</a>
+<a name="6330"><span class="lineNum">    6330 </span>            :          : pred_rdata_hold_data_2_entry_last_may_be_rvi_call) | total_hits_3</a>
+<a name="6331"><span class="lineNum">    6331 </span>            :     &amp; (pred_rdata_REG</a>
+<a name="6332"><span class="lineNum">    6332 </span>            :          ? _ftb_io_r_resp_data_3_entry_last_may_be_rvi_call</a>
+<a name="6333"><span class="lineNum">    6333 </span>            :          : pred_rdata_hold_data_3_entry_last_may_be_rvi_call);</a>
+<a name="6334"><span class="lineNum">    6334 </span>            :   assign io_read_resp_always_taken_0 =</a>
+<a name="6335"><span class="lineNum">    6335 </span>            :     total_hits_0</a>
+<a name="6336"><span class="lineNum">    6336 </span>            :     &amp; (pred_rdata_REG</a>
+<a name="6337"><span class="lineNum">    6337 </span>            :          ? _ftb_io_r_resp_data_0_entry_always_taken_0</a>
+<a name="6338"><span class="lineNum">    6338 </span>            :          : pred_rdata_hold_data_0_entry_always_taken_0) | total_hits_1</a>
+<a name="6339"><span class="lineNum">    6339 </span>            :     &amp; (pred_rdata_REG</a>
+<a name="6340"><span class="lineNum">    6340 </span>            :          ? _ftb_io_r_resp_data_1_entry_always_taken_0</a>
+<a name="6341"><span class="lineNum">    6341 </span>            :          : pred_rdata_hold_data_1_entry_always_taken_0) | total_hits_2</a>
+<a name="6342"><span class="lineNum">    6342 </span>            :     &amp; (pred_rdata_REG</a>
+<a name="6343"><span class="lineNum">    6343 </span>            :          ? _ftb_io_r_resp_data_2_entry_always_taken_0</a>
+<a name="6344"><span class="lineNum">    6344 </span>            :          : pred_rdata_hold_data_2_entry_always_taken_0) | total_hits_3</a>
+<a name="6345"><span class="lineNum">    6345 </span>            :     &amp; (pred_rdata_REG</a>
+<a name="6346"><span class="lineNum">    6346 </span>            :          ? _ftb_io_r_resp_data_3_entry_always_taken_0</a>
+<a name="6347"><span class="lineNum">    6347 </span>            :          : pred_rdata_hold_data_3_entry_always_taken_0);</a>
+<a name="6348"><span class="lineNum">    6348 </span>            :   assign io_read_resp_always_taken_1 =</a>
+<a name="6349"><span class="lineNum">    6349 </span>            :     total_hits_0</a>
+<a name="6350"><span class="lineNum">    6350 </span>            :     &amp; (pred_rdata_REG</a>
+<a name="6351"><span class="lineNum">    6351 </span>            :          ? _ftb_io_r_resp_data_0_entry_always_taken_1</a>
+<a name="6352"><span class="lineNum">    6352 </span>            :          : pred_rdata_hold_data_0_entry_always_taken_1) | total_hits_1</a>
+<a name="6353"><span class="lineNum">    6353 </span>            :     &amp; (pred_rdata_REG</a>
+<a name="6354"><span class="lineNum">    6354 </span>            :          ? _ftb_io_r_resp_data_1_entry_always_taken_1</a>
+<a name="6355"><span class="lineNum">    6355 </span>            :          : pred_rdata_hold_data_1_entry_always_taken_1) | total_hits_2</a>
+<a name="6356"><span class="lineNum">    6356 </span>            :     &amp; (pred_rdata_REG</a>
+<a name="6357"><span class="lineNum">    6357 </span>            :          ? _ftb_io_r_resp_data_2_entry_always_taken_1</a>
+<a name="6358"><span class="lineNum">    6358 </span>            :          : pred_rdata_hold_data_2_entry_always_taken_1) | total_hits_3</a>
+<a name="6359"><span class="lineNum">    6359 </span>            :     &amp; (pred_rdata_REG</a>
+<a name="6360"><span class="lineNum">    6360 </span>            :          ? _ftb_io_r_resp_data_3_entry_always_taken_1</a>
+<a name="6361"><span class="lineNum">    6361 </span>            :          : pred_rdata_hold_data_3_entry_always_taken_1);</a>
+<a name="6362"><span class="lineNum">    6362 </span>            :   assign io_read_hits_valid = hit;</a>
+<a name="6363"><span class="lineNum">    6363 </span>            :   assign io_read_hits_bits = hit_way;</a>
+<a name="6364"><span class="lineNum">    6364 </span>            :   assign io_update_hits_valid =</a>
+<a name="6365"><span class="lineNum">    6365 </span>            :     _ftb_io_r_resp_data_0_tag == u_req_tag &amp; _ftb_io_r_resp_data_0_entry_valid</a>
+<a name="6366"><span class="lineNum">    6366 </span>            :     &amp; u_total_hits_REG | u_total_hits_1 | u_total_hits_2 | u_total_hits_3;</a>
+<a name="6367"><span class="lineNum">    6367 </span>            :   assign io_update_hits_bits =</a>
+<a name="6368"><span class="lineNum">    6368 </span>            :     {|{u_total_hits_3, u_total_hits_2}, u_total_hits_3 | u_total_hits_1};</a>
+<a name="6369"><span class="lineNum">    6369 </span>            : endmodule</a>
+<a name="6370"><span class="lineNum">    6370 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FauFTB.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FauFTB.sv.func-sort-c.html
new file mode 100644
index 0000000..e620a4c
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FauFTB.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/FauFTB.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - FauFTB.sv<span style="font-size: 80%;"> (<a href="FauFTB.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">648</td>
+            <td class="headerCovTableEntry">1058</td>
+            <td class="headerCovTableEntryLo">61.2 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="FauFTB.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FauFTB.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FauFTB.sv.func.html
new file mode 100644
index 0000000..c05f544
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FauFTB.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/FauFTB.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - FauFTB.sv<span style="font-size: 80%;"> (<a href="FauFTB.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">648</td>
+            <td class="headerCovTableEntry">1058</td>
+            <td class="headerCovTableEntryLo">61.2 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="FauFTB.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FauFTB.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FauFTB.sv.gcov.html
new file mode 100644
index 0000000..d0a7e70
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FauFTB.sv.gcov.html
@@ -0,0 +1,4831 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/FauFTB.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - FauFTB.sv<span style="font-size: 80%;"> (source / <a href="FauFTB.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">648</td>
+            <td class="headerCovTableEntry">1058</td>
+            <td class="headerCovTableEntryLo">61.2 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : module FauFTB(</a>
+<a name="59"><span class="lineNum">      59 </span><span class="lineCov">     127786 :   input          clock,</span></a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">         62 :   input          reset,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">       1105 :   input  [35:0]  io_reset_vector,</span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">      10337 :   input  [40:0]  io_in_bits_s0_pc_0,</span></a>
+<a name="63"><span class="lineNum">      63 </span><span class="lineCov">      10224 :   input  [40:0]  io_in_bits_s0_pc_1,</span></a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">      10251 :   input  [40:0]  io_in_bits_s0_pc_2,</span></a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">      35066 :   input  [40:0]  io_in_bits_s0_pc_3,</span></a>
+<a name="66"><span class="lineNum">      66 </span><span class="lineCov">       9878 :   output [40:0]  io_out_s1_pc_0,</span></a>
+<a name="67"><span class="lineNum">      67 </span><span class="lineCov">       9918 :   output [40:0]  io_out_s1_pc_1,</span></a>
+<a name="68"><span class="lineNum">      68 </span><span class="lineCov">       9857 :   output [40:0]  io_out_s1_pc_2,</span></a>
+<a name="69"><span class="lineNum">      69 </span><span class="lineCov">       9933 :   output [40:0]  io_out_s1_pc_3,</span></a>
+<a name="70"><span class="lineNum">      70 </span><span class="lineCov">         15 :   output         io_out_s1_full_pred_0_br_taken_mask_0,</span></a>
+<a name="71"><span class="lineNum">      71 </span><span class="lineCov">         17 :   output         io_out_s1_full_pred_0_br_taken_mask_1,</span></a>
+<a name="72"><span class="lineNum">      72 </span><span class="lineCov">         12 :   output         io_out_s1_full_pred_0_slot_valids_0,</span></a>
+<a name="73"><span class="lineNum">      73 </span><span class="lineCov">          9 :   output         io_out_s1_full_pred_0_slot_valids_1,</span></a>
+<a name="74"><span class="lineNum">      74 </span><span class="lineCov">        615 :   output [40:0]  io_out_s1_full_pred_0_targets_0,</span></a>
+<a name="75"><span class="lineNum">      75 </span><span class="lineCov">        574 :   output [40:0]  io_out_s1_full_pred_0_targets_1,</span></a>
+<a name="76"><span class="lineNum">      76 </span><span class="lineCov">         57 :   output [3:0]   io_out_s1_full_pred_0_offsets_0,</span></a>
+<a name="77"><span class="lineNum">      77 </span><span class="lineCov">         64 :   output [3:0]   io_out_s1_full_pred_0_offsets_1,</span></a>
+<a name="78"><span class="lineNum">      78 </span><span class="lineCov">        596 :   output [40:0]  io_out_s1_full_pred_0_fallThroughAddr,</span></a>
+<a name="79"><span class="lineNum">      79 </span><span class="lineCov">         14 :   output         io_out_s1_full_pred_0_is_br_sharing,</span></a>
+<a name="80"><span class="lineNum">      80 </span><span class="lineCov">         14 :   output         io_out_s1_full_pred_0_hit,</span></a>
+<a name="81"><span class="lineNum">      81 </span><span class="lineCov">         15 :   output         io_out_s1_full_pred_1_br_taken_mask_0,</span></a>
+<a name="82"><span class="lineNum">      82 </span><span class="lineCov">         17 :   output         io_out_s1_full_pred_1_br_taken_mask_1,</span></a>
+<a name="83"><span class="lineNum">      83 </span><span class="lineCov">         12 :   output         io_out_s1_full_pred_1_slot_valids_0,</span></a>
+<a name="84"><span class="lineNum">      84 </span><span class="lineCov">          9 :   output         io_out_s1_full_pred_1_slot_valids_1,</span></a>
+<a name="85"><span class="lineNum">      85 </span><span class="lineCov">        615 :   output [40:0]  io_out_s1_full_pred_1_targets_0,</span></a>
+<a name="86"><span class="lineNum">      86 </span><span class="lineCov">        574 :   output [40:0]  io_out_s1_full_pred_1_targets_1,</span></a>
+<a name="87"><span class="lineNum">      87 </span><span class="lineCov">         57 :   output [3:0]   io_out_s1_full_pred_1_offsets_0,</span></a>
+<a name="88"><span class="lineNum">      88 </span><span class="lineCov">         64 :   output [3:0]   io_out_s1_full_pred_1_offsets_1,</span></a>
+<a name="89"><span class="lineNum">      89 </span><span class="lineCov">        596 :   output [40:0]  io_out_s1_full_pred_1_fallThroughAddr,</span></a>
+<a name="90"><span class="lineNum">      90 </span><span class="lineCov">         14 :   output         io_out_s1_full_pred_1_is_br_sharing,</span></a>
+<a name="91"><span class="lineNum">      91 </span><span class="lineCov">         14 :   output         io_out_s1_full_pred_1_hit,</span></a>
+<a name="92"><span class="lineNum">      92 </span><span class="lineCov">         15 :   output         io_out_s1_full_pred_2_br_taken_mask_0,</span></a>
+<a name="93"><span class="lineNum">      93 </span><span class="lineCov">         17 :   output         io_out_s1_full_pred_2_br_taken_mask_1,</span></a>
+<a name="94"><span class="lineNum">      94 </span><span class="lineCov">         12 :   output         io_out_s1_full_pred_2_slot_valids_0,</span></a>
+<a name="95"><span class="lineNum">      95 </span><span class="lineCov">          9 :   output         io_out_s1_full_pred_2_slot_valids_1,</span></a>
+<a name="96"><span class="lineNum">      96 </span><span class="lineCov">        615 :   output [40:0]  io_out_s1_full_pred_2_targets_0,</span></a>
+<a name="97"><span class="lineNum">      97 </span><span class="lineCov">        574 :   output [40:0]  io_out_s1_full_pred_2_targets_1,</span></a>
+<a name="98"><span class="lineNum">      98 </span><span class="lineCov">         57 :   output [3:0]   io_out_s1_full_pred_2_offsets_0,</span></a>
+<a name="99"><span class="lineNum">      99 </span><span class="lineCov">         64 :   output [3:0]   io_out_s1_full_pred_2_offsets_1,</span></a>
+<a name="100"><span class="lineNum">     100 </span><span class="lineCov">        596 :   output [40:0]  io_out_s1_full_pred_2_fallThroughAddr,</span></a>
+<a name="101"><span class="lineNum">     101 </span><span class="lineCov">         14 :   output         io_out_s1_full_pred_2_is_br_sharing,</span></a>
+<a name="102"><span class="lineNum">     102 </span><span class="lineCov">         14 :   output         io_out_s1_full_pred_2_hit,</span></a>
+<a name="103"><span class="lineNum">     103 </span><span class="lineCov">         15 :   output         io_out_s1_full_pred_3_br_taken_mask_0,</span></a>
+<a name="104"><span class="lineNum">     104 </span><span class="lineCov">         17 :   output         io_out_s1_full_pred_3_br_taken_mask_1,</span></a>
+<a name="105"><span class="lineNum">     105 </span><span class="lineCov">         12 :   output         io_out_s1_full_pred_3_slot_valids_0,</span></a>
+<a name="106"><span class="lineNum">     106 </span><span class="lineCov">          9 :   output         io_out_s1_full_pred_3_slot_valids_1,</span></a>
+<a name="107"><span class="lineNum">     107 </span><span class="lineCov">        615 :   output [40:0]  io_out_s1_full_pred_3_targets_0,</span></a>
+<a name="108"><span class="lineNum">     108 </span><span class="lineCov">        574 :   output [40:0]  io_out_s1_full_pred_3_targets_1,</span></a>
+<a name="109"><span class="lineNum">     109 </span><span class="lineCov">         57 :   output [3:0]   io_out_s1_full_pred_3_offsets_0,</span></a>
+<a name="110"><span class="lineNum">     110 </span><span class="lineCov">         64 :   output [3:0]   io_out_s1_full_pred_3_offsets_1,</span></a>
+<a name="111"><span class="lineNum">     111 </span><span class="lineCov">        596 :   output [40:0]  io_out_s1_full_pred_3_fallThroughAddr,</span></a>
+<a name="112"><span class="lineNum">     112 </span><span class="lineCov">         10 :   output         io_out_s1_full_pred_3_fallThroughErr,</span></a>
+<a name="113"><span class="lineNum">     113 </span><span class="lineCov">         14 :   output         io_out_s1_full_pred_3_is_br_sharing,</span></a>
+<a name="114"><span class="lineNum">     114 </span><span class="lineCov">         14 :   output         io_out_s1_full_pred_3_hit,</span></a>
+<a name="115"><span class="lineNum">     115 </span><span class="lineCov">       3291 :   output [222:0] io_out_last_stage_meta,</span></a>
+<a name="116"><span class="lineNum">     116 </span><span class="lineCov">         84 :   input          io_ctrl_ubtb_enable,</span></a>
+<a name="117"><span class="lineNum">     117 </span><span class="lineCov">         75 :   input          io_s0_fire_0,</span></a>
+<a name="118"><span class="lineNum">     118 </span><span class="lineCov">         76 :   input          io_s0_fire_1,</span></a>
+<a name="119"><span class="lineNum">     119 </span><span class="lineCov">         76 :   input          io_s0_fire_2,</span></a>
+<a name="120"><span class="lineNum">     120 </span><span class="lineCov">         73 :   input          io_s0_fire_3,</span></a>
+<a name="121"><span class="lineNum">     121 </span><span class="lineCov">        133 :   input          io_s1_fire_0,</span></a>
+<a name="122"><span class="lineNum">     122 </span><span class="lineCov">        127 :   input          io_s2_fire_0,</span></a>
+<a name="123"><span class="lineNum">     123 </span><span class="lineCov">        105 :   input          io_update_valid,</span></a>
+<a name="124"><span class="lineNum">     124 </span><span class="lineCov">       1143 :   input  [40:0]  io_update_bits_pc,</span></a>
+<a name="125"><span class="lineNum">     125 </span><span class="lineCov">        122 :   input  [3:0]   io_update_bits_ftb_entry_brSlots_0_offset,</span></a>
+<a name="126"><span class="lineNum">     126 </span><span class="lineCov">        337 :   input  [11:0]  io_update_bits_ftb_entry_brSlots_0_lower,</span></a>
+<a name="127"><span class="lineNum">     127 </span><span class="lineCov">         65 :   input  [1:0]   io_update_bits_ftb_entry_brSlots_0_tarStat,</span></a>
+<a name="128"><span class="lineNum">     128 </span><span class="lineCov">         35 :   input          io_update_bits_ftb_entry_brSlots_0_valid,</span></a>
+<a name="129"><span class="lineNum">     129 </span><span class="lineCov">        137 :   input  [3:0]   io_update_bits_ftb_entry_tailSlot_offset,</span></a>
+<a name="130"><span class="lineNum">     130 </span><span class="lineCov">        552 :   input  [19:0]  io_update_bits_ftb_entry_tailSlot_lower,</span></a>
+<a name="131"><span class="lineNum">     131 </span><span class="lineCov">         63 :   input  [1:0]   io_update_bits_ftb_entry_tailSlot_tarStat,</span></a>
+<a name="132"><span class="lineNum">     132 </span><span class="lineCov">         33 :   input          io_update_bits_ftb_entry_tailSlot_sharing,</span></a>
+<a name="133"><span class="lineNum">     133 </span><span class="lineCov">         28 :   input          io_update_bits_ftb_entry_tailSlot_valid,</span></a>
+<a name="134"><span class="lineNum">     134 </span><span class="lineCov">        152 :   input  [3:0]   io_update_bits_ftb_entry_pftAddr,</span></a>
+<a name="135"><span class="lineNum">     135 </span><span class="lineCov">         34 :   input          io_update_bits_ftb_entry_carry,</span></a>
+<a name="136"><span class="lineNum">     136 </span><span class="lineCov">         32 :   input          io_update_bits_ftb_entry_always_taken_0,</span></a>
+<a name="137"><span class="lineNum">     137 </span><span class="lineCov">         33 :   input          io_update_bits_ftb_entry_always_taken_1,</span></a>
+<a name="138"><span class="lineNum">     138 </span><span class="lineCov">         24 :   input          io_update_bits_br_taken_mask_0,</span></a>
+<a name="139"><span class="lineNum">     139 </span><span class="lineCov">         40 :   input          io_update_bits_br_taken_mask_1,</span></a>
+<a name="140"><span class="lineNum">     140 </span><span class="lineCov">       3277 :   input  [222:0] io_update_bits_meta,</span></a>
+<a name="141"><span class="lineNum">     141 </span><span class="lineCov">        124 :   output [5:0]   io_perf_0_value,</span></a>
+<a name="142"><span class="lineNum">     142 </span><span class="lineCov">        208 :   output [5:0]   io_perf_1_value</span></a>
+<a name="143"><span class="lineNum">     143 </span>            : );</a>
+<a name="144"><span class="lineNum">     144 </span>            : </a>
+<a name="145"><span class="lineNum">     145 </span><span class="lineCov">        158 :   reg  [4:0]  resp_meta_pred_way_r_1;</span></a>
+<a name="146"><span class="lineNum">     146 </span><span class="lineCov">         37 :   reg         resp_meta_hit_r_1;</span></a>
+<a name="147"><span class="lineNum">     147 </span>            :   wire [3:0]  _ways_31_io_resp_brSlots_0_offset;</a>
+<a name="148"><span class="lineNum">     148 </span>            :   wire [11:0] _ways_31_io_resp_brSlots_0_lower;</a>
+<a name="149"><span class="lineNum">     149 </span>            :   wire [1:0]  _ways_31_io_resp_brSlots_0_tarStat;</a>
+<a name="150"><span class="lineNum">     150 </span>            :   wire        _ways_31_io_resp_brSlots_0_valid;</a>
+<a name="151"><span class="lineNum">     151 </span>            :   wire [3:0]  _ways_31_io_resp_tailSlot_offset;</a>
+<a name="152"><span class="lineNum">     152 </span>            :   wire [19:0] _ways_31_io_resp_tailSlot_lower;</a>
+<a name="153"><span class="lineNum">     153 </span>            :   wire [1:0]  _ways_31_io_resp_tailSlot_tarStat;</a>
+<a name="154"><span class="lineNum">     154 </span>            :   wire        _ways_31_io_resp_tailSlot_sharing;</a>
+<a name="155"><span class="lineNum">     155 </span>            :   wire        _ways_31_io_resp_tailSlot_valid;</a>
+<a name="156"><span class="lineNum">     156 </span>            :   wire [3:0]  _ways_31_io_resp_pftAddr;</a>
+<a name="157"><span class="lineNum">     157 </span>            :   wire        _ways_31_io_resp_carry;</a>
+<a name="158"><span class="lineNum">     158 </span>            :   wire        _ways_31_io_resp_always_taken_0;</a>
+<a name="159"><span class="lineNum">     159 </span>            :   wire        _ways_31_io_resp_always_taken_1;</a>
+<a name="160"><span class="lineNum">     160 </span>            :   wire        _ways_31_io_resp_hit;</a>
+<a name="161"><span class="lineNum">     161 </span>            :   wire        _ways_31_io_update_hit;</a>
+<a name="162"><span class="lineNum">     162 </span>            :   wire [3:0]  _ways_30_io_resp_brSlots_0_offset;</a>
+<a name="163"><span class="lineNum">     163 </span>            :   wire [11:0] _ways_30_io_resp_brSlots_0_lower;</a>
+<a name="164"><span class="lineNum">     164 </span>            :   wire [1:0]  _ways_30_io_resp_brSlots_0_tarStat;</a>
+<a name="165"><span class="lineNum">     165 </span>            :   wire        _ways_30_io_resp_brSlots_0_valid;</a>
+<a name="166"><span class="lineNum">     166 </span>            :   wire [3:0]  _ways_30_io_resp_tailSlot_offset;</a>
+<a name="167"><span class="lineNum">     167 </span>            :   wire [19:0] _ways_30_io_resp_tailSlot_lower;</a>
+<a name="168"><span class="lineNum">     168 </span>            :   wire [1:0]  _ways_30_io_resp_tailSlot_tarStat;</a>
+<a name="169"><span class="lineNum">     169 </span>            :   wire        _ways_30_io_resp_tailSlot_sharing;</a>
+<a name="170"><span class="lineNum">     170 </span>            :   wire        _ways_30_io_resp_tailSlot_valid;</a>
+<a name="171"><span class="lineNum">     171 </span>            :   wire [3:0]  _ways_30_io_resp_pftAddr;</a>
+<a name="172"><span class="lineNum">     172 </span>            :   wire        _ways_30_io_resp_carry;</a>
+<a name="173"><span class="lineNum">     173 </span>            :   wire        _ways_30_io_resp_always_taken_0;</a>
+<a name="174"><span class="lineNum">     174 </span>            :   wire        _ways_30_io_resp_always_taken_1;</a>
+<a name="175"><span class="lineNum">     175 </span>            :   wire        _ways_30_io_resp_hit;</a>
+<a name="176"><span class="lineNum">     176 </span>            :   wire        _ways_30_io_update_hit;</a>
+<a name="177"><span class="lineNum">     177 </span>            :   wire [3:0]  _ways_29_io_resp_brSlots_0_offset;</a>
+<a name="178"><span class="lineNum">     178 </span>            :   wire [11:0] _ways_29_io_resp_brSlots_0_lower;</a>
+<a name="179"><span class="lineNum">     179 </span>            :   wire [1:0]  _ways_29_io_resp_brSlots_0_tarStat;</a>
+<a name="180"><span class="lineNum">     180 </span>            :   wire        _ways_29_io_resp_brSlots_0_valid;</a>
+<a name="181"><span class="lineNum">     181 </span>            :   wire [3:0]  _ways_29_io_resp_tailSlot_offset;</a>
+<a name="182"><span class="lineNum">     182 </span>            :   wire [19:0] _ways_29_io_resp_tailSlot_lower;</a>
+<a name="183"><span class="lineNum">     183 </span>            :   wire [1:0]  _ways_29_io_resp_tailSlot_tarStat;</a>
+<a name="184"><span class="lineNum">     184 </span>            :   wire        _ways_29_io_resp_tailSlot_sharing;</a>
+<a name="185"><span class="lineNum">     185 </span>            :   wire        _ways_29_io_resp_tailSlot_valid;</a>
+<a name="186"><span class="lineNum">     186 </span>            :   wire [3:0]  _ways_29_io_resp_pftAddr;</a>
+<a name="187"><span class="lineNum">     187 </span>            :   wire        _ways_29_io_resp_carry;</a>
+<a name="188"><span class="lineNum">     188 </span>            :   wire        _ways_29_io_resp_always_taken_0;</a>
+<a name="189"><span class="lineNum">     189 </span>            :   wire        _ways_29_io_resp_always_taken_1;</a>
+<a name="190"><span class="lineNum">     190 </span>            :   wire        _ways_29_io_resp_hit;</a>
+<a name="191"><span class="lineNum">     191 </span>            :   wire        _ways_29_io_update_hit;</a>
+<a name="192"><span class="lineNum">     192 </span>            :   wire [3:0]  _ways_28_io_resp_brSlots_0_offset;</a>
+<a name="193"><span class="lineNum">     193 </span>            :   wire [11:0] _ways_28_io_resp_brSlots_0_lower;</a>
+<a name="194"><span class="lineNum">     194 </span>            :   wire [1:0]  _ways_28_io_resp_brSlots_0_tarStat;</a>
+<a name="195"><span class="lineNum">     195 </span>            :   wire        _ways_28_io_resp_brSlots_0_valid;</a>
+<a name="196"><span class="lineNum">     196 </span>            :   wire [3:0]  _ways_28_io_resp_tailSlot_offset;</a>
+<a name="197"><span class="lineNum">     197 </span>            :   wire [19:0] _ways_28_io_resp_tailSlot_lower;</a>
+<a name="198"><span class="lineNum">     198 </span>            :   wire [1:0]  _ways_28_io_resp_tailSlot_tarStat;</a>
+<a name="199"><span class="lineNum">     199 </span>            :   wire        _ways_28_io_resp_tailSlot_sharing;</a>
+<a name="200"><span class="lineNum">     200 </span>            :   wire        _ways_28_io_resp_tailSlot_valid;</a>
+<a name="201"><span class="lineNum">     201 </span>            :   wire [3:0]  _ways_28_io_resp_pftAddr;</a>
+<a name="202"><span class="lineNum">     202 </span>            :   wire        _ways_28_io_resp_carry;</a>
+<a name="203"><span class="lineNum">     203 </span>            :   wire        _ways_28_io_resp_always_taken_0;</a>
+<a name="204"><span class="lineNum">     204 </span>            :   wire        _ways_28_io_resp_always_taken_1;</a>
+<a name="205"><span class="lineNum">     205 </span>            :   wire        _ways_28_io_resp_hit;</a>
+<a name="206"><span class="lineNum">     206 </span>            :   wire        _ways_28_io_update_hit;</a>
+<a name="207"><span class="lineNum">     207 </span>            :   wire [3:0]  _ways_27_io_resp_brSlots_0_offset;</a>
+<a name="208"><span class="lineNum">     208 </span>            :   wire [11:0] _ways_27_io_resp_brSlots_0_lower;</a>
+<a name="209"><span class="lineNum">     209 </span>            :   wire [1:0]  _ways_27_io_resp_brSlots_0_tarStat;</a>
+<a name="210"><span class="lineNum">     210 </span>            :   wire        _ways_27_io_resp_brSlots_0_valid;</a>
+<a name="211"><span class="lineNum">     211 </span>            :   wire [3:0]  _ways_27_io_resp_tailSlot_offset;</a>
+<a name="212"><span class="lineNum">     212 </span>            :   wire [19:0] _ways_27_io_resp_tailSlot_lower;</a>
+<a name="213"><span class="lineNum">     213 </span>            :   wire [1:0]  _ways_27_io_resp_tailSlot_tarStat;</a>
+<a name="214"><span class="lineNum">     214 </span>            :   wire        _ways_27_io_resp_tailSlot_sharing;</a>
+<a name="215"><span class="lineNum">     215 </span>            :   wire        _ways_27_io_resp_tailSlot_valid;</a>
+<a name="216"><span class="lineNum">     216 </span>            :   wire [3:0]  _ways_27_io_resp_pftAddr;</a>
+<a name="217"><span class="lineNum">     217 </span>            :   wire        _ways_27_io_resp_carry;</a>
+<a name="218"><span class="lineNum">     218 </span>            :   wire        _ways_27_io_resp_always_taken_0;</a>
+<a name="219"><span class="lineNum">     219 </span>            :   wire        _ways_27_io_resp_always_taken_1;</a>
+<a name="220"><span class="lineNum">     220 </span>            :   wire        _ways_27_io_resp_hit;</a>
+<a name="221"><span class="lineNum">     221 </span>            :   wire        _ways_27_io_update_hit;</a>
+<a name="222"><span class="lineNum">     222 </span>            :   wire [3:0]  _ways_26_io_resp_brSlots_0_offset;</a>
+<a name="223"><span class="lineNum">     223 </span>            :   wire [11:0] _ways_26_io_resp_brSlots_0_lower;</a>
+<a name="224"><span class="lineNum">     224 </span>            :   wire [1:0]  _ways_26_io_resp_brSlots_0_tarStat;</a>
+<a name="225"><span class="lineNum">     225 </span>            :   wire        _ways_26_io_resp_brSlots_0_valid;</a>
+<a name="226"><span class="lineNum">     226 </span>            :   wire [3:0]  _ways_26_io_resp_tailSlot_offset;</a>
+<a name="227"><span class="lineNum">     227 </span>            :   wire [19:0] _ways_26_io_resp_tailSlot_lower;</a>
+<a name="228"><span class="lineNum">     228 </span>            :   wire [1:0]  _ways_26_io_resp_tailSlot_tarStat;</a>
+<a name="229"><span class="lineNum">     229 </span>            :   wire        _ways_26_io_resp_tailSlot_sharing;</a>
+<a name="230"><span class="lineNum">     230 </span>            :   wire        _ways_26_io_resp_tailSlot_valid;</a>
+<a name="231"><span class="lineNum">     231 </span>            :   wire [3:0]  _ways_26_io_resp_pftAddr;</a>
+<a name="232"><span class="lineNum">     232 </span>            :   wire        _ways_26_io_resp_carry;</a>
+<a name="233"><span class="lineNum">     233 </span>            :   wire        _ways_26_io_resp_always_taken_0;</a>
+<a name="234"><span class="lineNum">     234 </span>            :   wire        _ways_26_io_resp_always_taken_1;</a>
+<a name="235"><span class="lineNum">     235 </span>            :   wire        _ways_26_io_resp_hit;</a>
+<a name="236"><span class="lineNum">     236 </span>            :   wire        _ways_26_io_update_hit;</a>
+<a name="237"><span class="lineNum">     237 </span>            :   wire [3:0]  _ways_25_io_resp_brSlots_0_offset;</a>
+<a name="238"><span class="lineNum">     238 </span>            :   wire [11:0] _ways_25_io_resp_brSlots_0_lower;</a>
+<a name="239"><span class="lineNum">     239 </span>            :   wire [1:0]  _ways_25_io_resp_brSlots_0_tarStat;</a>
+<a name="240"><span class="lineNum">     240 </span>            :   wire        _ways_25_io_resp_brSlots_0_valid;</a>
+<a name="241"><span class="lineNum">     241 </span>            :   wire [3:0]  _ways_25_io_resp_tailSlot_offset;</a>
+<a name="242"><span class="lineNum">     242 </span>            :   wire [19:0] _ways_25_io_resp_tailSlot_lower;</a>
+<a name="243"><span class="lineNum">     243 </span>            :   wire [1:0]  _ways_25_io_resp_tailSlot_tarStat;</a>
+<a name="244"><span class="lineNum">     244 </span>            :   wire        _ways_25_io_resp_tailSlot_sharing;</a>
+<a name="245"><span class="lineNum">     245 </span>            :   wire        _ways_25_io_resp_tailSlot_valid;</a>
+<a name="246"><span class="lineNum">     246 </span>            :   wire [3:0]  _ways_25_io_resp_pftAddr;</a>
+<a name="247"><span class="lineNum">     247 </span>            :   wire        _ways_25_io_resp_carry;</a>
+<a name="248"><span class="lineNum">     248 </span>            :   wire        _ways_25_io_resp_always_taken_0;</a>
+<a name="249"><span class="lineNum">     249 </span>            :   wire        _ways_25_io_resp_always_taken_1;</a>
+<a name="250"><span class="lineNum">     250 </span>            :   wire        _ways_25_io_resp_hit;</a>
+<a name="251"><span class="lineNum">     251 </span>            :   wire        _ways_25_io_update_hit;</a>
+<a name="252"><span class="lineNum">     252 </span>            :   wire [3:0]  _ways_24_io_resp_brSlots_0_offset;</a>
+<a name="253"><span class="lineNum">     253 </span>            :   wire [11:0] _ways_24_io_resp_brSlots_0_lower;</a>
+<a name="254"><span class="lineNum">     254 </span>            :   wire [1:0]  _ways_24_io_resp_brSlots_0_tarStat;</a>
+<a name="255"><span class="lineNum">     255 </span>            :   wire        _ways_24_io_resp_brSlots_0_valid;</a>
+<a name="256"><span class="lineNum">     256 </span>            :   wire [3:0]  _ways_24_io_resp_tailSlot_offset;</a>
+<a name="257"><span class="lineNum">     257 </span>            :   wire [19:0] _ways_24_io_resp_tailSlot_lower;</a>
+<a name="258"><span class="lineNum">     258 </span>            :   wire [1:0]  _ways_24_io_resp_tailSlot_tarStat;</a>
+<a name="259"><span class="lineNum">     259 </span>            :   wire        _ways_24_io_resp_tailSlot_sharing;</a>
+<a name="260"><span class="lineNum">     260 </span>            :   wire        _ways_24_io_resp_tailSlot_valid;</a>
+<a name="261"><span class="lineNum">     261 </span>            :   wire [3:0]  _ways_24_io_resp_pftAddr;</a>
+<a name="262"><span class="lineNum">     262 </span>            :   wire        _ways_24_io_resp_carry;</a>
+<a name="263"><span class="lineNum">     263 </span>            :   wire        _ways_24_io_resp_always_taken_0;</a>
+<a name="264"><span class="lineNum">     264 </span>            :   wire        _ways_24_io_resp_always_taken_1;</a>
+<a name="265"><span class="lineNum">     265 </span>            :   wire        _ways_24_io_resp_hit;</a>
+<a name="266"><span class="lineNum">     266 </span>            :   wire        _ways_24_io_update_hit;</a>
+<a name="267"><span class="lineNum">     267 </span>            :   wire [3:0]  _ways_23_io_resp_brSlots_0_offset;</a>
+<a name="268"><span class="lineNum">     268 </span>            :   wire [11:0] _ways_23_io_resp_brSlots_0_lower;</a>
+<a name="269"><span class="lineNum">     269 </span>            :   wire [1:0]  _ways_23_io_resp_brSlots_0_tarStat;</a>
+<a name="270"><span class="lineNum">     270 </span>            :   wire        _ways_23_io_resp_brSlots_0_valid;</a>
+<a name="271"><span class="lineNum">     271 </span>            :   wire [3:0]  _ways_23_io_resp_tailSlot_offset;</a>
+<a name="272"><span class="lineNum">     272 </span>            :   wire [19:0] _ways_23_io_resp_tailSlot_lower;</a>
+<a name="273"><span class="lineNum">     273 </span>            :   wire [1:0]  _ways_23_io_resp_tailSlot_tarStat;</a>
+<a name="274"><span class="lineNum">     274 </span>            :   wire        _ways_23_io_resp_tailSlot_sharing;</a>
+<a name="275"><span class="lineNum">     275 </span>            :   wire        _ways_23_io_resp_tailSlot_valid;</a>
+<a name="276"><span class="lineNum">     276 </span>            :   wire [3:0]  _ways_23_io_resp_pftAddr;</a>
+<a name="277"><span class="lineNum">     277 </span>            :   wire        _ways_23_io_resp_carry;</a>
+<a name="278"><span class="lineNum">     278 </span>            :   wire        _ways_23_io_resp_always_taken_0;</a>
+<a name="279"><span class="lineNum">     279 </span>            :   wire        _ways_23_io_resp_always_taken_1;</a>
+<a name="280"><span class="lineNum">     280 </span>            :   wire        _ways_23_io_resp_hit;</a>
+<a name="281"><span class="lineNum">     281 </span>            :   wire        _ways_23_io_update_hit;</a>
+<a name="282"><span class="lineNum">     282 </span>            :   wire [3:0]  _ways_22_io_resp_brSlots_0_offset;</a>
+<a name="283"><span class="lineNum">     283 </span>            :   wire [11:0] _ways_22_io_resp_brSlots_0_lower;</a>
+<a name="284"><span class="lineNum">     284 </span>            :   wire [1:0]  _ways_22_io_resp_brSlots_0_tarStat;</a>
+<a name="285"><span class="lineNum">     285 </span>            :   wire        _ways_22_io_resp_brSlots_0_valid;</a>
+<a name="286"><span class="lineNum">     286 </span>            :   wire [3:0]  _ways_22_io_resp_tailSlot_offset;</a>
+<a name="287"><span class="lineNum">     287 </span>            :   wire [19:0] _ways_22_io_resp_tailSlot_lower;</a>
+<a name="288"><span class="lineNum">     288 </span>            :   wire [1:0]  _ways_22_io_resp_tailSlot_tarStat;</a>
+<a name="289"><span class="lineNum">     289 </span>            :   wire        _ways_22_io_resp_tailSlot_sharing;</a>
+<a name="290"><span class="lineNum">     290 </span>            :   wire        _ways_22_io_resp_tailSlot_valid;</a>
+<a name="291"><span class="lineNum">     291 </span>            :   wire [3:0]  _ways_22_io_resp_pftAddr;</a>
+<a name="292"><span class="lineNum">     292 </span>            :   wire        _ways_22_io_resp_carry;</a>
+<a name="293"><span class="lineNum">     293 </span>            :   wire        _ways_22_io_resp_always_taken_0;</a>
+<a name="294"><span class="lineNum">     294 </span>            :   wire        _ways_22_io_resp_always_taken_1;</a>
+<a name="295"><span class="lineNum">     295 </span>            :   wire        _ways_22_io_resp_hit;</a>
+<a name="296"><span class="lineNum">     296 </span>            :   wire        _ways_22_io_update_hit;</a>
+<a name="297"><span class="lineNum">     297 </span>            :   wire [3:0]  _ways_21_io_resp_brSlots_0_offset;</a>
+<a name="298"><span class="lineNum">     298 </span>            :   wire [11:0] _ways_21_io_resp_brSlots_0_lower;</a>
+<a name="299"><span class="lineNum">     299 </span>            :   wire [1:0]  _ways_21_io_resp_brSlots_0_tarStat;</a>
+<a name="300"><span class="lineNum">     300 </span>            :   wire        _ways_21_io_resp_brSlots_0_valid;</a>
+<a name="301"><span class="lineNum">     301 </span>            :   wire [3:0]  _ways_21_io_resp_tailSlot_offset;</a>
+<a name="302"><span class="lineNum">     302 </span>            :   wire [19:0] _ways_21_io_resp_tailSlot_lower;</a>
+<a name="303"><span class="lineNum">     303 </span>            :   wire [1:0]  _ways_21_io_resp_tailSlot_tarStat;</a>
+<a name="304"><span class="lineNum">     304 </span>            :   wire        _ways_21_io_resp_tailSlot_sharing;</a>
+<a name="305"><span class="lineNum">     305 </span>            :   wire        _ways_21_io_resp_tailSlot_valid;</a>
+<a name="306"><span class="lineNum">     306 </span>            :   wire [3:0]  _ways_21_io_resp_pftAddr;</a>
+<a name="307"><span class="lineNum">     307 </span>            :   wire        _ways_21_io_resp_carry;</a>
+<a name="308"><span class="lineNum">     308 </span>            :   wire        _ways_21_io_resp_always_taken_0;</a>
+<a name="309"><span class="lineNum">     309 </span>            :   wire        _ways_21_io_resp_always_taken_1;</a>
+<a name="310"><span class="lineNum">     310 </span>            :   wire        _ways_21_io_resp_hit;</a>
+<a name="311"><span class="lineNum">     311 </span>            :   wire        _ways_21_io_update_hit;</a>
+<a name="312"><span class="lineNum">     312 </span>            :   wire [3:0]  _ways_20_io_resp_brSlots_0_offset;</a>
+<a name="313"><span class="lineNum">     313 </span>            :   wire [11:0] _ways_20_io_resp_brSlots_0_lower;</a>
+<a name="314"><span class="lineNum">     314 </span>            :   wire [1:0]  _ways_20_io_resp_brSlots_0_tarStat;</a>
+<a name="315"><span class="lineNum">     315 </span>            :   wire        _ways_20_io_resp_brSlots_0_valid;</a>
+<a name="316"><span class="lineNum">     316 </span>            :   wire [3:0]  _ways_20_io_resp_tailSlot_offset;</a>
+<a name="317"><span class="lineNum">     317 </span>            :   wire [19:0] _ways_20_io_resp_tailSlot_lower;</a>
+<a name="318"><span class="lineNum">     318 </span>            :   wire [1:0]  _ways_20_io_resp_tailSlot_tarStat;</a>
+<a name="319"><span class="lineNum">     319 </span>            :   wire        _ways_20_io_resp_tailSlot_sharing;</a>
+<a name="320"><span class="lineNum">     320 </span>            :   wire        _ways_20_io_resp_tailSlot_valid;</a>
+<a name="321"><span class="lineNum">     321 </span>            :   wire [3:0]  _ways_20_io_resp_pftAddr;</a>
+<a name="322"><span class="lineNum">     322 </span>            :   wire        _ways_20_io_resp_carry;</a>
+<a name="323"><span class="lineNum">     323 </span>            :   wire        _ways_20_io_resp_always_taken_0;</a>
+<a name="324"><span class="lineNum">     324 </span>            :   wire        _ways_20_io_resp_always_taken_1;</a>
+<a name="325"><span class="lineNum">     325 </span>            :   wire        _ways_20_io_resp_hit;</a>
+<a name="326"><span class="lineNum">     326 </span>            :   wire        _ways_20_io_update_hit;</a>
+<a name="327"><span class="lineNum">     327 </span>            :   wire [3:0]  _ways_19_io_resp_brSlots_0_offset;</a>
+<a name="328"><span class="lineNum">     328 </span>            :   wire [11:0] _ways_19_io_resp_brSlots_0_lower;</a>
+<a name="329"><span class="lineNum">     329 </span>            :   wire [1:0]  _ways_19_io_resp_brSlots_0_tarStat;</a>
+<a name="330"><span class="lineNum">     330 </span>            :   wire        _ways_19_io_resp_brSlots_0_valid;</a>
+<a name="331"><span class="lineNum">     331 </span>            :   wire [3:0]  _ways_19_io_resp_tailSlot_offset;</a>
+<a name="332"><span class="lineNum">     332 </span>            :   wire [19:0] _ways_19_io_resp_tailSlot_lower;</a>
+<a name="333"><span class="lineNum">     333 </span>            :   wire [1:0]  _ways_19_io_resp_tailSlot_tarStat;</a>
+<a name="334"><span class="lineNum">     334 </span>            :   wire        _ways_19_io_resp_tailSlot_sharing;</a>
+<a name="335"><span class="lineNum">     335 </span>            :   wire        _ways_19_io_resp_tailSlot_valid;</a>
+<a name="336"><span class="lineNum">     336 </span>            :   wire [3:0]  _ways_19_io_resp_pftAddr;</a>
+<a name="337"><span class="lineNum">     337 </span>            :   wire        _ways_19_io_resp_carry;</a>
+<a name="338"><span class="lineNum">     338 </span>            :   wire        _ways_19_io_resp_always_taken_0;</a>
+<a name="339"><span class="lineNum">     339 </span>            :   wire        _ways_19_io_resp_always_taken_1;</a>
+<a name="340"><span class="lineNum">     340 </span>            :   wire        _ways_19_io_resp_hit;</a>
+<a name="341"><span class="lineNum">     341 </span>            :   wire        _ways_19_io_update_hit;</a>
+<a name="342"><span class="lineNum">     342 </span>            :   wire [3:0]  _ways_18_io_resp_brSlots_0_offset;</a>
+<a name="343"><span class="lineNum">     343 </span>            :   wire [11:0] _ways_18_io_resp_brSlots_0_lower;</a>
+<a name="344"><span class="lineNum">     344 </span>            :   wire [1:0]  _ways_18_io_resp_brSlots_0_tarStat;</a>
+<a name="345"><span class="lineNum">     345 </span>            :   wire        _ways_18_io_resp_brSlots_0_valid;</a>
+<a name="346"><span class="lineNum">     346 </span>            :   wire [3:0]  _ways_18_io_resp_tailSlot_offset;</a>
+<a name="347"><span class="lineNum">     347 </span>            :   wire [19:0] _ways_18_io_resp_tailSlot_lower;</a>
+<a name="348"><span class="lineNum">     348 </span>            :   wire [1:0]  _ways_18_io_resp_tailSlot_tarStat;</a>
+<a name="349"><span class="lineNum">     349 </span>            :   wire        _ways_18_io_resp_tailSlot_sharing;</a>
+<a name="350"><span class="lineNum">     350 </span>            :   wire        _ways_18_io_resp_tailSlot_valid;</a>
+<a name="351"><span class="lineNum">     351 </span>            :   wire [3:0]  _ways_18_io_resp_pftAddr;</a>
+<a name="352"><span class="lineNum">     352 </span>            :   wire        _ways_18_io_resp_carry;</a>
+<a name="353"><span class="lineNum">     353 </span>            :   wire        _ways_18_io_resp_always_taken_0;</a>
+<a name="354"><span class="lineNum">     354 </span>            :   wire        _ways_18_io_resp_always_taken_1;</a>
+<a name="355"><span class="lineNum">     355 </span>            :   wire        _ways_18_io_resp_hit;</a>
+<a name="356"><span class="lineNum">     356 </span>            :   wire        _ways_18_io_update_hit;</a>
+<a name="357"><span class="lineNum">     357 </span>            :   wire [3:0]  _ways_17_io_resp_brSlots_0_offset;</a>
+<a name="358"><span class="lineNum">     358 </span>            :   wire [11:0] _ways_17_io_resp_brSlots_0_lower;</a>
+<a name="359"><span class="lineNum">     359 </span>            :   wire [1:0]  _ways_17_io_resp_brSlots_0_tarStat;</a>
+<a name="360"><span class="lineNum">     360 </span>            :   wire        _ways_17_io_resp_brSlots_0_valid;</a>
+<a name="361"><span class="lineNum">     361 </span>            :   wire [3:0]  _ways_17_io_resp_tailSlot_offset;</a>
+<a name="362"><span class="lineNum">     362 </span>            :   wire [19:0] _ways_17_io_resp_tailSlot_lower;</a>
+<a name="363"><span class="lineNum">     363 </span>            :   wire [1:0]  _ways_17_io_resp_tailSlot_tarStat;</a>
+<a name="364"><span class="lineNum">     364 </span>            :   wire        _ways_17_io_resp_tailSlot_sharing;</a>
+<a name="365"><span class="lineNum">     365 </span>            :   wire        _ways_17_io_resp_tailSlot_valid;</a>
+<a name="366"><span class="lineNum">     366 </span>            :   wire [3:0]  _ways_17_io_resp_pftAddr;</a>
+<a name="367"><span class="lineNum">     367 </span>            :   wire        _ways_17_io_resp_carry;</a>
+<a name="368"><span class="lineNum">     368 </span>            :   wire        _ways_17_io_resp_always_taken_0;</a>
+<a name="369"><span class="lineNum">     369 </span>            :   wire        _ways_17_io_resp_always_taken_1;</a>
+<a name="370"><span class="lineNum">     370 </span>            :   wire        _ways_17_io_resp_hit;</a>
+<a name="371"><span class="lineNum">     371 </span>            :   wire        _ways_17_io_update_hit;</a>
+<a name="372"><span class="lineNum">     372 </span>            :   wire [3:0]  _ways_16_io_resp_brSlots_0_offset;</a>
+<a name="373"><span class="lineNum">     373 </span>            :   wire [11:0] _ways_16_io_resp_brSlots_0_lower;</a>
+<a name="374"><span class="lineNum">     374 </span>            :   wire [1:0]  _ways_16_io_resp_brSlots_0_tarStat;</a>
+<a name="375"><span class="lineNum">     375 </span>            :   wire        _ways_16_io_resp_brSlots_0_valid;</a>
+<a name="376"><span class="lineNum">     376 </span>            :   wire [3:0]  _ways_16_io_resp_tailSlot_offset;</a>
+<a name="377"><span class="lineNum">     377 </span>            :   wire [19:0] _ways_16_io_resp_tailSlot_lower;</a>
+<a name="378"><span class="lineNum">     378 </span>            :   wire [1:0]  _ways_16_io_resp_tailSlot_tarStat;</a>
+<a name="379"><span class="lineNum">     379 </span>            :   wire        _ways_16_io_resp_tailSlot_sharing;</a>
+<a name="380"><span class="lineNum">     380 </span>            :   wire        _ways_16_io_resp_tailSlot_valid;</a>
+<a name="381"><span class="lineNum">     381 </span>            :   wire [3:0]  _ways_16_io_resp_pftAddr;</a>
+<a name="382"><span class="lineNum">     382 </span>            :   wire        _ways_16_io_resp_carry;</a>
+<a name="383"><span class="lineNum">     383 </span>            :   wire        _ways_16_io_resp_always_taken_0;</a>
+<a name="384"><span class="lineNum">     384 </span>            :   wire        _ways_16_io_resp_always_taken_1;</a>
+<a name="385"><span class="lineNum">     385 </span>            :   wire        _ways_16_io_resp_hit;</a>
+<a name="386"><span class="lineNum">     386 </span>            :   wire        _ways_16_io_update_hit;</a>
+<a name="387"><span class="lineNum">     387 </span>            :   wire [3:0]  _ways_15_io_resp_brSlots_0_offset;</a>
+<a name="388"><span class="lineNum">     388 </span>            :   wire [11:0] _ways_15_io_resp_brSlots_0_lower;</a>
+<a name="389"><span class="lineNum">     389 </span>            :   wire [1:0]  _ways_15_io_resp_brSlots_0_tarStat;</a>
+<a name="390"><span class="lineNum">     390 </span>            :   wire        _ways_15_io_resp_brSlots_0_valid;</a>
+<a name="391"><span class="lineNum">     391 </span>            :   wire [3:0]  _ways_15_io_resp_tailSlot_offset;</a>
+<a name="392"><span class="lineNum">     392 </span>            :   wire [19:0] _ways_15_io_resp_tailSlot_lower;</a>
+<a name="393"><span class="lineNum">     393 </span>            :   wire [1:0]  _ways_15_io_resp_tailSlot_tarStat;</a>
+<a name="394"><span class="lineNum">     394 </span>            :   wire        _ways_15_io_resp_tailSlot_sharing;</a>
+<a name="395"><span class="lineNum">     395 </span>            :   wire        _ways_15_io_resp_tailSlot_valid;</a>
+<a name="396"><span class="lineNum">     396 </span>            :   wire [3:0]  _ways_15_io_resp_pftAddr;</a>
+<a name="397"><span class="lineNum">     397 </span>            :   wire        _ways_15_io_resp_carry;</a>
+<a name="398"><span class="lineNum">     398 </span>            :   wire        _ways_15_io_resp_always_taken_0;</a>
+<a name="399"><span class="lineNum">     399 </span>            :   wire        _ways_15_io_resp_always_taken_1;</a>
+<a name="400"><span class="lineNum">     400 </span>            :   wire        _ways_15_io_resp_hit;</a>
+<a name="401"><span class="lineNum">     401 </span>            :   wire        _ways_15_io_update_hit;</a>
+<a name="402"><span class="lineNum">     402 </span>            :   wire [3:0]  _ways_14_io_resp_brSlots_0_offset;</a>
+<a name="403"><span class="lineNum">     403 </span>            :   wire [11:0] _ways_14_io_resp_brSlots_0_lower;</a>
+<a name="404"><span class="lineNum">     404 </span>            :   wire [1:0]  _ways_14_io_resp_brSlots_0_tarStat;</a>
+<a name="405"><span class="lineNum">     405 </span>            :   wire        _ways_14_io_resp_brSlots_0_valid;</a>
+<a name="406"><span class="lineNum">     406 </span>            :   wire [3:0]  _ways_14_io_resp_tailSlot_offset;</a>
+<a name="407"><span class="lineNum">     407 </span>            :   wire [19:0] _ways_14_io_resp_tailSlot_lower;</a>
+<a name="408"><span class="lineNum">     408 </span>            :   wire [1:0]  _ways_14_io_resp_tailSlot_tarStat;</a>
+<a name="409"><span class="lineNum">     409 </span>            :   wire        _ways_14_io_resp_tailSlot_sharing;</a>
+<a name="410"><span class="lineNum">     410 </span>            :   wire        _ways_14_io_resp_tailSlot_valid;</a>
+<a name="411"><span class="lineNum">     411 </span>            :   wire [3:0]  _ways_14_io_resp_pftAddr;</a>
+<a name="412"><span class="lineNum">     412 </span>            :   wire        _ways_14_io_resp_carry;</a>
+<a name="413"><span class="lineNum">     413 </span>            :   wire        _ways_14_io_resp_always_taken_0;</a>
+<a name="414"><span class="lineNum">     414 </span>            :   wire        _ways_14_io_resp_always_taken_1;</a>
+<a name="415"><span class="lineNum">     415 </span>            :   wire        _ways_14_io_resp_hit;</a>
+<a name="416"><span class="lineNum">     416 </span>            :   wire        _ways_14_io_update_hit;</a>
+<a name="417"><span class="lineNum">     417 </span>            :   wire [3:0]  _ways_13_io_resp_brSlots_0_offset;</a>
+<a name="418"><span class="lineNum">     418 </span>            :   wire [11:0] _ways_13_io_resp_brSlots_0_lower;</a>
+<a name="419"><span class="lineNum">     419 </span>            :   wire [1:0]  _ways_13_io_resp_brSlots_0_tarStat;</a>
+<a name="420"><span class="lineNum">     420 </span>            :   wire        _ways_13_io_resp_brSlots_0_valid;</a>
+<a name="421"><span class="lineNum">     421 </span>            :   wire [3:0]  _ways_13_io_resp_tailSlot_offset;</a>
+<a name="422"><span class="lineNum">     422 </span>            :   wire [19:0] _ways_13_io_resp_tailSlot_lower;</a>
+<a name="423"><span class="lineNum">     423 </span>            :   wire [1:0]  _ways_13_io_resp_tailSlot_tarStat;</a>
+<a name="424"><span class="lineNum">     424 </span>            :   wire        _ways_13_io_resp_tailSlot_sharing;</a>
+<a name="425"><span class="lineNum">     425 </span>            :   wire        _ways_13_io_resp_tailSlot_valid;</a>
+<a name="426"><span class="lineNum">     426 </span>            :   wire [3:0]  _ways_13_io_resp_pftAddr;</a>
+<a name="427"><span class="lineNum">     427 </span>            :   wire        _ways_13_io_resp_carry;</a>
+<a name="428"><span class="lineNum">     428 </span>            :   wire        _ways_13_io_resp_always_taken_0;</a>
+<a name="429"><span class="lineNum">     429 </span>            :   wire        _ways_13_io_resp_always_taken_1;</a>
+<a name="430"><span class="lineNum">     430 </span>            :   wire        _ways_13_io_resp_hit;</a>
+<a name="431"><span class="lineNum">     431 </span>            :   wire        _ways_13_io_update_hit;</a>
+<a name="432"><span class="lineNum">     432 </span>            :   wire [3:0]  _ways_12_io_resp_brSlots_0_offset;</a>
+<a name="433"><span class="lineNum">     433 </span>            :   wire [11:0] _ways_12_io_resp_brSlots_0_lower;</a>
+<a name="434"><span class="lineNum">     434 </span>            :   wire [1:0]  _ways_12_io_resp_brSlots_0_tarStat;</a>
+<a name="435"><span class="lineNum">     435 </span>            :   wire        _ways_12_io_resp_brSlots_0_valid;</a>
+<a name="436"><span class="lineNum">     436 </span>            :   wire [3:0]  _ways_12_io_resp_tailSlot_offset;</a>
+<a name="437"><span class="lineNum">     437 </span>            :   wire [19:0] _ways_12_io_resp_tailSlot_lower;</a>
+<a name="438"><span class="lineNum">     438 </span>            :   wire [1:0]  _ways_12_io_resp_tailSlot_tarStat;</a>
+<a name="439"><span class="lineNum">     439 </span>            :   wire        _ways_12_io_resp_tailSlot_sharing;</a>
+<a name="440"><span class="lineNum">     440 </span>            :   wire        _ways_12_io_resp_tailSlot_valid;</a>
+<a name="441"><span class="lineNum">     441 </span>            :   wire [3:0]  _ways_12_io_resp_pftAddr;</a>
+<a name="442"><span class="lineNum">     442 </span>            :   wire        _ways_12_io_resp_carry;</a>
+<a name="443"><span class="lineNum">     443 </span>            :   wire        _ways_12_io_resp_always_taken_0;</a>
+<a name="444"><span class="lineNum">     444 </span>            :   wire        _ways_12_io_resp_always_taken_1;</a>
+<a name="445"><span class="lineNum">     445 </span>            :   wire        _ways_12_io_resp_hit;</a>
+<a name="446"><span class="lineNum">     446 </span>            :   wire        _ways_12_io_update_hit;</a>
+<a name="447"><span class="lineNum">     447 </span>            :   wire [3:0]  _ways_11_io_resp_brSlots_0_offset;</a>
+<a name="448"><span class="lineNum">     448 </span>            :   wire [11:0] _ways_11_io_resp_brSlots_0_lower;</a>
+<a name="449"><span class="lineNum">     449 </span>            :   wire [1:0]  _ways_11_io_resp_brSlots_0_tarStat;</a>
+<a name="450"><span class="lineNum">     450 </span>            :   wire        _ways_11_io_resp_brSlots_0_valid;</a>
+<a name="451"><span class="lineNum">     451 </span>            :   wire [3:0]  _ways_11_io_resp_tailSlot_offset;</a>
+<a name="452"><span class="lineNum">     452 </span>            :   wire [19:0] _ways_11_io_resp_tailSlot_lower;</a>
+<a name="453"><span class="lineNum">     453 </span>            :   wire [1:0]  _ways_11_io_resp_tailSlot_tarStat;</a>
+<a name="454"><span class="lineNum">     454 </span>            :   wire        _ways_11_io_resp_tailSlot_sharing;</a>
+<a name="455"><span class="lineNum">     455 </span>            :   wire        _ways_11_io_resp_tailSlot_valid;</a>
+<a name="456"><span class="lineNum">     456 </span>            :   wire [3:0]  _ways_11_io_resp_pftAddr;</a>
+<a name="457"><span class="lineNum">     457 </span>            :   wire        _ways_11_io_resp_carry;</a>
+<a name="458"><span class="lineNum">     458 </span>            :   wire        _ways_11_io_resp_always_taken_0;</a>
+<a name="459"><span class="lineNum">     459 </span>            :   wire        _ways_11_io_resp_always_taken_1;</a>
+<a name="460"><span class="lineNum">     460 </span>            :   wire        _ways_11_io_resp_hit;</a>
+<a name="461"><span class="lineNum">     461 </span>            :   wire        _ways_11_io_update_hit;</a>
+<a name="462"><span class="lineNum">     462 </span>            :   wire [3:0]  _ways_10_io_resp_brSlots_0_offset;</a>
+<a name="463"><span class="lineNum">     463 </span>            :   wire [11:0] _ways_10_io_resp_brSlots_0_lower;</a>
+<a name="464"><span class="lineNum">     464 </span>            :   wire [1:0]  _ways_10_io_resp_brSlots_0_tarStat;</a>
+<a name="465"><span class="lineNum">     465 </span>            :   wire        _ways_10_io_resp_brSlots_0_valid;</a>
+<a name="466"><span class="lineNum">     466 </span>            :   wire [3:0]  _ways_10_io_resp_tailSlot_offset;</a>
+<a name="467"><span class="lineNum">     467 </span>            :   wire [19:0] _ways_10_io_resp_tailSlot_lower;</a>
+<a name="468"><span class="lineNum">     468 </span>            :   wire [1:0]  _ways_10_io_resp_tailSlot_tarStat;</a>
+<a name="469"><span class="lineNum">     469 </span>            :   wire        _ways_10_io_resp_tailSlot_sharing;</a>
+<a name="470"><span class="lineNum">     470 </span>            :   wire        _ways_10_io_resp_tailSlot_valid;</a>
+<a name="471"><span class="lineNum">     471 </span>            :   wire [3:0]  _ways_10_io_resp_pftAddr;</a>
+<a name="472"><span class="lineNum">     472 </span>            :   wire        _ways_10_io_resp_carry;</a>
+<a name="473"><span class="lineNum">     473 </span>            :   wire        _ways_10_io_resp_always_taken_0;</a>
+<a name="474"><span class="lineNum">     474 </span>            :   wire        _ways_10_io_resp_always_taken_1;</a>
+<a name="475"><span class="lineNum">     475 </span>            :   wire        _ways_10_io_resp_hit;</a>
+<a name="476"><span class="lineNum">     476 </span>            :   wire        _ways_10_io_update_hit;</a>
+<a name="477"><span class="lineNum">     477 </span>            :   wire [3:0]  _ways_9_io_resp_brSlots_0_offset;</a>
+<a name="478"><span class="lineNum">     478 </span>            :   wire [11:0] _ways_9_io_resp_brSlots_0_lower;</a>
+<a name="479"><span class="lineNum">     479 </span>            :   wire [1:0]  _ways_9_io_resp_brSlots_0_tarStat;</a>
+<a name="480"><span class="lineNum">     480 </span>            :   wire        _ways_9_io_resp_brSlots_0_valid;</a>
+<a name="481"><span class="lineNum">     481 </span>            :   wire [3:0]  _ways_9_io_resp_tailSlot_offset;</a>
+<a name="482"><span class="lineNum">     482 </span>            :   wire [19:0] _ways_9_io_resp_tailSlot_lower;</a>
+<a name="483"><span class="lineNum">     483 </span>            :   wire [1:0]  _ways_9_io_resp_tailSlot_tarStat;</a>
+<a name="484"><span class="lineNum">     484 </span>            :   wire        _ways_9_io_resp_tailSlot_sharing;</a>
+<a name="485"><span class="lineNum">     485 </span>            :   wire        _ways_9_io_resp_tailSlot_valid;</a>
+<a name="486"><span class="lineNum">     486 </span>            :   wire [3:0]  _ways_9_io_resp_pftAddr;</a>
+<a name="487"><span class="lineNum">     487 </span>            :   wire        _ways_9_io_resp_carry;</a>
+<a name="488"><span class="lineNum">     488 </span>            :   wire        _ways_9_io_resp_always_taken_0;</a>
+<a name="489"><span class="lineNum">     489 </span>            :   wire        _ways_9_io_resp_always_taken_1;</a>
+<a name="490"><span class="lineNum">     490 </span>            :   wire        _ways_9_io_resp_hit;</a>
+<a name="491"><span class="lineNum">     491 </span>            :   wire        _ways_9_io_update_hit;</a>
+<a name="492"><span class="lineNum">     492 </span>            :   wire [3:0]  _ways_8_io_resp_brSlots_0_offset;</a>
+<a name="493"><span class="lineNum">     493 </span>            :   wire [11:0] _ways_8_io_resp_brSlots_0_lower;</a>
+<a name="494"><span class="lineNum">     494 </span>            :   wire [1:0]  _ways_8_io_resp_brSlots_0_tarStat;</a>
+<a name="495"><span class="lineNum">     495 </span>            :   wire        _ways_8_io_resp_brSlots_0_valid;</a>
+<a name="496"><span class="lineNum">     496 </span>            :   wire [3:0]  _ways_8_io_resp_tailSlot_offset;</a>
+<a name="497"><span class="lineNum">     497 </span>            :   wire [19:0] _ways_8_io_resp_tailSlot_lower;</a>
+<a name="498"><span class="lineNum">     498 </span>            :   wire [1:0]  _ways_8_io_resp_tailSlot_tarStat;</a>
+<a name="499"><span class="lineNum">     499 </span>            :   wire        _ways_8_io_resp_tailSlot_sharing;</a>
+<a name="500"><span class="lineNum">     500 </span>            :   wire        _ways_8_io_resp_tailSlot_valid;</a>
+<a name="501"><span class="lineNum">     501 </span>            :   wire [3:0]  _ways_8_io_resp_pftAddr;</a>
+<a name="502"><span class="lineNum">     502 </span>            :   wire        _ways_8_io_resp_carry;</a>
+<a name="503"><span class="lineNum">     503 </span>            :   wire        _ways_8_io_resp_always_taken_0;</a>
+<a name="504"><span class="lineNum">     504 </span>            :   wire        _ways_8_io_resp_always_taken_1;</a>
+<a name="505"><span class="lineNum">     505 </span>            :   wire        _ways_8_io_resp_hit;</a>
+<a name="506"><span class="lineNum">     506 </span>            :   wire        _ways_8_io_update_hit;</a>
+<a name="507"><span class="lineNum">     507 </span>            :   wire [3:0]  _ways_7_io_resp_brSlots_0_offset;</a>
+<a name="508"><span class="lineNum">     508 </span>            :   wire [11:0] _ways_7_io_resp_brSlots_0_lower;</a>
+<a name="509"><span class="lineNum">     509 </span>            :   wire [1:0]  _ways_7_io_resp_brSlots_0_tarStat;</a>
+<a name="510"><span class="lineNum">     510 </span>            :   wire        _ways_7_io_resp_brSlots_0_valid;</a>
+<a name="511"><span class="lineNum">     511 </span>            :   wire [3:0]  _ways_7_io_resp_tailSlot_offset;</a>
+<a name="512"><span class="lineNum">     512 </span>            :   wire [19:0] _ways_7_io_resp_tailSlot_lower;</a>
+<a name="513"><span class="lineNum">     513 </span>            :   wire [1:0]  _ways_7_io_resp_tailSlot_tarStat;</a>
+<a name="514"><span class="lineNum">     514 </span>            :   wire        _ways_7_io_resp_tailSlot_sharing;</a>
+<a name="515"><span class="lineNum">     515 </span>            :   wire        _ways_7_io_resp_tailSlot_valid;</a>
+<a name="516"><span class="lineNum">     516 </span>            :   wire [3:0]  _ways_7_io_resp_pftAddr;</a>
+<a name="517"><span class="lineNum">     517 </span>            :   wire        _ways_7_io_resp_carry;</a>
+<a name="518"><span class="lineNum">     518 </span>            :   wire        _ways_7_io_resp_always_taken_0;</a>
+<a name="519"><span class="lineNum">     519 </span>            :   wire        _ways_7_io_resp_always_taken_1;</a>
+<a name="520"><span class="lineNum">     520 </span>            :   wire        _ways_7_io_resp_hit;</a>
+<a name="521"><span class="lineNum">     521 </span>            :   wire        _ways_7_io_update_hit;</a>
+<a name="522"><span class="lineNum">     522 </span>            :   wire [3:0]  _ways_6_io_resp_brSlots_0_offset;</a>
+<a name="523"><span class="lineNum">     523 </span>            :   wire [11:0] _ways_6_io_resp_brSlots_0_lower;</a>
+<a name="524"><span class="lineNum">     524 </span>            :   wire [1:0]  _ways_6_io_resp_brSlots_0_tarStat;</a>
+<a name="525"><span class="lineNum">     525 </span>            :   wire        _ways_6_io_resp_brSlots_0_valid;</a>
+<a name="526"><span class="lineNum">     526 </span>            :   wire [3:0]  _ways_6_io_resp_tailSlot_offset;</a>
+<a name="527"><span class="lineNum">     527 </span>            :   wire [19:0] _ways_6_io_resp_tailSlot_lower;</a>
+<a name="528"><span class="lineNum">     528 </span>            :   wire [1:0]  _ways_6_io_resp_tailSlot_tarStat;</a>
+<a name="529"><span class="lineNum">     529 </span>            :   wire        _ways_6_io_resp_tailSlot_sharing;</a>
+<a name="530"><span class="lineNum">     530 </span>            :   wire        _ways_6_io_resp_tailSlot_valid;</a>
+<a name="531"><span class="lineNum">     531 </span>            :   wire [3:0]  _ways_6_io_resp_pftAddr;</a>
+<a name="532"><span class="lineNum">     532 </span>            :   wire        _ways_6_io_resp_carry;</a>
+<a name="533"><span class="lineNum">     533 </span>            :   wire        _ways_6_io_resp_always_taken_0;</a>
+<a name="534"><span class="lineNum">     534 </span>            :   wire        _ways_6_io_resp_always_taken_1;</a>
+<a name="535"><span class="lineNum">     535 </span>            :   wire        _ways_6_io_resp_hit;</a>
+<a name="536"><span class="lineNum">     536 </span>            :   wire        _ways_6_io_update_hit;</a>
+<a name="537"><span class="lineNum">     537 </span>            :   wire [3:0]  _ways_5_io_resp_brSlots_0_offset;</a>
+<a name="538"><span class="lineNum">     538 </span>            :   wire [11:0] _ways_5_io_resp_brSlots_0_lower;</a>
+<a name="539"><span class="lineNum">     539 </span>            :   wire [1:0]  _ways_5_io_resp_brSlots_0_tarStat;</a>
+<a name="540"><span class="lineNum">     540 </span>            :   wire        _ways_5_io_resp_brSlots_0_valid;</a>
+<a name="541"><span class="lineNum">     541 </span>            :   wire [3:0]  _ways_5_io_resp_tailSlot_offset;</a>
+<a name="542"><span class="lineNum">     542 </span>            :   wire [19:0] _ways_5_io_resp_tailSlot_lower;</a>
+<a name="543"><span class="lineNum">     543 </span>            :   wire [1:0]  _ways_5_io_resp_tailSlot_tarStat;</a>
+<a name="544"><span class="lineNum">     544 </span>            :   wire        _ways_5_io_resp_tailSlot_sharing;</a>
+<a name="545"><span class="lineNum">     545 </span>            :   wire        _ways_5_io_resp_tailSlot_valid;</a>
+<a name="546"><span class="lineNum">     546 </span>            :   wire [3:0]  _ways_5_io_resp_pftAddr;</a>
+<a name="547"><span class="lineNum">     547 </span>            :   wire        _ways_5_io_resp_carry;</a>
+<a name="548"><span class="lineNum">     548 </span>            :   wire        _ways_5_io_resp_always_taken_0;</a>
+<a name="549"><span class="lineNum">     549 </span>            :   wire        _ways_5_io_resp_always_taken_1;</a>
+<a name="550"><span class="lineNum">     550 </span>            :   wire        _ways_5_io_resp_hit;</a>
+<a name="551"><span class="lineNum">     551 </span>            :   wire        _ways_5_io_update_hit;</a>
+<a name="552"><span class="lineNum">     552 </span>            :   wire [3:0]  _ways_4_io_resp_brSlots_0_offset;</a>
+<a name="553"><span class="lineNum">     553 </span>            :   wire [11:0] _ways_4_io_resp_brSlots_0_lower;</a>
+<a name="554"><span class="lineNum">     554 </span>            :   wire [1:0]  _ways_4_io_resp_brSlots_0_tarStat;</a>
+<a name="555"><span class="lineNum">     555 </span>            :   wire        _ways_4_io_resp_brSlots_0_valid;</a>
+<a name="556"><span class="lineNum">     556 </span>            :   wire [3:0]  _ways_4_io_resp_tailSlot_offset;</a>
+<a name="557"><span class="lineNum">     557 </span>            :   wire [19:0] _ways_4_io_resp_tailSlot_lower;</a>
+<a name="558"><span class="lineNum">     558 </span>            :   wire [1:0]  _ways_4_io_resp_tailSlot_tarStat;</a>
+<a name="559"><span class="lineNum">     559 </span>            :   wire        _ways_4_io_resp_tailSlot_sharing;</a>
+<a name="560"><span class="lineNum">     560 </span>            :   wire        _ways_4_io_resp_tailSlot_valid;</a>
+<a name="561"><span class="lineNum">     561 </span>            :   wire [3:0]  _ways_4_io_resp_pftAddr;</a>
+<a name="562"><span class="lineNum">     562 </span>            :   wire        _ways_4_io_resp_carry;</a>
+<a name="563"><span class="lineNum">     563 </span>            :   wire        _ways_4_io_resp_always_taken_0;</a>
+<a name="564"><span class="lineNum">     564 </span>            :   wire        _ways_4_io_resp_always_taken_1;</a>
+<a name="565"><span class="lineNum">     565 </span>            :   wire        _ways_4_io_resp_hit;</a>
+<a name="566"><span class="lineNum">     566 </span>            :   wire        _ways_4_io_update_hit;</a>
+<a name="567"><span class="lineNum">     567 </span>            :   wire [3:0]  _ways_3_io_resp_brSlots_0_offset;</a>
+<a name="568"><span class="lineNum">     568 </span>            :   wire [11:0] _ways_3_io_resp_brSlots_0_lower;</a>
+<a name="569"><span class="lineNum">     569 </span>            :   wire [1:0]  _ways_3_io_resp_brSlots_0_tarStat;</a>
+<a name="570"><span class="lineNum">     570 </span>            :   wire        _ways_3_io_resp_brSlots_0_valid;</a>
+<a name="571"><span class="lineNum">     571 </span>            :   wire [3:0]  _ways_3_io_resp_tailSlot_offset;</a>
+<a name="572"><span class="lineNum">     572 </span>            :   wire [19:0] _ways_3_io_resp_tailSlot_lower;</a>
+<a name="573"><span class="lineNum">     573 </span>            :   wire [1:0]  _ways_3_io_resp_tailSlot_tarStat;</a>
+<a name="574"><span class="lineNum">     574 </span>            :   wire        _ways_3_io_resp_tailSlot_sharing;</a>
+<a name="575"><span class="lineNum">     575 </span>            :   wire        _ways_3_io_resp_tailSlot_valid;</a>
+<a name="576"><span class="lineNum">     576 </span>            :   wire [3:0]  _ways_3_io_resp_pftAddr;</a>
+<a name="577"><span class="lineNum">     577 </span>            :   wire        _ways_3_io_resp_carry;</a>
+<a name="578"><span class="lineNum">     578 </span>            :   wire        _ways_3_io_resp_always_taken_0;</a>
+<a name="579"><span class="lineNum">     579 </span>            :   wire        _ways_3_io_resp_always_taken_1;</a>
+<a name="580"><span class="lineNum">     580 </span>            :   wire        _ways_3_io_resp_hit;</a>
+<a name="581"><span class="lineNum">     581 </span>            :   wire        _ways_3_io_update_hit;</a>
+<a name="582"><span class="lineNum">     582 </span>            :   wire [3:0]  _ways_2_io_resp_brSlots_0_offset;</a>
+<a name="583"><span class="lineNum">     583 </span>            :   wire [11:0] _ways_2_io_resp_brSlots_0_lower;</a>
+<a name="584"><span class="lineNum">     584 </span>            :   wire [1:0]  _ways_2_io_resp_brSlots_0_tarStat;</a>
+<a name="585"><span class="lineNum">     585 </span>            :   wire        _ways_2_io_resp_brSlots_0_valid;</a>
+<a name="586"><span class="lineNum">     586 </span>            :   wire [3:0]  _ways_2_io_resp_tailSlot_offset;</a>
+<a name="587"><span class="lineNum">     587 </span>            :   wire [19:0] _ways_2_io_resp_tailSlot_lower;</a>
+<a name="588"><span class="lineNum">     588 </span>            :   wire [1:0]  _ways_2_io_resp_tailSlot_tarStat;</a>
+<a name="589"><span class="lineNum">     589 </span>            :   wire        _ways_2_io_resp_tailSlot_sharing;</a>
+<a name="590"><span class="lineNum">     590 </span>            :   wire        _ways_2_io_resp_tailSlot_valid;</a>
+<a name="591"><span class="lineNum">     591 </span>            :   wire [3:0]  _ways_2_io_resp_pftAddr;</a>
+<a name="592"><span class="lineNum">     592 </span>            :   wire        _ways_2_io_resp_carry;</a>
+<a name="593"><span class="lineNum">     593 </span>            :   wire        _ways_2_io_resp_always_taken_0;</a>
+<a name="594"><span class="lineNum">     594 </span>            :   wire        _ways_2_io_resp_always_taken_1;</a>
+<a name="595"><span class="lineNum">     595 </span>            :   wire        _ways_2_io_resp_hit;</a>
+<a name="596"><span class="lineNum">     596 </span>            :   wire        _ways_2_io_update_hit;</a>
+<a name="597"><span class="lineNum">     597 </span>            :   wire [3:0]  _ways_1_io_resp_brSlots_0_offset;</a>
+<a name="598"><span class="lineNum">     598 </span>            :   wire [11:0] _ways_1_io_resp_brSlots_0_lower;</a>
+<a name="599"><span class="lineNum">     599 </span>            :   wire [1:0]  _ways_1_io_resp_brSlots_0_tarStat;</a>
+<a name="600"><span class="lineNum">     600 </span>            :   wire        _ways_1_io_resp_brSlots_0_valid;</a>
+<a name="601"><span class="lineNum">     601 </span>            :   wire [3:0]  _ways_1_io_resp_tailSlot_offset;</a>
+<a name="602"><span class="lineNum">     602 </span>            :   wire [19:0] _ways_1_io_resp_tailSlot_lower;</a>
+<a name="603"><span class="lineNum">     603 </span>            :   wire [1:0]  _ways_1_io_resp_tailSlot_tarStat;</a>
+<a name="604"><span class="lineNum">     604 </span>            :   wire        _ways_1_io_resp_tailSlot_sharing;</a>
+<a name="605"><span class="lineNum">     605 </span>            :   wire        _ways_1_io_resp_tailSlot_valid;</a>
+<a name="606"><span class="lineNum">     606 </span>            :   wire [3:0]  _ways_1_io_resp_pftAddr;</a>
+<a name="607"><span class="lineNum">     607 </span>            :   wire        _ways_1_io_resp_carry;</a>
+<a name="608"><span class="lineNum">     608 </span>            :   wire        _ways_1_io_resp_always_taken_0;</a>
+<a name="609"><span class="lineNum">     609 </span>            :   wire        _ways_1_io_resp_always_taken_1;</a>
+<a name="610"><span class="lineNum">     610 </span>            :   wire        _ways_1_io_resp_hit;</a>
+<a name="611"><span class="lineNum">     611 </span>            :   wire        _ways_1_io_update_hit;</a>
+<a name="612"><span class="lineNum">     612 </span>            :   wire [3:0]  _ways_0_io_resp_brSlots_0_offset;</a>
+<a name="613"><span class="lineNum">     613 </span>            :   wire [11:0] _ways_0_io_resp_brSlots_0_lower;</a>
+<a name="614"><span class="lineNum">     614 </span>            :   wire [1:0]  _ways_0_io_resp_brSlots_0_tarStat;</a>
+<a name="615"><span class="lineNum">     615 </span>            :   wire        _ways_0_io_resp_brSlots_0_valid;</a>
+<a name="616"><span class="lineNum">     616 </span>            :   wire [3:0]  _ways_0_io_resp_tailSlot_offset;</a>
+<a name="617"><span class="lineNum">     617 </span>            :   wire [19:0] _ways_0_io_resp_tailSlot_lower;</a>
+<a name="618"><span class="lineNum">     618 </span>            :   wire [1:0]  _ways_0_io_resp_tailSlot_tarStat;</a>
+<a name="619"><span class="lineNum">     619 </span>            :   wire        _ways_0_io_resp_tailSlot_sharing;</a>
+<a name="620"><span class="lineNum">     620 </span>            :   wire        _ways_0_io_resp_tailSlot_valid;</a>
+<a name="621"><span class="lineNum">     621 </span>            :   wire [3:0]  _ways_0_io_resp_pftAddr;</a>
+<a name="622"><span class="lineNum">     622 </span>            :   wire        _ways_0_io_resp_carry;</a>
+<a name="623"><span class="lineNum">     623 </span>            :   wire        _ways_0_io_resp_always_taken_0;</a>
+<a name="624"><span class="lineNum">     624 </span>            :   wire        _ways_0_io_resp_always_taken_1;</a>
+<a name="625"><span class="lineNum">     625 </span>            :   wire        _ways_0_io_resp_hit;</a>
+<a name="626"><span class="lineNum">     626 </span>            :   wire        _ways_0_io_update_hit;</a>
+<a name="627"><span class="lineNum">     627 </span>            :   wire [35:0] _reset_vector_delay_io_out;</a>
+<a name="628"><span class="lineNum">     628 </span><span class="lineCov">       9878 :   reg  [40:0] s1_pc_dup_0;</span></a>
+<a name="629"><span class="lineNum">     629 </span><span class="lineCov">       9918 :   reg  [40:0] s1_pc_dup_1;</span></a>
+<a name="630"><span class="lineNum">     630 </span><span class="lineCov">       9857 :   reg  [40:0] s1_pc_dup_2;</span></a>
+<a name="631"><span class="lineNum">     631 </span><span class="lineCov">       9933 :   reg  [40:0] s1_pc_dup_3;</span></a>
+<a name="632"><span class="lineNum">     632 </span><span class="lineCov">         77 :   reg         REG;</span></a>
+<a name="633"><span class="lineNum">     633 </span><span class="lineCov">         98 :   reg         REG_1;</span></a>
+<a name="634"><span class="lineNum">     634 </span><span class="lineCov">         50 :   reg  [1:0]  ctrs_0_0;</span></a>
+<a name="635"><span class="lineNum">     635 </span><span class="lineCov">         47 :   reg  [1:0]  ctrs_0_1;</span></a>
+<a name="636"><span class="lineNum">     636 </span><span class="lineCov">         44 :   reg  [1:0]  ctrs_1_0;</span></a>
+<a name="637"><span class="lineNum">     637 </span><span class="lineCov">         48 :   reg  [1:0]  ctrs_1_1;</span></a>
+<a name="638"><span class="lineNum">     638 </span><span class="lineCov">         43 :   reg  [1:0]  ctrs_2_0;</span></a>
+<a name="639"><span class="lineNum">     639 </span><span class="lineCov">         40 :   reg  [1:0]  ctrs_2_1;</span></a>
+<a name="640"><span class="lineNum">     640 </span><span class="lineCov">         43 :   reg  [1:0]  ctrs_3_0;</span></a>
+<a name="641"><span class="lineNum">     641 </span><span class="lineCov">         53 :   reg  [1:0]  ctrs_3_1;</span></a>
+<a name="642"><span class="lineNum">     642 </span><span class="lineCov">         48 :   reg  [1:0]  ctrs_4_0;</span></a>
+<a name="643"><span class="lineNum">     643 </span><span class="lineCov">         42 :   reg  [1:0]  ctrs_4_1;</span></a>
+<a name="644"><span class="lineNum">     644 </span><span class="lineCov">         57 :   reg  [1:0]  ctrs_5_0;</span></a>
+<a name="645"><span class="lineNum">     645 </span><span class="lineCov">         45 :   reg  [1:0]  ctrs_5_1;</span></a>
+<a name="646"><span class="lineNum">     646 </span><span class="lineCov">         47 :   reg  [1:0]  ctrs_6_0;</span></a>
+<a name="647"><span class="lineNum">     647 </span><span class="lineCov">         37 :   reg  [1:0]  ctrs_6_1;</span></a>
+<a name="648"><span class="lineNum">     648 </span><span class="lineCov">         51 :   reg  [1:0]  ctrs_7_0;</span></a>
+<a name="649"><span class="lineNum">     649 </span><span class="lineCov">         38 :   reg  [1:0]  ctrs_7_1;</span></a>
+<a name="650"><span class="lineNum">     650 </span><span class="lineCov">         52 :   reg  [1:0]  ctrs_8_0;</span></a>
+<a name="651"><span class="lineNum">     651 </span><span class="lineCov">         41 :   reg  [1:0]  ctrs_8_1;</span></a>
+<a name="652"><span class="lineNum">     652 </span><span class="lineCov">         47 :   reg  [1:0]  ctrs_9_0;</span></a>
+<a name="653"><span class="lineNum">     653 </span><span class="lineCov">         47 :   reg  [1:0]  ctrs_9_1;</span></a>
+<a name="654"><span class="lineNum">     654 </span><span class="lineCov">         60 :   reg  [1:0]  ctrs_10_0;</span></a>
+<a name="655"><span class="lineNum">     655 </span><span class="lineCov">         40 :   reg  [1:0]  ctrs_10_1;</span></a>
+<a name="656"><span class="lineNum">     656 </span><span class="lineCov">         41 :   reg  [1:0]  ctrs_11_0;</span></a>
+<a name="657"><span class="lineNum">     657 </span><span class="lineCov">         42 :   reg  [1:0]  ctrs_11_1;</span></a>
+<a name="658"><span class="lineNum">     658 </span><span class="lineCov">         57 :   reg  [1:0]  ctrs_12_0;</span></a>
+<a name="659"><span class="lineNum">     659 </span><span class="lineCov">         46 :   reg  [1:0]  ctrs_12_1;</span></a>
+<a name="660"><span class="lineNum">     660 </span><span class="lineCov">         47 :   reg  [1:0]  ctrs_13_0;</span></a>
+<a name="661"><span class="lineNum">     661 </span><span class="lineCov">         51 :   reg  [1:0]  ctrs_13_1;</span></a>
+<a name="662"><span class="lineNum">     662 </span><span class="lineCov">         51 :   reg  [1:0]  ctrs_14_0;</span></a>
+<a name="663"><span class="lineNum">     663 </span><span class="lineCov">         49 :   reg  [1:0]  ctrs_14_1;</span></a>
+<a name="664"><span class="lineNum">     664 </span><span class="lineCov">         38 :   reg  [1:0]  ctrs_15_0;</span></a>
+<a name="665"><span class="lineNum">     665 </span><span class="lineCov">         42 :   reg  [1:0]  ctrs_15_1;</span></a>
+<a name="666"><span class="lineNum">     666 </span><span class="lineCov">         51 :   reg  [1:0]  ctrs_16_0;</span></a>
+<a name="667"><span class="lineNum">     667 </span><span class="lineCov">         39 :   reg  [1:0]  ctrs_16_1;</span></a>
+<a name="668"><span class="lineNum">     668 </span><span class="lineCov">         42 :   reg  [1:0]  ctrs_17_0;</span></a>
+<a name="669"><span class="lineNum">     669 </span><span class="lineCov">         42 :   reg  [1:0]  ctrs_17_1;</span></a>
+<a name="670"><span class="lineNum">     670 </span><span class="lineCov">         42 :   reg  [1:0]  ctrs_18_0;</span></a>
+<a name="671"><span class="lineNum">     671 </span><span class="lineCov">         54 :   reg  [1:0]  ctrs_18_1;</span></a>
+<a name="672"><span class="lineNum">     672 </span><span class="lineCov">         53 :   reg  [1:0]  ctrs_19_0;</span></a>
+<a name="673"><span class="lineNum">     673 </span><span class="lineCov">         55 :   reg  [1:0]  ctrs_19_1;</span></a>
+<a name="674"><span class="lineNum">     674 </span><span class="lineCov">         44 :   reg  [1:0]  ctrs_20_0;</span></a>
+<a name="675"><span class="lineNum">     675 </span><span class="lineCov">         42 :   reg  [1:0]  ctrs_20_1;</span></a>
+<a name="676"><span class="lineNum">     676 </span><span class="lineCov">         45 :   reg  [1:0]  ctrs_21_0;</span></a>
+<a name="677"><span class="lineNum">     677 </span><span class="lineCov">         52 :   reg  [1:0]  ctrs_21_1;</span></a>
+<a name="678"><span class="lineNum">     678 </span><span class="lineCov">         50 :   reg  [1:0]  ctrs_22_0;</span></a>
+<a name="679"><span class="lineNum">     679 </span><span class="lineCov">         50 :   reg  [1:0]  ctrs_22_1;</span></a>
+<a name="680"><span class="lineNum">     680 </span><span class="lineCov">         49 :   reg  [1:0]  ctrs_23_0;</span></a>
+<a name="681"><span class="lineNum">     681 </span><span class="lineCov">         47 :   reg  [1:0]  ctrs_23_1;</span></a>
+<a name="682"><span class="lineNum">     682 </span><span class="lineCov">         44 :   reg  [1:0]  ctrs_24_0;</span></a>
+<a name="683"><span class="lineNum">     683 </span><span class="lineCov">         43 :   reg  [1:0]  ctrs_24_1;</span></a>
+<a name="684"><span class="lineNum">     684 </span><span class="lineCov">         56 :   reg  [1:0]  ctrs_25_0;</span></a>
+<a name="685"><span class="lineNum">     685 </span><span class="lineCov">         46 :   reg  [1:0]  ctrs_25_1;</span></a>
+<a name="686"><span class="lineNum">     686 </span><span class="lineCov">         45 :   reg  [1:0]  ctrs_26_0;</span></a>
+<a name="687"><span class="lineNum">     687 </span><span class="lineCov">         45 :   reg  [1:0]  ctrs_26_1;</span></a>
+<a name="688"><span class="lineNum">     688 </span><span class="lineCov">         42 :   reg  [1:0]  ctrs_27_0;</span></a>
+<a name="689"><span class="lineNum">     689 </span><span class="lineCov">         41 :   reg  [1:0]  ctrs_27_1;</span></a>
+<a name="690"><span class="lineNum">     690 </span><span class="lineCov">         37 :   reg  [1:0]  ctrs_28_0;</span></a>
+<a name="691"><span class="lineNum">     691 </span><span class="lineCov">         49 :   reg  [1:0]  ctrs_28_1;</span></a>
+<a name="692"><span class="lineNum">     692 </span><span class="lineCov">         42 :   reg  [1:0]  ctrs_29_0;</span></a>
+<a name="693"><span class="lineNum">     693 </span><span class="lineCov">         49 :   reg  [1:0]  ctrs_29_1;</span></a>
+<a name="694"><span class="lineNum">     694 </span><span class="lineCov">         57 :   reg  [1:0]  ctrs_30_0;</span></a>
+<a name="695"><span class="lineNum">     695 </span><span class="lineCov">         52 :   reg  [1:0]  ctrs_30_1;</span></a>
+<a name="696"><span class="lineNum">     696 </span><span class="lineCov">         43 :   reg  [1:0]  ctrs_31_0;</span></a>
+<a name="697"><span class="lineNum">     697 </span><span class="lineCov">         46 :   reg  [1:0]  ctrs_31_1;</span></a>
+<a name="698"><span class="lineNum">     698 </span><span class="lineCov">        784 :   reg  [30:0] state_reg;</span></a>
+<a name="699"><span class="lineNum">     699 </span><span class="lineCov">        480 :   wire [31:0] s1_hit_oh =</span></a>
+<a name="700"><span class="lineNum">     700 </span>            :     {_ways_31_io_resp_hit,</a>
+<a name="701"><span class="lineNum">     701 </span>            :      _ways_30_io_resp_hit,</a>
+<a name="702"><span class="lineNum">     702 </span>            :      _ways_29_io_resp_hit,</a>
+<a name="703"><span class="lineNum">     703 </span>            :      _ways_28_io_resp_hit,</a>
+<a name="704"><span class="lineNum">     704 </span>            :      _ways_27_io_resp_hit,</a>
+<a name="705"><span class="lineNum">     705 </span>            :      _ways_26_io_resp_hit,</a>
+<a name="706"><span class="lineNum">     706 </span>            :      _ways_25_io_resp_hit,</a>
+<a name="707"><span class="lineNum">     707 </span>            :      _ways_24_io_resp_hit,</a>
+<a name="708"><span class="lineNum">     708 </span>            :      _ways_23_io_resp_hit,</a>
+<a name="709"><span class="lineNum">     709 </span>            :      _ways_22_io_resp_hit,</a>
+<a name="710"><span class="lineNum">     710 </span>            :      _ways_21_io_resp_hit,</a>
+<a name="711"><span class="lineNum">     711 </span>            :      _ways_20_io_resp_hit,</a>
+<a name="712"><span class="lineNum">     712 </span>            :      _ways_19_io_resp_hit,</a>
+<a name="713"><span class="lineNum">     713 </span>            :      _ways_18_io_resp_hit,</a>
+<a name="714"><span class="lineNum">     714 </span>            :      _ways_17_io_resp_hit,</a>
+<a name="715"><span class="lineNum">     715 </span>            :      _ways_16_io_resp_hit,</a>
+<a name="716"><span class="lineNum">     716 </span>            :      _ways_15_io_resp_hit,</a>
+<a name="717"><span class="lineNum">     717 </span>            :      _ways_14_io_resp_hit,</a>
+<a name="718"><span class="lineNum">     718 </span>            :      _ways_13_io_resp_hit,</a>
+<a name="719"><span class="lineNum">     719 </span>            :      _ways_12_io_resp_hit,</a>
+<a name="720"><span class="lineNum">     720 </span>            :      _ways_11_io_resp_hit,</a>
+<a name="721"><span class="lineNum">     721 </span>            :      _ways_10_io_resp_hit,</a>
+<a name="722"><span class="lineNum">     722 </span>            :      _ways_9_io_resp_hit,</a>
+<a name="723"><span class="lineNum">     723 </span>            :      _ways_8_io_resp_hit,</a>
+<a name="724"><span class="lineNum">     724 </span>            :      _ways_7_io_resp_hit,</a>
+<a name="725"><span class="lineNum">     725 </span>            :      _ways_6_io_resp_hit,</a>
+<a name="726"><span class="lineNum">     726 </span>            :      _ways_5_io_resp_hit,</a>
+<a name="727"><span class="lineNum">     727 </span>            :      _ways_4_io_resp_hit,</a>
+<a name="728"><span class="lineNum">     728 </span>            :      _ways_3_io_resp_hit,</a>
+<a name="729"><span class="lineNum">     729 </span>            :      _ways_2_io_resp_hit,</a>
+<a name="730"><span class="lineNum">     730 </span>            :      _ways_1_io_resp_hit,</a>
+<a name="731"><span class="lineNum">     731 </span>            :      _ways_0_io_resp_hit};</a>
+<a name="732"><span class="lineNum">     732 </span>            :   wire        _target_T_18 = _ways_0_io_resp_tailSlot_tarStat == 2'h1;</a>
+<a name="733"><span class="lineNum">     733 </span>            :   wire        _target_T_19 = _ways_0_io_resp_tailSlot_tarStat == 2'h2;</a>
+<a name="734"><span class="lineNum">     734 </span>            :   wire        _target_T_20 = _ways_0_io_resp_tailSlot_tarStat == 2'h0;</a>
+<a name="735"><span class="lineNum">     735 </span><span class="lineCov">         26 :   wire        s1_possible_full_preds_0_fallThroughErr =</span></a>
+<a name="736"><span class="lineNum">     736 </span>            :     {1'h0, s1_pc_dup_0[4:1]} &gt;= {_ways_0_io_resp_carry, _ways_0_io_resp_pftAddr};</a>
+<a name="737"><span class="lineNum">     737 </span>            :   wire [40:0] _s1_possible_full_preds_31_fallThroughAddr_T = 41'(s1_pc_dup_0 + 41'h20);</a>
+<a name="738"><span class="lineNum">     738 </span>            :   wire        _target_T_45 = _ways_1_io_resp_tailSlot_tarStat == 2'h1;</a>
+<a name="739"><span class="lineNum">     739 </span>            :   wire        _target_T_46 = _ways_1_io_resp_tailSlot_tarStat == 2'h2;</a>
+<a name="740"><span class="lineNum">     740 </span>            :   wire        _target_T_47 = _ways_1_io_resp_tailSlot_tarStat == 2'h0;</a>
+<a name="741"><span class="lineNum">     741 </span><span class="lineCov">         23 :   wire        s1_possible_full_preds_1_fallThroughErr =</span></a>
+<a name="742"><span class="lineNum">     742 </span>            :     {1'h0, s1_pc_dup_0[4:1]} &gt;= {_ways_1_io_resp_carry, _ways_1_io_resp_pftAddr};</a>
+<a name="743"><span class="lineNum">     743 </span>            :   wire        _target_T_72 = _ways_2_io_resp_tailSlot_tarStat == 2'h1;</a>
+<a name="744"><span class="lineNum">     744 </span>            :   wire        _target_T_73 = _ways_2_io_resp_tailSlot_tarStat == 2'h2;</a>
+<a name="745"><span class="lineNum">     745 </span>            :   wire        _target_T_74 = _ways_2_io_resp_tailSlot_tarStat == 2'h0;</a>
+<a name="746"><span class="lineNum">     746 </span><span class="lineCov">         29 :   wire        s1_possible_full_preds_2_fallThroughErr =</span></a>
+<a name="747"><span class="lineNum">     747 </span>            :     {1'h0, s1_pc_dup_0[4:1]} &gt;= {_ways_2_io_resp_carry, _ways_2_io_resp_pftAddr};</a>
+<a name="748"><span class="lineNum">     748 </span>            :   wire        _target_T_99 = _ways_3_io_resp_tailSlot_tarStat == 2'h1;</a>
+<a name="749"><span class="lineNum">     749 </span>            :   wire        _target_T_100 = _ways_3_io_resp_tailSlot_tarStat == 2'h2;</a>
+<a name="750"><span class="lineNum">     750 </span>            :   wire        _target_T_101 = _ways_3_io_resp_tailSlot_tarStat == 2'h0;</a>
+<a name="751"><span class="lineNum">     751 </span><span class="lineCov">         26 :   wire        s1_possible_full_preds_3_fallThroughErr =</span></a>
+<a name="752"><span class="lineNum">     752 </span>            :     {1'h0, s1_pc_dup_0[4:1]} &gt;= {_ways_3_io_resp_carry, _ways_3_io_resp_pftAddr};</a>
+<a name="753"><span class="lineNum">     753 </span>            :   wire        _target_T_126 = _ways_4_io_resp_tailSlot_tarStat == 2'h1;</a>
+<a name="754"><span class="lineNum">     754 </span>            :   wire        _target_T_127 = _ways_4_io_resp_tailSlot_tarStat == 2'h2;</a>
+<a name="755"><span class="lineNum">     755 </span>            :   wire        _target_T_128 = _ways_4_io_resp_tailSlot_tarStat == 2'h0;</a>
+<a name="756"><span class="lineNum">     756 </span><span class="lineCov">         26 :   wire        s1_possible_full_preds_4_fallThroughErr =</span></a>
+<a name="757"><span class="lineNum">     757 </span>            :     {1'h0, s1_pc_dup_0[4:1]} &gt;= {_ways_4_io_resp_carry, _ways_4_io_resp_pftAddr};</a>
+<a name="758"><span class="lineNum">     758 </span>            :   wire        _target_T_153 = _ways_5_io_resp_tailSlot_tarStat == 2'h1;</a>
+<a name="759"><span class="lineNum">     759 </span>            :   wire        _target_T_154 = _ways_5_io_resp_tailSlot_tarStat == 2'h2;</a>
+<a name="760"><span class="lineNum">     760 </span>            :   wire        _target_T_155 = _ways_5_io_resp_tailSlot_tarStat == 2'h0;</a>
+<a name="761"><span class="lineNum">     761 </span><span class="lineCov">         31 :   wire        s1_possible_full_preds_5_fallThroughErr =</span></a>
+<a name="762"><span class="lineNum">     762 </span>            :     {1'h0, s1_pc_dup_0[4:1]} &gt;= {_ways_5_io_resp_carry, _ways_5_io_resp_pftAddr};</a>
+<a name="763"><span class="lineNum">     763 </span>            :   wire        _target_T_180 = _ways_6_io_resp_tailSlot_tarStat == 2'h1;</a>
+<a name="764"><span class="lineNum">     764 </span>            :   wire        _target_T_181 = _ways_6_io_resp_tailSlot_tarStat == 2'h2;</a>
+<a name="765"><span class="lineNum">     765 </span>            :   wire        _target_T_182 = _ways_6_io_resp_tailSlot_tarStat == 2'h0;</a>
+<a name="766"><span class="lineNum">     766 </span><span class="lineCov">         34 :   wire        s1_possible_full_preds_6_fallThroughErr =</span></a>
+<a name="767"><span class="lineNum">     767 </span>            :     {1'h0, s1_pc_dup_0[4:1]} &gt;= {_ways_6_io_resp_carry, _ways_6_io_resp_pftAddr};</a>
+<a name="768"><span class="lineNum">     768 </span>            :   wire        _target_T_207 = _ways_7_io_resp_tailSlot_tarStat == 2'h1;</a>
+<a name="769"><span class="lineNum">     769 </span>            :   wire        _target_T_208 = _ways_7_io_resp_tailSlot_tarStat == 2'h2;</a>
+<a name="770"><span class="lineNum">     770 </span>            :   wire        _target_T_209 = _ways_7_io_resp_tailSlot_tarStat == 2'h0;</a>
+<a name="771"><span class="lineNum">     771 </span><span class="lineCov">         23 :   wire        s1_possible_full_preds_7_fallThroughErr =</span></a>
+<a name="772"><span class="lineNum">     772 </span>            :     {1'h0, s1_pc_dup_0[4:1]} &gt;= {_ways_7_io_resp_carry, _ways_7_io_resp_pftAddr};</a>
+<a name="773"><span class="lineNum">     773 </span>            :   wire        _target_T_234 = _ways_8_io_resp_tailSlot_tarStat == 2'h1;</a>
+<a name="774"><span class="lineNum">     774 </span>            :   wire        _target_T_235 = _ways_8_io_resp_tailSlot_tarStat == 2'h2;</a>
+<a name="775"><span class="lineNum">     775 </span>            :   wire        _target_T_236 = _ways_8_io_resp_tailSlot_tarStat == 2'h0;</a>
+<a name="776"><span class="lineNum">     776 </span><span class="lineCov">         25 :   wire        s1_possible_full_preds_8_fallThroughErr =</span></a>
+<a name="777"><span class="lineNum">     777 </span>            :     {1'h0, s1_pc_dup_0[4:1]} &gt;= {_ways_8_io_resp_carry, _ways_8_io_resp_pftAddr};</a>
+<a name="778"><span class="lineNum">     778 </span>            :   wire        _target_T_261 = _ways_9_io_resp_tailSlot_tarStat == 2'h1;</a>
+<a name="779"><span class="lineNum">     779 </span>            :   wire        _target_T_262 = _ways_9_io_resp_tailSlot_tarStat == 2'h2;</a>
+<a name="780"><span class="lineNum">     780 </span>            :   wire        _target_T_263 = _ways_9_io_resp_tailSlot_tarStat == 2'h0;</a>
+<a name="781"><span class="lineNum">     781 </span><span class="lineCov">         22 :   wire        s1_possible_full_preds_9_fallThroughErr =</span></a>
+<a name="782"><span class="lineNum">     782 </span>            :     {1'h0, s1_pc_dup_0[4:1]} &gt;= {_ways_9_io_resp_carry, _ways_9_io_resp_pftAddr};</a>
+<a name="783"><span class="lineNum">     783 </span>            :   wire        _target_T_288 = _ways_10_io_resp_tailSlot_tarStat == 2'h1;</a>
+<a name="784"><span class="lineNum">     784 </span>            :   wire        _target_T_289 = _ways_10_io_resp_tailSlot_tarStat == 2'h2;</a>
+<a name="785"><span class="lineNum">     785 </span>            :   wire        _target_T_290 = _ways_10_io_resp_tailSlot_tarStat == 2'h0;</a>
+<a name="786"><span class="lineNum">     786 </span><span class="lineCov">         24 :   wire        s1_possible_full_preds_10_fallThroughErr =</span></a>
+<a name="787"><span class="lineNum">     787 </span>            :     {1'h0, s1_pc_dup_0[4:1]} &gt;= {_ways_10_io_resp_carry, _ways_10_io_resp_pftAddr};</a>
+<a name="788"><span class="lineNum">     788 </span>            :   wire        _target_T_315 = _ways_11_io_resp_tailSlot_tarStat == 2'h1;</a>
+<a name="789"><span class="lineNum">     789 </span>            :   wire        _target_T_316 = _ways_11_io_resp_tailSlot_tarStat == 2'h2;</a>
+<a name="790"><span class="lineNum">     790 </span>            :   wire        _target_T_317 = _ways_11_io_resp_tailSlot_tarStat == 2'h0;</a>
+<a name="791"><span class="lineNum">     791 </span><span class="lineCov">         18 :   wire        s1_possible_full_preds_11_fallThroughErr =</span></a>
+<a name="792"><span class="lineNum">     792 </span>            :     {1'h0, s1_pc_dup_0[4:1]} &gt;= {_ways_11_io_resp_carry, _ways_11_io_resp_pftAddr};</a>
+<a name="793"><span class="lineNum">     793 </span>            :   wire        _target_T_342 = _ways_12_io_resp_tailSlot_tarStat == 2'h1;</a>
+<a name="794"><span class="lineNum">     794 </span>            :   wire        _target_T_343 = _ways_12_io_resp_tailSlot_tarStat == 2'h2;</a>
+<a name="795"><span class="lineNum">     795 </span>            :   wire        _target_T_344 = _ways_12_io_resp_tailSlot_tarStat == 2'h0;</a>
+<a name="796"><span class="lineNum">     796 </span><span class="lineCov">         25 :   wire        s1_possible_full_preds_12_fallThroughErr =</span></a>
+<a name="797"><span class="lineNum">     797 </span>            :     {1'h0, s1_pc_dup_0[4:1]} &gt;= {_ways_12_io_resp_carry, _ways_12_io_resp_pftAddr};</a>
+<a name="798"><span class="lineNum">     798 </span>            :   wire        _target_T_369 = _ways_13_io_resp_tailSlot_tarStat == 2'h1;</a>
+<a name="799"><span class="lineNum">     799 </span>            :   wire        _target_T_370 = _ways_13_io_resp_tailSlot_tarStat == 2'h2;</a>
+<a name="800"><span class="lineNum">     800 </span>            :   wire        _target_T_371 = _ways_13_io_resp_tailSlot_tarStat == 2'h0;</a>
+<a name="801"><span class="lineNum">     801 </span><span class="lineCov">         29 :   wire        s1_possible_full_preds_13_fallThroughErr =</span></a>
+<a name="802"><span class="lineNum">     802 </span>            :     {1'h0, s1_pc_dup_0[4:1]} &gt;= {_ways_13_io_resp_carry, _ways_13_io_resp_pftAddr};</a>
+<a name="803"><span class="lineNum">     803 </span>            :   wire        _target_T_396 = _ways_14_io_resp_tailSlot_tarStat == 2'h1;</a>
+<a name="804"><span class="lineNum">     804 </span>            :   wire        _target_T_397 = _ways_14_io_resp_tailSlot_tarStat == 2'h2;</a>
+<a name="805"><span class="lineNum">     805 </span>            :   wire        _target_T_398 = _ways_14_io_resp_tailSlot_tarStat == 2'h0;</a>
+<a name="806"><span class="lineNum">     806 </span><span class="lineCov">         25 :   wire        s1_possible_full_preds_14_fallThroughErr =</span></a>
+<a name="807"><span class="lineNum">     807 </span>            :     {1'h0, s1_pc_dup_0[4:1]} &gt;= {_ways_14_io_resp_carry, _ways_14_io_resp_pftAddr};</a>
+<a name="808"><span class="lineNum">     808 </span>            :   wire        _target_T_423 = _ways_15_io_resp_tailSlot_tarStat == 2'h1;</a>
+<a name="809"><span class="lineNum">     809 </span>            :   wire        _target_T_424 = _ways_15_io_resp_tailSlot_tarStat == 2'h2;</a>
+<a name="810"><span class="lineNum">     810 </span>            :   wire        _target_T_425 = _ways_15_io_resp_tailSlot_tarStat == 2'h0;</a>
+<a name="811"><span class="lineNum">     811 </span><span class="lineCov">         23 :   wire        s1_possible_full_preds_15_fallThroughErr =</span></a>
+<a name="812"><span class="lineNum">     812 </span>            :     {1'h0, s1_pc_dup_0[4:1]} &gt;= {_ways_15_io_resp_carry, _ways_15_io_resp_pftAddr};</a>
+<a name="813"><span class="lineNum">     813 </span>            :   wire        _target_T_450 = _ways_16_io_resp_tailSlot_tarStat == 2'h1;</a>
+<a name="814"><span class="lineNum">     814 </span>            :   wire        _target_T_451 = _ways_16_io_resp_tailSlot_tarStat == 2'h2;</a>
+<a name="815"><span class="lineNum">     815 </span>            :   wire        _target_T_452 = _ways_16_io_resp_tailSlot_tarStat == 2'h0;</a>
+<a name="816"><span class="lineNum">     816 </span><span class="lineCov">         18 :   wire        s1_possible_full_preds_16_fallThroughErr =</span></a>
+<a name="817"><span class="lineNum">     817 </span>            :     {1'h0, s1_pc_dup_0[4:1]} &gt;= {_ways_16_io_resp_carry, _ways_16_io_resp_pftAddr};</a>
+<a name="818"><span class="lineNum">     818 </span>            :   wire        _target_T_477 = _ways_17_io_resp_tailSlot_tarStat == 2'h1;</a>
+<a name="819"><span class="lineNum">     819 </span>            :   wire        _target_T_478 = _ways_17_io_resp_tailSlot_tarStat == 2'h2;</a>
+<a name="820"><span class="lineNum">     820 </span>            :   wire        _target_T_479 = _ways_17_io_resp_tailSlot_tarStat == 2'h0;</a>
+<a name="821"><span class="lineNum">     821 </span><span class="lineCov">         22 :   wire        s1_possible_full_preds_17_fallThroughErr =</span></a>
+<a name="822"><span class="lineNum">     822 </span>            :     {1'h0, s1_pc_dup_0[4:1]} &gt;= {_ways_17_io_resp_carry, _ways_17_io_resp_pftAddr};</a>
+<a name="823"><span class="lineNum">     823 </span>            :   wire        _target_T_504 = _ways_18_io_resp_tailSlot_tarStat == 2'h1;</a>
+<a name="824"><span class="lineNum">     824 </span>            :   wire        _target_T_505 = _ways_18_io_resp_tailSlot_tarStat == 2'h2;</a>
+<a name="825"><span class="lineNum">     825 </span>            :   wire        _target_T_506 = _ways_18_io_resp_tailSlot_tarStat == 2'h0;</a>
+<a name="826"><span class="lineNum">     826 </span><span class="lineCov">         25 :   wire        s1_possible_full_preds_18_fallThroughErr =</span></a>
+<a name="827"><span class="lineNum">     827 </span>            :     {1'h0, s1_pc_dup_0[4:1]} &gt;= {_ways_18_io_resp_carry, _ways_18_io_resp_pftAddr};</a>
+<a name="828"><span class="lineNum">     828 </span>            :   wire        _target_T_531 = _ways_19_io_resp_tailSlot_tarStat == 2'h1;</a>
+<a name="829"><span class="lineNum">     829 </span>            :   wire        _target_T_532 = _ways_19_io_resp_tailSlot_tarStat == 2'h2;</a>
+<a name="830"><span class="lineNum">     830 </span>            :   wire        _target_T_533 = _ways_19_io_resp_tailSlot_tarStat == 2'h0;</a>
+<a name="831"><span class="lineNum">     831 </span><span class="lineCov">         25 :   wire        s1_possible_full_preds_19_fallThroughErr =</span></a>
+<a name="832"><span class="lineNum">     832 </span>            :     {1'h0, s1_pc_dup_0[4:1]} &gt;= {_ways_19_io_resp_carry, _ways_19_io_resp_pftAddr};</a>
+<a name="833"><span class="lineNum">     833 </span>            :   wire        _target_T_558 = _ways_20_io_resp_tailSlot_tarStat == 2'h1;</a>
+<a name="834"><span class="lineNum">     834 </span>            :   wire        _target_T_559 = _ways_20_io_resp_tailSlot_tarStat == 2'h2;</a>
+<a name="835"><span class="lineNum">     835 </span>            :   wire        _target_T_560 = _ways_20_io_resp_tailSlot_tarStat == 2'h0;</a>
+<a name="836"><span class="lineNum">     836 </span><span class="lineCov">         21 :   wire        s1_possible_full_preds_20_fallThroughErr =</span></a>
+<a name="837"><span class="lineNum">     837 </span>            :     {1'h0, s1_pc_dup_0[4:1]} &gt;= {_ways_20_io_resp_carry, _ways_20_io_resp_pftAddr};</a>
+<a name="838"><span class="lineNum">     838 </span>            :   wire        _target_T_585 = _ways_21_io_resp_tailSlot_tarStat == 2'h1;</a>
+<a name="839"><span class="lineNum">     839 </span>            :   wire        _target_T_586 = _ways_21_io_resp_tailSlot_tarStat == 2'h2;</a>
+<a name="840"><span class="lineNum">     840 </span>            :   wire        _target_T_587 = _ways_21_io_resp_tailSlot_tarStat == 2'h0;</a>
+<a name="841"><span class="lineNum">     841 </span><span class="lineCov">         22 :   wire        s1_possible_full_preds_21_fallThroughErr =</span></a>
+<a name="842"><span class="lineNum">     842 </span>            :     {1'h0, s1_pc_dup_0[4:1]} &gt;= {_ways_21_io_resp_carry, _ways_21_io_resp_pftAddr};</a>
+<a name="843"><span class="lineNum">     843 </span>            :   wire        _target_T_612 = _ways_22_io_resp_tailSlot_tarStat == 2'h1;</a>
+<a name="844"><span class="lineNum">     844 </span>            :   wire        _target_T_613 = _ways_22_io_resp_tailSlot_tarStat == 2'h2;</a>
+<a name="845"><span class="lineNum">     845 </span>            :   wire        _target_T_614 = _ways_22_io_resp_tailSlot_tarStat == 2'h0;</a>
+<a name="846"><span class="lineNum">     846 </span><span class="lineCov">         22 :   wire        s1_possible_full_preds_22_fallThroughErr =</span></a>
+<a name="847"><span class="lineNum">     847 </span>            :     {1'h0, s1_pc_dup_0[4:1]} &gt;= {_ways_22_io_resp_carry, _ways_22_io_resp_pftAddr};</a>
+<a name="848"><span class="lineNum">     848 </span>            :   wire        _target_T_639 = _ways_23_io_resp_tailSlot_tarStat == 2'h1;</a>
+<a name="849"><span class="lineNum">     849 </span>            :   wire        _target_T_640 = _ways_23_io_resp_tailSlot_tarStat == 2'h2;</a>
+<a name="850"><span class="lineNum">     850 </span>            :   wire        _target_T_641 = _ways_23_io_resp_tailSlot_tarStat == 2'h0;</a>
+<a name="851"><span class="lineNum">     851 </span><span class="lineCov">         29 :   wire        s1_possible_full_preds_23_fallThroughErr =</span></a>
+<a name="852"><span class="lineNum">     852 </span>            :     {1'h0, s1_pc_dup_0[4:1]} &gt;= {_ways_23_io_resp_carry, _ways_23_io_resp_pftAddr};</a>
+<a name="853"><span class="lineNum">     853 </span>            :   wire        _target_T_666 = _ways_24_io_resp_tailSlot_tarStat == 2'h1;</a>
+<a name="854"><span class="lineNum">     854 </span>            :   wire        _target_T_667 = _ways_24_io_resp_tailSlot_tarStat == 2'h2;</a>
+<a name="855"><span class="lineNum">     855 </span>            :   wire        _target_T_668 = _ways_24_io_resp_tailSlot_tarStat == 2'h0;</a>
+<a name="856"><span class="lineNum">     856 </span><span class="lineCov">         25 :   wire        s1_possible_full_preds_24_fallThroughErr =</span></a>
+<a name="857"><span class="lineNum">     857 </span>            :     {1'h0, s1_pc_dup_0[4:1]} &gt;= {_ways_24_io_resp_carry, _ways_24_io_resp_pftAddr};</a>
+<a name="858"><span class="lineNum">     858 </span>            :   wire        _target_T_693 = _ways_25_io_resp_tailSlot_tarStat == 2'h1;</a>
+<a name="859"><span class="lineNum">     859 </span>            :   wire        _target_T_694 = _ways_25_io_resp_tailSlot_tarStat == 2'h2;</a>
+<a name="860"><span class="lineNum">     860 </span>            :   wire        _target_T_695 = _ways_25_io_resp_tailSlot_tarStat == 2'h0;</a>
+<a name="861"><span class="lineNum">     861 </span><span class="lineCov">         27 :   wire        s1_possible_full_preds_25_fallThroughErr =</span></a>
+<a name="862"><span class="lineNum">     862 </span>            :     {1'h0, s1_pc_dup_0[4:1]} &gt;= {_ways_25_io_resp_carry, _ways_25_io_resp_pftAddr};</a>
+<a name="863"><span class="lineNum">     863 </span>            :   wire        _target_T_720 = _ways_26_io_resp_tailSlot_tarStat == 2'h1;</a>
+<a name="864"><span class="lineNum">     864 </span>            :   wire        _target_T_721 = _ways_26_io_resp_tailSlot_tarStat == 2'h2;</a>
+<a name="865"><span class="lineNum">     865 </span>            :   wire        _target_T_722 = _ways_26_io_resp_tailSlot_tarStat == 2'h0;</a>
+<a name="866"><span class="lineNum">     866 </span><span class="lineCov">         26 :   wire        s1_possible_full_preds_26_fallThroughErr =</span></a>
+<a name="867"><span class="lineNum">     867 </span>            :     {1'h0, s1_pc_dup_0[4:1]} &gt;= {_ways_26_io_resp_carry, _ways_26_io_resp_pftAddr};</a>
+<a name="868"><span class="lineNum">     868 </span>            :   wire        _target_T_747 = _ways_27_io_resp_tailSlot_tarStat == 2'h1;</a>
+<a name="869"><span class="lineNum">     869 </span>            :   wire        _target_T_748 = _ways_27_io_resp_tailSlot_tarStat == 2'h2;</a>
+<a name="870"><span class="lineNum">     870 </span>            :   wire        _target_T_749 = _ways_27_io_resp_tailSlot_tarStat == 2'h0;</a>
+<a name="871"><span class="lineNum">     871 </span><span class="lineCov">         28 :   wire        s1_possible_full_preds_27_fallThroughErr =</span></a>
+<a name="872"><span class="lineNum">     872 </span>            :     {1'h0, s1_pc_dup_0[4:1]} &gt;= {_ways_27_io_resp_carry, _ways_27_io_resp_pftAddr};</a>
+<a name="873"><span class="lineNum">     873 </span>            :   wire        _target_T_774 = _ways_28_io_resp_tailSlot_tarStat == 2'h1;</a>
+<a name="874"><span class="lineNum">     874 </span>            :   wire        _target_T_775 = _ways_28_io_resp_tailSlot_tarStat == 2'h2;</a>
+<a name="875"><span class="lineNum">     875 </span>            :   wire        _target_T_776 = _ways_28_io_resp_tailSlot_tarStat == 2'h0;</a>
+<a name="876"><span class="lineNum">     876 </span><span class="lineCov">         21 :   wire        s1_possible_full_preds_28_fallThroughErr =</span></a>
+<a name="877"><span class="lineNum">     877 </span>            :     {1'h0, s1_pc_dup_0[4:1]} &gt;= {_ways_28_io_resp_carry, _ways_28_io_resp_pftAddr};</a>
+<a name="878"><span class="lineNum">     878 </span>            :   wire        _target_T_801 = _ways_29_io_resp_tailSlot_tarStat == 2'h1;</a>
+<a name="879"><span class="lineNum">     879 </span>            :   wire        _target_T_802 = _ways_29_io_resp_tailSlot_tarStat == 2'h2;</a>
+<a name="880"><span class="lineNum">     880 </span>            :   wire        _target_T_803 = _ways_29_io_resp_tailSlot_tarStat == 2'h0;</a>
+<a name="881"><span class="lineNum">     881 </span><span class="lineCov">         17 :   wire        s1_possible_full_preds_29_fallThroughErr =</span></a>
+<a name="882"><span class="lineNum">     882 </span>            :     {1'h0, s1_pc_dup_0[4:1]} &gt;= {_ways_29_io_resp_carry, _ways_29_io_resp_pftAddr};</a>
+<a name="883"><span class="lineNum">     883 </span>            :   wire        _target_T_828 = _ways_30_io_resp_tailSlot_tarStat == 2'h1;</a>
+<a name="884"><span class="lineNum">     884 </span>            :   wire        _target_T_829 = _ways_30_io_resp_tailSlot_tarStat == 2'h2;</a>
+<a name="885"><span class="lineNum">     885 </span>            :   wire        _target_T_830 = _ways_30_io_resp_tailSlot_tarStat == 2'h0;</a>
+<a name="886"><span class="lineNum">     886 </span><span class="lineCov">         26 :   wire        s1_possible_full_preds_30_fallThroughErr =</span></a>
+<a name="887"><span class="lineNum">     887 </span>            :     {1'h0, s1_pc_dup_0[4:1]} &gt;= {_ways_30_io_resp_carry, _ways_30_io_resp_pftAddr};</a>
+<a name="888"><span class="lineNum">     888 </span>            :   wire        _target_T_855 = _ways_31_io_resp_tailSlot_tarStat == 2'h1;</a>
+<a name="889"><span class="lineNum">     889 </span>            :   wire        _target_T_856 = _ways_31_io_resp_tailSlot_tarStat == 2'h2;</a>
+<a name="890"><span class="lineNum">     890 </span>            :   wire        _target_T_857 = _ways_31_io_resp_tailSlot_tarStat == 2'h0;</a>
+<a name="891"><span class="lineNum">     891 </span><span class="lineCov">         31 :   wire        s1_possible_full_preds_31_fallThroughErr =</span></a>
+<a name="892"><span class="lineNum">     892 </span>            :     {1'h0, s1_pc_dup_0[4:1]} &gt;= {_ways_31_io_resp_carry, _ways_31_io_resp_pftAddr};</a>
+<a name="893"><span class="lineNum">     893 </span>            :   wire        _s1_hit_full_pred_T_157 =</a>
+<a name="894"><span class="lineNum">     894 </span>            :     _ways_0_io_resp_hit &amp; _ways_0_io_resp_tailSlot_valid</a>
+<a name="895"><span class="lineNum">     895 </span>            :     &amp; _ways_0_io_resp_tailSlot_sharing | _ways_1_io_resp_hit</a>
+<a name="896"><span class="lineNum">     896 </span>            :     &amp; _ways_1_io_resp_tailSlot_valid &amp; _ways_1_io_resp_tailSlot_sharing</a>
+<a name="897"><span class="lineNum">     897 </span>            :     | _ways_2_io_resp_hit &amp; _ways_2_io_resp_tailSlot_valid</a>
+<a name="898"><span class="lineNum">     898 </span>            :     &amp; _ways_2_io_resp_tailSlot_sharing | _ways_3_io_resp_hit</a>
+<a name="899"><span class="lineNum">     899 </span>            :     &amp; _ways_3_io_resp_tailSlot_valid &amp; _ways_3_io_resp_tailSlot_sharing</a>
+<a name="900"><span class="lineNum">     900 </span>            :     | _ways_4_io_resp_hit &amp; _ways_4_io_resp_tailSlot_valid</a>
+<a name="901"><span class="lineNum">     901 </span>            :     &amp; _ways_4_io_resp_tailSlot_sharing | _ways_5_io_resp_hit</a>
+<a name="902"><span class="lineNum">     902 </span>            :     &amp; _ways_5_io_resp_tailSlot_valid &amp; _ways_5_io_resp_tailSlot_sharing</a>
+<a name="903"><span class="lineNum">     903 </span>            :     | _ways_6_io_resp_hit &amp; _ways_6_io_resp_tailSlot_valid</a>
+<a name="904"><span class="lineNum">     904 </span>            :     &amp; _ways_6_io_resp_tailSlot_sharing | _ways_7_io_resp_hit</a>
+<a name="905"><span class="lineNum">     905 </span>            :     &amp; _ways_7_io_resp_tailSlot_valid &amp; _ways_7_io_resp_tailSlot_sharing</a>
+<a name="906"><span class="lineNum">     906 </span>            :     | _ways_8_io_resp_hit &amp; _ways_8_io_resp_tailSlot_valid</a>
+<a name="907"><span class="lineNum">     907 </span>            :     &amp; _ways_8_io_resp_tailSlot_sharing | _ways_9_io_resp_hit</a>
+<a name="908"><span class="lineNum">     908 </span>            :     &amp; _ways_9_io_resp_tailSlot_valid &amp; _ways_9_io_resp_tailSlot_sharing</a>
+<a name="909"><span class="lineNum">     909 </span>            :     | _ways_10_io_resp_hit &amp; _ways_10_io_resp_tailSlot_valid</a>
+<a name="910"><span class="lineNum">     910 </span>            :     &amp; _ways_10_io_resp_tailSlot_sharing | _ways_11_io_resp_hit</a>
+<a name="911"><span class="lineNum">     911 </span>            :     &amp; _ways_11_io_resp_tailSlot_valid &amp; _ways_11_io_resp_tailSlot_sharing</a>
+<a name="912"><span class="lineNum">     912 </span>            :     | _ways_12_io_resp_hit &amp; _ways_12_io_resp_tailSlot_valid</a>
+<a name="913"><span class="lineNum">     913 </span>            :     &amp; _ways_12_io_resp_tailSlot_sharing | _ways_13_io_resp_hit</a>
+<a name="914"><span class="lineNum">     914 </span>            :     &amp; _ways_13_io_resp_tailSlot_valid &amp; _ways_13_io_resp_tailSlot_sharing</a>
+<a name="915"><span class="lineNum">     915 </span>            :     | _ways_14_io_resp_hit &amp; _ways_14_io_resp_tailSlot_valid</a>
+<a name="916"><span class="lineNum">     916 </span>            :     &amp; _ways_14_io_resp_tailSlot_sharing | _ways_15_io_resp_hit</a>
+<a name="917"><span class="lineNum">     917 </span>            :     &amp; _ways_15_io_resp_tailSlot_valid &amp; _ways_15_io_resp_tailSlot_sharing</a>
+<a name="918"><span class="lineNum">     918 </span>            :     | _ways_16_io_resp_hit &amp; _ways_16_io_resp_tailSlot_valid</a>
+<a name="919"><span class="lineNum">     919 </span>            :     &amp; _ways_16_io_resp_tailSlot_sharing | _ways_17_io_resp_hit</a>
+<a name="920"><span class="lineNum">     920 </span>            :     &amp; _ways_17_io_resp_tailSlot_valid &amp; _ways_17_io_resp_tailSlot_sharing</a>
+<a name="921"><span class="lineNum">     921 </span>            :     | _ways_18_io_resp_hit &amp; _ways_18_io_resp_tailSlot_valid</a>
+<a name="922"><span class="lineNum">     922 </span>            :     &amp; _ways_18_io_resp_tailSlot_sharing | _ways_19_io_resp_hit</a>
+<a name="923"><span class="lineNum">     923 </span>            :     &amp; _ways_19_io_resp_tailSlot_valid &amp; _ways_19_io_resp_tailSlot_sharing</a>
+<a name="924"><span class="lineNum">     924 </span>            :     | _ways_20_io_resp_hit &amp; _ways_20_io_resp_tailSlot_valid</a>
+<a name="925"><span class="lineNum">     925 </span>            :     &amp; _ways_20_io_resp_tailSlot_sharing | _ways_21_io_resp_hit</a>
+<a name="926"><span class="lineNum">     926 </span>            :     &amp; _ways_21_io_resp_tailSlot_valid &amp; _ways_21_io_resp_tailSlot_sharing</a>
+<a name="927"><span class="lineNum">     927 </span>            :     | _ways_22_io_resp_hit &amp; _ways_22_io_resp_tailSlot_valid</a>
+<a name="928"><span class="lineNum">     928 </span>            :     &amp; _ways_22_io_resp_tailSlot_sharing | _ways_23_io_resp_hit</a>
+<a name="929"><span class="lineNum">     929 </span>            :     &amp; _ways_23_io_resp_tailSlot_valid &amp; _ways_23_io_resp_tailSlot_sharing</a>
+<a name="930"><span class="lineNum">     930 </span>            :     | _ways_24_io_resp_hit &amp; _ways_24_io_resp_tailSlot_valid</a>
+<a name="931"><span class="lineNum">     931 </span>            :     &amp; _ways_24_io_resp_tailSlot_sharing | _ways_25_io_resp_hit</a>
+<a name="932"><span class="lineNum">     932 </span>            :     &amp; _ways_25_io_resp_tailSlot_valid &amp; _ways_25_io_resp_tailSlot_sharing</a>
+<a name="933"><span class="lineNum">     933 </span>            :     | _ways_26_io_resp_hit &amp; _ways_26_io_resp_tailSlot_valid</a>
+<a name="934"><span class="lineNum">     934 </span>            :     &amp; _ways_26_io_resp_tailSlot_sharing | _ways_27_io_resp_hit</a>
+<a name="935"><span class="lineNum">     935 </span>            :     &amp; _ways_27_io_resp_tailSlot_valid &amp; _ways_27_io_resp_tailSlot_sharing</a>
+<a name="936"><span class="lineNum">     936 </span>            :     | _ways_28_io_resp_hit &amp; _ways_28_io_resp_tailSlot_valid</a>
+<a name="937"><span class="lineNum">     937 </span>            :     &amp; _ways_28_io_resp_tailSlot_sharing | _ways_29_io_resp_hit</a>
+<a name="938"><span class="lineNum">     938 </span>            :     &amp; _ways_29_io_resp_tailSlot_valid &amp; _ways_29_io_resp_tailSlot_sharing</a>
+<a name="939"><span class="lineNum">     939 </span>            :     | _ways_30_io_resp_hit &amp; _ways_30_io_resp_tailSlot_valid</a>
+<a name="940"><span class="lineNum">     940 </span>            :     &amp; _ways_30_io_resp_tailSlot_sharing | _ways_31_io_resp_hit</a>
+<a name="941"><span class="lineNum">     941 </span>            :     &amp; _ways_31_io_resp_tailSlot_valid &amp; _ways_31_io_resp_tailSlot_sharing;</a>
+<a name="942"><span class="lineNum">     942 </span>            :   wire [40:0] _s1_hit_full_pred_T_598 =</a>
+<a name="943"><span class="lineNum">     943 </span>            :     (_ways_0_io_resp_hit</a>
+<a name="944"><span class="lineNum">     944 </span>            :        ? (s1_possible_full_preds_0_fallThroughErr</a>
+<a name="945"><span class="lineNum">     945 </span>            :             ? _s1_possible_full_preds_31_fallThroughAddr_T</a>
+<a name="946"><span class="lineNum">     946 </span>            :             : {_ways_0_io_resp_carry ? 36'(s1_pc_dup_0[40:5] + 36'h1) : s1_pc_dup_0[40:5],</a>
+<a name="947"><span class="lineNum">     947 </span>            :                _ways_0_io_resp_pftAddr,</a>
+<a name="948"><span class="lineNum">     948 </span>            :                1'h0})</a>
+<a name="949"><span class="lineNum">     949 </span>            :        : 41'h0)</a>
+<a name="950"><span class="lineNum">     950 </span>            :     | (_ways_1_io_resp_hit</a>
+<a name="951"><span class="lineNum">     951 </span>            :          ? (s1_possible_full_preds_1_fallThroughErr</a>
+<a name="952"><span class="lineNum">     952 </span>            :               ? _s1_possible_full_preds_31_fallThroughAddr_T</a>
+<a name="953"><span class="lineNum">     953 </span>            :               : {_ways_1_io_resp_carry</a>
+<a name="954"><span class="lineNum">     954 </span>            :                    ? 36'(s1_pc_dup_0[40:5] + 36'h1)</a>
+<a name="955"><span class="lineNum">     955 </span>            :                    : s1_pc_dup_0[40:5],</a>
+<a name="956"><span class="lineNum">     956 </span>            :                  _ways_1_io_resp_pftAddr,</a>
+<a name="957"><span class="lineNum">     957 </span>            :                  1'h0})</a>
+<a name="958"><span class="lineNum">     958 </span>            :          : 41'h0)</a>
+<a name="959"><span class="lineNum">     959 </span>            :     | (_ways_2_io_resp_hit</a>
+<a name="960"><span class="lineNum">     960 </span>            :          ? (s1_possible_full_preds_2_fallThroughErr</a>
+<a name="961"><span class="lineNum">     961 </span>            :               ? _s1_possible_full_preds_31_fallThroughAddr_T</a>
+<a name="962"><span class="lineNum">     962 </span>            :               : {_ways_2_io_resp_carry</a>
+<a name="963"><span class="lineNum">     963 </span>            :                    ? 36'(s1_pc_dup_0[40:5] + 36'h1)</a>
+<a name="964"><span class="lineNum">     964 </span>            :                    : s1_pc_dup_0[40:5],</a>
+<a name="965"><span class="lineNum">     965 </span>            :                  _ways_2_io_resp_pftAddr,</a>
+<a name="966"><span class="lineNum">     966 </span>            :                  1'h0})</a>
+<a name="967"><span class="lineNum">     967 </span>            :          : 41'h0)</a>
+<a name="968"><span class="lineNum">     968 </span>            :     | (_ways_3_io_resp_hit</a>
+<a name="969"><span class="lineNum">     969 </span>            :          ? (s1_possible_full_preds_3_fallThroughErr</a>
+<a name="970"><span class="lineNum">     970 </span>            :               ? _s1_possible_full_preds_31_fallThroughAddr_T</a>
+<a name="971"><span class="lineNum">     971 </span>            :               : {_ways_3_io_resp_carry</a>
+<a name="972"><span class="lineNum">     972 </span>            :                    ? 36'(s1_pc_dup_0[40:5] + 36'h1)</a>
+<a name="973"><span class="lineNum">     973 </span>            :                    : s1_pc_dup_0[40:5],</a>
+<a name="974"><span class="lineNum">     974 </span>            :                  _ways_3_io_resp_pftAddr,</a>
+<a name="975"><span class="lineNum">     975 </span>            :                  1'h0})</a>
+<a name="976"><span class="lineNum">     976 </span>            :          : 41'h0)</a>
+<a name="977"><span class="lineNum">     977 </span>            :     | (_ways_4_io_resp_hit</a>
+<a name="978"><span class="lineNum">     978 </span>            :          ? (s1_possible_full_preds_4_fallThroughErr</a>
+<a name="979"><span class="lineNum">     979 </span>            :               ? _s1_possible_full_preds_31_fallThroughAddr_T</a>
+<a name="980"><span class="lineNum">     980 </span>            :               : {_ways_4_io_resp_carry</a>
+<a name="981"><span class="lineNum">     981 </span>            :                    ? 36'(s1_pc_dup_0[40:5] + 36'h1)</a>
+<a name="982"><span class="lineNum">     982 </span>            :                    : s1_pc_dup_0[40:5],</a>
+<a name="983"><span class="lineNum">     983 </span>            :                  _ways_4_io_resp_pftAddr,</a>
+<a name="984"><span class="lineNum">     984 </span>            :                  1'h0})</a>
+<a name="985"><span class="lineNum">     985 </span>            :          : 41'h0)</a>
+<a name="986"><span class="lineNum">     986 </span>            :     | (_ways_5_io_resp_hit</a>
+<a name="987"><span class="lineNum">     987 </span>            :          ? (s1_possible_full_preds_5_fallThroughErr</a>
+<a name="988"><span class="lineNum">     988 </span>            :               ? _s1_possible_full_preds_31_fallThroughAddr_T</a>
+<a name="989"><span class="lineNum">     989 </span>            :               : {_ways_5_io_resp_carry</a>
+<a name="990"><span class="lineNum">     990 </span>            :                    ? 36'(s1_pc_dup_0[40:5] + 36'h1)</a>
+<a name="991"><span class="lineNum">     991 </span>            :                    : s1_pc_dup_0[40:5],</a>
+<a name="992"><span class="lineNum">     992 </span>            :                  _ways_5_io_resp_pftAddr,</a>
+<a name="993"><span class="lineNum">     993 </span>            :                  1'h0})</a>
+<a name="994"><span class="lineNum">     994 </span>            :          : 41'h0)</a>
+<a name="995"><span class="lineNum">     995 </span>            :     | (_ways_6_io_resp_hit</a>
+<a name="996"><span class="lineNum">     996 </span>            :          ? (s1_possible_full_preds_6_fallThroughErr</a>
+<a name="997"><span class="lineNum">     997 </span>            :               ? _s1_possible_full_preds_31_fallThroughAddr_T</a>
+<a name="998"><span class="lineNum">     998 </span>            :               : {_ways_6_io_resp_carry</a>
+<a name="999"><span class="lineNum">     999 </span>            :                    ? 36'(s1_pc_dup_0[40:5] + 36'h1)</a>
+<a name="1000"><span class="lineNum">    1000 </span>            :                    : s1_pc_dup_0[40:5],</a>
+<a name="1001"><span class="lineNum">    1001 </span>            :                  _ways_6_io_resp_pftAddr,</a>
+<a name="1002"><span class="lineNum">    1002 </span>            :                  1'h0})</a>
+<a name="1003"><span class="lineNum">    1003 </span>            :          : 41'h0)</a>
+<a name="1004"><span class="lineNum">    1004 </span>            :     | (_ways_7_io_resp_hit</a>
+<a name="1005"><span class="lineNum">    1005 </span>            :          ? (s1_possible_full_preds_7_fallThroughErr</a>
+<a name="1006"><span class="lineNum">    1006 </span>            :               ? _s1_possible_full_preds_31_fallThroughAddr_T</a>
+<a name="1007"><span class="lineNum">    1007 </span>            :               : {_ways_7_io_resp_carry</a>
+<a name="1008"><span class="lineNum">    1008 </span>            :                    ? 36'(s1_pc_dup_0[40:5] + 36'h1)</a>
+<a name="1009"><span class="lineNum">    1009 </span>            :                    : s1_pc_dup_0[40:5],</a>
+<a name="1010"><span class="lineNum">    1010 </span>            :                  _ways_7_io_resp_pftAddr,</a>
+<a name="1011"><span class="lineNum">    1011 </span>            :                  1'h0})</a>
+<a name="1012"><span class="lineNum">    1012 </span>            :          : 41'h0)</a>
+<a name="1013"><span class="lineNum">    1013 </span>            :     | (_ways_8_io_resp_hit</a>
+<a name="1014"><span class="lineNum">    1014 </span>            :          ? (s1_possible_full_preds_8_fallThroughErr</a>
+<a name="1015"><span class="lineNum">    1015 </span>            :               ? _s1_possible_full_preds_31_fallThroughAddr_T</a>
+<a name="1016"><span class="lineNum">    1016 </span>            :               : {_ways_8_io_resp_carry</a>
+<a name="1017"><span class="lineNum">    1017 </span>            :                    ? 36'(s1_pc_dup_0[40:5] + 36'h1)</a>
+<a name="1018"><span class="lineNum">    1018 </span>            :                    : s1_pc_dup_0[40:5],</a>
+<a name="1019"><span class="lineNum">    1019 </span>            :                  _ways_8_io_resp_pftAddr,</a>
+<a name="1020"><span class="lineNum">    1020 </span>            :                  1'h0})</a>
+<a name="1021"><span class="lineNum">    1021 </span>            :          : 41'h0)</a>
+<a name="1022"><span class="lineNum">    1022 </span>            :     | (_ways_9_io_resp_hit</a>
+<a name="1023"><span class="lineNum">    1023 </span>            :          ? (s1_possible_full_preds_9_fallThroughErr</a>
+<a name="1024"><span class="lineNum">    1024 </span>            :               ? _s1_possible_full_preds_31_fallThroughAddr_T</a>
+<a name="1025"><span class="lineNum">    1025 </span>            :               : {_ways_9_io_resp_carry</a>
+<a name="1026"><span class="lineNum">    1026 </span>            :                    ? 36'(s1_pc_dup_0[40:5] + 36'h1)</a>
+<a name="1027"><span class="lineNum">    1027 </span>            :                    : s1_pc_dup_0[40:5],</a>
+<a name="1028"><span class="lineNum">    1028 </span>            :                  _ways_9_io_resp_pftAddr,</a>
+<a name="1029"><span class="lineNum">    1029 </span>            :                  1'h0})</a>
+<a name="1030"><span class="lineNum">    1030 </span>            :          : 41'h0)</a>
+<a name="1031"><span class="lineNum">    1031 </span>            :     | (_ways_10_io_resp_hit</a>
+<a name="1032"><span class="lineNum">    1032 </span>            :          ? (s1_possible_full_preds_10_fallThroughErr</a>
+<a name="1033"><span class="lineNum">    1033 </span>            :               ? _s1_possible_full_preds_31_fallThroughAddr_T</a>
+<a name="1034"><span class="lineNum">    1034 </span>            :               : {_ways_10_io_resp_carry</a>
+<a name="1035"><span class="lineNum">    1035 </span>            :                    ? 36'(s1_pc_dup_0[40:5] + 36'h1)</a>
+<a name="1036"><span class="lineNum">    1036 </span>            :                    : s1_pc_dup_0[40:5],</a>
+<a name="1037"><span class="lineNum">    1037 </span>            :                  _ways_10_io_resp_pftAddr,</a>
+<a name="1038"><span class="lineNum">    1038 </span>            :                  1'h0})</a>
+<a name="1039"><span class="lineNum">    1039 </span>            :          : 41'h0)</a>
+<a name="1040"><span class="lineNum">    1040 </span>            :     | (_ways_11_io_resp_hit</a>
+<a name="1041"><span class="lineNum">    1041 </span>            :          ? (s1_possible_full_preds_11_fallThroughErr</a>
+<a name="1042"><span class="lineNum">    1042 </span>            :               ? _s1_possible_full_preds_31_fallThroughAddr_T</a>
+<a name="1043"><span class="lineNum">    1043 </span>            :               : {_ways_11_io_resp_carry</a>
+<a name="1044"><span class="lineNum">    1044 </span>            :                    ? 36'(s1_pc_dup_0[40:5] + 36'h1)</a>
+<a name="1045"><span class="lineNum">    1045 </span>            :                    : s1_pc_dup_0[40:5],</a>
+<a name="1046"><span class="lineNum">    1046 </span>            :                  _ways_11_io_resp_pftAddr,</a>
+<a name="1047"><span class="lineNum">    1047 </span>            :                  1'h0})</a>
+<a name="1048"><span class="lineNum">    1048 </span>            :          : 41'h0)</a>
+<a name="1049"><span class="lineNum">    1049 </span>            :     | (_ways_12_io_resp_hit</a>
+<a name="1050"><span class="lineNum">    1050 </span>            :          ? (s1_possible_full_preds_12_fallThroughErr</a>
+<a name="1051"><span class="lineNum">    1051 </span>            :               ? _s1_possible_full_preds_31_fallThroughAddr_T</a>
+<a name="1052"><span class="lineNum">    1052 </span>            :               : {_ways_12_io_resp_carry</a>
+<a name="1053"><span class="lineNum">    1053 </span>            :                    ? 36'(s1_pc_dup_0[40:5] + 36'h1)</a>
+<a name="1054"><span class="lineNum">    1054 </span>            :                    : s1_pc_dup_0[40:5],</a>
+<a name="1055"><span class="lineNum">    1055 </span>            :                  _ways_12_io_resp_pftAddr,</a>
+<a name="1056"><span class="lineNum">    1056 </span>            :                  1'h0})</a>
+<a name="1057"><span class="lineNum">    1057 </span>            :          : 41'h0)</a>
+<a name="1058"><span class="lineNum">    1058 </span>            :     | (_ways_13_io_resp_hit</a>
+<a name="1059"><span class="lineNum">    1059 </span>            :          ? (s1_possible_full_preds_13_fallThroughErr</a>
+<a name="1060"><span class="lineNum">    1060 </span>            :               ? _s1_possible_full_preds_31_fallThroughAddr_T</a>
+<a name="1061"><span class="lineNum">    1061 </span>            :               : {_ways_13_io_resp_carry</a>
+<a name="1062"><span class="lineNum">    1062 </span>            :                    ? 36'(s1_pc_dup_0[40:5] + 36'h1)</a>
+<a name="1063"><span class="lineNum">    1063 </span>            :                    : s1_pc_dup_0[40:5],</a>
+<a name="1064"><span class="lineNum">    1064 </span>            :                  _ways_13_io_resp_pftAddr,</a>
+<a name="1065"><span class="lineNum">    1065 </span>            :                  1'h0})</a>
+<a name="1066"><span class="lineNum">    1066 </span>            :          : 41'h0)</a>
+<a name="1067"><span class="lineNum">    1067 </span>            :     | (_ways_14_io_resp_hit</a>
+<a name="1068"><span class="lineNum">    1068 </span>            :          ? (s1_possible_full_preds_14_fallThroughErr</a>
+<a name="1069"><span class="lineNum">    1069 </span>            :               ? _s1_possible_full_preds_31_fallThroughAddr_T</a>
+<a name="1070"><span class="lineNum">    1070 </span>            :               : {_ways_14_io_resp_carry</a>
+<a name="1071"><span class="lineNum">    1071 </span>            :                    ? 36'(s1_pc_dup_0[40:5] + 36'h1)</a>
+<a name="1072"><span class="lineNum">    1072 </span>            :                    : s1_pc_dup_0[40:5],</a>
+<a name="1073"><span class="lineNum">    1073 </span>            :                  _ways_14_io_resp_pftAddr,</a>
+<a name="1074"><span class="lineNum">    1074 </span>            :                  1'h0})</a>
+<a name="1075"><span class="lineNum">    1075 </span>            :          : 41'h0)</a>
+<a name="1076"><span class="lineNum">    1076 </span>            :     | (_ways_15_io_resp_hit</a>
+<a name="1077"><span class="lineNum">    1077 </span>            :          ? (s1_possible_full_preds_15_fallThroughErr</a>
+<a name="1078"><span class="lineNum">    1078 </span>            :               ? _s1_possible_full_preds_31_fallThroughAddr_T</a>
+<a name="1079"><span class="lineNum">    1079 </span>            :               : {_ways_15_io_resp_carry</a>
+<a name="1080"><span class="lineNum">    1080 </span>            :                    ? 36'(s1_pc_dup_0[40:5] + 36'h1)</a>
+<a name="1081"><span class="lineNum">    1081 </span>            :                    : s1_pc_dup_0[40:5],</a>
+<a name="1082"><span class="lineNum">    1082 </span>            :                  _ways_15_io_resp_pftAddr,</a>
+<a name="1083"><span class="lineNum">    1083 </span>            :                  1'h0})</a>
+<a name="1084"><span class="lineNum">    1084 </span>            :          : 41'h0)</a>
+<a name="1085"><span class="lineNum">    1085 </span>            :     | (_ways_16_io_resp_hit</a>
+<a name="1086"><span class="lineNum">    1086 </span>            :          ? (s1_possible_full_preds_16_fallThroughErr</a>
+<a name="1087"><span class="lineNum">    1087 </span>            :               ? _s1_possible_full_preds_31_fallThroughAddr_T</a>
+<a name="1088"><span class="lineNum">    1088 </span>            :               : {_ways_16_io_resp_carry</a>
+<a name="1089"><span class="lineNum">    1089 </span>            :                    ? 36'(s1_pc_dup_0[40:5] + 36'h1)</a>
+<a name="1090"><span class="lineNum">    1090 </span>            :                    : s1_pc_dup_0[40:5],</a>
+<a name="1091"><span class="lineNum">    1091 </span>            :                  _ways_16_io_resp_pftAddr,</a>
+<a name="1092"><span class="lineNum">    1092 </span>            :                  1'h0})</a>
+<a name="1093"><span class="lineNum">    1093 </span>            :          : 41'h0)</a>
+<a name="1094"><span class="lineNum">    1094 </span>            :     | (_ways_17_io_resp_hit</a>
+<a name="1095"><span class="lineNum">    1095 </span>            :          ? (s1_possible_full_preds_17_fallThroughErr</a>
+<a name="1096"><span class="lineNum">    1096 </span>            :               ? _s1_possible_full_preds_31_fallThroughAddr_T</a>
+<a name="1097"><span class="lineNum">    1097 </span>            :               : {_ways_17_io_resp_carry</a>
+<a name="1098"><span class="lineNum">    1098 </span>            :                    ? 36'(s1_pc_dup_0[40:5] + 36'h1)</a>
+<a name="1099"><span class="lineNum">    1099 </span>            :                    : s1_pc_dup_0[40:5],</a>
+<a name="1100"><span class="lineNum">    1100 </span>            :                  _ways_17_io_resp_pftAddr,</a>
+<a name="1101"><span class="lineNum">    1101 </span>            :                  1'h0})</a>
+<a name="1102"><span class="lineNum">    1102 </span>            :          : 41'h0)</a>
+<a name="1103"><span class="lineNum">    1103 </span>            :     | (_ways_18_io_resp_hit</a>
+<a name="1104"><span class="lineNum">    1104 </span>            :          ? (s1_possible_full_preds_18_fallThroughErr</a>
+<a name="1105"><span class="lineNum">    1105 </span>            :               ? _s1_possible_full_preds_31_fallThroughAddr_T</a>
+<a name="1106"><span class="lineNum">    1106 </span>            :               : {_ways_18_io_resp_carry</a>
+<a name="1107"><span class="lineNum">    1107 </span>            :                    ? 36'(s1_pc_dup_0[40:5] + 36'h1)</a>
+<a name="1108"><span class="lineNum">    1108 </span>            :                    : s1_pc_dup_0[40:5],</a>
+<a name="1109"><span class="lineNum">    1109 </span>            :                  _ways_18_io_resp_pftAddr,</a>
+<a name="1110"><span class="lineNum">    1110 </span>            :                  1'h0})</a>
+<a name="1111"><span class="lineNum">    1111 </span>            :          : 41'h0)</a>
+<a name="1112"><span class="lineNum">    1112 </span>            :     | (_ways_19_io_resp_hit</a>
+<a name="1113"><span class="lineNum">    1113 </span>            :          ? (s1_possible_full_preds_19_fallThroughErr</a>
+<a name="1114"><span class="lineNum">    1114 </span>            :               ? _s1_possible_full_preds_31_fallThroughAddr_T</a>
+<a name="1115"><span class="lineNum">    1115 </span>            :               : {_ways_19_io_resp_carry</a>
+<a name="1116"><span class="lineNum">    1116 </span>            :                    ? 36'(s1_pc_dup_0[40:5] + 36'h1)</a>
+<a name="1117"><span class="lineNum">    1117 </span>            :                    : s1_pc_dup_0[40:5],</a>
+<a name="1118"><span class="lineNum">    1118 </span>            :                  _ways_19_io_resp_pftAddr,</a>
+<a name="1119"><span class="lineNum">    1119 </span>            :                  1'h0})</a>
+<a name="1120"><span class="lineNum">    1120 </span>            :          : 41'h0)</a>
+<a name="1121"><span class="lineNum">    1121 </span>            :     | (_ways_20_io_resp_hit</a>
+<a name="1122"><span class="lineNum">    1122 </span>            :          ? (s1_possible_full_preds_20_fallThroughErr</a>
+<a name="1123"><span class="lineNum">    1123 </span>            :               ? _s1_possible_full_preds_31_fallThroughAddr_T</a>
+<a name="1124"><span class="lineNum">    1124 </span>            :               : {_ways_20_io_resp_carry</a>
+<a name="1125"><span class="lineNum">    1125 </span>            :                    ? 36'(s1_pc_dup_0[40:5] + 36'h1)</a>
+<a name="1126"><span class="lineNum">    1126 </span>            :                    : s1_pc_dup_0[40:5],</a>
+<a name="1127"><span class="lineNum">    1127 </span>            :                  _ways_20_io_resp_pftAddr,</a>
+<a name="1128"><span class="lineNum">    1128 </span>            :                  1'h0})</a>
+<a name="1129"><span class="lineNum">    1129 </span>            :          : 41'h0)</a>
+<a name="1130"><span class="lineNum">    1130 </span>            :     | (_ways_21_io_resp_hit</a>
+<a name="1131"><span class="lineNum">    1131 </span>            :          ? (s1_possible_full_preds_21_fallThroughErr</a>
+<a name="1132"><span class="lineNum">    1132 </span>            :               ? _s1_possible_full_preds_31_fallThroughAddr_T</a>
+<a name="1133"><span class="lineNum">    1133 </span>            :               : {_ways_21_io_resp_carry</a>
+<a name="1134"><span class="lineNum">    1134 </span>            :                    ? 36'(s1_pc_dup_0[40:5] + 36'h1)</a>
+<a name="1135"><span class="lineNum">    1135 </span>            :                    : s1_pc_dup_0[40:5],</a>
+<a name="1136"><span class="lineNum">    1136 </span>            :                  _ways_21_io_resp_pftAddr,</a>
+<a name="1137"><span class="lineNum">    1137 </span>            :                  1'h0})</a>
+<a name="1138"><span class="lineNum">    1138 </span>            :          : 41'h0)</a>
+<a name="1139"><span class="lineNum">    1139 </span>            :     | (_ways_22_io_resp_hit</a>
+<a name="1140"><span class="lineNum">    1140 </span>            :          ? (s1_possible_full_preds_22_fallThroughErr</a>
+<a name="1141"><span class="lineNum">    1141 </span>            :               ? _s1_possible_full_preds_31_fallThroughAddr_T</a>
+<a name="1142"><span class="lineNum">    1142 </span>            :               : {_ways_22_io_resp_carry</a>
+<a name="1143"><span class="lineNum">    1143 </span>            :                    ? 36'(s1_pc_dup_0[40:5] + 36'h1)</a>
+<a name="1144"><span class="lineNum">    1144 </span>            :                    : s1_pc_dup_0[40:5],</a>
+<a name="1145"><span class="lineNum">    1145 </span>            :                  _ways_22_io_resp_pftAddr,</a>
+<a name="1146"><span class="lineNum">    1146 </span>            :                  1'h0})</a>
+<a name="1147"><span class="lineNum">    1147 </span>            :          : 41'h0)</a>
+<a name="1148"><span class="lineNum">    1148 </span>            :     | (_ways_23_io_resp_hit</a>
+<a name="1149"><span class="lineNum">    1149 </span>            :          ? (s1_possible_full_preds_23_fallThroughErr</a>
+<a name="1150"><span class="lineNum">    1150 </span>            :               ? _s1_possible_full_preds_31_fallThroughAddr_T</a>
+<a name="1151"><span class="lineNum">    1151 </span>            :               : {_ways_23_io_resp_carry</a>
+<a name="1152"><span class="lineNum">    1152 </span>            :                    ? 36'(s1_pc_dup_0[40:5] + 36'h1)</a>
+<a name="1153"><span class="lineNum">    1153 </span>            :                    : s1_pc_dup_0[40:5],</a>
+<a name="1154"><span class="lineNum">    1154 </span>            :                  _ways_23_io_resp_pftAddr,</a>
+<a name="1155"><span class="lineNum">    1155 </span>            :                  1'h0})</a>
+<a name="1156"><span class="lineNum">    1156 </span>            :          : 41'h0)</a>
+<a name="1157"><span class="lineNum">    1157 </span>            :     | (_ways_24_io_resp_hit</a>
+<a name="1158"><span class="lineNum">    1158 </span>            :          ? (s1_possible_full_preds_24_fallThroughErr</a>
+<a name="1159"><span class="lineNum">    1159 </span>            :               ? _s1_possible_full_preds_31_fallThroughAddr_T</a>
+<a name="1160"><span class="lineNum">    1160 </span>            :               : {_ways_24_io_resp_carry</a>
+<a name="1161"><span class="lineNum">    1161 </span>            :                    ? 36'(s1_pc_dup_0[40:5] + 36'h1)</a>
+<a name="1162"><span class="lineNum">    1162 </span>            :                    : s1_pc_dup_0[40:5],</a>
+<a name="1163"><span class="lineNum">    1163 </span>            :                  _ways_24_io_resp_pftAddr,</a>
+<a name="1164"><span class="lineNum">    1164 </span>            :                  1'h0})</a>
+<a name="1165"><span class="lineNum">    1165 </span>            :          : 41'h0)</a>
+<a name="1166"><span class="lineNum">    1166 </span>            :     | (_ways_25_io_resp_hit</a>
+<a name="1167"><span class="lineNum">    1167 </span>            :          ? (s1_possible_full_preds_25_fallThroughErr</a>
+<a name="1168"><span class="lineNum">    1168 </span>            :               ? _s1_possible_full_preds_31_fallThroughAddr_T</a>
+<a name="1169"><span class="lineNum">    1169 </span>            :               : {_ways_25_io_resp_carry</a>
+<a name="1170"><span class="lineNum">    1170 </span>            :                    ? 36'(s1_pc_dup_0[40:5] + 36'h1)</a>
+<a name="1171"><span class="lineNum">    1171 </span>            :                    : s1_pc_dup_0[40:5],</a>
+<a name="1172"><span class="lineNum">    1172 </span>            :                  _ways_25_io_resp_pftAddr,</a>
+<a name="1173"><span class="lineNum">    1173 </span>            :                  1'h0})</a>
+<a name="1174"><span class="lineNum">    1174 </span>            :          : 41'h0)</a>
+<a name="1175"><span class="lineNum">    1175 </span>            :     | (_ways_26_io_resp_hit</a>
+<a name="1176"><span class="lineNum">    1176 </span>            :          ? (s1_possible_full_preds_26_fallThroughErr</a>
+<a name="1177"><span class="lineNum">    1177 </span>            :               ? _s1_possible_full_preds_31_fallThroughAddr_T</a>
+<a name="1178"><span class="lineNum">    1178 </span>            :               : {_ways_26_io_resp_carry</a>
+<a name="1179"><span class="lineNum">    1179 </span>            :                    ? 36'(s1_pc_dup_0[40:5] + 36'h1)</a>
+<a name="1180"><span class="lineNum">    1180 </span>            :                    : s1_pc_dup_0[40:5],</a>
+<a name="1181"><span class="lineNum">    1181 </span>            :                  _ways_26_io_resp_pftAddr,</a>
+<a name="1182"><span class="lineNum">    1182 </span>            :                  1'h0})</a>
+<a name="1183"><span class="lineNum">    1183 </span>            :          : 41'h0)</a>
+<a name="1184"><span class="lineNum">    1184 </span>            :     | (_ways_27_io_resp_hit</a>
+<a name="1185"><span class="lineNum">    1185 </span>            :          ? (s1_possible_full_preds_27_fallThroughErr</a>
+<a name="1186"><span class="lineNum">    1186 </span>            :               ? _s1_possible_full_preds_31_fallThroughAddr_T</a>
+<a name="1187"><span class="lineNum">    1187 </span>            :               : {_ways_27_io_resp_carry</a>
+<a name="1188"><span class="lineNum">    1188 </span>            :                    ? 36'(s1_pc_dup_0[40:5] + 36'h1)</a>
+<a name="1189"><span class="lineNum">    1189 </span>            :                    : s1_pc_dup_0[40:5],</a>
+<a name="1190"><span class="lineNum">    1190 </span>            :                  _ways_27_io_resp_pftAddr,</a>
+<a name="1191"><span class="lineNum">    1191 </span>            :                  1'h0})</a>
+<a name="1192"><span class="lineNum">    1192 </span>            :          : 41'h0)</a>
+<a name="1193"><span class="lineNum">    1193 </span>            :     | (_ways_28_io_resp_hit</a>
+<a name="1194"><span class="lineNum">    1194 </span>            :          ? (s1_possible_full_preds_28_fallThroughErr</a>
+<a name="1195"><span class="lineNum">    1195 </span>            :               ? _s1_possible_full_preds_31_fallThroughAddr_T</a>
+<a name="1196"><span class="lineNum">    1196 </span>            :               : {_ways_28_io_resp_carry</a>
+<a name="1197"><span class="lineNum">    1197 </span>            :                    ? 36'(s1_pc_dup_0[40:5] + 36'h1)</a>
+<a name="1198"><span class="lineNum">    1198 </span>            :                    : s1_pc_dup_0[40:5],</a>
+<a name="1199"><span class="lineNum">    1199 </span>            :                  _ways_28_io_resp_pftAddr,</a>
+<a name="1200"><span class="lineNum">    1200 </span>            :                  1'h0})</a>
+<a name="1201"><span class="lineNum">    1201 </span>            :          : 41'h0)</a>
+<a name="1202"><span class="lineNum">    1202 </span>            :     | (_ways_29_io_resp_hit</a>
+<a name="1203"><span class="lineNum">    1203 </span>            :          ? (s1_possible_full_preds_29_fallThroughErr</a>
+<a name="1204"><span class="lineNum">    1204 </span>            :               ? _s1_possible_full_preds_31_fallThroughAddr_T</a>
+<a name="1205"><span class="lineNum">    1205 </span>            :               : {_ways_29_io_resp_carry</a>
+<a name="1206"><span class="lineNum">    1206 </span>            :                    ? 36'(s1_pc_dup_0[40:5] + 36'h1)</a>
+<a name="1207"><span class="lineNum">    1207 </span>            :                    : s1_pc_dup_0[40:5],</a>
+<a name="1208"><span class="lineNum">    1208 </span>            :                  _ways_29_io_resp_pftAddr,</a>
+<a name="1209"><span class="lineNum">    1209 </span>            :                  1'h0})</a>
+<a name="1210"><span class="lineNum">    1210 </span>            :          : 41'h0)</a>
+<a name="1211"><span class="lineNum">    1211 </span>            :     | (_ways_30_io_resp_hit</a>
+<a name="1212"><span class="lineNum">    1212 </span>            :          ? (s1_possible_full_preds_30_fallThroughErr</a>
+<a name="1213"><span class="lineNum">    1213 </span>            :               ? _s1_possible_full_preds_31_fallThroughAddr_T</a>
+<a name="1214"><span class="lineNum">    1214 </span>            :               : {_ways_30_io_resp_carry</a>
+<a name="1215"><span class="lineNum">    1215 </span>            :                    ? 36'(s1_pc_dup_0[40:5] + 36'h1)</a>
+<a name="1216"><span class="lineNum">    1216 </span>            :                    : s1_pc_dup_0[40:5],</a>
+<a name="1217"><span class="lineNum">    1217 </span>            :                  _ways_30_io_resp_pftAddr,</a>
+<a name="1218"><span class="lineNum">    1218 </span>            :                  1'h0})</a>
+<a name="1219"><span class="lineNum">    1219 </span>            :          : 41'h0)</a>
+<a name="1220"><span class="lineNum">    1220 </span>            :     | (_ways_31_io_resp_hit</a>
+<a name="1221"><span class="lineNum">    1221 </span>            :          ? (s1_possible_full_preds_31_fallThroughErr</a>
+<a name="1222"><span class="lineNum">    1222 </span>            :               ? _s1_possible_full_preds_31_fallThroughAddr_T</a>
+<a name="1223"><span class="lineNum">    1223 </span>            :               : {_ways_31_io_resp_carry</a>
+<a name="1224"><span class="lineNum">    1224 </span>            :                    ? 36'(s1_pc_dup_0[40:5] + 36'h1)</a>
+<a name="1225"><span class="lineNum">    1225 </span>            :                    : s1_pc_dup_0[40:5],</a>
+<a name="1226"><span class="lineNum">    1226 </span>            :                  _ways_31_io_resp_pftAddr,</a>
+<a name="1227"><span class="lineNum">    1227 </span>            :                  1'h0})</a>
+<a name="1228"><span class="lineNum">    1228 </span>            :          : 41'h0);</a>
+<a name="1229"><span class="lineNum">    1229 </span>            :   wire [3:0]  _s1_hit_full_pred_T_661 =</a>
+<a name="1230"><span class="lineNum">    1230 </span>            :     (_ways_0_io_resp_hit ? _ways_0_io_resp_brSlots_0_offset : 4'h0)</a>
+<a name="1231"><span class="lineNum">    1231 </span>            :     | (_ways_1_io_resp_hit ? _ways_1_io_resp_brSlots_0_offset : 4'h0)</a>
+<a name="1232"><span class="lineNum">    1232 </span>            :     | (_ways_2_io_resp_hit ? _ways_2_io_resp_brSlots_0_offset : 4'h0)</a>
+<a name="1233"><span class="lineNum">    1233 </span>            :     | (_ways_3_io_resp_hit ? _ways_3_io_resp_brSlots_0_offset : 4'h0)</a>
+<a name="1234"><span class="lineNum">    1234 </span>            :     | (_ways_4_io_resp_hit ? _ways_4_io_resp_brSlots_0_offset : 4'h0)</a>
+<a name="1235"><span class="lineNum">    1235 </span>            :     | (_ways_5_io_resp_hit ? _ways_5_io_resp_brSlots_0_offset : 4'h0)</a>
+<a name="1236"><span class="lineNum">    1236 </span>            :     | (_ways_6_io_resp_hit ? _ways_6_io_resp_brSlots_0_offset : 4'h0)</a>
+<a name="1237"><span class="lineNum">    1237 </span>            :     | (_ways_7_io_resp_hit ? _ways_7_io_resp_brSlots_0_offset : 4'h0)</a>
+<a name="1238"><span class="lineNum">    1238 </span>            :     | (_ways_8_io_resp_hit ? _ways_8_io_resp_brSlots_0_offset : 4'h0)</a>
+<a name="1239"><span class="lineNum">    1239 </span>            :     | (_ways_9_io_resp_hit ? _ways_9_io_resp_brSlots_0_offset : 4'h0)</a>
+<a name="1240"><span class="lineNum">    1240 </span>            :     | (_ways_10_io_resp_hit ? _ways_10_io_resp_brSlots_0_offset : 4'h0)</a>
+<a name="1241"><span class="lineNum">    1241 </span>            :     | (_ways_11_io_resp_hit ? _ways_11_io_resp_brSlots_0_offset : 4'h0)</a>
+<a name="1242"><span class="lineNum">    1242 </span>            :     | (_ways_12_io_resp_hit ? _ways_12_io_resp_brSlots_0_offset : 4'h0)</a>
+<a name="1243"><span class="lineNum">    1243 </span>            :     | (_ways_13_io_resp_hit ? _ways_13_io_resp_brSlots_0_offset : 4'h0)</a>
+<a name="1244"><span class="lineNum">    1244 </span>            :     | (_ways_14_io_resp_hit ? _ways_14_io_resp_brSlots_0_offset : 4'h0)</a>
+<a name="1245"><span class="lineNum">    1245 </span>            :     | (_ways_15_io_resp_hit ? _ways_15_io_resp_brSlots_0_offset : 4'h0)</a>
+<a name="1246"><span class="lineNum">    1246 </span>            :     | (_ways_16_io_resp_hit ? _ways_16_io_resp_brSlots_0_offset : 4'h0)</a>
+<a name="1247"><span class="lineNum">    1247 </span>            :     | (_ways_17_io_resp_hit ? _ways_17_io_resp_brSlots_0_offset : 4'h0)</a>
+<a name="1248"><span class="lineNum">    1248 </span>            :     | (_ways_18_io_resp_hit ? _ways_18_io_resp_brSlots_0_offset : 4'h0)</a>
+<a name="1249"><span class="lineNum">    1249 </span>            :     | (_ways_19_io_resp_hit ? _ways_19_io_resp_brSlots_0_offset : 4'h0)</a>
+<a name="1250"><span class="lineNum">    1250 </span>            :     | (_ways_20_io_resp_hit ? _ways_20_io_resp_brSlots_0_offset : 4'h0)</a>
+<a name="1251"><span class="lineNum">    1251 </span>            :     | (_ways_21_io_resp_hit ? _ways_21_io_resp_brSlots_0_offset : 4'h0)</a>
+<a name="1252"><span class="lineNum">    1252 </span>            :     | (_ways_22_io_resp_hit ? _ways_22_io_resp_brSlots_0_offset : 4'h0)</a>
+<a name="1253"><span class="lineNum">    1253 </span>            :     | (_ways_23_io_resp_hit ? _ways_23_io_resp_brSlots_0_offset : 4'h0)</a>
+<a name="1254"><span class="lineNum">    1254 </span>            :     | (_ways_24_io_resp_hit ? _ways_24_io_resp_brSlots_0_offset : 4'h0)</a>
+<a name="1255"><span class="lineNum">    1255 </span>            :     | (_ways_25_io_resp_hit ? _ways_25_io_resp_brSlots_0_offset : 4'h0)</a>
+<a name="1256"><span class="lineNum">    1256 </span>            :     | (_ways_26_io_resp_hit ? _ways_26_io_resp_brSlots_0_offset : 4'h0)</a>
+<a name="1257"><span class="lineNum">    1257 </span>            :     | (_ways_27_io_resp_hit ? _ways_27_io_resp_brSlots_0_offset : 4'h0)</a>
+<a name="1258"><span class="lineNum">    1258 </span>            :     | (_ways_28_io_resp_hit ? _ways_28_io_resp_brSlots_0_offset : 4'h0)</a>
+<a name="1259"><span class="lineNum">    1259 </span>            :     | (_ways_29_io_resp_hit ? _ways_29_io_resp_brSlots_0_offset : 4'h0)</a>
+<a name="1260"><span class="lineNum">    1260 </span>            :     | (_ways_30_io_resp_hit ? _ways_30_io_resp_brSlots_0_offset : 4'h0)</a>
+<a name="1261"><span class="lineNum">    1261 </span>            :     | (_ways_31_io_resp_hit ? _ways_31_io_resp_brSlots_0_offset : 4'h0);</a>
+<a name="1262"><span class="lineNum">    1262 </span>            :   wire [3:0]  _s1_hit_full_pred_T_724 =</a>
+<a name="1263"><span class="lineNum">    1263 </span>            :     (_ways_0_io_resp_hit ? _ways_0_io_resp_tailSlot_offset : 4'h0)</a>
+<a name="1264"><span class="lineNum">    1264 </span>            :     | (_ways_1_io_resp_hit ? _ways_1_io_resp_tailSlot_offset : 4'h0)</a>
+<a name="1265"><span class="lineNum">    1265 </span>            :     | (_ways_2_io_resp_hit ? _ways_2_io_resp_tailSlot_offset : 4'h0)</a>
+<a name="1266"><span class="lineNum">    1266 </span>            :     | (_ways_3_io_resp_hit ? _ways_3_io_resp_tailSlot_offset : 4'h0)</a>
+<a name="1267"><span class="lineNum">    1267 </span>            :     | (_ways_4_io_resp_hit ? _ways_4_io_resp_tailSlot_offset : 4'h0)</a>
+<a name="1268"><span class="lineNum">    1268 </span>            :     | (_ways_5_io_resp_hit ? _ways_5_io_resp_tailSlot_offset : 4'h0)</a>
+<a name="1269"><span class="lineNum">    1269 </span>            :     | (_ways_6_io_resp_hit ? _ways_6_io_resp_tailSlot_offset : 4'h0)</a>
+<a name="1270"><span class="lineNum">    1270 </span>            :     | (_ways_7_io_resp_hit ? _ways_7_io_resp_tailSlot_offset : 4'h0)</a>
+<a name="1271"><span class="lineNum">    1271 </span>            :     | (_ways_8_io_resp_hit ? _ways_8_io_resp_tailSlot_offset : 4'h0)</a>
+<a name="1272"><span class="lineNum">    1272 </span>            :     | (_ways_9_io_resp_hit ? _ways_9_io_resp_tailSlot_offset : 4'h0)</a>
+<a name="1273"><span class="lineNum">    1273 </span>            :     | (_ways_10_io_resp_hit ? _ways_10_io_resp_tailSlot_offset : 4'h0)</a>
+<a name="1274"><span class="lineNum">    1274 </span>            :     | (_ways_11_io_resp_hit ? _ways_11_io_resp_tailSlot_offset : 4'h0)</a>
+<a name="1275"><span class="lineNum">    1275 </span>            :     | (_ways_12_io_resp_hit ? _ways_12_io_resp_tailSlot_offset : 4'h0)</a>
+<a name="1276"><span class="lineNum">    1276 </span>            :     | (_ways_13_io_resp_hit ? _ways_13_io_resp_tailSlot_offset : 4'h0)</a>
+<a name="1277"><span class="lineNum">    1277 </span>            :     | (_ways_14_io_resp_hit ? _ways_14_io_resp_tailSlot_offset : 4'h0)</a>
+<a name="1278"><span class="lineNum">    1278 </span>            :     | (_ways_15_io_resp_hit ? _ways_15_io_resp_tailSlot_offset : 4'h0)</a>
+<a name="1279"><span class="lineNum">    1279 </span>            :     | (_ways_16_io_resp_hit ? _ways_16_io_resp_tailSlot_offset : 4'h0)</a>
+<a name="1280"><span class="lineNum">    1280 </span>            :     | (_ways_17_io_resp_hit ? _ways_17_io_resp_tailSlot_offset : 4'h0)</a>
+<a name="1281"><span class="lineNum">    1281 </span>            :     | (_ways_18_io_resp_hit ? _ways_18_io_resp_tailSlot_offset : 4'h0)</a>
+<a name="1282"><span class="lineNum">    1282 </span>            :     | (_ways_19_io_resp_hit ? _ways_19_io_resp_tailSlot_offset : 4'h0)</a>
+<a name="1283"><span class="lineNum">    1283 </span>            :     | (_ways_20_io_resp_hit ? _ways_20_io_resp_tailSlot_offset : 4'h0)</a>
+<a name="1284"><span class="lineNum">    1284 </span>            :     | (_ways_21_io_resp_hit ? _ways_21_io_resp_tailSlot_offset : 4'h0)</a>
+<a name="1285"><span class="lineNum">    1285 </span>            :     | (_ways_22_io_resp_hit ? _ways_22_io_resp_tailSlot_offset : 4'h0)</a>
+<a name="1286"><span class="lineNum">    1286 </span>            :     | (_ways_23_io_resp_hit ? _ways_23_io_resp_tailSlot_offset : 4'h0)</a>
+<a name="1287"><span class="lineNum">    1287 </span>            :     | (_ways_24_io_resp_hit ? _ways_24_io_resp_tailSlot_offset : 4'h0)</a>
+<a name="1288"><span class="lineNum">    1288 </span>            :     | (_ways_25_io_resp_hit ? _ways_25_io_resp_tailSlot_offset : 4'h0)</a>
+<a name="1289"><span class="lineNum">    1289 </span>            :     | (_ways_26_io_resp_hit ? _ways_26_io_resp_tailSlot_offset : 4'h0)</a>
+<a name="1290"><span class="lineNum">    1290 </span>            :     | (_ways_27_io_resp_hit ? _ways_27_io_resp_tailSlot_offset : 4'h0)</a>
+<a name="1291"><span class="lineNum">    1291 </span>            :     | (_ways_28_io_resp_hit ? _ways_28_io_resp_tailSlot_offset : 4'h0)</a>
+<a name="1292"><span class="lineNum">    1292 </span>            :     | (_ways_29_io_resp_hit ? _ways_29_io_resp_tailSlot_offset : 4'h0)</a>
+<a name="1293"><span class="lineNum">    1293 </span>            :     | (_ways_30_io_resp_hit ? _ways_30_io_resp_tailSlot_offset : 4'h0)</a>
+<a name="1294"><span class="lineNum">    1294 </span>            :     | (_ways_31_io_resp_hit ? _ways_31_io_resp_tailSlot_offset : 4'h0);</a>
+<a name="1295"><span class="lineNum">    1295 </span>            :   wire [40:0] _GEN =</a>
+<a name="1296"><span class="lineNum">    1296 </span>            :     (_ways_0_io_resp_hit</a>
+<a name="1297"><span class="lineNum">    1297 </span>            :        ? {(_ways_0_io_resp_brSlots_0_tarStat == 2'h1</a>
+<a name="1298"><span class="lineNum">    1298 </span>            :              ? 28'(s1_pc_dup_0[40:13] + 28'h1)</a>
+<a name="1299"><span class="lineNum">    1299 </span>            :              : 28'h0)</a>
+<a name="1300"><span class="lineNum">    1300 </span>            :             | (_ways_0_io_resp_brSlots_0_tarStat == 2'h2</a>
+<a name="1301"><span class="lineNum">    1301 </span>            :                  ? 28'(s1_pc_dup_0[40:13] - 28'h1)</a>
+<a name="1302"><span class="lineNum">    1302 </span>            :                  : 28'h0)</a>
+<a name="1303"><span class="lineNum">    1303 </span>            :             | (_ways_0_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0),</a>
+<a name="1304"><span class="lineNum">    1304 </span>            :           _ways_0_io_resp_brSlots_0_lower,</a>
+<a name="1305"><span class="lineNum">    1305 </span>            :           1'h0}</a>
+<a name="1306"><span class="lineNum">    1306 </span>            :        : 41'h0)</a>
+<a name="1307"><span class="lineNum">    1307 </span>            :     | (_ways_1_io_resp_hit</a>
+<a name="1308"><span class="lineNum">    1308 </span>            :          ? {(_ways_1_io_resp_brSlots_0_tarStat == 2'h1</a>
+<a name="1309"><span class="lineNum">    1309 </span>            :                ? 28'(s1_pc_dup_0[40:13] + 28'h1)</a>
+<a name="1310"><span class="lineNum">    1310 </span>            :                : 28'h0)</a>
+<a name="1311"><span class="lineNum">    1311 </span>            :               | (_ways_1_io_resp_brSlots_0_tarStat == 2'h2</a>
+<a name="1312"><span class="lineNum">    1312 </span>            :                    ? 28'(s1_pc_dup_0[40:13] - 28'h1)</a>
+<a name="1313"><span class="lineNum">    1313 </span>            :                    : 28'h0)</a>
+<a name="1314"><span class="lineNum">    1314 </span>            :               | (_ways_1_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0),</a>
+<a name="1315"><span class="lineNum">    1315 </span>            :             _ways_1_io_resp_brSlots_0_lower,</a>
+<a name="1316"><span class="lineNum">    1316 </span>            :             1'h0}</a>
+<a name="1317"><span class="lineNum">    1317 </span>            :          : 41'h0)</a>
+<a name="1318"><span class="lineNum">    1318 </span>            :     | (_ways_2_io_resp_hit</a>
+<a name="1319"><span class="lineNum">    1319 </span>            :          ? {(_ways_2_io_resp_brSlots_0_tarStat == 2'h1</a>
+<a name="1320"><span class="lineNum">    1320 </span>            :                ? 28'(s1_pc_dup_0[40:13] + 28'h1)</a>
+<a name="1321"><span class="lineNum">    1321 </span>            :                : 28'h0)</a>
+<a name="1322"><span class="lineNum">    1322 </span>            :               | (_ways_2_io_resp_brSlots_0_tarStat == 2'h2</a>
+<a name="1323"><span class="lineNum">    1323 </span>            :                    ? 28'(s1_pc_dup_0[40:13] - 28'h1)</a>
+<a name="1324"><span class="lineNum">    1324 </span>            :                    : 28'h0)</a>
+<a name="1325"><span class="lineNum">    1325 </span>            :               | (_ways_2_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0),</a>
+<a name="1326"><span class="lineNum">    1326 </span>            :             _ways_2_io_resp_brSlots_0_lower,</a>
+<a name="1327"><span class="lineNum">    1327 </span>            :             1'h0}</a>
+<a name="1328"><span class="lineNum">    1328 </span>            :          : 41'h0)</a>
+<a name="1329"><span class="lineNum">    1329 </span>            :     | (_ways_3_io_resp_hit</a>
+<a name="1330"><span class="lineNum">    1330 </span>            :          ? {(_ways_3_io_resp_brSlots_0_tarStat == 2'h1</a>
+<a name="1331"><span class="lineNum">    1331 </span>            :                ? 28'(s1_pc_dup_0[40:13] + 28'h1)</a>
+<a name="1332"><span class="lineNum">    1332 </span>            :                : 28'h0)</a>
+<a name="1333"><span class="lineNum">    1333 </span>            :               | (_ways_3_io_resp_brSlots_0_tarStat == 2'h2</a>
+<a name="1334"><span class="lineNum">    1334 </span>            :                    ? 28'(s1_pc_dup_0[40:13] - 28'h1)</a>
+<a name="1335"><span class="lineNum">    1335 </span>            :                    : 28'h0)</a>
+<a name="1336"><span class="lineNum">    1336 </span>            :               | (_ways_3_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0),</a>
+<a name="1337"><span class="lineNum">    1337 </span>            :             _ways_3_io_resp_brSlots_0_lower,</a>
+<a name="1338"><span class="lineNum">    1338 </span>            :             1'h0}</a>
+<a name="1339"><span class="lineNum">    1339 </span>            :          : 41'h0)</a>
+<a name="1340"><span class="lineNum">    1340 </span>            :     | (_ways_4_io_resp_hit</a>
+<a name="1341"><span class="lineNum">    1341 </span>            :          ? {(_ways_4_io_resp_brSlots_0_tarStat == 2'h1</a>
+<a name="1342"><span class="lineNum">    1342 </span>            :                ? 28'(s1_pc_dup_0[40:13] + 28'h1)</a>
+<a name="1343"><span class="lineNum">    1343 </span>            :                : 28'h0)</a>
+<a name="1344"><span class="lineNum">    1344 </span>            :               | (_ways_4_io_resp_brSlots_0_tarStat == 2'h2</a>
+<a name="1345"><span class="lineNum">    1345 </span>            :                    ? 28'(s1_pc_dup_0[40:13] - 28'h1)</a>
+<a name="1346"><span class="lineNum">    1346 </span>            :                    : 28'h0)</a>
+<a name="1347"><span class="lineNum">    1347 </span>            :               | (_ways_4_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0),</a>
+<a name="1348"><span class="lineNum">    1348 </span>            :             _ways_4_io_resp_brSlots_0_lower,</a>
+<a name="1349"><span class="lineNum">    1349 </span>            :             1'h0}</a>
+<a name="1350"><span class="lineNum">    1350 </span>            :          : 41'h0)</a>
+<a name="1351"><span class="lineNum">    1351 </span>            :     | (_ways_5_io_resp_hit</a>
+<a name="1352"><span class="lineNum">    1352 </span>            :          ? {(_ways_5_io_resp_brSlots_0_tarStat == 2'h1</a>
+<a name="1353"><span class="lineNum">    1353 </span>            :                ? 28'(s1_pc_dup_0[40:13] + 28'h1)</a>
+<a name="1354"><span class="lineNum">    1354 </span>            :                : 28'h0)</a>
+<a name="1355"><span class="lineNum">    1355 </span>            :               | (_ways_5_io_resp_brSlots_0_tarStat == 2'h2</a>
+<a name="1356"><span class="lineNum">    1356 </span>            :                    ? 28'(s1_pc_dup_0[40:13] - 28'h1)</a>
+<a name="1357"><span class="lineNum">    1357 </span>            :                    : 28'h0)</a>
+<a name="1358"><span class="lineNum">    1358 </span>            :               | (_ways_5_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0),</a>
+<a name="1359"><span class="lineNum">    1359 </span>            :             _ways_5_io_resp_brSlots_0_lower,</a>
+<a name="1360"><span class="lineNum">    1360 </span>            :             1'h0}</a>
+<a name="1361"><span class="lineNum">    1361 </span>            :          : 41'h0)</a>
+<a name="1362"><span class="lineNum">    1362 </span>            :     | (_ways_6_io_resp_hit</a>
+<a name="1363"><span class="lineNum">    1363 </span>            :          ? {(_ways_6_io_resp_brSlots_0_tarStat == 2'h1</a>
+<a name="1364"><span class="lineNum">    1364 </span>            :                ? 28'(s1_pc_dup_0[40:13] + 28'h1)</a>
+<a name="1365"><span class="lineNum">    1365 </span>            :                : 28'h0)</a>
+<a name="1366"><span class="lineNum">    1366 </span>            :               | (_ways_6_io_resp_brSlots_0_tarStat == 2'h2</a>
+<a name="1367"><span class="lineNum">    1367 </span>            :                    ? 28'(s1_pc_dup_0[40:13] - 28'h1)</a>
+<a name="1368"><span class="lineNum">    1368 </span>            :                    : 28'h0)</a>
+<a name="1369"><span class="lineNum">    1369 </span>            :               | (_ways_6_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0),</a>
+<a name="1370"><span class="lineNum">    1370 </span>            :             _ways_6_io_resp_brSlots_0_lower,</a>
+<a name="1371"><span class="lineNum">    1371 </span>            :             1'h0}</a>
+<a name="1372"><span class="lineNum">    1372 </span>            :          : 41'h0)</a>
+<a name="1373"><span class="lineNum">    1373 </span>            :     | (_ways_7_io_resp_hit</a>
+<a name="1374"><span class="lineNum">    1374 </span>            :          ? {(_ways_7_io_resp_brSlots_0_tarStat == 2'h1</a>
+<a name="1375"><span class="lineNum">    1375 </span>            :                ? 28'(s1_pc_dup_0[40:13] + 28'h1)</a>
+<a name="1376"><span class="lineNum">    1376 </span>            :                : 28'h0)</a>
+<a name="1377"><span class="lineNum">    1377 </span>            :               | (_ways_7_io_resp_brSlots_0_tarStat == 2'h2</a>
+<a name="1378"><span class="lineNum">    1378 </span>            :                    ? 28'(s1_pc_dup_0[40:13] - 28'h1)</a>
+<a name="1379"><span class="lineNum">    1379 </span>            :                    : 28'h0)</a>
+<a name="1380"><span class="lineNum">    1380 </span>            :               | (_ways_7_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0),</a>
+<a name="1381"><span class="lineNum">    1381 </span>            :             _ways_7_io_resp_brSlots_0_lower,</a>
+<a name="1382"><span class="lineNum">    1382 </span>            :             1'h0}</a>
+<a name="1383"><span class="lineNum">    1383 </span>            :          : 41'h0)</a>
+<a name="1384"><span class="lineNum">    1384 </span>            :     | (_ways_8_io_resp_hit</a>
+<a name="1385"><span class="lineNum">    1385 </span>            :          ? {(_ways_8_io_resp_brSlots_0_tarStat == 2'h1</a>
+<a name="1386"><span class="lineNum">    1386 </span>            :                ? 28'(s1_pc_dup_0[40:13] + 28'h1)</a>
+<a name="1387"><span class="lineNum">    1387 </span>            :                : 28'h0)</a>
+<a name="1388"><span class="lineNum">    1388 </span>            :               | (_ways_8_io_resp_brSlots_0_tarStat == 2'h2</a>
+<a name="1389"><span class="lineNum">    1389 </span>            :                    ? 28'(s1_pc_dup_0[40:13] - 28'h1)</a>
+<a name="1390"><span class="lineNum">    1390 </span>            :                    : 28'h0)</a>
+<a name="1391"><span class="lineNum">    1391 </span>            :               | (_ways_8_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0),</a>
+<a name="1392"><span class="lineNum">    1392 </span>            :             _ways_8_io_resp_brSlots_0_lower,</a>
+<a name="1393"><span class="lineNum">    1393 </span>            :             1'h0}</a>
+<a name="1394"><span class="lineNum">    1394 </span>            :          : 41'h0)</a>
+<a name="1395"><span class="lineNum">    1395 </span>            :     | (_ways_9_io_resp_hit</a>
+<a name="1396"><span class="lineNum">    1396 </span>            :          ? {(_ways_9_io_resp_brSlots_0_tarStat == 2'h1</a>
+<a name="1397"><span class="lineNum">    1397 </span>            :                ? 28'(s1_pc_dup_0[40:13] + 28'h1)</a>
+<a name="1398"><span class="lineNum">    1398 </span>            :                : 28'h0)</a>
+<a name="1399"><span class="lineNum">    1399 </span>            :               | (_ways_9_io_resp_brSlots_0_tarStat == 2'h2</a>
+<a name="1400"><span class="lineNum">    1400 </span>            :                    ? 28'(s1_pc_dup_0[40:13] - 28'h1)</a>
+<a name="1401"><span class="lineNum">    1401 </span>            :                    : 28'h0)</a>
+<a name="1402"><span class="lineNum">    1402 </span>            :               | (_ways_9_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0),</a>
+<a name="1403"><span class="lineNum">    1403 </span>            :             _ways_9_io_resp_brSlots_0_lower,</a>
+<a name="1404"><span class="lineNum">    1404 </span>            :             1'h0}</a>
+<a name="1405"><span class="lineNum">    1405 </span>            :          : 41'h0)</a>
+<a name="1406"><span class="lineNum">    1406 </span>            :     | (_ways_10_io_resp_hit</a>
+<a name="1407"><span class="lineNum">    1407 </span>            :          ? {(_ways_10_io_resp_brSlots_0_tarStat == 2'h1</a>
+<a name="1408"><span class="lineNum">    1408 </span>            :                ? 28'(s1_pc_dup_0[40:13] + 28'h1)</a>
+<a name="1409"><span class="lineNum">    1409 </span>            :                : 28'h0)</a>
+<a name="1410"><span class="lineNum">    1410 </span>            :               | (_ways_10_io_resp_brSlots_0_tarStat == 2'h2</a>
+<a name="1411"><span class="lineNum">    1411 </span>            :                    ? 28'(s1_pc_dup_0[40:13] - 28'h1)</a>
+<a name="1412"><span class="lineNum">    1412 </span>            :                    : 28'h0)</a>
+<a name="1413"><span class="lineNum">    1413 </span>            :               | (_ways_10_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0),</a>
+<a name="1414"><span class="lineNum">    1414 </span>            :             _ways_10_io_resp_brSlots_0_lower,</a>
+<a name="1415"><span class="lineNum">    1415 </span>            :             1'h0}</a>
+<a name="1416"><span class="lineNum">    1416 </span>            :          : 41'h0)</a>
+<a name="1417"><span class="lineNum">    1417 </span>            :     | (_ways_11_io_resp_hit</a>
+<a name="1418"><span class="lineNum">    1418 </span>            :          ? {(_ways_11_io_resp_brSlots_0_tarStat == 2'h1</a>
+<a name="1419"><span class="lineNum">    1419 </span>            :                ? 28'(s1_pc_dup_0[40:13] + 28'h1)</a>
+<a name="1420"><span class="lineNum">    1420 </span>            :                : 28'h0)</a>
+<a name="1421"><span class="lineNum">    1421 </span>            :               | (_ways_11_io_resp_brSlots_0_tarStat == 2'h2</a>
+<a name="1422"><span class="lineNum">    1422 </span>            :                    ? 28'(s1_pc_dup_0[40:13] - 28'h1)</a>
+<a name="1423"><span class="lineNum">    1423 </span>            :                    : 28'h0)</a>
+<a name="1424"><span class="lineNum">    1424 </span>            :               | (_ways_11_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0),</a>
+<a name="1425"><span class="lineNum">    1425 </span>            :             _ways_11_io_resp_brSlots_0_lower,</a>
+<a name="1426"><span class="lineNum">    1426 </span>            :             1'h0}</a>
+<a name="1427"><span class="lineNum">    1427 </span>            :          : 41'h0)</a>
+<a name="1428"><span class="lineNum">    1428 </span>            :     | (_ways_12_io_resp_hit</a>
+<a name="1429"><span class="lineNum">    1429 </span>            :          ? {(_ways_12_io_resp_brSlots_0_tarStat == 2'h1</a>
+<a name="1430"><span class="lineNum">    1430 </span>            :                ? 28'(s1_pc_dup_0[40:13] + 28'h1)</a>
+<a name="1431"><span class="lineNum">    1431 </span>            :                : 28'h0)</a>
+<a name="1432"><span class="lineNum">    1432 </span>            :               | (_ways_12_io_resp_brSlots_0_tarStat == 2'h2</a>
+<a name="1433"><span class="lineNum">    1433 </span>            :                    ? 28'(s1_pc_dup_0[40:13] - 28'h1)</a>
+<a name="1434"><span class="lineNum">    1434 </span>            :                    : 28'h0)</a>
+<a name="1435"><span class="lineNum">    1435 </span>            :               | (_ways_12_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0),</a>
+<a name="1436"><span class="lineNum">    1436 </span>            :             _ways_12_io_resp_brSlots_0_lower,</a>
+<a name="1437"><span class="lineNum">    1437 </span>            :             1'h0}</a>
+<a name="1438"><span class="lineNum">    1438 </span>            :          : 41'h0)</a>
+<a name="1439"><span class="lineNum">    1439 </span>            :     | (_ways_13_io_resp_hit</a>
+<a name="1440"><span class="lineNum">    1440 </span>            :          ? {(_ways_13_io_resp_brSlots_0_tarStat == 2'h1</a>
+<a name="1441"><span class="lineNum">    1441 </span>            :                ? 28'(s1_pc_dup_0[40:13] + 28'h1)</a>
+<a name="1442"><span class="lineNum">    1442 </span>            :                : 28'h0)</a>
+<a name="1443"><span class="lineNum">    1443 </span>            :               | (_ways_13_io_resp_brSlots_0_tarStat == 2'h2</a>
+<a name="1444"><span class="lineNum">    1444 </span>            :                    ? 28'(s1_pc_dup_0[40:13] - 28'h1)</a>
+<a name="1445"><span class="lineNum">    1445 </span>            :                    : 28'h0)</a>
+<a name="1446"><span class="lineNum">    1446 </span>            :               | (_ways_13_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0),</a>
+<a name="1447"><span class="lineNum">    1447 </span>            :             _ways_13_io_resp_brSlots_0_lower,</a>
+<a name="1448"><span class="lineNum">    1448 </span>            :             1'h0}</a>
+<a name="1449"><span class="lineNum">    1449 </span>            :          : 41'h0)</a>
+<a name="1450"><span class="lineNum">    1450 </span>            :     | (_ways_14_io_resp_hit</a>
+<a name="1451"><span class="lineNum">    1451 </span>            :          ? {(_ways_14_io_resp_brSlots_0_tarStat == 2'h1</a>
+<a name="1452"><span class="lineNum">    1452 </span>            :                ? 28'(s1_pc_dup_0[40:13] + 28'h1)</a>
+<a name="1453"><span class="lineNum">    1453 </span>            :                : 28'h0)</a>
+<a name="1454"><span class="lineNum">    1454 </span>            :               | (_ways_14_io_resp_brSlots_0_tarStat == 2'h2</a>
+<a name="1455"><span class="lineNum">    1455 </span>            :                    ? 28'(s1_pc_dup_0[40:13] - 28'h1)</a>
+<a name="1456"><span class="lineNum">    1456 </span>            :                    : 28'h0)</a>
+<a name="1457"><span class="lineNum">    1457 </span>            :               | (_ways_14_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0),</a>
+<a name="1458"><span class="lineNum">    1458 </span>            :             _ways_14_io_resp_brSlots_0_lower,</a>
+<a name="1459"><span class="lineNum">    1459 </span>            :             1'h0}</a>
+<a name="1460"><span class="lineNum">    1460 </span>            :          : 41'h0)</a>
+<a name="1461"><span class="lineNum">    1461 </span>            :     | (_ways_15_io_resp_hit</a>
+<a name="1462"><span class="lineNum">    1462 </span>            :          ? {(_ways_15_io_resp_brSlots_0_tarStat == 2'h1</a>
+<a name="1463"><span class="lineNum">    1463 </span>            :                ? 28'(s1_pc_dup_0[40:13] + 28'h1)</a>
+<a name="1464"><span class="lineNum">    1464 </span>            :                : 28'h0)</a>
+<a name="1465"><span class="lineNum">    1465 </span>            :               | (_ways_15_io_resp_brSlots_0_tarStat == 2'h2</a>
+<a name="1466"><span class="lineNum">    1466 </span>            :                    ? 28'(s1_pc_dup_0[40:13] - 28'h1)</a>
+<a name="1467"><span class="lineNum">    1467 </span>            :                    : 28'h0)</a>
+<a name="1468"><span class="lineNum">    1468 </span>            :               | (_ways_15_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0),</a>
+<a name="1469"><span class="lineNum">    1469 </span>            :             _ways_15_io_resp_brSlots_0_lower,</a>
+<a name="1470"><span class="lineNum">    1470 </span>            :             1'h0}</a>
+<a name="1471"><span class="lineNum">    1471 </span>            :          : 41'h0);</a>
+<a name="1472"><span class="lineNum">    1472 </span>            :   wire [40:0] _GEN_0 =</a>
+<a name="1473"><span class="lineNum">    1473 </span>            :     (_ways_16_io_resp_hit</a>
+<a name="1474"><span class="lineNum">    1474 </span>            :        ? {(_ways_16_io_resp_brSlots_0_tarStat == 2'h1</a>
+<a name="1475"><span class="lineNum">    1475 </span>            :              ? 28'(s1_pc_dup_0[40:13] + 28'h1)</a>
+<a name="1476"><span class="lineNum">    1476 </span>            :              : 28'h0)</a>
+<a name="1477"><span class="lineNum">    1477 </span>            :             | (_ways_16_io_resp_brSlots_0_tarStat == 2'h2</a>
+<a name="1478"><span class="lineNum">    1478 </span>            :                  ? 28'(s1_pc_dup_0[40:13] - 28'h1)</a>
+<a name="1479"><span class="lineNum">    1479 </span>            :                  : 28'h0)</a>
+<a name="1480"><span class="lineNum">    1480 </span>            :             | (_ways_16_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0),</a>
+<a name="1481"><span class="lineNum">    1481 </span>            :           _ways_16_io_resp_brSlots_0_lower,</a>
+<a name="1482"><span class="lineNum">    1482 </span>            :           1'h0}</a>
+<a name="1483"><span class="lineNum">    1483 </span>            :        : 41'h0)</a>
+<a name="1484"><span class="lineNum">    1484 </span>            :     | (_ways_17_io_resp_hit</a>
+<a name="1485"><span class="lineNum">    1485 </span>            :          ? {(_ways_17_io_resp_brSlots_0_tarStat == 2'h1</a>
+<a name="1486"><span class="lineNum">    1486 </span>            :                ? 28'(s1_pc_dup_0[40:13] + 28'h1)</a>
+<a name="1487"><span class="lineNum">    1487 </span>            :                : 28'h0)</a>
+<a name="1488"><span class="lineNum">    1488 </span>            :               | (_ways_17_io_resp_brSlots_0_tarStat == 2'h2</a>
+<a name="1489"><span class="lineNum">    1489 </span>            :                    ? 28'(s1_pc_dup_0[40:13] - 28'h1)</a>
+<a name="1490"><span class="lineNum">    1490 </span>            :                    : 28'h0)</a>
+<a name="1491"><span class="lineNum">    1491 </span>            :               | (_ways_17_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0),</a>
+<a name="1492"><span class="lineNum">    1492 </span>            :             _ways_17_io_resp_brSlots_0_lower,</a>
+<a name="1493"><span class="lineNum">    1493 </span>            :             1'h0}</a>
+<a name="1494"><span class="lineNum">    1494 </span>            :          : 41'h0)</a>
+<a name="1495"><span class="lineNum">    1495 </span>            :     | (_ways_18_io_resp_hit</a>
+<a name="1496"><span class="lineNum">    1496 </span>            :          ? {(_ways_18_io_resp_brSlots_0_tarStat == 2'h1</a>
+<a name="1497"><span class="lineNum">    1497 </span>            :                ? 28'(s1_pc_dup_0[40:13] + 28'h1)</a>
+<a name="1498"><span class="lineNum">    1498 </span>            :                : 28'h0)</a>
+<a name="1499"><span class="lineNum">    1499 </span>            :               | (_ways_18_io_resp_brSlots_0_tarStat == 2'h2</a>
+<a name="1500"><span class="lineNum">    1500 </span>            :                    ? 28'(s1_pc_dup_0[40:13] - 28'h1)</a>
+<a name="1501"><span class="lineNum">    1501 </span>            :                    : 28'h0)</a>
+<a name="1502"><span class="lineNum">    1502 </span>            :               | (_ways_18_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0),</a>
+<a name="1503"><span class="lineNum">    1503 </span>            :             _ways_18_io_resp_brSlots_0_lower,</a>
+<a name="1504"><span class="lineNum">    1504 </span>            :             1'h0}</a>
+<a name="1505"><span class="lineNum">    1505 </span>            :          : 41'h0)</a>
+<a name="1506"><span class="lineNum">    1506 </span>            :     | (_ways_19_io_resp_hit</a>
+<a name="1507"><span class="lineNum">    1507 </span>            :          ? {(_ways_19_io_resp_brSlots_0_tarStat == 2'h1</a>
+<a name="1508"><span class="lineNum">    1508 </span>            :                ? 28'(s1_pc_dup_0[40:13] + 28'h1)</a>
+<a name="1509"><span class="lineNum">    1509 </span>            :                : 28'h0)</a>
+<a name="1510"><span class="lineNum">    1510 </span>            :               | (_ways_19_io_resp_brSlots_0_tarStat == 2'h2</a>
+<a name="1511"><span class="lineNum">    1511 </span>            :                    ? 28'(s1_pc_dup_0[40:13] - 28'h1)</a>
+<a name="1512"><span class="lineNum">    1512 </span>            :                    : 28'h0)</a>
+<a name="1513"><span class="lineNum">    1513 </span>            :               | (_ways_19_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0),</a>
+<a name="1514"><span class="lineNum">    1514 </span>            :             _ways_19_io_resp_brSlots_0_lower,</a>
+<a name="1515"><span class="lineNum">    1515 </span>            :             1'h0}</a>
+<a name="1516"><span class="lineNum">    1516 </span>            :          : 41'h0)</a>
+<a name="1517"><span class="lineNum">    1517 </span>            :     | (_ways_20_io_resp_hit</a>
+<a name="1518"><span class="lineNum">    1518 </span>            :          ? {(_ways_20_io_resp_brSlots_0_tarStat == 2'h1</a>
+<a name="1519"><span class="lineNum">    1519 </span>            :                ? 28'(s1_pc_dup_0[40:13] + 28'h1)</a>
+<a name="1520"><span class="lineNum">    1520 </span>            :                : 28'h0)</a>
+<a name="1521"><span class="lineNum">    1521 </span>            :               | (_ways_20_io_resp_brSlots_0_tarStat == 2'h2</a>
+<a name="1522"><span class="lineNum">    1522 </span>            :                    ? 28'(s1_pc_dup_0[40:13] - 28'h1)</a>
+<a name="1523"><span class="lineNum">    1523 </span>            :                    : 28'h0)</a>
+<a name="1524"><span class="lineNum">    1524 </span>            :               | (_ways_20_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0),</a>
+<a name="1525"><span class="lineNum">    1525 </span>            :             _ways_20_io_resp_brSlots_0_lower,</a>
+<a name="1526"><span class="lineNum">    1526 </span>            :             1'h0}</a>
+<a name="1527"><span class="lineNum">    1527 </span>            :          : 41'h0)</a>
+<a name="1528"><span class="lineNum">    1528 </span>            :     | (_ways_21_io_resp_hit</a>
+<a name="1529"><span class="lineNum">    1529 </span>            :          ? {(_ways_21_io_resp_brSlots_0_tarStat == 2'h1</a>
+<a name="1530"><span class="lineNum">    1530 </span>            :                ? 28'(s1_pc_dup_0[40:13] + 28'h1)</a>
+<a name="1531"><span class="lineNum">    1531 </span>            :                : 28'h0)</a>
+<a name="1532"><span class="lineNum">    1532 </span>            :               | (_ways_21_io_resp_brSlots_0_tarStat == 2'h2</a>
+<a name="1533"><span class="lineNum">    1533 </span>            :                    ? 28'(s1_pc_dup_0[40:13] - 28'h1)</a>
+<a name="1534"><span class="lineNum">    1534 </span>            :                    : 28'h0)</a>
+<a name="1535"><span class="lineNum">    1535 </span>            :               | (_ways_21_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0),</a>
+<a name="1536"><span class="lineNum">    1536 </span>            :             _ways_21_io_resp_brSlots_0_lower,</a>
+<a name="1537"><span class="lineNum">    1537 </span>            :             1'h0}</a>
+<a name="1538"><span class="lineNum">    1538 </span>            :          : 41'h0)</a>
+<a name="1539"><span class="lineNum">    1539 </span>            :     | (_ways_22_io_resp_hit</a>
+<a name="1540"><span class="lineNum">    1540 </span>            :          ? {(_ways_22_io_resp_brSlots_0_tarStat == 2'h1</a>
+<a name="1541"><span class="lineNum">    1541 </span>            :                ? 28'(s1_pc_dup_0[40:13] + 28'h1)</a>
+<a name="1542"><span class="lineNum">    1542 </span>            :                : 28'h0)</a>
+<a name="1543"><span class="lineNum">    1543 </span>            :               | (_ways_22_io_resp_brSlots_0_tarStat == 2'h2</a>
+<a name="1544"><span class="lineNum">    1544 </span>            :                    ? 28'(s1_pc_dup_0[40:13] - 28'h1)</a>
+<a name="1545"><span class="lineNum">    1545 </span>            :                    : 28'h0)</a>
+<a name="1546"><span class="lineNum">    1546 </span>            :               | (_ways_22_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0),</a>
+<a name="1547"><span class="lineNum">    1547 </span>            :             _ways_22_io_resp_brSlots_0_lower,</a>
+<a name="1548"><span class="lineNum">    1548 </span>            :             1'h0}</a>
+<a name="1549"><span class="lineNum">    1549 </span>            :          : 41'h0)</a>
+<a name="1550"><span class="lineNum">    1550 </span>            :     | (_ways_23_io_resp_hit</a>
+<a name="1551"><span class="lineNum">    1551 </span>            :          ? {(_ways_23_io_resp_brSlots_0_tarStat == 2'h1</a>
+<a name="1552"><span class="lineNum">    1552 </span>            :                ? 28'(s1_pc_dup_0[40:13] + 28'h1)</a>
+<a name="1553"><span class="lineNum">    1553 </span>            :                : 28'h0)</a>
+<a name="1554"><span class="lineNum">    1554 </span>            :               | (_ways_23_io_resp_brSlots_0_tarStat == 2'h2</a>
+<a name="1555"><span class="lineNum">    1555 </span>            :                    ? 28'(s1_pc_dup_0[40:13] - 28'h1)</a>
+<a name="1556"><span class="lineNum">    1556 </span>            :                    : 28'h0)</a>
+<a name="1557"><span class="lineNum">    1557 </span>            :               | (_ways_23_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0),</a>
+<a name="1558"><span class="lineNum">    1558 </span>            :             _ways_23_io_resp_brSlots_0_lower,</a>
+<a name="1559"><span class="lineNum">    1559 </span>            :             1'h0}</a>
+<a name="1560"><span class="lineNum">    1560 </span>            :          : 41'h0)</a>
+<a name="1561"><span class="lineNum">    1561 </span>            :     | (_ways_24_io_resp_hit</a>
+<a name="1562"><span class="lineNum">    1562 </span>            :          ? {(_ways_24_io_resp_brSlots_0_tarStat == 2'h1</a>
+<a name="1563"><span class="lineNum">    1563 </span>            :                ? 28'(s1_pc_dup_0[40:13] + 28'h1)</a>
+<a name="1564"><span class="lineNum">    1564 </span>            :                : 28'h0)</a>
+<a name="1565"><span class="lineNum">    1565 </span>            :               | (_ways_24_io_resp_brSlots_0_tarStat == 2'h2</a>
+<a name="1566"><span class="lineNum">    1566 </span>            :                    ? 28'(s1_pc_dup_0[40:13] - 28'h1)</a>
+<a name="1567"><span class="lineNum">    1567 </span>            :                    : 28'h0)</a>
+<a name="1568"><span class="lineNum">    1568 </span>            :               | (_ways_24_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0),</a>
+<a name="1569"><span class="lineNum">    1569 </span>            :             _ways_24_io_resp_brSlots_0_lower,</a>
+<a name="1570"><span class="lineNum">    1570 </span>            :             1'h0}</a>
+<a name="1571"><span class="lineNum">    1571 </span>            :          : 41'h0)</a>
+<a name="1572"><span class="lineNum">    1572 </span>            :     | (_ways_25_io_resp_hit</a>
+<a name="1573"><span class="lineNum">    1573 </span>            :          ? {(_ways_25_io_resp_brSlots_0_tarStat == 2'h1</a>
+<a name="1574"><span class="lineNum">    1574 </span>            :                ? 28'(s1_pc_dup_0[40:13] + 28'h1)</a>
+<a name="1575"><span class="lineNum">    1575 </span>            :                : 28'h0)</a>
+<a name="1576"><span class="lineNum">    1576 </span>            :               | (_ways_25_io_resp_brSlots_0_tarStat == 2'h2</a>
+<a name="1577"><span class="lineNum">    1577 </span>            :                    ? 28'(s1_pc_dup_0[40:13] - 28'h1)</a>
+<a name="1578"><span class="lineNum">    1578 </span>            :                    : 28'h0)</a>
+<a name="1579"><span class="lineNum">    1579 </span>            :               | (_ways_25_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0),</a>
+<a name="1580"><span class="lineNum">    1580 </span>            :             _ways_25_io_resp_brSlots_0_lower,</a>
+<a name="1581"><span class="lineNum">    1581 </span>            :             1'h0}</a>
+<a name="1582"><span class="lineNum">    1582 </span>            :          : 41'h0)</a>
+<a name="1583"><span class="lineNum">    1583 </span>            :     | (_ways_26_io_resp_hit</a>
+<a name="1584"><span class="lineNum">    1584 </span>            :          ? {(_ways_26_io_resp_brSlots_0_tarStat == 2'h1</a>
+<a name="1585"><span class="lineNum">    1585 </span>            :                ? 28'(s1_pc_dup_0[40:13] + 28'h1)</a>
+<a name="1586"><span class="lineNum">    1586 </span>            :                : 28'h0)</a>
+<a name="1587"><span class="lineNum">    1587 </span>            :               | (_ways_26_io_resp_brSlots_0_tarStat == 2'h2</a>
+<a name="1588"><span class="lineNum">    1588 </span>            :                    ? 28'(s1_pc_dup_0[40:13] - 28'h1)</a>
+<a name="1589"><span class="lineNum">    1589 </span>            :                    : 28'h0)</a>
+<a name="1590"><span class="lineNum">    1590 </span>            :               | (_ways_26_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0),</a>
+<a name="1591"><span class="lineNum">    1591 </span>            :             _ways_26_io_resp_brSlots_0_lower,</a>
+<a name="1592"><span class="lineNum">    1592 </span>            :             1'h0}</a>
+<a name="1593"><span class="lineNum">    1593 </span>            :          : 41'h0)</a>
+<a name="1594"><span class="lineNum">    1594 </span>            :     | (_ways_27_io_resp_hit</a>
+<a name="1595"><span class="lineNum">    1595 </span>            :          ? {(_ways_27_io_resp_brSlots_0_tarStat == 2'h1</a>
+<a name="1596"><span class="lineNum">    1596 </span>            :                ? 28'(s1_pc_dup_0[40:13] + 28'h1)</a>
+<a name="1597"><span class="lineNum">    1597 </span>            :                : 28'h0)</a>
+<a name="1598"><span class="lineNum">    1598 </span>            :               | (_ways_27_io_resp_brSlots_0_tarStat == 2'h2</a>
+<a name="1599"><span class="lineNum">    1599 </span>            :                    ? 28'(s1_pc_dup_0[40:13] - 28'h1)</a>
+<a name="1600"><span class="lineNum">    1600 </span>            :                    : 28'h0)</a>
+<a name="1601"><span class="lineNum">    1601 </span>            :               | (_ways_27_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0),</a>
+<a name="1602"><span class="lineNum">    1602 </span>            :             _ways_27_io_resp_brSlots_0_lower,</a>
+<a name="1603"><span class="lineNum">    1603 </span>            :             1'h0}</a>
+<a name="1604"><span class="lineNum">    1604 </span>            :          : 41'h0)</a>
+<a name="1605"><span class="lineNum">    1605 </span>            :     | (_ways_28_io_resp_hit</a>
+<a name="1606"><span class="lineNum">    1606 </span>            :          ? {(_ways_28_io_resp_brSlots_0_tarStat == 2'h1</a>
+<a name="1607"><span class="lineNum">    1607 </span>            :                ? 28'(s1_pc_dup_0[40:13] + 28'h1)</a>
+<a name="1608"><span class="lineNum">    1608 </span>            :                : 28'h0)</a>
+<a name="1609"><span class="lineNum">    1609 </span>            :               | (_ways_28_io_resp_brSlots_0_tarStat == 2'h2</a>
+<a name="1610"><span class="lineNum">    1610 </span>            :                    ? 28'(s1_pc_dup_0[40:13] - 28'h1)</a>
+<a name="1611"><span class="lineNum">    1611 </span>            :                    : 28'h0)</a>
+<a name="1612"><span class="lineNum">    1612 </span>            :               | (_ways_28_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0),</a>
+<a name="1613"><span class="lineNum">    1613 </span>            :             _ways_28_io_resp_brSlots_0_lower,</a>
+<a name="1614"><span class="lineNum">    1614 </span>            :             1'h0}</a>
+<a name="1615"><span class="lineNum">    1615 </span>            :          : 41'h0)</a>
+<a name="1616"><span class="lineNum">    1616 </span>            :     | (_ways_29_io_resp_hit</a>
+<a name="1617"><span class="lineNum">    1617 </span>            :          ? {(_ways_29_io_resp_brSlots_0_tarStat == 2'h1</a>
+<a name="1618"><span class="lineNum">    1618 </span>            :                ? 28'(s1_pc_dup_0[40:13] + 28'h1)</a>
+<a name="1619"><span class="lineNum">    1619 </span>            :                : 28'h0)</a>
+<a name="1620"><span class="lineNum">    1620 </span>            :               | (_ways_29_io_resp_brSlots_0_tarStat == 2'h2</a>
+<a name="1621"><span class="lineNum">    1621 </span>            :                    ? 28'(s1_pc_dup_0[40:13] - 28'h1)</a>
+<a name="1622"><span class="lineNum">    1622 </span>            :                    : 28'h0)</a>
+<a name="1623"><span class="lineNum">    1623 </span>            :               | (_ways_29_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0),</a>
+<a name="1624"><span class="lineNum">    1624 </span>            :             _ways_29_io_resp_brSlots_0_lower,</a>
+<a name="1625"><span class="lineNum">    1625 </span>            :             1'h0}</a>
+<a name="1626"><span class="lineNum">    1626 </span>            :          : 41'h0)</a>
+<a name="1627"><span class="lineNum">    1627 </span>            :     | (_ways_30_io_resp_hit</a>
+<a name="1628"><span class="lineNum">    1628 </span>            :          ? {(_ways_30_io_resp_brSlots_0_tarStat == 2'h1</a>
+<a name="1629"><span class="lineNum">    1629 </span>            :                ? 28'(s1_pc_dup_0[40:13] + 28'h1)</a>
+<a name="1630"><span class="lineNum">    1630 </span>            :                : 28'h0)</a>
+<a name="1631"><span class="lineNum">    1631 </span>            :               | (_ways_30_io_resp_brSlots_0_tarStat == 2'h2</a>
+<a name="1632"><span class="lineNum">    1632 </span>            :                    ? 28'(s1_pc_dup_0[40:13] - 28'h1)</a>
+<a name="1633"><span class="lineNum">    1633 </span>            :                    : 28'h0)</a>
+<a name="1634"><span class="lineNum">    1634 </span>            :               | (_ways_30_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0),</a>
+<a name="1635"><span class="lineNum">    1635 </span>            :             _ways_30_io_resp_brSlots_0_lower,</a>
+<a name="1636"><span class="lineNum">    1636 </span>            :             1'h0}</a>
+<a name="1637"><span class="lineNum">    1637 </span>            :          : 41'h0)</a>
+<a name="1638"><span class="lineNum">    1638 </span>            :     | (_ways_31_io_resp_hit</a>
+<a name="1639"><span class="lineNum">    1639 </span>            :          ? {(_ways_31_io_resp_brSlots_0_tarStat == 2'h1</a>
+<a name="1640"><span class="lineNum">    1640 </span>            :                ? 28'(s1_pc_dup_0[40:13] + 28'h1)</a>
+<a name="1641"><span class="lineNum">    1641 </span>            :                : 28'h0)</a>
+<a name="1642"><span class="lineNum">    1642 </span>            :               | (_ways_31_io_resp_brSlots_0_tarStat == 2'h2</a>
+<a name="1643"><span class="lineNum">    1643 </span>            :                    ? 28'(s1_pc_dup_0[40:13] - 28'h1)</a>
+<a name="1644"><span class="lineNum">    1644 </span>            :                    : 28'h0)</a>
+<a name="1645"><span class="lineNum">    1645 </span>            :               | (_ways_31_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0),</a>
+<a name="1646"><span class="lineNum">    1646 </span>            :             _ways_31_io_resp_brSlots_0_lower,</a>
+<a name="1647"><span class="lineNum">    1647 </span>            :             1'h0}</a>
+<a name="1648"><span class="lineNum">    1648 </span>            :          : 41'h0);</a>
+<a name="1649"><span class="lineNum">    1649 </span>            :   wire [40:0] _s1_hit_full_pred_T_850 = _GEN | _GEN_0;</a>
+<a name="1650"><span class="lineNum">    1650 </span>            :   wire [40:0] _GEN_1 =</a>
+<a name="1651"><span class="lineNum">    1651 </span>            :     (_ways_0_io_resp_hit</a>
+<a name="1652"><span class="lineNum">    1652 </span>            :        ? {_ways_0_io_resp_tailSlot_sharing</a>
+<a name="1653"><span class="lineNum">    1653 </span>            :             ? {(_target_T_18 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0)</a>
+<a name="1654"><span class="lineNum">    1654 </span>            :                  | (_target_T_19 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0)</a>
+<a name="1655"><span class="lineNum">    1655 </span>            :                  | (_target_T_20 ? s1_pc_dup_0[40:13] : 28'h0),</a>
+<a name="1656"><span class="lineNum">    1656 </span>            :                _ways_0_io_resp_tailSlot_lower[11:0]}</a>
+<a name="1657"><span class="lineNum">    1657 </span>            :             : {(_target_T_18 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0)</a>
+<a name="1658"><span class="lineNum">    1658 </span>            :                  | (_target_T_19 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0)</a>
+<a name="1659"><span class="lineNum">    1659 </span>            :                  | (_target_T_20 ? s1_pc_dup_0[40:21] : 20'h0),</a>
+<a name="1660"><span class="lineNum">    1660 </span>            :                _ways_0_io_resp_tailSlot_lower},</a>
+<a name="1661"><span class="lineNum">    1661 </span>            :           1'h0}</a>
+<a name="1662"><span class="lineNum">    1662 </span>            :        : 41'h0)</a>
+<a name="1663"><span class="lineNum">    1663 </span>            :     | (_ways_1_io_resp_hit</a>
+<a name="1664"><span class="lineNum">    1664 </span>            :          ? {_ways_1_io_resp_tailSlot_sharing</a>
+<a name="1665"><span class="lineNum">    1665 </span>            :               ? {(_target_T_45 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0)</a>
+<a name="1666"><span class="lineNum">    1666 </span>            :                    | (_target_T_46 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0)</a>
+<a name="1667"><span class="lineNum">    1667 </span>            :                    | (_target_T_47 ? s1_pc_dup_0[40:13] : 28'h0),</a>
+<a name="1668"><span class="lineNum">    1668 </span>            :                  _ways_1_io_resp_tailSlot_lower[11:0]}</a>
+<a name="1669"><span class="lineNum">    1669 </span>            :               : {(_target_T_45 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0)</a>
+<a name="1670"><span class="lineNum">    1670 </span>            :                    | (_target_T_46 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0)</a>
+<a name="1671"><span class="lineNum">    1671 </span>            :                    | (_target_T_47 ? s1_pc_dup_0[40:21] : 20'h0),</a>
+<a name="1672"><span class="lineNum">    1672 </span>            :                  _ways_1_io_resp_tailSlot_lower},</a>
+<a name="1673"><span class="lineNum">    1673 </span>            :             1'h0}</a>
+<a name="1674"><span class="lineNum">    1674 </span>            :          : 41'h0)</a>
+<a name="1675"><span class="lineNum">    1675 </span>            :     | (_ways_2_io_resp_hit</a>
+<a name="1676"><span class="lineNum">    1676 </span>            :          ? {_ways_2_io_resp_tailSlot_sharing</a>
+<a name="1677"><span class="lineNum">    1677 </span>            :               ? {(_target_T_72 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0)</a>
+<a name="1678"><span class="lineNum">    1678 </span>            :                    | (_target_T_73 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0)</a>
+<a name="1679"><span class="lineNum">    1679 </span>            :                    | (_target_T_74 ? s1_pc_dup_0[40:13] : 28'h0),</a>
+<a name="1680"><span class="lineNum">    1680 </span>            :                  _ways_2_io_resp_tailSlot_lower[11:0]}</a>
+<a name="1681"><span class="lineNum">    1681 </span>            :               : {(_target_T_72 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0)</a>
+<a name="1682"><span class="lineNum">    1682 </span>            :                    | (_target_T_73 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0)</a>
+<a name="1683"><span class="lineNum">    1683 </span>            :                    | (_target_T_74 ? s1_pc_dup_0[40:21] : 20'h0),</a>
+<a name="1684"><span class="lineNum">    1684 </span>            :                  _ways_2_io_resp_tailSlot_lower},</a>
+<a name="1685"><span class="lineNum">    1685 </span>            :             1'h0}</a>
+<a name="1686"><span class="lineNum">    1686 </span>            :          : 41'h0)</a>
+<a name="1687"><span class="lineNum">    1687 </span>            :     | (_ways_3_io_resp_hit</a>
+<a name="1688"><span class="lineNum">    1688 </span>            :          ? {_ways_3_io_resp_tailSlot_sharing</a>
+<a name="1689"><span class="lineNum">    1689 </span>            :               ? {(_target_T_99 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0)</a>
+<a name="1690"><span class="lineNum">    1690 </span>            :                    | (_target_T_100 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0)</a>
+<a name="1691"><span class="lineNum">    1691 </span>            :                    | (_target_T_101 ? s1_pc_dup_0[40:13] : 28'h0),</a>
+<a name="1692"><span class="lineNum">    1692 </span>            :                  _ways_3_io_resp_tailSlot_lower[11:0]}</a>
+<a name="1693"><span class="lineNum">    1693 </span>            :               : {(_target_T_99 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0)</a>
+<a name="1694"><span class="lineNum">    1694 </span>            :                    | (_target_T_100 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0)</a>
+<a name="1695"><span class="lineNum">    1695 </span>            :                    | (_target_T_101 ? s1_pc_dup_0[40:21] : 20'h0),</a>
+<a name="1696"><span class="lineNum">    1696 </span>            :                  _ways_3_io_resp_tailSlot_lower},</a>
+<a name="1697"><span class="lineNum">    1697 </span>            :             1'h0}</a>
+<a name="1698"><span class="lineNum">    1698 </span>            :          : 41'h0)</a>
+<a name="1699"><span class="lineNum">    1699 </span>            :     | (_ways_4_io_resp_hit</a>
+<a name="1700"><span class="lineNum">    1700 </span>            :          ? {_ways_4_io_resp_tailSlot_sharing</a>
+<a name="1701"><span class="lineNum">    1701 </span>            :               ? {(_target_T_126 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0)</a>
+<a name="1702"><span class="lineNum">    1702 </span>            :                    | (_target_T_127 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0)</a>
+<a name="1703"><span class="lineNum">    1703 </span>            :                    | (_target_T_128 ? s1_pc_dup_0[40:13] : 28'h0),</a>
+<a name="1704"><span class="lineNum">    1704 </span>            :                  _ways_4_io_resp_tailSlot_lower[11:0]}</a>
+<a name="1705"><span class="lineNum">    1705 </span>            :               : {(_target_T_126 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0)</a>
+<a name="1706"><span class="lineNum">    1706 </span>            :                    | (_target_T_127 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0)</a>
+<a name="1707"><span class="lineNum">    1707 </span>            :                    | (_target_T_128 ? s1_pc_dup_0[40:21] : 20'h0),</a>
+<a name="1708"><span class="lineNum">    1708 </span>            :                  _ways_4_io_resp_tailSlot_lower},</a>
+<a name="1709"><span class="lineNum">    1709 </span>            :             1'h0}</a>
+<a name="1710"><span class="lineNum">    1710 </span>            :          : 41'h0)</a>
+<a name="1711"><span class="lineNum">    1711 </span>            :     | (_ways_5_io_resp_hit</a>
+<a name="1712"><span class="lineNum">    1712 </span>            :          ? {_ways_5_io_resp_tailSlot_sharing</a>
+<a name="1713"><span class="lineNum">    1713 </span>            :               ? {(_target_T_153 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0)</a>
+<a name="1714"><span class="lineNum">    1714 </span>            :                    | (_target_T_154 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0)</a>
+<a name="1715"><span class="lineNum">    1715 </span>            :                    | (_target_T_155 ? s1_pc_dup_0[40:13] : 28'h0),</a>
+<a name="1716"><span class="lineNum">    1716 </span>            :                  _ways_5_io_resp_tailSlot_lower[11:0]}</a>
+<a name="1717"><span class="lineNum">    1717 </span>            :               : {(_target_T_153 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0)</a>
+<a name="1718"><span class="lineNum">    1718 </span>            :                    | (_target_T_154 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0)</a>
+<a name="1719"><span class="lineNum">    1719 </span>            :                    | (_target_T_155 ? s1_pc_dup_0[40:21] : 20'h0),</a>
+<a name="1720"><span class="lineNum">    1720 </span>            :                  _ways_5_io_resp_tailSlot_lower},</a>
+<a name="1721"><span class="lineNum">    1721 </span>            :             1'h0}</a>
+<a name="1722"><span class="lineNum">    1722 </span>            :          : 41'h0)</a>
+<a name="1723"><span class="lineNum">    1723 </span>            :     | (_ways_6_io_resp_hit</a>
+<a name="1724"><span class="lineNum">    1724 </span>            :          ? {_ways_6_io_resp_tailSlot_sharing</a>
+<a name="1725"><span class="lineNum">    1725 </span>            :               ? {(_target_T_180 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0)</a>
+<a name="1726"><span class="lineNum">    1726 </span>            :                    | (_target_T_181 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0)</a>
+<a name="1727"><span class="lineNum">    1727 </span>            :                    | (_target_T_182 ? s1_pc_dup_0[40:13] : 28'h0),</a>
+<a name="1728"><span class="lineNum">    1728 </span>            :                  _ways_6_io_resp_tailSlot_lower[11:0]}</a>
+<a name="1729"><span class="lineNum">    1729 </span>            :               : {(_target_T_180 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0)</a>
+<a name="1730"><span class="lineNum">    1730 </span>            :                    | (_target_T_181 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0)</a>
+<a name="1731"><span class="lineNum">    1731 </span>            :                    | (_target_T_182 ? s1_pc_dup_0[40:21] : 20'h0),</a>
+<a name="1732"><span class="lineNum">    1732 </span>            :                  _ways_6_io_resp_tailSlot_lower},</a>
+<a name="1733"><span class="lineNum">    1733 </span>            :             1'h0}</a>
+<a name="1734"><span class="lineNum">    1734 </span>            :          : 41'h0)</a>
+<a name="1735"><span class="lineNum">    1735 </span>            :     | (_ways_7_io_resp_hit</a>
+<a name="1736"><span class="lineNum">    1736 </span>            :          ? {_ways_7_io_resp_tailSlot_sharing</a>
+<a name="1737"><span class="lineNum">    1737 </span>            :               ? {(_target_T_207 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0)</a>
+<a name="1738"><span class="lineNum">    1738 </span>            :                    | (_target_T_208 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0)</a>
+<a name="1739"><span class="lineNum">    1739 </span>            :                    | (_target_T_209 ? s1_pc_dup_0[40:13] : 28'h0),</a>
+<a name="1740"><span class="lineNum">    1740 </span>            :                  _ways_7_io_resp_tailSlot_lower[11:0]}</a>
+<a name="1741"><span class="lineNum">    1741 </span>            :               : {(_target_T_207 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0)</a>
+<a name="1742"><span class="lineNum">    1742 </span>            :                    | (_target_T_208 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0)</a>
+<a name="1743"><span class="lineNum">    1743 </span>            :                    | (_target_T_209 ? s1_pc_dup_0[40:21] : 20'h0),</a>
+<a name="1744"><span class="lineNum">    1744 </span>            :                  _ways_7_io_resp_tailSlot_lower},</a>
+<a name="1745"><span class="lineNum">    1745 </span>            :             1'h0}</a>
+<a name="1746"><span class="lineNum">    1746 </span>            :          : 41'h0)</a>
+<a name="1747"><span class="lineNum">    1747 </span>            :     | (_ways_8_io_resp_hit</a>
+<a name="1748"><span class="lineNum">    1748 </span>            :          ? {_ways_8_io_resp_tailSlot_sharing</a>
+<a name="1749"><span class="lineNum">    1749 </span>            :               ? {(_target_T_234 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0)</a>
+<a name="1750"><span class="lineNum">    1750 </span>            :                    | (_target_T_235 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0)</a>
+<a name="1751"><span class="lineNum">    1751 </span>            :                    | (_target_T_236 ? s1_pc_dup_0[40:13] : 28'h0),</a>
+<a name="1752"><span class="lineNum">    1752 </span>            :                  _ways_8_io_resp_tailSlot_lower[11:0]}</a>
+<a name="1753"><span class="lineNum">    1753 </span>            :               : {(_target_T_234 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0)</a>
+<a name="1754"><span class="lineNum">    1754 </span>            :                    | (_target_T_235 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0)</a>
+<a name="1755"><span class="lineNum">    1755 </span>            :                    | (_target_T_236 ? s1_pc_dup_0[40:21] : 20'h0),</a>
+<a name="1756"><span class="lineNum">    1756 </span>            :                  _ways_8_io_resp_tailSlot_lower},</a>
+<a name="1757"><span class="lineNum">    1757 </span>            :             1'h0}</a>
+<a name="1758"><span class="lineNum">    1758 </span>            :          : 41'h0)</a>
+<a name="1759"><span class="lineNum">    1759 </span>            :     | (_ways_9_io_resp_hit</a>
+<a name="1760"><span class="lineNum">    1760 </span>            :          ? {_ways_9_io_resp_tailSlot_sharing</a>
+<a name="1761"><span class="lineNum">    1761 </span>            :               ? {(_target_T_261 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0)</a>
+<a name="1762"><span class="lineNum">    1762 </span>            :                    | (_target_T_262 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0)</a>
+<a name="1763"><span class="lineNum">    1763 </span>            :                    | (_target_T_263 ? s1_pc_dup_0[40:13] : 28'h0),</a>
+<a name="1764"><span class="lineNum">    1764 </span>            :                  _ways_9_io_resp_tailSlot_lower[11:0]}</a>
+<a name="1765"><span class="lineNum">    1765 </span>            :               : {(_target_T_261 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0)</a>
+<a name="1766"><span class="lineNum">    1766 </span>            :                    | (_target_T_262 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0)</a>
+<a name="1767"><span class="lineNum">    1767 </span>            :                    | (_target_T_263 ? s1_pc_dup_0[40:21] : 20'h0),</a>
+<a name="1768"><span class="lineNum">    1768 </span>            :                  _ways_9_io_resp_tailSlot_lower},</a>
+<a name="1769"><span class="lineNum">    1769 </span>            :             1'h0}</a>
+<a name="1770"><span class="lineNum">    1770 </span>            :          : 41'h0)</a>
+<a name="1771"><span class="lineNum">    1771 </span>            :     | (_ways_10_io_resp_hit</a>
+<a name="1772"><span class="lineNum">    1772 </span>            :          ? {_ways_10_io_resp_tailSlot_sharing</a>
+<a name="1773"><span class="lineNum">    1773 </span>            :               ? {(_target_T_288 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0)</a>
+<a name="1774"><span class="lineNum">    1774 </span>            :                    | (_target_T_289 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0)</a>
+<a name="1775"><span class="lineNum">    1775 </span>            :                    | (_target_T_290 ? s1_pc_dup_0[40:13] : 28'h0),</a>
+<a name="1776"><span class="lineNum">    1776 </span>            :                  _ways_10_io_resp_tailSlot_lower[11:0]}</a>
+<a name="1777"><span class="lineNum">    1777 </span>            :               : {(_target_T_288 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0)</a>
+<a name="1778"><span class="lineNum">    1778 </span>            :                    | (_target_T_289 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0)</a>
+<a name="1779"><span class="lineNum">    1779 </span>            :                    | (_target_T_290 ? s1_pc_dup_0[40:21] : 20'h0),</a>
+<a name="1780"><span class="lineNum">    1780 </span>            :                  _ways_10_io_resp_tailSlot_lower},</a>
+<a name="1781"><span class="lineNum">    1781 </span>            :             1'h0}</a>
+<a name="1782"><span class="lineNum">    1782 </span>            :          : 41'h0)</a>
+<a name="1783"><span class="lineNum">    1783 </span>            :     | (_ways_11_io_resp_hit</a>
+<a name="1784"><span class="lineNum">    1784 </span>            :          ? {_ways_11_io_resp_tailSlot_sharing</a>
+<a name="1785"><span class="lineNum">    1785 </span>            :               ? {(_target_T_315 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0)</a>
+<a name="1786"><span class="lineNum">    1786 </span>            :                    | (_target_T_316 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0)</a>
+<a name="1787"><span class="lineNum">    1787 </span>            :                    | (_target_T_317 ? s1_pc_dup_0[40:13] : 28'h0),</a>
+<a name="1788"><span class="lineNum">    1788 </span>            :                  _ways_11_io_resp_tailSlot_lower[11:0]}</a>
+<a name="1789"><span class="lineNum">    1789 </span>            :               : {(_target_T_315 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0)</a>
+<a name="1790"><span class="lineNum">    1790 </span>            :                    | (_target_T_316 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0)</a>
+<a name="1791"><span class="lineNum">    1791 </span>            :                    | (_target_T_317 ? s1_pc_dup_0[40:21] : 20'h0),</a>
+<a name="1792"><span class="lineNum">    1792 </span>            :                  _ways_11_io_resp_tailSlot_lower},</a>
+<a name="1793"><span class="lineNum">    1793 </span>            :             1'h0}</a>
+<a name="1794"><span class="lineNum">    1794 </span>            :          : 41'h0)</a>
+<a name="1795"><span class="lineNum">    1795 </span>            :     | (_ways_12_io_resp_hit</a>
+<a name="1796"><span class="lineNum">    1796 </span>            :          ? {_ways_12_io_resp_tailSlot_sharing</a>
+<a name="1797"><span class="lineNum">    1797 </span>            :               ? {(_target_T_342 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0)</a>
+<a name="1798"><span class="lineNum">    1798 </span>            :                    | (_target_T_343 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0)</a>
+<a name="1799"><span class="lineNum">    1799 </span>            :                    | (_target_T_344 ? s1_pc_dup_0[40:13] : 28'h0),</a>
+<a name="1800"><span class="lineNum">    1800 </span>            :                  _ways_12_io_resp_tailSlot_lower[11:0]}</a>
+<a name="1801"><span class="lineNum">    1801 </span>            :               : {(_target_T_342 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0)</a>
+<a name="1802"><span class="lineNum">    1802 </span>            :                    | (_target_T_343 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0)</a>
+<a name="1803"><span class="lineNum">    1803 </span>            :                    | (_target_T_344 ? s1_pc_dup_0[40:21] : 20'h0),</a>
+<a name="1804"><span class="lineNum">    1804 </span>            :                  _ways_12_io_resp_tailSlot_lower},</a>
+<a name="1805"><span class="lineNum">    1805 </span>            :             1'h0}</a>
+<a name="1806"><span class="lineNum">    1806 </span>            :          : 41'h0)</a>
+<a name="1807"><span class="lineNum">    1807 </span>            :     | (_ways_13_io_resp_hit</a>
+<a name="1808"><span class="lineNum">    1808 </span>            :          ? {_ways_13_io_resp_tailSlot_sharing</a>
+<a name="1809"><span class="lineNum">    1809 </span>            :               ? {(_target_T_369 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0)</a>
+<a name="1810"><span class="lineNum">    1810 </span>            :                    | (_target_T_370 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0)</a>
+<a name="1811"><span class="lineNum">    1811 </span>            :                    | (_target_T_371 ? s1_pc_dup_0[40:13] : 28'h0),</a>
+<a name="1812"><span class="lineNum">    1812 </span>            :                  _ways_13_io_resp_tailSlot_lower[11:0]}</a>
+<a name="1813"><span class="lineNum">    1813 </span>            :               : {(_target_T_369 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0)</a>
+<a name="1814"><span class="lineNum">    1814 </span>            :                    | (_target_T_370 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0)</a>
+<a name="1815"><span class="lineNum">    1815 </span>            :                    | (_target_T_371 ? s1_pc_dup_0[40:21] : 20'h0),</a>
+<a name="1816"><span class="lineNum">    1816 </span>            :                  _ways_13_io_resp_tailSlot_lower},</a>
+<a name="1817"><span class="lineNum">    1817 </span>            :             1'h0}</a>
+<a name="1818"><span class="lineNum">    1818 </span>            :          : 41'h0)</a>
+<a name="1819"><span class="lineNum">    1819 </span>            :     | (_ways_14_io_resp_hit</a>
+<a name="1820"><span class="lineNum">    1820 </span>            :          ? {_ways_14_io_resp_tailSlot_sharing</a>
+<a name="1821"><span class="lineNum">    1821 </span>            :               ? {(_target_T_396 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0)</a>
+<a name="1822"><span class="lineNum">    1822 </span>            :                    | (_target_T_397 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0)</a>
+<a name="1823"><span class="lineNum">    1823 </span>            :                    | (_target_T_398 ? s1_pc_dup_0[40:13] : 28'h0),</a>
+<a name="1824"><span class="lineNum">    1824 </span>            :                  _ways_14_io_resp_tailSlot_lower[11:0]}</a>
+<a name="1825"><span class="lineNum">    1825 </span>            :               : {(_target_T_396 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0)</a>
+<a name="1826"><span class="lineNum">    1826 </span>            :                    | (_target_T_397 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0)</a>
+<a name="1827"><span class="lineNum">    1827 </span>            :                    | (_target_T_398 ? s1_pc_dup_0[40:21] : 20'h0),</a>
+<a name="1828"><span class="lineNum">    1828 </span>            :                  _ways_14_io_resp_tailSlot_lower},</a>
+<a name="1829"><span class="lineNum">    1829 </span>            :             1'h0}</a>
+<a name="1830"><span class="lineNum">    1830 </span>            :          : 41'h0)</a>
+<a name="1831"><span class="lineNum">    1831 </span>            :     | (_ways_15_io_resp_hit</a>
+<a name="1832"><span class="lineNum">    1832 </span>            :          ? {_ways_15_io_resp_tailSlot_sharing</a>
+<a name="1833"><span class="lineNum">    1833 </span>            :               ? {(_target_T_423 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0)</a>
+<a name="1834"><span class="lineNum">    1834 </span>            :                    | (_target_T_424 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0)</a>
+<a name="1835"><span class="lineNum">    1835 </span>            :                    | (_target_T_425 ? s1_pc_dup_0[40:13] : 28'h0),</a>
+<a name="1836"><span class="lineNum">    1836 </span>            :                  _ways_15_io_resp_tailSlot_lower[11:0]}</a>
+<a name="1837"><span class="lineNum">    1837 </span>            :               : {(_target_T_423 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0)</a>
+<a name="1838"><span class="lineNum">    1838 </span>            :                    | (_target_T_424 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0)</a>
+<a name="1839"><span class="lineNum">    1839 </span>            :                    | (_target_T_425 ? s1_pc_dup_0[40:21] : 20'h0),</a>
+<a name="1840"><span class="lineNum">    1840 </span>            :                  _ways_15_io_resp_tailSlot_lower},</a>
+<a name="1841"><span class="lineNum">    1841 </span>            :             1'h0}</a>
+<a name="1842"><span class="lineNum">    1842 </span>            :          : 41'h0);</a>
+<a name="1843"><span class="lineNum">    1843 </span>            :   wire [40:0] _GEN_2 =</a>
+<a name="1844"><span class="lineNum">    1844 </span>            :     (_ways_16_io_resp_hit</a>
+<a name="1845"><span class="lineNum">    1845 </span>            :        ? {_ways_16_io_resp_tailSlot_sharing</a>
+<a name="1846"><span class="lineNum">    1846 </span>            :             ? {(_target_T_450 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0)</a>
+<a name="1847"><span class="lineNum">    1847 </span>            :                  | (_target_T_451 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0)</a>
+<a name="1848"><span class="lineNum">    1848 </span>            :                  | (_target_T_452 ? s1_pc_dup_0[40:13] : 28'h0),</a>
+<a name="1849"><span class="lineNum">    1849 </span>            :                _ways_16_io_resp_tailSlot_lower[11:0]}</a>
+<a name="1850"><span class="lineNum">    1850 </span>            :             : {(_target_T_450 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0)</a>
+<a name="1851"><span class="lineNum">    1851 </span>            :                  | (_target_T_451 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0)</a>
+<a name="1852"><span class="lineNum">    1852 </span>            :                  | (_target_T_452 ? s1_pc_dup_0[40:21] : 20'h0),</a>
+<a name="1853"><span class="lineNum">    1853 </span>            :                _ways_16_io_resp_tailSlot_lower},</a>
+<a name="1854"><span class="lineNum">    1854 </span>            :           1'h0}</a>
+<a name="1855"><span class="lineNum">    1855 </span>            :        : 41'h0)</a>
+<a name="1856"><span class="lineNum">    1856 </span>            :     | (_ways_17_io_resp_hit</a>
+<a name="1857"><span class="lineNum">    1857 </span>            :          ? {_ways_17_io_resp_tailSlot_sharing</a>
+<a name="1858"><span class="lineNum">    1858 </span>            :               ? {(_target_T_477 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0)</a>
+<a name="1859"><span class="lineNum">    1859 </span>            :                    | (_target_T_478 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0)</a>
+<a name="1860"><span class="lineNum">    1860 </span>            :                    | (_target_T_479 ? s1_pc_dup_0[40:13] : 28'h0),</a>
+<a name="1861"><span class="lineNum">    1861 </span>            :                  _ways_17_io_resp_tailSlot_lower[11:0]}</a>
+<a name="1862"><span class="lineNum">    1862 </span>            :               : {(_target_T_477 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0)</a>
+<a name="1863"><span class="lineNum">    1863 </span>            :                    | (_target_T_478 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0)</a>
+<a name="1864"><span class="lineNum">    1864 </span>            :                    | (_target_T_479 ? s1_pc_dup_0[40:21] : 20'h0),</a>
+<a name="1865"><span class="lineNum">    1865 </span>            :                  _ways_17_io_resp_tailSlot_lower},</a>
+<a name="1866"><span class="lineNum">    1866 </span>            :             1'h0}</a>
+<a name="1867"><span class="lineNum">    1867 </span>            :          : 41'h0)</a>
+<a name="1868"><span class="lineNum">    1868 </span>            :     | (_ways_18_io_resp_hit</a>
+<a name="1869"><span class="lineNum">    1869 </span>            :          ? {_ways_18_io_resp_tailSlot_sharing</a>
+<a name="1870"><span class="lineNum">    1870 </span>            :               ? {(_target_T_504 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0)</a>
+<a name="1871"><span class="lineNum">    1871 </span>            :                    | (_target_T_505 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0)</a>
+<a name="1872"><span class="lineNum">    1872 </span>            :                    | (_target_T_506 ? s1_pc_dup_0[40:13] : 28'h0),</a>
+<a name="1873"><span class="lineNum">    1873 </span>            :                  _ways_18_io_resp_tailSlot_lower[11:0]}</a>
+<a name="1874"><span class="lineNum">    1874 </span>            :               : {(_target_T_504 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0)</a>
+<a name="1875"><span class="lineNum">    1875 </span>            :                    | (_target_T_505 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0)</a>
+<a name="1876"><span class="lineNum">    1876 </span>            :                    | (_target_T_506 ? s1_pc_dup_0[40:21] : 20'h0),</a>
+<a name="1877"><span class="lineNum">    1877 </span>            :                  _ways_18_io_resp_tailSlot_lower},</a>
+<a name="1878"><span class="lineNum">    1878 </span>            :             1'h0}</a>
+<a name="1879"><span class="lineNum">    1879 </span>            :          : 41'h0)</a>
+<a name="1880"><span class="lineNum">    1880 </span>            :     | (_ways_19_io_resp_hit</a>
+<a name="1881"><span class="lineNum">    1881 </span>            :          ? {_ways_19_io_resp_tailSlot_sharing</a>
+<a name="1882"><span class="lineNum">    1882 </span>            :               ? {(_target_T_531 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0)</a>
+<a name="1883"><span class="lineNum">    1883 </span>            :                    | (_target_T_532 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0)</a>
+<a name="1884"><span class="lineNum">    1884 </span>            :                    | (_target_T_533 ? s1_pc_dup_0[40:13] : 28'h0),</a>
+<a name="1885"><span class="lineNum">    1885 </span>            :                  _ways_19_io_resp_tailSlot_lower[11:0]}</a>
+<a name="1886"><span class="lineNum">    1886 </span>            :               : {(_target_T_531 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0)</a>
+<a name="1887"><span class="lineNum">    1887 </span>            :                    | (_target_T_532 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0)</a>
+<a name="1888"><span class="lineNum">    1888 </span>            :                    | (_target_T_533 ? s1_pc_dup_0[40:21] : 20'h0),</a>
+<a name="1889"><span class="lineNum">    1889 </span>            :                  _ways_19_io_resp_tailSlot_lower},</a>
+<a name="1890"><span class="lineNum">    1890 </span>            :             1'h0}</a>
+<a name="1891"><span class="lineNum">    1891 </span>            :          : 41'h0)</a>
+<a name="1892"><span class="lineNum">    1892 </span>            :     | (_ways_20_io_resp_hit</a>
+<a name="1893"><span class="lineNum">    1893 </span>            :          ? {_ways_20_io_resp_tailSlot_sharing</a>
+<a name="1894"><span class="lineNum">    1894 </span>            :               ? {(_target_T_558 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0)</a>
+<a name="1895"><span class="lineNum">    1895 </span>            :                    | (_target_T_559 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0)</a>
+<a name="1896"><span class="lineNum">    1896 </span>            :                    | (_target_T_560 ? s1_pc_dup_0[40:13] : 28'h0),</a>
+<a name="1897"><span class="lineNum">    1897 </span>            :                  _ways_20_io_resp_tailSlot_lower[11:0]}</a>
+<a name="1898"><span class="lineNum">    1898 </span>            :               : {(_target_T_558 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0)</a>
+<a name="1899"><span class="lineNum">    1899 </span>            :                    | (_target_T_559 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0)</a>
+<a name="1900"><span class="lineNum">    1900 </span>            :                    | (_target_T_560 ? s1_pc_dup_0[40:21] : 20'h0),</a>
+<a name="1901"><span class="lineNum">    1901 </span>            :                  _ways_20_io_resp_tailSlot_lower},</a>
+<a name="1902"><span class="lineNum">    1902 </span>            :             1'h0}</a>
+<a name="1903"><span class="lineNum">    1903 </span>            :          : 41'h0)</a>
+<a name="1904"><span class="lineNum">    1904 </span>            :     | (_ways_21_io_resp_hit</a>
+<a name="1905"><span class="lineNum">    1905 </span>            :          ? {_ways_21_io_resp_tailSlot_sharing</a>
+<a name="1906"><span class="lineNum">    1906 </span>            :               ? {(_target_T_585 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0)</a>
+<a name="1907"><span class="lineNum">    1907 </span>            :                    | (_target_T_586 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0)</a>
+<a name="1908"><span class="lineNum">    1908 </span>            :                    | (_target_T_587 ? s1_pc_dup_0[40:13] : 28'h0),</a>
+<a name="1909"><span class="lineNum">    1909 </span>            :                  _ways_21_io_resp_tailSlot_lower[11:0]}</a>
+<a name="1910"><span class="lineNum">    1910 </span>            :               : {(_target_T_585 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0)</a>
+<a name="1911"><span class="lineNum">    1911 </span>            :                    | (_target_T_586 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0)</a>
+<a name="1912"><span class="lineNum">    1912 </span>            :                    | (_target_T_587 ? s1_pc_dup_0[40:21] : 20'h0),</a>
+<a name="1913"><span class="lineNum">    1913 </span>            :                  _ways_21_io_resp_tailSlot_lower},</a>
+<a name="1914"><span class="lineNum">    1914 </span>            :             1'h0}</a>
+<a name="1915"><span class="lineNum">    1915 </span>            :          : 41'h0)</a>
+<a name="1916"><span class="lineNum">    1916 </span>            :     | (_ways_22_io_resp_hit</a>
+<a name="1917"><span class="lineNum">    1917 </span>            :          ? {_ways_22_io_resp_tailSlot_sharing</a>
+<a name="1918"><span class="lineNum">    1918 </span>            :               ? {(_target_T_612 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0)</a>
+<a name="1919"><span class="lineNum">    1919 </span>            :                    | (_target_T_613 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0)</a>
+<a name="1920"><span class="lineNum">    1920 </span>            :                    | (_target_T_614 ? s1_pc_dup_0[40:13] : 28'h0),</a>
+<a name="1921"><span class="lineNum">    1921 </span>            :                  _ways_22_io_resp_tailSlot_lower[11:0]}</a>
+<a name="1922"><span class="lineNum">    1922 </span>            :               : {(_target_T_612 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0)</a>
+<a name="1923"><span class="lineNum">    1923 </span>            :                    | (_target_T_613 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0)</a>
+<a name="1924"><span class="lineNum">    1924 </span>            :                    | (_target_T_614 ? s1_pc_dup_0[40:21] : 20'h0),</a>
+<a name="1925"><span class="lineNum">    1925 </span>            :                  _ways_22_io_resp_tailSlot_lower},</a>
+<a name="1926"><span class="lineNum">    1926 </span>            :             1'h0}</a>
+<a name="1927"><span class="lineNum">    1927 </span>            :          : 41'h0)</a>
+<a name="1928"><span class="lineNum">    1928 </span>            :     | (_ways_23_io_resp_hit</a>
+<a name="1929"><span class="lineNum">    1929 </span>            :          ? {_ways_23_io_resp_tailSlot_sharing</a>
+<a name="1930"><span class="lineNum">    1930 </span>            :               ? {(_target_T_639 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0)</a>
+<a name="1931"><span class="lineNum">    1931 </span>            :                    | (_target_T_640 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0)</a>
+<a name="1932"><span class="lineNum">    1932 </span>            :                    | (_target_T_641 ? s1_pc_dup_0[40:13] : 28'h0),</a>
+<a name="1933"><span class="lineNum">    1933 </span>            :                  _ways_23_io_resp_tailSlot_lower[11:0]}</a>
+<a name="1934"><span class="lineNum">    1934 </span>            :               : {(_target_T_639 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0)</a>
+<a name="1935"><span class="lineNum">    1935 </span>            :                    | (_target_T_640 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0)</a>
+<a name="1936"><span class="lineNum">    1936 </span>            :                    | (_target_T_641 ? s1_pc_dup_0[40:21] : 20'h0),</a>
+<a name="1937"><span class="lineNum">    1937 </span>            :                  _ways_23_io_resp_tailSlot_lower},</a>
+<a name="1938"><span class="lineNum">    1938 </span>            :             1'h0}</a>
+<a name="1939"><span class="lineNum">    1939 </span>            :          : 41'h0)</a>
+<a name="1940"><span class="lineNum">    1940 </span>            :     | (_ways_24_io_resp_hit</a>
+<a name="1941"><span class="lineNum">    1941 </span>            :          ? {_ways_24_io_resp_tailSlot_sharing</a>
+<a name="1942"><span class="lineNum">    1942 </span>            :               ? {(_target_T_666 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0)</a>
+<a name="1943"><span class="lineNum">    1943 </span>            :                    | (_target_T_667 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0)</a>
+<a name="1944"><span class="lineNum">    1944 </span>            :                    | (_target_T_668 ? s1_pc_dup_0[40:13] : 28'h0),</a>
+<a name="1945"><span class="lineNum">    1945 </span>            :                  _ways_24_io_resp_tailSlot_lower[11:0]}</a>
+<a name="1946"><span class="lineNum">    1946 </span>            :               : {(_target_T_666 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0)</a>
+<a name="1947"><span class="lineNum">    1947 </span>            :                    | (_target_T_667 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0)</a>
+<a name="1948"><span class="lineNum">    1948 </span>            :                    | (_target_T_668 ? s1_pc_dup_0[40:21] : 20'h0),</a>
+<a name="1949"><span class="lineNum">    1949 </span>            :                  _ways_24_io_resp_tailSlot_lower},</a>
+<a name="1950"><span class="lineNum">    1950 </span>            :             1'h0}</a>
+<a name="1951"><span class="lineNum">    1951 </span>            :          : 41'h0)</a>
+<a name="1952"><span class="lineNum">    1952 </span>            :     | (_ways_25_io_resp_hit</a>
+<a name="1953"><span class="lineNum">    1953 </span>            :          ? {_ways_25_io_resp_tailSlot_sharing</a>
+<a name="1954"><span class="lineNum">    1954 </span>            :               ? {(_target_T_693 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0)</a>
+<a name="1955"><span class="lineNum">    1955 </span>            :                    | (_target_T_694 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0)</a>
+<a name="1956"><span class="lineNum">    1956 </span>            :                    | (_target_T_695 ? s1_pc_dup_0[40:13] : 28'h0),</a>
+<a name="1957"><span class="lineNum">    1957 </span>            :                  _ways_25_io_resp_tailSlot_lower[11:0]}</a>
+<a name="1958"><span class="lineNum">    1958 </span>            :               : {(_target_T_693 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0)</a>
+<a name="1959"><span class="lineNum">    1959 </span>            :                    | (_target_T_694 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0)</a>
+<a name="1960"><span class="lineNum">    1960 </span>            :                    | (_target_T_695 ? s1_pc_dup_0[40:21] : 20'h0),</a>
+<a name="1961"><span class="lineNum">    1961 </span>            :                  _ways_25_io_resp_tailSlot_lower},</a>
+<a name="1962"><span class="lineNum">    1962 </span>            :             1'h0}</a>
+<a name="1963"><span class="lineNum">    1963 </span>            :          : 41'h0)</a>
+<a name="1964"><span class="lineNum">    1964 </span>            :     | (_ways_26_io_resp_hit</a>
+<a name="1965"><span class="lineNum">    1965 </span>            :          ? {_ways_26_io_resp_tailSlot_sharing</a>
+<a name="1966"><span class="lineNum">    1966 </span>            :               ? {(_target_T_720 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0)</a>
+<a name="1967"><span class="lineNum">    1967 </span>            :                    | (_target_T_721 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0)</a>
+<a name="1968"><span class="lineNum">    1968 </span>            :                    | (_target_T_722 ? s1_pc_dup_0[40:13] : 28'h0),</a>
+<a name="1969"><span class="lineNum">    1969 </span>            :                  _ways_26_io_resp_tailSlot_lower[11:0]}</a>
+<a name="1970"><span class="lineNum">    1970 </span>            :               : {(_target_T_720 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0)</a>
+<a name="1971"><span class="lineNum">    1971 </span>            :                    | (_target_T_721 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0)</a>
+<a name="1972"><span class="lineNum">    1972 </span>            :                    | (_target_T_722 ? s1_pc_dup_0[40:21] : 20'h0),</a>
+<a name="1973"><span class="lineNum">    1973 </span>            :                  _ways_26_io_resp_tailSlot_lower},</a>
+<a name="1974"><span class="lineNum">    1974 </span>            :             1'h0}</a>
+<a name="1975"><span class="lineNum">    1975 </span>            :          : 41'h0)</a>
+<a name="1976"><span class="lineNum">    1976 </span>            :     | (_ways_27_io_resp_hit</a>
+<a name="1977"><span class="lineNum">    1977 </span>            :          ? {_ways_27_io_resp_tailSlot_sharing</a>
+<a name="1978"><span class="lineNum">    1978 </span>            :               ? {(_target_T_747 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0)</a>
+<a name="1979"><span class="lineNum">    1979 </span>            :                    | (_target_T_748 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0)</a>
+<a name="1980"><span class="lineNum">    1980 </span>            :                    | (_target_T_749 ? s1_pc_dup_0[40:13] : 28'h0),</a>
+<a name="1981"><span class="lineNum">    1981 </span>            :                  _ways_27_io_resp_tailSlot_lower[11:0]}</a>
+<a name="1982"><span class="lineNum">    1982 </span>            :               : {(_target_T_747 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0)</a>
+<a name="1983"><span class="lineNum">    1983 </span>            :                    | (_target_T_748 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0)</a>
+<a name="1984"><span class="lineNum">    1984 </span>            :                    | (_target_T_749 ? s1_pc_dup_0[40:21] : 20'h0),</a>
+<a name="1985"><span class="lineNum">    1985 </span>            :                  _ways_27_io_resp_tailSlot_lower},</a>
+<a name="1986"><span class="lineNum">    1986 </span>            :             1'h0}</a>
+<a name="1987"><span class="lineNum">    1987 </span>            :          : 41'h0)</a>
+<a name="1988"><span class="lineNum">    1988 </span>            :     | (_ways_28_io_resp_hit</a>
+<a name="1989"><span class="lineNum">    1989 </span>            :          ? {_ways_28_io_resp_tailSlot_sharing</a>
+<a name="1990"><span class="lineNum">    1990 </span>            :               ? {(_target_T_774 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0)</a>
+<a name="1991"><span class="lineNum">    1991 </span>            :                    | (_target_T_775 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0)</a>
+<a name="1992"><span class="lineNum">    1992 </span>            :                    | (_target_T_776 ? s1_pc_dup_0[40:13] : 28'h0),</a>
+<a name="1993"><span class="lineNum">    1993 </span>            :                  _ways_28_io_resp_tailSlot_lower[11:0]}</a>
+<a name="1994"><span class="lineNum">    1994 </span>            :               : {(_target_T_774 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0)</a>
+<a name="1995"><span class="lineNum">    1995 </span>            :                    | (_target_T_775 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0)</a>
+<a name="1996"><span class="lineNum">    1996 </span>            :                    | (_target_T_776 ? s1_pc_dup_0[40:21] : 20'h0),</a>
+<a name="1997"><span class="lineNum">    1997 </span>            :                  _ways_28_io_resp_tailSlot_lower},</a>
+<a name="1998"><span class="lineNum">    1998 </span>            :             1'h0}</a>
+<a name="1999"><span class="lineNum">    1999 </span>            :          : 41'h0)</a>
+<a name="2000"><span class="lineNum">    2000 </span>            :     | (_ways_29_io_resp_hit</a>
+<a name="2001"><span class="lineNum">    2001 </span>            :          ? {_ways_29_io_resp_tailSlot_sharing</a>
+<a name="2002"><span class="lineNum">    2002 </span>            :               ? {(_target_T_801 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0)</a>
+<a name="2003"><span class="lineNum">    2003 </span>            :                    | (_target_T_802 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0)</a>
+<a name="2004"><span class="lineNum">    2004 </span>            :                    | (_target_T_803 ? s1_pc_dup_0[40:13] : 28'h0),</a>
+<a name="2005"><span class="lineNum">    2005 </span>            :                  _ways_29_io_resp_tailSlot_lower[11:0]}</a>
+<a name="2006"><span class="lineNum">    2006 </span>            :               : {(_target_T_801 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0)</a>
+<a name="2007"><span class="lineNum">    2007 </span>            :                    | (_target_T_802 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0)</a>
+<a name="2008"><span class="lineNum">    2008 </span>            :                    | (_target_T_803 ? s1_pc_dup_0[40:21] : 20'h0),</a>
+<a name="2009"><span class="lineNum">    2009 </span>            :                  _ways_29_io_resp_tailSlot_lower},</a>
+<a name="2010"><span class="lineNum">    2010 </span>            :             1'h0}</a>
+<a name="2011"><span class="lineNum">    2011 </span>            :          : 41'h0)</a>
+<a name="2012"><span class="lineNum">    2012 </span>            :     | (_ways_30_io_resp_hit</a>
+<a name="2013"><span class="lineNum">    2013 </span>            :          ? {_ways_30_io_resp_tailSlot_sharing</a>
+<a name="2014"><span class="lineNum">    2014 </span>            :               ? {(_target_T_828 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0)</a>
+<a name="2015"><span class="lineNum">    2015 </span>            :                    | (_target_T_829 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0)</a>
+<a name="2016"><span class="lineNum">    2016 </span>            :                    | (_target_T_830 ? s1_pc_dup_0[40:13] : 28'h0),</a>
+<a name="2017"><span class="lineNum">    2017 </span>            :                  _ways_30_io_resp_tailSlot_lower[11:0]}</a>
+<a name="2018"><span class="lineNum">    2018 </span>            :               : {(_target_T_828 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0)</a>
+<a name="2019"><span class="lineNum">    2019 </span>            :                    | (_target_T_829 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0)</a>
+<a name="2020"><span class="lineNum">    2020 </span>            :                    | (_target_T_830 ? s1_pc_dup_0[40:21] : 20'h0),</a>
+<a name="2021"><span class="lineNum">    2021 </span>            :                  _ways_30_io_resp_tailSlot_lower},</a>
+<a name="2022"><span class="lineNum">    2022 </span>            :             1'h0}</a>
+<a name="2023"><span class="lineNum">    2023 </span>            :          : 41'h0)</a>
+<a name="2024"><span class="lineNum">    2024 </span>            :     | (_ways_31_io_resp_hit</a>
+<a name="2025"><span class="lineNum">    2025 </span>            :          ? {_ways_31_io_resp_tailSlot_sharing</a>
+<a name="2026"><span class="lineNum">    2026 </span>            :               ? {(_target_T_855 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0)</a>
+<a name="2027"><span class="lineNum">    2027 </span>            :                    | (_target_T_856 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0)</a>
+<a name="2028"><span class="lineNum">    2028 </span>            :                    | (_target_T_857 ? s1_pc_dup_0[40:13] : 28'h0),</a>
+<a name="2029"><span class="lineNum">    2029 </span>            :                  _ways_31_io_resp_tailSlot_lower[11:0]}</a>
+<a name="2030"><span class="lineNum">    2030 </span>            :               : {(_target_T_855 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0)</a>
+<a name="2031"><span class="lineNum">    2031 </span>            :                    | (_target_T_856 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0)</a>
+<a name="2032"><span class="lineNum">    2032 </span>            :                    | (_target_T_857 ? s1_pc_dup_0[40:21] : 20'h0),</a>
+<a name="2033"><span class="lineNum">    2033 </span>            :                  _ways_31_io_resp_tailSlot_lower},</a>
+<a name="2034"><span class="lineNum">    2034 </span>            :             1'h0}</a>
+<a name="2035"><span class="lineNum">    2035 </span>            :          : 41'h0);</a>
+<a name="2036"><span class="lineNum">    2036 </span>            :   wire [40:0] _s1_hit_full_pred_T_913 = _GEN_1 | _GEN_2;</a>
+<a name="2037"><span class="lineNum">    2037 </span>            :   wire        _s1_hit_full_pred_T_976 =</a>
+<a name="2038"><span class="lineNum">    2038 </span>            :     _ways_0_io_resp_hit &amp; _ways_0_io_resp_brSlots_0_valid | _ways_1_io_resp_hit</a>
+<a name="2039"><span class="lineNum">    2039 </span>            :     &amp; _ways_1_io_resp_brSlots_0_valid | _ways_2_io_resp_hit</a>
+<a name="2040"><span class="lineNum">    2040 </span>            :     &amp; _ways_2_io_resp_brSlots_0_valid | _ways_3_io_resp_hit</a>
+<a name="2041"><span class="lineNum">    2041 </span>            :     &amp; _ways_3_io_resp_brSlots_0_valid | _ways_4_io_resp_hit</a>
+<a name="2042"><span class="lineNum">    2042 </span>            :     &amp; _ways_4_io_resp_brSlots_0_valid | _ways_5_io_resp_hit</a>
+<a name="2043"><span class="lineNum">    2043 </span>            :     &amp; _ways_5_io_resp_brSlots_0_valid | _ways_6_io_resp_hit</a>
+<a name="2044"><span class="lineNum">    2044 </span>            :     &amp; _ways_6_io_resp_brSlots_0_valid | _ways_7_io_resp_hit</a>
+<a name="2045"><span class="lineNum">    2045 </span>            :     &amp; _ways_7_io_resp_brSlots_0_valid | _ways_8_io_resp_hit</a>
+<a name="2046"><span class="lineNum">    2046 </span>            :     &amp; _ways_8_io_resp_brSlots_0_valid | _ways_9_io_resp_hit</a>
+<a name="2047"><span class="lineNum">    2047 </span>            :     &amp; _ways_9_io_resp_brSlots_0_valid | _ways_10_io_resp_hit</a>
+<a name="2048"><span class="lineNum">    2048 </span>            :     &amp; _ways_10_io_resp_brSlots_0_valid | _ways_11_io_resp_hit</a>
+<a name="2049"><span class="lineNum">    2049 </span>            :     &amp; _ways_11_io_resp_brSlots_0_valid | _ways_12_io_resp_hit</a>
+<a name="2050"><span class="lineNum">    2050 </span>            :     &amp; _ways_12_io_resp_brSlots_0_valid | _ways_13_io_resp_hit</a>
+<a name="2051"><span class="lineNum">    2051 </span>            :     &amp; _ways_13_io_resp_brSlots_0_valid | _ways_14_io_resp_hit</a>
+<a name="2052"><span class="lineNum">    2052 </span>            :     &amp; _ways_14_io_resp_brSlots_0_valid | _ways_15_io_resp_hit</a>
+<a name="2053"><span class="lineNum">    2053 </span>            :     &amp; _ways_15_io_resp_brSlots_0_valid | _ways_16_io_resp_hit</a>
+<a name="2054"><span class="lineNum">    2054 </span>            :     &amp; _ways_16_io_resp_brSlots_0_valid | _ways_17_io_resp_hit</a>
+<a name="2055"><span class="lineNum">    2055 </span>            :     &amp; _ways_17_io_resp_brSlots_0_valid | _ways_18_io_resp_hit</a>
+<a name="2056"><span class="lineNum">    2056 </span>            :     &amp; _ways_18_io_resp_brSlots_0_valid | _ways_19_io_resp_hit</a>
+<a name="2057"><span class="lineNum">    2057 </span>            :     &amp; _ways_19_io_resp_brSlots_0_valid | _ways_20_io_resp_hit</a>
+<a name="2058"><span class="lineNum">    2058 </span>            :     &amp; _ways_20_io_resp_brSlots_0_valid | _ways_21_io_resp_hit</a>
+<a name="2059"><span class="lineNum">    2059 </span>            :     &amp; _ways_21_io_resp_brSlots_0_valid | _ways_22_io_resp_hit</a>
+<a name="2060"><span class="lineNum">    2060 </span>            :     &amp; _ways_22_io_resp_brSlots_0_valid | _ways_23_io_resp_hit</a>
+<a name="2061"><span class="lineNum">    2061 </span>            :     &amp; _ways_23_io_resp_brSlots_0_valid | _ways_24_io_resp_hit</a>
+<a name="2062"><span class="lineNum">    2062 </span>            :     &amp; _ways_24_io_resp_brSlots_0_valid | _ways_25_io_resp_hit</a>
+<a name="2063"><span class="lineNum">    2063 </span>            :     &amp; _ways_25_io_resp_brSlots_0_valid | _ways_26_io_resp_hit</a>
+<a name="2064"><span class="lineNum">    2064 </span>            :     &amp; _ways_26_io_resp_brSlots_0_valid | _ways_27_io_resp_hit</a>
+<a name="2065"><span class="lineNum">    2065 </span>            :     &amp; _ways_27_io_resp_brSlots_0_valid | _ways_28_io_resp_hit</a>
+<a name="2066"><span class="lineNum">    2066 </span>            :     &amp; _ways_28_io_resp_brSlots_0_valid | _ways_29_io_resp_hit</a>
+<a name="2067"><span class="lineNum">    2067 </span>            :     &amp; _ways_29_io_resp_brSlots_0_valid | _ways_30_io_resp_hit</a>
+<a name="2068"><span class="lineNum">    2068 </span>            :     &amp; _ways_30_io_resp_brSlots_0_valid | _ways_31_io_resp_hit</a>
+<a name="2069"><span class="lineNum">    2069 </span>            :     &amp; _ways_31_io_resp_brSlots_0_valid;</a>
+<a name="2070"><span class="lineNum">    2070 </span>            :   wire        _s1_hit_full_pred_T_1039 =</a>
+<a name="2071"><span class="lineNum">    2071 </span>            :     _ways_0_io_resp_hit &amp; _ways_0_io_resp_tailSlot_valid | _ways_1_io_resp_hit</a>
+<a name="2072"><span class="lineNum">    2072 </span>            :     &amp; _ways_1_io_resp_tailSlot_valid | _ways_2_io_resp_hit</a>
+<a name="2073"><span class="lineNum">    2073 </span>            :     &amp; _ways_2_io_resp_tailSlot_valid | _ways_3_io_resp_hit</a>
+<a name="2074"><span class="lineNum">    2074 </span>            :     &amp; _ways_3_io_resp_tailSlot_valid | _ways_4_io_resp_hit</a>
+<a name="2075"><span class="lineNum">    2075 </span>            :     &amp; _ways_4_io_resp_tailSlot_valid | _ways_5_io_resp_hit</a>
+<a name="2076"><span class="lineNum">    2076 </span>            :     &amp; _ways_5_io_resp_tailSlot_valid | _ways_6_io_resp_hit</a>
+<a name="2077"><span class="lineNum">    2077 </span>            :     &amp; _ways_6_io_resp_tailSlot_valid | _ways_7_io_resp_hit</a>
+<a name="2078"><span class="lineNum">    2078 </span>            :     &amp; _ways_7_io_resp_tailSlot_valid | _ways_8_io_resp_hit</a>
+<a name="2079"><span class="lineNum">    2079 </span>            :     &amp; _ways_8_io_resp_tailSlot_valid | _ways_9_io_resp_hit</a>
+<a name="2080"><span class="lineNum">    2080 </span>            :     &amp; _ways_9_io_resp_tailSlot_valid | _ways_10_io_resp_hit</a>
+<a name="2081"><span class="lineNum">    2081 </span>            :     &amp; _ways_10_io_resp_tailSlot_valid | _ways_11_io_resp_hit</a>
+<a name="2082"><span class="lineNum">    2082 </span>            :     &amp; _ways_11_io_resp_tailSlot_valid | _ways_12_io_resp_hit</a>
+<a name="2083"><span class="lineNum">    2083 </span>            :     &amp; _ways_12_io_resp_tailSlot_valid | _ways_13_io_resp_hit</a>
+<a name="2084"><span class="lineNum">    2084 </span>            :     &amp; _ways_13_io_resp_tailSlot_valid | _ways_14_io_resp_hit</a>
+<a name="2085"><span class="lineNum">    2085 </span>            :     &amp; _ways_14_io_resp_tailSlot_valid | _ways_15_io_resp_hit</a>
+<a name="2086"><span class="lineNum">    2086 </span>            :     &amp; _ways_15_io_resp_tailSlot_valid | _ways_16_io_resp_hit</a>
+<a name="2087"><span class="lineNum">    2087 </span>            :     &amp; _ways_16_io_resp_tailSlot_valid | _ways_17_io_resp_hit</a>
+<a name="2088"><span class="lineNum">    2088 </span>            :     &amp; _ways_17_io_resp_tailSlot_valid | _ways_18_io_resp_hit</a>
+<a name="2089"><span class="lineNum">    2089 </span>            :     &amp; _ways_18_io_resp_tailSlot_valid | _ways_19_io_resp_hit</a>
+<a name="2090"><span class="lineNum">    2090 </span>            :     &amp; _ways_19_io_resp_tailSlot_valid | _ways_20_io_resp_hit</a>
+<a name="2091"><span class="lineNum">    2091 </span>            :     &amp; _ways_20_io_resp_tailSlot_valid | _ways_21_io_resp_hit</a>
+<a name="2092"><span class="lineNum">    2092 </span>            :     &amp; _ways_21_io_resp_tailSlot_valid | _ways_22_io_resp_hit</a>
+<a name="2093"><span class="lineNum">    2093 </span>            :     &amp; _ways_22_io_resp_tailSlot_valid | _ways_23_io_resp_hit</a>
+<a name="2094"><span class="lineNum">    2094 </span>            :     &amp; _ways_23_io_resp_tailSlot_valid | _ways_24_io_resp_hit</a>
+<a name="2095"><span class="lineNum">    2095 </span>            :     &amp; _ways_24_io_resp_tailSlot_valid | _ways_25_io_resp_hit</a>
+<a name="2096"><span class="lineNum">    2096 </span>            :     &amp; _ways_25_io_resp_tailSlot_valid | _ways_26_io_resp_hit</a>
+<a name="2097"><span class="lineNum">    2097 </span>            :     &amp; _ways_26_io_resp_tailSlot_valid | _ways_27_io_resp_hit</a>
+<a name="2098"><span class="lineNum">    2098 </span>            :     &amp; _ways_27_io_resp_tailSlot_valid | _ways_28_io_resp_hit</a>
+<a name="2099"><span class="lineNum">    2099 </span>            :     &amp; _ways_28_io_resp_tailSlot_valid | _ways_29_io_resp_hit</a>
+<a name="2100"><span class="lineNum">    2100 </span>            :     &amp; _ways_29_io_resp_tailSlot_valid | _ways_30_io_resp_hit</a>
+<a name="2101"><span class="lineNum">    2101 </span>            :     &amp; _ways_30_io_resp_tailSlot_valid | _ways_31_io_resp_hit</a>
+<a name="2102"><span class="lineNum">    2102 </span>            :     &amp; _ways_31_io_resp_tailSlot_valid;</a>
+<a name="2103"><span class="lineNum">    2103 </span>            :   wire        _s1_hit_full_pred_T_1102 =</a>
+<a name="2104"><span class="lineNum">    2104 </span>            :     _ways_0_io_resp_hit &amp; (ctrs_0_0[1] | _ways_0_io_resp_always_taken_0)</a>
+<a name="2105"><span class="lineNum">    2105 </span>            :     | _ways_1_io_resp_hit &amp; (ctrs_1_0[1] | _ways_1_io_resp_always_taken_0)</a>
+<a name="2106"><span class="lineNum">    2106 </span>            :     | _ways_2_io_resp_hit &amp; (ctrs_2_0[1] | _ways_2_io_resp_always_taken_0)</a>
+<a name="2107"><span class="lineNum">    2107 </span>            :     | _ways_3_io_resp_hit &amp; (ctrs_3_0[1] | _ways_3_io_resp_always_taken_0)</a>
+<a name="2108"><span class="lineNum">    2108 </span>            :     | _ways_4_io_resp_hit &amp; (ctrs_4_0[1] | _ways_4_io_resp_always_taken_0)</a>
+<a name="2109"><span class="lineNum">    2109 </span>            :     | _ways_5_io_resp_hit &amp; (ctrs_5_0[1] | _ways_5_io_resp_always_taken_0)</a>
+<a name="2110"><span class="lineNum">    2110 </span>            :     | _ways_6_io_resp_hit &amp; (ctrs_6_0[1] | _ways_6_io_resp_always_taken_0)</a>
+<a name="2111"><span class="lineNum">    2111 </span>            :     | _ways_7_io_resp_hit &amp; (ctrs_7_0[1] | _ways_7_io_resp_always_taken_0)</a>
+<a name="2112"><span class="lineNum">    2112 </span>            :     | _ways_8_io_resp_hit &amp; (ctrs_8_0[1] | _ways_8_io_resp_always_taken_0)</a>
+<a name="2113"><span class="lineNum">    2113 </span>            :     | _ways_9_io_resp_hit &amp; (ctrs_9_0[1] | _ways_9_io_resp_always_taken_0)</a>
+<a name="2114"><span class="lineNum">    2114 </span>            :     | _ways_10_io_resp_hit &amp; (ctrs_10_0[1] | _ways_10_io_resp_always_taken_0)</a>
+<a name="2115"><span class="lineNum">    2115 </span>            :     | _ways_11_io_resp_hit &amp; (ctrs_11_0[1] | _ways_11_io_resp_always_taken_0)</a>
+<a name="2116"><span class="lineNum">    2116 </span>            :     | _ways_12_io_resp_hit &amp; (ctrs_12_0[1] | _ways_12_io_resp_always_taken_0)</a>
+<a name="2117"><span class="lineNum">    2117 </span>            :     | _ways_13_io_resp_hit &amp; (ctrs_13_0[1] | _ways_13_io_resp_always_taken_0)</a>
+<a name="2118"><span class="lineNum">    2118 </span>            :     | _ways_14_io_resp_hit &amp; (ctrs_14_0[1] | _ways_14_io_resp_always_taken_0)</a>
+<a name="2119"><span class="lineNum">    2119 </span>            :     | _ways_15_io_resp_hit &amp; (ctrs_15_0[1] | _ways_15_io_resp_always_taken_0)</a>
+<a name="2120"><span class="lineNum">    2120 </span>            :     | _ways_16_io_resp_hit &amp; (ctrs_16_0[1] | _ways_16_io_resp_always_taken_0)</a>
+<a name="2121"><span class="lineNum">    2121 </span>            :     | _ways_17_io_resp_hit &amp; (ctrs_17_0[1] | _ways_17_io_resp_always_taken_0)</a>
+<a name="2122"><span class="lineNum">    2122 </span>            :     | _ways_18_io_resp_hit &amp; (ctrs_18_0[1] | _ways_18_io_resp_always_taken_0)</a>
+<a name="2123"><span class="lineNum">    2123 </span>            :     | _ways_19_io_resp_hit &amp; (ctrs_19_0[1] | _ways_19_io_resp_always_taken_0)</a>
+<a name="2124"><span class="lineNum">    2124 </span>            :     | _ways_20_io_resp_hit &amp; (ctrs_20_0[1] | _ways_20_io_resp_always_taken_0)</a>
+<a name="2125"><span class="lineNum">    2125 </span>            :     | _ways_21_io_resp_hit &amp; (ctrs_21_0[1] | _ways_21_io_resp_always_taken_0)</a>
+<a name="2126"><span class="lineNum">    2126 </span>            :     | _ways_22_io_resp_hit &amp; (ctrs_22_0[1] | _ways_22_io_resp_always_taken_0)</a>
+<a name="2127"><span class="lineNum">    2127 </span>            :     | _ways_23_io_resp_hit &amp; (ctrs_23_0[1] | _ways_23_io_resp_always_taken_0)</a>
+<a name="2128"><span class="lineNum">    2128 </span>            :     | _ways_24_io_resp_hit &amp; (ctrs_24_0[1] | _ways_24_io_resp_always_taken_0)</a>
+<a name="2129"><span class="lineNum">    2129 </span>            :     | _ways_25_io_resp_hit &amp; (ctrs_25_0[1] | _ways_25_io_resp_always_taken_0)</a>
+<a name="2130"><span class="lineNum">    2130 </span>            :     | _ways_26_io_resp_hit &amp; (ctrs_26_0[1] | _ways_26_io_resp_always_taken_0)</a>
+<a name="2131"><span class="lineNum">    2131 </span>            :     | _ways_27_io_resp_hit &amp; (ctrs_27_0[1] | _ways_27_io_resp_always_taken_0)</a>
+<a name="2132"><span class="lineNum">    2132 </span>            :     | _ways_28_io_resp_hit &amp; (ctrs_28_0[1] | _ways_28_io_resp_always_taken_0)</a>
+<a name="2133"><span class="lineNum">    2133 </span>            :     | _ways_29_io_resp_hit &amp; (ctrs_29_0[1] | _ways_29_io_resp_always_taken_0)</a>
+<a name="2134"><span class="lineNum">    2134 </span>            :     | _ways_30_io_resp_hit &amp; (ctrs_30_0[1] | _ways_30_io_resp_always_taken_0)</a>
+<a name="2135"><span class="lineNum">    2135 </span>            :     | _ways_31_io_resp_hit &amp; (ctrs_31_0[1] | _ways_31_io_resp_always_taken_0);</a>
+<a name="2136"><span class="lineNum">    2136 </span>            :   wire        _s1_hit_full_pred_T_1165 =</a>
+<a name="2137"><span class="lineNum">    2137 </span>            :     _ways_0_io_resp_hit &amp; (ctrs_0_1[1] | _ways_0_io_resp_always_taken_1)</a>
+<a name="2138"><span class="lineNum">    2138 </span>            :     | _ways_1_io_resp_hit &amp; (ctrs_1_1[1] | _ways_1_io_resp_always_taken_1)</a>
+<a name="2139"><span class="lineNum">    2139 </span>            :     | _ways_2_io_resp_hit &amp; (ctrs_2_1[1] | _ways_2_io_resp_always_taken_1)</a>
+<a name="2140"><span class="lineNum">    2140 </span>            :     | _ways_3_io_resp_hit &amp; (ctrs_3_1[1] | _ways_3_io_resp_always_taken_1)</a>
+<a name="2141"><span class="lineNum">    2141 </span>            :     | _ways_4_io_resp_hit &amp; (ctrs_4_1[1] | _ways_4_io_resp_always_taken_1)</a>
+<a name="2142"><span class="lineNum">    2142 </span>            :     | _ways_5_io_resp_hit &amp; (ctrs_5_1[1] | _ways_5_io_resp_always_taken_1)</a>
+<a name="2143"><span class="lineNum">    2143 </span>            :     | _ways_6_io_resp_hit &amp; (ctrs_6_1[1] | _ways_6_io_resp_always_taken_1)</a>
+<a name="2144"><span class="lineNum">    2144 </span>            :     | _ways_7_io_resp_hit &amp; (ctrs_7_1[1] | _ways_7_io_resp_always_taken_1)</a>
+<a name="2145"><span class="lineNum">    2145 </span>            :     | _ways_8_io_resp_hit &amp; (ctrs_8_1[1] | _ways_8_io_resp_always_taken_1)</a>
+<a name="2146"><span class="lineNum">    2146 </span>            :     | _ways_9_io_resp_hit &amp; (ctrs_9_1[1] | _ways_9_io_resp_always_taken_1)</a>
+<a name="2147"><span class="lineNum">    2147 </span>            :     | _ways_10_io_resp_hit &amp; (ctrs_10_1[1] | _ways_10_io_resp_always_taken_1)</a>
+<a name="2148"><span class="lineNum">    2148 </span>            :     | _ways_11_io_resp_hit &amp; (ctrs_11_1[1] | _ways_11_io_resp_always_taken_1)</a>
+<a name="2149"><span class="lineNum">    2149 </span>            :     | _ways_12_io_resp_hit &amp; (ctrs_12_1[1] | _ways_12_io_resp_always_taken_1)</a>
+<a name="2150"><span class="lineNum">    2150 </span>            :     | _ways_13_io_resp_hit &amp; (ctrs_13_1[1] | _ways_13_io_resp_always_taken_1)</a>
+<a name="2151"><span class="lineNum">    2151 </span>            :     | _ways_14_io_resp_hit &amp; (ctrs_14_1[1] | _ways_14_io_resp_always_taken_1)</a>
+<a name="2152"><span class="lineNum">    2152 </span>            :     | _ways_15_io_resp_hit &amp; (ctrs_15_1[1] | _ways_15_io_resp_always_taken_1)</a>
+<a name="2153"><span class="lineNum">    2153 </span>            :     | _ways_16_io_resp_hit &amp; (ctrs_16_1[1] | _ways_16_io_resp_always_taken_1)</a>
+<a name="2154"><span class="lineNum">    2154 </span>            :     | _ways_17_io_resp_hit &amp; (ctrs_17_1[1] | _ways_17_io_resp_always_taken_1)</a>
+<a name="2155"><span class="lineNum">    2155 </span>            :     | _ways_18_io_resp_hit &amp; (ctrs_18_1[1] | _ways_18_io_resp_always_taken_1)</a>
+<a name="2156"><span class="lineNum">    2156 </span>            :     | _ways_19_io_resp_hit &amp; (ctrs_19_1[1] | _ways_19_io_resp_always_taken_1)</a>
+<a name="2157"><span class="lineNum">    2157 </span>            :     | _ways_20_io_resp_hit &amp; (ctrs_20_1[1] | _ways_20_io_resp_always_taken_1)</a>
+<a name="2158"><span class="lineNum">    2158 </span>            :     | _ways_21_io_resp_hit &amp; (ctrs_21_1[1] | _ways_21_io_resp_always_taken_1)</a>
+<a name="2159"><span class="lineNum">    2159 </span>            :     | _ways_22_io_resp_hit &amp; (ctrs_22_1[1] | _ways_22_io_resp_always_taken_1)</a>
+<a name="2160"><span class="lineNum">    2160 </span>            :     | _ways_23_io_resp_hit &amp; (ctrs_23_1[1] | _ways_23_io_resp_always_taken_1)</a>
+<a name="2161"><span class="lineNum">    2161 </span>            :     | _ways_24_io_resp_hit &amp; (ctrs_24_1[1] | _ways_24_io_resp_always_taken_1)</a>
+<a name="2162"><span class="lineNum">    2162 </span>            :     | _ways_25_io_resp_hit &amp; (ctrs_25_1[1] | _ways_25_io_resp_always_taken_1)</a>
+<a name="2163"><span class="lineNum">    2163 </span>            :     | _ways_26_io_resp_hit &amp; (ctrs_26_1[1] | _ways_26_io_resp_always_taken_1)</a>
+<a name="2164"><span class="lineNum">    2164 </span>            :     | _ways_27_io_resp_hit &amp; (ctrs_27_1[1] | _ways_27_io_resp_always_taken_1)</a>
+<a name="2165"><span class="lineNum">    2165 </span>            :     | _ways_28_io_resp_hit &amp; (ctrs_28_1[1] | _ways_28_io_resp_always_taken_1)</a>
+<a name="2166"><span class="lineNum">    2166 </span>            :     | _ways_29_io_resp_hit &amp; (ctrs_29_1[1] | _ways_29_io_resp_always_taken_1)</a>
+<a name="2167"><span class="lineNum">    2167 </span>            :     | _ways_30_io_resp_hit &amp; (ctrs_30_1[1] | _ways_30_io_resp_always_taken_1)</a>
+<a name="2168"><span class="lineNum">    2168 </span>            :     | _ways_31_io_resp_hit &amp; (ctrs_31_1[1] | _ways_31_io_resp_always_taken_1);</a>
+<a name="2169"><span class="lineNum">    2169 </span><span class="lineCov">         97 :   reg         fauftb_enable;</span></a>
+<a name="2170"><span class="lineNum">    2170 </span><span class="lineCov">         14 :   wire        io_out_s1_full_pred_3_hit_0 = (|s1_hit_oh) &amp; fauftb_enable;</span></a>
+<a name="2171"><span class="lineNum">    2171 </span><span class="lineCov">         31 :   reg         resp_meta_hit_r;</span></a>
+<a name="2172"><span class="lineNum">    2172 </span><span class="lineCov">        165 :   reg  [4:0]  resp_meta_pred_way_r;</span></a>
+<a name="2173"><span class="lineNum">    2173 </span><span class="lineCov">         21 :   reg         replacer_touch_ways_0_valid_REG;</span></a>
+<a name="2174"><span class="lineNum">    2174 </span><span class="lineCov">         76 :   reg  [4:0]  replacer_touch_ways_0_bits_r;</span></a>
+<a name="2175"><span class="lineNum">    2175 </span><span class="lineCov">        118 :   reg         u_s1_valid;</span></a>
+<a name="2176"><span class="lineNum">    2176 </span><span class="lineCov">        435 :   reg  [15:0] u_s1_tag;</span></a>
+<a name="2177"><span class="lineNum">    2177 </span><span class="lineCov">        843 :   reg  [31:0] u_s1_hit_oh;</span></a>
+<a name="2178"><span class="lineNum">    2178 </span><span class="lineCov">         31 :   reg         u_s1_hit;</span></a>
+<a name="2179"><span class="lineNum">    2179 </span><span class="lineCov">        680 :   wire [31:0] u_s1_write_way_oh =</span></a>
+<a name="2180"><span class="lineNum">    2180 </span>            :     u_s1_hit</a>
+<a name="2181"><span class="lineNum">    2181 </span>            :       ? u_s1_hit_oh</a>
+<a name="2182"><span class="lineNum">    2182 </span>            :       : 32'h1</a>
+<a name="2183"><span class="lineNum">    2183 </span>            :         &lt;&lt; {27'h0,</a>
+<a name="2184"><span class="lineNum">    2184 </span>            :             state_reg[30],</a>
+<a name="2185"><span class="lineNum">    2185 </span>            :             state_reg[30]</a>
+<a name="2186"><span class="lineNum">    2186 </span>            :               ? {state_reg[29],</a>
+<a name="2187"><span class="lineNum">    2187 </span>            :                  state_reg[29]</a>
+<a name="2188"><span class="lineNum">    2188 </span>            :                    ? {state_reg[28],</a>
+<a name="2189"><span class="lineNum">    2189 </span>            :                       state_reg[28]</a>
+<a name="2190"><span class="lineNum">    2190 </span>            :                         ? {state_reg[27], state_reg[27] ? state_reg[26] : state_reg[25]}</a>
+<a name="2191"><span class="lineNum">    2191 </span>            :                         : {state_reg[24], state_reg[24] ? state_reg[23] : state_reg[22]}}</a>
+<a name="2192"><span class="lineNum">    2192 </span>            :                    : {state_reg[21],</a>
+<a name="2193"><span class="lineNum">    2193 </span>            :                       state_reg[21]</a>
+<a name="2194"><span class="lineNum">    2194 </span>            :                         ? {state_reg[20], state_reg[20] ? state_reg[19] : state_reg[18]}</a>
+<a name="2195"><span class="lineNum">    2195 </span>            :                         : {state_reg[17], state_reg[17] ? state_reg[16] : state_reg[15]}}}</a>
+<a name="2196"><span class="lineNum">    2196 </span>            :               : {state_reg[14],</a>
+<a name="2197"><span class="lineNum">    2197 </span>            :                  state_reg[14]</a>
+<a name="2198"><span class="lineNum">    2198 </span>            :                    ? {state_reg[13],</a>
+<a name="2199"><span class="lineNum">    2199 </span>            :                       state_reg[13]</a>
+<a name="2200"><span class="lineNum">    2200 </span>            :                         ? {state_reg[12], state_reg[12] ? state_reg[11] : state_reg[10]}</a>
+<a name="2201"><span class="lineNum">    2201 </span>            :                         : {state_reg[9], state_reg[9] ? state_reg[8] : state_reg[7]}}</a>
+<a name="2202"><span class="lineNum">    2202 </span>            :                    : {state_reg[6],</a>
+<a name="2203"><span class="lineNum">    2203 </span>            :                       state_reg[6]</a>
+<a name="2204"><span class="lineNum">    2204 </span>            :                         ? {state_reg[5], state_reg[5] ? state_reg[4] : state_reg[3]}</a>
+<a name="2205"><span class="lineNum">    2205 </span>            :                         : {state_reg[2], state_reg[2] ? state_reg[1] : state_reg[0]}}}};</a>
+<a name="2206"><span class="lineNum">    2206 </span><span class="lineCov">        127 :   reg  [3:0]  u_s1_ftb_entry_brSlots_0_offset;</span></a>
+<a name="2207"><span class="lineNum">    2207 </span><span class="lineCov">        345 :   reg  [11:0] u_s1_ftb_entry_brSlots_0_lower;</span></a>
+<a name="2208"><span class="lineNum">    2208 </span><span class="lineCov">         57 :   reg  [1:0]  u_s1_ftb_entry_brSlots_0_tarStat;</span></a>
+<a name="2209"><span class="lineNum">    2209 </span><span class="lineCov">         43 :   reg         u_s1_ftb_entry_brSlots_0_valid;</span></a>
+<a name="2210"><span class="lineNum">    2210 </span><span class="lineCov">        127 :   reg  [3:0]  u_s1_ftb_entry_tailSlot_offset;</span></a>
+<a name="2211"><span class="lineNum">    2211 </span><span class="lineCov">        573 :   reg  [19:0] u_s1_ftb_entry_tailSlot_lower;</span></a>
+<a name="2212"><span class="lineNum">    2212 </span><span class="lineCov">         70 :   reg  [1:0]  u_s1_ftb_entry_tailSlot_tarStat;</span></a>
+<a name="2213"><span class="lineNum">    2213 </span><span class="lineCov">         33 :   reg         u_s1_ftb_entry_tailSlot_sharing;</span></a>
+<a name="2214"><span class="lineNum">    2214 </span><span class="lineCov">         29 :   reg         u_s1_ftb_entry_tailSlot_valid;</span></a>
+<a name="2215"><span class="lineNum">    2215 </span><span class="lineCov">        135 :   reg  [3:0]  u_s1_ftb_entry_pftAddr;</span></a>
+<a name="2216"><span class="lineNum">    2216 </span><span class="lineCov">         30 :   reg         u_s1_ftb_entry_carry;</span></a>
+<a name="2217"><span class="lineNum">    2217 </span><span class="lineCov">         26 :   reg         u_s1_ftb_entry_always_taken_0;</span></a>
+<a name="2218"><span class="lineNum">    2218 </span><span class="lineCov">         37 :   reg         u_s1_ftb_entry_always_taken_1;</span></a>
+<a name="2219"><span class="lineNum">    2219 </span><span class="lineCov">        114 :   wire        u_s1_ways_write_valid_0 = u_s1_write_way_oh[0] &amp; u_s1_valid;</span></a>
+<a name="2220"><span class="lineNum">    2220 </span><span class="lineCov">         23 :   wire        u_s1_ways_write_valid_1 = u_s1_write_way_oh[1] &amp; u_s1_valid;</span></a>
+<a name="2221"><span class="lineNum">    2221 </span><span class="lineCov">         13 :   wire        u_s1_ways_write_valid_2 = u_s1_write_way_oh[2] &amp; u_s1_valid;</span></a>
+<a name="2222"><span class="lineNum">    2222 </span><span class="lineCov">         24 :   wire        u_s1_ways_write_valid_3 = u_s1_write_way_oh[3] &amp; u_s1_valid;</span></a>
+<a name="2223"><span class="lineNum">    2223 </span><span class="lineCov">         19 :   wire        u_s1_ways_write_valid_4 = u_s1_write_way_oh[4] &amp; u_s1_valid;</span></a>
+<a name="2224"><span class="lineNum">    2224 </span><span class="lineCov">         20 :   wire        u_s1_ways_write_valid_5 = u_s1_write_way_oh[5] &amp; u_s1_valid;</span></a>
+<a name="2225"><span class="lineNum">    2225 </span><span class="lineCov">         17 :   wire        u_s1_ways_write_valid_6 = u_s1_write_way_oh[6] &amp; u_s1_valid;</span></a>
+<a name="2226"><span class="lineNum">    2226 </span><span class="lineCov">         18 :   wire        u_s1_ways_write_valid_7 = u_s1_write_way_oh[7] &amp; u_s1_valid;</span></a>
+<a name="2227"><span class="lineNum">    2227 </span><span class="lineCov">         22 :   wire        u_s1_ways_write_valid_8 = u_s1_write_way_oh[8] &amp; u_s1_valid;</span></a>
+<a name="2228"><span class="lineNum">    2228 </span><span class="lineCov">         16 :   wire        u_s1_ways_write_valid_9 = u_s1_write_way_oh[9] &amp; u_s1_valid;</span></a>
+<a name="2229"><span class="lineNum">    2229 </span><span class="lineCov">         20 :   wire        u_s1_ways_write_valid_10 = u_s1_write_way_oh[10] &amp; u_s1_valid;</span></a>
+<a name="2230"><span class="lineNum">    2230 </span><span class="lineCov">         27 :   wire        u_s1_ways_write_valid_11 = u_s1_write_way_oh[11] &amp; u_s1_valid;</span></a>
+<a name="2231"><span class="lineNum">    2231 </span><span class="lineCov">         19 :   wire        u_s1_ways_write_valid_12 = u_s1_write_way_oh[12] &amp; u_s1_valid;</span></a>
+<a name="2232"><span class="lineNum">    2232 </span><span class="lineCov">         13 :   wire        u_s1_ways_write_valid_13 = u_s1_write_way_oh[13] &amp; u_s1_valid;</span></a>
+<a name="2233"><span class="lineNum">    2233 </span><span class="lineCov">         19 :   wire        u_s1_ways_write_valid_14 = u_s1_write_way_oh[14] &amp; u_s1_valid;</span></a>
+<a name="2234"><span class="lineNum">    2234 </span><span class="lineCov">         18 :   wire        u_s1_ways_write_valid_15 = u_s1_write_way_oh[15] &amp; u_s1_valid;</span></a>
+<a name="2235"><span class="lineNum">    2235 </span><span class="lineCov">         20 :   wire        u_s1_ways_write_valid_16 = u_s1_write_way_oh[16] &amp; u_s1_valid;</span></a>
+<a name="2236"><span class="lineNum">    2236 </span><span class="lineCov">         17 :   wire        u_s1_ways_write_valid_17 = u_s1_write_way_oh[17] &amp; u_s1_valid;</span></a>
+<a name="2237"><span class="lineNum">    2237 </span><span class="lineCov">         23 :   wire        u_s1_ways_write_valid_18 = u_s1_write_way_oh[18] &amp; u_s1_valid;</span></a>
+<a name="2238"><span class="lineNum">    2238 </span><span class="lineCov">         23 :   wire        u_s1_ways_write_valid_19 = u_s1_write_way_oh[19] &amp; u_s1_valid;</span></a>
+<a name="2239"><span class="lineNum">    2239 </span><span class="lineCov">         17 :   wire        u_s1_ways_write_valid_20 = u_s1_write_way_oh[20] &amp; u_s1_valid;</span></a>
+<a name="2240"><span class="lineNum">    2240 </span><span class="lineCov">         19 :   wire        u_s1_ways_write_valid_21 = u_s1_write_way_oh[21] &amp; u_s1_valid;</span></a>
+<a name="2241"><span class="lineNum">    2241 </span><span class="lineCov">         18 :   wire        u_s1_ways_write_valid_22 = u_s1_write_way_oh[22] &amp; u_s1_valid;</span></a>
+<a name="2242"><span class="lineNum">    2242 </span><span class="lineCov">         14 :   wire        u_s1_ways_write_valid_23 = u_s1_write_way_oh[23] &amp; u_s1_valid;</span></a>
+<a name="2243"><span class="lineNum">    2243 </span><span class="lineCov">         23 :   wire        u_s1_ways_write_valid_24 = u_s1_write_way_oh[24] &amp; u_s1_valid;</span></a>
+<a name="2244"><span class="lineNum">    2244 </span><span class="lineCov">         20 :   wire        u_s1_ways_write_valid_25 = u_s1_write_way_oh[25] &amp; u_s1_valid;</span></a>
+<a name="2245"><span class="lineNum">    2245 </span><span class="lineCov">         16 :   wire        u_s1_ways_write_valid_26 = u_s1_write_way_oh[26] &amp; u_s1_valid;</span></a>
+<a name="2246"><span class="lineNum">    2246 </span><span class="lineCov">         21 :   wire        u_s1_ways_write_valid_27 = u_s1_write_way_oh[27] &amp; u_s1_valid;</span></a>
+<a name="2247"><span class="lineNum">    2247 </span><span class="lineCov">         22 :   wire        u_s1_ways_write_valid_28 = u_s1_write_way_oh[28] &amp; u_s1_valid;</span></a>
+<a name="2248"><span class="lineNum">    2248 </span><span class="lineCov">         17 :   wire        u_s1_ways_write_valid_29 = u_s1_write_way_oh[29] &amp; u_s1_valid;</span></a>
+<a name="2249"><span class="lineNum">    2249 </span><span class="lineCov">         13 :   wire        u_s1_ways_write_valid_30 = u_s1_write_way_oh[30] &amp; u_s1_valid;</span></a>
+<a name="2250"><span class="lineNum">    2250 </span><span class="lineCov">         12 :   wire        u_s1_ways_write_valid_31 = u_s1_write_way_oh[31] &amp; u_s1_valid;</span></a>
+<a name="2251"><span class="lineNum">    2251 </span><span class="lineCov">         25 :   reg         u_s1_br_update_valids_0;</span></a>
+<a name="2252"><span class="lineNum">    2252 </span><span class="lineCov">         33 :   reg         u_s1_br_update_valids_1;</span></a>
+<a name="2253"><span class="lineNum">    2253 </span><span class="lineCov">         26 :   reg         u_s1_br_takens_0;</span></a>
+<a name="2254"><span class="lineNum">    2254 </span><span class="lineCov">         42 :   reg         u_s1_br_takens_1;</span></a>
+<a name="2255"><span class="lineNum">    2255 </span><span class="lineCov">         29 :   reg         io_perf_0_value_REG;</span></a>
+<a name="2256"><span class="lineNum">    2256 </span><span class="lineCov">         45 :   reg         io_perf_0_value_REG_1;</span></a>
+<a name="2257"><span class="lineNum">    2257 </span><span class="lineCov">        106 :   reg         io_perf_1_value_REG;</span></a>
+<a name="2258"><span class="lineNum">    2258 </span><span class="lineCov">        126 :   reg         io_perf_1_value_REG_1;</span></a>
+<a name="2259"><span class="lineNum">    2259 </span>            :   wire [40:0] _GEN_3 = {5'h0, _reset_vector_delay_io_out};</a>
+<a name="2260"><span class="lineNum">    2260 </span><span class="lineCov">        495 :   wire [31:0] u_s0_hit_oh =</span></a>
+<a name="2261"><span class="lineNum">    2261 </span>            :     {_ways_31_io_update_hit,</a>
+<a name="2262"><span class="lineNum">    2262 </span>            :      _ways_30_io_update_hit,</a>
+<a name="2263"><span class="lineNum">    2263 </span>            :      _ways_29_io_update_hit,</a>
+<a name="2264"><span class="lineNum">    2264 </span>            :      _ways_28_io_update_hit,</a>
+<a name="2265"><span class="lineNum">    2265 </span>            :      _ways_27_io_update_hit,</a>
+<a name="2266"><span class="lineNum">    2266 </span>            :      _ways_26_io_update_hit,</a>
+<a name="2267"><span class="lineNum">    2267 </span>            :      _ways_25_io_update_hit,</a>
+<a name="2268"><span class="lineNum">    2268 </span>            :      _ways_24_io_update_hit,</a>
+<a name="2269"><span class="lineNum">    2269 </span>            :      _ways_23_io_update_hit,</a>
+<a name="2270"><span class="lineNum">    2270 </span>            :      _ways_22_io_update_hit,</a>
+<a name="2271"><span class="lineNum">    2271 </span>            :      _ways_21_io_update_hit,</a>
+<a name="2272"><span class="lineNum">    2272 </span>            :      _ways_20_io_update_hit,</a>
+<a name="2273"><span class="lineNum">    2273 </span>            :      _ways_19_io_update_hit,</a>
+<a name="2274"><span class="lineNum">    2274 </span>            :      _ways_18_io_update_hit,</a>
+<a name="2275"><span class="lineNum">    2275 </span>            :      _ways_17_io_update_hit,</a>
+<a name="2276"><span class="lineNum">    2276 </span>            :      _ways_16_io_update_hit,</a>
+<a name="2277"><span class="lineNum">    2277 </span>            :      _ways_15_io_update_hit,</a>
+<a name="2278"><span class="lineNum">    2278 </span>            :      _ways_14_io_update_hit,</a>
+<a name="2279"><span class="lineNum">    2279 </span>            :      _ways_13_io_update_hit,</a>
+<a name="2280"><span class="lineNum">    2280 </span>            :      _ways_12_io_update_hit,</a>
+<a name="2281"><span class="lineNum">    2281 </span>            :      _ways_11_io_update_hit,</a>
+<a name="2282"><span class="lineNum">    2282 </span>            :      _ways_10_io_update_hit,</a>
+<a name="2283"><span class="lineNum">    2283 </span>            :      _ways_9_io_update_hit,</a>
+<a name="2284"><span class="lineNum">    2284 </span>            :      _ways_8_io_update_hit,</a>
+<a name="2285"><span class="lineNum">    2285 </span>            :      _ways_7_io_update_hit,</a>
+<a name="2286"><span class="lineNum">    2286 </span>            :      _ways_6_io_update_hit,</a>
+<a name="2287"><span class="lineNum">    2287 </span>            :      _ways_5_io_update_hit,</a>
+<a name="2288"><span class="lineNum">    2288 </span>            :      _ways_4_io_update_hit,</a>
+<a name="2289"><span class="lineNum">    2289 </span>            :      _ways_3_io_update_hit,</a>
+<a name="2290"><span class="lineNum">    2290 </span>            :      _ways_2_io_update_hit,</a>
+<a name="2291"><span class="lineNum">    2291 </span>            :      _ways_1_io_update_hit,</a>
+<a name="2292"><span class="lineNum">    2292 </span>            :      _ways_0_io_update_hit};</a>
+<a name="2293"><span class="lineNum">    2293 </span>            :   wire [14:0] _s1_hit_way_T_1 =</a>
+<a name="2294"><span class="lineNum">    2294 </span>            :     {_ways_31_io_resp_hit,</a>
+<a name="2295"><span class="lineNum">    2295 </span>            :      _ways_30_io_resp_hit,</a>
+<a name="2296"><span class="lineNum">    2296 </span>            :      _ways_29_io_resp_hit,</a>
+<a name="2297"><span class="lineNum">    2297 </span>            :      _ways_28_io_resp_hit,</a>
+<a name="2298"><span class="lineNum">    2298 </span>            :      _ways_27_io_resp_hit,</a>
+<a name="2299"><span class="lineNum">    2299 </span>            :      _ways_26_io_resp_hit,</a>
+<a name="2300"><span class="lineNum">    2300 </span>            :      _ways_25_io_resp_hit,</a>
+<a name="2301"><span class="lineNum">    2301 </span>            :      _ways_24_io_resp_hit,</a>
+<a name="2302"><span class="lineNum">    2302 </span>            :      _ways_23_io_resp_hit,</a>
+<a name="2303"><span class="lineNum">    2303 </span>            :      _ways_22_io_resp_hit,</a>
+<a name="2304"><span class="lineNum">    2304 </span>            :      _ways_21_io_resp_hit,</a>
+<a name="2305"><span class="lineNum">    2305 </span>            :      _ways_20_io_resp_hit,</a>
+<a name="2306"><span class="lineNum">    2306 </span>            :      _ways_19_io_resp_hit,</a>
+<a name="2307"><span class="lineNum">    2307 </span>            :      _ways_18_io_resp_hit,</a>
+<a name="2308"><span class="lineNum">    2308 </span>            :      _ways_17_io_resp_hit}</a>
+<a name="2309"><span class="lineNum">    2309 </span>            :     | {_ways_15_io_resp_hit,</a>
+<a name="2310"><span class="lineNum">    2310 </span>            :        _ways_14_io_resp_hit,</a>
+<a name="2311"><span class="lineNum">    2311 </span>            :        _ways_13_io_resp_hit,</a>
+<a name="2312"><span class="lineNum">    2312 </span>            :        _ways_12_io_resp_hit,</a>
+<a name="2313"><span class="lineNum">    2313 </span>            :        _ways_11_io_resp_hit,</a>
+<a name="2314"><span class="lineNum">    2314 </span>            :        _ways_10_io_resp_hit,</a>
+<a name="2315"><span class="lineNum">    2315 </span>            :        _ways_9_io_resp_hit,</a>
+<a name="2316"><span class="lineNum">    2316 </span>            :        _ways_8_io_resp_hit,</a>
+<a name="2317"><span class="lineNum">    2317 </span>            :        _ways_7_io_resp_hit,</a>
+<a name="2318"><span class="lineNum">    2318 </span>            :        _ways_6_io_resp_hit,</a>
+<a name="2319"><span class="lineNum">    2319 </span>            :        _ways_5_io_resp_hit,</a>
+<a name="2320"><span class="lineNum">    2320 </span>            :        _ways_4_io_resp_hit,</a>
+<a name="2321"><span class="lineNum">    2321 </span>            :        _ways_3_io_resp_hit,</a>
+<a name="2322"><span class="lineNum">    2322 </span>            :        _ways_2_io_resp_hit,</a>
+<a name="2323"><span class="lineNum">    2323 </span>            :        _ways_1_io_resp_hit};</a>
+<a name="2324"><span class="lineNum">    2324 </span>            :   wire [6:0]  _s1_hit_way_T_3 = _s1_hit_way_T_1[14:8] | _s1_hit_way_T_1[6:0];</a>
+<a name="2325"><span class="lineNum">    2325 </span>            :   wire [2:0]  _s1_hit_way_T_5 = _s1_hit_way_T_3[6:4] | _s1_hit_way_T_3[2:0];</a>
+<a name="2326"><span class="lineNum">    2326 </span><span class="lineCov">         80 :   wire [4:0]  s1_hit_way =</span></a>
+<a name="2327"><span class="lineNum">    2327 </span>            :     {|{_ways_31_io_resp_hit,</a>
+<a name="2328"><span class="lineNum">    2328 </span>            :        _ways_30_io_resp_hit,</a>
+<a name="2329"><span class="lineNum">    2329 </span>            :        _ways_29_io_resp_hit,</a>
+<a name="2330"><span class="lineNum">    2330 </span>            :        _ways_28_io_resp_hit,</a>
+<a name="2331"><span class="lineNum">    2331 </span>            :        _ways_27_io_resp_hit,</a>
+<a name="2332"><span class="lineNum">    2332 </span>            :        _ways_26_io_resp_hit,</a>
+<a name="2333"><span class="lineNum">    2333 </span>            :        _ways_25_io_resp_hit,</a>
+<a name="2334"><span class="lineNum">    2334 </span>            :        _ways_24_io_resp_hit,</a>
+<a name="2335"><span class="lineNum">    2335 </span>            :        _ways_23_io_resp_hit,</a>
+<a name="2336"><span class="lineNum">    2336 </span>            :        _ways_22_io_resp_hit,</a>
+<a name="2337"><span class="lineNum">    2337 </span>            :        _ways_21_io_resp_hit,</a>
+<a name="2338"><span class="lineNum">    2338 </span>            :        _ways_20_io_resp_hit,</a>
+<a name="2339"><span class="lineNum">    2339 </span>            :        _ways_19_io_resp_hit,</a>
+<a name="2340"><span class="lineNum">    2340 </span>            :        _ways_18_io_resp_hit,</a>
+<a name="2341"><span class="lineNum">    2341 </span>            :        _ways_17_io_resp_hit,</a>
+<a name="2342"><span class="lineNum">    2342 </span>            :        _ways_16_io_resp_hit},</a>
+<a name="2343"><span class="lineNum">    2343 </span>            :      |(_s1_hit_way_T_1[14:7]),</a>
+<a name="2344"><span class="lineNum">    2344 </span>            :      |(_s1_hit_way_T_3[6:3]),</a>
+<a name="2345"><span class="lineNum">    2345 </span>            :      |(_s1_hit_way_T_5[2:1]),</a>
+<a name="2346"><span class="lineNum">    2346 </span>            :      _s1_hit_way_T_5[2] | _s1_hit_way_T_5[0]};</a>
+<a name="2347"><span class="lineNum">    2347 </span><span class="lineCov">     127694 :   always @(posedge clock) begin</span></a>
+<a name="2348"><span class="lineNum">    2348 </span><span class="lineCov">         98 :     if (REG_1) begin</span></a>
+<a name="2349"><span class="lineNum">    2349 </span><span class="lineCov">         49 :       s1_pc_dup_0 &lt;= _GEN_3;</span></a>
+<a name="2350"><span class="lineNum">    2350 </span><span class="lineCov">         49 :       s1_pc_dup_1 &lt;= _GEN_3;</span></a>
+<a name="2351"><span class="lineNum">    2351 </span><span class="lineCov">         49 :       s1_pc_dup_2 &lt;= _GEN_3;</span></a>
+<a name="2352"><span class="lineNum">    2352 </span><span class="lineCov">         49 :       s1_pc_dup_3 &lt;= _GEN_3;</span></a>
+<a name="2353"><span class="lineNum">    2353 </span>            :     end</a>
+<a name="2354"><span class="lineNum">    2354 </span><span class="lineCov">      63798 :     else begin</span></a>
+<a name="2355"><span class="lineNum">    2355 </span><span class="lineCov">       8350 :       if (io_s0_fire_0)</span></a>
+<a name="2356"><span class="lineNum">    2356 </span><span class="lineCov">       4175 :         s1_pc_dup_0 &lt;= io_in_bits_s0_pc_0;</span></a>
+<a name="2357"><span class="lineNum">    2357 </span><span class="lineCov">       8350 :       if (io_s0_fire_1)</span></a>
+<a name="2358"><span class="lineNum">    2358 </span><span class="lineCov">       4175 :         s1_pc_dup_1 &lt;= io_in_bits_s0_pc_1;</span></a>
+<a name="2359"><span class="lineNum">    2359 </span><span class="lineCov">       8350 :       if (io_s0_fire_2)</span></a>
+<a name="2360"><span class="lineNum">    2360 </span><span class="lineCov">       4175 :         s1_pc_dup_2 &lt;= io_in_bits_s0_pc_2;</span></a>
+<a name="2361"><span class="lineNum">    2361 </span><span class="lineCov">       8350 :       if (io_s0_fire_3)</span></a>
+<a name="2362"><span class="lineNum">    2362 </span><span class="lineCov">       4175 :         s1_pc_dup_3 &lt;= io_in_bits_s0_pc_3;</span></a>
+<a name="2363"><span class="lineNum">    2363 </span>            :     end</a>
+<a name="2364"><span class="lineNum">    2364 </span><span class="lineCov">      63847 :     REG &lt;= reset;</span></a>
+<a name="2365"><span class="lineNum">    2365 </span><span class="lineCov">      63847 :     REG_1 &lt;= REG &amp; ~reset;</span></a>
+<a name="2366"><span class="lineNum">    2366 </span><span class="lineCov">      63847 :     fauftb_enable &lt;= io_ctrl_ubtb_enable;</span></a>
+<a name="2367"><span class="lineNum">    2367 </span><span class="lineCov">       8252 :     if (io_s1_fire_0) begin</span></a>
+<a name="2368"><span class="lineNum">    2368 </span><span class="lineCov">       4126 :       resp_meta_hit_r &lt;= |s1_hit_oh;</span></a>
+<a name="2369"><span class="lineNum">    2369 </span><span class="lineCov">       4126 :       resp_meta_pred_way_r &lt;= s1_hit_way;</span></a>
+<a name="2370"><span class="lineNum">    2370 </span>            :     end</a>
+<a name="2371"><span class="lineNum">    2371 </span><span class="lineCov">       8150 :     if (io_s2_fire_0) begin</span></a>
+<a name="2372"><span class="lineNum">    2372 </span><span class="lineCov">       4075 :       resp_meta_hit_r_1 &lt;= resp_meta_hit_r;</span></a>
+<a name="2373"><span class="lineNum">    2373 </span><span class="lineCov">       4075 :       resp_meta_pred_way_r_1 &lt;= resp_meta_pred_way_r;</span></a>
+<a name="2374"><span class="lineNum">    2374 </span>            :     end</a>
+<a name="2375"><span class="lineNum">    2375 </span><span class="lineCov">      63847 :     replacer_touch_ways_0_valid_REG &lt;= io_s1_fire_0 &amp; (|s1_hit_oh);</span></a>
+<a name="2376"><span class="lineNum">    2376 </span><span class="lineNoCov">          0 :     if (io_s1_fire_0 &amp; (|s1_hit_oh))</span></a>
+<a name="2377"><span class="lineNum">    2377 </span><span class="lineNoCov">          0 :       replacer_touch_ways_0_bits_r &lt;= s1_hit_way;</span></a>
+<a name="2378"><span class="lineNum">    2378 </span><span class="lineCov">      63847 :     u_s1_valid &lt;= io_update_valid;</span></a>
+<a name="2379"><span class="lineNum">    2379 </span><span class="lineCov">         94 :     if (io_update_valid) begin</span></a>
+<a name="2380"><span class="lineNum">    2380 </span><span class="lineCov">         47 :       u_s1_tag &lt;= io_update_bits_pc[16:1];</span></a>
+<a name="2381"><span class="lineNum">    2381 </span><span class="lineCov">         47 :       u_s1_hit_oh &lt;= u_s0_hit_oh;</span></a>
+<a name="2382"><span class="lineNum">    2382 </span><span class="lineCov">         47 :       u_s1_hit &lt;= |u_s0_hit_oh;</span></a>
+<a name="2383"><span class="lineNum">    2383 </span><span class="lineCov">         47 :       u_s1_ftb_entry_brSlots_0_offset &lt;= io_update_bits_ftb_entry_brSlots_0_offset;</span></a>
+<a name="2384"><span class="lineNum">    2384 </span><span class="lineCov">         47 :       u_s1_ftb_entry_brSlots_0_lower &lt;= io_update_bits_ftb_entry_brSlots_0_lower;</span></a>
+<a name="2385"><span class="lineNum">    2385 </span><span class="lineCov">         47 :       u_s1_ftb_entry_brSlots_0_tarStat &lt;= io_update_bits_ftb_entry_brSlots_0_tarStat;</span></a>
+<a name="2386"><span class="lineNum">    2386 </span><span class="lineCov">         47 :       u_s1_ftb_entry_brSlots_0_valid &lt;= io_update_bits_ftb_entry_brSlots_0_valid;</span></a>
+<a name="2387"><span class="lineNum">    2387 </span><span class="lineCov">         47 :       u_s1_ftb_entry_tailSlot_offset &lt;= io_update_bits_ftb_entry_tailSlot_offset;</span></a>
+<a name="2388"><span class="lineNum">    2388 </span><span class="lineCov">         47 :       u_s1_ftb_entry_tailSlot_lower &lt;= io_update_bits_ftb_entry_tailSlot_lower;</span></a>
+<a name="2389"><span class="lineNum">    2389 </span><span class="lineCov">         47 :       u_s1_ftb_entry_tailSlot_tarStat &lt;= io_update_bits_ftb_entry_tailSlot_tarStat;</span></a>
+<a name="2390"><span class="lineNum">    2390 </span><span class="lineCov">         47 :       u_s1_ftb_entry_tailSlot_sharing &lt;= io_update_bits_ftb_entry_tailSlot_sharing;</span></a>
+<a name="2391"><span class="lineNum">    2391 </span><span class="lineCov">         47 :       u_s1_ftb_entry_tailSlot_valid &lt;= io_update_bits_ftb_entry_tailSlot_valid;</span></a>
+<a name="2392"><span class="lineNum">    2392 </span><span class="lineCov">         47 :       u_s1_ftb_entry_pftAddr &lt;= io_update_bits_ftb_entry_pftAddr;</span></a>
+<a name="2393"><span class="lineNum">    2393 </span><span class="lineCov">         47 :       u_s1_ftb_entry_carry &lt;= io_update_bits_ftb_entry_carry;</span></a>
+<a name="2394"><span class="lineNum">    2394 </span><span class="lineCov">         47 :       u_s1_ftb_entry_always_taken_0 &lt;= io_update_bits_ftb_entry_always_taken_0;</span></a>
+<a name="2395"><span class="lineNum">    2395 </span><span class="lineCov">         47 :       u_s1_ftb_entry_always_taken_1 &lt;= io_update_bits_ftb_entry_always_taken_1;</span></a>
+<a name="2396"><span class="lineNum">    2396 </span><span class="lineCov">         47 :       u_s1_br_update_valids_0 &lt;=</span></a>
+<a name="2397"><span class="lineNum">    2397 </span><span class="lineCov">         47 :         io_update_bits_ftb_entry_brSlots_0_valid &amp; io_update_valid</span></a>
+<a name="2398"><span class="lineNum">    2398 </span><span class="lineCov">         47 :         &amp; ~io_update_bits_ftb_entry_always_taken_0;</span></a>
+<a name="2399"><span class="lineNum">    2399 </span><span class="lineCov">         47 :       u_s1_br_update_valids_1 &lt;=</span></a>
+<a name="2400"><span class="lineNum">    2400 </span><span class="lineCov">         47 :         io_update_bits_ftb_entry_tailSlot_valid</span></a>
+<a name="2401"><span class="lineNum">    2401 </span><span class="lineCov">         47 :         &amp; io_update_bits_ftb_entry_tailSlot_sharing &amp; io_update_valid</span></a>
+<a name="2402"><span class="lineNum">    2402 </span><span class="lineCov">         47 :         &amp; ~io_update_bits_ftb_entry_always_taken_1 &amp; ~io_update_bits_br_taken_mask_0;</span></a>
+<a name="2403"><span class="lineNum">    2403 </span><span class="lineCov">         47 :       u_s1_br_takens_0 &lt;= io_update_bits_br_taken_mask_0;</span></a>
+<a name="2404"><span class="lineNum">    2404 </span><span class="lineCov">         47 :       u_s1_br_takens_1 &lt;= io_update_bits_br_taken_mask_1;</span></a>
+<a name="2405"><span class="lineNum">    2405 </span>            :     end</a>
+<a name="2406"><span class="lineNum">    2406 </span><span class="lineCov">      63847 :     io_perf_0_value_REG &lt;= io_update_valid &amp; io_update_bits_meta[0];</span></a>
+<a name="2407"><span class="lineNum">    2407 </span><span class="lineCov">      63847 :     io_perf_0_value_REG_1 &lt;= io_perf_0_value_REG;</span></a>
+<a name="2408"><span class="lineNum">    2408 </span><span class="lineCov">      63847 :     io_perf_1_value_REG &lt;= io_update_valid &amp; ~(io_update_bits_meta[0]);</span></a>
+<a name="2409"><span class="lineNum">    2409 </span><span class="lineCov">      63847 :     io_perf_1_value_REG_1 &lt;= io_perf_1_value_REG;</span></a>
+<a name="2410"><span class="lineNum">    2410 </span>            :   end // always @(posedge)</a>
+<a name="2411"><span class="lineNum">    2411 </span>            :   wire [14:0] _replacer_touch_ways_1_bits_T_1 =</a>
+<a name="2412"><span class="lineNum">    2412 </span>            :     u_s1_write_way_oh[31:17] | u_s1_write_way_oh[15:1];</a>
+<a name="2413"><span class="lineNum">    2413 </span>            :   wire [6:0]  _replacer_touch_ways_1_bits_T_3 =</a>
+<a name="2414"><span class="lineNum">    2414 </span>            :     _replacer_touch_ways_1_bits_T_1[14:8] | _replacer_touch_ways_1_bits_T_1[6:0];</a>
+<a name="2415"><span class="lineNum">    2415 </span>            :   wire [2:0]  _replacer_touch_ways_1_bits_T_5 =</a>
+<a name="2416"><span class="lineNum">    2416 </span>            :     _replacer_touch_ways_1_bits_T_3[6:4] | _replacer_touch_ways_1_bits_T_3[2:0];</a>
+<a name="2417"><span class="lineNum">    2417 </span>            :   wire        _replacer_touch_ways_1_bits_T_7 =</a>
+<a name="2418"><span class="lineNum">    2418 </span>            :     _replacer_touch_ways_1_bits_T_5[2] | _replacer_touch_ways_1_bits_T_5[0];</a>
+<a name="2419"><span class="lineNum">    2419 </span>            :   wire [14:0] _state_reg_T_52 =</a>
+<a name="2420"><span class="lineNum">    2420 </span>            :     replacer_touch_ways_0_bits_r[4]</a>
+<a name="2421"><span class="lineNum">    2421 </span>            :       ? {~(replacer_touch_ways_0_bits_r[3]),</a>
+<a name="2422"><span class="lineNum">    2422 </span>            :          replacer_touch_ways_0_bits_r[3]</a>
+<a name="2423"><span class="lineNum">    2423 </span>            :            ? {~(replacer_touch_ways_0_bits_r[2]),</a>
+<a name="2424"><span class="lineNum">    2424 </span>            :               replacer_touch_ways_0_bits_r[2]</a>
+<a name="2425"><span class="lineNum">    2425 </span>            :                 ? {~(replacer_touch_ways_0_bits_r[1]),</a>
+<a name="2426"><span class="lineNum">    2426 </span>            :                    replacer_touch_ways_0_bits_r[1]</a>
+<a name="2427"><span class="lineNum">    2427 </span>            :                      ? ~(replacer_touch_ways_0_bits_r[0])</a>
+<a name="2428"><span class="lineNum">    2428 </span>            :                      : state_reg[26],</a>
+<a name="2429"><span class="lineNum">    2429 </span>            :                    replacer_touch_ways_0_bits_r[1]</a>
+<a name="2430"><span class="lineNum">    2430 </span>            :                      ? state_reg[25]</a>
+<a name="2431"><span class="lineNum">    2431 </span>            :                      : ~(replacer_touch_ways_0_bits_r[0])}</a>
+<a name="2432"><span class="lineNum">    2432 </span>            :                 : state_reg[27:25],</a>
+<a name="2433"><span class="lineNum">    2433 </span>            :               replacer_touch_ways_0_bits_r[2]</a>
+<a name="2434"><span class="lineNum">    2434 </span>            :                 ? state_reg[24:22]</a>
+<a name="2435"><span class="lineNum">    2435 </span>            :                 : {~(replacer_touch_ways_0_bits_r[1]),</a>
+<a name="2436"><span class="lineNum">    2436 </span>            :                    replacer_touch_ways_0_bits_r[1]</a>
+<a name="2437"><span class="lineNum">    2437 </span>            :                      ? ~(replacer_touch_ways_0_bits_r[0])</a>
+<a name="2438"><span class="lineNum">    2438 </span>            :                      : state_reg[23],</a>
+<a name="2439"><span class="lineNum">    2439 </span>            :                    replacer_touch_ways_0_bits_r[1]</a>
+<a name="2440"><span class="lineNum">    2440 </span>            :                      ? state_reg[22]</a>
+<a name="2441"><span class="lineNum">    2441 </span>            :                      : ~(replacer_touch_ways_0_bits_r[0])}}</a>
+<a name="2442"><span class="lineNum">    2442 </span>            :            : state_reg[28:22],</a>
+<a name="2443"><span class="lineNum">    2443 </span>            :          replacer_touch_ways_0_bits_r[3]</a>
+<a name="2444"><span class="lineNum">    2444 </span>            :            ? state_reg[21:15]</a>
+<a name="2445"><span class="lineNum">    2445 </span>            :            : {~(replacer_touch_ways_0_bits_r[2]),</a>
+<a name="2446"><span class="lineNum">    2446 </span>            :               replacer_touch_ways_0_bits_r[2]</a>
+<a name="2447"><span class="lineNum">    2447 </span>            :                 ? {~(replacer_touch_ways_0_bits_r[1]),</a>
+<a name="2448"><span class="lineNum">    2448 </span>            :                    replacer_touch_ways_0_bits_r[1]</a>
+<a name="2449"><span class="lineNum">    2449 </span>            :                      ? ~(replacer_touch_ways_0_bits_r[0])</a>
+<a name="2450"><span class="lineNum">    2450 </span>            :                      : state_reg[19],</a>
+<a name="2451"><span class="lineNum">    2451 </span>            :                    replacer_touch_ways_0_bits_r[1]</a>
+<a name="2452"><span class="lineNum">    2452 </span>            :                      ? state_reg[18]</a>
+<a name="2453"><span class="lineNum">    2453 </span>            :                      : ~(replacer_touch_ways_0_bits_r[0])}</a>
+<a name="2454"><span class="lineNum">    2454 </span>            :                 : state_reg[20:18],</a>
+<a name="2455"><span class="lineNum">    2455 </span>            :               replacer_touch_ways_0_bits_r[2]</a>
+<a name="2456"><span class="lineNum">    2456 </span>            :                 ? state_reg[17:15]</a>
+<a name="2457"><span class="lineNum">    2457 </span>            :                 : {~(replacer_touch_ways_0_bits_r[1]),</a>
+<a name="2458"><span class="lineNum">    2458 </span>            :                    replacer_touch_ways_0_bits_r[1]</a>
+<a name="2459"><span class="lineNum">    2459 </span>            :                      ? ~(replacer_touch_ways_0_bits_r[0])</a>
+<a name="2460"><span class="lineNum">    2460 </span>            :                      : state_reg[16],</a>
+<a name="2461"><span class="lineNum">    2461 </span>            :                    replacer_touch_ways_0_bits_r[1]</a>
+<a name="2462"><span class="lineNum">    2462 </span>            :                      ? state_reg[15]</a>
+<a name="2463"><span class="lineNum">    2463 </span>            :                      : ~(replacer_touch_ways_0_bits_r[0])}}}</a>
+<a name="2464"><span class="lineNum">    2464 </span>            :       : state_reg[29:15];</a>
+<a name="2465"><span class="lineNum">    2465 </span>            :   wire [14:0] _state_reg_T_105 =</a>
+<a name="2466"><span class="lineNum">    2466 </span>            :     replacer_touch_ways_0_bits_r[4]</a>
+<a name="2467"><span class="lineNum">    2467 </span>            :       ? state_reg[14:0]</a>
+<a name="2468"><span class="lineNum">    2468 </span>            :       : {~(replacer_touch_ways_0_bits_r[3]),</a>
+<a name="2469"><span class="lineNum">    2469 </span>            :          replacer_touch_ways_0_bits_r[3]</a>
+<a name="2470"><span class="lineNum">    2470 </span>            :            ? {~(replacer_touch_ways_0_bits_r[2]),</a>
+<a name="2471"><span class="lineNum">    2471 </span>            :               replacer_touch_ways_0_bits_r[2]</a>
+<a name="2472"><span class="lineNum">    2472 </span>            :                 ? {~(replacer_touch_ways_0_bits_r[1]),</a>
+<a name="2473"><span class="lineNum">    2473 </span>            :                    replacer_touch_ways_0_bits_r[1]</a>
+<a name="2474"><span class="lineNum">    2474 </span>            :                      ? ~(replacer_touch_ways_0_bits_r[0])</a>
+<a name="2475"><span class="lineNum">    2475 </span>            :                      : state_reg[11],</a>
+<a name="2476"><span class="lineNum">    2476 </span>            :                    replacer_touch_ways_0_bits_r[1]</a>
+<a name="2477"><span class="lineNum">    2477 </span>            :                      ? state_reg[10]</a>
+<a name="2478"><span class="lineNum">    2478 </span>            :                      : ~(replacer_touch_ways_0_bits_r[0])}</a>
+<a name="2479"><span class="lineNum">    2479 </span>            :                 : state_reg[12:10],</a>
+<a name="2480"><span class="lineNum">    2480 </span>            :               replacer_touch_ways_0_bits_r[2]</a>
+<a name="2481"><span class="lineNum">    2481 </span>            :                 ? state_reg[9:7]</a>
+<a name="2482"><span class="lineNum">    2482 </span>            :                 : {~(replacer_touch_ways_0_bits_r[1]),</a>
+<a name="2483"><span class="lineNum">    2483 </span>            :                    replacer_touch_ways_0_bits_r[1]</a>
+<a name="2484"><span class="lineNum">    2484 </span>            :                      ? ~(replacer_touch_ways_0_bits_r[0])</a>
+<a name="2485"><span class="lineNum">    2485 </span>            :                      : state_reg[8],</a>
+<a name="2486"><span class="lineNum">    2486 </span>            :                    replacer_touch_ways_0_bits_r[1]</a>
+<a name="2487"><span class="lineNum">    2487 </span>            :                      ? state_reg[7]</a>
+<a name="2488"><span class="lineNum">    2488 </span>            :                      : ~(replacer_touch_ways_0_bits_r[0])}}</a>
+<a name="2489"><span class="lineNum">    2489 </span>            :            : state_reg[13:7],</a>
+<a name="2490"><span class="lineNum">    2490 </span>            :          replacer_touch_ways_0_bits_r[3]</a>
+<a name="2491"><span class="lineNum">    2491 </span>            :            ? state_reg[6:0]</a>
+<a name="2492"><span class="lineNum">    2492 </span>            :            : {~(replacer_touch_ways_0_bits_r[2]),</a>
+<a name="2493"><span class="lineNum">    2493 </span>            :               replacer_touch_ways_0_bits_r[2]</a>
+<a name="2494"><span class="lineNum">    2494 </span>            :                 ? {~(replacer_touch_ways_0_bits_r[1]),</a>
+<a name="2495"><span class="lineNum">    2495 </span>            :                    replacer_touch_ways_0_bits_r[1]</a>
+<a name="2496"><span class="lineNum">    2496 </span>            :                      ? ~(replacer_touch_ways_0_bits_r[0])</a>
+<a name="2497"><span class="lineNum">    2497 </span>            :                      : state_reg[4],</a>
+<a name="2498"><span class="lineNum">    2498 </span>            :                    replacer_touch_ways_0_bits_r[1]</a>
+<a name="2499"><span class="lineNum">    2499 </span>            :                      ? state_reg[3]</a>
+<a name="2500"><span class="lineNum">    2500 </span>            :                      : ~(replacer_touch_ways_0_bits_r[0])}</a>
+<a name="2501"><span class="lineNum">    2501 </span>            :                 : state_reg[5:3],</a>
+<a name="2502"><span class="lineNum">    2502 </span>            :               replacer_touch_ways_0_bits_r[2]</a>
+<a name="2503"><span class="lineNum">    2503 </span>            :                 ? state_reg[2:0]</a>
+<a name="2504"><span class="lineNum">    2504 </span>            :                 : {~(replacer_touch_ways_0_bits_r[1]),</a>
+<a name="2505"><span class="lineNum">    2505 </span>            :                    replacer_touch_ways_0_bits_r[1]</a>
+<a name="2506"><span class="lineNum">    2506 </span>            :                      ? ~(replacer_touch_ways_0_bits_r[0])</a>
+<a name="2507"><span class="lineNum">    2507 </span>            :                      : state_reg[1],</a>
+<a name="2508"><span class="lineNum">    2508 </span>            :                    replacer_touch_ways_0_bits_r[1]</a>
+<a name="2509"><span class="lineNum">    2509 </span>            :                      ? state_reg[0]</a>
+<a name="2510"><span class="lineNum">    2510 </span>            :                      : ~(replacer_touch_ways_0_bits_r[0])}}};</a>
+<a name="2511"><span class="lineNum">    2511 </span>            :   wire [29:0] _state_reg_T_107 =</a>
+<a name="2512"><span class="lineNum">    2512 </span>            :     replacer_touch_ways_0_valid_REG</a>
+<a name="2513"><span class="lineNum">    2513 </span>            :       ? {_state_reg_T_52, _state_reg_T_105}</a>
+<a name="2514"><span class="lineNum">    2514 </span>            :       : state_reg[29:0];</a>
+<a name="2515"><span class="lineNum">    2515 </span><span class="lineCov">     127730 :   always @(posedge clock or posedge reset) begin</span></a>
+<a name="2516"><span class="lineNum">    2516 </span><span class="lineCov">        272 :     if (reset) begin</span></a>
+<a name="2517"><span class="lineNum">    2517 </span><span class="lineCov">        136 :       ctrs_0_0 &lt;= 2'h2;</span></a>
+<a name="2518"><span class="lineNum">    2518 </span><span class="lineCov">        136 :       ctrs_0_1 &lt;= 2'h2;</span></a>
+<a name="2519"><span class="lineNum">    2519 </span><span class="lineCov">        136 :       ctrs_1_0 &lt;= 2'h2;</span></a>
+<a name="2520"><span class="lineNum">    2520 </span><span class="lineCov">        136 :       ctrs_1_1 &lt;= 2'h2;</span></a>
+<a name="2521"><span class="lineNum">    2521 </span><span class="lineCov">        136 :       ctrs_2_0 &lt;= 2'h2;</span></a>
+<a name="2522"><span class="lineNum">    2522 </span><span class="lineCov">        136 :       ctrs_2_1 &lt;= 2'h2;</span></a>
+<a name="2523"><span class="lineNum">    2523 </span><span class="lineCov">        136 :       ctrs_3_0 &lt;= 2'h2;</span></a>
+<a name="2524"><span class="lineNum">    2524 </span><span class="lineCov">        136 :       ctrs_3_1 &lt;= 2'h2;</span></a>
+<a name="2525"><span class="lineNum">    2525 </span><span class="lineCov">        136 :       ctrs_4_0 &lt;= 2'h2;</span></a>
+<a name="2526"><span class="lineNum">    2526 </span><span class="lineCov">        136 :       ctrs_4_1 &lt;= 2'h2;</span></a>
+<a name="2527"><span class="lineNum">    2527 </span><span class="lineCov">        136 :       ctrs_5_0 &lt;= 2'h2;</span></a>
+<a name="2528"><span class="lineNum">    2528 </span><span class="lineCov">        136 :       ctrs_5_1 &lt;= 2'h2;</span></a>
+<a name="2529"><span class="lineNum">    2529 </span><span class="lineCov">        136 :       ctrs_6_0 &lt;= 2'h2;</span></a>
+<a name="2530"><span class="lineNum">    2530 </span><span class="lineCov">        136 :       ctrs_6_1 &lt;= 2'h2;</span></a>
+<a name="2531"><span class="lineNum">    2531 </span><span class="lineCov">        136 :       ctrs_7_0 &lt;= 2'h2;</span></a>
+<a name="2532"><span class="lineNum">    2532 </span><span class="lineCov">        136 :       ctrs_7_1 &lt;= 2'h2;</span></a>
+<a name="2533"><span class="lineNum">    2533 </span><span class="lineCov">        136 :       ctrs_8_0 &lt;= 2'h2;</span></a>
+<a name="2534"><span class="lineNum">    2534 </span><span class="lineCov">        136 :       ctrs_8_1 &lt;= 2'h2;</span></a>
+<a name="2535"><span class="lineNum">    2535 </span><span class="lineCov">        136 :       ctrs_9_0 &lt;= 2'h2;</span></a>
+<a name="2536"><span class="lineNum">    2536 </span><span class="lineCov">        136 :       ctrs_9_1 &lt;= 2'h2;</span></a>
+<a name="2537"><span class="lineNum">    2537 </span><span class="lineCov">        136 :       ctrs_10_0 &lt;= 2'h2;</span></a>
+<a name="2538"><span class="lineNum">    2538 </span><span class="lineCov">        136 :       ctrs_10_1 &lt;= 2'h2;</span></a>
+<a name="2539"><span class="lineNum">    2539 </span><span class="lineCov">        136 :       ctrs_11_0 &lt;= 2'h2;</span></a>
+<a name="2540"><span class="lineNum">    2540 </span><span class="lineCov">        136 :       ctrs_11_1 &lt;= 2'h2;</span></a>
+<a name="2541"><span class="lineNum">    2541 </span><span class="lineCov">        136 :       ctrs_12_0 &lt;= 2'h2;</span></a>
+<a name="2542"><span class="lineNum">    2542 </span><span class="lineCov">        136 :       ctrs_12_1 &lt;= 2'h2;</span></a>
+<a name="2543"><span class="lineNum">    2543 </span><span class="lineCov">        136 :       ctrs_13_0 &lt;= 2'h2;</span></a>
+<a name="2544"><span class="lineNum">    2544 </span><span class="lineCov">        136 :       ctrs_13_1 &lt;= 2'h2;</span></a>
+<a name="2545"><span class="lineNum">    2545 </span><span class="lineCov">        136 :       ctrs_14_0 &lt;= 2'h2;</span></a>
+<a name="2546"><span class="lineNum">    2546 </span><span class="lineCov">        136 :       ctrs_14_1 &lt;= 2'h2;</span></a>
+<a name="2547"><span class="lineNum">    2547 </span><span class="lineCov">        136 :       ctrs_15_0 &lt;= 2'h2;</span></a>
+<a name="2548"><span class="lineNum">    2548 </span><span class="lineCov">        136 :       ctrs_15_1 &lt;= 2'h2;</span></a>
+<a name="2549"><span class="lineNum">    2549 </span><span class="lineCov">        136 :       ctrs_16_0 &lt;= 2'h2;</span></a>
+<a name="2550"><span class="lineNum">    2550 </span><span class="lineCov">        136 :       ctrs_16_1 &lt;= 2'h2;</span></a>
+<a name="2551"><span class="lineNum">    2551 </span><span class="lineCov">        136 :       ctrs_17_0 &lt;= 2'h2;</span></a>
+<a name="2552"><span class="lineNum">    2552 </span><span class="lineCov">        136 :       ctrs_17_1 &lt;= 2'h2;</span></a>
+<a name="2553"><span class="lineNum">    2553 </span><span class="lineCov">        136 :       ctrs_18_0 &lt;= 2'h2;</span></a>
+<a name="2554"><span class="lineNum">    2554 </span><span class="lineCov">        136 :       ctrs_18_1 &lt;= 2'h2;</span></a>
+<a name="2555"><span class="lineNum">    2555 </span><span class="lineCov">        136 :       ctrs_19_0 &lt;= 2'h2;</span></a>
+<a name="2556"><span class="lineNum">    2556 </span><span class="lineCov">        136 :       ctrs_19_1 &lt;= 2'h2;</span></a>
+<a name="2557"><span class="lineNum">    2557 </span><span class="lineCov">        136 :       ctrs_20_0 &lt;= 2'h2;</span></a>
+<a name="2558"><span class="lineNum">    2558 </span><span class="lineCov">        136 :       ctrs_20_1 &lt;= 2'h2;</span></a>
+<a name="2559"><span class="lineNum">    2559 </span><span class="lineCov">        136 :       ctrs_21_0 &lt;= 2'h2;</span></a>
+<a name="2560"><span class="lineNum">    2560 </span><span class="lineCov">        136 :       ctrs_21_1 &lt;= 2'h2;</span></a>
+<a name="2561"><span class="lineNum">    2561 </span><span class="lineCov">        136 :       ctrs_22_0 &lt;= 2'h2;</span></a>
+<a name="2562"><span class="lineNum">    2562 </span><span class="lineCov">        136 :       ctrs_22_1 &lt;= 2'h2;</span></a>
+<a name="2563"><span class="lineNum">    2563 </span><span class="lineCov">        136 :       ctrs_23_0 &lt;= 2'h2;</span></a>
+<a name="2564"><span class="lineNum">    2564 </span><span class="lineCov">        136 :       ctrs_23_1 &lt;= 2'h2;</span></a>
+<a name="2565"><span class="lineNum">    2565 </span><span class="lineCov">        136 :       ctrs_24_0 &lt;= 2'h2;</span></a>
+<a name="2566"><span class="lineNum">    2566 </span><span class="lineCov">        136 :       ctrs_24_1 &lt;= 2'h2;</span></a>
+<a name="2567"><span class="lineNum">    2567 </span><span class="lineCov">        136 :       ctrs_25_0 &lt;= 2'h2;</span></a>
+<a name="2568"><span class="lineNum">    2568 </span><span class="lineCov">        136 :       ctrs_25_1 &lt;= 2'h2;</span></a>
+<a name="2569"><span class="lineNum">    2569 </span><span class="lineCov">        136 :       ctrs_26_0 &lt;= 2'h2;</span></a>
+<a name="2570"><span class="lineNum">    2570 </span><span class="lineCov">        136 :       ctrs_26_1 &lt;= 2'h2;</span></a>
+<a name="2571"><span class="lineNum">    2571 </span><span class="lineCov">        136 :       ctrs_27_0 &lt;= 2'h2;</span></a>
+<a name="2572"><span class="lineNum">    2572 </span><span class="lineCov">        136 :       ctrs_27_1 &lt;= 2'h2;</span></a>
+<a name="2573"><span class="lineNum">    2573 </span><span class="lineCov">        136 :       ctrs_28_0 &lt;= 2'h2;</span></a>
+<a name="2574"><span class="lineNum">    2574 </span><span class="lineCov">        136 :       ctrs_28_1 &lt;= 2'h2;</span></a>
+<a name="2575"><span class="lineNum">    2575 </span><span class="lineCov">        136 :       ctrs_29_0 &lt;= 2'h2;</span></a>
+<a name="2576"><span class="lineNum">    2576 </span><span class="lineCov">        136 :       ctrs_29_1 &lt;= 2'h2;</span></a>
+<a name="2577"><span class="lineNum">    2577 </span><span class="lineCov">        136 :       ctrs_30_0 &lt;= 2'h2;</span></a>
+<a name="2578"><span class="lineNum">    2578 </span><span class="lineCov">        136 :       ctrs_30_1 &lt;= 2'h2;</span></a>
+<a name="2579"><span class="lineNum">    2579 </span><span class="lineCov">        136 :       ctrs_31_0 &lt;= 2'h2;</span></a>
+<a name="2580"><span class="lineNum">    2580 </span><span class="lineCov">        136 :       ctrs_31_1 &lt;= 2'h2;</span></a>
+<a name="2581"><span class="lineNum">    2581 </span><span class="lineCov">        136 :       state_reg &lt;= 31'h0;</span></a>
+<a name="2582"><span class="lineNum">    2582 </span>            :     end</a>
+<a name="2583"><span class="lineNum">    2583 </span><span class="lineCov">      63729 :     else begin</span></a>
+<a name="2584"><span class="lineNum">    2584 </span><span class="lineCov">          2 :       if (u_s1_ways_write_valid_0 &amp; u_s1_br_update_valids_0) begin</span></a>
+<a name="2585"><span class="lineNum">    2585 </span><span class="lineNoCov">          0 :         if ((&amp;ctrs_0_0) &amp; u_s1_br_takens_0)</span></a>
+<a name="2586"><span class="lineNum">    2586 </span><span class="lineNoCov">          0 :           ctrs_0_0 &lt;= 2'h3;</span></a>
+<a name="2587"><span class="lineNum">    2587 </span><span class="lineNoCov">          0 :         else if (ctrs_0_0 == 2'h0 &amp; ~u_s1_br_takens_0)</span></a>
+<a name="2588"><span class="lineNum">    2588 </span><span class="lineNoCov">          0 :           ctrs_0_0 &lt;= 2'h0;</span></a>
+<a name="2589"><span class="lineNum">    2589 </span><span class="lineNoCov">          0 :         else if (u_s1_br_takens_0)</span></a>
+<a name="2590"><span class="lineNum">    2590 </span><span class="lineCov">          1 :           ctrs_0_0 &lt;= 2'(ctrs_0_0 + 2'h1);</span></a>
+<a name="2591"><span class="lineNum">    2591 </span>            :         else</a>
+<a name="2592"><span class="lineNum">    2592 </span><span class="lineNoCov">          0 :           ctrs_0_0 &lt;= 2'(ctrs_0_0 - 2'h1);</span></a>
+<a name="2593"><span class="lineNum">    2593 </span>            :       end</a>
+<a name="2594"><span class="lineNum">    2594 </span><span class="lineCov">          4 :       if (u_s1_ways_write_valid_0 &amp; u_s1_br_update_valids_1) begin</span></a>
+<a name="2595"><span class="lineNum">    2595 </span><span class="lineNoCov">          0 :         if ((&amp;ctrs_0_1) &amp; u_s1_br_takens_1)</span></a>
+<a name="2596"><span class="lineNum">    2596 </span><span class="lineNoCov">          0 :           ctrs_0_1 &lt;= 2'h3;</span></a>
+<a name="2597"><span class="lineNum">    2597 </span><span class="lineCov">          2 :         else if (ctrs_0_1 == 2'h0 &amp; ~u_s1_br_takens_1)</span></a>
+<a name="2598"><span class="lineNum">    2598 </span><span class="lineCov">          1 :           ctrs_0_1 &lt;= 2'h0;</span></a>
+<a name="2599"><span class="lineNum">    2599 </span><span class="lineNoCov">          0 :         else if (u_s1_br_takens_1)</span></a>
+<a name="2600"><span class="lineNum">    2600 </span><span class="lineNoCov">          0 :           ctrs_0_1 &lt;= 2'(ctrs_0_1 + 2'h1);</span></a>
+<a name="2601"><span class="lineNum">    2601 </span>            :         else</a>
+<a name="2602"><span class="lineNum">    2602 </span><span class="lineCov">          1 :           ctrs_0_1 &lt;= 2'(ctrs_0_1 - 2'h1);</span></a>
+<a name="2603"><span class="lineNum">    2603 </span>            :       end</a>
+<a name="2604"><span class="lineNum">    2604 </span><span class="lineCov">          2 :       if (u_s1_ways_write_valid_1 &amp; u_s1_br_update_valids_0) begin</span></a>
+<a name="2605"><span class="lineNum">    2605 </span><span class="lineNoCov">          0 :         if ((&amp;ctrs_1_0) &amp; u_s1_br_takens_0)</span></a>
+<a name="2606"><span class="lineNum">    2606 </span><span class="lineNoCov">          0 :           ctrs_1_0 &lt;= 2'h3;</span></a>
+<a name="2607"><span class="lineNum">    2607 </span><span class="lineNoCov">          0 :         else if (ctrs_1_0 == 2'h0 &amp; ~u_s1_br_takens_0)</span></a>
+<a name="2608"><span class="lineNum">    2608 </span><span class="lineNoCov">          0 :           ctrs_1_0 &lt;= 2'h0;</span></a>
+<a name="2609"><span class="lineNum">    2609 </span><span class="lineNoCov">          0 :         else if (u_s1_br_takens_0)</span></a>
+<a name="2610"><span class="lineNum">    2610 </span><span class="lineCov">          1 :           ctrs_1_0 &lt;= 2'(ctrs_1_0 + 2'h1);</span></a>
+<a name="2611"><span class="lineNum">    2611 </span>            :         else</a>
+<a name="2612"><span class="lineNum">    2612 </span><span class="lineNoCov">          0 :           ctrs_1_0 &lt;= 2'(ctrs_1_0 - 2'h1);</span></a>
+<a name="2613"><span class="lineNum">    2613 </span>            :       end</a>
+<a name="2614"><span class="lineNum">    2614 </span><span class="lineCov">          2 :       if (u_s1_ways_write_valid_1 &amp; u_s1_br_update_valids_1) begin</span></a>
+<a name="2615"><span class="lineNum">    2615 </span><span class="lineNoCov">          0 :         if ((&amp;ctrs_1_1) &amp; u_s1_br_takens_1)</span></a>
+<a name="2616"><span class="lineNum">    2616 </span><span class="lineNoCov">          0 :           ctrs_1_1 &lt;= 2'h3;</span></a>
+<a name="2617"><span class="lineNum">    2617 </span><span class="lineNoCov">          0 :         else if (ctrs_1_1 == 2'h0 &amp; ~u_s1_br_takens_1)</span></a>
+<a name="2618"><span class="lineNum">    2618 </span><span class="lineNoCov">          0 :           ctrs_1_1 &lt;= 2'h0;</span></a>
+<a name="2619"><span class="lineNum">    2619 </span><span class="lineNoCov">          0 :         else if (u_s1_br_takens_1)</span></a>
+<a name="2620"><span class="lineNum">    2620 </span><span class="lineNoCov">          0 :           ctrs_1_1 &lt;= 2'(ctrs_1_1 + 2'h1);</span></a>
+<a name="2621"><span class="lineNum">    2621 </span>            :         else</a>
+<a name="2622"><span class="lineNum">    2622 </span><span class="lineCov">          1 :           ctrs_1_1 &lt;= 2'(ctrs_1_1 - 2'h1);</span></a>
+<a name="2623"><span class="lineNum">    2623 </span>            :       end</a>
+<a name="2624"><span class="lineNum">    2624 </span><span class="lineNoCov">          0 :       if (u_s1_ways_write_valid_2 &amp; u_s1_br_update_valids_0) begin</span></a>
+<a name="2625"><span class="lineNum">    2625 </span><span class="lineNoCov">          0 :         if ((&amp;ctrs_2_0) &amp; u_s1_br_takens_0)</span></a>
+<a name="2626"><span class="lineNum">    2626 </span><span class="lineNoCov">          0 :           ctrs_2_0 &lt;= 2'h3;</span></a>
+<a name="2627"><span class="lineNum">    2627 </span><span class="lineNoCov">          0 :         else if (ctrs_2_0 == 2'h0 &amp; ~u_s1_br_takens_0)</span></a>
+<a name="2628"><span class="lineNum">    2628 </span><span class="lineNoCov">          0 :           ctrs_2_0 &lt;= 2'h0;</span></a>
+<a name="2629"><span class="lineNum">    2629 </span><span class="lineNoCov">          0 :         else if (u_s1_br_takens_0)</span></a>
+<a name="2630"><span class="lineNum">    2630 </span><span class="lineNoCov">          0 :           ctrs_2_0 &lt;= 2'(ctrs_2_0 + 2'h1);</span></a>
+<a name="2631"><span class="lineNum">    2631 </span>            :         else</a>
+<a name="2632"><span class="lineNum">    2632 </span><span class="lineNoCov">          0 :           ctrs_2_0 &lt;= 2'(ctrs_2_0 - 2'h1);</span></a>
+<a name="2633"><span class="lineNum">    2633 </span>            :       end</a>
+<a name="2634"><span class="lineNum">    2634 </span><span class="lineNoCov">          0 :       if (u_s1_ways_write_valid_2 &amp; u_s1_br_update_valids_1) begin</span></a>
+<a name="2635"><span class="lineNum">    2635 </span><span class="lineNoCov">          0 :         if ((&amp;ctrs_2_1) &amp; u_s1_br_takens_1)</span></a>
+<a name="2636"><span class="lineNum">    2636 </span><span class="lineNoCov">          0 :           ctrs_2_1 &lt;= 2'h3;</span></a>
+<a name="2637"><span class="lineNum">    2637 </span><span class="lineNoCov">          0 :         else if (ctrs_2_1 == 2'h0 &amp; ~u_s1_br_takens_1)</span></a>
+<a name="2638"><span class="lineNum">    2638 </span><span class="lineNoCov">          0 :           ctrs_2_1 &lt;= 2'h0;</span></a>
+<a name="2639"><span class="lineNum">    2639 </span><span class="lineNoCov">          0 :         else if (u_s1_br_takens_1)</span></a>
+<a name="2640"><span class="lineNum">    2640 </span><span class="lineNoCov">          0 :           ctrs_2_1 &lt;= 2'(ctrs_2_1 + 2'h1);</span></a>
+<a name="2641"><span class="lineNum">    2641 </span>            :         else</a>
+<a name="2642"><span class="lineNum">    2642 </span><span class="lineNoCov">          0 :           ctrs_2_1 &lt;= 2'(ctrs_2_1 - 2'h1);</span></a>
+<a name="2643"><span class="lineNum">    2643 </span>            :       end</a>
+<a name="2644"><span class="lineNum">    2644 </span><span class="lineNoCov">          0 :       if (u_s1_ways_write_valid_3 &amp; u_s1_br_update_valids_0) begin</span></a>
+<a name="2645"><span class="lineNum">    2645 </span><span class="lineNoCov">          0 :         if ((&amp;ctrs_3_0) &amp; u_s1_br_takens_0)</span></a>
+<a name="2646"><span class="lineNum">    2646 </span><span class="lineNoCov">          0 :           ctrs_3_0 &lt;= 2'h3;</span></a>
+<a name="2647"><span class="lineNum">    2647 </span><span class="lineNoCov">          0 :         else if (ctrs_3_0 == 2'h0 &amp; ~u_s1_br_takens_0)</span></a>
+<a name="2648"><span class="lineNum">    2648 </span><span class="lineNoCov">          0 :           ctrs_3_0 &lt;= 2'h0;</span></a>
+<a name="2649"><span class="lineNum">    2649 </span><span class="lineNoCov">          0 :         else if (u_s1_br_takens_0)</span></a>
+<a name="2650"><span class="lineNum">    2650 </span><span class="lineNoCov">          0 :           ctrs_3_0 &lt;= 2'(ctrs_3_0 + 2'h1);</span></a>
+<a name="2651"><span class="lineNum">    2651 </span>            :         else</a>
+<a name="2652"><span class="lineNum">    2652 </span><span class="lineNoCov">          0 :           ctrs_3_0 &lt;= 2'(ctrs_3_0 - 2'h1);</span></a>
+<a name="2653"><span class="lineNum">    2653 </span>            :       end</a>
+<a name="2654"><span class="lineNum">    2654 </span><span class="lineCov">          4 :       if (u_s1_ways_write_valid_3 &amp; u_s1_br_update_valids_1) begin</span></a>
+<a name="2655"><span class="lineNum">    2655 </span><span class="lineNoCov">          0 :         if ((&amp;ctrs_3_1) &amp; u_s1_br_takens_1)</span></a>
+<a name="2656"><span class="lineNum">    2656 </span><span class="lineNoCov">          0 :           ctrs_3_1 &lt;= 2'h3;</span></a>
+<a name="2657"><span class="lineNum">    2657 </span><span class="lineNoCov">          0 :         else if (ctrs_3_1 == 2'h0 &amp; ~u_s1_br_takens_1)</span></a>
+<a name="2658"><span class="lineNum">    2658 </span><span class="lineNoCov">          0 :           ctrs_3_1 &lt;= 2'h0;</span></a>
+<a name="2659"><span class="lineNum">    2659 </span><span class="lineNoCov">          0 :         else if (u_s1_br_takens_1)</span></a>
+<a name="2660"><span class="lineNum">    2660 </span><span class="lineNoCov">          0 :           ctrs_3_1 &lt;= 2'(ctrs_3_1 + 2'h1);</span></a>
+<a name="2661"><span class="lineNum">    2661 </span>            :         else</a>
+<a name="2662"><span class="lineNum">    2662 </span><span class="lineCov">          2 :           ctrs_3_1 &lt;= 2'(ctrs_3_1 - 2'h1);</span></a>
+<a name="2663"><span class="lineNum">    2663 </span>            :       end</a>
+<a name="2664"><span class="lineNum">    2664 </span><span class="lineCov">          2 :       if (u_s1_ways_write_valid_4 &amp; u_s1_br_update_valids_0) begin</span></a>
+<a name="2665"><span class="lineNum">    2665 </span><span class="lineNoCov">          0 :         if ((&amp;ctrs_4_0) &amp; u_s1_br_takens_0)</span></a>
+<a name="2666"><span class="lineNum">    2666 </span><span class="lineNoCov">          0 :           ctrs_4_0 &lt;= 2'h3;</span></a>
+<a name="2667"><span class="lineNum">    2667 </span><span class="lineNoCov">          0 :         else if (ctrs_4_0 == 2'h0 &amp; ~u_s1_br_takens_0)</span></a>
+<a name="2668"><span class="lineNum">    2668 </span><span class="lineNoCov">          0 :           ctrs_4_0 &lt;= 2'h0;</span></a>
+<a name="2669"><span class="lineNum">    2669 </span><span class="lineNoCov">          0 :         else if (u_s1_br_takens_0)</span></a>
+<a name="2670"><span class="lineNum">    2670 </span><span class="lineCov">          1 :           ctrs_4_0 &lt;= 2'(ctrs_4_0 + 2'h1);</span></a>
+<a name="2671"><span class="lineNum">    2671 </span>            :         else</a>
+<a name="2672"><span class="lineNum">    2672 </span><span class="lineNoCov">          0 :           ctrs_4_0 &lt;= 2'(ctrs_4_0 - 2'h1);</span></a>
+<a name="2673"><span class="lineNum">    2673 </span>            :       end</a>
+<a name="2674"><span class="lineNum">    2674 </span><span class="lineNoCov">          0 :       if (u_s1_ways_write_valid_4 &amp; u_s1_br_update_valids_1) begin</span></a>
+<a name="2675"><span class="lineNum">    2675 </span><span class="lineNoCov">          0 :         if ((&amp;ctrs_4_1) &amp; u_s1_br_takens_1)</span></a>
+<a name="2676"><span class="lineNum">    2676 </span><span class="lineNoCov">          0 :           ctrs_4_1 &lt;= 2'h3;</span></a>
+<a name="2677"><span class="lineNum">    2677 </span><span class="lineNoCov">          0 :         else if (ctrs_4_1 == 2'h0 &amp; ~u_s1_br_takens_1)</span></a>
+<a name="2678"><span class="lineNum">    2678 </span><span class="lineNoCov">          0 :           ctrs_4_1 &lt;= 2'h0;</span></a>
+<a name="2679"><span class="lineNum">    2679 </span><span class="lineNoCov">          0 :         else if (u_s1_br_takens_1)</span></a>
+<a name="2680"><span class="lineNum">    2680 </span><span class="lineNoCov">          0 :           ctrs_4_1 &lt;= 2'(ctrs_4_1 + 2'h1);</span></a>
+<a name="2681"><span class="lineNum">    2681 </span>            :         else</a>
+<a name="2682"><span class="lineNum">    2682 </span><span class="lineNoCov">          0 :           ctrs_4_1 &lt;= 2'(ctrs_4_1 - 2'h1);</span></a>
+<a name="2683"><span class="lineNum">    2683 </span>            :       end</a>
+<a name="2684"><span class="lineNum">    2684 </span><span class="lineCov">          2 :       if (u_s1_ways_write_valid_5 &amp; u_s1_br_update_valids_0) begin</span></a>
+<a name="2685"><span class="lineNum">    2685 </span><span class="lineNoCov">          0 :         if ((&amp;ctrs_5_0) &amp; u_s1_br_takens_0)</span></a>
+<a name="2686"><span class="lineNum">    2686 </span><span class="lineNoCov">          0 :           ctrs_5_0 &lt;= 2'h3;</span></a>
+<a name="2687"><span class="lineNum">    2687 </span><span class="lineNoCov">          0 :         else if (ctrs_5_0 == 2'h0 &amp; ~u_s1_br_takens_0)</span></a>
+<a name="2688"><span class="lineNum">    2688 </span><span class="lineNoCov">          0 :           ctrs_5_0 &lt;= 2'h0;</span></a>
+<a name="2689"><span class="lineNum">    2689 </span><span class="lineNoCov">          0 :         else if (u_s1_br_takens_0)</span></a>
+<a name="2690"><span class="lineNum">    2690 </span><span class="lineCov">          1 :           ctrs_5_0 &lt;= 2'(ctrs_5_0 + 2'h1);</span></a>
+<a name="2691"><span class="lineNum">    2691 </span>            :         else</a>
+<a name="2692"><span class="lineNum">    2692 </span><span class="lineNoCov">          0 :           ctrs_5_0 &lt;= 2'(ctrs_5_0 - 2'h1);</span></a>
+<a name="2693"><span class="lineNum">    2693 </span>            :       end</a>
+<a name="2694"><span class="lineNum">    2694 </span><span class="lineCov">          4 :       if (u_s1_ways_write_valid_5 &amp; u_s1_br_update_valids_1) begin</span></a>
+<a name="2695"><span class="lineNum">    2695 </span><span class="lineNoCov">          0 :         if ((&amp;ctrs_5_1) &amp; u_s1_br_takens_1)</span></a>
+<a name="2696"><span class="lineNum">    2696 </span><span class="lineNoCov">          0 :           ctrs_5_1 &lt;= 2'h3;</span></a>
+<a name="2697"><span class="lineNum">    2697 </span><span class="lineNoCov">          0 :         else if (ctrs_5_1 == 2'h0 &amp; ~u_s1_br_takens_1)</span></a>
+<a name="2698"><span class="lineNum">    2698 </span><span class="lineNoCov">          0 :           ctrs_5_1 &lt;= 2'h0;</span></a>
+<a name="2699"><span class="lineNum">    2699 </span><span class="lineNoCov">          0 :         else if (u_s1_br_takens_1)</span></a>
+<a name="2700"><span class="lineNum">    2700 </span><span class="lineNoCov">          0 :           ctrs_5_1 &lt;= 2'(ctrs_5_1 + 2'h1);</span></a>
+<a name="2701"><span class="lineNum">    2701 </span>            :         else</a>
+<a name="2702"><span class="lineNum">    2702 </span><span class="lineCov">          2 :           ctrs_5_1 &lt;= 2'(ctrs_5_1 - 2'h1);</span></a>
+<a name="2703"><span class="lineNum">    2703 </span>            :       end</a>
+<a name="2704"><span class="lineNum">    2704 </span><span class="lineNoCov">          0 :       if (u_s1_ways_write_valid_6 &amp; u_s1_br_update_valids_0) begin</span></a>
+<a name="2705"><span class="lineNum">    2705 </span><span class="lineNoCov">          0 :         if ((&amp;ctrs_6_0) &amp; u_s1_br_takens_0)</span></a>
+<a name="2706"><span class="lineNum">    2706 </span><span class="lineNoCov">          0 :           ctrs_6_0 &lt;= 2'h3;</span></a>
+<a name="2707"><span class="lineNum">    2707 </span><span class="lineNoCov">          0 :         else if (ctrs_6_0 == 2'h0 &amp; ~u_s1_br_takens_0)</span></a>
+<a name="2708"><span class="lineNum">    2708 </span><span class="lineNoCov">          0 :           ctrs_6_0 &lt;= 2'h0;</span></a>
+<a name="2709"><span class="lineNum">    2709 </span><span class="lineNoCov">          0 :         else if (u_s1_br_takens_0)</span></a>
+<a name="2710"><span class="lineNum">    2710 </span><span class="lineNoCov">          0 :           ctrs_6_0 &lt;= 2'(ctrs_6_0 + 2'h1);</span></a>
+<a name="2711"><span class="lineNum">    2711 </span>            :         else</a>
+<a name="2712"><span class="lineNum">    2712 </span><span class="lineNoCov">          0 :           ctrs_6_0 &lt;= 2'(ctrs_6_0 - 2'h1);</span></a>
+<a name="2713"><span class="lineNum">    2713 </span>            :       end</a>
+<a name="2714"><span class="lineNum">    2714 </span><span class="lineCov">          2 :       if (u_s1_ways_write_valid_6 &amp; u_s1_br_update_valids_1) begin</span></a>
+<a name="2715"><span class="lineNum">    2715 </span><span class="lineNoCov">          0 :         if ((&amp;ctrs_6_1) &amp; u_s1_br_takens_1)</span></a>
+<a name="2716"><span class="lineNum">    2716 </span><span class="lineNoCov">          0 :           ctrs_6_1 &lt;= 2'h3;</span></a>
+<a name="2717"><span class="lineNum">    2717 </span><span class="lineCov">          2 :         else if (ctrs_6_1 == 2'h0 &amp; ~u_s1_br_takens_1)</span></a>
+<a name="2718"><span class="lineNum">    2718 </span><span class="lineCov">          1 :           ctrs_6_1 &lt;= 2'h0;</span></a>
+<a name="2719"><span class="lineNum">    2719 </span><span class="lineNoCov">          0 :         else if (u_s1_br_takens_1)</span></a>
+<a name="2720"><span class="lineNum">    2720 </span><span class="lineNoCov">          0 :           ctrs_6_1 &lt;= 2'(ctrs_6_1 + 2'h1);</span></a>
+<a name="2721"><span class="lineNum">    2721 </span>            :         else</a>
+<a name="2722"><span class="lineNum">    2722 </span><span class="lineNoCov">          0 :           ctrs_6_1 &lt;= 2'(ctrs_6_1 - 2'h1);</span></a>
+<a name="2723"><span class="lineNum">    2723 </span>            :       end</a>
+<a name="2724"><span class="lineNum">    2724 </span><span class="lineCov">          2 :       if (u_s1_ways_write_valid_7 &amp; u_s1_br_update_valids_0) begin</span></a>
+<a name="2725"><span class="lineNum">    2725 </span><span class="lineCov">          2 :         if ((&amp;ctrs_7_0) &amp; u_s1_br_takens_0)</span></a>
+<a name="2726"><span class="lineNum">    2726 </span><span class="lineCov">          1 :           ctrs_7_0 &lt;= 2'h3;</span></a>
+<a name="2727"><span class="lineNum">    2727 </span><span class="lineNoCov">          0 :         else if (ctrs_7_0 == 2'h0 &amp; ~u_s1_br_takens_0)</span></a>
+<a name="2728"><span class="lineNum">    2728 </span><span class="lineNoCov">          0 :           ctrs_7_0 &lt;= 2'h0;</span></a>
+<a name="2729"><span class="lineNum">    2729 </span><span class="lineNoCov">          0 :         else if (u_s1_br_takens_0)</span></a>
+<a name="2730"><span class="lineNum">    2730 </span><span class="lineNoCov">          0 :           ctrs_7_0 &lt;= 2'(ctrs_7_0 + 2'h1);</span></a>
+<a name="2731"><span class="lineNum">    2731 </span>            :         else</a>
+<a name="2732"><span class="lineNum">    2732 </span><span class="lineNoCov">          0 :           ctrs_7_0 &lt;= 2'(ctrs_7_0 - 2'h1);</span></a>
+<a name="2733"><span class="lineNum">    2733 </span>            :       end</a>
+<a name="2734"><span class="lineNum">    2734 </span><span class="lineCov">          2 :       if (u_s1_ways_write_valid_7 &amp; u_s1_br_update_valids_1) begin</span></a>
+<a name="2735"><span class="lineNum">    2735 </span><span class="lineNoCov">          0 :         if ((&amp;ctrs_7_1) &amp; u_s1_br_takens_1)</span></a>
+<a name="2736"><span class="lineNum">    2736 </span><span class="lineNoCov">          0 :           ctrs_7_1 &lt;= 2'h3;</span></a>
+<a name="2737"><span class="lineNum">    2737 </span><span class="lineNoCov">          0 :         else if (ctrs_7_1 == 2'h0 &amp; ~u_s1_br_takens_1)</span></a>
+<a name="2738"><span class="lineNum">    2738 </span><span class="lineNoCov">          0 :           ctrs_7_1 &lt;= 2'h0;</span></a>
+<a name="2739"><span class="lineNum">    2739 </span><span class="lineNoCov">          0 :         else if (u_s1_br_takens_1)</span></a>
+<a name="2740"><span class="lineNum">    2740 </span><span class="lineNoCov">          0 :           ctrs_7_1 &lt;= 2'(ctrs_7_1 + 2'h1);</span></a>
+<a name="2741"><span class="lineNum">    2741 </span>            :         else</a>
+<a name="2742"><span class="lineNum">    2742 </span><span class="lineCov">          1 :           ctrs_7_1 &lt;= 2'(ctrs_7_1 - 2'h1);</span></a>
+<a name="2743"><span class="lineNum">    2743 </span>            :       end</a>
+<a name="2744"><span class="lineNum">    2744 </span><span class="lineNoCov">          0 :       if (u_s1_ways_write_valid_8 &amp; u_s1_br_update_valids_0) begin</span></a>
+<a name="2745"><span class="lineNum">    2745 </span><span class="lineNoCov">          0 :         if ((&amp;ctrs_8_0) &amp; u_s1_br_takens_0)</span></a>
+<a name="2746"><span class="lineNum">    2746 </span><span class="lineNoCov">          0 :           ctrs_8_0 &lt;= 2'h3;</span></a>
+<a name="2747"><span class="lineNum">    2747 </span><span class="lineNoCov">          0 :         else if (ctrs_8_0 == 2'h0 &amp; ~u_s1_br_takens_0)</span></a>
+<a name="2748"><span class="lineNum">    2748 </span><span class="lineNoCov">          0 :           ctrs_8_0 &lt;= 2'h0;</span></a>
+<a name="2749"><span class="lineNum">    2749 </span><span class="lineNoCov">          0 :         else if (u_s1_br_takens_0)</span></a>
+<a name="2750"><span class="lineNum">    2750 </span><span class="lineNoCov">          0 :           ctrs_8_0 &lt;= 2'(ctrs_8_0 + 2'h1);</span></a>
+<a name="2751"><span class="lineNum">    2751 </span>            :         else</a>
+<a name="2752"><span class="lineNum">    2752 </span><span class="lineNoCov">          0 :           ctrs_8_0 &lt;= 2'(ctrs_8_0 - 2'h1);</span></a>
+<a name="2753"><span class="lineNum">    2753 </span>            :       end</a>
+<a name="2754"><span class="lineNum">    2754 </span><span class="lineNoCov">          0 :       if (u_s1_ways_write_valid_8 &amp; u_s1_br_update_valids_1) begin</span></a>
+<a name="2755"><span class="lineNum">    2755 </span><span class="lineNoCov">          0 :         if ((&amp;ctrs_8_1) &amp; u_s1_br_takens_1)</span></a>
+<a name="2756"><span class="lineNum">    2756 </span><span class="lineNoCov">          0 :           ctrs_8_1 &lt;= 2'h3;</span></a>
+<a name="2757"><span class="lineNum">    2757 </span><span class="lineNoCov">          0 :         else if (ctrs_8_1 == 2'h0 &amp; ~u_s1_br_takens_1)</span></a>
+<a name="2758"><span class="lineNum">    2758 </span><span class="lineNoCov">          0 :           ctrs_8_1 &lt;= 2'h0;</span></a>
+<a name="2759"><span class="lineNum">    2759 </span><span class="lineNoCov">          0 :         else if (u_s1_br_takens_1)</span></a>
+<a name="2760"><span class="lineNum">    2760 </span><span class="lineNoCov">          0 :           ctrs_8_1 &lt;= 2'(ctrs_8_1 + 2'h1);</span></a>
+<a name="2761"><span class="lineNum">    2761 </span>            :         else</a>
+<a name="2762"><span class="lineNum">    2762 </span><span class="lineNoCov">          0 :           ctrs_8_1 &lt;= 2'(ctrs_8_1 - 2'h1);</span></a>
+<a name="2763"><span class="lineNum">    2763 </span>            :       end</a>
+<a name="2764"><span class="lineNum">    2764 </span><span class="lineNoCov">          0 :       if (u_s1_ways_write_valid_9 &amp; u_s1_br_update_valids_0) begin</span></a>
+<a name="2765"><span class="lineNum">    2765 </span><span class="lineNoCov">          0 :         if ((&amp;ctrs_9_0) &amp; u_s1_br_takens_0)</span></a>
+<a name="2766"><span class="lineNum">    2766 </span><span class="lineNoCov">          0 :           ctrs_9_0 &lt;= 2'h3;</span></a>
+<a name="2767"><span class="lineNum">    2767 </span><span class="lineNoCov">          0 :         else if (ctrs_9_0 == 2'h0 &amp; ~u_s1_br_takens_0)</span></a>
+<a name="2768"><span class="lineNum">    2768 </span><span class="lineNoCov">          0 :           ctrs_9_0 &lt;= 2'h0;</span></a>
+<a name="2769"><span class="lineNum">    2769 </span><span class="lineNoCov">          0 :         else if (u_s1_br_takens_0)</span></a>
+<a name="2770"><span class="lineNum">    2770 </span><span class="lineNoCov">          0 :           ctrs_9_0 &lt;= 2'(ctrs_9_0 + 2'h1);</span></a>
+<a name="2771"><span class="lineNum">    2771 </span>            :         else</a>
+<a name="2772"><span class="lineNum">    2772 </span><span class="lineNoCov">          0 :           ctrs_9_0 &lt;= 2'(ctrs_9_0 - 2'h1);</span></a>
+<a name="2773"><span class="lineNum">    2773 </span>            :       end</a>
+<a name="2774"><span class="lineNum">    2774 </span><span class="lineCov">          4 :       if (u_s1_ways_write_valid_9 &amp; u_s1_br_update_valids_1) begin</span></a>
+<a name="2775"><span class="lineNum">    2775 </span><span class="lineNoCov">          0 :         if ((&amp;ctrs_9_1) &amp; u_s1_br_takens_1)</span></a>
+<a name="2776"><span class="lineNum">    2776 </span><span class="lineNoCov">          0 :           ctrs_9_1 &lt;= 2'h3;</span></a>
+<a name="2777"><span class="lineNum">    2777 </span><span class="lineCov">          2 :         else if (ctrs_9_1 == 2'h0 &amp; ~u_s1_br_takens_1)</span></a>
+<a name="2778"><span class="lineNum">    2778 </span><span class="lineCov">          1 :           ctrs_9_1 &lt;= 2'h0;</span></a>
+<a name="2779"><span class="lineNum">    2779 </span><span class="lineNoCov">          0 :         else if (u_s1_br_takens_1)</span></a>
+<a name="2780"><span class="lineNum">    2780 </span><span class="lineNoCov">          0 :           ctrs_9_1 &lt;= 2'(ctrs_9_1 + 2'h1);</span></a>
+<a name="2781"><span class="lineNum">    2781 </span>            :         else</a>
+<a name="2782"><span class="lineNum">    2782 </span><span class="lineCov">          1 :           ctrs_9_1 &lt;= 2'(ctrs_9_1 - 2'h1);</span></a>
+<a name="2783"><span class="lineNum">    2783 </span>            :       end</a>
+<a name="2784"><span class="lineNum">    2784 </span><span class="lineCov">          2 :       if (u_s1_ways_write_valid_10 &amp; u_s1_br_update_valids_0) begin</span></a>
+<a name="2785"><span class="lineNum">    2785 </span><span class="lineNoCov">          0 :         if ((&amp;ctrs_10_0) &amp; u_s1_br_takens_0)</span></a>
+<a name="2786"><span class="lineNum">    2786 </span><span class="lineNoCov">          0 :           ctrs_10_0 &lt;= 2'h3;</span></a>
+<a name="2787"><span class="lineNum">    2787 </span><span class="lineNoCov">          0 :         else if (ctrs_10_0 == 2'h0 &amp; ~u_s1_br_takens_0)</span></a>
+<a name="2788"><span class="lineNum">    2788 </span><span class="lineNoCov">          0 :           ctrs_10_0 &lt;= 2'h0;</span></a>
+<a name="2789"><span class="lineNum">    2789 </span><span class="lineNoCov">          0 :         else if (u_s1_br_takens_0)</span></a>
+<a name="2790"><span class="lineNum">    2790 </span><span class="lineCov">          1 :           ctrs_10_0 &lt;= 2'(ctrs_10_0 + 2'h1);</span></a>
+<a name="2791"><span class="lineNum">    2791 </span>            :         else</a>
+<a name="2792"><span class="lineNum">    2792 </span><span class="lineNoCov">          0 :           ctrs_10_0 &lt;= 2'(ctrs_10_0 - 2'h1);</span></a>
+<a name="2793"><span class="lineNum">    2793 </span>            :       end</a>
+<a name="2794"><span class="lineNum">    2794 </span><span class="lineCov">          2 :       if (u_s1_ways_write_valid_10 &amp; u_s1_br_update_valids_1) begin</span></a>
+<a name="2795"><span class="lineNum">    2795 </span><span class="lineNoCov">          0 :         if ((&amp;ctrs_10_1) &amp; u_s1_br_takens_1)</span></a>
+<a name="2796"><span class="lineNum">    2796 </span><span class="lineNoCov">          0 :           ctrs_10_1 &lt;= 2'h3;</span></a>
+<a name="2797"><span class="lineNum">    2797 </span><span class="lineNoCov">          0 :         else if (ctrs_10_1 == 2'h0 &amp; ~u_s1_br_takens_1)</span></a>
+<a name="2798"><span class="lineNum">    2798 </span><span class="lineNoCov">          0 :           ctrs_10_1 &lt;= 2'h0;</span></a>
+<a name="2799"><span class="lineNum">    2799 </span><span class="lineNoCov">          0 :         else if (u_s1_br_takens_1)</span></a>
+<a name="2800"><span class="lineNum">    2800 </span><span class="lineNoCov">          0 :           ctrs_10_1 &lt;= 2'(ctrs_10_1 + 2'h1);</span></a>
+<a name="2801"><span class="lineNum">    2801 </span>            :         else</a>
+<a name="2802"><span class="lineNum">    2802 </span><span class="lineCov">          1 :           ctrs_10_1 &lt;= 2'(ctrs_10_1 - 2'h1);</span></a>
+<a name="2803"><span class="lineNum">    2803 </span>            :       end</a>
+<a name="2804"><span class="lineNum">    2804 </span><span class="lineCov">          2 :       if (u_s1_ways_write_valid_11 &amp; u_s1_br_update_valids_0) begin</span></a>
+<a name="2805"><span class="lineNum">    2805 </span><span class="lineNoCov">          0 :         if ((&amp;ctrs_11_0) &amp; u_s1_br_takens_0)</span></a>
+<a name="2806"><span class="lineNum">    2806 </span><span class="lineNoCov">          0 :           ctrs_11_0 &lt;= 2'h3;</span></a>
+<a name="2807"><span class="lineNum">    2807 </span><span class="lineNoCov">          0 :         else if (ctrs_11_0 == 2'h0 &amp; ~u_s1_br_takens_0)</span></a>
+<a name="2808"><span class="lineNum">    2808 </span><span class="lineNoCov">          0 :           ctrs_11_0 &lt;= 2'h0;</span></a>
+<a name="2809"><span class="lineNum">    2809 </span><span class="lineNoCov">          0 :         else if (u_s1_br_takens_0)</span></a>
+<a name="2810"><span class="lineNum">    2810 </span><span class="lineCov">          1 :           ctrs_11_0 &lt;= 2'(ctrs_11_0 + 2'h1);</span></a>
+<a name="2811"><span class="lineNum">    2811 </span>            :         else</a>
+<a name="2812"><span class="lineNum">    2812 </span><span class="lineNoCov">          0 :           ctrs_11_0 &lt;= 2'(ctrs_11_0 - 2'h1);</span></a>
+<a name="2813"><span class="lineNum">    2813 </span>            :       end</a>
+<a name="2814"><span class="lineNum">    2814 </span><span class="lineCov">          4 :       if (u_s1_ways_write_valid_11 &amp; u_s1_br_update_valids_1) begin</span></a>
+<a name="2815"><span class="lineNum">    2815 </span><span class="lineNoCov">          0 :         if ((&amp;ctrs_11_1) &amp; u_s1_br_takens_1)</span></a>
+<a name="2816"><span class="lineNum">    2816 </span><span class="lineNoCov">          0 :           ctrs_11_1 &lt;= 2'h3;</span></a>
+<a name="2817"><span class="lineNum">    2817 </span><span class="lineNoCov">          0 :         else if (ctrs_11_1 == 2'h0 &amp; ~u_s1_br_takens_1)</span></a>
+<a name="2818"><span class="lineNum">    2818 </span><span class="lineNoCov">          0 :           ctrs_11_1 &lt;= 2'h0;</span></a>
+<a name="2819"><span class="lineNum">    2819 </span><span class="lineNoCov">          0 :         else if (u_s1_br_takens_1)</span></a>
+<a name="2820"><span class="lineNum">    2820 </span><span class="lineNoCov">          0 :           ctrs_11_1 &lt;= 2'(ctrs_11_1 + 2'h1);</span></a>
+<a name="2821"><span class="lineNum">    2821 </span>            :         else</a>
+<a name="2822"><span class="lineNum">    2822 </span><span class="lineCov">          2 :           ctrs_11_1 &lt;= 2'(ctrs_11_1 - 2'h1);</span></a>
+<a name="2823"><span class="lineNum">    2823 </span>            :       end</a>
+<a name="2824"><span class="lineNum">    2824 </span><span class="lineCov">          2 :       if (u_s1_ways_write_valid_12 &amp; u_s1_br_update_valids_0) begin</span></a>
+<a name="2825"><span class="lineNum">    2825 </span><span class="lineCov">          2 :         if ((&amp;ctrs_12_0) &amp; u_s1_br_takens_0)</span></a>
+<a name="2826"><span class="lineNum">    2826 </span><span class="lineCov">          1 :           ctrs_12_0 &lt;= 2'h3;</span></a>
+<a name="2827"><span class="lineNum">    2827 </span><span class="lineNoCov">          0 :         else if (ctrs_12_0 == 2'h0 &amp; ~u_s1_br_takens_0)</span></a>
+<a name="2828"><span class="lineNum">    2828 </span><span class="lineNoCov">          0 :           ctrs_12_0 &lt;= 2'h0;</span></a>
+<a name="2829"><span class="lineNum">    2829 </span><span class="lineNoCov">          0 :         else if (u_s1_br_takens_0)</span></a>
+<a name="2830"><span class="lineNum">    2830 </span><span class="lineNoCov">          0 :           ctrs_12_0 &lt;= 2'(ctrs_12_0 + 2'h1);</span></a>
+<a name="2831"><span class="lineNum">    2831 </span>            :         else</a>
+<a name="2832"><span class="lineNum">    2832 </span><span class="lineNoCov">          0 :           ctrs_12_0 &lt;= 2'(ctrs_12_0 - 2'h1);</span></a>
+<a name="2833"><span class="lineNum">    2833 </span>            :       end</a>
+<a name="2834"><span class="lineNum">    2834 </span><span class="lineCov">          4 :       if (u_s1_ways_write_valid_12 &amp; u_s1_br_update_valids_1) begin</span></a>
+<a name="2835"><span class="lineNum">    2835 </span><span class="lineNoCov">          0 :         if ((&amp;ctrs_12_1) &amp; u_s1_br_takens_1)</span></a>
+<a name="2836"><span class="lineNum">    2836 </span><span class="lineNoCov">          0 :           ctrs_12_1 &lt;= 2'h3;</span></a>
+<a name="2837"><span class="lineNum">    2837 </span><span class="lineCov">          2 :         else if (ctrs_12_1 == 2'h0 &amp; ~u_s1_br_takens_1)</span></a>
+<a name="2838"><span class="lineNum">    2838 </span><span class="lineCov">          1 :           ctrs_12_1 &lt;= 2'h0;</span></a>
+<a name="2839"><span class="lineNum">    2839 </span><span class="lineNoCov">          0 :         else if (u_s1_br_takens_1)</span></a>
+<a name="2840"><span class="lineNum">    2840 </span><span class="lineNoCov">          0 :           ctrs_12_1 &lt;= 2'(ctrs_12_1 + 2'h1);</span></a>
+<a name="2841"><span class="lineNum">    2841 </span>            :         else</a>
+<a name="2842"><span class="lineNum">    2842 </span><span class="lineCov">          1 :           ctrs_12_1 &lt;= 2'(ctrs_12_1 - 2'h1);</span></a>
+<a name="2843"><span class="lineNum">    2843 </span>            :       end</a>
+<a name="2844"><span class="lineNum">    2844 </span><span class="lineNoCov">          0 :       if (u_s1_ways_write_valid_13 &amp; u_s1_br_update_valids_0) begin</span></a>
+<a name="2845"><span class="lineNum">    2845 </span><span class="lineNoCov">          0 :         if ((&amp;ctrs_13_0) &amp; u_s1_br_takens_0)</span></a>
+<a name="2846"><span class="lineNum">    2846 </span><span class="lineNoCov">          0 :           ctrs_13_0 &lt;= 2'h3;</span></a>
+<a name="2847"><span class="lineNum">    2847 </span><span class="lineNoCov">          0 :         else if (ctrs_13_0 == 2'h0 &amp; ~u_s1_br_takens_0)</span></a>
+<a name="2848"><span class="lineNum">    2848 </span><span class="lineNoCov">          0 :           ctrs_13_0 &lt;= 2'h0;</span></a>
+<a name="2849"><span class="lineNum">    2849 </span><span class="lineNoCov">          0 :         else if (u_s1_br_takens_0)</span></a>
+<a name="2850"><span class="lineNum">    2850 </span><span class="lineNoCov">          0 :           ctrs_13_0 &lt;= 2'(ctrs_13_0 + 2'h1);</span></a>
+<a name="2851"><span class="lineNum">    2851 </span>            :         else</a>
+<a name="2852"><span class="lineNum">    2852 </span><span class="lineNoCov">          0 :           ctrs_13_0 &lt;= 2'(ctrs_13_0 - 2'h1);</span></a>
+<a name="2853"><span class="lineNum">    2853 </span>            :       end</a>
+<a name="2854"><span class="lineNum">    2854 </span><span class="lineCov">          2 :       if (u_s1_ways_write_valid_13 &amp; u_s1_br_update_valids_1) begin</span></a>
+<a name="2855"><span class="lineNum">    2855 </span><span class="lineNoCov">          0 :         if ((&amp;ctrs_13_1) &amp; u_s1_br_takens_1)</span></a>
+<a name="2856"><span class="lineNum">    2856 </span><span class="lineNoCov">          0 :           ctrs_13_1 &lt;= 2'h3;</span></a>
+<a name="2857"><span class="lineNum">    2857 </span><span class="lineCov">          2 :         else if (ctrs_13_1 == 2'h0 &amp; ~u_s1_br_takens_1)</span></a>
+<a name="2858"><span class="lineNum">    2858 </span><span class="lineCov">          1 :           ctrs_13_1 &lt;= 2'h0;</span></a>
+<a name="2859"><span class="lineNum">    2859 </span><span class="lineNoCov">          0 :         else if (u_s1_br_takens_1)</span></a>
+<a name="2860"><span class="lineNum">    2860 </span><span class="lineNoCov">          0 :           ctrs_13_1 &lt;= 2'(ctrs_13_1 + 2'h1);</span></a>
+<a name="2861"><span class="lineNum">    2861 </span>            :         else</a>
+<a name="2862"><span class="lineNum">    2862 </span><span class="lineNoCov">          0 :           ctrs_13_1 &lt;= 2'(ctrs_13_1 - 2'h1);</span></a>
+<a name="2863"><span class="lineNum">    2863 </span>            :       end</a>
+<a name="2864"><span class="lineNum">    2864 </span><span class="lineNoCov">          0 :       if (u_s1_ways_write_valid_14 &amp; u_s1_br_update_valids_0) begin</span></a>
+<a name="2865"><span class="lineNum">    2865 </span><span class="lineNoCov">          0 :         if ((&amp;ctrs_14_0) &amp; u_s1_br_takens_0)</span></a>
+<a name="2866"><span class="lineNum">    2866 </span><span class="lineNoCov">          0 :           ctrs_14_0 &lt;= 2'h3;</span></a>
+<a name="2867"><span class="lineNum">    2867 </span><span class="lineNoCov">          0 :         else if (ctrs_14_0 == 2'h0 &amp; ~u_s1_br_takens_0)</span></a>
+<a name="2868"><span class="lineNum">    2868 </span><span class="lineNoCov">          0 :           ctrs_14_0 &lt;= 2'h0;</span></a>
+<a name="2869"><span class="lineNum">    2869 </span><span class="lineNoCov">          0 :         else if (u_s1_br_takens_0)</span></a>
+<a name="2870"><span class="lineNum">    2870 </span><span class="lineNoCov">          0 :           ctrs_14_0 &lt;= 2'(ctrs_14_0 + 2'h1);</span></a>
+<a name="2871"><span class="lineNum">    2871 </span>            :         else</a>
+<a name="2872"><span class="lineNum">    2872 </span><span class="lineNoCov">          0 :           ctrs_14_0 &lt;= 2'(ctrs_14_0 - 2'h1);</span></a>
+<a name="2873"><span class="lineNum">    2873 </span>            :       end</a>
+<a name="2874"><span class="lineNum">    2874 </span><span class="lineCov">          2 :       if (u_s1_ways_write_valid_14 &amp; u_s1_br_update_valids_1) begin</span></a>
+<a name="2875"><span class="lineNum">    2875 </span><span class="lineNoCov">          0 :         if ((&amp;ctrs_14_1) &amp; u_s1_br_takens_1)</span></a>
+<a name="2876"><span class="lineNum">    2876 </span><span class="lineNoCov">          0 :           ctrs_14_1 &lt;= 2'h3;</span></a>
+<a name="2877"><span class="lineNum">    2877 </span><span class="lineCov">          2 :         else if (ctrs_14_1 == 2'h0 &amp; ~u_s1_br_takens_1)</span></a>
+<a name="2878"><span class="lineNum">    2878 </span><span class="lineCov">          1 :           ctrs_14_1 &lt;= 2'h0;</span></a>
+<a name="2879"><span class="lineNum">    2879 </span><span class="lineNoCov">          0 :         else if (u_s1_br_takens_1)</span></a>
+<a name="2880"><span class="lineNum">    2880 </span><span class="lineNoCov">          0 :           ctrs_14_1 &lt;= 2'(ctrs_14_1 + 2'h1);</span></a>
+<a name="2881"><span class="lineNum">    2881 </span>            :         else</a>
+<a name="2882"><span class="lineNum">    2882 </span><span class="lineNoCov">          0 :           ctrs_14_1 &lt;= 2'(ctrs_14_1 - 2'h1);</span></a>
+<a name="2883"><span class="lineNum">    2883 </span>            :       end</a>
+<a name="2884"><span class="lineNum">    2884 </span><span class="lineNoCov">          0 :       if (u_s1_ways_write_valid_15 &amp; u_s1_br_update_valids_0) begin</span></a>
+<a name="2885"><span class="lineNum">    2885 </span><span class="lineNoCov">          0 :         if ((&amp;ctrs_15_0) &amp; u_s1_br_takens_0)</span></a>
+<a name="2886"><span class="lineNum">    2886 </span><span class="lineNoCov">          0 :           ctrs_15_0 &lt;= 2'h3;</span></a>
+<a name="2887"><span class="lineNum">    2887 </span><span class="lineNoCov">          0 :         else if (ctrs_15_0 == 2'h0 &amp; ~u_s1_br_takens_0)</span></a>
+<a name="2888"><span class="lineNum">    2888 </span><span class="lineNoCov">          0 :           ctrs_15_0 &lt;= 2'h0;</span></a>
+<a name="2889"><span class="lineNum">    2889 </span><span class="lineNoCov">          0 :         else if (u_s1_br_takens_0)</span></a>
+<a name="2890"><span class="lineNum">    2890 </span><span class="lineNoCov">          0 :           ctrs_15_0 &lt;= 2'(ctrs_15_0 + 2'h1);</span></a>
+<a name="2891"><span class="lineNum">    2891 </span>            :         else</a>
+<a name="2892"><span class="lineNum">    2892 </span><span class="lineNoCov">          0 :           ctrs_15_0 &lt;= 2'(ctrs_15_0 - 2'h1);</span></a>
+<a name="2893"><span class="lineNum">    2893 </span>            :       end</a>
+<a name="2894"><span class="lineNum">    2894 </span><span class="lineCov">          2 :       if (u_s1_ways_write_valid_15 &amp; u_s1_br_update_valids_1) begin</span></a>
+<a name="2895"><span class="lineNum">    2895 </span><span class="lineNoCov">          0 :         if ((&amp;ctrs_15_1) &amp; u_s1_br_takens_1)</span></a>
+<a name="2896"><span class="lineNum">    2896 </span><span class="lineNoCov">          0 :           ctrs_15_1 &lt;= 2'h3;</span></a>
+<a name="2897"><span class="lineNum">    2897 </span><span class="lineCov">          2 :         else if (ctrs_15_1 == 2'h0 &amp; ~u_s1_br_takens_1)</span></a>
+<a name="2898"><span class="lineNum">    2898 </span><span class="lineCov">          1 :           ctrs_15_1 &lt;= 2'h0;</span></a>
+<a name="2899"><span class="lineNum">    2899 </span><span class="lineNoCov">          0 :         else if (u_s1_br_takens_1)</span></a>
+<a name="2900"><span class="lineNum">    2900 </span><span class="lineNoCov">          0 :           ctrs_15_1 &lt;= 2'(ctrs_15_1 + 2'h1);</span></a>
+<a name="2901"><span class="lineNum">    2901 </span>            :         else</a>
+<a name="2902"><span class="lineNum">    2902 </span><span class="lineNoCov">          0 :           ctrs_15_1 &lt;= 2'(ctrs_15_1 - 2'h1);</span></a>
+<a name="2903"><span class="lineNum">    2903 </span>            :       end</a>
+<a name="2904"><span class="lineNum">    2904 </span><span class="lineNoCov">          0 :       if (u_s1_ways_write_valid_16 &amp; u_s1_br_update_valids_0) begin</span></a>
+<a name="2905"><span class="lineNum">    2905 </span><span class="lineNoCov">          0 :         if ((&amp;ctrs_16_0) &amp; u_s1_br_takens_0)</span></a>
+<a name="2906"><span class="lineNum">    2906 </span><span class="lineNoCov">          0 :           ctrs_16_0 &lt;= 2'h3;</span></a>
+<a name="2907"><span class="lineNum">    2907 </span><span class="lineNoCov">          0 :         else if (ctrs_16_0 == 2'h0 &amp; ~u_s1_br_takens_0)</span></a>
+<a name="2908"><span class="lineNum">    2908 </span><span class="lineNoCov">          0 :           ctrs_16_0 &lt;= 2'h0;</span></a>
+<a name="2909"><span class="lineNum">    2909 </span><span class="lineNoCov">          0 :         else if (u_s1_br_takens_0)</span></a>
+<a name="2910"><span class="lineNum">    2910 </span><span class="lineNoCov">          0 :           ctrs_16_0 &lt;= 2'(ctrs_16_0 + 2'h1);</span></a>
+<a name="2911"><span class="lineNum">    2911 </span>            :         else</a>
+<a name="2912"><span class="lineNum">    2912 </span><span class="lineNoCov">          0 :           ctrs_16_0 &lt;= 2'(ctrs_16_0 - 2'h1);</span></a>
+<a name="2913"><span class="lineNum">    2913 </span>            :       end</a>
+<a name="2914"><span class="lineNum">    2914 </span><span class="lineCov">          2 :       if (u_s1_ways_write_valid_16 &amp; u_s1_br_update_valids_1) begin</span></a>
+<a name="2915"><span class="lineNum">    2915 </span><span class="lineNoCov">          0 :         if ((&amp;ctrs_16_1) &amp; u_s1_br_takens_1)</span></a>
+<a name="2916"><span class="lineNum">    2916 </span><span class="lineNoCov">          0 :           ctrs_16_1 &lt;= 2'h3;</span></a>
+<a name="2917"><span class="lineNum">    2917 </span><span class="lineCov">          2 :         else if (ctrs_16_1 == 2'h0 &amp; ~u_s1_br_takens_1)</span></a>
+<a name="2918"><span class="lineNum">    2918 </span><span class="lineCov">          1 :           ctrs_16_1 &lt;= 2'h0;</span></a>
+<a name="2919"><span class="lineNum">    2919 </span><span class="lineNoCov">          0 :         else if (u_s1_br_takens_1)</span></a>
+<a name="2920"><span class="lineNum">    2920 </span><span class="lineNoCov">          0 :           ctrs_16_1 &lt;= 2'(ctrs_16_1 + 2'h1);</span></a>
+<a name="2921"><span class="lineNum">    2921 </span>            :         else</a>
+<a name="2922"><span class="lineNum">    2922 </span><span class="lineNoCov">          0 :           ctrs_16_1 &lt;= 2'(ctrs_16_1 - 2'h1);</span></a>
+<a name="2923"><span class="lineNum">    2923 </span>            :       end</a>
+<a name="2924"><span class="lineNum">    2924 </span><span class="lineNoCov">          0 :       if (u_s1_ways_write_valid_17 &amp; u_s1_br_update_valids_0) begin</span></a>
+<a name="2925"><span class="lineNum">    2925 </span><span class="lineNoCov">          0 :         if ((&amp;ctrs_17_0) &amp; u_s1_br_takens_0)</span></a>
+<a name="2926"><span class="lineNum">    2926 </span><span class="lineNoCov">          0 :           ctrs_17_0 &lt;= 2'h3;</span></a>
+<a name="2927"><span class="lineNum">    2927 </span><span class="lineNoCov">          0 :         else if (ctrs_17_0 == 2'h0 &amp; ~u_s1_br_takens_0)</span></a>
+<a name="2928"><span class="lineNum">    2928 </span><span class="lineNoCov">          0 :           ctrs_17_0 &lt;= 2'h0;</span></a>
+<a name="2929"><span class="lineNum">    2929 </span><span class="lineNoCov">          0 :         else if (u_s1_br_takens_0)</span></a>
+<a name="2930"><span class="lineNum">    2930 </span><span class="lineNoCov">          0 :           ctrs_17_0 &lt;= 2'(ctrs_17_0 + 2'h1);</span></a>
+<a name="2931"><span class="lineNum">    2931 </span>            :         else</a>
+<a name="2932"><span class="lineNum">    2932 </span><span class="lineNoCov">          0 :           ctrs_17_0 &lt;= 2'(ctrs_17_0 - 2'h1);</span></a>
+<a name="2933"><span class="lineNum">    2933 </span>            :       end</a>
+<a name="2934"><span class="lineNum">    2934 </span><span class="lineCov">          2 :       if (u_s1_ways_write_valid_17 &amp; u_s1_br_update_valids_1) begin</span></a>
+<a name="2935"><span class="lineNum">    2935 </span><span class="lineNoCov">          0 :         if ((&amp;ctrs_17_1) &amp; u_s1_br_takens_1)</span></a>
+<a name="2936"><span class="lineNum">    2936 </span><span class="lineNoCov">          0 :           ctrs_17_1 &lt;= 2'h3;</span></a>
+<a name="2937"><span class="lineNum">    2937 </span><span class="lineCov">          2 :         else if (ctrs_17_1 == 2'h0 &amp; ~u_s1_br_takens_1)</span></a>
+<a name="2938"><span class="lineNum">    2938 </span><span class="lineCov">          1 :           ctrs_17_1 &lt;= 2'h0;</span></a>
+<a name="2939"><span class="lineNum">    2939 </span><span class="lineNoCov">          0 :         else if (u_s1_br_takens_1)</span></a>
+<a name="2940"><span class="lineNum">    2940 </span><span class="lineNoCov">          0 :           ctrs_17_1 &lt;= 2'(ctrs_17_1 + 2'h1);</span></a>
+<a name="2941"><span class="lineNum">    2941 </span>            :         else</a>
+<a name="2942"><span class="lineNum">    2942 </span><span class="lineNoCov">          0 :           ctrs_17_1 &lt;= 2'(ctrs_17_1 - 2'h1);</span></a>
+<a name="2943"><span class="lineNum">    2943 </span>            :       end</a>
+<a name="2944"><span class="lineNum">    2944 </span><span class="lineNoCov">          0 :       if (u_s1_ways_write_valid_18 &amp; u_s1_br_update_valids_0) begin</span></a>
+<a name="2945"><span class="lineNum">    2945 </span><span class="lineNoCov">          0 :         if ((&amp;ctrs_18_0) &amp; u_s1_br_takens_0)</span></a>
+<a name="2946"><span class="lineNum">    2946 </span><span class="lineNoCov">          0 :           ctrs_18_0 &lt;= 2'h3;</span></a>
+<a name="2947"><span class="lineNum">    2947 </span><span class="lineNoCov">          0 :         else if (ctrs_18_0 == 2'h0 &amp; ~u_s1_br_takens_0)</span></a>
+<a name="2948"><span class="lineNum">    2948 </span><span class="lineNoCov">          0 :           ctrs_18_0 &lt;= 2'h0;</span></a>
+<a name="2949"><span class="lineNum">    2949 </span><span class="lineNoCov">          0 :         else if (u_s1_br_takens_0)</span></a>
+<a name="2950"><span class="lineNum">    2950 </span><span class="lineNoCov">          0 :           ctrs_18_0 &lt;= 2'(ctrs_18_0 + 2'h1);</span></a>
+<a name="2951"><span class="lineNum">    2951 </span>            :         else</a>
+<a name="2952"><span class="lineNum">    2952 </span><span class="lineNoCov">          0 :           ctrs_18_0 &lt;= 2'(ctrs_18_0 - 2'h1);</span></a>
+<a name="2953"><span class="lineNum">    2953 </span>            :       end</a>
+<a name="2954"><span class="lineNum">    2954 </span><span class="lineCov">          4 :       if (u_s1_ways_write_valid_18 &amp; u_s1_br_update_valids_1) begin</span></a>
+<a name="2955"><span class="lineNum">    2955 </span><span class="lineNoCov">          0 :         if ((&amp;ctrs_18_1) &amp; u_s1_br_takens_1)</span></a>
+<a name="2956"><span class="lineNum">    2956 </span><span class="lineNoCov">          0 :           ctrs_18_1 &lt;= 2'h3;</span></a>
+<a name="2957"><span class="lineNum">    2957 </span><span class="lineCov">          2 :         else if (ctrs_18_1 == 2'h0 &amp; ~u_s1_br_takens_1)</span></a>
+<a name="2958"><span class="lineNum">    2958 </span><span class="lineCov">          1 :           ctrs_18_1 &lt;= 2'h0;</span></a>
+<a name="2959"><span class="lineNum">    2959 </span><span class="lineNoCov">          0 :         else if (u_s1_br_takens_1)</span></a>
+<a name="2960"><span class="lineNum">    2960 </span><span class="lineNoCov">          0 :           ctrs_18_1 &lt;= 2'(ctrs_18_1 + 2'h1);</span></a>
+<a name="2961"><span class="lineNum">    2961 </span>            :         else</a>
+<a name="2962"><span class="lineNum">    2962 </span><span class="lineCov">          1 :           ctrs_18_1 &lt;= 2'(ctrs_18_1 - 2'h1);</span></a>
+<a name="2963"><span class="lineNum">    2963 </span>            :       end</a>
+<a name="2964"><span class="lineNum">    2964 </span><span class="lineCov">          2 :       if (u_s1_ways_write_valid_19 &amp; u_s1_br_update_valids_0) begin</span></a>
+<a name="2965"><span class="lineNum">    2965 </span><span class="lineNoCov">          0 :         if ((&amp;ctrs_19_0) &amp; u_s1_br_takens_0)</span></a>
+<a name="2966"><span class="lineNum">    2966 </span><span class="lineNoCov">          0 :           ctrs_19_0 &lt;= 2'h3;</span></a>
+<a name="2967"><span class="lineNum">    2967 </span><span class="lineNoCov">          0 :         else if (ctrs_19_0 == 2'h0 &amp; ~u_s1_br_takens_0)</span></a>
+<a name="2968"><span class="lineNum">    2968 </span><span class="lineNoCov">          0 :           ctrs_19_0 &lt;= 2'h0;</span></a>
+<a name="2969"><span class="lineNum">    2969 </span><span class="lineNoCov">          0 :         else if (u_s1_br_takens_0)</span></a>
+<a name="2970"><span class="lineNum">    2970 </span><span class="lineCov">          1 :           ctrs_19_0 &lt;= 2'(ctrs_19_0 + 2'h1);</span></a>
+<a name="2971"><span class="lineNum">    2971 </span>            :         else</a>
+<a name="2972"><span class="lineNum">    2972 </span><span class="lineNoCov">          0 :           ctrs_19_0 &lt;= 2'(ctrs_19_0 - 2'h1);</span></a>
+<a name="2973"><span class="lineNum">    2973 </span>            :       end</a>
+<a name="2974"><span class="lineNum">    2974 </span><span class="lineNoCov">          0 :       if (u_s1_ways_write_valid_19 &amp; u_s1_br_update_valids_1) begin</span></a>
+<a name="2975"><span class="lineNum">    2975 </span><span class="lineNoCov">          0 :         if ((&amp;ctrs_19_1) &amp; u_s1_br_takens_1)</span></a>
+<a name="2976"><span class="lineNum">    2976 </span><span class="lineNoCov">          0 :           ctrs_19_1 &lt;= 2'h3;</span></a>
+<a name="2977"><span class="lineNum">    2977 </span><span class="lineNoCov">          0 :         else if (ctrs_19_1 == 2'h0 &amp; ~u_s1_br_takens_1)</span></a>
+<a name="2978"><span class="lineNum">    2978 </span><span class="lineNoCov">          0 :           ctrs_19_1 &lt;= 2'h0;</span></a>
+<a name="2979"><span class="lineNum">    2979 </span><span class="lineNoCov">          0 :         else if (u_s1_br_takens_1)</span></a>
+<a name="2980"><span class="lineNum">    2980 </span><span class="lineNoCov">          0 :           ctrs_19_1 &lt;= 2'(ctrs_19_1 + 2'h1);</span></a>
+<a name="2981"><span class="lineNum">    2981 </span>            :         else</a>
+<a name="2982"><span class="lineNum">    2982 </span><span class="lineNoCov">          0 :           ctrs_19_1 &lt;= 2'(ctrs_19_1 - 2'h1);</span></a>
+<a name="2983"><span class="lineNum">    2983 </span>            :       end</a>
+<a name="2984"><span class="lineNum">    2984 </span><span class="lineNoCov">          0 :       if (u_s1_ways_write_valid_20 &amp; u_s1_br_update_valids_0) begin</span></a>
+<a name="2985"><span class="lineNum">    2985 </span><span class="lineNoCov">          0 :         if ((&amp;ctrs_20_0) &amp; u_s1_br_takens_0)</span></a>
+<a name="2986"><span class="lineNum">    2986 </span><span class="lineNoCov">          0 :           ctrs_20_0 &lt;= 2'h3;</span></a>
+<a name="2987"><span class="lineNum">    2987 </span><span class="lineNoCov">          0 :         else if (ctrs_20_0 == 2'h0 &amp; ~u_s1_br_takens_0)</span></a>
+<a name="2988"><span class="lineNum">    2988 </span><span class="lineNoCov">          0 :           ctrs_20_0 &lt;= 2'h0;</span></a>
+<a name="2989"><span class="lineNum">    2989 </span><span class="lineNoCov">          0 :         else if (u_s1_br_takens_0)</span></a>
+<a name="2990"><span class="lineNum">    2990 </span><span class="lineNoCov">          0 :           ctrs_20_0 &lt;= 2'(ctrs_20_0 + 2'h1);</span></a>
+<a name="2991"><span class="lineNum">    2991 </span>            :         else</a>
+<a name="2992"><span class="lineNum">    2992 </span><span class="lineNoCov">          0 :           ctrs_20_0 &lt;= 2'(ctrs_20_0 - 2'h1);</span></a>
+<a name="2993"><span class="lineNum">    2993 </span>            :       end</a>
+<a name="2994"><span class="lineNum">    2994 </span><span class="lineCov">          2 :       if (u_s1_ways_write_valid_20 &amp; u_s1_br_update_valids_1) begin</span></a>
+<a name="2995"><span class="lineNum">    2995 </span><span class="lineNoCov">          0 :         if ((&amp;ctrs_20_1) &amp; u_s1_br_takens_1)</span></a>
+<a name="2996"><span class="lineNum">    2996 </span><span class="lineNoCov">          0 :           ctrs_20_1 &lt;= 2'h3;</span></a>
+<a name="2997"><span class="lineNum">    2997 </span><span class="lineNoCov">          0 :         else if (ctrs_20_1 == 2'h0 &amp; ~u_s1_br_takens_1)</span></a>
+<a name="2998"><span class="lineNum">    2998 </span><span class="lineNoCov">          0 :           ctrs_20_1 &lt;= 2'h0;</span></a>
+<a name="2999"><span class="lineNum">    2999 </span><span class="lineNoCov">          0 :         else if (u_s1_br_takens_1)</span></a>
+<a name="3000"><span class="lineNum">    3000 </span><span class="lineNoCov">          0 :           ctrs_20_1 &lt;= 2'(ctrs_20_1 + 2'h1);</span></a>
+<a name="3001"><span class="lineNum">    3001 </span>            :         else</a>
+<a name="3002"><span class="lineNum">    3002 </span><span class="lineCov">          1 :           ctrs_20_1 &lt;= 2'(ctrs_20_1 - 2'h1);</span></a>
+<a name="3003"><span class="lineNum">    3003 </span>            :       end</a>
+<a name="3004"><span class="lineNum">    3004 </span><span class="lineCov">          2 :       if (u_s1_ways_write_valid_21 &amp; u_s1_br_update_valids_0) begin</span></a>
+<a name="3005"><span class="lineNum">    3005 </span><span class="lineNoCov">          0 :         if ((&amp;ctrs_21_0) &amp; u_s1_br_takens_0)</span></a>
+<a name="3006"><span class="lineNum">    3006 </span><span class="lineNoCov">          0 :           ctrs_21_0 &lt;= 2'h3;</span></a>
+<a name="3007"><span class="lineNum">    3007 </span><span class="lineNoCov">          0 :         else if (ctrs_21_0 == 2'h0 &amp; ~u_s1_br_takens_0)</span></a>
+<a name="3008"><span class="lineNum">    3008 </span><span class="lineNoCov">          0 :           ctrs_21_0 &lt;= 2'h0;</span></a>
+<a name="3009"><span class="lineNum">    3009 </span><span class="lineNoCov">          0 :         else if (u_s1_br_takens_0)</span></a>
+<a name="3010"><span class="lineNum">    3010 </span><span class="lineCov">          1 :           ctrs_21_0 &lt;= 2'(ctrs_21_0 + 2'h1);</span></a>
+<a name="3011"><span class="lineNum">    3011 </span>            :         else</a>
+<a name="3012"><span class="lineNum">    3012 </span><span class="lineNoCov">          0 :           ctrs_21_0 &lt;= 2'(ctrs_21_0 - 2'h1);</span></a>
+<a name="3013"><span class="lineNum">    3013 </span>            :       end</a>
+<a name="3014"><span class="lineNum">    3014 </span><span class="lineCov">          2 :       if (u_s1_ways_write_valid_21 &amp; u_s1_br_update_valids_1) begin</span></a>
+<a name="3015"><span class="lineNum">    3015 </span><span class="lineNoCov">          0 :         if ((&amp;ctrs_21_1) &amp; u_s1_br_takens_1)</span></a>
+<a name="3016"><span class="lineNum">    3016 </span><span class="lineNoCov">          0 :           ctrs_21_1 &lt;= 2'h3;</span></a>
+<a name="3017"><span class="lineNum">    3017 </span><span class="lineNoCov">          0 :         else if (ctrs_21_1 == 2'h0 &amp; ~u_s1_br_takens_1)</span></a>
+<a name="3018"><span class="lineNum">    3018 </span><span class="lineNoCov">          0 :           ctrs_21_1 &lt;= 2'h0;</span></a>
+<a name="3019"><span class="lineNum">    3019 </span><span class="lineNoCov">          0 :         else if (u_s1_br_takens_1)</span></a>
+<a name="3020"><span class="lineNum">    3020 </span><span class="lineNoCov">          0 :           ctrs_21_1 &lt;= 2'(ctrs_21_1 + 2'h1);</span></a>
+<a name="3021"><span class="lineNum">    3021 </span>            :         else</a>
+<a name="3022"><span class="lineNum">    3022 </span><span class="lineCov">          1 :           ctrs_21_1 &lt;= 2'(ctrs_21_1 - 2'h1);</span></a>
+<a name="3023"><span class="lineNum">    3023 </span>            :       end</a>
+<a name="3024"><span class="lineNum">    3024 </span><span class="lineCov">          2 :       if (u_s1_ways_write_valid_22 &amp; u_s1_br_update_valids_0) begin</span></a>
+<a name="3025"><span class="lineNum">    3025 </span><span class="lineCov">          2 :         if ((&amp;ctrs_22_0) &amp; u_s1_br_takens_0)</span></a>
+<a name="3026"><span class="lineNum">    3026 </span><span class="lineCov">          1 :           ctrs_22_0 &lt;= 2'h3;</span></a>
+<a name="3027"><span class="lineNum">    3027 </span><span class="lineNoCov">          0 :         else if (ctrs_22_0 == 2'h0 &amp; ~u_s1_br_takens_0)</span></a>
+<a name="3028"><span class="lineNum">    3028 </span><span class="lineNoCov">          0 :           ctrs_22_0 &lt;= 2'h0;</span></a>
+<a name="3029"><span class="lineNum">    3029 </span><span class="lineNoCov">          0 :         else if (u_s1_br_takens_0)</span></a>
+<a name="3030"><span class="lineNum">    3030 </span><span class="lineNoCov">          0 :           ctrs_22_0 &lt;= 2'(ctrs_22_0 + 2'h1);</span></a>
+<a name="3031"><span class="lineNum">    3031 </span>            :         else</a>
+<a name="3032"><span class="lineNum">    3032 </span><span class="lineNoCov">          0 :           ctrs_22_0 &lt;= 2'(ctrs_22_0 - 2'h1);</span></a>
+<a name="3033"><span class="lineNum">    3033 </span>            :       end</a>
+<a name="3034"><span class="lineNum">    3034 </span><span class="lineCov">          2 :       if (u_s1_ways_write_valid_22 &amp; u_s1_br_update_valids_1) begin</span></a>
+<a name="3035"><span class="lineNum">    3035 </span><span class="lineNoCov">          0 :         if ((&amp;ctrs_22_1) &amp; u_s1_br_takens_1)</span></a>
+<a name="3036"><span class="lineNum">    3036 </span><span class="lineNoCov">          0 :           ctrs_22_1 &lt;= 2'h3;</span></a>
+<a name="3037"><span class="lineNum">    3037 </span><span class="lineCov">          2 :         else if (ctrs_22_1 == 2'h0 &amp; ~u_s1_br_takens_1)</span></a>
+<a name="3038"><span class="lineNum">    3038 </span><span class="lineCov">          1 :           ctrs_22_1 &lt;= 2'h0;</span></a>
+<a name="3039"><span class="lineNum">    3039 </span><span class="lineNoCov">          0 :         else if (u_s1_br_takens_1)</span></a>
+<a name="3040"><span class="lineNum">    3040 </span><span class="lineNoCov">          0 :           ctrs_22_1 &lt;= 2'(ctrs_22_1 + 2'h1);</span></a>
+<a name="3041"><span class="lineNum">    3041 </span>            :         else</a>
+<a name="3042"><span class="lineNum">    3042 </span><span class="lineNoCov">          0 :           ctrs_22_1 &lt;= 2'(ctrs_22_1 - 2'h1);</span></a>
+<a name="3043"><span class="lineNum">    3043 </span>            :       end</a>
+<a name="3044"><span class="lineNum">    3044 </span><span class="lineNoCov">          0 :       if (u_s1_ways_write_valid_23 &amp; u_s1_br_update_valids_0) begin</span></a>
+<a name="3045"><span class="lineNum">    3045 </span><span class="lineNoCov">          0 :         if ((&amp;ctrs_23_0) &amp; u_s1_br_takens_0)</span></a>
+<a name="3046"><span class="lineNum">    3046 </span><span class="lineNoCov">          0 :           ctrs_23_0 &lt;= 2'h3;</span></a>
+<a name="3047"><span class="lineNum">    3047 </span><span class="lineNoCov">          0 :         else if (ctrs_23_0 == 2'h0 &amp; ~u_s1_br_takens_0)</span></a>
+<a name="3048"><span class="lineNum">    3048 </span><span class="lineNoCov">          0 :           ctrs_23_0 &lt;= 2'h0;</span></a>
+<a name="3049"><span class="lineNum">    3049 </span><span class="lineNoCov">          0 :         else if (u_s1_br_takens_0)</span></a>
+<a name="3050"><span class="lineNum">    3050 </span><span class="lineNoCov">          0 :           ctrs_23_0 &lt;= 2'(ctrs_23_0 + 2'h1);</span></a>
+<a name="3051"><span class="lineNum">    3051 </span>            :         else</a>
+<a name="3052"><span class="lineNum">    3052 </span><span class="lineNoCov">          0 :           ctrs_23_0 &lt;= 2'(ctrs_23_0 - 2'h1);</span></a>
+<a name="3053"><span class="lineNum">    3053 </span>            :       end</a>
+<a name="3054"><span class="lineNum">    3054 </span><span class="lineNoCov">          0 :       if (u_s1_ways_write_valid_23 &amp; u_s1_br_update_valids_1) begin</span></a>
+<a name="3055"><span class="lineNum">    3055 </span><span class="lineNoCov">          0 :         if ((&amp;ctrs_23_1) &amp; u_s1_br_takens_1)</span></a>
+<a name="3056"><span class="lineNum">    3056 </span><span class="lineNoCov">          0 :           ctrs_23_1 &lt;= 2'h3;</span></a>
+<a name="3057"><span class="lineNum">    3057 </span><span class="lineNoCov">          0 :         else if (ctrs_23_1 == 2'h0 &amp; ~u_s1_br_takens_1)</span></a>
+<a name="3058"><span class="lineNum">    3058 </span><span class="lineNoCov">          0 :           ctrs_23_1 &lt;= 2'h0;</span></a>
+<a name="3059"><span class="lineNum">    3059 </span><span class="lineNoCov">          0 :         else if (u_s1_br_takens_1)</span></a>
+<a name="3060"><span class="lineNum">    3060 </span><span class="lineNoCov">          0 :           ctrs_23_1 &lt;= 2'(ctrs_23_1 + 2'h1);</span></a>
+<a name="3061"><span class="lineNum">    3061 </span>            :         else</a>
+<a name="3062"><span class="lineNum">    3062 </span><span class="lineNoCov">          0 :           ctrs_23_1 &lt;= 2'(ctrs_23_1 - 2'h1);</span></a>
+<a name="3063"><span class="lineNum">    3063 </span>            :       end</a>
+<a name="3064"><span class="lineNum">    3064 </span><span class="lineNoCov">          0 :       if (u_s1_ways_write_valid_24 &amp; u_s1_br_update_valids_0) begin</span></a>
+<a name="3065"><span class="lineNum">    3065 </span><span class="lineNoCov">          0 :         if ((&amp;ctrs_24_0) &amp; u_s1_br_takens_0)</span></a>
+<a name="3066"><span class="lineNum">    3066 </span><span class="lineNoCov">          0 :           ctrs_24_0 &lt;= 2'h3;</span></a>
+<a name="3067"><span class="lineNum">    3067 </span><span class="lineNoCov">          0 :         else if (ctrs_24_0 == 2'h0 &amp; ~u_s1_br_takens_0)</span></a>
+<a name="3068"><span class="lineNum">    3068 </span><span class="lineNoCov">          0 :           ctrs_24_0 &lt;= 2'h0;</span></a>
+<a name="3069"><span class="lineNum">    3069 </span><span class="lineNoCov">          0 :         else if (u_s1_br_takens_0)</span></a>
+<a name="3070"><span class="lineNum">    3070 </span><span class="lineNoCov">          0 :           ctrs_24_0 &lt;= 2'(ctrs_24_0 + 2'h1);</span></a>
+<a name="3071"><span class="lineNum">    3071 </span>            :         else</a>
+<a name="3072"><span class="lineNum">    3072 </span><span class="lineNoCov">          0 :           ctrs_24_0 &lt;= 2'(ctrs_24_0 - 2'h1);</span></a>
+<a name="3073"><span class="lineNum">    3073 </span>            :       end</a>
+<a name="3074"><span class="lineNum">    3074 </span><span class="lineCov">          6 :       if (u_s1_ways_write_valid_24 &amp; u_s1_br_update_valids_1) begin</span></a>
+<a name="3075"><span class="lineNum">    3075 </span><span class="lineNoCov">          0 :         if ((&amp;ctrs_24_1) &amp; u_s1_br_takens_1)</span></a>
+<a name="3076"><span class="lineNum">    3076 </span><span class="lineNoCov">          0 :           ctrs_24_1 &lt;= 2'h3;</span></a>
+<a name="3077"><span class="lineNum">    3077 </span><span class="lineCov">          4 :         else if (ctrs_24_1 == 2'h0 &amp; ~u_s1_br_takens_1)</span></a>
+<a name="3078"><span class="lineNum">    3078 </span><span class="lineCov">          2 :           ctrs_24_1 &lt;= 2'h0;</span></a>
+<a name="3079"><span class="lineNum">    3079 </span><span class="lineNoCov">          0 :         else if (u_s1_br_takens_1)</span></a>
+<a name="3080"><span class="lineNum">    3080 </span><span class="lineNoCov">          0 :           ctrs_24_1 &lt;= 2'(ctrs_24_1 + 2'h1);</span></a>
+<a name="3081"><span class="lineNum">    3081 </span>            :         else</a>
+<a name="3082"><span class="lineNum">    3082 </span><span class="lineCov">          1 :           ctrs_24_1 &lt;= 2'(ctrs_24_1 - 2'h1);</span></a>
+<a name="3083"><span class="lineNum">    3083 </span>            :       end</a>
+<a name="3084"><span class="lineNum">    3084 </span><span class="lineCov">          2 :       if (u_s1_ways_write_valid_25 &amp; u_s1_br_update_valids_0) begin</span></a>
+<a name="3085"><span class="lineNum">    3085 </span><span class="lineNoCov">          0 :         if ((&amp;ctrs_25_0) &amp; u_s1_br_takens_0)</span></a>
+<a name="3086"><span class="lineNum">    3086 </span><span class="lineNoCov">          0 :           ctrs_25_0 &lt;= 2'h3;</span></a>
+<a name="3087"><span class="lineNum">    3087 </span><span class="lineNoCov">          0 :         else if (ctrs_25_0 == 2'h0 &amp; ~u_s1_br_takens_0)</span></a>
+<a name="3088"><span class="lineNum">    3088 </span><span class="lineNoCov">          0 :           ctrs_25_0 &lt;= 2'h0;</span></a>
+<a name="3089"><span class="lineNum">    3089 </span><span class="lineNoCov">          0 :         else if (u_s1_br_takens_0)</span></a>
+<a name="3090"><span class="lineNum">    3090 </span><span class="lineCov">          1 :           ctrs_25_0 &lt;= 2'(ctrs_25_0 + 2'h1);</span></a>
+<a name="3091"><span class="lineNum">    3091 </span>            :         else</a>
+<a name="3092"><span class="lineNum">    3092 </span><span class="lineNoCov">          0 :           ctrs_25_0 &lt;= 2'(ctrs_25_0 - 2'h1);</span></a>
+<a name="3093"><span class="lineNum">    3093 </span>            :       end</a>
+<a name="3094"><span class="lineNum">    3094 </span><span class="lineCov">          4 :       if (u_s1_ways_write_valid_25 &amp; u_s1_br_update_valids_1) begin</span></a>
+<a name="3095"><span class="lineNum">    3095 </span><span class="lineNoCov">          0 :         if ((&amp;ctrs_25_1) &amp; u_s1_br_takens_1)</span></a>
+<a name="3096"><span class="lineNum">    3096 </span><span class="lineNoCov">          0 :           ctrs_25_1 &lt;= 2'h3;</span></a>
+<a name="3097"><span class="lineNum">    3097 </span><span class="lineCov">          2 :         else if (ctrs_25_1 == 2'h0 &amp; ~u_s1_br_takens_1)</span></a>
+<a name="3098"><span class="lineNum">    3098 </span><span class="lineCov">          1 :           ctrs_25_1 &lt;= 2'h0;</span></a>
+<a name="3099"><span class="lineNum">    3099 </span><span class="lineNoCov">          0 :         else if (u_s1_br_takens_1)</span></a>
+<a name="3100"><span class="lineNum">    3100 </span><span class="lineNoCov">          0 :           ctrs_25_1 &lt;= 2'(ctrs_25_1 + 2'h1);</span></a>
+<a name="3101"><span class="lineNum">    3101 </span>            :         else</a>
+<a name="3102"><span class="lineNum">    3102 </span><span class="lineCov">          1 :           ctrs_25_1 &lt;= 2'(ctrs_25_1 - 2'h1);</span></a>
+<a name="3103"><span class="lineNum">    3103 </span>            :       end</a>
+<a name="3104"><span class="lineNum">    3104 </span><span class="lineCov">          2 :       if (u_s1_ways_write_valid_26 &amp; u_s1_br_update_valids_0) begin</span></a>
+<a name="3105"><span class="lineNum">    3105 </span><span class="lineNoCov">          0 :         if ((&amp;ctrs_26_0) &amp; u_s1_br_takens_0)</span></a>
+<a name="3106"><span class="lineNum">    3106 </span><span class="lineNoCov">          0 :           ctrs_26_0 &lt;= 2'h3;</span></a>
+<a name="3107"><span class="lineNum">    3107 </span><span class="lineNoCov">          0 :         else if (ctrs_26_0 == 2'h0 &amp; ~u_s1_br_takens_0)</span></a>
+<a name="3108"><span class="lineNum">    3108 </span><span class="lineNoCov">          0 :           ctrs_26_0 &lt;= 2'h0;</span></a>
+<a name="3109"><span class="lineNum">    3109 </span><span class="lineNoCov">          0 :         else if (u_s1_br_takens_0)</span></a>
+<a name="3110"><span class="lineNum">    3110 </span><span class="lineCov">          1 :           ctrs_26_0 &lt;= 2'(ctrs_26_0 + 2'h1);</span></a>
+<a name="3111"><span class="lineNum">    3111 </span>            :         else</a>
+<a name="3112"><span class="lineNum">    3112 </span><span class="lineNoCov">          0 :           ctrs_26_0 &lt;= 2'(ctrs_26_0 - 2'h1);</span></a>
+<a name="3113"><span class="lineNum">    3113 </span>            :       end</a>
+<a name="3114"><span class="lineNum">    3114 </span><span class="lineCov">          2 :       if (u_s1_ways_write_valid_26 &amp; u_s1_br_update_valids_1) begin</span></a>
+<a name="3115"><span class="lineNum">    3115 </span><span class="lineNoCov">          0 :         if ((&amp;ctrs_26_1) &amp; u_s1_br_takens_1)</span></a>
+<a name="3116"><span class="lineNum">    3116 </span><span class="lineNoCov">          0 :           ctrs_26_1 &lt;= 2'h3;</span></a>
+<a name="3117"><span class="lineNum">    3117 </span><span class="lineNoCov">          0 :         else if (ctrs_26_1 == 2'h0 &amp; ~u_s1_br_takens_1)</span></a>
+<a name="3118"><span class="lineNum">    3118 </span><span class="lineNoCov">          0 :           ctrs_26_1 &lt;= 2'h0;</span></a>
+<a name="3119"><span class="lineNum">    3119 </span><span class="lineNoCov">          0 :         else if (u_s1_br_takens_1)</span></a>
+<a name="3120"><span class="lineNum">    3120 </span><span class="lineNoCov">          0 :           ctrs_26_1 &lt;= 2'(ctrs_26_1 + 2'h1);</span></a>
+<a name="3121"><span class="lineNum">    3121 </span>            :         else</a>
+<a name="3122"><span class="lineNum">    3122 </span><span class="lineCov">          1 :           ctrs_26_1 &lt;= 2'(ctrs_26_1 - 2'h1);</span></a>
+<a name="3123"><span class="lineNum">    3123 </span>            :       end</a>
+<a name="3124"><span class="lineNum">    3124 </span><span class="lineCov">          2 :       if (u_s1_ways_write_valid_27 &amp; u_s1_br_update_valids_0) begin</span></a>
+<a name="3125"><span class="lineNum">    3125 </span><span class="lineNoCov">          0 :         if ((&amp;ctrs_27_0) &amp; u_s1_br_takens_0)</span></a>
+<a name="3126"><span class="lineNum">    3126 </span><span class="lineNoCov">          0 :           ctrs_27_0 &lt;= 2'h3;</span></a>
+<a name="3127"><span class="lineNum">    3127 </span><span class="lineNoCov">          0 :         else if (ctrs_27_0 == 2'h0 &amp; ~u_s1_br_takens_0)</span></a>
+<a name="3128"><span class="lineNum">    3128 </span><span class="lineNoCov">          0 :           ctrs_27_0 &lt;= 2'h0;</span></a>
+<a name="3129"><span class="lineNum">    3129 </span><span class="lineNoCov">          0 :         else if (u_s1_br_takens_0)</span></a>
+<a name="3130"><span class="lineNum">    3130 </span><span class="lineCov">          1 :           ctrs_27_0 &lt;= 2'(ctrs_27_0 + 2'h1);</span></a>
+<a name="3131"><span class="lineNum">    3131 </span>            :         else</a>
+<a name="3132"><span class="lineNum">    3132 </span><span class="lineNoCov">          0 :           ctrs_27_0 &lt;= 2'(ctrs_27_0 - 2'h1);</span></a>
+<a name="3133"><span class="lineNum">    3133 </span>            :       end</a>
+<a name="3134"><span class="lineNum">    3134 </span><span class="lineNoCov">          0 :       if (u_s1_ways_write_valid_27 &amp; u_s1_br_update_valids_1) begin</span></a>
+<a name="3135"><span class="lineNum">    3135 </span><span class="lineNoCov">          0 :         if ((&amp;ctrs_27_1) &amp; u_s1_br_takens_1)</span></a>
+<a name="3136"><span class="lineNum">    3136 </span><span class="lineNoCov">          0 :           ctrs_27_1 &lt;= 2'h3;</span></a>
+<a name="3137"><span class="lineNum">    3137 </span><span class="lineNoCov">          0 :         else if (ctrs_27_1 == 2'h0 &amp; ~u_s1_br_takens_1)</span></a>
+<a name="3138"><span class="lineNum">    3138 </span><span class="lineNoCov">          0 :           ctrs_27_1 &lt;= 2'h0;</span></a>
+<a name="3139"><span class="lineNum">    3139 </span><span class="lineNoCov">          0 :         else if (u_s1_br_takens_1)</span></a>
+<a name="3140"><span class="lineNum">    3140 </span><span class="lineNoCov">          0 :           ctrs_27_1 &lt;= 2'(ctrs_27_1 + 2'h1);</span></a>
+<a name="3141"><span class="lineNum">    3141 </span>            :         else</a>
+<a name="3142"><span class="lineNum">    3142 </span><span class="lineNoCov">          0 :           ctrs_27_1 &lt;= 2'(ctrs_27_1 - 2'h1);</span></a>
+<a name="3143"><span class="lineNum">    3143 </span>            :       end</a>
+<a name="3144"><span class="lineNum">    3144 </span><span class="lineCov">          2 :       if (u_s1_ways_write_valid_28 &amp; u_s1_br_update_valids_0) begin</span></a>
+<a name="3145"><span class="lineNum">    3145 </span><span class="lineNoCov">          0 :         if ((&amp;ctrs_28_0) &amp; u_s1_br_takens_0)</span></a>
+<a name="3146"><span class="lineNum">    3146 </span><span class="lineNoCov">          0 :           ctrs_28_0 &lt;= 2'h3;</span></a>
+<a name="3147"><span class="lineNum">    3147 </span><span class="lineNoCov">          0 :         else if (ctrs_28_0 == 2'h0 &amp; ~u_s1_br_takens_0)</span></a>
+<a name="3148"><span class="lineNum">    3148 </span><span class="lineNoCov">          0 :           ctrs_28_0 &lt;= 2'h0;</span></a>
+<a name="3149"><span class="lineNum">    3149 </span><span class="lineNoCov">          0 :         else if (u_s1_br_takens_0)</span></a>
+<a name="3150"><span class="lineNum">    3150 </span><span class="lineCov">          1 :           ctrs_28_0 &lt;= 2'(ctrs_28_0 + 2'h1);</span></a>
+<a name="3151"><span class="lineNum">    3151 </span>            :         else</a>
+<a name="3152"><span class="lineNum">    3152 </span><span class="lineNoCov">          0 :           ctrs_28_0 &lt;= 2'(ctrs_28_0 - 2'h1);</span></a>
+<a name="3153"><span class="lineNum">    3153 </span>            :       end</a>
+<a name="3154"><span class="lineNum">    3154 </span><span class="lineCov">          4 :       if (u_s1_ways_write_valid_28 &amp; u_s1_br_update_valids_1) begin</span></a>
+<a name="3155"><span class="lineNum">    3155 </span><span class="lineNoCov">          0 :         if ((&amp;ctrs_28_1) &amp; u_s1_br_takens_1)</span></a>
+<a name="3156"><span class="lineNum">    3156 </span><span class="lineNoCov">          0 :           ctrs_28_1 &lt;= 2'h3;</span></a>
+<a name="3157"><span class="lineNum">    3157 </span><span class="lineNoCov">          0 :         else if (ctrs_28_1 == 2'h0 &amp; ~u_s1_br_takens_1)</span></a>
+<a name="3158"><span class="lineNum">    3158 </span><span class="lineNoCov">          0 :           ctrs_28_1 &lt;= 2'h0;</span></a>
+<a name="3159"><span class="lineNum">    3159 </span><span class="lineNoCov">          0 :         else if (u_s1_br_takens_1)</span></a>
+<a name="3160"><span class="lineNum">    3160 </span><span class="lineNoCov">          0 :           ctrs_28_1 &lt;= 2'(ctrs_28_1 + 2'h1);</span></a>
+<a name="3161"><span class="lineNum">    3161 </span>            :         else</a>
+<a name="3162"><span class="lineNum">    3162 </span><span class="lineCov">          2 :           ctrs_28_1 &lt;= 2'(ctrs_28_1 - 2'h1);</span></a>
+<a name="3163"><span class="lineNum">    3163 </span>            :       end</a>
+<a name="3164"><span class="lineNum">    3164 </span><span class="lineNoCov">          0 :       if (u_s1_ways_write_valid_29 &amp; u_s1_br_update_valids_0) begin</span></a>
+<a name="3165"><span class="lineNum">    3165 </span><span class="lineNoCov">          0 :         if ((&amp;ctrs_29_0) &amp; u_s1_br_takens_0)</span></a>
+<a name="3166"><span class="lineNum">    3166 </span><span class="lineNoCov">          0 :           ctrs_29_0 &lt;= 2'h3;</span></a>
+<a name="3167"><span class="lineNum">    3167 </span><span class="lineNoCov">          0 :         else if (ctrs_29_0 == 2'h0 &amp; ~u_s1_br_takens_0)</span></a>
+<a name="3168"><span class="lineNum">    3168 </span><span class="lineNoCov">          0 :           ctrs_29_0 &lt;= 2'h0;</span></a>
+<a name="3169"><span class="lineNum">    3169 </span><span class="lineNoCov">          0 :         else if (u_s1_br_takens_0)</span></a>
+<a name="3170"><span class="lineNum">    3170 </span><span class="lineNoCov">          0 :           ctrs_29_0 &lt;= 2'(ctrs_29_0 + 2'h1);</span></a>
+<a name="3171"><span class="lineNum">    3171 </span>            :         else</a>
+<a name="3172"><span class="lineNum">    3172 </span><span class="lineNoCov">          0 :           ctrs_29_0 &lt;= 2'(ctrs_29_0 - 2'h1);</span></a>
+<a name="3173"><span class="lineNum">    3173 </span>            :       end</a>
+<a name="3174"><span class="lineNum">    3174 </span><span class="lineCov">          2 :       if (u_s1_ways_write_valid_29 &amp; u_s1_br_update_valids_1) begin</span></a>
+<a name="3175"><span class="lineNum">    3175 </span><span class="lineNoCov">          0 :         if ((&amp;ctrs_29_1) &amp; u_s1_br_takens_1)</span></a>
+<a name="3176"><span class="lineNum">    3176 </span><span class="lineNoCov">          0 :           ctrs_29_1 &lt;= 2'h3;</span></a>
+<a name="3177"><span class="lineNum">    3177 </span><span class="lineCov">          2 :         else if (ctrs_29_1 == 2'h0 &amp; ~u_s1_br_takens_1)</span></a>
+<a name="3178"><span class="lineNum">    3178 </span><span class="lineCov">          1 :           ctrs_29_1 &lt;= 2'h0;</span></a>
+<a name="3179"><span class="lineNum">    3179 </span><span class="lineNoCov">          0 :         else if (u_s1_br_takens_1)</span></a>
+<a name="3180"><span class="lineNum">    3180 </span><span class="lineNoCov">          0 :           ctrs_29_1 &lt;= 2'(ctrs_29_1 + 2'h1);</span></a>
+<a name="3181"><span class="lineNum">    3181 </span>            :         else</a>
+<a name="3182"><span class="lineNum">    3182 </span><span class="lineNoCov">          0 :           ctrs_29_1 &lt;= 2'(ctrs_29_1 - 2'h1);</span></a>
+<a name="3183"><span class="lineNum">    3183 </span>            :       end</a>
+<a name="3184"><span class="lineNum">    3184 </span><span class="lineCov">          2 :       if (u_s1_ways_write_valid_30 &amp; u_s1_br_update_valids_0) begin</span></a>
+<a name="3185"><span class="lineNum">    3185 </span><span class="lineNoCov">          0 :         if ((&amp;ctrs_30_0) &amp; u_s1_br_takens_0)</span></a>
+<a name="3186"><span class="lineNum">    3186 </span><span class="lineNoCov">          0 :           ctrs_30_0 &lt;= 2'h3;</span></a>
+<a name="3187"><span class="lineNum">    3187 </span><span class="lineNoCov">          0 :         else if (ctrs_30_0 == 2'h0 &amp; ~u_s1_br_takens_0)</span></a>
+<a name="3188"><span class="lineNum">    3188 </span><span class="lineNoCov">          0 :           ctrs_30_0 &lt;= 2'h0;</span></a>
+<a name="3189"><span class="lineNum">    3189 </span><span class="lineNoCov">          0 :         else if (u_s1_br_takens_0)</span></a>
+<a name="3190"><span class="lineNum">    3190 </span><span class="lineCov">          1 :           ctrs_30_0 &lt;= 2'(ctrs_30_0 + 2'h1);</span></a>
+<a name="3191"><span class="lineNum">    3191 </span>            :         else</a>
+<a name="3192"><span class="lineNum">    3192 </span><span class="lineNoCov">          0 :           ctrs_30_0 &lt;= 2'(ctrs_30_0 - 2'h1);</span></a>
+<a name="3193"><span class="lineNum">    3193 </span>            :       end</a>
+<a name="3194"><span class="lineNum">    3194 </span><span class="lineNoCov">          0 :       if (u_s1_ways_write_valid_30 &amp; u_s1_br_update_valids_1) begin</span></a>
+<a name="3195"><span class="lineNum">    3195 </span><span class="lineNoCov">          0 :         if ((&amp;ctrs_30_1) &amp; u_s1_br_takens_1)</span></a>
+<a name="3196"><span class="lineNum">    3196 </span><span class="lineNoCov">          0 :           ctrs_30_1 &lt;= 2'h3;</span></a>
+<a name="3197"><span class="lineNum">    3197 </span><span class="lineNoCov">          0 :         else if (ctrs_30_1 == 2'h0 &amp; ~u_s1_br_takens_1)</span></a>
+<a name="3198"><span class="lineNum">    3198 </span><span class="lineNoCov">          0 :           ctrs_30_1 &lt;= 2'h0;</span></a>
+<a name="3199"><span class="lineNum">    3199 </span><span class="lineNoCov">          0 :         else if (u_s1_br_takens_1)</span></a>
+<a name="3200"><span class="lineNum">    3200 </span><span class="lineNoCov">          0 :           ctrs_30_1 &lt;= 2'(ctrs_30_1 + 2'h1);</span></a>
+<a name="3201"><span class="lineNum">    3201 </span>            :         else</a>
+<a name="3202"><span class="lineNum">    3202 </span><span class="lineNoCov">          0 :           ctrs_30_1 &lt;= 2'(ctrs_30_1 - 2'h1);</span></a>
+<a name="3203"><span class="lineNum">    3203 </span>            :       end</a>
+<a name="3204"><span class="lineNum">    3204 </span><span class="lineNoCov">          0 :       if (u_s1_ways_write_valid_31 &amp; u_s1_br_update_valids_0) begin</span></a>
+<a name="3205"><span class="lineNum">    3205 </span><span class="lineNoCov">          0 :         if ((&amp;ctrs_31_0) &amp; u_s1_br_takens_0)</span></a>
+<a name="3206"><span class="lineNum">    3206 </span><span class="lineNoCov">          0 :           ctrs_31_0 &lt;= 2'h3;</span></a>
+<a name="3207"><span class="lineNum">    3207 </span><span class="lineNoCov">          0 :         else if (ctrs_31_0 == 2'h0 &amp; ~u_s1_br_takens_0)</span></a>
+<a name="3208"><span class="lineNum">    3208 </span><span class="lineNoCov">          0 :           ctrs_31_0 &lt;= 2'h0;</span></a>
+<a name="3209"><span class="lineNum">    3209 </span><span class="lineNoCov">          0 :         else if (u_s1_br_takens_0)</span></a>
+<a name="3210"><span class="lineNum">    3210 </span><span class="lineNoCov">          0 :           ctrs_31_0 &lt;= 2'(ctrs_31_0 + 2'h1);</span></a>
+<a name="3211"><span class="lineNum">    3211 </span>            :         else</a>
+<a name="3212"><span class="lineNum">    3212 </span><span class="lineNoCov">          0 :           ctrs_31_0 &lt;= 2'(ctrs_31_0 - 2'h1);</span></a>
+<a name="3213"><span class="lineNum">    3213 </span>            :       end</a>
+<a name="3214"><span class="lineNum">    3214 </span><span class="lineCov">          2 :       if (u_s1_ways_write_valid_31 &amp; u_s1_br_update_valids_1) begin</span></a>
+<a name="3215"><span class="lineNum">    3215 </span><span class="lineNoCov">          0 :         if ((&amp;ctrs_31_1) &amp; u_s1_br_takens_1)</span></a>
+<a name="3216"><span class="lineNum">    3216 </span><span class="lineNoCov">          0 :           ctrs_31_1 &lt;= 2'h3;</span></a>
+<a name="3217"><span class="lineNum">    3217 </span><span class="lineNoCov">          0 :         else if (ctrs_31_1 == 2'h0 &amp; ~u_s1_br_takens_1)</span></a>
+<a name="3218"><span class="lineNum">    3218 </span><span class="lineNoCov">          0 :           ctrs_31_1 &lt;= 2'h0;</span></a>
+<a name="3219"><span class="lineNum">    3219 </span><span class="lineNoCov">          0 :         else if (u_s1_br_takens_1)</span></a>
+<a name="3220"><span class="lineNum">    3220 </span><span class="lineNoCov">          0 :           ctrs_31_1 &lt;= 2'(ctrs_31_1 + 2'h1);</span></a>
+<a name="3221"><span class="lineNum">    3221 </span>            :         else</a>
+<a name="3222"><span class="lineNum">    3222 </span><span class="lineCov">          1 :           ctrs_31_1 &lt;= 2'(ctrs_31_1 - 2'h1);</span></a>
+<a name="3223"><span class="lineNum">    3223 </span>            :       end</a>
+<a name="3224"><span class="lineNum">    3224 </span><span class="lineCov">         92 :       if (replacer_touch_ways_0_valid_REG | u_s1_valid) begin</span></a>
+<a name="3225"><span class="lineNum">    3225 </span><span class="lineCov">         86 :         if (u_s1_valid)</span></a>
+<a name="3226"><span class="lineNum">    3226 </span><span class="lineCov">         43 :           state_reg &lt;=</span></a>
+<a name="3227"><span class="lineNum">    3227 </span><span class="lineCov">         43 :             {~(|(u_s1_write_way_oh[31:16])),</span></a>
+<a name="3228"><span class="lineNum">    3228 </span><span class="lineCov">         43 :              (|(u_s1_write_way_oh[31:16]))</span></a>
+<a name="3229"><span class="lineNum">    3229 </span><span class="lineCov">         43 :                ? {~(|(_replacer_touch_ways_1_bits_T_1[14:7])),</span></a>
+<a name="3230"><span class="lineNum">    3230 </span><span class="lineCov">         43 :                   (|(_replacer_touch_ways_1_bits_T_1[14:7]))</span></a>
+<a name="3231"><span class="lineNum">    3231 </span><span class="lineCov">         43 :                     ? {~(|(_replacer_touch_ways_1_bits_T_3[6:3])),</span></a>
+<a name="3232"><span class="lineNum">    3232 </span><span class="lineCov">         43 :                        (|(_replacer_touch_ways_1_bits_T_3[6:3]))</span></a>
+<a name="3233"><span class="lineNum">    3233 </span><span class="lineCov">         43 :                          ? {~(|(_replacer_touch_ways_1_bits_T_5[2:1])),</span></a>
+<a name="3234"><span class="lineNum">    3234 </span><span class="lineCov">         43 :                             (|(_replacer_touch_ways_1_bits_T_5[2:1]))</span></a>
+<a name="3235"><span class="lineNum">    3235 </span><span class="lineCov">         43 :                               ? ~_replacer_touch_ways_1_bits_T_7</span></a>
+<a name="3236"><span class="lineNum">    3236 </span><span class="lineCov">         43 :                               : _state_reg_T_107[26],</span></a>
+<a name="3237"><span class="lineNum">    3237 </span><span class="lineCov">         43 :                             (|(_replacer_touch_ways_1_bits_T_5[2:1]))</span></a>
+<a name="3238"><span class="lineNum">    3238 </span><span class="lineCov">         43 :                               ? _state_reg_T_107[25]</span></a>
+<a name="3239"><span class="lineNum">    3239 </span><span class="lineCov">         43 :                               : ~_replacer_touch_ways_1_bits_T_7}</span></a>
+<a name="3240"><span class="lineNum">    3240 </span><span class="lineCov">         43 :                          : _state_reg_T_107[27:25],</span></a>
+<a name="3241"><span class="lineNum">    3241 </span><span class="lineCov">         43 :                        (|(_replacer_touch_ways_1_bits_T_3[6:3]))</span></a>
+<a name="3242"><span class="lineNum">    3242 </span><span class="lineCov">         43 :                          ? _state_reg_T_107[24:22]</span></a>
+<a name="3243"><span class="lineNum">    3243 </span><span class="lineCov">         43 :                          : {~(|(_replacer_touch_ways_1_bits_T_5[2:1])),</span></a>
+<a name="3244"><span class="lineNum">    3244 </span><span class="lineCov">         43 :                             (|(_replacer_touch_ways_1_bits_T_5[2:1]))</span></a>
+<a name="3245"><span class="lineNum">    3245 </span><span class="lineCov">         43 :                               ? ~_replacer_touch_ways_1_bits_T_7</span></a>
+<a name="3246"><span class="lineNum">    3246 </span><span class="lineCov">         43 :                               : _state_reg_T_107[23],</span></a>
+<a name="3247"><span class="lineNum">    3247 </span><span class="lineCov">         43 :                             (|(_replacer_touch_ways_1_bits_T_5[2:1]))</span></a>
+<a name="3248"><span class="lineNum">    3248 </span><span class="lineCov">         43 :                               ? _state_reg_T_107[22]</span></a>
+<a name="3249"><span class="lineNum">    3249 </span><span class="lineCov">         43 :                               : ~_replacer_touch_ways_1_bits_T_7}}</span></a>
+<a name="3250"><span class="lineNum">    3250 </span><span class="lineCov">         43 :                     : _state_reg_T_107[28:22],</span></a>
+<a name="3251"><span class="lineNum">    3251 </span><span class="lineCov">         43 :                   (|(_replacer_touch_ways_1_bits_T_1[14:7]))</span></a>
+<a name="3252"><span class="lineNum">    3252 </span><span class="lineCov">         43 :                     ? _state_reg_T_107[21:15]</span></a>
+<a name="3253"><span class="lineNum">    3253 </span><span class="lineCov">         43 :                     : {~(|(_replacer_touch_ways_1_bits_T_3[6:3])),</span></a>
+<a name="3254"><span class="lineNum">    3254 </span><span class="lineCov">         43 :                        (|(_replacer_touch_ways_1_bits_T_3[6:3]))</span></a>
+<a name="3255"><span class="lineNum">    3255 </span><span class="lineCov">         43 :                          ? {~(|(_replacer_touch_ways_1_bits_T_5[2:1])),</span></a>
+<a name="3256"><span class="lineNum">    3256 </span><span class="lineCov">         43 :                             (|(_replacer_touch_ways_1_bits_T_5[2:1]))</span></a>
+<a name="3257"><span class="lineNum">    3257 </span><span class="lineCov">         43 :                               ? ~_replacer_touch_ways_1_bits_T_7</span></a>
+<a name="3258"><span class="lineNum">    3258 </span><span class="lineCov">         43 :                               : _state_reg_T_107[19],</span></a>
+<a name="3259"><span class="lineNum">    3259 </span><span class="lineCov">         43 :                             (|(_replacer_touch_ways_1_bits_T_5[2:1]))</span></a>
+<a name="3260"><span class="lineNum">    3260 </span><span class="lineCov">         43 :                               ? _state_reg_T_107[18]</span></a>
+<a name="3261"><span class="lineNum">    3261 </span><span class="lineCov">         43 :                               : ~_replacer_touch_ways_1_bits_T_7}</span></a>
+<a name="3262"><span class="lineNum">    3262 </span><span class="lineCov">         43 :                          : _state_reg_T_107[20:18],</span></a>
+<a name="3263"><span class="lineNum">    3263 </span><span class="lineCov">         43 :                        (|(_replacer_touch_ways_1_bits_T_3[6:3]))</span></a>
+<a name="3264"><span class="lineNum">    3264 </span><span class="lineCov">         43 :                          ? _state_reg_T_107[17:15]</span></a>
+<a name="3265"><span class="lineNum">    3265 </span><span class="lineCov">         43 :                          : {~(|(_replacer_touch_ways_1_bits_T_5[2:1])),</span></a>
+<a name="3266"><span class="lineNum">    3266 </span><span class="lineCov">         43 :                             (|(_replacer_touch_ways_1_bits_T_5[2:1]))</span></a>
+<a name="3267"><span class="lineNum">    3267 </span><span class="lineCov">         43 :                               ? ~_replacer_touch_ways_1_bits_T_7</span></a>
+<a name="3268"><span class="lineNum">    3268 </span><span class="lineCov">         43 :                               : _state_reg_T_107[16],</span></a>
+<a name="3269"><span class="lineNum">    3269 </span><span class="lineCov">         43 :                             (|(_replacer_touch_ways_1_bits_T_5[2:1]))</span></a>
+<a name="3270"><span class="lineNum">    3270 </span><span class="lineCov">         43 :                               ? _state_reg_T_107[15]</span></a>
+<a name="3271"><span class="lineNum">    3271 </span><span class="lineCov">         43 :                               : ~_replacer_touch_ways_1_bits_T_7}}}</span></a>
+<a name="3272"><span class="lineNum">    3272 </span><span class="lineCov">         43 :                : _state_reg_T_107[29:15],</span></a>
+<a name="3273"><span class="lineNum">    3273 </span><span class="lineCov">         43 :              (|(u_s1_write_way_oh[31:16]))</span></a>
+<a name="3274"><span class="lineNum">    3274 </span><span class="lineCov">         43 :                ? _state_reg_T_107[14:0]</span></a>
+<a name="3275"><span class="lineNum">    3275 </span><span class="lineCov">         43 :                : {~(|(_replacer_touch_ways_1_bits_T_1[14:7])),</span></a>
+<a name="3276"><span class="lineNum">    3276 </span><span class="lineCov">         43 :                   (|(_replacer_touch_ways_1_bits_T_1[14:7]))</span></a>
+<a name="3277"><span class="lineNum">    3277 </span><span class="lineCov">         43 :                     ? {~(|(_replacer_touch_ways_1_bits_T_3[6:3])),</span></a>
+<a name="3278"><span class="lineNum">    3278 </span><span class="lineCov">         43 :                        (|(_replacer_touch_ways_1_bits_T_3[6:3]))</span></a>
+<a name="3279"><span class="lineNum">    3279 </span><span class="lineCov">         43 :                          ? {~(|(_replacer_touch_ways_1_bits_T_5[2:1])),</span></a>
+<a name="3280"><span class="lineNum">    3280 </span><span class="lineCov">         43 :                             (|(_replacer_touch_ways_1_bits_T_5[2:1]))</span></a>
+<a name="3281"><span class="lineNum">    3281 </span><span class="lineCov">         43 :                               ? ~_replacer_touch_ways_1_bits_T_7</span></a>
+<a name="3282"><span class="lineNum">    3282 </span><span class="lineCov">         43 :                               : _state_reg_T_107[11],</span></a>
+<a name="3283"><span class="lineNum">    3283 </span><span class="lineCov">         43 :                             (|(_replacer_touch_ways_1_bits_T_5[2:1]))</span></a>
+<a name="3284"><span class="lineNum">    3284 </span><span class="lineCov">         43 :                               ? _state_reg_T_107[10]</span></a>
+<a name="3285"><span class="lineNum">    3285 </span><span class="lineCov">         43 :                               : ~_replacer_touch_ways_1_bits_T_7}</span></a>
+<a name="3286"><span class="lineNum">    3286 </span><span class="lineCov">         43 :                          : _state_reg_T_107[12:10],</span></a>
+<a name="3287"><span class="lineNum">    3287 </span><span class="lineCov">         43 :                        (|(_replacer_touch_ways_1_bits_T_3[6:3]))</span></a>
+<a name="3288"><span class="lineNum">    3288 </span><span class="lineCov">         43 :                          ? _state_reg_T_107[9:7]</span></a>
+<a name="3289"><span class="lineNum">    3289 </span><span class="lineCov">         43 :                          : {~(|(_replacer_touch_ways_1_bits_T_5[2:1])),</span></a>
+<a name="3290"><span class="lineNum">    3290 </span><span class="lineCov">         43 :                             (|(_replacer_touch_ways_1_bits_T_5[2:1]))</span></a>
+<a name="3291"><span class="lineNum">    3291 </span><span class="lineCov">         43 :                               ? ~_replacer_touch_ways_1_bits_T_7</span></a>
+<a name="3292"><span class="lineNum">    3292 </span><span class="lineCov">         43 :                               : _state_reg_T_107[8],</span></a>
+<a name="3293"><span class="lineNum">    3293 </span><span class="lineCov">         43 :                             (|(_replacer_touch_ways_1_bits_T_5[2:1]))</span></a>
+<a name="3294"><span class="lineNum">    3294 </span><span class="lineCov">         43 :                               ? _state_reg_T_107[7]</span></a>
+<a name="3295"><span class="lineNum">    3295 </span><span class="lineCov">         43 :                               : ~_replacer_touch_ways_1_bits_T_7}}</span></a>
+<a name="3296"><span class="lineNum">    3296 </span><span class="lineCov">         43 :                     : _state_reg_T_107[13:7],</span></a>
+<a name="3297"><span class="lineNum">    3297 </span><span class="lineCov">         43 :                   (|(_replacer_touch_ways_1_bits_T_1[14:7]))</span></a>
+<a name="3298"><span class="lineNum">    3298 </span><span class="lineCov">         43 :                     ? _state_reg_T_107[6:0]</span></a>
+<a name="3299"><span class="lineNum">    3299 </span><span class="lineCov">         43 :                     : {~(|(_replacer_touch_ways_1_bits_T_3[6:3])),</span></a>
+<a name="3300"><span class="lineNum">    3300 </span><span class="lineCov">         43 :                        (|(_replacer_touch_ways_1_bits_T_3[6:3]))</span></a>
+<a name="3301"><span class="lineNum">    3301 </span><span class="lineCov">         43 :                          ? {~(|(_replacer_touch_ways_1_bits_T_5[2:1])),</span></a>
+<a name="3302"><span class="lineNum">    3302 </span><span class="lineCov">         43 :                             (|(_replacer_touch_ways_1_bits_T_5[2:1]))</span></a>
+<a name="3303"><span class="lineNum">    3303 </span><span class="lineCov">         43 :                               ? ~_replacer_touch_ways_1_bits_T_7</span></a>
+<a name="3304"><span class="lineNum">    3304 </span><span class="lineCov">         43 :                               : _state_reg_T_107[4],</span></a>
+<a name="3305"><span class="lineNum">    3305 </span><span class="lineCov">         43 :                             (|(_replacer_touch_ways_1_bits_T_5[2:1]))</span></a>
+<a name="3306"><span class="lineNum">    3306 </span><span class="lineCov">         43 :                               ? _state_reg_T_107[3]</span></a>
+<a name="3307"><span class="lineNum">    3307 </span><span class="lineCov">         43 :                               : ~_replacer_touch_ways_1_bits_T_7}</span></a>
+<a name="3308"><span class="lineNum">    3308 </span><span class="lineCov">         43 :                          : _state_reg_T_107[5:3],</span></a>
+<a name="3309"><span class="lineNum">    3309 </span><span class="lineCov">         43 :                        (|(_replacer_touch_ways_1_bits_T_3[6:3]))</span></a>
+<a name="3310"><span class="lineNum">    3310 </span><span class="lineCov">         43 :                          ? _state_reg_T_107[2:0]</span></a>
+<a name="3311"><span class="lineNum">    3311 </span><span class="lineCov">         43 :                          : {~(|(_replacer_touch_ways_1_bits_T_5[2:1])),</span></a>
+<a name="3312"><span class="lineNum">    3312 </span><span class="lineCov">         43 :                             (|(_replacer_touch_ways_1_bits_T_5[2:1]))</span></a>
+<a name="3313"><span class="lineNum">    3313 </span><span class="lineCov">         43 :                               ? ~_replacer_touch_ways_1_bits_T_7</span></a>
+<a name="3314"><span class="lineNum">    3314 </span><span class="lineCov">         43 :                               : _state_reg_T_107[1],</span></a>
+<a name="3315"><span class="lineNum">    3315 </span><span class="lineCov">         43 :                             (|(_replacer_touch_ways_1_bits_T_5[2:1]))</span></a>
+<a name="3316"><span class="lineNum">    3316 </span><span class="lineCov">         43 :                               ? _state_reg_T_107[0]</span></a>
+<a name="3317"><span class="lineNum">    3317 </span><span class="lineCov">         43 :                               : ~_replacer_touch_ways_1_bits_T_7}}}};</span></a>
+<a name="3318"><span class="lineNum">    3318 </span><span class="lineNoCov">          0 :         else if (replacer_touch_ways_0_valid_REG)</span></a>
+<a name="3319"><span class="lineNum">    3319 </span><span class="lineCov">          3 :           state_reg &lt;=</span></a>
+<a name="3320"><span class="lineNum">    3320 </span><span class="lineCov">          3 :             {~(replacer_touch_ways_0_bits_r[4]), _state_reg_T_52, _state_reg_T_105};</span></a>
+<a name="3321"><span class="lineNum">    3321 </span>            :       end</a>
+<a name="3322"><span class="lineNum">    3322 </span>            :     end</a>
+<a name="3323"><span class="lineNum">    3323 </span>            :   end // always @(posedge, posedge)</a>
+<a name="3324"><span class="lineNum">    3324 </span>            :   `ifdef ENABLE_INITIAL_REG_</a>
+<a name="3325"><span class="lineNum">    3325 </span>            :     `ifdef FIRRTL_BEFORE_INITIAL</a>
+<a name="3326"><span class="lineNum">    3326 </span>            :       `FIRRTL_BEFORE_INITIAL</a>
+<a name="3327"><span class="lineNum">    3327 </span>            :     `endif // FIRRTL_BEFORE_INITIAL</a>
+<a name="3328"><span class="lineNum">    3328 </span>            :     logic [31:0] _RANDOM[0:24];</a>
+<a name="3329"><span class="lineNum">    3329 </span><span class="lineCov">         58 :     initial begin</span></a>
+<a name="3330"><span class="lineNum">    3330 </span>            :       `ifdef INIT_RANDOM_PROLOG_</a>
+<a name="3331"><span class="lineNum">    3331 </span>            :         `INIT_RANDOM_PROLOG_</a>
+<a name="3332"><span class="lineNum">    3332 </span>            :       `endif // INIT_RANDOM_PROLOG_</a>
+<a name="3333"><span class="lineNum">    3333 </span>            :       `ifdef RANDOMIZE_REG_INIT</a>
+<a name="3334"><span class="lineNum">    3334 </span>            :         for (logic [4:0] i = 5'h0; i &lt; 5'h19; i += 5'h1) begin</a>
+<a name="3335"><span class="lineNum">    3335 </span>            :           _RANDOM[i] = `RANDOM;</a>
+<a name="3336"><span class="lineNum">    3336 </span>            :         end</a>
+<a name="3337"><span class="lineNum">    3337 </span>            :         s1_pc_dup_0 = {_RANDOM[5'h0], _RANDOM[5'h1][8:0]};</a>
+<a name="3338"><span class="lineNum">    3338 </span>            :         s1_pc_dup_1 = {_RANDOM[5'h1][31:9], _RANDOM[5'h2][17:0]};</a>
+<a name="3339"><span class="lineNum">    3339 </span>            :         s1_pc_dup_2 = {_RANDOM[5'h2][31:18], _RANDOM[5'h3][26:0]};</a>
+<a name="3340"><span class="lineNum">    3340 </span>            :         s1_pc_dup_3 = {_RANDOM[5'h3][31:27], _RANDOM[5'h4], _RANDOM[5'h5][3:0]};</a>
+<a name="3341"><span class="lineNum">    3341 </span>            :         REG = _RANDOM[5'hF][12];</a>
+<a name="3342"><span class="lineNum">    3342 </span>            :         REG_1 = _RANDOM[5'hF][13];</a>
+<a name="3343"><span class="lineNum">    3343 </span>            :         ctrs_0_0 = _RANDOM[5'hF][15:14];</a>
+<a name="3344"><span class="lineNum">    3344 </span>            :         ctrs_0_1 = _RANDOM[5'hF][17:16];</a>
+<a name="3345"><span class="lineNum">    3345 </span>            :         ctrs_1_0 = _RANDOM[5'hF][19:18];</a>
+<a name="3346"><span class="lineNum">    3346 </span>            :         ctrs_1_1 = _RANDOM[5'hF][21:20];</a>
+<a name="3347"><span class="lineNum">    3347 </span>            :         ctrs_2_0 = _RANDOM[5'hF][23:22];</a>
+<a name="3348"><span class="lineNum">    3348 </span>            :         ctrs_2_1 = _RANDOM[5'hF][25:24];</a>
+<a name="3349"><span class="lineNum">    3349 </span>            :         ctrs_3_0 = _RANDOM[5'hF][27:26];</a>
+<a name="3350"><span class="lineNum">    3350 </span>            :         ctrs_3_1 = _RANDOM[5'hF][29:28];</a>
+<a name="3351"><span class="lineNum">    3351 </span>            :         ctrs_4_0 = _RANDOM[5'hF][31:30];</a>
+<a name="3352"><span class="lineNum">    3352 </span>            :         ctrs_4_1 = _RANDOM[5'h10][1:0];</a>
+<a name="3353"><span class="lineNum">    3353 </span>            :         ctrs_5_0 = _RANDOM[5'h10][3:2];</a>
+<a name="3354"><span class="lineNum">    3354 </span>            :         ctrs_5_1 = _RANDOM[5'h10][5:4];</a>
+<a name="3355"><span class="lineNum">    3355 </span>            :         ctrs_6_0 = _RANDOM[5'h10][7:6];</a>
+<a name="3356"><span class="lineNum">    3356 </span>            :         ctrs_6_1 = _RANDOM[5'h10][9:8];</a>
+<a name="3357"><span class="lineNum">    3357 </span>            :         ctrs_7_0 = _RANDOM[5'h10][11:10];</a>
+<a name="3358"><span class="lineNum">    3358 </span>            :         ctrs_7_1 = _RANDOM[5'h10][13:12];</a>
+<a name="3359"><span class="lineNum">    3359 </span>            :         ctrs_8_0 = _RANDOM[5'h10][15:14];</a>
+<a name="3360"><span class="lineNum">    3360 </span>            :         ctrs_8_1 = _RANDOM[5'h10][17:16];</a>
+<a name="3361"><span class="lineNum">    3361 </span>            :         ctrs_9_0 = _RANDOM[5'h10][19:18];</a>
+<a name="3362"><span class="lineNum">    3362 </span>            :         ctrs_9_1 = _RANDOM[5'h10][21:20];</a>
+<a name="3363"><span class="lineNum">    3363 </span>            :         ctrs_10_0 = _RANDOM[5'h10][23:22];</a>
+<a name="3364"><span class="lineNum">    3364 </span>            :         ctrs_10_1 = _RANDOM[5'h10][25:24];</a>
+<a name="3365"><span class="lineNum">    3365 </span>            :         ctrs_11_0 = _RANDOM[5'h10][27:26];</a>
+<a name="3366"><span class="lineNum">    3366 </span>            :         ctrs_11_1 = _RANDOM[5'h10][29:28];</a>
+<a name="3367"><span class="lineNum">    3367 </span>            :         ctrs_12_0 = _RANDOM[5'h10][31:30];</a>
+<a name="3368"><span class="lineNum">    3368 </span>            :         ctrs_12_1 = _RANDOM[5'h11][1:0];</a>
+<a name="3369"><span class="lineNum">    3369 </span>            :         ctrs_13_0 = _RANDOM[5'h11][3:2];</a>
+<a name="3370"><span class="lineNum">    3370 </span>            :         ctrs_13_1 = _RANDOM[5'h11][5:4];</a>
+<a name="3371"><span class="lineNum">    3371 </span>            :         ctrs_14_0 = _RANDOM[5'h11][7:6];</a>
+<a name="3372"><span class="lineNum">    3372 </span>            :         ctrs_14_1 = _RANDOM[5'h11][9:8];</a>
+<a name="3373"><span class="lineNum">    3373 </span>            :         ctrs_15_0 = _RANDOM[5'h11][11:10];</a>
+<a name="3374"><span class="lineNum">    3374 </span>            :         ctrs_15_1 = _RANDOM[5'h11][13:12];</a>
+<a name="3375"><span class="lineNum">    3375 </span>            :         ctrs_16_0 = _RANDOM[5'h11][15:14];</a>
+<a name="3376"><span class="lineNum">    3376 </span>            :         ctrs_16_1 = _RANDOM[5'h11][17:16];</a>
+<a name="3377"><span class="lineNum">    3377 </span>            :         ctrs_17_0 = _RANDOM[5'h11][19:18];</a>
+<a name="3378"><span class="lineNum">    3378 </span>            :         ctrs_17_1 = _RANDOM[5'h11][21:20];</a>
+<a name="3379"><span class="lineNum">    3379 </span>            :         ctrs_18_0 = _RANDOM[5'h11][23:22];</a>
+<a name="3380"><span class="lineNum">    3380 </span>            :         ctrs_18_1 = _RANDOM[5'h11][25:24];</a>
+<a name="3381"><span class="lineNum">    3381 </span>            :         ctrs_19_0 = _RANDOM[5'h11][27:26];</a>
+<a name="3382"><span class="lineNum">    3382 </span>            :         ctrs_19_1 = _RANDOM[5'h11][29:28];</a>
+<a name="3383"><span class="lineNum">    3383 </span>            :         ctrs_20_0 = _RANDOM[5'h11][31:30];</a>
+<a name="3384"><span class="lineNum">    3384 </span>            :         ctrs_20_1 = _RANDOM[5'h12][1:0];</a>
+<a name="3385"><span class="lineNum">    3385 </span>            :         ctrs_21_0 = _RANDOM[5'h12][3:2];</a>
+<a name="3386"><span class="lineNum">    3386 </span>            :         ctrs_21_1 = _RANDOM[5'h12][5:4];</a>
+<a name="3387"><span class="lineNum">    3387 </span>            :         ctrs_22_0 = _RANDOM[5'h12][7:6];</a>
+<a name="3388"><span class="lineNum">    3388 </span>            :         ctrs_22_1 = _RANDOM[5'h12][9:8];</a>
+<a name="3389"><span class="lineNum">    3389 </span>            :         ctrs_23_0 = _RANDOM[5'h12][11:10];</a>
+<a name="3390"><span class="lineNum">    3390 </span>            :         ctrs_23_1 = _RANDOM[5'h12][13:12];</a>
+<a name="3391"><span class="lineNum">    3391 </span>            :         ctrs_24_0 = _RANDOM[5'h12][15:14];</a>
+<a name="3392"><span class="lineNum">    3392 </span>            :         ctrs_24_1 = _RANDOM[5'h12][17:16];</a>
+<a name="3393"><span class="lineNum">    3393 </span>            :         ctrs_25_0 = _RANDOM[5'h12][19:18];</a>
+<a name="3394"><span class="lineNum">    3394 </span>            :         ctrs_25_1 = _RANDOM[5'h12][21:20];</a>
+<a name="3395"><span class="lineNum">    3395 </span>            :         ctrs_26_0 = _RANDOM[5'h12][23:22];</a>
+<a name="3396"><span class="lineNum">    3396 </span>            :         ctrs_26_1 = _RANDOM[5'h12][25:24];</a>
+<a name="3397"><span class="lineNum">    3397 </span>            :         ctrs_27_0 = _RANDOM[5'h12][27:26];</a>
+<a name="3398"><span class="lineNum">    3398 </span>            :         ctrs_27_1 = _RANDOM[5'h12][29:28];</a>
+<a name="3399"><span class="lineNum">    3399 </span>            :         ctrs_28_0 = _RANDOM[5'h12][31:30];</a>
+<a name="3400"><span class="lineNum">    3400 </span>            :         ctrs_28_1 = _RANDOM[5'h13][1:0];</a>
+<a name="3401"><span class="lineNum">    3401 </span>            :         ctrs_29_0 = _RANDOM[5'h13][3:2];</a>
+<a name="3402"><span class="lineNum">    3402 </span>            :         ctrs_29_1 = _RANDOM[5'h13][5:4];</a>
+<a name="3403"><span class="lineNum">    3403 </span>            :         ctrs_30_0 = _RANDOM[5'h13][7:6];</a>
+<a name="3404"><span class="lineNum">    3404 </span>            :         ctrs_30_1 = _RANDOM[5'h13][9:8];</a>
+<a name="3405"><span class="lineNum">    3405 </span>            :         ctrs_31_0 = _RANDOM[5'h13][11:10];</a>
+<a name="3406"><span class="lineNum">    3406 </span>            :         ctrs_31_1 = _RANDOM[5'h13][13:12];</a>
+<a name="3407"><span class="lineNum">    3407 </span>            :         state_reg = {_RANDOM[5'h13][31:14], _RANDOM[5'h14][12:0]};</a>
+<a name="3408"><span class="lineNum">    3408 </span>            :         fauftb_enable = _RANDOM[5'h14][13];</a>
+<a name="3409"><span class="lineNum">    3409 </span>            :         resp_meta_hit_r = _RANDOM[5'h14][14];</a>
+<a name="3410"><span class="lineNum">    3410 </span>            :         resp_meta_hit_r_1 = _RANDOM[5'h14][15];</a>
+<a name="3411"><span class="lineNum">    3411 </span>            :         resp_meta_pred_way_r = _RANDOM[5'h14][20:16];</a>
+<a name="3412"><span class="lineNum">    3412 </span>            :         resp_meta_pred_way_r_1 = _RANDOM[5'h14][25:21];</a>
+<a name="3413"><span class="lineNum">    3413 </span>            :         replacer_touch_ways_0_valid_REG = _RANDOM[5'h14][26];</a>
+<a name="3414"><span class="lineNum">    3414 </span>            :         replacer_touch_ways_0_bits_r = _RANDOM[5'h14][31:27];</a>
+<a name="3415"><span class="lineNum">    3415 </span>            :         u_s1_valid = _RANDOM[5'h15][0];</a>
+<a name="3416"><span class="lineNum">    3416 </span>            :         u_s1_tag = _RANDOM[5'h15][16:1];</a>
+<a name="3417"><span class="lineNum">    3417 </span>            :         u_s1_hit_oh = {_RANDOM[5'h15][31:17], _RANDOM[5'h16][16:0]};</a>
+<a name="3418"><span class="lineNum">    3418 </span>            :         u_s1_hit = _RANDOM[5'h16][17];</a>
+<a name="3419"><span class="lineNum">    3419 </span>            :         u_s1_ftb_entry_brSlots_0_offset = _RANDOM[5'h16][22:19];</a>
+<a name="3420"><span class="lineNum">    3420 </span>            :         u_s1_ftb_entry_brSlots_0_lower = {_RANDOM[5'h16][31:23], _RANDOM[5'h17][2:0]};</a>
+<a name="3421"><span class="lineNum">    3421 </span>            :         u_s1_ftb_entry_brSlots_0_tarStat = _RANDOM[5'h17][4:3];</a>
+<a name="3422"><span class="lineNum">    3422 </span>            :         u_s1_ftb_entry_brSlots_0_valid = _RANDOM[5'h17][6];</a>
+<a name="3423"><span class="lineNum">    3423 </span>            :         u_s1_ftb_entry_tailSlot_offset = _RANDOM[5'h17][10:7];</a>
+<a name="3424"><span class="lineNum">    3424 </span>            :         u_s1_ftb_entry_tailSlot_lower = _RANDOM[5'h17][30:11];</a>
+<a name="3425"><span class="lineNum">    3425 </span>            :         u_s1_ftb_entry_tailSlot_tarStat = {_RANDOM[5'h17][31], _RANDOM[5'h18][0]};</a>
+<a name="3426"><span class="lineNum">    3426 </span>            :         u_s1_ftb_entry_tailSlot_sharing = _RANDOM[5'h18][1];</a>
+<a name="3427"><span class="lineNum">    3427 </span>            :         u_s1_ftb_entry_tailSlot_valid = _RANDOM[5'h18][2];</a>
+<a name="3428"><span class="lineNum">    3428 </span>            :         u_s1_ftb_entry_pftAddr = _RANDOM[5'h18][6:3];</a>
+<a name="3429"><span class="lineNum">    3429 </span>            :         u_s1_ftb_entry_carry = _RANDOM[5'h18][7];</a>
+<a name="3430"><span class="lineNum">    3430 </span>            :         u_s1_ftb_entry_always_taken_0 = _RANDOM[5'h18][12];</a>
+<a name="3431"><span class="lineNum">    3431 </span>            :         u_s1_ftb_entry_always_taken_1 = _RANDOM[5'h18][13];</a>
+<a name="3432"><span class="lineNum">    3432 </span>            :         u_s1_br_update_valids_0 = _RANDOM[5'h18][14];</a>
+<a name="3433"><span class="lineNum">    3433 </span>            :         u_s1_br_update_valids_1 = _RANDOM[5'h18][15];</a>
+<a name="3434"><span class="lineNum">    3434 </span>            :         u_s1_br_takens_0 = _RANDOM[5'h18][16];</a>
+<a name="3435"><span class="lineNum">    3435 </span>            :         u_s1_br_takens_1 = _RANDOM[5'h18][17];</a>
+<a name="3436"><span class="lineNum">    3436 </span>            :         io_perf_0_value_REG = _RANDOM[5'h18][19];</a>
+<a name="3437"><span class="lineNum">    3437 </span>            :         io_perf_0_value_REG_1 = _RANDOM[5'h18][20];</a>
+<a name="3438"><span class="lineNum">    3438 </span>            :         io_perf_1_value_REG = _RANDOM[5'h18][21];</a>
+<a name="3439"><span class="lineNum">    3439 </span>            :         io_perf_1_value_REG_1 = _RANDOM[5'h18][22];</a>
+<a name="3440"><span class="lineNum">    3440 </span>            :       `endif // RANDOMIZE_REG_INIT</a>
+<a name="3441"><span class="lineNum">    3441 </span><span class="lineCov">         17 :       if (reset) begin</span></a>
+<a name="3442"><span class="lineNum">    3442 </span><span class="lineCov">         12 :         ctrs_0_0 = 2'h2;</span></a>
+<a name="3443"><span class="lineNum">    3443 </span><span class="lineCov">         12 :         ctrs_0_1 = 2'h2;</span></a>
+<a name="3444"><span class="lineNum">    3444 </span><span class="lineCov">         12 :         ctrs_1_0 = 2'h2;</span></a>
+<a name="3445"><span class="lineNum">    3445 </span><span class="lineCov">         12 :         ctrs_1_1 = 2'h2;</span></a>
+<a name="3446"><span class="lineNum">    3446 </span><span class="lineCov">         12 :         ctrs_2_0 = 2'h2;</span></a>
+<a name="3447"><span class="lineNum">    3447 </span><span class="lineCov">         12 :         ctrs_2_1 = 2'h2;</span></a>
+<a name="3448"><span class="lineNum">    3448 </span><span class="lineCov">         12 :         ctrs_3_0 = 2'h2;</span></a>
+<a name="3449"><span class="lineNum">    3449 </span><span class="lineCov">         12 :         ctrs_3_1 = 2'h2;</span></a>
+<a name="3450"><span class="lineNum">    3450 </span><span class="lineCov">         12 :         ctrs_4_0 = 2'h2;</span></a>
+<a name="3451"><span class="lineNum">    3451 </span><span class="lineCov">         12 :         ctrs_4_1 = 2'h2;</span></a>
+<a name="3452"><span class="lineNum">    3452 </span><span class="lineCov">         12 :         ctrs_5_0 = 2'h2;</span></a>
+<a name="3453"><span class="lineNum">    3453 </span><span class="lineCov">         12 :         ctrs_5_1 = 2'h2;</span></a>
+<a name="3454"><span class="lineNum">    3454 </span><span class="lineCov">         12 :         ctrs_6_0 = 2'h2;</span></a>
+<a name="3455"><span class="lineNum">    3455 </span><span class="lineCov">         12 :         ctrs_6_1 = 2'h2;</span></a>
+<a name="3456"><span class="lineNum">    3456 </span><span class="lineCov">         12 :         ctrs_7_0 = 2'h2;</span></a>
+<a name="3457"><span class="lineNum">    3457 </span><span class="lineCov">         12 :         ctrs_7_1 = 2'h2;</span></a>
+<a name="3458"><span class="lineNum">    3458 </span><span class="lineCov">         12 :         ctrs_8_0 = 2'h2;</span></a>
+<a name="3459"><span class="lineNum">    3459 </span><span class="lineCov">         12 :         ctrs_8_1 = 2'h2;</span></a>
+<a name="3460"><span class="lineNum">    3460 </span><span class="lineCov">         12 :         ctrs_9_0 = 2'h2;</span></a>
+<a name="3461"><span class="lineNum">    3461 </span><span class="lineCov">         12 :         ctrs_9_1 = 2'h2;</span></a>
+<a name="3462"><span class="lineNum">    3462 </span><span class="lineCov">         12 :         ctrs_10_0 = 2'h2;</span></a>
+<a name="3463"><span class="lineNum">    3463 </span><span class="lineCov">         12 :         ctrs_10_1 = 2'h2;</span></a>
+<a name="3464"><span class="lineNum">    3464 </span><span class="lineCov">         12 :         ctrs_11_0 = 2'h2;</span></a>
+<a name="3465"><span class="lineNum">    3465 </span><span class="lineCov">         12 :         ctrs_11_1 = 2'h2;</span></a>
+<a name="3466"><span class="lineNum">    3466 </span><span class="lineCov">         12 :         ctrs_12_0 = 2'h2;</span></a>
+<a name="3467"><span class="lineNum">    3467 </span><span class="lineCov">         12 :         ctrs_12_1 = 2'h2;</span></a>
+<a name="3468"><span class="lineNum">    3468 </span><span class="lineCov">         12 :         ctrs_13_0 = 2'h2;</span></a>
+<a name="3469"><span class="lineNum">    3469 </span><span class="lineCov">         12 :         ctrs_13_1 = 2'h2;</span></a>
+<a name="3470"><span class="lineNum">    3470 </span><span class="lineCov">         12 :         ctrs_14_0 = 2'h2;</span></a>
+<a name="3471"><span class="lineNum">    3471 </span><span class="lineCov">         12 :         ctrs_14_1 = 2'h2;</span></a>
+<a name="3472"><span class="lineNum">    3472 </span><span class="lineCov">         12 :         ctrs_15_0 = 2'h2;</span></a>
+<a name="3473"><span class="lineNum">    3473 </span><span class="lineCov">         12 :         ctrs_15_1 = 2'h2;</span></a>
+<a name="3474"><span class="lineNum">    3474 </span><span class="lineCov">         12 :         ctrs_16_0 = 2'h2;</span></a>
+<a name="3475"><span class="lineNum">    3475 </span><span class="lineCov">         12 :         ctrs_16_1 = 2'h2;</span></a>
+<a name="3476"><span class="lineNum">    3476 </span><span class="lineCov">         12 :         ctrs_17_0 = 2'h2;</span></a>
+<a name="3477"><span class="lineNum">    3477 </span><span class="lineCov">         12 :         ctrs_17_1 = 2'h2;</span></a>
+<a name="3478"><span class="lineNum">    3478 </span><span class="lineCov">         12 :         ctrs_18_0 = 2'h2;</span></a>
+<a name="3479"><span class="lineNum">    3479 </span><span class="lineCov">         12 :         ctrs_18_1 = 2'h2;</span></a>
+<a name="3480"><span class="lineNum">    3480 </span><span class="lineCov">         12 :         ctrs_19_0 = 2'h2;</span></a>
+<a name="3481"><span class="lineNum">    3481 </span><span class="lineCov">         12 :         ctrs_19_1 = 2'h2;</span></a>
+<a name="3482"><span class="lineNum">    3482 </span><span class="lineCov">         12 :         ctrs_20_0 = 2'h2;</span></a>
+<a name="3483"><span class="lineNum">    3483 </span><span class="lineCov">         12 :         ctrs_20_1 = 2'h2;</span></a>
+<a name="3484"><span class="lineNum">    3484 </span><span class="lineCov">         12 :         ctrs_21_0 = 2'h2;</span></a>
+<a name="3485"><span class="lineNum">    3485 </span><span class="lineCov">         12 :         ctrs_21_1 = 2'h2;</span></a>
+<a name="3486"><span class="lineNum">    3486 </span><span class="lineCov">         12 :         ctrs_22_0 = 2'h2;</span></a>
+<a name="3487"><span class="lineNum">    3487 </span><span class="lineCov">         12 :         ctrs_22_1 = 2'h2;</span></a>
+<a name="3488"><span class="lineNum">    3488 </span><span class="lineCov">         12 :         ctrs_23_0 = 2'h2;</span></a>
+<a name="3489"><span class="lineNum">    3489 </span><span class="lineCov">         12 :         ctrs_23_1 = 2'h2;</span></a>
+<a name="3490"><span class="lineNum">    3490 </span><span class="lineCov">         12 :         ctrs_24_0 = 2'h2;</span></a>
+<a name="3491"><span class="lineNum">    3491 </span><span class="lineCov">         12 :         ctrs_24_1 = 2'h2;</span></a>
+<a name="3492"><span class="lineNum">    3492 </span><span class="lineCov">         12 :         ctrs_25_0 = 2'h2;</span></a>
+<a name="3493"><span class="lineNum">    3493 </span><span class="lineCov">         12 :         ctrs_25_1 = 2'h2;</span></a>
+<a name="3494"><span class="lineNum">    3494 </span><span class="lineCov">         12 :         ctrs_26_0 = 2'h2;</span></a>
+<a name="3495"><span class="lineNum">    3495 </span><span class="lineCov">         12 :         ctrs_26_1 = 2'h2;</span></a>
+<a name="3496"><span class="lineNum">    3496 </span><span class="lineCov">         12 :         ctrs_27_0 = 2'h2;</span></a>
+<a name="3497"><span class="lineNum">    3497 </span><span class="lineCov">         12 :         ctrs_27_1 = 2'h2;</span></a>
+<a name="3498"><span class="lineNum">    3498 </span><span class="lineCov">         12 :         ctrs_28_0 = 2'h2;</span></a>
+<a name="3499"><span class="lineNum">    3499 </span><span class="lineCov">         12 :         ctrs_28_1 = 2'h2;</span></a>
+<a name="3500"><span class="lineNum">    3500 </span><span class="lineCov">         12 :         ctrs_29_0 = 2'h2;</span></a>
+<a name="3501"><span class="lineNum">    3501 </span><span class="lineCov">         12 :         ctrs_29_1 = 2'h2;</span></a>
+<a name="3502"><span class="lineNum">    3502 </span><span class="lineCov">         12 :         ctrs_30_0 = 2'h2;</span></a>
+<a name="3503"><span class="lineNum">    3503 </span><span class="lineCov">         12 :         ctrs_30_1 = 2'h2;</span></a>
+<a name="3504"><span class="lineNum">    3504 </span><span class="lineCov">         12 :         ctrs_31_0 = 2'h2;</span></a>
+<a name="3505"><span class="lineNum">    3505 </span><span class="lineCov">         12 :         ctrs_31_1 = 2'h2;</span></a>
+<a name="3506"><span class="lineNum">    3506 </span><span class="lineCov">         12 :         state_reg = 31'h0;</span></a>
+<a name="3507"><span class="lineNum">    3507 </span>            :       end</a>
+<a name="3508"><span class="lineNum">    3508 </span>            :     end // initial</a>
+<a name="3509"><span class="lineNum">    3509 </span>            :     `ifdef FIRRTL_AFTER_INITIAL</a>
+<a name="3510"><span class="lineNum">    3510 </span>            :       `FIRRTL_AFTER_INITIAL</a>
+<a name="3511"><span class="lineNum">    3511 </span>            :     `endif // FIRRTL_AFTER_INITIAL</a>
+<a name="3512"><span class="lineNum">    3512 </span>            :   `endif // ENABLE_INITIAL_REG_</a>
+<a name="3513"><span class="lineNum">    3513 </span>            :   DelayN_2 reset_vector_delay (</a>
+<a name="3514"><span class="lineNum">    3514 </span>            :     .clock  (clock),</a>
+<a name="3515"><span class="lineNum">    3515 </span>            :     .io_in  (io_reset_vector),</a>
+<a name="3516"><span class="lineNum">    3516 </span>            :     .io_out (_reset_vector_delay_io_out)</a>
+<a name="3517"><span class="lineNum">    3517 </span>            :   );</a>
+<a name="3518"><span class="lineNum">    3518 </span>            :   FauFTBWay ways_0 (</a>
+<a name="3519"><span class="lineNum">    3519 </span>            :     .clock                            (clock),</a>
+<a name="3520"><span class="lineNum">    3520 </span>            :     .reset                            (reset),</a>
+<a name="3521"><span class="lineNum">    3521 </span>            :     .io_req_tag                       (s1_pc_dup_0[16:1]),</a>
+<a name="3522"><span class="lineNum">    3522 </span>            :     .io_resp_brSlots_0_offset         (_ways_0_io_resp_brSlots_0_offset),</a>
+<a name="3523"><span class="lineNum">    3523 </span>            :     .io_resp_brSlots_0_lower          (_ways_0_io_resp_brSlots_0_lower),</a>
+<a name="3524"><span class="lineNum">    3524 </span>            :     .io_resp_brSlots_0_tarStat        (_ways_0_io_resp_brSlots_0_tarStat),</a>
+<a name="3525"><span class="lineNum">    3525 </span>            :     .io_resp_brSlots_0_valid          (_ways_0_io_resp_brSlots_0_valid),</a>
+<a name="3526"><span class="lineNum">    3526 </span>            :     .io_resp_tailSlot_offset          (_ways_0_io_resp_tailSlot_offset),</a>
+<a name="3527"><span class="lineNum">    3527 </span>            :     .io_resp_tailSlot_lower           (_ways_0_io_resp_tailSlot_lower),</a>
+<a name="3528"><span class="lineNum">    3528 </span>            :     .io_resp_tailSlot_tarStat         (_ways_0_io_resp_tailSlot_tarStat),</a>
+<a name="3529"><span class="lineNum">    3529 </span>            :     .io_resp_tailSlot_sharing         (_ways_0_io_resp_tailSlot_sharing),</a>
+<a name="3530"><span class="lineNum">    3530 </span>            :     .io_resp_tailSlot_valid           (_ways_0_io_resp_tailSlot_valid),</a>
+<a name="3531"><span class="lineNum">    3531 </span>            :     .io_resp_pftAddr                  (_ways_0_io_resp_pftAddr),</a>
+<a name="3532"><span class="lineNum">    3532 </span>            :     .io_resp_carry                    (_ways_0_io_resp_carry),</a>
+<a name="3533"><span class="lineNum">    3533 </span>            :     .io_resp_always_taken_0           (_ways_0_io_resp_always_taken_0),</a>
+<a name="3534"><span class="lineNum">    3534 </span>            :     .io_resp_always_taken_1           (_ways_0_io_resp_always_taken_1),</a>
+<a name="3535"><span class="lineNum">    3535 </span>            :     .io_resp_hit                      (_ways_0_io_resp_hit),</a>
+<a name="3536"><span class="lineNum">    3536 </span>            :     .io_update_req_tag                (io_update_bits_pc[16:1]),</a>
+<a name="3537"><span class="lineNum">    3537 </span>            :     .io_update_hit                    (_ways_0_io_update_hit),</a>
+<a name="3538"><span class="lineNum">    3538 </span>            :     .io_write_valid                   (u_s1_ways_write_valid_0),</a>
+<a name="3539"><span class="lineNum">    3539 </span>            :     .io_write_entry_brSlots_0_offset  (u_s1_ftb_entry_brSlots_0_offset),</a>
+<a name="3540"><span class="lineNum">    3540 </span>            :     .io_write_entry_brSlots_0_lower   (u_s1_ftb_entry_brSlots_0_lower),</a>
+<a name="3541"><span class="lineNum">    3541 </span>            :     .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat),</a>
+<a name="3542"><span class="lineNum">    3542 </span>            :     .io_write_entry_brSlots_0_valid   (u_s1_ftb_entry_brSlots_0_valid),</a>
+<a name="3543"><span class="lineNum">    3543 </span>            :     .io_write_entry_tailSlot_offset   (u_s1_ftb_entry_tailSlot_offset),</a>
+<a name="3544"><span class="lineNum">    3544 </span>            :     .io_write_entry_tailSlot_lower    (u_s1_ftb_entry_tailSlot_lower),</a>
+<a name="3545"><span class="lineNum">    3545 </span>            :     .io_write_entry_tailSlot_tarStat  (u_s1_ftb_entry_tailSlot_tarStat),</a>
+<a name="3546"><span class="lineNum">    3546 </span>            :     .io_write_entry_tailSlot_sharing  (u_s1_ftb_entry_tailSlot_sharing),</a>
+<a name="3547"><span class="lineNum">    3547 </span>            :     .io_write_entry_tailSlot_valid    (u_s1_ftb_entry_tailSlot_valid),</a>
+<a name="3548"><span class="lineNum">    3548 </span>            :     .io_write_entry_pftAddr           (u_s1_ftb_entry_pftAddr),</a>
+<a name="3549"><span class="lineNum">    3549 </span>            :     .io_write_entry_carry             (u_s1_ftb_entry_carry),</a>
+<a name="3550"><span class="lineNum">    3550 </span>            :     .io_write_entry_always_taken_0    (u_s1_ftb_entry_always_taken_0),</a>
+<a name="3551"><span class="lineNum">    3551 </span>            :     .io_write_entry_always_taken_1    (u_s1_ftb_entry_always_taken_1),</a>
+<a name="3552"><span class="lineNum">    3552 </span>            :     .io_write_tag                     (u_s1_tag)</a>
+<a name="3553"><span class="lineNum">    3553 </span>            :   );</a>
+<a name="3554"><span class="lineNum">    3554 </span>            :   FauFTBWay ways_1 (</a>
+<a name="3555"><span class="lineNum">    3555 </span>            :     .clock                            (clock),</a>
+<a name="3556"><span class="lineNum">    3556 </span>            :     .reset                            (reset),</a>
+<a name="3557"><span class="lineNum">    3557 </span>            :     .io_req_tag                       (s1_pc_dup_0[16:1]),</a>
+<a name="3558"><span class="lineNum">    3558 </span>            :     .io_resp_brSlots_0_offset         (_ways_1_io_resp_brSlots_0_offset),</a>
+<a name="3559"><span class="lineNum">    3559 </span>            :     .io_resp_brSlots_0_lower          (_ways_1_io_resp_brSlots_0_lower),</a>
+<a name="3560"><span class="lineNum">    3560 </span>            :     .io_resp_brSlots_0_tarStat        (_ways_1_io_resp_brSlots_0_tarStat),</a>
+<a name="3561"><span class="lineNum">    3561 </span>            :     .io_resp_brSlots_0_valid          (_ways_1_io_resp_brSlots_0_valid),</a>
+<a name="3562"><span class="lineNum">    3562 </span>            :     .io_resp_tailSlot_offset          (_ways_1_io_resp_tailSlot_offset),</a>
+<a name="3563"><span class="lineNum">    3563 </span>            :     .io_resp_tailSlot_lower           (_ways_1_io_resp_tailSlot_lower),</a>
+<a name="3564"><span class="lineNum">    3564 </span>            :     .io_resp_tailSlot_tarStat         (_ways_1_io_resp_tailSlot_tarStat),</a>
+<a name="3565"><span class="lineNum">    3565 </span>            :     .io_resp_tailSlot_sharing         (_ways_1_io_resp_tailSlot_sharing),</a>
+<a name="3566"><span class="lineNum">    3566 </span>            :     .io_resp_tailSlot_valid           (_ways_1_io_resp_tailSlot_valid),</a>
+<a name="3567"><span class="lineNum">    3567 </span>            :     .io_resp_pftAddr                  (_ways_1_io_resp_pftAddr),</a>
+<a name="3568"><span class="lineNum">    3568 </span>            :     .io_resp_carry                    (_ways_1_io_resp_carry),</a>
+<a name="3569"><span class="lineNum">    3569 </span>            :     .io_resp_always_taken_0           (_ways_1_io_resp_always_taken_0),</a>
+<a name="3570"><span class="lineNum">    3570 </span>            :     .io_resp_always_taken_1           (_ways_1_io_resp_always_taken_1),</a>
+<a name="3571"><span class="lineNum">    3571 </span>            :     .io_resp_hit                      (_ways_1_io_resp_hit),</a>
+<a name="3572"><span class="lineNum">    3572 </span>            :     .io_update_req_tag                (io_update_bits_pc[16:1]),</a>
+<a name="3573"><span class="lineNum">    3573 </span>            :     .io_update_hit                    (_ways_1_io_update_hit),</a>
+<a name="3574"><span class="lineNum">    3574 </span>            :     .io_write_valid                   (u_s1_ways_write_valid_1),</a>
+<a name="3575"><span class="lineNum">    3575 </span>            :     .io_write_entry_brSlots_0_offset  (u_s1_ftb_entry_brSlots_0_offset),</a>
+<a name="3576"><span class="lineNum">    3576 </span>            :     .io_write_entry_brSlots_0_lower   (u_s1_ftb_entry_brSlots_0_lower),</a>
+<a name="3577"><span class="lineNum">    3577 </span>            :     .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat),</a>
+<a name="3578"><span class="lineNum">    3578 </span>            :     .io_write_entry_brSlots_0_valid   (u_s1_ftb_entry_brSlots_0_valid),</a>
+<a name="3579"><span class="lineNum">    3579 </span>            :     .io_write_entry_tailSlot_offset   (u_s1_ftb_entry_tailSlot_offset),</a>
+<a name="3580"><span class="lineNum">    3580 </span>            :     .io_write_entry_tailSlot_lower    (u_s1_ftb_entry_tailSlot_lower),</a>
+<a name="3581"><span class="lineNum">    3581 </span>            :     .io_write_entry_tailSlot_tarStat  (u_s1_ftb_entry_tailSlot_tarStat),</a>
+<a name="3582"><span class="lineNum">    3582 </span>            :     .io_write_entry_tailSlot_sharing  (u_s1_ftb_entry_tailSlot_sharing),</a>
+<a name="3583"><span class="lineNum">    3583 </span>            :     .io_write_entry_tailSlot_valid    (u_s1_ftb_entry_tailSlot_valid),</a>
+<a name="3584"><span class="lineNum">    3584 </span>            :     .io_write_entry_pftAddr           (u_s1_ftb_entry_pftAddr),</a>
+<a name="3585"><span class="lineNum">    3585 </span>            :     .io_write_entry_carry             (u_s1_ftb_entry_carry),</a>
+<a name="3586"><span class="lineNum">    3586 </span>            :     .io_write_entry_always_taken_0    (u_s1_ftb_entry_always_taken_0),</a>
+<a name="3587"><span class="lineNum">    3587 </span>            :     .io_write_entry_always_taken_1    (u_s1_ftb_entry_always_taken_1),</a>
+<a name="3588"><span class="lineNum">    3588 </span>            :     .io_write_tag                     (u_s1_tag)</a>
+<a name="3589"><span class="lineNum">    3589 </span>            :   );</a>
+<a name="3590"><span class="lineNum">    3590 </span>            :   FauFTBWay ways_2 (</a>
+<a name="3591"><span class="lineNum">    3591 </span>            :     .clock                            (clock),</a>
+<a name="3592"><span class="lineNum">    3592 </span>            :     .reset                            (reset),</a>
+<a name="3593"><span class="lineNum">    3593 </span>            :     .io_req_tag                       (s1_pc_dup_0[16:1]),</a>
+<a name="3594"><span class="lineNum">    3594 </span>            :     .io_resp_brSlots_0_offset         (_ways_2_io_resp_brSlots_0_offset),</a>
+<a name="3595"><span class="lineNum">    3595 </span>            :     .io_resp_brSlots_0_lower          (_ways_2_io_resp_brSlots_0_lower),</a>
+<a name="3596"><span class="lineNum">    3596 </span>            :     .io_resp_brSlots_0_tarStat        (_ways_2_io_resp_brSlots_0_tarStat),</a>
+<a name="3597"><span class="lineNum">    3597 </span>            :     .io_resp_brSlots_0_valid          (_ways_2_io_resp_brSlots_0_valid),</a>
+<a name="3598"><span class="lineNum">    3598 </span>            :     .io_resp_tailSlot_offset          (_ways_2_io_resp_tailSlot_offset),</a>
+<a name="3599"><span class="lineNum">    3599 </span>            :     .io_resp_tailSlot_lower           (_ways_2_io_resp_tailSlot_lower),</a>
+<a name="3600"><span class="lineNum">    3600 </span>            :     .io_resp_tailSlot_tarStat         (_ways_2_io_resp_tailSlot_tarStat),</a>
+<a name="3601"><span class="lineNum">    3601 </span>            :     .io_resp_tailSlot_sharing         (_ways_2_io_resp_tailSlot_sharing),</a>
+<a name="3602"><span class="lineNum">    3602 </span>            :     .io_resp_tailSlot_valid           (_ways_2_io_resp_tailSlot_valid),</a>
+<a name="3603"><span class="lineNum">    3603 </span>            :     .io_resp_pftAddr                  (_ways_2_io_resp_pftAddr),</a>
+<a name="3604"><span class="lineNum">    3604 </span>            :     .io_resp_carry                    (_ways_2_io_resp_carry),</a>
+<a name="3605"><span class="lineNum">    3605 </span>            :     .io_resp_always_taken_0           (_ways_2_io_resp_always_taken_0),</a>
+<a name="3606"><span class="lineNum">    3606 </span>            :     .io_resp_always_taken_1           (_ways_2_io_resp_always_taken_1),</a>
+<a name="3607"><span class="lineNum">    3607 </span>            :     .io_resp_hit                      (_ways_2_io_resp_hit),</a>
+<a name="3608"><span class="lineNum">    3608 </span>            :     .io_update_req_tag                (io_update_bits_pc[16:1]),</a>
+<a name="3609"><span class="lineNum">    3609 </span>            :     .io_update_hit                    (_ways_2_io_update_hit),</a>
+<a name="3610"><span class="lineNum">    3610 </span>            :     .io_write_valid                   (u_s1_ways_write_valid_2),</a>
+<a name="3611"><span class="lineNum">    3611 </span>            :     .io_write_entry_brSlots_0_offset  (u_s1_ftb_entry_brSlots_0_offset),</a>
+<a name="3612"><span class="lineNum">    3612 </span>            :     .io_write_entry_brSlots_0_lower   (u_s1_ftb_entry_brSlots_0_lower),</a>
+<a name="3613"><span class="lineNum">    3613 </span>            :     .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat),</a>
+<a name="3614"><span class="lineNum">    3614 </span>            :     .io_write_entry_brSlots_0_valid   (u_s1_ftb_entry_brSlots_0_valid),</a>
+<a name="3615"><span class="lineNum">    3615 </span>            :     .io_write_entry_tailSlot_offset   (u_s1_ftb_entry_tailSlot_offset),</a>
+<a name="3616"><span class="lineNum">    3616 </span>            :     .io_write_entry_tailSlot_lower    (u_s1_ftb_entry_tailSlot_lower),</a>
+<a name="3617"><span class="lineNum">    3617 </span>            :     .io_write_entry_tailSlot_tarStat  (u_s1_ftb_entry_tailSlot_tarStat),</a>
+<a name="3618"><span class="lineNum">    3618 </span>            :     .io_write_entry_tailSlot_sharing  (u_s1_ftb_entry_tailSlot_sharing),</a>
+<a name="3619"><span class="lineNum">    3619 </span>            :     .io_write_entry_tailSlot_valid    (u_s1_ftb_entry_tailSlot_valid),</a>
+<a name="3620"><span class="lineNum">    3620 </span>            :     .io_write_entry_pftAddr           (u_s1_ftb_entry_pftAddr),</a>
+<a name="3621"><span class="lineNum">    3621 </span>            :     .io_write_entry_carry             (u_s1_ftb_entry_carry),</a>
+<a name="3622"><span class="lineNum">    3622 </span>            :     .io_write_entry_always_taken_0    (u_s1_ftb_entry_always_taken_0),</a>
+<a name="3623"><span class="lineNum">    3623 </span>            :     .io_write_entry_always_taken_1    (u_s1_ftb_entry_always_taken_1),</a>
+<a name="3624"><span class="lineNum">    3624 </span>            :     .io_write_tag                     (u_s1_tag)</a>
+<a name="3625"><span class="lineNum">    3625 </span>            :   );</a>
+<a name="3626"><span class="lineNum">    3626 </span>            :   FauFTBWay ways_3 (</a>
+<a name="3627"><span class="lineNum">    3627 </span>            :     .clock                            (clock),</a>
+<a name="3628"><span class="lineNum">    3628 </span>            :     .reset                            (reset),</a>
+<a name="3629"><span class="lineNum">    3629 </span>            :     .io_req_tag                       (s1_pc_dup_0[16:1]),</a>
+<a name="3630"><span class="lineNum">    3630 </span>            :     .io_resp_brSlots_0_offset         (_ways_3_io_resp_brSlots_0_offset),</a>
+<a name="3631"><span class="lineNum">    3631 </span>            :     .io_resp_brSlots_0_lower          (_ways_3_io_resp_brSlots_0_lower),</a>
+<a name="3632"><span class="lineNum">    3632 </span>            :     .io_resp_brSlots_0_tarStat        (_ways_3_io_resp_brSlots_0_tarStat),</a>
+<a name="3633"><span class="lineNum">    3633 </span>            :     .io_resp_brSlots_0_valid          (_ways_3_io_resp_brSlots_0_valid),</a>
+<a name="3634"><span class="lineNum">    3634 </span>            :     .io_resp_tailSlot_offset          (_ways_3_io_resp_tailSlot_offset),</a>
+<a name="3635"><span class="lineNum">    3635 </span>            :     .io_resp_tailSlot_lower           (_ways_3_io_resp_tailSlot_lower),</a>
+<a name="3636"><span class="lineNum">    3636 </span>            :     .io_resp_tailSlot_tarStat         (_ways_3_io_resp_tailSlot_tarStat),</a>
+<a name="3637"><span class="lineNum">    3637 </span>            :     .io_resp_tailSlot_sharing         (_ways_3_io_resp_tailSlot_sharing),</a>
+<a name="3638"><span class="lineNum">    3638 </span>            :     .io_resp_tailSlot_valid           (_ways_3_io_resp_tailSlot_valid),</a>
+<a name="3639"><span class="lineNum">    3639 </span>            :     .io_resp_pftAddr                  (_ways_3_io_resp_pftAddr),</a>
+<a name="3640"><span class="lineNum">    3640 </span>            :     .io_resp_carry                    (_ways_3_io_resp_carry),</a>
+<a name="3641"><span class="lineNum">    3641 </span>            :     .io_resp_always_taken_0           (_ways_3_io_resp_always_taken_0),</a>
+<a name="3642"><span class="lineNum">    3642 </span>            :     .io_resp_always_taken_1           (_ways_3_io_resp_always_taken_1),</a>
+<a name="3643"><span class="lineNum">    3643 </span>            :     .io_resp_hit                      (_ways_3_io_resp_hit),</a>
+<a name="3644"><span class="lineNum">    3644 </span>            :     .io_update_req_tag                (io_update_bits_pc[16:1]),</a>
+<a name="3645"><span class="lineNum">    3645 </span>            :     .io_update_hit                    (_ways_3_io_update_hit),</a>
+<a name="3646"><span class="lineNum">    3646 </span>            :     .io_write_valid                   (u_s1_ways_write_valid_3),</a>
+<a name="3647"><span class="lineNum">    3647 </span>            :     .io_write_entry_brSlots_0_offset  (u_s1_ftb_entry_brSlots_0_offset),</a>
+<a name="3648"><span class="lineNum">    3648 </span>            :     .io_write_entry_brSlots_0_lower   (u_s1_ftb_entry_brSlots_0_lower),</a>
+<a name="3649"><span class="lineNum">    3649 </span>            :     .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat),</a>
+<a name="3650"><span class="lineNum">    3650 </span>            :     .io_write_entry_brSlots_0_valid   (u_s1_ftb_entry_brSlots_0_valid),</a>
+<a name="3651"><span class="lineNum">    3651 </span>            :     .io_write_entry_tailSlot_offset   (u_s1_ftb_entry_tailSlot_offset),</a>
+<a name="3652"><span class="lineNum">    3652 </span>            :     .io_write_entry_tailSlot_lower    (u_s1_ftb_entry_tailSlot_lower),</a>
+<a name="3653"><span class="lineNum">    3653 </span>            :     .io_write_entry_tailSlot_tarStat  (u_s1_ftb_entry_tailSlot_tarStat),</a>
+<a name="3654"><span class="lineNum">    3654 </span>            :     .io_write_entry_tailSlot_sharing  (u_s1_ftb_entry_tailSlot_sharing),</a>
+<a name="3655"><span class="lineNum">    3655 </span>            :     .io_write_entry_tailSlot_valid    (u_s1_ftb_entry_tailSlot_valid),</a>
+<a name="3656"><span class="lineNum">    3656 </span>            :     .io_write_entry_pftAddr           (u_s1_ftb_entry_pftAddr),</a>
+<a name="3657"><span class="lineNum">    3657 </span>            :     .io_write_entry_carry             (u_s1_ftb_entry_carry),</a>
+<a name="3658"><span class="lineNum">    3658 </span>            :     .io_write_entry_always_taken_0    (u_s1_ftb_entry_always_taken_0),</a>
+<a name="3659"><span class="lineNum">    3659 </span>            :     .io_write_entry_always_taken_1    (u_s1_ftb_entry_always_taken_1),</a>
+<a name="3660"><span class="lineNum">    3660 </span>            :     .io_write_tag                     (u_s1_tag)</a>
+<a name="3661"><span class="lineNum">    3661 </span>            :   );</a>
+<a name="3662"><span class="lineNum">    3662 </span>            :   FauFTBWay ways_4 (</a>
+<a name="3663"><span class="lineNum">    3663 </span>            :     .clock                            (clock),</a>
+<a name="3664"><span class="lineNum">    3664 </span>            :     .reset                            (reset),</a>
+<a name="3665"><span class="lineNum">    3665 </span>            :     .io_req_tag                       (s1_pc_dup_0[16:1]),</a>
+<a name="3666"><span class="lineNum">    3666 </span>            :     .io_resp_brSlots_0_offset         (_ways_4_io_resp_brSlots_0_offset),</a>
+<a name="3667"><span class="lineNum">    3667 </span>            :     .io_resp_brSlots_0_lower          (_ways_4_io_resp_brSlots_0_lower),</a>
+<a name="3668"><span class="lineNum">    3668 </span>            :     .io_resp_brSlots_0_tarStat        (_ways_4_io_resp_brSlots_0_tarStat),</a>
+<a name="3669"><span class="lineNum">    3669 </span>            :     .io_resp_brSlots_0_valid          (_ways_4_io_resp_brSlots_0_valid),</a>
+<a name="3670"><span class="lineNum">    3670 </span>            :     .io_resp_tailSlot_offset          (_ways_4_io_resp_tailSlot_offset),</a>
+<a name="3671"><span class="lineNum">    3671 </span>            :     .io_resp_tailSlot_lower           (_ways_4_io_resp_tailSlot_lower),</a>
+<a name="3672"><span class="lineNum">    3672 </span>            :     .io_resp_tailSlot_tarStat         (_ways_4_io_resp_tailSlot_tarStat),</a>
+<a name="3673"><span class="lineNum">    3673 </span>            :     .io_resp_tailSlot_sharing         (_ways_4_io_resp_tailSlot_sharing),</a>
+<a name="3674"><span class="lineNum">    3674 </span>            :     .io_resp_tailSlot_valid           (_ways_4_io_resp_tailSlot_valid),</a>
+<a name="3675"><span class="lineNum">    3675 </span>            :     .io_resp_pftAddr                  (_ways_4_io_resp_pftAddr),</a>
+<a name="3676"><span class="lineNum">    3676 </span>            :     .io_resp_carry                    (_ways_4_io_resp_carry),</a>
+<a name="3677"><span class="lineNum">    3677 </span>            :     .io_resp_always_taken_0           (_ways_4_io_resp_always_taken_0),</a>
+<a name="3678"><span class="lineNum">    3678 </span>            :     .io_resp_always_taken_1           (_ways_4_io_resp_always_taken_1),</a>
+<a name="3679"><span class="lineNum">    3679 </span>            :     .io_resp_hit                      (_ways_4_io_resp_hit),</a>
+<a name="3680"><span class="lineNum">    3680 </span>            :     .io_update_req_tag                (io_update_bits_pc[16:1]),</a>
+<a name="3681"><span class="lineNum">    3681 </span>            :     .io_update_hit                    (_ways_4_io_update_hit),</a>
+<a name="3682"><span class="lineNum">    3682 </span>            :     .io_write_valid                   (u_s1_ways_write_valid_4),</a>
+<a name="3683"><span class="lineNum">    3683 </span>            :     .io_write_entry_brSlots_0_offset  (u_s1_ftb_entry_brSlots_0_offset),</a>
+<a name="3684"><span class="lineNum">    3684 </span>            :     .io_write_entry_brSlots_0_lower   (u_s1_ftb_entry_brSlots_0_lower),</a>
+<a name="3685"><span class="lineNum">    3685 </span>            :     .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat),</a>
+<a name="3686"><span class="lineNum">    3686 </span>            :     .io_write_entry_brSlots_0_valid   (u_s1_ftb_entry_brSlots_0_valid),</a>
+<a name="3687"><span class="lineNum">    3687 </span>            :     .io_write_entry_tailSlot_offset   (u_s1_ftb_entry_tailSlot_offset),</a>
+<a name="3688"><span class="lineNum">    3688 </span>            :     .io_write_entry_tailSlot_lower    (u_s1_ftb_entry_tailSlot_lower),</a>
+<a name="3689"><span class="lineNum">    3689 </span>            :     .io_write_entry_tailSlot_tarStat  (u_s1_ftb_entry_tailSlot_tarStat),</a>
+<a name="3690"><span class="lineNum">    3690 </span>            :     .io_write_entry_tailSlot_sharing  (u_s1_ftb_entry_tailSlot_sharing),</a>
+<a name="3691"><span class="lineNum">    3691 </span>            :     .io_write_entry_tailSlot_valid    (u_s1_ftb_entry_tailSlot_valid),</a>
+<a name="3692"><span class="lineNum">    3692 </span>            :     .io_write_entry_pftAddr           (u_s1_ftb_entry_pftAddr),</a>
+<a name="3693"><span class="lineNum">    3693 </span>            :     .io_write_entry_carry             (u_s1_ftb_entry_carry),</a>
+<a name="3694"><span class="lineNum">    3694 </span>            :     .io_write_entry_always_taken_0    (u_s1_ftb_entry_always_taken_0),</a>
+<a name="3695"><span class="lineNum">    3695 </span>            :     .io_write_entry_always_taken_1    (u_s1_ftb_entry_always_taken_1),</a>
+<a name="3696"><span class="lineNum">    3696 </span>            :     .io_write_tag                     (u_s1_tag)</a>
+<a name="3697"><span class="lineNum">    3697 </span>            :   );</a>
+<a name="3698"><span class="lineNum">    3698 </span>            :   FauFTBWay ways_5 (</a>
+<a name="3699"><span class="lineNum">    3699 </span>            :     .clock                            (clock),</a>
+<a name="3700"><span class="lineNum">    3700 </span>            :     .reset                            (reset),</a>
+<a name="3701"><span class="lineNum">    3701 </span>            :     .io_req_tag                       (s1_pc_dup_0[16:1]),</a>
+<a name="3702"><span class="lineNum">    3702 </span>            :     .io_resp_brSlots_0_offset         (_ways_5_io_resp_brSlots_0_offset),</a>
+<a name="3703"><span class="lineNum">    3703 </span>            :     .io_resp_brSlots_0_lower          (_ways_5_io_resp_brSlots_0_lower),</a>
+<a name="3704"><span class="lineNum">    3704 </span>            :     .io_resp_brSlots_0_tarStat        (_ways_5_io_resp_brSlots_0_tarStat),</a>
+<a name="3705"><span class="lineNum">    3705 </span>            :     .io_resp_brSlots_0_valid          (_ways_5_io_resp_brSlots_0_valid),</a>
+<a name="3706"><span class="lineNum">    3706 </span>            :     .io_resp_tailSlot_offset          (_ways_5_io_resp_tailSlot_offset),</a>
+<a name="3707"><span class="lineNum">    3707 </span>            :     .io_resp_tailSlot_lower           (_ways_5_io_resp_tailSlot_lower),</a>
+<a name="3708"><span class="lineNum">    3708 </span>            :     .io_resp_tailSlot_tarStat         (_ways_5_io_resp_tailSlot_tarStat),</a>
+<a name="3709"><span class="lineNum">    3709 </span>            :     .io_resp_tailSlot_sharing         (_ways_5_io_resp_tailSlot_sharing),</a>
+<a name="3710"><span class="lineNum">    3710 </span>            :     .io_resp_tailSlot_valid           (_ways_5_io_resp_tailSlot_valid),</a>
+<a name="3711"><span class="lineNum">    3711 </span>            :     .io_resp_pftAddr                  (_ways_5_io_resp_pftAddr),</a>
+<a name="3712"><span class="lineNum">    3712 </span>            :     .io_resp_carry                    (_ways_5_io_resp_carry),</a>
+<a name="3713"><span class="lineNum">    3713 </span>            :     .io_resp_always_taken_0           (_ways_5_io_resp_always_taken_0),</a>
+<a name="3714"><span class="lineNum">    3714 </span>            :     .io_resp_always_taken_1           (_ways_5_io_resp_always_taken_1),</a>
+<a name="3715"><span class="lineNum">    3715 </span>            :     .io_resp_hit                      (_ways_5_io_resp_hit),</a>
+<a name="3716"><span class="lineNum">    3716 </span>            :     .io_update_req_tag                (io_update_bits_pc[16:1]),</a>
+<a name="3717"><span class="lineNum">    3717 </span>            :     .io_update_hit                    (_ways_5_io_update_hit),</a>
+<a name="3718"><span class="lineNum">    3718 </span>            :     .io_write_valid                   (u_s1_ways_write_valid_5),</a>
+<a name="3719"><span class="lineNum">    3719 </span>            :     .io_write_entry_brSlots_0_offset  (u_s1_ftb_entry_brSlots_0_offset),</a>
+<a name="3720"><span class="lineNum">    3720 </span>            :     .io_write_entry_brSlots_0_lower   (u_s1_ftb_entry_brSlots_0_lower),</a>
+<a name="3721"><span class="lineNum">    3721 </span>            :     .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat),</a>
+<a name="3722"><span class="lineNum">    3722 </span>            :     .io_write_entry_brSlots_0_valid   (u_s1_ftb_entry_brSlots_0_valid),</a>
+<a name="3723"><span class="lineNum">    3723 </span>            :     .io_write_entry_tailSlot_offset   (u_s1_ftb_entry_tailSlot_offset),</a>
+<a name="3724"><span class="lineNum">    3724 </span>            :     .io_write_entry_tailSlot_lower    (u_s1_ftb_entry_tailSlot_lower),</a>
+<a name="3725"><span class="lineNum">    3725 </span>            :     .io_write_entry_tailSlot_tarStat  (u_s1_ftb_entry_tailSlot_tarStat),</a>
+<a name="3726"><span class="lineNum">    3726 </span>            :     .io_write_entry_tailSlot_sharing  (u_s1_ftb_entry_tailSlot_sharing),</a>
+<a name="3727"><span class="lineNum">    3727 </span>            :     .io_write_entry_tailSlot_valid    (u_s1_ftb_entry_tailSlot_valid),</a>
+<a name="3728"><span class="lineNum">    3728 </span>            :     .io_write_entry_pftAddr           (u_s1_ftb_entry_pftAddr),</a>
+<a name="3729"><span class="lineNum">    3729 </span>            :     .io_write_entry_carry             (u_s1_ftb_entry_carry),</a>
+<a name="3730"><span class="lineNum">    3730 </span>            :     .io_write_entry_always_taken_0    (u_s1_ftb_entry_always_taken_0),</a>
+<a name="3731"><span class="lineNum">    3731 </span>            :     .io_write_entry_always_taken_1    (u_s1_ftb_entry_always_taken_1),</a>
+<a name="3732"><span class="lineNum">    3732 </span>            :     .io_write_tag                     (u_s1_tag)</a>
+<a name="3733"><span class="lineNum">    3733 </span>            :   );</a>
+<a name="3734"><span class="lineNum">    3734 </span>            :   FauFTBWay ways_6 (</a>
+<a name="3735"><span class="lineNum">    3735 </span>            :     .clock                            (clock),</a>
+<a name="3736"><span class="lineNum">    3736 </span>            :     .reset                            (reset),</a>
+<a name="3737"><span class="lineNum">    3737 </span>            :     .io_req_tag                       (s1_pc_dup_0[16:1]),</a>
+<a name="3738"><span class="lineNum">    3738 </span>            :     .io_resp_brSlots_0_offset         (_ways_6_io_resp_brSlots_0_offset),</a>
+<a name="3739"><span class="lineNum">    3739 </span>            :     .io_resp_brSlots_0_lower          (_ways_6_io_resp_brSlots_0_lower),</a>
+<a name="3740"><span class="lineNum">    3740 </span>            :     .io_resp_brSlots_0_tarStat        (_ways_6_io_resp_brSlots_0_tarStat),</a>
+<a name="3741"><span class="lineNum">    3741 </span>            :     .io_resp_brSlots_0_valid          (_ways_6_io_resp_brSlots_0_valid),</a>
+<a name="3742"><span class="lineNum">    3742 </span>            :     .io_resp_tailSlot_offset          (_ways_6_io_resp_tailSlot_offset),</a>
+<a name="3743"><span class="lineNum">    3743 </span>            :     .io_resp_tailSlot_lower           (_ways_6_io_resp_tailSlot_lower),</a>
+<a name="3744"><span class="lineNum">    3744 </span>            :     .io_resp_tailSlot_tarStat         (_ways_6_io_resp_tailSlot_tarStat),</a>
+<a name="3745"><span class="lineNum">    3745 </span>            :     .io_resp_tailSlot_sharing         (_ways_6_io_resp_tailSlot_sharing),</a>
+<a name="3746"><span class="lineNum">    3746 </span>            :     .io_resp_tailSlot_valid           (_ways_6_io_resp_tailSlot_valid),</a>
+<a name="3747"><span class="lineNum">    3747 </span>            :     .io_resp_pftAddr                  (_ways_6_io_resp_pftAddr),</a>
+<a name="3748"><span class="lineNum">    3748 </span>            :     .io_resp_carry                    (_ways_6_io_resp_carry),</a>
+<a name="3749"><span class="lineNum">    3749 </span>            :     .io_resp_always_taken_0           (_ways_6_io_resp_always_taken_0),</a>
+<a name="3750"><span class="lineNum">    3750 </span>            :     .io_resp_always_taken_1           (_ways_6_io_resp_always_taken_1),</a>
+<a name="3751"><span class="lineNum">    3751 </span>            :     .io_resp_hit                      (_ways_6_io_resp_hit),</a>
+<a name="3752"><span class="lineNum">    3752 </span>            :     .io_update_req_tag                (io_update_bits_pc[16:1]),</a>
+<a name="3753"><span class="lineNum">    3753 </span>            :     .io_update_hit                    (_ways_6_io_update_hit),</a>
+<a name="3754"><span class="lineNum">    3754 </span>            :     .io_write_valid                   (u_s1_ways_write_valid_6),</a>
+<a name="3755"><span class="lineNum">    3755 </span>            :     .io_write_entry_brSlots_0_offset  (u_s1_ftb_entry_brSlots_0_offset),</a>
+<a name="3756"><span class="lineNum">    3756 </span>            :     .io_write_entry_brSlots_0_lower   (u_s1_ftb_entry_brSlots_0_lower),</a>
+<a name="3757"><span class="lineNum">    3757 </span>            :     .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat),</a>
+<a name="3758"><span class="lineNum">    3758 </span>            :     .io_write_entry_brSlots_0_valid   (u_s1_ftb_entry_brSlots_0_valid),</a>
+<a name="3759"><span class="lineNum">    3759 </span>            :     .io_write_entry_tailSlot_offset   (u_s1_ftb_entry_tailSlot_offset),</a>
+<a name="3760"><span class="lineNum">    3760 </span>            :     .io_write_entry_tailSlot_lower    (u_s1_ftb_entry_tailSlot_lower),</a>
+<a name="3761"><span class="lineNum">    3761 </span>            :     .io_write_entry_tailSlot_tarStat  (u_s1_ftb_entry_tailSlot_tarStat),</a>
+<a name="3762"><span class="lineNum">    3762 </span>            :     .io_write_entry_tailSlot_sharing  (u_s1_ftb_entry_tailSlot_sharing),</a>
+<a name="3763"><span class="lineNum">    3763 </span>            :     .io_write_entry_tailSlot_valid    (u_s1_ftb_entry_tailSlot_valid),</a>
+<a name="3764"><span class="lineNum">    3764 </span>            :     .io_write_entry_pftAddr           (u_s1_ftb_entry_pftAddr),</a>
+<a name="3765"><span class="lineNum">    3765 </span>            :     .io_write_entry_carry             (u_s1_ftb_entry_carry),</a>
+<a name="3766"><span class="lineNum">    3766 </span>            :     .io_write_entry_always_taken_0    (u_s1_ftb_entry_always_taken_0),</a>
+<a name="3767"><span class="lineNum">    3767 </span>            :     .io_write_entry_always_taken_1    (u_s1_ftb_entry_always_taken_1),</a>
+<a name="3768"><span class="lineNum">    3768 </span>            :     .io_write_tag                     (u_s1_tag)</a>
+<a name="3769"><span class="lineNum">    3769 </span>            :   );</a>
+<a name="3770"><span class="lineNum">    3770 </span>            :   FauFTBWay ways_7 (</a>
+<a name="3771"><span class="lineNum">    3771 </span>            :     .clock                            (clock),</a>
+<a name="3772"><span class="lineNum">    3772 </span>            :     .reset                            (reset),</a>
+<a name="3773"><span class="lineNum">    3773 </span>            :     .io_req_tag                       (s1_pc_dup_0[16:1]),</a>
+<a name="3774"><span class="lineNum">    3774 </span>            :     .io_resp_brSlots_0_offset         (_ways_7_io_resp_brSlots_0_offset),</a>
+<a name="3775"><span class="lineNum">    3775 </span>            :     .io_resp_brSlots_0_lower          (_ways_7_io_resp_brSlots_0_lower),</a>
+<a name="3776"><span class="lineNum">    3776 </span>            :     .io_resp_brSlots_0_tarStat        (_ways_7_io_resp_brSlots_0_tarStat),</a>
+<a name="3777"><span class="lineNum">    3777 </span>            :     .io_resp_brSlots_0_valid          (_ways_7_io_resp_brSlots_0_valid),</a>
+<a name="3778"><span class="lineNum">    3778 </span>            :     .io_resp_tailSlot_offset          (_ways_7_io_resp_tailSlot_offset),</a>
+<a name="3779"><span class="lineNum">    3779 </span>            :     .io_resp_tailSlot_lower           (_ways_7_io_resp_tailSlot_lower),</a>
+<a name="3780"><span class="lineNum">    3780 </span>            :     .io_resp_tailSlot_tarStat         (_ways_7_io_resp_tailSlot_tarStat),</a>
+<a name="3781"><span class="lineNum">    3781 </span>            :     .io_resp_tailSlot_sharing         (_ways_7_io_resp_tailSlot_sharing),</a>
+<a name="3782"><span class="lineNum">    3782 </span>            :     .io_resp_tailSlot_valid           (_ways_7_io_resp_tailSlot_valid),</a>
+<a name="3783"><span class="lineNum">    3783 </span>            :     .io_resp_pftAddr                  (_ways_7_io_resp_pftAddr),</a>
+<a name="3784"><span class="lineNum">    3784 </span>            :     .io_resp_carry                    (_ways_7_io_resp_carry),</a>
+<a name="3785"><span class="lineNum">    3785 </span>            :     .io_resp_always_taken_0           (_ways_7_io_resp_always_taken_0),</a>
+<a name="3786"><span class="lineNum">    3786 </span>            :     .io_resp_always_taken_1           (_ways_7_io_resp_always_taken_1),</a>
+<a name="3787"><span class="lineNum">    3787 </span>            :     .io_resp_hit                      (_ways_7_io_resp_hit),</a>
+<a name="3788"><span class="lineNum">    3788 </span>            :     .io_update_req_tag                (io_update_bits_pc[16:1]),</a>
+<a name="3789"><span class="lineNum">    3789 </span>            :     .io_update_hit                    (_ways_7_io_update_hit),</a>
+<a name="3790"><span class="lineNum">    3790 </span>            :     .io_write_valid                   (u_s1_ways_write_valid_7),</a>
+<a name="3791"><span class="lineNum">    3791 </span>            :     .io_write_entry_brSlots_0_offset  (u_s1_ftb_entry_brSlots_0_offset),</a>
+<a name="3792"><span class="lineNum">    3792 </span>            :     .io_write_entry_brSlots_0_lower   (u_s1_ftb_entry_brSlots_0_lower),</a>
+<a name="3793"><span class="lineNum">    3793 </span>            :     .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat),</a>
+<a name="3794"><span class="lineNum">    3794 </span>            :     .io_write_entry_brSlots_0_valid   (u_s1_ftb_entry_brSlots_0_valid),</a>
+<a name="3795"><span class="lineNum">    3795 </span>            :     .io_write_entry_tailSlot_offset   (u_s1_ftb_entry_tailSlot_offset),</a>
+<a name="3796"><span class="lineNum">    3796 </span>            :     .io_write_entry_tailSlot_lower    (u_s1_ftb_entry_tailSlot_lower),</a>
+<a name="3797"><span class="lineNum">    3797 </span>            :     .io_write_entry_tailSlot_tarStat  (u_s1_ftb_entry_tailSlot_tarStat),</a>
+<a name="3798"><span class="lineNum">    3798 </span>            :     .io_write_entry_tailSlot_sharing  (u_s1_ftb_entry_tailSlot_sharing),</a>
+<a name="3799"><span class="lineNum">    3799 </span>            :     .io_write_entry_tailSlot_valid    (u_s1_ftb_entry_tailSlot_valid),</a>
+<a name="3800"><span class="lineNum">    3800 </span>            :     .io_write_entry_pftAddr           (u_s1_ftb_entry_pftAddr),</a>
+<a name="3801"><span class="lineNum">    3801 </span>            :     .io_write_entry_carry             (u_s1_ftb_entry_carry),</a>
+<a name="3802"><span class="lineNum">    3802 </span>            :     .io_write_entry_always_taken_0    (u_s1_ftb_entry_always_taken_0),</a>
+<a name="3803"><span class="lineNum">    3803 </span>            :     .io_write_entry_always_taken_1    (u_s1_ftb_entry_always_taken_1),</a>
+<a name="3804"><span class="lineNum">    3804 </span>            :     .io_write_tag                     (u_s1_tag)</a>
+<a name="3805"><span class="lineNum">    3805 </span>            :   );</a>
+<a name="3806"><span class="lineNum">    3806 </span>            :   FauFTBWay ways_8 (</a>
+<a name="3807"><span class="lineNum">    3807 </span>            :     .clock                            (clock),</a>
+<a name="3808"><span class="lineNum">    3808 </span>            :     .reset                            (reset),</a>
+<a name="3809"><span class="lineNum">    3809 </span>            :     .io_req_tag                       (s1_pc_dup_0[16:1]),</a>
+<a name="3810"><span class="lineNum">    3810 </span>            :     .io_resp_brSlots_0_offset         (_ways_8_io_resp_brSlots_0_offset),</a>
+<a name="3811"><span class="lineNum">    3811 </span>            :     .io_resp_brSlots_0_lower          (_ways_8_io_resp_brSlots_0_lower),</a>
+<a name="3812"><span class="lineNum">    3812 </span>            :     .io_resp_brSlots_0_tarStat        (_ways_8_io_resp_brSlots_0_tarStat),</a>
+<a name="3813"><span class="lineNum">    3813 </span>            :     .io_resp_brSlots_0_valid          (_ways_8_io_resp_brSlots_0_valid),</a>
+<a name="3814"><span class="lineNum">    3814 </span>            :     .io_resp_tailSlot_offset          (_ways_8_io_resp_tailSlot_offset),</a>
+<a name="3815"><span class="lineNum">    3815 </span>            :     .io_resp_tailSlot_lower           (_ways_8_io_resp_tailSlot_lower),</a>
+<a name="3816"><span class="lineNum">    3816 </span>            :     .io_resp_tailSlot_tarStat         (_ways_8_io_resp_tailSlot_tarStat),</a>
+<a name="3817"><span class="lineNum">    3817 </span>            :     .io_resp_tailSlot_sharing         (_ways_8_io_resp_tailSlot_sharing),</a>
+<a name="3818"><span class="lineNum">    3818 </span>            :     .io_resp_tailSlot_valid           (_ways_8_io_resp_tailSlot_valid),</a>
+<a name="3819"><span class="lineNum">    3819 </span>            :     .io_resp_pftAddr                  (_ways_8_io_resp_pftAddr),</a>
+<a name="3820"><span class="lineNum">    3820 </span>            :     .io_resp_carry                    (_ways_8_io_resp_carry),</a>
+<a name="3821"><span class="lineNum">    3821 </span>            :     .io_resp_always_taken_0           (_ways_8_io_resp_always_taken_0),</a>
+<a name="3822"><span class="lineNum">    3822 </span>            :     .io_resp_always_taken_1           (_ways_8_io_resp_always_taken_1),</a>
+<a name="3823"><span class="lineNum">    3823 </span>            :     .io_resp_hit                      (_ways_8_io_resp_hit),</a>
+<a name="3824"><span class="lineNum">    3824 </span>            :     .io_update_req_tag                (io_update_bits_pc[16:1]),</a>
+<a name="3825"><span class="lineNum">    3825 </span>            :     .io_update_hit                    (_ways_8_io_update_hit),</a>
+<a name="3826"><span class="lineNum">    3826 </span>            :     .io_write_valid                   (u_s1_ways_write_valid_8),</a>
+<a name="3827"><span class="lineNum">    3827 </span>            :     .io_write_entry_brSlots_0_offset  (u_s1_ftb_entry_brSlots_0_offset),</a>
+<a name="3828"><span class="lineNum">    3828 </span>            :     .io_write_entry_brSlots_0_lower   (u_s1_ftb_entry_brSlots_0_lower),</a>
+<a name="3829"><span class="lineNum">    3829 </span>            :     .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat),</a>
+<a name="3830"><span class="lineNum">    3830 </span>            :     .io_write_entry_brSlots_0_valid   (u_s1_ftb_entry_brSlots_0_valid),</a>
+<a name="3831"><span class="lineNum">    3831 </span>            :     .io_write_entry_tailSlot_offset   (u_s1_ftb_entry_tailSlot_offset),</a>
+<a name="3832"><span class="lineNum">    3832 </span>            :     .io_write_entry_tailSlot_lower    (u_s1_ftb_entry_tailSlot_lower),</a>
+<a name="3833"><span class="lineNum">    3833 </span>            :     .io_write_entry_tailSlot_tarStat  (u_s1_ftb_entry_tailSlot_tarStat),</a>
+<a name="3834"><span class="lineNum">    3834 </span>            :     .io_write_entry_tailSlot_sharing  (u_s1_ftb_entry_tailSlot_sharing),</a>
+<a name="3835"><span class="lineNum">    3835 </span>            :     .io_write_entry_tailSlot_valid    (u_s1_ftb_entry_tailSlot_valid),</a>
+<a name="3836"><span class="lineNum">    3836 </span>            :     .io_write_entry_pftAddr           (u_s1_ftb_entry_pftAddr),</a>
+<a name="3837"><span class="lineNum">    3837 </span>            :     .io_write_entry_carry             (u_s1_ftb_entry_carry),</a>
+<a name="3838"><span class="lineNum">    3838 </span>            :     .io_write_entry_always_taken_0    (u_s1_ftb_entry_always_taken_0),</a>
+<a name="3839"><span class="lineNum">    3839 </span>            :     .io_write_entry_always_taken_1    (u_s1_ftb_entry_always_taken_1),</a>
+<a name="3840"><span class="lineNum">    3840 </span>            :     .io_write_tag                     (u_s1_tag)</a>
+<a name="3841"><span class="lineNum">    3841 </span>            :   );</a>
+<a name="3842"><span class="lineNum">    3842 </span>            :   FauFTBWay ways_9 (</a>
+<a name="3843"><span class="lineNum">    3843 </span>            :     .clock                            (clock),</a>
+<a name="3844"><span class="lineNum">    3844 </span>            :     .reset                            (reset),</a>
+<a name="3845"><span class="lineNum">    3845 </span>            :     .io_req_tag                       (s1_pc_dup_0[16:1]),</a>
+<a name="3846"><span class="lineNum">    3846 </span>            :     .io_resp_brSlots_0_offset         (_ways_9_io_resp_brSlots_0_offset),</a>
+<a name="3847"><span class="lineNum">    3847 </span>            :     .io_resp_brSlots_0_lower          (_ways_9_io_resp_brSlots_0_lower),</a>
+<a name="3848"><span class="lineNum">    3848 </span>            :     .io_resp_brSlots_0_tarStat        (_ways_9_io_resp_brSlots_0_tarStat),</a>
+<a name="3849"><span class="lineNum">    3849 </span>            :     .io_resp_brSlots_0_valid          (_ways_9_io_resp_brSlots_0_valid),</a>
+<a name="3850"><span class="lineNum">    3850 </span>            :     .io_resp_tailSlot_offset          (_ways_9_io_resp_tailSlot_offset),</a>
+<a name="3851"><span class="lineNum">    3851 </span>            :     .io_resp_tailSlot_lower           (_ways_9_io_resp_tailSlot_lower),</a>
+<a name="3852"><span class="lineNum">    3852 </span>            :     .io_resp_tailSlot_tarStat         (_ways_9_io_resp_tailSlot_tarStat),</a>
+<a name="3853"><span class="lineNum">    3853 </span>            :     .io_resp_tailSlot_sharing         (_ways_9_io_resp_tailSlot_sharing),</a>
+<a name="3854"><span class="lineNum">    3854 </span>            :     .io_resp_tailSlot_valid           (_ways_9_io_resp_tailSlot_valid),</a>
+<a name="3855"><span class="lineNum">    3855 </span>            :     .io_resp_pftAddr                  (_ways_9_io_resp_pftAddr),</a>
+<a name="3856"><span class="lineNum">    3856 </span>            :     .io_resp_carry                    (_ways_9_io_resp_carry),</a>
+<a name="3857"><span class="lineNum">    3857 </span>            :     .io_resp_always_taken_0           (_ways_9_io_resp_always_taken_0),</a>
+<a name="3858"><span class="lineNum">    3858 </span>            :     .io_resp_always_taken_1           (_ways_9_io_resp_always_taken_1),</a>
+<a name="3859"><span class="lineNum">    3859 </span>            :     .io_resp_hit                      (_ways_9_io_resp_hit),</a>
+<a name="3860"><span class="lineNum">    3860 </span>            :     .io_update_req_tag                (io_update_bits_pc[16:1]),</a>
+<a name="3861"><span class="lineNum">    3861 </span>            :     .io_update_hit                    (_ways_9_io_update_hit),</a>
+<a name="3862"><span class="lineNum">    3862 </span>            :     .io_write_valid                   (u_s1_ways_write_valid_9),</a>
+<a name="3863"><span class="lineNum">    3863 </span>            :     .io_write_entry_brSlots_0_offset  (u_s1_ftb_entry_brSlots_0_offset),</a>
+<a name="3864"><span class="lineNum">    3864 </span>            :     .io_write_entry_brSlots_0_lower   (u_s1_ftb_entry_brSlots_0_lower),</a>
+<a name="3865"><span class="lineNum">    3865 </span>            :     .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat),</a>
+<a name="3866"><span class="lineNum">    3866 </span>            :     .io_write_entry_brSlots_0_valid   (u_s1_ftb_entry_brSlots_0_valid),</a>
+<a name="3867"><span class="lineNum">    3867 </span>            :     .io_write_entry_tailSlot_offset   (u_s1_ftb_entry_tailSlot_offset),</a>
+<a name="3868"><span class="lineNum">    3868 </span>            :     .io_write_entry_tailSlot_lower    (u_s1_ftb_entry_tailSlot_lower),</a>
+<a name="3869"><span class="lineNum">    3869 </span>            :     .io_write_entry_tailSlot_tarStat  (u_s1_ftb_entry_tailSlot_tarStat),</a>
+<a name="3870"><span class="lineNum">    3870 </span>            :     .io_write_entry_tailSlot_sharing  (u_s1_ftb_entry_tailSlot_sharing),</a>
+<a name="3871"><span class="lineNum">    3871 </span>            :     .io_write_entry_tailSlot_valid    (u_s1_ftb_entry_tailSlot_valid),</a>
+<a name="3872"><span class="lineNum">    3872 </span>            :     .io_write_entry_pftAddr           (u_s1_ftb_entry_pftAddr),</a>
+<a name="3873"><span class="lineNum">    3873 </span>            :     .io_write_entry_carry             (u_s1_ftb_entry_carry),</a>
+<a name="3874"><span class="lineNum">    3874 </span>            :     .io_write_entry_always_taken_0    (u_s1_ftb_entry_always_taken_0),</a>
+<a name="3875"><span class="lineNum">    3875 </span>            :     .io_write_entry_always_taken_1    (u_s1_ftb_entry_always_taken_1),</a>
+<a name="3876"><span class="lineNum">    3876 </span>            :     .io_write_tag                     (u_s1_tag)</a>
+<a name="3877"><span class="lineNum">    3877 </span>            :   );</a>
+<a name="3878"><span class="lineNum">    3878 </span>            :   FauFTBWay ways_10 (</a>
+<a name="3879"><span class="lineNum">    3879 </span>            :     .clock                            (clock),</a>
+<a name="3880"><span class="lineNum">    3880 </span>            :     .reset                            (reset),</a>
+<a name="3881"><span class="lineNum">    3881 </span>            :     .io_req_tag                       (s1_pc_dup_0[16:1]),</a>
+<a name="3882"><span class="lineNum">    3882 </span>            :     .io_resp_brSlots_0_offset         (_ways_10_io_resp_brSlots_0_offset),</a>
+<a name="3883"><span class="lineNum">    3883 </span>            :     .io_resp_brSlots_0_lower          (_ways_10_io_resp_brSlots_0_lower),</a>
+<a name="3884"><span class="lineNum">    3884 </span>            :     .io_resp_brSlots_0_tarStat        (_ways_10_io_resp_brSlots_0_tarStat),</a>
+<a name="3885"><span class="lineNum">    3885 </span>            :     .io_resp_brSlots_0_valid          (_ways_10_io_resp_brSlots_0_valid),</a>
+<a name="3886"><span class="lineNum">    3886 </span>            :     .io_resp_tailSlot_offset          (_ways_10_io_resp_tailSlot_offset),</a>
+<a name="3887"><span class="lineNum">    3887 </span>            :     .io_resp_tailSlot_lower           (_ways_10_io_resp_tailSlot_lower),</a>
+<a name="3888"><span class="lineNum">    3888 </span>            :     .io_resp_tailSlot_tarStat         (_ways_10_io_resp_tailSlot_tarStat),</a>
+<a name="3889"><span class="lineNum">    3889 </span>            :     .io_resp_tailSlot_sharing         (_ways_10_io_resp_tailSlot_sharing),</a>
+<a name="3890"><span class="lineNum">    3890 </span>            :     .io_resp_tailSlot_valid           (_ways_10_io_resp_tailSlot_valid),</a>
+<a name="3891"><span class="lineNum">    3891 </span>            :     .io_resp_pftAddr                  (_ways_10_io_resp_pftAddr),</a>
+<a name="3892"><span class="lineNum">    3892 </span>            :     .io_resp_carry                    (_ways_10_io_resp_carry),</a>
+<a name="3893"><span class="lineNum">    3893 </span>            :     .io_resp_always_taken_0           (_ways_10_io_resp_always_taken_0),</a>
+<a name="3894"><span class="lineNum">    3894 </span>            :     .io_resp_always_taken_1           (_ways_10_io_resp_always_taken_1),</a>
+<a name="3895"><span class="lineNum">    3895 </span>            :     .io_resp_hit                      (_ways_10_io_resp_hit),</a>
+<a name="3896"><span class="lineNum">    3896 </span>            :     .io_update_req_tag                (io_update_bits_pc[16:1]),</a>
+<a name="3897"><span class="lineNum">    3897 </span>            :     .io_update_hit                    (_ways_10_io_update_hit),</a>
+<a name="3898"><span class="lineNum">    3898 </span>            :     .io_write_valid                   (u_s1_ways_write_valid_10),</a>
+<a name="3899"><span class="lineNum">    3899 </span>            :     .io_write_entry_brSlots_0_offset  (u_s1_ftb_entry_brSlots_0_offset),</a>
+<a name="3900"><span class="lineNum">    3900 </span>            :     .io_write_entry_brSlots_0_lower   (u_s1_ftb_entry_brSlots_0_lower),</a>
+<a name="3901"><span class="lineNum">    3901 </span>            :     .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat),</a>
+<a name="3902"><span class="lineNum">    3902 </span>            :     .io_write_entry_brSlots_0_valid   (u_s1_ftb_entry_brSlots_0_valid),</a>
+<a name="3903"><span class="lineNum">    3903 </span>            :     .io_write_entry_tailSlot_offset   (u_s1_ftb_entry_tailSlot_offset),</a>
+<a name="3904"><span class="lineNum">    3904 </span>            :     .io_write_entry_tailSlot_lower    (u_s1_ftb_entry_tailSlot_lower),</a>
+<a name="3905"><span class="lineNum">    3905 </span>            :     .io_write_entry_tailSlot_tarStat  (u_s1_ftb_entry_tailSlot_tarStat),</a>
+<a name="3906"><span class="lineNum">    3906 </span>            :     .io_write_entry_tailSlot_sharing  (u_s1_ftb_entry_tailSlot_sharing),</a>
+<a name="3907"><span class="lineNum">    3907 </span>            :     .io_write_entry_tailSlot_valid    (u_s1_ftb_entry_tailSlot_valid),</a>
+<a name="3908"><span class="lineNum">    3908 </span>            :     .io_write_entry_pftAddr           (u_s1_ftb_entry_pftAddr),</a>
+<a name="3909"><span class="lineNum">    3909 </span>            :     .io_write_entry_carry             (u_s1_ftb_entry_carry),</a>
+<a name="3910"><span class="lineNum">    3910 </span>            :     .io_write_entry_always_taken_0    (u_s1_ftb_entry_always_taken_0),</a>
+<a name="3911"><span class="lineNum">    3911 </span>            :     .io_write_entry_always_taken_1    (u_s1_ftb_entry_always_taken_1),</a>
+<a name="3912"><span class="lineNum">    3912 </span>            :     .io_write_tag                     (u_s1_tag)</a>
+<a name="3913"><span class="lineNum">    3913 </span>            :   );</a>
+<a name="3914"><span class="lineNum">    3914 </span>            :   FauFTBWay ways_11 (</a>
+<a name="3915"><span class="lineNum">    3915 </span>            :     .clock                            (clock),</a>
+<a name="3916"><span class="lineNum">    3916 </span>            :     .reset                            (reset),</a>
+<a name="3917"><span class="lineNum">    3917 </span>            :     .io_req_tag                       (s1_pc_dup_0[16:1]),</a>
+<a name="3918"><span class="lineNum">    3918 </span>            :     .io_resp_brSlots_0_offset         (_ways_11_io_resp_brSlots_0_offset),</a>
+<a name="3919"><span class="lineNum">    3919 </span>            :     .io_resp_brSlots_0_lower          (_ways_11_io_resp_brSlots_0_lower),</a>
+<a name="3920"><span class="lineNum">    3920 </span>            :     .io_resp_brSlots_0_tarStat        (_ways_11_io_resp_brSlots_0_tarStat),</a>
+<a name="3921"><span class="lineNum">    3921 </span>            :     .io_resp_brSlots_0_valid          (_ways_11_io_resp_brSlots_0_valid),</a>
+<a name="3922"><span class="lineNum">    3922 </span>            :     .io_resp_tailSlot_offset          (_ways_11_io_resp_tailSlot_offset),</a>
+<a name="3923"><span class="lineNum">    3923 </span>            :     .io_resp_tailSlot_lower           (_ways_11_io_resp_tailSlot_lower),</a>
+<a name="3924"><span class="lineNum">    3924 </span>            :     .io_resp_tailSlot_tarStat         (_ways_11_io_resp_tailSlot_tarStat),</a>
+<a name="3925"><span class="lineNum">    3925 </span>            :     .io_resp_tailSlot_sharing         (_ways_11_io_resp_tailSlot_sharing),</a>
+<a name="3926"><span class="lineNum">    3926 </span>            :     .io_resp_tailSlot_valid           (_ways_11_io_resp_tailSlot_valid),</a>
+<a name="3927"><span class="lineNum">    3927 </span>            :     .io_resp_pftAddr                  (_ways_11_io_resp_pftAddr),</a>
+<a name="3928"><span class="lineNum">    3928 </span>            :     .io_resp_carry                    (_ways_11_io_resp_carry),</a>
+<a name="3929"><span class="lineNum">    3929 </span>            :     .io_resp_always_taken_0           (_ways_11_io_resp_always_taken_0),</a>
+<a name="3930"><span class="lineNum">    3930 </span>            :     .io_resp_always_taken_1           (_ways_11_io_resp_always_taken_1),</a>
+<a name="3931"><span class="lineNum">    3931 </span>            :     .io_resp_hit                      (_ways_11_io_resp_hit),</a>
+<a name="3932"><span class="lineNum">    3932 </span>            :     .io_update_req_tag                (io_update_bits_pc[16:1]),</a>
+<a name="3933"><span class="lineNum">    3933 </span>            :     .io_update_hit                    (_ways_11_io_update_hit),</a>
+<a name="3934"><span class="lineNum">    3934 </span>            :     .io_write_valid                   (u_s1_ways_write_valid_11),</a>
+<a name="3935"><span class="lineNum">    3935 </span>            :     .io_write_entry_brSlots_0_offset  (u_s1_ftb_entry_brSlots_0_offset),</a>
+<a name="3936"><span class="lineNum">    3936 </span>            :     .io_write_entry_brSlots_0_lower   (u_s1_ftb_entry_brSlots_0_lower),</a>
+<a name="3937"><span class="lineNum">    3937 </span>            :     .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat),</a>
+<a name="3938"><span class="lineNum">    3938 </span>            :     .io_write_entry_brSlots_0_valid   (u_s1_ftb_entry_brSlots_0_valid),</a>
+<a name="3939"><span class="lineNum">    3939 </span>            :     .io_write_entry_tailSlot_offset   (u_s1_ftb_entry_tailSlot_offset),</a>
+<a name="3940"><span class="lineNum">    3940 </span>            :     .io_write_entry_tailSlot_lower    (u_s1_ftb_entry_tailSlot_lower),</a>
+<a name="3941"><span class="lineNum">    3941 </span>            :     .io_write_entry_tailSlot_tarStat  (u_s1_ftb_entry_tailSlot_tarStat),</a>
+<a name="3942"><span class="lineNum">    3942 </span>            :     .io_write_entry_tailSlot_sharing  (u_s1_ftb_entry_tailSlot_sharing),</a>
+<a name="3943"><span class="lineNum">    3943 </span>            :     .io_write_entry_tailSlot_valid    (u_s1_ftb_entry_tailSlot_valid),</a>
+<a name="3944"><span class="lineNum">    3944 </span>            :     .io_write_entry_pftAddr           (u_s1_ftb_entry_pftAddr),</a>
+<a name="3945"><span class="lineNum">    3945 </span>            :     .io_write_entry_carry             (u_s1_ftb_entry_carry),</a>
+<a name="3946"><span class="lineNum">    3946 </span>            :     .io_write_entry_always_taken_0    (u_s1_ftb_entry_always_taken_0),</a>
+<a name="3947"><span class="lineNum">    3947 </span>            :     .io_write_entry_always_taken_1    (u_s1_ftb_entry_always_taken_1),</a>
+<a name="3948"><span class="lineNum">    3948 </span>            :     .io_write_tag                     (u_s1_tag)</a>
+<a name="3949"><span class="lineNum">    3949 </span>            :   );</a>
+<a name="3950"><span class="lineNum">    3950 </span>            :   FauFTBWay ways_12 (</a>
+<a name="3951"><span class="lineNum">    3951 </span>            :     .clock                            (clock),</a>
+<a name="3952"><span class="lineNum">    3952 </span>            :     .reset                            (reset),</a>
+<a name="3953"><span class="lineNum">    3953 </span>            :     .io_req_tag                       (s1_pc_dup_0[16:1]),</a>
+<a name="3954"><span class="lineNum">    3954 </span>            :     .io_resp_brSlots_0_offset         (_ways_12_io_resp_brSlots_0_offset),</a>
+<a name="3955"><span class="lineNum">    3955 </span>            :     .io_resp_brSlots_0_lower          (_ways_12_io_resp_brSlots_0_lower),</a>
+<a name="3956"><span class="lineNum">    3956 </span>            :     .io_resp_brSlots_0_tarStat        (_ways_12_io_resp_brSlots_0_tarStat),</a>
+<a name="3957"><span class="lineNum">    3957 </span>            :     .io_resp_brSlots_0_valid          (_ways_12_io_resp_brSlots_0_valid),</a>
+<a name="3958"><span class="lineNum">    3958 </span>            :     .io_resp_tailSlot_offset          (_ways_12_io_resp_tailSlot_offset),</a>
+<a name="3959"><span class="lineNum">    3959 </span>            :     .io_resp_tailSlot_lower           (_ways_12_io_resp_tailSlot_lower),</a>
+<a name="3960"><span class="lineNum">    3960 </span>            :     .io_resp_tailSlot_tarStat         (_ways_12_io_resp_tailSlot_tarStat),</a>
+<a name="3961"><span class="lineNum">    3961 </span>            :     .io_resp_tailSlot_sharing         (_ways_12_io_resp_tailSlot_sharing),</a>
+<a name="3962"><span class="lineNum">    3962 </span>            :     .io_resp_tailSlot_valid           (_ways_12_io_resp_tailSlot_valid),</a>
+<a name="3963"><span class="lineNum">    3963 </span>            :     .io_resp_pftAddr                  (_ways_12_io_resp_pftAddr),</a>
+<a name="3964"><span class="lineNum">    3964 </span>            :     .io_resp_carry                    (_ways_12_io_resp_carry),</a>
+<a name="3965"><span class="lineNum">    3965 </span>            :     .io_resp_always_taken_0           (_ways_12_io_resp_always_taken_0),</a>
+<a name="3966"><span class="lineNum">    3966 </span>            :     .io_resp_always_taken_1           (_ways_12_io_resp_always_taken_1),</a>
+<a name="3967"><span class="lineNum">    3967 </span>            :     .io_resp_hit                      (_ways_12_io_resp_hit),</a>
+<a name="3968"><span class="lineNum">    3968 </span>            :     .io_update_req_tag                (io_update_bits_pc[16:1]),</a>
+<a name="3969"><span class="lineNum">    3969 </span>            :     .io_update_hit                    (_ways_12_io_update_hit),</a>
+<a name="3970"><span class="lineNum">    3970 </span>            :     .io_write_valid                   (u_s1_ways_write_valid_12),</a>
+<a name="3971"><span class="lineNum">    3971 </span>            :     .io_write_entry_brSlots_0_offset  (u_s1_ftb_entry_brSlots_0_offset),</a>
+<a name="3972"><span class="lineNum">    3972 </span>            :     .io_write_entry_brSlots_0_lower   (u_s1_ftb_entry_brSlots_0_lower),</a>
+<a name="3973"><span class="lineNum">    3973 </span>            :     .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat),</a>
+<a name="3974"><span class="lineNum">    3974 </span>            :     .io_write_entry_brSlots_0_valid   (u_s1_ftb_entry_brSlots_0_valid),</a>
+<a name="3975"><span class="lineNum">    3975 </span>            :     .io_write_entry_tailSlot_offset   (u_s1_ftb_entry_tailSlot_offset),</a>
+<a name="3976"><span class="lineNum">    3976 </span>            :     .io_write_entry_tailSlot_lower    (u_s1_ftb_entry_tailSlot_lower),</a>
+<a name="3977"><span class="lineNum">    3977 </span>            :     .io_write_entry_tailSlot_tarStat  (u_s1_ftb_entry_tailSlot_tarStat),</a>
+<a name="3978"><span class="lineNum">    3978 </span>            :     .io_write_entry_tailSlot_sharing  (u_s1_ftb_entry_tailSlot_sharing),</a>
+<a name="3979"><span class="lineNum">    3979 </span>            :     .io_write_entry_tailSlot_valid    (u_s1_ftb_entry_tailSlot_valid),</a>
+<a name="3980"><span class="lineNum">    3980 </span>            :     .io_write_entry_pftAddr           (u_s1_ftb_entry_pftAddr),</a>
+<a name="3981"><span class="lineNum">    3981 </span>            :     .io_write_entry_carry             (u_s1_ftb_entry_carry),</a>
+<a name="3982"><span class="lineNum">    3982 </span>            :     .io_write_entry_always_taken_0    (u_s1_ftb_entry_always_taken_0),</a>
+<a name="3983"><span class="lineNum">    3983 </span>            :     .io_write_entry_always_taken_1    (u_s1_ftb_entry_always_taken_1),</a>
+<a name="3984"><span class="lineNum">    3984 </span>            :     .io_write_tag                     (u_s1_tag)</a>
+<a name="3985"><span class="lineNum">    3985 </span>            :   );</a>
+<a name="3986"><span class="lineNum">    3986 </span>            :   FauFTBWay ways_13 (</a>
+<a name="3987"><span class="lineNum">    3987 </span>            :     .clock                            (clock),</a>
+<a name="3988"><span class="lineNum">    3988 </span>            :     .reset                            (reset),</a>
+<a name="3989"><span class="lineNum">    3989 </span>            :     .io_req_tag                       (s1_pc_dup_0[16:1]),</a>
+<a name="3990"><span class="lineNum">    3990 </span>            :     .io_resp_brSlots_0_offset         (_ways_13_io_resp_brSlots_0_offset),</a>
+<a name="3991"><span class="lineNum">    3991 </span>            :     .io_resp_brSlots_0_lower          (_ways_13_io_resp_brSlots_0_lower),</a>
+<a name="3992"><span class="lineNum">    3992 </span>            :     .io_resp_brSlots_0_tarStat        (_ways_13_io_resp_brSlots_0_tarStat),</a>
+<a name="3993"><span class="lineNum">    3993 </span>            :     .io_resp_brSlots_0_valid          (_ways_13_io_resp_brSlots_0_valid),</a>
+<a name="3994"><span class="lineNum">    3994 </span>            :     .io_resp_tailSlot_offset          (_ways_13_io_resp_tailSlot_offset),</a>
+<a name="3995"><span class="lineNum">    3995 </span>            :     .io_resp_tailSlot_lower           (_ways_13_io_resp_tailSlot_lower),</a>
+<a name="3996"><span class="lineNum">    3996 </span>            :     .io_resp_tailSlot_tarStat         (_ways_13_io_resp_tailSlot_tarStat),</a>
+<a name="3997"><span class="lineNum">    3997 </span>            :     .io_resp_tailSlot_sharing         (_ways_13_io_resp_tailSlot_sharing),</a>
+<a name="3998"><span class="lineNum">    3998 </span>            :     .io_resp_tailSlot_valid           (_ways_13_io_resp_tailSlot_valid),</a>
+<a name="3999"><span class="lineNum">    3999 </span>            :     .io_resp_pftAddr                  (_ways_13_io_resp_pftAddr),</a>
+<a name="4000"><span class="lineNum">    4000 </span>            :     .io_resp_carry                    (_ways_13_io_resp_carry),</a>
+<a name="4001"><span class="lineNum">    4001 </span>            :     .io_resp_always_taken_0           (_ways_13_io_resp_always_taken_0),</a>
+<a name="4002"><span class="lineNum">    4002 </span>            :     .io_resp_always_taken_1           (_ways_13_io_resp_always_taken_1),</a>
+<a name="4003"><span class="lineNum">    4003 </span>            :     .io_resp_hit                      (_ways_13_io_resp_hit),</a>
+<a name="4004"><span class="lineNum">    4004 </span>            :     .io_update_req_tag                (io_update_bits_pc[16:1]),</a>
+<a name="4005"><span class="lineNum">    4005 </span>            :     .io_update_hit                    (_ways_13_io_update_hit),</a>
+<a name="4006"><span class="lineNum">    4006 </span>            :     .io_write_valid                   (u_s1_ways_write_valid_13),</a>
+<a name="4007"><span class="lineNum">    4007 </span>            :     .io_write_entry_brSlots_0_offset  (u_s1_ftb_entry_brSlots_0_offset),</a>
+<a name="4008"><span class="lineNum">    4008 </span>            :     .io_write_entry_brSlots_0_lower   (u_s1_ftb_entry_brSlots_0_lower),</a>
+<a name="4009"><span class="lineNum">    4009 </span>            :     .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat),</a>
+<a name="4010"><span class="lineNum">    4010 </span>            :     .io_write_entry_brSlots_0_valid   (u_s1_ftb_entry_brSlots_0_valid),</a>
+<a name="4011"><span class="lineNum">    4011 </span>            :     .io_write_entry_tailSlot_offset   (u_s1_ftb_entry_tailSlot_offset),</a>
+<a name="4012"><span class="lineNum">    4012 </span>            :     .io_write_entry_tailSlot_lower    (u_s1_ftb_entry_tailSlot_lower),</a>
+<a name="4013"><span class="lineNum">    4013 </span>            :     .io_write_entry_tailSlot_tarStat  (u_s1_ftb_entry_tailSlot_tarStat),</a>
+<a name="4014"><span class="lineNum">    4014 </span>            :     .io_write_entry_tailSlot_sharing  (u_s1_ftb_entry_tailSlot_sharing),</a>
+<a name="4015"><span class="lineNum">    4015 </span>            :     .io_write_entry_tailSlot_valid    (u_s1_ftb_entry_tailSlot_valid),</a>
+<a name="4016"><span class="lineNum">    4016 </span>            :     .io_write_entry_pftAddr           (u_s1_ftb_entry_pftAddr),</a>
+<a name="4017"><span class="lineNum">    4017 </span>            :     .io_write_entry_carry             (u_s1_ftb_entry_carry),</a>
+<a name="4018"><span class="lineNum">    4018 </span>            :     .io_write_entry_always_taken_0    (u_s1_ftb_entry_always_taken_0),</a>
+<a name="4019"><span class="lineNum">    4019 </span>            :     .io_write_entry_always_taken_1    (u_s1_ftb_entry_always_taken_1),</a>
+<a name="4020"><span class="lineNum">    4020 </span>            :     .io_write_tag                     (u_s1_tag)</a>
+<a name="4021"><span class="lineNum">    4021 </span>            :   );</a>
+<a name="4022"><span class="lineNum">    4022 </span>            :   FauFTBWay ways_14 (</a>
+<a name="4023"><span class="lineNum">    4023 </span>            :     .clock                            (clock),</a>
+<a name="4024"><span class="lineNum">    4024 </span>            :     .reset                            (reset),</a>
+<a name="4025"><span class="lineNum">    4025 </span>            :     .io_req_tag                       (s1_pc_dup_0[16:1]),</a>
+<a name="4026"><span class="lineNum">    4026 </span>            :     .io_resp_brSlots_0_offset         (_ways_14_io_resp_brSlots_0_offset),</a>
+<a name="4027"><span class="lineNum">    4027 </span>            :     .io_resp_brSlots_0_lower          (_ways_14_io_resp_brSlots_0_lower),</a>
+<a name="4028"><span class="lineNum">    4028 </span>            :     .io_resp_brSlots_0_tarStat        (_ways_14_io_resp_brSlots_0_tarStat),</a>
+<a name="4029"><span class="lineNum">    4029 </span>            :     .io_resp_brSlots_0_valid          (_ways_14_io_resp_brSlots_0_valid),</a>
+<a name="4030"><span class="lineNum">    4030 </span>            :     .io_resp_tailSlot_offset          (_ways_14_io_resp_tailSlot_offset),</a>
+<a name="4031"><span class="lineNum">    4031 </span>            :     .io_resp_tailSlot_lower           (_ways_14_io_resp_tailSlot_lower),</a>
+<a name="4032"><span class="lineNum">    4032 </span>            :     .io_resp_tailSlot_tarStat         (_ways_14_io_resp_tailSlot_tarStat),</a>
+<a name="4033"><span class="lineNum">    4033 </span>            :     .io_resp_tailSlot_sharing         (_ways_14_io_resp_tailSlot_sharing),</a>
+<a name="4034"><span class="lineNum">    4034 </span>            :     .io_resp_tailSlot_valid           (_ways_14_io_resp_tailSlot_valid),</a>
+<a name="4035"><span class="lineNum">    4035 </span>            :     .io_resp_pftAddr                  (_ways_14_io_resp_pftAddr),</a>
+<a name="4036"><span class="lineNum">    4036 </span>            :     .io_resp_carry                    (_ways_14_io_resp_carry),</a>
+<a name="4037"><span class="lineNum">    4037 </span>            :     .io_resp_always_taken_0           (_ways_14_io_resp_always_taken_0),</a>
+<a name="4038"><span class="lineNum">    4038 </span>            :     .io_resp_always_taken_1           (_ways_14_io_resp_always_taken_1),</a>
+<a name="4039"><span class="lineNum">    4039 </span>            :     .io_resp_hit                      (_ways_14_io_resp_hit),</a>
+<a name="4040"><span class="lineNum">    4040 </span>            :     .io_update_req_tag                (io_update_bits_pc[16:1]),</a>
+<a name="4041"><span class="lineNum">    4041 </span>            :     .io_update_hit                    (_ways_14_io_update_hit),</a>
+<a name="4042"><span class="lineNum">    4042 </span>            :     .io_write_valid                   (u_s1_ways_write_valid_14),</a>
+<a name="4043"><span class="lineNum">    4043 </span>            :     .io_write_entry_brSlots_0_offset  (u_s1_ftb_entry_brSlots_0_offset),</a>
+<a name="4044"><span class="lineNum">    4044 </span>            :     .io_write_entry_brSlots_0_lower   (u_s1_ftb_entry_brSlots_0_lower),</a>
+<a name="4045"><span class="lineNum">    4045 </span>            :     .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat),</a>
+<a name="4046"><span class="lineNum">    4046 </span>            :     .io_write_entry_brSlots_0_valid   (u_s1_ftb_entry_brSlots_0_valid),</a>
+<a name="4047"><span class="lineNum">    4047 </span>            :     .io_write_entry_tailSlot_offset   (u_s1_ftb_entry_tailSlot_offset),</a>
+<a name="4048"><span class="lineNum">    4048 </span>            :     .io_write_entry_tailSlot_lower    (u_s1_ftb_entry_tailSlot_lower),</a>
+<a name="4049"><span class="lineNum">    4049 </span>            :     .io_write_entry_tailSlot_tarStat  (u_s1_ftb_entry_tailSlot_tarStat),</a>
+<a name="4050"><span class="lineNum">    4050 </span>            :     .io_write_entry_tailSlot_sharing  (u_s1_ftb_entry_tailSlot_sharing),</a>
+<a name="4051"><span class="lineNum">    4051 </span>            :     .io_write_entry_tailSlot_valid    (u_s1_ftb_entry_tailSlot_valid),</a>
+<a name="4052"><span class="lineNum">    4052 </span>            :     .io_write_entry_pftAddr           (u_s1_ftb_entry_pftAddr),</a>
+<a name="4053"><span class="lineNum">    4053 </span>            :     .io_write_entry_carry             (u_s1_ftb_entry_carry),</a>
+<a name="4054"><span class="lineNum">    4054 </span>            :     .io_write_entry_always_taken_0    (u_s1_ftb_entry_always_taken_0),</a>
+<a name="4055"><span class="lineNum">    4055 </span>            :     .io_write_entry_always_taken_1    (u_s1_ftb_entry_always_taken_1),</a>
+<a name="4056"><span class="lineNum">    4056 </span>            :     .io_write_tag                     (u_s1_tag)</a>
+<a name="4057"><span class="lineNum">    4057 </span>            :   );</a>
+<a name="4058"><span class="lineNum">    4058 </span>            :   FauFTBWay ways_15 (</a>
+<a name="4059"><span class="lineNum">    4059 </span>            :     .clock                            (clock),</a>
+<a name="4060"><span class="lineNum">    4060 </span>            :     .reset                            (reset),</a>
+<a name="4061"><span class="lineNum">    4061 </span>            :     .io_req_tag                       (s1_pc_dup_0[16:1]),</a>
+<a name="4062"><span class="lineNum">    4062 </span>            :     .io_resp_brSlots_0_offset         (_ways_15_io_resp_brSlots_0_offset),</a>
+<a name="4063"><span class="lineNum">    4063 </span>            :     .io_resp_brSlots_0_lower          (_ways_15_io_resp_brSlots_0_lower),</a>
+<a name="4064"><span class="lineNum">    4064 </span>            :     .io_resp_brSlots_0_tarStat        (_ways_15_io_resp_brSlots_0_tarStat),</a>
+<a name="4065"><span class="lineNum">    4065 </span>            :     .io_resp_brSlots_0_valid          (_ways_15_io_resp_brSlots_0_valid),</a>
+<a name="4066"><span class="lineNum">    4066 </span>            :     .io_resp_tailSlot_offset          (_ways_15_io_resp_tailSlot_offset),</a>
+<a name="4067"><span class="lineNum">    4067 </span>            :     .io_resp_tailSlot_lower           (_ways_15_io_resp_tailSlot_lower),</a>
+<a name="4068"><span class="lineNum">    4068 </span>            :     .io_resp_tailSlot_tarStat         (_ways_15_io_resp_tailSlot_tarStat),</a>
+<a name="4069"><span class="lineNum">    4069 </span>            :     .io_resp_tailSlot_sharing         (_ways_15_io_resp_tailSlot_sharing),</a>
+<a name="4070"><span class="lineNum">    4070 </span>            :     .io_resp_tailSlot_valid           (_ways_15_io_resp_tailSlot_valid),</a>
+<a name="4071"><span class="lineNum">    4071 </span>            :     .io_resp_pftAddr                  (_ways_15_io_resp_pftAddr),</a>
+<a name="4072"><span class="lineNum">    4072 </span>            :     .io_resp_carry                    (_ways_15_io_resp_carry),</a>
+<a name="4073"><span class="lineNum">    4073 </span>            :     .io_resp_always_taken_0           (_ways_15_io_resp_always_taken_0),</a>
+<a name="4074"><span class="lineNum">    4074 </span>            :     .io_resp_always_taken_1           (_ways_15_io_resp_always_taken_1),</a>
+<a name="4075"><span class="lineNum">    4075 </span>            :     .io_resp_hit                      (_ways_15_io_resp_hit),</a>
+<a name="4076"><span class="lineNum">    4076 </span>            :     .io_update_req_tag                (io_update_bits_pc[16:1]),</a>
+<a name="4077"><span class="lineNum">    4077 </span>            :     .io_update_hit                    (_ways_15_io_update_hit),</a>
+<a name="4078"><span class="lineNum">    4078 </span>            :     .io_write_valid                   (u_s1_ways_write_valid_15),</a>
+<a name="4079"><span class="lineNum">    4079 </span>            :     .io_write_entry_brSlots_0_offset  (u_s1_ftb_entry_brSlots_0_offset),</a>
+<a name="4080"><span class="lineNum">    4080 </span>            :     .io_write_entry_brSlots_0_lower   (u_s1_ftb_entry_brSlots_0_lower),</a>
+<a name="4081"><span class="lineNum">    4081 </span>            :     .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat),</a>
+<a name="4082"><span class="lineNum">    4082 </span>            :     .io_write_entry_brSlots_0_valid   (u_s1_ftb_entry_brSlots_0_valid),</a>
+<a name="4083"><span class="lineNum">    4083 </span>            :     .io_write_entry_tailSlot_offset   (u_s1_ftb_entry_tailSlot_offset),</a>
+<a name="4084"><span class="lineNum">    4084 </span>            :     .io_write_entry_tailSlot_lower    (u_s1_ftb_entry_tailSlot_lower),</a>
+<a name="4085"><span class="lineNum">    4085 </span>            :     .io_write_entry_tailSlot_tarStat  (u_s1_ftb_entry_tailSlot_tarStat),</a>
+<a name="4086"><span class="lineNum">    4086 </span>            :     .io_write_entry_tailSlot_sharing  (u_s1_ftb_entry_tailSlot_sharing),</a>
+<a name="4087"><span class="lineNum">    4087 </span>            :     .io_write_entry_tailSlot_valid    (u_s1_ftb_entry_tailSlot_valid),</a>
+<a name="4088"><span class="lineNum">    4088 </span>            :     .io_write_entry_pftAddr           (u_s1_ftb_entry_pftAddr),</a>
+<a name="4089"><span class="lineNum">    4089 </span>            :     .io_write_entry_carry             (u_s1_ftb_entry_carry),</a>
+<a name="4090"><span class="lineNum">    4090 </span>            :     .io_write_entry_always_taken_0    (u_s1_ftb_entry_always_taken_0),</a>
+<a name="4091"><span class="lineNum">    4091 </span>            :     .io_write_entry_always_taken_1    (u_s1_ftb_entry_always_taken_1),</a>
+<a name="4092"><span class="lineNum">    4092 </span>            :     .io_write_tag                     (u_s1_tag)</a>
+<a name="4093"><span class="lineNum">    4093 </span>            :   );</a>
+<a name="4094"><span class="lineNum">    4094 </span>            :   FauFTBWay ways_16 (</a>
+<a name="4095"><span class="lineNum">    4095 </span>            :     .clock                            (clock),</a>
+<a name="4096"><span class="lineNum">    4096 </span>            :     .reset                            (reset),</a>
+<a name="4097"><span class="lineNum">    4097 </span>            :     .io_req_tag                       (s1_pc_dup_0[16:1]),</a>
+<a name="4098"><span class="lineNum">    4098 </span>            :     .io_resp_brSlots_0_offset         (_ways_16_io_resp_brSlots_0_offset),</a>
+<a name="4099"><span class="lineNum">    4099 </span>            :     .io_resp_brSlots_0_lower          (_ways_16_io_resp_brSlots_0_lower),</a>
+<a name="4100"><span class="lineNum">    4100 </span>            :     .io_resp_brSlots_0_tarStat        (_ways_16_io_resp_brSlots_0_tarStat),</a>
+<a name="4101"><span class="lineNum">    4101 </span>            :     .io_resp_brSlots_0_valid          (_ways_16_io_resp_brSlots_0_valid),</a>
+<a name="4102"><span class="lineNum">    4102 </span>            :     .io_resp_tailSlot_offset          (_ways_16_io_resp_tailSlot_offset),</a>
+<a name="4103"><span class="lineNum">    4103 </span>            :     .io_resp_tailSlot_lower           (_ways_16_io_resp_tailSlot_lower),</a>
+<a name="4104"><span class="lineNum">    4104 </span>            :     .io_resp_tailSlot_tarStat         (_ways_16_io_resp_tailSlot_tarStat),</a>
+<a name="4105"><span class="lineNum">    4105 </span>            :     .io_resp_tailSlot_sharing         (_ways_16_io_resp_tailSlot_sharing),</a>
+<a name="4106"><span class="lineNum">    4106 </span>            :     .io_resp_tailSlot_valid           (_ways_16_io_resp_tailSlot_valid),</a>
+<a name="4107"><span class="lineNum">    4107 </span>            :     .io_resp_pftAddr                  (_ways_16_io_resp_pftAddr),</a>
+<a name="4108"><span class="lineNum">    4108 </span>            :     .io_resp_carry                    (_ways_16_io_resp_carry),</a>
+<a name="4109"><span class="lineNum">    4109 </span>            :     .io_resp_always_taken_0           (_ways_16_io_resp_always_taken_0),</a>
+<a name="4110"><span class="lineNum">    4110 </span>            :     .io_resp_always_taken_1           (_ways_16_io_resp_always_taken_1),</a>
+<a name="4111"><span class="lineNum">    4111 </span>            :     .io_resp_hit                      (_ways_16_io_resp_hit),</a>
+<a name="4112"><span class="lineNum">    4112 </span>            :     .io_update_req_tag                (io_update_bits_pc[16:1]),</a>
+<a name="4113"><span class="lineNum">    4113 </span>            :     .io_update_hit                    (_ways_16_io_update_hit),</a>
+<a name="4114"><span class="lineNum">    4114 </span>            :     .io_write_valid                   (u_s1_ways_write_valid_16),</a>
+<a name="4115"><span class="lineNum">    4115 </span>            :     .io_write_entry_brSlots_0_offset  (u_s1_ftb_entry_brSlots_0_offset),</a>
+<a name="4116"><span class="lineNum">    4116 </span>            :     .io_write_entry_brSlots_0_lower   (u_s1_ftb_entry_brSlots_0_lower),</a>
+<a name="4117"><span class="lineNum">    4117 </span>            :     .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat),</a>
+<a name="4118"><span class="lineNum">    4118 </span>            :     .io_write_entry_brSlots_0_valid   (u_s1_ftb_entry_brSlots_0_valid),</a>
+<a name="4119"><span class="lineNum">    4119 </span>            :     .io_write_entry_tailSlot_offset   (u_s1_ftb_entry_tailSlot_offset),</a>
+<a name="4120"><span class="lineNum">    4120 </span>            :     .io_write_entry_tailSlot_lower    (u_s1_ftb_entry_tailSlot_lower),</a>
+<a name="4121"><span class="lineNum">    4121 </span>            :     .io_write_entry_tailSlot_tarStat  (u_s1_ftb_entry_tailSlot_tarStat),</a>
+<a name="4122"><span class="lineNum">    4122 </span>            :     .io_write_entry_tailSlot_sharing  (u_s1_ftb_entry_tailSlot_sharing),</a>
+<a name="4123"><span class="lineNum">    4123 </span>            :     .io_write_entry_tailSlot_valid    (u_s1_ftb_entry_tailSlot_valid),</a>
+<a name="4124"><span class="lineNum">    4124 </span>            :     .io_write_entry_pftAddr           (u_s1_ftb_entry_pftAddr),</a>
+<a name="4125"><span class="lineNum">    4125 </span>            :     .io_write_entry_carry             (u_s1_ftb_entry_carry),</a>
+<a name="4126"><span class="lineNum">    4126 </span>            :     .io_write_entry_always_taken_0    (u_s1_ftb_entry_always_taken_0),</a>
+<a name="4127"><span class="lineNum">    4127 </span>            :     .io_write_entry_always_taken_1    (u_s1_ftb_entry_always_taken_1),</a>
+<a name="4128"><span class="lineNum">    4128 </span>            :     .io_write_tag                     (u_s1_tag)</a>
+<a name="4129"><span class="lineNum">    4129 </span>            :   );</a>
+<a name="4130"><span class="lineNum">    4130 </span>            :   FauFTBWay ways_17 (</a>
+<a name="4131"><span class="lineNum">    4131 </span>            :     .clock                            (clock),</a>
+<a name="4132"><span class="lineNum">    4132 </span>            :     .reset                            (reset),</a>
+<a name="4133"><span class="lineNum">    4133 </span>            :     .io_req_tag                       (s1_pc_dup_0[16:1]),</a>
+<a name="4134"><span class="lineNum">    4134 </span>            :     .io_resp_brSlots_0_offset         (_ways_17_io_resp_brSlots_0_offset),</a>
+<a name="4135"><span class="lineNum">    4135 </span>            :     .io_resp_brSlots_0_lower          (_ways_17_io_resp_brSlots_0_lower),</a>
+<a name="4136"><span class="lineNum">    4136 </span>            :     .io_resp_brSlots_0_tarStat        (_ways_17_io_resp_brSlots_0_tarStat),</a>
+<a name="4137"><span class="lineNum">    4137 </span>            :     .io_resp_brSlots_0_valid          (_ways_17_io_resp_brSlots_0_valid),</a>
+<a name="4138"><span class="lineNum">    4138 </span>            :     .io_resp_tailSlot_offset          (_ways_17_io_resp_tailSlot_offset),</a>
+<a name="4139"><span class="lineNum">    4139 </span>            :     .io_resp_tailSlot_lower           (_ways_17_io_resp_tailSlot_lower),</a>
+<a name="4140"><span class="lineNum">    4140 </span>            :     .io_resp_tailSlot_tarStat         (_ways_17_io_resp_tailSlot_tarStat),</a>
+<a name="4141"><span class="lineNum">    4141 </span>            :     .io_resp_tailSlot_sharing         (_ways_17_io_resp_tailSlot_sharing),</a>
+<a name="4142"><span class="lineNum">    4142 </span>            :     .io_resp_tailSlot_valid           (_ways_17_io_resp_tailSlot_valid),</a>
+<a name="4143"><span class="lineNum">    4143 </span>            :     .io_resp_pftAddr                  (_ways_17_io_resp_pftAddr),</a>
+<a name="4144"><span class="lineNum">    4144 </span>            :     .io_resp_carry                    (_ways_17_io_resp_carry),</a>
+<a name="4145"><span class="lineNum">    4145 </span>            :     .io_resp_always_taken_0           (_ways_17_io_resp_always_taken_0),</a>
+<a name="4146"><span class="lineNum">    4146 </span>            :     .io_resp_always_taken_1           (_ways_17_io_resp_always_taken_1),</a>
+<a name="4147"><span class="lineNum">    4147 </span>            :     .io_resp_hit                      (_ways_17_io_resp_hit),</a>
+<a name="4148"><span class="lineNum">    4148 </span>            :     .io_update_req_tag                (io_update_bits_pc[16:1]),</a>
+<a name="4149"><span class="lineNum">    4149 </span>            :     .io_update_hit                    (_ways_17_io_update_hit),</a>
+<a name="4150"><span class="lineNum">    4150 </span>            :     .io_write_valid                   (u_s1_ways_write_valid_17),</a>
+<a name="4151"><span class="lineNum">    4151 </span>            :     .io_write_entry_brSlots_0_offset  (u_s1_ftb_entry_brSlots_0_offset),</a>
+<a name="4152"><span class="lineNum">    4152 </span>            :     .io_write_entry_brSlots_0_lower   (u_s1_ftb_entry_brSlots_0_lower),</a>
+<a name="4153"><span class="lineNum">    4153 </span>            :     .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat),</a>
+<a name="4154"><span class="lineNum">    4154 </span>            :     .io_write_entry_brSlots_0_valid   (u_s1_ftb_entry_brSlots_0_valid),</a>
+<a name="4155"><span class="lineNum">    4155 </span>            :     .io_write_entry_tailSlot_offset   (u_s1_ftb_entry_tailSlot_offset),</a>
+<a name="4156"><span class="lineNum">    4156 </span>            :     .io_write_entry_tailSlot_lower    (u_s1_ftb_entry_tailSlot_lower),</a>
+<a name="4157"><span class="lineNum">    4157 </span>            :     .io_write_entry_tailSlot_tarStat  (u_s1_ftb_entry_tailSlot_tarStat),</a>
+<a name="4158"><span class="lineNum">    4158 </span>            :     .io_write_entry_tailSlot_sharing  (u_s1_ftb_entry_tailSlot_sharing),</a>
+<a name="4159"><span class="lineNum">    4159 </span>            :     .io_write_entry_tailSlot_valid    (u_s1_ftb_entry_tailSlot_valid),</a>
+<a name="4160"><span class="lineNum">    4160 </span>            :     .io_write_entry_pftAddr           (u_s1_ftb_entry_pftAddr),</a>
+<a name="4161"><span class="lineNum">    4161 </span>            :     .io_write_entry_carry             (u_s1_ftb_entry_carry),</a>
+<a name="4162"><span class="lineNum">    4162 </span>            :     .io_write_entry_always_taken_0    (u_s1_ftb_entry_always_taken_0),</a>
+<a name="4163"><span class="lineNum">    4163 </span>            :     .io_write_entry_always_taken_1    (u_s1_ftb_entry_always_taken_1),</a>
+<a name="4164"><span class="lineNum">    4164 </span>            :     .io_write_tag                     (u_s1_tag)</a>
+<a name="4165"><span class="lineNum">    4165 </span>            :   );</a>
+<a name="4166"><span class="lineNum">    4166 </span>            :   FauFTBWay ways_18 (</a>
+<a name="4167"><span class="lineNum">    4167 </span>            :     .clock                            (clock),</a>
+<a name="4168"><span class="lineNum">    4168 </span>            :     .reset                            (reset),</a>
+<a name="4169"><span class="lineNum">    4169 </span>            :     .io_req_tag                       (s1_pc_dup_0[16:1]),</a>
+<a name="4170"><span class="lineNum">    4170 </span>            :     .io_resp_brSlots_0_offset         (_ways_18_io_resp_brSlots_0_offset),</a>
+<a name="4171"><span class="lineNum">    4171 </span>            :     .io_resp_brSlots_0_lower          (_ways_18_io_resp_brSlots_0_lower),</a>
+<a name="4172"><span class="lineNum">    4172 </span>            :     .io_resp_brSlots_0_tarStat        (_ways_18_io_resp_brSlots_0_tarStat),</a>
+<a name="4173"><span class="lineNum">    4173 </span>            :     .io_resp_brSlots_0_valid          (_ways_18_io_resp_brSlots_0_valid),</a>
+<a name="4174"><span class="lineNum">    4174 </span>            :     .io_resp_tailSlot_offset          (_ways_18_io_resp_tailSlot_offset),</a>
+<a name="4175"><span class="lineNum">    4175 </span>            :     .io_resp_tailSlot_lower           (_ways_18_io_resp_tailSlot_lower),</a>
+<a name="4176"><span class="lineNum">    4176 </span>            :     .io_resp_tailSlot_tarStat         (_ways_18_io_resp_tailSlot_tarStat),</a>
+<a name="4177"><span class="lineNum">    4177 </span>            :     .io_resp_tailSlot_sharing         (_ways_18_io_resp_tailSlot_sharing),</a>
+<a name="4178"><span class="lineNum">    4178 </span>            :     .io_resp_tailSlot_valid           (_ways_18_io_resp_tailSlot_valid),</a>
+<a name="4179"><span class="lineNum">    4179 </span>            :     .io_resp_pftAddr                  (_ways_18_io_resp_pftAddr),</a>
+<a name="4180"><span class="lineNum">    4180 </span>            :     .io_resp_carry                    (_ways_18_io_resp_carry),</a>
+<a name="4181"><span class="lineNum">    4181 </span>            :     .io_resp_always_taken_0           (_ways_18_io_resp_always_taken_0),</a>
+<a name="4182"><span class="lineNum">    4182 </span>            :     .io_resp_always_taken_1           (_ways_18_io_resp_always_taken_1),</a>
+<a name="4183"><span class="lineNum">    4183 </span>            :     .io_resp_hit                      (_ways_18_io_resp_hit),</a>
+<a name="4184"><span class="lineNum">    4184 </span>            :     .io_update_req_tag                (io_update_bits_pc[16:1]),</a>
+<a name="4185"><span class="lineNum">    4185 </span>            :     .io_update_hit                    (_ways_18_io_update_hit),</a>
+<a name="4186"><span class="lineNum">    4186 </span>            :     .io_write_valid                   (u_s1_ways_write_valid_18),</a>
+<a name="4187"><span class="lineNum">    4187 </span>            :     .io_write_entry_brSlots_0_offset  (u_s1_ftb_entry_brSlots_0_offset),</a>
+<a name="4188"><span class="lineNum">    4188 </span>            :     .io_write_entry_brSlots_0_lower   (u_s1_ftb_entry_brSlots_0_lower),</a>
+<a name="4189"><span class="lineNum">    4189 </span>            :     .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat),</a>
+<a name="4190"><span class="lineNum">    4190 </span>            :     .io_write_entry_brSlots_0_valid   (u_s1_ftb_entry_brSlots_0_valid),</a>
+<a name="4191"><span class="lineNum">    4191 </span>            :     .io_write_entry_tailSlot_offset   (u_s1_ftb_entry_tailSlot_offset),</a>
+<a name="4192"><span class="lineNum">    4192 </span>            :     .io_write_entry_tailSlot_lower    (u_s1_ftb_entry_tailSlot_lower),</a>
+<a name="4193"><span class="lineNum">    4193 </span>            :     .io_write_entry_tailSlot_tarStat  (u_s1_ftb_entry_tailSlot_tarStat),</a>
+<a name="4194"><span class="lineNum">    4194 </span>            :     .io_write_entry_tailSlot_sharing  (u_s1_ftb_entry_tailSlot_sharing),</a>
+<a name="4195"><span class="lineNum">    4195 </span>            :     .io_write_entry_tailSlot_valid    (u_s1_ftb_entry_tailSlot_valid),</a>
+<a name="4196"><span class="lineNum">    4196 </span>            :     .io_write_entry_pftAddr           (u_s1_ftb_entry_pftAddr),</a>
+<a name="4197"><span class="lineNum">    4197 </span>            :     .io_write_entry_carry             (u_s1_ftb_entry_carry),</a>
+<a name="4198"><span class="lineNum">    4198 </span>            :     .io_write_entry_always_taken_0    (u_s1_ftb_entry_always_taken_0),</a>
+<a name="4199"><span class="lineNum">    4199 </span>            :     .io_write_entry_always_taken_1    (u_s1_ftb_entry_always_taken_1),</a>
+<a name="4200"><span class="lineNum">    4200 </span>            :     .io_write_tag                     (u_s1_tag)</a>
+<a name="4201"><span class="lineNum">    4201 </span>            :   );</a>
+<a name="4202"><span class="lineNum">    4202 </span>            :   FauFTBWay ways_19 (</a>
+<a name="4203"><span class="lineNum">    4203 </span>            :     .clock                            (clock),</a>
+<a name="4204"><span class="lineNum">    4204 </span>            :     .reset                            (reset),</a>
+<a name="4205"><span class="lineNum">    4205 </span>            :     .io_req_tag                       (s1_pc_dup_0[16:1]),</a>
+<a name="4206"><span class="lineNum">    4206 </span>            :     .io_resp_brSlots_0_offset         (_ways_19_io_resp_brSlots_0_offset),</a>
+<a name="4207"><span class="lineNum">    4207 </span>            :     .io_resp_brSlots_0_lower          (_ways_19_io_resp_brSlots_0_lower),</a>
+<a name="4208"><span class="lineNum">    4208 </span>            :     .io_resp_brSlots_0_tarStat        (_ways_19_io_resp_brSlots_0_tarStat),</a>
+<a name="4209"><span class="lineNum">    4209 </span>            :     .io_resp_brSlots_0_valid          (_ways_19_io_resp_brSlots_0_valid),</a>
+<a name="4210"><span class="lineNum">    4210 </span>            :     .io_resp_tailSlot_offset          (_ways_19_io_resp_tailSlot_offset),</a>
+<a name="4211"><span class="lineNum">    4211 </span>            :     .io_resp_tailSlot_lower           (_ways_19_io_resp_tailSlot_lower),</a>
+<a name="4212"><span class="lineNum">    4212 </span>            :     .io_resp_tailSlot_tarStat         (_ways_19_io_resp_tailSlot_tarStat),</a>
+<a name="4213"><span class="lineNum">    4213 </span>            :     .io_resp_tailSlot_sharing         (_ways_19_io_resp_tailSlot_sharing),</a>
+<a name="4214"><span class="lineNum">    4214 </span>            :     .io_resp_tailSlot_valid           (_ways_19_io_resp_tailSlot_valid),</a>
+<a name="4215"><span class="lineNum">    4215 </span>            :     .io_resp_pftAddr                  (_ways_19_io_resp_pftAddr),</a>
+<a name="4216"><span class="lineNum">    4216 </span>            :     .io_resp_carry                    (_ways_19_io_resp_carry),</a>
+<a name="4217"><span class="lineNum">    4217 </span>            :     .io_resp_always_taken_0           (_ways_19_io_resp_always_taken_0),</a>
+<a name="4218"><span class="lineNum">    4218 </span>            :     .io_resp_always_taken_1           (_ways_19_io_resp_always_taken_1),</a>
+<a name="4219"><span class="lineNum">    4219 </span>            :     .io_resp_hit                      (_ways_19_io_resp_hit),</a>
+<a name="4220"><span class="lineNum">    4220 </span>            :     .io_update_req_tag                (io_update_bits_pc[16:1]),</a>
+<a name="4221"><span class="lineNum">    4221 </span>            :     .io_update_hit                    (_ways_19_io_update_hit),</a>
+<a name="4222"><span class="lineNum">    4222 </span>            :     .io_write_valid                   (u_s1_ways_write_valid_19),</a>
+<a name="4223"><span class="lineNum">    4223 </span>            :     .io_write_entry_brSlots_0_offset  (u_s1_ftb_entry_brSlots_0_offset),</a>
+<a name="4224"><span class="lineNum">    4224 </span>            :     .io_write_entry_brSlots_0_lower   (u_s1_ftb_entry_brSlots_0_lower),</a>
+<a name="4225"><span class="lineNum">    4225 </span>            :     .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat),</a>
+<a name="4226"><span class="lineNum">    4226 </span>            :     .io_write_entry_brSlots_0_valid   (u_s1_ftb_entry_brSlots_0_valid),</a>
+<a name="4227"><span class="lineNum">    4227 </span>            :     .io_write_entry_tailSlot_offset   (u_s1_ftb_entry_tailSlot_offset),</a>
+<a name="4228"><span class="lineNum">    4228 </span>            :     .io_write_entry_tailSlot_lower    (u_s1_ftb_entry_tailSlot_lower),</a>
+<a name="4229"><span class="lineNum">    4229 </span>            :     .io_write_entry_tailSlot_tarStat  (u_s1_ftb_entry_tailSlot_tarStat),</a>
+<a name="4230"><span class="lineNum">    4230 </span>            :     .io_write_entry_tailSlot_sharing  (u_s1_ftb_entry_tailSlot_sharing),</a>
+<a name="4231"><span class="lineNum">    4231 </span>            :     .io_write_entry_tailSlot_valid    (u_s1_ftb_entry_tailSlot_valid),</a>
+<a name="4232"><span class="lineNum">    4232 </span>            :     .io_write_entry_pftAddr           (u_s1_ftb_entry_pftAddr),</a>
+<a name="4233"><span class="lineNum">    4233 </span>            :     .io_write_entry_carry             (u_s1_ftb_entry_carry),</a>
+<a name="4234"><span class="lineNum">    4234 </span>            :     .io_write_entry_always_taken_0    (u_s1_ftb_entry_always_taken_0),</a>
+<a name="4235"><span class="lineNum">    4235 </span>            :     .io_write_entry_always_taken_1    (u_s1_ftb_entry_always_taken_1),</a>
+<a name="4236"><span class="lineNum">    4236 </span>            :     .io_write_tag                     (u_s1_tag)</a>
+<a name="4237"><span class="lineNum">    4237 </span>            :   );</a>
+<a name="4238"><span class="lineNum">    4238 </span>            :   FauFTBWay ways_20 (</a>
+<a name="4239"><span class="lineNum">    4239 </span>            :     .clock                            (clock),</a>
+<a name="4240"><span class="lineNum">    4240 </span>            :     .reset                            (reset),</a>
+<a name="4241"><span class="lineNum">    4241 </span>            :     .io_req_tag                       (s1_pc_dup_0[16:1]),</a>
+<a name="4242"><span class="lineNum">    4242 </span>            :     .io_resp_brSlots_0_offset         (_ways_20_io_resp_brSlots_0_offset),</a>
+<a name="4243"><span class="lineNum">    4243 </span>            :     .io_resp_brSlots_0_lower          (_ways_20_io_resp_brSlots_0_lower),</a>
+<a name="4244"><span class="lineNum">    4244 </span>            :     .io_resp_brSlots_0_tarStat        (_ways_20_io_resp_brSlots_0_tarStat),</a>
+<a name="4245"><span class="lineNum">    4245 </span>            :     .io_resp_brSlots_0_valid          (_ways_20_io_resp_brSlots_0_valid),</a>
+<a name="4246"><span class="lineNum">    4246 </span>            :     .io_resp_tailSlot_offset          (_ways_20_io_resp_tailSlot_offset),</a>
+<a name="4247"><span class="lineNum">    4247 </span>            :     .io_resp_tailSlot_lower           (_ways_20_io_resp_tailSlot_lower),</a>
+<a name="4248"><span class="lineNum">    4248 </span>            :     .io_resp_tailSlot_tarStat         (_ways_20_io_resp_tailSlot_tarStat),</a>
+<a name="4249"><span class="lineNum">    4249 </span>            :     .io_resp_tailSlot_sharing         (_ways_20_io_resp_tailSlot_sharing),</a>
+<a name="4250"><span class="lineNum">    4250 </span>            :     .io_resp_tailSlot_valid           (_ways_20_io_resp_tailSlot_valid),</a>
+<a name="4251"><span class="lineNum">    4251 </span>            :     .io_resp_pftAddr                  (_ways_20_io_resp_pftAddr),</a>
+<a name="4252"><span class="lineNum">    4252 </span>            :     .io_resp_carry                    (_ways_20_io_resp_carry),</a>
+<a name="4253"><span class="lineNum">    4253 </span>            :     .io_resp_always_taken_0           (_ways_20_io_resp_always_taken_0),</a>
+<a name="4254"><span class="lineNum">    4254 </span>            :     .io_resp_always_taken_1           (_ways_20_io_resp_always_taken_1),</a>
+<a name="4255"><span class="lineNum">    4255 </span>            :     .io_resp_hit                      (_ways_20_io_resp_hit),</a>
+<a name="4256"><span class="lineNum">    4256 </span>            :     .io_update_req_tag                (io_update_bits_pc[16:1]),</a>
+<a name="4257"><span class="lineNum">    4257 </span>            :     .io_update_hit                    (_ways_20_io_update_hit),</a>
+<a name="4258"><span class="lineNum">    4258 </span>            :     .io_write_valid                   (u_s1_ways_write_valid_20),</a>
+<a name="4259"><span class="lineNum">    4259 </span>            :     .io_write_entry_brSlots_0_offset  (u_s1_ftb_entry_brSlots_0_offset),</a>
+<a name="4260"><span class="lineNum">    4260 </span>            :     .io_write_entry_brSlots_0_lower   (u_s1_ftb_entry_brSlots_0_lower),</a>
+<a name="4261"><span class="lineNum">    4261 </span>            :     .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat),</a>
+<a name="4262"><span class="lineNum">    4262 </span>            :     .io_write_entry_brSlots_0_valid   (u_s1_ftb_entry_brSlots_0_valid),</a>
+<a name="4263"><span class="lineNum">    4263 </span>            :     .io_write_entry_tailSlot_offset   (u_s1_ftb_entry_tailSlot_offset),</a>
+<a name="4264"><span class="lineNum">    4264 </span>            :     .io_write_entry_tailSlot_lower    (u_s1_ftb_entry_tailSlot_lower),</a>
+<a name="4265"><span class="lineNum">    4265 </span>            :     .io_write_entry_tailSlot_tarStat  (u_s1_ftb_entry_tailSlot_tarStat),</a>
+<a name="4266"><span class="lineNum">    4266 </span>            :     .io_write_entry_tailSlot_sharing  (u_s1_ftb_entry_tailSlot_sharing),</a>
+<a name="4267"><span class="lineNum">    4267 </span>            :     .io_write_entry_tailSlot_valid    (u_s1_ftb_entry_tailSlot_valid),</a>
+<a name="4268"><span class="lineNum">    4268 </span>            :     .io_write_entry_pftAddr           (u_s1_ftb_entry_pftAddr),</a>
+<a name="4269"><span class="lineNum">    4269 </span>            :     .io_write_entry_carry             (u_s1_ftb_entry_carry),</a>
+<a name="4270"><span class="lineNum">    4270 </span>            :     .io_write_entry_always_taken_0    (u_s1_ftb_entry_always_taken_0),</a>
+<a name="4271"><span class="lineNum">    4271 </span>            :     .io_write_entry_always_taken_1    (u_s1_ftb_entry_always_taken_1),</a>
+<a name="4272"><span class="lineNum">    4272 </span>            :     .io_write_tag                     (u_s1_tag)</a>
+<a name="4273"><span class="lineNum">    4273 </span>            :   );</a>
+<a name="4274"><span class="lineNum">    4274 </span>            :   FauFTBWay ways_21 (</a>
+<a name="4275"><span class="lineNum">    4275 </span>            :     .clock                            (clock),</a>
+<a name="4276"><span class="lineNum">    4276 </span>            :     .reset                            (reset),</a>
+<a name="4277"><span class="lineNum">    4277 </span>            :     .io_req_tag                       (s1_pc_dup_0[16:1]),</a>
+<a name="4278"><span class="lineNum">    4278 </span>            :     .io_resp_brSlots_0_offset         (_ways_21_io_resp_brSlots_0_offset),</a>
+<a name="4279"><span class="lineNum">    4279 </span>            :     .io_resp_brSlots_0_lower          (_ways_21_io_resp_brSlots_0_lower),</a>
+<a name="4280"><span class="lineNum">    4280 </span>            :     .io_resp_brSlots_0_tarStat        (_ways_21_io_resp_brSlots_0_tarStat),</a>
+<a name="4281"><span class="lineNum">    4281 </span>            :     .io_resp_brSlots_0_valid          (_ways_21_io_resp_brSlots_0_valid),</a>
+<a name="4282"><span class="lineNum">    4282 </span>            :     .io_resp_tailSlot_offset          (_ways_21_io_resp_tailSlot_offset),</a>
+<a name="4283"><span class="lineNum">    4283 </span>            :     .io_resp_tailSlot_lower           (_ways_21_io_resp_tailSlot_lower),</a>
+<a name="4284"><span class="lineNum">    4284 </span>            :     .io_resp_tailSlot_tarStat         (_ways_21_io_resp_tailSlot_tarStat),</a>
+<a name="4285"><span class="lineNum">    4285 </span>            :     .io_resp_tailSlot_sharing         (_ways_21_io_resp_tailSlot_sharing),</a>
+<a name="4286"><span class="lineNum">    4286 </span>            :     .io_resp_tailSlot_valid           (_ways_21_io_resp_tailSlot_valid),</a>
+<a name="4287"><span class="lineNum">    4287 </span>            :     .io_resp_pftAddr                  (_ways_21_io_resp_pftAddr),</a>
+<a name="4288"><span class="lineNum">    4288 </span>            :     .io_resp_carry                    (_ways_21_io_resp_carry),</a>
+<a name="4289"><span class="lineNum">    4289 </span>            :     .io_resp_always_taken_0           (_ways_21_io_resp_always_taken_0),</a>
+<a name="4290"><span class="lineNum">    4290 </span>            :     .io_resp_always_taken_1           (_ways_21_io_resp_always_taken_1),</a>
+<a name="4291"><span class="lineNum">    4291 </span>            :     .io_resp_hit                      (_ways_21_io_resp_hit),</a>
+<a name="4292"><span class="lineNum">    4292 </span>            :     .io_update_req_tag                (io_update_bits_pc[16:1]),</a>
+<a name="4293"><span class="lineNum">    4293 </span>            :     .io_update_hit                    (_ways_21_io_update_hit),</a>
+<a name="4294"><span class="lineNum">    4294 </span>            :     .io_write_valid                   (u_s1_ways_write_valid_21),</a>
+<a name="4295"><span class="lineNum">    4295 </span>            :     .io_write_entry_brSlots_0_offset  (u_s1_ftb_entry_brSlots_0_offset),</a>
+<a name="4296"><span class="lineNum">    4296 </span>            :     .io_write_entry_brSlots_0_lower   (u_s1_ftb_entry_brSlots_0_lower),</a>
+<a name="4297"><span class="lineNum">    4297 </span>            :     .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat),</a>
+<a name="4298"><span class="lineNum">    4298 </span>            :     .io_write_entry_brSlots_0_valid   (u_s1_ftb_entry_brSlots_0_valid),</a>
+<a name="4299"><span class="lineNum">    4299 </span>            :     .io_write_entry_tailSlot_offset   (u_s1_ftb_entry_tailSlot_offset),</a>
+<a name="4300"><span class="lineNum">    4300 </span>            :     .io_write_entry_tailSlot_lower    (u_s1_ftb_entry_tailSlot_lower),</a>
+<a name="4301"><span class="lineNum">    4301 </span>            :     .io_write_entry_tailSlot_tarStat  (u_s1_ftb_entry_tailSlot_tarStat),</a>
+<a name="4302"><span class="lineNum">    4302 </span>            :     .io_write_entry_tailSlot_sharing  (u_s1_ftb_entry_tailSlot_sharing),</a>
+<a name="4303"><span class="lineNum">    4303 </span>            :     .io_write_entry_tailSlot_valid    (u_s1_ftb_entry_tailSlot_valid),</a>
+<a name="4304"><span class="lineNum">    4304 </span>            :     .io_write_entry_pftAddr           (u_s1_ftb_entry_pftAddr),</a>
+<a name="4305"><span class="lineNum">    4305 </span>            :     .io_write_entry_carry             (u_s1_ftb_entry_carry),</a>
+<a name="4306"><span class="lineNum">    4306 </span>            :     .io_write_entry_always_taken_0    (u_s1_ftb_entry_always_taken_0),</a>
+<a name="4307"><span class="lineNum">    4307 </span>            :     .io_write_entry_always_taken_1    (u_s1_ftb_entry_always_taken_1),</a>
+<a name="4308"><span class="lineNum">    4308 </span>            :     .io_write_tag                     (u_s1_tag)</a>
+<a name="4309"><span class="lineNum">    4309 </span>            :   );</a>
+<a name="4310"><span class="lineNum">    4310 </span>            :   FauFTBWay ways_22 (</a>
+<a name="4311"><span class="lineNum">    4311 </span>            :     .clock                            (clock),</a>
+<a name="4312"><span class="lineNum">    4312 </span>            :     .reset                            (reset),</a>
+<a name="4313"><span class="lineNum">    4313 </span>            :     .io_req_tag                       (s1_pc_dup_0[16:1]),</a>
+<a name="4314"><span class="lineNum">    4314 </span>            :     .io_resp_brSlots_0_offset         (_ways_22_io_resp_brSlots_0_offset),</a>
+<a name="4315"><span class="lineNum">    4315 </span>            :     .io_resp_brSlots_0_lower          (_ways_22_io_resp_brSlots_0_lower),</a>
+<a name="4316"><span class="lineNum">    4316 </span>            :     .io_resp_brSlots_0_tarStat        (_ways_22_io_resp_brSlots_0_tarStat),</a>
+<a name="4317"><span class="lineNum">    4317 </span>            :     .io_resp_brSlots_0_valid          (_ways_22_io_resp_brSlots_0_valid),</a>
+<a name="4318"><span class="lineNum">    4318 </span>            :     .io_resp_tailSlot_offset          (_ways_22_io_resp_tailSlot_offset),</a>
+<a name="4319"><span class="lineNum">    4319 </span>            :     .io_resp_tailSlot_lower           (_ways_22_io_resp_tailSlot_lower),</a>
+<a name="4320"><span class="lineNum">    4320 </span>            :     .io_resp_tailSlot_tarStat         (_ways_22_io_resp_tailSlot_tarStat),</a>
+<a name="4321"><span class="lineNum">    4321 </span>            :     .io_resp_tailSlot_sharing         (_ways_22_io_resp_tailSlot_sharing),</a>
+<a name="4322"><span class="lineNum">    4322 </span>            :     .io_resp_tailSlot_valid           (_ways_22_io_resp_tailSlot_valid),</a>
+<a name="4323"><span class="lineNum">    4323 </span>            :     .io_resp_pftAddr                  (_ways_22_io_resp_pftAddr),</a>
+<a name="4324"><span class="lineNum">    4324 </span>            :     .io_resp_carry                    (_ways_22_io_resp_carry),</a>
+<a name="4325"><span class="lineNum">    4325 </span>            :     .io_resp_always_taken_0           (_ways_22_io_resp_always_taken_0),</a>
+<a name="4326"><span class="lineNum">    4326 </span>            :     .io_resp_always_taken_1           (_ways_22_io_resp_always_taken_1),</a>
+<a name="4327"><span class="lineNum">    4327 </span>            :     .io_resp_hit                      (_ways_22_io_resp_hit),</a>
+<a name="4328"><span class="lineNum">    4328 </span>            :     .io_update_req_tag                (io_update_bits_pc[16:1]),</a>
+<a name="4329"><span class="lineNum">    4329 </span>            :     .io_update_hit                    (_ways_22_io_update_hit),</a>
+<a name="4330"><span class="lineNum">    4330 </span>            :     .io_write_valid                   (u_s1_ways_write_valid_22),</a>
+<a name="4331"><span class="lineNum">    4331 </span>            :     .io_write_entry_brSlots_0_offset  (u_s1_ftb_entry_brSlots_0_offset),</a>
+<a name="4332"><span class="lineNum">    4332 </span>            :     .io_write_entry_brSlots_0_lower   (u_s1_ftb_entry_brSlots_0_lower),</a>
+<a name="4333"><span class="lineNum">    4333 </span>            :     .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat),</a>
+<a name="4334"><span class="lineNum">    4334 </span>            :     .io_write_entry_brSlots_0_valid   (u_s1_ftb_entry_brSlots_0_valid),</a>
+<a name="4335"><span class="lineNum">    4335 </span>            :     .io_write_entry_tailSlot_offset   (u_s1_ftb_entry_tailSlot_offset),</a>
+<a name="4336"><span class="lineNum">    4336 </span>            :     .io_write_entry_tailSlot_lower    (u_s1_ftb_entry_tailSlot_lower),</a>
+<a name="4337"><span class="lineNum">    4337 </span>            :     .io_write_entry_tailSlot_tarStat  (u_s1_ftb_entry_tailSlot_tarStat),</a>
+<a name="4338"><span class="lineNum">    4338 </span>            :     .io_write_entry_tailSlot_sharing  (u_s1_ftb_entry_tailSlot_sharing),</a>
+<a name="4339"><span class="lineNum">    4339 </span>            :     .io_write_entry_tailSlot_valid    (u_s1_ftb_entry_tailSlot_valid),</a>
+<a name="4340"><span class="lineNum">    4340 </span>            :     .io_write_entry_pftAddr           (u_s1_ftb_entry_pftAddr),</a>
+<a name="4341"><span class="lineNum">    4341 </span>            :     .io_write_entry_carry             (u_s1_ftb_entry_carry),</a>
+<a name="4342"><span class="lineNum">    4342 </span>            :     .io_write_entry_always_taken_0    (u_s1_ftb_entry_always_taken_0),</a>
+<a name="4343"><span class="lineNum">    4343 </span>            :     .io_write_entry_always_taken_1    (u_s1_ftb_entry_always_taken_1),</a>
+<a name="4344"><span class="lineNum">    4344 </span>            :     .io_write_tag                     (u_s1_tag)</a>
+<a name="4345"><span class="lineNum">    4345 </span>            :   );</a>
+<a name="4346"><span class="lineNum">    4346 </span>            :   FauFTBWay ways_23 (</a>
+<a name="4347"><span class="lineNum">    4347 </span>            :     .clock                            (clock),</a>
+<a name="4348"><span class="lineNum">    4348 </span>            :     .reset                            (reset),</a>
+<a name="4349"><span class="lineNum">    4349 </span>            :     .io_req_tag                       (s1_pc_dup_0[16:1]),</a>
+<a name="4350"><span class="lineNum">    4350 </span>            :     .io_resp_brSlots_0_offset         (_ways_23_io_resp_brSlots_0_offset),</a>
+<a name="4351"><span class="lineNum">    4351 </span>            :     .io_resp_brSlots_0_lower          (_ways_23_io_resp_brSlots_0_lower),</a>
+<a name="4352"><span class="lineNum">    4352 </span>            :     .io_resp_brSlots_0_tarStat        (_ways_23_io_resp_brSlots_0_tarStat),</a>
+<a name="4353"><span class="lineNum">    4353 </span>            :     .io_resp_brSlots_0_valid          (_ways_23_io_resp_brSlots_0_valid),</a>
+<a name="4354"><span class="lineNum">    4354 </span>            :     .io_resp_tailSlot_offset          (_ways_23_io_resp_tailSlot_offset),</a>
+<a name="4355"><span class="lineNum">    4355 </span>            :     .io_resp_tailSlot_lower           (_ways_23_io_resp_tailSlot_lower),</a>
+<a name="4356"><span class="lineNum">    4356 </span>            :     .io_resp_tailSlot_tarStat         (_ways_23_io_resp_tailSlot_tarStat),</a>
+<a name="4357"><span class="lineNum">    4357 </span>            :     .io_resp_tailSlot_sharing         (_ways_23_io_resp_tailSlot_sharing),</a>
+<a name="4358"><span class="lineNum">    4358 </span>            :     .io_resp_tailSlot_valid           (_ways_23_io_resp_tailSlot_valid),</a>
+<a name="4359"><span class="lineNum">    4359 </span>            :     .io_resp_pftAddr                  (_ways_23_io_resp_pftAddr),</a>
+<a name="4360"><span class="lineNum">    4360 </span>            :     .io_resp_carry                    (_ways_23_io_resp_carry),</a>
+<a name="4361"><span class="lineNum">    4361 </span>            :     .io_resp_always_taken_0           (_ways_23_io_resp_always_taken_0),</a>
+<a name="4362"><span class="lineNum">    4362 </span>            :     .io_resp_always_taken_1           (_ways_23_io_resp_always_taken_1),</a>
+<a name="4363"><span class="lineNum">    4363 </span>            :     .io_resp_hit                      (_ways_23_io_resp_hit),</a>
+<a name="4364"><span class="lineNum">    4364 </span>            :     .io_update_req_tag                (io_update_bits_pc[16:1]),</a>
+<a name="4365"><span class="lineNum">    4365 </span>            :     .io_update_hit                    (_ways_23_io_update_hit),</a>
+<a name="4366"><span class="lineNum">    4366 </span>            :     .io_write_valid                   (u_s1_ways_write_valid_23),</a>
+<a name="4367"><span class="lineNum">    4367 </span>            :     .io_write_entry_brSlots_0_offset  (u_s1_ftb_entry_brSlots_0_offset),</a>
+<a name="4368"><span class="lineNum">    4368 </span>            :     .io_write_entry_brSlots_0_lower   (u_s1_ftb_entry_brSlots_0_lower),</a>
+<a name="4369"><span class="lineNum">    4369 </span>            :     .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat),</a>
+<a name="4370"><span class="lineNum">    4370 </span>            :     .io_write_entry_brSlots_0_valid   (u_s1_ftb_entry_brSlots_0_valid),</a>
+<a name="4371"><span class="lineNum">    4371 </span>            :     .io_write_entry_tailSlot_offset   (u_s1_ftb_entry_tailSlot_offset),</a>
+<a name="4372"><span class="lineNum">    4372 </span>            :     .io_write_entry_tailSlot_lower    (u_s1_ftb_entry_tailSlot_lower),</a>
+<a name="4373"><span class="lineNum">    4373 </span>            :     .io_write_entry_tailSlot_tarStat  (u_s1_ftb_entry_tailSlot_tarStat),</a>
+<a name="4374"><span class="lineNum">    4374 </span>            :     .io_write_entry_tailSlot_sharing  (u_s1_ftb_entry_tailSlot_sharing),</a>
+<a name="4375"><span class="lineNum">    4375 </span>            :     .io_write_entry_tailSlot_valid    (u_s1_ftb_entry_tailSlot_valid),</a>
+<a name="4376"><span class="lineNum">    4376 </span>            :     .io_write_entry_pftAddr           (u_s1_ftb_entry_pftAddr),</a>
+<a name="4377"><span class="lineNum">    4377 </span>            :     .io_write_entry_carry             (u_s1_ftb_entry_carry),</a>
+<a name="4378"><span class="lineNum">    4378 </span>            :     .io_write_entry_always_taken_0    (u_s1_ftb_entry_always_taken_0),</a>
+<a name="4379"><span class="lineNum">    4379 </span>            :     .io_write_entry_always_taken_1    (u_s1_ftb_entry_always_taken_1),</a>
+<a name="4380"><span class="lineNum">    4380 </span>            :     .io_write_tag                     (u_s1_tag)</a>
+<a name="4381"><span class="lineNum">    4381 </span>            :   );</a>
+<a name="4382"><span class="lineNum">    4382 </span>            :   FauFTBWay ways_24 (</a>
+<a name="4383"><span class="lineNum">    4383 </span>            :     .clock                            (clock),</a>
+<a name="4384"><span class="lineNum">    4384 </span>            :     .reset                            (reset),</a>
+<a name="4385"><span class="lineNum">    4385 </span>            :     .io_req_tag                       (s1_pc_dup_0[16:1]),</a>
+<a name="4386"><span class="lineNum">    4386 </span>            :     .io_resp_brSlots_0_offset         (_ways_24_io_resp_brSlots_0_offset),</a>
+<a name="4387"><span class="lineNum">    4387 </span>            :     .io_resp_brSlots_0_lower          (_ways_24_io_resp_brSlots_0_lower),</a>
+<a name="4388"><span class="lineNum">    4388 </span>            :     .io_resp_brSlots_0_tarStat        (_ways_24_io_resp_brSlots_0_tarStat),</a>
+<a name="4389"><span class="lineNum">    4389 </span>            :     .io_resp_brSlots_0_valid          (_ways_24_io_resp_brSlots_0_valid),</a>
+<a name="4390"><span class="lineNum">    4390 </span>            :     .io_resp_tailSlot_offset          (_ways_24_io_resp_tailSlot_offset),</a>
+<a name="4391"><span class="lineNum">    4391 </span>            :     .io_resp_tailSlot_lower           (_ways_24_io_resp_tailSlot_lower),</a>
+<a name="4392"><span class="lineNum">    4392 </span>            :     .io_resp_tailSlot_tarStat         (_ways_24_io_resp_tailSlot_tarStat),</a>
+<a name="4393"><span class="lineNum">    4393 </span>            :     .io_resp_tailSlot_sharing         (_ways_24_io_resp_tailSlot_sharing),</a>
+<a name="4394"><span class="lineNum">    4394 </span>            :     .io_resp_tailSlot_valid           (_ways_24_io_resp_tailSlot_valid),</a>
+<a name="4395"><span class="lineNum">    4395 </span>            :     .io_resp_pftAddr                  (_ways_24_io_resp_pftAddr),</a>
+<a name="4396"><span class="lineNum">    4396 </span>            :     .io_resp_carry                    (_ways_24_io_resp_carry),</a>
+<a name="4397"><span class="lineNum">    4397 </span>            :     .io_resp_always_taken_0           (_ways_24_io_resp_always_taken_0),</a>
+<a name="4398"><span class="lineNum">    4398 </span>            :     .io_resp_always_taken_1           (_ways_24_io_resp_always_taken_1),</a>
+<a name="4399"><span class="lineNum">    4399 </span>            :     .io_resp_hit                      (_ways_24_io_resp_hit),</a>
+<a name="4400"><span class="lineNum">    4400 </span>            :     .io_update_req_tag                (io_update_bits_pc[16:1]),</a>
+<a name="4401"><span class="lineNum">    4401 </span>            :     .io_update_hit                    (_ways_24_io_update_hit),</a>
+<a name="4402"><span class="lineNum">    4402 </span>            :     .io_write_valid                   (u_s1_ways_write_valid_24),</a>
+<a name="4403"><span class="lineNum">    4403 </span>            :     .io_write_entry_brSlots_0_offset  (u_s1_ftb_entry_brSlots_0_offset),</a>
+<a name="4404"><span class="lineNum">    4404 </span>            :     .io_write_entry_brSlots_0_lower   (u_s1_ftb_entry_brSlots_0_lower),</a>
+<a name="4405"><span class="lineNum">    4405 </span>            :     .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat),</a>
+<a name="4406"><span class="lineNum">    4406 </span>            :     .io_write_entry_brSlots_0_valid   (u_s1_ftb_entry_brSlots_0_valid),</a>
+<a name="4407"><span class="lineNum">    4407 </span>            :     .io_write_entry_tailSlot_offset   (u_s1_ftb_entry_tailSlot_offset),</a>
+<a name="4408"><span class="lineNum">    4408 </span>            :     .io_write_entry_tailSlot_lower    (u_s1_ftb_entry_tailSlot_lower),</a>
+<a name="4409"><span class="lineNum">    4409 </span>            :     .io_write_entry_tailSlot_tarStat  (u_s1_ftb_entry_tailSlot_tarStat),</a>
+<a name="4410"><span class="lineNum">    4410 </span>            :     .io_write_entry_tailSlot_sharing  (u_s1_ftb_entry_tailSlot_sharing),</a>
+<a name="4411"><span class="lineNum">    4411 </span>            :     .io_write_entry_tailSlot_valid    (u_s1_ftb_entry_tailSlot_valid),</a>
+<a name="4412"><span class="lineNum">    4412 </span>            :     .io_write_entry_pftAddr           (u_s1_ftb_entry_pftAddr),</a>
+<a name="4413"><span class="lineNum">    4413 </span>            :     .io_write_entry_carry             (u_s1_ftb_entry_carry),</a>
+<a name="4414"><span class="lineNum">    4414 </span>            :     .io_write_entry_always_taken_0    (u_s1_ftb_entry_always_taken_0),</a>
+<a name="4415"><span class="lineNum">    4415 </span>            :     .io_write_entry_always_taken_1    (u_s1_ftb_entry_always_taken_1),</a>
+<a name="4416"><span class="lineNum">    4416 </span>            :     .io_write_tag                     (u_s1_tag)</a>
+<a name="4417"><span class="lineNum">    4417 </span>            :   );</a>
+<a name="4418"><span class="lineNum">    4418 </span>            :   FauFTBWay ways_25 (</a>
+<a name="4419"><span class="lineNum">    4419 </span>            :     .clock                            (clock),</a>
+<a name="4420"><span class="lineNum">    4420 </span>            :     .reset                            (reset),</a>
+<a name="4421"><span class="lineNum">    4421 </span>            :     .io_req_tag                       (s1_pc_dup_0[16:1]),</a>
+<a name="4422"><span class="lineNum">    4422 </span>            :     .io_resp_brSlots_0_offset         (_ways_25_io_resp_brSlots_0_offset),</a>
+<a name="4423"><span class="lineNum">    4423 </span>            :     .io_resp_brSlots_0_lower          (_ways_25_io_resp_brSlots_0_lower),</a>
+<a name="4424"><span class="lineNum">    4424 </span>            :     .io_resp_brSlots_0_tarStat        (_ways_25_io_resp_brSlots_0_tarStat),</a>
+<a name="4425"><span class="lineNum">    4425 </span>            :     .io_resp_brSlots_0_valid          (_ways_25_io_resp_brSlots_0_valid),</a>
+<a name="4426"><span class="lineNum">    4426 </span>            :     .io_resp_tailSlot_offset          (_ways_25_io_resp_tailSlot_offset),</a>
+<a name="4427"><span class="lineNum">    4427 </span>            :     .io_resp_tailSlot_lower           (_ways_25_io_resp_tailSlot_lower),</a>
+<a name="4428"><span class="lineNum">    4428 </span>            :     .io_resp_tailSlot_tarStat         (_ways_25_io_resp_tailSlot_tarStat),</a>
+<a name="4429"><span class="lineNum">    4429 </span>            :     .io_resp_tailSlot_sharing         (_ways_25_io_resp_tailSlot_sharing),</a>
+<a name="4430"><span class="lineNum">    4430 </span>            :     .io_resp_tailSlot_valid           (_ways_25_io_resp_tailSlot_valid),</a>
+<a name="4431"><span class="lineNum">    4431 </span>            :     .io_resp_pftAddr                  (_ways_25_io_resp_pftAddr),</a>
+<a name="4432"><span class="lineNum">    4432 </span>            :     .io_resp_carry                    (_ways_25_io_resp_carry),</a>
+<a name="4433"><span class="lineNum">    4433 </span>            :     .io_resp_always_taken_0           (_ways_25_io_resp_always_taken_0),</a>
+<a name="4434"><span class="lineNum">    4434 </span>            :     .io_resp_always_taken_1           (_ways_25_io_resp_always_taken_1),</a>
+<a name="4435"><span class="lineNum">    4435 </span>            :     .io_resp_hit                      (_ways_25_io_resp_hit),</a>
+<a name="4436"><span class="lineNum">    4436 </span>            :     .io_update_req_tag                (io_update_bits_pc[16:1]),</a>
+<a name="4437"><span class="lineNum">    4437 </span>            :     .io_update_hit                    (_ways_25_io_update_hit),</a>
+<a name="4438"><span class="lineNum">    4438 </span>            :     .io_write_valid                   (u_s1_ways_write_valid_25),</a>
+<a name="4439"><span class="lineNum">    4439 </span>            :     .io_write_entry_brSlots_0_offset  (u_s1_ftb_entry_brSlots_0_offset),</a>
+<a name="4440"><span class="lineNum">    4440 </span>            :     .io_write_entry_brSlots_0_lower   (u_s1_ftb_entry_brSlots_0_lower),</a>
+<a name="4441"><span class="lineNum">    4441 </span>            :     .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat),</a>
+<a name="4442"><span class="lineNum">    4442 </span>            :     .io_write_entry_brSlots_0_valid   (u_s1_ftb_entry_brSlots_0_valid),</a>
+<a name="4443"><span class="lineNum">    4443 </span>            :     .io_write_entry_tailSlot_offset   (u_s1_ftb_entry_tailSlot_offset),</a>
+<a name="4444"><span class="lineNum">    4444 </span>            :     .io_write_entry_tailSlot_lower    (u_s1_ftb_entry_tailSlot_lower),</a>
+<a name="4445"><span class="lineNum">    4445 </span>            :     .io_write_entry_tailSlot_tarStat  (u_s1_ftb_entry_tailSlot_tarStat),</a>
+<a name="4446"><span class="lineNum">    4446 </span>            :     .io_write_entry_tailSlot_sharing  (u_s1_ftb_entry_tailSlot_sharing),</a>
+<a name="4447"><span class="lineNum">    4447 </span>            :     .io_write_entry_tailSlot_valid    (u_s1_ftb_entry_tailSlot_valid),</a>
+<a name="4448"><span class="lineNum">    4448 </span>            :     .io_write_entry_pftAddr           (u_s1_ftb_entry_pftAddr),</a>
+<a name="4449"><span class="lineNum">    4449 </span>            :     .io_write_entry_carry             (u_s1_ftb_entry_carry),</a>
+<a name="4450"><span class="lineNum">    4450 </span>            :     .io_write_entry_always_taken_0    (u_s1_ftb_entry_always_taken_0),</a>
+<a name="4451"><span class="lineNum">    4451 </span>            :     .io_write_entry_always_taken_1    (u_s1_ftb_entry_always_taken_1),</a>
+<a name="4452"><span class="lineNum">    4452 </span>            :     .io_write_tag                     (u_s1_tag)</a>
+<a name="4453"><span class="lineNum">    4453 </span>            :   );</a>
+<a name="4454"><span class="lineNum">    4454 </span>            :   FauFTBWay ways_26 (</a>
+<a name="4455"><span class="lineNum">    4455 </span>            :     .clock                            (clock),</a>
+<a name="4456"><span class="lineNum">    4456 </span>            :     .reset                            (reset),</a>
+<a name="4457"><span class="lineNum">    4457 </span>            :     .io_req_tag                       (s1_pc_dup_0[16:1]),</a>
+<a name="4458"><span class="lineNum">    4458 </span>            :     .io_resp_brSlots_0_offset         (_ways_26_io_resp_brSlots_0_offset),</a>
+<a name="4459"><span class="lineNum">    4459 </span>            :     .io_resp_brSlots_0_lower          (_ways_26_io_resp_brSlots_0_lower),</a>
+<a name="4460"><span class="lineNum">    4460 </span>            :     .io_resp_brSlots_0_tarStat        (_ways_26_io_resp_brSlots_0_tarStat),</a>
+<a name="4461"><span class="lineNum">    4461 </span>            :     .io_resp_brSlots_0_valid          (_ways_26_io_resp_brSlots_0_valid),</a>
+<a name="4462"><span class="lineNum">    4462 </span>            :     .io_resp_tailSlot_offset          (_ways_26_io_resp_tailSlot_offset),</a>
+<a name="4463"><span class="lineNum">    4463 </span>            :     .io_resp_tailSlot_lower           (_ways_26_io_resp_tailSlot_lower),</a>
+<a name="4464"><span class="lineNum">    4464 </span>            :     .io_resp_tailSlot_tarStat         (_ways_26_io_resp_tailSlot_tarStat),</a>
+<a name="4465"><span class="lineNum">    4465 </span>            :     .io_resp_tailSlot_sharing         (_ways_26_io_resp_tailSlot_sharing),</a>
+<a name="4466"><span class="lineNum">    4466 </span>            :     .io_resp_tailSlot_valid           (_ways_26_io_resp_tailSlot_valid),</a>
+<a name="4467"><span class="lineNum">    4467 </span>            :     .io_resp_pftAddr                  (_ways_26_io_resp_pftAddr),</a>
+<a name="4468"><span class="lineNum">    4468 </span>            :     .io_resp_carry                    (_ways_26_io_resp_carry),</a>
+<a name="4469"><span class="lineNum">    4469 </span>            :     .io_resp_always_taken_0           (_ways_26_io_resp_always_taken_0),</a>
+<a name="4470"><span class="lineNum">    4470 </span>            :     .io_resp_always_taken_1           (_ways_26_io_resp_always_taken_1),</a>
+<a name="4471"><span class="lineNum">    4471 </span>            :     .io_resp_hit                      (_ways_26_io_resp_hit),</a>
+<a name="4472"><span class="lineNum">    4472 </span>            :     .io_update_req_tag                (io_update_bits_pc[16:1]),</a>
+<a name="4473"><span class="lineNum">    4473 </span>            :     .io_update_hit                    (_ways_26_io_update_hit),</a>
+<a name="4474"><span class="lineNum">    4474 </span>            :     .io_write_valid                   (u_s1_ways_write_valid_26),</a>
+<a name="4475"><span class="lineNum">    4475 </span>            :     .io_write_entry_brSlots_0_offset  (u_s1_ftb_entry_brSlots_0_offset),</a>
+<a name="4476"><span class="lineNum">    4476 </span>            :     .io_write_entry_brSlots_0_lower   (u_s1_ftb_entry_brSlots_0_lower),</a>
+<a name="4477"><span class="lineNum">    4477 </span>            :     .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat),</a>
+<a name="4478"><span class="lineNum">    4478 </span>            :     .io_write_entry_brSlots_0_valid   (u_s1_ftb_entry_brSlots_0_valid),</a>
+<a name="4479"><span class="lineNum">    4479 </span>            :     .io_write_entry_tailSlot_offset   (u_s1_ftb_entry_tailSlot_offset),</a>
+<a name="4480"><span class="lineNum">    4480 </span>            :     .io_write_entry_tailSlot_lower    (u_s1_ftb_entry_tailSlot_lower),</a>
+<a name="4481"><span class="lineNum">    4481 </span>            :     .io_write_entry_tailSlot_tarStat  (u_s1_ftb_entry_tailSlot_tarStat),</a>
+<a name="4482"><span class="lineNum">    4482 </span>            :     .io_write_entry_tailSlot_sharing  (u_s1_ftb_entry_tailSlot_sharing),</a>
+<a name="4483"><span class="lineNum">    4483 </span>            :     .io_write_entry_tailSlot_valid    (u_s1_ftb_entry_tailSlot_valid),</a>
+<a name="4484"><span class="lineNum">    4484 </span>            :     .io_write_entry_pftAddr           (u_s1_ftb_entry_pftAddr),</a>
+<a name="4485"><span class="lineNum">    4485 </span>            :     .io_write_entry_carry             (u_s1_ftb_entry_carry),</a>
+<a name="4486"><span class="lineNum">    4486 </span>            :     .io_write_entry_always_taken_0    (u_s1_ftb_entry_always_taken_0),</a>
+<a name="4487"><span class="lineNum">    4487 </span>            :     .io_write_entry_always_taken_1    (u_s1_ftb_entry_always_taken_1),</a>
+<a name="4488"><span class="lineNum">    4488 </span>            :     .io_write_tag                     (u_s1_tag)</a>
+<a name="4489"><span class="lineNum">    4489 </span>            :   );</a>
+<a name="4490"><span class="lineNum">    4490 </span>            :   FauFTBWay ways_27 (</a>
+<a name="4491"><span class="lineNum">    4491 </span>            :     .clock                            (clock),</a>
+<a name="4492"><span class="lineNum">    4492 </span>            :     .reset                            (reset),</a>
+<a name="4493"><span class="lineNum">    4493 </span>            :     .io_req_tag                       (s1_pc_dup_0[16:1]),</a>
+<a name="4494"><span class="lineNum">    4494 </span>            :     .io_resp_brSlots_0_offset         (_ways_27_io_resp_brSlots_0_offset),</a>
+<a name="4495"><span class="lineNum">    4495 </span>            :     .io_resp_brSlots_0_lower          (_ways_27_io_resp_brSlots_0_lower),</a>
+<a name="4496"><span class="lineNum">    4496 </span>            :     .io_resp_brSlots_0_tarStat        (_ways_27_io_resp_brSlots_0_tarStat),</a>
+<a name="4497"><span class="lineNum">    4497 </span>            :     .io_resp_brSlots_0_valid          (_ways_27_io_resp_brSlots_0_valid),</a>
+<a name="4498"><span class="lineNum">    4498 </span>            :     .io_resp_tailSlot_offset          (_ways_27_io_resp_tailSlot_offset),</a>
+<a name="4499"><span class="lineNum">    4499 </span>            :     .io_resp_tailSlot_lower           (_ways_27_io_resp_tailSlot_lower),</a>
+<a name="4500"><span class="lineNum">    4500 </span>            :     .io_resp_tailSlot_tarStat         (_ways_27_io_resp_tailSlot_tarStat),</a>
+<a name="4501"><span class="lineNum">    4501 </span>            :     .io_resp_tailSlot_sharing         (_ways_27_io_resp_tailSlot_sharing),</a>
+<a name="4502"><span class="lineNum">    4502 </span>            :     .io_resp_tailSlot_valid           (_ways_27_io_resp_tailSlot_valid),</a>
+<a name="4503"><span class="lineNum">    4503 </span>            :     .io_resp_pftAddr                  (_ways_27_io_resp_pftAddr),</a>
+<a name="4504"><span class="lineNum">    4504 </span>            :     .io_resp_carry                    (_ways_27_io_resp_carry),</a>
+<a name="4505"><span class="lineNum">    4505 </span>            :     .io_resp_always_taken_0           (_ways_27_io_resp_always_taken_0),</a>
+<a name="4506"><span class="lineNum">    4506 </span>            :     .io_resp_always_taken_1           (_ways_27_io_resp_always_taken_1),</a>
+<a name="4507"><span class="lineNum">    4507 </span>            :     .io_resp_hit                      (_ways_27_io_resp_hit),</a>
+<a name="4508"><span class="lineNum">    4508 </span>            :     .io_update_req_tag                (io_update_bits_pc[16:1]),</a>
+<a name="4509"><span class="lineNum">    4509 </span>            :     .io_update_hit                    (_ways_27_io_update_hit),</a>
+<a name="4510"><span class="lineNum">    4510 </span>            :     .io_write_valid                   (u_s1_ways_write_valid_27),</a>
+<a name="4511"><span class="lineNum">    4511 </span>            :     .io_write_entry_brSlots_0_offset  (u_s1_ftb_entry_brSlots_0_offset),</a>
+<a name="4512"><span class="lineNum">    4512 </span>            :     .io_write_entry_brSlots_0_lower   (u_s1_ftb_entry_brSlots_0_lower),</a>
+<a name="4513"><span class="lineNum">    4513 </span>            :     .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat),</a>
+<a name="4514"><span class="lineNum">    4514 </span>            :     .io_write_entry_brSlots_0_valid   (u_s1_ftb_entry_brSlots_0_valid),</a>
+<a name="4515"><span class="lineNum">    4515 </span>            :     .io_write_entry_tailSlot_offset   (u_s1_ftb_entry_tailSlot_offset),</a>
+<a name="4516"><span class="lineNum">    4516 </span>            :     .io_write_entry_tailSlot_lower    (u_s1_ftb_entry_tailSlot_lower),</a>
+<a name="4517"><span class="lineNum">    4517 </span>            :     .io_write_entry_tailSlot_tarStat  (u_s1_ftb_entry_tailSlot_tarStat),</a>
+<a name="4518"><span class="lineNum">    4518 </span>            :     .io_write_entry_tailSlot_sharing  (u_s1_ftb_entry_tailSlot_sharing),</a>
+<a name="4519"><span class="lineNum">    4519 </span>            :     .io_write_entry_tailSlot_valid    (u_s1_ftb_entry_tailSlot_valid),</a>
+<a name="4520"><span class="lineNum">    4520 </span>            :     .io_write_entry_pftAddr           (u_s1_ftb_entry_pftAddr),</a>
+<a name="4521"><span class="lineNum">    4521 </span>            :     .io_write_entry_carry             (u_s1_ftb_entry_carry),</a>
+<a name="4522"><span class="lineNum">    4522 </span>            :     .io_write_entry_always_taken_0    (u_s1_ftb_entry_always_taken_0),</a>
+<a name="4523"><span class="lineNum">    4523 </span>            :     .io_write_entry_always_taken_1    (u_s1_ftb_entry_always_taken_1),</a>
+<a name="4524"><span class="lineNum">    4524 </span>            :     .io_write_tag                     (u_s1_tag)</a>
+<a name="4525"><span class="lineNum">    4525 </span>            :   );</a>
+<a name="4526"><span class="lineNum">    4526 </span>            :   FauFTBWay ways_28 (</a>
+<a name="4527"><span class="lineNum">    4527 </span>            :     .clock                            (clock),</a>
+<a name="4528"><span class="lineNum">    4528 </span>            :     .reset                            (reset),</a>
+<a name="4529"><span class="lineNum">    4529 </span>            :     .io_req_tag                       (s1_pc_dup_0[16:1]),</a>
+<a name="4530"><span class="lineNum">    4530 </span>            :     .io_resp_brSlots_0_offset         (_ways_28_io_resp_brSlots_0_offset),</a>
+<a name="4531"><span class="lineNum">    4531 </span>            :     .io_resp_brSlots_0_lower          (_ways_28_io_resp_brSlots_0_lower),</a>
+<a name="4532"><span class="lineNum">    4532 </span>            :     .io_resp_brSlots_0_tarStat        (_ways_28_io_resp_brSlots_0_tarStat),</a>
+<a name="4533"><span class="lineNum">    4533 </span>            :     .io_resp_brSlots_0_valid          (_ways_28_io_resp_brSlots_0_valid),</a>
+<a name="4534"><span class="lineNum">    4534 </span>            :     .io_resp_tailSlot_offset          (_ways_28_io_resp_tailSlot_offset),</a>
+<a name="4535"><span class="lineNum">    4535 </span>            :     .io_resp_tailSlot_lower           (_ways_28_io_resp_tailSlot_lower),</a>
+<a name="4536"><span class="lineNum">    4536 </span>            :     .io_resp_tailSlot_tarStat         (_ways_28_io_resp_tailSlot_tarStat),</a>
+<a name="4537"><span class="lineNum">    4537 </span>            :     .io_resp_tailSlot_sharing         (_ways_28_io_resp_tailSlot_sharing),</a>
+<a name="4538"><span class="lineNum">    4538 </span>            :     .io_resp_tailSlot_valid           (_ways_28_io_resp_tailSlot_valid),</a>
+<a name="4539"><span class="lineNum">    4539 </span>            :     .io_resp_pftAddr                  (_ways_28_io_resp_pftAddr),</a>
+<a name="4540"><span class="lineNum">    4540 </span>            :     .io_resp_carry                    (_ways_28_io_resp_carry),</a>
+<a name="4541"><span class="lineNum">    4541 </span>            :     .io_resp_always_taken_0           (_ways_28_io_resp_always_taken_0),</a>
+<a name="4542"><span class="lineNum">    4542 </span>            :     .io_resp_always_taken_1           (_ways_28_io_resp_always_taken_1),</a>
+<a name="4543"><span class="lineNum">    4543 </span>            :     .io_resp_hit                      (_ways_28_io_resp_hit),</a>
+<a name="4544"><span class="lineNum">    4544 </span>            :     .io_update_req_tag                (io_update_bits_pc[16:1]),</a>
+<a name="4545"><span class="lineNum">    4545 </span>            :     .io_update_hit                    (_ways_28_io_update_hit),</a>
+<a name="4546"><span class="lineNum">    4546 </span>            :     .io_write_valid                   (u_s1_ways_write_valid_28),</a>
+<a name="4547"><span class="lineNum">    4547 </span>            :     .io_write_entry_brSlots_0_offset  (u_s1_ftb_entry_brSlots_0_offset),</a>
+<a name="4548"><span class="lineNum">    4548 </span>            :     .io_write_entry_brSlots_0_lower   (u_s1_ftb_entry_brSlots_0_lower),</a>
+<a name="4549"><span class="lineNum">    4549 </span>            :     .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat),</a>
+<a name="4550"><span class="lineNum">    4550 </span>            :     .io_write_entry_brSlots_0_valid   (u_s1_ftb_entry_brSlots_0_valid),</a>
+<a name="4551"><span class="lineNum">    4551 </span>            :     .io_write_entry_tailSlot_offset   (u_s1_ftb_entry_tailSlot_offset),</a>
+<a name="4552"><span class="lineNum">    4552 </span>            :     .io_write_entry_tailSlot_lower    (u_s1_ftb_entry_tailSlot_lower),</a>
+<a name="4553"><span class="lineNum">    4553 </span>            :     .io_write_entry_tailSlot_tarStat  (u_s1_ftb_entry_tailSlot_tarStat),</a>
+<a name="4554"><span class="lineNum">    4554 </span>            :     .io_write_entry_tailSlot_sharing  (u_s1_ftb_entry_tailSlot_sharing),</a>
+<a name="4555"><span class="lineNum">    4555 </span>            :     .io_write_entry_tailSlot_valid    (u_s1_ftb_entry_tailSlot_valid),</a>
+<a name="4556"><span class="lineNum">    4556 </span>            :     .io_write_entry_pftAddr           (u_s1_ftb_entry_pftAddr),</a>
+<a name="4557"><span class="lineNum">    4557 </span>            :     .io_write_entry_carry             (u_s1_ftb_entry_carry),</a>
+<a name="4558"><span class="lineNum">    4558 </span>            :     .io_write_entry_always_taken_0    (u_s1_ftb_entry_always_taken_0),</a>
+<a name="4559"><span class="lineNum">    4559 </span>            :     .io_write_entry_always_taken_1    (u_s1_ftb_entry_always_taken_1),</a>
+<a name="4560"><span class="lineNum">    4560 </span>            :     .io_write_tag                     (u_s1_tag)</a>
+<a name="4561"><span class="lineNum">    4561 </span>            :   );</a>
+<a name="4562"><span class="lineNum">    4562 </span>            :   FauFTBWay ways_29 (</a>
+<a name="4563"><span class="lineNum">    4563 </span>            :     .clock                            (clock),</a>
+<a name="4564"><span class="lineNum">    4564 </span>            :     .reset                            (reset),</a>
+<a name="4565"><span class="lineNum">    4565 </span>            :     .io_req_tag                       (s1_pc_dup_0[16:1]),</a>
+<a name="4566"><span class="lineNum">    4566 </span>            :     .io_resp_brSlots_0_offset         (_ways_29_io_resp_brSlots_0_offset),</a>
+<a name="4567"><span class="lineNum">    4567 </span>            :     .io_resp_brSlots_0_lower          (_ways_29_io_resp_brSlots_0_lower),</a>
+<a name="4568"><span class="lineNum">    4568 </span>            :     .io_resp_brSlots_0_tarStat        (_ways_29_io_resp_brSlots_0_tarStat),</a>
+<a name="4569"><span class="lineNum">    4569 </span>            :     .io_resp_brSlots_0_valid          (_ways_29_io_resp_brSlots_0_valid),</a>
+<a name="4570"><span class="lineNum">    4570 </span>            :     .io_resp_tailSlot_offset          (_ways_29_io_resp_tailSlot_offset),</a>
+<a name="4571"><span class="lineNum">    4571 </span>            :     .io_resp_tailSlot_lower           (_ways_29_io_resp_tailSlot_lower),</a>
+<a name="4572"><span class="lineNum">    4572 </span>            :     .io_resp_tailSlot_tarStat         (_ways_29_io_resp_tailSlot_tarStat),</a>
+<a name="4573"><span class="lineNum">    4573 </span>            :     .io_resp_tailSlot_sharing         (_ways_29_io_resp_tailSlot_sharing),</a>
+<a name="4574"><span class="lineNum">    4574 </span>            :     .io_resp_tailSlot_valid           (_ways_29_io_resp_tailSlot_valid),</a>
+<a name="4575"><span class="lineNum">    4575 </span>            :     .io_resp_pftAddr                  (_ways_29_io_resp_pftAddr),</a>
+<a name="4576"><span class="lineNum">    4576 </span>            :     .io_resp_carry                    (_ways_29_io_resp_carry),</a>
+<a name="4577"><span class="lineNum">    4577 </span>            :     .io_resp_always_taken_0           (_ways_29_io_resp_always_taken_0),</a>
+<a name="4578"><span class="lineNum">    4578 </span>            :     .io_resp_always_taken_1           (_ways_29_io_resp_always_taken_1),</a>
+<a name="4579"><span class="lineNum">    4579 </span>            :     .io_resp_hit                      (_ways_29_io_resp_hit),</a>
+<a name="4580"><span class="lineNum">    4580 </span>            :     .io_update_req_tag                (io_update_bits_pc[16:1]),</a>
+<a name="4581"><span class="lineNum">    4581 </span>            :     .io_update_hit                    (_ways_29_io_update_hit),</a>
+<a name="4582"><span class="lineNum">    4582 </span>            :     .io_write_valid                   (u_s1_ways_write_valid_29),</a>
+<a name="4583"><span class="lineNum">    4583 </span>            :     .io_write_entry_brSlots_0_offset  (u_s1_ftb_entry_brSlots_0_offset),</a>
+<a name="4584"><span class="lineNum">    4584 </span>            :     .io_write_entry_brSlots_0_lower   (u_s1_ftb_entry_brSlots_0_lower),</a>
+<a name="4585"><span class="lineNum">    4585 </span>            :     .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat),</a>
+<a name="4586"><span class="lineNum">    4586 </span>            :     .io_write_entry_brSlots_0_valid   (u_s1_ftb_entry_brSlots_0_valid),</a>
+<a name="4587"><span class="lineNum">    4587 </span>            :     .io_write_entry_tailSlot_offset   (u_s1_ftb_entry_tailSlot_offset),</a>
+<a name="4588"><span class="lineNum">    4588 </span>            :     .io_write_entry_tailSlot_lower    (u_s1_ftb_entry_tailSlot_lower),</a>
+<a name="4589"><span class="lineNum">    4589 </span>            :     .io_write_entry_tailSlot_tarStat  (u_s1_ftb_entry_tailSlot_tarStat),</a>
+<a name="4590"><span class="lineNum">    4590 </span>            :     .io_write_entry_tailSlot_sharing  (u_s1_ftb_entry_tailSlot_sharing),</a>
+<a name="4591"><span class="lineNum">    4591 </span>            :     .io_write_entry_tailSlot_valid    (u_s1_ftb_entry_tailSlot_valid),</a>
+<a name="4592"><span class="lineNum">    4592 </span>            :     .io_write_entry_pftAddr           (u_s1_ftb_entry_pftAddr),</a>
+<a name="4593"><span class="lineNum">    4593 </span>            :     .io_write_entry_carry             (u_s1_ftb_entry_carry),</a>
+<a name="4594"><span class="lineNum">    4594 </span>            :     .io_write_entry_always_taken_0    (u_s1_ftb_entry_always_taken_0),</a>
+<a name="4595"><span class="lineNum">    4595 </span>            :     .io_write_entry_always_taken_1    (u_s1_ftb_entry_always_taken_1),</a>
+<a name="4596"><span class="lineNum">    4596 </span>            :     .io_write_tag                     (u_s1_tag)</a>
+<a name="4597"><span class="lineNum">    4597 </span>            :   );</a>
+<a name="4598"><span class="lineNum">    4598 </span>            :   FauFTBWay ways_30 (</a>
+<a name="4599"><span class="lineNum">    4599 </span>            :     .clock                            (clock),</a>
+<a name="4600"><span class="lineNum">    4600 </span>            :     .reset                            (reset),</a>
+<a name="4601"><span class="lineNum">    4601 </span>            :     .io_req_tag                       (s1_pc_dup_0[16:1]),</a>
+<a name="4602"><span class="lineNum">    4602 </span>            :     .io_resp_brSlots_0_offset         (_ways_30_io_resp_brSlots_0_offset),</a>
+<a name="4603"><span class="lineNum">    4603 </span>            :     .io_resp_brSlots_0_lower          (_ways_30_io_resp_brSlots_0_lower),</a>
+<a name="4604"><span class="lineNum">    4604 </span>            :     .io_resp_brSlots_0_tarStat        (_ways_30_io_resp_brSlots_0_tarStat),</a>
+<a name="4605"><span class="lineNum">    4605 </span>            :     .io_resp_brSlots_0_valid          (_ways_30_io_resp_brSlots_0_valid),</a>
+<a name="4606"><span class="lineNum">    4606 </span>            :     .io_resp_tailSlot_offset          (_ways_30_io_resp_tailSlot_offset),</a>
+<a name="4607"><span class="lineNum">    4607 </span>            :     .io_resp_tailSlot_lower           (_ways_30_io_resp_tailSlot_lower),</a>
+<a name="4608"><span class="lineNum">    4608 </span>            :     .io_resp_tailSlot_tarStat         (_ways_30_io_resp_tailSlot_tarStat),</a>
+<a name="4609"><span class="lineNum">    4609 </span>            :     .io_resp_tailSlot_sharing         (_ways_30_io_resp_tailSlot_sharing),</a>
+<a name="4610"><span class="lineNum">    4610 </span>            :     .io_resp_tailSlot_valid           (_ways_30_io_resp_tailSlot_valid),</a>
+<a name="4611"><span class="lineNum">    4611 </span>            :     .io_resp_pftAddr                  (_ways_30_io_resp_pftAddr),</a>
+<a name="4612"><span class="lineNum">    4612 </span>            :     .io_resp_carry                    (_ways_30_io_resp_carry),</a>
+<a name="4613"><span class="lineNum">    4613 </span>            :     .io_resp_always_taken_0           (_ways_30_io_resp_always_taken_0),</a>
+<a name="4614"><span class="lineNum">    4614 </span>            :     .io_resp_always_taken_1           (_ways_30_io_resp_always_taken_1),</a>
+<a name="4615"><span class="lineNum">    4615 </span>            :     .io_resp_hit                      (_ways_30_io_resp_hit),</a>
+<a name="4616"><span class="lineNum">    4616 </span>            :     .io_update_req_tag                (io_update_bits_pc[16:1]),</a>
+<a name="4617"><span class="lineNum">    4617 </span>            :     .io_update_hit                    (_ways_30_io_update_hit),</a>
+<a name="4618"><span class="lineNum">    4618 </span>            :     .io_write_valid                   (u_s1_ways_write_valid_30),</a>
+<a name="4619"><span class="lineNum">    4619 </span>            :     .io_write_entry_brSlots_0_offset  (u_s1_ftb_entry_brSlots_0_offset),</a>
+<a name="4620"><span class="lineNum">    4620 </span>            :     .io_write_entry_brSlots_0_lower   (u_s1_ftb_entry_brSlots_0_lower),</a>
+<a name="4621"><span class="lineNum">    4621 </span>            :     .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat),</a>
+<a name="4622"><span class="lineNum">    4622 </span>            :     .io_write_entry_brSlots_0_valid   (u_s1_ftb_entry_brSlots_0_valid),</a>
+<a name="4623"><span class="lineNum">    4623 </span>            :     .io_write_entry_tailSlot_offset   (u_s1_ftb_entry_tailSlot_offset),</a>
+<a name="4624"><span class="lineNum">    4624 </span>            :     .io_write_entry_tailSlot_lower    (u_s1_ftb_entry_tailSlot_lower),</a>
+<a name="4625"><span class="lineNum">    4625 </span>            :     .io_write_entry_tailSlot_tarStat  (u_s1_ftb_entry_tailSlot_tarStat),</a>
+<a name="4626"><span class="lineNum">    4626 </span>            :     .io_write_entry_tailSlot_sharing  (u_s1_ftb_entry_tailSlot_sharing),</a>
+<a name="4627"><span class="lineNum">    4627 </span>            :     .io_write_entry_tailSlot_valid    (u_s1_ftb_entry_tailSlot_valid),</a>
+<a name="4628"><span class="lineNum">    4628 </span>            :     .io_write_entry_pftAddr           (u_s1_ftb_entry_pftAddr),</a>
+<a name="4629"><span class="lineNum">    4629 </span>            :     .io_write_entry_carry             (u_s1_ftb_entry_carry),</a>
+<a name="4630"><span class="lineNum">    4630 </span>            :     .io_write_entry_always_taken_0    (u_s1_ftb_entry_always_taken_0),</a>
+<a name="4631"><span class="lineNum">    4631 </span>            :     .io_write_entry_always_taken_1    (u_s1_ftb_entry_always_taken_1),</a>
+<a name="4632"><span class="lineNum">    4632 </span>            :     .io_write_tag                     (u_s1_tag)</a>
+<a name="4633"><span class="lineNum">    4633 </span>            :   );</a>
+<a name="4634"><span class="lineNum">    4634 </span>            :   FauFTBWay ways_31 (</a>
+<a name="4635"><span class="lineNum">    4635 </span>            :     .clock                            (clock),</a>
+<a name="4636"><span class="lineNum">    4636 </span>            :     .reset                            (reset),</a>
+<a name="4637"><span class="lineNum">    4637 </span>            :     .io_req_tag                       (s1_pc_dup_0[16:1]),</a>
+<a name="4638"><span class="lineNum">    4638 </span>            :     .io_resp_brSlots_0_offset         (_ways_31_io_resp_brSlots_0_offset),</a>
+<a name="4639"><span class="lineNum">    4639 </span>            :     .io_resp_brSlots_0_lower          (_ways_31_io_resp_brSlots_0_lower),</a>
+<a name="4640"><span class="lineNum">    4640 </span>            :     .io_resp_brSlots_0_tarStat        (_ways_31_io_resp_brSlots_0_tarStat),</a>
+<a name="4641"><span class="lineNum">    4641 </span>            :     .io_resp_brSlots_0_valid          (_ways_31_io_resp_brSlots_0_valid),</a>
+<a name="4642"><span class="lineNum">    4642 </span>            :     .io_resp_tailSlot_offset          (_ways_31_io_resp_tailSlot_offset),</a>
+<a name="4643"><span class="lineNum">    4643 </span>            :     .io_resp_tailSlot_lower           (_ways_31_io_resp_tailSlot_lower),</a>
+<a name="4644"><span class="lineNum">    4644 </span>            :     .io_resp_tailSlot_tarStat         (_ways_31_io_resp_tailSlot_tarStat),</a>
+<a name="4645"><span class="lineNum">    4645 </span>            :     .io_resp_tailSlot_sharing         (_ways_31_io_resp_tailSlot_sharing),</a>
+<a name="4646"><span class="lineNum">    4646 </span>            :     .io_resp_tailSlot_valid           (_ways_31_io_resp_tailSlot_valid),</a>
+<a name="4647"><span class="lineNum">    4647 </span>            :     .io_resp_pftAddr                  (_ways_31_io_resp_pftAddr),</a>
+<a name="4648"><span class="lineNum">    4648 </span>            :     .io_resp_carry                    (_ways_31_io_resp_carry),</a>
+<a name="4649"><span class="lineNum">    4649 </span>            :     .io_resp_always_taken_0           (_ways_31_io_resp_always_taken_0),</a>
+<a name="4650"><span class="lineNum">    4650 </span>            :     .io_resp_always_taken_1           (_ways_31_io_resp_always_taken_1),</a>
+<a name="4651"><span class="lineNum">    4651 </span>            :     .io_resp_hit                      (_ways_31_io_resp_hit),</a>
+<a name="4652"><span class="lineNum">    4652 </span>            :     .io_update_req_tag                (io_update_bits_pc[16:1]),</a>
+<a name="4653"><span class="lineNum">    4653 </span>            :     .io_update_hit                    (_ways_31_io_update_hit),</a>
+<a name="4654"><span class="lineNum">    4654 </span>            :     .io_write_valid                   (u_s1_ways_write_valid_31),</a>
+<a name="4655"><span class="lineNum">    4655 </span>            :     .io_write_entry_brSlots_0_offset  (u_s1_ftb_entry_brSlots_0_offset),</a>
+<a name="4656"><span class="lineNum">    4656 </span>            :     .io_write_entry_brSlots_0_lower   (u_s1_ftb_entry_brSlots_0_lower),</a>
+<a name="4657"><span class="lineNum">    4657 </span>            :     .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat),</a>
+<a name="4658"><span class="lineNum">    4658 </span>            :     .io_write_entry_brSlots_0_valid   (u_s1_ftb_entry_brSlots_0_valid),</a>
+<a name="4659"><span class="lineNum">    4659 </span>            :     .io_write_entry_tailSlot_offset   (u_s1_ftb_entry_tailSlot_offset),</a>
+<a name="4660"><span class="lineNum">    4660 </span>            :     .io_write_entry_tailSlot_lower    (u_s1_ftb_entry_tailSlot_lower),</a>
+<a name="4661"><span class="lineNum">    4661 </span>            :     .io_write_entry_tailSlot_tarStat  (u_s1_ftb_entry_tailSlot_tarStat),</a>
+<a name="4662"><span class="lineNum">    4662 </span>            :     .io_write_entry_tailSlot_sharing  (u_s1_ftb_entry_tailSlot_sharing),</a>
+<a name="4663"><span class="lineNum">    4663 </span>            :     .io_write_entry_tailSlot_valid    (u_s1_ftb_entry_tailSlot_valid),</a>
+<a name="4664"><span class="lineNum">    4664 </span>            :     .io_write_entry_pftAddr           (u_s1_ftb_entry_pftAddr),</a>
+<a name="4665"><span class="lineNum">    4665 </span>            :     .io_write_entry_carry             (u_s1_ftb_entry_carry),</a>
+<a name="4666"><span class="lineNum">    4666 </span>            :     .io_write_entry_always_taken_0    (u_s1_ftb_entry_always_taken_0),</a>
+<a name="4667"><span class="lineNum">    4667 </span>            :     .io_write_entry_always_taken_1    (u_s1_ftb_entry_always_taken_1),</a>
+<a name="4668"><span class="lineNum">    4668 </span>            :     .io_write_tag                     (u_s1_tag)</a>
+<a name="4669"><span class="lineNum">    4669 </span>            :   );</a>
+<a name="4670"><span class="lineNum">    4670 </span>            :   assign io_out_s1_pc_0 = s1_pc_dup_0;</a>
+<a name="4671"><span class="lineNum">    4671 </span>            :   assign io_out_s1_pc_1 = s1_pc_dup_1;</a>
+<a name="4672"><span class="lineNum">    4672 </span>            :   assign io_out_s1_pc_2 = s1_pc_dup_2;</a>
+<a name="4673"><span class="lineNum">    4673 </span>            :   assign io_out_s1_pc_3 = s1_pc_dup_3;</a>
+<a name="4674"><span class="lineNum">    4674 </span>            :   assign io_out_s1_full_pred_0_br_taken_mask_0 = _s1_hit_full_pred_T_1102;</a>
+<a name="4675"><span class="lineNum">    4675 </span>            :   assign io_out_s1_full_pred_0_br_taken_mask_1 = _s1_hit_full_pred_T_1165;</a>
+<a name="4676"><span class="lineNum">    4676 </span>            :   assign io_out_s1_full_pred_0_slot_valids_0 = _s1_hit_full_pred_T_976;</a>
+<a name="4677"><span class="lineNum">    4677 </span>            :   assign io_out_s1_full_pred_0_slot_valids_1 = _s1_hit_full_pred_T_1039;</a>
+<a name="4678"><span class="lineNum">    4678 </span>            :   assign io_out_s1_full_pred_0_targets_0 = _s1_hit_full_pred_T_850;</a>
+<a name="4679"><span class="lineNum">    4679 </span>            :   assign io_out_s1_full_pred_0_targets_1 = _s1_hit_full_pred_T_913;</a>
+<a name="4680"><span class="lineNum">    4680 </span>            :   assign io_out_s1_full_pred_0_offsets_0 = _s1_hit_full_pred_T_661;</a>
+<a name="4681"><span class="lineNum">    4681 </span>            :   assign io_out_s1_full_pred_0_offsets_1 = _s1_hit_full_pred_T_724;</a>
+<a name="4682"><span class="lineNum">    4682 </span>            :   assign io_out_s1_full_pred_0_fallThroughAddr = _s1_hit_full_pred_T_598;</a>
+<a name="4683"><span class="lineNum">    4683 </span>            :   assign io_out_s1_full_pred_0_is_br_sharing = _s1_hit_full_pred_T_157;</a>
+<a name="4684"><span class="lineNum">    4684 </span>            :   assign io_out_s1_full_pred_0_hit = io_out_s1_full_pred_3_hit_0;</a>
+<a name="4685"><span class="lineNum">    4685 </span>            :   assign io_out_s1_full_pred_1_br_taken_mask_0 = _s1_hit_full_pred_T_1102;</a>
+<a name="4686"><span class="lineNum">    4686 </span>            :   assign io_out_s1_full_pred_1_br_taken_mask_1 = _s1_hit_full_pred_T_1165;</a>
+<a name="4687"><span class="lineNum">    4687 </span>            :   assign io_out_s1_full_pred_1_slot_valids_0 = _s1_hit_full_pred_T_976;</a>
+<a name="4688"><span class="lineNum">    4688 </span>            :   assign io_out_s1_full_pred_1_slot_valids_1 = _s1_hit_full_pred_T_1039;</a>
+<a name="4689"><span class="lineNum">    4689 </span>            :   assign io_out_s1_full_pred_1_targets_0 = _s1_hit_full_pred_T_850;</a>
+<a name="4690"><span class="lineNum">    4690 </span>            :   assign io_out_s1_full_pred_1_targets_1 = _s1_hit_full_pred_T_913;</a>
+<a name="4691"><span class="lineNum">    4691 </span>            :   assign io_out_s1_full_pred_1_offsets_0 = _s1_hit_full_pred_T_661;</a>
+<a name="4692"><span class="lineNum">    4692 </span>            :   assign io_out_s1_full_pred_1_offsets_1 = _s1_hit_full_pred_T_724;</a>
+<a name="4693"><span class="lineNum">    4693 </span>            :   assign io_out_s1_full_pred_1_fallThroughAddr = _s1_hit_full_pred_T_598;</a>
+<a name="4694"><span class="lineNum">    4694 </span>            :   assign io_out_s1_full_pred_1_is_br_sharing = _s1_hit_full_pred_T_157;</a>
+<a name="4695"><span class="lineNum">    4695 </span>            :   assign io_out_s1_full_pred_1_hit = io_out_s1_full_pred_3_hit_0;</a>
+<a name="4696"><span class="lineNum">    4696 </span>            :   assign io_out_s1_full_pred_2_br_taken_mask_0 = _s1_hit_full_pred_T_1102;</a>
+<a name="4697"><span class="lineNum">    4697 </span>            :   assign io_out_s1_full_pred_2_br_taken_mask_1 = _s1_hit_full_pred_T_1165;</a>
+<a name="4698"><span class="lineNum">    4698 </span>            :   assign io_out_s1_full_pred_2_slot_valids_0 = _s1_hit_full_pred_T_976;</a>
+<a name="4699"><span class="lineNum">    4699 </span>            :   assign io_out_s1_full_pred_2_slot_valids_1 = _s1_hit_full_pred_T_1039;</a>
+<a name="4700"><span class="lineNum">    4700 </span>            :   assign io_out_s1_full_pred_2_targets_0 = _s1_hit_full_pred_T_850;</a>
+<a name="4701"><span class="lineNum">    4701 </span>            :   assign io_out_s1_full_pred_2_targets_1 = _s1_hit_full_pred_T_913;</a>
+<a name="4702"><span class="lineNum">    4702 </span>            :   assign io_out_s1_full_pred_2_offsets_0 = _s1_hit_full_pred_T_661;</a>
+<a name="4703"><span class="lineNum">    4703 </span>            :   assign io_out_s1_full_pred_2_offsets_1 = _s1_hit_full_pred_T_724;</a>
+<a name="4704"><span class="lineNum">    4704 </span>            :   assign io_out_s1_full_pred_2_fallThroughAddr = _s1_hit_full_pred_T_598;</a>
+<a name="4705"><span class="lineNum">    4705 </span>            :   assign io_out_s1_full_pred_2_is_br_sharing = _s1_hit_full_pred_T_157;</a>
+<a name="4706"><span class="lineNum">    4706 </span>            :   assign io_out_s1_full_pred_2_hit = io_out_s1_full_pred_3_hit_0;</a>
+<a name="4707"><span class="lineNum">    4707 </span>            :   assign io_out_s1_full_pred_3_br_taken_mask_0 = _s1_hit_full_pred_T_1102;</a>
+<a name="4708"><span class="lineNum">    4708 </span>            :   assign io_out_s1_full_pred_3_br_taken_mask_1 = _s1_hit_full_pred_T_1165;</a>
+<a name="4709"><span class="lineNum">    4709 </span>            :   assign io_out_s1_full_pred_3_slot_valids_0 = _s1_hit_full_pred_T_976;</a>
+<a name="4710"><span class="lineNum">    4710 </span>            :   assign io_out_s1_full_pred_3_slot_valids_1 = _s1_hit_full_pred_T_1039;</a>
+<a name="4711"><span class="lineNum">    4711 </span>            :   assign io_out_s1_full_pred_3_targets_0 = _s1_hit_full_pred_T_850;</a>
+<a name="4712"><span class="lineNum">    4712 </span>            :   assign io_out_s1_full_pred_3_targets_1 = _s1_hit_full_pred_T_913;</a>
+<a name="4713"><span class="lineNum">    4713 </span>            :   assign io_out_s1_full_pred_3_offsets_0 = _s1_hit_full_pred_T_661;</a>
+<a name="4714"><span class="lineNum">    4714 </span>            :   assign io_out_s1_full_pred_3_offsets_1 = _s1_hit_full_pred_T_724;</a>
+<a name="4715"><span class="lineNum">    4715 </span>            :   assign io_out_s1_full_pred_3_fallThroughAddr = _s1_hit_full_pred_T_598;</a>
+<a name="4716"><span class="lineNum">    4716 </span>            :   assign io_out_s1_full_pred_3_fallThroughErr =</a>
+<a name="4717"><span class="lineNum">    4717 </span>            :     _ways_0_io_resp_hit &amp; s1_possible_full_preds_0_fallThroughErr | _ways_1_io_resp_hit</a>
+<a name="4718"><span class="lineNum">    4718 </span>            :     &amp; s1_possible_full_preds_1_fallThroughErr | _ways_2_io_resp_hit</a>
+<a name="4719"><span class="lineNum">    4719 </span>            :     &amp; s1_possible_full_preds_2_fallThroughErr | _ways_3_io_resp_hit</a>
+<a name="4720"><span class="lineNum">    4720 </span>            :     &amp; s1_possible_full_preds_3_fallThroughErr | _ways_4_io_resp_hit</a>
+<a name="4721"><span class="lineNum">    4721 </span>            :     &amp; s1_possible_full_preds_4_fallThroughErr | _ways_5_io_resp_hit</a>
+<a name="4722"><span class="lineNum">    4722 </span>            :     &amp; s1_possible_full_preds_5_fallThroughErr | _ways_6_io_resp_hit</a>
+<a name="4723"><span class="lineNum">    4723 </span>            :     &amp; s1_possible_full_preds_6_fallThroughErr | _ways_7_io_resp_hit</a>
+<a name="4724"><span class="lineNum">    4724 </span>            :     &amp; s1_possible_full_preds_7_fallThroughErr | _ways_8_io_resp_hit</a>
+<a name="4725"><span class="lineNum">    4725 </span>            :     &amp; s1_possible_full_preds_8_fallThroughErr | _ways_9_io_resp_hit</a>
+<a name="4726"><span class="lineNum">    4726 </span>            :     &amp; s1_possible_full_preds_9_fallThroughErr | _ways_10_io_resp_hit</a>
+<a name="4727"><span class="lineNum">    4727 </span>            :     &amp; s1_possible_full_preds_10_fallThroughErr | _ways_11_io_resp_hit</a>
+<a name="4728"><span class="lineNum">    4728 </span>            :     &amp; s1_possible_full_preds_11_fallThroughErr | _ways_12_io_resp_hit</a>
+<a name="4729"><span class="lineNum">    4729 </span>            :     &amp; s1_possible_full_preds_12_fallThroughErr | _ways_13_io_resp_hit</a>
+<a name="4730"><span class="lineNum">    4730 </span>            :     &amp; s1_possible_full_preds_13_fallThroughErr | _ways_14_io_resp_hit</a>
+<a name="4731"><span class="lineNum">    4731 </span>            :     &amp; s1_possible_full_preds_14_fallThroughErr | _ways_15_io_resp_hit</a>
+<a name="4732"><span class="lineNum">    4732 </span>            :     &amp; s1_possible_full_preds_15_fallThroughErr | _ways_16_io_resp_hit</a>
+<a name="4733"><span class="lineNum">    4733 </span>            :     &amp; s1_possible_full_preds_16_fallThroughErr | _ways_17_io_resp_hit</a>
+<a name="4734"><span class="lineNum">    4734 </span>            :     &amp; s1_possible_full_preds_17_fallThroughErr | _ways_18_io_resp_hit</a>
+<a name="4735"><span class="lineNum">    4735 </span>            :     &amp; s1_possible_full_preds_18_fallThroughErr | _ways_19_io_resp_hit</a>
+<a name="4736"><span class="lineNum">    4736 </span>            :     &amp; s1_possible_full_preds_19_fallThroughErr | _ways_20_io_resp_hit</a>
+<a name="4737"><span class="lineNum">    4737 </span>            :     &amp; s1_possible_full_preds_20_fallThroughErr | _ways_21_io_resp_hit</a>
+<a name="4738"><span class="lineNum">    4738 </span>            :     &amp; s1_possible_full_preds_21_fallThroughErr | _ways_22_io_resp_hit</a>
+<a name="4739"><span class="lineNum">    4739 </span>            :     &amp; s1_possible_full_preds_22_fallThroughErr | _ways_23_io_resp_hit</a>
+<a name="4740"><span class="lineNum">    4740 </span>            :     &amp; s1_possible_full_preds_23_fallThroughErr | _ways_24_io_resp_hit</a>
+<a name="4741"><span class="lineNum">    4741 </span>            :     &amp; s1_possible_full_preds_24_fallThroughErr | _ways_25_io_resp_hit</a>
+<a name="4742"><span class="lineNum">    4742 </span>            :     &amp; s1_possible_full_preds_25_fallThroughErr | _ways_26_io_resp_hit</a>
+<a name="4743"><span class="lineNum">    4743 </span>            :     &amp; s1_possible_full_preds_26_fallThroughErr | _ways_27_io_resp_hit</a>
+<a name="4744"><span class="lineNum">    4744 </span>            :     &amp; s1_possible_full_preds_27_fallThroughErr | _ways_28_io_resp_hit</a>
+<a name="4745"><span class="lineNum">    4745 </span>            :     &amp; s1_possible_full_preds_28_fallThroughErr | _ways_29_io_resp_hit</a>
+<a name="4746"><span class="lineNum">    4746 </span>            :     &amp; s1_possible_full_preds_29_fallThroughErr | _ways_30_io_resp_hit</a>
+<a name="4747"><span class="lineNum">    4747 </span>            :     &amp; s1_possible_full_preds_30_fallThroughErr | _ways_31_io_resp_hit</a>
+<a name="4748"><span class="lineNum">    4748 </span>            :     &amp; s1_possible_full_preds_31_fallThroughErr;</a>
+<a name="4749"><span class="lineNum">    4749 </span>            :   assign io_out_s1_full_pred_3_is_br_sharing = _s1_hit_full_pred_T_157;</a>
+<a name="4750"><span class="lineNum">    4750 </span>            :   assign io_out_s1_full_pred_3_hit = io_out_s1_full_pred_3_hit_0;</a>
+<a name="4751"><span class="lineNum">    4751 </span>            :   assign io_out_last_stage_meta = {217'h0, resp_meta_pred_way_r_1, resp_meta_hit_r_1};</a>
+<a name="4752"><span class="lineNum">    4752 </span>            :   assign io_perf_0_value = {5'h0, io_perf_0_value_REG_1};</a>
+<a name="4753"><span class="lineNum">    4753 </span>            :   assign io_perf_1_value = {5'h0, io_perf_1_value_REG_1};</a>
+<a name="4754"><span class="lineNum">    4754 </span>            : endmodule</a>
+<a name="4755"><span class="lineNum">    4755 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FauFTBWay.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FauFTBWay.sv.func-sort-c.html
new file mode 100644
index 0000000..4df977a
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FauFTBWay.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/FauFTBWay.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - FauFTBWay.sv<span style="font-size: 80%;"> (<a href="FauFTBWay.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">72</td>
+            <td class="headerCovTableEntry">72</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="FauFTBWay.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FauFTBWay.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FauFTBWay.sv.func.html
new file mode 100644
index 0000000..edc118b
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FauFTBWay.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/FauFTBWay.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - FauFTBWay.sv<span style="font-size: 80%;"> (<a href="FauFTBWay.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">72</td>
+            <td class="headerCovTableEntry">72</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="FauFTBWay.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FauFTBWay.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FauFTBWay.sv.gcov.html
new file mode 100644
index 0000000..8690024
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FauFTBWay.sv.gcov.html
@@ -0,0 +1,263 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/FauFTBWay.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - FauFTBWay.sv<span style="font-size: 80%;"> (source / <a href="FauFTBWay.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">72</td>
+            <td class="headerCovTableEntry">72</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : module FauFTBWay(</a>
+<a name="59"><span class="lineNum">      59 </span><span class="lineCov">     127786 :   input         clock,</span></a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">         62 :   input         reset,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">       8872 :   input  [15:0] io_req_tag,</span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">       2268 :   output [3:0]  io_resp_brSlots_0_offset,</span></a>
+<a name="63"><span class="lineNum">      63 </span><span class="lineCov">       6550 :   output [11:0] io_resp_brSlots_0_lower,</span></a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">       1131 :   output [1:0]  io_resp_brSlots_0_tarStat,</span></a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">        544 :   output        io_resp_brSlots_0_valid,</span></a>
+<a name="66"><span class="lineNum">      66 </span><span class="lineCov">       2222 :   output [3:0]  io_resp_tailSlot_offset,</span></a>
+<a name="67"><span class="lineNum">      67 </span><span class="lineCov">      10939 :   output [19:0] io_resp_tailSlot_lower,</span></a>
+<a name="68"><span class="lineNum">      68 </span><span class="lineCov">       1094 :   output [1:0]  io_resp_tailSlot_tarStat,</span></a>
+<a name="69"><span class="lineNum">      69 </span><span class="lineCov">        551 :   output        io_resp_tailSlot_sharing,</span></a>
+<a name="70"><span class="lineNum">      70 </span><span class="lineCov">        567 :   output        io_resp_tailSlot_valid,</span></a>
+<a name="71"><span class="lineNum">      71 </span><span class="lineCov">       2286 :   output [3:0]  io_resp_pftAddr,</span></a>
+<a name="72"><span class="lineNum">      72 </span><span class="lineCov">        558 :   output        io_resp_carry,</span></a>
+<a name="73"><span class="lineNum">      73 </span><span class="lineCov">        564 :   output        io_resp_always_taken_0,</span></a>
+<a name="74"><span class="lineNum">      74 </span><span class="lineCov">        543 :   output        io_resp_always_taken_1,</span></a>
+<a name="75"><span class="lineNum">      75 </span><span class="lineCov">        510 :   output        io_resp_hit,</span></a>
+<a name="76"><span class="lineNum">      76 </span><span class="lineCov">        454 :   input  [15:0] io_update_req_tag,</span></a>
+<a name="77"><span class="lineNum">      77 </span><span class="lineCov">        527 :   output        io_update_hit,</span></a>
+<a name="78"><span class="lineNum">      78 </span><span class="lineCov">         12 :   input         io_write_valid,</span></a>
+<a name="79"><span class="lineNum">      79 </span><span class="lineCov">        127 :   input  [3:0]  io_write_entry_brSlots_0_offset,</span></a>
+<a name="80"><span class="lineNum">      80 </span><span class="lineCov">        345 :   input  [11:0] io_write_entry_brSlots_0_lower,</span></a>
+<a name="81"><span class="lineNum">      81 </span><span class="lineCov">         57 :   input  [1:0]  io_write_entry_brSlots_0_tarStat,</span></a>
+<a name="82"><span class="lineNum">      82 </span><span class="lineCov">         43 :   input         io_write_entry_brSlots_0_valid,</span></a>
+<a name="83"><span class="lineNum">      83 </span><span class="lineCov">        127 :   input  [3:0]  io_write_entry_tailSlot_offset,</span></a>
+<a name="84"><span class="lineNum">      84 </span><span class="lineCov">        573 :   input  [19:0] io_write_entry_tailSlot_lower,</span></a>
+<a name="85"><span class="lineNum">      85 </span><span class="lineCov">         70 :   input  [1:0]  io_write_entry_tailSlot_tarStat,</span></a>
+<a name="86"><span class="lineNum">      86 </span><span class="lineCov">         33 :   input         io_write_entry_tailSlot_sharing,</span></a>
+<a name="87"><span class="lineNum">      87 </span><span class="lineCov">         29 :   input         io_write_entry_tailSlot_valid,</span></a>
+<a name="88"><span class="lineNum">      88 </span><span class="lineCov">        135 :   input  [3:0]  io_write_entry_pftAddr,</span></a>
+<a name="89"><span class="lineNum">      89 </span><span class="lineCov">         30 :   input         io_write_entry_carry,</span></a>
+<a name="90"><span class="lineNum">      90 </span><span class="lineCov">         26 :   input         io_write_entry_always_taken_0,</span></a>
+<a name="91"><span class="lineNum">      91 </span><span class="lineCov">         37 :   input         io_write_entry_always_taken_1,</span></a>
+<a name="92"><span class="lineNum">      92 </span><span class="lineCov">        435 :   input  [15:0] io_write_tag</span></a>
+<a name="93"><span class="lineNum">      93 </span>            : );</a>
+<a name="94"><span class="lineNum">      94 </span>            : </a>
+<a name="95"><span class="lineNum">      95 </span><span class="lineCov">       2268 :   reg [3:0]  data_brSlots_0_offset;</span></a>
+<a name="96"><span class="lineNum">      96 </span><span class="lineCov">       6550 :   reg [11:0] data_brSlots_0_lower;</span></a>
+<a name="97"><span class="lineNum">      97 </span><span class="lineCov">       1131 :   reg [1:0]  data_brSlots_0_tarStat;</span></a>
+<a name="98"><span class="lineNum">      98 </span><span class="lineCov">        544 :   reg        data_brSlots_0_valid;</span></a>
+<a name="99"><span class="lineNum">      99 </span><span class="lineCov">       2222 :   reg [3:0]  data_tailSlot_offset;</span></a>
+<a name="100"><span class="lineNum">     100 </span><span class="lineCov">      10939 :   reg [19:0] data_tailSlot_lower;</span></a>
+<a name="101"><span class="lineNum">     101 </span><span class="lineCov">       1094 :   reg [1:0]  data_tailSlot_tarStat;</span></a>
+<a name="102"><span class="lineNum">     102 </span><span class="lineCov">        551 :   reg        data_tailSlot_sharing;</span></a>
+<a name="103"><span class="lineNum">     103 </span><span class="lineCov">        567 :   reg        data_tailSlot_valid;</span></a>
+<a name="104"><span class="lineNum">     104 </span><span class="lineCov">       2286 :   reg [3:0]  data_pftAddr;</span></a>
+<a name="105"><span class="lineNum">     105 </span><span class="lineCov">        558 :   reg        data_carry;</span></a>
+<a name="106"><span class="lineNum">     106 </span><span class="lineCov">        564 :   reg        data_always_taken_0;</span></a>
+<a name="107"><span class="lineNum">     107 </span><span class="lineCov">        543 :   reg        data_always_taken_1;</span></a>
+<a name="108"><span class="lineNum">     108 </span><span class="lineCov">       8837 :   reg [15:0] tag;</span></a>
+<a name="109"><span class="lineNum">     109 </span><span class="lineCov">        831 :   reg        valid;</span></a>
+<a name="110"><span class="lineNum">     110 </span><span class="lineCov">    4086208 :   always @(posedge clock) begin</span></a>
+<a name="111"><span class="lineNum">     111 </span><span class="lineCov">        380 :     if (io_write_valid) begin</span></a>
+<a name="112"><span class="lineNum">     112 </span><span class="lineCov">        190 :       data_brSlots_0_offset &lt;= io_write_entry_brSlots_0_offset;</span></a>
+<a name="113"><span class="lineNum">     113 </span><span class="lineCov">        190 :       data_brSlots_0_lower &lt;= io_write_entry_brSlots_0_lower;</span></a>
+<a name="114"><span class="lineNum">     114 </span><span class="lineCov">        190 :       data_brSlots_0_tarStat &lt;= io_write_entry_brSlots_0_tarStat;</span></a>
+<a name="115"><span class="lineNum">     115 </span><span class="lineCov">        190 :       data_brSlots_0_valid &lt;= io_write_entry_brSlots_0_valid;</span></a>
+<a name="116"><span class="lineNum">     116 </span><span class="lineCov">        190 :       data_tailSlot_offset &lt;= io_write_entry_tailSlot_offset;</span></a>
+<a name="117"><span class="lineNum">     117 </span><span class="lineCov">        190 :       data_tailSlot_lower &lt;= io_write_entry_tailSlot_lower;</span></a>
+<a name="118"><span class="lineNum">     118 </span><span class="lineCov">        190 :       data_tailSlot_tarStat &lt;= io_write_entry_tailSlot_tarStat;</span></a>
+<a name="119"><span class="lineNum">     119 </span><span class="lineCov">        190 :       data_tailSlot_sharing &lt;= io_write_entry_tailSlot_sharing;</span></a>
+<a name="120"><span class="lineNum">     120 </span><span class="lineCov">        190 :       data_tailSlot_valid &lt;= io_write_entry_tailSlot_valid;</span></a>
+<a name="121"><span class="lineNum">     121 </span><span class="lineCov">        190 :       data_pftAddr &lt;= io_write_entry_pftAddr;</span></a>
+<a name="122"><span class="lineNum">     122 </span><span class="lineCov">        190 :       data_carry &lt;= io_write_entry_carry;</span></a>
+<a name="123"><span class="lineNum">     123 </span><span class="lineCov">        190 :       data_always_taken_0 &lt;= io_write_entry_always_taken_0;</span></a>
+<a name="124"><span class="lineNum">     124 </span><span class="lineCov">        190 :       data_always_taken_1 &lt;= io_write_entry_always_taken_1;</span></a>
+<a name="125"><span class="lineNum">     125 </span><span class="lineCov">        190 :       tag &lt;= io_write_tag;</span></a>
+<a name="126"><span class="lineNum">     126 </span>            :     end</a>
+<a name="127"><span class="lineNum">     127 </span>            :   end // always @(posedge)</a>
+<a name="128"><span class="lineNum">     128 </span><span class="lineCov">    4087360 :   always @(posedge clock or posedge reset) begin</span></a>
+<a name="129"><span class="lineNum">     129 </span><span class="lineCov">       8704 :     if (reset)</span></a>
+<a name="130"><span class="lineNum">     130 </span><span class="lineCov">       4352 :       valid &lt;= 1'h0;</span></a>
+<a name="131"><span class="lineNum">     131 </span>            :     else</a>
+<a name="132"><span class="lineNum">     132 </span><span class="lineCov">    2039328 :       valid &lt;= io_write_valid &amp; ~valid | valid;</span></a>
+<a name="133"><span class="lineNum">     133 </span>            :   end // always @(posedge, posedge)</a>
+<a name="134"><span class="lineNum">     134 </span>            :   `ifdef ENABLE_INITIAL_REG_</a>
+<a name="135"><span class="lineNum">     135 </span>            :     `ifdef FIRRTL_BEFORE_INITIAL</a>
+<a name="136"><span class="lineNum">     136 </span>            :       `FIRRTL_BEFORE_INITIAL</a>
+<a name="137"><span class="lineNum">     137 </span>            :     `endif // FIRRTL_BEFORE_INITIAL</a>
+<a name="138"><span class="lineNum">     138 </span>            :     logic [31:0] _RANDOM[0:2];</a>
+<a name="139"><span class="lineNum">     139 </span><span class="lineCov">       1856 :     initial begin</span></a>
+<a name="140"><span class="lineNum">     140 </span>            :       `ifdef INIT_RANDOM_PROLOG_</a>
+<a name="141"><span class="lineNum">     141 </span>            :         `INIT_RANDOM_PROLOG_</a>
+<a name="142"><span class="lineNum">     142 </span>            :       `endif // INIT_RANDOM_PROLOG_</a>
+<a name="143"><span class="lineNum">     143 </span>            :       `ifdef RANDOMIZE_REG_INIT</a>
+<a name="144"><span class="lineNum">     144 </span>            :         for (logic [1:0] i = 2'h0; i &lt; 2'h3; i += 2'h1) begin</a>
+<a name="145"><span class="lineNum">     145 </span>            :           _RANDOM[i] = `RANDOM;</a>
+<a name="146"><span class="lineNum">     146 </span>            :         end</a>
+<a name="147"><span class="lineNum">     147 </span>            :         data_brSlots_0_offset = _RANDOM[2'h0][4:1];</a>
+<a name="148"><span class="lineNum">     148 </span>            :         data_brSlots_0_lower = _RANDOM[2'h0][16:5];</a>
+<a name="149"><span class="lineNum">     149 </span>            :         data_brSlots_0_tarStat = _RANDOM[2'h0][18:17];</a>
+<a name="150"><span class="lineNum">     150 </span>            :         data_brSlots_0_valid = _RANDOM[2'h0][20];</a>
+<a name="151"><span class="lineNum">     151 </span>            :         data_tailSlot_offset = _RANDOM[2'h0][24:21];</a>
+<a name="152"><span class="lineNum">     152 </span>            :         data_tailSlot_lower = {_RANDOM[2'h0][31:25], _RANDOM[2'h1][12:0]};</a>
+<a name="153"><span class="lineNum">     153 </span>            :         data_tailSlot_tarStat = _RANDOM[2'h1][14:13];</a>
+<a name="154"><span class="lineNum">     154 </span>            :         data_tailSlot_sharing = _RANDOM[2'h1][15];</a>
+<a name="155"><span class="lineNum">     155 </span>            :         data_tailSlot_valid = _RANDOM[2'h1][16];</a>
+<a name="156"><span class="lineNum">     156 </span>            :         data_pftAddr = _RANDOM[2'h1][20:17];</a>
+<a name="157"><span class="lineNum">     157 </span>            :         data_carry = _RANDOM[2'h1][21];</a>
+<a name="158"><span class="lineNum">     158 </span>            :         data_always_taken_0 = _RANDOM[2'h1][26];</a>
+<a name="159"><span class="lineNum">     159 </span>            :         data_always_taken_1 = _RANDOM[2'h1][27];</a>
+<a name="160"><span class="lineNum">     160 </span>            :         tag = {_RANDOM[2'h1][31:28], _RANDOM[2'h2][11:0]};</a>
+<a name="161"><span class="lineNum">     161 </span>            :         valid = _RANDOM[2'h2][12];</a>
+<a name="162"><span class="lineNum">     162 </span>            :       `endif // RANDOMIZE_REG_INIT</a>
+<a name="163"><span class="lineNum">     163 </span><span class="lineCov">        544 :       if (reset)</span></a>
+<a name="164"><span class="lineNum">     164 </span><span class="lineCov">        384 :         valid = 1'h0;</span></a>
+<a name="165"><span class="lineNum">     165 </span>            :     end // initial</a>
+<a name="166"><span class="lineNum">     166 </span>            :     `ifdef FIRRTL_AFTER_INITIAL</a>
+<a name="167"><span class="lineNum">     167 </span>            :       `FIRRTL_AFTER_INITIAL</a>
+<a name="168"><span class="lineNum">     168 </span>            :     `endif // FIRRTL_AFTER_INITIAL</a>
+<a name="169"><span class="lineNum">     169 </span>            :   `endif // ENABLE_INITIAL_REG_</a>
+<a name="170"><span class="lineNum">     170 </span>            :   assign io_resp_brSlots_0_offset = data_brSlots_0_offset;</a>
+<a name="171"><span class="lineNum">     171 </span>            :   assign io_resp_brSlots_0_lower = data_brSlots_0_lower;</a>
+<a name="172"><span class="lineNum">     172 </span>            :   assign io_resp_brSlots_0_tarStat = data_brSlots_0_tarStat;</a>
+<a name="173"><span class="lineNum">     173 </span>            :   assign io_resp_brSlots_0_valid = data_brSlots_0_valid;</a>
+<a name="174"><span class="lineNum">     174 </span>            :   assign io_resp_tailSlot_offset = data_tailSlot_offset;</a>
+<a name="175"><span class="lineNum">     175 </span>            :   assign io_resp_tailSlot_lower = data_tailSlot_lower;</a>
+<a name="176"><span class="lineNum">     176 </span>            :   assign io_resp_tailSlot_tarStat = data_tailSlot_tarStat;</a>
+<a name="177"><span class="lineNum">     177 </span>            :   assign io_resp_tailSlot_sharing = data_tailSlot_sharing;</a>
+<a name="178"><span class="lineNum">     178 </span>            :   assign io_resp_tailSlot_valid = data_tailSlot_valid;</a>
+<a name="179"><span class="lineNum">     179 </span>            :   assign io_resp_pftAddr = data_pftAddr;</a>
+<a name="180"><span class="lineNum">     180 </span>            :   assign io_resp_carry = data_carry;</a>
+<a name="181"><span class="lineNum">     181 </span>            :   assign io_resp_always_taken_0 = data_always_taken_0;</a>
+<a name="182"><span class="lineNum">     182 </span>            :   assign io_resp_always_taken_1 = data_always_taken_1;</a>
+<a name="183"><span class="lineNum">     183 </span>            :   assign io_resp_hit = tag == io_req_tag &amp; valid;</a>
+<a name="184"><span class="lineNum">     184 </span>            :   assign io_update_hit =</a>
+<a name="185"><span class="lineNum">     185 </span>            :     tag == io_update_req_tag &amp; valid | io_write_tag == io_update_req_tag &amp; io_write_valid;</a>
+<a name="186"><span class="lineNum">     186 </span>            : endmodule</a>
+<a name="187"><span class="lineNum">     187 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/Folded1WDataModuleTemplate.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/Folded1WDataModuleTemplate.sv.func-sort-c.html
new file mode 100644
index 0000000..40517c6
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/Folded1WDataModuleTemplate.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/Folded1WDataModuleTemplate.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - Folded1WDataModuleTemplate.sv<span style="font-size: 80%;"> (<a href="Folded1WDataModuleTemplate.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">27</td>
+            <td class="headerCovTableEntry">27</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="Folded1WDataModuleTemplate.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/Folded1WDataModuleTemplate.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/Folded1WDataModuleTemplate.sv.func.html
new file mode 100644
index 0000000..8bd8e9d
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/Folded1WDataModuleTemplate.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/Folded1WDataModuleTemplate.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - Folded1WDataModuleTemplate.sv<span style="font-size: 80%;"> (<a href="Folded1WDataModuleTemplate.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">27</td>
+            <td class="headerCovTableEntry">27</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="Folded1WDataModuleTemplate.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
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+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/Folded1WDataModuleTemplate.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/Folded1WDataModuleTemplate.sv.gcov.html
new file mode 100644
index 0000000..9659bac
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/Folded1WDataModuleTemplate.sv.gcov.html
@@ -0,0 +1,222 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/Folded1WDataModuleTemplate.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - Folded1WDataModuleTemplate.sv<span style="font-size: 80%;"> (source / <a href="Folded1WDataModuleTemplate.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">27</td>
+            <td class="headerCovTableEntry">27</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : module Folded1WDataModuleTemplate(</a>
+<a name="59"><span class="lineNum">      59 </span><span class="lineCov">     127786 :   input        clock,</span></a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">         62 :   input        reset,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">         73 :   input        io_ren_0,</span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">      24675 :   input  [7:0] io_raddr_0,</span></a>
+<a name="63"><span class="lineNum">      63 </span><span class="lineCov">        127 :   output       io_rdata_0,</span></a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">         11 :   input        io_wen,</span></a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">        105 :   input  [7:0] io_waddr,</span></a>
+<a name="66"><span class="lineNum">      66 </span><span class="lineCov">         14 :   input        io_wdata,</span></a>
+<a name="67"><span class="lineNum">      67 </span><span class="lineCov">         33 :   input        io_resetEn</span></a>
+<a name="68"><span class="lineNum">      68 </span>            : );</a>
+<a name="69"><span class="lineNum">      69 </span>            : </a>
+<a name="70"><span class="lineNum">      70 </span>            :   wire [15:0] _data_ext_R0_data;</a>
+<a name="71"><span class="lineNum">      71 </span><span class="lineCov">        113 :   reg         doing_reset;</span></a>
+<a name="72"><span class="lineNum">      72 </span><span class="lineCov">       2019 :   reg  [3:0]  resetRow;</span></a>
+<a name="73"><span class="lineNum">      73 </span><span class="lineCov">      16031 :   reg  [7:0]  raddr_0;</span></a>
+<a name="74"><span class="lineNum">      74 </span>            :   wire [15:0] _GEN =</a>
+<a name="75"><span class="lineNum">      75 </span>            :     {{_data_ext_R0_data[15]},</a>
+<a name="76"><span class="lineNum">      76 </span>            :      {_data_ext_R0_data[14]},</a>
+<a name="77"><span class="lineNum">      77 </span>            :      {_data_ext_R0_data[13]},</a>
+<a name="78"><span class="lineNum">      78 </span>            :      {_data_ext_R0_data[12]},</a>
+<a name="79"><span class="lineNum">      79 </span>            :      {_data_ext_R0_data[11]},</a>
+<a name="80"><span class="lineNum">      80 </span>            :      {_data_ext_R0_data[10]},</a>
+<a name="81"><span class="lineNum">      81 </span>            :      {_data_ext_R0_data[9]},</a>
+<a name="82"><span class="lineNum">      82 </span>            :      {_data_ext_R0_data[8]},</a>
+<a name="83"><span class="lineNum">      83 </span>            :      {_data_ext_R0_data[7]},</a>
+<a name="84"><span class="lineNum">      84 </span>            :      {_data_ext_R0_data[6]},</a>
+<a name="85"><span class="lineNum">      85 </span>            :      {_data_ext_R0_data[5]},</a>
+<a name="86"><span class="lineNum">      86 </span>            :      {_data_ext_R0_data[4]},</a>
+<a name="87"><span class="lineNum">      87 </span>            :      {_data_ext_R0_data[3]},</a>
+<a name="88"><span class="lineNum">      88 </span>            :      {_data_ext_R0_data[2]},</a>
+<a name="89"><span class="lineNum">      89 </span>            :      {_data_ext_R0_data[1]},</a>
+<a name="90"><span class="lineNum">      90 </span>            :      {_data_ext_R0_data[0]}};</a>
+<a name="91"><span class="lineNum">      91 </span><span class="lineCov">     255460 :   always @(posedge clock or posedge reset) begin</span></a>
+<a name="92"><span class="lineNum">      92 </span><span class="lineCov">        544 :     if (reset) begin</span></a>
+<a name="93"><span class="lineNum">      93 </span><span class="lineCov">        272 :       doing_reset &lt;= 1'h1;</span></a>
+<a name="94"><span class="lineNum">      94 </span><span class="lineCov">        272 :       resetRow &lt;= 4'h0;</span></a>
+<a name="95"><span class="lineNum">      95 </span>            :     end</a>
+<a name="96"><span class="lineNum">      96 </span><span class="lineCov">     127458 :     else begin</span></a>
+<a name="97"><span class="lineNum">      97 </span><span class="lineCov">     127458 :       doing_reset &lt;= resetRow != 4'hF &amp; (io_resetEn | doing_reset);</span></a>
+<a name="98"><span class="lineNum">      98 </span><span class="lineCov">       1956 :       if (doing_reset)</span></a>
+<a name="99"><span class="lineNum">      99 </span><span class="lineCov">        978 :         resetRow &lt;= 4'(resetRow + 4'h1);</span></a>
+<a name="100"><span class="lineNum">     100 </span>            :     end</a>
+<a name="101"><span class="lineNum">     101 </span>            :   end // always @(posedge, posedge)</a>
+<a name="102"><span class="lineNum">     102 </span><span class="lineCov">     255388 :   always @(posedge clock) begin</span></a>
+<a name="103"><span class="lineNum">     103 </span><span class="lineCov">      16700 :     if (io_ren_0)</span></a>
+<a name="104"><span class="lineNum">     104 </span><span class="lineCov">       8350 :       raddr_0 &lt;= io_raddr_0;</span></a>
+<a name="105"><span class="lineNum">     105 </span>            :   end // always @(posedge)</a>
+<a name="106"><span class="lineNum">     106 </span>            :   `ifdef ENABLE_INITIAL_REG_</a>
+<a name="107"><span class="lineNum">     107 </span>            :     `ifdef FIRRTL_BEFORE_INITIAL</a>
+<a name="108"><span class="lineNum">     108 </span>            :       `FIRRTL_BEFORE_INITIAL</a>
+<a name="109"><span class="lineNum">     109 </span>            :     `endif // FIRRTL_BEFORE_INITIAL</a>
+<a name="110"><span class="lineNum">     110 </span>            :     logic [31:0] _RANDOM[0:0];</a>
+<a name="111"><span class="lineNum">     111 </span><span class="lineCov">        116 :     initial begin</span></a>
+<a name="112"><span class="lineNum">     112 </span>            :       `ifdef INIT_RANDOM_PROLOG_</a>
+<a name="113"><span class="lineNum">     113 </span>            :         `INIT_RANDOM_PROLOG_</a>
+<a name="114"><span class="lineNum">     114 </span>            :       `endif // INIT_RANDOM_PROLOG_</a>
+<a name="115"><span class="lineNum">     115 </span>            :       `ifdef RANDOMIZE_REG_INIT</a>
+<a name="116"><span class="lineNum">     116 </span>            :         _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;</a>
+<a name="117"><span class="lineNum">     117 </span>            :         doing_reset = _RANDOM[/*Zero width*/ 1'b0][0];</a>
+<a name="118"><span class="lineNum">     118 </span>            :         resetRow = _RANDOM[/*Zero width*/ 1'b0][4:1];</a>
+<a name="119"><span class="lineNum">     119 </span>            :         raddr_0 = _RANDOM[/*Zero width*/ 1'b0][12:5];</a>
+<a name="120"><span class="lineNum">     120 </span>            :       `endif // RANDOMIZE_REG_INIT</a>
+<a name="121"><span class="lineNum">     121 </span><span class="lineCov">         34 :       if (reset) begin</span></a>
+<a name="122"><span class="lineNum">     122 </span><span class="lineCov">         24 :         doing_reset = 1'h1;</span></a>
+<a name="123"><span class="lineNum">     123 </span><span class="lineCov">         24 :         resetRow = 4'h0;</span></a>
+<a name="124"><span class="lineNum">     124 </span>            :       end</a>
+<a name="125"><span class="lineNum">     125 </span>            :     end // initial</a>
+<a name="126"><span class="lineNum">     126 </span>            :     `ifdef FIRRTL_AFTER_INITIAL</a>
+<a name="127"><span class="lineNum">     127 </span>            :       `FIRRTL_AFTER_INITIAL</a>
+<a name="128"><span class="lineNum">     128 </span>            :     `endif // FIRRTL_AFTER_INITIAL</a>
+<a name="129"><span class="lineNum">     129 </span>            :   `endif // ENABLE_INITIAL_REG_</a>
+<a name="130"><span class="lineNum">     130 </span>            :   data_16x16 data_ext (</a>
+<a name="131"><span class="lineNum">     131 </span>            :     .R0_addr (raddr_0[7:4]),</a>
+<a name="132"><span class="lineNum">     132 </span>            :     .R0_en   (1'h1),</a>
+<a name="133"><span class="lineNum">     133 </span>            :     .R0_clk  (clock),</a>
+<a name="134"><span class="lineNum">     134 </span>            :     .R0_data (_data_ext_R0_data),</a>
+<a name="135"><span class="lineNum">     135 </span>            :     .W0_addr (io_waddr[7:4]),</a>
+<a name="136"><span class="lineNum">     136 </span>            :     .W0_en   (~doing_reset &amp; io_wen),</a>
+<a name="137"><span class="lineNum">     137 </span>            :     .W0_clk  (clock),</a>
+<a name="138"><span class="lineNum">     138 </span>            :     .W0_data ({16{io_wdata}}),</a>
+<a name="139"><span class="lineNum">     139 </span>            :     .W1_addr (resetRow),</a>
+<a name="140"><span class="lineNum">     140 </span>            :     .W1_en   (doing_reset),</a>
+<a name="141"><span class="lineNum">     141 </span>            :     .W1_clk  (clock),</a>
+<a name="142"><span class="lineNum">     142 </span>            :     .W1_data (16'h0)</a>
+<a name="143"><span class="lineNum">     143 </span>            :   );</a>
+<a name="144"><span class="lineNum">     144 </span>            :   assign io_rdata_0 = ~doing_reset &amp; _GEN[raddr_0[3:0]];</a>
+<a name="145"><span class="lineNum">     145 </span>            : endmodule</a>
+<a name="146"><span class="lineNum">     146 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/Folded1WDataModuleTemplate_2.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/Folded1WDataModuleTemplate_2.sv.func-sort-c.html
new file mode 100644
index 0000000..c7fa68a
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/Folded1WDataModuleTemplate_2.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/Folded1WDataModuleTemplate_2.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - Folded1WDataModuleTemplate_2.sv<span style="font-size: 80%;"> (<a href="Folded1WDataModuleTemplate_2.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">27</td>
+            <td class="headerCovTableEntry">27</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="Folded1WDataModuleTemplate_2.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/Folded1WDataModuleTemplate_2.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/Folded1WDataModuleTemplate_2.sv.func.html
new file mode 100644
index 0000000..957a621
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/Folded1WDataModuleTemplate_2.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/Folded1WDataModuleTemplate_2.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - Folded1WDataModuleTemplate_2.sv<span style="font-size: 80%;"> (<a href="Folded1WDataModuleTemplate_2.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">27</td>
+            <td class="headerCovTableEntry">27</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="Folded1WDataModuleTemplate_2.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/Folded1WDataModuleTemplate_2.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/Folded1WDataModuleTemplate_2.sv.gcov.html
new file mode 100644
index 0000000..a790657
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/Folded1WDataModuleTemplate_2.sv.gcov.html
@@ -0,0 +1,222 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/Folded1WDataModuleTemplate_2.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - Folded1WDataModuleTemplate_2.sv<span style="font-size: 80%;"> (source / <a href="Folded1WDataModuleTemplate_2.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">27</td>
+            <td class="headerCovTableEntry">27</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : module Folded1WDataModuleTemplate_2(</a>
+<a name="59"><span class="lineNum">      59 </span><span class="lineCov">     127786 :   input        clock,</span></a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">         62 :   input        reset,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">         73 :   input        io_ren_0,</span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">       8597 :   input  [8:0] io_raddr_0,</span></a>
+<a name="63"><span class="lineNum">      63 </span><span class="lineCov">         36 :   output       io_rdata_0,</span></a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">         17 :   input        io_wen,</span></a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">        125 :   input  [8:0] io_waddr,</span></a>
+<a name="66"><span class="lineNum">      66 </span><span class="lineCov">         20 :   input        io_wdata,</span></a>
+<a name="67"><span class="lineNum">      67 </span><span class="lineCov">         27 :   input        io_resetEn</span></a>
+<a name="68"><span class="lineNum">      68 </span>            : );</a>
+<a name="69"><span class="lineNum">      69 </span>            : </a>
+<a name="70"><span class="lineNum">      70 </span>            :   wire [15:0] _data_ext_R0_data;</a>
+<a name="71"><span class="lineNum">      71 </span><span class="lineCov">        176 :   reg         doing_reset;</span></a>
+<a name="72"><span class="lineNum">      72 </span><span class="lineCov">       5949 :   reg  [4:0]  resetRow;</span></a>
+<a name="73"><span class="lineNum">      73 </span><span class="lineCov">      24862 :   reg  [8:0]  raddr_0;</span></a>
+<a name="74"><span class="lineNum">      74 </span>            :   wire [15:0] _GEN =</a>
+<a name="75"><span class="lineNum">      75 </span>            :     {{_data_ext_R0_data[15]},</a>
+<a name="76"><span class="lineNum">      76 </span>            :      {_data_ext_R0_data[14]},</a>
+<a name="77"><span class="lineNum">      77 </span>            :      {_data_ext_R0_data[13]},</a>
+<a name="78"><span class="lineNum">      78 </span>            :      {_data_ext_R0_data[12]},</a>
+<a name="79"><span class="lineNum">      79 </span>            :      {_data_ext_R0_data[11]},</a>
+<a name="80"><span class="lineNum">      80 </span>            :      {_data_ext_R0_data[10]},</a>
+<a name="81"><span class="lineNum">      81 </span>            :      {_data_ext_R0_data[9]},</a>
+<a name="82"><span class="lineNum">      82 </span>            :      {_data_ext_R0_data[8]},</a>
+<a name="83"><span class="lineNum">      83 </span>            :      {_data_ext_R0_data[7]},</a>
+<a name="84"><span class="lineNum">      84 </span>            :      {_data_ext_R0_data[6]},</a>
+<a name="85"><span class="lineNum">      85 </span>            :      {_data_ext_R0_data[5]},</a>
+<a name="86"><span class="lineNum">      86 </span>            :      {_data_ext_R0_data[4]},</a>
+<a name="87"><span class="lineNum">      87 </span>            :      {_data_ext_R0_data[3]},</a>
+<a name="88"><span class="lineNum">      88 </span>            :      {_data_ext_R0_data[2]},</a>
+<a name="89"><span class="lineNum">      89 </span>            :      {_data_ext_R0_data[1]},</a>
+<a name="90"><span class="lineNum">      90 </span>            :      {_data_ext_R0_data[0]}};</a>
+<a name="91"><span class="lineNum">      91 </span><span class="lineCov">     383190 :   always @(posedge clock or posedge reset) begin</span></a>
+<a name="92"><span class="lineNum">      92 </span><span class="lineCov">        816 :     if (reset) begin</span></a>
+<a name="93"><span class="lineNum">      93 </span><span class="lineCov">        408 :       doing_reset &lt;= 1'h1;</span></a>
+<a name="94"><span class="lineNum">      94 </span><span class="lineCov">        408 :       resetRow &lt;= 5'h0;</span></a>
+<a name="95"><span class="lineNum">      95 </span>            :     end</a>
+<a name="96"><span class="lineNum">      96 </span><span class="lineCov">     191187 :     else begin</span></a>
+<a name="97"><span class="lineNum">      97 </span><span class="lineCov">     191187 :       doing_reset &lt;= resetRow != 5'h1F &amp; (io_resetEn | doing_reset);</span></a>
+<a name="98"><span class="lineNum">      98 </span><span class="lineCov">       5800 :       if (doing_reset)</span></a>
+<a name="99"><span class="lineNum">      99 </span><span class="lineCov">       2900 :         resetRow &lt;= 5'(resetRow + 5'h1);</span></a>
+<a name="100"><span class="lineNum">     100 </span>            :     end</a>
+<a name="101"><span class="lineNum">     101 </span>            :   end // always @(posedge, posedge)</a>
+<a name="102"><span class="lineNum">     102 </span><span class="lineCov">     383082 :   always @(posedge clock) begin</span></a>
+<a name="103"><span class="lineNum">     103 </span><span class="lineCov">      25050 :     if (io_ren_0)</span></a>
+<a name="104"><span class="lineNum">     104 </span><span class="lineCov">      12525 :       raddr_0 &lt;= io_raddr_0;</span></a>
+<a name="105"><span class="lineNum">     105 </span>            :   end // always @(posedge)</a>
+<a name="106"><span class="lineNum">     106 </span>            :   `ifdef ENABLE_INITIAL_REG_</a>
+<a name="107"><span class="lineNum">     107 </span>            :     `ifdef FIRRTL_BEFORE_INITIAL</a>
+<a name="108"><span class="lineNum">     108 </span>            :       `FIRRTL_BEFORE_INITIAL</a>
+<a name="109"><span class="lineNum">     109 </span>            :     `endif // FIRRTL_BEFORE_INITIAL</a>
+<a name="110"><span class="lineNum">     110 </span>            :     logic [31:0] _RANDOM[0:0];</a>
+<a name="111"><span class="lineNum">     111 </span><span class="lineCov">        174 :     initial begin</span></a>
+<a name="112"><span class="lineNum">     112 </span>            :       `ifdef INIT_RANDOM_PROLOG_</a>
+<a name="113"><span class="lineNum">     113 </span>            :         `INIT_RANDOM_PROLOG_</a>
+<a name="114"><span class="lineNum">     114 </span>            :       `endif // INIT_RANDOM_PROLOG_</a>
+<a name="115"><span class="lineNum">     115 </span>            :       `ifdef RANDOMIZE_REG_INIT</a>
+<a name="116"><span class="lineNum">     116 </span>            :         _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;</a>
+<a name="117"><span class="lineNum">     117 </span>            :         doing_reset = _RANDOM[/*Zero width*/ 1'b0][0];</a>
+<a name="118"><span class="lineNum">     118 </span>            :         resetRow = _RANDOM[/*Zero width*/ 1'b0][5:1];</a>
+<a name="119"><span class="lineNum">     119 </span>            :         raddr_0 = _RANDOM[/*Zero width*/ 1'b0][14:6];</a>
+<a name="120"><span class="lineNum">     120 </span>            :       `endif // RANDOMIZE_REG_INIT</a>
+<a name="121"><span class="lineNum">     121 </span><span class="lineCov">         51 :       if (reset) begin</span></a>
+<a name="122"><span class="lineNum">     122 </span><span class="lineCov">         36 :         doing_reset = 1'h1;</span></a>
+<a name="123"><span class="lineNum">     123 </span><span class="lineCov">         36 :         resetRow = 5'h0;</span></a>
+<a name="124"><span class="lineNum">     124 </span>            :       end</a>
+<a name="125"><span class="lineNum">     125 </span>            :     end // initial</a>
+<a name="126"><span class="lineNum">     126 </span>            :     `ifdef FIRRTL_AFTER_INITIAL</a>
+<a name="127"><span class="lineNum">     127 </span>            :       `FIRRTL_AFTER_INITIAL</a>
+<a name="128"><span class="lineNum">     128 </span>            :     `endif // FIRRTL_AFTER_INITIAL</a>
+<a name="129"><span class="lineNum">     129 </span>            :   `endif // ENABLE_INITIAL_REG_</a>
+<a name="130"><span class="lineNum">     130 </span>            :   data_32x16 data_ext (</a>
+<a name="131"><span class="lineNum">     131 </span>            :     .R0_addr (raddr_0[8:4]),</a>
+<a name="132"><span class="lineNum">     132 </span>            :     .R0_en   (1'h1),</a>
+<a name="133"><span class="lineNum">     133 </span>            :     .R0_clk  (clock),</a>
+<a name="134"><span class="lineNum">     134 </span>            :     .R0_data (_data_ext_R0_data),</a>
+<a name="135"><span class="lineNum">     135 </span>            :     .W0_addr (io_waddr[8:4]),</a>
+<a name="136"><span class="lineNum">     136 </span>            :     .W0_en   (~doing_reset &amp; io_wen),</a>
+<a name="137"><span class="lineNum">     137 </span>            :     .W0_clk  (clock),</a>
+<a name="138"><span class="lineNum">     138 </span>            :     .W0_data ({16{io_wdata}}),</a>
+<a name="139"><span class="lineNum">     139 </span>            :     .W1_addr (resetRow),</a>
+<a name="140"><span class="lineNum">     140 </span>            :     .W1_en   (doing_reset),</a>
+<a name="141"><span class="lineNum">     141 </span>            :     .W1_clk  (clock),</a>
+<a name="142"><span class="lineNum">     142 </span>            :     .W1_data (16'h0)</a>
+<a name="143"><span class="lineNum">     143 </span>            :   );</a>
+<a name="144"><span class="lineNum">     144 </span>            :   assign io_rdata_0 = ~doing_reset &amp; _GEN[raddr_0[3:0]];</a>
+<a name="145"><span class="lineNum">     145 </span>            : endmodule</a>
+<a name="146"><span class="lineNum">     146 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FoldedSRAMTemplate.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FoldedSRAMTemplate.sv.func-sort-c.html
new file mode 100644
index 0000000..c683b87
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FoldedSRAMTemplate.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/FoldedSRAMTemplate.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - FoldedSRAMTemplate.sv<span style="font-size: 80%;"> (<a href="FoldedSRAMTemplate.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">40</td>
+            <td class="headerCovTableEntry">40</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="FoldedSRAMTemplate.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FoldedSRAMTemplate.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FoldedSRAMTemplate.sv.func.html
new file mode 100644
index 0000000..ef87a51
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FoldedSRAMTemplate.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/FoldedSRAMTemplate.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - FoldedSRAMTemplate.sv<span style="font-size: 80%;"> (<a href="FoldedSRAMTemplate.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">40</td>
+            <td class="headerCovTableEntry">40</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="FoldedSRAMTemplate.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FoldedSRAMTemplate.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FoldedSRAMTemplate.sv.gcov.html
new file mode 100644
index 0000000..fa60106
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FoldedSRAMTemplate.sv.gcov.html
@@ -0,0 +1,300 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/FoldedSRAMTemplate.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - FoldedSRAMTemplate.sv<span style="font-size: 80%;"> (source / <a href="FoldedSRAMTemplate.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">40</td>
+            <td class="headerCovTableEntry">40</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : module FoldedSRAMTemplate(</a>
+<a name="59"><span class="lineNum">      59 </span><span class="lineCov">     127786 :   input         clock,</span></a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">         62 :   input         reset,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">        201 :   output        io_r_req_ready,</span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">        309 :   input         io_r_req_valid,</span></a>
+<a name="63"><span class="lineNum">      63 </span><span class="lineCov">      26388 :   input  [10:0] io_r_req_bits_setIdx,</span></a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">        106 :   output        io_r_resp_data_0,</span></a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">        119 :   output        io_r_resp_data_1,</span></a>
+<a name="66"><span class="lineNum">      66 </span><span class="lineCov">        125 :   input         io_w_req_valid,</span></a>
+<a name="67"><span class="lineNum">      67 </span><span class="lineCov">        323 :   input  [10:0] io_w_req_bits_setIdx,</span></a>
+<a name="68"><span class="lineNum">      68 </span><span class="lineCov">         53 :   input         io_w_req_bits_data_0,</span></a>
+<a name="69"><span class="lineNum">      69 </span><span class="lineCov">         65 :   input         io_w_req_bits_data_1,</span></a>
+<a name="70"><span class="lineNum">      70 </span><span class="lineCov">        114 :   input  [1:0]  io_w_req_bits_waymask,</span></a>
+<a name="71"><span class="lineNum">      71 </span><span class="lineCov">        146 :   input         extra_reset</span></a>
+<a name="72"><span class="lineNum">      72 </span>            : );</a>
+<a name="73"><span class="lineNum">      73 </span>            : </a>
+<a name="74"><span class="lineNum">      74 </span>            :   wire       _array_io_r_resp_data_0;</a>
+<a name="75"><span class="lineNum">      75 </span>            :   wire       _array_io_r_resp_data_1;</a>
+<a name="76"><span class="lineNum">      76 </span>            :   wire       _array_io_r_resp_data_2;</a>
+<a name="77"><span class="lineNum">      77 </span>            :   wire       _array_io_r_resp_data_3;</a>
+<a name="78"><span class="lineNum">      78 </span>            :   wire       _array_io_r_resp_data_4;</a>
+<a name="79"><span class="lineNum">      79 </span>            :   wire       _array_io_r_resp_data_5;</a>
+<a name="80"><span class="lineNum">      80 </span>            :   wire       _array_io_r_resp_data_6;</a>
+<a name="81"><span class="lineNum">      81 </span>            :   wire       _array_io_r_resp_data_7;</a>
+<a name="82"><span class="lineNum">      82 </span>            :   wire       _array_io_r_resp_data_8;</a>
+<a name="83"><span class="lineNum">      83 </span>            :   wire       _array_io_r_resp_data_9;</a>
+<a name="84"><span class="lineNum">      84 </span>            :   wire       _array_io_r_resp_data_10;</a>
+<a name="85"><span class="lineNum">      85 </span>            :   wire       _array_io_r_resp_data_11;</a>
+<a name="86"><span class="lineNum">      86 </span>            :   wire       _array_io_r_resp_data_12;</a>
+<a name="87"><span class="lineNum">      87 </span>            :   wire       _array_io_r_resp_data_13;</a>
+<a name="88"><span class="lineNum">      88 </span>            :   wire       _array_io_r_resp_data_14;</a>
+<a name="89"><span class="lineNum">      89 </span>            :   wire       _array_io_r_resp_data_15;</a>
+<a name="90"><span class="lineNum">      90 </span><span class="lineCov">        485 :   reg  [2:0] ridx;</span></a>
+<a name="91"><span class="lineNum">      91 </span><span class="lineCov">        326 :   reg        holdRidx_last_r;</span></a>
+<a name="92"><span class="lineNum">      92 </span><span class="lineCov">        564 :   reg  [2:0] holdRidx_hold_data;</span></a>
+<a name="93"><span class="lineNum">      93 </span><span class="lineCov">        507 :   wire [2:0] holdRidx = holdRidx_last_r ? ridx : holdRidx_hold_data;</span></a>
+<a name="94"><span class="lineNum">      94 </span><span class="lineCov">        340 :   reg        holdRidx_last_r_1;</span></a>
+<a name="95"><span class="lineNum">      95 </span><span class="lineCov">        544 :   reg  [2:0] holdRidx_hold_data_1;</span></a>
+<a name="96"><span class="lineNum">      96 </span><span class="lineCov">        495 :   wire [2:0] holdRidx_1 = holdRidx_last_r_1 ? ridx : holdRidx_hold_data_1;</span></a>
+<a name="97"><span class="lineNum">      97 </span>            :   wire       _wmask_T_3 = io_w_req_bits_setIdx[2:0] == 3'h0;</a>
+<a name="98"><span class="lineNum">      98 </span>            :   wire       _wmask_T_9 = io_w_req_bits_setIdx[2:0] == 3'h1;</a>
+<a name="99"><span class="lineNum">      99 </span>            :   wire       _wmask_T_15 = io_w_req_bits_setIdx[2:0] == 3'h2;</a>
+<a name="100"><span class="lineNum">     100 </span>            :   wire       _wmask_T_21 = io_w_req_bits_setIdx[2:0] == 3'h3;</a>
+<a name="101"><span class="lineNum">     101 </span>            :   wire       _wmask_T_27 = io_w_req_bits_setIdx[2:0] == 3'h4;</a>
+<a name="102"><span class="lineNum">     102 </span>            :   wire       _wmask_T_33 = io_w_req_bits_setIdx[2:0] == 3'h5;</a>
+<a name="103"><span class="lineNum">     103 </span>            :   wire       _wmask_T_39 = io_w_req_bits_setIdx[2:0] == 3'h6;</a>
+<a name="104"><span class="lineNum">     104 </span><span class="lineCov">     510776 :   always @(posedge clock) begin</span></a>
+<a name="105"><span class="lineNum">     105 </span><span class="lineCov">      33400 :     if (io_r_req_valid)</span></a>
+<a name="106"><span class="lineNum">     106 </span><span class="lineCov">      16700 :       ridx &lt;= io_r_req_bits_setIdx[2:0];</span></a>
+<a name="107"><span class="lineNum">     107 </span><span class="lineCov">      33224 :     if (holdRidx_last_r)</span></a>
+<a name="108"><span class="lineNum">     108 </span><span class="lineCov">      16612 :       holdRidx_hold_data &lt;= ridx;</span></a>
+<a name="109"><span class="lineNum">     109 </span><span class="lineCov">      33232 :     if (holdRidx_last_r_1)</span></a>
+<a name="110"><span class="lineNum">     110 </span><span class="lineCov">      16616 :       holdRidx_hold_data_1 &lt;= ridx;</span></a>
+<a name="111"><span class="lineNum">     111 </span>            :   end // always @(posedge)</a>
+<a name="112"><span class="lineNum">     112 </span><span class="lineCov">     510920 :   always @(posedge clock or posedge reset) begin</span></a>
+<a name="113"><span class="lineNum">     113 </span><span class="lineCov">       1088 :     if (reset) begin</span></a>
+<a name="114"><span class="lineNum">     114 </span><span class="lineCov">        544 :       holdRidx_last_r &lt;= 1'h0;</span></a>
+<a name="115"><span class="lineNum">     115 </span><span class="lineCov">        544 :       holdRidx_last_r_1 &lt;= 1'h0;</span></a>
+<a name="116"><span class="lineNum">     116 </span>            :     end</a>
+<a name="117"><span class="lineNum">     117 </span><span class="lineCov">     254916 :     else begin</span></a>
+<a name="118"><span class="lineNum">     118 </span><span class="lineCov">      33584 :       if (io_r_req_valid | holdRidx_last_r)</span></a>
+<a name="119"><span class="lineNum">     119 </span><span class="lineCov">      16792 :         holdRidx_last_r &lt;= io_r_req_valid;</span></a>
+<a name="120"><span class="lineNum">     120 </span><span class="lineCov">      33592 :       if (io_r_req_valid | holdRidx_last_r_1)</span></a>
+<a name="121"><span class="lineNum">     121 </span><span class="lineCov">      16796 :         holdRidx_last_r_1 &lt;= io_r_req_valid;</span></a>
+<a name="122"><span class="lineNum">     122 </span>            :     end</a>
+<a name="123"><span class="lineNum">     123 </span>            :   end // always @(posedge, posedge)</a>
+<a name="124"><span class="lineNum">     124 </span>            :   `ifdef ENABLE_INITIAL_REG_</a>
+<a name="125"><span class="lineNum">     125 </span>            :     `ifdef FIRRTL_BEFORE_INITIAL</a>
+<a name="126"><span class="lineNum">     126 </span>            :       `FIRRTL_BEFORE_INITIAL</a>
+<a name="127"><span class="lineNum">     127 </span>            :     `endif // FIRRTL_BEFORE_INITIAL</a>
+<a name="128"><span class="lineNum">     128 </span>            :     logic [31:0] _RANDOM[0:0];</a>
+<a name="129"><span class="lineNum">     129 </span><span class="lineCov">        232 :     initial begin</span></a>
+<a name="130"><span class="lineNum">     130 </span>            :       `ifdef INIT_RANDOM_PROLOG_</a>
+<a name="131"><span class="lineNum">     131 </span>            :         `INIT_RANDOM_PROLOG_</a>
+<a name="132"><span class="lineNum">     132 </span>            :       `endif // INIT_RANDOM_PROLOG_</a>
+<a name="133"><span class="lineNum">     133 </span>            :       `ifdef RANDOMIZE_REG_INIT</a>
+<a name="134"><span class="lineNum">     134 </span>            :         _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;</a>
+<a name="135"><span class="lineNum">     135 </span>            :         ridx = _RANDOM[/*Zero width*/ 1'b0][2:0];</a>
+<a name="136"><span class="lineNum">     136 </span>            :         holdRidx_last_r = _RANDOM[/*Zero width*/ 1'b0][3];</a>
+<a name="137"><span class="lineNum">     137 </span>            :         holdRidx_hold_data = _RANDOM[/*Zero width*/ 1'b0][6:4];</a>
+<a name="138"><span class="lineNum">     138 </span>            :         holdRidx_last_r_1 = _RANDOM[/*Zero width*/ 1'b0][7];</a>
+<a name="139"><span class="lineNum">     139 </span>            :         holdRidx_hold_data_1 = _RANDOM[/*Zero width*/ 1'b0][10:8];</a>
+<a name="140"><span class="lineNum">     140 </span>            :       `endif // RANDOMIZE_REG_INIT</a>
+<a name="141"><span class="lineNum">     141 </span><span class="lineCov">         68 :       if (reset) begin</span></a>
+<a name="142"><span class="lineNum">     142 </span><span class="lineCov">         48 :         holdRidx_last_r = 1'h0;</span></a>
+<a name="143"><span class="lineNum">     143 </span><span class="lineCov">         48 :         holdRidx_last_r_1 = 1'h0;</span></a>
+<a name="144"><span class="lineNum">     144 </span>            :       end</a>
+<a name="145"><span class="lineNum">     145 </span>            :     end // initial</a>
+<a name="146"><span class="lineNum">     146 </span>            :     `ifdef FIRRTL_AFTER_INITIAL</a>
+<a name="147"><span class="lineNum">     147 </span>            :       `FIRRTL_AFTER_INITIAL</a>
+<a name="148"><span class="lineNum">     148 </span>            :     `endif // FIRRTL_AFTER_INITIAL</a>
+<a name="149"><span class="lineNum">     149 </span>            :   `endif // ENABLE_INITIAL_REG_</a>
+<a name="150"><span class="lineNum">     150 </span>            :   SRAMTemplate_14 array (</a>
+<a name="151"><span class="lineNum">     151 </span>            :     .clock                 (clock),</a>
+<a name="152"><span class="lineNum">     152 </span>            :     .reset                 (reset),</a>
+<a name="153"><span class="lineNum">     153 </span>            :     .io_r_req_ready        (io_r_req_ready),</a>
+<a name="154"><span class="lineNum">     154 </span>            :     .io_r_req_valid        (io_r_req_valid),</a>
+<a name="155"><span class="lineNum">     155 </span>            :     .io_r_req_bits_setIdx  (io_r_req_bits_setIdx[10:3]),</a>
+<a name="156"><span class="lineNum">     156 </span>            :     .io_r_resp_data_0      (_array_io_r_resp_data_0),</a>
+<a name="157"><span class="lineNum">     157 </span>            :     .io_r_resp_data_1      (_array_io_r_resp_data_1),</a>
+<a name="158"><span class="lineNum">     158 </span>            :     .io_r_resp_data_2      (_array_io_r_resp_data_2),</a>
+<a name="159"><span class="lineNum">     159 </span>            :     .io_r_resp_data_3      (_array_io_r_resp_data_3),</a>
+<a name="160"><span class="lineNum">     160 </span>            :     .io_r_resp_data_4      (_array_io_r_resp_data_4),</a>
+<a name="161"><span class="lineNum">     161 </span>            :     .io_r_resp_data_5      (_array_io_r_resp_data_5),</a>
+<a name="162"><span class="lineNum">     162 </span>            :     .io_r_resp_data_6      (_array_io_r_resp_data_6),</a>
+<a name="163"><span class="lineNum">     163 </span>            :     .io_r_resp_data_7      (_array_io_r_resp_data_7),</a>
+<a name="164"><span class="lineNum">     164 </span>            :     .io_r_resp_data_8      (_array_io_r_resp_data_8),</a>
+<a name="165"><span class="lineNum">     165 </span>            :     .io_r_resp_data_9      (_array_io_r_resp_data_9),</a>
+<a name="166"><span class="lineNum">     166 </span>            :     .io_r_resp_data_10     (_array_io_r_resp_data_10),</a>
+<a name="167"><span class="lineNum">     167 </span>            :     .io_r_resp_data_11     (_array_io_r_resp_data_11),</a>
+<a name="168"><span class="lineNum">     168 </span>            :     .io_r_resp_data_12     (_array_io_r_resp_data_12),</a>
+<a name="169"><span class="lineNum">     169 </span>            :     .io_r_resp_data_13     (_array_io_r_resp_data_13),</a>
+<a name="170"><span class="lineNum">     170 </span>            :     .io_r_resp_data_14     (_array_io_r_resp_data_14),</a>
+<a name="171"><span class="lineNum">     171 </span>            :     .io_r_resp_data_15     (_array_io_r_resp_data_15),</a>
+<a name="172"><span class="lineNum">     172 </span>            :     .io_w_req_valid        (io_w_req_valid),</a>
+<a name="173"><span class="lineNum">     173 </span>            :     .io_w_req_bits_setIdx  (io_w_req_bits_setIdx[10:3]),</a>
+<a name="174"><span class="lineNum">     174 </span>            :     .io_w_req_bits_data_0  (io_w_req_bits_data_0),</a>
+<a name="175"><span class="lineNum">     175 </span>            :     .io_w_req_bits_data_1  (io_w_req_bits_data_1),</a>
+<a name="176"><span class="lineNum">     176 </span>            :     .io_w_req_bits_data_2  (io_w_req_bits_data_0),</a>
+<a name="177"><span class="lineNum">     177 </span>            :     .io_w_req_bits_data_3  (io_w_req_bits_data_1),</a>
+<a name="178"><span class="lineNum">     178 </span>            :     .io_w_req_bits_data_4  (io_w_req_bits_data_0),</a>
+<a name="179"><span class="lineNum">     179 </span>            :     .io_w_req_bits_data_5  (io_w_req_bits_data_1),</a>
+<a name="180"><span class="lineNum">     180 </span>            :     .io_w_req_bits_data_6  (io_w_req_bits_data_0),</a>
+<a name="181"><span class="lineNum">     181 </span>            :     .io_w_req_bits_data_7  (io_w_req_bits_data_1),</a>
+<a name="182"><span class="lineNum">     182 </span>            :     .io_w_req_bits_data_8  (io_w_req_bits_data_0),</a>
+<a name="183"><span class="lineNum">     183 </span>            :     .io_w_req_bits_data_9  (io_w_req_bits_data_1),</a>
+<a name="184"><span class="lineNum">     184 </span>            :     .io_w_req_bits_data_10 (io_w_req_bits_data_0),</a>
+<a name="185"><span class="lineNum">     185 </span>            :     .io_w_req_bits_data_11 (io_w_req_bits_data_1),</a>
+<a name="186"><span class="lineNum">     186 </span>            :     .io_w_req_bits_data_12 (io_w_req_bits_data_0),</a>
+<a name="187"><span class="lineNum">     187 </span>            :     .io_w_req_bits_data_13 (io_w_req_bits_data_1),</a>
+<a name="188"><span class="lineNum">     188 </span>            :     .io_w_req_bits_data_14 (io_w_req_bits_data_0),</a>
+<a name="189"><span class="lineNum">     189 </span>            :     .io_w_req_bits_data_15 (io_w_req_bits_data_1),</a>
+<a name="190"><span class="lineNum">     190 </span>            :     .io_w_req_bits_waymask</a>
+<a name="191"><span class="lineNum">     191 </span>            :       ({(&amp;(io_w_req_bits_setIdx[2:0])) &amp; io_w_req_bits_waymask[1],</a>
+<a name="192"><span class="lineNum">     192 </span>            :         (&amp;(io_w_req_bits_setIdx[2:0])) &amp; io_w_req_bits_waymask[0],</a>
+<a name="193"><span class="lineNum">     193 </span>            :         _wmask_T_39 &amp; io_w_req_bits_waymask[1],</a>
+<a name="194"><span class="lineNum">     194 </span>            :         _wmask_T_39 &amp; io_w_req_bits_waymask[0],</a>
+<a name="195"><span class="lineNum">     195 </span>            :         _wmask_T_33 &amp; io_w_req_bits_waymask[1],</a>
+<a name="196"><span class="lineNum">     196 </span>            :         _wmask_T_33 &amp; io_w_req_bits_waymask[0],</a>
+<a name="197"><span class="lineNum">     197 </span>            :         _wmask_T_27 &amp; io_w_req_bits_waymask[1],</a>
+<a name="198"><span class="lineNum">     198 </span>            :         _wmask_T_27 &amp; io_w_req_bits_waymask[0],</a>
+<a name="199"><span class="lineNum">     199 </span>            :         _wmask_T_21 &amp; io_w_req_bits_waymask[1],</a>
+<a name="200"><span class="lineNum">     200 </span>            :         _wmask_T_21 &amp; io_w_req_bits_waymask[0],</a>
+<a name="201"><span class="lineNum">     201 </span>            :         _wmask_T_15 &amp; io_w_req_bits_waymask[1],</a>
+<a name="202"><span class="lineNum">     202 </span>            :         _wmask_T_15 &amp; io_w_req_bits_waymask[0],</a>
+<a name="203"><span class="lineNum">     203 </span>            :         _wmask_T_9 &amp; io_w_req_bits_waymask[1],</a>
+<a name="204"><span class="lineNum">     204 </span>            :         _wmask_T_9 &amp; io_w_req_bits_waymask[0],</a>
+<a name="205"><span class="lineNum">     205 </span>            :         _wmask_T_3 &amp; io_w_req_bits_waymask[1],</a>
+<a name="206"><span class="lineNum">     206 </span>            :         _wmask_T_3 &amp; io_w_req_bits_waymask[0]}),</a>
+<a name="207"><span class="lineNum">     207 </span>            :     .extra_reset           (extra_reset)</a>
+<a name="208"><span class="lineNum">     208 </span>            :   );</a>
+<a name="209"><span class="lineNum">     209 </span>            :   assign io_r_resp_data_0 =</a>
+<a name="210"><span class="lineNum">     210 </span>            :     holdRidx == 3'h0 &amp; _array_io_r_resp_data_0 | holdRidx == 3'h1</a>
+<a name="211"><span class="lineNum">     211 </span>            :     &amp; _array_io_r_resp_data_2 | holdRidx == 3'h2 &amp; _array_io_r_resp_data_4</a>
+<a name="212"><span class="lineNum">     212 </span>            :     | holdRidx == 3'h3 &amp; _array_io_r_resp_data_6 | holdRidx == 3'h4</a>
+<a name="213"><span class="lineNum">     213 </span>            :     &amp; _array_io_r_resp_data_8 | holdRidx == 3'h5 &amp; _array_io_r_resp_data_10</a>
+<a name="214"><span class="lineNum">     214 </span>            :     | holdRidx == 3'h6 &amp; _array_io_r_resp_data_12 | (&amp;holdRidx)</a>
+<a name="215"><span class="lineNum">     215 </span>            :     &amp; _array_io_r_resp_data_14;</a>
+<a name="216"><span class="lineNum">     216 </span>            :   assign io_r_resp_data_1 =</a>
+<a name="217"><span class="lineNum">     217 </span>            :     holdRidx_1 == 3'h0 &amp; _array_io_r_resp_data_1 | holdRidx_1 == 3'h1</a>
+<a name="218"><span class="lineNum">     218 </span>            :     &amp; _array_io_r_resp_data_3 | holdRidx_1 == 3'h2 &amp; _array_io_r_resp_data_5</a>
+<a name="219"><span class="lineNum">     219 </span>            :     | holdRidx_1 == 3'h3 &amp; _array_io_r_resp_data_7 | holdRidx_1 == 3'h4</a>
+<a name="220"><span class="lineNum">     220 </span>            :     &amp; _array_io_r_resp_data_9 | holdRidx_1 == 3'h5 &amp; _array_io_r_resp_data_11</a>
+<a name="221"><span class="lineNum">     221 </span>            :     | holdRidx_1 == 3'h6 &amp; _array_io_r_resp_data_13 | (&amp;holdRidx_1)</a>
+<a name="222"><span class="lineNum">     222 </span>            :     &amp; _array_io_r_resp_data_15;</a>
+<a name="223"><span class="lineNum">     223 </span>            : endmodule</a>
+<a name="224"><span class="lineNum">     224 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FoldedSRAMTemplate_1.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FoldedSRAMTemplate_1.sv.func-sort-c.html
new file mode 100644
index 0000000..65d2569
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FoldedSRAMTemplate_1.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/FoldedSRAMTemplate_1.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - FoldedSRAMTemplate_1.sv<span style="font-size: 80%;"> (<a href="FoldedSRAMTemplate_1.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">18</td>
+            <td class="headerCovTableEntry">18</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="FoldedSRAMTemplate_1.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FoldedSRAMTemplate_1.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FoldedSRAMTemplate_1.sv.func.html
new file mode 100644
index 0000000..af8e202
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FoldedSRAMTemplate_1.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/FoldedSRAMTemplate_1.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - FoldedSRAMTemplate_1.sv<span style="font-size: 80%;"> (<a href="FoldedSRAMTemplate_1.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">18</td>
+            <td class="headerCovTableEntry">18</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="FoldedSRAMTemplate_1.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FoldedSRAMTemplate_1.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FoldedSRAMTemplate_1.sv.gcov.html
new file mode 100644
index 0000000..2b6114c
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FoldedSRAMTemplate_1.sv.gcov.html
@@ -0,0 +1,176 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/FoldedSRAMTemplate_1.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - FoldedSRAMTemplate_1.sv<span style="font-size: 80%;"> (source / <a href="FoldedSRAMTemplate_1.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">18</td>
+            <td class="headerCovTableEntry">18</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : module FoldedSRAMTemplate_1(</a>
+<a name="59"><span class="lineNum">      59 </span><span class="lineCov">     127786 :   input        clock,</span></a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">         62 :   input        reset,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">        883 :   output       io_r_req_ready,</span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">        630 :   input        io_r_req_valid,</span></a>
+<a name="63"><span class="lineNum">      63 </span><span class="lineCov">      26102 :   input  [8:0] io_r_req_bits_setIdx,</span></a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">        341 :   output       io_r_resp_data_0_valid,</span></a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">       2670 :   output [7:0] io_r_resp_data_0_tag,</span></a>
+<a name="66"><span class="lineNum">      66 </span><span class="lineCov">       1013 :   output [2:0] io_r_resp_data_0_ctr,</span></a>
+<a name="67"><span class="lineNum">      67 </span><span class="lineCov">        339 :   output       io_r_resp_data_1_valid,</span></a>
+<a name="68"><span class="lineNum">      68 </span><span class="lineCov">       2650 :   output [7:0] io_r_resp_data_1_tag,</span></a>
+<a name="69"><span class="lineNum">      69 </span><span class="lineCov">       1006 :   output [2:0] io_r_resp_data_1_ctr,</span></a>
+<a name="70"><span class="lineNum">      70 </span><span class="lineCov">        331 :   input        io_w_req_valid,</span></a>
+<a name="71"><span class="lineNum">      71 </span><span class="lineCov">        261 :   input  [8:0] io_w_req_bits_setIdx,</span></a>
+<a name="72"><span class="lineNum">      72 </span><span class="lineCov">        123 :   input  [7:0] io_w_req_bits_data_0_tag,</span></a>
+<a name="73"><span class="lineNum">      73 </span><span class="lineCov">         41 :   input  [2:0] io_w_req_bits_data_0_ctr,</span></a>
+<a name="74"><span class="lineNum">      74 </span><span class="lineCov">        123 :   input  [7:0] io_w_req_bits_data_1_tag,</span></a>
+<a name="75"><span class="lineNum">      75 </span><span class="lineCov">         45 :   input  [2:0] io_w_req_bits_data_1_ctr,</span></a>
+<a name="76"><span class="lineNum">      76 </span><span class="lineCov">         63 :   input  [1:0] io_w_req_bits_waymask</span></a>
+<a name="77"><span class="lineNum">      77 </span>            : );</a>
+<a name="78"><span class="lineNum">      78 </span>            : </a>
+<a name="79"><span class="lineNum">      79 </span>            :   SRAMTemplate_15 array (</a>
+<a name="80"><span class="lineNum">      80 </span>            :     .clock                    (clock),</a>
+<a name="81"><span class="lineNum">      81 </span>            :     .reset                    (reset),</a>
+<a name="82"><span class="lineNum">      82 </span>            :     .io_r_req_ready           (io_r_req_ready),</a>
+<a name="83"><span class="lineNum">      83 </span>            :     .io_r_req_valid           (io_r_req_valid),</a>
+<a name="84"><span class="lineNum">      84 </span>            :     .io_r_req_bits_setIdx     (io_r_req_bits_setIdx),</a>
+<a name="85"><span class="lineNum">      85 </span>            :     .io_r_resp_data_0_valid   (io_r_resp_data_0_valid),</a>
+<a name="86"><span class="lineNum">      86 </span>            :     .io_r_resp_data_0_tag     (io_r_resp_data_0_tag),</a>
+<a name="87"><span class="lineNum">      87 </span>            :     .io_r_resp_data_0_ctr     (io_r_resp_data_0_ctr),</a>
+<a name="88"><span class="lineNum">      88 </span>            :     .io_r_resp_data_1_valid   (io_r_resp_data_1_valid),</a>
+<a name="89"><span class="lineNum">      89 </span>            :     .io_r_resp_data_1_tag     (io_r_resp_data_1_tag),</a>
+<a name="90"><span class="lineNum">      90 </span>            :     .io_r_resp_data_1_ctr     (io_r_resp_data_1_ctr),</a>
+<a name="91"><span class="lineNum">      91 </span>            :     .io_w_req_valid           (io_w_req_valid),</a>
+<a name="92"><span class="lineNum">      92 </span>            :     .io_w_req_bits_setIdx     (io_w_req_bits_setIdx),</a>
+<a name="93"><span class="lineNum">      93 </span>            :     .io_w_req_bits_data_0_tag (io_w_req_bits_data_0_tag),</a>
+<a name="94"><span class="lineNum">      94 </span>            :     .io_w_req_bits_data_0_ctr (io_w_req_bits_data_0_ctr),</a>
+<a name="95"><span class="lineNum">      95 </span>            :     .io_w_req_bits_data_1_tag (io_w_req_bits_data_1_tag),</a>
+<a name="96"><span class="lineNum">      96 </span>            :     .io_w_req_bits_data_1_ctr (io_w_req_bits_data_1_ctr),</a>
+<a name="97"><span class="lineNum">      97 </span>            :     .io_w_req_bits_waymask    (io_w_req_bits_waymask)</a>
+<a name="98"><span class="lineNum">      98 </span>            :   );</a>
+<a name="99"><span class="lineNum">      99 </span>            : endmodule</a>
+<a name="100"><span class="lineNum">     100 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FoldedSRAMTemplate_20.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FoldedSRAMTemplate_20.sv.func-sort-c.html
new file mode 100644
index 0000000..1a7c43b
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FoldedSRAMTemplate_20.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/FoldedSRAMTemplate_20.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - FoldedSRAMTemplate_20.sv<span style="font-size: 80%;"> (<a href="FoldedSRAMTemplate_20.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">38</td>
+            <td class="headerCovTableEntry">38</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="FoldedSRAMTemplate_20.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FoldedSRAMTemplate_20.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FoldedSRAMTemplate_20.sv.func.html
new file mode 100644
index 0000000..6e13a45
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FoldedSRAMTemplate_20.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/FoldedSRAMTemplate_20.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - FoldedSRAMTemplate_20.sv<span style="font-size: 80%;"> (<a href="FoldedSRAMTemplate_20.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">38</td>
+            <td class="headerCovTableEntry">38</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="FoldedSRAMTemplate_20.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FoldedSRAMTemplate_20.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FoldedSRAMTemplate_20.sv.gcov.html
new file mode 100644
index 0000000..b78ab72
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FoldedSRAMTemplate_20.sv.gcov.html
@@ -0,0 +1,256 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/FoldedSRAMTemplate_20.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - FoldedSRAMTemplate_20.sv<span style="font-size: 80%;"> (source / <a href="FoldedSRAMTemplate_20.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">38</td>
+            <td class="headerCovTableEntry">38</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : module FoldedSRAMTemplate_20(</a>
+<a name="59"><span class="lineNum">      59 </span><span class="lineCov">     127786 :   input         clock,</span></a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">         62 :   input         reset,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">         76 :   input         io_r_req_valid,</span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">       8746 :   input  [10:0] io_r_req_bits_setIdx,</span></a>
+<a name="63"><span class="lineNum">      63 </span><span class="lineCov">         56 :   output [1:0]  io_r_resp_data_0,</span></a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">         59 :   output [1:0]  io_r_resp_data_1,</span></a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">         59 :   input         io_w_req_valid,</span></a>
+<a name="66"><span class="lineNum">      66 </span><span class="lineCov">     119038 :   input  [10:0] io_w_req_bits_setIdx,</span></a>
+<a name="67"><span class="lineNum">      67 </span><span class="lineCov">         76 :   input  [1:0]  io_w_req_bits_data_0,</span></a>
+<a name="68"><span class="lineNum">      68 </span><span class="lineCov">         64 :   input  [1:0]  io_w_req_bits_data_1,</span></a>
+<a name="69"><span class="lineNum">      69 </span><span class="lineCov">        113 :   input  [1:0]  io_w_req_bits_waymask</span></a>
+<a name="70"><span class="lineNum">      70 </span>            : );</a>
+<a name="71"><span class="lineNum">      71 </span>            : </a>
+<a name="72"><span class="lineNum">      72 </span>            :   wire [1:0] _array_io_r_resp_data_0;</a>
+<a name="73"><span class="lineNum">      73 </span>            :   wire [1:0] _array_io_r_resp_data_1;</a>
+<a name="74"><span class="lineNum">      74 </span>            :   wire [1:0] _array_io_r_resp_data_2;</a>
+<a name="75"><span class="lineNum">      75 </span>            :   wire [1:0] _array_io_r_resp_data_3;</a>
+<a name="76"><span class="lineNum">      76 </span>            :   wire [1:0] _array_io_r_resp_data_4;</a>
+<a name="77"><span class="lineNum">      77 </span>            :   wire [1:0] _array_io_r_resp_data_5;</a>
+<a name="78"><span class="lineNum">      78 </span>            :   wire [1:0] _array_io_r_resp_data_6;</a>
+<a name="79"><span class="lineNum">      79 </span>            :   wire [1:0] _array_io_r_resp_data_7;</a>
+<a name="80"><span class="lineNum">      80 </span><span class="lineCov">         58 :   reg  [1:0] ridx;</span></a>
+<a name="81"><span class="lineNum">      81 </span><span class="lineCov">         87 :   reg        holdRidx_last_r;</span></a>
+<a name="82"><span class="lineNum">      82 </span><span class="lineCov">         60 :   reg  [1:0] holdRidx_hold_data;</span></a>
+<a name="83"><span class="lineNum">      83 </span><span class="lineCov">         55 :   wire [1:0] holdRidx = holdRidx_last_r ? ridx : holdRidx_hold_data;</span></a>
+<a name="84"><span class="lineNum">      84 </span><span class="lineCov">         78 :   reg        holdRidx_last_r_1;</span></a>
+<a name="85"><span class="lineNum">      85 </span><span class="lineCov">         60 :   reg  [1:0] holdRidx_hold_data_1;</span></a>
+<a name="86"><span class="lineNum">      86 </span><span class="lineCov">         64 :   wire [1:0] holdRidx_1 = holdRidx_last_r_1 ? ridx : holdRidx_hold_data_1;</span></a>
+<a name="87"><span class="lineNum">      87 </span>            :   wire       _wmask_T_3 = io_w_req_bits_setIdx[1:0] == 2'h0;</a>
+<a name="88"><span class="lineNum">      88 </span>            :   wire       _wmask_T_9 = io_w_req_bits_setIdx[1:0] == 2'h1;</a>
+<a name="89"><span class="lineNum">      89 </span>            :   wire       _wmask_T_15 = io_w_req_bits_setIdx[1:0] == 2'h2;</a>
+<a name="90"><span class="lineNum">      90 </span><span class="lineCov">     127694 :   always @(posedge clock) begin</span></a>
+<a name="91"><span class="lineNum">      91 </span><span class="lineCov">       8350 :     if (io_r_req_valid)</span></a>
+<a name="92"><span class="lineNum">      92 </span><span class="lineCov">       4175 :       ridx &lt;= io_r_req_bits_setIdx[1:0];</span></a>
+<a name="93"><span class="lineNum">      93 </span><span class="lineCov">       8310 :     if (holdRidx_last_r)</span></a>
+<a name="94"><span class="lineNum">      94 </span><span class="lineCov">       4155 :       holdRidx_hold_data &lt;= ridx;</span></a>
+<a name="95"><span class="lineNum">      95 </span><span class="lineCov">       8300 :     if (holdRidx_last_r_1)</span></a>
+<a name="96"><span class="lineNum">      96 </span><span class="lineCov">       4150 :       holdRidx_hold_data_1 &lt;= ridx;</span></a>
+<a name="97"><span class="lineNum">      97 </span>            :   end // always @(posedge)</a>
+<a name="98"><span class="lineNum">      98 </span><span class="lineCov">     127730 :   always @(posedge clock or posedge reset) begin</span></a>
+<a name="99"><span class="lineNum">      99 </span><span class="lineCov">        272 :     if (reset) begin</span></a>
+<a name="100"><span class="lineNum">     100 </span><span class="lineCov">        136 :       holdRidx_last_r &lt;= 1'h0;</span></a>
+<a name="101"><span class="lineNum">     101 </span><span class="lineCov">        136 :       holdRidx_last_r_1 &lt;= 1'h0;</span></a>
+<a name="102"><span class="lineNum">     102 </span>            :     end</a>
+<a name="103"><span class="lineNum">     103 </span><span class="lineCov">      63729 :     else begin</span></a>
+<a name="104"><span class="lineNum">     104 </span><span class="lineCov">       8400 :       if (io_r_req_valid | holdRidx_last_r)</span></a>
+<a name="105"><span class="lineNum">     105 </span><span class="lineCov">       4200 :         holdRidx_last_r &lt;= io_r_req_valid;</span></a>
+<a name="106"><span class="lineNum">     106 </span><span class="lineCov">       8390 :       if (io_r_req_valid | holdRidx_last_r_1)</span></a>
+<a name="107"><span class="lineNum">     107 </span><span class="lineCov">       4195 :         holdRidx_last_r_1 &lt;= io_r_req_valid;</span></a>
+<a name="108"><span class="lineNum">     108 </span>            :     end</a>
+<a name="109"><span class="lineNum">     109 </span>            :   end // always @(posedge, posedge)</a>
+<a name="110"><span class="lineNum">     110 </span>            :   `ifdef ENABLE_INITIAL_REG_</a>
+<a name="111"><span class="lineNum">     111 </span>            :     `ifdef FIRRTL_BEFORE_INITIAL</a>
+<a name="112"><span class="lineNum">     112 </span>            :       `FIRRTL_BEFORE_INITIAL</a>
+<a name="113"><span class="lineNum">     113 </span>            :     `endif // FIRRTL_BEFORE_INITIAL</a>
+<a name="114"><span class="lineNum">     114 </span>            :     logic [31:0] _RANDOM[0:0];</a>
+<a name="115"><span class="lineNum">     115 </span><span class="lineCov">         58 :     initial begin</span></a>
+<a name="116"><span class="lineNum">     116 </span>            :       `ifdef INIT_RANDOM_PROLOG_</a>
+<a name="117"><span class="lineNum">     117 </span>            :         `INIT_RANDOM_PROLOG_</a>
+<a name="118"><span class="lineNum">     118 </span>            :       `endif // INIT_RANDOM_PROLOG_</a>
+<a name="119"><span class="lineNum">     119 </span>            :       `ifdef RANDOMIZE_REG_INIT</a>
+<a name="120"><span class="lineNum">     120 </span>            :         _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;</a>
+<a name="121"><span class="lineNum">     121 </span>            :         ridx = _RANDOM[/*Zero width*/ 1'b0][1:0];</a>
+<a name="122"><span class="lineNum">     122 </span>            :         holdRidx_last_r = _RANDOM[/*Zero width*/ 1'b0][2];</a>
+<a name="123"><span class="lineNum">     123 </span>            :         holdRidx_hold_data = _RANDOM[/*Zero width*/ 1'b0][4:3];</a>
+<a name="124"><span class="lineNum">     124 </span>            :         holdRidx_last_r_1 = _RANDOM[/*Zero width*/ 1'b0][5];</a>
+<a name="125"><span class="lineNum">     125 </span>            :         holdRidx_hold_data_1 = _RANDOM[/*Zero width*/ 1'b0][7:6];</a>
+<a name="126"><span class="lineNum">     126 </span>            :       `endif // RANDOMIZE_REG_INIT</a>
+<a name="127"><span class="lineNum">     127 </span><span class="lineCov">         17 :       if (reset) begin</span></a>
+<a name="128"><span class="lineNum">     128 </span><span class="lineCov">         12 :         holdRidx_last_r = 1'h0;</span></a>
+<a name="129"><span class="lineNum">     129 </span><span class="lineCov">         12 :         holdRidx_last_r_1 = 1'h0;</span></a>
+<a name="130"><span class="lineNum">     130 </span>            :       end</a>
+<a name="131"><span class="lineNum">     131 </span>            :     end // initial</a>
+<a name="132"><span class="lineNum">     132 </span>            :     `ifdef FIRRTL_AFTER_INITIAL</a>
+<a name="133"><span class="lineNum">     133 </span>            :       `FIRRTL_AFTER_INITIAL</a>
+<a name="134"><span class="lineNum">     134 </span>            :     `endif // FIRRTL_AFTER_INITIAL</a>
+<a name="135"><span class="lineNum">     135 </span>            :   `endif // ENABLE_INITIAL_REG_</a>
+<a name="136"><span class="lineNum">     136 </span>            :   SRAMTemplate_34 array (</a>
+<a name="137"><span class="lineNum">     137 </span>            :     .clock                 (clock),</a>
+<a name="138"><span class="lineNum">     138 </span>            :     .reset                 (reset),</a>
+<a name="139"><span class="lineNum">     139 </span>            :     .io_r_req_valid        (io_r_req_valid),</a>
+<a name="140"><span class="lineNum">     140 </span>            :     .io_r_req_bits_setIdx  (io_r_req_bits_setIdx[10:2]),</a>
+<a name="141"><span class="lineNum">     141 </span>            :     .io_r_resp_data_0      (_array_io_r_resp_data_0),</a>
+<a name="142"><span class="lineNum">     142 </span>            :     .io_r_resp_data_1      (_array_io_r_resp_data_1),</a>
+<a name="143"><span class="lineNum">     143 </span>            :     .io_r_resp_data_2      (_array_io_r_resp_data_2),</a>
+<a name="144"><span class="lineNum">     144 </span>            :     .io_r_resp_data_3      (_array_io_r_resp_data_3),</a>
+<a name="145"><span class="lineNum">     145 </span>            :     .io_r_resp_data_4      (_array_io_r_resp_data_4),</a>
+<a name="146"><span class="lineNum">     146 </span>            :     .io_r_resp_data_5      (_array_io_r_resp_data_5),</a>
+<a name="147"><span class="lineNum">     147 </span>            :     .io_r_resp_data_6      (_array_io_r_resp_data_6),</a>
+<a name="148"><span class="lineNum">     148 </span>            :     .io_r_resp_data_7      (_array_io_r_resp_data_7),</a>
+<a name="149"><span class="lineNum">     149 </span>            :     .io_w_req_valid        (io_w_req_valid),</a>
+<a name="150"><span class="lineNum">     150 </span>            :     .io_w_req_bits_setIdx  (io_w_req_bits_setIdx[10:2]),</a>
+<a name="151"><span class="lineNum">     151 </span>            :     .io_w_req_bits_data_0  (io_w_req_bits_data_0),</a>
+<a name="152"><span class="lineNum">     152 </span>            :     .io_w_req_bits_data_1  (io_w_req_bits_data_1),</a>
+<a name="153"><span class="lineNum">     153 </span>            :     .io_w_req_bits_data_2  (io_w_req_bits_data_0),</a>
+<a name="154"><span class="lineNum">     154 </span>            :     .io_w_req_bits_data_3  (io_w_req_bits_data_1),</a>
+<a name="155"><span class="lineNum">     155 </span>            :     .io_w_req_bits_data_4  (io_w_req_bits_data_0),</a>
+<a name="156"><span class="lineNum">     156 </span>            :     .io_w_req_bits_data_5  (io_w_req_bits_data_1),</a>
+<a name="157"><span class="lineNum">     157 </span>            :     .io_w_req_bits_data_6  (io_w_req_bits_data_0),</a>
+<a name="158"><span class="lineNum">     158 </span>            :     .io_w_req_bits_data_7  (io_w_req_bits_data_1),</a>
+<a name="159"><span class="lineNum">     159 </span>            :     .io_w_req_bits_waymask</a>
+<a name="160"><span class="lineNum">     160 </span>            :       ({(&amp;(io_w_req_bits_setIdx[1:0])) &amp; io_w_req_bits_waymask[1],</a>
+<a name="161"><span class="lineNum">     161 </span>            :         (&amp;(io_w_req_bits_setIdx[1:0])) &amp; io_w_req_bits_waymask[0],</a>
+<a name="162"><span class="lineNum">     162 </span>            :         _wmask_T_15 &amp; io_w_req_bits_waymask[1],</a>
+<a name="163"><span class="lineNum">     163 </span>            :         _wmask_T_15 &amp; io_w_req_bits_waymask[0],</a>
+<a name="164"><span class="lineNum">     164 </span>            :         _wmask_T_9 &amp; io_w_req_bits_waymask[1],</a>
+<a name="165"><span class="lineNum">     165 </span>            :         _wmask_T_9 &amp; io_w_req_bits_waymask[0],</a>
+<a name="166"><span class="lineNum">     166 </span>            :         _wmask_T_3 &amp; io_w_req_bits_waymask[1],</a>
+<a name="167"><span class="lineNum">     167 </span>            :         _wmask_T_3 &amp; io_w_req_bits_waymask[0]})</a>
+<a name="168"><span class="lineNum">     168 </span>            :   );</a>
+<a name="169"><span class="lineNum">     169 </span>            :   assign io_r_resp_data_0 =</a>
+<a name="170"><span class="lineNum">     170 </span>            :     (holdRidx == 2'h0 ? _array_io_r_resp_data_0 : 2'h0)</a>
+<a name="171"><span class="lineNum">     171 </span>            :     | (holdRidx == 2'h1 ? _array_io_r_resp_data_2 : 2'h0)</a>
+<a name="172"><span class="lineNum">     172 </span>            :     | (holdRidx == 2'h2 ? _array_io_r_resp_data_4 : 2'h0)</a>
+<a name="173"><span class="lineNum">     173 </span>            :     | ((&amp;holdRidx) ? _array_io_r_resp_data_6 : 2'h0);</a>
+<a name="174"><span class="lineNum">     174 </span>            :   assign io_r_resp_data_1 =</a>
+<a name="175"><span class="lineNum">     175 </span>            :     (holdRidx_1 == 2'h0 ? _array_io_r_resp_data_1 : 2'h0)</a>
+<a name="176"><span class="lineNum">     176 </span>            :     | (holdRidx_1 == 2'h1 ? _array_io_r_resp_data_3 : 2'h0)</a>
+<a name="177"><span class="lineNum">     177 </span>            :     | (holdRidx_1 == 2'h2 ? _array_io_r_resp_data_5 : 2'h0)</a>
+<a name="178"><span class="lineNum">     178 </span>            :     | ((&amp;holdRidx_1) ? _array_io_r_resp_data_7 : 2'h0);</a>
+<a name="179"><span class="lineNum">     179 </span>            : endmodule</a>
+<a name="180"><span class="lineNum">     180 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FoldedSRAMTemplate_21.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FoldedSRAMTemplate_21.sv.func-sort-c.html
new file mode 100644
index 0000000..8cbcc80
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FoldedSRAMTemplate_21.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/FoldedSRAMTemplate_21.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - FoldedSRAMTemplate_21.sv<span style="font-size: 80%;"> (<a href="FoldedSRAMTemplate_21.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">13</td>
+            <td class="headerCovTableEntry">13</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="FoldedSRAMTemplate_21.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FoldedSRAMTemplate_21.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FoldedSRAMTemplate_21.sv.func.html
new file mode 100644
index 0000000..7443be9
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FoldedSRAMTemplate_21.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/FoldedSRAMTemplate_21.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - FoldedSRAMTemplate_21.sv<span style="font-size: 80%;"> (<a href="FoldedSRAMTemplate_21.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">13</td>
+            <td class="headerCovTableEntry">13</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="FoldedSRAMTemplate_21.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FoldedSRAMTemplate_21.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FoldedSRAMTemplate_21.sv.gcov.html
new file mode 100644
index 0000000..6a7bee7
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FoldedSRAMTemplate_21.sv.gcov.html
@@ -0,0 +1,166 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/FoldedSRAMTemplate_21.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - FoldedSRAMTemplate_21.sv<span style="font-size: 80%;"> (source / <a href="FoldedSRAMTemplate_21.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">13</td>
+            <td class="headerCovTableEntry">13</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : module FoldedSRAMTemplate_21(</a>
+<a name="59"><span class="lineNum">      59 </span><span class="lineCov">     127786 :   input         clock,</span></a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">         62 :   input         reset,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">        254 :   input         io_r_req_valid,</span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">      24520 :   input  [6:0]  io_r_req_bits_setIdx,</span></a>
+<a name="63"><span class="lineNum">      63 </span><span class="lineCov">        100 :   output        io_r_resp_data_0_valid,</span></a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">        846 :   output [8:0]  io_r_resp_data_0_tag,</span></a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">        197 :   output [1:0]  io_r_resp_data_0_ctr,</span></a>
+<a name="66"><span class="lineNum">      66 </span><span class="lineCov">       4028 :   output [40:0] io_r_resp_data_0_target,</span></a>
+<a name="67"><span class="lineNum">      67 </span><span class="lineCov">         80 :   input         io_w_req_valid,</span></a>
+<a name="68"><span class="lineNum">      68 </span><span class="lineCov">         91 :   input  [6:0]  io_w_req_bits_setIdx,</span></a>
+<a name="69"><span class="lineNum">      69 </span><span class="lineCov">        127 :   input  [8:0]  io_w_req_bits_data_0_tag,</span></a>
+<a name="70"><span class="lineNum">      70 </span><span class="lineCov">         36 :   input  [1:0]  io_w_req_bits_data_0_ctr,</span></a>
+<a name="71"><span class="lineNum">      71 </span><span class="lineCov">        642 :   input  [40:0] io_w_req_bits_data_0_target</span></a>
+<a name="72"><span class="lineNum">      72 </span>            : );</a>
+<a name="73"><span class="lineNum">      73 </span>            : </a>
+<a name="74"><span class="lineNum">      74 </span>            :   SRAMTemplate_39 array (</a>
+<a name="75"><span class="lineNum">      75 </span>            :     .clock                       (clock),</a>
+<a name="76"><span class="lineNum">      76 </span>            :     .reset                       (reset),</a>
+<a name="77"><span class="lineNum">      77 </span>            :     .io_r_req_valid              (io_r_req_valid),</a>
+<a name="78"><span class="lineNum">      78 </span>            :     .io_r_req_bits_setIdx        (io_r_req_bits_setIdx),</a>
+<a name="79"><span class="lineNum">      79 </span>            :     .io_r_resp_data_0_valid      (io_r_resp_data_0_valid),</a>
+<a name="80"><span class="lineNum">      80 </span>            :     .io_r_resp_data_0_tag        (io_r_resp_data_0_tag),</a>
+<a name="81"><span class="lineNum">      81 </span>            :     .io_r_resp_data_0_ctr        (io_r_resp_data_0_ctr),</a>
+<a name="82"><span class="lineNum">      82 </span>            :     .io_r_resp_data_0_target     (io_r_resp_data_0_target),</a>
+<a name="83"><span class="lineNum">      83 </span>            :     .io_w_req_valid              (io_w_req_valid),</a>
+<a name="84"><span class="lineNum">      84 </span>            :     .io_w_req_bits_setIdx        (io_w_req_bits_setIdx),</a>
+<a name="85"><span class="lineNum">      85 </span>            :     .io_w_req_bits_data_0_tag    (io_w_req_bits_data_0_tag),</a>
+<a name="86"><span class="lineNum">      86 </span>            :     .io_w_req_bits_data_0_ctr    (io_w_req_bits_data_0_ctr),</a>
+<a name="87"><span class="lineNum">      87 </span>            :     .io_w_req_bits_data_0_target (io_w_req_bits_data_0_target)</a>
+<a name="88"><span class="lineNum">      88 </span>            :   );</a>
+<a name="89"><span class="lineNum">      89 </span>            : endmodule</a>
+<a name="90"><span class="lineNum">      90 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FoldedSRAMTemplate_25.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FoldedSRAMTemplate_25.sv.func-sort-c.html
new file mode 100644
index 0000000..a1e5a50
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FoldedSRAMTemplate_25.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/FoldedSRAMTemplate_25.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - FoldedSRAMTemplate_25.sv<span style="font-size: 80%;"> (<a href="FoldedSRAMTemplate_25.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">30</td>
+            <td class="headerCovTableEntry">30</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="FoldedSRAMTemplate_25.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FoldedSRAMTemplate_25.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FoldedSRAMTemplate_25.sv.func.html
new file mode 100644
index 0000000..59f3b84
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FoldedSRAMTemplate_25.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/FoldedSRAMTemplate_25.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - FoldedSRAMTemplate_25.sv<span style="font-size: 80%;"> (<a href="FoldedSRAMTemplate_25.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">30</td>
+            <td class="headerCovTableEntry">30</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="FoldedSRAMTemplate_25.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FoldedSRAMTemplate_25.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FoldedSRAMTemplate_25.sv.gcov.html
new file mode 100644
index 0000000..65e4193
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/FoldedSRAMTemplate_25.sv.gcov.html
@@ -0,0 +1,231 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/FoldedSRAMTemplate_25.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - FoldedSRAMTemplate_25.sv<span style="font-size: 80%;"> (source / <a href="FoldedSRAMTemplate_25.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">30</td>
+            <td class="headerCovTableEntry">30</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : module FoldedSRAMTemplate_25(</a>
+<a name="59"><span class="lineNum">      59 </span><span class="lineCov">     127786 :   input         clock,</span></a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">         62 :   input         reset,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">        394 :   input         io_r_req_valid,</span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">       8520 :   input  [7:0]  io_r_req_bits_setIdx,</span></a>
+<a name="63"><span class="lineNum">      63 </span><span class="lineCov">        145 :   output        io_r_resp_data_0_valid,</span></a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">       1367 :   output [8:0]  io_r_resp_data_0_tag,</span></a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">        287 :   output [1:0]  io_r_resp_data_0_ctr,</span></a>
+<a name="66"><span class="lineNum">      66 </span><span class="lineCov">       6132 :   output [40:0] io_r_resp_data_0_target,</span></a>
+<a name="67"><span class="lineNum">      67 </span><span class="lineCov">        129 :   input         io_w_req_valid,</span></a>
+<a name="68"><span class="lineNum">      68 </span><span class="lineCov">        109 :   input  [7:0]  io_w_req_bits_setIdx,</span></a>
+<a name="69"><span class="lineNum">      69 </span><span class="lineCov">        122 :   input  [8:0]  io_w_req_bits_data_0_tag,</span></a>
+<a name="70"><span class="lineNum">      70 </span><span class="lineCov">         33 :   input  [1:0]  io_w_req_bits_data_0_ctr,</span></a>
+<a name="71"><span class="lineNum">      71 </span><span class="lineCov">        607 :   input  [40:0] io_w_req_bits_data_0_target</span></a>
+<a name="72"><span class="lineNum">      72 </span>            : );</a>
+<a name="73"><span class="lineNum">      73 </span>            : </a>
+<a name="74"><span class="lineNum">      74 </span>            :   wire        _array_io_r_resp_data_0_valid;</a>
+<a name="75"><span class="lineNum">      75 </span>            :   wire [8:0]  _array_io_r_resp_data_0_tag;</a>
+<a name="76"><span class="lineNum">      76 </span>            :   wire [1:0]  _array_io_r_resp_data_0_ctr;</a>
+<a name="77"><span class="lineNum">      77 </span>            :   wire [40:0] _array_io_r_resp_data_0_target;</a>
+<a name="78"><span class="lineNum">      78 </span>            :   wire        _array_io_r_resp_data_1_valid;</a>
+<a name="79"><span class="lineNum">      79 </span>            :   wire [8:0]  _array_io_r_resp_data_1_tag;</a>
+<a name="80"><span class="lineNum">      80 </span>            :   wire [1:0]  _array_io_r_resp_data_1_ctr;</a>
+<a name="81"><span class="lineNum">      81 </span>            :   wire [40:0] _array_io_r_resp_data_1_target;</a>
+<a name="82"><span class="lineNum">      82 </span><span class="lineCov">        163 :   reg         ridx;</span></a>
+<a name="83"><span class="lineNum">      83 </span><span class="lineCov">        448 :   reg         holdRidx_last_r;</span></a>
+<a name="84"><span class="lineNum">      84 </span><span class="lineCov">        215 :   reg         holdRidx_hold_data;</span></a>
+<a name="85"><span class="lineNum">      85 </span><span class="lineCov">        179 :   wire        holdRidx = holdRidx_last_r ? ridx : holdRidx_hold_data;</span></a>
+<a name="86"><span class="lineNum">      86 </span><span class="lineCov">     766164 :   always @(posedge clock) begin</span></a>
+<a name="87"><span class="lineNum">      87 </span><span class="lineCov">      25050 :     if (io_r_req_valid)</span></a>
+<a name="88"><span class="lineNum">      88 </span><span class="lineCov">      12525 :       ridx &lt;= io_r_req_bits_setIdx[0];</span></a>
+<a name="89"><span class="lineNum">      89 </span><span class="lineCov">      24990 :     if (holdRidx_last_r)</span></a>
+<a name="90"><span class="lineNum">      90 </span><span class="lineCov">      12495 :       holdRidx_hold_data &lt;= ridx;</span></a>
+<a name="91"><span class="lineNum">      91 </span>            :   end // always @(posedge)</a>
+<a name="92"><span class="lineNum">      92 </span><span class="lineCov">     766380 :   always @(posedge clock or posedge reset) begin</span></a>
+<a name="93"><span class="lineNum">      93 </span><span class="lineCov">       1632 :     if (reset)</span></a>
+<a name="94"><span class="lineNum">      94 </span><span class="lineCov">        816 :       holdRidx_last_r &lt;= 1'h0;</span></a>
+<a name="95"><span class="lineNum">      95 </span><span class="lineCov">      25380 :     else if (io_r_req_valid | holdRidx_last_r)</span></a>
+<a name="96"><span class="lineNum">      96 </span><span class="lineCov">      12690 :       holdRidx_last_r &lt;= io_r_req_valid;</span></a>
+<a name="97"><span class="lineNum">      97 </span>            :   end // always @(posedge, posedge)</a>
+<a name="98"><span class="lineNum">      98 </span>            :   `ifdef ENABLE_INITIAL_REG_</a>
+<a name="99"><span class="lineNum">      99 </span>            :     `ifdef FIRRTL_BEFORE_INITIAL</a>
+<a name="100"><span class="lineNum">     100 </span>            :       `FIRRTL_BEFORE_INITIAL</a>
+<a name="101"><span class="lineNum">     101 </span>            :     `endif // FIRRTL_BEFORE_INITIAL</a>
+<a name="102"><span class="lineNum">     102 </span>            :     logic [31:0] _RANDOM[0:0];</a>
+<a name="103"><span class="lineNum">     103 </span><span class="lineCov">        348 :     initial begin</span></a>
+<a name="104"><span class="lineNum">     104 </span>            :       `ifdef INIT_RANDOM_PROLOG_</a>
+<a name="105"><span class="lineNum">     105 </span>            :         `INIT_RANDOM_PROLOG_</a>
+<a name="106"><span class="lineNum">     106 </span>            :       `endif // INIT_RANDOM_PROLOG_</a>
+<a name="107"><span class="lineNum">     107 </span>            :       `ifdef RANDOMIZE_REG_INIT</a>
+<a name="108"><span class="lineNum">     108 </span>            :         _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;</a>
+<a name="109"><span class="lineNum">     109 </span>            :         ridx = _RANDOM[/*Zero width*/ 1'b0][0];</a>
+<a name="110"><span class="lineNum">     110 </span>            :         holdRidx_last_r = _RANDOM[/*Zero width*/ 1'b0][1];</a>
+<a name="111"><span class="lineNum">     111 </span>            :         holdRidx_hold_data = _RANDOM[/*Zero width*/ 1'b0][2];</a>
+<a name="112"><span class="lineNum">     112 </span>            :       `endif // RANDOMIZE_REG_INIT</a>
+<a name="113"><span class="lineNum">     113 </span><span class="lineCov">        102 :       if (reset)</span></a>
+<a name="114"><span class="lineNum">     114 </span><span class="lineCov">         72 :         holdRidx_last_r = 1'h0;</span></a>
+<a name="115"><span class="lineNum">     115 </span>            :     end // initial</a>
+<a name="116"><span class="lineNum">     116 </span>            :     `ifdef FIRRTL_AFTER_INITIAL</a>
+<a name="117"><span class="lineNum">     117 </span>            :       `FIRRTL_AFTER_INITIAL</a>
+<a name="118"><span class="lineNum">     118 </span>            :     `endif // FIRRTL_AFTER_INITIAL</a>
+<a name="119"><span class="lineNum">     119 </span>            :   `endif // ENABLE_INITIAL_REG_</a>
+<a name="120"><span class="lineNum">     120 </span>            :   SRAMTemplate_43 array (</a>
+<a name="121"><span class="lineNum">     121 </span>            :     .clock                       (clock),</a>
+<a name="122"><span class="lineNum">     122 </span>            :     .reset                       (reset),</a>
+<a name="123"><span class="lineNum">     123 </span>            :     .io_r_req_valid              (io_r_req_valid),</a>
+<a name="124"><span class="lineNum">     124 </span>            :     .io_r_req_bits_setIdx        (io_r_req_bits_setIdx[7:1]),</a>
+<a name="125"><span class="lineNum">     125 </span>            :     .io_r_resp_data_0_valid      (_array_io_r_resp_data_0_valid),</a>
+<a name="126"><span class="lineNum">     126 </span>            :     .io_r_resp_data_0_tag        (_array_io_r_resp_data_0_tag),</a>
+<a name="127"><span class="lineNum">     127 </span>            :     .io_r_resp_data_0_ctr        (_array_io_r_resp_data_0_ctr),</a>
+<a name="128"><span class="lineNum">     128 </span>            :     .io_r_resp_data_0_target     (_array_io_r_resp_data_0_target),</a>
+<a name="129"><span class="lineNum">     129 </span>            :     .io_r_resp_data_1_valid      (_array_io_r_resp_data_1_valid),</a>
+<a name="130"><span class="lineNum">     130 </span>            :     .io_r_resp_data_1_tag        (_array_io_r_resp_data_1_tag),</a>
+<a name="131"><span class="lineNum">     131 </span>            :     .io_r_resp_data_1_ctr        (_array_io_r_resp_data_1_ctr),</a>
+<a name="132"><span class="lineNum">     132 </span>            :     .io_r_resp_data_1_target     (_array_io_r_resp_data_1_target),</a>
+<a name="133"><span class="lineNum">     133 </span>            :     .io_w_req_valid              (io_w_req_valid),</a>
+<a name="134"><span class="lineNum">     134 </span>            :     .io_w_req_bits_setIdx        (io_w_req_bits_setIdx[7:1]),</a>
+<a name="135"><span class="lineNum">     135 </span>            :     .io_w_req_bits_data_0_tag    (io_w_req_bits_data_0_tag),</a>
+<a name="136"><span class="lineNum">     136 </span>            :     .io_w_req_bits_data_0_ctr    (io_w_req_bits_data_0_ctr),</a>
+<a name="137"><span class="lineNum">     137 </span>            :     .io_w_req_bits_data_0_target (io_w_req_bits_data_0_target),</a>
+<a name="138"><span class="lineNum">     138 </span>            :     .io_w_req_bits_data_1_tag    (io_w_req_bits_data_0_tag),</a>
+<a name="139"><span class="lineNum">     139 </span>            :     .io_w_req_bits_data_1_ctr    (io_w_req_bits_data_0_ctr),</a>
+<a name="140"><span class="lineNum">     140 </span>            :     .io_w_req_bits_data_1_target (io_w_req_bits_data_0_target),</a>
+<a name="141"><span class="lineNum">     141 </span>            :     .io_w_req_bits_waymask       (2'h1 &lt;&lt; io_w_req_bits_setIdx[0])</a>
+<a name="142"><span class="lineNum">     142 </span>            :   );</a>
+<a name="143"><span class="lineNum">     143 </span>            :   assign io_r_resp_data_0_valid =</a>
+<a name="144"><span class="lineNum">     144 </span>            :     ~holdRidx &amp; _array_io_r_resp_data_0_valid | holdRidx &amp; _array_io_r_resp_data_1_valid;</a>
+<a name="145"><span class="lineNum">     145 </span>            :   assign io_r_resp_data_0_tag =</a>
+<a name="146"><span class="lineNum">     146 </span>            :     (holdRidx ? 9'h0 : _array_io_r_resp_data_0_tag)</a>
+<a name="147"><span class="lineNum">     147 </span>            :     | (holdRidx ? _array_io_r_resp_data_1_tag : 9'h0);</a>
+<a name="148"><span class="lineNum">     148 </span>            :   assign io_r_resp_data_0_ctr =</a>
+<a name="149"><span class="lineNum">     149 </span>            :     (holdRidx ? 2'h0 : _array_io_r_resp_data_0_ctr)</a>
+<a name="150"><span class="lineNum">     150 </span>            :     | (holdRidx ? _array_io_r_resp_data_1_ctr : 2'h0);</a>
+<a name="151"><span class="lineNum">     151 </span>            :   assign io_r_resp_data_0_target =</a>
+<a name="152"><span class="lineNum">     152 </span>            :     (holdRidx ? 41'h0 : _array_io_r_resp_data_0_target)</a>
+<a name="153"><span class="lineNum">     153 </span>            :     | (holdRidx ? _array_io_r_resp_data_1_target : 41'h0);</a>
+<a name="154"><span class="lineNum">     154 </span>            : endmodule</a>
+<a name="155"><span class="lineNum">     155 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/ITTage.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/ITTage.sv.func-sort-c.html
new file mode 100644
index 0000000..14d1233
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/ITTage.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/ITTage.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - ITTage.sv<span style="font-size: 80%;"> (<a href="ITTage.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">495</td>
+            <td class="headerCovTableEntry">578</td>
+            <td class="headerCovTableEntryMed">85.6 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="ITTage.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/ITTage.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/ITTage.sv.func.html
new file mode 100644
index 0000000..877c0c9
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/ITTage.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/ITTage.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - ITTage.sv<span style="font-size: 80%;"> (<a href="ITTage.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">495</td>
+            <td class="headerCovTableEntry">578</td>
+            <td class="headerCovTableEntryMed">85.6 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="ITTage.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/ITTage.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/ITTage.sv.gcov.html
new file mode 100644
index 0000000..78ef1e1
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/ITTage.sv.gcov.html
@@ -0,0 +1,1345 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/ITTage.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - ITTage.sv<span style="font-size: 80%;"> (source / <a href="ITTage.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">495</td>
+            <td class="headerCovTableEntry">578</td>
+            <td class="headerCovTableEntryMed">85.6 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : module ITTage(</a>
+<a name="59"><span class="lineNum">      59 </span><span class="lineCov">     127786 :   input          clock,</span></a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">         62 :   input          reset,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">      35066 :   input  [40:0]  io_in_bits_s0_pc_3,</span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">        564 :   input  [7:0]   io_in_bits_folded_hist_3_hist_14_folded_hist,</span></a>
+<a name="63"><span class="lineNum">      63 </span><span class="lineCov">        989 :   input  [8:0]   io_in_bits_folded_hist_3_hist_13_folded_hist,</span></a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">        474 :   input  [3:0]   io_in_bits_folded_hist_3_hist_12_folded_hist,</span></a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">        998 :   input  [8:0]   io_in_bits_folded_hist_3_hist_10_folded_hist,</span></a>
+<a name="66"><span class="lineNum">      66 </span><span class="lineCov">        987 :   input  [8:0]   io_in_bits_folded_hist_3_hist_6_folded_hist,</span></a>
+<a name="67"><span class="lineNum">      67 </span><span class="lineCov">        602 :   input  [7:0]   io_in_bits_folded_hist_3_hist_4_folded_hist,</span></a>
+<a name="68"><span class="lineNum">      68 </span><span class="lineCov">        517 :   input  [7:0]   io_in_bits_folded_hist_3_hist_3_folded_hist,</span></a>
+<a name="69"><span class="lineNum">      69 </span><span class="lineCov">        811 :   input  [7:0]   io_in_bits_folded_hist_3_hist_2_folded_hist,</span></a>
+<a name="70"><span class="lineNum">      70 </span><span class="lineCov">         79 :   input          io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_0,</span></a>
+<a name="71"><span class="lineNum">      71 </span><span class="lineCov">         69 :   input          io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_1,</span></a>
+<a name="72"><span class="lineNum">      72 </span><span class="lineCov">         31 :   input          io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_0,</span></a>
+<a name="73"><span class="lineNum">      73 </span><span class="lineCov">         30 :   input          io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_1,</span></a>
+<a name="74"><span class="lineNum">      74 </span><span class="lineCov">       1189 :   input  [40:0]  io_in_bits_resp_in_0_s2_full_pred_0_targets_0,</span></a>
+<a name="75"><span class="lineNum">      75 </span><span class="lineCov">       1202 :   input  [40:0]  io_in_bits_resp_in_0_s2_full_pred_0_targets_1,</span></a>
+<a name="76"><span class="lineNum">      76 </span><span class="lineCov">       1202 :   input  [40:0]  io_in_bits_resp_in_0_s2_full_pred_0_jalr_target,</span></a>
+<a name="77"><span class="lineNum">      77 </span><span class="lineCov">        116 :   input  [3:0]   io_in_bits_resp_in_0_s2_full_pred_0_offsets_0,</span></a>
+<a name="78"><span class="lineNum">      78 </span><span class="lineCov">        107 :   input  [3:0]   io_in_bits_resp_in_0_s2_full_pred_0_offsets_1,</span></a>
+<a name="79"><span class="lineNum">      79 </span><span class="lineCov">       9456 :   input  [40:0]  io_in_bits_resp_in_0_s2_full_pred_0_fallThroughAddr,</span></a>
+<a name="80"><span class="lineNum">      80 </span><span class="lineCov">         31 :   input          io_in_bits_resp_in_0_s2_full_pred_0_is_br_sharing,</span></a>
+<a name="81"><span class="lineNum">      81 </span><span class="lineCov">         18 :   input          io_in_bits_resp_in_0_s2_full_pred_0_hit,</span></a>
+<a name="82"><span class="lineNum">      82 </span><span class="lineCov">         59 :   input          io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_0,</span></a>
+<a name="83"><span class="lineNum">      83 </span><span class="lineCov">         71 :   input          io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_1,</span></a>
+<a name="84"><span class="lineNum">      84 </span><span class="lineCov">         24 :   input          io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_0,</span></a>
+<a name="85"><span class="lineNum">      85 </span><span class="lineCov">         24 :   input          io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_1,</span></a>
+<a name="86"><span class="lineNum">      86 </span><span class="lineCov">       1278 :   input  [40:0]  io_in_bits_resp_in_0_s2_full_pred_1_targets_0,</span></a>
+<a name="87"><span class="lineNum">      87 </span><span class="lineCov">       1114 :   input  [40:0]  io_in_bits_resp_in_0_s2_full_pred_1_targets_1,</span></a>
+<a name="88"><span class="lineNum">      88 </span><span class="lineCov">       1114 :   input  [40:0]  io_in_bits_resp_in_0_s2_full_pred_1_jalr_target,</span></a>
+<a name="89"><span class="lineNum">      89 </span><span class="lineCov">        108 :   input  [3:0]   io_in_bits_resp_in_0_s2_full_pred_1_offsets_0,</span></a>
+<a name="90"><span class="lineNum">      90 </span><span class="lineCov">        119 :   input  [3:0]   io_in_bits_resp_in_0_s2_full_pred_1_offsets_1,</span></a>
+<a name="91"><span class="lineNum">      91 </span><span class="lineCov">       9458 :   input  [40:0]  io_in_bits_resp_in_0_s2_full_pred_1_fallThroughAddr,</span></a>
+<a name="92"><span class="lineNum">      92 </span><span class="lineCov">         17 :   input          io_in_bits_resp_in_0_s2_full_pred_1_is_br_sharing,</span></a>
+<a name="93"><span class="lineNum">      93 </span><span class="lineCov">         25 :   input          io_in_bits_resp_in_0_s2_full_pred_1_hit,</span></a>
+<a name="94"><span class="lineNum">      94 </span><span class="lineCov">         72 :   input          io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_0,</span></a>
+<a name="95"><span class="lineNum">      95 </span><span class="lineCov">         58 :   input          io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_1,</span></a>
+<a name="96"><span class="lineNum">      96 </span><span class="lineCov">         31 :   input          io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_0,</span></a>
+<a name="97"><span class="lineNum">      97 </span><span class="lineCov">         28 :   input          io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_1,</span></a>
+<a name="98"><span class="lineNum">      98 </span><span class="lineCov">       1211 :   input  [40:0]  io_in_bits_resp_in_0_s2_full_pred_2_targets_0,</span></a>
+<a name="99"><span class="lineNum">      99 </span><span class="lineCov">       1198 :   input  [40:0]  io_in_bits_resp_in_0_s2_full_pred_2_targets_1,</span></a>
+<a name="100"><span class="lineNum">     100 </span><span class="lineCov">       1198 :   input  [40:0]  io_in_bits_resp_in_0_s2_full_pred_2_jalr_target,</span></a>
+<a name="101"><span class="lineNum">     101 </span><span class="lineCov">        114 :   input  [3:0]   io_in_bits_resp_in_0_s2_full_pred_2_offsets_0,</span></a>
+<a name="102"><span class="lineNum">     102 </span><span class="lineCov">        120 :   input  [3:0]   io_in_bits_resp_in_0_s2_full_pred_2_offsets_1,</span></a>
+<a name="103"><span class="lineNum">     103 </span><span class="lineCov">       9409 :   input  [40:0]  io_in_bits_resp_in_0_s2_full_pred_2_fallThroughAddr,</span></a>
+<a name="104"><span class="lineNum">     104 </span><span class="lineCov">         23 :   input          io_in_bits_resp_in_0_s2_full_pred_2_is_jalr,</span></a>
+<a name="105"><span class="lineNum">     105 </span><span class="lineCov">         21 :   input          io_in_bits_resp_in_0_s2_full_pred_2_is_call,</span></a>
+<a name="106"><span class="lineNum">     106 </span><span class="lineCov">         26 :   input          io_in_bits_resp_in_0_s2_full_pred_2_is_ret,</span></a>
+<a name="107"><span class="lineNum">     107 </span><span class="lineCov">         25 :   input          io_in_bits_resp_in_0_s2_full_pred_2_last_may_be_rvi_call,</span></a>
+<a name="108"><span class="lineNum">     108 </span><span class="lineCov">         23 :   input          io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing,</span></a>
+<a name="109"><span class="lineNum">     109 </span><span class="lineCov">         29 :   input          io_in_bits_resp_in_0_s2_full_pred_2_hit,</span></a>
+<a name="110"><span class="lineNum">     110 </span><span class="lineCov">         79 :   input          io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_0,</span></a>
+<a name="111"><span class="lineNum">     111 </span><span class="lineCov">         76 :   input          io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_1,</span></a>
+<a name="112"><span class="lineNum">     112 </span><span class="lineCov">         27 :   input          io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_0,</span></a>
+<a name="113"><span class="lineNum">     113 </span><span class="lineCov">         30 :   input          io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_1,</span></a>
+<a name="114"><span class="lineNum">     114 </span><span class="lineCov">       1252 :   input  [40:0]  io_in_bits_resp_in_0_s2_full_pred_3_targets_0,</span></a>
+<a name="115"><span class="lineNum">     115 </span><span class="lineCov">       1179 :   input  [40:0]  io_in_bits_resp_in_0_s2_full_pred_3_targets_1,</span></a>
+<a name="116"><span class="lineNum">     116 </span><span class="lineCov">       1179 :   input  [40:0]  io_in_bits_resp_in_0_s2_full_pred_3_jalr_target,</span></a>
+<a name="117"><span class="lineNum">     117 </span><span class="lineCov">        119 :   input  [3:0]   io_in_bits_resp_in_0_s2_full_pred_3_offsets_0,</span></a>
+<a name="118"><span class="lineNum">     118 </span><span class="lineCov">        105 :   input  [3:0]   io_in_bits_resp_in_0_s2_full_pred_3_offsets_1,</span></a>
+<a name="119"><span class="lineNum">     119 </span><span class="lineCov">       9476 :   input  [40:0]  io_in_bits_resp_in_0_s2_full_pred_3_fallThroughAddr,</span></a>
+<a name="120"><span class="lineNum">     120 </span><span class="lineCov">         33 :   input          io_in_bits_resp_in_0_s2_full_pred_3_fallThroughErr,</span></a>
+<a name="121"><span class="lineNum">     121 </span><span class="lineCov">         22 :   input          io_in_bits_resp_in_0_s2_full_pred_3_is_br_sharing,</span></a>
+<a name="122"><span class="lineNum">     122 </span><span class="lineCov">         18 :   input          io_in_bits_resp_in_0_s2_full_pred_3_hit,</span></a>
+<a name="123"><span class="lineNum">     123 </span><span class="lineCov">         82 :   input          io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_0,</span></a>
+<a name="124"><span class="lineNum">     124 </span><span class="lineCov">         70 :   input          io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_1,</span></a>
+<a name="125"><span class="lineNum">     125 </span><span class="lineCov">         30 :   input          io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_0,</span></a>
+<a name="126"><span class="lineNum">     126 </span><span class="lineCov">         33 :   input          io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_1,</span></a>
+<a name="127"><span class="lineNum">     127 </span><span class="lineCov">       1241 :   input  [40:0]  io_in_bits_resp_in_0_s3_full_pred_0_targets_0,</span></a>
+<a name="128"><span class="lineNum">     128 </span><span class="lineCov">       1247 :   input  [40:0]  io_in_bits_resp_in_0_s3_full_pred_0_targets_1,</span></a>
+<a name="129"><span class="lineNum">     129 </span><span class="lineCov">       1247 :   input  [40:0]  io_in_bits_resp_in_0_s3_full_pred_0_jalr_target,</span></a>
+<a name="130"><span class="lineNum">     130 </span><span class="lineCov">       9423 :   input  [40:0]  io_in_bits_resp_in_0_s3_full_pred_0_fallThroughAddr,</span></a>
+<a name="131"><span class="lineNum">     131 </span><span class="lineCov">         39 :   input          io_in_bits_resp_in_0_s3_full_pred_0_fallThroughErr,</span></a>
+<a name="132"><span class="lineNum">     132 </span><span class="lineCov">         26 :   input          io_in_bits_resp_in_0_s3_full_pred_0_is_br_sharing,</span></a>
+<a name="133"><span class="lineNum">     133 </span><span class="lineCov">         24 :   input          io_in_bits_resp_in_0_s3_full_pred_0_hit,</span></a>
+<a name="134"><span class="lineNum">     134 </span><span class="lineCov">         80 :   input          io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_0,</span></a>
+<a name="135"><span class="lineNum">     135 </span><span class="lineCov">         75 :   input          io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_1,</span></a>
+<a name="136"><span class="lineNum">     136 </span><span class="lineCov">         30 :   input          io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_0,</span></a>
+<a name="137"><span class="lineNum">     137 </span><span class="lineCov">         39 :   input          io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_1,</span></a>
+<a name="138"><span class="lineNum">     138 </span><span class="lineCov">       1262 :   input  [40:0]  io_in_bits_resp_in_0_s3_full_pred_1_targets_0,</span></a>
+<a name="139"><span class="lineNum">     139 </span><span class="lineCov">       1289 :   input  [40:0]  io_in_bits_resp_in_0_s3_full_pred_1_targets_1,</span></a>
+<a name="140"><span class="lineNum">     140 </span><span class="lineCov">       1289 :   input  [40:0]  io_in_bits_resp_in_0_s3_full_pred_1_jalr_target,</span></a>
+<a name="141"><span class="lineNum">     141 </span><span class="lineCov">       9377 :   input  [40:0]  io_in_bits_resp_in_0_s3_full_pred_1_fallThroughAddr,</span></a>
+<a name="142"><span class="lineNum">     142 </span><span class="lineCov">         35 :   input          io_in_bits_resp_in_0_s3_full_pred_1_fallThroughErr,</span></a>
+<a name="143"><span class="lineNum">     143 </span><span class="lineCov">         24 :   input          io_in_bits_resp_in_0_s3_full_pred_1_is_br_sharing,</span></a>
+<a name="144"><span class="lineNum">     144 </span><span class="lineCov">         33 :   input          io_in_bits_resp_in_0_s3_full_pred_1_hit,</span></a>
+<a name="145"><span class="lineNum">     145 </span><span class="lineCov">         86 :   input          io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_0,</span></a>
+<a name="146"><span class="lineNum">     146 </span><span class="lineCov">         70 :   input          io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_1,</span></a>
+<a name="147"><span class="lineNum">     147 </span><span class="lineCov">         26 :   input          io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_0,</span></a>
+<a name="148"><span class="lineNum">     148 </span><span class="lineCov">         30 :   input          io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_1,</span></a>
+<a name="149"><span class="lineNum">     149 </span><span class="lineCov">       1286 :   input  [40:0]  io_in_bits_resp_in_0_s3_full_pred_2_targets_0,</span></a>
+<a name="150"><span class="lineNum">     150 </span><span class="lineCov">       1331 :   input  [40:0]  io_in_bits_resp_in_0_s3_full_pred_2_targets_1,</span></a>
+<a name="151"><span class="lineNum">     151 </span><span class="lineCov">       1331 :   input  [40:0]  io_in_bits_resp_in_0_s3_full_pred_2_jalr_target,</span></a>
+<a name="152"><span class="lineNum">     152 </span><span class="lineCov">       9424 :   input  [40:0]  io_in_bits_resp_in_0_s3_full_pred_2_fallThroughAddr,</span></a>
+<a name="153"><span class="lineNum">     153 </span><span class="lineCov">         35 :   input          io_in_bits_resp_in_0_s3_full_pred_2_fallThroughErr,</span></a>
+<a name="154"><span class="lineNum">     154 </span><span class="lineCov">         23 :   input          io_in_bits_resp_in_0_s3_full_pred_2_is_jalr,</span></a>
+<a name="155"><span class="lineNum">     155 </span><span class="lineCov">         23 :   input          io_in_bits_resp_in_0_s3_full_pred_2_is_call,</span></a>
+<a name="156"><span class="lineNum">     156 </span><span class="lineCov">         24 :   input          io_in_bits_resp_in_0_s3_full_pred_2_is_ret,</span></a>
+<a name="157"><span class="lineNum">     157 </span><span class="lineCov">         21 :   input          io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing,</span></a>
+<a name="158"><span class="lineNum">     158 </span><span class="lineCov">         29 :   input          io_in_bits_resp_in_0_s3_full_pred_2_hit,</span></a>
+<a name="159"><span class="lineNum">     159 </span><span class="lineCov">         75 :   input          io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_0,</span></a>
+<a name="160"><span class="lineNum">     160 </span><span class="lineCov">         76 :   input          io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_1,</span></a>
+<a name="161"><span class="lineNum">     161 </span><span class="lineCov">         41 :   input          io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_0,</span></a>
+<a name="162"><span class="lineNum">     162 </span><span class="lineCov">         42 :   input          io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_1,</span></a>
+<a name="163"><span class="lineNum">     163 </span><span class="lineCov">       1231 :   input  [40:0]  io_in_bits_resp_in_0_s3_full_pred_3_targets_0,</span></a>
+<a name="164"><span class="lineNum">     164 </span><span class="lineCov">       1247 :   input  [40:0]  io_in_bits_resp_in_0_s3_full_pred_3_targets_1,</span></a>
+<a name="165"><span class="lineNum">     165 </span><span class="lineCov">       1247 :   input  [40:0]  io_in_bits_resp_in_0_s3_full_pred_3_jalr_target,</span></a>
+<a name="166"><span class="lineNum">     166 </span><span class="lineCov">        128 :   input  [3:0]   io_in_bits_resp_in_0_s3_full_pred_3_offsets_0,</span></a>
+<a name="167"><span class="lineNum">     167 </span><span class="lineCov">        137 :   input  [3:0]   io_in_bits_resp_in_0_s3_full_pred_3_offsets_1,</span></a>
+<a name="168"><span class="lineNum">     168 </span><span class="lineCov">       9391 :   input  [40:0]  io_in_bits_resp_in_0_s3_full_pred_3_fallThroughAddr,</span></a>
+<a name="169"><span class="lineNum">     169 </span><span class="lineCov">         41 :   input          io_in_bits_resp_in_0_s3_full_pred_3_fallThroughErr,</span></a>
+<a name="170"><span class="lineNum">     170 </span><span class="lineCov">         30 :   input          io_in_bits_resp_in_0_s3_full_pred_3_is_br_sharing,</span></a>
+<a name="171"><span class="lineNum">     171 </span><span class="lineCov">         27 :   input          io_in_bits_resp_in_0_s3_full_pred_3_hit,</span></a>
+<a name="172"><span class="lineNum">     172 </span><span class="lineCov">         29 :   input          io_in_bits_resp_in_0_last_stage_ftb_entry_valid,</span></a>
+<a name="173"><span class="lineNum">     173 </span><span class="lineCov">        126 :   input  [3:0]   io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_offset,</span></a>
+<a name="174"><span class="lineNum">     174 </span><span class="lineCov">        409 :   input  [11:0]  io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_lower,</span></a>
+<a name="175"><span class="lineNum">     175 </span><span class="lineCov">         65 :   input  [1:0]   io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_tarStat,</span></a>
+<a name="176"><span class="lineNum">     176 </span><span class="lineCov">         32 :   input          io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_sharing,</span></a>
+<a name="177"><span class="lineNum">     177 </span><span class="lineCov">         30 :   input          io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_valid,</span></a>
+<a name="178"><span class="lineNum">     178 </span><span class="lineCov">        116 :   input  [3:0]   io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_offset,</span></a>
+<a name="179"><span class="lineNum">     179 </span><span class="lineCov">        705 :   input  [19:0]  io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_lower,</span></a>
+<a name="180"><span class="lineNum">     180 </span><span class="lineCov">         65 :   input  [1:0]   io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_tarStat,</span></a>
+<a name="181"><span class="lineNum">     181 </span><span class="lineCov">         37 :   input          io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_sharing,</span></a>
+<a name="182"><span class="lineNum">     182 </span><span class="lineCov">         33 :   input          io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_valid,</span></a>
+<a name="183"><span class="lineNum">     183 </span><span class="lineCov">        142 :   input  [3:0]   io_in_bits_resp_in_0_last_stage_ftb_entry_pftAddr,</span></a>
+<a name="184"><span class="lineNum">     184 </span><span class="lineCov">         35 :   input          io_in_bits_resp_in_0_last_stage_ftb_entry_carry,</span></a>
+<a name="185"><span class="lineNum">     185 </span><span class="lineCov">         34 :   input          io_in_bits_resp_in_0_last_stage_ftb_entry_isCall,</span></a>
+<a name="186"><span class="lineNum">     186 </span><span class="lineCov">         33 :   input          io_in_bits_resp_in_0_last_stage_ftb_entry_isRet,</span></a>
+<a name="187"><span class="lineNum">     187 </span><span class="lineCov">         36 :   input          io_in_bits_resp_in_0_last_stage_ftb_entry_isJalr,</span></a>
+<a name="188"><span class="lineNum">     188 </span><span class="lineCov">         31 :   input          io_in_bits_resp_in_0_last_stage_ftb_entry_last_may_be_rvi_call,</span></a>
+<a name="189"><span class="lineNum">     189 </span><span class="lineCov">         27 :   input          io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_0,</span></a>
+<a name="190"><span class="lineNum">     190 </span><span class="lineCov">         33 :   input          io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_1,</span></a>
+<a name="191"><span class="lineNum">     191 </span><span class="lineCov">         79 :   output         io_out_s2_full_pred_0_br_taken_mask_0,</span></a>
+<a name="192"><span class="lineNum">     192 </span><span class="lineCov">         69 :   output         io_out_s2_full_pred_0_br_taken_mask_1,</span></a>
+<a name="193"><span class="lineNum">     193 </span><span class="lineCov">         31 :   output         io_out_s2_full_pred_0_slot_valids_0,</span></a>
+<a name="194"><span class="lineNum">     194 </span><span class="lineCov">         30 :   output         io_out_s2_full_pred_0_slot_valids_1,</span></a>
+<a name="195"><span class="lineNum">     195 </span><span class="lineCov">       1189 :   output [40:0]  io_out_s2_full_pred_0_targets_0,</span></a>
+<a name="196"><span class="lineNum">     196 </span><span class="lineCov">       1202 :   output [40:0]  io_out_s2_full_pred_0_targets_1,</span></a>
+<a name="197"><span class="lineNum">     197 </span><span class="lineCov">       1202 :   output [40:0]  io_out_s2_full_pred_0_jalr_target,</span></a>
+<a name="198"><span class="lineNum">     198 </span><span class="lineCov">        116 :   output [3:0]   io_out_s2_full_pred_0_offsets_0,</span></a>
+<a name="199"><span class="lineNum">     199 </span><span class="lineCov">        107 :   output [3:0]   io_out_s2_full_pred_0_offsets_1,</span></a>
+<a name="200"><span class="lineNum">     200 </span><span class="lineCov">       9456 :   output [40:0]  io_out_s2_full_pred_0_fallThroughAddr,</span></a>
+<a name="201"><span class="lineNum">     201 </span><span class="lineCov">         31 :   output         io_out_s2_full_pred_0_is_br_sharing,</span></a>
+<a name="202"><span class="lineNum">     202 </span><span class="lineCov">         18 :   output         io_out_s2_full_pred_0_hit,</span></a>
+<a name="203"><span class="lineNum">     203 </span><span class="lineCov">         59 :   output         io_out_s2_full_pred_1_br_taken_mask_0,</span></a>
+<a name="204"><span class="lineNum">     204 </span><span class="lineCov">         71 :   output         io_out_s2_full_pred_1_br_taken_mask_1,</span></a>
+<a name="205"><span class="lineNum">     205 </span><span class="lineCov">         24 :   output         io_out_s2_full_pred_1_slot_valids_0,</span></a>
+<a name="206"><span class="lineNum">     206 </span><span class="lineCov">         24 :   output         io_out_s2_full_pred_1_slot_valids_1,</span></a>
+<a name="207"><span class="lineNum">     207 </span><span class="lineCov">       1278 :   output [40:0]  io_out_s2_full_pred_1_targets_0,</span></a>
+<a name="208"><span class="lineNum">     208 </span><span class="lineCov">       1114 :   output [40:0]  io_out_s2_full_pred_1_targets_1,</span></a>
+<a name="209"><span class="lineNum">     209 </span><span class="lineCov">       1114 :   output [40:0]  io_out_s2_full_pred_1_jalr_target,</span></a>
+<a name="210"><span class="lineNum">     210 </span><span class="lineCov">        108 :   output [3:0]   io_out_s2_full_pred_1_offsets_0,</span></a>
+<a name="211"><span class="lineNum">     211 </span><span class="lineCov">        119 :   output [3:0]   io_out_s2_full_pred_1_offsets_1,</span></a>
+<a name="212"><span class="lineNum">     212 </span><span class="lineCov">       9458 :   output [40:0]  io_out_s2_full_pred_1_fallThroughAddr,</span></a>
+<a name="213"><span class="lineNum">     213 </span><span class="lineCov">         17 :   output         io_out_s2_full_pred_1_is_br_sharing,</span></a>
+<a name="214"><span class="lineNum">     214 </span><span class="lineCov">         25 :   output         io_out_s2_full_pred_1_hit,</span></a>
+<a name="215"><span class="lineNum">     215 </span><span class="lineCov">         72 :   output         io_out_s2_full_pred_2_br_taken_mask_0,</span></a>
+<a name="216"><span class="lineNum">     216 </span><span class="lineCov">         58 :   output         io_out_s2_full_pred_2_br_taken_mask_1,</span></a>
+<a name="217"><span class="lineNum">     217 </span><span class="lineCov">         31 :   output         io_out_s2_full_pred_2_slot_valids_0,</span></a>
+<a name="218"><span class="lineNum">     218 </span><span class="lineCov">         28 :   output         io_out_s2_full_pred_2_slot_valids_1,</span></a>
+<a name="219"><span class="lineNum">     219 </span><span class="lineCov">       1211 :   output [40:0]  io_out_s2_full_pred_2_targets_0,</span></a>
+<a name="220"><span class="lineNum">     220 </span><span class="lineCov">       1198 :   output [40:0]  io_out_s2_full_pred_2_targets_1,</span></a>
+<a name="221"><span class="lineNum">     221 </span><span class="lineCov">       1198 :   output [40:0]  io_out_s2_full_pred_2_jalr_target,</span></a>
+<a name="222"><span class="lineNum">     222 </span><span class="lineCov">        114 :   output [3:0]   io_out_s2_full_pred_2_offsets_0,</span></a>
+<a name="223"><span class="lineNum">     223 </span><span class="lineCov">        120 :   output [3:0]   io_out_s2_full_pred_2_offsets_1,</span></a>
+<a name="224"><span class="lineNum">     224 </span><span class="lineCov">       9409 :   output [40:0]  io_out_s2_full_pred_2_fallThroughAddr,</span></a>
+<a name="225"><span class="lineNum">     225 </span><span class="lineCov">         23 :   output         io_out_s2_full_pred_2_is_jalr,</span></a>
+<a name="226"><span class="lineNum">     226 </span><span class="lineCov">         21 :   output         io_out_s2_full_pred_2_is_call,</span></a>
+<a name="227"><span class="lineNum">     227 </span><span class="lineCov">         26 :   output         io_out_s2_full_pred_2_is_ret,</span></a>
+<a name="228"><span class="lineNum">     228 </span><span class="lineCov">         25 :   output         io_out_s2_full_pred_2_last_may_be_rvi_call,</span></a>
+<a name="229"><span class="lineNum">     229 </span><span class="lineCov">         23 :   output         io_out_s2_full_pred_2_is_br_sharing,</span></a>
+<a name="230"><span class="lineNum">     230 </span><span class="lineCov">         29 :   output         io_out_s2_full_pred_2_hit,</span></a>
+<a name="231"><span class="lineNum">     231 </span><span class="lineCov">         79 :   output         io_out_s2_full_pred_3_br_taken_mask_0,</span></a>
+<a name="232"><span class="lineNum">     232 </span><span class="lineCov">         76 :   output         io_out_s2_full_pred_3_br_taken_mask_1,</span></a>
+<a name="233"><span class="lineNum">     233 </span><span class="lineCov">         27 :   output         io_out_s2_full_pred_3_slot_valids_0,</span></a>
+<a name="234"><span class="lineNum">     234 </span><span class="lineCov">         30 :   output         io_out_s2_full_pred_3_slot_valids_1,</span></a>
+<a name="235"><span class="lineNum">     235 </span><span class="lineCov">       1252 :   output [40:0]  io_out_s2_full_pred_3_targets_0,</span></a>
+<a name="236"><span class="lineNum">     236 </span><span class="lineCov">       1179 :   output [40:0]  io_out_s2_full_pred_3_targets_1,</span></a>
+<a name="237"><span class="lineNum">     237 </span><span class="lineCov">       1179 :   output [40:0]  io_out_s2_full_pred_3_jalr_target,</span></a>
+<a name="238"><span class="lineNum">     238 </span><span class="lineCov">        119 :   output [3:0]   io_out_s2_full_pred_3_offsets_0,</span></a>
+<a name="239"><span class="lineNum">     239 </span><span class="lineCov">        105 :   output [3:0]   io_out_s2_full_pred_3_offsets_1,</span></a>
+<a name="240"><span class="lineNum">     240 </span><span class="lineCov">       9476 :   output [40:0]  io_out_s2_full_pred_3_fallThroughAddr,</span></a>
+<a name="241"><span class="lineNum">     241 </span><span class="lineCov">         33 :   output         io_out_s2_full_pred_3_fallThroughErr,</span></a>
+<a name="242"><span class="lineNum">     242 </span><span class="lineCov">         22 :   output         io_out_s2_full_pred_3_is_br_sharing,</span></a>
+<a name="243"><span class="lineNum">     243 </span><span class="lineCov">         18 :   output         io_out_s2_full_pred_3_hit,</span></a>
+<a name="244"><span class="lineNum">     244 </span><span class="lineCov">         82 :   output         io_out_s3_full_pred_0_br_taken_mask_0,</span></a>
+<a name="245"><span class="lineNum">     245 </span><span class="lineCov">         70 :   output         io_out_s3_full_pred_0_br_taken_mask_1,</span></a>
+<a name="246"><span class="lineNum">     246 </span><span class="lineCov">         30 :   output         io_out_s3_full_pred_0_slot_valids_0,</span></a>
+<a name="247"><span class="lineNum">     247 </span><span class="lineCov">         33 :   output         io_out_s3_full_pred_0_slot_valids_1,</span></a>
+<a name="248"><span class="lineNum">     248 </span><span class="lineCov">       1241 :   output [40:0]  io_out_s3_full_pred_0_targets_0,</span></a>
+<a name="249"><span class="lineNum">     249 </span><span class="lineCov">       1247 :   output [40:0]  io_out_s3_full_pred_0_targets_1,</span></a>
+<a name="250"><span class="lineNum">     250 </span><span class="lineCov">       1318 :   output [40:0]  io_out_s3_full_pred_0_jalr_target,</span></a>
+<a name="251"><span class="lineNum">     251 </span><span class="lineCov">       9423 :   output [40:0]  io_out_s3_full_pred_0_fallThroughAddr,</span></a>
+<a name="252"><span class="lineNum">     252 </span><span class="lineCov">         39 :   output         io_out_s3_full_pred_0_fallThroughErr,</span></a>
+<a name="253"><span class="lineNum">     253 </span><span class="lineCov">         26 :   output         io_out_s3_full_pred_0_is_br_sharing,</span></a>
+<a name="254"><span class="lineNum">     254 </span><span class="lineCov">         24 :   output         io_out_s3_full_pred_0_hit,</span></a>
+<a name="255"><span class="lineNum">     255 </span><span class="lineCov">         80 :   output         io_out_s3_full_pred_1_br_taken_mask_0,</span></a>
+<a name="256"><span class="lineNum">     256 </span><span class="lineCov">         75 :   output         io_out_s3_full_pred_1_br_taken_mask_1,</span></a>
+<a name="257"><span class="lineNum">     257 </span><span class="lineCov">         30 :   output         io_out_s3_full_pred_1_slot_valids_0,</span></a>
+<a name="258"><span class="lineNum">     258 </span><span class="lineCov">         39 :   output         io_out_s3_full_pred_1_slot_valids_1,</span></a>
+<a name="259"><span class="lineNum">     259 </span><span class="lineCov">       1262 :   output [40:0]  io_out_s3_full_pred_1_targets_0,</span></a>
+<a name="260"><span class="lineNum">     260 </span><span class="lineCov">       1289 :   output [40:0]  io_out_s3_full_pred_1_targets_1,</span></a>
+<a name="261"><span class="lineNum">     261 </span><span class="lineCov">       1313 :   output [40:0]  io_out_s3_full_pred_1_jalr_target,</span></a>
+<a name="262"><span class="lineNum">     262 </span><span class="lineCov">       9377 :   output [40:0]  io_out_s3_full_pred_1_fallThroughAddr,</span></a>
+<a name="263"><span class="lineNum">     263 </span><span class="lineCov">         35 :   output         io_out_s3_full_pred_1_fallThroughErr,</span></a>
+<a name="264"><span class="lineNum">     264 </span><span class="lineCov">         24 :   output         io_out_s3_full_pred_1_is_br_sharing,</span></a>
+<a name="265"><span class="lineNum">     265 </span><span class="lineCov">         33 :   output         io_out_s3_full_pred_1_hit,</span></a>
+<a name="266"><span class="lineNum">     266 </span><span class="lineCov">         86 :   output         io_out_s3_full_pred_2_br_taken_mask_0,</span></a>
+<a name="267"><span class="lineNum">     267 </span><span class="lineCov">         70 :   output         io_out_s3_full_pred_2_br_taken_mask_1,</span></a>
+<a name="268"><span class="lineNum">     268 </span><span class="lineCov">         26 :   output         io_out_s3_full_pred_2_slot_valids_0,</span></a>
+<a name="269"><span class="lineNum">     269 </span><span class="lineCov">         30 :   output         io_out_s3_full_pred_2_slot_valids_1,</span></a>
+<a name="270"><span class="lineNum">     270 </span><span class="lineCov">       1286 :   output [40:0]  io_out_s3_full_pred_2_targets_0,</span></a>
+<a name="271"><span class="lineNum">     271 </span><span class="lineCov">       1331 :   output [40:0]  io_out_s3_full_pred_2_targets_1,</span></a>
+<a name="272"><span class="lineNum">     272 </span><span class="lineCov">       1351 :   output [40:0]  io_out_s3_full_pred_2_jalr_target,</span></a>
+<a name="273"><span class="lineNum">     273 </span><span class="lineCov">       9424 :   output [40:0]  io_out_s3_full_pred_2_fallThroughAddr,</span></a>
+<a name="274"><span class="lineNum">     274 </span><span class="lineCov">         35 :   output         io_out_s3_full_pred_2_fallThroughErr,</span></a>
+<a name="275"><span class="lineNum">     275 </span><span class="lineCov">         23 :   output         io_out_s3_full_pred_2_is_jalr,</span></a>
+<a name="276"><span class="lineNum">     276 </span><span class="lineCov">         23 :   output         io_out_s3_full_pred_2_is_call,</span></a>
+<a name="277"><span class="lineNum">     277 </span><span class="lineCov">         24 :   output         io_out_s3_full_pred_2_is_ret,</span></a>
+<a name="278"><span class="lineNum">     278 </span><span class="lineCov">         21 :   output         io_out_s3_full_pred_2_is_br_sharing,</span></a>
+<a name="279"><span class="lineNum">     279 </span><span class="lineCov">         29 :   output         io_out_s3_full_pred_2_hit,</span></a>
+<a name="280"><span class="lineNum">     280 </span><span class="lineCov">         75 :   output         io_out_s3_full_pred_3_br_taken_mask_0,</span></a>
+<a name="281"><span class="lineNum">     281 </span><span class="lineCov">         76 :   output         io_out_s3_full_pred_3_br_taken_mask_1,</span></a>
+<a name="282"><span class="lineNum">     282 </span><span class="lineCov">         41 :   output         io_out_s3_full_pred_3_slot_valids_0,</span></a>
+<a name="283"><span class="lineNum">     283 </span><span class="lineCov">         42 :   output         io_out_s3_full_pred_3_slot_valids_1,</span></a>
+<a name="284"><span class="lineNum">     284 </span><span class="lineCov">       1231 :   output [40:0]  io_out_s3_full_pred_3_targets_0,</span></a>
+<a name="285"><span class="lineNum">     285 </span><span class="lineCov">       1247 :   output [40:0]  io_out_s3_full_pred_3_targets_1,</span></a>
+<a name="286"><span class="lineNum">     286 </span><span class="lineCov">       1327 :   output [40:0]  io_out_s3_full_pred_3_jalr_target,</span></a>
+<a name="287"><span class="lineNum">     287 </span><span class="lineCov">        128 :   output [3:0]   io_out_s3_full_pred_3_offsets_0,</span></a>
+<a name="288"><span class="lineNum">     288 </span><span class="lineCov">        137 :   output [3:0]   io_out_s3_full_pred_3_offsets_1,</span></a>
+<a name="289"><span class="lineNum">     289 </span><span class="lineCov">       9391 :   output [40:0]  io_out_s3_full_pred_3_fallThroughAddr,</span></a>
+<a name="290"><span class="lineNum">     290 </span><span class="lineCov">         41 :   output         io_out_s3_full_pred_3_fallThroughErr,</span></a>
+<a name="291"><span class="lineNum">     291 </span><span class="lineCov">         30 :   output         io_out_s3_full_pred_3_is_br_sharing,</span></a>
+<a name="292"><span class="lineNum">     292 </span><span class="lineCov">         27 :   output         io_out_s3_full_pred_3_hit,</span></a>
+<a name="293"><span class="lineNum">     293 </span><span class="lineCov">       9084 :   output [222:0] io_out_last_stage_meta,</span></a>
+<a name="294"><span class="lineNum">     294 </span><span class="lineCov">         29 :   output         io_out_last_stage_ftb_entry_valid,</span></a>
+<a name="295"><span class="lineNum">     295 </span><span class="lineCov">        126 :   output [3:0]   io_out_last_stage_ftb_entry_brSlots_0_offset,</span></a>
+<a name="296"><span class="lineNum">     296 </span><span class="lineCov">        409 :   output [11:0]  io_out_last_stage_ftb_entry_brSlots_0_lower,</span></a>
+<a name="297"><span class="lineNum">     297 </span><span class="lineCov">         65 :   output [1:0]   io_out_last_stage_ftb_entry_brSlots_0_tarStat,</span></a>
+<a name="298"><span class="lineNum">     298 </span><span class="lineCov">         32 :   output         io_out_last_stage_ftb_entry_brSlots_0_sharing,</span></a>
+<a name="299"><span class="lineNum">     299 </span><span class="lineCov">         30 :   output         io_out_last_stage_ftb_entry_brSlots_0_valid,</span></a>
+<a name="300"><span class="lineNum">     300 </span><span class="lineCov">        116 :   output [3:0]   io_out_last_stage_ftb_entry_tailSlot_offset,</span></a>
+<a name="301"><span class="lineNum">     301 </span><span class="lineCov">        705 :   output [19:0]  io_out_last_stage_ftb_entry_tailSlot_lower,</span></a>
+<a name="302"><span class="lineNum">     302 </span><span class="lineCov">         65 :   output [1:0]   io_out_last_stage_ftb_entry_tailSlot_tarStat,</span></a>
+<a name="303"><span class="lineNum">     303 </span><span class="lineCov">         37 :   output         io_out_last_stage_ftb_entry_tailSlot_sharing,</span></a>
+<a name="304"><span class="lineNum">     304 </span><span class="lineCov">         33 :   output         io_out_last_stage_ftb_entry_tailSlot_valid,</span></a>
+<a name="305"><span class="lineNum">     305 </span><span class="lineCov">        142 :   output [3:0]   io_out_last_stage_ftb_entry_pftAddr,</span></a>
+<a name="306"><span class="lineNum">     306 </span><span class="lineCov">         35 :   output         io_out_last_stage_ftb_entry_carry,</span></a>
+<a name="307"><span class="lineNum">     307 </span><span class="lineCov">         34 :   output         io_out_last_stage_ftb_entry_isCall,</span></a>
+<a name="308"><span class="lineNum">     308 </span><span class="lineCov">         33 :   output         io_out_last_stage_ftb_entry_isRet,</span></a>
+<a name="309"><span class="lineNum">     309 </span><span class="lineCov">         36 :   output         io_out_last_stage_ftb_entry_isJalr,</span></a>
+<a name="310"><span class="lineNum">     310 </span><span class="lineCov">         31 :   output         io_out_last_stage_ftb_entry_last_may_be_rvi_call,</span></a>
+<a name="311"><span class="lineNum">     311 </span><span class="lineCov">         27 :   output         io_out_last_stage_ftb_entry_always_taken_0,</span></a>
+<a name="312"><span class="lineNum">     312 </span><span class="lineCov">         33 :   output         io_out_last_stage_ftb_entry_always_taken_1,</span></a>
+<a name="313"><span class="lineNum">     313 </span><span class="lineCov">         73 :   input          io_s0_fire_3,</span></a>
+<a name="314"><span class="lineNum">     314 </span><span class="lineCov">        133 :   input          io_s1_fire_3,</span></a>
+<a name="315"><span class="lineNum">     315 </span><span class="lineCov">        127 :   input          io_s2_fire_0,</span></a>
+<a name="316"><span class="lineNum">     316 </span><span class="lineCov">        127 :   input          io_s2_fire_1,</span></a>
+<a name="317"><span class="lineNum">     317 </span><span class="lineCov">        127 :   input          io_s2_fire_2,</span></a>
+<a name="318"><span class="lineNum">     318 </span><span class="lineCov">        127 :   input          io_s2_fire_3,</span></a>
+<a name="319"><span class="lineNum">     319 </span><span class="lineCov">        105 :   input          io_update_valid,</span></a>
+<a name="320"><span class="lineNum">     320 </span><span class="lineCov">       1143 :   input  [40:0]  io_update_bits_pc,</span></a>
+<a name="321"><span class="lineNum">     321 </span><span class="lineCov">        243 :   input  [7:0]   io_update_bits_spec_info_folded_hist_hist_14_folded_hist,</span></a>
+<a name="322"><span class="lineNum">     322 </span><span class="lineCov">        250 :   input  [8:0]   io_update_bits_spec_info_folded_hist_hist_13_folded_hist,</span></a>
+<a name="323"><span class="lineNum">     323 </span><span class="lineCov">        108 :   input  [3:0]   io_update_bits_spec_info_folded_hist_hist_12_folded_hist,</span></a>
+<a name="324"><span class="lineNum">     324 </span><span class="lineCov">        282 :   input  [8:0]   io_update_bits_spec_info_folded_hist_hist_10_folded_hist,</span></a>
+<a name="325"><span class="lineNum">     325 </span><span class="lineCov">        285 :   input  [8:0]   io_update_bits_spec_info_folded_hist_hist_6_folded_hist,</span></a>
+<a name="326"><span class="lineNum">     326 </span><span class="lineCov">        219 :   input  [7:0]   io_update_bits_spec_info_folded_hist_hist_4_folded_hist,</span></a>
+<a name="327"><span class="lineNum">     327 </span><span class="lineCov">        233 :   input  [7:0]   io_update_bits_spec_info_folded_hist_hist_3_folded_hist,</span></a>
+<a name="328"><span class="lineNum">     328 </span><span class="lineCov">        231 :   input  [7:0]   io_update_bits_spec_info_folded_hist_hist_2_folded_hist,</span></a>
+<a name="329"><span class="lineNum">     329 </span><span class="lineCov">        137 :   input  [3:0]   io_update_bits_ftb_entry_tailSlot_offset,</span></a>
+<a name="330"><span class="lineNum">     330 </span><span class="lineCov">         33 :   input          io_update_bits_ftb_entry_tailSlot_sharing,</span></a>
+<a name="331"><span class="lineNum">     331 </span><span class="lineCov">         28 :   input          io_update_bits_ftb_entry_tailSlot_valid,</span></a>
+<a name="332"><span class="lineNum">     332 </span><span class="lineCov">         36 :   input          io_update_bits_ftb_entry_isRet,</span></a>
+<a name="333"><span class="lineNum">     333 </span><span class="lineCov">         37 :   input          io_update_bits_ftb_entry_isJalr,</span></a>
+<a name="334"><span class="lineNum">     334 </span><span class="lineCov">         22 :   input          io_update_bits_cfi_idx_valid,</span></a>
+<a name="335"><span class="lineNum">     335 </span><span class="lineCov">        155 :   input  [3:0]   io_update_bits_cfi_idx_bits,</span></a>
+<a name="336"><span class="lineNum">     336 </span><span class="lineCov">         40 :   input          io_update_bits_jmp_taken,</span></a>
+<a name="337"><span class="lineNum">     337 </span><span class="lineCov">         42 :   input          io_update_bits_mispred_mask_2,</span></a>
+<a name="338"><span class="lineNum">     338 </span><span class="lineCov">       5927 :   input  [222:0] io_update_bits_meta,</span></a>
+<a name="339"><span class="lineNum">     339 </span><span class="lineCov">       1185 :   input  [40:0]  io_update_bits_full_target</span></a>
+<a name="340"><span class="lineNum">     340 </span>            : );</a>
+<a name="341"><span class="lineNum">     341 </span>            : </a>
+<a name="342"><span class="lineNum">     342 </span><span class="lineCov">       4013 :   reg  [2:0]  resp_meta_allocate_bits_r;</span></a>
+<a name="343"><span class="lineNum">     343 </span><span class="lineCov">         40 :   reg         resp_meta_allocate_valid_r;</span></a>
+<a name="344"><span class="lineNum">     344 </span><span class="lineCov">         30 :   wire        resp_meta_altDiffers;</span></a>
+<a name="345"><span class="lineNum">     345 </span>            :   wire        _tables_4_io_resp_valid;</a>
+<a name="346"><span class="lineNum">     346 </span>            :   wire [1:0]  _tables_4_io_resp_bits_ctr;</a>
+<a name="347"><span class="lineNum">     347 </span>            :   wire [1:0]  _tables_4_io_resp_bits_u;</a>
+<a name="348"><span class="lineNum">     348 </span>            :   wire [40:0] _tables_4_io_resp_bits_target;</a>
+<a name="349"><span class="lineNum">     349 </span>            :   wire        _tables_3_io_resp_valid;</a>
+<a name="350"><span class="lineNum">     350 </span>            :   wire [1:0]  _tables_3_io_resp_bits_ctr;</a>
+<a name="351"><span class="lineNum">     351 </span>            :   wire [1:0]  _tables_3_io_resp_bits_u;</a>
+<a name="352"><span class="lineNum">     352 </span>            :   wire [40:0] _tables_3_io_resp_bits_target;</a>
+<a name="353"><span class="lineNum">     353 </span>            :   wire        _tables_2_io_resp_valid;</a>
+<a name="354"><span class="lineNum">     354 </span>            :   wire [1:0]  _tables_2_io_resp_bits_ctr;</a>
+<a name="355"><span class="lineNum">     355 </span>            :   wire [1:0]  _tables_2_io_resp_bits_u;</a>
+<a name="356"><span class="lineNum">     356 </span>            :   wire [40:0] _tables_2_io_resp_bits_target;</a>
+<a name="357"><span class="lineNum">     357 </span>            :   wire        _tables_1_io_resp_valid;</a>
+<a name="358"><span class="lineNum">     358 </span>            :   wire [1:0]  _tables_1_io_resp_bits_ctr;</a>
+<a name="359"><span class="lineNum">     359 </span>            :   wire [1:0]  _tables_1_io_resp_bits_u;</a>
+<a name="360"><span class="lineNum">     360 </span>            :   wire [40:0] _tables_1_io_resp_bits_target;</a>
+<a name="361"><span class="lineNum">     361 </span>            :   wire        _tables_0_io_resp_valid;</a>
+<a name="362"><span class="lineNum">     362 </span>            :   wire [1:0]  _tables_0_io_resp_bits_ctr;</a>
+<a name="363"><span class="lineNum">     363 </span>            :   wire [1:0]  _tables_0_io_resp_bits_u;</a>
+<a name="364"><span class="lineNum">     364 </span>            :   wire [40:0] _tables_0_io_resp_bits_target;</a>
+<a name="365"><span class="lineNum">     365 </span><span class="lineCov">        181 :   reg  [7:0]  tickCtr;</span></a>
+<a name="366"><span class="lineNum">     366 </span><span class="lineCov">         26 :   reg         s2_resps_0_valid;</span></a>
+<a name="367"><span class="lineNum">     367 </span><span class="lineCov">         66 :   reg  [1:0]  s2_resps_0_bits_ctr;</span></a>
+<a name="368"><span class="lineNum">     368 </span><span class="lineCov">        209 :   reg  [1:0]  s2_resps_0_bits_u;</span></a>
+<a name="369"><span class="lineNum">     369 </span><span class="lineCov">       1291 :   reg  [40:0] s2_resps_0_bits_target;</span></a>
+<a name="370"><span class="lineNum">     370 </span><span class="lineCov">         33 :   reg         s2_resps_1_valid;</span></a>
+<a name="371"><span class="lineNum">     371 </span><span class="lineCov">         57 :   reg  [1:0]  s2_resps_1_bits_ctr;</span></a>
+<a name="372"><span class="lineNum">     372 </span><span class="lineCov">        165 :   reg  [1:0]  s2_resps_1_bits_u;</span></a>
+<a name="373"><span class="lineNum">     373 </span><span class="lineCov">       1334 :   reg  [40:0] s2_resps_1_bits_target;</span></a>
+<a name="374"><span class="lineNum">     374 </span><span class="lineCov">         32 :   reg         s2_resps_2_valid;</span></a>
+<a name="375"><span class="lineNum">     375 </span><span class="lineCov">         71 :   reg  [1:0]  s2_resps_2_bits_ctr;</span></a>
+<a name="376"><span class="lineNum">     376 </span><span class="lineCov">        145 :   reg  [1:0]  s2_resps_2_bits_u;</span></a>
+<a name="377"><span class="lineNum">     377 </span><span class="lineCov">       1328 :   reg  [40:0] s2_resps_2_bits_target;</span></a>
+<a name="378"><span class="lineNum">     378 </span><span class="lineCov">         25 :   reg         s2_resps_3_valid;</span></a>
+<a name="379"><span class="lineNum">     379 </span><span class="lineCov">         52 :   reg  [1:0]  s2_resps_3_bits_ctr;</span></a>
+<a name="380"><span class="lineNum">     380 </span><span class="lineCov">        117 :   reg  [1:0]  s2_resps_3_bits_u;</span></a>
+<a name="381"><span class="lineNum">     381 </span><span class="lineCov">       1348 :   reg  [40:0] s2_resps_3_bits_target;</span></a>
+<a name="382"><span class="lineNum">     382 </span><span class="lineCov">         30 :   reg         s2_resps_4_valid;</span></a>
+<a name="383"><span class="lineNum">     383 </span><span class="lineCov">         62 :   reg  [1:0]  s2_resps_4_bits_ctr;</span></a>
+<a name="384"><span class="lineNum">     384 </span><span class="lineCov">         82 :   reg  [1:0]  s2_resps_4_bits_u;</span></a>
+<a name="385"><span class="lineNum">     385 </span><span class="lineCov">       1223 :   reg  [40:0] s2_resps_4_bits_target;</span></a>
+<a name="386"><span class="lineNum">     386 </span><span class="lineCov">         30 :   reg         s3_tageTaken_dup_0;</span></a>
+<a name="387"><span class="lineNum">     387 </span><span class="lineCov">         27 :   reg         s3_tageTaken_dup_1;</span></a>
+<a name="388"><span class="lineNum">     388 </span><span class="lineCov">         22 :   reg         s3_tageTaken_dup_2;</span></a>
+<a name="389"><span class="lineNum">     389 </span><span class="lineCov">         26 :   reg         s3_tageTaken_dup_3;</span></a>
+<a name="390"><span class="lineNum">     390 </span><span class="lineCov">       1353 :   reg  [40:0] s3_tageTarget_dup_0;</span></a>
+<a name="391"><span class="lineNum">     391 </span><span class="lineCov">       1401 :   reg  [40:0] s3_tageTarget_dup_1;</span></a>
+<a name="392"><span class="lineNum">     392 </span><span class="lineCov">       1337 :   reg  [40:0] s3_tageTarget_dup_2;</span></a>
+<a name="393"><span class="lineNum">     393 </span><span class="lineCov">       1319 :   reg  [40:0] s3_tageTarget_dup_3;</span></a>
+<a name="394"><span class="lineNum">     394 </span><span class="lineCov">       1340 :   reg  [40:0] s3_providerTarget;</span></a>
+<a name="395"><span class="lineNum">     395 </span><span class="lineCov">       1333 :   reg  [40:0] s3_altProviderTarget;</span></a>
+<a name="396"><span class="lineNum">     396 </span><span class="lineCov">         44 :   reg         s3_provided;</span></a>
+<a name="397"><span class="lineNum">     397 </span><span class="lineCov">         99 :   reg  [2:0]  s3_provider;</span></a>
+<a name="398"><span class="lineNum">     398 </span><span class="lineCov">         38 :   reg         s3_altProvided;</span></a>
+<a name="399"><span class="lineNum">     399 </span><span class="lineCov">         95 :   reg  [2:0]  s3_altProvider;</span></a>
+<a name="400"><span class="lineNum">     400 </span><span class="lineCov">         31 :   reg         s3_finalAltPred;</span></a>
+<a name="401"><span class="lineNum">     401 </span><span class="lineCov">        167 :   reg         s3_providerU;</span></a>
+<a name="402"><span class="lineNum">     402 </span><span class="lineCov">         62 :   reg  [1:0]  s3_providerCtr;</span></a>
+<a name="403"><span class="lineNum">     403 </span><span class="lineCov">         64 :   reg  [1:0]  s3_altProviderCtr;</span></a>
+<a name="404"><span class="lineNum">     404 </span><span class="lineCov">         12 :   wire        updateValid =</span></a>
+<a name="405"><span class="lineNum">     405 </span>            :     io_update_bits_ftb_entry_tailSlot_valid &amp; io_update_bits_ftb_entry_isJalr</a>
+<a name="406"><span class="lineNum">     406 </span>            :     &amp; ~(io_update_bits_ftb_entry_tailSlot_valid &amp; io_update_bits_ftb_entry_isRet)</a>
+<a name="407"><span class="lineNum">     407 </span>            :     &amp; io_update_valid &amp; ~io_update_bits_ftb_entry_tailSlot_sharing</a>
+<a name="408"><span class="lineNum">     408 </span>            :     &amp; io_update_bits_jmp_taken &amp; io_update_bits_cfi_idx_valid</a>
+<a name="409"><span class="lineNum">     409 </span>            :     &amp; io_update_bits_cfi_idx_bits == io_update_bits_ftb_entry_tailSlot_offset;</a>
+<a name="410"><span class="lineNum">     410 </span>            :   assign resp_meta_altDiffers = s3_finalAltPred != s3_tageTaken_dup_3;</a>
+<a name="411"><span class="lineNum">     411 </span><span class="lineCov">    2001245 :   reg  [63:0] s2_allocLFSR_lfsr;</span></a>
+<a name="412"><span class="lineNum">     412 </span>            :   wire        _GEN =</a>
+<a name="413"><span class="lineNum">     413 </span>            :     updateValid &amp; io_update_bits_mispred_mask_2</a>
+<a name="414"><span class="lineNum">     414 </span>            :     &amp; ~(io_update_bits_meta[100]</a>
+<a name="415"><span class="lineNum">     415 </span>            :         &amp; io_update_bits_meta[81:41] == io_update_bits_full_target</a>
+<a name="416"><span class="lineNum">     416 </span>            :         &amp; io_update_bits_meta[90:89] == 2'h0);</a>
+<a name="417"><span class="lineNum">     417 </span><span class="lineCov">         25 :   reg         tables_0_io_update_valid_REG;</span></a>
+<a name="418"><span class="lineNum">     418 </span><span class="lineCov">         28 :   reg         tables_0_io_update_reset_u_REG;</span></a>
+<a name="419"><span class="lineNum">     419 </span><span class="lineCov">         15 :   reg         tables_0_io_update_correct_r;</span></a>
+<a name="420"><span class="lineNum">     420 </span><span class="lineCov">        585 :   reg  [40:0] tables_0_io_update_target_r;</span></a>
+<a name="421"><span class="lineNum">     421 </span><span class="lineCov">        611 :   reg  [40:0] tables_0_io_update_old_target_r;</span></a>
+<a name="422"><span class="lineNum">     422 </span><span class="lineCov">         13 :   reg         tables_0_io_update_alloc_r;</span></a>
+<a name="423"><span class="lineNum">     423 </span><span class="lineCov">         27 :   reg  [1:0]  tables_0_io_update_oldCtr_r;</span></a>
+<a name="424"><span class="lineNum">     424 </span><span class="lineCov">         12 :   reg         tables_0_io_update_uValid_r;</span></a>
+<a name="425"><span class="lineNum">     425 </span><span class="lineCov">         16 :   reg         tables_0_io_update_u_r;</span></a>
+<a name="426"><span class="lineNum">     426 </span><span class="lineCov">        594 :   reg  [40:0] tables_0_io_update_pc_r;</span></a>
+<a name="427"><span class="lineNum">     427 </span><span class="lineCov">         54 :   reg  [3:0]  tables_0_io_update_folded_hist_r_hist_12_folded_hist;</span></a>
+<a name="428"><span class="lineNum">     428 </span><span class="lineCov">         27 :   reg         tables_1_io_update_valid_REG;</span></a>
+<a name="429"><span class="lineNum">     429 </span><span class="lineCov">         33 :   reg         tables_1_io_update_reset_u_REG;</span></a>
+<a name="430"><span class="lineNum">     430 </span><span class="lineCov">         13 :   reg         tables_1_io_update_correct_r;</span></a>
+<a name="431"><span class="lineNum">     431 </span><span class="lineCov">        588 :   reg  [40:0] tables_1_io_update_target_r;</span></a>
+<a name="432"><span class="lineNum">     432 </span><span class="lineCov">        587 :   reg  [40:0] tables_1_io_update_old_target_r;</span></a>
+<a name="433"><span class="lineNum">     433 </span><span class="lineCov">         13 :   reg         tables_1_io_update_alloc_r;</span></a>
+<a name="434"><span class="lineNum">     434 </span><span class="lineCov">         33 :   reg  [1:0]  tables_1_io_update_oldCtr_r;</span></a>
+<a name="435"><span class="lineNum">     435 </span><span class="lineCov">         11 :   reg         tables_1_io_update_uValid_r;</span></a>
+<a name="436"><span class="lineNum">     436 </span><span class="lineCov">         14 :   reg         tables_1_io_update_u_r;</span></a>
+<a name="437"><span class="lineNum">     437 </span><span class="lineCov">        577 :   reg  [40:0] tables_1_io_update_pc_r;</span></a>
+<a name="438"><span class="lineNum">     438 </span><span class="lineCov">        108 :   reg  [7:0]  tables_1_io_update_folded_hist_r_hist_14_folded_hist;</span></a>
+<a name="439"><span class="lineNum">     439 </span><span class="lineCov">         27 :   reg         tables_2_io_update_valid_REG;</span></a>
+<a name="440"><span class="lineNum">     440 </span><span class="lineCov">         32 :   reg         tables_2_io_update_reset_u_REG;</span></a>
+<a name="441"><span class="lineNum">     441 </span><span class="lineCov">         13 :   reg         tables_2_io_update_correct_r;</span></a>
+<a name="442"><span class="lineNum">     442 </span><span class="lineCov">        620 :   reg  [40:0] tables_2_io_update_target_r;</span></a>
+<a name="443"><span class="lineNum">     443 </span><span class="lineCov">        577 :   reg  [40:0] tables_2_io_update_old_target_r;</span></a>
+<a name="444"><span class="lineNum">     444 </span><span class="lineCov">         16 :   reg         tables_2_io_update_alloc_r;</span></a>
+<a name="445"><span class="lineNum">     445 </span><span class="lineCov">         24 :   reg  [1:0]  tables_2_io_update_oldCtr_r;</span></a>
+<a name="446"><span class="lineNum">     446 </span><span class="lineCov">         17 :   reg         tables_2_io_update_uValid_r;</span></a>
+<a name="447"><span class="lineNum">     447 </span><span class="lineCov">         13 :   reg         tables_2_io_update_u_r;</span></a>
+<a name="448"><span class="lineNum">     448 </span><span class="lineCov">        598 :   reg  [40:0] tables_2_io_update_pc_r;</span></a>
+<a name="449"><span class="lineNum">     449 </span><span class="lineCov">        111 :   reg  [8:0]  tables_2_io_update_folded_hist_r_hist_13_folded_hist;</span></a>
+<a name="450"><span class="lineNum">     450 </span><span class="lineCov">        106 :   reg  [7:0]  tables_2_io_update_folded_hist_r_hist_4_folded_hist;</span></a>
+<a name="451"><span class="lineNum">     451 </span><span class="lineCov">         26 :   reg         tables_3_io_update_valid_REG;</span></a>
+<a name="452"><span class="lineNum">     452 </span><span class="lineCov">         29 :   reg         tables_3_io_update_reset_u_REG;</span></a>
+<a name="453"><span class="lineNum">     453 </span><span class="lineCov">         16 :   reg         tables_3_io_update_correct_r;</span></a>
+<a name="454"><span class="lineNum">     454 </span><span class="lineCov">        602 :   reg  [40:0] tables_3_io_update_target_r;</span></a>
+<a name="455"><span class="lineNum">     455 </span><span class="lineCov">        599 :   reg  [40:0] tables_3_io_update_old_target_r;</span></a>
+<a name="456"><span class="lineNum">     456 </span><span class="lineCov">         17 :   reg         tables_3_io_update_alloc_r;</span></a>
+<a name="457"><span class="lineNum">     457 </span><span class="lineCov">         28 :   reg  [1:0]  tables_3_io_update_oldCtr_r;</span></a>
+<a name="458"><span class="lineNum">     458 </span><span class="lineCov">         15 :   reg         tables_3_io_update_uValid_r;</span></a>
+<a name="459"><span class="lineNum">     459 </span><span class="lineCov">         13 :   reg         tables_3_io_update_u_r;</span></a>
+<a name="460"><span class="lineNum">     460 </span><span class="lineCov">        591 :   reg  [40:0] tables_3_io_update_pc_r;</span></a>
+<a name="461"><span class="lineNum">     461 </span><span class="lineCov">        128 :   reg  [8:0]  tables_3_io_update_folded_hist_r_hist_6_folded_hist;</span></a>
+<a name="462"><span class="lineNum">     462 </span><span class="lineCov">        111 :   reg  [7:0]  tables_3_io_update_folded_hist_r_hist_2_folded_hist;</span></a>
+<a name="463"><span class="lineNum">     463 </span><span class="lineCov">         24 :   reg         tables_4_io_update_valid_REG;</span></a>
+<a name="464"><span class="lineNum">     464 </span><span class="lineCov">         27 :   reg         tables_4_io_update_reset_u_REG;</span></a>
+<a name="465"><span class="lineNum">     465 </span><span class="lineCov">         11 :   reg         tables_4_io_update_correct_r;</span></a>
+<a name="466"><span class="lineNum">     466 </span><span class="lineCov">        628 :   reg  [40:0] tables_4_io_update_target_r;</span></a>
+<a name="467"><span class="lineNum">     467 </span><span class="lineCov">        594 :   reg  [40:0] tables_4_io_update_old_target_r;</span></a>
+<a name="468"><span class="lineNum">     468 </span><span class="lineCov">         16 :   reg         tables_4_io_update_alloc_r;</span></a>
+<a name="469"><span class="lineNum">     469 </span><span class="lineCov">         28 :   reg  [1:0]  tables_4_io_update_oldCtr_r;</span></a>
+<a name="470"><span class="lineNum">     470 </span><span class="lineCov">         17 :   reg         tables_4_io_update_uValid_r;</span></a>
+<a name="471"><span class="lineNum">     471 </span><span class="lineCov">         20 :   reg         tables_4_io_update_u_r;</span></a>
+<a name="472"><span class="lineNum">     472 </span><span class="lineCov">        595 :   reg  [40:0] tables_4_io_update_pc_r;</span></a>
+<a name="473"><span class="lineNum">     473 </span><span class="lineCov">        127 :   reg  [8:0]  tables_4_io_update_folded_hist_r_hist_10_folded_hist;</span></a>
+<a name="474"><span class="lineNum">     474 </span><span class="lineCov">        113 :   reg  [7:0]  tables_4_io_update_folded_hist_r_hist_3_folded_hist;</span></a>
+<a name="475"><span class="lineNum">     475 </span><span class="lineCov">     127730 :   always @(posedge clock or posedge reset) begin</span></a>
+<a name="476"><span class="lineNum">     476 </span><span class="lineCov">        272 :     if (reset) begin</span></a>
+<a name="477"><span class="lineNum">     477 </span><span class="lineCov">        136 :       tickCtr &lt;= 8'h0;</span></a>
+<a name="478"><span class="lineNum">     478 </span><span class="lineCov">        136 :       s2_allocLFSR_lfsr &lt;= 64'h1234567887654321;</span></a>
+<a name="479"><span class="lineNum">     479 </span>            :     end</a>
+<a name="480"><span class="lineNum">     480 </span><span class="lineCov">      63729 :     else begin</span></a>
+<a name="481"><span class="lineNum">     481 </span><span class="lineNoCov">          0 :       if (&amp;tickCtr)</span></a>
+<a name="482"><span class="lineNum">     482 </span><span class="lineNoCov">          0 :         tickCtr &lt;= 8'h0;</span></a>
+<a name="483"><span class="lineNum">     483 </span><span class="lineNoCov">          0 :       else if (_GEN) begin</span></a>
+<a name="484"><span class="lineNum">     484 </span><span class="lineNoCov">          0 :         if ((&amp;tickCtr) &amp; ~(io_update_bits_meta[86]))</span></a>
+<a name="485"><span class="lineNum">     485 </span><span class="lineNoCov">          0 :           tickCtr &lt;= 8'hFF;</span></a>
+<a name="486"><span class="lineNum">     486 </span><span class="lineNoCov">          0 :         else if (tickCtr == 8'h0 &amp; io_update_bits_meta[86])</span></a>
+<a name="487"><span class="lineNum">     487 </span><span class="lineNoCov">          0 :           tickCtr &lt;= 8'h0;</span></a>
+<a name="488"><span class="lineNum">     488 </span><span class="lineNoCov">          0 :         else if (io_update_bits_meta[86])</span></a>
+<a name="489"><span class="lineNum">     489 </span><span class="lineNoCov">          0 :           tickCtr &lt;= 8'(tickCtr - 8'h1);</span></a>
+<a name="490"><span class="lineNum">     490 </span>            :         else</a>
+<a name="491"><span class="lineNum">     491 </span><span class="lineNoCov">          0 :           tickCtr &lt;= 8'(tickCtr + 8'h1);</span></a>
+<a name="492"><span class="lineNum">     492 </span>            :       end</a>
+<a name="493"><span class="lineNum">     493 </span><span class="lineNoCov">          0 :       if (s2_allocLFSR_lfsr == 64'h0)</span></a>
+<a name="494"><span class="lineNum">     494 </span><span class="lineNoCov">          0 :         s2_allocLFSR_lfsr &lt;= 64'h1;</span></a>
+<a name="495"><span class="lineNum">     495 </span>            :       else</a>
+<a name="496"><span class="lineNum">     496 </span><span class="lineCov">      63729 :         s2_allocLFSR_lfsr &lt;=</span></a>
+<a name="497"><span class="lineNum">     497 </span><span class="lineCov">      63729 :           {s2_allocLFSR_lfsr[0] ^ s2_allocLFSR_lfsr[1] ^ s2_allocLFSR_lfsr[3]</span></a>
+<a name="498"><span class="lineNum">     498 </span><span class="lineCov">      63729 :              ^ s2_allocLFSR_lfsr[4],</span></a>
+<a name="499"><span class="lineNum">     499 </span><span class="lineCov">      63729 :            s2_allocLFSR_lfsr[63:1]};</span></a>
+<a name="500"><span class="lineNum">     500 </span>            :     end</a>
+<a name="501"><span class="lineNum">     501 </span>            :   end // always @(posedge, posedge)</a>
+<a name="502"><span class="lineNum">     502 </span><span class="lineCov">         56 :   wire [2:0]  selectedInfo_res_1_first_tableIdx = {2'h0, s2_resps_1_valid};</span></a>
+<a name="503"><span class="lineNum">     503 </span><span class="lineCov">         73 :   wire [2:0]  selectedInfo_res_2_first_tableIdx =</span></a>
+<a name="504"><span class="lineNum">     504 </span>            :     s2_resps_2_valid ? 3'h2 : selectedInfo_res_1_first_tableIdx;</a>
+<a name="505"><span class="lineNum">     505 </span><span class="lineCov">         31 :   wire        selectedInfo_res_hasOne = s2_resps_4_valid | s2_resps_3_valid;</span></a>
+<a name="506"><span class="lineNum">     506 </span><span class="lineCov">         23 :   wire        selectedInfo_res_hasTwo = s2_resps_4_valid &amp; s2_resps_3_valid;</span></a>
+<a name="507"><span class="lineNum">     507 </span><span class="lineCov">         41 :   wire        selectedInfo_res_1_hasOne = s2_resps_1_valid | s2_resps_0_valid;</span></a>
+<a name="508"><span class="lineNum">     508 </span><span class="lineCov">         55 :   wire [1:0]  selectedInfo_res_1_first_ctr =</span></a>
+<a name="509"><span class="lineNum">     509 </span>            :     s2_resps_1_valid ? s2_resps_1_bits_ctr : s2_resps_0_bits_ctr;</a>
+<a name="510"><span class="lineNum">     510 </span><span class="lineCov">       1270 :   wire [40:0] selectedInfo_res_1_first_target =</span></a>
+<a name="511"><span class="lineNum">     511 </span>            :     s2_resps_1_valid ? s2_resps_1_bits_target : s2_resps_0_bits_target;</a>
+<a name="512"><span class="lineNum">     512 </span><span class="lineCov">         38 :   wire        selectedInfo_res_2_hasOne = s2_resps_2_valid | selectedInfo_res_1_hasOne;</span></a>
+<a name="513"><span class="lineNum">     513 </span><span class="lineCov">         62 :   wire [1:0]  selectedInfo_res_2_first_ctr =</span></a>
+<a name="514"><span class="lineNum">     514 </span>            :     s2_resps_2_valid ? s2_resps_2_bits_ctr : selectedInfo_res_1_first_ctr;</a>
+<a name="515"><span class="lineNum">     515 </span><span class="lineCov">       1279 :   wire [40:0] selectedInfo_res_2_first_target =</span></a>
+<a name="516"><span class="lineNum">     516 </span>            :     s2_resps_2_valid ? s2_resps_2_bits_target : selectedInfo_res_1_first_target;</a>
+<a name="517"><span class="lineNum">     517 </span><span class="lineCov">         41 :   wire        selectedInfo_hasOne = selectedInfo_res_hasOne | selectedInfo_res_2_hasOne;</span></a>
+<a name="518"><span class="lineNum">     518 </span><span class="lineCov">         41 :   wire        selectedInfo_hasTwo =</span></a>
+<a name="519"><span class="lineNum">     519 </span>            :     selectedInfo_res_hasTwo | s2_resps_1_valid &amp; s2_resps_0_valid | s2_resps_2_valid</a>
+<a name="520"><span class="lineNum">     520 </span>            :     &amp; selectedInfo_res_1_hasOne | selectedInfo_res_hasOne &amp; selectedInfo_res_2_hasOne;</a>
+<a name="521"><span class="lineNum">     521 </span><span class="lineCov">         46 :   wire [1:0]  selectedInfo_first_ctr =</span></a>
+<a name="522"><span class="lineNum">     522 </span>            :     selectedInfo_res_hasOne</a>
+<a name="523"><span class="lineNum">     523 </span>            :       ? (s2_resps_4_valid ? s2_resps_4_bits_ctr : s2_resps_3_bits_ctr)</a>
+<a name="524"><span class="lineNum">     524 </span>            :       : selectedInfo_res_2_first_ctr;</a>
+<a name="525"><span class="lineNum">     525 </span><span class="lineCov">       1284 :   wire [40:0] selectedInfo_first_target =</span></a>
+<a name="526"><span class="lineNum">     526 </span>            :     selectedInfo_res_hasOne</a>
+<a name="527"><span class="lineNum">     527 </span>            :       ? (s2_resps_4_valid ? s2_resps_4_bits_target : s2_resps_3_bits_target)</a>
+<a name="528"><span class="lineNum">     528 </span>            :       : selectedInfo_res_2_first_target;</a>
+<a name="529"><span class="lineNum">     529 </span>            :   wire        _selectedInfo_T_91 = selectedInfo_res_hasOne &amp; ~selectedInfo_res_hasTwo;</a>
+<a name="530"><span class="lineNum">     530 </span><span class="lineCov">       1300 :   wire [40:0] selectedInfo_second_target =</span></a>
+<a name="531"><span class="lineNum">     531 </span>            :     (selectedInfo_res_hasOne</a>
+<a name="532"><span class="lineNum">     532 </span>            :        ? 41'h0</a>
+<a name="533"><span class="lineNum">     533 </span>            :        : (s2_resps_2_valid</a>
+<a name="534"><span class="lineNum">     534 </span>            :             ? 41'h0</a>
+<a name="535"><span class="lineNum">     535 </span>            :             : (s2_resps_1_valid ? 41'h0 : s2_resps_0_bits_target)</a>
+<a name="536"><span class="lineNum">     536 </span>            :               | (s2_resps_1_valid ? s2_resps_0_bits_target : 41'h0))</a>
+<a name="537"><span class="lineNum">     537 </span>            :          | (s2_resps_2_valid ? selectedInfo_res_1_first_target : 41'h0))</a>
+<a name="538"><span class="lineNum">     538 </span>            :     | (_selectedInfo_T_91 ? selectedInfo_res_2_first_target : 41'h0)</a>
+<a name="539"><span class="lineNum">     539 </span>            :     | (selectedInfo_res_hasTwo</a>
+<a name="540"><span class="lineNum">     540 </span>            :          ? (s2_resps_4_valid ? 41'h0 : s2_resps_3_bits_target)</a>
+<a name="541"><span class="lineNum">     541 </span>            :            | (s2_resps_4_valid ? s2_resps_3_bits_target : 41'h0)</a>
+<a name="542"><span class="lineNum">     542 </span>            :          : 41'h0);</a>
+<a name="543"><span class="lineNum">     543 </span><span class="lineCov">         36 :   wire        providerNull = selectedInfo_first_ctr == 2'h0;</span></a>
+<a name="544"><span class="lineNum">     544 </span>            :   wire        _s2_tageTarget_T = providerNull &amp; selectedInfo_hasTwo;</a>
+<a name="545"><span class="lineNum">     545 </span>            :   wire        _s2_tageTarget_T_3 = selectedInfo_hasTwo &amp; providerNull;</a>
+<a name="546"><span class="lineNum">     546 </span>            :   wire        _s2_tageTaken_T_9 =</a>
+<a name="547"><span class="lineNum">     547 </span>            :     selectedInfo_hasOne &amp; ~_s2_tageTarget_T | _s2_tageTarget_T_3 | ~selectedInfo_hasOne;</a>
+<a name="548"><span class="lineNum">     548 </span>            :   wire [40:0] _s2_tageTarget_T_12 =</a>
+<a name="549"><span class="lineNum">     549 </span>            :     (selectedInfo_hasOne &amp; ~_s2_tageTarget_T ? selectedInfo_first_target : 41'h0)</a>
+<a name="550"><span class="lineNum">     550 </span>            :     | (_s2_tageTarget_T_3 ? selectedInfo_second_target : 41'h0)</a>
+<a name="551"><span class="lineNum">     551 </span>            :     | (~selectedInfo_hasOne | providerNull &amp; ~selectedInfo_hasTwo</a>
+<a name="552"><span class="lineNum">     552 </span>            :          ? io_in_bits_resp_in_0_s2_full_pred_3_jalr_target</a>
+<a name="553"><span class="lineNum">     553 </span>            :          : 41'h0);</a>
+<a name="554"><span class="lineNum">     554 </span>            :   wire        _GEN_0 =</a>
+<a name="555"><span class="lineNum">     555 </span>            :     io_update_bits_meta[96] &amp; io_update_bits_meta[90:89] == 2'h0</a>
+<a name="556"><span class="lineNum">     556 </span>            :     &amp; io_update_bits_mispred_mask_2;</a>
+<a name="557"><span class="lineNum">     557 </span>            :   wire        _GEN_1 = io_update_bits_meta[99:97] == 3'h0;</a>
+<a name="558"><span class="lineNum">     558 </span>            :   wire        _GEN_2 = updateValid &amp; io_update_bits_meta[100];</a>
+<a name="559"><span class="lineNum">     559 </span>            :   wire        _GEN_3 = io_update_bits_meta[99:97] == 3'h1;</a>
+<a name="560"><span class="lineNum">     560 </span>            :   wire        _GEN_4 = io_update_bits_meta[99:97] == 3'h2;</a>
+<a name="561"><span class="lineNum">     561 </span>            :   wire        _GEN_5 = io_update_bits_meta[99:97] == 3'h3;</a>
+<a name="562"><span class="lineNum">     562 </span>            :   wire        _GEN_6 = io_update_bits_meta[99:97] == 3'h4;</a>
+<a name="563"><span class="lineNum">     563 </span>            :   wire        _updateU_T_2 =</a>
+<a name="564"><span class="lineNum">     564 </span>            :     io_update_bits_meta[92] ? ~io_update_bits_mispred_mask_2 : io_update_bits_meta[91];</a>
+<a name="565"><span class="lineNum">     565 </span>            :   wire        _updateCorrect_T = io_update_bits_meta[81:41] == io_update_bits_full_target;</a>
+<a name="566"><span class="lineNum">     566 </span>            :   wire        _GEN_7 = io_update_bits_meta[85:83] == 3'h0;</a>
+<a name="567"><span class="lineNum">     567 </span>            :   wire        _GEN_8 = _GEN &amp; io_update_bits_meta[86] &amp; _GEN_7;</a>
+<a name="568"><span class="lineNum">     568 </span><span class="lineCov">         12 :   wire        updateMask_0 =</span></a>
+<a name="569"><span class="lineNum">     569 </span>            :     _GEN_8 | _GEN_2 &amp; (_GEN_1 | _GEN_0 &amp; io_update_bits_meta[95:93] == 3'h0);</a>
+<a name="570"><span class="lineNum">     570 </span>            :   wire        _GEN_9 = io_update_bits_meta[85:83] == 3'h1;</a>
+<a name="571"><span class="lineNum">     571 </span>            :   wire        _GEN_10 = _GEN &amp; io_update_bits_meta[86] &amp; _GEN_9;</a>
+<a name="572"><span class="lineNum">     572 </span><span class="lineCov">         16 :   wire        updateMask_1 =</span></a>
+<a name="573"><span class="lineNum">     573 </span>            :     _GEN_10 | _GEN_2 &amp; (_GEN_3 | _GEN_0 &amp; io_update_bits_meta[95:93] == 3'h1);</a>
+<a name="574"><span class="lineNum">     574 </span>            :   wire        _GEN_11 = io_update_bits_meta[85:83] == 3'h2;</a>
+<a name="575"><span class="lineNum">     575 </span>            :   wire        _GEN_12 = _GEN &amp; io_update_bits_meta[86] &amp; _GEN_11;</a>
+<a name="576"><span class="lineNum">     576 </span><span class="lineCov">         17 :   wire        updateMask_2 =</span></a>
+<a name="577"><span class="lineNum">     577 </span>            :     _GEN_12 | _GEN_2 &amp; (_GEN_4 | _GEN_0 &amp; io_update_bits_meta[95:93] == 3'h2);</a>
+<a name="578"><span class="lineNum">     578 </span>            :   wire        _GEN_13 = io_update_bits_meta[85:83] == 3'h3;</a>
+<a name="579"><span class="lineNum">     579 </span>            :   wire        _GEN_14 = _GEN &amp; io_update_bits_meta[86] &amp; _GEN_13;</a>
+<a name="580"><span class="lineNum">     580 </span><span class="lineCov">         12 :   wire        updateMask_3 =</span></a>
+<a name="581"><span class="lineNum">     581 </span>            :     _GEN_14 | _GEN_2 &amp; (_GEN_5 | _GEN_0 &amp; io_update_bits_meta[95:93] == 3'h3);</a>
+<a name="582"><span class="lineNum">     582 </span>            :   wire        _GEN_15 = io_update_bits_meta[85:83] == 3'h4;</a>
+<a name="583"><span class="lineNum">     583 </span>            :   wire        _GEN_16 = _GEN &amp; io_update_bits_meta[86] &amp; _GEN_15;</a>
+<a name="584"><span class="lineNum">     584 </span><span class="lineCov">         15 :   wire        updateMask_4 =</span></a>
+<a name="585"><span class="lineNum">     585 </span>            :     _GEN_16 | _GEN_2 &amp; (_GEN_6 | _GEN_0 &amp; io_update_bits_meta[95:93] == 3'h4);</a>
+<a name="586"><span class="lineNum">     586 </span>            :   wire        _GEN_17 = _GEN &amp; io_update_bits_meta[86];</a>
+<a name="587"><span class="lineNum">     587 </span><span class="lineCov">         78 :   wire [2:0]  selectedInfo_first_tableIdx =</span></a>
+<a name="588"><span class="lineNum">     588 </span>            :     selectedInfo_res_hasOne</a>
+<a name="589"><span class="lineNum">     589 </span>            :       ? (s2_resps_4_valid ? 3'h4 : 3'h3)</a>
+<a name="590"><span class="lineNum">     590 </span>            :       : selectedInfo_res_2_first_tableIdx;</a>
+<a name="591"><span class="lineNum">     591 </span><span class="lineCov">         54 :   wire [1:0]  selectedInfo_second_ctr =</span></a>
+<a name="592"><span class="lineNum">     592 </span>            :     (selectedInfo_res_hasOne</a>
+<a name="593"><span class="lineNum">     593 </span>            :        ? 2'h0</a>
+<a name="594"><span class="lineNum">     594 </span>            :        : (s2_resps_2_valid</a>
+<a name="595"><span class="lineNum">     595 </span>            :             ? 2'h0</a>
+<a name="596"><span class="lineNum">     596 </span>            :             : (s2_resps_1_valid ? 2'h0 : s2_resps_0_bits_ctr)</a>
+<a name="597"><span class="lineNum">     597 </span>            :               | (s2_resps_1_valid ? s2_resps_0_bits_ctr : 2'h0))</a>
+<a name="598"><span class="lineNum">     598 </span>            :          | (s2_resps_2_valid ? selectedInfo_res_1_first_ctr : 2'h0))</a>
+<a name="599"><span class="lineNum">     599 </span>            :     | (_selectedInfo_T_91 ? selectedInfo_res_2_first_ctr : 2'h0)</a>
+<a name="600"><span class="lineNum">     600 </span>            :     | (selectedInfo_res_hasTwo</a>
+<a name="601"><span class="lineNum">     601 </span>            :          ? (s2_resps_4_valid ? 2'h0 : s2_resps_3_bits_ctr)</a>
+<a name="602"><span class="lineNum">     602 </span>            :            | (s2_resps_4_valid ? s2_resps_3_bits_ctr : 2'h0)</a>
+<a name="603"><span class="lineNum">     603 </span>            :          : 2'h0);</a>
+<a name="604"><span class="lineNum">     604 </span>            :   wire [7:0]  _s2_allocatableSlots_T_17 = 8'h1 &lt;&lt; selectedInfo_first_tableIdx;</a>
+<a name="605"><span class="lineNum">     605 </span>            :   wire [4:0]  _GEN_18 = _s2_allocatableSlots_T_17[4:0] | _s2_allocatableSlots_T_17[5:1];</a>
+<a name="606"><span class="lineNum">     606 </span>            :   wire [4:0]  _GEN_19 =</a>
+<a name="607"><span class="lineNum">     607 </span>            :     ~({_GEN_18[4] | selectedInfo_first_tableIdx == 3'h6 | (&amp;selectedInfo_first_tableIdx),</a>
+<a name="608"><span class="lineNum">     608 </span>            :        _GEN_18[3:0] | _s2_allocatableSlots_T_17[5:2] | _s2_allocatableSlots_T_17[6:3]</a>
+<a name="609"><span class="lineNum">     609 </span>            :          | _s2_allocatableSlots_T_17[7:4]} &amp; {5{selectedInfo_hasOne}})</a>
+<a name="610"><span class="lineNum">     610 </span>            :     &amp; {~s2_resps_4_valid &amp; s2_resps_4_bits_u == 2'h0,</a>
+<a name="611"><span class="lineNum">     611 </span>            :        ~s2_resps_3_valid &amp; s2_resps_3_bits_u == 2'h0,</a>
+<a name="612"><span class="lineNum">     612 </span>            :        ~s2_resps_2_valid &amp; s2_resps_2_bits_u == 2'h0,</a>
+<a name="613"><span class="lineNum">     613 </span>            :        ~s2_resps_1_valid &amp; s2_resps_1_bits_u == 2'h0,</a>
+<a name="614"><span class="lineNum">     614 </span>            :        ~s2_resps_0_valid &amp; s2_resps_0_bits_u == 2'h0};</a>
+<a name="615"><span class="lineNum">     615 </span>            :   wire [4:0]  _GEN_20 = _GEN_19 &amp; s2_allocLFSR_lfsr[4:0];</a>
+<a name="616"><span class="lineNum">     616 </span><span class="lineCov">      24259 :   wire [2:0]  s2_maskedEntry =</span></a>
+<a name="617"><span class="lineNum">     617 </span>            :     _GEN_20[0]</a>
+<a name="618"><span class="lineNum">     618 </span>            :       ? 3'h0</a>
+<a name="619"><span class="lineNum">     619 </span>            :       : _GEN_20[1]</a>
+<a name="620"><span class="lineNum">     620 </span>            :           ? 3'h1</a>
+<a name="621"><span class="lineNum">     621 </span>            :           : _GEN_20[2] ? 3'h2 : _GEN_20[3] ? 3'h3 : _GEN_20[4] ? 3'h4 : 3'h7;</a>
+<a name="622"><span class="lineNum">     622 </span>            :   wire [7:0]  _s2_allocEntry_T = {3'h0, _GEN_19} &gt;&gt; s2_maskedEntry;</a>
+<a name="623"><span class="lineNum">     623 </span><span class="lineCov">     127694 :   always @(posedge clock) begin</span></a>
+<a name="624"><span class="lineNum">     624 </span><span class="lineCov">       8252 :     if (io_s1_fire_3) begin</span></a>
+<a name="625"><span class="lineNum">     625 </span><span class="lineCov">       4126 :       s2_resps_0_valid &lt;= _tables_0_io_resp_valid;</span></a>
+<a name="626"><span class="lineNum">     626 </span><span class="lineCov">       4126 :       s2_resps_0_bits_ctr &lt;= _tables_0_io_resp_bits_ctr;</span></a>
+<a name="627"><span class="lineNum">     627 </span><span class="lineCov">       4126 :       s2_resps_0_bits_u &lt;= _tables_0_io_resp_bits_u;</span></a>
+<a name="628"><span class="lineNum">     628 </span><span class="lineCov">       4126 :       s2_resps_0_bits_target &lt;= _tables_0_io_resp_bits_target;</span></a>
+<a name="629"><span class="lineNum">     629 </span><span class="lineCov">       4126 :       s2_resps_1_valid &lt;= _tables_1_io_resp_valid;</span></a>
+<a name="630"><span class="lineNum">     630 </span><span class="lineCov">       4126 :       s2_resps_1_bits_ctr &lt;= _tables_1_io_resp_bits_ctr;</span></a>
+<a name="631"><span class="lineNum">     631 </span><span class="lineCov">       4126 :       s2_resps_1_bits_u &lt;= _tables_1_io_resp_bits_u;</span></a>
+<a name="632"><span class="lineNum">     632 </span><span class="lineCov">       4126 :       s2_resps_1_bits_target &lt;= _tables_1_io_resp_bits_target;</span></a>
+<a name="633"><span class="lineNum">     633 </span><span class="lineCov">       4126 :       s2_resps_2_valid &lt;= _tables_2_io_resp_valid;</span></a>
+<a name="634"><span class="lineNum">     634 </span><span class="lineCov">       4126 :       s2_resps_2_bits_ctr &lt;= _tables_2_io_resp_bits_ctr;</span></a>
+<a name="635"><span class="lineNum">     635 </span><span class="lineCov">       4126 :       s2_resps_2_bits_u &lt;= _tables_2_io_resp_bits_u;</span></a>
+<a name="636"><span class="lineNum">     636 </span><span class="lineCov">       4126 :       s2_resps_2_bits_target &lt;= _tables_2_io_resp_bits_target;</span></a>
+<a name="637"><span class="lineNum">     637 </span><span class="lineCov">       4126 :       s2_resps_3_valid &lt;= _tables_3_io_resp_valid;</span></a>
+<a name="638"><span class="lineNum">     638 </span><span class="lineCov">       4126 :       s2_resps_3_bits_ctr &lt;= _tables_3_io_resp_bits_ctr;</span></a>
+<a name="639"><span class="lineNum">     639 </span><span class="lineCov">       4126 :       s2_resps_3_bits_u &lt;= _tables_3_io_resp_bits_u;</span></a>
+<a name="640"><span class="lineNum">     640 </span><span class="lineCov">       4126 :       s2_resps_3_bits_target &lt;= _tables_3_io_resp_bits_target;</span></a>
+<a name="641"><span class="lineNum">     641 </span><span class="lineCov">       4126 :       s2_resps_4_valid &lt;= _tables_4_io_resp_valid;</span></a>
+<a name="642"><span class="lineNum">     642 </span><span class="lineCov">       4126 :       s2_resps_4_bits_ctr &lt;= _tables_4_io_resp_bits_ctr;</span></a>
+<a name="643"><span class="lineNum">     643 </span><span class="lineCov">       4126 :       s2_resps_4_bits_u &lt;= _tables_4_io_resp_bits_u;</span></a>
+<a name="644"><span class="lineNum">     644 </span><span class="lineCov">       4126 :       s2_resps_4_bits_target &lt;= _tables_4_io_resp_bits_target;</span></a>
+<a name="645"><span class="lineNum">     645 </span>            :     end</a>
+<a name="646"><span class="lineNum">     646 </span><span class="lineCov">       8150 :     if (io_s2_fire_0) begin</span></a>
+<a name="647"><span class="lineNum">     647 </span><span class="lineCov">       4075 :       s3_tageTaken_dup_0 &lt;= _s2_tageTaken_T_9;</span></a>
+<a name="648"><span class="lineNum">     648 </span><span class="lineCov">       4075 :       s3_tageTarget_dup_0 &lt;= _s2_tageTarget_T_12;</span></a>
+<a name="649"><span class="lineNum">     649 </span>            :     end</a>
+<a name="650"><span class="lineNum">     650 </span><span class="lineCov">       8150 :     if (io_s2_fire_1) begin</span></a>
+<a name="651"><span class="lineNum">     651 </span><span class="lineCov">       4075 :       s3_tageTaken_dup_1 &lt;= _s2_tageTaken_T_9;</span></a>
+<a name="652"><span class="lineNum">     652 </span><span class="lineCov">       4075 :       s3_tageTarget_dup_1 &lt;= _s2_tageTarget_T_12;</span></a>
+<a name="653"><span class="lineNum">     653 </span>            :     end</a>
+<a name="654"><span class="lineNum">     654 </span><span class="lineCov">       8150 :     if (io_s2_fire_2) begin</span></a>
+<a name="655"><span class="lineNum">     655 </span><span class="lineCov">       4075 :       s3_tageTaken_dup_2 &lt;= _s2_tageTaken_T_9;</span></a>
+<a name="656"><span class="lineNum">     656 </span><span class="lineCov">       4075 :       s3_tageTarget_dup_2 &lt;= _s2_tageTarget_T_12;</span></a>
+<a name="657"><span class="lineNum">     657 </span>            :     end</a>
+<a name="658"><span class="lineNum">     658 </span><span class="lineCov">       8150 :     if (io_s2_fire_3) begin</span></a>
+<a name="659"><span class="lineNum">     659 </span><span class="lineCov">       4075 :       s3_tageTaken_dup_3 &lt;= _s2_tageTaken_T_9;</span></a>
+<a name="660"><span class="lineNum">     660 </span><span class="lineCov">       4075 :       s3_tageTarget_dup_3 &lt;= _s2_tageTarget_T_12;</span></a>
+<a name="661"><span class="lineNum">     661 </span><span class="lineCov">       4075 :       s3_providerTarget &lt;= selectedInfo_first_target;</span></a>
+<a name="662"><span class="lineNum">     662 </span><span class="lineCov">       4075 :       s3_altProviderTarget &lt;= selectedInfo_second_target;</span></a>
+<a name="663"><span class="lineNum">     663 </span><span class="lineCov">       4075 :       s3_provided &lt;= selectedInfo_hasOne;</span></a>
+<a name="664"><span class="lineNum">     664 </span><span class="lineCov">       4075 :       s3_provider &lt;= selectedInfo_first_tableIdx;</span></a>
+<a name="665"><span class="lineNum">     665 </span><span class="lineCov">       4075 :       s3_altProvided &lt;= selectedInfo_hasTwo;</span></a>
+<a name="666"><span class="lineNum">     666 </span><span class="lineCov">       4075 :       s3_altProvider &lt;=</span></a>
+<a name="667"><span class="lineNum">     667 </span><span class="lineCov">       4075 :         (selectedInfo_res_hasOne | ~s2_resps_2_valid</span></a>
+<a name="668"><span class="lineNum">     668 </span><span class="lineCov">       4075 :            ? 3'h0</span></a>
+<a name="669"><span class="lineNum">     669 </span><span class="lineCov">       4075 :            : selectedInfo_res_1_first_tableIdx)</span></a>
+<a name="670"><span class="lineNum">     670 </span><span class="lineCov">       4075 :         | (_selectedInfo_T_91 ? selectedInfo_res_2_first_tableIdx : 3'h0)</span></a>
+<a name="671"><span class="lineNum">     671 </span><span class="lineCov">       4075 :         | (selectedInfo_res_hasTwo</span></a>
+<a name="672"><span class="lineNum">     672 </span><span class="lineCov">       4075 :              ? (s2_resps_4_valid ? 3'h0 : 3'h3) | (s2_resps_4_valid ? 3'h3 : 3'h0)</span></a>
+<a name="673"><span class="lineNum">     673 </span><span class="lineCov">       4075 :              : 3'h0);</span></a>
+<a name="674"><span class="lineNum">     674 </span><span class="lineCov">       4075 :       s3_finalAltPred &lt;= ~selectedInfo_hasTwo | selectedInfo_second_ctr[1];</span></a>
+<a name="675"><span class="lineNum">     675 </span><span class="lineCov">       4075 :       s3_providerU &lt;=</span></a>
+<a name="676"><span class="lineNum">     676 </span><span class="lineCov">       4075 :         selectedInfo_res_hasOne</span></a>
+<a name="677"><span class="lineNum">     677 </span><span class="lineCov">       4075 :           ? (s2_resps_4_valid ? s2_resps_4_bits_u[0] : s2_resps_3_bits_u[0])</span></a>
+<a name="678"><span class="lineNum">     678 </span><span class="lineCov">       4075 :           : s2_resps_2_valid</span></a>
+<a name="679"><span class="lineNum">     679 </span><span class="lineCov">       4075 :               ? s2_resps_2_bits_u[0]</span></a>
+<a name="680"><span class="lineNum">     680 </span><span class="lineCov">       4075 :               : s2_resps_1_valid ? s2_resps_1_bits_u[0] : s2_resps_0_bits_u[0];</span></a>
+<a name="681"><span class="lineNum">     681 </span><span class="lineCov">       4075 :       s3_providerCtr &lt;= selectedInfo_first_ctr;</span></a>
+<a name="682"><span class="lineNum">     682 </span><span class="lineCov">       4075 :       s3_altProviderCtr &lt;= selectedInfo_second_ctr;</span></a>
+<a name="683"><span class="lineNum">     683 </span><span class="lineCov">       4075 :       resp_meta_allocate_valid_r &lt;= |_GEN_19;</span></a>
+<a name="684"><span class="lineNum">     684 </span><span class="lineCov">       4075 :       resp_meta_allocate_bits_r &lt;=</span></a>
+<a name="685"><span class="lineNum">     685 </span><span class="lineCov">       4075 :         _s2_allocEntry_T[0]</span></a>
+<a name="686"><span class="lineNum">     686 </span><span class="lineCov">       4075 :           ? s2_maskedEntry</span></a>
+<a name="687"><span class="lineNum">     687 </span><span class="lineCov">       4075 :           : _GEN_19[0]</span></a>
+<a name="688"><span class="lineNum">     688 </span><span class="lineCov">       4075 :               ? 3'h0</span></a>
+<a name="689"><span class="lineNum">     689 </span><span class="lineCov">       4075 :               : _GEN_19[1]</span></a>
+<a name="690"><span class="lineNum">     690 </span><span class="lineCov">       4075 :                   ? 3'h1</span></a>
+<a name="691"><span class="lineNum">     691 </span><span class="lineCov">       4075 :                   : _GEN_19[2] ? 3'h2 : _GEN_19[3] ? 3'h3 : _GEN_19[4] ? 3'h4 : 3'h7;</span></a>
+<a name="692"><span class="lineNum">     692 </span>            :     end</a>
+<a name="693"><span class="lineNum">     693 </span><span class="lineCov">      63847 :     tables_0_io_update_valid_REG &lt;= updateMask_0;</span></a>
+<a name="694"><span class="lineNum">     694 </span><span class="lineCov">      63847 :     tables_0_io_update_reset_u_REG &lt;= &amp;tickCtr;</span></a>
+<a name="695"><span class="lineNum">     695 </span><span class="lineNoCov">          0 :     if (updateMask_0) begin</span></a>
+<a name="696"><span class="lineNum">     696 </span><span class="lineNoCov">          0 :       tables_0_io_update_correct_r &lt;= _GEN_8 | _GEN_1 &amp; _updateCorrect_T;</span></a>
+<a name="697"><span class="lineNum">     697 </span><span class="lineNoCov">          0 :       tables_0_io_update_target_r &lt;= io_update_bits_full_target;</span></a>
+<a name="698"><span class="lineNum">     698 </span><span class="lineNoCov">          0 :       tables_0_io_update_old_target_r &lt;=</span></a>
+<a name="699"><span class="lineNum">     699 </span><span class="lineNoCov">          0 :         _GEN_1 ? io_update_bits_meta[81:41] : io_update_bits_meta[40:0];</span></a>
+<a name="700"><span class="lineNum">     700 </span><span class="lineNoCov">          0 :       tables_0_io_update_alloc_r &lt;= _GEN_17 &amp; _GEN_7;</span></a>
+<a name="701"><span class="lineNum">     701 </span><span class="lineNoCov">          0 :       tables_0_io_update_oldCtr_r &lt;=</span></a>
+<a name="702"><span class="lineNum">     702 </span><span class="lineNoCov">          0 :         _GEN_1 ? io_update_bits_meta[90:89] : io_update_bits_meta[88:87];</span></a>
+<a name="703"><span class="lineNum">     703 </span><span class="lineNoCov">          0 :       tables_0_io_update_uValid_r &lt;= _GEN_8 | _GEN_2 &amp; _GEN_1;</span></a>
+<a name="704"><span class="lineNum">     704 </span><span class="lineNoCov">          0 :       tables_0_io_update_u_r &lt;= ~_GEN_8 &amp; _updateU_T_2;</span></a>
+<a name="705"><span class="lineNum">     705 </span><span class="lineNoCov">          0 :       tables_0_io_update_pc_r &lt;= io_update_bits_pc;</span></a>
+<a name="706"><span class="lineNum">     706 </span><span class="lineNoCov">          0 :       tables_0_io_update_folded_hist_r_hist_12_folded_hist &lt;=</span></a>
+<a name="707"><span class="lineNum">     707 </span><span class="lineNoCov">          0 :         io_update_bits_spec_info_folded_hist_hist_12_folded_hist;</span></a>
+<a name="708"><span class="lineNum">     708 </span>            :     end</a>
+<a name="709"><span class="lineNum">     709 </span><span class="lineCov">      63847 :     tables_1_io_update_valid_REG &lt;= updateMask_1;</span></a>
+<a name="710"><span class="lineNum">     710 </span><span class="lineCov">      63847 :     tables_1_io_update_reset_u_REG &lt;= &amp;tickCtr;</span></a>
+<a name="711"><span class="lineNum">     711 </span><span class="lineNoCov">          0 :     if (updateMask_1) begin</span></a>
+<a name="712"><span class="lineNum">     712 </span><span class="lineNoCov">          0 :       tables_1_io_update_correct_r &lt;= _GEN_10 | _GEN_3 &amp; _updateCorrect_T;</span></a>
+<a name="713"><span class="lineNum">     713 </span><span class="lineNoCov">          0 :       tables_1_io_update_target_r &lt;= io_update_bits_full_target;</span></a>
+<a name="714"><span class="lineNum">     714 </span><span class="lineNoCov">          0 :       tables_1_io_update_old_target_r &lt;=</span></a>
+<a name="715"><span class="lineNum">     715 </span><span class="lineNoCov">          0 :         _GEN_3 ? io_update_bits_meta[81:41] : io_update_bits_meta[40:0];</span></a>
+<a name="716"><span class="lineNum">     716 </span><span class="lineNoCov">          0 :       tables_1_io_update_alloc_r &lt;= _GEN_17 &amp; _GEN_9;</span></a>
+<a name="717"><span class="lineNum">     717 </span><span class="lineNoCov">          0 :       tables_1_io_update_oldCtr_r &lt;=</span></a>
+<a name="718"><span class="lineNum">     718 </span><span class="lineNoCov">          0 :         _GEN_3 ? io_update_bits_meta[90:89] : io_update_bits_meta[88:87];</span></a>
+<a name="719"><span class="lineNum">     719 </span><span class="lineNoCov">          0 :       tables_1_io_update_uValid_r &lt;= _GEN_10 | _GEN_2 &amp; _GEN_3;</span></a>
+<a name="720"><span class="lineNum">     720 </span><span class="lineNoCov">          0 :       tables_1_io_update_u_r &lt;= ~_GEN_10 &amp; _updateU_T_2;</span></a>
+<a name="721"><span class="lineNum">     721 </span><span class="lineNoCov">          0 :       tables_1_io_update_pc_r &lt;= io_update_bits_pc;</span></a>
+<a name="722"><span class="lineNum">     722 </span><span class="lineNoCov">          0 :       tables_1_io_update_folded_hist_r_hist_14_folded_hist &lt;=</span></a>
+<a name="723"><span class="lineNum">     723 </span><span class="lineNoCov">          0 :         io_update_bits_spec_info_folded_hist_hist_14_folded_hist;</span></a>
+<a name="724"><span class="lineNum">     724 </span>            :     end</a>
+<a name="725"><span class="lineNum">     725 </span><span class="lineCov">      63847 :     tables_2_io_update_valid_REG &lt;= updateMask_2;</span></a>
+<a name="726"><span class="lineNum">     726 </span><span class="lineCov">      63847 :     tables_2_io_update_reset_u_REG &lt;= &amp;tickCtr;</span></a>
+<a name="727"><span class="lineNum">     727 </span><span class="lineNoCov">          0 :     if (updateMask_2) begin</span></a>
+<a name="728"><span class="lineNum">     728 </span><span class="lineNoCov">          0 :       tables_2_io_update_correct_r &lt;= _GEN_12 | _GEN_4 &amp; _updateCorrect_T;</span></a>
+<a name="729"><span class="lineNum">     729 </span><span class="lineNoCov">          0 :       tables_2_io_update_target_r &lt;= io_update_bits_full_target;</span></a>
+<a name="730"><span class="lineNum">     730 </span><span class="lineNoCov">          0 :       tables_2_io_update_old_target_r &lt;=</span></a>
+<a name="731"><span class="lineNum">     731 </span><span class="lineNoCov">          0 :         _GEN_4 ? io_update_bits_meta[81:41] : io_update_bits_meta[40:0];</span></a>
+<a name="732"><span class="lineNum">     732 </span><span class="lineNoCov">          0 :       tables_2_io_update_alloc_r &lt;= _GEN_17 &amp; _GEN_11;</span></a>
+<a name="733"><span class="lineNum">     733 </span><span class="lineNoCov">          0 :       tables_2_io_update_oldCtr_r &lt;=</span></a>
+<a name="734"><span class="lineNum">     734 </span><span class="lineNoCov">          0 :         _GEN_4 ? io_update_bits_meta[90:89] : io_update_bits_meta[88:87];</span></a>
+<a name="735"><span class="lineNum">     735 </span><span class="lineNoCov">          0 :       tables_2_io_update_uValid_r &lt;= _GEN_12 | _GEN_2 &amp; _GEN_4;</span></a>
+<a name="736"><span class="lineNum">     736 </span><span class="lineNoCov">          0 :       tables_2_io_update_u_r &lt;= ~_GEN_12 &amp; _updateU_T_2;</span></a>
+<a name="737"><span class="lineNum">     737 </span><span class="lineNoCov">          0 :       tables_2_io_update_pc_r &lt;= io_update_bits_pc;</span></a>
+<a name="738"><span class="lineNum">     738 </span><span class="lineNoCov">          0 :       tables_2_io_update_folded_hist_r_hist_13_folded_hist &lt;=</span></a>
+<a name="739"><span class="lineNum">     739 </span><span class="lineNoCov">          0 :         io_update_bits_spec_info_folded_hist_hist_13_folded_hist;</span></a>
+<a name="740"><span class="lineNum">     740 </span><span class="lineNoCov">          0 :       tables_2_io_update_folded_hist_r_hist_4_folded_hist &lt;=</span></a>
+<a name="741"><span class="lineNum">     741 </span><span class="lineNoCov">          0 :         io_update_bits_spec_info_folded_hist_hist_4_folded_hist;</span></a>
+<a name="742"><span class="lineNum">     742 </span>            :     end</a>
+<a name="743"><span class="lineNum">     743 </span><span class="lineCov">      63847 :     tables_3_io_update_valid_REG &lt;= updateMask_3;</span></a>
+<a name="744"><span class="lineNum">     744 </span><span class="lineCov">      63847 :     tables_3_io_update_reset_u_REG &lt;= &amp;tickCtr;</span></a>
+<a name="745"><span class="lineNum">     745 </span><span class="lineNoCov">          0 :     if (updateMask_3) begin</span></a>
+<a name="746"><span class="lineNum">     746 </span><span class="lineNoCov">          0 :       tables_3_io_update_correct_r &lt;= _GEN_14 | _GEN_5 &amp; _updateCorrect_T;</span></a>
+<a name="747"><span class="lineNum">     747 </span><span class="lineNoCov">          0 :       tables_3_io_update_target_r &lt;= io_update_bits_full_target;</span></a>
+<a name="748"><span class="lineNum">     748 </span><span class="lineNoCov">          0 :       tables_3_io_update_old_target_r &lt;=</span></a>
+<a name="749"><span class="lineNum">     749 </span><span class="lineNoCov">          0 :         _GEN_5 ? io_update_bits_meta[81:41] : io_update_bits_meta[40:0];</span></a>
+<a name="750"><span class="lineNum">     750 </span><span class="lineNoCov">          0 :       tables_3_io_update_alloc_r &lt;= _GEN_17 &amp; _GEN_13;</span></a>
+<a name="751"><span class="lineNum">     751 </span><span class="lineNoCov">          0 :       tables_3_io_update_oldCtr_r &lt;=</span></a>
+<a name="752"><span class="lineNum">     752 </span><span class="lineNoCov">          0 :         _GEN_5 ? io_update_bits_meta[90:89] : io_update_bits_meta[88:87];</span></a>
+<a name="753"><span class="lineNum">     753 </span><span class="lineNoCov">          0 :       tables_3_io_update_uValid_r &lt;= _GEN_14 | _GEN_2 &amp; _GEN_5;</span></a>
+<a name="754"><span class="lineNum">     754 </span><span class="lineNoCov">          0 :       tables_3_io_update_u_r &lt;= ~_GEN_14 &amp; _updateU_T_2;</span></a>
+<a name="755"><span class="lineNum">     755 </span><span class="lineNoCov">          0 :       tables_3_io_update_pc_r &lt;= io_update_bits_pc;</span></a>
+<a name="756"><span class="lineNum">     756 </span><span class="lineNoCov">          0 :       tables_3_io_update_folded_hist_r_hist_6_folded_hist &lt;=</span></a>
+<a name="757"><span class="lineNum">     757 </span><span class="lineNoCov">          0 :         io_update_bits_spec_info_folded_hist_hist_6_folded_hist;</span></a>
+<a name="758"><span class="lineNum">     758 </span><span class="lineNoCov">          0 :       tables_3_io_update_folded_hist_r_hist_2_folded_hist &lt;=</span></a>
+<a name="759"><span class="lineNum">     759 </span><span class="lineNoCov">          0 :         io_update_bits_spec_info_folded_hist_hist_2_folded_hist;</span></a>
+<a name="760"><span class="lineNum">     760 </span>            :     end</a>
+<a name="761"><span class="lineNum">     761 </span><span class="lineCov">      63847 :     tables_4_io_update_valid_REG &lt;= updateMask_4;</span></a>
+<a name="762"><span class="lineNum">     762 </span><span class="lineCov">      63847 :     tables_4_io_update_reset_u_REG &lt;= &amp;tickCtr;</span></a>
+<a name="763"><span class="lineNum">     763 </span><span class="lineNoCov">          0 :     if (updateMask_4) begin</span></a>
+<a name="764"><span class="lineNum">     764 </span><span class="lineNoCov">          0 :       tables_4_io_update_correct_r &lt;= _GEN_16 | _GEN_6 &amp; _updateCorrect_T;</span></a>
+<a name="765"><span class="lineNum">     765 </span><span class="lineNoCov">          0 :       tables_4_io_update_target_r &lt;= io_update_bits_full_target;</span></a>
+<a name="766"><span class="lineNum">     766 </span><span class="lineNoCov">          0 :       tables_4_io_update_old_target_r &lt;=</span></a>
+<a name="767"><span class="lineNum">     767 </span><span class="lineNoCov">          0 :         _GEN_6 ? io_update_bits_meta[81:41] : io_update_bits_meta[40:0];</span></a>
+<a name="768"><span class="lineNum">     768 </span><span class="lineNoCov">          0 :       tables_4_io_update_alloc_r &lt;= _GEN_17 &amp; _GEN_15;</span></a>
+<a name="769"><span class="lineNum">     769 </span><span class="lineNoCov">          0 :       tables_4_io_update_oldCtr_r &lt;=</span></a>
+<a name="770"><span class="lineNum">     770 </span><span class="lineNoCov">          0 :         _GEN_6 ? io_update_bits_meta[90:89] : io_update_bits_meta[88:87];</span></a>
+<a name="771"><span class="lineNum">     771 </span><span class="lineNoCov">          0 :       tables_4_io_update_uValid_r &lt;= _GEN_16 | _GEN_2 &amp; _GEN_6;</span></a>
+<a name="772"><span class="lineNum">     772 </span><span class="lineNoCov">          0 :       tables_4_io_update_u_r &lt;= ~_GEN_16 &amp; _updateU_T_2;</span></a>
+<a name="773"><span class="lineNum">     773 </span><span class="lineNoCov">          0 :       tables_4_io_update_pc_r &lt;= io_update_bits_pc;</span></a>
+<a name="774"><span class="lineNum">     774 </span><span class="lineNoCov">          0 :       tables_4_io_update_folded_hist_r_hist_10_folded_hist &lt;=</span></a>
+<a name="775"><span class="lineNum">     775 </span><span class="lineNoCov">          0 :         io_update_bits_spec_info_folded_hist_hist_10_folded_hist;</span></a>
+<a name="776"><span class="lineNum">     776 </span><span class="lineNoCov">          0 :       tables_4_io_update_folded_hist_r_hist_3_folded_hist &lt;=</span></a>
+<a name="777"><span class="lineNum">     777 </span><span class="lineNoCov">          0 :         io_update_bits_spec_info_folded_hist_hist_3_folded_hist;</span></a>
+<a name="778"><span class="lineNum">     778 </span>            :     end</a>
+<a name="779"><span class="lineNum">     779 </span>            :   end // always @(posedge)</a>
+<a name="780"><span class="lineNum">     780 </span>            :   `ifdef ENABLE_INITIAL_REG_</a>
+<a name="781"><span class="lineNum">     781 </span>            :     `ifdef FIRRTL_BEFORE_INITIAL</a>
+<a name="782"><span class="lineNum">     782 </span>            :       `FIRRTL_BEFORE_INITIAL</a>
+<a name="783"><span class="lineNum">     783 </span>            :     `endif // FIRRTL_BEFORE_INITIAL</a>
+<a name="784"><span class="lineNum">     784 </span>            :     logic [31:0] _RANDOM[0:79];</a>
+<a name="785"><span class="lineNum">     785 </span><span class="lineCov">         58 :     initial begin</span></a>
+<a name="786"><span class="lineNum">     786 </span>            :       `ifdef INIT_RANDOM_PROLOG_</a>
+<a name="787"><span class="lineNum">     787 </span>            :         `INIT_RANDOM_PROLOG_</a>
+<a name="788"><span class="lineNum">     788 </span>            :       `endif // INIT_RANDOM_PROLOG_</a>
+<a name="789"><span class="lineNum">     789 </span>            :       `ifdef RANDOMIZE_REG_INIT</a>
+<a name="790"><span class="lineNum">     790 </span>            :         for (logic [6:0] i = 7'h0; i &lt; 7'h50; i += 7'h1) begin</a>
+<a name="791"><span class="lineNum">     791 </span>            :           _RANDOM[i] = `RANDOM;</a>
+<a name="792"><span class="lineNum">     792 </span>            :         end</a>
+<a name="793"><span class="lineNum">     793 </span>            :         tickCtr = _RANDOM[7'hF][25:18];</a>
+<a name="794"><span class="lineNum">     794 </span>            :         s2_resps_0_valid = _RANDOM[7'hF][26];</a>
+<a name="795"><span class="lineNum">     795 </span>            :         s2_resps_0_bits_ctr = _RANDOM[7'hF][28:27];</a>
+<a name="796"><span class="lineNum">     796 </span>            :         s2_resps_0_bits_u = _RANDOM[7'hF][30:29];</a>
+<a name="797"><span class="lineNum">     797 </span>            :         s2_resps_0_bits_target = {_RANDOM[7'hF][31], _RANDOM[7'h10], _RANDOM[7'h11][7:0]};</a>
+<a name="798"><span class="lineNum">     798 </span>            :         s2_resps_1_valid = _RANDOM[7'h11][8];</a>
+<a name="799"><span class="lineNum">     799 </span>            :         s2_resps_1_bits_ctr = _RANDOM[7'h11][10:9];</a>
+<a name="800"><span class="lineNum">     800 </span>            :         s2_resps_1_bits_u = _RANDOM[7'h11][12:11];</a>
+<a name="801"><span class="lineNum">     801 </span>            :         s2_resps_1_bits_target = {_RANDOM[7'h11][31:13], _RANDOM[7'h12][21:0]};</a>
+<a name="802"><span class="lineNum">     802 </span>            :         s2_resps_2_valid = _RANDOM[7'h12][22];</a>
+<a name="803"><span class="lineNum">     803 </span>            :         s2_resps_2_bits_ctr = _RANDOM[7'h12][24:23];</a>
+<a name="804"><span class="lineNum">     804 </span>            :         s2_resps_2_bits_u = _RANDOM[7'h12][26:25];</a>
+<a name="805"><span class="lineNum">     805 </span>            :         s2_resps_2_bits_target =</a>
+<a name="806"><span class="lineNum">     806 </span>            :           {_RANDOM[7'h12][31:27], _RANDOM[7'h13], _RANDOM[7'h14][3:0]};</a>
+<a name="807"><span class="lineNum">     807 </span>            :         s2_resps_3_valid = _RANDOM[7'h14][4];</a>
+<a name="808"><span class="lineNum">     808 </span>            :         s2_resps_3_bits_ctr = _RANDOM[7'h14][6:5];</a>
+<a name="809"><span class="lineNum">     809 </span>            :         s2_resps_3_bits_u = _RANDOM[7'h14][8:7];</a>
+<a name="810"><span class="lineNum">     810 </span>            :         s2_resps_3_bits_target = {_RANDOM[7'h14][31:9], _RANDOM[7'h15][17:0]};</a>
+<a name="811"><span class="lineNum">     811 </span>            :         s2_resps_4_valid = _RANDOM[7'h15][18];</a>
+<a name="812"><span class="lineNum">     812 </span>            :         s2_resps_4_bits_ctr = _RANDOM[7'h15][20:19];</a>
+<a name="813"><span class="lineNum">     813 </span>            :         s2_resps_4_bits_u = _RANDOM[7'h15][22:21];</a>
+<a name="814"><span class="lineNum">     814 </span>            :         s2_resps_4_bits_target = {_RANDOM[7'h15][31:23], _RANDOM[7'h16]};</a>
+<a name="815"><span class="lineNum">     815 </span>            :         s3_tageTaken_dup_0 = _RANDOM[7'h1A][27];</a>
+<a name="816"><span class="lineNum">     816 </span>            :         s3_tageTaken_dup_1 = _RANDOM[7'h1A][28];</a>
+<a name="817"><span class="lineNum">     817 </span>            :         s3_tageTaken_dup_2 = _RANDOM[7'h1A][29];</a>
+<a name="818"><span class="lineNum">     818 </span>            :         s3_tageTaken_dup_3 = _RANDOM[7'h1A][30];</a>
+<a name="819"><span class="lineNum">     819 </span>            :         s3_tageTarget_dup_0 = {_RANDOM[7'h1A][31], _RANDOM[7'h1B], _RANDOM[7'h1C][7:0]};</a>
+<a name="820"><span class="lineNum">     820 </span>            :         s3_tageTarget_dup_1 = {_RANDOM[7'h1C][31:8], _RANDOM[7'h1D][16:0]};</a>
+<a name="821"><span class="lineNum">     821 </span>            :         s3_tageTarget_dup_2 = {_RANDOM[7'h1D][31:17], _RANDOM[7'h1E][25:0]};</a>
+<a name="822"><span class="lineNum">     822 </span>            :         s3_tageTarget_dup_3 =</a>
+<a name="823"><span class="lineNum">     823 </span>            :           {_RANDOM[7'h1E][31:26], _RANDOM[7'h1F], _RANDOM[7'h20][2:0]};</a>
+<a name="824"><span class="lineNum">     824 </span>            :         s3_providerTarget = {_RANDOM[7'h20][31:3], _RANDOM[7'h21][11:0]};</a>
+<a name="825"><span class="lineNum">     825 </span>            :         s3_altProviderTarget = {_RANDOM[7'h21][31:12], _RANDOM[7'h22][20:0]};</a>
+<a name="826"><span class="lineNum">     826 </span>            :         s3_provided = _RANDOM[7'h22][21];</a>
+<a name="827"><span class="lineNum">     827 </span>            :         s3_provider = _RANDOM[7'h22][24:22];</a>
+<a name="828"><span class="lineNum">     828 </span>            :         s3_altProvided = _RANDOM[7'h22][25];</a>
+<a name="829"><span class="lineNum">     829 </span>            :         s3_altProvider = _RANDOM[7'h22][28:26];</a>
+<a name="830"><span class="lineNum">     830 </span>            :         s3_finalAltPred = _RANDOM[7'h22][29];</a>
+<a name="831"><span class="lineNum">     831 </span>            :         s3_providerU = _RANDOM[7'h22][30];</a>
+<a name="832"><span class="lineNum">     832 </span>            :         s3_providerCtr = {_RANDOM[7'h22][31], _RANDOM[7'h23][0]};</a>
+<a name="833"><span class="lineNum">     833 </span>            :         s3_altProviderCtr = _RANDOM[7'h23][2:1];</a>
+<a name="834"><span class="lineNum">     834 </span>            :         s2_allocLFSR_lfsr = {_RANDOM[7'h23][31:3], _RANDOM[7'h24], _RANDOM[7'h25][2:0]};</a>
+<a name="835"><span class="lineNum">     835 </span>            :         resp_meta_allocate_valid_r = _RANDOM[7'h25][3];</a>
+<a name="836"><span class="lineNum">     836 </span>            :         resp_meta_allocate_bits_r = _RANDOM[7'h25][6:4];</a>
+<a name="837"><span class="lineNum">     837 </span>            :         tables_0_io_update_valid_REG = _RANDOM[7'h25][7];</a>
+<a name="838"><span class="lineNum">     838 </span>            :         tables_0_io_update_reset_u_REG = _RANDOM[7'h25][8];</a>
+<a name="839"><span class="lineNum">     839 </span>            :         tables_0_io_update_correct_r = _RANDOM[7'h25][9];</a>
+<a name="840"><span class="lineNum">     840 </span>            :         tables_0_io_update_target_r = {_RANDOM[7'h25][31:10], _RANDOM[7'h26][18:0]};</a>
+<a name="841"><span class="lineNum">     841 </span>            :         tables_0_io_update_old_target_r = {_RANDOM[7'h26][31:19], _RANDOM[7'h27][27:0]};</a>
+<a name="842"><span class="lineNum">     842 </span>            :         tables_0_io_update_alloc_r = _RANDOM[7'h27][28];</a>
+<a name="843"><span class="lineNum">     843 </span>            :         tables_0_io_update_oldCtr_r = _RANDOM[7'h27][30:29];</a>
+<a name="844"><span class="lineNum">     844 </span>            :         tables_0_io_update_uValid_r = _RANDOM[7'h27][31];</a>
+<a name="845"><span class="lineNum">     845 </span>            :         tables_0_io_update_u_r = _RANDOM[7'h28][0];</a>
+<a name="846"><span class="lineNum">     846 </span>            :         tables_0_io_update_pc_r = {_RANDOM[7'h28][31:1], _RANDOM[7'h29][9:0]};</a>
+<a name="847"><span class="lineNum">     847 </span>            :         tables_0_io_update_folded_hist_r_hist_12_folded_hist = _RANDOM[7'h2A][27:24];</a>
+<a name="848"><span class="lineNum">     848 </span>            :         tables_1_io_update_valid_REG = _RANDOM[7'h2D][30];</a>
+<a name="849"><span class="lineNum">     849 </span>            :         tables_1_io_update_reset_u_REG = _RANDOM[7'h2D][31];</a>
+<a name="850"><span class="lineNum">     850 </span>            :         tables_1_io_update_correct_r = _RANDOM[7'h2E][0];</a>
+<a name="851"><span class="lineNum">     851 </span>            :         tables_1_io_update_target_r = {_RANDOM[7'h2E][31:1], _RANDOM[7'h2F][9:0]};</a>
+<a name="852"><span class="lineNum">     852 </span>            :         tables_1_io_update_old_target_r = {_RANDOM[7'h2F][31:10], _RANDOM[7'h30][18:0]};</a>
+<a name="853"><span class="lineNum">     853 </span>            :         tables_1_io_update_alloc_r = _RANDOM[7'h30][19];</a>
+<a name="854"><span class="lineNum">     854 </span>            :         tables_1_io_update_oldCtr_r = _RANDOM[7'h30][21:20];</a>
+<a name="855"><span class="lineNum">     855 </span>            :         tables_1_io_update_uValid_r = _RANDOM[7'h30][22];</a>
+<a name="856"><span class="lineNum">     856 </span>            :         tables_1_io_update_u_r = _RANDOM[7'h30][23];</a>
+<a name="857"><span class="lineNum">     857 </span>            :         tables_1_io_update_pc_r =</a>
+<a name="858"><span class="lineNum">     858 </span>            :           {_RANDOM[7'h30][31:24], _RANDOM[7'h31], _RANDOM[7'h32][0]};</a>
+<a name="859"><span class="lineNum">     859 </span>            :         tables_1_io_update_folded_hist_r_hist_14_folded_hist =</a>
+<a name="860"><span class="lineNum">     860 </span>            :           {_RANDOM[7'h32][31:30], _RANDOM[7'h33][5:0]};</a>
+<a name="861"><span class="lineNum">     861 </span>            :         tables_2_io_update_valid_REG = _RANDOM[7'h36][21];</a>
+<a name="862"><span class="lineNum">     862 </span>            :         tables_2_io_update_reset_u_REG = _RANDOM[7'h36][22];</a>
+<a name="863"><span class="lineNum">     863 </span>            :         tables_2_io_update_correct_r = _RANDOM[7'h36][23];</a>
+<a name="864"><span class="lineNum">     864 </span>            :         tables_2_io_update_target_r =</a>
+<a name="865"><span class="lineNum">     865 </span>            :           {_RANDOM[7'h36][31:24], _RANDOM[7'h37], _RANDOM[7'h38][0]};</a>
+<a name="866"><span class="lineNum">     866 </span>            :         tables_2_io_update_old_target_r = {_RANDOM[7'h38][31:1], _RANDOM[7'h39][9:0]};</a>
+<a name="867"><span class="lineNum">     867 </span>            :         tables_2_io_update_alloc_r = _RANDOM[7'h39][10];</a>
+<a name="868"><span class="lineNum">     868 </span>            :         tables_2_io_update_oldCtr_r = _RANDOM[7'h39][12:11];</a>
+<a name="869"><span class="lineNum">     869 </span>            :         tables_2_io_update_uValid_r = _RANDOM[7'h39][13];</a>
+<a name="870"><span class="lineNum">     870 </span>            :         tables_2_io_update_u_r = _RANDOM[7'h39][14];</a>
+<a name="871"><span class="lineNum">     871 </span>            :         tables_2_io_update_pc_r = {_RANDOM[7'h39][31:15], _RANDOM[7'h3A][23:0]};</a>
+<a name="872"><span class="lineNum">     872 </span>            :         tables_2_io_update_folded_hist_r_hist_13_folded_hist =</a>
+<a name="873"><span class="lineNum">     873 </span>            :           {_RANDOM[7'h3B][31:29], _RANDOM[7'h3C][5:0]};</a>
+<a name="874"><span class="lineNum">     874 </span>            :         tables_2_io_update_folded_hist_r_hist_4_folded_hist = _RANDOM[7'h3E][8:1];</a>
+<a name="875"><span class="lineNum">     875 </span>            :         tables_3_io_update_valid_REG = _RANDOM[7'h3F][12];</a>
+<a name="876"><span class="lineNum">     876 </span>            :         tables_3_io_update_reset_u_REG = _RANDOM[7'h3F][13];</a>
+<a name="877"><span class="lineNum">     877 </span>            :         tables_3_io_update_correct_r = _RANDOM[7'h3F][14];</a>
+<a name="878"><span class="lineNum">     878 </span>            :         tables_3_io_update_target_r = {_RANDOM[7'h3F][31:15], _RANDOM[7'h40][23:0]};</a>
+<a name="879"><span class="lineNum">     879 </span>            :         tables_3_io_update_old_target_r =</a>
+<a name="880"><span class="lineNum">     880 </span>            :           {_RANDOM[7'h40][31:24], _RANDOM[7'h41], _RANDOM[7'h42][0]};</a>
+<a name="881"><span class="lineNum">     881 </span>            :         tables_3_io_update_alloc_r = _RANDOM[7'h42][1];</a>
+<a name="882"><span class="lineNum">     882 </span>            :         tables_3_io_update_oldCtr_r = _RANDOM[7'h42][3:2];</a>
+<a name="883"><span class="lineNum">     883 </span>            :         tables_3_io_update_uValid_r = _RANDOM[7'h42][4];</a>
+<a name="884"><span class="lineNum">     884 </span>            :         tables_3_io_update_u_r = _RANDOM[7'h42][5];</a>
+<a name="885"><span class="lineNum">     885 </span>            :         tables_3_io_update_pc_r = {_RANDOM[7'h42][31:6], _RANDOM[7'h43][14:0]};</a>
+<a name="886"><span class="lineNum">     886 </span>            :         tables_3_io_update_folded_hist_r_hist_6_folded_hist = _RANDOM[7'h46][16:8];</a>
+<a name="887"><span class="lineNum">     887 </span>            :         tables_3_io_update_folded_hist_r_hist_2_folded_hist = _RANDOM[7'h47][15:8];</a>
+<a name="888"><span class="lineNum">     888 </span>            :         tables_4_io_update_valid_REG = _RANDOM[7'h48][3];</a>
+<a name="889"><span class="lineNum">     889 </span>            :         tables_4_io_update_reset_u_REG = _RANDOM[7'h48][4];</a>
+<a name="890"><span class="lineNum">     890 </span>            :         tables_4_io_update_correct_r = _RANDOM[7'h48][5];</a>
+<a name="891"><span class="lineNum">     891 </span>            :         tables_4_io_update_target_r = {_RANDOM[7'h48][31:6], _RANDOM[7'h49][14:0]};</a>
+<a name="892"><span class="lineNum">     892 </span>            :         tables_4_io_update_old_target_r = {_RANDOM[7'h49][31:15], _RANDOM[7'h4A][23:0]};</a>
+<a name="893"><span class="lineNum">     893 </span>            :         tables_4_io_update_alloc_r = _RANDOM[7'h4A][24];</a>
+<a name="894"><span class="lineNum">     894 </span>            :         tables_4_io_update_oldCtr_r = _RANDOM[7'h4A][26:25];</a>
+<a name="895"><span class="lineNum">     895 </span>            :         tables_4_io_update_uValid_r = _RANDOM[7'h4A][27];</a>
+<a name="896"><span class="lineNum">     896 </span>            :         tables_4_io_update_u_r = _RANDOM[7'h4A][28];</a>
+<a name="897"><span class="lineNum">     897 </span>            :         tables_4_io_update_pc_r =</a>
+<a name="898"><span class="lineNum">     898 </span>            :           {_RANDOM[7'h4A][31:29], _RANDOM[7'h4B], _RANDOM[7'h4C][5:0]};</a>
+<a name="899"><span class="lineNum">     899 </span>            :         tables_4_io_update_folded_hist_r_hist_10_folded_hist = _RANDOM[7'h4E][8:0];</a>
+<a name="900"><span class="lineNum">     900 </span>            :         tables_4_io_update_folded_hist_r_hist_3_folded_hist = _RANDOM[7'h4F][30:23];</a>
+<a name="901"><span class="lineNum">     901 </span>            :       `endif // RANDOMIZE_REG_INIT</a>
+<a name="902"><span class="lineNum">     902 </span><span class="lineCov">         17 :       if (reset) begin</span></a>
+<a name="903"><span class="lineNum">     903 </span><span class="lineCov">         12 :         tickCtr = 8'h0;</span></a>
+<a name="904"><span class="lineNum">     904 </span><span class="lineCov">         12 :         s2_allocLFSR_lfsr = 64'h1234567887654321;</span></a>
+<a name="905"><span class="lineNum">     905 </span>            :       end</a>
+<a name="906"><span class="lineNum">     906 </span>            :     end // initial</a>
+<a name="907"><span class="lineNum">     907 </span>            :     `ifdef FIRRTL_AFTER_INITIAL</a>
+<a name="908"><span class="lineNum">     908 </span>            :       `FIRRTL_AFTER_INITIAL</a>
+<a name="909"><span class="lineNum">     909 </span>            :     `endif // FIRRTL_AFTER_INITIAL</a>
+<a name="910"><span class="lineNum">     910 </span>            :   `endif // ENABLE_INITIAL_REG_</a>
+<a name="911"><span class="lineNum">     911 </span>            :   ITTageTable tables_0 (</a>
+<a name="912"><span class="lineNum">     912 </span>            :     .clock                                       (clock),</a>
+<a name="913"><span class="lineNum">     913 </span>            :     .reset                                       (reset),</a>
+<a name="914"><span class="lineNum">     914 </span>            :     .io_req_valid                                (io_s0_fire_3),</a>
+<a name="915"><span class="lineNum">     915 </span>            :     .io_req_bits_pc                              (io_in_bits_s0_pc_3),</a>
+<a name="916"><span class="lineNum">     916 </span>            :     .io_req_bits_folded_hist_hist_12_folded_hist</a>
+<a name="917"><span class="lineNum">     917 </span>            :       (io_in_bits_folded_hist_3_hist_12_folded_hist),</a>
+<a name="918"><span class="lineNum">     918 </span>            :     .io_resp_valid                               (_tables_0_io_resp_valid),</a>
+<a name="919"><span class="lineNum">     919 </span>            :     .io_resp_bits_ctr                            (_tables_0_io_resp_bits_ctr),</a>
+<a name="920"><span class="lineNum">     920 </span>            :     .io_resp_bits_u                              (_tables_0_io_resp_bits_u),</a>
+<a name="921"><span class="lineNum">     921 </span>            :     .io_resp_bits_target                         (_tables_0_io_resp_bits_target),</a>
+<a name="922"><span class="lineNum">     922 </span>            :     .io_update_pc                                (tables_0_io_update_pc_r),</a>
+<a name="923"><span class="lineNum">     923 </span>            :     .io_update_folded_hist_hist_12_folded_hist</a>
+<a name="924"><span class="lineNum">     924 </span>            :       (tables_0_io_update_folded_hist_r_hist_12_folded_hist),</a>
+<a name="925"><span class="lineNum">     925 </span>            :     .io_update_valid                             (tables_0_io_update_valid_REG),</a>
+<a name="926"><span class="lineNum">     926 </span>            :     .io_update_correct                           (tables_0_io_update_correct_r),</a>
+<a name="927"><span class="lineNum">     927 </span>            :     .io_update_alloc                             (tables_0_io_update_alloc_r),</a>
+<a name="928"><span class="lineNum">     928 </span>            :     .io_update_oldCtr                            (tables_0_io_update_oldCtr_r),</a>
+<a name="929"><span class="lineNum">     929 </span>            :     .io_update_uValid                            (tables_0_io_update_uValid_r),</a>
+<a name="930"><span class="lineNum">     930 </span>            :     .io_update_u                                 (tables_0_io_update_u_r),</a>
+<a name="931"><span class="lineNum">     931 </span>            :     .io_update_reset_u                           (tables_0_io_update_reset_u_REG),</a>
+<a name="932"><span class="lineNum">     932 </span>            :     .io_update_target                            (tables_0_io_update_target_r),</a>
+<a name="933"><span class="lineNum">     933 </span>            :     .io_update_old_target                        (tables_0_io_update_old_target_r)</a>
+<a name="934"><span class="lineNum">     934 </span>            :   );</a>
+<a name="935"><span class="lineNum">     935 </span>            :   ITTageTable_1 tables_1 (</a>
+<a name="936"><span class="lineNum">     936 </span>            :     .clock                                       (clock),</a>
+<a name="937"><span class="lineNum">     937 </span>            :     .reset                                       (reset),</a>
+<a name="938"><span class="lineNum">     938 </span>            :     .io_req_valid                                (io_s0_fire_3),</a>
+<a name="939"><span class="lineNum">     939 </span>            :     .io_req_bits_pc                              (io_in_bits_s0_pc_3),</a>
+<a name="940"><span class="lineNum">     940 </span>            :     .io_req_bits_folded_hist_hist_14_folded_hist</a>
+<a name="941"><span class="lineNum">     941 </span>            :       (io_in_bits_folded_hist_3_hist_14_folded_hist),</a>
+<a name="942"><span class="lineNum">     942 </span>            :     .io_resp_valid                               (_tables_1_io_resp_valid),</a>
+<a name="943"><span class="lineNum">     943 </span>            :     .io_resp_bits_ctr                            (_tables_1_io_resp_bits_ctr),</a>
+<a name="944"><span class="lineNum">     944 </span>            :     .io_resp_bits_u                              (_tables_1_io_resp_bits_u),</a>
+<a name="945"><span class="lineNum">     945 </span>            :     .io_resp_bits_target                         (_tables_1_io_resp_bits_target),</a>
+<a name="946"><span class="lineNum">     946 </span>            :     .io_update_pc                                (tables_1_io_update_pc_r),</a>
+<a name="947"><span class="lineNum">     947 </span>            :     .io_update_folded_hist_hist_14_folded_hist</a>
+<a name="948"><span class="lineNum">     948 </span>            :       (tables_1_io_update_folded_hist_r_hist_14_folded_hist),</a>
+<a name="949"><span class="lineNum">     949 </span>            :     .io_update_valid                             (tables_1_io_update_valid_REG),</a>
+<a name="950"><span class="lineNum">     950 </span>            :     .io_update_correct                           (tables_1_io_update_correct_r),</a>
+<a name="951"><span class="lineNum">     951 </span>            :     .io_update_alloc                             (tables_1_io_update_alloc_r),</a>
+<a name="952"><span class="lineNum">     952 </span>            :     .io_update_oldCtr                            (tables_1_io_update_oldCtr_r),</a>
+<a name="953"><span class="lineNum">     953 </span>            :     .io_update_uValid                            (tables_1_io_update_uValid_r),</a>
+<a name="954"><span class="lineNum">     954 </span>            :     .io_update_u                                 (tables_1_io_update_u_r),</a>
+<a name="955"><span class="lineNum">     955 </span>            :     .io_update_reset_u                           (tables_1_io_update_reset_u_REG),</a>
+<a name="956"><span class="lineNum">     956 </span>            :     .io_update_target                            (tables_1_io_update_target_r),</a>
+<a name="957"><span class="lineNum">     957 </span>            :     .io_update_old_target                        (tables_1_io_update_old_target_r)</a>
+<a name="958"><span class="lineNum">     958 </span>            :   );</a>
+<a name="959"><span class="lineNum">     959 </span>            :   ITTageTable_2 tables_2 (</a>
+<a name="960"><span class="lineNum">     960 </span>            :     .clock                                       (clock),</a>
+<a name="961"><span class="lineNum">     961 </span>            :     .reset                                       (reset),</a>
+<a name="962"><span class="lineNum">     962 </span>            :     .io_req_valid                                (io_s0_fire_3),</a>
+<a name="963"><span class="lineNum">     963 </span>            :     .io_req_bits_pc                              (io_in_bits_s0_pc_3),</a>
+<a name="964"><span class="lineNum">     964 </span>            :     .io_req_bits_folded_hist_hist_13_folded_hist</a>
+<a name="965"><span class="lineNum">     965 </span>            :       (io_in_bits_folded_hist_3_hist_13_folded_hist),</a>
+<a name="966"><span class="lineNum">     966 </span>            :     .io_req_bits_folded_hist_hist_4_folded_hist</a>
+<a name="967"><span class="lineNum">     967 </span>            :       (io_in_bits_folded_hist_3_hist_4_folded_hist),</a>
+<a name="968"><span class="lineNum">     968 </span>            :     .io_resp_valid                               (_tables_2_io_resp_valid),</a>
+<a name="969"><span class="lineNum">     969 </span>            :     .io_resp_bits_ctr                            (_tables_2_io_resp_bits_ctr),</a>
+<a name="970"><span class="lineNum">     970 </span>            :     .io_resp_bits_u                              (_tables_2_io_resp_bits_u),</a>
+<a name="971"><span class="lineNum">     971 </span>            :     .io_resp_bits_target                         (_tables_2_io_resp_bits_target),</a>
+<a name="972"><span class="lineNum">     972 </span>            :     .io_update_pc                                (tables_2_io_update_pc_r),</a>
+<a name="973"><span class="lineNum">     973 </span>            :     .io_update_folded_hist_hist_13_folded_hist</a>
+<a name="974"><span class="lineNum">     974 </span>            :       (tables_2_io_update_folded_hist_r_hist_13_folded_hist),</a>
+<a name="975"><span class="lineNum">     975 </span>            :     .io_update_folded_hist_hist_4_folded_hist</a>
+<a name="976"><span class="lineNum">     976 </span>            :       (tables_2_io_update_folded_hist_r_hist_4_folded_hist),</a>
+<a name="977"><span class="lineNum">     977 </span>            :     .io_update_valid                             (tables_2_io_update_valid_REG),</a>
+<a name="978"><span class="lineNum">     978 </span>            :     .io_update_correct                           (tables_2_io_update_correct_r),</a>
+<a name="979"><span class="lineNum">     979 </span>            :     .io_update_alloc                             (tables_2_io_update_alloc_r),</a>
+<a name="980"><span class="lineNum">     980 </span>            :     .io_update_oldCtr                            (tables_2_io_update_oldCtr_r),</a>
+<a name="981"><span class="lineNum">     981 </span>            :     .io_update_uValid                            (tables_2_io_update_uValid_r),</a>
+<a name="982"><span class="lineNum">     982 </span>            :     .io_update_u                                 (tables_2_io_update_u_r),</a>
+<a name="983"><span class="lineNum">     983 </span>            :     .io_update_reset_u                           (tables_2_io_update_reset_u_REG),</a>
+<a name="984"><span class="lineNum">     984 </span>            :     .io_update_target                            (tables_2_io_update_target_r),</a>
+<a name="985"><span class="lineNum">     985 </span>            :     .io_update_old_target                        (tables_2_io_update_old_target_r)</a>
+<a name="986"><span class="lineNum">     986 </span>            :   );</a>
+<a name="987"><span class="lineNum">     987 </span>            :   ITTageTable_3 tables_3 (</a>
+<a name="988"><span class="lineNum">     988 </span>            :     .clock                                      (clock),</a>
+<a name="989"><span class="lineNum">     989 </span>            :     .reset                                      (reset),</a>
+<a name="990"><span class="lineNum">     990 </span>            :     .io_req_valid                               (io_s0_fire_3),</a>
+<a name="991"><span class="lineNum">     991 </span>            :     .io_req_bits_pc                             (io_in_bits_s0_pc_3),</a>
+<a name="992"><span class="lineNum">     992 </span>            :     .io_req_bits_folded_hist_hist_6_folded_hist</a>
+<a name="993"><span class="lineNum">     993 </span>            :       (io_in_bits_folded_hist_3_hist_6_folded_hist),</a>
+<a name="994"><span class="lineNum">     994 </span>            :     .io_req_bits_folded_hist_hist_2_folded_hist</a>
+<a name="995"><span class="lineNum">     995 </span>            :       (io_in_bits_folded_hist_3_hist_2_folded_hist),</a>
+<a name="996"><span class="lineNum">     996 </span>            :     .io_resp_valid                              (_tables_3_io_resp_valid),</a>
+<a name="997"><span class="lineNum">     997 </span>            :     .io_resp_bits_ctr                           (_tables_3_io_resp_bits_ctr),</a>
+<a name="998"><span class="lineNum">     998 </span>            :     .io_resp_bits_u                             (_tables_3_io_resp_bits_u),</a>
+<a name="999"><span class="lineNum">     999 </span>            :     .io_resp_bits_target                        (_tables_3_io_resp_bits_target),</a>
+<a name="1000"><span class="lineNum">    1000 </span>            :     .io_update_pc                               (tables_3_io_update_pc_r),</a>
+<a name="1001"><span class="lineNum">    1001 </span>            :     .io_update_folded_hist_hist_6_folded_hist</a>
+<a name="1002"><span class="lineNum">    1002 </span>            :       (tables_3_io_update_folded_hist_r_hist_6_folded_hist),</a>
+<a name="1003"><span class="lineNum">    1003 </span>            :     .io_update_folded_hist_hist_2_folded_hist</a>
+<a name="1004"><span class="lineNum">    1004 </span>            :       (tables_3_io_update_folded_hist_r_hist_2_folded_hist),</a>
+<a name="1005"><span class="lineNum">    1005 </span>            :     .io_update_valid                            (tables_3_io_update_valid_REG),</a>
+<a name="1006"><span class="lineNum">    1006 </span>            :     .io_update_correct                          (tables_3_io_update_correct_r),</a>
+<a name="1007"><span class="lineNum">    1007 </span>            :     .io_update_alloc                            (tables_3_io_update_alloc_r),</a>
+<a name="1008"><span class="lineNum">    1008 </span>            :     .io_update_oldCtr                           (tables_3_io_update_oldCtr_r),</a>
+<a name="1009"><span class="lineNum">    1009 </span>            :     .io_update_uValid                           (tables_3_io_update_uValid_r),</a>
+<a name="1010"><span class="lineNum">    1010 </span>            :     .io_update_u                                (tables_3_io_update_u_r),</a>
+<a name="1011"><span class="lineNum">    1011 </span>            :     .io_update_reset_u                          (tables_3_io_update_reset_u_REG),</a>
+<a name="1012"><span class="lineNum">    1012 </span>            :     .io_update_target                           (tables_3_io_update_target_r),</a>
+<a name="1013"><span class="lineNum">    1013 </span>            :     .io_update_old_target                       (tables_3_io_update_old_target_r)</a>
+<a name="1014"><span class="lineNum">    1014 </span>            :   );</a>
+<a name="1015"><span class="lineNum">    1015 </span>            :   ITTageTable_4 tables_4 (</a>
+<a name="1016"><span class="lineNum">    1016 </span>            :     .clock                                       (clock),</a>
+<a name="1017"><span class="lineNum">    1017 </span>            :     .reset                                       (reset),</a>
+<a name="1018"><span class="lineNum">    1018 </span>            :     .io_req_valid                                (io_s0_fire_3),</a>
+<a name="1019"><span class="lineNum">    1019 </span>            :     .io_req_bits_pc                              (io_in_bits_s0_pc_3),</a>
+<a name="1020"><span class="lineNum">    1020 </span>            :     .io_req_bits_folded_hist_hist_10_folded_hist</a>
+<a name="1021"><span class="lineNum">    1021 </span>            :       (io_in_bits_folded_hist_3_hist_10_folded_hist),</a>
+<a name="1022"><span class="lineNum">    1022 </span>            :     .io_req_bits_folded_hist_hist_3_folded_hist</a>
+<a name="1023"><span class="lineNum">    1023 </span>            :       (io_in_bits_folded_hist_3_hist_3_folded_hist),</a>
+<a name="1024"><span class="lineNum">    1024 </span>            :     .io_resp_valid                               (_tables_4_io_resp_valid),</a>
+<a name="1025"><span class="lineNum">    1025 </span>            :     .io_resp_bits_ctr                            (_tables_4_io_resp_bits_ctr),</a>
+<a name="1026"><span class="lineNum">    1026 </span>            :     .io_resp_bits_u                              (_tables_4_io_resp_bits_u),</a>
+<a name="1027"><span class="lineNum">    1027 </span>            :     .io_resp_bits_target                         (_tables_4_io_resp_bits_target),</a>
+<a name="1028"><span class="lineNum">    1028 </span>            :     .io_update_pc                                (tables_4_io_update_pc_r),</a>
+<a name="1029"><span class="lineNum">    1029 </span>            :     .io_update_folded_hist_hist_10_folded_hist</a>
+<a name="1030"><span class="lineNum">    1030 </span>            :       (tables_4_io_update_folded_hist_r_hist_10_folded_hist),</a>
+<a name="1031"><span class="lineNum">    1031 </span>            :     .io_update_folded_hist_hist_3_folded_hist</a>
+<a name="1032"><span class="lineNum">    1032 </span>            :       (tables_4_io_update_folded_hist_r_hist_3_folded_hist),</a>
+<a name="1033"><span class="lineNum">    1033 </span>            :     .io_update_valid                             (tables_4_io_update_valid_REG),</a>
+<a name="1034"><span class="lineNum">    1034 </span>            :     .io_update_correct                           (tables_4_io_update_correct_r),</a>
+<a name="1035"><span class="lineNum">    1035 </span>            :     .io_update_alloc                             (tables_4_io_update_alloc_r),</a>
+<a name="1036"><span class="lineNum">    1036 </span>            :     .io_update_oldCtr                            (tables_4_io_update_oldCtr_r),</a>
+<a name="1037"><span class="lineNum">    1037 </span>            :     .io_update_uValid                            (tables_4_io_update_uValid_r),</a>
+<a name="1038"><span class="lineNum">    1038 </span>            :     .io_update_u                                 (tables_4_io_update_u_r),</a>
+<a name="1039"><span class="lineNum">    1039 </span>            :     .io_update_reset_u                           (tables_4_io_update_reset_u_REG),</a>
+<a name="1040"><span class="lineNum">    1040 </span>            :     .io_update_target                            (tables_4_io_update_target_r),</a>
+<a name="1041"><span class="lineNum">    1041 </span>            :     .io_update_old_target                        (tables_4_io_update_old_target_r)</a>
+<a name="1042"><span class="lineNum">    1042 </span>            :   );</a>
+<a name="1043"><span class="lineNum">    1043 </span>            :   assign io_out_s2_full_pred_0_br_taken_mask_0 =</a>
+<a name="1044"><span class="lineNum">    1044 </span>            :     io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_0;</a>
+<a name="1045"><span class="lineNum">    1045 </span>            :   assign io_out_s2_full_pred_0_br_taken_mask_1 =</a>
+<a name="1046"><span class="lineNum">    1046 </span>            :     io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_1;</a>
+<a name="1047"><span class="lineNum">    1047 </span>            :   assign io_out_s2_full_pred_0_slot_valids_0 =</a>
+<a name="1048"><span class="lineNum">    1048 </span>            :     io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_0;</a>
+<a name="1049"><span class="lineNum">    1049 </span>            :   assign io_out_s2_full_pred_0_slot_valids_1 =</a>
+<a name="1050"><span class="lineNum">    1050 </span>            :     io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_1;</a>
+<a name="1051"><span class="lineNum">    1051 </span>            :   assign io_out_s2_full_pred_0_targets_0 = io_in_bits_resp_in_0_s2_full_pred_0_targets_0;</a>
+<a name="1052"><span class="lineNum">    1052 </span>            :   assign io_out_s2_full_pred_0_targets_1 = io_in_bits_resp_in_0_s2_full_pred_0_targets_1;</a>
+<a name="1053"><span class="lineNum">    1053 </span>            :   assign io_out_s2_full_pred_0_jalr_target =</a>
+<a name="1054"><span class="lineNum">    1054 </span>            :     io_in_bits_resp_in_0_s2_full_pred_0_jalr_target;</a>
+<a name="1055"><span class="lineNum">    1055 </span>            :   assign io_out_s2_full_pred_0_offsets_0 = io_in_bits_resp_in_0_s2_full_pred_0_offsets_0;</a>
+<a name="1056"><span class="lineNum">    1056 </span>            :   assign io_out_s2_full_pred_0_offsets_1 = io_in_bits_resp_in_0_s2_full_pred_0_offsets_1;</a>
+<a name="1057"><span class="lineNum">    1057 </span>            :   assign io_out_s2_full_pred_0_fallThroughAddr =</a>
+<a name="1058"><span class="lineNum">    1058 </span>            :     io_in_bits_resp_in_0_s2_full_pred_0_fallThroughAddr;</a>
+<a name="1059"><span class="lineNum">    1059 </span>            :   assign io_out_s2_full_pred_0_is_br_sharing =</a>
+<a name="1060"><span class="lineNum">    1060 </span>            :     io_in_bits_resp_in_0_s2_full_pred_0_is_br_sharing;</a>
+<a name="1061"><span class="lineNum">    1061 </span>            :   assign io_out_s2_full_pred_0_hit = io_in_bits_resp_in_0_s2_full_pred_0_hit;</a>
+<a name="1062"><span class="lineNum">    1062 </span>            :   assign io_out_s2_full_pred_1_br_taken_mask_0 =</a>
+<a name="1063"><span class="lineNum">    1063 </span>            :     io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_0;</a>
+<a name="1064"><span class="lineNum">    1064 </span>            :   assign io_out_s2_full_pred_1_br_taken_mask_1 =</a>
+<a name="1065"><span class="lineNum">    1065 </span>            :     io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_1;</a>
+<a name="1066"><span class="lineNum">    1066 </span>            :   assign io_out_s2_full_pred_1_slot_valids_0 =</a>
+<a name="1067"><span class="lineNum">    1067 </span>            :     io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_0;</a>
+<a name="1068"><span class="lineNum">    1068 </span>            :   assign io_out_s2_full_pred_1_slot_valids_1 =</a>
+<a name="1069"><span class="lineNum">    1069 </span>            :     io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_1;</a>
+<a name="1070"><span class="lineNum">    1070 </span>            :   assign io_out_s2_full_pred_1_targets_0 = io_in_bits_resp_in_0_s2_full_pred_1_targets_0;</a>
+<a name="1071"><span class="lineNum">    1071 </span>            :   assign io_out_s2_full_pred_1_targets_1 = io_in_bits_resp_in_0_s2_full_pred_1_targets_1;</a>
+<a name="1072"><span class="lineNum">    1072 </span>            :   assign io_out_s2_full_pred_1_jalr_target =</a>
+<a name="1073"><span class="lineNum">    1073 </span>            :     io_in_bits_resp_in_0_s2_full_pred_1_jalr_target;</a>
+<a name="1074"><span class="lineNum">    1074 </span>            :   assign io_out_s2_full_pred_1_offsets_0 = io_in_bits_resp_in_0_s2_full_pred_1_offsets_0;</a>
+<a name="1075"><span class="lineNum">    1075 </span>            :   assign io_out_s2_full_pred_1_offsets_1 = io_in_bits_resp_in_0_s2_full_pred_1_offsets_1;</a>
+<a name="1076"><span class="lineNum">    1076 </span>            :   assign io_out_s2_full_pred_1_fallThroughAddr =</a>
+<a name="1077"><span class="lineNum">    1077 </span>            :     io_in_bits_resp_in_0_s2_full_pred_1_fallThroughAddr;</a>
+<a name="1078"><span class="lineNum">    1078 </span>            :   assign io_out_s2_full_pred_1_is_br_sharing =</a>
+<a name="1079"><span class="lineNum">    1079 </span>            :     io_in_bits_resp_in_0_s2_full_pred_1_is_br_sharing;</a>
+<a name="1080"><span class="lineNum">    1080 </span>            :   assign io_out_s2_full_pred_1_hit = io_in_bits_resp_in_0_s2_full_pred_1_hit;</a>
+<a name="1081"><span class="lineNum">    1081 </span>            :   assign io_out_s2_full_pred_2_br_taken_mask_0 =</a>
+<a name="1082"><span class="lineNum">    1082 </span>            :     io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_0;</a>
+<a name="1083"><span class="lineNum">    1083 </span>            :   assign io_out_s2_full_pred_2_br_taken_mask_1 =</a>
+<a name="1084"><span class="lineNum">    1084 </span>            :     io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_1;</a>
+<a name="1085"><span class="lineNum">    1085 </span>            :   assign io_out_s2_full_pred_2_slot_valids_0 =</a>
+<a name="1086"><span class="lineNum">    1086 </span>            :     io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_0;</a>
+<a name="1087"><span class="lineNum">    1087 </span>            :   assign io_out_s2_full_pred_2_slot_valids_1 =</a>
+<a name="1088"><span class="lineNum">    1088 </span>            :     io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_1;</a>
+<a name="1089"><span class="lineNum">    1089 </span>            :   assign io_out_s2_full_pred_2_targets_0 = io_in_bits_resp_in_0_s2_full_pred_2_targets_0;</a>
+<a name="1090"><span class="lineNum">    1090 </span>            :   assign io_out_s2_full_pred_2_targets_1 = io_in_bits_resp_in_0_s2_full_pred_2_targets_1;</a>
+<a name="1091"><span class="lineNum">    1091 </span>            :   assign io_out_s2_full_pred_2_jalr_target =</a>
+<a name="1092"><span class="lineNum">    1092 </span>            :     io_in_bits_resp_in_0_s2_full_pred_2_jalr_target;</a>
+<a name="1093"><span class="lineNum">    1093 </span>            :   assign io_out_s2_full_pred_2_offsets_0 = io_in_bits_resp_in_0_s2_full_pred_2_offsets_0;</a>
+<a name="1094"><span class="lineNum">    1094 </span>            :   assign io_out_s2_full_pred_2_offsets_1 = io_in_bits_resp_in_0_s2_full_pred_2_offsets_1;</a>
+<a name="1095"><span class="lineNum">    1095 </span>            :   assign io_out_s2_full_pred_2_fallThroughAddr =</a>
+<a name="1096"><span class="lineNum">    1096 </span>            :     io_in_bits_resp_in_0_s2_full_pred_2_fallThroughAddr;</a>
+<a name="1097"><span class="lineNum">    1097 </span>            :   assign io_out_s2_full_pred_2_is_jalr = io_in_bits_resp_in_0_s2_full_pred_2_is_jalr;</a>
+<a name="1098"><span class="lineNum">    1098 </span>            :   assign io_out_s2_full_pred_2_is_call = io_in_bits_resp_in_0_s2_full_pred_2_is_call;</a>
+<a name="1099"><span class="lineNum">    1099 </span>            :   assign io_out_s2_full_pred_2_is_ret = io_in_bits_resp_in_0_s2_full_pred_2_is_ret;</a>
+<a name="1100"><span class="lineNum">    1100 </span>            :   assign io_out_s2_full_pred_2_last_may_be_rvi_call =</a>
+<a name="1101"><span class="lineNum">    1101 </span>            :     io_in_bits_resp_in_0_s2_full_pred_2_last_may_be_rvi_call;</a>
+<a name="1102"><span class="lineNum">    1102 </span>            :   assign io_out_s2_full_pred_2_is_br_sharing =</a>
+<a name="1103"><span class="lineNum">    1103 </span>            :     io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing;</a>
+<a name="1104"><span class="lineNum">    1104 </span>            :   assign io_out_s2_full_pred_2_hit = io_in_bits_resp_in_0_s2_full_pred_2_hit;</a>
+<a name="1105"><span class="lineNum">    1105 </span>            :   assign io_out_s2_full_pred_3_br_taken_mask_0 =</a>
+<a name="1106"><span class="lineNum">    1106 </span>            :     io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_0;</a>
+<a name="1107"><span class="lineNum">    1107 </span>            :   assign io_out_s2_full_pred_3_br_taken_mask_1 =</a>
+<a name="1108"><span class="lineNum">    1108 </span>            :     io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_1;</a>
+<a name="1109"><span class="lineNum">    1109 </span>            :   assign io_out_s2_full_pred_3_slot_valids_0 =</a>
+<a name="1110"><span class="lineNum">    1110 </span>            :     io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_0;</a>
+<a name="1111"><span class="lineNum">    1111 </span>            :   assign io_out_s2_full_pred_3_slot_valids_1 =</a>
+<a name="1112"><span class="lineNum">    1112 </span>            :     io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_1;</a>
+<a name="1113"><span class="lineNum">    1113 </span>            :   assign io_out_s2_full_pred_3_targets_0 = io_in_bits_resp_in_0_s2_full_pred_3_targets_0;</a>
+<a name="1114"><span class="lineNum">    1114 </span>            :   assign io_out_s2_full_pred_3_targets_1 = io_in_bits_resp_in_0_s2_full_pred_3_targets_1;</a>
+<a name="1115"><span class="lineNum">    1115 </span>            :   assign io_out_s2_full_pred_3_jalr_target =</a>
+<a name="1116"><span class="lineNum">    1116 </span>            :     io_in_bits_resp_in_0_s2_full_pred_3_jalr_target;</a>
+<a name="1117"><span class="lineNum">    1117 </span>            :   assign io_out_s2_full_pred_3_offsets_0 = io_in_bits_resp_in_0_s2_full_pred_3_offsets_0;</a>
+<a name="1118"><span class="lineNum">    1118 </span>            :   assign io_out_s2_full_pred_3_offsets_1 = io_in_bits_resp_in_0_s2_full_pred_3_offsets_1;</a>
+<a name="1119"><span class="lineNum">    1119 </span>            :   assign io_out_s2_full_pred_3_fallThroughAddr =</a>
+<a name="1120"><span class="lineNum">    1120 </span>            :     io_in_bits_resp_in_0_s2_full_pred_3_fallThroughAddr;</a>
+<a name="1121"><span class="lineNum">    1121 </span>            :   assign io_out_s2_full_pred_3_fallThroughErr =</a>
+<a name="1122"><span class="lineNum">    1122 </span>            :     io_in_bits_resp_in_0_s2_full_pred_3_fallThroughErr;</a>
+<a name="1123"><span class="lineNum">    1123 </span>            :   assign io_out_s2_full_pred_3_is_br_sharing =</a>
+<a name="1124"><span class="lineNum">    1124 </span>            :     io_in_bits_resp_in_0_s2_full_pred_3_is_br_sharing;</a>
+<a name="1125"><span class="lineNum">    1125 </span>            :   assign io_out_s2_full_pred_3_hit = io_in_bits_resp_in_0_s2_full_pred_3_hit;</a>
+<a name="1126"><span class="lineNum">    1126 </span>            :   assign io_out_s3_full_pred_0_br_taken_mask_0 =</a>
+<a name="1127"><span class="lineNum">    1127 </span>            :     io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_0;</a>
+<a name="1128"><span class="lineNum">    1128 </span>            :   assign io_out_s3_full_pred_0_br_taken_mask_1 =</a>
+<a name="1129"><span class="lineNum">    1129 </span>            :     io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_1;</a>
+<a name="1130"><span class="lineNum">    1130 </span>            :   assign io_out_s3_full_pred_0_slot_valids_0 =</a>
+<a name="1131"><span class="lineNum">    1131 </span>            :     io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_0;</a>
+<a name="1132"><span class="lineNum">    1132 </span>            :   assign io_out_s3_full_pred_0_slot_valids_1 =</a>
+<a name="1133"><span class="lineNum">    1133 </span>            :     io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_1;</a>
+<a name="1134"><span class="lineNum">    1134 </span>            :   assign io_out_s3_full_pred_0_targets_0 = io_in_bits_resp_in_0_s3_full_pred_0_targets_0;</a>
+<a name="1135"><span class="lineNum">    1135 </span>            :   assign io_out_s3_full_pred_0_targets_1 = io_in_bits_resp_in_0_s3_full_pred_0_targets_1;</a>
+<a name="1136"><span class="lineNum">    1136 </span>            :   assign io_out_s3_full_pred_0_jalr_target =</a>
+<a name="1137"><span class="lineNum">    1137 </span>            :     s3_tageTaken_dup_0</a>
+<a name="1138"><span class="lineNum">    1138 </span>            :       ? s3_tageTarget_dup_0</a>
+<a name="1139"><span class="lineNum">    1139 </span>            :       : io_in_bits_resp_in_0_s3_full_pred_0_jalr_target;</a>
+<a name="1140"><span class="lineNum">    1140 </span>            :   assign io_out_s3_full_pred_0_fallThroughAddr =</a>
+<a name="1141"><span class="lineNum">    1141 </span>            :     io_in_bits_resp_in_0_s3_full_pred_0_fallThroughAddr;</a>
+<a name="1142"><span class="lineNum">    1142 </span>            :   assign io_out_s3_full_pred_0_fallThroughErr =</a>
+<a name="1143"><span class="lineNum">    1143 </span>            :     io_in_bits_resp_in_0_s3_full_pred_0_fallThroughErr;</a>
+<a name="1144"><span class="lineNum">    1144 </span>            :   assign io_out_s3_full_pred_0_is_br_sharing =</a>
+<a name="1145"><span class="lineNum">    1145 </span>            :     io_in_bits_resp_in_0_s3_full_pred_0_is_br_sharing;</a>
+<a name="1146"><span class="lineNum">    1146 </span>            :   assign io_out_s3_full_pred_0_hit = io_in_bits_resp_in_0_s3_full_pred_0_hit;</a>
+<a name="1147"><span class="lineNum">    1147 </span>            :   assign io_out_s3_full_pred_1_br_taken_mask_0 =</a>
+<a name="1148"><span class="lineNum">    1148 </span>            :     io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_0;</a>
+<a name="1149"><span class="lineNum">    1149 </span>            :   assign io_out_s3_full_pred_1_br_taken_mask_1 =</a>
+<a name="1150"><span class="lineNum">    1150 </span>            :     io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_1;</a>
+<a name="1151"><span class="lineNum">    1151 </span>            :   assign io_out_s3_full_pred_1_slot_valids_0 =</a>
+<a name="1152"><span class="lineNum">    1152 </span>            :     io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_0;</a>
+<a name="1153"><span class="lineNum">    1153 </span>            :   assign io_out_s3_full_pred_1_slot_valids_1 =</a>
+<a name="1154"><span class="lineNum">    1154 </span>            :     io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_1;</a>
+<a name="1155"><span class="lineNum">    1155 </span>            :   assign io_out_s3_full_pred_1_targets_0 = io_in_bits_resp_in_0_s3_full_pred_1_targets_0;</a>
+<a name="1156"><span class="lineNum">    1156 </span>            :   assign io_out_s3_full_pred_1_targets_1 = io_in_bits_resp_in_0_s3_full_pred_1_targets_1;</a>
+<a name="1157"><span class="lineNum">    1157 </span>            :   assign io_out_s3_full_pred_1_jalr_target =</a>
+<a name="1158"><span class="lineNum">    1158 </span>            :     s3_tageTaken_dup_1</a>
+<a name="1159"><span class="lineNum">    1159 </span>            :       ? s3_tageTarget_dup_1</a>
+<a name="1160"><span class="lineNum">    1160 </span>            :       : io_in_bits_resp_in_0_s3_full_pred_1_jalr_target;</a>
+<a name="1161"><span class="lineNum">    1161 </span>            :   assign io_out_s3_full_pred_1_fallThroughAddr =</a>
+<a name="1162"><span class="lineNum">    1162 </span>            :     io_in_bits_resp_in_0_s3_full_pred_1_fallThroughAddr;</a>
+<a name="1163"><span class="lineNum">    1163 </span>            :   assign io_out_s3_full_pred_1_fallThroughErr =</a>
+<a name="1164"><span class="lineNum">    1164 </span>            :     io_in_bits_resp_in_0_s3_full_pred_1_fallThroughErr;</a>
+<a name="1165"><span class="lineNum">    1165 </span>            :   assign io_out_s3_full_pred_1_is_br_sharing =</a>
+<a name="1166"><span class="lineNum">    1166 </span>            :     io_in_bits_resp_in_0_s3_full_pred_1_is_br_sharing;</a>
+<a name="1167"><span class="lineNum">    1167 </span>            :   assign io_out_s3_full_pred_1_hit = io_in_bits_resp_in_0_s3_full_pred_1_hit;</a>
+<a name="1168"><span class="lineNum">    1168 </span>            :   assign io_out_s3_full_pred_2_br_taken_mask_0 =</a>
+<a name="1169"><span class="lineNum">    1169 </span>            :     io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_0;</a>
+<a name="1170"><span class="lineNum">    1170 </span>            :   assign io_out_s3_full_pred_2_br_taken_mask_1 =</a>
+<a name="1171"><span class="lineNum">    1171 </span>            :     io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_1;</a>
+<a name="1172"><span class="lineNum">    1172 </span>            :   assign io_out_s3_full_pred_2_slot_valids_0 =</a>
+<a name="1173"><span class="lineNum">    1173 </span>            :     io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_0;</a>
+<a name="1174"><span class="lineNum">    1174 </span>            :   assign io_out_s3_full_pred_2_slot_valids_1 =</a>
+<a name="1175"><span class="lineNum">    1175 </span>            :     io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_1;</a>
+<a name="1176"><span class="lineNum">    1176 </span>            :   assign io_out_s3_full_pred_2_targets_0 = io_in_bits_resp_in_0_s3_full_pred_2_targets_0;</a>
+<a name="1177"><span class="lineNum">    1177 </span>            :   assign io_out_s3_full_pred_2_targets_1 = io_in_bits_resp_in_0_s3_full_pred_2_targets_1;</a>
+<a name="1178"><span class="lineNum">    1178 </span>            :   assign io_out_s3_full_pred_2_jalr_target =</a>
+<a name="1179"><span class="lineNum">    1179 </span>            :     s3_tageTaken_dup_2</a>
+<a name="1180"><span class="lineNum">    1180 </span>            :       ? s3_tageTarget_dup_2</a>
+<a name="1181"><span class="lineNum">    1181 </span>            :       : io_in_bits_resp_in_0_s3_full_pred_2_jalr_target;</a>
+<a name="1182"><span class="lineNum">    1182 </span>            :   assign io_out_s3_full_pred_2_fallThroughAddr =</a>
+<a name="1183"><span class="lineNum">    1183 </span>            :     io_in_bits_resp_in_0_s3_full_pred_2_fallThroughAddr;</a>
+<a name="1184"><span class="lineNum">    1184 </span>            :   assign io_out_s3_full_pred_2_fallThroughErr =</a>
+<a name="1185"><span class="lineNum">    1185 </span>            :     io_in_bits_resp_in_0_s3_full_pred_2_fallThroughErr;</a>
+<a name="1186"><span class="lineNum">    1186 </span>            :   assign io_out_s3_full_pred_2_is_jalr = io_in_bits_resp_in_0_s3_full_pred_2_is_jalr;</a>
+<a name="1187"><span class="lineNum">    1187 </span>            :   assign io_out_s3_full_pred_2_is_call = io_in_bits_resp_in_0_s3_full_pred_2_is_call;</a>
+<a name="1188"><span class="lineNum">    1188 </span>            :   assign io_out_s3_full_pred_2_is_ret = io_in_bits_resp_in_0_s3_full_pred_2_is_ret;</a>
+<a name="1189"><span class="lineNum">    1189 </span>            :   assign io_out_s3_full_pred_2_is_br_sharing =</a>
+<a name="1190"><span class="lineNum">    1190 </span>            :     io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing;</a>
+<a name="1191"><span class="lineNum">    1191 </span>            :   assign io_out_s3_full_pred_2_hit = io_in_bits_resp_in_0_s3_full_pred_2_hit;</a>
+<a name="1192"><span class="lineNum">    1192 </span>            :   assign io_out_s3_full_pred_3_br_taken_mask_0 =</a>
+<a name="1193"><span class="lineNum">    1193 </span>            :     io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_0;</a>
+<a name="1194"><span class="lineNum">    1194 </span>            :   assign io_out_s3_full_pred_3_br_taken_mask_1 =</a>
+<a name="1195"><span class="lineNum">    1195 </span>            :     io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_1;</a>
+<a name="1196"><span class="lineNum">    1196 </span>            :   assign io_out_s3_full_pred_3_slot_valids_0 =</a>
+<a name="1197"><span class="lineNum">    1197 </span>            :     io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_0;</a>
+<a name="1198"><span class="lineNum">    1198 </span>            :   assign io_out_s3_full_pred_3_slot_valids_1 =</a>
+<a name="1199"><span class="lineNum">    1199 </span>            :     io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_1;</a>
+<a name="1200"><span class="lineNum">    1200 </span>            :   assign io_out_s3_full_pred_3_targets_0 = io_in_bits_resp_in_0_s3_full_pred_3_targets_0;</a>
+<a name="1201"><span class="lineNum">    1201 </span>            :   assign io_out_s3_full_pred_3_targets_1 = io_in_bits_resp_in_0_s3_full_pred_3_targets_1;</a>
+<a name="1202"><span class="lineNum">    1202 </span>            :   assign io_out_s3_full_pred_3_jalr_target =</a>
+<a name="1203"><span class="lineNum">    1203 </span>            :     s3_tageTaken_dup_3</a>
+<a name="1204"><span class="lineNum">    1204 </span>            :       ? s3_tageTarget_dup_3</a>
+<a name="1205"><span class="lineNum">    1205 </span>            :       : io_in_bits_resp_in_0_s3_full_pred_3_jalr_target;</a>
+<a name="1206"><span class="lineNum">    1206 </span>            :   assign io_out_s3_full_pred_3_offsets_0 = io_in_bits_resp_in_0_s3_full_pred_3_offsets_0;</a>
+<a name="1207"><span class="lineNum">    1207 </span>            :   assign io_out_s3_full_pred_3_offsets_1 = io_in_bits_resp_in_0_s3_full_pred_3_offsets_1;</a>
+<a name="1208"><span class="lineNum">    1208 </span>            :   assign io_out_s3_full_pred_3_fallThroughAddr =</a>
+<a name="1209"><span class="lineNum">    1209 </span>            :     io_in_bits_resp_in_0_s3_full_pred_3_fallThroughAddr;</a>
+<a name="1210"><span class="lineNum">    1210 </span>            :   assign io_out_s3_full_pred_3_fallThroughErr =</a>
+<a name="1211"><span class="lineNum">    1211 </span>            :     io_in_bits_resp_in_0_s3_full_pred_3_fallThroughErr;</a>
+<a name="1212"><span class="lineNum">    1212 </span>            :   assign io_out_s3_full_pred_3_is_br_sharing =</a>
+<a name="1213"><span class="lineNum">    1213 </span>            :     io_in_bits_resp_in_0_s3_full_pred_3_is_br_sharing;</a>
+<a name="1214"><span class="lineNum">    1214 </span>            :   assign io_out_s3_full_pred_3_hit = io_in_bits_resp_in_0_s3_full_pred_3_hit;</a>
+<a name="1215"><span class="lineNum">    1215 </span>            :   assign io_out_last_stage_meta =</a>
+<a name="1216"><span class="lineNum">    1216 </span>            :     {122'h0,</a>
+<a name="1217"><span class="lineNum">    1217 </span>            :      s3_provided,</a>
+<a name="1218"><span class="lineNum">    1218 </span>            :      s3_provider,</a>
+<a name="1219"><span class="lineNum">    1219 </span>            :      s3_altProvided,</a>
+<a name="1220"><span class="lineNum">    1220 </span>            :      s3_altProvider,</a>
+<a name="1221"><span class="lineNum">    1221 </span>            :      resp_meta_altDiffers,</a>
+<a name="1222"><span class="lineNum">    1222 </span>            :      s3_providerU,</a>
+<a name="1223"><span class="lineNum">    1223 </span>            :      s3_providerCtr,</a>
+<a name="1224"><span class="lineNum">    1224 </span>            :      s3_altProviderCtr,</a>
+<a name="1225"><span class="lineNum">    1225 </span>            :      resp_meta_allocate_valid_r,</a>
+<a name="1226"><span class="lineNum">    1226 </span>            :      resp_meta_allocate_bits_r,</a>
+<a name="1227"><span class="lineNum">    1227 </span>            :      s3_tageTaken_dup_3,</a>
+<a name="1228"><span class="lineNum">    1228 </span>            :      s3_providerTarget,</a>
+<a name="1229"><span class="lineNum">    1229 </span>            :      s3_altProviderTarget};</a>
+<a name="1230"><span class="lineNum">    1230 </span>            :   assign io_out_last_stage_ftb_entry_valid =</a>
+<a name="1231"><span class="lineNum">    1231 </span>            :     io_in_bits_resp_in_0_last_stage_ftb_entry_valid;</a>
+<a name="1232"><span class="lineNum">    1232 </span>            :   assign io_out_last_stage_ftb_entry_brSlots_0_offset =</a>
+<a name="1233"><span class="lineNum">    1233 </span>            :     io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_offset;</a>
+<a name="1234"><span class="lineNum">    1234 </span>            :   assign io_out_last_stage_ftb_entry_brSlots_0_lower =</a>
+<a name="1235"><span class="lineNum">    1235 </span>            :     io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_lower;</a>
+<a name="1236"><span class="lineNum">    1236 </span>            :   assign io_out_last_stage_ftb_entry_brSlots_0_tarStat =</a>
+<a name="1237"><span class="lineNum">    1237 </span>            :     io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_tarStat;</a>
+<a name="1238"><span class="lineNum">    1238 </span>            :   assign io_out_last_stage_ftb_entry_brSlots_0_sharing =</a>
+<a name="1239"><span class="lineNum">    1239 </span>            :     io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_sharing;</a>
+<a name="1240"><span class="lineNum">    1240 </span>            :   assign io_out_last_stage_ftb_entry_brSlots_0_valid =</a>
+<a name="1241"><span class="lineNum">    1241 </span>            :     io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_valid;</a>
+<a name="1242"><span class="lineNum">    1242 </span>            :   assign io_out_last_stage_ftb_entry_tailSlot_offset =</a>
+<a name="1243"><span class="lineNum">    1243 </span>            :     io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_offset;</a>
+<a name="1244"><span class="lineNum">    1244 </span>            :   assign io_out_last_stage_ftb_entry_tailSlot_lower =</a>
+<a name="1245"><span class="lineNum">    1245 </span>            :     io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_lower;</a>
+<a name="1246"><span class="lineNum">    1246 </span>            :   assign io_out_last_stage_ftb_entry_tailSlot_tarStat =</a>
+<a name="1247"><span class="lineNum">    1247 </span>            :     io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_tarStat;</a>
+<a name="1248"><span class="lineNum">    1248 </span>            :   assign io_out_last_stage_ftb_entry_tailSlot_sharing =</a>
+<a name="1249"><span class="lineNum">    1249 </span>            :     io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_sharing;</a>
+<a name="1250"><span class="lineNum">    1250 </span>            :   assign io_out_last_stage_ftb_entry_tailSlot_valid =</a>
+<a name="1251"><span class="lineNum">    1251 </span>            :     io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_valid;</a>
+<a name="1252"><span class="lineNum">    1252 </span>            :   assign io_out_last_stage_ftb_entry_pftAddr =</a>
+<a name="1253"><span class="lineNum">    1253 </span>            :     io_in_bits_resp_in_0_last_stage_ftb_entry_pftAddr;</a>
+<a name="1254"><span class="lineNum">    1254 </span>            :   assign io_out_last_stage_ftb_entry_carry =</a>
+<a name="1255"><span class="lineNum">    1255 </span>            :     io_in_bits_resp_in_0_last_stage_ftb_entry_carry;</a>
+<a name="1256"><span class="lineNum">    1256 </span>            :   assign io_out_last_stage_ftb_entry_isCall =</a>
+<a name="1257"><span class="lineNum">    1257 </span>            :     io_in_bits_resp_in_0_last_stage_ftb_entry_isCall;</a>
+<a name="1258"><span class="lineNum">    1258 </span>            :   assign io_out_last_stage_ftb_entry_isRet =</a>
+<a name="1259"><span class="lineNum">    1259 </span>            :     io_in_bits_resp_in_0_last_stage_ftb_entry_isRet;</a>
+<a name="1260"><span class="lineNum">    1260 </span>            :   assign io_out_last_stage_ftb_entry_isJalr =</a>
+<a name="1261"><span class="lineNum">    1261 </span>            :     io_in_bits_resp_in_0_last_stage_ftb_entry_isJalr;</a>
+<a name="1262"><span class="lineNum">    1262 </span>            :   assign io_out_last_stage_ftb_entry_last_may_be_rvi_call =</a>
+<a name="1263"><span class="lineNum">    1263 </span>            :     io_in_bits_resp_in_0_last_stage_ftb_entry_last_may_be_rvi_call;</a>
+<a name="1264"><span class="lineNum">    1264 </span>            :   assign io_out_last_stage_ftb_entry_always_taken_0 =</a>
+<a name="1265"><span class="lineNum">    1265 </span>            :     io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_0;</a>
+<a name="1266"><span class="lineNum">    1266 </span>            :   assign io_out_last_stage_ftb_entry_always_taken_1 =</a>
+<a name="1267"><span class="lineNum">    1267 </span>            :     io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_1;</a>
+<a name="1268"><span class="lineNum">    1268 </span>            : endmodule</a>
+<a name="1269"><span class="lineNum">    1269 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/ITTageTable.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/ITTageTable.sv.func-sort-c.html
new file mode 100644
index 0000000..7c8bf11
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/ITTageTable.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/ITTageTable.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - ITTageTable.sv<span style="font-size: 80%;"> (<a href="ITTageTable.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">44</td>
+            <td class="headerCovTableEntry">44</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="ITTageTable.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/ITTageTable.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/ITTageTable.sv.func.html
new file mode 100644
index 0000000..8bd627e
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/ITTageTable.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/ITTageTable.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - ITTageTable.sv<span style="font-size: 80%;"> (<a href="ITTageTable.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">44</td>
+            <td class="headerCovTableEntry">44</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="ITTageTable.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/ITTageTable.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/ITTageTable.sv.gcov.html
new file mode 100644
index 0000000..99de3b7
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/ITTageTable.sv.gcov.html
@@ -0,0 +1,302 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/ITTageTable.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - ITTageTable.sv<span style="font-size: 80%;"> (source / <a href="ITTageTable.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">44</td>
+            <td class="headerCovTableEntry">44</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : module ITTageTable(</a>
+<a name="59"><span class="lineNum">      59 </span><span class="lineCov">     127786 :   input         clock,</span></a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">         62 :   input         reset,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">         73 :   input         io_req_valid,</span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">      35066 :   input  [40:0] io_req_bits_pc,</span></a>
+<a name="63"><span class="lineNum">      63 </span><span class="lineCov">        474 :   input  [3:0]  io_req_bits_folded_hist_hist_12_folded_hist,</span></a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">         13 :   output        io_resp_valid,</span></a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">         48 :   output [1:0]  io_resp_bits_ctr,</span></a>
+<a name="66"><span class="lineNum">      66 </span><span class="lineCov">        176 :   output [1:0]  io_resp_bits_u,</span></a>
+<a name="67"><span class="lineNum">      67 </span><span class="lineCov">       1096 :   output [40:0] io_resp_bits_target,</span></a>
+<a name="68"><span class="lineNum">      68 </span><span class="lineCov">        594 :   input  [40:0] io_update_pc,</span></a>
+<a name="69"><span class="lineNum">      69 </span><span class="lineCov">         54 :   input  [3:0]  io_update_folded_hist_hist_12_folded_hist,</span></a>
+<a name="70"><span class="lineNum">      70 </span><span class="lineCov">         25 :   input         io_update_valid,</span></a>
+<a name="71"><span class="lineNum">      71 </span><span class="lineCov">         15 :   input         io_update_correct,</span></a>
+<a name="72"><span class="lineNum">      72 </span><span class="lineCov">         13 :   input         io_update_alloc,</span></a>
+<a name="73"><span class="lineNum">      73 </span><span class="lineCov">         27 :   input  [1:0]  io_update_oldCtr,</span></a>
+<a name="74"><span class="lineNum">      74 </span><span class="lineCov">         12 :   input         io_update_uValid,</span></a>
+<a name="75"><span class="lineNum">      75 </span><span class="lineCov">         16 :   input         io_update_u,</span></a>
+<a name="76"><span class="lineNum">      76 </span><span class="lineCov">         28 :   input         io_update_reset_u,</span></a>
+<a name="77"><span class="lineNum">      77 </span><span class="lineCov">        585 :   input  [40:0] io_update_target,</span></a>
+<a name="78"><span class="lineNum">      78 </span><span class="lineCov">        611 :   input  [40:0] io_update_old_target</span></a>
+<a name="79"><span class="lineNum">      79 </span>            : );</a>
+<a name="80"><span class="lineNum">      80 </span>            : </a>
+<a name="81"><span class="lineNum">      81 </span>            :   wire        _resp_invalid_by_write_T_2;</a>
+<a name="82"><span class="lineNum">      82 </span>            :   wire        _wrbypass_io_hit;</a>
+<a name="83"><span class="lineNum">      83 </span>            :   wire [1:0]  _wrbypass_io_hit_data_0_bits;</a>
+<a name="84"><span class="lineNum">      84 </span>            :   wire        _table_banks_1_io_r_resp_data_0_valid;</a>
+<a name="85"><span class="lineNum">      85 </span>            :   wire [8:0]  _table_banks_1_io_r_resp_data_0_tag;</a>
+<a name="86"><span class="lineNum">      86 </span>            :   wire [1:0]  _table_banks_1_io_r_resp_data_0_ctr;</a>
+<a name="87"><span class="lineNum">      87 </span>            :   wire [40:0] _table_banks_1_io_r_resp_data_0_target;</a>
+<a name="88"><span class="lineNum">      88 </span>            :   wire        _table_banks_0_io_r_resp_data_0_valid;</a>
+<a name="89"><span class="lineNum">      89 </span>            :   wire [8:0]  _table_banks_0_io_r_resp_data_0_tag;</a>
+<a name="90"><span class="lineNum">      90 </span>            :   wire [1:0]  _table_banks_0_io_r_resp_data_0_ctr;</a>
+<a name="91"><span class="lineNum">      91 </span>            :   wire [40:0] _table_banks_0_io_r_resp_data_0_target;</a>
+<a name="92"><span class="lineNum">      92 </span>            :   wire        _us_io_rdata_0;</a>
+<a name="93"><span class="lineNum">      93 </span>            :   wire [3:0]  _GEN = io_req_bits_pc[4:1] ^ io_req_bits_folded_hist_hist_12_folded_hist;</a>
+<a name="94"><span class="lineNum">      94 </span><span class="lineCov">        714 :   reg  [8:0]  s1_tag;</span></a>
+<a name="95"><span class="lineNum">      95 </span><span class="lineCov">         53 :   reg         s1_bank_req_1h_0;</span></a>
+<a name="96"><span class="lineNum">      96 </span><span class="lineCov">         46 :   reg         s1_bank_req_1h_1;</span></a>
+<a name="97"><span class="lineNum">      97 </span>            :   wire [6:0]  _table_banks_1_io_r_req_bits_setIdx_T = {io_req_bits_pc[8:5], _GEN[3:1]};</a>
+<a name="98"><span class="lineNum">      98 </span><span class="lineCov">         34 :   reg         s1_bank_has_write_on_this_req_0;</span></a>
+<a name="99"><span class="lineNum">      99 </span><span class="lineCov">         35 :   reg         s1_bank_has_write_on_this_req_1;</span></a>
+<a name="100"><span class="lineNum">     100 </span>            :   wire [3:0]  _GEN_0 = io_update_pc[4:1] ^ io_update_folded_hist_hist_12_folded_hist;</a>
+<a name="101"><span class="lineNum">     101 </span><span class="lineCov">        105 :   wire [7:0]  update_idx = {io_update_pc[8:5], _GEN_0};</span></a>
+<a name="102"><span class="lineNum">     102 </span><span class="lineCov">        131 :   wire [8:0]  update_tag =</span></a>
+<a name="103"><span class="lineNum">     103 </span>            :     {io_update_pc[17:14],</a>
+<a name="104"><span class="lineNum">     104 </span>            :      {io_update_pc[13], io_update_pc[12:9] ^ io_update_folded_hist_hist_12_folded_hist}</a>
+<a name="105"><span class="lineNum">     105 </span>            :        ^ {io_update_folded_hist_hist_12_folded_hist, 1'h0}};</a>
+<a name="106"><span class="lineNum">     106 </span><span class="lineCov">         99 :   wire [6:0]  update_idx_in_bank = {io_update_pc[8:5], _GEN_0[3:1]};</span></a>
+<a name="107"><span class="lineNum">     107 </span>            :   assign _resp_invalid_by_write_T_2 =</a>
+<a name="108"><span class="lineNum">     108 </span>            :     s1_bank_req_1h_0 &amp; s1_bank_has_write_on_this_req_0 | s1_bank_req_1h_1</a>
+<a name="109"><span class="lineNum">     109 </span>            :     &amp; s1_bank_has_write_on_this_req_1;</a>
+<a name="110"><span class="lineNum">     110 </span>            :   wire        _s1_bank_has_write_on_this_req_WIRE_0 = io_update_valid &amp; ~(_GEN_0[0]);</a>
+<a name="111"><span class="lineNum">     111 </span>            :   wire        _s1_bank_has_write_on_this_req_WIRE_1 = io_update_valid &amp; _GEN_0[0];</a>
+<a name="112"><span class="lineNum">     112 </span><span class="lineCov">         44 :   wire [1:0]  old_ctr =</span></a>
+<a name="113"><span class="lineNum">     113 </span>            :     _wrbypass_io_hit ? _wrbypass_io_hit_data_0_bits : io_update_oldCtr;</a>
+<a name="114"><span class="lineNum">     114 </span><span class="lineCov">         16 :   wire        update_wdata_ctr_oldSatNotTaken = old_ctr == 2'h0;</span></a>
+<a name="115"><span class="lineNum">     115 </span><span class="lineCov">         51 :   wire [1:0]  update_wdata_ctr =</span></a>
+<a name="116"><span class="lineNum">     116 </span>            :     io_update_alloc</a>
+<a name="117"><span class="lineNum">     117 </span>            :       ? 2'h2</a>
+<a name="118"><span class="lineNum">     118 </span>            :       : (&amp;old_ctr) &amp; io_update_correct</a>
+<a name="119"><span class="lineNum">     119 </span>            :           ? 2'h3</a>
+<a name="120"><span class="lineNum">     120 </span>            :           : update_wdata_ctr_oldSatNotTaken &amp; ~io_update_correct</a>
+<a name="121"><span class="lineNum">     121 </span>            :               ? 2'h0</a>
+<a name="122"><span class="lineNum">     122 </span>            :               : io_update_correct ? 2'(old_ctr + 2'h1) : 2'(old_ctr - 2'h1);</a>
+<a name="123"><span class="lineNum">     123 </span><span class="lineCov">        599 :   wire [40:0] update_wdata_target =</span></a>
+<a name="124"><span class="lineNum">     124 </span>            :     io_update_alloc | update_wdata_ctr_oldSatNotTaken</a>
+<a name="125"><span class="lineNum">     125 </span>            :       ? io_update_target</a>
+<a name="126"><span class="lineNum">     126 </span>            :       : io_update_old_target;</a>
+<a name="127"><span class="lineNum">     127 </span><span class="lineCov">     127694 :   always @(posedge clock) begin</span></a>
+<a name="128"><span class="lineNum">     128 </span><span class="lineCov">       8350 :     if (io_req_valid) begin</span></a>
+<a name="129"><span class="lineNum">     129 </span><span class="lineCov">       4175 :       s1_tag &lt;=</span></a>
+<a name="130"><span class="lineNum">     130 </span><span class="lineCov">       4175 :         {io_req_bits_pc[17:14],</span></a>
+<a name="131"><span class="lineNum">     131 </span><span class="lineCov">       4175 :          {io_req_bits_pc[13],</span></a>
+<a name="132"><span class="lineNum">     132 </span><span class="lineCov">       4175 :           io_req_bits_pc[12:9] ^ io_req_bits_folded_hist_hist_12_folded_hist}</span></a>
+<a name="133"><span class="lineNum">     133 </span><span class="lineCov">       4175 :            ^ {io_req_bits_folded_hist_hist_12_folded_hist, 1'h0}};</span></a>
+<a name="134"><span class="lineNum">     134 </span><span class="lineCov">       4175 :       s1_bank_req_1h_0 &lt;= ~(_GEN[0]);</span></a>
+<a name="135"><span class="lineNum">     135 </span><span class="lineCov">       4175 :       s1_bank_req_1h_1 &lt;= _GEN[0];</span></a>
+<a name="136"><span class="lineNum">     136 </span><span class="lineCov">       4175 :       s1_bank_has_write_on_this_req_0 &lt;= _s1_bank_has_write_on_this_req_WIRE_0;</span></a>
+<a name="137"><span class="lineNum">     137 </span><span class="lineCov">       4175 :       s1_bank_has_write_on_this_req_1 &lt;= _s1_bank_has_write_on_this_req_WIRE_1;</span></a>
+<a name="138"><span class="lineNum">     138 </span>            :     end</a>
+<a name="139"><span class="lineNum">     139 </span>            :   end // always @(posedge)</a>
+<a name="140"><span class="lineNum">     140 </span>            :   `ifdef ENABLE_INITIAL_REG_</a>
+<a name="141"><span class="lineNum">     141 </span>            :     `ifdef FIRRTL_BEFORE_INITIAL</a>
+<a name="142"><span class="lineNum">     142 </span>            :       `FIRRTL_BEFORE_INITIAL</a>
+<a name="143"><span class="lineNum">     143 </span>            :     `endif // FIRRTL_BEFORE_INITIAL</a>
+<a name="144"><span class="lineNum">     144 </span>            :     logic [31:0] _RANDOM[0:0];</a>
+<a name="145"><span class="lineNum">     145 </span><span class="lineCov">         58 :     initial begin</span></a>
+<a name="146"><span class="lineNum">     146 </span>            :       `ifdef INIT_RANDOM_PROLOG_</a>
+<a name="147"><span class="lineNum">     147 </span>            :         `INIT_RANDOM_PROLOG_</a>
+<a name="148"><span class="lineNum">     148 </span>            :       `endif // INIT_RANDOM_PROLOG_</a>
+<a name="149"><span class="lineNum">     149 </span>            :       `ifdef RANDOMIZE_REG_INIT</a>
+<a name="150"><span class="lineNum">     150 </span>            :         _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;</a>
+<a name="151"><span class="lineNum">     151 </span>            :         s1_tag = _RANDOM[/*Zero width*/ 1'b0][16:8];</a>
+<a name="152"><span class="lineNum">     152 </span>            :         s1_bank_req_1h_0 = _RANDOM[/*Zero width*/ 1'b0][17];</a>
+<a name="153"><span class="lineNum">     153 </span>            :         s1_bank_req_1h_1 = _RANDOM[/*Zero width*/ 1'b0][18];</a>
+<a name="154"><span class="lineNum">     154 </span>            :         s1_bank_has_write_on_this_req_0 = _RANDOM[/*Zero width*/ 1'b0][19];</a>
+<a name="155"><span class="lineNum">     155 </span>            :         s1_bank_has_write_on_this_req_1 = _RANDOM[/*Zero width*/ 1'b0][20];</a>
+<a name="156"><span class="lineNum">     156 </span>            :       `endif // RANDOMIZE_REG_INIT</a>
+<a name="157"><span class="lineNum">     157 </span>            :     end // initial</a>
+<a name="158"><span class="lineNum">     158 </span>            :     `ifdef FIRRTL_AFTER_INITIAL</a>
+<a name="159"><span class="lineNum">     159 </span>            :       `FIRRTL_AFTER_INITIAL</a>
+<a name="160"><span class="lineNum">     160 </span>            :     `endif // FIRRTL_AFTER_INITIAL</a>
+<a name="161"><span class="lineNum">     161 </span>            :   `endif // ENABLE_INITIAL_REG_</a>
+<a name="162"><span class="lineNum">     162 </span>            :   Folded1WDataModuleTemplate us (</a>
+<a name="163"><span class="lineNum">     163 </span>            :     .clock      (clock),</a>
+<a name="164"><span class="lineNum">     164 </span>            :     .reset      (reset),</a>
+<a name="165"><span class="lineNum">     165 </span>            :     .io_ren_0   (io_req_valid),</a>
+<a name="166"><span class="lineNum">     166 </span>            :     .io_raddr_0 ({io_req_bits_pc[8:5], _GEN}),</a>
+<a name="167"><span class="lineNum">     167 </span>            :     .io_rdata_0 (_us_io_rdata_0),</a>
+<a name="168"><span class="lineNum">     168 </span>            :     .io_wen     (io_update_uValid),</a>
+<a name="169"><span class="lineNum">     169 </span>            :     .io_waddr   (update_idx),</a>
+<a name="170"><span class="lineNum">     170 </span>            :     .io_wdata   (io_update_u),</a>
+<a name="171"><span class="lineNum">     171 </span>            :     .io_resetEn (io_update_reset_u)</a>
+<a name="172"><span class="lineNum">     172 </span>            :   );</a>
+<a name="173"><span class="lineNum">     173 </span>            :   FoldedSRAMTemplate_21 table_banks_0 (</a>
+<a name="174"><span class="lineNum">     174 </span>            :     .clock                       (clock),</a>
+<a name="175"><span class="lineNum">     175 </span>            :     .reset                       (reset),</a>
+<a name="176"><span class="lineNum">     176 </span>            :     .io_r_req_valid              (io_req_valid &amp; ~(_GEN[0])),</a>
+<a name="177"><span class="lineNum">     177 </span>            :     .io_r_req_bits_setIdx        (_table_banks_1_io_r_req_bits_setIdx_T),</a>
+<a name="178"><span class="lineNum">     178 </span>            :     .io_r_resp_data_0_valid      (_table_banks_0_io_r_resp_data_0_valid),</a>
+<a name="179"><span class="lineNum">     179 </span>            :     .io_r_resp_data_0_tag        (_table_banks_0_io_r_resp_data_0_tag),</a>
+<a name="180"><span class="lineNum">     180 </span>            :     .io_r_resp_data_0_ctr        (_table_banks_0_io_r_resp_data_0_ctr),</a>
+<a name="181"><span class="lineNum">     181 </span>            :     .io_r_resp_data_0_target     (_table_banks_0_io_r_resp_data_0_target),</a>
+<a name="182"><span class="lineNum">     182 </span>            :     .io_w_req_valid              (_s1_bank_has_write_on_this_req_WIRE_0),</a>
+<a name="183"><span class="lineNum">     183 </span>            :     .io_w_req_bits_setIdx        (update_idx_in_bank),</a>
+<a name="184"><span class="lineNum">     184 </span>            :     .io_w_req_bits_data_0_tag    (update_tag),</a>
+<a name="185"><span class="lineNum">     185 </span>            :     .io_w_req_bits_data_0_ctr    (update_wdata_ctr),</a>
+<a name="186"><span class="lineNum">     186 </span>            :     .io_w_req_bits_data_0_target (update_wdata_target)</a>
+<a name="187"><span class="lineNum">     187 </span>            :   );</a>
+<a name="188"><span class="lineNum">     188 </span>            :   FoldedSRAMTemplate_21 table_banks_1 (</a>
+<a name="189"><span class="lineNum">     189 </span>            :     .clock                       (clock),</a>
+<a name="190"><span class="lineNum">     190 </span>            :     .reset                       (reset),</a>
+<a name="191"><span class="lineNum">     191 </span>            :     .io_r_req_valid              (io_req_valid &amp; _GEN[0]),</a>
+<a name="192"><span class="lineNum">     192 </span>            :     .io_r_req_bits_setIdx        (_table_banks_1_io_r_req_bits_setIdx_T),</a>
+<a name="193"><span class="lineNum">     193 </span>            :     .io_r_resp_data_0_valid      (_table_banks_1_io_r_resp_data_0_valid),</a>
+<a name="194"><span class="lineNum">     194 </span>            :     .io_r_resp_data_0_tag        (_table_banks_1_io_r_resp_data_0_tag),</a>
+<a name="195"><span class="lineNum">     195 </span>            :     .io_r_resp_data_0_ctr        (_table_banks_1_io_r_resp_data_0_ctr),</a>
+<a name="196"><span class="lineNum">     196 </span>            :     .io_r_resp_data_0_target     (_table_banks_1_io_r_resp_data_0_target),</a>
+<a name="197"><span class="lineNum">     197 </span>            :     .io_w_req_valid              (_s1_bank_has_write_on_this_req_WIRE_1),</a>
+<a name="198"><span class="lineNum">     198 </span>            :     .io_w_req_bits_setIdx        (update_idx_in_bank),</a>
+<a name="199"><span class="lineNum">     199 </span>            :     .io_w_req_bits_data_0_tag    (update_tag),</a>
+<a name="200"><span class="lineNum">     200 </span>            :     .io_w_req_bits_data_0_ctr    (update_wdata_ctr),</a>
+<a name="201"><span class="lineNum">     201 </span>            :     .io_w_req_bits_data_0_target (update_wdata_target)</a>
+<a name="202"><span class="lineNum">     202 </span>            :   );</a>
+<a name="203"><span class="lineNum">     203 </span>            :   WrBypass_41 wrbypass (</a>
+<a name="204"><span class="lineNum">     204 </span>            :     .clock              (clock),</a>
+<a name="205"><span class="lineNum">     205 </span>            :     .reset              (reset),</a>
+<a name="206"><span class="lineNum">     206 </span>            :     .io_wen             (io_update_valid),</a>
+<a name="207"><span class="lineNum">     207 </span>            :     .io_write_idx       (update_idx),</a>
+<a name="208"><span class="lineNum">     208 </span>            :     .io_write_data_0    (update_wdata_ctr),</a>
+<a name="209"><span class="lineNum">     209 </span>            :     .io_hit             (_wrbypass_io_hit),</a>
+<a name="210"><span class="lineNum">     210 </span>            :     .io_hit_data_0_bits (_wrbypass_io_hit_data_0_bits)</a>
+<a name="211"><span class="lineNum">     211 </span>            :   );</a>
+<a name="212"><span class="lineNum">     212 </span>            :   assign io_resp_valid =</a>
+<a name="213"><span class="lineNum">     213 </span>            :     (s1_bank_req_1h_0 &amp; _table_banks_0_io_r_resp_data_0_valid | s1_bank_req_1h_1</a>
+<a name="214"><span class="lineNum">     214 </span>            :      &amp; _table_banks_1_io_r_resp_data_0_valid)</a>
+<a name="215"><span class="lineNum">     215 </span>            :     &amp; ((s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_tag : 9'h0)</a>
+<a name="216"><span class="lineNum">     216 </span>            :        | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_tag : 9'h0)) == s1_tag</a>
+<a name="217"><span class="lineNum">     217 </span>            :     &amp; ~_resp_invalid_by_write_T_2;</a>
+<a name="218"><span class="lineNum">     218 </span>            :   assign io_resp_bits_ctr =</a>
+<a name="219"><span class="lineNum">     219 </span>            :     (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_ctr : 2'h0)</a>
+<a name="220"><span class="lineNum">     220 </span>            :     | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 2'h0);</a>
+<a name="221"><span class="lineNum">     221 </span>            :   assign io_resp_bits_u = {1'h0, _us_io_rdata_0};</a>
+<a name="222"><span class="lineNum">     222 </span>            :   assign io_resp_bits_target =</a>
+<a name="223"><span class="lineNum">     223 </span>            :     (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_target : 41'h0)</a>
+<a name="224"><span class="lineNum">     224 </span>            :     | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_target : 41'h0);</a>
+<a name="225"><span class="lineNum">     225 </span>            : endmodule</a>
+<a name="226"><span class="lineNum">     226 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/ITTageTable_1.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/ITTageTable_1.sv.func-sort-c.html
new file mode 100644
index 0000000..716f3b8
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/ITTageTable_1.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/ITTageTable_1.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - ITTageTable_1.sv<span style="font-size: 80%;"> (<a href="ITTageTable_1.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">43</td>
+            <td class="headerCovTableEntry">43</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="ITTageTable_1.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/ITTageTable_1.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/ITTageTable_1.sv.func.html
new file mode 100644
index 0000000..760112c
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/ITTageTable_1.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/ITTageTable_1.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - ITTageTable_1.sv<span style="font-size: 80%;"> (<a href="ITTageTable_1.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">43</td>
+            <td class="headerCovTableEntry">43</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="ITTageTable_1.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/ITTageTable_1.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/ITTageTable_1.sv.gcov.html
new file mode 100644
index 0000000..e3cb537
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/ITTageTable_1.sv.gcov.html
@@ -0,0 +1,297 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/ITTageTable_1.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - ITTageTable_1.sv<span style="font-size: 80%;"> (source / <a href="ITTageTable_1.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">43</td>
+            <td class="headerCovTableEntry">43</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : module ITTageTable_1(</a>
+<a name="59"><span class="lineNum">      59 </span><span class="lineCov">     127786 :   input         clock,</span></a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">         62 :   input         reset,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">         73 :   input         io_req_valid,</span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">      35066 :   input  [40:0] io_req_bits_pc,</span></a>
+<a name="63"><span class="lineNum">      63 </span><span class="lineCov">        564 :   input  [7:0]  io_req_bits_folded_hist_hist_14_folded_hist,</span></a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">         12 :   output        io_resp_valid,</span></a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">         55 :   output [1:0]  io_resp_bits_ctr,</span></a>
+<a name="66"><span class="lineNum">      66 </span><span class="lineCov">        144 :   output [1:0]  io_resp_bits_u,</span></a>
+<a name="67"><span class="lineNum">      67 </span><span class="lineCov">       1170 :   output [40:0] io_resp_bits_target,</span></a>
+<a name="68"><span class="lineNum">      68 </span><span class="lineCov">        577 :   input  [40:0] io_update_pc,</span></a>
+<a name="69"><span class="lineNum">      69 </span><span class="lineCov">        108 :   input  [7:0]  io_update_folded_hist_hist_14_folded_hist,</span></a>
+<a name="70"><span class="lineNum">      70 </span><span class="lineCov">         27 :   input         io_update_valid,</span></a>
+<a name="71"><span class="lineNum">      71 </span><span class="lineCov">         13 :   input         io_update_correct,</span></a>
+<a name="72"><span class="lineNum">      72 </span><span class="lineCov">         13 :   input         io_update_alloc,</span></a>
+<a name="73"><span class="lineNum">      73 </span><span class="lineCov">         33 :   input  [1:0]  io_update_oldCtr,</span></a>
+<a name="74"><span class="lineNum">      74 </span><span class="lineCov">         11 :   input         io_update_uValid,</span></a>
+<a name="75"><span class="lineNum">      75 </span><span class="lineCov">         14 :   input         io_update_u,</span></a>
+<a name="76"><span class="lineNum">      76 </span><span class="lineCov">         33 :   input         io_update_reset_u,</span></a>
+<a name="77"><span class="lineNum">      77 </span><span class="lineCov">        588 :   input  [40:0] io_update_target,</span></a>
+<a name="78"><span class="lineNum">      78 </span><span class="lineCov">        587 :   input  [40:0] io_update_old_target</span></a>
+<a name="79"><span class="lineNum">      79 </span>            : );</a>
+<a name="80"><span class="lineNum">      80 </span>            : </a>
+<a name="81"><span class="lineNum">      81 </span>            :   wire        _resp_invalid_by_write_T_2;</a>
+<a name="82"><span class="lineNum">      82 </span>            :   wire        _wrbypass_io_hit;</a>
+<a name="83"><span class="lineNum">      83 </span>            :   wire [1:0]  _wrbypass_io_hit_data_0_bits;</a>
+<a name="84"><span class="lineNum">      84 </span>            :   wire        _table_banks_1_io_r_resp_data_0_valid;</a>
+<a name="85"><span class="lineNum">      85 </span>            :   wire [8:0]  _table_banks_1_io_r_resp_data_0_tag;</a>
+<a name="86"><span class="lineNum">      86 </span>            :   wire [1:0]  _table_banks_1_io_r_resp_data_0_ctr;</a>
+<a name="87"><span class="lineNum">      87 </span>            :   wire [40:0] _table_banks_1_io_r_resp_data_0_target;</a>
+<a name="88"><span class="lineNum">      88 </span>            :   wire        _table_banks_0_io_r_resp_data_0_valid;</a>
+<a name="89"><span class="lineNum">      89 </span>            :   wire [8:0]  _table_banks_0_io_r_resp_data_0_tag;</a>
+<a name="90"><span class="lineNum">      90 </span>            :   wire [1:0]  _table_banks_0_io_r_resp_data_0_ctr;</a>
+<a name="91"><span class="lineNum">      91 </span>            :   wire [40:0] _table_banks_0_io_r_resp_data_0_target;</a>
+<a name="92"><span class="lineNum">      92 </span>            :   wire        _us_io_rdata_0;</a>
+<a name="93"><span class="lineNum">      93 </span><span class="lineCov">      24675 :   wire [7:0]  s0_idx = io_req_bits_pc[8:1] ^ io_req_bits_folded_hist_hist_14_folded_hist;</span></a>
+<a name="94"><span class="lineNum">      94 </span><span class="lineCov">        720 :   reg  [8:0]  s1_tag;</span></a>
+<a name="95"><span class="lineNum">      95 </span><span class="lineCov">         46 :   reg         s1_bank_req_1h_0;</span></a>
+<a name="96"><span class="lineNum">      96 </span><span class="lineCov">         53 :   reg         s1_bank_req_1h_1;</span></a>
+<a name="97"><span class="lineNum">      97 </span><span class="lineCov">         29 :   reg         s1_bank_has_write_on_this_req_0;</span></a>
+<a name="98"><span class="lineNum">      98 </span><span class="lineCov">         30 :   reg         s1_bank_has_write_on_this_req_1;</span></a>
+<a name="99"><span class="lineNum">      99 </span><span class="lineCov">        105 :   wire [7:0]  update_idx = io_update_pc[8:1] ^ io_update_folded_hist_hist_14_folded_hist;</span></a>
+<a name="100"><span class="lineNum">     100 </span><span class="lineCov">        127 :   wire [8:0]  update_tag =</span></a>
+<a name="101"><span class="lineNum">     101 </span>            :     {io_update_pc[17], io_update_pc[16:9] ^ io_update_folded_hist_hist_14_folded_hist}</a>
+<a name="102"><span class="lineNum">     102 </span>            :     ^ {io_update_folded_hist_hist_14_folded_hist, 1'h0};</a>
+<a name="103"><span class="lineNum">     103 </span>            :   assign _resp_invalid_by_write_T_2 =</a>
+<a name="104"><span class="lineNum">     104 </span>            :     s1_bank_req_1h_0 &amp; s1_bank_has_write_on_this_req_0 | s1_bank_req_1h_1</a>
+<a name="105"><span class="lineNum">     105 </span>            :     &amp; s1_bank_has_write_on_this_req_1;</a>
+<a name="106"><span class="lineNum">     106 </span>            :   wire        _s1_bank_has_write_on_this_req_WIRE_0 = io_update_valid &amp; ~(update_idx[0]);</a>
+<a name="107"><span class="lineNum">     107 </span>            :   wire        _s1_bank_has_write_on_this_req_WIRE_1 = io_update_valid &amp; update_idx[0];</a>
+<a name="108"><span class="lineNum">     108 </span><span class="lineCov">         51 :   wire [1:0]  old_ctr =</span></a>
+<a name="109"><span class="lineNum">     109 </span>            :     _wrbypass_io_hit ? _wrbypass_io_hit_data_0_bits : io_update_oldCtr;</a>
+<a name="110"><span class="lineNum">     110 </span><span class="lineCov">         19 :   wire        update_wdata_ctr_oldSatNotTaken = old_ctr == 2'h0;</span></a>
+<a name="111"><span class="lineNum">     111 </span><span class="lineCov">         36 :   wire [1:0]  update_wdata_ctr =</span></a>
+<a name="112"><span class="lineNum">     112 </span>            :     io_update_alloc</a>
+<a name="113"><span class="lineNum">     113 </span>            :       ? 2'h2</a>
+<a name="114"><span class="lineNum">     114 </span>            :       : (&amp;old_ctr) &amp; io_update_correct</a>
+<a name="115"><span class="lineNum">     115 </span>            :           ? 2'h3</a>
+<a name="116"><span class="lineNum">     116 </span>            :           : update_wdata_ctr_oldSatNotTaken &amp; ~io_update_correct</a>
+<a name="117"><span class="lineNum">     117 </span>            :               ? 2'h0</a>
+<a name="118"><span class="lineNum">     118 </span>            :               : io_update_correct ? 2'(old_ctr + 2'h1) : 2'(old_ctr - 2'h1);</a>
+<a name="119"><span class="lineNum">     119 </span><span class="lineCov">        642 :   wire [40:0] update_wdata_target =</span></a>
+<a name="120"><span class="lineNum">     120 </span>            :     io_update_alloc | update_wdata_ctr_oldSatNotTaken</a>
+<a name="121"><span class="lineNum">     121 </span>            :       ? io_update_target</a>
+<a name="122"><span class="lineNum">     122 </span>            :       : io_update_old_target;</a>
+<a name="123"><span class="lineNum">     123 </span><span class="lineCov">     127694 :   always @(posedge clock) begin</span></a>
+<a name="124"><span class="lineNum">     124 </span><span class="lineCov">       8350 :     if (io_req_valid) begin</span></a>
+<a name="125"><span class="lineNum">     125 </span><span class="lineCov">       4175 :       s1_tag &lt;=</span></a>
+<a name="126"><span class="lineNum">     126 </span><span class="lineCov">       4175 :         {io_req_bits_pc[17],</span></a>
+<a name="127"><span class="lineNum">     127 </span><span class="lineCov">       4175 :          io_req_bits_pc[16:9] ^ io_req_bits_folded_hist_hist_14_folded_hist}</span></a>
+<a name="128"><span class="lineNum">     128 </span><span class="lineCov">       4175 :         ^ {io_req_bits_folded_hist_hist_14_folded_hist, 1'h0};</span></a>
+<a name="129"><span class="lineNum">     129 </span><span class="lineCov">       4175 :       s1_bank_req_1h_0 &lt;= ~(s0_idx[0]);</span></a>
+<a name="130"><span class="lineNum">     130 </span><span class="lineCov">       4175 :       s1_bank_req_1h_1 &lt;= s0_idx[0];</span></a>
+<a name="131"><span class="lineNum">     131 </span><span class="lineCov">       4175 :       s1_bank_has_write_on_this_req_0 &lt;= _s1_bank_has_write_on_this_req_WIRE_0;</span></a>
+<a name="132"><span class="lineNum">     132 </span><span class="lineCov">       4175 :       s1_bank_has_write_on_this_req_1 &lt;= _s1_bank_has_write_on_this_req_WIRE_1;</span></a>
+<a name="133"><span class="lineNum">     133 </span>            :     end</a>
+<a name="134"><span class="lineNum">     134 </span>            :   end // always @(posedge)</a>
+<a name="135"><span class="lineNum">     135 </span>            :   `ifdef ENABLE_INITIAL_REG_</a>
+<a name="136"><span class="lineNum">     136 </span>            :     `ifdef FIRRTL_BEFORE_INITIAL</a>
+<a name="137"><span class="lineNum">     137 </span>            :       `FIRRTL_BEFORE_INITIAL</a>
+<a name="138"><span class="lineNum">     138 </span>            :     `endif // FIRRTL_BEFORE_INITIAL</a>
+<a name="139"><span class="lineNum">     139 </span>            :     logic [31:0] _RANDOM[0:0];</a>
+<a name="140"><span class="lineNum">     140 </span><span class="lineCov">         58 :     initial begin</span></a>
+<a name="141"><span class="lineNum">     141 </span>            :       `ifdef INIT_RANDOM_PROLOG_</a>
+<a name="142"><span class="lineNum">     142 </span>            :         `INIT_RANDOM_PROLOG_</a>
+<a name="143"><span class="lineNum">     143 </span>            :       `endif // INIT_RANDOM_PROLOG_</a>
+<a name="144"><span class="lineNum">     144 </span>            :       `ifdef RANDOMIZE_REG_INIT</a>
+<a name="145"><span class="lineNum">     145 </span>            :         _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;</a>
+<a name="146"><span class="lineNum">     146 </span>            :         s1_tag = _RANDOM[/*Zero width*/ 1'b0][16:8];</a>
+<a name="147"><span class="lineNum">     147 </span>            :         s1_bank_req_1h_0 = _RANDOM[/*Zero width*/ 1'b0][17];</a>
+<a name="148"><span class="lineNum">     148 </span>            :         s1_bank_req_1h_1 = _RANDOM[/*Zero width*/ 1'b0][18];</a>
+<a name="149"><span class="lineNum">     149 </span>            :         s1_bank_has_write_on_this_req_0 = _RANDOM[/*Zero width*/ 1'b0][19];</a>
+<a name="150"><span class="lineNum">     150 </span>            :         s1_bank_has_write_on_this_req_1 = _RANDOM[/*Zero width*/ 1'b0][20];</a>
+<a name="151"><span class="lineNum">     151 </span>            :       `endif // RANDOMIZE_REG_INIT</a>
+<a name="152"><span class="lineNum">     152 </span>            :     end // initial</a>
+<a name="153"><span class="lineNum">     153 </span>            :     `ifdef FIRRTL_AFTER_INITIAL</a>
+<a name="154"><span class="lineNum">     154 </span>            :       `FIRRTL_AFTER_INITIAL</a>
+<a name="155"><span class="lineNum">     155 </span>            :     `endif // FIRRTL_AFTER_INITIAL</a>
+<a name="156"><span class="lineNum">     156 </span>            :   `endif // ENABLE_INITIAL_REG_</a>
+<a name="157"><span class="lineNum">     157 </span>            :   Folded1WDataModuleTemplate us (</a>
+<a name="158"><span class="lineNum">     158 </span>            :     .clock      (clock),</a>
+<a name="159"><span class="lineNum">     159 </span>            :     .reset      (reset),</a>
+<a name="160"><span class="lineNum">     160 </span>            :     .io_ren_0   (io_req_valid),</a>
+<a name="161"><span class="lineNum">     161 </span>            :     .io_raddr_0 (s0_idx),</a>
+<a name="162"><span class="lineNum">     162 </span>            :     .io_rdata_0 (_us_io_rdata_0),</a>
+<a name="163"><span class="lineNum">     163 </span>            :     .io_wen     (io_update_uValid),</a>
+<a name="164"><span class="lineNum">     164 </span>            :     .io_waddr   (update_idx),</a>
+<a name="165"><span class="lineNum">     165 </span>            :     .io_wdata   (io_update_u),</a>
+<a name="166"><span class="lineNum">     166 </span>            :     .io_resetEn (io_update_reset_u)</a>
+<a name="167"><span class="lineNum">     167 </span>            :   );</a>
+<a name="168"><span class="lineNum">     168 </span>            :   FoldedSRAMTemplate_21 table_banks_0 (</a>
+<a name="169"><span class="lineNum">     169 </span>            :     .clock                       (clock),</a>
+<a name="170"><span class="lineNum">     170 </span>            :     .reset                       (reset),</a>
+<a name="171"><span class="lineNum">     171 </span>            :     .io_r_req_valid              (io_req_valid &amp; ~(s0_idx[0])),</a>
+<a name="172"><span class="lineNum">     172 </span>            :     .io_r_req_bits_setIdx        (s0_idx[7:1]),</a>
+<a name="173"><span class="lineNum">     173 </span>            :     .io_r_resp_data_0_valid      (_table_banks_0_io_r_resp_data_0_valid),</a>
+<a name="174"><span class="lineNum">     174 </span>            :     .io_r_resp_data_0_tag        (_table_banks_0_io_r_resp_data_0_tag),</a>
+<a name="175"><span class="lineNum">     175 </span>            :     .io_r_resp_data_0_ctr        (_table_banks_0_io_r_resp_data_0_ctr),</a>
+<a name="176"><span class="lineNum">     176 </span>            :     .io_r_resp_data_0_target     (_table_banks_0_io_r_resp_data_0_target),</a>
+<a name="177"><span class="lineNum">     177 </span>            :     .io_w_req_valid              (_s1_bank_has_write_on_this_req_WIRE_0),</a>
+<a name="178"><span class="lineNum">     178 </span>            :     .io_w_req_bits_setIdx        (update_idx[7:1]),</a>
+<a name="179"><span class="lineNum">     179 </span>            :     .io_w_req_bits_data_0_tag    (update_tag),</a>
+<a name="180"><span class="lineNum">     180 </span>            :     .io_w_req_bits_data_0_ctr    (update_wdata_ctr),</a>
+<a name="181"><span class="lineNum">     181 </span>            :     .io_w_req_bits_data_0_target (update_wdata_target)</a>
+<a name="182"><span class="lineNum">     182 </span>            :   );</a>
+<a name="183"><span class="lineNum">     183 </span>            :   FoldedSRAMTemplate_21 table_banks_1 (</a>
+<a name="184"><span class="lineNum">     184 </span>            :     .clock                       (clock),</a>
+<a name="185"><span class="lineNum">     185 </span>            :     .reset                       (reset),</a>
+<a name="186"><span class="lineNum">     186 </span>            :     .io_r_req_valid              (io_req_valid &amp; s0_idx[0]),</a>
+<a name="187"><span class="lineNum">     187 </span>            :     .io_r_req_bits_setIdx        (s0_idx[7:1]),</a>
+<a name="188"><span class="lineNum">     188 </span>            :     .io_r_resp_data_0_valid      (_table_banks_1_io_r_resp_data_0_valid),</a>
+<a name="189"><span class="lineNum">     189 </span>            :     .io_r_resp_data_0_tag        (_table_banks_1_io_r_resp_data_0_tag),</a>
+<a name="190"><span class="lineNum">     190 </span>            :     .io_r_resp_data_0_ctr        (_table_banks_1_io_r_resp_data_0_ctr),</a>
+<a name="191"><span class="lineNum">     191 </span>            :     .io_r_resp_data_0_target     (_table_banks_1_io_r_resp_data_0_target),</a>
+<a name="192"><span class="lineNum">     192 </span>            :     .io_w_req_valid              (_s1_bank_has_write_on_this_req_WIRE_1),</a>
+<a name="193"><span class="lineNum">     193 </span>            :     .io_w_req_bits_setIdx        (update_idx[7:1]),</a>
+<a name="194"><span class="lineNum">     194 </span>            :     .io_w_req_bits_data_0_tag    (update_tag),</a>
+<a name="195"><span class="lineNum">     195 </span>            :     .io_w_req_bits_data_0_ctr    (update_wdata_ctr),</a>
+<a name="196"><span class="lineNum">     196 </span>            :     .io_w_req_bits_data_0_target (update_wdata_target)</a>
+<a name="197"><span class="lineNum">     197 </span>            :   );</a>
+<a name="198"><span class="lineNum">     198 </span>            :   WrBypass_41 wrbypass (</a>
+<a name="199"><span class="lineNum">     199 </span>            :     .clock              (clock),</a>
+<a name="200"><span class="lineNum">     200 </span>            :     .reset              (reset),</a>
+<a name="201"><span class="lineNum">     201 </span>            :     .io_wen             (io_update_valid),</a>
+<a name="202"><span class="lineNum">     202 </span>            :     .io_write_idx       (update_idx),</a>
+<a name="203"><span class="lineNum">     203 </span>            :     .io_write_data_0    (update_wdata_ctr),</a>
+<a name="204"><span class="lineNum">     204 </span>            :     .io_hit             (_wrbypass_io_hit),</a>
+<a name="205"><span class="lineNum">     205 </span>            :     .io_hit_data_0_bits (_wrbypass_io_hit_data_0_bits)</a>
+<a name="206"><span class="lineNum">     206 </span>            :   );</a>
+<a name="207"><span class="lineNum">     207 </span>            :   assign io_resp_valid =</a>
+<a name="208"><span class="lineNum">     208 </span>            :     (s1_bank_req_1h_0 &amp; _table_banks_0_io_r_resp_data_0_valid | s1_bank_req_1h_1</a>
+<a name="209"><span class="lineNum">     209 </span>            :      &amp; _table_banks_1_io_r_resp_data_0_valid)</a>
+<a name="210"><span class="lineNum">     210 </span>            :     &amp; ((s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_tag : 9'h0)</a>
+<a name="211"><span class="lineNum">     211 </span>            :        | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_tag : 9'h0)) == s1_tag</a>
+<a name="212"><span class="lineNum">     212 </span>            :     &amp; ~_resp_invalid_by_write_T_2;</a>
+<a name="213"><span class="lineNum">     213 </span>            :   assign io_resp_bits_ctr =</a>
+<a name="214"><span class="lineNum">     214 </span>            :     (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_ctr : 2'h0)</a>
+<a name="215"><span class="lineNum">     215 </span>            :     | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 2'h0);</a>
+<a name="216"><span class="lineNum">     216 </span>            :   assign io_resp_bits_u = {1'h0, _us_io_rdata_0};</a>
+<a name="217"><span class="lineNum">     217 </span>            :   assign io_resp_bits_target =</a>
+<a name="218"><span class="lineNum">     218 </span>            :     (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_target : 41'h0)</a>
+<a name="219"><span class="lineNum">     219 </span>            :     | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_target : 41'h0);</a>
+<a name="220"><span class="lineNum">     220 </span>            : endmodule</a>
+<a name="221"><span class="lineNum">     221 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/ITTageTable_2.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/ITTageTable_2.sv.func-sort-c.html
new file mode 100644
index 0000000..8a8c0d9
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/ITTageTable_2.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/ITTageTable_2.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - ITTageTable_2.sv<span style="font-size: 80%;"> (<a href="ITTageTable_2.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">44</td>
+            <td class="headerCovTableEntry">44</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="ITTageTable_2.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/ITTageTable_2.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/ITTageTable_2.sv.func.html
new file mode 100644
index 0000000..0dd0676
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/ITTageTable_2.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/ITTageTable_2.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - ITTageTable_2.sv<span style="font-size: 80%;"> (<a href="ITTageTable_2.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">44</td>
+            <td class="headerCovTableEntry">44</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="ITTageTable_2.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/ITTageTable_2.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/ITTageTable_2.sv.gcov.html
new file mode 100644
index 0000000..a48f1ea
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/ITTageTable_2.sv.gcov.html
@@ -0,0 +1,298 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/ITTageTable_2.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - ITTageTable_2.sv<span style="font-size: 80%;"> (source / <a href="ITTageTable_2.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">44</td>
+            <td class="headerCovTableEntry">44</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : module ITTageTable_2(</a>
+<a name="59"><span class="lineNum">      59 </span><span class="lineCov">     127786 :   input         clock,</span></a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">         62 :   input         reset,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">         73 :   input         io_req_valid,</span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">      35066 :   input  [40:0] io_req_bits_pc,</span></a>
+<a name="63"><span class="lineNum">      63 </span><span class="lineCov">        989 :   input  [8:0]  io_req_bits_folded_hist_hist_13_folded_hist,</span></a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">        602 :   input  [7:0]  io_req_bits_folded_hist_hist_4_folded_hist,</span></a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">         20 :   output        io_resp_valid,</span></a>
+<a name="66"><span class="lineNum">      66 </span><span class="lineCov">         54 :   output [1:0]  io_resp_bits_ctr,</span></a>
+<a name="67"><span class="lineNum">      67 </span><span class="lineCov">        123 :   output [1:0]  io_resp_bits_u,</span></a>
+<a name="68"><span class="lineNum">      68 </span><span class="lineCov">       1136 :   output [40:0] io_resp_bits_target,</span></a>
+<a name="69"><span class="lineNum">      69 </span><span class="lineCov">        598 :   input  [40:0] io_update_pc,</span></a>
+<a name="70"><span class="lineNum">      70 </span><span class="lineCov">        111 :   input  [8:0]  io_update_folded_hist_hist_13_folded_hist,</span></a>
+<a name="71"><span class="lineNum">      71 </span><span class="lineCov">        106 :   input  [7:0]  io_update_folded_hist_hist_4_folded_hist,</span></a>
+<a name="72"><span class="lineNum">      72 </span><span class="lineCov">         27 :   input         io_update_valid,</span></a>
+<a name="73"><span class="lineNum">      73 </span><span class="lineCov">         13 :   input         io_update_correct,</span></a>
+<a name="74"><span class="lineNum">      74 </span><span class="lineCov">         16 :   input         io_update_alloc,</span></a>
+<a name="75"><span class="lineNum">      75 </span><span class="lineCov">         24 :   input  [1:0]  io_update_oldCtr,</span></a>
+<a name="76"><span class="lineNum">      76 </span><span class="lineCov">         17 :   input         io_update_uValid,</span></a>
+<a name="77"><span class="lineNum">      77 </span><span class="lineCov">         13 :   input         io_update_u,</span></a>
+<a name="78"><span class="lineNum">      78 </span><span class="lineCov">         32 :   input         io_update_reset_u,</span></a>
+<a name="79"><span class="lineNum">      79 </span><span class="lineCov">        620 :   input  [40:0] io_update_target,</span></a>
+<a name="80"><span class="lineNum">      80 </span><span class="lineCov">        577 :   input  [40:0] io_update_old_target</span></a>
+<a name="81"><span class="lineNum">      81 </span>            : );</a>
+<a name="82"><span class="lineNum">      82 </span>            : </a>
+<a name="83"><span class="lineNum">      83 </span>            :   wire        _resp_invalid_by_write_T_2;</a>
+<a name="84"><span class="lineNum">      84 </span>            :   wire        _wrbypass_io_hit;</a>
+<a name="85"><span class="lineNum">      85 </span>            :   wire [1:0]  _wrbypass_io_hit_data_0_bits;</a>
+<a name="86"><span class="lineNum">      86 </span>            :   wire        _table_banks_1_io_r_resp_data_0_valid;</a>
+<a name="87"><span class="lineNum">      87 </span>            :   wire [8:0]  _table_banks_1_io_r_resp_data_0_tag;</a>
+<a name="88"><span class="lineNum">      88 </span>            :   wire [1:0]  _table_banks_1_io_r_resp_data_0_ctr;</a>
+<a name="89"><span class="lineNum">      89 </span>            :   wire [40:0] _table_banks_1_io_r_resp_data_0_target;</a>
+<a name="90"><span class="lineNum">      90 </span>            :   wire        _table_banks_0_io_r_resp_data_0_valid;</a>
+<a name="91"><span class="lineNum">      91 </span>            :   wire [8:0]  _table_banks_0_io_r_resp_data_0_tag;</a>
+<a name="92"><span class="lineNum">      92 </span>            :   wire [1:0]  _table_banks_0_io_r_resp_data_0_ctr;</a>
+<a name="93"><span class="lineNum">      93 </span>            :   wire [40:0] _table_banks_0_io_r_resp_data_0_target;</a>
+<a name="94"><span class="lineNum">      94 </span>            :   wire        _us_io_rdata_0;</a>
+<a name="95"><span class="lineNum">      95 </span><span class="lineCov">       8574 :   wire [8:0]  s0_idx = io_req_bits_pc[9:1] ^ io_req_bits_folded_hist_hist_13_folded_hist;</span></a>
+<a name="96"><span class="lineNum">      96 </span><span class="lineCov">        516 :   reg  [8:0]  s1_tag;</span></a>
+<a name="97"><span class="lineNum">      97 </span><span class="lineCov">         48 :   reg         s1_bank_req_1h_0;</span></a>
+<a name="98"><span class="lineNum">      98 </span><span class="lineCov">         52 :   reg         s1_bank_req_1h_1;</span></a>
+<a name="99"><span class="lineNum">      99 </span><span class="lineCov">         34 :   reg         s1_bank_has_write_on_this_req_0;</span></a>
+<a name="100"><span class="lineNum">     100 </span><span class="lineCov">         28 :   reg         s1_bank_has_write_on_this_req_1;</span></a>
+<a name="101"><span class="lineNum">     101 </span><span class="lineCov">        126 :   wire [8:0]  update_idx = io_update_pc[9:1] ^ io_update_folded_hist_hist_13_folded_hist;</span></a>
+<a name="102"><span class="lineNum">     102 </span><span class="lineCov">        121 :   wire [8:0]  update_tag =</span></a>
+<a name="103"><span class="lineNum">     103 </span>            :     io_update_pc[18:10] ^ io_update_folded_hist_hist_13_folded_hist</a>
+<a name="104"><span class="lineNum">     104 </span>            :     ^ {io_update_folded_hist_hist_4_folded_hist, 1'h0};</a>
+<a name="105"><span class="lineNum">     105 </span>            :   assign _resp_invalid_by_write_T_2 =</a>
+<a name="106"><span class="lineNum">     106 </span>            :     s1_bank_req_1h_0 &amp; s1_bank_has_write_on_this_req_0 | s1_bank_req_1h_1</a>
+<a name="107"><span class="lineNum">     107 </span>            :     &amp; s1_bank_has_write_on_this_req_1;</a>
+<a name="108"><span class="lineNum">     108 </span>            :   wire        _s1_bank_has_write_on_this_req_WIRE_0 = io_update_valid &amp; ~(update_idx[0]);</a>
+<a name="109"><span class="lineNum">     109 </span>            :   wire        _s1_bank_has_write_on_this_req_WIRE_1 = io_update_valid &amp; update_idx[0];</a>
+<a name="110"><span class="lineNum">     110 </span><span class="lineCov">         45 :   wire [1:0]  old_ctr =</span></a>
+<a name="111"><span class="lineNum">     111 </span>            :     _wrbypass_io_hit ? _wrbypass_io_hit_data_0_bits : io_update_oldCtr;</a>
+<a name="112"><span class="lineNum">     112 </span><span class="lineCov">         11 :   wire        update_wdata_ctr_oldSatNotTaken = old_ctr == 2'h0;</span></a>
+<a name="113"><span class="lineNum">     113 </span><span class="lineCov">         31 :   wire [1:0]  update_wdata_ctr =</span></a>
+<a name="114"><span class="lineNum">     114 </span>            :     io_update_alloc</a>
+<a name="115"><span class="lineNum">     115 </span>            :       ? 2'h2</a>
+<a name="116"><span class="lineNum">     116 </span>            :       : (&amp;old_ctr) &amp; io_update_correct</a>
+<a name="117"><span class="lineNum">     117 </span>            :           ? 2'h3</a>
+<a name="118"><span class="lineNum">     118 </span>            :           : update_wdata_ctr_oldSatNotTaken &amp; ~io_update_correct</a>
+<a name="119"><span class="lineNum">     119 </span>            :               ? 2'h0</a>
+<a name="120"><span class="lineNum">     120 </span>            :               : io_update_correct ? 2'(old_ctr + 2'h1) : 2'(old_ctr - 2'h1);</a>
+<a name="121"><span class="lineNum">     121 </span><span class="lineCov">        613 :   wire [40:0] update_wdata_target =</span></a>
+<a name="122"><span class="lineNum">     122 </span>            :     io_update_alloc | update_wdata_ctr_oldSatNotTaken</a>
+<a name="123"><span class="lineNum">     123 </span>            :       ? io_update_target</a>
+<a name="124"><span class="lineNum">     124 </span>            :       : io_update_old_target;</a>
+<a name="125"><span class="lineNum">     125 </span><span class="lineCov">     127694 :   always @(posedge clock) begin</span></a>
+<a name="126"><span class="lineNum">     126 </span><span class="lineCov">       8350 :     if (io_req_valid) begin</span></a>
+<a name="127"><span class="lineNum">     127 </span><span class="lineCov">       4175 :       s1_tag &lt;=</span></a>
+<a name="128"><span class="lineNum">     128 </span><span class="lineCov">       4175 :         io_req_bits_pc[18:10] ^ io_req_bits_folded_hist_hist_13_folded_hist</span></a>
+<a name="129"><span class="lineNum">     129 </span><span class="lineCov">       4175 :         ^ {io_req_bits_folded_hist_hist_4_folded_hist, 1'h0};</span></a>
+<a name="130"><span class="lineNum">     130 </span><span class="lineCov">       4175 :       s1_bank_req_1h_0 &lt;= ~(s0_idx[0]);</span></a>
+<a name="131"><span class="lineNum">     131 </span><span class="lineCov">       4175 :       s1_bank_req_1h_1 &lt;= s0_idx[0];</span></a>
+<a name="132"><span class="lineNum">     132 </span><span class="lineCov">       4175 :       s1_bank_has_write_on_this_req_0 &lt;= _s1_bank_has_write_on_this_req_WIRE_0;</span></a>
+<a name="133"><span class="lineNum">     133 </span><span class="lineCov">       4175 :       s1_bank_has_write_on_this_req_1 &lt;= _s1_bank_has_write_on_this_req_WIRE_1;</span></a>
+<a name="134"><span class="lineNum">     134 </span>            :     end</a>
+<a name="135"><span class="lineNum">     135 </span>            :   end // always @(posedge)</a>
+<a name="136"><span class="lineNum">     136 </span>            :   `ifdef ENABLE_INITIAL_REG_</a>
+<a name="137"><span class="lineNum">     137 </span>            :     `ifdef FIRRTL_BEFORE_INITIAL</a>
+<a name="138"><span class="lineNum">     138 </span>            :       `FIRRTL_BEFORE_INITIAL</a>
+<a name="139"><span class="lineNum">     139 </span>            :     `endif // FIRRTL_BEFORE_INITIAL</a>
+<a name="140"><span class="lineNum">     140 </span>            :     logic [31:0] _RANDOM[0:0];</a>
+<a name="141"><span class="lineNum">     141 </span><span class="lineCov">         58 :     initial begin</span></a>
+<a name="142"><span class="lineNum">     142 </span>            :       `ifdef INIT_RANDOM_PROLOG_</a>
+<a name="143"><span class="lineNum">     143 </span>            :         `INIT_RANDOM_PROLOG_</a>
+<a name="144"><span class="lineNum">     144 </span>            :       `endif // INIT_RANDOM_PROLOG_</a>
+<a name="145"><span class="lineNum">     145 </span>            :       `ifdef RANDOMIZE_REG_INIT</a>
+<a name="146"><span class="lineNum">     146 </span>            :         _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;</a>
+<a name="147"><span class="lineNum">     147 </span>            :         s1_tag = _RANDOM[/*Zero width*/ 1'b0][17:9];</a>
+<a name="148"><span class="lineNum">     148 </span>            :         s1_bank_req_1h_0 = _RANDOM[/*Zero width*/ 1'b0][18];</a>
+<a name="149"><span class="lineNum">     149 </span>            :         s1_bank_req_1h_1 = _RANDOM[/*Zero width*/ 1'b0][19];</a>
+<a name="150"><span class="lineNum">     150 </span>            :         s1_bank_has_write_on_this_req_0 = _RANDOM[/*Zero width*/ 1'b0][20];</a>
+<a name="151"><span class="lineNum">     151 </span>            :         s1_bank_has_write_on_this_req_1 = _RANDOM[/*Zero width*/ 1'b0][21];</a>
+<a name="152"><span class="lineNum">     152 </span>            :       `endif // RANDOMIZE_REG_INIT</a>
+<a name="153"><span class="lineNum">     153 </span>            :     end // initial</a>
+<a name="154"><span class="lineNum">     154 </span>            :     `ifdef FIRRTL_AFTER_INITIAL</a>
+<a name="155"><span class="lineNum">     155 </span>            :       `FIRRTL_AFTER_INITIAL</a>
+<a name="156"><span class="lineNum">     156 </span>            :     `endif // FIRRTL_AFTER_INITIAL</a>
+<a name="157"><span class="lineNum">     157 </span>            :   `endif // ENABLE_INITIAL_REG_</a>
+<a name="158"><span class="lineNum">     158 </span>            :   Folded1WDataModuleTemplate_2 us (</a>
+<a name="159"><span class="lineNum">     159 </span>            :     .clock      (clock),</a>
+<a name="160"><span class="lineNum">     160 </span>            :     .reset      (reset),</a>
+<a name="161"><span class="lineNum">     161 </span>            :     .io_ren_0   (io_req_valid),</a>
+<a name="162"><span class="lineNum">     162 </span>            :     .io_raddr_0 (s0_idx),</a>
+<a name="163"><span class="lineNum">     163 </span>            :     .io_rdata_0 (_us_io_rdata_0),</a>
+<a name="164"><span class="lineNum">     164 </span>            :     .io_wen     (io_update_uValid),</a>
+<a name="165"><span class="lineNum">     165 </span>            :     .io_waddr   (update_idx),</a>
+<a name="166"><span class="lineNum">     166 </span>            :     .io_wdata   (io_update_u),</a>
+<a name="167"><span class="lineNum">     167 </span>            :     .io_resetEn (io_update_reset_u)</a>
+<a name="168"><span class="lineNum">     168 </span>            :   );</a>
+<a name="169"><span class="lineNum">     169 </span>            :   FoldedSRAMTemplate_25 table_banks_0 (</a>
+<a name="170"><span class="lineNum">     170 </span>            :     .clock                       (clock),</a>
+<a name="171"><span class="lineNum">     171 </span>            :     .reset                       (reset),</a>
+<a name="172"><span class="lineNum">     172 </span>            :     .io_r_req_valid              (io_req_valid &amp; ~(s0_idx[0])),</a>
+<a name="173"><span class="lineNum">     173 </span>            :     .io_r_req_bits_setIdx        (s0_idx[8:1]),</a>
+<a name="174"><span class="lineNum">     174 </span>            :     .io_r_resp_data_0_valid      (_table_banks_0_io_r_resp_data_0_valid),</a>
+<a name="175"><span class="lineNum">     175 </span>            :     .io_r_resp_data_0_tag        (_table_banks_0_io_r_resp_data_0_tag),</a>
+<a name="176"><span class="lineNum">     176 </span>            :     .io_r_resp_data_0_ctr        (_table_banks_0_io_r_resp_data_0_ctr),</a>
+<a name="177"><span class="lineNum">     177 </span>            :     .io_r_resp_data_0_target     (_table_banks_0_io_r_resp_data_0_target),</a>
+<a name="178"><span class="lineNum">     178 </span>            :     .io_w_req_valid              (_s1_bank_has_write_on_this_req_WIRE_0),</a>
+<a name="179"><span class="lineNum">     179 </span>            :     .io_w_req_bits_setIdx        (update_idx[8:1]),</a>
+<a name="180"><span class="lineNum">     180 </span>            :     .io_w_req_bits_data_0_tag    (update_tag),</a>
+<a name="181"><span class="lineNum">     181 </span>            :     .io_w_req_bits_data_0_ctr    (update_wdata_ctr),</a>
+<a name="182"><span class="lineNum">     182 </span>            :     .io_w_req_bits_data_0_target (update_wdata_target)</a>
+<a name="183"><span class="lineNum">     183 </span>            :   );</a>
+<a name="184"><span class="lineNum">     184 </span>            :   FoldedSRAMTemplate_25 table_banks_1 (</a>
+<a name="185"><span class="lineNum">     185 </span>            :     .clock                       (clock),</a>
+<a name="186"><span class="lineNum">     186 </span>            :     .reset                       (reset),</a>
+<a name="187"><span class="lineNum">     187 </span>            :     .io_r_req_valid              (io_req_valid &amp; s0_idx[0]),</a>
+<a name="188"><span class="lineNum">     188 </span>            :     .io_r_req_bits_setIdx        (s0_idx[8:1]),</a>
+<a name="189"><span class="lineNum">     189 </span>            :     .io_r_resp_data_0_valid      (_table_banks_1_io_r_resp_data_0_valid),</a>
+<a name="190"><span class="lineNum">     190 </span>            :     .io_r_resp_data_0_tag        (_table_banks_1_io_r_resp_data_0_tag),</a>
+<a name="191"><span class="lineNum">     191 </span>            :     .io_r_resp_data_0_ctr        (_table_banks_1_io_r_resp_data_0_ctr),</a>
+<a name="192"><span class="lineNum">     192 </span>            :     .io_r_resp_data_0_target     (_table_banks_1_io_r_resp_data_0_target),</a>
+<a name="193"><span class="lineNum">     193 </span>            :     .io_w_req_valid              (_s1_bank_has_write_on_this_req_WIRE_1),</a>
+<a name="194"><span class="lineNum">     194 </span>            :     .io_w_req_bits_setIdx        (update_idx[8:1]),</a>
+<a name="195"><span class="lineNum">     195 </span>            :     .io_w_req_bits_data_0_tag    (update_tag),</a>
+<a name="196"><span class="lineNum">     196 </span>            :     .io_w_req_bits_data_0_ctr    (update_wdata_ctr),</a>
+<a name="197"><span class="lineNum">     197 </span>            :     .io_w_req_bits_data_0_target (update_wdata_target)</a>
+<a name="198"><span class="lineNum">     198 </span>            :   );</a>
+<a name="199"><span class="lineNum">     199 </span>            :   WrBypass_43 wrbypass (</a>
+<a name="200"><span class="lineNum">     200 </span>            :     .clock              (clock),</a>
+<a name="201"><span class="lineNum">     201 </span>            :     .reset              (reset),</a>
+<a name="202"><span class="lineNum">     202 </span>            :     .io_wen             (io_update_valid),</a>
+<a name="203"><span class="lineNum">     203 </span>            :     .io_write_idx       (update_idx),</a>
+<a name="204"><span class="lineNum">     204 </span>            :     .io_write_data_0    (update_wdata_ctr),</a>
+<a name="205"><span class="lineNum">     205 </span>            :     .io_hit             (_wrbypass_io_hit),</a>
+<a name="206"><span class="lineNum">     206 </span>            :     .io_hit_data_0_bits (_wrbypass_io_hit_data_0_bits)</a>
+<a name="207"><span class="lineNum">     207 </span>            :   );</a>
+<a name="208"><span class="lineNum">     208 </span>            :   assign io_resp_valid =</a>
+<a name="209"><span class="lineNum">     209 </span>            :     (s1_bank_req_1h_0 &amp; _table_banks_0_io_r_resp_data_0_valid | s1_bank_req_1h_1</a>
+<a name="210"><span class="lineNum">     210 </span>            :      &amp; _table_banks_1_io_r_resp_data_0_valid)</a>
+<a name="211"><span class="lineNum">     211 </span>            :     &amp; ((s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_tag : 9'h0)</a>
+<a name="212"><span class="lineNum">     212 </span>            :        | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_tag : 9'h0)) == s1_tag</a>
+<a name="213"><span class="lineNum">     213 </span>            :     &amp; ~_resp_invalid_by_write_T_2;</a>
+<a name="214"><span class="lineNum">     214 </span>            :   assign io_resp_bits_ctr =</a>
+<a name="215"><span class="lineNum">     215 </span>            :     (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_ctr : 2'h0)</a>
+<a name="216"><span class="lineNum">     216 </span>            :     | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 2'h0);</a>
+<a name="217"><span class="lineNum">     217 </span>            :   assign io_resp_bits_u = {1'h0, _us_io_rdata_0};</a>
+<a name="218"><span class="lineNum">     218 </span>            :   assign io_resp_bits_target =</a>
+<a name="219"><span class="lineNum">     219 </span>            :     (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_target : 41'h0)</a>
+<a name="220"><span class="lineNum">     220 </span>            :     | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_target : 41'h0);</a>
+<a name="221"><span class="lineNum">     221 </span>            : endmodule</a>
+<a name="222"><span class="lineNum">     222 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/ITTageTable_3.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/ITTageTable_3.sv.func-sort-c.html
new file mode 100644
index 0000000..c9a6a1d
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/ITTageTable_3.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/ITTageTable_3.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - ITTageTable_3.sv<span style="font-size: 80%;"> (<a href="ITTageTable_3.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">44</td>
+            <td class="headerCovTableEntry">44</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="ITTageTable_3.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/ITTageTable_3.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/ITTageTable_3.sv.func.html
new file mode 100644
index 0000000..f30600a
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/ITTageTable_3.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/ITTageTable_3.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - ITTageTable_3.sv<span style="font-size: 80%;"> (<a href="ITTageTable_3.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">44</td>
+            <td class="headerCovTableEntry">44</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="ITTageTable_3.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/ITTageTable_3.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/ITTageTable_3.sv.gcov.html
new file mode 100644
index 0000000..4af36b8
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/ITTageTable_3.sv.gcov.html
@@ -0,0 +1,298 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/ITTageTable_3.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - ITTageTable_3.sv<span style="font-size: 80%;"> (source / <a href="ITTageTable_3.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">44</td>
+            <td class="headerCovTableEntry">44</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : module ITTageTable_3(</a>
+<a name="59"><span class="lineNum">      59 </span><span class="lineCov">     127786 :   input         clock,</span></a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">         62 :   input         reset,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">         73 :   input         io_req_valid,</span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">      35066 :   input  [40:0] io_req_bits_pc,</span></a>
+<a name="63"><span class="lineNum">      63 </span><span class="lineCov">        987 :   input  [8:0]  io_req_bits_folded_hist_hist_6_folded_hist,</span></a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">        811 :   input  [7:0]  io_req_bits_folded_hist_hist_2_folded_hist,</span></a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">         10 :   output        io_resp_valid,</span></a>
+<a name="66"><span class="lineNum">      66 </span><span class="lineCov">         53 :   output [1:0]  io_resp_bits_ctr,</span></a>
+<a name="67"><span class="lineNum">      67 </span><span class="lineCov">        103 :   output [1:0]  io_resp_bits_u,</span></a>
+<a name="68"><span class="lineNum">      68 </span><span class="lineCov">       1103 :   output [40:0] io_resp_bits_target,</span></a>
+<a name="69"><span class="lineNum">      69 </span><span class="lineCov">        591 :   input  [40:0] io_update_pc,</span></a>
+<a name="70"><span class="lineNum">      70 </span><span class="lineCov">        128 :   input  [8:0]  io_update_folded_hist_hist_6_folded_hist,</span></a>
+<a name="71"><span class="lineNum">      71 </span><span class="lineCov">        111 :   input  [7:0]  io_update_folded_hist_hist_2_folded_hist,</span></a>
+<a name="72"><span class="lineNum">      72 </span><span class="lineCov">         26 :   input         io_update_valid,</span></a>
+<a name="73"><span class="lineNum">      73 </span><span class="lineCov">         16 :   input         io_update_correct,</span></a>
+<a name="74"><span class="lineNum">      74 </span><span class="lineCov">         17 :   input         io_update_alloc,</span></a>
+<a name="75"><span class="lineNum">      75 </span><span class="lineCov">         28 :   input  [1:0]  io_update_oldCtr,</span></a>
+<a name="76"><span class="lineNum">      76 </span><span class="lineCov">         15 :   input         io_update_uValid,</span></a>
+<a name="77"><span class="lineNum">      77 </span><span class="lineCov">         13 :   input         io_update_u,</span></a>
+<a name="78"><span class="lineNum">      78 </span><span class="lineCov">         29 :   input         io_update_reset_u,</span></a>
+<a name="79"><span class="lineNum">      79 </span><span class="lineCov">        602 :   input  [40:0] io_update_target,</span></a>
+<a name="80"><span class="lineNum">      80 </span><span class="lineCov">        599 :   input  [40:0] io_update_old_target</span></a>
+<a name="81"><span class="lineNum">      81 </span>            : );</a>
+<a name="82"><span class="lineNum">      82 </span>            : </a>
+<a name="83"><span class="lineNum">      83 </span>            :   wire        _resp_invalid_by_write_T_2;</a>
+<a name="84"><span class="lineNum">      84 </span>            :   wire        _wrbypass_io_hit;</a>
+<a name="85"><span class="lineNum">      85 </span>            :   wire [1:0]  _wrbypass_io_hit_data_0_bits;</a>
+<a name="86"><span class="lineNum">      86 </span>            :   wire        _table_banks_1_io_r_resp_data_0_valid;</a>
+<a name="87"><span class="lineNum">      87 </span>            :   wire [8:0]  _table_banks_1_io_r_resp_data_0_tag;</a>
+<a name="88"><span class="lineNum">      88 </span>            :   wire [1:0]  _table_banks_1_io_r_resp_data_0_ctr;</a>
+<a name="89"><span class="lineNum">      89 </span>            :   wire [40:0] _table_banks_1_io_r_resp_data_0_target;</a>
+<a name="90"><span class="lineNum">      90 </span>            :   wire        _table_banks_0_io_r_resp_data_0_valid;</a>
+<a name="91"><span class="lineNum">      91 </span>            :   wire [8:0]  _table_banks_0_io_r_resp_data_0_tag;</a>
+<a name="92"><span class="lineNum">      92 </span>            :   wire [1:0]  _table_banks_0_io_r_resp_data_0_ctr;</a>
+<a name="93"><span class="lineNum">      93 </span>            :   wire [40:0] _table_banks_0_io_r_resp_data_0_target;</a>
+<a name="94"><span class="lineNum">      94 </span>            :   wire        _us_io_rdata_0;</a>
+<a name="95"><span class="lineNum">      95 </span><span class="lineCov">       8579 :   wire [8:0]  s0_idx = io_req_bits_pc[9:1] ^ io_req_bits_folded_hist_hist_6_folded_hist;</span></a>
+<a name="96"><span class="lineNum">      96 </span><span class="lineCov">        550 :   reg  [8:0]  s1_tag;</span></a>
+<a name="97"><span class="lineNum">      97 </span><span class="lineCov">         49 :   reg         s1_bank_req_1h_0;</span></a>
+<a name="98"><span class="lineNum">      98 </span><span class="lineCov">         51 :   reg         s1_bank_req_1h_1;</span></a>
+<a name="99"><span class="lineNum">      99 </span><span class="lineCov">         16 :   reg         s1_bank_has_write_on_this_req_0;</span></a>
+<a name="100"><span class="lineNum">     100 </span><span class="lineCov">         30 :   reg         s1_bank_has_write_on_this_req_1;</span></a>
+<a name="101"><span class="lineNum">     101 </span><span class="lineCov">        132 :   wire [8:0]  update_idx = io_update_pc[9:1] ^ io_update_folded_hist_hist_6_folded_hist;</span></a>
+<a name="102"><span class="lineNum">     102 </span><span class="lineCov">        128 :   wire [8:0]  update_tag =</span></a>
+<a name="103"><span class="lineNum">     103 </span>            :     io_update_pc[18:10] ^ io_update_folded_hist_hist_6_folded_hist</a>
+<a name="104"><span class="lineNum">     104 </span>            :     ^ {io_update_folded_hist_hist_2_folded_hist, 1'h0};</a>
+<a name="105"><span class="lineNum">     105 </span>            :   assign _resp_invalid_by_write_T_2 =</a>
+<a name="106"><span class="lineNum">     106 </span>            :     s1_bank_req_1h_0 &amp; s1_bank_has_write_on_this_req_0 | s1_bank_req_1h_1</a>
+<a name="107"><span class="lineNum">     107 </span>            :     &amp; s1_bank_has_write_on_this_req_1;</a>
+<a name="108"><span class="lineNum">     108 </span>            :   wire        _s1_bank_has_write_on_this_req_WIRE_0 = io_update_valid &amp; ~(update_idx[0]);</a>
+<a name="109"><span class="lineNum">     109 </span>            :   wire        _s1_bank_has_write_on_this_req_WIRE_1 = io_update_valid &amp; update_idx[0];</a>
+<a name="110"><span class="lineNum">     110 </span><span class="lineCov">         52 :   wire [1:0]  old_ctr =</span></a>
+<a name="111"><span class="lineNum">     111 </span>            :     _wrbypass_io_hit ? _wrbypass_io_hit_data_0_bits : io_update_oldCtr;</a>
+<a name="112"><span class="lineNum">     112 </span><span class="lineCov">         21 :   wire        update_wdata_ctr_oldSatNotTaken = old_ctr == 2'h0;</span></a>
+<a name="113"><span class="lineNum">     113 </span><span class="lineCov">         50 :   wire [1:0]  update_wdata_ctr =</span></a>
+<a name="114"><span class="lineNum">     114 </span>            :     io_update_alloc</a>
+<a name="115"><span class="lineNum">     115 </span>            :       ? 2'h2</a>
+<a name="116"><span class="lineNum">     116 </span>            :       : (&amp;old_ctr) &amp; io_update_correct</a>
+<a name="117"><span class="lineNum">     117 </span>            :           ? 2'h3</a>
+<a name="118"><span class="lineNum">     118 </span>            :           : update_wdata_ctr_oldSatNotTaken &amp; ~io_update_correct</a>
+<a name="119"><span class="lineNum">     119 </span>            :               ? 2'h0</a>
+<a name="120"><span class="lineNum">     120 </span>            :               : io_update_correct ? 2'(old_ctr + 2'h1) : 2'(old_ctr - 2'h1);</a>
+<a name="121"><span class="lineNum">     121 </span><span class="lineCov">        577 :   wire [40:0] update_wdata_target =</span></a>
+<a name="122"><span class="lineNum">     122 </span>            :     io_update_alloc | update_wdata_ctr_oldSatNotTaken</a>
+<a name="123"><span class="lineNum">     123 </span>            :       ? io_update_target</a>
+<a name="124"><span class="lineNum">     124 </span>            :       : io_update_old_target;</a>
+<a name="125"><span class="lineNum">     125 </span><span class="lineCov">     127694 :   always @(posedge clock) begin</span></a>
+<a name="126"><span class="lineNum">     126 </span><span class="lineCov">       8350 :     if (io_req_valid) begin</span></a>
+<a name="127"><span class="lineNum">     127 </span><span class="lineCov">       4175 :       s1_tag &lt;=</span></a>
+<a name="128"><span class="lineNum">     128 </span><span class="lineCov">       4175 :         io_req_bits_pc[18:10] ^ io_req_bits_folded_hist_hist_6_folded_hist</span></a>
+<a name="129"><span class="lineNum">     129 </span><span class="lineCov">       4175 :         ^ {io_req_bits_folded_hist_hist_2_folded_hist, 1'h0};</span></a>
+<a name="130"><span class="lineNum">     130 </span><span class="lineCov">       4175 :       s1_bank_req_1h_0 &lt;= ~(s0_idx[0]);</span></a>
+<a name="131"><span class="lineNum">     131 </span><span class="lineCov">       4175 :       s1_bank_req_1h_1 &lt;= s0_idx[0];</span></a>
+<a name="132"><span class="lineNum">     132 </span><span class="lineCov">       4175 :       s1_bank_has_write_on_this_req_0 &lt;= _s1_bank_has_write_on_this_req_WIRE_0;</span></a>
+<a name="133"><span class="lineNum">     133 </span><span class="lineCov">       4175 :       s1_bank_has_write_on_this_req_1 &lt;= _s1_bank_has_write_on_this_req_WIRE_1;</span></a>
+<a name="134"><span class="lineNum">     134 </span>            :     end</a>
+<a name="135"><span class="lineNum">     135 </span>            :   end // always @(posedge)</a>
+<a name="136"><span class="lineNum">     136 </span>            :   `ifdef ENABLE_INITIAL_REG_</a>
+<a name="137"><span class="lineNum">     137 </span>            :     `ifdef FIRRTL_BEFORE_INITIAL</a>
+<a name="138"><span class="lineNum">     138 </span>            :       `FIRRTL_BEFORE_INITIAL</a>
+<a name="139"><span class="lineNum">     139 </span>            :     `endif // FIRRTL_BEFORE_INITIAL</a>
+<a name="140"><span class="lineNum">     140 </span>            :     logic [31:0] _RANDOM[0:0];</a>
+<a name="141"><span class="lineNum">     141 </span><span class="lineCov">         58 :     initial begin</span></a>
+<a name="142"><span class="lineNum">     142 </span>            :       `ifdef INIT_RANDOM_PROLOG_</a>
+<a name="143"><span class="lineNum">     143 </span>            :         `INIT_RANDOM_PROLOG_</a>
+<a name="144"><span class="lineNum">     144 </span>            :       `endif // INIT_RANDOM_PROLOG_</a>
+<a name="145"><span class="lineNum">     145 </span>            :       `ifdef RANDOMIZE_REG_INIT</a>
+<a name="146"><span class="lineNum">     146 </span>            :         _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;</a>
+<a name="147"><span class="lineNum">     147 </span>            :         s1_tag = _RANDOM[/*Zero width*/ 1'b0][17:9];</a>
+<a name="148"><span class="lineNum">     148 </span>            :         s1_bank_req_1h_0 = _RANDOM[/*Zero width*/ 1'b0][18];</a>
+<a name="149"><span class="lineNum">     149 </span>            :         s1_bank_req_1h_1 = _RANDOM[/*Zero width*/ 1'b0][19];</a>
+<a name="150"><span class="lineNum">     150 </span>            :         s1_bank_has_write_on_this_req_0 = _RANDOM[/*Zero width*/ 1'b0][20];</a>
+<a name="151"><span class="lineNum">     151 </span>            :         s1_bank_has_write_on_this_req_1 = _RANDOM[/*Zero width*/ 1'b0][21];</a>
+<a name="152"><span class="lineNum">     152 </span>            :       `endif // RANDOMIZE_REG_INIT</a>
+<a name="153"><span class="lineNum">     153 </span>            :     end // initial</a>
+<a name="154"><span class="lineNum">     154 </span>            :     `ifdef FIRRTL_AFTER_INITIAL</a>
+<a name="155"><span class="lineNum">     155 </span>            :       `FIRRTL_AFTER_INITIAL</a>
+<a name="156"><span class="lineNum">     156 </span>            :     `endif // FIRRTL_AFTER_INITIAL</a>
+<a name="157"><span class="lineNum">     157 </span>            :   `endif // ENABLE_INITIAL_REG_</a>
+<a name="158"><span class="lineNum">     158 </span>            :   Folded1WDataModuleTemplate_2 us (</a>
+<a name="159"><span class="lineNum">     159 </span>            :     .clock      (clock),</a>
+<a name="160"><span class="lineNum">     160 </span>            :     .reset      (reset),</a>
+<a name="161"><span class="lineNum">     161 </span>            :     .io_ren_0   (io_req_valid),</a>
+<a name="162"><span class="lineNum">     162 </span>            :     .io_raddr_0 (s0_idx),</a>
+<a name="163"><span class="lineNum">     163 </span>            :     .io_rdata_0 (_us_io_rdata_0),</a>
+<a name="164"><span class="lineNum">     164 </span>            :     .io_wen     (io_update_uValid),</a>
+<a name="165"><span class="lineNum">     165 </span>            :     .io_waddr   (update_idx),</a>
+<a name="166"><span class="lineNum">     166 </span>            :     .io_wdata   (io_update_u),</a>
+<a name="167"><span class="lineNum">     167 </span>            :     .io_resetEn (io_update_reset_u)</a>
+<a name="168"><span class="lineNum">     168 </span>            :   );</a>
+<a name="169"><span class="lineNum">     169 </span>            :   FoldedSRAMTemplate_25 table_banks_0 (</a>
+<a name="170"><span class="lineNum">     170 </span>            :     .clock                       (clock),</a>
+<a name="171"><span class="lineNum">     171 </span>            :     .reset                       (reset),</a>
+<a name="172"><span class="lineNum">     172 </span>            :     .io_r_req_valid              (io_req_valid &amp; ~(s0_idx[0])),</a>
+<a name="173"><span class="lineNum">     173 </span>            :     .io_r_req_bits_setIdx        (s0_idx[8:1]),</a>
+<a name="174"><span class="lineNum">     174 </span>            :     .io_r_resp_data_0_valid      (_table_banks_0_io_r_resp_data_0_valid),</a>
+<a name="175"><span class="lineNum">     175 </span>            :     .io_r_resp_data_0_tag        (_table_banks_0_io_r_resp_data_0_tag),</a>
+<a name="176"><span class="lineNum">     176 </span>            :     .io_r_resp_data_0_ctr        (_table_banks_0_io_r_resp_data_0_ctr),</a>
+<a name="177"><span class="lineNum">     177 </span>            :     .io_r_resp_data_0_target     (_table_banks_0_io_r_resp_data_0_target),</a>
+<a name="178"><span class="lineNum">     178 </span>            :     .io_w_req_valid              (_s1_bank_has_write_on_this_req_WIRE_0),</a>
+<a name="179"><span class="lineNum">     179 </span>            :     .io_w_req_bits_setIdx        (update_idx[8:1]),</a>
+<a name="180"><span class="lineNum">     180 </span>            :     .io_w_req_bits_data_0_tag    (update_tag),</a>
+<a name="181"><span class="lineNum">     181 </span>            :     .io_w_req_bits_data_0_ctr    (update_wdata_ctr),</a>
+<a name="182"><span class="lineNum">     182 </span>            :     .io_w_req_bits_data_0_target (update_wdata_target)</a>
+<a name="183"><span class="lineNum">     183 </span>            :   );</a>
+<a name="184"><span class="lineNum">     184 </span>            :   FoldedSRAMTemplate_25 table_banks_1 (</a>
+<a name="185"><span class="lineNum">     185 </span>            :     .clock                       (clock),</a>
+<a name="186"><span class="lineNum">     186 </span>            :     .reset                       (reset),</a>
+<a name="187"><span class="lineNum">     187 </span>            :     .io_r_req_valid              (io_req_valid &amp; s0_idx[0]),</a>
+<a name="188"><span class="lineNum">     188 </span>            :     .io_r_req_bits_setIdx        (s0_idx[8:1]),</a>
+<a name="189"><span class="lineNum">     189 </span>            :     .io_r_resp_data_0_valid      (_table_banks_1_io_r_resp_data_0_valid),</a>
+<a name="190"><span class="lineNum">     190 </span>            :     .io_r_resp_data_0_tag        (_table_banks_1_io_r_resp_data_0_tag),</a>
+<a name="191"><span class="lineNum">     191 </span>            :     .io_r_resp_data_0_ctr        (_table_banks_1_io_r_resp_data_0_ctr),</a>
+<a name="192"><span class="lineNum">     192 </span>            :     .io_r_resp_data_0_target     (_table_banks_1_io_r_resp_data_0_target),</a>
+<a name="193"><span class="lineNum">     193 </span>            :     .io_w_req_valid              (_s1_bank_has_write_on_this_req_WIRE_1),</a>
+<a name="194"><span class="lineNum">     194 </span>            :     .io_w_req_bits_setIdx        (update_idx[8:1]),</a>
+<a name="195"><span class="lineNum">     195 </span>            :     .io_w_req_bits_data_0_tag    (update_tag),</a>
+<a name="196"><span class="lineNum">     196 </span>            :     .io_w_req_bits_data_0_ctr    (update_wdata_ctr),</a>
+<a name="197"><span class="lineNum">     197 </span>            :     .io_w_req_bits_data_0_target (update_wdata_target)</a>
+<a name="198"><span class="lineNum">     198 </span>            :   );</a>
+<a name="199"><span class="lineNum">     199 </span>            :   WrBypass_43 wrbypass (</a>
+<a name="200"><span class="lineNum">     200 </span>            :     .clock              (clock),</a>
+<a name="201"><span class="lineNum">     201 </span>            :     .reset              (reset),</a>
+<a name="202"><span class="lineNum">     202 </span>            :     .io_wen             (io_update_valid),</a>
+<a name="203"><span class="lineNum">     203 </span>            :     .io_write_idx       (update_idx),</a>
+<a name="204"><span class="lineNum">     204 </span>            :     .io_write_data_0    (update_wdata_ctr),</a>
+<a name="205"><span class="lineNum">     205 </span>            :     .io_hit             (_wrbypass_io_hit),</a>
+<a name="206"><span class="lineNum">     206 </span>            :     .io_hit_data_0_bits (_wrbypass_io_hit_data_0_bits)</a>
+<a name="207"><span class="lineNum">     207 </span>            :   );</a>
+<a name="208"><span class="lineNum">     208 </span>            :   assign io_resp_valid =</a>
+<a name="209"><span class="lineNum">     209 </span>            :     (s1_bank_req_1h_0 &amp; _table_banks_0_io_r_resp_data_0_valid | s1_bank_req_1h_1</a>
+<a name="210"><span class="lineNum">     210 </span>            :      &amp; _table_banks_1_io_r_resp_data_0_valid)</a>
+<a name="211"><span class="lineNum">     211 </span>            :     &amp; ((s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_tag : 9'h0)</a>
+<a name="212"><span class="lineNum">     212 </span>            :        | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_tag : 9'h0)) == s1_tag</a>
+<a name="213"><span class="lineNum">     213 </span>            :     &amp; ~_resp_invalid_by_write_T_2;</a>
+<a name="214"><span class="lineNum">     214 </span>            :   assign io_resp_bits_ctr =</a>
+<a name="215"><span class="lineNum">     215 </span>            :     (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_ctr : 2'h0)</a>
+<a name="216"><span class="lineNum">     216 </span>            :     | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 2'h0);</a>
+<a name="217"><span class="lineNum">     217 </span>            :   assign io_resp_bits_u = {1'h0, _us_io_rdata_0};</a>
+<a name="218"><span class="lineNum">     218 </span>            :   assign io_resp_bits_target =</a>
+<a name="219"><span class="lineNum">     219 </span>            :     (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_target : 41'h0)</a>
+<a name="220"><span class="lineNum">     220 </span>            :     | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_target : 41'h0);</a>
+<a name="221"><span class="lineNum">     221 </span>            : endmodule</a>
+<a name="222"><span class="lineNum">     222 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/ITTageTable_4.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/ITTageTable_4.sv.func-sort-c.html
new file mode 100644
index 0000000..66f381e
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/ITTageTable_4.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/ITTageTable_4.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - ITTageTable_4.sv<span style="font-size: 80%;"> (<a href="ITTageTable_4.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">44</td>
+            <td class="headerCovTableEntry">44</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="ITTageTable_4.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/ITTageTable_4.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/ITTageTable_4.sv.func.html
new file mode 100644
index 0000000..77e7ae3
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/ITTageTable_4.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/ITTageTable_4.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - ITTageTable_4.sv<span style="font-size: 80%;"> (<a href="ITTageTable_4.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">44</td>
+            <td class="headerCovTableEntry">44</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="ITTageTable_4.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/ITTageTable_4.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/ITTageTable_4.sv.gcov.html
new file mode 100644
index 0000000..df92faa
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/ITTageTable_4.sv.gcov.html
@@ -0,0 +1,298 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/ITTageTable_4.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - ITTageTable_4.sv<span style="font-size: 80%;"> (source / <a href="ITTageTable_4.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">44</td>
+            <td class="headerCovTableEntry">44</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : module ITTageTable_4(</a>
+<a name="59"><span class="lineNum">      59 </span><span class="lineCov">     127786 :   input         clock,</span></a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">         62 :   input         reset,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">         73 :   input         io_req_valid,</span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">      35066 :   input  [40:0] io_req_bits_pc,</span></a>
+<a name="63"><span class="lineNum">      63 </span><span class="lineCov">        998 :   input  [8:0]  io_req_bits_folded_hist_hist_10_folded_hist,</span></a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">        517 :   input  [7:0]  io_req_bits_folded_hist_hist_3_folded_hist,</span></a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">         16 :   output        io_resp_valid,</span></a>
+<a name="66"><span class="lineNum">      66 </span><span class="lineCov">         56 :   output [1:0]  io_resp_bits_ctr,</span></a>
+<a name="67"><span class="lineNum">      67 </span><span class="lineCov">         52 :   output [1:0]  io_resp_bits_u,</span></a>
+<a name="68"><span class="lineNum">      68 </span><span class="lineCov">       1123 :   output [40:0] io_resp_bits_target,</span></a>
+<a name="69"><span class="lineNum">      69 </span><span class="lineCov">        595 :   input  [40:0] io_update_pc,</span></a>
+<a name="70"><span class="lineNum">      70 </span><span class="lineCov">        127 :   input  [8:0]  io_update_folded_hist_hist_10_folded_hist,</span></a>
+<a name="71"><span class="lineNum">      71 </span><span class="lineCov">        113 :   input  [7:0]  io_update_folded_hist_hist_3_folded_hist,</span></a>
+<a name="72"><span class="lineNum">      72 </span><span class="lineCov">         24 :   input         io_update_valid,</span></a>
+<a name="73"><span class="lineNum">      73 </span><span class="lineCov">         11 :   input         io_update_correct,</span></a>
+<a name="74"><span class="lineNum">      74 </span><span class="lineCov">         16 :   input         io_update_alloc,</span></a>
+<a name="75"><span class="lineNum">      75 </span><span class="lineCov">         28 :   input  [1:0]  io_update_oldCtr,</span></a>
+<a name="76"><span class="lineNum">      76 </span><span class="lineCov">         17 :   input         io_update_uValid,</span></a>
+<a name="77"><span class="lineNum">      77 </span><span class="lineCov">         20 :   input         io_update_u,</span></a>
+<a name="78"><span class="lineNum">      78 </span><span class="lineCov">         27 :   input         io_update_reset_u,</span></a>
+<a name="79"><span class="lineNum">      79 </span><span class="lineCov">        628 :   input  [40:0] io_update_target,</span></a>
+<a name="80"><span class="lineNum">      80 </span><span class="lineCov">        594 :   input  [40:0] io_update_old_target</span></a>
+<a name="81"><span class="lineNum">      81 </span>            : );</a>
+<a name="82"><span class="lineNum">      82 </span>            : </a>
+<a name="83"><span class="lineNum">      83 </span>            :   wire        _resp_invalid_by_write_T_2;</a>
+<a name="84"><span class="lineNum">      84 </span>            :   wire        _wrbypass_io_hit;</a>
+<a name="85"><span class="lineNum">      85 </span>            :   wire [1:0]  _wrbypass_io_hit_data_0_bits;</a>
+<a name="86"><span class="lineNum">      86 </span>            :   wire        _table_banks_1_io_r_resp_data_0_valid;</a>
+<a name="87"><span class="lineNum">      87 </span>            :   wire [8:0]  _table_banks_1_io_r_resp_data_0_tag;</a>
+<a name="88"><span class="lineNum">      88 </span>            :   wire [1:0]  _table_banks_1_io_r_resp_data_0_ctr;</a>
+<a name="89"><span class="lineNum">      89 </span>            :   wire [40:0] _table_banks_1_io_r_resp_data_0_target;</a>
+<a name="90"><span class="lineNum">      90 </span>            :   wire        _table_banks_0_io_r_resp_data_0_valid;</a>
+<a name="91"><span class="lineNum">      91 </span>            :   wire [8:0]  _table_banks_0_io_r_resp_data_0_tag;</a>
+<a name="92"><span class="lineNum">      92 </span>            :   wire [1:0]  _table_banks_0_io_r_resp_data_0_ctr;</a>
+<a name="93"><span class="lineNum">      93 </span>            :   wire [40:0] _table_banks_0_io_r_resp_data_0_target;</a>
+<a name="94"><span class="lineNum">      94 </span>            :   wire        _us_io_rdata_0;</a>
+<a name="95"><span class="lineNum">      95 </span><span class="lineCov">       8597 :   wire [8:0]  s0_idx = io_req_bits_pc[9:1] ^ io_req_bits_folded_hist_hist_10_folded_hist;</span></a>
+<a name="96"><span class="lineNum">      96 </span><span class="lineCov">        534 :   reg  [8:0]  s1_tag;</span></a>
+<a name="97"><span class="lineNum">      97 </span><span class="lineCov">         41 :   reg         s1_bank_req_1h_0;</span></a>
+<a name="98"><span class="lineNum">      98 </span><span class="lineCov">         50 :   reg         s1_bank_req_1h_1;</span></a>
+<a name="99"><span class="lineNum">      99 </span><span class="lineCov">         31 :   reg         s1_bank_has_write_on_this_req_0;</span></a>
+<a name="100"><span class="lineNum">     100 </span><span class="lineCov">         29 :   reg         s1_bank_has_write_on_this_req_1;</span></a>
+<a name="101"><span class="lineNum">     101 </span><span class="lineCov">        125 :   wire [8:0]  update_idx = io_update_pc[9:1] ^ io_update_folded_hist_hist_10_folded_hist;</span></a>
+<a name="102"><span class="lineNum">     102 </span><span class="lineCov">        122 :   wire [8:0]  update_tag =</span></a>
+<a name="103"><span class="lineNum">     103 </span>            :     io_update_pc[18:10] ^ io_update_folded_hist_hist_10_folded_hist</a>
+<a name="104"><span class="lineNum">     104 </span>            :     ^ {io_update_folded_hist_hist_3_folded_hist, 1'h0};</a>
+<a name="105"><span class="lineNum">     105 </span>            :   assign _resp_invalid_by_write_T_2 =</a>
+<a name="106"><span class="lineNum">     106 </span>            :     s1_bank_req_1h_0 &amp; s1_bank_has_write_on_this_req_0 | s1_bank_req_1h_1</a>
+<a name="107"><span class="lineNum">     107 </span>            :     &amp; s1_bank_has_write_on_this_req_1;</a>
+<a name="108"><span class="lineNum">     108 </span>            :   wire        _s1_bank_has_write_on_this_req_WIRE_0 = io_update_valid &amp; ~(update_idx[0]);</a>
+<a name="109"><span class="lineNum">     109 </span>            :   wire        _s1_bank_has_write_on_this_req_WIRE_1 = io_update_valid &amp; update_idx[0];</a>
+<a name="110"><span class="lineNum">     110 </span><span class="lineCov">         38 :   wire [1:0]  old_ctr =</span></a>
+<a name="111"><span class="lineNum">     111 </span>            :     _wrbypass_io_hit ? _wrbypass_io_hit_data_0_bits : io_update_oldCtr;</a>
+<a name="112"><span class="lineNum">     112 </span><span class="lineCov">         18 :   wire        update_wdata_ctr_oldSatNotTaken = old_ctr == 2'h0;</span></a>
+<a name="113"><span class="lineNum">     113 </span><span class="lineCov">         33 :   wire [1:0]  update_wdata_ctr =</span></a>
+<a name="114"><span class="lineNum">     114 </span>            :     io_update_alloc</a>
+<a name="115"><span class="lineNum">     115 </span>            :       ? 2'h2</a>
+<a name="116"><span class="lineNum">     116 </span>            :       : (&amp;old_ctr) &amp; io_update_correct</a>
+<a name="117"><span class="lineNum">     117 </span>            :           ? 2'h3</a>
+<a name="118"><span class="lineNum">     118 </span>            :           : update_wdata_ctr_oldSatNotTaken &amp; ~io_update_correct</a>
+<a name="119"><span class="lineNum">     119 </span>            :               ? 2'h0</a>
+<a name="120"><span class="lineNum">     120 </span>            :               : io_update_correct ? 2'(old_ctr + 2'h1) : 2'(old_ctr - 2'h1);</a>
+<a name="121"><span class="lineNum">     121 </span><span class="lineCov">        607 :   wire [40:0] update_wdata_target =</span></a>
+<a name="122"><span class="lineNum">     122 </span>            :     io_update_alloc | update_wdata_ctr_oldSatNotTaken</a>
+<a name="123"><span class="lineNum">     123 </span>            :       ? io_update_target</a>
+<a name="124"><span class="lineNum">     124 </span>            :       : io_update_old_target;</a>
+<a name="125"><span class="lineNum">     125 </span><span class="lineCov">     127694 :   always @(posedge clock) begin</span></a>
+<a name="126"><span class="lineNum">     126 </span><span class="lineCov">       8350 :     if (io_req_valid) begin</span></a>
+<a name="127"><span class="lineNum">     127 </span><span class="lineCov">       4175 :       s1_tag &lt;=</span></a>
+<a name="128"><span class="lineNum">     128 </span><span class="lineCov">       4175 :         io_req_bits_pc[18:10] ^ io_req_bits_folded_hist_hist_10_folded_hist</span></a>
+<a name="129"><span class="lineNum">     129 </span><span class="lineCov">       4175 :         ^ {io_req_bits_folded_hist_hist_3_folded_hist, 1'h0};</span></a>
+<a name="130"><span class="lineNum">     130 </span><span class="lineCov">       4175 :       s1_bank_req_1h_0 &lt;= ~(s0_idx[0]);</span></a>
+<a name="131"><span class="lineNum">     131 </span><span class="lineCov">       4175 :       s1_bank_req_1h_1 &lt;= s0_idx[0];</span></a>
+<a name="132"><span class="lineNum">     132 </span><span class="lineCov">       4175 :       s1_bank_has_write_on_this_req_0 &lt;= _s1_bank_has_write_on_this_req_WIRE_0;</span></a>
+<a name="133"><span class="lineNum">     133 </span><span class="lineCov">       4175 :       s1_bank_has_write_on_this_req_1 &lt;= _s1_bank_has_write_on_this_req_WIRE_1;</span></a>
+<a name="134"><span class="lineNum">     134 </span>            :     end</a>
+<a name="135"><span class="lineNum">     135 </span>            :   end // always @(posedge)</a>
+<a name="136"><span class="lineNum">     136 </span>            :   `ifdef ENABLE_INITIAL_REG_</a>
+<a name="137"><span class="lineNum">     137 </span>            :     `ifdef FIRRTL_BEFORE_INITIAL</a>
+<a name="138"><span class="lineNum">     138 </span>            :       `FIRRTL_BEFORE_INITIAL</a>
+<a name="139"><span class="lineNum">     139 </span>            :     `endif // FIRRTL_BEFORE_INITIAL</a>
+<a name="140"><span class="lineNum">     140 </span>            :     logic [31:0] _RANDOM[0:0];</a>
+<a name="141"><span class="lineNum">     141 </span><span class="lineCov">         58 :     initial begin</span></a>
+<a name="142"><span class="lineNum">     142 </span>            :       `ifdef INIT_RANDOM_PROLOG_</a>
+<a name="143"><span class="lineNum">     143 </span>            :         `INIT_RANDOM_PROLOG_</a>
+<a name="144"><span class="lineNum">     144 </span>            :       `endif // INIT_RANDOM_PROLOG_</a>
+<a name="145"><span class="lineNum">     145 </span>            :       `ifdef RANDOMIZE_REG_INIT</a>
+<a name="146"><span class="lineNum">     146 </span>            :         _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;</a>
+<a name="147"><span class="lineNum">     147 </span>            :         s1_tag = _RANDOM[/*Zero width*/ 1'b0][17:9];</a>
+<a name="148"><span class="lineNum">     148 </span>            :         s1_bank_req_1h_0 = _RANDOM[/*Zero width*/ 1'b0][18];</a>
+<a name="149"><span class="lineNum">     149 </span>            :         s1_bank_req_1h_1 = _RANDOM[/*Zero width*/ 1'b0][19];</a>
+<a name="150"><span class="lineNum">     150 </span>            :         s1_bank_has_write_on_this_req_0 = _RANDOM[/*Zero width*/ 1'b0][20];</a>
+<a name="151"><span class="lineNum">     151 </span>            :         s1_bank_has_write_on_this_req_1 = _RANDOM[/*Zero width*/ 1'b0][21];</a>
+<a name="152"><span class="lineNum">     152 </span>            :       `endif // RANDOMIZE_REG_INIT</a>
+<a name="153"><span class="lineNum">     153 </span>            :     end // initial</a>
+<a name="154"><span class="lineNum">     154 </span>            :     `ifdef FIRRTL_AFTER_INITIAL</a>
+<a name="155"><span class="lineNum">     155 </span>            :       `FIRRTL_AFTER_INITIAL</a>
+<a name="156"><span class="lineNum">     156 </span>            :     `endif // FIRRTL_AFTER_INITIAL</a>
+<a name="157"><span class="lineNum">     157 </span>            :   `endif // ENABLE_INITIAL_REG_</a>
+<a name="158"><span class="lineNum">     158 </span>            :   Folded1WDataModuleTemplate_2 us (</a>
+<a name="159"><span class="lineNum">     159 </span>            :     .clock      (clock),</a>
+<a name="160"><span class="lineNum">     160 </span>            :     .reset      (reset),</a>
+<a name="161"><span class="lineNum">     161 </span>            :     .io_ren_0   (io_req_valid),</a>
+<a name="162"><span class="lineNum">     162 </span>            :     .io_raddr_0 (s0_idx),</a>
+<a name="163"><span class="lineNum">     163 </span>            :     .io_rdata_0 (_us_io_rdata_0),</a>
+<a name="164"><span class="lineNum">     164 </span>            :     .io_wen     (io_update_uValid),</a>
+<a name="165"><span class="lineNum">     165 </span>            :     .io_waddr   (update_idx),</a>
+<a name="166"><span class="lineNum">     166 </span>            :     .io_wdata   (io_update_u),</a>
+<a name="167"><span class="lineNum">     167 </span>            :     .io_resetEn (io_update_reset_u)</a>
+<a name="168"><span class="lineNum">     168 </span>            :   );</a>
+<a name="169"><span class="lineNum">     169 </span>            :   FoldedSRAMTemplate_25 table_banks_0 (</a>
+<a name="170"><span class="lineNum">     170 </span>            :     .clock                       (clock),</a>
+<a name="171"><span class="lineNum">     171 </span>            :     .reset                       (reset),</a>
+<a name="172"><span class="lineNum">     172 </span>            :     .io_r_req_valid              (io_req_valid &amp; ~(s0_idx[0])),</a>
+<a name="173"><span class="lineNum">     173 </span>            :     .io_r_req_bits_setIdx        (s0_idx[8:1]),</a>
+<a name="174"><span class="lineNum">     174 </span>            :     .io_r_resp_data_0_valid      (_table_banks_0_io_r_resp_data_0_valid),</a>
+<a name="175"><span class="lineNum">     175 </span>            :     .io_r_resp_data_0_tag        (_table_banks_0_io_r_resp_data_0_tag),</a>
+<a name="176"><span class="lineNum">     176 </span>            :     .io_r_resp_data_0_ctr        (_table_banks_0_io_r_resp_data_0_ctr),</a>
+<a name="177"><span class="lineNum">     177 </span>            :     .io_r_resp_data_0_target     (_table_banks_0_io_r_resp_data_0_target),</a>
+<a name="178"><span class="lineNum">     178 </span>            :     .io_w_req_valid              (_s1_bank_has_write_on_this_req_WIRE_0),</a>
+<a name="179"><span class="lineNum">     179 </span>            :     .io_w_req_bits_setIdx        (update_idx[8:1]),</a>
+<a name="180"><span class="lineNum">     180 </span>            :     .io_w_req_bits_data_0_tag    (update_tag),</a>
+<a name="181"><span class="lineNum">     181 </span>            :     .io_w_req_bits_data_0_ctr    (update_wdata_ctr),</a>
+<a name="182"><span class="lineNum">     182 </span>            :     .io_w_req_bits_data_0_target (update_wdata_target)</a>
+<a name="183"><span class="lineNum">     183 </span>            :   );</a>
+<a name="184"><span class="lineNum">     184 </span>            :   FoldedSRAMTemplate_25 table_banks_1 (</a>
+<a name="185"><span class="lineNum">     185 </span>            :     .clock                       (clock),</a>
+<a name="186"><span class="lineNum">     186 </span>            :     .reset                       (reset),</a>
+<a name="187"><span class="lineNum">     187 </span>            :     .io_r_req_valid              (io_req_valid &amp; s0_idx[0]),</a>
+<a name="188"><span class="lineNum">     188 </span>            :     .io_r_req_bits_setIdx        (s0_idx[8:1]),</a>
+<a name="189"><span class="lineNum">     189 </span>            :     .io_r_resp_data_0_valid      (_table_banks_1_io_r_resp_data_0_valid),</a>
+<a name="190"><span class="lineNum">     190 </span>            :     .io_r_resp_data_0_tag        (_table_banks_1_io_r_resp_data_0_tag),</a>
+<a name="191"><span class="lineNum">     191 </span>            :     .io_r_resp_data_0_ctr        (_table_banks_1_io_r_resp_data_0_ctr),</a>
+<a name="192"><span class="lineNum">     192 </span>            :     .io_r_resp_data_0_target     (_table_banks_1_io_r_resp_data_0_target),</a>
+<a name="193"><span class="lineNum">     193 </span>            :     .io_w_req_valid              (_s1_bank_has_write_on_this_req_WIRE_1),</a>
+<a name="194"><span class="lineNum">     194 </span>            :     .io_w_req_bits_setIdx        (update_idx[8:1]),</a>
+<a name="195"><span class="lineNum">     195 </span>            :     .io_w_req_bits_data_0_tag    (update_tag),</a>
+<a name="196"><span class="lineNum">     196 </span>            :     .io_w_req_bits_data_0_ctr    (update_wdata_ctr),</a>
+<a name="197"><span class="lineNum">     197 </span>            :     .io_w_req_bits_data_0_target (update_wdata_target)</a>
+<a name="198"><span class="lineNum">     198 </span>            :   );</a>
+<a name="199"><span class="lineNum">     199 </span>            :   WrBypass_43 wrbypass (</a>
+<a name="200"><span class="lineNum">     200 </span>            :     .clock              (clock),</a>
+<a name="201"><span class="lineNum">     201 </span>            :     .reset              (reset),</a>
+<a name="202"><span class="lineNum">     202 </span>            :     .io_wen             (io_update_valid),</a>
+<a name="203"><span class="lineNum">     203 </span>            :     .io_write_idx       (update_idx),</a>
+<a name="204"><span class="lineNum">     204 </span>            :     .io_write_data_0    (update_wdata_ctr),</a>
+<a name="205"><span class="lineNum">     205 </span>            :     .io_hit             (_wrbypass_io_hit),</a>
+<a name="206"><span class="lineNum">     206 </span>            :     .io_hit_data_0_bits (_wrbypass_io_hit_data_0_bits)</a>
+<a name="207"><span class="lineNum">     207 </span>            :   );</a>
+<a name="208"><span class="lineNum">     208 </span>            :   assign io_resp_valid =</a>
+<a name="209"><span class="lineNum">     209 </span>            :     (s1_bank_req_1h_0 &amp; _table_banks_0_io_r_resp_data_0_valid | s1_bank_req_1h_1</a>
+<a name="210"><span class="lineNum">     210 </span>            :      &amp; _table_banks_1_io_r_resp_data_0_valid)</a>
+<a name="211"><span class="lineNum">     211 </span>            :     &amp; ((s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_tag : 9'h0)</a>
+<a name="212"><span class="lineNum">     212 </span>            :        | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_tag : 9'h0)) == s1_tag</a>
+<a name="213"><span class="lineNum">     213 </span>            :     &amp; ~_resp_invalid_by_write_T_2;</a>
+<a name="214"><span class="lineNum">     214 </span>            :   assign io_resp_bits_ctr =</a>
+<a name="215"><span class="lineNum">     215 </span>            :     (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_ctr : 2'h0)</a>
+<a name="216"><span class="lineNum">     216 </span>            :     | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 2'h0);</a>
+<a name="217"><span class="lineNum">     217 </span>            :   assign io_resp_bits_u = {1'h0, _us_io_rdata_0};</a>
+<a name="218"><span class="lineNum">     218 </span>            :   assign io_resp_bits_target =</a>
+<a name="219"><span class="lineNum">     219 </span>            :     (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_target : 41'h0)</a>
+<a name="220"><span class="lineNum">     220 </span>            :     | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_target : 41'h0);</a>
+<a name="221"><span class="lineNum">     221 </span>            : endmodule</a>
+<a name="222"><span class="lineNum">     222 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/PriorityMuxModule.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/PriorityMuxModule.sv.func-sort-c.html
new file mode 100644
index 0000000..ae34f0f
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/PriorityMuxModule.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/PriorityMuxModule.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - PriorityMuxModule.sv<span style="font-size: 80%;"> (<a href="PriorityMuxModule.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">10</td>
+            <td class="headerCovTableEntry">10</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="PriorityMuxModule.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/PriorityMuxModule.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/PriorityMuxModule.sv.func.html
new file mode 100644
index 0000000..3e58a42
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/PriorityMuxModule.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/PriorityMuxModule.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - PriorityMuxModule.sv<span style="font-size: 80%;"> (<a href="PriorityMuxModule.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">10</td>
+            <td class="headerCovTableEntry">10</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="PriorityMuxModule.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/PriorityMuxModule.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/PriorityMuxModule.sv.gcov.html
new file mode 100644
index 0000000..85e54c4
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/PriorityMuxModule.sv.gcov.html
@@ -0,0 +1,156 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/PriorityMuxModule.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - PriorityMuxModule.sv<span style="font-size: 80%;"> (source / <a href="PriorityMuxModule.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">10</td>
+            <td class="headerCovTableEntry">10</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : module PriorityMuxModule(</a>
+<a name="59"><span class="lineNum">      59 </span><span class="lineCov">         69 :   input         s2_target_sel,</span></a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">      38209 :   input  [40:0] s2_target_src,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">        523 :   input         s1_target_sel,</span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">      39759 :   input  [40:0] s1_target_src,</span></a>
+<a name="63"><span class="lineNum">      63 </span><span class="lineCov">         87 :   input         s3_target_sel,</span></a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">      38523 :   input  [40:0] s3_target_src,</span></a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">         84 :   input         redirect_target_sel,</span></a>
+<a name="66"><span class="lineNum">      66 </span><span class="lineCov">       1178 :   input  [40:0] redirect_target_src,</span></a>
+<a name="67"><span class="lineNum">      67 </span><span class="lineCov">      10063 :   input  [40:0] stallPC_src,</span></a>
+<a name="68"><span class="lineNum">      68 </span><span class="lineCov">      35066 :   output [40:0] out_res</span></a>
+<a name="69"><span class="lineNum">      69 </span>            : );</a>
+<a name="70"><span class="lineNum">      70 </span>            : </a>
+<a name="71"><span class="lineNum">      71 </span>            :   assign out_res =</a>
+<a name="72"><span class="lineNum">      72 </span>            :     s2_target_sel</a>
+<a name="73"><span class="lineNum">      73 </span>            :       ? s2_target_src</a>
+<a name="74"><span class="lineNum">      74 </span>            :       : s1_target_sel</a>
+<a name="75"><span class="lineNum">      75 </span>            :           ? s1_target_src</a>
+<a name="76"><span class="lineNum">      76 </span>            :           : s3_target_sel</a>
+<a name="77"><span class="lineNum">      77 </span>            :               ? s3_target_src</a>
+<a name="78"><span class="lineNum">      78 </span>            :               : redirect_target_sel ? redirect_target_src : stallPC_src;</a>
+<a name="79"><span class="lineNum">      79 </span>            : endmodule</a>
+<a name="80"><span class="lineNum">      80 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/PriorityMuxModule_12.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/PriorityMuxModule_12.sv.func-sort-c.html
new file mode 100644
index 0000000..e3832b4
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/PriorityMuxModule_12.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/PriorityMuxModule_12.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - PriorityMuxModule_12.sv<span style="font-size: 80%;"> (<a href="PriorityMuxModule_12.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">148</td>
+            <td class="headerCovTableEntry">148</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="PriorityMuxModule_12.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/PriorityMuxModule_12.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/PriorityMuxModule_12.sv.func.html
new file mode 100644
index 0000000..10f23e1
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/PriorityMuxModule_12.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/PriorityMuxModule_12.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - PriorityMuxModule_12.sv<span style="font-size: 80%;"> (<a href="PriorityMuxModule_12.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">148</td>
+            <td class="headerCovTableEntry">148</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="PriorityMuxModule_12.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/PriorityMuxModule_12.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/PriorityMuxModule_12.sv.gcov.html
new file mode 100644
index 0000000..78dced9
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/PriorityMuxModule_12.sv.gcov.html
@@ -0,0 +1,526 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/PriorityMuxModule_12.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - PriorityMuxModule_12.sv<span style="font-size: 80%;"> (source / <a href="PriorityMuxModule_12.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">148</td>
+            <td class="headerCovTableEntry">148</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : module PriorityMuxModule_12(</a>
+<a name="59"><span class="lineNum">      59 </span><span class="lineCov">         53 :   input  s2_AFHOB_sel,</span></a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">         82 :   input  s2_AFHOB_src_afhob_5_bits_0,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">         71 :   input  s2_AFHOB_src_afhob_5_bits_1,</span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">         64 :   input  s2_AFHOB_src_afhob_5_bits_2,</span></a>
+<a name="63"><span class="lineNum">      63 </span><span class="lineCov">         74 :   input  s2_AFHOB_src_afhob_5_bits_3,</span></a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">         23 :   input  s2_AFHOB_src_afhob_4_bits_0,</span></a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">         26 :   input  s2_AFHOB_src_afhob_4_bits_1,</span></a>
+<a name="66"><span class="lineNum">      66 </span><span class="lineCov">         73 :   input  s2_AFHOB_src_afhob_4_bits_2,</span></a>
+<a name="67"><span class="lineNum">      67 </span><span class="lineCov">         75 :   input  s2_AFHOB_src_afhob_4_bits_3,</span></a>
+<a name="68"><span class="lineNum">      68 </span><span class="lineCov">         77 :   input  s2_AFHOB_src_afhob_3_bits_0,</span></a>
+<a name="69"><span class="lineNum">      69 </span><span class="lineCov">         77 :   input  s2_AFHOB_src_afhob_3_bits_1,</span></a>
+<a name="70"><span class="lineNum">      70 </span><span class="lineCov">         70 :   input  s2_AFHOB_src_afhob_3_bits_2,</span></a>
+<a name="71"><span class="lineNum">      71 </span><span class="lineCov">         29 :   input  s2_AFHOB_src_afhob_3_bits_3,</span></a>
+<a name="72"><span class="lineNum">      72 </span><span class="lineCov">         90 :   input  s2_AFHOB_src_afhob_2_bits_0,</span></a>
+<a name="73"><span class="lineNum">      73 </span><span class="lineCov">         73 :   input  s2_AFHOB_src_afhob_2_bits_1,</span></a>
+<a name="74"><span class="lineNum">      74 </span><span class="lineCov">         70 :   input  s2_AFHOB_src_afhob_2_bits_2,</span></a>
+<a name="75"><span class="lineNum">      75 </span><span class="lineCov">         77 :   input  s2_AFHOB_src_afhob_2_bits_3,</span></a>
+<a name="76"><span class="lineNum">      76 </span><span class="lineCov">         29 :   input  s2_AFHOB_src_afhob_1_bits_0,</span></a>
+<a name="77"><span class="lineNum">      77 </span><span class="lineCov">         70 :   input  s2_AFHOB_src_afhob_1_bits_1,</span></a>
+<a name="78"><span class="lineNum">      78 </span><span class="lineCov">         63 :   input  s2_AFHOB_src_afhob_1_bits_2,</span></a>
+<a name="79"><span class="lineNum">      79 </span><span class="lineCov">         23 :   input  s2_AFHOB_src_afhob_1_bits_3,</span></a>
+<a name="80"><span class="lineNum">      80 </span><span class="lineCov">         23 :   input  s2_AFHOB_src_afhob_0_bits_0,</span></a>
+<a name="81"><span class="lineNum">      81 </span><span class="lineCov">         66 :   input  s2_AFHOB_src_afhob_0_bits_1,</span></a>
+<a name="82"><span class="lineNum">      82 </span><span class="lineCov">         23 :   input  s2_AFHOB_src_afhob_0_bits_2,</span></a>
+<a name="83"><span class="lineNum">      83 </span><span class="lineCov">         26 :   input  s2_AFHOB_src_afhob_0_bits_3,</span></a>
+<a name="84"><span class="lineNum">      84 </span><span class="lineCov">        382 :   input  s1_AFHOB_sel,</span></a>
+<a name="85"><span class="lineNum">      85 </span><span class="lineCov">         65 :   input  s1_AFHOB_src_afhob_5_bits_0,</span></a>
+<a name="86"><span class="lineNum">      86 </span><span class="lineCov">         69 :   input  s1_AFHOB_src_afhob_5_bits_1,</span></a>
+<a name="87"><span class="lineNum">      87 </span><span class="lineCov">         59 :   input  s1_AFHOB_src_afhob_5_bits_2,</span></a>
+<a name="88"><span class="lineNum">      88 </span><span class="lineCov">         81 :   input  s1_AFHOB_src_afhob_5_bits_3,</span></a>
+<a name="89"><span class="lineNum">      89 </span><span class="lineCov">         18 :   input  s1_AFHOB_src_afhob_4_bits_0,</span></a>
+<a name="90"><span class="lineNum">      90 </span><span class="lineCov">         22 :   input  s1_AFHOB_src_afhob_4_bits_1,</span></a>
+<a name="91"><span class="lineNum">      91 </span><span class="lineCov">         83 :   input  s1_AFHOB_src_afhob_4_bits_2,</span></a>
+<a name="92"><span class="lineNum">      92 </span><span class="lineCov">         67 :   input  s1_AFHOB_src_afhob_4_bits_3,</span></a>
+<a name="93"><span class="lineNum">      93 </span><span class="lineCov">         63 :   input  s1_AFHOB_src_afhob_3_bits_0,</span></a>
+<a name="94"><span class="lineNum">      94 </span><span class="lineCov">         75 :   input  s1_AFHOB_src_afhob_3_bits_1,</span></a>
+<a name="95"><span class="lineNum">      95 </span><span class="lineCov">         63 :   input  s1_AFHOB_src_afhob_3_bits_2,</span></a>
+<a name="96"><span class="lineNum">      96 </span><span class="lineCov">         21 :   input  s1_AFHOB_src_afhob_3_bits_3,</span></a>
+<a name="97"><span class="lineNum">      97 </span><span class="lineCov">         67 :   input  s1_AFHOB_src_afhob_2_bits_0,</span></a>
+<a name="98"><span class="lineNum">      98 </span><span class="lineCov">         69 :   input  s1_AFHOB_src_afhob_2_bits_1,</span></a>
+<a name="99"><span class="lineNum">      99 </span><span class="lineCov">         67 :   input  s1_AFHOB_src_afhob_2_bits_2,</span></a>
+<a name="100"><span class="lineNum">     100 </span><span class="lineCov">         57 :   input  s1_AFHOB_src_afhob_2_bits_3,</span></a>
+<a name="101"><span class="lineNum">     101 </span><span class="lineCov">         21 :   input  s1_AFHOB_src_afhob_1_bits_0,</span></a>
+<a name="102"><span class="lineNum">     102 </span><span class="lineCov">         69 :   input  s1_AFHOB_src_afhob_1_bits_1,</span></a>
+<a name="103"><span class="lineNum">     103 </span><span class="lineCov">         74 :   input  s1_AFHOB_src_afhob_1_bits_2,</span></a>
+<a name="104"><span class="lineNum">     104 </span><span class="lineCov">         21 :   input  s1_AFHOB_src_afhob_1_bits_3,</span></a>
+<a name="105"><span class="lineNum">     105 </span><span class="lineCov">         21 :   input  s1_AFHOB_src_afhob_0_bits_0,</span></a>
+<a name="106"><span class="lineNum">     106 </span><span class="lineCov">         74 :   input  s1_AFHOB_src_afhob_0_bits_1,</span></a>
+<a name="107"><span class="lineNum">     107 </span><span class="lineCov">         18 :   input  s1_AFHOB_src_afhob_0_bits_2,</span></a>
+<a name="108"><span class="lineNum">     108 </span><span class="lineCov">         22 :   input  s1_AFHOB_src_afhob_0_bits_3,</span></a>
+<a name="109"><span class="lineNum">     109 </span><span class="lineCov">         56 :   input  s3_AFHOB_sel,</span></a>
+<a name="110"><span class="lineNum">     110 </span><span class="lineCov">         83 :   input  s3_AFHOB_src_afhob_5_bits_0,</span></a>
+<a name="111"><span class="lineNum">     111 </span><span class="lineCov">         75 :   input  s3_AFHOB_src_afhob_5_bits_1,</span></a>
+<a name="112"><span class="lineNum">     112 </span><span class="lineCov">         75 :   input  s3_AFHOB_src_afhob_5_bits_2,</span></a>
+<a name="113"><span class="lineNum">     113 </span><span class="lineCov">         80 :   input  s3_AFHOB_src_afhob_5_bits_3,</span></a>
+<a name="114"><span class="lineNum">     114 </span><span class="lineCov">         21 :   input  s3_AFHOB_src_afhob_4_bits_0,</span></a>
+<a name="115"><span class="lineNum">     115 </span><span class="lineCov">         22 :   input  s3_AFHOB_src_afhob_4_bits_1,</span></a>
+<a name="116"><span class="lineNum">     116 </span><span class="lineCov">         82 :   input  s3_AFHOB_src_afhob_4_bits_2,</span></a>
+<a name="117"><span class="lineNum">     117 </span><span class="lineCov">         76 :   input  s3_AFHOB_src_afhob_4_bits_3,</span></a>
+<a name="118"><span class="lineNum">     118 </span><span class="lineCov">         76 :   input  s3_AFHOB_src_afhob_3_bits_0,</span></a>
+<a name="119"><span class="lineNum">     119 </span><span class="lineCov">         72 :   input  s3_AFHOB_src_afhob_3_bits_1,</span></a>
+<a name="120"><span class="lineNum">     120 </span><span class="lineCov">         86 :   input  s3_AFHOB_src_afhob_3_bits_2,</span></a>
+<a name="121"><span class="lineNum">     121 </span><span class="lineCov">         30 :   input  s3_AFHOB_src_afhob_3_bits_3,</span></a>
+<a name="122"><span class="lineNum">     122 </span><span class="lineCov">         73 :   input  s3_AFHOB_src_afhob_2_bits_0,</span></a>
+<a name="123"><span class="lineNum">     123 </span><span class="lineCov">         89 :   input  s3_AFHOB_src_afhob_2_bits_1,</span></a>
+<a name="124"><span class="lineNum">     124 </span><span class="lineCov">         79 :   input  s3_AFHOB_src_afhob_2_bits_2,</span></a>
+<a name="125"><span class="lineNum">     125 </span><span class="lineCov">         83 :   input  s3_AFHOB_src_afhob_2_bits_3,</span></a>
+<a name="126"><span class="lineNum">     126 </span><span class="lineCov">         30 :   input  s3_AFHOB_src_afhob_1_bits_0,</span></a>
+<a name="127"><span class="lineNum">     127 </span><span class="lineCov">         89 :   input  s3_AFHOB_src_afhob_1_bits_1,</span></a>
+<a name="128"><span class="lineNum">     128 </span><span class="lineCov">         76 :   input  s3_AFHOB_src_afhob_1_bits_2,</span></a>
+<a name="129"><span class="lineNum">     129 </span><span class="lineCov">         25 :   input  s3_AFHOB_src_afhob_1_bits_3,</span></a>
+<a name="130"><span class="lineNum">     130 </span><span class="lineCov">         25 :   input  s3_AFHOB_src_afhob_0_bits_0,</span></a>
+<a name="131"><span class="lineNum">     131 </span><span class="lineCov">         73 :   input  s3_AFHOB_src_afhob_0_bits_1,</span></a>
+<a name="132"><span class="lineNum">     132 </span><span class="lineCov">         21 :   input  s3_AFHOB_src_afhob_0_bits_2,</span></a>
+<a name="133"><span class="lineNum">     133 </span><span class="lineCov">         22 :   input  s3_AFHOB_src_afhob_0_bits_3,</span></a>
+<a name="134"><span class="lineNum">     134 </span><span class="lineCov">         84 :   input  redirect_AFHOB_sel,</span></a>
+<a name="135"><span class="lineNum">     135 </span><span class="lineCov">         81 :   input  redirect_AFHOB_src_afhob_5_bits_0,</span></a>
+<a name="136"><span class="lineNum">     136 </span><span class="lineCov">         93 :   input  redirect_AFHOB_src_afhob_5_bits_1,</span></a>
+<a name="137"><span class="lineNum">     137 </span><span class="lineCov">         88 :   input  redirect_AFHOB_src_afhob_5_bits_2,</span></a>
+<a name="138"><span class="lineNum">     138 </span><span class="lineCov">         78 :   input  redirect_AFHOB_src_afhob_5_bits_3,</span></a>
+<a name="139"><span class="lineNum">     139 </span><span class="lineCov">         21 :   input  redirect_AFHOB_src_afhob_4_bits_0,</span></a>
+<a name="140"><span class="lineNum">     140 </span><span class="lineCov">         27 :   input  redirect_AFHOB_src_afhob_4_bits_1,</span></a>
+<a name="141"><span class="lineNum">     141 </span><span class="lineCov">         87 :   input  redirect_AFHOB_src_afhob_4_bits_2,</span></a>
+<a name="142"><span class="lineNum">     142 </span><span class="lineCov">         63 :   input  redirect_AFHOB_src_afhob_4_bits_3,</span></a>
+<a name="143"><span class="lineNum">     143 </span><span class="lineCov">         91 :   input  redirect_AFHOB_src_afhob_3_bits_0,</span></a>
+<a name="144"><span class="lineNum">     144 </span><span class="lineCov">         72 :   input  redirect_AFHOB_src_afhob_3_bits_1,</span></a>
+<a name="145"><span class="lineNum">     145 </span><span class="lineCov">         80 :   input  redirect_AFHOB_src_afhob_3_bits_2,</span></a>
+<a name="146"><span class="lineNum">     146 </span><span class="lineCov">         28 :   input  redirect_AFHOB_src_afhob_3_bits_3,</span></a>
+<a name="147"><span class="lineNum">     147 </span><span class="lineCov">         75 :   input  redirect_AFHOB_src_afhob_2_bits_0,</span></a>
+<a name="148"><span class="lineNum">     148 </span><span class="lineCov">         81 :   input  redirect_AFHOB_src_afhob_2_bits_1,</span></a>
+<a name="149"><span class="lineNum">     149 </span><span class="lineCov">         78 :   input  redirect_AFHOB_src_afhob_2_bits_2,</span></a>
+<a name="150"><span class="lineNum">     150 </span><span class="lineCov">         80 :   input  redirect_AFHOB_src_afhob_2_bits_3,</span></a>
+<a name="151"><span class="lineNum">     151 </span><span class="lineCov">         28 :   input  redirect_AFHOB_src_afhob_1_bits_0,</span></a>
+<a name="152"><span class="lineNum">     152 </span><span class="lineCov">         91 :   input  redirect_AFHOB_src_afhob_1_bits_1,</span></a>
+<a name="153"><span class="lineNum">     153 </span><span class="lineCov">         71 :   input  redirect_AFHOB_src_afhob_1_bits_2,</span></a>
+<a name="154"><span class="lineNum">     154 </span><span class="lineCov">         23 :   input  redirect_AFHOB_src_afhob_1_bits_3,</span></a>
+<a name="155"><span class="lineNum">     155 </span><span class="lineCov">         23 :   input  redirect_AFHOB_src_afhob_0_bits_0,</span></a>
+<a name="156"><span class="lineNum">     156 </span><span class="lineCov">         96 :   input  redirect_AFHOB_src_afhob_0_bits_1,</span></a>
+<a name="157"><span class="lineNum">     157 </span><span class="lineCov">         21 :   input  redirect_AFHOB_src_afhob_0_bits_2,</span></a>
+<a name="158"><span class="lineNum">     158 </span><span class="lineCov">         27 :   input  redirect_AFHOB_src_afhob_0_bits_3,</span></a>
+<a name="159"><span class="lineNum">     159 </span><span class="lineCov">         36 :   input  stallAFHOB_src_afhob_5_bits_0,</span></a>
+<a name="160"><span class="lineNum">     160 </span><span class="lineCov">         33 :   input  stallAFHOB_src_afhob_5_bits_1,</span></a>
+<a name="161"><span class="lineNum">     161 </span><span class="lineCov">         25 :   input  stallAFHOB_src_afhob_5_bits_2,</span></a>
+<a name="162"><span class="lineNum">     162 </span><span class="lineCov">         35 :   input  stallAFHOB_src_afhob_5_bits_3,</span></a>
+<a name="163"><span class="lineNum">     163 </span><span class="lineCov">         30 :   input  stallAFHOB_src_afhob_4_bits_0,</span></a>
+<a name="164"><span class="lineNum">     164 </span><span class="lineCov">         35 :   input  stallAFHOB_src_afhob_4_bits_1,</span></a>
+<a name="165"><span class="lineNum">     165 </span><span class="lineCov">         32 :   input  stallAFHOB_src_afhob_4_bits_2,</span></a>
+<a name="166"><span class="lineNum">     166 </span><span class="lineCov">         31 :   input  stallAFHOB_src_afhob_4_bits_3,</span></a>
+<a name="167"><span class="lineNum">     167 </span><span class="lineCov">         23 :   input  stallAFHOB_src_afhob_3_bits_0,</span></a>
+<a name="168"><span class="lineNum">     168 </span><span class="lineCov">         24 :   input  stallAFHOB_src_afhob_3_bits_1,</span></a>
+<a name="169"><span class="lineNum">     169 </span><span class="lineCov">         33 :   input  stallAFHOB_src_afhob_3_bits_2,</span></a>
+<a name="170"><span class="lineNum">     170 </span><span class="lineCov">         31 :   input  stallAFHOB_src_afhob_3_bits_3,</span></a>
+<a name="171"><span class="lineNum">     171 </span><span class="lineCov">         28 :   input  stallAFHOB_src_afhob_2_bits_0,</span></a>
+<a name="172"><span class="lineNum">     172 </span><span class="lineCov">         31 :   input  stallAFHOB_src_afhob_2_bits_1,</span></a>
+<a name="173"><span class="lineNum">     173 </span><span class="lineCov">         26 :   input  stallAFHOB_src_afhob_2_bits_2,</span></a>
+<a name="174"><span class="lineNum">     174 </span><span class="lineCov">         24 :   input  stallAFHOB_src_afhob_2_bits_3,</span></a>
+<a name="175"><span class="lineNum">     175 </span><span class="lineCov">         24 :   input  stallAFHOB_src_afhob_1_bits_0,</span></a>
+<a name="176"><span class="lineNum">     176 </span><span class="lineCov">         28 :   input  stallAFHOB_src_afhob_1_bits_1,</span></a>
+<a name="177"><span class="lineNum">     177 </span><span class="lineCov">         34 :   input  stallAFHOB_src_afhob_1_bits_2,</span></a>
+<a name="178"><span class="lineNum">     178 </span><span class="lineCov">         32 :   input  stallAFHOB_src_afhob_1_bits_3,</span></a>
+<a name="179"><span class="lineNum">     179 </span><span class="lineCov">         32 :   input  stallAFHOB_src_afhob_0_bits_0,</span></a>
+<a name="180"><span class="lineNum">     180 </span><span class="lineCov">         32 :   input  stallAFHOB_src_afhob_0_bits_1,</span></a>
+<a name="181"><span class="lineNum">     181 </span><span class="lineCov">         33 :   input  stallAFHOB_src_afhob_0_bits_2,</span></a>
+<a name="182"><span class="lineNum">     182 </span><span class="lineCov">         29 :   input  stallAFHOB_src_afhob_0_bits_3,</span></a>
+<a name="183"><span class="lineNum">     183 </span><span class="lineCov">         88 :   output out_res_afhob_5_bits_0,</span></a>
+<a name="184"><span class="lineNum">     184 </span><span class="lineCov">         98 :   output out_res_afhob_5_bits_1,</span></a>
+<a name="185"><span class="lineNum">     185 </span><span class="lineCov">         77 :   output out_res_afhob_5_bits_2,</span></a>
+<a name="186"><span class="lineNum">     186 </span><span class="lineCov">         87 :   output out_res_afhob_5_bits_3,</span></a>
+<a name="187"><span class="lineNum">     187 </span><span class="lineCov">         73 :   output out_res_afhob_4_bits_0,</span></a>
+<a name="188"><span class="lineNum">     188 </span><span class="lineCov">         79 :   output out_res_afhob_4_bits_1,</span></a>
+<a name="189"><span class="lineNum">     189 </span><span class="lineCov">         95 :   output out_res_afhob_4_bits_2,</span></a>
+<a name="190"><span class="lineNum">     190 </span><span class="lineCov">         73 :   output out_res_afhob_4_bits_3,</span></a>
+<a name="191"><span class="lineNum">     191 </span><span class="lineCov">        103 :   output out_res_afhob_3_bits_0,</span></a>
+<a name="192"><span class="lineNum">     192 </span><span class="lineCov">         74 :   output out_res_afhob_3_bits_1,</span></a>
+<a name="193"><span class="lineNum">     193 </span><span class="lineCov">         95 :   output out_res_afhob_3_bits_2,</span></a>
+<a name="194"><span class="lineNum">     194 </span><span class="lineCov">         88 :   output out_res_afhob_3_bits_3,</span></a>
+<a name="195"><span class="lineNum">     195 </span><span class="lineCov">         81 :   output out_res_afhob_2_bits_0,</span></a>
+<a name="196"><span class="lineNum">     196 </span><span class="lineCov">         89 :   output out_res_afhob_2_bits_1,</span></a>
+<a name="197"><span class="lineNum">     197 </span><span class="lineCov">         81 :   output out_res_afhob_2_bits_2,</span></a>
+<a name="198"><span class="lineNum">     198 </span><span class="lineCov">         77 :   output out_res_afhob_2_bits_3,</span></a>
+<a name="199"><span class="lineNum">     199 </span><span class="lineCov">         73 :   output out_res_afhob_1_bits_0,</span></a>
+<a name="200"><span class="lineNum">     200 </span><span class="lineCov">         83 :   output out_res_afhob_1_bits_1,</span></a>
+<a name="201"><span class="lineNum">     201 </span><span class="lineCov">         80 :   output out_res_afhob_1_bits_2,</span></a>
+<a name="202"><span class="lineNum">     202 </span><span class="lineCov">         67 :   output out_res_afhob_1_bits_3,</span></a>
+<a name="203"><span class="lineNum">     203 </span><span class="lineCov">         68 :   output out_res_afhob_0_bits_0,</span></a>
+<a name="204"><span class="lineNum">     204 </span><span class="lineCov">         87 :   output out_res_afhob_0_bits_1,</span></a>
+<a name="205"><span class="lineNum">     205 </span><span class="lineCov">         75 :   output out_res_afhob_0_bits_2,</span></a>
+<a name="206"><span class="lineNum">     206 </span><span class="lineCov">         80 :   output out_res_afhob_0_bits_3</span></a>
+<a name="207"><span class="lineNum">     207 </span>            : );</a>
+<a name="208"><span class="lineNum">     208 </span>            : </a>
+<a name="209"><span class="lineNum">     209 </span>            :   assign out_res_afhob_5_bits_0 =</a>
+<a name="210"><span class="lineNum">     210 </span>            :     s2_AFHOB_sel</a>
+<a name="211"><span class="lineNum">     211 </span>            :       ? s2_AFHOB_src_afhob_5_bits_0</a>
+<a name="212"><span class="lineNum">     212 </span>            :       : s1_AFHOB_sel</a>
+<a name="213"><span class="lineNum">     213 </span>            :           ? s1_AFHOB_src_afhob_5_bits_0</a>
+<a name="214"><span class="lineNum">     214 </span>            :           : s3_AFHOB_sel</a>
+<a name="215"><span class="lineNum">     215 </span>            :               ? s3_AFHOB_src_afhob_5_bits_0</a>
+<a name="216"><span class="lineNum">     216 </span>            :               : redirect_AFHOB_sel</a>
+<a name="217"><span class="lineNum">     217 </span>            :                   ? redirect_AFHOB_src_afhob_5_bits_0</a>
+<a name="218"><span class="lineNum">     218 </span>            :                   : stallAFHOB_src_afhob_5_bits_0;</a>
+<a name="219"><span class="lineNum">     219 </span>            :   assign out_res_afhob_5_bits_1 =</a>
+<a name="220"><span class="lineNum">     220 </span>            :     s2_AFHOB_sel</a>
+<a name="221"><span class="lineNum">     221 </span>            :       ? s2_AFHOB_src_afhob_5_bits_1</a>
+<a name="222"><span class="lineNum">     222 </span>            :       : s1_AFHOB_sel</a>
+<a name="223"><span class="lineNum">     223 </span>            :           ? s1_AFHOB_src_afhob_5_bits_1</a>
+<a name="224"><span class="lineNum">     224 </span>            :           : s3_AFHOB_sel</a>
+<a name="225"><span class="lineNum">     225 </span>            :               ? s3_AFHOB_src_afhob_5_bits_1</a>
+<a name="226"><span class="lineNum">     226 </span>            :               : redirect_AFHOB_sel</a>
+<a name="227"><span class="lineNum">     227 </span>            :                   ? redirect_AFHOB_src_afhob_5_bits_1</a>
+<a name="228"><span class="lineNum">     228 </span>            :                   : stallAFHOB_src_afhob_5_bits_1;</a>
+<a name="229"><span class="lineNum">     229 </span>            :   assign out_res_afhob_5_bits_2 =</a>
+<a name="230"><span class="lineNum">     230 </span>            :     s2_AFHOB_sel</a>
+<a name="231"><span class="lineNum">     231 </span>            :       ? s2_AFHOB_src_afhob_5_bits_2</a>
+<a name="232"><span class="lineNum">     232 </span>            :       : s1_AFHOB_sel</a>
+<a name="233"><span class="lineNum">     233 </span>            :           ? s1_AFHOB_src_afhob_5_bits_2</a>
+<a name="234"><span class="lineNum">     234 </span>            :           : s3_AFHOB_sel</a>
+<a name="235"><span class="lineNum">     235 </span>            :               ? s3_AFHOB_src_afhob_5_bits_2</a>
+<a name="236"><span class="lineNum">     236 </span>            :               : redirect_AFHOB_sel</a>
+<a name="237"><span class="lineNum">     237 </span>            :                   ? redirect_AFHOB_src_afhob_5_bits_2</a>
+<a name="238"><span class="lineNum">     238 </span>            :                   : stallAFHOB_src_afhob_5_bits_2;</a>
+<a name="239"><span class="lineNum">     239 </span>            :   assign out_res_afhob_5_bits_3 =</a>
+<a name="240"><span class="lineNum">     240 </span>            :     s2_AFHOB_sel</a>
+<a name="241"><span class="lineNum">     241 </span>            :       ? s2_AFHOB_src_afhob_5_bits_3</a>
+<a name="242"><span class="lineNum">     242 </span>            :       : s1_AFHOB_sel</a>
+<a name="243"><span class="lineNum">     243 </span>            :           ? s1_AFHOB_src_afhob_5_bits_3</a>
+<a name="244"><span class="lineNum">     244 </span>            :           : s3_AFHOB_sel</a>
+<a name="245"><span class="lineNum">     245 </span>            :               ? s3_AFHOB_src_afhob_5_bits_3</a>
+<a name="246"><span class="lineNum">     246 </span>            :               : redirect_AFHOB_sel</a>
+<a name="247"><span class="lineNum">     247 </span>            :                   ? redirect_AFHOB_src_afhob_5_bits_3</a>
+<a name="248"><span class="lineNum">     248 </span>            :                   : stallAFHOB_src_afhob_5_bits_3;</a>
+<a name="249"><span class="lineNum">     249 </span>            :   assign out_res_afhob_4_bits_0 =</a>
+<a name="250"><span class="lineNum">     250 </span>            :     s2_AFHOB_sel</a>
+<a name="251"><span class="lineNum">     251 </span>            :       ? s2_AFHOB_src_afhob_4_bits_0</a>
+<a name="252"><span class="lineNum">     252 </span>            :       : s1_AFHOB_sel</a>
+<a name="253"><span class="lineNum">     253 </span>            :           ? s1_AFHOB_src_afhob_4_bits_0</a>
+<a name="254"><span class="lineNum">     254 </span>            :           : s3_AFHOB_sel</a>
+<a name="255"><span class="lineNum">     255 </span>            :               ? s3_AFHOB_src_afhob_4_bits_0</a>
+<a name="256"><span class="lineNum">     256 </span>            :               : redirect_AFHOB_sel</a>
+<a name="257"><span class="lineNum">     257 </span>            :                   ? redirect_AFHOB_src_afhob_4_bits_0</a>
+<a name="258"><span class="lineNum">     258 </span>            :                   : stallAFHOB_src_afhob_4_bits_0;</a>
+<a name="259"><span class="lineNum">     259 </span>            :   assign out_res_afhob_4_bits_1 =</a>
+<a name="260"><span class="lineNum">     260 </span>            :     s2_AFHOB_sel</a>
+<a name="261"><span class="lineNum">     261 </span>            :       ? s2_AFHOB_src_afhob_4_bits_1</a>
+<a name="262"><span class="lineNum">     262 </span>            :       : s1_AFHOB_sel</a>
+<a name="263"><span class="lineNum">     263 </span>            :           ? s1_AFHOB_src_afhob_4_bits_1</a>
+<a name="264"><span class="lineNum">     264 </span>            :           : s3_AFHOB_sel</a>
+<a name="265"><span class="lineNum">     265 </span>            :               ? s3_AFHOB_src_afhob_4_bits_1</a>
+<a name="266"><span class="lineNum">     266 </span>            :               : redirect_AFHOB_sel</a>
+<a name="267"><span class="lineNum">     267 </span>            :                   ? redirect_AFHOB_src_afhob_4_bits_1</a>
+<a name="268"><span class="lineNum">     268 </span>            :                   : stallAFHOB_src_afhob_4_bits_1;</a>
+<a name="269"><span class="lineNum">     269 </span>            :   assign out_res_afhob_4_bits_2 =</a>
+<a name="270"><span class="lineNum">     270 </span>            :     s2_AFHOB_sel</a>
+<a name="271"><span class="lineNum">     271 </span>            :       ? s2_AFHOB_src_afhob_4_bits_2</a>
+<a name="272"><span class="lineNum">     272 </span>            :       : s1_AFHOB_sel</a>
+<a name="273"><span class="lineNum">     273 </span>            :           ? s1_AFHOB_src_afhob_4_bits_2</a>
+<a name="274"><span class="lineNum">     274 </span>            :           : s3_AFHOB_sel</a>
+<a name="275"><span class="lineNum">     275 </span>            :               ? s3_AFHOB_src_afhob_4_bits_2</a>
+<a name="276"><span class="lineNum">     276 </span>            :               : redirect_AFHOB_sel</a>
+<a name="277"><span class="lineNum">     277 </span>            :                   ? redirect_AFHOB_src_afhob_4_bits_2</a>
+<a name="278"><span class="lineNum">     278 </span>            :                   : stallAFHOB_src_afhob_4_bits_2;</a>
+<a name="279"><span class="lineNum">     279 </span>            :   assign out_res_afhob_4_bits_3 =</a>
+<a name="280"><span class="lineNum">     280 </span>            :     s2_AFHOB_sel</a>
+<a name="281"><span class="lineNum">     281 </span>            :       ? s2_AFHOB_src_afhob_4_bits_3</a>
+<a name="282"><span class="lineNum">     282 </span>            :       : s1_AFHOB_sel</a>
+<a name="283"><span class="lineNum">     283 </span>            :           ? s1_AFHOB_src_afhob_4_bits_3</a>
+<a name="284"><span class="lineNum">     284 </span>            :           : s3_AFHOB_sel</a>
+<a name="285"><span class="lineNum">     285 </span>            :               ? s3_AFHOB_src_afhob_4_bits_3</a>
+<a name="286"><span class="lineNum">     286 </span>            :               : redirect_AFHOB_sel</a>
+<a name="287"><span class="lineNum">     287 </span>            :                   ? redirect_AFHOB_src_afhob_4_bits_3</a>
+<a name="288"><span class="lineNum">     288 </span>            :                   : stallAFHOB_src_afhob_4_bits_3;</a>
+<a name="289"><span class="lineNum">     289 </span>            :   assign out_res_afhob_3_bits_0 =</a>
+<a name="290"><span class="lineNum">     290 </span>            :     s2_AFHOB_sel</a>
+<a name="291"><span class="lineNum">     291 </span>            :       ? s2_AFHOB_src_afhob_3_bits_0</a>
+<a name="292"><span class="lineNum">     292 </span>            :       : s1_AFHOB_sel</a>
+<a name="293"><span class="lineNum">     293 </span>            :           ? s1_AFHOB_src_afhob_3_bits_0</a>
+<a name="294"><span class="lineNum">     294 </span>            :           : s3_AFHOB_sel</a>
+<a name="295"><span class="lineNum">     295 </span>            :               ? s3_AFHOB_src_afhob_3_bits_0</a>
+<a name="296"><span class="lineNum">     296 </span>            :               : redirect_AFHOB_sel</a>
+<a name="297"><span class="lineNum">     297 </span>            :                   ? redirect_AFHOB_src_afhob_3_bits_0</a>
+<a name="298"><span class="lineNum">     298 </span>            :                   : stallAFHOB_src_afhob_3_bits_0;</a>
+<a name="299"><span class="lineNum">     299 </span>            :   assign out_res_afhob_3_bits_1 =</a>
+<a name="300"><span class="lineNum">     300 </span>            :     s2_AFHOB_sel</a>
+<a name="301"><span class="lineNum">     301 </span>            :       ? s2_AFHOB_src_afhob_3_bits_1</a>
+<a name="302"><span class="lineNum">     302 </span>            :       : s1_AFHOB_sel</a>
+<a name="303"><span class="lineNum">     303 </span>            :           ? s1_AFHOB_src_afhob_3_bits_1</a>
+<a name="304"><span class="lineNum">     304 </span>            :           : s3_AFHOB_sel</a>
+<a name="305"><span class="lineNum">     305 </span>            :               ? s3_AFHOB_src_afhob_3_bits_1</a>
+<a name="306"><span class="lineNum">     306 </span>            :               : redirect_AFHOB_sel</a>
+<a name="307"><span class="lineNum">     307 </span>            :                   ? redirect_AFHOB_src_afhob_3_bits_1</a>
+<a name="308"><span class="lineNum">     308 </span>            :                   : stallAFHOB_src_afhob_3_bits_1;</a>
+<a name="309"><span class="lineNum">     309 </span>            :   assign out_res_afhob_3_bits_2 =</a>
+<a name="310"><span class="lineNum">     310 </span>            :     s2_AFHOB_sel</a>
+<a name="311"><span class="lineNum">     311 </span>            :       ? s2_AFHOB_src_afhob_3_bits_2</a>
+<a name="312"><span class="lineNum">     312 </span>            :       : s1_AFHOB_sel</a>
+<a name="313"><span class="lineNum">     313 </span>            :           ? s1_AFHOB_src_afhob_3_bits_2</a>
+<a name="314"><span class="lineNum">     314 </span>            :           : s3_AFHOB_sel</a>
+<a name="315"><span class="lineNum">     315 </span>            :               ? s3_AFHOB_src_afhob_3_bits_2</a>
+<a name="316"><span class="lineNum">     316 </span>            :               : redirect_AFHOB_sel</a>
+<a name="317"><span class="lineNum">     317 </span>            :                   ? redirect_AFHOB_src_afhob_3_bits_2</a>
+<a name="318"><span class="lineNum">     318 </span>            :                   : stallAFHOB_src_afhob_3_bits_2;</a>
+<a name="319"><span class="lineNum">     319 </span>            :   assign out_res_afhob_3_bits_3 =</a>
+<a name="320"><span class="lineNum">     320 </span>            :     s2_AFHOB_sel</a>
+<a name="321"><span class="lineNum">     321 </span>            :       ? s2_AFHOB_src_afhob_3_bits_3</a>
+<a name="322"><span class="lineNum">     322 </span>            :       : s1_AFHOB_sel</a>
+<a name="323"><span class="lineNum">     323 </span>            :           ? s1_AFHOB_src_afhob_3_bits_3</a>
+<a name="324"><span class="lineNum">     324 </span>            :           : s3_AFHOB_sel</a>
+<a name="325"><span class="lineNum">     325 </span>            :               ? s3_AFHOB_src_afhob_3_bits_3</a>
+<a name="326"><span class="lineNum">     326 </span>            :               : redirect_AFHOB_sel</a>
+<a name="327"><span class="lineNum">     327 </span>            :                   ? redirect_AFHOB_src_afhob_3_bits_3</a>
+<a name="328"><span class="lineNum">     328 </span>            :                   : stallAFHOB_src_afhob_3_bits_3;</a>
+<a name="329"><span class="lineNum">     329 </span>            :   assign out_res_afhob_2_bits_0 =</a>
+<a name="330"><span class="lineNum">     330 </span>            :     s2_AFHOB_sel</a>
+<a name="331"><span class="lineNum">     331 </span>            :       ? s2_AFHOB_src_afhob_2_bits_0</a>
+<a name="332"><span class="lineNum">     332 </span>            :       : s1_AFHOB_sel</a>
+<a name="333"><span class="lineNum">     333 </span>            :           ? s1_AFHOB_src_afhob_2_bits_0</a>
+<a name="334"><span class="lineNum">     334 </span>            :           : s3_AFHOB_sel</a>
+<a name="335"><span class="lineNum">     335 </span>            :               ? s3_AFHOB_src_afhob_2_bits_0</a>
+<a name="336"><span class="lineNum">     336 </span>            :               : redirect_AFHOB_sel</a>
+<a name="337"><span class="lineNum">     337 </span>            :                   ? redirect_AFHOB_src_afhob_2_bits_0</a>
+<a name="338"><span class="lineNum">     338 </span>            :                   : stallAFHOB_src_afhob_2_bits_0;</a>
+<a name="339"><span class="lineNum">     339 </span>            :   assign out_res_afhob_2_bits_1 =</a>
+<a name="340"><span class="lineNum">     340 </span>            :     s2_AFHOB_sel</a>
+<a name="341"><span class="lineNum">     341 </span>            :       ? s2_AFHOB_src_afhob_2_bits_1</a>
+<a name="342"><span class="lineNum">     342 </span>            :       : s1_AFHOB_sel</a>
+<a name="343"><span class="lineNum">     343 </span>            :           ? s1_AFHOB_src_afhob_2_bits_1</a>
+<a name="344"><span class="lineNum">     344 </span>            :           : s3_AFHOB_sel</a>
+<a name="345"><span class="lineNum">     345 </span>            :               ? s3_AFHOB_src_afhob_2_bits_1</a>
+<a name="346"><span class="lineNum">     346 </span>            :               : redirect_AFHOB_sel</a>
+<a name="347"><span class="lineNum">     347 </span>            :                   ? redirect_AFHOB_src_afhob_2_bits_1</a>
+<a name="348"><span class="lineNum">     348 </span>            :                   : stallAFHOB_src_afhob_2_bits_1;</a>
+<a name="349"><span class="lineNum">     349 </span>            :   assign out_res_afhob_2_bits_2 =</a>
+<a name="350"><span class="lineNum">     350 </span>            :     s2_AFHOB_sel</a>
+<a name="351"><span class="lineNum">     351 </span>            :       ? s2_AFHOB_src_afhob_2_bits_2</a>
+<a name="352"><span class="lineNum">     352 </span>            :       : s1_AFHOB_sel</a>
+<a name="353"><span class="lineNum">     353 </span>            :           ? s1_AFHOB_src_afhob_2_bits_2</a>
+<a name="354"><span class="lineNum">     354 </span>            :           : s3_AFHOB_sel</a>
+<a name="355"><span class="lineNum">     355 </span>            :               ? s3_AFHOB_src_afhob_2_bits_2</a>
+<a name="356"><span class="lineNum">     356 </span>            :               : redirect_AFHOB_sel</a>
+<a name="357"><span class="lineNum">     357 </span>            :                   ? redirect_AFHOB_src_afhob_2_bits_2</a>
+<a name="358"><span class="lineNum">     358 </span>            :                   : stallAFHOB_src_afhob_2_bits_2;</a>
+<a name="359"><span class="lineNum">     359 </span>            :   assign out_res_afhob_2_bits_3 =</a>
+<a name="360"><span class="lineNum">     360 </span>            :     s2_AFHOB_sel</a>
+<a name="361"><span class="lineNum">     361 </span>            :       ? s2_AFHOB_src_afhob_2_bits_3</a>
+<a name="362"><span class="lineNum">     362 </span>            :       : s1_AFHOB_sel</a>
+<a name="363"><span class="lineNum">     363 </span>            :           ? s1_AFHOB_src_afhob_2_bits_3</a>
+<a name="364"><span class="lineNum">     364 </span>            :           : s3_AFHOB_sel</a>
+<a name="365"><span class="lineNum">     365 </span>            :               ? s3_AFHOB_src_afhob_2_bits_3</a>
+<a name="366"><span class="lineNum">     366 </span>            :               : redirect_AFHOB_sel</a>
+<a name="367"><span class="lineNum">     367 </span>            :                   ? redirect_AFHOB_src_afhob_2_bits_3</a>
+<a name="368"><span class="lineNum">     368 </span>            :                   : stallAFHOB_src_afhob_2_bits_3;</a>
+<a name="369"><span class="lineNum">     369 </span>            :   assign out_res_afhob_1_bits_0 =</a>
+<a name="370"><span class="lineNum">     370 </span>            :     s2_AFHOB_sel</a>
+<a name="371"><span class="lineNum">     371 </span>            :       ? s2_AFHOB_src_afhob_1_bits_0</a>
+<a name="372"><span class="lineNum">     372 </span>            :       : s1_AFHOB_sel</a>
+<a name="373"><span class="lineNum">     373 </span>            :           ? s1_AFHOB_src_afhob_1_bits_0</a>
+<a name="374"><span class="lineNum">     374 </span>            :           : s3_AFHOB_sel</a>
+<a name="375"><span class="lineNum">     375 </span>            :               ? s3_AFHOB_src_afhob_1_bits_0</a>
+<a name="376"><span class="lineNum">     376 </span>            :               : redirect_AFHOB_sel</a>
+<a name="377"><span class="lineNum">     377 </span>            :                   ? redirect_AFHOB_src_afhob_1_bits_0</a>
+<a name="378"><span class="lineNum">     378 </span>            :                   : stallAFHOB_src_afhob_1_bits_0;</a>
+<a name="379"><span class="lineNum">     379 </span>            :   assign out_res_afhob_1_bits_1 =</a>
+<a name="380"><span class="lineNum">     380 </span>            :     s2_AFHOB_sel</a>
+<a name="381"><span class="lineNum">     381 </span>            :       ? s2_AFHOB_src_afhob_1_bits_1</a>
+<a name="382"><span class="lineNum">     382 </span>            :       : s1_AFHOB_sel</a>
+<a name="383"><span class="lineNum">     383 </span>            :           ? s1_AFHOB_src_afhob_1_bits_1</a>
+<a name="384"><span class="lineNum">     384 </span>            :           : s3_AFHOB_sel</a>
+<a name="385"><span class="lineNum">     385 </span>            :               ? s3_AFHOB_src_afhob_1_bits_1</a>
+<a name="386"><span class="lineNum">     386 </span>            :               : redirect_AFHOB_sel</a>
+<a name="387"><span class="lineNum">     387 </span>            :                   ? redirect_AFHOB_src_afhob_1_bits_1</a>
+<a name="388"><span class="lineNum">     388 </span>            :                   : stallAFHOB_src_afhob_1_bits_1;</a>
+<a name="389"><span class="lineNum">     389 </span>            :   assign out_res_afhob_1_bits_2 =</a>
+<a name="390"><span class="lineNum">     390 </span>            :     s2_AFHOB_sel</a>
+<a name="391"><span class="lineNum">     391 </span>            :       ? s2_AFHOB_src_afhob_1_bits_2</a>
+<a name="392"><span class="lineNum">     392 </span>            :       : s1_AFHOB_sel</a>
+<a name="393"><span class="lineNum">     393 </span>            :           ? s1_AFHOB_src_afhob_1_bits_2</a>
+<a name="394"><span class="lineNum">     394 </span>            :           : s3_AFHOB_sel</a>
+<a name="395"><span class="lineNum">     395 </span>            :               ? s3_AFHOB_src_afhob_1_bits_2</a>
+<a name="396"><span class="lineNum">     396 </span>            :               : redirect_AFHOB_sel</a>
+<a name="397"><span class="lineNum">     397 </span>            :                   ? redirect_AFHOB_src_afhob_1_bits_2</a>
+<a name="398"><span class="lineNum">     398 </span>            :                   : stallAFHOB_src_afhob_1_bits_2;</a>
+<a name="399"><span class="lineNum">     399 </span>            :   assign out_res_afhob_1_bits_3 =</a>
+<a name="400"><span class="lineNum">     400 </span>            :     s2_AFHOB_sel</a>
+<a name="401"><span class="lineNum">     401 </span>            :       ? s2_AFHOB_src_afhob_1_bits_3</a>
+<a name="402"><span class="lineNum">     402 </span>            :       : s1_AFHOB_sel</a>
+<a name="403"><span class="lineNum">     403 </span>            :           ? s1_AFHOB_src_afhob_1_bits_3</a>
+<a name="404"><span class="lineNum">     404 </span>            :           : s3_AFHOB_sel</a>
+<a name="405"><span class="lineNum">     405 </span>            :               ? s3_AFHOB_src_afhob_1_bits_3</a>
+<a name="406"><span class="lineNum">     406 </span>            :               : redirect_AFHOB_sel</a>
+<a name="407"><span class="lineNum">     407 </span>            :                   ? redirect_AFHOB_src_afhob_1_bits_3</a>
+<a name="408"><span class="lineNum">     408 </span>            :                   : stallAFHOB_src_afhob_1_bits_3;</a>
+<a name="409"><span class="lineNum">     409 </span>            :   assign out_res_afhob_0_bits_0 =</a>
+<a name="410"><span class="lineNum">     410 </span>            :     s2_AFHOB_sel</a>
+<a name="411"><span class="lineNum">     411 </span>            :       ? s2_AFHOB_src_afhob_0_bits_0</a>
+<a name="412"><span class="lineNum">     412 </span>            :       : s1_AFHOB_sel</a>
+<a name="413"><span class="lineNum">     413 </span>            :           ? s1_AFHOB_src_afhob_0_bits_0</a>
+<a name="414"><span class="lineNum">     414 </span>            :           : s3_AFHOB_sel</a>
+<a name="415"><span class="lineNum">     415 </span>            :               ? s3_AFHOB_src_afhob_0_bits_0</a>
+<a name="416"><span class="lineNum">     416 </span>            :               : redirect_AFHOB_sel</a>
+<a name="417"><span class="lineNum">     417 </span>            :                   ? redirect_AFHOB_src_afhob_0_bits_0</a>
+<a name="418"><span class="lineNum">     418 </span>            :                   : stallAFHOB_src_afhob_0_bits_0;</a>
+<a name="419"><span class="lineNum">     419 </span>            :   assign out_res_afhob_0_bits_1 =</a>
+<a name="420"><span class="lineNum">     420 </span>            :     s2_AFHOB_sel</a>
+<a name="421"><span class="lineNum">     421 </span>            :       ? s2_AFHOB_src_afhob_0_bits_1</a>
+<a name="422"><span class="lineNum">     422 </span>            :       : s1_AFHOB_sel</a>
+<a name="423"><span class="lineNum">     423 </span>            :           ? s1_AFHOB_src_afhob_0_bits_1</a>
+<a name="424"><span class="lineNum">     424 </span>            :           : s3_AFHOB_sel</a>
+<a name="425"><span class="lineNum">     425 </span>            :               ? s3_AFHOB_src_afhob_0_bits_1</a>
+<a name="426"><span class="lineNum">     426 </span>            :               : redirect_AFHOB_sel</a>
+<a name="427"><span class="lineNum">     427 </span>            :                   ? redirect_AFHOB_src_afhob_0_bits_1</a>
+<a name="428"><span class="lineNum">     428 </span>            :                   : stallAFHOB_src_afhob_0_bits_1;</a>
+<a name="429"><span class="lineNum">     429 </span>            :   assign out_res_afhob_0_bits_2 =</a>
+<a name="430"><span class="lineNum">     430 </span>            :     s2_AFHOB_sel</a>
+<a name="431"><span class="lineNum">     431 </span>            :       ? s2_AFHOB_src_afhob_0_bits_2</a>
+<a name="432"><span class="lineNum">     432 </span>            :       : s1_AFHOB_sel</a>
+<a name="433"><span class="lineNum">     433 </span>            :           ? s1_AFHOB_src_afhob_0_bits_2</a>
+<a name="434"><span class="lineNum">     434 </span>            :           : s3_AFHOB_sel</a>
+<a name="435"><span class="lineNum">     435 </span>            :               ? s3_AFHOB_src_afhob_0_bits_2</a>
+<a name="436"><span class="lineNum">     436 </span>            :               : redirect_AFHOB_sel</a>
+<a name="437"><span class="lineNum">     437 </span>            :                   ? redirect_AFHOB_src_afhob_0_bits_2</a>
+<a name="438"><span class="lineNum">     438 </span>            :                   : stallAFHOB_src_afhob_0_bits_2;</a>
+<a name="439"><span class="lineNum">     439 </span>            :   assign out_res_afhob_0_bits_3 =</a>
+<a name="440"><span class="lineNum">     440 </span>            :     s2_AFHOB_sel</a>
+<a name="441"><span class="lineNum">     441 </span>            :       ? s2_AFHOB_src_afhob_0_bits_3</a>
+<a name="442"><span class="lineNum">     442 </span>            :       : s1_AFHOB_sel</a>
+<a name="443"><span class="lineNum">     443 </span>            :           ? s1_AFHOB_src_afhob_0_bits_3</a>
+<a name="444"><span class="lineNum">     444 </span>            :           : s3_AFHOB_sel</a>
+<a name="445"><span class="lineNum">     445 </span>            :               ? s3_AFHOB_src_afhob_0_bits_3</a>
+<a name="446"><span class="lineNum">     446 </span>            :               : redirect_AFHOB_sel</a>
+<a name="447"><span class="lineNum">     447 </span>            :                   ? redirect_AFHOB_src_afhob_0_bits_3</a>
+<a name="448"><span class="lineNum">     448 </span>            :                   : stallAFHOB_src_afhob_0_bits_3;</a>
+<a name="449"><span class="lineNum">     449 </span>            : endmodule</a>
+<a name="450"><span class="lineNum">     450 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/PriorityMuxModule_16.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/PriorityMuxModule_16.sv.func-sort-c.html
new file mode 100644
index 0000000..a899274
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/PriorityMuxModule_16.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/PriorityMuxModule_16.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - PriorityMuxModule_16.sv<span style="font-size: 80%;"> (<a href="PriorityMuxModule_16.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">10</td>
+            <td class="headerCovTableEntry">10</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="PriorityMuxModule_16.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/PriorityMuxModule_16.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/PriorityMuxModule_16.sv.func.html
new file mode 100644
index 0000000..d212dfe
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/PriorityMuxModule_16.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/PriorityMuxModule_16.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - PriorityMuxModule_16.sv<span style="font-size: 80%;"> (<a href="PriorityMuxModule_16.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">10</td>
+            <td class="headerCovTableEntry">10</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="PriorityMuxModule_16.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/PriorityMuxModule_16.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/PriorityMuxModule_16.sv.gcov.html
new file mode 100644
index 0000000..b329ca1
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/PriorityMuxModule_16.sv.gcov.html
@@ -0,0 +1,156 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/PriorityMuxModule_16.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - PriorityMuxModule_16.sv<span style="font-size: 80%;"> (source / <a href="PriorityMuxModule_16.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">10</td>
+            <td class="headerCovTableEntry">10</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : module PriorityMuxModule_16(</a>
+<a name="59"><span class="lineNum">      59 </span><span class="lineCov">         59 :   input        s2_BrNumOH_sel,</span></a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">        175 :   input  [2:0] s2_BrNumOH_src,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">        387 :   input        s1_BrNumOH_sel,</span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">        137 :   input  [2:0] s1_BrNumOH_src,</span></a>
+<a name="63"><span class="lineNum">      63 </span><span class="lineCov">         58 :   input        s3_BrNumOH_sel,</span></a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">        186 :   input  [2:0] s3_BrNumOH_src,</span></a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">        252 :   input        redirect_BrNumOH_sel,</span></a>
+<a name="66"><span class="lineNum">      66 </span><span class="lineCov">        243 :   input  [2:0] redirect_BrNumOH_src,</span></a>
+<a name="67"><span class="lineNum">      67 </span><span class="lineCov">        644 :   input  [2:0] stallBrNumOH_src,</span></a>
+<a name="68"><span class="lineNum">      68 </span><span class="lineCov">        573 :   output [2:0] out_res</span></a>
+<a name="69"><span class="lineNum">      69 </span>            : );</a>
+<a name="70"><span class="lineNum">      70 </span>            : </a>
+<a name="71"><span class="lineNum">      71 </span>            :   assign out_res =</a>
+<a name="72"><span class="lineNum">      72 </span>            :     s2_BrNumOH_sel</a>
+<a name="73"><span class="lineNum">      73 </span>            :       ? s2_BrNumOH_src</a>
+<a name="74"><span class="lineNum">      74 </span>            :       : s1_BrNumOH_sel</a>
+<a name="75"><span class="lineNum">      75 </span>            :           ? s1_BrNumOH_src</a>
+<a name="76"><span class="lineNum">      76 </span>            :           : s3_BrNumOH_sel</a>
+<a name="77"><span class="lineNum">      77 </span>            :               ? s3_BrNumOH_src</a>
+<a name="78"><span class="lineNum">      78 </span>            :               : redirect_BrNumOH_sel ? redirect_BrNumOH_src : stallBrNumOH_src;</a>
+<a name="79"><span class="lineNum">      79 </span>            : endmodule</a>
+<a name="80"><span class="lineNum">      80 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/PriorityMuxModule_20.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/PriorityMuxModule_20.sv.func-sort-c.html
new file mode 100644
index 0000000..665ebd1
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/PriorityMuxModule_20.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/PriorityMuxModule_20.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - PriorityMuxModule_20.sv<span style="font-size: 80%;"> (<a href="PriorityMuxModule_20.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">8</td>
+            <td class="headerCovTableEntry">8</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="PriorityMuxModule_20.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/PriorityMuxModule_20.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/PriorityMuxModule_20.sv.func.html
new file mode 100644
index 0000000..6be5c22
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/PriorityMuxModule_20.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/PriorityMuxModule_20.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - PriorityMuxModule_20.sv<span style="font-size: 80%;"> (<a href="PriorityMuxModule_20.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">8</td>
+            <td class="headerCovTableEntry">8</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="PriorityMuxModule_20.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/PriorityMuxModule_20.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/PriorityMuxModule_20.sv.gcov.html
new file mode 100644
index 0000000..319a6ec
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/PriorityMuxModule_20.sv.gcov.html
@@ -0,0 +1,152 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/PriorityMuxModule_20.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - PriorityMuxModule_20.sv<span style="font-size: 80%;"> (source / <a href="PriorityMuxModule_20.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">8</td>
+            <td class="headerCovTableEntry">8</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : module PriorityMuxModule_20(</a>
+<a name="59"><span class="lineNum">      59 </span><span class="lineCov">       3719 :   input  s2_new_bit_0_sel,</span></a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">       3730 :   input  s2_new_bit_0_src,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">       3742 :   input  s1_new_bit_0_sel,</span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">       3727 :   input  s1_new_bit_0_src,</span></a>
+<a name="63"><span class="lineNum">      63 </span><span class="lineCov">       3749 :   input  s3_new_bit_0_sel,</span></a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">       3843 :   input  s3_new_bit_0_src,</span></a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">       3790 :   input  redirect_new_bit_0_src,</span></a>
+<a name="66"><span class="lineNum">      66 </span><span class="lineCov">       3756 :   output out_res</span></a>
+<a name="67"><span class="lineNum">      67 </span>            : );</a>
+<a name="68"><span class="lineNum">      68 </span>            : </a>
+<a name="69"><span class="lineNum">      69 </span>            :   assign out_res =</a>
+<a name="70"><span class="lineNum">      70 </span>            :     s2_new_bit_0_sel</a>
+<a name="71"><span class="lineNum">      71 </span>            :       ? s2_new_bit_0_src</a>
+<a name="72"><span class="lineNum">      72 </span>            :       : s1_new_bit_0_sel</a>
+<a name="73"><span class="lineNum">      73 </span>            :           ? s1_new_bit_0_src</a>
+<a name="74"><span class="lineNum">      74 </span>            :           : s3_new_bit_0_sel ? s3_new_bit_0_src : redirect_new_bit_0_src;</a>
+<a name="75"><span class="lineNum">      75 </span>            : endmodule</a>
+<a name="76"><span class="lineNum">      76 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/PriorityMuxModule_4.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/PriorityMuxModule_4.sv.func-sort-c.html
new file mode 100644
index 0000000..0d21fdc
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/PriorityMuxModule_4.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/PriorityMuxModule_4.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - PriorityMuxModule_4.sv<span style="font-size: 80%;"> (<a href="PriorityMuxModule_4.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">112</td>
+            <td class="headerCovTableEntry">112</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="PriorityMuxModule_4.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/PriorityMuxModule_4.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/PriorityMuxModule_4.sv.func.html
new file mode 100644
index 0000000..fb20fd2
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/PriorityMuxModule_4.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/PriorityMuxModule_4.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - PriorityMuxModule_4.sv<span style="font-size: 80%;"> (<a href="PriorityMuxModule_4.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">112</td>
+            <td class="headerCovTableEntry">112</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="PriorityMuxModule_4.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/PriorityMuxModule_4.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/PriorityMuxModule_4.sv.gcov.html
new file mode 100644
index 0000000..a5781e8
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/PriorityMuxModule_4.sv.gcov.html
@@ -0,0 +1,430 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/PriorityMuxModule_4.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - PriorityMuxModule_4.sv<span style="font-size: 80%;"> (source / <a href="PriorityMuxModule_4.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">112</td>
+            <td class="headerCovTableEntry">112</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : module PriorityMuxModule_4(</a>
+<a name="59"><span class="lineNum">      59 </span><span class="lineCov">         47 :   input         s2_FGH_sel,</span></a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">       1045 :   input  [10:0] s2_FGH_src_hist_17_folded_hist,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">       1022 :   input  [10:0] s2_FGH_src_hist_16_folded_hist,</span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">        722 :   input  [6:0]  s2_FGH_src_hist_15_folded_hist,</span></a>
+<a name="63"><span class="lineNum">      63 </span><span class="lineCov">        746 :   input  [7:0]  s2_FGH_src_hist_14_folded_hist,</span></a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">        918 :   input  [8:0]  s2_FGH_src_hist_13_folded_hist,</span></a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">        473 :   input  [3:0]  s2_FGH_src_hist_12_folded_hist,</span></a>
+<a name="66"><span class="lineNum">      66 </span><span class="lineCov">        757 :   input  [7:0]  s2_FGH_src_hist_11_folded_hist,</span></a>
+<a name="67"><span class="lineNum">      67 </span><span class="lineCov">        899 :   input  [8:0]  s2_FGH_src_hist_10_folded_hist,</span></a>
+<a name="68"><span class="lineNum">      68 </span><span class="lineCov">        743 :   input  [6:0]  s2_FGH_src_hist_9_folded_hist,</span></a>
+<a name="69"><span class="lineNum">      69 </span><span class="lineCov">        843 :   input  [7:0]  s2_FGH_src_hist_8_folded_hist,</span></a>
+<a name="70"><span class="lineNum">      70 </span><span class="lineCov">        703 :   input  [6:0]  s2_FGH_src_hist_7_folded_hist,</span></a>
+<a name="71"><span class="lineNum">      71 </span><span class="lineCov">        888 :   input  [8:0]  s2_FGH_src_hist_6_folded_hist,</span></a>
+<a name="72"><span class="lineNum">      72 </span><span class="lineCov">        641 :   input  [6:0]  s2_FGH_src_hist_5_folded_hist,</span></a>
+<a name="73"><span class="lineNum">      73 </span><span class="lineCov">        832 :   input  [7:0]  s2_FGH_src_hist_4_folded_hist,</span></a>
+<a name="74"><span class="lineNum">      74 </span><span class="lineCov">        709 :   input  [7:0]  s2_FGH_src_hist_3_folded_hist,</span></a>
+<a name="75"><span class="lineNum">      75 </span><span class="lineCov">        698 :   input  [7:0]  s2_FGH_src_hist_2_folded_hist,</span></a>
+<a name="76"><span class="lineNum">      76 </span><span class="lineCov">        999 :   input  [10:0] s2_FGH_src_hist_1_folded_hist,</span></a>
+<a name="77"><span class="lineNum">      77 </span><span class="lineCov">        772 :   input  [7:0]  s2_FGH_src_hist_0_folded_hist,</span></a>
+<a name="78"><span class="lineNum">      78 </span><span class="lineCov">        380 :   input         s1_FGH_sel,</span></a>
+<a name="79"><span class="lineNum">      79 </span><span class="lineCov">        998 :   input  [10:0] s1_FGH_src_hist_17_folded_hist,</span></a>
+<a name="80"><span class="lineNum">      80 </span><span class="lineCov">        982 :   input  [10:0] s1_FGH_src_hist_16_folded_hist,</span></a>
+<a name="81"><span class="lineNum">      81 </span><span class="lineCov">        707 :   input  [6:0]  s1_FGH_src_hist_15_folded_hist,</span></a>
+<a name="82"><span class="lineNum">      82 </span><span class="lineCov">        709 :   input  [7:0]  s1_FGH_src_hist_14_folded_hist,</span></a>
+<a name="83"><span class="lineNum">      83 </span><span class="lineCov">        840 :   input  [8:0]  s1_FGH_src_hist_13_folded_hist,</span></a>
+<a name="84"><span class="lineNum">      84 </span><span class="lineCov">        425 :   input  [3:0]  s1_FGH_src_hist_12_folded_hist,</span></a>
+<a name="85"><span class="lineNum">      85 </span><span class="lineCov">        691 :   input  [7:0]  s1_FGH_src_hist_11_folded_hist,</span></a>
+<a name="86"><span class="lineNum">      86 </span><span class="lineCov">        833 :   input  [8:0]  s1_FGH_src_hist_10_folded_hist,</span></a>
+<a name="87"><span class="lineNum">      87 </span><span class="lineCov">        710 :   input  [6:0]  s1_FGH_src_hist_9_folded_hist,</span></a>
+<a name="88"><span class="lineNum">      88 </span><span class="lineCov">        791 :   input  [7:0]  s1_FGH_src_hist_8_folded_hist,</span></a>
+<a name="89"><span class="lineNum">      89 </span><span class="lineCov">        683 :   input  [6:0]  s1_FGH_src_hist_7_folded_hist,</span></a>
+<a name="90"><span class="lineNum">      90 </span><span class="lineCov">        824 :   input  [8:0]  s1_FGH_src_hist_6_folded_hist,</span></a>
+<a name="91"><span class="lineNum">      91 </span><span class="lineCov">        607 :   input  [6:0]  s1_FGH_src_hist_5_folded_hist,</span></a>
+<a name="92"><span class="lineNum">      92 </span><span class="lineCov">        789 :   input  [7:0]  s1_FGH_src_hist_4_folded_hist,</span></a>
+<a name="93"><span class="lineNum">      93 </span><span class="lineCov">        670 :   input  [7:0]  s1_FGH_src_hist_3_folded_hist,</span></a>
+<a name="94"><span class="lineNum">      94 </span><span class="lineCov">        637 :   input  [7:0]  s1_FGH_src_hist_2_folded_hist,</span></a>
+<a name="95"><span class="lineNum">      95 </span><span class="lineCov">        924 :   input  [10:0] s1_FGH_src_hist_1_folded_hist,</span></a>
+<a name="96"><span class="lineNum">      96 </span><span class="lineCov">        701 :   input  [7:0]  s1_FGH_src_hist_0_folded_hist,</span></a>
+<a name="97"><span class="lineNum">      97 </span><span class="lineCov">         49 :   input         s3_FGH_sel,</span></a>
+<a name="98"><span class="lineNum">      98 </span><span class="lineCov">       1076 :   input  [10:0] s3_FGH_src_hist_17_folded_hist,</span></a>
+<a name="99"><span class="lineNum">      99 </span><span class="lineCov">       1086 :   input  [10:0] s3_FGH_src_hist_16_folded_hist,</span></a>
+<a name="100"><span class="lineNum">     100 </span><span class="lineCov">        735 :   input  [6:0]  s3_FGH_src_hist_15_folded_hist,</span></a>
+<a name="101"><span class="lineNum">     101 </span><span class="lineCov">        769 :   input  [7:0]  s3_FGH_src_hist_14_folded_hist,</span></a>
+<a name="102"><span class="lineNum">     102 </span><span class="lineCov">        931 :   input  [8:0]  s3_FGH_src_hist_13_folded_hist,</span></a>
+<a name="103"><span class="lineNum">     103 </span><span class="lineCov">        479 :   input  [3:0]  s3_FGH_src_hist_12_folded_hist,</span></a>
+<a name="104"><span class="lineNum">     104 </span><span class="lineCov">        810 :   input  [7:0]  s3_FGH_src_hist_11_folded_hist,</span></a>
+<a name="105"><span class="lineNum">     105 </span><span class="lineCov">        936 :   input  [8:0]  s3_FGH_src_hist_10_folded_hist,</span></a>
+<a name="106"><span class="lineNum">     106 </span><span class="lineCov">        796 :   input  [6:0]  s3_FGH_src_hist_9_folded_hist,</span></a>
+<a name="107"><span class="lineNum">     107 </span><span class="lineCov">        866 :   input  [7:0]  s3_FGH_src_hist_8_folded_hist,</span></a>
+<a name="108"><span class="lineNum">     108 </span><span class="lineCov">        701 :   input  [6:0]  s3_FGH_src_hist_7_folded_hist,</span></a>
+<a name="109"><span class="lineNum">     109 </span><span class="lineCov">        933 :   input  [8:0]  s3_FGH_src_hist_6_folded_hist,</span></a>
+<a name="110"><span class="lineNum">     110 </span><span class="lineCov">        697 :   input  [6:0]  s3_FGH_src_hist_5_folded_hist,</span></a>
+<a name="111"><span class="lineNum">     111 </span><span class="lineCov">        849 :   input  [7:0]  s3_FGH_src_hist_4_folded_hist,</span></a>
+<a name="112"><span class="lineNum">     112 </span><span class="lineCov">        764 :   input  [7:0]  s3_FGH_src_hist_3_folded_hist,</span></a>
+<a name="113"><span class="lineNum">     113 </span><span class="lineCov">        771 :   input  [7:0]  s3_FGH_src_hist_2_folded_hist,</span></a>
+<a name="114"><span class="lineNum">     114 </span><span class="lineCov">       1050 :   input  [10:0] s3_FGH_src_hist_1_folded_hist,</span></a>
+<a name="115"><span class="lineNum">     115 </span><span class="lineCov">        815 :   input  [7:0]  s3_FGH_src_hist_0_folded_hist,</span></a>
+<a name="116"><span class="lineNum">     116 </span><span class="lineCov">         84 :   input         redirect_FGHT_sel,</span></a>
+<a name="117"><span class="lineNum">     117 </span><span class="lineCov">       1047 :   input  [10:0] redirect_FGHT_src_hist_17_folded_hist,</span></a>
+<a name="118"><span class="lineNum">     118 </span><span class="lineCov">       1040 :   input  [10:0] redirect_FGHT_src_hist_16_folded_hist,</span></a>
+<a name="119"><span class="lineNum">     119 </span><span class="lineCov">        723 :   input  [6:0]  redirect_FGHT_src_hist_15_folded_hist,</span></a>
+<a name="120"><span class="lineNum">     120 </span><span class="lineCov">        755 :   input  [7:0]  redirect_FGHT_src_hist_14_folded_hist,</span></a>
+<a name="121"><span class="lineNum">     121 </span><span class="lineCov">        867 :   input  [8:0]  redirect_FGHT_src_hist_13_folded_hist,</span></a>
+<a name="122"><span class="lineNum">     122 </span><span class="lineCov">        369 :   input  [3:0]  redirect_FGHT_src_hist_12_folded_hist,</span></a>
+<a name="123"><span class="lineNum">     123 </span><span class="lineCov">        751 :   input  [7:0]  redirect_FGHT_src_hist_11_folded_hist,</span></a>
+<a name="124"><span class="lineNum">     124 </span><span class="lineCov">        900 :   input  [8:0]  redirect_FGHT_src_hist_10_folded_hist,</span></a>
+<a name="125"><span class="lineNum">     125 </span><span class="lineCov">        692 :   input  [6:0]  redirect_FGHT_src_hist_9_folded_hist,</span></a>
+<a name="126"><span class="lineNum">     126 </span><span class="lineCov">        843 :   input  [7:0]  redirect_FGHT_src_hist_8_folded_hist,</span></a>
+<a name="127"><span class="lineNum">     127 </span><span class="lineCov">        664 :   input  [6:0]  redirect_FGHT_src_hist_7_folded_hist,</span></a>
+<a name="128"><span class="lineNum">     128 </span><span class="lineCov">        897 :   input  [8:0]  redirect_FGHT_src_hist_6_folded_hist,</span></a>
+<a name="129"><span class="lineNum">     129 </span><span class="lineCov">        703 :   input  [6:0]  redirect_FGHT_src_hist_5_folded_hist,</span></a>
+<a name="130"><span class="lineNum">     130 </span><span class="lineCov">        817 :   input  [7:0]  redirect_FGHT_src_hist_4_folded_hist,</span></a>
+<a name="131"><span class="lineNum">     131 </span><span class="lineCov">        716 :   input  [7:0]  redirect_FGHT_src_hist_3_folded_hist,</span></a>
+<a name="132"><span class="lineNum">     132 </span><span class="lineCov">        798 :   input  [7:0]  redirect_FGHT_src_hist_2_folded_hist,</span></a>
+<a name="133"><span class="lineNum">     133 </span><span class="lineCov">        957 :   input  [10:0] redirect_FGHT_src_hist_1_folded_hist,</span></a>
+<a name="134"><span class="lineNum">     134 </span><span class="lineCov">        749 :   input  [7:0]  redirect_FGHT_src_hist_0_folded_hist,</span></a>
+<a name="135"><span class="lineNum">     135 </span><span class="lineCov">        407 :   input  [10:0] stallFGH_src_hist_17_folded_hist,</span></a>
+<a name="136"><span class="lineNum">     136 </span><span class="lineCov">        397 :   input  [10:0] stallFGH_src_hist_16_folded_hist,</span></a>
+<a name="137"><span class="lineNum">     137 </span><span class="lineCov">        292 :   input  [6:0]  stallFGH_src_hist_15_folded_hist,</span></a>
+<a name="138"><span class="lineNum">     138 </span><span class="lineCov">        304 :   input  [7:0]  stallFGH_src_hist_14_folded_hist,</span></a>
+<a name="139"><span class="lineNum">     139 </span><span class="lineCov">        371 :   input  [8:0]  stallFGH_src_hist_13_folded_hist,</span></a>
+<a name="140"><span class="lineNum">     140 </span><span class="lineCov">        173 :   input  [3:0]  stallFGH_src_hist_12_folded_hist,</span></a>
+<a name="141"><span class="lineNum">     141 </span><span class="lineCov">        305 :   input  [7:0]  stallFGH_src_hist_11_folded_hist,</span></a>
+<a name="142"><span class="lineNum">     142 </span><span class="lineCov">        360 :   input  [8:0]  stallFGH_src_hist_10_folded_hist,</span></a>
+<a name="143"><span class="lineNum">     143 </span><span class="lineCov">        300 :   input  [6:0]  stallFGH_src_hist_9_folded_hist,</span></a>
+<a name="144"><span class="lineNum">     144 </span><span class="lineCov">        318 :   input  [7:0]  stallFGH_src_hist_8_folded_hist,</span></a>
+<a name="145"><span class="lineNum">     145 </span><span class="lineCov">        275 :   input  [6:0]  stallFGH_src_hist_7_folded_hist,</span></a>
+<a name="146"><span class="lineNum">     146 </span><span class="lineCov">        364 :   input  [8:0]  stallFGH_src_hist_6_folded_hist,</span></a>
+<a name="147"><span class="lineNum">     147 </span><span class="lineCov">        254 :   input  [6:0]  stallFGH_src_hist_5_folded_hist,</span></a>
+<a name="148"><span class="lineNum">     148 </span><span class="lineCov">        322 :   input  [7:0]  stallFGH_src_hist_4_folded_hist,</span></a>
+<a name="149"><span class="lineNum">     149 </span><span class="lineCov">        289 :   input  [7:0]  stallFGH_src_hist_3_folded_hist,</span></a>
+<a name="150"><span class="lineNum">     150 </span><span class="lineCov">        297 :   input  [7:0]  stallFGH_src_hist_2_folded_hist,</span></a>
+<a name="151"><span class="lineNum">     151 </span><span class="lineCov">        411 :   input  [10:0] stallFGH_src_hist_1_folded_hist,</span></a>
+<a name="152"><span class="lineNum">     152 </span><span class="lineCov">        337 :   input  [7:0]  stallFGH_src_hist_0_folded_hist,</span></a>
+<a name="153"><span class="lineNum">     153 </span><span class="lineCov">       1182 :   output [10:0] out_res_hist_17_folded_hist,</span></a>
+<a name="154"><span class="lineNum">     154 </span><span class="lineCov">       1102 :   output [10:0] out_res_hist_16_folded_hist,</span></a>
+<a name="155"><span class="lineNum">     155 </span><span class="lineCov">        828 :   output [6:0]  out_res_hist_15_folded_hist,</span></a>
+<a name="156"><span class="lineNum">     156 </span><span class="lineCov">        564 :   output [7:0]  out_res_hist_14_folded_hist,</span></a>
+<a name="157"><span class="lineNum">     157 </span><span class="lineCov">        989 :   output [8:0]  out_res_hist_13_folded_hist,</span></a>
+<a name="158"><span class="lineNum">     158 </span><span class="lineCov">        474 :   output [3:0]  out_res_hist_12_folded_hist,</span></a>
+<a name="159"><span class="lineNum">     159 </span><span class="lineCov">        858 :   output [7:0]  out_res_hist_11_folded_hist,</span></a>
+<a name="160"><span class="lineNum">     160 </span><span class="lineCov">        998 :   output [8:0]  out_res_hist_10_folded_hist,</span></a>
+<a name="161"><span class="lineNum">     161 </span><span class="lineCov">        844 :   output [6:0]  out_res_hist_9_folded_hist,</span></a>
+<a name="162"><span class="lineNum">     162 </span><span class="lineCov">        930 :   output [7:0]  out_res_hist_8_folded_hist,</span></a>
+<a name="163"><span class="lineNum">     163 </span><span class="lineCov">        760 :   output [6:0]  out_res_hist_7_folded_hist,</span></a>
+<a name="164"><span class="lineNum">     164 </span><span class="lineCov">        987 :   output [8:0]  out_res_hist_6_folded_hist,</span></a>
+<a name="165"><span class="lineNum">     165 </span><span class="lineCov">        711 :   output [6:0]  out_res_hist_5_folded_hist,</span></a>
+<a name="166"><span class="lineNum">     166 </span><span class="lineCov">        602 :   output [7:0]  out_res_hist_4_folded_hist,</span></a>
+<a name="167"><span class="lineNum">     167 </span><span class="lineCov">        517 :   output [7:0]  out_res_hist_3_folded_hist,</span></a>
+<a name="168"><span class="lineNum">     168 </span><span class="lineCov">        811 :   output [7:0]  out_res_hist_2_folded_hist,</span></a>
+<a name="169"><span class="lineNum">     169 </span><span class="lineCov">       1122 :   output [10:0] out_res_hist_1_folded_hist,</span></a>
+<a name="170"><span class="lineNum">     170 </span><span class="lineCov">        827 :   output [7:0]  out_res_hist_0_folded_hist</span></a>
+<a name="171"><span class="lineNum">     171 </span>            : );</a>
+<a name="172"><span class="lineNum">     172 </span>            : </a>
+<a name="173"><span class="lineNum">     173 </span>            :   assign out_res_hist_17_folded_hist =</a>
+<a name="174"><span class="lineNum">     174 </span>            :     s2_FGH_sel</a>
+<a name="175"><span class="lineNum">     175 </span>            :       ? s2_FGH_src_hist_17_folded_hist</a>
+<a name="176"><span class="lineNum">     176 </span>            :       : s1_FGH_sel</a>
+<a name="177"><span class="lineNum">     177 </span>            :           ? s1_FGH_src_hist_17_folded_hist</a>
+<a name="178"><span class="lineNum">     178 </span>            :           : s3_FGH_sel</a>
+<a name="179"><span class="lineNum">     179 </span>            :               ? s3_FGH_src_hist_17_folded_hist</a>
+<a name="180"><span class="lineNum">     180 </span>            :               : redirect_FGHT_sel</a>
+<a name="181"><span class="lineNum">     181 </span>            :                   ? redirect_FGHT_src_hist_17_folded_hist</a>
+<a name="182"><span class="lineNum">     182 </span>            :                   : stallFGH_src_hist_17_folded_hist;</a>
+<a name="183"><span class="lineNum">     183 </span>            :   assign out_res_hist_16_folded_hist =</a>
+<a name="184"><span class="lineNum">     184 </span>            :     s2_FGH_sel</a>
+<a name="185"><span class="lineNum">     185 </span>            :       ? s2_FGH_src_hist_16_folded_hist</a>
+<a name="186"><span class="lineNum">     186 </span>            :       : s1_FGH_sel</a>
+<a name="187"><span class="lineNum">     187 </span>            :           ? s1_FGH_src_hist_16_folded_hist</a>
+<a name="188"><span class="lineNum">     188 </span>            :           : s3_FGH_sel</a>
+<a name="189"><span class="lineNum">     189 </span>            :               ? s3_FGH_src_hist_16_folded_hist</a>
+<a name="190"><span class="lineNum">     190 </span>            :               : redirect_FGHT_sel</a>
+<a name="191"><span class="lineNum">     191 </span>            :                   ? redirect_FGHT_src_hist_16_folded_hist</a>
+<a name="192"><span class="lineNum">     192 </span>            :                   : stallFGH_src_hist_16_folded_hist;</a>
+<a name="193"><span class="lineNum">     193 </span>            :   assign out_res_hist_15_folded_hist =</a>
+<a name="194"><span class="lineNum">     194 </span>            :     s2_FGH_sel</a>
+<a name="195"><span class="lineNum">     195 </span>            :       ? s2_FGH_src_hist_15_folded_hist</a>
+<a name="196"><span class="lineNum">     196 </span>            :       : s1_FGH_sel</a>
+<a name="197"><span class="lineNum">     197 </span>            :           ? s1_FGH_src_hist_15_folded_hist</a>
+<a name="198"><span class="lineNum">     198 </span>            :           : s3_FGH_sel</a>
+<a name="199"><span class="lineNum">     199 </span>            :               ? s3_FGH_src_hist_15_folded_hist</a>
+<a name="200"><span class="lineNum">     200 </span>            :               : redirect_FGHT_sel</a>
+<a name="201"><span class="lineNum">     201 </span>            :                   ? redirect_FGHT_src_hist_15_folded_hist</a>
+<a name="202"><span class="lineNum">     202 </span>            :                   : stallFGH_src_hist_15_folded_hist;</a>
+<a name="203"><span class="lineNum">     203 </span>            :   assign out_res_hist_14_folded_hist =</a>
+<a name="204"><span class="lineNum">     204 </span>            :     s2_FGH_sel</a>
+<a name="205"><span class="lineNum">     205 </span>            :       ? s2_FGH_src_hist_14_folded_hist</a>
+<a name="206"><span class="lineNum">     206 </span>            :       : s1_FGH_sel</a>
+<a name="207"><span class="lineNum">     207 </span>            :           ? s1_FGH_src_hist_14_folded_hist</a>
+<a name="208"><span class="lineNum">     208 </span>            :           : s3_FGH_sel</a>
+<a name="209"><span class="lineNum">     209 </span>            :               ? s3_FGH_src_hist_14_folded_hist</a>
+<a name="210"><span class="lineNum">     210 </span>            :               : redirect_FGHT_sel</a>
+<a name="211"><span class="lineNum">     211 </span>            :                   ? redirect_FGHT_src_hist_14_folded_hist</a>
+<a name="212"><span class="lineNum">     212 </span>            :                   : stallFGH_src_hist_14_folded_hist;</a>
+<a name="213"><span class="lineNum">     213 </span>            :   assign out_res_hist_13_folded_hist =</a>
+<a name="214"><span class="lineNum">     214 </span>            :     s2_FGH_sel</a>
+<a name="215"><span class="lineNum">     215 </span>            :       ? s2_FGH_src_hist_13_folded_hist</a>
+<a name="216"><span class="lineNum">     216 </span>            :       : s1_FGH_sel</a>
+<a name="217"><span class="lineNum">     217 </span>            :           ? s1_FGH_src_hist_13_folded_hist</a>
+<a name="218"><span class="lineNum">     218 </span>            :           : s3_FGH_sel</a>
+<a name="219"><span class="lineNum">     219 </span>            :               ? s3_FGH_src_hist_13_folded_hist</a>
+<a name="220"><span class="lineNum">     220 </span>            :               : redirect_FGHT_sel</a>
+<a name="221"><span class="lineNum">     221 </span>            :                   ? redirect_FGHT_src_hist_13_folded_hist</a>
+<a name="222"><span class="lineNum">     222 </span>            :                   : stallFGH_src_hist_13_folded_hist;</a>
+<a name="223"><span class="lineNum">     223 </span>            :   assign out_res_hist_12_folded_hist =</a>
+<a name="224"><span class="lineNum">     224 </span>            :     s2_FGH_sel</a>
+<a name="225"><span class="lineNum">     225 </span>            :       ? s2_FGH_src_hist_12_folded_hist</a>
+<a name="226"><span class="lineNum">     226 </span>            :       : s1_FGH_sel</a>
+<a name="227"><span class="lineNum">     227 </span>            :           ? s1_FGH_src_hist_12_folded_hist</a>
+<a name="228"><span class="lineNum">     228 </span>            :           : s3_FGH_sel</a>
+<a name="229"><span class="lineNum">     229 </span>            :               ? s3_FGH_src_hist_12_folded_hist</a>
+<a name="230"><span class="lineNum">     230 </span>            :               : redirect_FGHT_sel</a>
+<a name="231"><span class="lineNum">     231 </span>            :                   ? redirect_FGHT_src_hist_12_folded_hist</a>
+<a name="232"><span class="lineNum">     232 </span>            :                   : stallFGH_src_hist_12_folded_hist;</a>
+<a name="233"><span class="lineNum">     233 </span>            :   assign out_res_hist_11_folded_hist =</a>
+<a name="234"><span class="lineNum">     234 </span>            :     s2_FGH_sel</a>
+<a name="235"><span class="lineNum">     235 </span>            :       ? s2_FGH_src_hist_11_folded_hist</a>
+<a name="236"><span class="lineNum">     236 </span>            :       : s1_FGH_sel</a>
+<a name="237"><span class="lineNum">     237 </span>            :           ? s1_FGH_src_hist_11_folded_hist</a>
+<a name="238"><span class="lineNum">     238 </span>            :           : s3_FGH_sel</a>
+<a name="239"><span class="lineNum">     239 </span>            :               ? s3_FGH_src_hist_11_folded_hist</a>
+<a name="240"><span class="lineNum">     240 </span>            :               : redirect_FGHT_sel</a>
+<a name="241"><span class="lineNum">     241 </span>            :                   ? redirect_FGHT_src_hist_11_folded_hist</a>
+<a name="242"><span class="lineNum">     242 </span>            :                   : stallFGH_src_hist_11_folded_hist;</a>
+<a name="243"><span class="lineNum">     243 </span>            :   assign out_res_hist_10_folded_hist =</a>
+<a name="244"><span class="lineNum">     244 </span>            :     s2_FGH_sel</a>
+<a name="245"><span class="lineNum">     245 </span>            :       ? s2_FGH_src_hist_10_folded_hist</a>
+<a name="246"><span class="lineNum">     246 </span>            :       : s1_FGH_sel</a>
+<a name="247"><span class="lineNum">     247 </span>            :           ? s1_FGH_src_hist_10_folded_hist</a>
+<a name="248"><span class="lineNum">     248 </span>            :           : s3_FGH_sel</a>
+<a name="249"><span class="lineNum">     249 </span>            :               ? s3_FGH_src_hist_10_folded_hist</a>
+<a name="250"><span class="lineNum">     250 </span>            :               : redirect_FGHT_sel</a>
+<a name="251"><span class="lineNum">     251 </span>            :                   ? redirect_FGHT_src_hist_10_folded_hist</a>
+<a name="252"><span class="lineNum">     252 </span>            :                   : stallFGH_src_hist_10_folded_hist;</a>
+<a name="253"><span class="lineNum">     253 </span>            :   assign out_res_hist_9_folded_hist =</a>
+<a name="254"><span class="lineNum">     254 </span>            :     s2_FGH_sel</a>
+<a name="255"><span class="lineNum">     255 </span>            :       ? s2_FGH_src_hist_9_folded_hist</a>
+<a name="256"><span class="lineNum">     256 </span>            :       : s1_FGH_sel</a>
+<a name="257"><span class="lineNum">     257 </span>            :           ? s1_FGH_src_hist_9_folded_hist</a>
+<a name="258"><span class="lineNum">     258 </span>            :           : s3_FGH_sel</a>
+<a name="259"><span class="lineNum">     259 </span>            :               ? s3_FGH_src_hist_9_folded_hist</a>
+<a name="260"><span class="lineNum">     260 </span>            :               : redirect_FGHT_sel</a>
+<a name="261"><span class="lineNum">     261 </span>            :                   ? redirect_FGHT_src_hist_9_folded_hist</a>
+<a name="262"><span class="lineNum">     262 </span>            :                   : stallFGH_src_hist_9_folded_hist;</a>
+<a name="263"><span class="lineNum">     263 </span>            :   assign out_res_hist_8_folded_hist =</a>
+<a name="264"><span class="lineNum">     264 </span>            :     s2_FGH_sel</a>
+<a name="265"><span class="lineNum">     265 </span>            :       ? s2_FGH_src_hist_8_folded_hist</a>
+<a name="266"><span class="lineNum">     266 </span>            :       : s1_FGH_sel</a>
+<a name="267"><span class="lineNum">     267 </span>            :           ? s1_FGH_src_hist_8_folded_hist</a>
+<a name="268"><span class="lineNum">     268 </span>            :           : s3_FGH_sel</a>
+<a name="269"><span class="lineNum">     269 </span>            :               ? s3_FGH_src_hist_8_folded_hist</a>
+<a name="270"><span class="lineNum">     270 </span>            :               : redirect_FGHT_sel</a>
+<a name="271"><span class="lineNum">     271 </span>            :                   ? redirect_FGHT_src_hist_8_folded_hist</a>
+<a name="272"><span class="lineNum">     272 </span>            :                   : stallFGH_src_hist_8_folded_hist;</a>
+<a name="273"><span class="lineNum">     273 </span>            :   assign out_res_hist_7_folded_hist =</a>
+<a name="274"><span class="lineNum">     274 </span>            :     s2_FGH_sel</a>
+<a name="275"><span class="lineNum">     275 </span>            :       ? s2_FGH_src_hist_7_folded_hist</a>
+<a name="276"><span class="lineNum">     276 </span>            :       : s1_FGH_sel</a>
+<a name="277"><span class="lineNum">     277 </span>            :           ? s1_FGH_src_hist_7_folded_hist</a>
+<a name="278"><span class="lineNum">     278 </span>            :           : s3_FGH_sel</a>
+<a name="279"><span class="lineNum">     279 </span>            :               ? s3_FGH_src_hist_7_folded_hist</a>
+<a name="280"><span class="lineNum">     280 </span>            :               : redirect_FGHT_sel</a>
+<a name="281"><span class="lineNum">     281 </span>            :                   ? redirect_FGHT_src_hist_7_folded_hist</a>
+<a name="282"><span class="lineNum">     282 </span>            :                   : stallFGH_src_hist_7_folded_hist;</a>
+<a name="283"><span class="lineNum">     283 </span>            :   assign out_res_hist_6_folded_hist =</a>
+<a name="284"><span class="lineNum">     284 </span>            :     s2_FGH_sel</a>
+<a name="285"><span class="lineNum">     285 </span>            :       ? s2_FGH_src_hist_6_folded_hist</a>
+<a name="286"><span class="lineNum">     286 </span>            :       : s1_FGH_sel</a>
+<a name="287"><span class="lineNum">     287 </span>            :           ? s1_FGH_src_hist_6_folded_hist</a>
+<a name="288"><span class="lineNum">     288 </span>            :           : s3_FGH_sel</a>
+<a name="289"><span class="lineNum">     289 </span>            :               ? s3_FGH_src_hist_6_folded_hist</a>
+<a name="290"><span class="lineNum">     290 </span>            :               : redirect_FGHT_sel</a>
+<a name="291"><span class="lineNum">     291 </span>            :                   ? redirect_FGHT_src_hist_6_folded_hist</a>
+<a name="292"><span class="lineNum">     292 </span>            :                   : stallFGH_src_hist_6_folded_hist;</a>
+<a name="293"><span class="lineNum">     293 </span>            :   assign out_res_hist_5_folded_hist =</a>
+<a name="294"><span class="lineNum">     294 </span>            :     s2_FGH_sel</a>
+<a name="295"><span class="lineNum">     295 </span>            :       ? s2_FGH_src_hist_5_folded_hist</a>
+<a name="296"><span class="lineNum">     296 </span>            :       : s1_FGH_sel</a>
+<a name="297"><span class="lineNum">     297 </span>            :           ? s1_FGH_src_hist_5_folded_hist</a>
+<a name="298"><span class="lineNum">     298 </span>            :           : s3_FGH_sel</a>
+<a name="299"><span class="lineNum">     299 </span>            :               ? s3_FGH_src_hist_5_folded_hist</a>
+<a name="300"><span class="lineNum">     300 </span>            :               : redirect_FGHT_sel</a>
+<a name="301"><span class="lineNum">     301 </span>            :                   ? redirect_FGHT_src_hist_5_folded_hist</a>
+<a name="302"><span class="lineNum">     302 </span>            :                   : stallFGH_src_hist_5_folded_hist;</a>
+<a name="303"><span class="lineNum">     303 </span>            :   assign out_res_hist_4_folded_hist =</a>
+<a name="304"><span class="lineNum">     304 </span>            :     s2_FGH_sel</a>
+<a name="305"><span class="lineNum">     305 </span>            :       ? s2_FGH_src_hist_4_folded_hist</a>
+<a name="306"><span class="lineNum">     306 </span>            :       : s1_FGH_sel</a>
+<a name="307"><span class="lineNum">     307 </span>            :           ? s1_FGH_src_hist_4_folded_hist</a>
+<a name="308"><span class="lineNum">     308 </span>            :           : s3_FGH_sel</a>
+<a name="309"><span class="lineNum">     309 </span>            :               ? s3_FGH_src_hist_4_folded_hist</a>
+<a name="310"><span class="lineNum">     310 </span>            :               : redirect_FGHT_sel</a>
+<a name="311"><span class="lineNum">     311 </span>            :                   ? redirect_FGHT_src_hist_4_folded_hist</a>
+<a name="312"><span class="lineNum">     312 </span>            :                   : stallFGH_src_hist_4_folded_hist;</a>
+<a name="313"><span class="lineNum">     313 </span>            :   assign out_res_hist_3_folded_hist =</a>
+<a name="314"><span class="lineNum">     314 </span>            :     s2_FGH_sel</a>
+<a name="315"><span class="lineNum">     315 </span>            :       ? s2_FGH_src_hist_3_folded_hist</a>
+<a name="316"><span class="lineNum">     316 </span>            :       : s1_FGH_sel</a>
+<a name="317"><span class="lineNum">     317 </span>            :           ? s1_FGH_src_hist_3_folded_hist</a>
+<a name="318"><span class="lineNum">     318 </span>            :           : s3_FGH_sel</a>
+<a name="319"><span class="lineNum">     319 </span>            :               ? s3_FGH_src_hist_3_folded_hist</a>
+<a name="320"><span class="lineNum">     320 </span>            :               : redirect_FGHT_sel</a>
+<a name="321"><span class="lineNum">     321 </span>            :                   ? redirect_FGHT_src_hist_3_folded_hist</a>
+<a name="322"><span class="lineNum">     322 </span>            :                   : stallFGH_src_hist_3_folded_hist;</a>
+<a name="323"><span class="lineNum">     323 </span>            :   assign out_res_hist_2_folded_hist =</a>
+<a name="324"><span class="lineNum">     324 </span>            :     s2_FGH_sel</a>
+<a name="325"><span class="lineNum">     325 </span>            :       ? s2_FGH_src_hist_2_folded_hist</a>
+<a name="326"><span class="lineNum">     326 </span>            :       : s1_FGH_sel</a>
+<a name="327"><span class="lineNum">     327 </span>            :           ? s1_FGH_src_hist_2_folded_hist</a>
+<a name="328"><span class="lineNum">     328 </span>            :           : s3_FGH_sel</a>
+<a name="329"><span class="lineNum">     329 </span>            :               ? s3_FGH_src_hist_2_folded_hist</a>
+<a name="330"><span class="lineNum">     330 </span>            :               : redirect_FGHT_sel</a>
+<a name="331"><span class="lineNum">     331 </span>            :                   ? redirect_FGHT_src_hist_2_folded_hist</a>
+<a name="332"><span class="lineNum">     332 </span>            :                   : stallFGH_src_hist_2_folded_hist;</a>
+<a name="333"><span class="lineNum">     333 </span>            :   assign out_res_hist_1_folded_hist =</a>
+<a name="334"><span class="lineNum">     334 </span>            :     s2_FGH_sel</a>
+<a name="335"><span class="lineNum">     335 </span>            :       ? s2_FGH_src_hist_1_folded_hist</a>
+<a name="336"><span class="lineNum">     336 </span>            :       : s1_FGH_sel</a>
+<a name="337"><span class="lineNum">     337 </span>            :           ? s1_FGH_src_hist_1_folded_hist</a>
+<a name="338"><span class="lineNum">     338 </span>            :           : s3_FGH_sel</a>
+<a name="339"><span class="lineNum">     339 </span>            :               ? s3_FGH_src_hist_1_folded_hist</a>
+<a name="340"><span class="lineNum">     340 </span>            :               : redirect_FGHT_sel</a>
+<a name="341"><span class="lineNum">     341 </span>            :                   ? redirect_FGHT_src_hist_1_folded_hist</a>
+<a name="342"><span class="lineNum">     342 </span>            :                   : stallFGH_src_hist_1_folded_hist;</a>
+<a name="343"><span class="lineNum">     343 </span>            :   assign out_res_hist_0_folded_hist =</a>
+<a name="344"><span class="lineNum">     344 </span>            :     s2_FGH_sel</a>
+<a name="345"><span class="lineNum">     345 </span>            :       ? s2_FGH_src_hist_0_folded_hist</a>
+<a name="346"><span class="lineNum">     346 </span>            :       : s1_FGH_sel</a>
+<a name="347"><span class="lineNum">     347 </span>            :           ? s1_FGH_src_hist_0_folded_hist</a>
+<a name="348"><span class="lineNum">     348 </span>            :           : s3_FGH_sel</a>
+<a name="349"><span class="lineNum">     349 </span>            :               ? s3_FGH_src_hist_0_folded_hist</a>
+<a name="350"><span class="lineNum">     350 </span>            :               : redirect_FGHT_sel</a>
+<a name="351"><span class="lineNum">     351 </span>            :                   ? redirect_FGHT_src_hist_0_folded_hist</a>
+<a name="352"><span class="lineNum">     352 </span>            :                   : stallFGH_src_hist_0_folded_hist;</a>
+<a name="353"><span class="lineNum">     353 </span>            : endmodule</a>
+<a name="354"><span class="lineNum">     354 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/PriorityMuxModule_8.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/PriorityMuxModule_8.sv.func-sort-c.html
new file mode 100644
index 0000000..e886007
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/PriorityMuxModule_8.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/PriorityMuxModule_8.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - PriorityMuxModule_8.sv<span style="font-size: 80%;"> (<a href="PriorityMuxModule_8.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">16</td>
+            <td class="headerCovTableEntry">16</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="PriorityMuxModule_8.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/PriorityMuxModule_8.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/PriorityMuxModule_8.sv.func.html
new file mode 100644
index 0000000..05ed04c
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/PriorityMuxModule_8.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/PriorityMuxModule_8.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - PriorityMuxModule_8.sv<span style="font-size: 80%;"> (<a href="PriorityMuxModule_8.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">16</td>
+            <td class="headerCovTableEntry">16</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="PriorityMuxModule_8.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/PriorityMuxModule_8.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/PriorityMuxModule_8.sv.gcov.html
new file mode 100644
index 0000000..36c3ddb
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/PriorityMuxModule_8.sv.gcov.html
@@ -0,0 +1,170 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/PriorityMuxModule_8.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - PriorityMuxModule_8.sv<span style="font-size: 80%;"> (source / <a href="PriorityMuxModule_8.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">16</td>
+            <td class="headerCovTableEntry">16</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : module PriorityMuxModule_8(</a>
+<a name="59"><span class="lineNum">      59 </span><span class="lineCov">         72 :   input        s2_GHPtr_sel,</span></a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">        183 :   input        s2_GHPtr_src_flag,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">       1077 :   input  [7:0] s2_GHPtr_src_value,</span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">        509 :   input        s1_GHPtr_sel,</span></a>
+<a name="63"><span class="lineNum">      63 </span><span class="lineCov">        168 :   input        s1_GHPtr_src_flag,</span></a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">       1069 :   input  [7:0] s1_GHPtr_src_value,</span></a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">         72 :   input        s3_GHPtr_sel,</span></a>
+<a name="66"><span class="lineNum">      66 </span><span class="lineCov">        173 :   input        s3_GHPtr_src_flag,</span></a>
+<a name="67"><span class="lineNum">      67 </span><span class="lineCov">       1180 :   input  [7:0] s3_GHPtr_src_value,</span></a>
+<a name="68"><span class="lineNum">      68 </span><span class="lineCov">         84 :   input        redirect_GHPtr_sel,</span></a>
+<a name="69"><span class="lineNum">      69 </span><span class="lineCov">        146 :   input        redirect_GHPtr_src_flag,</span></a>
+<a name="70"><span class="lineNum">      70 </span><span class="lineCov">       1184 :   input  [7:0] redirect_GHPtr_src_value,</span></a>
+<a name="71"><span class="lineNum">      71 </span><span class="lineCov">         49 :   input        stallGHPtr_src_flag,</span></a>
+<a name="72"><span class="lineNum">      72 </span><span class="lineCov">        317 :   input  [7:0] stallGHPtr_src_value,</span></a>
+<a name="73"><span class="lineNum">      73 </span><span class="lineCov">        198 :   output       out_res_flag,</span></a>
+<a name="74"><span class="lineNum">      74 </span><span class="lineCov">       1204 :   output [7:0] out_res_value</span></a>
+<a name="75"><span class="lineNum">      75 </span>            : );</a>
+<a name="76"><span class="lineNum">      76 </span>            : </a>
+<a name="77"><span class="lineNum">      77 </span>            :   assign out_res_flag =</a>
+<a name="78"><span class="lineNum">      78 </span>            :     s2_GHPtr_sel</a>
+<a name="79"><span class="lineNum">      79 </span>            :       ? s2_GHPtr_src_flag</a>
+<a name="80"><span class="lineNum">      80 </span>            :       : s1_GHPtr_sel</a>
+<a name="81"><span class="lineNum">      81 </span>            :           ? s1_GHPtr_src_flag</a>
+<a name="82"><span class="lineNum">      82 </span>            :           : s3_GHPtr_sel</a>
+<a name="83"><span class="lineNum">      83 </span>            :               ? s3_GHPtr_src_flag</a>
+<a name="84"><span class="lineNum">      84 </span>            :               : redirect_GHPtr_sel ? redirect_GHPtr_src_flag : stallGHPtr_src_flag;</a>
+<a name="85"><span class="lineNum">      85 </span>            :   assign out_res_value =</a>
+<a name="86"><span class="lineNum">      86 </span>            :     s2_GHPtr_sel</a>
+<a name="87"><span class="lineNum">      87 </span>            :       ? s2_GHPtr_src_value</a>
+<a name="88"><span class="lineNum">      88 </span>            :       : s1_GHPtr_sel</a>
+<a name="89"><span class="lineNum">      89 </span>            :           ? s1_GHPtr_src_value</a>
+<a name="90"><span class="lineNum">      90 </span>            :           : s3_GHPtr_sel</a>
+<a name="91"><span class="lineNum">      91 </span>            :               ? s3_GHPtr_src_value</a>
+<a name="92"><span class="lineNum">      92 </span>            :               : redirect_GHPtr_sel ? redirect_GHPtr_src_value : stallGHPtr_src_value;</a>
+<a name="93"><span class="lineNum">      93 </span>            : endmodule</a>
+<a name="94"><span class="lineNum">      94 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/RAS.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/RAS.sv.func-sort-c.html
new file mode 100644
index 0000000..2619122
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/RAS.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/RAS.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - RAS.sv<span style="font-size: 80%;"> (<a href="RAS.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">401</td>
+            <td class="headerCovTableEntry">401</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="RAS.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/RAS.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/RAS.sv.func.html
new file mode 100644
index 0000000..1fe19a8
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/RAS.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/RAS.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - RAS.sv<span style="font-size: 80%;"> (<a href="RAS.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">401</td>
+            <td class="headerCovTableEntry">401</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="RAS.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/RAS.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/RAS.sv.gcov.html
new file mode 100644
index 0000000..10ed0e2
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/RAS.sv.gcov.html
@@ -0,0 +1,959 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/RAS.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - RAS.sv<span style="font-size: 80%;"> (source / <a href="RAS.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">401</td>
+            <td class="headerCovTableEntry">401</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : module RAS(</a>
+<a name="59"><span class="lineNum">      59 </span><span class="lineCov">     127786 :   input          clock,</span></a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">         62 :   input          reset,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">       1105 :   input  [35:0]  io_reset_vector,</span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">      10337 :   input  [40:0]  io_in_bits_s0_pc_0,</span></a>
+<a name="63"><span class="lineNum">      63 </span><span class="lineCov">      10224 :   input  [40:0]  io_in_bits_s0_pc_1,</span></a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">      10251 :   input  [40:0]  io_in_bits_s0_pc_2,</span></a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">      35066 :   input  [40:0]  io_in_bits_s0_pc_3,</span></a>
+<a name="66"><span class="lineNum">      66 </span><span class="lineCov">         79 :   input          io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_0,</span></a>
+<a name="67"><span class="lineNum">      67 </span><span class="lineCov">         69 :   input          io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_1,</span></a>
+<a name="68"><span class="lineNum">      68 </span><span class="lineCov">         31 :   input          io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_0,</span></a>
+<a name="69"><span class="lineNum">      69 </span><span class="lineCov">         30 :   input          io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_1,</span></a>
+<a name="70"><span class="lineNum">      70 </span><span class="lineCov">       1189 :   input  [40:0]  io_in_bits_resp_in_0_s2_full_pred_0_targets_0,</span></a>
+<a name="71"><span class="lineNum">      71 </span><span class="lineCov">       1202 :   input  [40:0]  io_in_bits_resp_in_0_s2_full_pred_0_targets_1,</span></a>
+<a name="72"><span class="lineNum">      72 </span><span class="lineCov">       1202 :   input  [40:0]  io_in_bits_resp_in_0_s2_full_pred_0_jalr_target,</span></a>
+<a name="73"><span class="lineNum">      73 </span><span class="lineCov">        116 :   input  [3:0]   io_in_bits_resp_in_0_s2_full_pred_0_offsets_0,</span></a>
+<a name="74"><span class="lineNum">      74 </span><span class="lineCov">        107 :   input  [3:0]   io_in_bits_resp_in_0_s2_full_pred_0_offsets_1,</span></a>
+<a name="75"><span class="lineNum">      75 </span><span class="lineCov">       9456 :   input  [40:0]  io_in_bits_resp_in_0_s2_full_pred_0_fallThroughAddr,</span></a>
+<a name="76"><span class="lineNum">      76 </span><span class="lineCov">         31 :   input          io_in_bits_resp_in_0_s2_full_pred_0_is_br_sharing,</span></a>
+<a name="77"><span class="lineNum">      77 </span><span class="lineCov">         18 :   input          io_in_bits_resp_in_0_s2_full_pred_0_hit,</span></a>
+<a name="78"><span class="lineNum">      78 </span><span class="lineCov">         59 :   input          io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_0,</span></a>
+<a name="79"><span class="lineNum">      79 </span><span class="lineCov">         71 :   input          io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_1,</span></a>
+<a name="80"><span class="lineNum">      80 </span><span class="lineCov">         24 :   input          io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_0,</span></a>
+<a name="81"><span class="lineNum">      81 </span><span class="lineCov">         24 :   input          io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_1,</span></a>
+<a name="82"><span class="lineNum">      82 </span><span class="lineCov">       1278 :   input  [40:0]  io_in_bits_resp_in_0_s2_full_pred_1_targets_0,</span></a>
+<a name="83"><span class="lineNum">      83 </span><span class="lineCov">       1114 :   input  [40:0]  io_in_bits_resp_in_0_s2_full_pred_1_targets_1,</span></a>
+<a name="84"><span class="lineNum">      84 </span><span class="lineCov">       1114 :   input  [40:0]  io_in_bits_resp_in_0_s2_full_pred_1_jalr_target,</span></a>
+<a name="85"><span class="lineNum">      85 </span><span class="lineCov">        108 :   input  [3:0]   io_in_bits_resp_in_0_s2_full_pred_1_offsets_0,</span></a>
+<a name="86"><span class="lineNum">      86 </span><span class="lineCov">        119 :   input  [3:0]   io_in_bits_resp_in_0_s2_full_pred_1_offsets_1,</span></a>
+<a name="87"><span class="lineNum">      87 </span><span class="lineCov">       9458 :   input  [40:0]  io_in_bits_resp_in_0_s2_full_pred_1_fallThroughAddr,</span></a>
+<a name="88"><span class="lineNum">      88 </span><span class="lineCov">         17 :   input          io_in_bits_resp_in_0_s2_full_pred_1_is_br_sharing,</span></a>
+<a name="89"><span class="lineNum">      89 </span><span class="lineCov">         25 :   input          io_in_bits_resp_in_0_s2_full_pred_1_hit,</span></a>
+<a name="90"><span class="lineNum">      90 </span><span class="lineCov">         72 :   input          io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_0,</span></a>
+<a name="91"><span class="lineNum">      91 </span><span class="lineCov">         58 :   input          io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_1,</span></a>
+<a name="92"><span class="lineNum">      92 </span><span class="lineCov">         31 :   input          io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_0,</span></a>
+<a name="93"><span class="lineNum">      93 </span><span class="lineCov">         28 :   input          io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_1,</span></a>
+<a name="94"><span class="lineNum">      94 </span><span class="lineCov">       1211 :   input  [40:0]  io_in_bits_resp_in_0_s2_full_pred_2_targets_0,</span></a>
+<a name="95"><span class="lineNum">      95 </span><span class="lineCov">       1198 :   input  [40:0]  io_in_bits_resp_in_0_s2_full_pred_2_targets_1,</span></a>
+<a name="96"><span class="lineNum">      96 </span><span class="lineCov">       1198 :   input  [40:0]  io_in_bits_resp_in_0_s2_full_pred_2_jalr_target,</span></a>
+<a name="97"><span class="lineNum">      97 </span><span class="lineCov">        114 :   input  [3:0]   io_in_bits_resp_in_0_s2_full_pred_2_offsets_0,</span></a>
+<a name="98"><span class="lineNum">      98 </span><span class="lineCov">        120 :   input  [3:0]   io_in_bits_resp_in_0_s2_full_pred_2_offsets_1,</span></a>
+<a name="99"><span class="lineNum">      99 </span><span class="lineCov">       9409 :   input  [40:0]  io_in_bits_resp_in_0_s2_full_pred_2_fallThroughAddr,</span></a>
+<a name="100"><span class="lineNum">     100 </span><span class="lineCov">         23 :   input          io_in_bits_resp_in_0_s2_full_pred_2_is_jalr,</span></a>
+<a name="101"><span class="lineNum">     101 </span><span class="lineCov">         21 :   input          io_in_bits_resp_in_0_s2_full_pred_2_is_call,</span></a>
+<a name="102"><span class="lineNum">     102 </span><span class="lineCov">         26 :   input          io_in_bits_resp_in_0_s2_full_pred_2_is_ret,</span></a>
+<a name="103"><span class="lineNum">     103 </span><span class="lineCov">         25 :   input          io_in_bits_resp_in_0_s2_full_pred_2_last_may_be_rvi_call,</span></a>
+<a name="104"><span class="lineNum">     104 </span><span class="lineCov">         23 :   input          io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing,</span></a>
+<a name="105"><span class="lineNum">     105 </span><span class="lineCov">         29 :   input          io_in_bits_resp_in_0_s2_full_pred_2_hit,</span></a>
+<a name="106"><span class="lineNum">     106 </span><span class="lineCov">         79 :   input          io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_0,</span></a>
+<a name="107"><span class="lineNum">     107 </span><span class="lineCov">         76 :   input          io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_1,</span></a>
+<a name="108"><span class="lineNum">     108 </span><span class="lineCov">         27 :   input          io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_0,</span></a>
+<a name="109"><span class="lineNum">     109 </span><span class="lineCov">         30 :   input          io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_1,</span></a>
+<a name="110"><span class="lineNum">     110 </span><span class="lineCov">       1252 :   input  [40:0]  io_in_bits_resp_in_0_s2_full_pred_3_targets_0,</span></a>
+<a name="111"><span class="lineNum">     111 </span><span class="lineCov">       1179 :   input  [40:0]  io_in_bits_resp_in_0_s2_full_pred_3_targets_1,</span></a>
+<a name="112"><span class="lineNum">     112 </span><span class="lineCov">       1179 :   input  [40:0]  io_in_bits_resp_in_0_s2_full_pred_3_jalr_target,</span></a>
+<a name="113"><span class="lineNum">     113 </span><span class="lineCov">        119 :   input  [3:0]   io_in_bits_resp_in_0_s2_full_pred_3_offsets_0,</span></a>
+<a name="114"><span class="lineNum">     114 </span><span class="lineCov">        105 :   input  [3:0]   io_in_bits_resp_in_0_s2_full_pred_3_offsets_1,</span></a>
+<a name="115"><span class="lineNum">     115 </span><span class="lineCov">       9476 :   input  [40:0]  io_in_bits_resp_in_0_s2_full_pred_3_fallThroughAddr,</span></a>
+<a name="116"><span class="lineNum">     116 </span><span class="lineCov">         33 :   input          io_in_bits_resp_in_0_s2_full_pred_3_fallThroughErr,</span></a>
+<a name="117"><span class="lineNum">     117 </span><span class="lineCov">         22 :   input          io_in_bits_resp_in_0_s2_full_pred_3_is_br_sharing,</span></a>
+<a name="118"><span class="lineNum">     118 </span><span class="lineCov">         18 :   input          io_in_bits_resp_in_0_s2_full_pred_3_hit,</span></a>
+<a name="119"><span class="lineNum">     119 </span><span class="lineCov">         82 :   input          io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_0,</span></a>
+<a name="120"><span class="lineNum">     120 </span><span class="lineCov">         70 :   input          io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_1,</span></a>
+<a name="121"><span class="lineNum">     121 </span><span class="lineCov">         30 :   input          io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_0,</span></a>
+<a name="122"><span class="lineNum">     122 </span><span class="lineCov">         33 :   input          io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_1,</span></a>
+<a name="123"><span class="lineNum">     123 </span><span class="lineCov">       1241 :   input  [40:0]  io_in_bits_resp_in_0_s3_full_pred_0_targets_0,</span></a>
+<a name="124"><span class="lineNum">     124 </span><span class="lineCov">       1247 :   input  [40:0]  io_in_bits_resp_in_0_s3_full_pred_0_targets_1,</span></a>
+<a name="125"><span class="lineNum">     125 </span><span class="lineCov">       1318 :   input  [40:0]  io_in_bits_resp_in_0_s3_full_pred_0_jalr_target,</span></a>
+<a name="126"><span class="lineNum">     126 </span><span class="lineCov">       9423 :   input  [40:0]  io_in_bits_resp_in_0_s3_full_pred_0_fallThroughAddr,</span></a>
+<a name="127"><span class="lineNum">     127 </span><span class="lineCov">         39 :   input          io_in_bits_resp_in_0_s3_full_pred_0_fallThroughErr,</span></a>
+<a name="128"><span class="lineNum">     128 </span><span class="lineCov">         26 :   input          io_in_bits_resp_in_0_s3_full_pred_0_is_br_sharing,</span></a>
+<a name="129"><span class="lineNum">     129 </span><span class="lineCov">         24 :   input          io_in_bits_resp_in_0_s3_full_pred_0_hit,</span></a>
+<a name="130"><span class="lineNum">     130 </span><span class="lineCov">         80 :   input          io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_0,</span></a>
+<a name="131"><span class="lineNum">     131 </span><span class="lineCov">         75 :   input          io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_1,</span></a>
+<a name="132"><span class="lineNum">     132 </span><span class="lineCov">         30 :   input          io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_0,</span></a>
+<a name="133"><span class="lineNum">     133 </span><span class="lineCov">         39 :   input          io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_1,</span></a>
+<a name="134"><span class="lineNum">     134 </span><span class="lineCov">       1262 :   input  [40:0]  io_in_bits_resp_in_0_s3_full_pred_1_targets_0,</span></a>
+<a name="135"><span class="lineNum">     135 </span><span class="lineCov">       1289 :   input  [40:0]  io_in_bits_resp_in_0_s3_full_pred_1_targets_1,</span></a>
+<a name="136"><span class="lineNum">     136 </span><span class="lineCov">       1313 :   input  [40:0]  io_in_bits_resp_in_0_s3_full_pred_1_jalr_target,</span></a>
+<a name="137"><span class="lineNum">     137 </span><span class="lineCov">       9377 :   input  [40:0]  io_in_bits_resp_in_0_s3_full_pred_1_fallThroughAddr,</span></a>
+<a name="138"><span class="lineNum">     138 </span><span class="lineCov">         35 :   input          io_in_bits_resp_in_0_s3_full_pred_1_fallThroughErr,</span></a>
+<a name="139"><span class="lineNum">     139 </span><span class="lineCov">         24 :   input          io_in_bits_resp_in_0_s3_full_pred_1_is_br_sharing,</span></a>
+<a name="140"><span class="lineNum">     140 </span><span class="lineCov">         33 :   input          io_in_bits_resp_in_0_s3_full_pred_1_hit,</span></a>
+<a name="141"><span class="lineNum">     141 </span><span class="lineCov">         86 :   input          io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_0,</span></a>
+<a name="142"><span class="lineNum">     142 </span><span class="lineCov">         70 :   input          io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_1,</span></a>
+<a name="143"><span class="lineNum">     143 </span><span class="lineCov">         26 :   input          io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_0,</span></a>
+<a name="144"><span class="lineNum">     144 </span><span class="lineCov">         30 :   input          io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_1,</span></a>
+<a name="145"><span class="lineNum">     145 </span><span class="lineCov">       1286 :   input  [40:0]  io_in_bits_resp_in_0_s3_full_pred_2_targets_0,</span></a>
+<a name="146"><span class="lineNum">     146 </span><span class="lineCov">       1331 :   input  [40:0]  io_in_bits_resp_in_0_s3_full_pred_2_targets_1,</span></a>
+<a name="147"><span class="lineNum">     147 </span><span class="lineCov">       1351 :   input  [40:0]  io_in_bits_resp_in_0_s3_full_pred_2_jalr_target,</span></a>
+<a name="148"><span class="lineNum">     148 </span><span class="lineCov">       9424 :   input  [40:0]  io_in_bits_resp_in_0_s3_full_pred_2_fallThroughAddr,</span></a>
+<a name="149"><span class="lineNum">     149 </span><span class="lineCov">         35 :   input          io_in_bits_resp_in_0_s3_full_pred_2_fallThroughErr,</span></a>
+<a name="150"><span class="lineNum">     150 </span><span class="lineCov">         23 :   input          io_in_bits_resp_in_0_s3_full_pred_2_is_jalr,</span></a>
+<a name="151"><span class="lineNum">     151 </span><span class="lineCov">         23 :   input          io_in_bits_resp_in_0_s3_full_pred_2_is_call,</span></a>
+<a name="152"><span class="lineNum">     152 </span><span class="lineCov">         24 :   input          io_in_bits_resp_in_0_s3_full_pred_2_is_ret,</span></a>
+<a name="153"><span class="lineNum">     153 </span><span class="lineCov">         21 :   input          io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing,</span></a>
+<a name="154"><span class="lineNum">     154 </span><span class="lineCov">         29 :   input          io_in_bits_resp_in_0_s3_full_pred_2_hit,</span></a>
+<a name="155"><span class="lineNum">     155 </span><span class="lineCov">         75 :   input          io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_0,</span></a>
+<a name="156"><span class="lineNum">     156 </span><span class="lineCov">         76 :   input          io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_1,</span></a>
+<a name="157"><span class="lineNum">     157 </span><span class="lineCov">         41 :   input          io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_0,</span></a>
+<a name="158"><span class="lineNum">     158 </span><span class="lineCov">         42 :   input          io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_1,</span></a>
+<a name="159"><span class="lineNum">     159 </span><span class="lineCov">       1231 :   input  [40:0]  io_in_bits_resp_in_0_s3_full_pred_3_targets_0,</span></a>
+<a name="160"><span class="lineNum">     160 </span><span class="lineCov">       1247 :   input  [40:0]  io_in_bits_resp_in_0_s3_full_pred_3_targets_1,</span></a>
+<a name="161"><span class="lineNum">     161 </span><span class="lineCov">       1327 :   input  [40:0]  io_in_bits_resp_in_0_s3_full_pred_3_jalr_target,</span></a>
+<a name="162"><span class="lineNum">     162 </span><span class="lineCov">        128 :   input  [3:0]   io_in_bits_resp_in_0_s3_full_pred_3_offsets_0,</span></a>
+<a name="163"><span class="lineNum">     163 </span><span class="lineCov">        137 :   input  [3:0]   io_in_bits_resp_in_0_s3_full_pred_3_offsets_1,</span></a>
+<a name="164"><span class="lineNum">     164 </span><span class="lineCov">       9391 :   input  [40:0]  io_in_bits_resp_in_0_s3_full_pred_3_fallThroughAddr,</span></a>
+<a name="165"><span class="lineNum">     165 </span><span class="lineCov">         41 :   input          io_in_bits_resp_in_0_s3_full_pred_3_fallThroughErr,</span></a>
+<a name="166"><span class="lineNum">     166 </span><span class="lineCov">         30 :   input          io_in_bits_resp_in_0_s3_full_pred_3_is_br_sharing,</span></a>
+<a name="167"><span class="lineNum">     167 </span><span class="lineCov">         27 :   input          io_in_bits_resp_in_0_s3_full_pred_3_hit,</span></a>
+<a name="168"><span class="lineNum">     168 </span><span class="lineCov">         29 :   input          io_in_bits_resp_in_0_last_stage_ftb_entry_valid,</span></a>
+<a name="169"><span class="lineNum">     169 </span><span class="lineCov">        126 :   input  [3:0]   io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_offset,</span></a>
+<a name="170"><span class="lineNum">     170 </span><span class="lineCov">        409 :   input  [11:0]  io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_lower,</span></a>
+<a name="171"><span class="lineNum">     171 </span><span class="lineCov">         65 :   input  [1:0]   io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_tarStat,</span></a>
+<a name="172"><span class="lineNum">     172 </span><span class="lineCov">         32 :   input          io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_sharing,</span></a>
+<a name="173"><span class="lineNum">     173 </span><span class="lineCov">         30 :   input          io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_valid,</span></a>
+<a name="174"><span class="lineNum">     174 </span><span class="lineCov">        116 :   input  [3:0]   io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_offset,</span></a>
+<a name="175"><span class="lineNum">     175 </span><span class="lineCov">        705 :   input  [19:0]  io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_lower,</span></a>
+<a name="176"><span class="lineNum">     176 </span><span class="lineCov">         65 :   input  [1:0]   io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_tarStat,</span></a>
+<a name="177"><span class="lineNum">     177 </span><span class="lineCov">         37 :   input          io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_sharing,</span></a>
+<a name="178"><span class="lineNum">     178 </span><span class="lineCov">         33 :   input          io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_valid,</span></a>
+<a name="179"><span class="lineNum">     179 </span><span class="lineCov">        142 :   input  [3:0]   io_in_bits_resp_in_0_last_stage_ftb_entry_pftAddr,</span></a>
+<a name="180"><span class="lineNum">     180 </span><span class="lineCov">         35 :   input          io_in_bits_resp_in_0_last_stage_ftb_entry_carry,</span></a>
+<a name="181"><span class="lineNum">     181 </span><span class="lineCov">         34 :   input          io_in_bits_resp_in_0_last_stage_ftb_entry_isCall,</span></a>
+<a name="182"><span class="lineNum">     182 </span><span class="lineCov">         33 :   input          io_in_bits_resp_in_0_last_stage_ftb_entry_isRet,</span></a>
+<a name="183"><span class="lineNum">     183 </span><span class="lineCov">         36 :   input          io_in_bits_resp_in_0_last_stage_ftb_entry_isJalr,</span></a>
+<a name="184"><span class="lineNum">     184 </span><span class="lineCov">         31 :   input          io_in_bits_resp_in_0_last_stage_ftb_entry_last_may_be_rvi_call,</span></a>
+<a name="185"><span class="lineNum">     185 </span><span class="lineCov">         27 :   input          io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_0,</span></a>
+<a name="186"><span class="lineNum">     186 </span><span class="lineCov">         33 :   input          io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_1,</span></a>
+<a name="187"><span class="lineNum">     187 </span><span class="lineCov">       9399 :   output [40:0]  io_out_s2_pc_0,</span></a>
+<a name="188"><span class="lineNum">     188 </span><span class="lineCov">       9353 :   output [40:0]  io_out_s2_pc_1,</span></a>
+<a name="189"><span class="lineNum">     189 </span><span class="lineCov">       9356 :   output [40:0]  io_out_s2_pc_2,</span></a>
+<a name="190"><span class="lineNum">     190 </span><span class="lineCov">       9388 :   output [40:0]  io_out_s2_pc_3,</span></a>
+<a name="191"><span class="lineNum">     191 </span><span class="lineCov">         79 :   output         io_out_s2_full_pred_0_br_taken_mask_0,</span></a>
+<a name="192"><span class="lineNum">     192 </span><span class="lineCov">         69 :   output         io_out_s2_full_pred_0_br_taken_mask_1,</span></a>
+<a name="193"><span class="lineNum">     193 </span><span class="lineCov">         31 :   output         io_out_s2_full_pred_0_slot_valids_0,</span></a>
+<a name="194"><span class="lineNum">     194 </span><span class="lineCov">         30 :   output         io_out_s2_full_pred_0_slot_valids_1,</span></a>
+<a name="195"><span class="lineNum">     195 </span><span class="lineCov">       1189 :   output [40:0]  io_out_s2_full_pred_0_targets_0,</span></a>
+<a name="196"><span class="lineNum">     196 </span><span class="lineCov">       1454 :   output [40:0]  io_out_s2_full_pred_0_targets_1,</span></a>
+<a name="197"><span class="lineNum">     197 </span><span class="lineCov">        116 :   output [3:0]   io_out_s2_full_pred_0_offsets_0,</span></a>
+<a name="198"><span class="lineNum">     198 </span><span class="lineCov">        107 :   output [3:0]   io_out_s2_full_pred_0_offsets_1,</span></a>
+<a name="199"><span class="lineNum">     199 </span><span class="lineCov">       9456 :   output [40:0]  io_out_s2_full_pred_0_fallThroughAddr,</span></a>
+<a name="200"><span class="lineNum">     200 </span><span class="lineCov">         31 :   output         io_out_s2_full_pred_0_is_br_sharing,</span></a>
+<a name="201"><span class="lineNum">     201 </span><span class="lineCov">         18 :   output         io_out_s2_full_pred_0_hit,</span></a>
+<a name="202"><span class="lineNum">     202 </span><span class="lineCov">         59 :   output         io_out_s2_full_pred_1_br_taken_mask_0,</span></a>
+<a name="203"><span class="lineNum">     203 </span><span class="lineCov">         71 :   output         io_out_s2_full_pred_1_br_taken_mask_1,</span></a>
+<a name="204"><span class="lineNum">     204 </span><span class="lineCov">         24 :   output         io_out_s2_full_pred_1_slot_valids_0,</span></a>
+<a name="205"><span class="lineNum">     205 </span><span class="lineCov">         24 :   output         io_out_s2_full_pred_1_slot_valids_1,</span></a>
+<a name="206"><span class="lineNum">     206 </span><span class="lineCov">       1278 :   output [40:0]  io_out_s2_full_pred_1_targets_0,</span></a>
+<a name="207"><span class="lineNum">     207 </span><span class="lineCov">       1345 :   output [40:0]  io_out_s2_full_pred_1_targets_1,</span></a>
+<a name="208"><span class="lineNum">     208 </span><span class="lineCov">        108 :   output [3:0]   io_out_s2_full_pred_1_offsets_0,</span></a>
+<a name="209"><span class="lineNum">     209 </span><span class="lineCov">        119 :   output [3:0]   io_out_s2_full_pred_1_offsets_1,</span></a>
+<a name="210"><span class="lineNum">     210 </span><span class="lineCov">       9458 :   output [40:0]  io_out_s2_full_pred_1_fallThroughAddr,</span></a>
+<a name="211"><span class="lineNum">     211 </span><span class="lineCov">         17 :   output         io_out_s2_full_pred_1_is_br_sharing,</span></a>
+<a name="212"><span class="lineNum">     212 </span><span class="lineCov">         25 :   output         io_out_s2_full_pred_1_hit,</span></a>
+<a name="213"><span class="lineNum">     213 </span><span class="lineCov">         72 :   output         io_out_s2_full_pred_2_br_taken_mask_0,</span></a>
+<a name="214"><span class="lineNum">     214 </span><span class="lineCov">         58 :   output         io_out_s2_full_pred_2_br_taken_mask_1,</span></a>
+<a name="215"><span class="lineNum">     215 </span><span class="lineCov">         31 :   output         io_out_s2_full_pred_2_slot_valids_0,</span></a>
+<a name="216"><span class="lineNum">     216 </span><span class="lineCov">         28 :   output         io_out_s2_full_pred_2_slot_valids_1,</span></a>
+<a name="217"><span class="lineNum">     217 </span><span class="lineCov">       1211 :   output [40:0]  io_out_s2_full_pred_2_targets_0,</span></a>
+<a name="218"><span class="lineNum">     218 </span><span class="lineCov">       1384 :   output [40:0]  io_out_s2_full_pred_2_targets_1,</span></a>
+<a name="219"><span class="lineNum">     219 </span><span class="lineCov">        114 :   output [3:0]   io_out_s2_full_pred_2_offsets_0,</span></a>
+<a name="220"><span class="lineNum">     220 </span><span class="lineCov">        120 :   output [3:0]   io_out_s2_full_pred_2_offsets_1,</span></a>
+<a name="221"><span class="lineNum">     221 </span><span class="lineCov">       9409 :   output [40:0]  io_out_s2_full_pred_2_fallThroughAddr,</span></a>
+<a name="222"><span class="lineNum">     222 </span><span class="lineCov">         23 :   output         io_out_s2_full_pred_2_is_br_sharing,</span></a>
+<a name="223"><span class="lineNum">     223 </span><span class="lineCov">         29 :   output         io_out_s2_full_pred_2_hit,</span></a>
+<a name="224"><span class="lineNum">     224 </span><span class="lineCov">         79 :   output         io_out_s2_full_pred_3_br_taken_mask_0,</span></a>
+<a name="225"><span class="lineNum">     225 </span><span class="lineCov">         76 :   output         io_out_s2_full_pred_3_br_taken_mask_1,</span></a>
+<a name="226"><span class="lineNum">     226 </span><span class="lineCov">         27 :   output         io_out_s2_full_pred_3_slot_valids_0,</span></a>
+<a name="227"><span class="lineNum">     227 </span><span class="lineCov">         30 :   output         io_out_s2_full_pred_3_slot_valids_1,</span></a>
+<a name="228"><span class="lineNum">     228 </span><span class="lineCov">       1252 :   output [40:0]  io_out_s2_full_pred_3_targets_0,</span></a>
+<a name="229"><span class="lineNum">     229 </span><span class="lineCov">       1433 :   output [40:0]  io_out_s2_full_pred_3_targets_1,</span></a>
+<a name="230"><span class="lineNum">     230 </span><span class="lineCov">        119 :   output [3:0]   io_out_s2_full_pred_3_offsets_0,</span></a>
+<a name="231"><span class="lineNum">     231 </span><span class="lineCov">        105 :   output [3:0]   io_out_s2_full_pred_3_offsets_1,</span></a>
+<a name="232"><span class="lineNum">     232 </span><span class="lineCov">       9476 :   output [40:0]  io_out_s2_full_pred_3_fallThroughAddr,</span></a>
+<a name="233"><span class="lineNum">     233 </span><span class="lineCov">         41 :   output         io_out_s2_full_pred_3_fallThroughErr,</span></a>
+<a name="234"><span class="lineNum">     234 </span><span class="lineCov">         22 :   output         io_out_s2_full_pred_3_is_br_sharing,</span></a>
+<a name="235"><span class="lineNum">     235 </span><span class="lineCov">         18 :   output         io_out_s2_full_pred_3_hit,</span></a>
+<a name="236"><span class="lineNum">     236 </span><span class="lineCov">       9337 :   output [40:0]  io_out_s3_pc_0,</span></a>
+<a name="237"><span class="lineNum">     237 </span><span class="lineCov">       9352 :   output [40:0]  io_out_s3_pc_1,</span></a>
+<a name="238"><span class="lineNum">     238 </span><span class="lineCov">       9331 :   output [40:0]  io_out_s3_pc_2,</span></a>
+<a name="239"><span class="lineNum">     239 </span><span class="lineCov">       9336 :   output [40:0]  io_out_s3_pc_3,</span></a>
+<a name="240"><span class="lineNum">     240 </span><span class="lineCov">         82 :   output         io_out_s3_full_pred_0_br_taken_mask_0,</span></a>
+<a name="241"><span class="lineNum">     241 </span><span class="lineCov">         70 :   output         io_out_s3_full_pred_0_br_taken_mask_1,</span></a>
+<a name="242"><span class="lineNum">     242 </span><span class="lineCov">         30 :   output         io_out_s3_full_pred_0_slot_valids_0,</span></a>
+<a name="243"><span class="lineNum">     243 </span><span class="lineCov">         33 :   output         io_out_s3_full_pred_0_slot_valids_1,</span></a>
+<a name="244"><span class="lineNum">     244 </span><span class="lineCov">       1241 :   output [40:0]  io_out_s3_full_pred_0_targets_0,</span></a>
+<a name="245"><span class="lineNum">     245 </span><span class="lineCov">       1451 :   output [40:0]  io_out_s3_full_pred_0_targets_1,</span></a>
+<a name="246"><span class="lineNum">     246 </span><span class="lineCov">       9423 :   output [40:0]  io_out_s3_full_pred_0_fallThroughAddr,</span></a>
+<a name="247"><span class="lineNum">     247 </span><span class="lineCov">         39 :   output         io_out_s3_full_pred_0_fallThroughErr,</span></a>
+<a name="248"><span class="lineNum">     248 </span><span class="lineCov">         26 :   output         io_out_s3_full_pred_0_is_br_sharing,</span></a>
+<a name="249"><span class="lineNum">     249 </span><span class="lineCov">         24 :   output         io_out_s3_full_pred_0_hit,</span></a>
+<a name="250"><span class="lineNum">     250 </span><span class="lineCov">         80 :   output         io_out_s3_full_pred_1_br_taken_mask_0,</span></a>
+<a name="251"><span class="lineNum">     251 </span><span class="lineCov">         75 :   output         io_out_s3_full_pred_1_br_taken_mask_1,</span></a>
+<a name="252"><span class="lineNum">     252 </span><span class="lineCov">         30 :   output         io_out_s3_full_pred_1_slot_valids_0,</span></a>
+<a name="253"><span class="lineNum">     253 </span><span class="lineCov">         39 :   output         io_out_s3_full_pred_1_slot_valids_1,</span></a>
+<a name="254"><span class="lineNum">     254 </span><span class="lineCov">       1262 :   output [40:0]  io_out_s3_full_pred_1_targets_0,</span></a>
+<a name="255"><span class="lineNum">     255 </span><span class="lineCov">       1497 :   output [40:0]  io_out_s3_full_pred_1_targets_1,</span></a>
+<a name="256"><span class="lineNum">     256 </span><span class="lineCov">       9377 :   output [40:0]  io_out_s3_full_pred_1_fallThroughAddr,</span></a>
+<a name="257"><span class="lineNum">     257 </span><span class="lineCov">         35 :   output         io_out_s3_full_pred_1_fallThroughErr,</span></a>
+<a name="258"><span class="lineNum">     258 </span><span class="lineCov">         24 :   output         io_out_s3_full_pred_1_is_br_sharing,</span></a>
+<a name="259"><span class="lineNum">     259 </span><span class="lineCov">         33 :   output         io_out_s3_full_pred_1_hit,</span></a>
+<a name="260"><span class="lineNum">     260 </span><span class="lineCov">         86 :   output         io_out_s3_full_pred_2_br_taken_mask_0,</span></a>
+<a name="261"><span class="lineNum">     261 </span><span class="lineCov">         70 :   output         io_out_s3_full_pred_2_br_taken_mask_1,</span></a>
+<a name="262"><span class="lineNum">     262 </span><span class="lineCov">         26 :   output         io_out_s3_full_pred_2_slot_valids_0,</span></a>
+<a name="263"><span class="lineNum">     263 </span><span class="lineCov">         30 :   output         io_out_s3_full_pred_2_slot_valids_1,</span></a>
+<a name="264"><span class="lineNum">     264 </span><span class="lineCov">       1286 :   output [40:0]  io_out_s3_full_pred_2_targets_0,</span></a>
+<a name="265"><span class="lineNum">     265 </span><span class="lineCov">       1563 :   output [40:0]  io_out_s3_full_pred_2_targets_1,</span></a>
+<a name="266"><span class="lineNum">     266 </span><span class="lineCov">       9424 :   output [40:0]  io_out_s3_full_pred_2_fallThroughAddr,</span></a>
+<a name="267"><span class="lineNum">     267 </span><span class="lineCov">         35 :   output         io_out_s3_full_pred_2_fallThroughErr,</span></a>
+<a name="268"><span class="lineNum">     268 </span><span class="lineCov">         21 :   output         io_out_s3_full_pred_2_is_br_sharing,</span></a>
+<a name="269"><span class="lineNum">     269 </span><span class="lineCov">         29 :   output         io_out_s3_full_pred_2_hit,</span></a>
+<a name="270"><span class="lineNum">     270 </span><span class="lineCov">         75 :   output         io_out_s3_full_pred_3_br_taken_mask_0,</span></a>
+<a name="271"><span class="lineNum">     271 </span><span class="lineCov">         76 :   output         io_out_s3_full_pred_3_br_taken_mask_1,</span></a>
+<a name="272"><span class="lineNum">     272 </span><span class="lineCov">         41 :   output         io_out_s3_full_pred_3_slot_valids_0,</span></a>
+<a name="273"><span class="lineNum">     273 </span><span class="lineCov">         42 :   output         io_out_s3_full_pred_3_slot_valids_1,</span></a>
+<a name="274"><span class="lineNum">     274 </span><span class="lineCov">       1231 :   output [40:0]  io_out_s3_full_pred_3_targets_0,</span></a>
+<a name="275"><span class="lineNum">     275 </span><span class="lineCov">       1446 :   output [40:0]  io_out_s3_full_pred_3_targets_1,</span></a>
+<a name="276"><span class="lineNum">     276 </span><span class="lineCov">        136 :   output [3:0]   io_out_s3_full_pred_3_offsets_0,</span></a>
+<a name="277"><span class="lineNum">     277 </span><span class="lineCov">        131 :   output [3:0]   io_out_s3_full_pred_3_offsets_1,</span></a>
+<a name="278"><span class="lineNum">     278 </span><span class="lineCov">       9391 :   output [40:0]  io_out_s3_full_pred_3_fallThroughAddr,</span></a>
+<a name="279"><span class="lineNum">     279 </span><span class="lineCov">         41 :   output         io_out_s3_full_pred_3_fallThroughErr,</span></a>
+<a name="280"><span class="lineNum">     280 </span><span class="lineCov">         30 :   output         io_out_s3_full_pred_3_is_br_sharing,</span></a>
+<a name="281"><span class="lineNum">     281 </span><span class="lineCov">         27 :   output         io_out_s3_full_pred_3_hit,</span></a>
+<a name="282"><span class="lineNum">     282 </span><span class="lineCov">       3801 :   output [222:0] io_out_last_stage_meta,</span></a>
+<a name="283"><span class="lineNum">     283 </span><span class="lineCov">        149 :   output [3:0]   io_out_last_stage_spec_info_ssp,</span></a>
+<a name="284"><span class="lineNum">     284 </span><span class="lineCov">         80 :   output [1:0]   io_out_last_stage_spec_info_sctr,</span></a>
+<a name="285"><span class="lineNum">     285 </span><span class="lineCov">         41 :   output         io_out_last_stage_spec_info_TOSW_flag,</span></a>
+<a name="286"><span class="lineNum">     286 </span><span class="lineCov">        183 :   output [4:0]   io_out_last_stage_spec_info_TOSW_value,</span></a>
+<a name="287"><span class="lineNum">     287 </span><span class="lineCov">         40 :   output         io_out_last_stage_spec_info_TOSR_flag,</span></a>
+<a name="288"><span class="lineNum">     288 </span><span class="lineCov">        214 :   output [4:0]   io_out_last_stage_spec_info_TOSR_value,</span></a>
+<a name="289"><span class="lineNum">     289 </span><span class="lineCov">         31 :   output         io_out_last_stage_spec_info_NOS_flag,</span></a>
+<a name="290"><span class="lineNum">     290 </span><span class="lineCov">        160 :   output [4:0]   io_out_last_stage_spec_info_NOS_value,</span></a>
+<a name="291"><span class="lineNum">     291 </span><span class="lineCov">       1348 :   output [40:0]  io_out_last_stage_spec_info_topAddr,</span></a>
+<a name="292"><span class="lineNum">     292 </span><span class="lineCov">         33 :   output         io_out_last_stage_ftb_entry_valid,</span></a>
+<a name="293"><span class="lineNum">     293 </span><span class="lineCov">        119 :   output [3:0]   io_out_last_stage_ftb_entry_brSlots_0_offset,</span></a>
+<a name="294"><span class="lineNum">     294 </span><span class="lineCov">        411 :   output [11:0]  io_out_last_stage_ftb_entry_brSlots_0_lower,</span></a>
+<a name="295"><span class="lineNum">     295 </span><span class="lineCov">         59 :   output [1:0]   io_out_last_stage_ftb_entry_brSlots_0_tarStat,</span></a>
+<a name="296"><span class="lineNum">     296 </span><span class="lineCov">         34 :   output         io_out_last_stage_ftb_entry_brSlots_0_sharing,</span></a>
+<a name="297"><span class="lineNum">     297 </span><span class="lineCov">         29 :   output         io_out_last_stage_ftb_entry_brSlots_0_valid,</span></a>
+<a name="298"><span class="lineNum">     298 </span><span class="lineCov">        125 :   output [3:0]   io_out_last_stage_ftb_entry_tailSlot_offset,</span></a>
+<a name="299"><span class="lineNum">     299 </span><span class="lineCov">        676 :   output [19:0]  io_out_last_stage_ftb_entry_tailSlot_lower,</span></a>
+<a name="300"><span class="lineNum">     300 </span><span class="lineCov">         70 :   output [1:0]   io_out_last_stage_ftb_entry_tailSlot_tarStat,</span></a>
+<a name="301"><span class="lineNum">     301 </span><span class="lineCov">         30 :   output         io_out_last_stage_ftb_entry_tailSlot_sharing,</span></a>
+<a name="302"><span class="lineNum">     302 </span><span class="lineCov">         31 :   output         io_out_last_stage_ftb_entry_tailSlot_valid,</span></a>
+<a name="303"><span class="lineNum">     303 </span><span class="lineCov">        140 :   output [3:0]   io_out_last_stage_ftb_entry_pftAddr,</span></a>
+<a name="304"><span class="lineNum">     304 </span><span class="lineCov">         33 :   output         io_out_last_stage_ftb_entry_carry,</span></a>
+<a name="305"><span class="lineNum">     305 </span><span class="lineCov">         35 :   output         io_out_last_stage_ftb_entry_isCall,</span></a>
+<a name="306"><span class="lineNum">     306 </span><span class="lineCov">         29 :   output         io_out_last_stage_ftb_entry_isRet,</span></a>
+<a name="307"><span class="lineNum">     307 </span><span class="lineCov">         40 :   output         io_out_last_stage_ftb_entry_isJalr,</span></a>
+<a name="308"><span class="lineNum">     308 </span><span class="lineCov">         36 :   output         io_out_last_stage_ftb_entry_last_may_be_rvi_call,</span></a>
+<a name="309"><span class="lineNum">     309 </span><span class="lineCov">         27 :   output         io_out_last_stage_ftb_entry_always_taken_0,</span></a>
+<a name="310"><span class="lineNum">     310 </span><span class="lineCov">         32 :   output         io_out_last_stage_ftb_entry_always_taken_1,</span></a>
+<a name="311"><span class="lineNum">     311 </span><span class="lineCov">         82 :   input          io_ctrl_ras_enable,</span></a>
+<a name="312"><span class="lineNum">     312 </span><span class="lineCov">         75 :   input          io_s0_fire_0,</span></a>
+<a name="313"><span class="lineNum">     313 </span><span class="lineCov">         76 :   input          io_s0_fire_1,</span></a>
+<a name="314"><span class="lineNum">     314 </span><span class="lineCov">         76 :   input          io_s0_fire_2,</span></a>
+<a name="315"><span class="lineNum">     315 </span><span class="lineCov">         73 :   input          io_s0_fire_3,</span></a>
+<a name="316"><span class="lineNum">     316 </span><span class="lineCov">        133 :   input          io_s1_fire_0,</span></a>
+<a name="317"><span class="lineNum">     317 </span><span class="lineCov">        131 :   input          io_s1_fire_1,</span></a>
+<a name="318"><span class="lineNum">     318 </span><span class="lineCov">        135 :   input          io_s1_fire_2,</span></a>
+<a name="319"><span class="lineNum">     319 </span><span class="lineCov">        133 :   input          io_s1_fire_3,</span></a>
+<a name="320"><span class="lineNum">     320 </span><span class="lineCov">        127 :   input          io_s2_fire_0,</span></a>
+<a name="321"><span class="lineNum">     321 </span><span class="lineCov">        127 :   input          io_s2_fire_1,</span></a>
+<a name="322"><span class="lineNum">     322 </span><span class="lineCov">        127 :   input          io_s2_fire_2,</span></a>
+<a name="323"><span class="lineNum">     323 </span><span class="lineCov">        127 :   input          io_s2_fire_3,</span></a>
+<a name="324"><span class="lineNum">     324 </span><span class="lineCov">        127 :   input          io_s3_fire_2,</span></a>
+<a name="325"><span class="lineNum">     325 </span><span class="lineCov">         20 :   input          io_s3_redirect_2,</span></a>
+<a name="326"><span class="lineNum">     326 </span><span class="lineCov">        105 :   input          io_update_valid,</span></a>
+<a name="327"><span class="lineNum">     327 </span><span class="lineCov">        137 :   input  [3:0]   io_update_bits_ftb_entry_tailSlot_offset,</span></a>
+<a name="328"><span class="lineNum">     328 </span><span class="lineCov">         28 :   input          io_update_bits_ftb_entry_tailSlot_valid,</span></a>
+<a name="329"><span class="lineNum">     329 </span><span class="lineCov">         39 :   input          io_update_bits_ftb_entry_isCall,</span></a>
+<a name="330"><span class="lineNum">     330 </span><span class="lineCov">         36 :   input          io_update_bits_ftb_entry_isRet,</span></a>
+<a name="331"><span class="lineNum">     331 </span><span class="lineCov">         22 :   input          io_update_bits_cfi_idx_valid,</span></a>
+<a name="332"><span class="lineNum">     332 </span><span class="lineCov">        155 :   input  [3:0]   io_update_bits_cfi_idx_bits,</span></a>
+<a name="333"><span class="lineNum">     333 </span><span class="lineCov">         40 :   input          io_update_bits_jmp_taken,</span></a>
+<a name="334"><span class="lineNum">     334 </span><span class="lineCov">       6212 :   input  [222:0] io_update_bits_meta,</span></a>
+<a name="335"><span class="lineNum">     335 </span><span class="lineCov">         84 :   input          io_redirect_valid,</span></a>
+<a name="336"><span class="lineNum">     336 </span><span class="lineCov">         28 :   input          io_redirect_bits_level,</span></a>
+<a name="337"><span class="lineNum">     337 </span><span class="lineCov">       1207 :   input  [40:0]  io_redirect_bits_cfiUpdate_pc,</span></a>
+<a name="338"><span class="lineNum">     338 </span><span class="lineCov">         27 :   input          io_redirect_bits_cfiUpdate_pd_isRVC,</span></a>
+<a name="339"><span class="lineNum">     339 </span><span class="lineCov">         37 :   input          io_redirect_bits_cfiUpdate_pd_isCall,</span></a>
+<a name="340"><span class="lineNum">     340 </span><span class="lineCov">         37 :   input          io_redirect_bits_cfiUpdate_pd_isRet,</span></a>
+<a name="341"><span class="lineNum">     341 </span><span class="lineCov">        115 :   input  [3:0]   io_redirect_bits_cfiUpdate_ssp,</span></a>
+<a name="342"><span class="lineNum">     342 </span><span class="lineCov">         73 :   input  [1:0]   io_redirect_bits_cfiUpdate_sctr,</span></a>
+<a name="343"><span class="lineNum">     343 </span><span class="lineCov">         43 :   input          io_redirect_bits_cfiUpdate_TOSW_flag,</span></a>
+<a name="344"><span class="lineNum">     344 </span><span class="lineCov">        147 :   input  [4:0]   io_redirect_bits_cfiUpdate_TOSW_value,</span></a>
+<a name="345"><span class="lineNum">     345 </span><span class="lineCov">         42 :   input          io_redirect_bits_cfiUpdate_TOSR_flag,</span></a>
+<a name="346"><span class="lineNum">     346 </span><span class="lineCov">        138 :   input  [4:0]   io_redirect_bits_cfiUpdate_TOSR_value,</span></a>
+<a name="347"><span class="lineNum">     347 </span><span class="lineCov">         40 :   input          io_redirect_bits_cfiUpdate_NOS_flag,</span></a>
+<a name="348"><span class="lineNum">     348 </span><span class="lineCov">        150 :   input  [4:0]   io_redirect_bits_cfiUpdate_NOS_value</span></a>
+<a name="349"><span class="lineNum">     349 </span>            : );</a>
+<a name="350"><span class="lineNum">     350 </span>            : </a>
+<a name="351"><span class="lineNum">     351 </span>            :   wire [40:0] _RASStack_io_spec_pop_addr;</a>
+<a name="352"><span class="lineNum">     352 </span>            :   wire [3:0]  _RASStack_io_ssp;</a>
+<a name="353"><span class="lineNum">     353 </span>            :   wire [2:0]  _RASStack_io_sctr;</a>
+<a name="354"><span class="lineNum">     354 </span>            :   wire        _RASStack_io_TOSR_flag;</a>
+<a name="355"><span class="lineNum">     355 </span>            :   wire [4:0]  _RASStack_io_TOSR_value;</a>
+<a name="356"><span class="lineNum">     356 </span>            :   wire        _RASStack_io_TOSW_flag;</a>
+<a name="357"><span class="lineNum">     357 </span>            :   wire [4:0]  _RASStack_io_TOSW_value;</a>
+<a name="358"><span class="lineNum">     358 </span>            :   wire        _RASStack_io_NOS_flag;</a>
+<a name="359"><span class="lineNum">     359 </span>            :   wire [4:0]  _RASStack_io_NOS_value;</a>
+<a name="360"><span class="lineNum">     360 </span>            :   wire [35:0] _reset_vector_delay_io_out;</a>
+<a name="361"><span class="lineNum">     361 </span><span class="lineCov">       9961 :   reg  [40:0] s1_pc_dup_0;</span></a>
+<a name="362"><span class="lineNum">     362 </span><span class="lineCov">       9944 :   reg  [40:0] s1_pc_dup_1;</span></a>
+<a name="363"><span class="lineNum">     363 </span><span class="lineCov">       9990 :   reg  [40:0] s1_pc_dup_2;</span></a>
+<a name="364"><span class="lineNum">     364 </span><span class="lineCov">       9974 :   reg  [40:0] s1_pc_dup_3;</span></a>
+<a name="365"><span class="lineNum">     365 </span><span class="lineCov">       9399 :   reg  [40:0] s2_pc_dup_0;</span></a>
+<a name="366"><span class="lineNum">     366 </span><span class="lineCov">       9353 :   reg  [40:0] s2_pc_dup_1;</span></a>
+<a name="367"><span class="lineNum">     367 </span><span class="lineCov">       9356 :   reg  [40:0] s2_pc_dup_2;</span></a>
+<a name="368"><span class="lineNum">     368 </span><span class="lineCov">       9388 :   reg  [40:0] s2_pc_dup_3;</span></a>
+<a name="369"><span class="lineNum">     369 </span><span class="lineCov">       9337 :   reg  [40:0] s3_pc_dup_0;</span></a>
+<a name="370"><span class="lineNum">     370 </span><span class="lineCov">       9352 :   reg  [40:0] s3_pc_dup_1;</span></a>
+<a name="371"><span class="lineNum">     371 </span><span class="lineCov">       9331 :   reg  [40:0] s3_pc_dup_2;</span></a>
+<a name="372"><span class="lineNum">     372 </span><span class="lineCov">       9336 :   reg  [40:0] s3_pc_dup_3;</span></a>
+<a name="373"><span class="lineNum">     373 </span><span class="lineCov">         78 :   reg         REG;</span></a>
+<a name="374"><span class="lineNum">     374 </span><span class="lineCov">        102 :   reg         REG_1;</span></a>
+<a name="375"><span class="lineNum">     375 </span>            :   wire [40:0] _s2_spec_new_addr_T_1 =</a>
+<a name="376"><span class="lineNum">     376 </span>            :     41'(io_in_bits_resp_in_0_s2_full_pred_2_fallThroughAddr</a>
+<a name="377"><span class="lineNum">     377 </span>            :         + {39'h0, io_in_bits_resp_in_0_s2_full_pred_2_last_may_be_rvi_call, 1'h0});</a>
+<a name="378"><span class="lineNum">     378 </span>            :   wire        _s2_spec_pop_T_8 =</a>
+<a name="379"><span class="lineNum">     379 </span>            :     io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_0</a>
+<a name="380"><span class="lineNum">     380 </span>            :     &amp; io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_0;</a>
+<a name="381"><span class="lineNum">     381 </span>            :   wire        _s2_spec_pop_T_9 =</a>
+<a name="382"><span class="lineNum">     382 </span>            :     io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing</a>
+<a name="383"><span class="lineNum">     383 </span>            :     &amp; io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_1;</a>
+<a name="384"><span class="lineNum">     384 </span><span class="lineCov">         16 :   wire        s2_spec_push =</span></a>
+<a name="385"><span class="lineNum">     385 </span>            :     io_s2_fire_2 &amp; ~(_s2_spec_pop_T_8 &amp; io_in_bits_resp_in_0_s2_full_pred_2_hit)</a>
+<a name="386"><span class="lineNum">     386 </span>            :     &amp; io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_1</a>
+<a name="387"><span class="lineNum">     387 </span>            :     &amp; (_s2_spec_pop_T_9 | ~io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing)</a>
+<a name="388"><span class="lineNum">     388 </span>            :     &amp; io_in_bits_resp_in_0_s2_full_pred_2_hit</a>
+<a name="389"><span class="lineNum">     389 </span>            :     &amp; ~io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing</a>
+<a name="390"><span class="lineNum">     390 </span>            :     &amp; io_in_bits_resp_in_0_s2_full_pred_2_is_call &amp; ~io_s3_redirect_2;</a>
+<a name="391"><span class="lineNum">     391 </span><span class="lineCov">         16 :   wire        s2_spec_pop =</span></a>
+<a name="392"><span class="lineNum">     392 </span>            :     io_s2_fire_2 &amp; ~(_s2_spec_pop_T_8 &amp; io_in_bits_resp_in_0_s2_full_pred_2_hit)</a>
+<a name="393"><span class="lineNum">     393 </span>            :     &amp; io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_1</a>
+<a name="394"><span class="lineNum">     394 </span>            :     &amp; (_s2_spec_pop_T_9 | ~io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing)</a>
+<a name="395"><span class="lineNum">     395 </span>            :     &amp; io_in_bits_resp_in_0_s2_full_pred_2_hit</a>
+<a name="396"><span class="lineNum">     396 </span>            :     &amp; ~io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing</a>
+<a name="397"><span class="lineNum">     397 </span>            :     &amp; io_in_bits_resp_in_0_s2_full_pred_2_is_ret &amp; ~io_s3_redirect_2;</a>
+<a name="398"><span class="lineNum">     398 </span>            :   wire        _GEN = io_in_bits_resp_in_0_s2_full_pred_2_is_ret &amp; io_ctrl_ras_enable;</a>
+<a name="399"><span class="lineNum">     399 </span><span class="lineCov">       1303 :   reg  [40:0] s3_top;</span></a>
+<a name="400"><span class="lineNum">     400 </span><span class="lineCov">       9375 :   reg  [40:0] s3_spec_new_addr;</span></a>
+<a name="401"><span class="lineNum">     401 </span>            :   wire        _GEN_0 = io_in_bits_resp_in_0_s3_full_pred_2_is_ret &amp; io_ctrl_ras_enable;</a>
+<a name="402"><span class="lineNum">     402 </span><span class="lineCov">         25 :   reg         s3_pushed_in_s2;</span></a>
+<a name="403"><span class="lineNum">     403 </span><span class="lineCov">         23 :   reg         s3_popped_in_s2;</span></a>
+<a name="404"><span class="lineNum">     404 </span>            :   wire        _s3_pop_T_8 =</a>
+<a name="405"><span class="lineNum">     405 </span>            :     io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_0</a>
+<a name="406"><span class="lineNum">     406 </span>            :     &amp; io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_0;</a>
+<a name="407"><span class="lineNum">     407 </span>            :   wire        _s3_pop_T_9 =</a>
+<a name="408"><span class="lineNum">     408 </span>            :     io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing</a>
+<a name="409"><span class="lineNum">     409 </span>            :     &amp; io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_1;</a>
+<a name="410"><span class="lineNum">     410 </span><span class="lineCov">         16 :   wire        s3_push =</span></a>
+<a name="411"><span class="lineNum">     411 </span>            :     ~(_s3_pop_T_8 &amp; io_in_bits_resp_in_0_s3_full_pred_2_hit)</a>
+<a name="412"><span class="lineNum">     412 </span>            :     &amp; io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_1</a>
+<a name="413"><span class="lineNum">     413 </span>            :     &amp; (_s3_pop_T_9 | ~io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing)</a>
+<a name="414"><span class="lineNum">     414 </span>            :     &amp; io_in_bits_resp_in_0_s3_full_pred_2_hit</a>
+<a name="415"><span class="lineNum">     415 </span>            :     &amp; ~io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing</a>
+<a name="416"><span class="lineNum">     416 </span>            :     &amp; io_in_bits_resp_in_0_s3_full_pred_2_is_call;</a>
+<a name="417"><span class="lineNum">     417 </span><span class="lineCov">         14 :   wire        s3_pop =</span></a>
+<a name="418"><span class="lineNum">     418 </span>            :     ~(_s3_pop_T_8 &amp; io_in_bits_resp_in_0_s3_full_pred_2_hit)</a>
+<a name="419"><span class="lineNum">     419 </span>            :     &amp; io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_1</a>
+<a name="420"><span class="lineNum">     420 </span>            :     &amp; (_s3_pop_T_9 | ~io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing)</a>
+<a name="421"><span class="lineNum">     421 </span>            :     &amp; io_in_bits_resp_in_0_s3_full_pred_2_hit</a>
+<a name="422"><span class="lineNum">     422 </span>            :     &amp; ~io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing</a>
+<a name="423"><span class="lineNum">     423 </span>            :     &amp; io_in_bits_resp_in_0_s3_full_pred_2_is_ret;</a>
+<a name="424"><span class="lineNum">     424 </span><span class="lineCov">        156 :   reg  [3:0]  s3_meta_ssp;</span></a>
+<a name="425"><span class="lineNum">     425 </span><span class="lineCov">        124 :   reg  [2:0]  s3_meta_sctr;</span></a>
+<a name="426"><span class="lineNum">     426 </span><span class="lineCov">         48 :   reg         s3_meta_TOSW_flag;</span></a>
+<a name="427"><span class="lineNum">     427 </span><span class="lineCov">        173 :   reg  [4:0]  s3_meta_TOSW_value;</span></a>
+<a name="428"><span class="lineNum">     428 </span><span class="lineCov">         41 :   reg         s3_meta_TOSR_flag;</span></a>
+<a name="429"><span class="lineNum">     429 </span><span class="lineCov">        218 :   reg  [4:0]  s3_meta_TOSR_value;</span></a>
+<a name="430"><span class="lineNum">     430 </span><span class="lineCov">         28 :   reg         s3_meta_NOS_flag;</span></a>
+<a name="431"><span class="lineNum">     431 </span><span class="lineCov">        172 :   reg  [4:0]  s3_meta_NOS_value;</span></a>
+<a name="432"><span class="lineNum">     432 </span><span class="lineCov">         83 :   reg         redirect_next_valid_last_r;</span></a>
+<a name="433"><span class="lineNum">     433 </span><span class="lineCov">         23 :   reg         redirect_next_bits_r_level;</span></a>
+<a name="434"><span class="lineNum">     434 </span><span class="lineCov">       1032 :   reg  [40:0] redirect_next_bits_r_cfiUpdate_pc;</span></a>
+<a name="435"><span class="lineNum">     435 </span><span class="lineCov">         38 :   reg         redirect_next_bits_r_cfiUpdate_pd_isRVC;</span></a>
+<a name="436"><span class="lineNum">     436 </span><span class="lineCov">         29 :   reg         redirect_next_bits_r_cfiUpdate_pd_isCall;</span></a>
+<a name="437"><span class="lineNum">     437 </span><span class="lineCov">         34 :   reg         redirect_next_bits_r_cfiUpdate_pd_isRet;</span></a>
+<a name="438"><span class="lineNum">     438 </span><span class="lineCov">        106 :   reg  [3:0]  redirect_next_bits_r_cfiUpdate_ssp;</span></a>
+<a name="439"><span class="lineNum">     439 </span><span class="lineCov">         62 :   reg  [1:0]  redirect_next_bits_r_cfiUpdate_sctr;</span></a>
+<a name="440"><span class="lineNum">     440 </span><span class="lineCov">         28 :   reg         redirect_next_bits_r_cfiUpdate_TOSW_flag;</span></a>
+<a name="441"><span class="lineNum">     441 </span><span class="lineCov">        151 :   reg  [4:0]  redirect_next_bits_r_cfiUpdate_TOSW_value;</span></a>
+<a name="442"><span class="lineNum">     442 </span><span class="lineCov">         32 :   reg         redirect_next_bits_r_cfiUpdate_TOSR_flag;</span></a>
+<a name="443"><span class="lineNum">     443 </span><span class="lineCov">        132 :   reg  [4:0]  redirect_next_bits_r_cfiUpdate_TOSR_value;</span></a>
+<a name="444"><span class="lineNum">     444 </span><span class="lineCov">         37 :   reg         redirect_next_bits_r_cfiUpdate_NOS_flag;</span></a>
+<a name="445"><span class="lineNum">     445 </span><span class="lineCov">        134 :   reg  [4:0]  redirect_next_bits_r_cfiUpdate_NOS_value;</span></a>
+<a name="446"><span class="lineNum">     446 </span>            :   wire        _GEN_1 =</a>
+<a name="447"><span class="lineNum">     447 </span>            :     io_update_bits_cfi_idx_bits == io_update_bits_ftb_entry_tailSlot_offset;</a>
+<a name="448"><span class="lineNum">     448 </span>            :   wire [40:0] _GEN_2 = {5'h0, _reset_vector_delay_io_out};</a>
+<a name="449"><span class="lineNum">     449 </span><span class="lineCov">     127694 :   always @(posedge clock) begin</span></a>
+<a name="450"><span class="lineNum">     450 </span><span class="lineCov">        110 :     if (REG_1) begin</span></a>
+<a name="451"><span class="lineNum">     451 </span><span class="lineCov">         55 :       s1_pc_dup_0 &lt;= _GEN_2;</span></a>
+<a name="452"><span class="lineNum">     452 </span><span class="lineCov">         55 :       s1_pc_dup_1 &lt;= _GEN_2;</span></a>
+<a name="453"><span class="lineNum">     453 </span><span class="lineCov">         55 :       s1_pc_dup_2 &lt;= _GEN_2;</span></a>
+<a name="454"><span class="lineNum">     454 </span><span class="lineCov">         55 :       s1_pc_dup_3 &lt;= _GEN_2;</span></a>
+<a name="455"><span class="lineNum">     455 </span>            :     end</a>
+<a name="456"><span class="lineNum">     456 </span><span class="lineCov">      63792 :     else begin</span></a>
+<a name="457"><span class="lineNum">     457 </span><span class="lineCov">       8350 :       if (io_s0_fire_0)</span></a>
+<a name="458"><span class="lineNum">     458 </span><span class="lineCov">       4175 :         s1_pc_dup_0 &lt;= io_in_bits_s0_pc_0;</span></a>
+<a name="459"><span class="lineNum">     459 </span><span class="lineCov">       8350 :       if (io_s0_fire_1)</span></a>
+<a name="460"><span class="lineNum">     460 </span><span class="lineCov">       4175 :         s1_pc_dup_1 &lt;= io_in_bits_s0_pc_1;</span></a>
+<a name="461"><span class="lineNum">     461 </span><span class="lineCov">       8350 :       if (io_s0_fire_2)</span></a>
+<a name="462"><span class="lineNum">     462 </span><span class="lineCov">       4175 :         s1_pc_dup_2 &lt;= io_in_bits_s0_pc_2;</span></a>
+<a name="463"><span class="lineNum">     463 </span><span class="lineCov">       8350 :       if (io_s0_fire_3)</span></a>
+<a name="464"><span class="lineNum">     464 </span><span class="lineCov">       4175 :         s1_pc_dup_3 &lt;= io_in_bits_s0_pc_3;</span></a>
+<a name="465"><span class="lineNum">     465 </span>            :     end</a>
+<a name="466"><span class="lineNum">     466 </span><span class="lineCov">       8252 :     if (io_s1_fire_0)</span></a>
+<a name="467"><span class="lineNum">     467 </span><span class="lineCov">       4126 :       s2_pc_dup_0 &lt;= s1_pc_dup_0;</span></a>
+<a name="468"><span class="lineNum">     468 </span><span class="lineCov">       8252 :     if (io_s1_fire_1)</span></a>
+<a name="469"><span class="lineNum">     469 </span><span class="lineCov">       4126 :       s2_pc_dup_1 &lt;= s1_pc_dup_1;</span></a>
+<a name="470"><span class="lineNum">     470 </span><span class="lineCov">       8252 :     if (io_s1_fire_2)</span></a>
+<a name="471"><span class="lineNum">     471 </span><span class="lineCov">       4126 :       s2_pc_dup_2 &lt;= s1_pc_dup_2;</span></a>
+<a name="472"><span class="lineNum">     472 </span><span class="lineCov">       8252 :     if (io_s1_fire_3)</span></a>
+<a name="473"><span class="lineNum">     473 </span><span class="lineCov">       4126 :       s2_pc_dup_3 &lt;= s1_pc_dup_3;</span></a>
+<a name="474"><span class="lineNum">     474 </span><span class="lineCov">       8150 :     if (io_s2_fire_0)</span></a>
+<a name="475"><span class="lineNum">     475 </span><span class="lineCov">       4075 :       s3_pc_dup_0 &lt;= s2_pc_dup_0;</span></a>
+<a name="476"><span class="lineNum">     476 </span><span class="lineCov">       8150 :     if (io_s2_fire_1)</span></a>
+<a name="477"><span class="lineNum">     477 </span><span class="lineCov">       4075 :       s3_pc_dup_1 &lt;= s2_pc_dup_1;</span></a>
+<a name="478"><span class="lineNum">     478 </span><span class="lineCov">       8150 :     if (io_s2_fire_2) begin</span></a>
+<a name="479"><span class="lineNum">     479 </span><span class="lineCov">       4075 :       s3_pc_dup_2 &lt;= s2_pc_dup_2;</span></a>
+<a name="480"><span class="lineNum">     480 </span><span class="lineCov">       4075 :       s3_top &lt;= _RASStack_io_spec_pop_addr;</span></a>
+<a name="481"><span class="lineNum">     481 </span><span class="lineCov">       4075 :       s3_spec_new_addr &lt;= _s2_spec_new_addr_T_1;</span></a>
+<a name="482"><span class="lineNum">     482 </span><span class="lineCov">       4075 :       s3_pushed_in_s2 &lt;= s2_spec_push;</span></a>
+<a name="483"><span class="lineNum">     483 </span><span class="lineCov">       4075 :       s3_popped_in_s2 &lt;= s2_spec_pop;</span></a>
+<a name="484"><span class="lineNum">     484 </span><span class="lineCov">       4075 :       s3_meta_ssp &lt;= _RASStack_io_ssp;</span></a>
+<a name="485"><span class="lineNum">     485 </span><span class="lineCov">       4075 :       s3_meta_sctr &lt;= _RASStack_io_sctr;</span></a>
+<a name="486"><span class="lineNum">     486 </span><span class="lineCov">       4075 :       s3_meta_TOSW_flag &lt;= _RASStack_io_TOSW_flag;</span></a>
+<a name="487"><span class="lineNum">     487 </span><span class="lineCov">       4075 :       s3_meta_TOSW_value &lt;= _RASStack_io_TOSW_value;</span></a>
+<a name="488"><span class="lineNum">     488 </span><span class="lineCov">       4075 :       s3_meta_TOSR_flag &lt;= _RASStack_io_TOSR_flag;</span></a>
+<a name="489"><span class="lineNum">     489 </span><span class="lineCov">       4075 :       s3_meta_TOSR_value &lt;= _RASStack_io_TOSR_value;</span></a>
+<a name="490"><span class="lineNum">     490 </span><span class="lineCov">       4075 :       s3_meta_NOS_flag &lt;= _RASStack_io_NOS_flag;</span></a>
+<a name="491"><span class="lineNum">     491 </span><span class="lineCov">       4075 :       s3_meta_NOS_value &lt;= _RASStack_io_NOS_value;</span></a>
+<a name="492"><span class="lineNum">     492 </span>            :     end</a>
+<a name="493"><span class="lineNum">     493 </span><span class="lineCov">       8150 :     if (io_s2_fire_3)</span></a>
+<a name="494"><span class="lineNum">     494 </span><span class="lineCov">       4075 :       s3_pc_dup_3 &lt;= s2_pc_dup_3;</span></a>
+<a name="495"><span class="lineNum">     495 </span><span class="lineCov">      63847 :     REG &lt;= reset;</span></a>
+<a name="496"><span class="lineNum">     496 </span><span class="lineCov">      63847 :     REG_1 &lt;= REG &amp; ~reset;</span></a>
+<a name="497"><span class="lineNum">     497 </span><span class="lineCov">         72 :     if (io_redirect_valid) begin</span></a>
+<a name="498"><span class="lineNum">     498 </span><span class="lineCov">         36 :       redirect_next_bits_r_level &lt;= io_redirect_bits_level;</span></a>
+<a name="499"><span class="lineNum">     499 </span><span class="lineCov">         36 :       redirect_next_bits_r_cfiUpdate_pc &lt;= io_redirect_bits_cfiUpdate_pc;</span></a>
+<a name="500"><span class="lineNum">     500 </span><span class="lineCov">         36 :       redirect_next_bits_r_cfiUpdate_pd_isRVC &lt;= io_redirect_bits_cfiUpdate_pd_isRVC;</span></a>
+<a name="501"><span class="lineNum">     501 </span><span class="lineCov">         36 :       redirect_next_bits_r_cfiUpdate_pd_isCall &lt;= io_redirect_bits_cfiUpdate_pd_isCall;</span></a>
+<a name="502"><span class="lineNum">     502 </span><span class="lineCov">         36 :       redirect_next_bits_r_cfiUpdate_pd_isRet &lt;= io_redirect_bits_cfiUpdate_pd_isRet;</span></a>
+<a name="503"><span class="lineNum">     503 </span><span class="lineCov">         36 :       redirect_next_bits_r_cfiUpdate_ssp &lt;= io_redirect_bits_cfiUpdate_ssp;</span></a>
+<a name="504"><span class="lineNum">     504 </span><span class="lineCov">         36 :       redirect_next_bits_r_cfiUpdate_sctr &lt;= io_redirect_bits_cfiUpdate_sctr;</span></a>
+<a name="505"><span class="lineNum">     505 </span><span class="lineCov">         36 :       redirect_next_bits_r_cfiUpdate_TOSW_flag &lt;= io_redirect_bits_cfiUpdate_TOSW_flag;</span></a>
+<a name="506"><span class="lineNum">     506 </span><span class="lineCov">         36 :       redirect_next_bits_r_cfiUpdate_TOSW_value &lt;= io_redirect_bits_cfiUpdate_TOSW_value;</span></a>
+<a name="507"><span class="lineNum">     507 </span><span class="lineCov">         36 :       redirect_next_bits_r_cfiUpdate_TOSR_flag &lt;= io_redirect_bits_cfiUpdate_TOSR_flag;</span></a>
+<a name="508"><span class="lineNum">     508 </span><span class="lineCov">         36 :       redirect_next_bits_r_cfiUpdate_TOSR_value &lt;= io_redirect_bits_cfiUpdate_TOSR_value;</span></a>
+<a name="509"><span class="lineNum">     509 </span><span class="lineCov">         36 :       redirect_next_bits_r_cfiUpdate_NOS_flag &lt;= io_redirect_bits_cfiUpdate_NOS_flag;</span></a>
+<a name="510"><span class="lineNum">     510 </span><span class="lineCov">         36 :       redirect_next_bits_r_cfiUpdate_NOS_value &lt;= io_redirect_bits_cfiUpdate_NOS_value;</span></a>
+<a name="511"><span class="lineNum">     511 </span>            :     end</a>
+<a name="512"><span class="lineNum">     512 </span>            :   end // always @(posedge)</a>
+<a name="513"><span class="lineNum">     513 </span><span class="lineCov">     127730 :   always @(posedge clock or posedge reset) begin</span></a>
+<a name="514"><span class="lineNum">     514 </span><span class="lineCov">        272 :     if (reset)</span></a>
+<a name="515"><span class="lineNum">     515 </span><span class="lineCov">        136 :       redirect_next_valid_last_r &lt;= 1'h0;</span></a>
+<a name="516"><span class="lineNum">     516 </span><span class="lineCov">        126 :     else if (io_redirect_valid | redirect_next_valid_last_r)</span></a>
+<a name="517"><span class="lineNum">     517 </span><span class="lineCov">         63 :       redirect_next_valid_last_r &lt;= io_redirect_valid;</span></a>
+<a name="518"><span class="lineNum">     518 </span>            :   end // always @(posedge, posedge)</a>
+<a name="519"><span class="lineNum">     519 </span>            :   `ifdef ENABLE_INITIAL_REG_</a>
+<a name="520"><span class="lineNum">     520 </span>            :     `ifdef FIRRTL_BEFORE_INITIAL</a>
+<a name="521"><span class="lineNum">     521 </span>            :       `FIRRTL_BEFORE_INITIAL</a>
+<a name="522"><span class="lineNum">     522 </span>            :     `endif // FIRRTL_BEFORE_INITIAL</a>
+<a name="523"><span class="lineNum">     523 </span>            :     logic [31:0] _RANDOM[0:21];</a>
+<a name="524"><span class="lineNum">     524 </span><span class="lineCov">         58 :     initial begin</span></a>
+<a name="525"><span class="lineNum">     525 </span>            :       `ifdef INIT_RANDOM_PROLOG_</a>
+<a name="526"><span class="lineNum">     526 </span>            :         `INIT_RANDOM_PROLOG_</a>
+<a name="527"><span class="lineNum">     527 </span>            :       `endif // INIT_RANDOM_PROLOG_</a>
+<a name="528"><span class="lineNum">     528 </span>            :       `ifdef RANDOMIZE_REG_INIT</a>
+<a name="529"><span class="lineNum">     529 </span>            :         for (logic [4:0] i = 5'h0; i &lt; 5'h16; i += 5'h1) begin</a>
+<a name="530"><span class="lineNum">     530 </span>            :           _RANDOM[i] = `RANDOM;</a>
+<a name="531"><span class="lineNum">     531 </span>            :         end</a>
+<a name="532"><span class="lineNum">     532 </span>            :         s1_pc_dup_0 = {_RANDOM[5'h0], _RANDOM[5'h1][8:0]};</a>
+<a name="533"><span class="lineNum">     533 </span>            :         s1_pc_dup_1 = {_RANDOM[5'h1][31:9], _RANDOM[5'h2][17:0]};</a>
+<a name="534"><span class="lineNum">     534 </span>            :         s1_pc_dup_2 = {_RANDOM[5'h2][31:18], _RANDOM[5'h3][26:0]};</a>
+<a name="535"><span class="lineNum">     535 </span>            :         s1_pc_dup_3 = {_RANDOM[5'h3][31:27], _RANDOM[5'h4], _RANDOM[5'h5][3:0]};</a>
+<a name="536"><span class="lineNum">     536 </span>            :         s2_pc_dup_0 = {_RANDOM[5'h5][31:4], _RANDOM[5'h6][12:0]};</a>
+<a name="537"><span class="lineNum">     537 </span>            :         s2_pc_dup_1 = {_RANDOM[5'h6][31:13], _RANDOM[5'h7][21:0]};</a>
+<a name="538"><span class="lineNum">     538 </span>            :         s2_pc_dup_2 = {_RANDOM[5'h7][31:22], _RANDOM[5'h8][30:0]};</a>
+<a name="539"><span class="lineNum">     539 </span>            :         s2_pc_dup_3 = {_RANDOM[5'h8][31], _RANDOM[5'h9], _RANDOM[5'hA][7:0]};</a>
+<a name="540"><span class="lineNum">     540 </span>            :         s3_pc_dup_0 = {_RANDOM[5'hA][31:8], _RANDOM[5'hB][16:0]};</a>
+<a name="541"><span class="lineNum">     541 </span>            :         s3_pc_dup_1 = {_RANDOM[5'hB][31:17], _RANDOM[5'hC][25:0]};</a>
+<a name="542"><span class="lineNum">     542 </span>            :         s3_pc_dup_2 = {_RANDOM[5'hC][31:26], _RANDOM[5'hD], _RANDOM[5'hE][2:0]};</a>
+<a name="543"><span class="lineNum">     543 </span>            :         s3_pc_dup_3 = {_RANDOM[5'hE][31:3], _RANDOM[5'hF][11:0]};</a>
+<a name="544"><span class="lineNum">     544 </span>            :         REG = _RANDOM[5'hF][12];</a>
+<a name="545"><span class="lineNum">     545 </span>            :         REG_1 = _RANDOM[5'hF][13];</a>
+<a name="546"><span class="lineNum">     546 </span>            :         s3_top = {_RANDOM[5'hF][31:14], _RANDOM[5'h10][22:0]};</a>
+<a name="547"><span class="lineNum">     547 </span>            :         s3_spec_new_addr = {_RANDOM[5'h10][31:23], _RANDOM[5'h11]};</a>
+<a name="548"><span class="lineNum">     548 </span>            :         s3_pushed_in_s2 = _RANDOM[5'h12][0];</a>
+<a name="549"><span class="lineNum">     549 </span>            :         s3_popped_in_s2 = _RANDOM[5'h12][1];</a>
+<a name="550"><span class="lineNum">     550 </span>            :         s3_meta_ssp = _RANDOM[5'h12][5:2];</a>
+<a name="551"><span class="lineNum">     551 </span>            :         s3_meta_sctr = _RANDOM[5'h12][8:6];</a>
+<a name="552"><span class="lineNum">     552 </span>            :         s3_meta_TOSW_flag = _RANDOM[5'h12][9];</a>
+<a name="553"><span class="lineNum">     553 </span>            :         s3_meta_TOSW_value = _RANDOM[5'h12][14:10];</a>
+<a name="554"><span class="lineNum">     554 </span>            :         s3_meta_TOSR_flag = _RANDOM[5'h12][15];</a>
+<a name="555"><span class="lineNum">     555 </span>            :         s3_meta_TOSR_value = _RANDOM[5'h12][20:16];</a>
+<a name="556"><span class="lineNum">     556 </span>            :         s3_meta_NOS_flag = _RANDOM[5'h12][21];</a>
+<a name="557"><span class="lineNum">     557 </span>            :         s3_meta_NOS_value = _RANDOM[5'h12][26:22];</a>
+<a name="558"><span class="lineNum">     558 </span>            :         redirect_next_valid_last_r = _RANDOM[5'h12][27];</a>
+<a name="559"><span class="lineNum">     559 </span>            :         redirect_next_bits_r_level = _RANDOM[5'h13][17];</a>
+<a name="560"><span class="lineNum">     560 </span>            :         redirect_next_bits_r_cfiUpdate_pc = {_RANDOM[5'h13][31:19], _RANDOM[5'h14][27:0]};</a>
+<a name="561"><span class="lineNum">     561 </span>            :         redirect_next_bits_r_cfiUpdate_pd_isRVC = _RANDOM[5'h14][29];</a>
+<a name="562"><span class="lineNum">     562 </span>            :         redirect_next_bits_r_cfiUpdate_pd_isCall = _RANDOM[5'h15][0];</a>
+<a name="563"><span class="lineNum">     563 </span>            :         redirect_next_bits_r_cfiUpdate_pd_isRet = _RANDOM[5'h15][1];</a>
+<a name="564"><span class="lineNum">     564 </span>            :         redirect_next_bits_r_cfiUpdate_ssp = _RANDOM[5'h15][5:2];</a>
+<a name="565"><span class="lineNum">     565 </span>            :         redirect_next_bits_r_cfiUpdate_sctr = _RANDOM[5'h15][7:6];</a>
+<a name="566"><span class="lineNum">     566 </span>            :         redirect_next_bits_r_cfiUpdate_TOSW_flag = _RANDOM[5'h15][8];</a>
+<a name="567"><span class="lineNum">     567 </span>            :         redirect_next_bits_r_cfiUpdate_TOSW_value = _RANDOM[5'h15][13:9];</a>
+<a name="568"><span class="lineNum">     568 </span>            :         redirect_next_bits_r_cfiUpdate_TOSR_flag = _RANDOM[5'h15][14];</a>
+<a name="569"><span class="lineNum">     569 </span>            :         redirect_next_bits_r_cfiUpdate_TOSR_value = _RANDOM[5'h15][19:15];</a>
+<a name="570"><span class="lineNum">     570 </span>            :         redirect_next_bits_r_cfiUpdate_NOS_flag = _RANDOM[5'h15][20];</a>
+<a name="571"><span class="lineNum">     571 </span>            :         redirect_next_bits_r_cfiUpdate_NOS_value = _RANDOM[5'h15][25:21];</a>
+<a name="572"><span class="lineNum">     572 </span>            :       `endif // RANDOMIZE_REG_INIT</a>
+<a name="573"><span class="lineNum">     573 </span><span class="lineCov">         17 :       if (reset)</span></a>
+<a name="574"><span class="lineNum">     574 </span><span class="lineCov">         12 :         redirect_next_valid_last_r = 1'h0;</span></a>
+<a name="575"><span class="lineNum">     575 </span>            :     end // initial</a>
+<a name="576"><span class="lineNum">     576 </span>            :     `ifdef FIRRTL_AFTER_INITIAL</a>
+<a name="577"><span class="lineNum">     577 </span>            :       `FIRRTL_AFTER_INITIAL</a>
+<a name="578"><span class="lineNum">     578 </span>            :     `endif // FIRRTL_AFTER_INITIAL</a>
+<a name="579"><span class="lineNum">     579 </span>            :   `endif // ENABLE_INITIAL_REG_</a>
+<a name="580"><span class="lineNum">     580 </span>            :   DelayN_2 reset_vector_delay (</a>
+<a name="581"><span class="lineNum">     581 </span>            :     .clock  (clock),</a>
+<a name="582"><span class="lineNum">     582 </span>            :     .io_in  (io_reset_vector),</a>
+<a name="583"><span class="lineNum">     583 </span>            :     .io_out (_reset_vector_delay_io_out)</a>
+<a name="584"><span class="lineNum">     584 </span>            :   );</a>
+<a name="585"><span class="lineNum">     585 </span>            :   RASStack RASStack (</a>
+<a name="586"><span class="lineNum">     586 </span>            :     .clock                       (clock),</a>
+<a name="587"><span class="lineNum">     587 </span>            :     .reset                       (reset),</a>
+<a name="588"><span class="lineNum">     588 </span>            :     .io_spec_push_valid          (s2_spec_push),</a>
+<a name="589"><span class="lineNum">     589 </span>            :     .io_spec_pop_valid           (s2_spec_pop),</a>
+<a name="590"><span class="lineNum">     590 </span>            :     .io_spec_push_addr           (_s2_spec_new_addr_T_1),</a>
+<a name="591"><span class="lineNum">     591 </span>            :     .io_s2_fire                  (io_s2_fire_2),</a>
+<a name="592"><span class="lineNum">     592 </span>            :     .io_s3_fire                  (io_s3_fire_2),</a>
+<a name="593"><span class="lineNum">     593 </span>            :     .io_s3_cancel</a>
+<a name="594"><span class="lineNum">     594 </span>            :       (io_s3_fire_2 &amp; (s3_pushed_in_s2 != s3_push | s3_popped_in_s2 != s3_pop)),</a>
+<a name="595"><span class="lineNum">     595 </span>            :     .io_s3_meta_ssp              (s3_meta_ssp),</a>
+<a name="596"><span class="lineNum">     596 </span>            :     .io_s3_meta_sctr             (s3_meta_sctr),</a>
+<a name="597"><span class="lineNum">     597 </span>            :     .io_s3_meta_TOSW_flag        (s3_meta_TOSW_flag),</a>
+<a name="598"><span class="lineNum">     598 </span>            :     .io_s3_meta_TOSW_value       (s3_meta_TOSW_value),</a>
+<a name="599"><span class="lineNum">     599 </span>            :     .io_s3_meta_TOSR_flag        (s3_meta_TOSR_flag),</a>
+<a name="600"><span class="lineNum">     600 </span>            :     .io_s3_meta_TOSR_value       (s3_meta_TOSR_value),</a>
+<a name="601"><span class="lineNum">     601 </span>            :     .io_s3_meta_NOS_flag         (s3_meta_NOS_flag),</a>
+<a name="602"><span class="lineNum">     602 </span>            :     .io_s3_meta_NOS_value        (s3_meta_NOS_value),</a>
+<a name="603"><span class="lineNum">     603 </span>            :     .io_s3_missed_pop            (s3_pop &amp; ~s3_popped_in_s2),</a>
+<a name="604"><span class="lineNum">     604 </span>            :     .io_s3_missed_push           (s3_push &amp; ~s3_pushed_in_s2),</a>
+<a name="605"><span class="lineNum">     605 </span>            :     .io_s3_pushAddr              (s3_spec_new_addr),</a>
+<a name="606"><span class="lineNum">     606 </span>            :     .io_spec_pop_addr            (_RASStack_io_spec_pop_addr),</a>
+<a name="607"><span class="lineNum">     607 </span>            :     .io_commit_push_valid</a>
+<a name="608"><span class="lineNum">     608 </span>            :       (io_update_valid &amp; io_update_bits_ftb_entry_tailSlot_valid</a>
+<a name="609"><span class="lineNum">     609 </span>            :        &amp; io_update_bits_ftb_entry_isCall &amp; io_update_bits_jmp_taken</a>
+<a name="610"><span class="lineNum">     610 </span>            :        &amp; io_update_bits_cfi_idx_valid &amp; _GEN_1),</a>
+<a name="611"><span class="lineNum">     611 </span>            :     .io_commit_pop_valid</a>
+<a name="612"><span class="lineNum">     612 </span>            :       (io_update_valid &amp; io_update_bits_ftb_entry_tailSlot_valid</a>
+<a name="613"><span class="lineNum">     613 </span>            :        &amp; io_update_bits_ftb_entry_isRet &amp; io_update_bits_jmp_taken</a>
+<a name="614"><span class="lineNum">     614 </span>            :        &amp; io_update_bits_cfi_idx_valid &amp; _GEN_1),</a>
+<a name="615"><span class="lineNum">     615 </span>            :     .io_commit_meta_TOSW_flag    (io_update_bits_meta[17]),</a>
+<a name="616"><span class="lineNum">     616 </span>            :     .io_commit_meta_TOSW_value   (io_update_bits_meta[16:12]),</a>
+<a name="617"><span class="lineNum">     617 </span>            :     .io_commit_meta_ssp          (io_update_bits_meta[24:21]),</a>
+<a name="618"><span class="lineNum">     618 </span>            :     .io_redirect_valid           (redirect_next_valid_last_r),</a>
+<a name="619"><span class="lineNum">     619 </span>            :     .io_redirect_isCall</a>
+<a name="620"><span class="lineNum">     620 </span>            :       (redirect_next_valid_last_r &amp; ~redirect_next_bits_r_level</a>
+<a name="621"><span class="lineNum">     621 </span>            :        &amp; redirect_next_bits_r_cfiUpdate_pd_isCall),</a>
+<a name="622"><span class="lineNum">     622 </span>            :     .io_redirect_isRet</a>
+<a name="623"><span class="lineNum">     623 </span>            :       (redirect_next_valid_last_r &amp; ~redirect_next_bits_r_level</a>
+<a name="624"><span class="lineNum">     624 </span>            :        &amp; redirect_next_bits_r_cfiUpdate_pd_isRet),</a>
+<a name="625"><span class="lineNum">     625 </span>            :     .io_redirect_meta_ssp        (redirect_next_bits_r_cfiUpdate_ssp),</a>
+<a name="626"><span class="lineNum">     626 </span>            :     .io_redirect_meta_sctr       ({1'h0, redirect_next_bits_r_cfiUpdate_sctr}),</a>
+<a name="627"><span class="lineNum">     627 </span>            :     .io_redirect_meta_TOSW_flag  (redirect_next_bits_r_cfiUpdate_TOSW_flag),</a>
+<a name="628"><span class="lineNum">     628 </span>            :     .io_redirect_meta_TOSW_value (redirect_next_bits_r_cfiUpdate_TOSW_value),</a>
+<a name="629"><span class="lineNum">     629 </span>            :     .io_redirect_meta_TOSR_flag  (redirect_next_bits_r_cfiUpdate_TOSR_flag),</a>
+<a name="630"><span class="lineNum">     630 </span>            :     .io_redirect_meta_TOSR_value (redirect_next_bits_r_cfiUpdate_TOSR_value),</a>
+<a name="631"><span class="lineNum">     631 </span>            :     .io_redirect_meta_NOS_flag   (redirect_next_bits_r_cfiUpdate_NOS_flag),</a>
+<a name="632"><span class="lineNum">     632 </span>            :     .io_redirect_meta_NOS_value  (redirect_next_bits_r_cfiUpdate_NOS_value),</a>
+<a name="633"><span class="lineNum">     633 </span>            :     .io_redirect_callAddr</a>
+<a name="634"><span class="lineNum">     634 </span>            :       (41'(redirect_next_bits_r_cfiUpdate_pc</a>
+<a name="635"><span class="lineNum">     635 </span>            :            + {38'h0, redirect_next_bits_r_cfiUpdate_pd_isRVC ? 3'h2 : 3'h4})),</a>
+<a name="636"><span class="lineNum">     636 </span>            :     .io_ssp                      (_RASStack_io_ssp),</a>
+<a name="637"><span class="lineNum">     637 </span>            :     .io_sctr                     (_RASStack_io_sctr),</a>
+<a name="638"><span class="lineNum">     638 </span>            :     .io_TOSR_flag                (_RASStack_io_TOSR_flag),</a>
+<a name="639"><span class="lineNum">     639 </span>            :     .io_TOSR_value               (_RASStack_io_TOSR_value),</a>
+<a name="640"><span class="lineNum">     640 </span>            :     .io_TOSW_flag                (_RASStack_io_TOSW_flag),</a>
+<a name="641"><span class="lineNum">     641 </span>            :     .io_TOSW_value               (_RASStack_io_TOSW_value),</a>
+<a name="642"><span class="lineNum">     642 </span>            :     .io_NOS_flag                 (_RASStack_io_NOS_flag),</a>
+<a name="643"><span class="lineNum">     643 </span>            :     .io_NOS_value                (_RASStack_io_NOS_value)</a>
+<a name="644"><span class="lineNum">     644 </span>            :   );</a>
+<a name="645"><span class="lineNum">     645 </span>            :   assign io_out_s2_pc_0 = s2_pc_dup_0;</a>
+<a name="646"><span class="lineNum">     646 </span>            :   assign io_out_s2_pc_1 = s2_pc_dup_1;</a>
+<a name="647"><span class="lineNum">     647 </span>            :   assign io_out_s2_pc_2 = s2_pc_dup_2;</a>
+<a name="648"><span class="lineNum">     648 </span>            :   assign io_out_s2_pc_3 = s2_pc_dup_3;</a>
+<a name="649"><span class="lineNum">     649 </span>            :   assign io_out_s2_full_pred_0_br_taken_mask_0 =</a>
+<a name="650"><span class="lineNum">     650 </span>            :     io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_0;</a>
+<a name="651"><span class="lineNum">     651 </span>            :   assign io_out_s2_full_pred_0_br_taken_mask_1 =</a>
+<a name="652"><span class="lineNum">     652 </span>            :     io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_1;</a>
+<a name="653"><span class="lineNum">     653 </span>            :   assign io_out_s2_full_pred_0_slot_valids_0 =</a>
+<a name="654"><span class="lineNum">     654 </span>            :     io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_0;</a>
+<a name="655"><span class="lineNum">     655 </span>            :   assign io_out_s2_full_pred_0_slot_valids_1 =</a>
+<a name="656"><span class="lineNum">     656 </span>            :     io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_1;</a>
+<a name="657"><span class="lineNum">     657 </span>            :   assign io_out_s2_full_pred_0_targets_0 = io_in_bits_resp_in_0_s2_full_pred_0_targets_0;</a>
+<a name="658"><span class="lineNum">     658 </span>            :   assign io_out_s2_full_pred_0_targets_1 =</a>
+<a name="659"><span class="lineNum">     659 </span>            :     io_in_bits_resp_in_0_s2_full_pred_2_is_jalr</a>
+<a name="660"><span class="lineNum">     660 </span>            :       ? (_GEN</a>
+<a name="661"><span class="lineNum">     661 </span>            :            ? _RASStack_io_spec_pop_addr</a>
+<a name="662"><span class="lineNum">     662 </span>            :            : io_in_bits_resp_in_0_s2_full_pred_0_jalr_target)</a>
+<a name="663"><span class="lineNum">     663 </span>            :       : io_in_bits_resp_in_0_s2_full_pred_0_targets_1;</a>
+<a name="664"><span class="lineNum">     664 </span>            :   assign io_out_s2_full_pred_0_offsets_0 = io_in_bits_resp_in_0_s2_full_pred_0_offsets_0;</a>
+<a name="665"><span class="lineNum">     665 </span>            :   assign io_out_s2_full_pred_0_offsets_1 = io_in_bits_resp_in_0_s2_full_pred_0_offsets_1;</a>
+<a name="666"><span class="lineNum">     666 </span>            :   assign io_out_s2_full_pred_0_fallThroughAddr =</a>
+<a name="667"><span class="lineNum">     667 </span>            :     io_in_bits_resp_in_0_s2_full_pred_0_fallThroughAddr;</a>
+<a name="668"><span class="lineNum">     668 </span>            :   assign io_out_s2_full_pred_0_is_br_sharing =</a>
+<a name="669"><span class="lineNum">     669 </span>            :     io_in_bits_resp_in_0_s2_full_pred_0_is_br_sharing;</a>
+<a name="670"><span class="lineNum">     670 </span>            :   assign io_out_s2_full_pred_0_hit = io_in_bits_resp_in_0_s2_full_pred_0_hit;</a>
+<a name="671"><span class="lineNum">     671 </span>            :   assign io_out_s2_full_pred_1_br_taken_mask_0 =</a>
+<a name="672"><span class="lineNum">     672 </span>            :     io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_0;</a>
+<a name="673"><span class="lineNum">     673 </span>            :   assign io_out_s2_full_pred_1_br_taken_mask_1 =</a>
+<a name="674"><span class="lineNum">     674 </span>            :     io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_1;</a>
+<a name="675"><span class="lineNum">     675 </span>            :   assign io_out_s2_full_pred_1_slot_valids_0 =</a>
+<a name="676"><span class="lineNum">     676 </span>            :     io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_0;</a>
+<a name="677"><span class="lineNum">     677 </span>            :   assign io_out_s2_full_pred_1_slot_valids_1 =</a>
+<a name="678"><span class="lineNum">     678 </span>            :     io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_1;</a>
+<a name="679"><span class="lineNum">     679 </span>            :   assign io_out_s2_full_pred_1_targets_0 = io_in_bits_resp_in_0_s2_full_pred_1_targets_0;</a>
+<a name="680"><span class="lineNum">     680 </span>            :   assign io_out_s2_full_pred_1_targets_1 =</a>
+<a name="681"><span class="lineNum">     681 </span>            :     io_in_bits_resp_in_0_s2_full_pred_2_is_jalr</a>
+<a name="682"><span class="lineNum">     682 </span>            :       ? (_GEN</a>
+<a name="683"><span class="lineNum">     683 </span>            :            ? _RASStack_io_spec_pop_addr</a>
+<a name="684"><span class="lineNum">     684 </span>            :            : io_in_bits_resp_in_0_s2_full_pred_1_jalr_target)</a>
+<a name="685"><span class="lineNum">     685 </span>            :       : io_in_bits_resp_in_0_s2_full_pred_1_targets_1;</a>
+<a name="686"><span class="lineNum">     686 </span>            :   assign io_out_s2_full_pred_1_offsets_0 = io_in_bits_resp_in_0_s2_full_pred_1_offsets_0;</a>
+<a name="687"><span class="lineNum">     687 </span>            :   assign io_out_s2_full_pred_1_offsets_1 = io_in_bits_resp_in_0_s2_full_pred_1_offsets_1;</a>
+<a name="688"><span class="lineNum">     688 </span>            :   assign io_out_s2_full_pred_1_fallThroughAddr =</a>
+<a name="689"><span class="lineNum">     689 </span>            :     io_in_bits_resp_in_0_s2_full_pred_1_fallThroughAddr;</a>
+<a name="690"><span class="lineNum">     690 </span>            :   assign io_out_s2_full_pred_1_is_br_sharing =</a>
+<a name="691"><span class="lineNum">     691 </span>            :     io_in_bits_resp_in_0_s2_full_pred_1_is_br_sharing;</a>
+<a name="692"><span class="lineNum">     692 </span>            :   assign io_out_s2_full_pred_1_hit = io_in_bits_resp_in_0_s2_full_pred_1_hit;</a>
+<a name="693"><span class="lineNum">     693 </span>            :   assign io_out_s2_full_pred_2_br_taken_mask_0 =</a>
+<a name="694"><span class="lineNum">     694 </span>            :     io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_0;</a>
+<a name="695"><span class="lineNum">     695 </span>            :   assign io_out_s2_full_pred_2_br_taken_mask_1 =</a>
+<a name="696"><span class="lineNum">     696 </span>            :     io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_1;</a>
+<a name="697"><span class="lineNum">     697 </span>            :   assign io_out_s2_full_pred_2_slot_valids_0 =</a>
+<a name="698"><span class="lineNum">     698 </span>            :     io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_0;</a>
+<a name="699"><span class="lineNum">     699 </span>            :   assign io_out_s2_full_pred_2_slot_valids_1 =</a>
+<a name="700"><span class="lineNum">     700 </span>            :     io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_1;</a>
+<a name="701"><span class="lineNum">     701 </span>            :   assign io_out_s2_full_pred_2_targets_0 = io_in_bits_resp_in_0_s2_full_pred_2_targets_0;</a>
+<a name="702"><span class="lineNum">     702 </span>            :   assign io_out_s2_full_pred_2_targets_1 =</a>
+<a name="703"><span class="lineNum">     703 </span>            :     io_in_bits_resp_in_0_s2_full_pred_2_is_jalr</a>
+<a name="704"><span class="lineNum">     704 </span>            :       ? (_GEN</a>
+<a name="705"><span class="lineNum">     705 </span>            :            ? _RASStack_io_spec_pop_addr</a>
+<a name="706"><span class="lineNum">     706 </span>            :            : io_in_bits_resp_in_0_s2_full_pred_2_jalr_target)</a>
+<a name="707"><span class="lineNum">     707 </span>            :       : io_in_bits_resp_in_0_s2_full_pred_2_targets_1;</a>
+<a name="708"><span class="lineNum">     708 </span>            :   assign io_out_s2_full_pred_2_offsets_0 = io_in_bits_resp_in_0_s2_full_pred_2_offsets_0;</a>
+<a name="709"><span class="lineNum">     709 </span>            :   assign io_out_s2_full_pred_2_offsets_1 = io_in_bits_resp_in_0_s2_full_pred_2_offsets_1;</a>
+<a name="710"><span class="lineNum">     710 </span>            :   assign io_out_s2_full_pred_2_fallThroughAddr =</a>
+<a name="711"><span class="lineNum">     711 </span>            :     io_in_bits_resp_in_0_s2_full_pred_2_fallThroughAddr;</a>
+<a name="712"><span class="lineNum">     712 </span>            :   assign io_out_s2_full_pred_2_is_br_sharing =</a>
+<a name="713"><span class="lineNum">     713 </span>            :     io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing;</a>
+<a name="714"><span class="lineNum">     714 </span>            :   assign io_out_s2_full_pred_2_hit = io_in_bits_resp_in_0_s2_full_pred_2_hit;</a>
+<a name="715"><span class="lineNum">     715 </span>            :   assign io_out_s2_full_pred_3_br_taken_mask_0 =</a>
+<a name="716"><span class="lineNum">     716 </span>            :     io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_0;</a>
+<a name="717"><span class="lineNum">     717 </span>            :   assign io_out_s2_full_pred_3_br_taken_mask_1 =</a>
+<a name="718"><span class="lineNum">     718 </span>            :     io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_1;</a>
+<a name="719"><span class="lineNum">     719 </span>            :   assign io_out_s2_full_pred_3_slot_valids_0 =</a>
+<a name="720"><span class="lineNum">     720 </span>            :     io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_0;</a>
+<a name="721"><span class="lineNum">     721 </span>            :   assign io_out_s2_full_pred_3_slot_valids_1 =</a>
+<a name="722"><span class="lineNum">     722 </span>            :     io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_1;</a>
+<a name="723"><span class="lineNum">     723 </span>            :   assign io_out_s2_full_pred_3_targets_0 = io_in_bits_resp_in_0_s2_full_pred_3_targets_0;</a>
+<a name="724"><span class="lineNum">     724 </span>            :   assign io_out_s2_full_pred_3_targets_1 =</a>
+<a name="725"><span class="lineNum">     725 </span>            :     io_in_bits_resp_in_0_s2_full_pred_2_is_jalr</a>
+<a name="726"><span class="lineNum">     726 </span>            :       ? (_GEN</a>
+<a name="727"><span class="lineNum">     727 </span>            :            ? _RASStack_io_spec_pop_addr</a>
+<a name="728"><span class="lineNum">     728 </span>            :            : io_in_bits_resp_in_0_s2_full_pred_3_jalr_target)</a>
+<a name="729"><span class="lineNum">     729 </span>            :       : io_in_bits_resp_in_0_s2_full_pred_3_targets_1;</a>
+<a name="730"><span class="lineNum">     730 </span>            :   assign io_out_s2_full_pred_3_offsets_0 = io_in_bits_resp_in_0_s2_full_pred_3_offsets_0;</a>
+<a name="731"><span class="lineNum">     731 </span>            :   assign io_out_s2_full_pred_3_offsets_1 = io_in_bits_resp_in_0_s2_full_pred_3_offsets_1;</a>
+<a name="732"><span class="lineNum">     732 </span>            :   assign io_out_s2_full_pred_3_fallThroughAddr =</a>
+<a name="733"><span class="lineNum">     733 </span>            :     io_in_bits_resp_in_0_s2_full_pred_3_fallThroughAddr;</a>
+<a name="734"><span class="lineNum">     734 </span>            :   assign io_out_s2_full_pred_3_fallThroughErr =</a>
+<a name="735"><span class="lineNum">     735 </span>            :     io_in_bits_resp_in_0_s2_full_pred_3_fallThroughErr;</a>
+<a name="736"><span class="lineNum">     736 </span>            :   assign io_out_s2_full_pred_3_is_br_sharing =</a>
+<a name="737"><span class="lineNum">     737 </span>            :     io_in_bits_resp_in_0_s2_full_pred_3_is_br_sharing;</a>
+<a name="738"><span class="lineNum">     738 </span>            :   assign io_out_s2_full_pred_3_hit = io_in_bits_resp_in_0_s2_full_pred_3_hit;</a>
+<a name="739"><span class="lineNum">     739 </span>            :   assign io_out_s3_pc_0 = s3_pc_dup_0;</a>
+<a name="740"><span class="lineNum">     740 </span>            :   assign io_out_s3_pc_1 = s3_pc_dup_1;</a>
+<a name="741"><span class="lineNum">     741 </span>            :   assign io_out_s3_pc_2 = s3_pc_dup_2;</a>
+<a name="742"><span class="lineNum">     742 </span>            :   assign io_out_s3_pc_3 = s3_pc_dup_3;</a>
+<a name="743"><span class="lineNum">     743 </span>            :   assign io_out_s3_full_pred_0_br_taken_mask_0 =</a>
+<a name="744"><span class="lineNum">     744 </span>            :     io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_0;</a>
+<a name="745"><span class="lineNum">     745 </span>            :   assign io_out_s3_full_pred_0_br_taken_mask_1 =</a>
+<a name="746"><span class="lineNum">     746 </span>            :     io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_1;</a>
+<a name="747"><span class="lineNum">     747 </span>            :   assign io_out_s3_full_pred_0_slot_valids_0 =</a>
+<a name="748"><span class="lineNum">     748 </span>            :     io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_0;</a>
+<a name="749"><span class="lineNum">     749 </span>            :   assign io_out_s3_full_pred_0_slot_valids_1 =</a>
+<a name="750"><span class="lineNum">     750 </span>            :     io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_1;</a>
+<a name="751"><span class="lineNum">     751 </span>            :   assign io_out_s3_full_pred_0_targets_0 = io_in_bits_resp_in_0_s3_full_pred_0_targets_0;</a>
+<a name="752"><span class="lineNum">     752 </span>            :   assign io_out_s3_full_pred_0_targets_1 =</a>
+<a name="753"><span class="lineNum">     753 </span>            :     io_in_bits_resp_in_0_s3_full_pred_2_is_jalr</a>
+<a name="754"><span class="lineNum">     754 </span>            :       ? (_GEN_0 ? s3_top : io_in_bits_resp_in_0_s3_full_pred_0_jalr_target)</a>
+<a name="755"><span class="lineNum">     755 </span>            :       : io_in_bits_resp_in_0_s3_full_pred_0_targets_1;</a>
+<a name="756"><span class="lineNum">     756 </span>            :   assign io_out_s3_full_pred_0_fallThroughAddr =</a>
+<a name="757"><span class="lineNum">     757 </span>            :     io_in_bits_resp_in_0_s3_full_pred_0_fallThroughAddr;</a>
+<a name="758"><span class="lineNum">     758 </span>            :   assign io_out_s3_full_pred_0_fallThroughErr =</a>
+<a name="759"><span class="lineNum">     759 </span>            :     io_in_bits_resp_in_0_s3_full_pred_0_fallThroughErr;</a>
+<a name="760"><span class="lineNum">     760 </span>            :   assign io_out_s3_full_pred_0_is_br_sharing =</a>
+<a name="761"><span class="lineNum">     761 </span>            :     io_in_bits_resp_in_0_s3_full_pred_0_is_br_sharing;</a>
+<a name="762"><span class="lineNum">     762 </span>            :   assign io_out_s3_full_pred_0_hit = io_in_bits_resp_in_0_s3_full_pred_0_hit;</a>
+<a name="763"><span class="lineNum">     763 </span>            :   assign io_out_s3_full_pred_1_br_taken_mask_0 =</a>
+<a name="764"><span class="lineNum">     764 </span>            :     io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_0;</a>
+<a name="765"><span class="lineNum">     765 </span>            :   assign io_out_s3_full_pred_1_br_taken_mask_1 =</a>
+<a name="766"><span class="lineNum">     766 </span>            :     io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_1;</a>
+<a name="767"><span class="lineNum">     767 </span>            :   assign io_out_s3_full_pred_1_slot_valids_0 =</a>
+<a name="768"><span class="lineNum">     768 </span>            :     io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_0;</a>
+<a name="769"><span class="lineNum">     769 </span>            :   assign io_out_s3_full_pred_1_slot_valids_1 =</a>
+<a name="770"><span class="lineNum">     770 </span>            :     io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_1;</a>
+<a name="771"><span class="lineNum">     771 </span>            :   assign io_out_s3_full_pred_1_targets_0 = io_in_bits_resp_in_0_s3_full_pred_1_targets_0;</a>
+<a name="772"><span class="lineNum">     772 </span>            :   assign io_out_s3_full_pred_1_targets_1 =</a>
+<a name="773"><span class="lineNum">     773 </span>            :     io_in_bits_resp_in_0_s3_full_pred_2_is_jalr</a>
+<a name="774"><span class="lineNum">     774 </span>            :       ? (_GEN_0 ? s3_top : io_in_bits_resp_in_0_s3_full_pred_1_jalr_target)</a>
+<a name="775"><span class="lineNum">     775 </span>            :       : io_in_bits_resp_in_0_s3_full_pred_1_targets_1;</a>
+<a name="776"><span class="lineNum">     776 </span>            :   assign io_out_s3_full_pred_1_fallThroughAddr =</a>
+<a name="777"><span class="lineNum">     777 </span>            :     io_in_bits_resp_in_0_s3_full_pred_1_fallThroughAddr;</a>
+<a name="778"><span class="lineNum">     778 </span>            :   assign io_out_s3_full_pred_1_fallThroughErr =</a>
+<a name="779"><span class="lineNum">     779 </span>            :     io_in_bits_resp_in_0_s3_full_pred_1_fallThroughErr;</a>
+<a name="780"><span class="lineNum">     780 </span>            :   assign io_out_s3_full_pred_1_is_br_sharing =</a>
+<a name="781"><span class="lineNum">     781 </span>            :     io_in_bits_resp_in_0_s3_full_pred_1_is_br_sharing;</a>
+<a name="782"><span class="lineNum">     782 </span>            :   assign io_out_s3_full_pred_1_hit = io_in_bits_resp_in_0_s3_full_pred_1_hit;</a>
+<a name="783"><span class="lineNum">     783 </span>            :   assign io_out_s3_full_pred_2_br_taken_mask_0 =</a>
+<a name="784"><span class="lineNum">     784 </span>            :     io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_0;</a>
+<a name="785"><span class="lineNum">     785 </span>            :   assign io_out_s3_full_pred_2_br_taken_mask_1 =</a>
+<a name="786"><span class="lineNum">     786 </span>            :     io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_1;</a>
+<a name="787"><span class="lineNum">     787 </span>            :   assign io_out_s3_full_pred_2_slot_valids_0 =</a>
+<a name="788"><span class="lineNum">     788 </span>            :     io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_0;</a>
+<a name="789"><span class="lineNum">     789 </span>            :   assign io_out_s3_full_pred_2_slot_valids_1 =</a>
+<a name="790"><span class="lineNum">     790 </span>            :     io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_1;</a>
+<a name="791"><span class="lineNum">     791 </span>            :   assign io_out_s3_full_pred_2_targets_0 = io_in_bits_resp_in_0_s3_full_pred_2_targets_0;</a>
+<a name="792"><span class="lineNum">     792 </span>            :   assign io_out_s3_full_pred_2_targets_1 =</a>
+<a name="793"><span class="lineNum">     793 </span>            :     io_in_bits_resp_in_0_s3_full_pred_2_is_jalr</a>
+<a name="794"><span class="lineNum">     794 </span>            :       ? (_GEN_0 ? s3_top : io_in_bits_resp_in_0_s3_full_pred_2_jalr_target)</a>
+<a name="795"><span class="lineNum">     795 </span>            :       : io_in_bits_resp_in_0_s3_full_pred_2_targets_1;</a>
+<a name="796"><span class="lineNum">     796 </span>            :   assign io_out_s3_full_pred_2_fallThroughAddr =</a>
+<a name="797"><span class="lineNum">     797 </span>            :     io_in_bits_resp_in_0_s3_full_pred_2_fallThroughAddr;</a>
+<a name="798"><span class="lineNum">     798 </span>            :   assign io_out_s3_full_pred_2_fallThroughErr =</a>
+<a name="799"><span class="lineNum">     799 </span>            :     io_in_bits_resp_in_0_s3_full_pred_2_fallThroughErr;</a>
+<a name="800"><span class="lineNum">     800 </span>            :   assign io_out_s3_full_pred_2_is_br_sharing =</a>
+<a name="801"><span class="lineNum">     801 </span>            :     io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing;</a>
+<a name="802"><span class="lineNum">     802 </span>            :   assign io_out_s3_full_pred_2_hit = io_in_bits_resp_in_0_s3_full_pred_2_hit;</a>
+<a name="803"><span class="lineNum">     803 </span>            :   assign io_out_s3_full_pred_3_br_taken_mask_0 =</a>
+<a name="804"><span class="lineNum">     804 </span>            :     io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_0;</a>
+<a name="805"><span class="lineNum">     805 </span>            :   assign io_out_s3_full_pred_3_br_taken_mask_1 =</a>
+<a name="806"><span class="lineNum">     806 </span>            :     io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_1;</a>
+<a name="807"><span class="lineNum">     807 </span>            :   assign io_out_s3_full_pred_3_slot_valids_0 =</a>
+<a name="808"><span class="lineNum">     808 </span>            :     io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_0;</a>
+<a name="809"><span class="lineNum">     809 </span>            :   assign io_out_s3_full_pred_3_slot_valids_1 =</a>
+<a name="810"><span class="lineNum">     810 </span>            :     io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_1;</a>
+<a name="811"><span class="lineNum">     811 </span>            :   assign io_out_s3_full_pred_3_targets_0 = io_in_bits_resp_in_0_s3_full_pred_3_targets_0;</a>
+<a name="812"><span class="lineNum">     812 </span>            :   assign io_out_s3_full_pred_3_targets_1 =</a>
+<a name="813"><span class="lineNum">     813 </span>            :     io_in_bits_resp_in_0_s3_full_pred_2_is_jalr</a>
+<a name="814"><span class="lineNum">     814 </span>            :       ? (_GEN_0 ? s3_top : io_in_bits_resp_in_0_s3_full_pred_3_jalr_target)</a>
+<a name="815"><span class="lineNum">     815 </span>            :       : io_in_bits_resp_in_0_s3_full_pred_3_targets_1;</a>
+<a name="816"><span class="lineNum">     816 </span>            :   assign io_out_s3_full_pred_3_offsets_0 = io_in_bits_resp_in_0_s3_full_pred_3_offsets_0;</a>
+<a name="817"><span class="lineNum">     817 </span>            :   assign io_out_s3_full_pred_3_offsets_1 = io_in_bits_resp_in_0_s3_full_pred_3_offsets_1;</a>
+<a name="818"><span class="lineNum">     818 </span>            :   assign io_out_s3_full_pred_3_fallThroughAddr =</a>
+<a name="819"><span class="lineNum">     819 </span>            :     io_in_bits_resp_in_0_s3_full_pred_3_fallThroughAddr;</a>
+<a name="820"><span class="lineNum">     820 </span>            :   assign io_out_s3_full_pred_3_fallThroughErr =</a>
+<a name="821"><span class="lineNum">     821 </span>            :     io_in_bits_resp_in_0_s3_full_pred_3_fallThroughErr;</a>
+<a name="822"><span class="lineNum">     822 </span>            :   assign io_out_s3_full_pred_3_is_br_sharing =</a>
+<a name="823"><span class="lineNum">     823 </span>            :     io_in_bits_resp_in_0_s3_full_pred_3_is_br_sharing;</a>
+<a name="824"><span class="lineNum">     824 </span>            :   assign io_out_s3_full_pred_3_hit = io_in_bits_resp_in_0_s3_full_pred_3_hit;</a>
+<a name="825"><span class="lineNum">     825 </span>            :   assign io_out_last_stage_meta =</a>
+<a name="826"><span class="lineNum">     826 </span>            :     {198'h0,</a>
+<a name="827"><span class="lineNum">     827 </span>            :      s3_meta_ssp,</a>
+<a name="828"><span class="lineNum">     828 </span>            :      s3_meta_sctr,</a>
+<a name="829"><span class="lineNum">     829 </span>            :      s3_meta_TOSW_flag,</a>
+<a name="830"><span class="lineNum">     830 </span>            :      s3_meta_TOSW_value,</a>
+<a name="831"><span class="lineNum">     831 </span>            :      s3_meta_TOSR_flag,</a>
+<a name="832"><span class="lineNum">     832 </span>            :      s3_meta_TOSR_value,</a>
+<a name="833"><span class="lineNum">     833 </span>            :      s3_meta_NOS_flag,</a>
+<a name="834"><span class="lineNum">     834 </span>            :      s3_meta_NOS_value};</a>
+<a name="835"><span class="lineNum">     835 </span>            :   assign io_out_last_stage_spec_info_ssp = s3_meta_ssp;</a>
+<a name="836"><span class="lineNum">     836 </span>            :   assign io_out_last_stage_spec_info_sctr = s3_meta_sctr[1:0];</a>
+<a name="837"><span class="lineNum">     837 </span>            :   assign io_out_last_stage_spec_info_TOSW_flag = s3_meta_TOSW_flag;</a>
+<a name="838"><span class="lineNum">     838 </span>            :   assign io_out_last_stage_spec_info_TOSW_value = s3_meta_TOSW_value;</a>
+<a name="839"><span class="lineNum">     839 </span>            :   assign io_out_last_stage_spec_info_TOSR_flag = s3_meta_TOSR_flag;</a>
+<a name="840"><span class="lineNum">     840 </span>            :   assign io_out_last_stage_spec_info_TOSR_value = s3_meta_TOSR_value;</a>
+<a name="841"><span class="lineNum">     841 </span>            :   assign io_out_last_stage_spec_info_NOS_flag = s3_meta_NOS_flag;</a>
+<a name="842"><span class="lineNum">     842 </span>            :   assign io_out_last_stage_spec_info_NOS_value = s3_meta_NOS_value;</a>
+<a name="843"><span class="lineNum">     843 </span>            :   assign io_out_last_stage_spec_info_topAddr = s3_top;</a>
+<a name="844"><span class="lineNum">     844 </span>            :   assign io_out_last_stage_ftb_entry_valid =</a>
+<a name="845"><span class="lineNum">     845 </span>            :     io_in_bits_resp_in_0_last_stage_ftb_entry_valid;</a>
+<a name="846"><span class="lineNum">     846 </span>            :   assign io_out_last_stage_ftb_entry_brSlots_0_offset =</a>
+<a name="847"><span class="lineNum">     847 </span>            :     io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_offset;</a>
+<a name="848"><span class="lineNum">     848 </span>            :   assign io_out_last_stage_ftb_entry_brSlots_0_lower =</a>
+<a name="849"><span class="lineNum">     849 </span>            :     io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_lower;</a>
+<a name="850"><span class="lineNum">     850 </span>            :   assign io_out_last_stage_ftb_entry_brSlots_0_tarStat =</a>
+<a name="851"><span class="lineNum">     851 </span>            :     io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_tarStat;</a>
+<a name="852"><span class="lineNum">     852 </span>            :   assign io_out_last_stage_ftb_entry_brSlots_0_sharing =</a>
+<a name="853"><span class="lineNum">     853 </span>            :     io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_sharing;</a>
+<a name="854"><span class="lineNum">     854 </span>            :   assign io_out_last_stage_ftb_entry_brSlots_0_valid =</a>
+<a name="855"><span class="lineNum">     855 </span>            :     io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_valid;</a>
+<a name="856"><span class="lineNum">     856 </span>            :   assign io_out_last_stage_ftb_entry_tailSlot_offset =</a>
+<a name="857"><span class="lineNum">     857 </span>            :     io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_offset;</a>
+<a name="858"><span class="lineNum">     858 </span>            :   assign io_out_last_stage_ftb_entry_tailSlot_lower =</a>
+<a name="859"><span class="lineNum">     859 </span>            :     io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_lower;</a>
+<a name="860"><span class="lineNum">     860 </span>            :   assign io_out_last_stage_ftb_entry_tailSlot_tarStat =</a>
+<a name="861"><span class="lineNum">     861 </span>            :     io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_tarStat;</a>
+<a name="862"><span class="lineNum">     862 </span>            :   assign io_out_last_stage_ftb_entry_tailSlot_sharing =</a>
+<a name="863"><span class="lineNum">     863 </span>            :     io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_sharing;</a>
+<a name="864"><span class="lineNum">     864 </span>            :   assign io_out_last_stage_ftb_entry_tailSlot_valid =</a>
+<a name="865"><span class="lineNum">     865 </span>            :     io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_valid;</a>
+<a name="866"><span class="lineNum">     866 </span>            :   assign io_out_last_stage_ftb_entry_pftAddr =</a>
+<a name="867"><span class="lineNum">     867 </span>            :     io_in_bits_resp_in_0_last_stage_ftb_entry_pftAddr;</a>
+<a name="868"><span class="lineNum">     868 </span>            :   assign io_out_last_stage_ftb_entry_carry =</a>
+<a name="869"><span class="lineNum">     869 </span>            :     io_in_bits_resp_in_0_last_stage_ftb_entry_carry;</a>
+<a name="870"><span class="lineNum">     870 </span>            :   assign io_out_last_stage_ftb_entry_isCall =</a>
+<a name="871"><span class="lineNum">     871 </span>            :     io_in_bits_resp_in_0_last_stage_ftb_entry_isCall;</a>
+<a name="872"><span class="lineNum">     872 </span>            :   assign io_out_last_stage_ftb_entry_isRet =</a>
+<a name="873"><span class="lineNum">     873 </span>            :     io_in_bits_resp_in_0_last_stage_ftb_entry_isRet;</a>
+<a name="874"><span class="lineNum">     874 </span>            :   assign io_out_last_stage_ftb_entry_isJalr =</a>
+<a name="875"><span class="lineNum">     875 </span>            :     io_in_bits_resp_in_0_last_stage_ftb_entry_isJalr;</a>
+<a name="876"><span class="lineNum">     876 </span>            :   assign io_out_last_stage_ftb_entry_last_may_be_rvi_call =</a>
+<a name="877"><span class="lineNum">     877 </span>            :     io_in_bits_resp_in_0_last_stage_ftb_entry_last_may_be_rvi_call;</a>
+<a name="878"><span class="lineNum">     878 </span>            :   assign io_out_last_stage_ftb_entry_always_taken_0 =</a>
+<a name="879"><span class="lineNum">     879 </span>            :     io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_0;</a>
+<a name="880"><span class="lineNum">     880 </span>            :   assign io_out_last_stage_ftb_entry_always_taken_1 =</a>
+<a name="881"><span class="lineNum">     881 </span>            :     io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_1;</a>
+<a name="882"><span class="lineNum">     882 </span>            : endmodule</a>
+<a name="883"><span class="lineNum">     883 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/RASStack.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/RASStack.sv.func-sort-c.html
new file mode 100644
index 0000000..3a3d308
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/RASStack.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/RASStack.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - RASStack.sv<span style="font-size: 80%;"> (<a href="RASStack.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">790</td>
+            <td class="headerCovTableEntry">1205</td>
+            <td class="headerCovTableEntryLo">65.6 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="RASStack.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/RASStack.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/RASStack.sv.func.html
new file mode 100644
index 0000000..0c746f8
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/RASStack.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/RASStack.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - RASStack.sv<span style="font-size: 80%;"> (<a href="RASStack.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">790</td>
+            <td class="headerCovTableEntry">1205</td>
+            <td class="headerCovTableEntryLo">65.6 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="RASStack.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/RASStack.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/RASStack.sv.gcov.html
new file mode 100644
index 0000000..17c7161
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/RASStack.sv.gcov.html
@@ -0,0 +1,2010 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/RASStack.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - RASStack.sv<span style="font-size: 80%;"> (source / <a href="RASStack.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">790</td>
+            <td class="headerCovTableEntry">1205</td>
+            <td class="headerCovTableEntryLo">65.6 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : module RASStack(</a>
+<a name="59"><span class="lineNum">      59 </span><span class="lineCov">     127786 :   input         clock,</span></a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">         62 :   input         reset,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">         16 :   input         io_spec_push_valid,</span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">         16 :   input         io_spec_pop_valid,</span></a>
+<a name="63"><span class="lineNum">      63 </span><span class="lineCov">       9401 :   input  [40:0] io_spec_push_addr,</span></a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">        127 :   input         io_s2_fire,</span></a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">        127 :   input         io_s3_fire,</span></a>
+<a name="66"><span class="lineNum">      66 </span><span class="lineCov">         22 :   input         io_s3_cancel,</span></a>
+<a name="67"><span class="lineNum">      67 </span><span class="lineCov">        156 :   input  [3:0]  io_s3_meta_ssp,</span></a>
+<a name="68"><span class="lineNum">      68 </span><span class="lineCov">        124 :   input  [2:0]  io_s3_meta_sctr,</span></a>
+<a name="69"><span class="lineNum">      69 </span><span class="lineCov">         48 :   input         io_s3_meta_TOSW_flag,</span></a>
+<a name="70"><span class="lineNum">      70 </span><span class="lineCov">        173 :   input  [4:0]  io_s3_meta_TOSW_value,</span></a>
+<a name="71"><span class="lineNum">      71 </span><span class="lineCov">         41 :   input         io_s3_meta_TOSR_flag,</span></a>
+<a name="72"><span class="lineNum">      72 </span><span class="lineCov">        218 :   input  [4:0]  io_s3_meta_TOSR_value,</span></a>
+<a name="73"><span class="lineNum">      73 </span><span class="lineCov">         28 :   input         io_s3_meta_NOS_flag,</span></a>
+<a name="74"><span class="lineNum">      74 </span><span class="lineCov">        172 :   input  [4:0]  io_s3_meta_NOS_value,</span></a>
+<a name="75"><span class="lineNum">      75 </span><span class="lineCov">         10 :   input         io_s3_missed_pop,</span></a>
+<a name="76"><span class="lineNum">      76 </span><span class="lineCov">         19 :   input         io_s3_missed_push,</span></a>
+<a name="77"><span class="lineNum">      77 </span><span class="lineCov">       9375 :   input  [40:0] io_s3_pushAddr,</span></a>
+<a name="78"><span class="lineNum">      78 </span><span class="lineCov">       1235 :   output [40:0] io_spec_pop_addr,</span></a>
+<a name="79"><span class="lineNum">      79 </span><span class="lineCov">         33 :   input         io_commit_push_valid,</span></a>
+<a name="80"><span class="lineNum">      80 </span><span class="lineCov">         29 :   input         io_commit_pop_valid,</span></a>
+<a name="81"><span class="lineNum">      81 </span><span class="lineCov">         34 :   input         io_commit_meta_TOSW_flag,</span></a>
+<a name="82"><span class="lineNum">      82 </span><span class="lineCov">        148 :   input  [4:0]  io_commit_meta_TOSW_value,</span></a>
+<a name="83"><span class="lineNum">      83 </span><span class="lineCov">        100 :   input  [3:0]  io_commit_meta_ssp,</span></a>
+<a name="84"><span class="lineNum">      84 </span><span class="lineCov">         83 :   input         io_redirect_valid,</span></a>
+<a name="85"><span class="lineNum">      85 </span><span class="lineCov">         25 :   input         io_redirect_isCall,</span></a>
+<a name="86"><span class="lineNum">      86 </span><span class="lineCov">         23 :   input         io_redirect_isRet,</span></a>
+<a name="87"><span class="lineNum">      87 </span><span class="lineCov">        106 :   input  [3:0]  io_redirect_meta_ssp,</span></a>
+<a name="88"><span class="lineNum">      88 </span><span class="lineCov">         78 :   input  [2:0]  io_redirect_meta_sctr,</span></a>
+<a name="89"><span class="lineNum">      89 </span><span class="lineCov">         28 :   input         io_redirect_meta_TOSW_flag,</span></a>
+<a name="90"><span class="lineNum">      90 </span><span class="lineCov">        151 :   input  [4:0]  io_redirect_meta_TOSW_value,</span></a>
+<a name="91"><span class="lineNum">      91 </span><span class="lineCov">         32 :   input         io_redirect_meta_TOSR_flag,</span></a>
+<a name="92"><span class="lineNum">      92 </span><span class="lineCov">        132 :   input  [4:0]  io_redirect_meta_TOSR_value,</span></a>
+<a name="93"><span class="lineNum">      93 </span><span class="lineCov">         37 :   input         io_redirect_meta_NOS_flag,</span></a>
+<a name="94"><span class="lineNum">      94 </span><span class="lineCov">        134 :   input  [4:0]  io_redirect_meta_NOS_value,</span></a>
+<a name="95"><span class="lineNum">      95 </span><span class="lineCov">       1100 :   input  [40:0] io_redirect_callAddr,</span></a>
+<a name="96"><span class="lineNum">      96 </span><span class="lineCov">        120 :   output [3:0]  io_ssp,</span></a>
+<a name="97"><span class="lineNum">      97 </span><span class="lineCov">        107 :   output [2:0]  io_sctr,</span></a>
+<a name="98"><span class="lineNum">      98 </span><span class="lineCov">         31 :   output        io_TOSR_flag,</span></a>
+<a name="99"><span class="lineNum">      99 </span><span class="lineCov">        180 :   output [4:0]  io_TOSR_value,</span></a>
+<a name="100"><span class="lineNum">     100 </span><span class="lineCov">         36 :   output        io_TOSW_flag,</span></a>
+<a name="101"><span class="lineNum">     101 </span><span class="lineCov">        174 :   output [4:0]  io_TOSW_value,</span></a>
+<a name="102"><span class="lineNum">     102 </span><span class="lineCov">         29 :   output        io_NOS_flag,</span></a>
+<a name="103"><span class="lineNum">     103 </span><span class="lineCov">        142 :   output [4:0]  io_NOS_value</span></a>
+<a name="104"><span class="lineNum">     104 </span>            : );</a>
+<a name="105"><span class="lineNum">     105 </span>            : </a>
+<a name="106"><span class="lineNum">     106 </span><span class="lineCov">        963 :   reg  [40:0]       commit_stack_0_retAddr;</span></a>
+<a name="107"><span class="lineNum">     107 </span><span class="lineCov">        203 :   reg  [7:0]        commit_stack_0_ctr;</span></a>
+<a name="108"><span class="lineNum">     108 </span><span class="lineCov">        905 :   reg  [40:0]       commit_stack_1_retAddr;</span></a>
+<a name="109"><span class="lineNum">     109 </span><span class="lineCov">        182 :   reg  [7:0]        commit_stack_1_ctr;</span></a>
+<a name="110"><span class="lineNum">     110 </span><span class="lineCov">        967 :   reg  [40:0]       commit_stack_2_retAddr;</span></a>
+<a name="111"><span class="lineNum">     111 </span><span class="lineCov">        192 :   reg  [7:0]        commit_stack_2_ctr;</span></a>
+<a name="112"><span class="lineNum">     112 </span><span class="lineCov">        942 :   reg  [40:0]       commit_stack_3_retAddr;</span></a>
+<a name="113"><span class="lineNum">     113 </span><span class="lineCov">        197 :   reg  [7:0]        commit_stack_3_ctr;</span></a>
+<a name="114"><span class="lineNum">     114 </span><span class="lineCov">        909 :   reg  [40:0]       commit_stack_4_retAddr;</span></a>
+<a name="115"><span class="lineNum">     115 </span><span class="lineCov">        172 :   reg  [7:0]        commit_stack_4_ctr;</span></a>
+<a name="116"><span class="lineNum">     116 </span><span class="lineCov">        965 :   reg  [40:0]       commit_stack_5_retAddr;</span></a>
+<a name="117"><span class="lineNum">     117 </span><span class="lineCov">        180 :   reg  [7:0]        commit_stack_5_ctr;</span></a>
+<a name="118"><span class="lineNum">     118 </span><span class="lineCov">        980 :   reg  [40:0]       commit_stack_6_retAddr;</span></a>
+<a name="119"><span class="lineNum">     119 </span><span class="lineCov">        182 :   reg  [7:0]        commit_stack_6_ctr;</span></a>
+<a name="120"><span class="lineNum">     120 </span><span class="lineCov">        977 :   reg  [40:0]       commit_stack_7_retAddr;</span></a>
+<a name="121"><span class="lineNum">     121 </span><span class="lineCov">        178 :   reg  [7:0]        commit_stack_7_ctr;</span></a>
+<a name="122"><span class="lineNum">     122 </span><span class="lineCov">        950 :   reg  [40:0]       commit_stack_8_retAddr;</span></a>
+<a name="123"><span class="lineNum">     123 </span><span class="lineCov">        176 :   reg  [7:0]        commit_stack_8_ctr;</span></a>
+<a name="124"><span class="lineNum">     124 </span><span class="lineCov">        957 :   reg  [40:0]       commit_stack_9_retAddr;</span></a>
+<a name="125"><span class="lineNum">     125 </span><span class="lineCov">        171 :   reg  [7:0]        commit_stack_9_ctr;</span></a>
+<a name="126"><span class="lineNum">     126 </span><span class="lineCov">        968 :   reg  [40:0]       commit_stack_10_retAddr;</span></a>
+<a name="127"><span class="lineNum">     127 </span><span class="lineCov">        211 :   reg  [7:0]        commit_stack_10_ctr;</span></a>
+<a name="128"><span class="lineNum">     128 </span><span class="lineCov">        939 :   reg  [40:0]       commit_stack_11_retAddr;</span></a>
+<a name="129"><span class="lineNum">     129 </span><span class="lineCov">        164 :   reg  [7:0]        commit_stack_11_ctr;</span></a>
+<a name="130"><span class="lineNum">     130 </span><span class="lineCov">        953 :   reg  [40:0]       commit_stack_12_retAddr;</span></a>
+<a name="131"><span class="lineNum">     131 </span><span class="lineCov">        187 :   reg  [7:0]        commit_stack_12_ctr;</span></a>
+<a name="132"><span class="lineNum">     132 </span><span class="lineCov">        931 :   reg  [40:0]       commit_stack_13_retAddr;</span></a>
+<a name="133"><span class="lineNum">     133 </span><span class="lineCov">        173 :   reg  [7:0]        commit_stack_13_ctr;</span></a>
+<a name="134"><span class="lineNum">     134 </span><span class="lineCov">        933 :   reg  [40:0]       commit_stack_14_retAddr;</span></a>
+<a name="135"><span class="lineNum">     135 </span><span class="lineCov">        187 :   reg  [7:0]        commit_stack_14_ctr;</span></a>
+<a name="136"><span class="lineNum">     136 </span><span class="lineCov">        940 :   reg  [40:0]       commit_stack_15_retAddr;</span></a>
+<a name="137"><span class="lineNum">     137 </span><span class="lineCov">        187 :   reg  [7:0]        commit_stack_15_ctr;</span></a>
+<a name="138"><span class="lineNum">     138 </span><span class="lineCov">        946 :   reg  [40:0]       spec_queue_0_retAddr;</span></a>
+<a name="139"><span class="lineNum">     139 </span><span class="lineCov">        202 :   reg  [7:0]        spec_queue_0_ctr;</span></a>
+<a name="140"><span class="lineNum">     140 </span><span class="lineCov">        974 :   reg  [40:0]       spec_queue_1_retAddr;</span></a>
+<a name="141"><span class="lineNum">     141 </span><span class="lineCov">        169 :   reg  [7:0]        spec_queue_1_ctr;</span></a>
+<a name="142"><span class="lineNum">     142 </span><span class="lineCov">        912 :   reg  [40:0]       spec_queue_2_retAddr;</span></a>
+<a name="143"><span class="lineNum">     143 </span><span class="lineCov">        185 :   reg  [7:0]        spec_queue_2_ctr;</span></a>
+<a name="144"><span class="lineNum">     144 </span><span class="lineCov">        955 :   reg  [40:0]       spec_queue_3_retAddr;</span></a>
+<a name="145"><span class="lineNum">     145 </span><span class="lineCov">        185 :   reg  [7:0]        spec_queue_3_ctr;</span></a>
+<a name="146"><span class="lineNum">     146 </span><span class="lineCov">        946 :   reg  [40:0]       spec_queue_4_retAddr;</span></a>
+<a name="147"><span class="lineNum">     147 </span><span class="lineCov">        184 :   reg  [7:0]        spec_queue_4_ctr;</span></a>
+<a name="148"><span class="lineNum">     148 </span><span class="lineCov">        997 :   reg  [40:0]       spec_queue_5_retAddr;</span></a>
+<a name="149"><span class="lineNum">     149 </span><span class="lineCov">        195 :   reg  [7:0]        spec_queue_5_ctr;</span></a>
+<a name="150"><span class="lineNum">     150 </span><span class="lineCov">        924 :   reg  [40:0]       spec_queue_6_retAddr;</span></a>
+<a name="151"><span class="lineNum">     151 </span><span class="lineCov">        184 :   reg  [7:0]        spec_queue_6_ctr;</span></a>
+<a name="152"><span class="lineNum">     152 </span><span class="lineCov">        956 :   reg  [40:0]       spec_queue_7_retAddr;</span></a>
+<a name="153"><span class="lineNum">     153 </span><span class="lineCov">        172 :   reg  [7:0]        spec_queue_7_ctr;</span></a>
+<a name="154"><span class="lineNum">     154 </span><span class="lineCov">        973 :   reg  [40:0]       spec_queue_8_retAddr;</span></a>
+<a name="155"><span class="lineNum">     155 </span><span class="lineCov">        183 :   reg  [7:0]        spec_queue_8_ctr;</span></a>
+<a name="156"><span class="lineNum">     156 </span><span class="lineCov">        980 :   reg  [40:0]       spec_queue_9_retAddr;</span></a>
+<a name="157"><span class="lineNum">     157 </span><span class="lineCov">        183 :   reg  [7:0]        spec_queue_9_ctr;</span></a>
+<a name="158"><span class="lineNum">     158 </span><span class="lineCov">        943 :   reg  [40:0]       spec_queue_10_retAddr;</span></a>
+<a name="159"><span class="lineNum">     159 </span><span class="lineCov">        172 :   reg  [7:0]        spec_queue_10_ctr;</span></a>
+<a name="160"><span class="lineNum">     160 </span><span class="lineCov">        924 :   reg  [40:0]       spec_queue_11_retAddr;</span></a>
+<a name="161"><span class="lineNum">     161 </span><span class="lineCov">        202 :   reg  [7:0]        spec_queue_11_ctr;</span></a>
+<a name="162"><span class="lineNum">     162 </span><span class="lineCov">        918 :   reg  [40:0]       spec_queue_12_retAddr;</span></a>
+<a name="163"><span class="lineNum">     163 </span><span class="lineCov">        185 :   reg  [7:0]        spec_queue_12_ctr;</span></a>
+<a name="164"><span class="lineNum">     164 </span><span class="lineCov">       1005 :   reg  [40:0]       spec_queue_13_retAddr;</span></a>
+<a name="165"><span class="lineNum">     165 </span><span class="lineCov">        196 :   reg  [7:0]        spec_queue_13_ctr;</span></a>
+<a name="166"><span class="lineNum">     166 </span><span class="lineCov">        958 :   reg  [40:0]       spec_queue_14_retAddr;</span></a>
+<a name="167"><span class="lineNum">     167 </span><span class="lineCov">        192 :   reg  [7:0]        spec_queue_14_ctr;</span></a>
+<a name="168"><span class="lineNum">     168 </span><span class="lineCov">        972 :   reg  [40:0]       spec_queue_15_retAddr;</span></a>
+<a name="169"><span class="lineNum">     169 </span><span class="lineCov">        188 :   reg  [7:0]        spec_queue_15_ctr;</span></a>
+<a name="170"><span class="lineNum">     170 </span><span class="lineCov">        928 :   reg  [40:0]       spec_queue_16_retAddr;</span></a>
+<a name="171"><span class="lineNum">     171 </span><span class="lineCov">        175 :   reg  [7:0]        spec_queue_16_ctr;</span></a>
+<a name="172"><span class="lineNum">     172 </span><span class="lineCov">       1001 :   reg  [40:0]       spec_queue_17_retAddr;</span></a>
+<a name="173"><span class="lineNum">     173 </span><span class="lineCov">        189 :   reg  [7:0]        spec_queue_17_ctr;</span></a>
+<a name="174"><span class="lineNum">     174 </span><span class="lineCov">        968 :   reg  [40:0]       spec_queue_18_retAddr;</span></a>
+<a name="175"><span class="lineNum">     175 </span><span class="lineCov">        177 :   reg  [7:0]        spec_queue_18_ctr;</span></a>
+<a name="176"><span class="lineNum">     176 </span><span class="lineCov">        948 :   reg  [40:0]       spec_queue_19_retAddr;</span></a>
+<a name="177"><span class="lineNum">     177 </span><span class="lineCov">        204 :   reg  [7:0]        spec_queue_19_ctr;</span></a>
+<a name="178"><span class="lineNum">     178 </span><span class="lineCov">        920 :   reg  [40:0]       spec_queue_20_retAddr;</span></a>
+<a name="179"><span class="lineNum">     179 </span><span class="lineCov">        181 :   reg  [7:0]        spec_queue_20_ctr;</span></a>
+<a name="180"><span class="lineNum">     180 </span><span class="lineCov">        941 :   reg  [40:0]       spec_queue_21_retAddr;</span></a>
+<a name="181"><span class="lineNum">     181 </span><span class="lineCov">        192 :   reg  [7:0]        spec_queue_21_ctr;</span></a>
+<a name="182"><span class="lineNum">     182 </span><span class="lineCov">        968 :   reg  [40:0]       spec_queue_22_retAddr;</span></a>
+<a name="183"><span class="lineNum">     183 </span><span class="lineCov">        198 :   reg  [7:0]        spec_queue_22_ctr;</span></a>
+<a name="184"><span class="lineNum">     184 </span><span class="lineCov">        907 :   reg  [40:0]       spec_queue_23_retAddr;</span></a>
+<a name="185"><span class="lineNum">     185 </span><span class="lineCov">        181 :   reg  [7:0]        spec_queue_23_ctr;</span></a>
+<a name="186"><span class="lineNum">     186 </span><span class="lineCov">        942 :   reg  [40:0]       spec_queue_24_retAddr;</span></a>
+<a name="187"><span class="lineNum">     187 </span><span class="lineCov">        201 :   reg  [7:0]        spec_queue_24_ctr;</span></a>
+<a name="188"><span class="lineNum">     188 </span><span class="lineCov">        938 :   reg  [40:0]       spec_queue_25_retAddr;</span></a>
+<a name="189"><span class="lineNum">     189 </span><span class="lineCov">        185 :   reg  [7:0]        spec_queue_25_ctr;</span></a>
+<a name="190"><span class="lineNum">     190 </span><span class="lineCov">        935 :   reg  [40:0]       spec_queue_26_retAddr;</span></a>
+<a name="191"><span class="lineNum">     191 </span><span class="lineCov">        169 :   reg  [7:0]        spec_queue_26_ctr;</span></a>
+<a name="192"><span class="lineNum">     192 </span><span class="lineCov">        959 :   reg  [40:0]       spec_queue_27_retAddr;</span></a>
+<a name="193"><span class="lineNum">     193 </span><span class="lineCov">        189 :   reg  [7:0]        spec_queue_27_ctr;</span></a>
+<a name="194"><span class="lineNum">     194 </span><span class="lineCov">        937 :   reg  [40:0]       spec_queue_28_retAddr;</span></a>
+<a name="195"><span class="lineNum">     195 </span><span class="lineCov">        181 :   reg  [7:0]        spec_queue_28_ctr;</span></a>
+<a name="196"><span class="lineNum">     196 </span><span class="lineCov">        949 :   reg  [40:0]       spec_queue_29_retAddr;</span></a>
+<a name="197"><span class="lineNum">     197 </span><span class="lineCov">        197 :   reg  [7:0]        spec_queue_29_ctr;</span></a>
+<a name="198"><span class="lineNum">     198 </span><span class="lineCov">        957 :   reg  [40:0]       spec_queue_30_retAddr;</span></a>
+<a name="199"><span class="lineNum">     199 </span><span class="lineCov">        180 :   reg  [7:0]        spec_queue_30_ctr;</span></a>
+<a name="200"><span class="lineNum">     200 </span><span class="lineCov">        948 :   reg  [40:0]       spec_queue_31_retAddr;</span></a>
+<a name="201"><span class="lineNum">     201 </span><span class="lineCov">        167 :   reg  [7:0]        spec_queue_31_ctr;</span></a>
+<a name="202"><span class="lineNum">     202 </span><span class="lineCov">         25 :   reg               spec_nos_0_flag;</span></a>
+<a name="203"><span class="lineNum">     203 </span><span class="lineCov">        115 :   reg  [4:0]        spec_nos_0_value;</span></a>
+<a name="204"><span class="lineNum">     204 </span><span class="lineCov">         19 :   reg               spec_nos_1_flag;</span></a>
+<a name="205"><span class="lineNum">     205 </span><span class="lineCov">        106 :   reg  [4:0]        spec_nos_1_value;</span></a>
+<a name="206"><span class="lineNum">     206 </span><span class="lineCov">         27 :   reg               spec_nos_2_flag;</span></a>
+<a name="207"><span class="lineNum">     207 </span><span class="lineCov">        107 :   reg  [4:0]        spec_nos_2_value;</span></a>
+<a name="208"><span class="lineNum">     208 </span><span class="lineCov">         24 :   reg               spec_nos_3_flag;</span></a>
+<a name="209"><span class="lineNum">     209 </span><span class="lineCov">        110 :   reg  [4:0]        spec_nos_3_value;</span></a>
+<a name="210"><span class="lineNum">     210 </span><span class="lineCov">         24 :   reg               spec_nos_4_flag;</span></a>
+<a name="211"><span class="lineNum">     211 </span><span class="lineCov">        116 :   reg  [4:0]        spec_nos_4_value;</span></a>
+<a name="212"><span class="lineNum">     212 </span><span class="lineCov">         25 :   reg               spec_nos_5_flag;</span></a>
+<a name="213"><span class="lineNum">     213 </span><span class="lineCov">        121 :   reg  [4:0]        spec_nos_5_value;</span></a>
+<a name="214"><span class="lineNum">     214 </span><span class="lineCov">         23 :   reg               spec_nos_6_flag;</span></a>
+<a name="215"><span class="lineNum">     215 </span><span class="lineCov">        109 :   reg  [4:0]        spec_nos_6_value;</span></a>
+<a name="216"><span class="lineNum">     216 </span><span class="lineCov">         24 :   reg               spec_nos_7_flag;</span></a>
+<a name="217"><span class="lineNum">     217 </span><span class="lineCov">        117 :   reg  [4:0]        spec_nos_7_value;</span></a>
+<a name="218"><span class="lineNum">     218 </span><span class="lineCov">         19 :   reg               spec_nos_8_flag;</span></a>
+<a name="219"><span class="lineNum">     219 </span><span class="lineCov">        112 :   reg  [4:0]        spec_nos_8_value;</span></a>
+<a name="220"><span class="lineNum">     220 </span><span class="lineCov">         24 :   reg               spec_nos_9_flag;</span></a>
+<a name="221"><span class="lineNum">     221 </span><span class="lineCov">        108 :   reg  [4:0]        spec_nos_9_value;</span></a>
+<a name="222"><span class="lineNum">     222 </span><span class="lineCov">         21 :   reg               spec_nos_10_flag;</span></a>
+<a name="223"><span class="lineNum">     223 </span><span class="lineCov">        115 :   reg  [4:0]        spec_nos_10_value;</span></a>
+<a name="224"><span class="lineNum">     224 </span><span class="lineCov">         23 :   reg               spec_nos_11_flag;</span></a>
+<a name="225"><span class="lineNum">     225 </span><span class="lineCov">        127 :   reg  [4:0]        spec_nos_11_value;</span></a>
+<a name="226"><span class="lineNum">     226 </span><span class="lineCov">         22 :   reg               spec_nos_12_flag;</span></a>
+<a name="227"><span class="lineNum">     227 </span><span class="lineCov">        113 :   reg  [4:0]        spec_nos_12_value;</span></a>
+<a name="228"><span class="lineNum">     228 </span><span class="lineCov">         17 :   reg               spec_nos_13_flag;</span></a>
+<a name="229"><span class="lineNum">     229 </span><span class="lineCov">        122 :   reg  [4:0]        spec_nos_13_value;</span></a>
+<a name="230"><span class="lineNum">     230 </span><span class="lineCov">         22 :   reg               spec_nos_14_flag;</span></a>
+<a name="231"><span class="lineNum">     231 </span><span class="lineCov">        121 :   reg  [4:0]        spec_nos_14_value;</span></a>
+<a name="232"><span class="lineNum">     232 </span><span class="lineCov">         17 :   reg               spec_nos_15_flag;</span></a>
+<a name="233"><span class="lineNum">     233 </span><span class="lineCov">        116 :   reg  [4:0]        spec_nos_15_value;</span></a>
+<a name="234"><span class="lineNum">     234 </span><span class="lineCov">         21 :   reg               spec_nos_16_flag;</span></a>
+<a name="235"><span class="lineNum">     235 </span><span class="lineCov">        116 :   reg  [4:0]        spec_nos_16_value;</span></a>
+<a name="236"><span class="lineNum">     236 </span><span class="lineCov">         26 :   reg               spec_nos_17_flag;</span></a>
+<a name="237"><span class="lineNum">     237 </span><span class="lineCov">        123 :   reg  [4:0]        spec_nos_17_value;</span></a>
+<a name="238"><span class="lineNum">     238 </span><span class="lineCov">         24 :   reg               spec_nos_18_flag;</span></a>
+<a name="239"><span class="lineNum">     239 </span><span class="lineCov">        103 :   reg  [4:0]        spec_nos_18_value;</span></a>
+<a name="240"><span class="lineNum">     240 </span><span class="lineCov">         25 :   reg               spec_nos_19_flag;</span></a>
+<a name="241"><span class="lineNum">     241 </span><span class="lineCov">        109 :   reg  [4:0]        spec_nos_19_value;</span></a>
+<a name="242"><span class="lineNum">     242 </span><span class="lineCov">         19 :   reg               spec_nos_20_flag;</span></a>
+<a name="243"><span class="lineNum">     243 </span><span class="lineCov">        112 :   reg  [4:0]        spec_nos_20_value;</span></a>
+<a name="244"><span class="lineNum">     244 </span><span class="lineCov">         27 :   reg               spec_nos_21_flag;</span></a>
+<a name="245"><span class="lineNum">     245 </span><span class="lineCov">        110 :   reg  [4:0]        spec_nos_21_value;</span></a>
+<a name="246"><span class="lineNum">     246 </span><span class="lineCov">         25 :   reg               spec_nos_22_flag;</span></a>
+<a name="247"><span class="lineNum">     247 </span><span class="lineCov">        129 :   reg  [4:0]        spec_nos_22_value;</span></a>
+<a name="248"><span class="lineNum">     248 </span><span class="lineCov">         24 :   reg               spec_nos_23_flag;</span></a>
+<a name="249"><span class="lineNum">     249 </span><span class="lineCov">        125 :   reg  [4:0]        spec_nos_23_value;</span></a>
+<a name="250"><span class="lineNum">     250 </span><span class="lineCov">         24 :   reg               spec_nos_24_flag;</span></a>
+<a name="251"><span class="lineNum">     251 </span><span class="lineCov">        107 :   reg  [4:0]        spec_nos_24_value;</span></a>
+<a name="252"><span class="lineNum">     252 </span><span class="lineCov">         22 :   reg               spec_nos_25_flag;</span></a>
+<a name="253"><span class="lineNum">     253 </span><span class="lineCov">        121 :   reg  [4:0]        spec_nos_25_value;</span></a>
+<a name="254"><span class="lineNum">     254 </span><span class="lineCov">         23 :   reg               spec_nos_26_flag;</span></a>
+<a name="255"><span class="lineNum">     255 </span><span class="lineCov">        118 :   reg  [4:0]        spec_nos_26_value;</span></a>
+<a name="256"><span class="lineNum">     256 </span><span class="lineCov">         21 :   reg               spec_nos_27_flag;</span></a>
+<a name="257"><span class="lineNum">     257 </span><span class="lineCov">        127 :   reg  [4:0]        spec_nos_27_value;</span></a>
+<a name="258"><span class="lineNum">     258 </span><span class="lineCov">         22 :   reg               spec_nos_28_flag;</span></a>
+<a name="259"><span class="lineNum">     259 </span><span class="lineCov">        125 :   reg  [4:0]        spec_nos_28_value;</span></a>
+<a name="260"><span class="lineNum">     260 </span><span class="lineCov">         24 :   reg               spec_nos_29_flag;</span></a>
+<a name="261"><span class="lineNum">     261 </span><span class="lineCov">        115 :   reg  [4:0]        spec_nos_29_value;</span></a>
+<a name="262"><span class="lineNum">     262 </span><span class="lineCov">         25 :   reg               spec_nos_30_flag;</span></a>
+<a name="263"><span class="lineNum">     263 </span><span class="lineCov">        105 :   reg  [4:0]        spec_nos_30_value;</span></a>
+<a name="264"><span class="lineNum">     264 </span><span class="lineCov">         24 :   reg               spec_nos_31_flag;</span></a>
+<a name="265"><span class="lineNum">     265 </span><span class="lineCov">        115 :   reg  [4:0]        spec_nos_31_value;</span></a>
+<a name="266"><span class="lineNum">     266 </span><span class="lineCov">         89 :   reg  [3:0]        nsp;</span></a>
+<a name="267"><span class="lineNum">     267 </span><span class="lineCov">        120 :   reg  [3:0]        ssp;</span></a>
+<a name="268"><span class="lineNum">     268 </span><span class="lineCov">        107 :   reg  [2:0]        sctr;</span></a>
+<a name="269"><span class="lineNum">     269 </span><span class="lineCov">         31 :   reg               TOSR_flag;</span></a>
+<a name="270"><span class="lineNum">     270 </span><span class="lineCov">        180 :   reg  [4:0]        TOSR_value;</span></a>
+<a name="271"><span class="lineNum">     271 </span><span class="lineCov">         36 :   reg               TOSW_flag;</span></a>
+<a name="272"><span class="lineNum">     272 </span><span class="lineCov">        174 :   reg  [4:0]        TOSW_value;</span></a>
+<a name="273"><span class="lineNum">     273 </span><span class="lineCov">         21 :   reg               BOS_flag;</span></a>
+<a name="274"><span class="lineNum">     274 </span><span class="lineCov">        104 :   reg  [4:0]        BOS_value;</span></a>
+<a name="275"><span class="lineNum">     275 </span><span class="lineCov">         19 :   reg               spec_overflowed;</span></a>
+<a name="276"><span class="lineNum">     276 </span><span class="lineCov">        606 :   reg  [40:0]       writeBypassEntry_retAddr;</span></a>
+<a name="277"><span class="lineNum">     277 </span><span class="lineCov">        103 :   reg  [7:0]        writeBypassEntry_ctr;</span></a>
+<a name="278"><span class="lineNum">     278 </span><span class="lineCov">         13 :   reg               writeBypassNos_flag;</span></a>
+<a name="279"><span class="lineNum">     279 </span><span class="lineCov">         77 :   reg  [4:0]        writeBypassNos_value;</span></a>
+<a name="280"><span class="lineNum">     280 </span><span class="lineCov">         27 :   reg               writeBypassValid;</span></a>
+<a name="281"><span class="lineNum">     281 </span>            :   wire              _realPush_T_4 = io_redirect_valid &amp; io_redirect_isCall;</a>
+<a name="282"><span class="lineNum">     282 </span>            :   wire              _GEN = TOSR_value &gt;= BOS_value;</a>
+<a name="283"><span class="lineNum">     283 </span><span class="lineCov">         28 :   wire              topEntry_inflightValid =</span></a>
+<a name="284"><span class="lineNum">     284 </span>            :     (TOSR_flag ^ BOS_flag ^ _GEN) &amp; (TOSR_flag ^ TOSW_flag ^ TOSR_value &lt; TOSW_value);</a>
+<a name="285"><span class="lineNum">     285 </span>            :   wire [31:0][40:0] _GEN_0 =</a>
+<a name="286"><span class="lineNum">     286 </span>            :     {{spec_queue_31_retAddr},</a>
+<a name="287"><span class="lineNum">     287 </span>            :      {spec_queue_30_retAddr},</a>
+<a name="288"><span class="lineNum">     288 </span>            :      {spec_queue_29_retAddr},</a>
+<a name="289"><span class="lineNum">     289 </span>            :      {spec_queue_28_retAddr},</a>
+<a name="290"><span class="lineNum">     290 </span>            :      {spec_queue_27_retAddr},</a>
+<a name="291"><span class="lineNum">     291 </span>            :      {spec_queue_26_retAddr},</a>
+<a name="292"><span class="lineNum">     292 </span>            :      {spec_queue_25_retAddr},</a>
+<a name="293"><span class="lineNum">     293 </span>            :      {spec_queue_24_retAddr},</a>
+<a name="294"><span class="lineNum">     294 </span>            :      {spec_queue_23_retAddr},</a>
+<a name="295"><span class="lineNum">     295 </span>            :      {spec_queue_22_retAddr},</a>
+<a name="296"><span class="lineNum">     296 </span>            :      {spec_queue_21_retAddr},</a>
+<a name="297"><span class="lineNum">     297 </span>            :      {spec_queue_20_retAddr},</a>
+<a name="298"><span class="lineNum">     298 </span>            :      {spec_queue_19_retAddr},</a>
+<a name="299"><span class="lineNum">     299 </span>            :      {spec_queue_18_retAddr},</a>
+<a name="300"><span class="lineNum">     300 </span>            :      {spec_queue_17_retAddr},</a>
+<a name="301"><span class="lineNum">     301 </span>            :      {spec_queue_16_retAddr},</a>
+<a name="302"><span class="lineNum">     302 </span>            :      {spec_queue_15_retAddr},</a>
+<a name="303"><span class="lineNum">     303 </span>            :      {spec_queue_14_retAddr},</a>
+<a name="304"><span class="lineNum">     304 </span>            :      {spec_queue_13_retAddr},</a>
+<a name="305"><span class="lineNum">     305 </span>            :      {spec_queue_12_retAddr},</a>
+<a name="306"><span class="lineNum">     306 </span>            :      {spec_queue_11_retAddr},</a>
+<a name="307"><span class="lineNum">     307 </span>            :      {spec_queue_10_retAddr},</a>
+<a name="308"><span class="lineNum">     308 </span>            :      {spec_queue_9_retAddr},</a>
+<a name="309"><span class="lineNum">     309 </span>            :      {spec_queue_8_retAddr},</a>
+<a name="310"><span class="lineNum">     310 </span>            :      {spec_queue_7_retAddr},</a>
+<a name="311"><span class="lineNum">     311 </span>            :      {spec_queue_6_retAddr},</a>
+<a name="312"><span class="lineNum">     312 </span>            :      {spec_queue_5_retAddr},</a>
+<a name="313"><span class="lineNum">     313 </span>            :      {spec_queue_4_retAddr},</a>
+<a name="314"><span class="lineNum">     314 </span>            :      {spec_queue_3_retAddr},</a>
+<a name="315"><span class="lineNum">     315 </span>            :      {spec_queue_2_retAddr},</a>
+<a name="316"><span class="lineNum">     316 </span>            :      {spec_queue_1_retAddr},</a>
+<a name="317"><span class="lineNum">     317 </span>            :      {spec_queue_0_retAddr}};</a>
+<a name="318"><span class="lineNum">     318 </span>            :   wire [40:0]       _GEN_1 = _GEN_0[TOSR_value];</a>
+<a name="319"><span class="lineNum">     319 </span>            :   wire [31:0][7:0]  _GEN_2 =</a>
+<a name="320"><span class="lineNum">     320 </span>            :     {{spec_queue_31_ctr},</a>
+<a name="321"><span class="lineNum">     321 </span>            :      {spec_queue_30_ctr},</a>
+<a name="322"><span class="lineNum">     322 </span>            :      {spec_queue_29_ctr},</a>
+<a name="323"><span class="lineNum">     323 </span>            :      {spec_queue_28_ctr},</a>
+<a name="324"><span class="lineNum">     324 </span>            :      {spec_queue_27_ctr},</a>
+<a name="325"><span class="lineNum">     325 </span>            :      {spec_queue_26_ctr},</a>
+<a name="326"><span class="lineNum">     326 </span>            :      {spec_queue_25_ctr},</a>
+<a name="327"><span class="lineNum">     327 </span>            :      {spec_queue_24_ctr},</a>
+<a name="328"><span class="lineNum">     328 </span>            :      {spec_queue_23_ctr},</a>
+<a name="329"><span class="lineNum">     329 </span>            :      {spec_queue_22_ctr},</a>
+<a name="330"><span class="lineNum">     330 </span>            :      {spec_queue_21_ctr},</a>
+<a name="331"><span class="lineNum">     331 </span>            :      {spec_queue_20_ctr},</a>
+<a name="332"><span class="lineNum">     332 </span>            :      {spec_queue_19_ctr},</a>
+<a name="333"><span class="lineNum">     333 </span>            :      {spec_queue_18_ctr},</a>
+<a name="334"><span class="lineNum">     334 </span>            :      {spec_queue_17_ctr},</a>
+<a name="335"><span class="lineNum">     335 </span>            :      {spec_queue_16_ctr},</a>
+<a name="336"><span class="lineNum">     336 </span>            :      {spec_queue_15_ctr},</a>
+<a name="337"><span class="lineNum">     337 </span>            :      {spec_queue_14_ctr},</a>
+<a name="338"><span class="lineNum">     338 </span>            :      {spec_queue_13_ctr},</a>
+<a name="339"><span class="lineNum">     339 </span>            :      {spec_queue_12_ctr},</a>
+<a name="340"><span class="lineNum">     340 </span>            :      {spec_queue_11_ctr},</a>
+<a name="341"><span class="lineNum">     341 </span>            :      {spec_queue_10_ctr},</a>
+<a name="342"><span class="lineNum">     342 </span>            :      {spec_queue_9_ctr},</a>
+<a name="343"><span class="lineNum">     343 </span>            :      {spec_queue_8_ctr},</a>
+<a name="344"><span class="lineNum">     344 </span>            :      {spec_queue_7_ctr},</a>
+<a name="345"><span class="lineNum">     345 </span>            :      {spec_queue_6_ctr},</a>
+<a name="346"><span class="lineNum">     346 </span>            :      {spec_queue_5_ctr},</a>
+<a name="347"><span class="lineNum">     347 </span>            :      {spec_queue_4_ctr},</a>
+<a name="348"><span class="lineNum">     348 </span>            :      {spec_queue_3_ctr},</a>
+<a name="349"><span class="lineNum">     349 </span>            :      {spec_queue_2_ctr},</a>
+<a name="350"><span class="lineNum">     350 </span>            :      {spec_queue_1_ctr},</a>
+<a name="351"><span class="lineNum">     351 </span>            :      {spec_queue_0_ctr}};</a>
+<a name="352"><span class="lineNum">     352 </span>            :   wire [15:0][40:0] _GEN_3 =</a>
+<a name="353"><span class="lineNum">     353 </span>            :     {{commit_stack_15_retAddr},</a>
+<a name="354"><span class="lineNum">     354 </span>            :      {commit_stack_14_retAddr},</a>
+<a name="355"><span class="lineNum">     355 </span>            :      {commit_stack_13_retAddr},</a>
+<a name="356"><span class="lineNum">     356 </span>            :      {commit_stack_12_retAddr},</a>
+<a name="357"><span class="lineNum">     357 </span>            :      {commit_stack_11_retAddr},</a>
+<a name="358"><span class="lineNum">     358 </span>            :      {commit_stack_10_retAddr},</a>
+<a name="359"><span class="lineNum">     359 </span>            :      {commit_stack_9_retAddr},</a>
+<a name="360"><span class="lineNum">     360 </span>            :      {commit_stack_8_retAddr},</a>
+<a name="361"><span class="lineNum">     361 </span>            :      {commit_stack_7_retAddr},</a>
+<a name="362"><span class="lineNum">     362 </span>            :      {commit_stack_6_retAddr},</a>
+<a name="363"><span class="lineNum">     363 </span>            :      {commit_stack_5_retAddr},</a>
+<a name="364"><span class="lineNum">     364 </span>            :      {commit_stack_4_retAddr},</a>
+<a name="365"><span class="lineNum">     365 </span>            :      {commit_stack_3_retAddr},</a>
+<a name="366"><span class="lineNum">     366 </span>            :      {commit_stack_2_retAddr},</a>
+<a name="367"><span class="lineNum">     367 </span>            :      {commit_stack_1_retAddr},</a>
+<a name="368"><span class="lineNum">     368 </span>            :      {commit_stack_0_retAddr}};</a>
+<a name="369"><span class="lineNum">     369 </span>            :   wire [40:0]       _GEN_4 = _GEN_3[ssp];</a>
+<a name="370"><span class="lineNum">     370 </span>            :   wire [15:0][7:0]  _GEN_5 =</a>
+<a name="371"><span class="lineNum">     371 </span>            :     {{commit_stack_15_ctr},</a>
+<a name="372"><span class="lineNum">     372 </span>            :      {commit_stack_14_ctr},</a>
+<a name="373"><span class="lineNum">     373 </span>            :      {commit_stack_13_ctr},</a>
+<a name="374"><span class="lineNum">     374 </span>            :      {commit_stack_12_ctr},</a>
+<a name="375"><span class="lineNum">     375 </span>            :      {commit_stack_11_ctr},</a>
+<a name="376"><span class="lineNum">     376 </span>            :      {commit_stack_10_ctr},</a>
+<a name="377"><span class="lineNum">     377 </span>            :      {commit_stack_9_ctr},</a>
+<a name="378"><span class="lineNum">     378 </span>            :      {commit_stack_8_ctr},</a>
+<a name="379"><span class="lineNum">     379 </span>            :      {commit_stack_7_ctr},</a>
+<a name="380"><span class="lineNum">     380 </span>            :      {commit_stack_6_ctr},</a>
+<a name="381"><span class="lineNum">     381 </span>            :      {commit_stack_5_ctr},</a>
+<a name="382"><span class="lineNum">     382 </span>            :      {commit_stack_4_ctr},</a>
+<a name="383"><span class="lineNum">     383 </span>            :      {commit_stack_3_ctr},</a>
+<a name="384"><span class="lineNum">     384 </span>            :      {commit_stack_2_ctr},</a>
+<a name="385"><span class="lineNum">     385 </span>            :      {commit_stack_1_ctr},</a>
+<a name="386"><span class="lineNum">     386 </span>            :      {commit_stack_0_ctr}};</a>
+<a name="387"><span class="lineNum">     387 </span>            :   wire [31:0]       _GEN_6 =</a>
+<a name="388"><span class="lineNum">     388 </span>            :     {{spec_nos_31_flag},</a>
+<a name="389"><span class="lineNum">     389 </span>            :      {spec_nos_30_flag},</a>
+<a name="390"><span class="lineNum">     390 </span>            :      {spec_nos_29_flag},</a>
+<a name="391"><span class="lineNum">     391 </span>            :      {spec_nos_28_flag},</a>
+<a name="392"><span class="lineNum">     392 </span>            :      {spec_nos_27_flag},</a>
+<a name="393"><span class="lineNum">     393 </span>            :      {spec_nos_26_flag},</a>
+<a name="394"><span class="lineNum">     394 </span>            :      {spec_nos_25_flag},</a>
+<a name="395"><span class="lineNum">     395 </span>            :      {spec_nos_24_flag},</a>
+<a name="396"><span class="lineNum">     396 </span>            :      {spec_nos_23_flag},</a>
+<a name="397"><span class="lineNum">     397 </span>            :      {spec_nos_22_flag},</a>
+<a name="398"><span class="lineNum">     398 </span>            :      {spec_nos_21_flag},</a>
+<a name="399"><span class="lineNum">     399 </span>            :      {spec_nos_20_flag},</a>
+<a name="400"><span class="lineNum">     400 </span>            :      {spec_nos_19_flag},</a>
+<a name="401"><span class="lineNum">     401 </span>            :      {spec_nos_18_flag},</a>
+<a name="402"><span class="lineNum">     402 </span>            :      {spec_nos_17_flag},</a>
+<a name="403"><span class="lineNum">     403 </span>            :      {spec_nos_16_flag},</a>
+<a name="404"><span class="lineNum">     404 </span>            :      {spec_nos_15_flag},</a>
+<a name="405"><span class="lineNum">     405 </span>            :      {spec_nos_14_flag},</a>
+<a name="406"><span class="lineNum">     406 </span>            :      {spec_nos_13_flag},</a>
+<a name="407"><span class="lineNum">     407 </span>            :      {spec_nos_12_flag},</a>
+<a name="408"><span class="lineNum">     408 </span>            :      {spec_nos_11_flag},</a>
+<a name="409"><span class="lineNum">     409 </span>            :      {spec_nos_10_flag},</a>
+<a name="410"><span class="lineNum">     410 </span>            :      {spec_nos_9_flag},</a>
+<a name="411"><span class="lineNum">     411 </span>            :      {spec_nos_8_flag},</a>
+<a name="412"><span class="lineNum">     412 </span>            :      {spec_nos_7_flag},</a>
+<a name="413"><span class="lineNum">     413 </span>            :      {spec_nos_6_flag},</a>
+<a name="414"><span class="lineNum">     414 </span>            :      {spec_nos_5_flag},</a>
+<a name="415"><span class="lineNum">     415 </span>            :      {spec_nos_4_flag},</a>
+<a name="416"><span class="lineNum">     416 </span>            :      {spec_nos_3_flag},</a>
+<a name="417"><span class="lineNum">     417 </span>            :      {spec_nos_2_flag},</a>
+<a name="418"><span class="lineNum">     418 </span>            :      {spec_nos_1_flag},</a>
+<a name="419"><span class="lineNum">     419 </span>            :      {spec_nos_0_flag}};</a>
+<a name="420"><span class="lineNum">     420 </span>            :   wire [31:0][4:0]  _GEN_7 =</a>
+<a name="421"><span class="lineNum">     421 </span>            :     {{spec_nos_31_value},</a>
+<a name="422"><span class="lineNum">     422 </span>            :      {spec_nos_30_value},</a>
+<a name="423"><span class="lineNum">     423 </span>            :      {spec_nos_29_value},</a>
+<a name="424"><span class="lineNum">     424 </span>            :      {spec_nos_28_value},</a>
+<a name="425"><span class="lineNum">     425 </span>            :      {spec_nos_27_value},</a>
+<a name="426"><span class="lineNum">     426 </span>            :      {spec_nos_26_value},</a>
+<a name="427"><span class="lineNum">     427 </span>            :      {spec_nos_25_value},</a>
+<a name="428"><span class="lineNum">     428 </span>            :      {spec_nos_24_value},</a>
+<a name="429"><span class="lineNum">     429 </span>            :      {spec_nos_23_value},</a>
+<a name="430"><span class="lineNum">     430 </span>            :      {spec_nos_22_value},</a>
+<a name="431"><span class="lineNum">     431 </span>            :      {spec_nos_21_value},</a>
+<a name="432"><span class="lineNum">     432 </span>            :      {spec_nos_20_value},</a>
+<a name="433"><span class="lineNum">     433 </span>            :      {spec_nos_19_value},</a>
+<a name="434"><span class="lineNum">     434 </span>            :      {spec_nos_18_value},</a>
+<a name="435"><span class="lineNum">     435 </span>            :      {spec_nos_17_value},</a>
+<a name="436"><span class="lineNum">     436 </span>            :      {spec_nos_16_value},</a>
+<a name="437"><span class="lineNum">     437 </span>            :      {spec_nos_15_value},</a>
+<a name="438"><span class="lineNum">     438 </span>            :      {spec_nos_14_value},</a>
+<a name="439"><span class="lineNum">     439 </span>            :      {spec_nos_13_value},</a>
+<a name="440"><span class="lineNum">     440 </span>            :      {spec_nos_12_value},</a>
+<a name="441"><span class="lineNum">     441 </span>            :      {spec_nos_11_value},</a>
+<a name="442"><span class="lineNum">     442 </span>            :      {spec_nos_10_value},</a>
+<a name="443"><span class="lineNum">     443 </span>            :      {spec_nos_9_value},</a>
+<a name="444"><span class="lineNum">     444 </span>            :      {spec_nos_8_value},</a>
+<a name="445"><span class="lineNum">     445 </span>            :      {spec_nos_7_value},</a>
+<a name="446"><span class="lineNum">     446 </span>            :      {spec_nos_6_value},</a>
+<a name="447"><span class="lineNum">     447 </span>            :      {spec_nos_5_value},</a>
+<a name="448"><span class="lineNum">     448 </span>            :      {spec_nos_4_value},</a>
+<a name="449"><span class="lineNum">     449 </span>            :      {spec_nos_3_value},</a>
+<a name="450"><span class="lineNum">     450 </span>            :      {spec_nos_2_value},</a>
+<a name="451"><span class="lineNum">     451 </span>            :      {spec_nos_1_value},</a>
+<a name="452"><span class="lineNum">     452 </span>            :      {spec_nos_0_value}};</a>
+<a name="453"><span class="lineNum">     453 </span>            :   wire [4:0]        _GEN_8 = _GEN_7[TOSR_value];</a>
+<a name="454"><span class="lineNum">     454 </span><span class="lineCov">         29 :   wire              topNos_flag =</span></a>
+<a name="455"><span class="lineNum">     455 </span>            :     writeBypassValid ? writeBypassNos_flag : _GEN_6[TOSR_value];</a>
+<a name="456"><span class="lineNum">     456 </span><span class="lineCov">        142 :   wire [4:0]        topNos_value = writeBypassValid ? writeBypassNos_value : _GEN_8;</span></a>
+<a name="457"><span class="lineNum">     457 </span><span class="lineCov">         41 :   wire              differentFlag_15 = io_redirect_meta_TOSR_flag ^ BOS_flag;</span></a>
+<a name="458"><span class="lineNum">     458 </span><span class="lineCov">         23 :   wire              compare_15 = io_redirect_meta_TOSR_value &lt; BOS_value;</span></a>
+<a name="459"><span class="lineNum">     459 </span><span class="lineCov">         32 :   wire              differentFlag_16 =</span></a>
+<a name="460"><span class="lineNum">     460 </span>            :     io_redirect_meta_TOSR_flag ^ io_redirect_meta_TOSW_flag;</a>
+<a name="461"><span class="lineNum">     461 </span><span class="lineCov">         27 :   wire              compare_16 =</span></a>
+<a name="462"><span class="lineNum">     462 </span>            :     io_redirect_meta_TOSR_value &lt; io_redirect_meta_TOSW_value;</a>
+<a name="463"><span class="lineNum">     463 </span><span class="lineCov">         32 :   wire              redirectTopEntry_inflightValid =</span></a>
+<a name="464"><span class="lineNum">     464 </span>            :     (differentFlag_15 ^ ~compare_15) &amp; (differentFlag_16 ^ compare_16);</a>
+<a name="465"><span class="lineNum">     465 </span><span class="lineCov">       9630 :   wire [40:0]       writeEntry_retAddr =</span></a>
+<a name="466"><span class="lineNum">     466 </span>            :     _realPush_T_4 ? io_redirect_callAddr : io_spec_push_addr;</a>
+<a name="467"><span class="lineNum">     467 </span>            :   wire              _writeEntry_ctr_T_1 =</a>
+<a name="468"><span class="lineNum">     468 </span>            :     (redirectTopEntry_inflightValid</a>
+<a name="469"><span class="lineNum">     469 </span>            :        ? _GEN_0[io_redirect_meta_TOSR_value]</a>
+<a name="470"><span class="lineNum">     470 </span>            :        : _GEN_3[io_redirect_meta_ssp]) == io_redirect_callAddr;</a>
+<a name="471"><span class="lineNum">     471 </span>            :   wire [2:0]        _sctr_T_12 = 3'(io_redirect_meta_sctr + 3'h1);</a>
+<a name="472"><span class="lineNum">     472 </span>            :   wire              _writeEntry_ctr_T_7 =</a>
+<a name="473"><span class="lineNum">     473 </span>            :     (writeBypassValid</a>
+<a name="474"><span class="lineNum">     474 </span>            :        ? writeBypassEntry_retAddr</a>
+<a name="475"><span class="lineNum">     475 </span>            :        : topEntry_inflightValid ? _GEN_1 : _GEN_4) == io_spec_push_addr;</a>
+<a name="476"><span class="lineNum">     476 </span>            :   wire [2:0]        _sctr_T = 3'(sctr + 3'h1);</a>
+<a name="477"><span class="lineNum">     477 </span><span class="lineCov">       1235 :   reg  [40:0]       timingTop_retAddr;</span></a>
+<a name="478"><span class="lineNum">     478 </span><span class="lineCov">       9381 :   reg  [40:0]       realWriteEntry_next_retAddr;</span></a>
+<a name="479"><span class="lineNum">     479 </span><span class="lineCov">        239 :   reg  [7:0]        realWriteEntry_next_ctr;</span></a>
+<a name="480"><span class="lineNum">     480 </span>            :   wire              _GEN_9 = io_redirect_isCall | ~io_s3_missed_push;</a>
+<a name="481"><span class="lineNum">     481 </span><span class="lineCov">       9410 :   wire [40:0]       realWriteEntry_retAddr =</span></a>
+<a name="482"><span class="lineNum">     482 </span>            :     _GEN_9 ? realWriteEntry_next_retAddr : io_s3_pushAddr;</a>
+<a name="483"><span class="lineNum">     483 </span><span class="lineCov">        193 :   reg  [4:0]        realWriteAddr_next_value;</span></a>
+<a name="484"><span class="lineNum">     484 </span><span class="lineCov">         32 :   reg               realNos_next_flag;</span></a>
+<a name="485"><span class="lineNum">     485 </span><span class="lineCov">        216 :   reg  [4:0]        realNos_next_value;</span></a>
+<a name="486"><span class="lineNum">     486 </span><span class="lineCov">         31 :   reg               realPush_r;</span></a>
+<a name="487"><span class="lineNum">     487 </span><span class="lineCov">         28 :   reg               realPush_REG;</span></a>
+<a name="488"><span class="lineNum">     488 </span><span class="lineCov">         32 :   wire              realPush =</span></a>
+<a name="489"><span class="lineNum">     489 </span>            :     io_s3_fire &amp; (~io_s3_cancel &amp; realPush_r | io_s3_missed_push) | realPush_REG;</a>
+<a name="490"><span class="lineNum">     490 </span>            :   wire              _GEN_10 = _writeEntry_ctr_T_1 &amp; io_redirect_meta_sctr != 3'h7;</a>
+<a name="491"><span class="lineNum">     491 </span>            :   wire              _GEN_11 =</a>
+<a name="492"><span class="lineNum">     492 </span>            :     io_redirect_isRet &amp; (differentFlag_15 ^ ~compare_15)</a>
+<a name="493"><span class="lineNum">     493 </span>            :     &amp; (differentFlag_16 ^ compare_16);</a>
+<a name="494"><span class="lineNum">     494 </span>            :   wire [3:0]        _sctr_T_16 = 4'(io_redirect_meta_ssp - 4'h1);</a>
+<a name="495"><span class="lineNum">     495 </span>            :   wire [3:0]        _sctr_T_8 = 4'(io_s3_meta_ssp - 4'h1);</a>
+<a name="496"><span class="lineNum">     496 </span>            :   wire              _GEN_12 = _writeEntry_ctr_T_7 &amp; sctr != 3'h7;</a>
+<a name="497"><span class="lineNum">     497 </span>            :   wire [3:0]        _sctr_T_4 = 4'(ssp - 4'h1);</a>
+<a name="498"><span class="lineNum">     498 </span><span class="lineCov">         23 :   wire              writeBypassValidWire =</span></a>
+<a name="499"><span class="lineNum">     499 </span>            :     _realPush_T_4 | ~io_redirect_valid</a>
+<a name="500"><span class="lineNum">     500 </span>            :     &amp; (io_s2_fire ? io_spec_push_valid : ~io_s3_fire &amp; writeBypassValid);</a>
+<a name="501"><span class="lineNum">     501 </span><span class="lineCov">         42 :   wire              differentFlag_10 = io_s3_meta_TOSR_flag ^ BOS_flag;</span></a>
+<a name="502"><span class="lineNum">     502 </span><span class="lineCov">         18 :   wire              compare_10 = io_s3_meta_TOSR_value &lt; BOS_value;</span></a>
+<a name="503"><span class="lineNum">     503 </span><span class="lineCov">         53 :   wire              differentFlag_11 = io_s3_meta_TOSR_flag ^ io_s3_meta_TOSW_flag;</span></a>
+<a name="504"><span class="lineNum">     504 </span><span class="lineCov">         41 :   wire              compare_11 = io_s3_meta_TOSR_value &lt; io_s3_meta_TOSW_value;</span></a>
+<a name="505"><span class="lineNum">     505 </span><span class="lineCov">         35 :   wire              s3TopEntry_inflightValid =</span></a>
+<a name="506"><span class="lineNum">     506 </span>            :     (differentFlag_10 ^ ~compare_10) &amp; (differentFlag_11 ^ compare_11);</a>
+<a name="507"><span class="lineNum">     507 </span>            :   wire              _GEN_13 = io_redirect_meta_NOS_value &gt;= BOS_value;</a>
+<a name="508"><span class="lineNum">     508 </span>            :   wire              _GEN_14 = io_redirect_meta_NOS_flag ^ BOS_flag ^ _GEN_13;</a>
+<a name="509"><span class="lineNum">     509 </span>            :   wire              _GEN_15 = topNos_value &gt;= BOS_value;</a>
+<a name="510"><span class="lineNum">     510 </span>            :   wire              _GEN_16 = topNos_flag ^ BOS_flag ^ _GEN_15;</a>
+<a name="511"><span class="lineNum">     511 </span>            :   wire              _GEN_17 = io_s3_meta_NOS_value &gt;= BOS_value;</a>
+<a name="512"><span class="lineNum">     512 </span>            :   wire              _GEN_18 = io_s3_meta_NOS_flag ^ BOS_flag ^ _GEN_17;</a>
+<a name="513"><span class="lineNum">     513 </span>            :   wire              _s3_missPushEntry_ctr_T =</a>
+<a name="514"><span class="lineNum">     514 </span>            :     (s3TopEntry_inflightValid</a>
+<a name="515"><span class="lineNum">     515 </span>            :        ? _GEN_0[io_s3_meta_TOSR_value]</a>
+<a name="516"><span class="lineNum">     516 </span>            :        : _GEN_3[io_s3_meta_ssp]) == io_s3_pushAddr;</a>
+<a name="517"><span class="lineNum">     517 </span>            :   wire [2:0]        _sctr_T_10 = 3'(io_s3_meta_sctr + 3'h1);</a>
+<a name="518"><span class="lineNum">     518 </span><span class="lineCov">        121 :   wire [7:0]        s3_missPushEntry_ctr =</span></a>
+<a name="519"><span class="lineNum">     519 </span>            :     {5'h0,</a>
+<a name="520"><span class="lineNum">     520 </span>            :      _s3_missPushEntry_ctr_T</a>
+<a name="521"><span class="lineNum">     521 </span>            :      &amp; (s3TopEntry_inflightValid</a>
+<a name="522"><span class="lineNum">     522 </span>            :           ? _GEN_2[io_s3_meta_TOSR_value]</a>
+<a name="523"><span class="lineNum">     523 </span>            :           : _GEN_5[io_s3_meta_ssp]) &lt; 8'h7</a>
+<a name="524"><span class="lineNum">     524 </span>            :        ? _sctr_T_10</a>
+<a name="525"><span class="lineNum">     525 </span>            :        : 3'h0};</a>
+<a name="526"><span class="lineNum">     526 </span><span class="lineCov">        185 :   wire [4:0]        realWriteAddr_value =</span></a>
+<a name="527"><span class="lineNum">     527 </span>            :     _GEN_9 ? realWriteAddr_next_value : io_s3_meta_TOSW_value;</a>
+<a name="528"><span class="lineNum">     528 </span><span class="lineCov">         35 :   wire              realNos_flag = _GEN_9 ? realNos_next_flag : io_s3_meta_TOSR_flag;</span></a>
+<a name="529"><span class="lineNum">     529 </span><span class="lineCov">        215 :   wire [4:0]        realNos_value = _GEN_9 ? realNos_next_value : io_s3_meta_TOSR_value;</span></a>
+<a name="530"><span class="lineNum">     530 </span>            :   wire [5:0]        _GEN_19 = {TOSW_flag, TOSW_value};</a>
+<a name="531"><span class="lineNum">     531 </span>            :   wire [5:0]        _GEN_20 = {BOS_flag, BOS_value};</a>
+<a name="532"><span class="lineNum">     532 </span>            :   wire              _GEN_21 =</a>
+<a name="533"><span class="lineNum">     533 </span>            :     io_spec_push_valid &amp; 6'(_GEN_19 + 6'h1) == {BOS_flag, BOS_value};</a>
+<a name="534"><span class="lineNum">     534 </span>            :   wire [5:0]        _GEN_22 = {io_s3_meta_TOSW_flag, io_s3_meta_TOSW_value};</a>
+<a name="535"><span class="lineNum">     535 </span>            :   wire              _GEN_23 = 6'(_GEN_22 + 6'h1) == {BOS_flag, BOS_value};</a>
+<a name="536"><span class="lineNum">     536 </span>            :   wire [7:0]        _GEN_24 = _GEN_5[nsp];</a>
+<a name="537"><span class="lineNum">     537 </span>            :   wire [7:0]        _commit_stack_ctr_T = 8'(_GEN_24 - 8'h1);</a>
+<a name="538"><span class="lineNum">     538 </span>            :   wire              _GEN_25 = io_commit_meta_ssp == 4'h0;</a>
+<a name="539"><span class="lineNum">     539 </span>            :   wire              _GEN_26 = io_commit_pop_valid &amp; (|_GEN_24) &amp; _GEN_25;</a>
+<a name="540"><span class="lineNum">     540 </span>            :   wire              _GEN_27 = io_commit_meta_ssp == 4'h1;</a>
+<a name="541"><span class="lineNum">     541 </span>            :   wire              _GEN_28 = io_commit_pop_valid &amp; (|_GEN_24) &amp; _GEN_27;</a>
+<a name="542"><span class="lineNum">     542 </span>            :   wire              _GEN_29 = io_commit_meta_ssp == 4'h2;</a>
+<a name="543"><span class="lineNum">     543 </span>            :   wire              _GEN_30 = io_commit_pop_valid &amp; (|_GEN_24) &amp; _GEN_29;</a>
+<a name="544"><span class="lineNum">     544 </span>            :   wire              _GEN_31 = io_commit_meta_ssp == 4'h3;</a>
+<a name="545"><span class="lineNum">     545 </span>            :   wire              _GEN_32 = io_commit_pop_valid &amp; (|_GEN_24) &amp; _GEN_31;</a>
+<a name="546"><span class="lineNum">     546 </span>            :   wire              _GEN_33 = io_commit_meta_ssp == 4'h4;</a>
+<a name="547"><span class="lineNum">     547 </span>            :   wire              _GEN_34 = io_commit_pop_valid &amp; (|_GEN_24) &amp; _GEN_33;</a>
+<a name="548"><span class="lineNum">     548 </span>            :   wire              _GEN_35 = io_commit_meta_ssp == 4'h5;</a>
+<a name="549"><span class="lineNum">     549 </span>            :   wire              _GEN_36 = io_commit_pop_valid &amp; (|_GEN_24) &amp; _GEN_35;</a>
+<a name="550"><span class="lineNum">     550 </span>            :   wire              _GEN_37 = io_commit_meta_ssp == 4'h6;</a>
+<a name="551"><span class="lineNum">     551 </span>            :   wire              _GEN_38 = io_commit_pop_valid &amp; (|_GEN_24) &amp; _GEN_37;</a>
+<a name="552"><span class="lineNum">     552 </span>            :   wire              _GEN_39 = io_commit_meta_ssp == 4'h7;</a>
+<a name="553"><span class="lineNum">     553 </span>            :   wire              _GEN_40 = io_commit_pop_valid &amp; (|_GEN_24) &amp; _GEN_39;</a>
+<a name="554"><span class="lineNum">     554 </span>            :   wire              _GEN_41 = io_commit_meta_ssp == 4'h8;</a>
+<a name="555"><span class="lineNum">     555 </span>            :   wire              _GEN_42 = io_commit_pop_valid &amp; (|_GEN_24) &amp; _GEN_41;</a>
+<a name="556"><span class="lineNum">     556 </span>            :   wire              _GEN_43 = io_commit_meta_ssp == 4'h9;</a>
+<a name="557"><span class="lineNum">     557 </span>            :   wire              _GEN_44 = io_commit_pop_valid &amp; (|_GEN_24) &amp; _GEN_43;</a>
+<a name="558"><span class="lineNum">     558 </span>            :   wire              _GEN_45 = io_commit_meta_ssp == 4'hA;</a>
+<a name="559"><span class="lineNum">     559 </span>            :   wire              _GEN_46 = io_commit_pop_valid &amp; (|_GEN_24) &amp; _GEN_45;</a>
+<a name="560"><span class="lineNum">     560 </span>            :   wire              _GEN_47 = io_commit_meta_ssp == 4'hB;</a>
+<a name="561"><span class="lineNum">     561 </span>            :   wire              _GEN_48 = io_commit_pop_valid &amp; (|_GEN_24) &amp; _GEN_47;</a>
+<a name="562"><span class="lineNum">     562 </span>            :   wire              _GEN_49 = io_commit_meta_ssp == 4'hC;</a>
+<a name="563"><span class="lineNum">     563 </span>            :   wire              _GEN_50 = io_commit_pop_valid &amp; (|_GEN_24) &amp; _GEN_49;</a>
+<a name="564"><span class="lineNum">     564 </span>            :   wire              _GEN_51 = io_commit_meta_ssp == 4'hD;</a>
+<a name="565"><span class="lineNum">     565 </span>            :   wire              _GEN_52 = io_commit_pop_valid &amp; (|_GEN_24) &amp; _GEN_51;</a>
+<a name="566"><span class="lineNum">     566 </span>            :   wire              _GEN_53 = io_commit_meta_ssp == 4'hE;</a>
+<a name="567"><span class="lineNum">     567 </span>            :   wire              _GEN_54 = io_commit_pop_valid &amp; (|_GEN_24) &amp; _GEN_53;</a>
+<a name="568"><span class="lineNum">     568 </span>            :   wire              _GEN_55 = io_commit_pop_valid &amp; (|_GEN_24) &amp; (&amp;io_commit_meta_ssp);</a>
+<a name="569"><span class="lineNum">     569 </span>            :   wire              _GEN_56 =</a>
+<a name="570"><span class="lineNum">     570 </span>            :     _GEN_24 &lt; 8'h7 &amp; _GEN_3[nsp] == _GEN_0[io_commit_meta_TOSW_value];</a>
+<a name="571"><span class="lineNum">     571 </span>            :   wire [3:0]        _nsp_T_2 = 4'(io_commit_meta_ssp + 4'h1);</a>
+<a name="572"><span class="lineNum">     572 </span>            :   wire              _GEN_57 = _nsp_T_2 == 4'h0;</a>
+<a name="573"><span class="lineNum">     573 </span>            :   wire              _GEN_58 = _nsp_T_2 == 4'h1;</a>
+<a name="574"><span class="lineNum">     574 </span>            :   wire              _GEN_59 = _nsp_T_2 == 4'h2;</a>
+<a name="575"><span class="lineNum">     575 </span>            :   wire              _GEN_60 = _nsp_T_2 == 4'h3;</a>
+<a name="576"><span class="lineNum">     576 </span>            :   wire              _GEN_61 = _nsp_T_2 == 4'h4;</a>
+<a name="577"><span class="lineNum">     577 </span>            :   wire              _GEN_62 = _nsp_T_2 == 4'h5;</a>
+<a name="578"><span class="lineNum">     578 </span>            :   wire              _GEN_63 = _nsp_T_2 == 4'h6;</a>
+<a name="579"><span class="lineNum">     579 </span>            :   wire              _GEN_64 = _nsp_T_2 == 4'h7;</a>
+<a name="580"><span class="lineNum">     580 </span>            :   wire              _GEN_65 = _nsp_T_2 == 4'h8;</a>
+<a name="581"><span class="lineNum">     581 </span>            :   wire              _GEN_66 = _nsp_T_2 == 4'h9;</a>
+<a name="582"><span class="lineNum">     582 </span>            :   wire              _GEN_67 = _nsp_T_2 == 4'hA;</a>
+<a name="583"><span class="lineNum">     583 </span>            :   wire              _GEN_68 = _nsp_T_2 == 4'hB;</a>
+<a name="584"><span class="lineNum">     584 </span>            :   wire              _GEN_69 = _nsp_T_2 == 4'hC;</a>
+<a name="585"><span class="lineNum">     585 </span>            :   wire              _GEN_70 = _nsp_T_2 == 4'hD;</a>
+<a name="586"><span class="lineNum">     586 </span>            :   wire              _GEN_71 = _nsp_T_2 == 4'hE;</a>
+<a name="587"><span class="lineNum">     587 </span>            :   wire [5:0]        _GEN_72 = {io_commit_meta_TOSW_flag, io_commit_meta_TOSW_value};</a>
+<a name="588"><span class="lineNum">     588 </span>            :   wire [5:0]        _new_ptr_T_11 = 6'(_GEN_72 + 6'h1);</a>
+<a name="589"><span class="lineNum">     589 </span>            :   wire              _GEN_73 =</a>
+<a name="590"><span class="lineNum">     590 </span>            :     io_commit_push_valid</a>
+<a name="591"><span class="lineNum">     591 </span>            :     &amp; (~spec_overflowed | _new_ptr_T_11[5] ^ BOS_flag ^ _new_ptr_T_11[4:0] &gt; BOS_value);</a>
+<a name="592"><span class="lineNum">     592 </span>            :   wire [5:0]        _GEN_74 = {io_redirect_meta_TOSW_flag, io_redirect_meta_TOSW_value};</a>
+<a name="593"><span class="lineNum">     593 </span>            :   wire              _GEN_75 =</a>
+<a name="594"><span class="lineNum">     594 </span>            :     io_redirect_valid &amp; io_redirect_isCall &amp; 6'(_GEN_74 + 6'h1) == {BOS_flag, BOS_value};</a>
+<a name="595"><span class="lineNum">     595 </span>            :   wire [7:0]        _commit_stack_ctr_T_2 = 8'(_GEN_24 + 8'h1);</a>
+<a name="596"><span class="lineNum">     596 </span>            :   wire [5:0]        _GEN_76 = 6'(_GEN_74 + 6'h1);</a>
+<a name="597"><span class="lineNum">     597 </span><span class="lineCov">         19 :   wire              inflightValid_8 =</span></a>
+<a name="598"><span class="lineNum">     598 </span>            :     _GEN_14</a>
+<a name="599"><span class="lineNum">     599 </span>            :     &amp; (io_redirect_meta_NOS_flag ^ io_redirect_meta_TOSW_flag</a>
+<a name="600"><span class="lineNum">     600 </span>            :        ^ io_redirect_meta_NOS_value &lt; io_redirect_meta_TOSW_value);</a>
+<a name="601"><span class="lineNum">     601 </span>            :   wire              _GEN_77 =</a>
+<a name="602"><span class="lineNum">     602 </span>            :     io_s3_missed_pop &amp; (differentFlag_10 ^ ~compare_10) &amp; (differentFlag_11 ^ compare_11);</a>
+<a name="603"><span class="lineNum">     603 </span><span class="lineCov">         25 :   wire              inflightValid_6 =</span></a>
+<a name="604"><span class="lineNum">     604 </span>            :     _GEN_18</a>
+<a name="605"><span class="lineNum">     605 </span>            :     &amp; (io_s3_meta_NOS_flag ^ io_s3_meta_TOSW_flag</a>
+<a name="606"><span class="lineNum">     606 </span>            :        ^ io_s3_meta_NOS_value &lt; io_s3_meta_TOSW_value);</a>
+<a name="607"><span class="lineNum">     607 </span>            :   wire [5:0]        _GEN_78 = 6'(_GEN_22 + 6'h1);</a>
+<a name="608"><span class="lineNum">     608 </span>            :   wire              _GEN_79 = _s3_missPushEntry_ctr_T &amp; io_s3_meta_sctr != 3'h7;</a>
+<a name="609"><span class="lineNum">     609 </span><span class="lineCov">         24 :   wire              inflightValid_4 =</span></a>
+<a name="610"><span class="lineNum">     610 </span>            :     _GEN_16 &amp; (topNos_flag ^ TOSW_flag ^ topNos_value &lt; TOSW_value);</a>
+<a name="611"><span class="lineNum">     611 </span>            :   wire [5:0]        _GEN_80 = 6'(_GEN_19 + 6'h1);</a>
+<a name="612"><span class="lineNum">     612 </span>            :   wire [5:0]        _BOS_new_ptr_T_16 = 6'(_GEN_20 + 6'h1);</a>
+<a name="613"><span class="lineNum">     613 </span>            :   wire [5:0]        _BOS_new_ptr_T_11 = 6'(_GEN_72 + 6'h1);</a>
+<a name="614"><span class="lineNum">     614 </span>            :   wire [5:0]        _BOS_new_ptr_T_6 = 6'(_GEN_20 + 6'h1);</a>
+<a name="615"><span class="lineNum">     615 </span>            :   wire [5:0]        _BOS_new_ptr_T_1 = 6'(_GEN_20 + 6'h1);</a>
+<a name="616"><span class="lineNum">     616 </span><span class="lineCov">     127730 :   always @(posedge clock or posedge reset) begin</span></a>
+<a name="617"><span class="lineNum">     617 </span><span class="lineCov">        272 :     if (reset) begin</span></a>
+<a name="618"><span class="lineNum">     618 </span><span class="lineCov">        136 :       commit_stack_0_retAddr &lt;= 41'h0;</span></a>
+<a name="619"><span class="lineNum">     619 </span><span class="lineCov">        136 :       commit_stack_0_ctr &lt;= 8'h0;</span></a>
+<a name="620"><span class="lineNum">     620 </span><span class="lineCov">        136 :       commit_stack_1_retAddr &lt;= 41'h0;</span></a>
+<a name="621"><span class="lineNum">     621 </span><span class="lineCov">        136 :       commit_stack_1_ctr &lt;= 8'h0;</span></a>
+<a name="622"><span class="lineNum">     622 </span><span class="lineCov">        136 :       commit_stack_2_retAddr &lt;= 41'h0;</span></a>
+<a name="623"><span class="lineNum">     623 </span><span class="lineCov">        136 :       commit_stack_2_ctr &lt;= 8'h0;</span></a>
+<a name="624"><span class="lineNum">     624 </span><span class="lineCov">        136 :       commit_stack_3_retAddr &lt;= 41'h0;</span></a>
+<a name="625"><span class="lineNum">     625 </span><span class="lineCov">        136 :       commit_stack_3_ctr &lt;= 8'h0;</span></a>
+<a name="626"><span class="lineNum">     626 </span><span class="lineCov">        136 :       commit_stack_4_retAddr &lt;= 41'h0;</span></a>
+<a name="627"><span class="lineNum">     627 </span><span class="lineCov">        136 :       commit_stack_4_ctr &lt;= 8'h0;</span></a>
+<a name="628"><span class="lineNum">     628 </span><span class="lineCov">        136 :       commit_stack_5_retAddr &lt;= 41'h0;</span></a>
+<a name="629"><span class="lineNum">     629 </span><span class="lineCov">        136 :       commit_stack_5_ctr &lt;= 8'h0;</span></a>
+<a name="630"><span class="lineNum">     630 </span><span class="lineCov">        136 :       commit_stack_6_retAddr &lt;= 41'h0;</span></a>
+<a name="631"><span class="lineNum">     631 </span><span class="lineCov">        136 :       commit_stack_6_ctr &lt;= 8'h0;</span></a>
+<a name="632"><span class="lineNum">     632 </span><span class="lineCov">        136 :       commit_stack_7_retAddr &lt;= 41'h0;</span></a>
+<a name="633"><span class="lineNum">     633 </span><span class="lineCov">        136 :       commit_stack_7_ctr &lt;= 8'h0;</span></a>
+<a name="634"><span class="lineNum">     634 </span><span class="lineCov">        136 :       commit_stack_8_retAddr &lt;= 41'h0;</span></a>
+<a name="635"><span class="lineNum">     635 </span><span class="lineCov">        136 :       commit_stack_8_ctr &lt;= 8'h0;</span></a>
+<a name="636"><span class="lineNum">     636 </span><span class="lineCov">        136 :       commit_stack_9_retAddr &lt;= 41'h0;</span></a>
+<a name="637"><span class="lineNum">     637 </span><span class="lineCov">        136 :       commit_stack_9_ctr &lt;= 8'h0;</span></a>
+<a name="638"><span class="lineNum">     638 </span><span class="lineCov">        136 :       commit_stack_10_retAddr &lt;= 41'h0;</span></a>
+<a name="639"><span class="lineNum">     639 </span><span class="lineCov">        136 :       commit_stack_10_ctr &lt;= 8'h0;</span></a>
+<a name="640"><span class="lineNum">     640 </span><span class="lineCov">        136 :       commit_stack_11_retAddr &lt;= 41'h0;</span></a>
+<a name="641"><span class="lineNum">     641 </span><span class="lineCov">        136 :       commit_stack_11_ctr &lt;= 8'h0;</span></a>
+<a name="642"><span class="lineNum">     642 </span><span class="lineCov">        136 :       commit_stack_12_retAddr &lt;= 41'h0;</span></a>
+<a name="643"><span class="lineNum">     643 </span><span class="lineCov">        136 :       commit_stack_12_ctr &lt;= 8'h0;</span></a>
+<a name="644"><span class="lineNum">     644 </span><span class="lineCov">        136 :       commit_stack_13_retAddr &lt;= 41'h0;</span></a>
+<a name="645"><span class="lineNum">     645 </span><span class="lineCov">        136 :       commit_stack_13_ctr &lt;= 8'h0;</span></a>
+<a name="646"><span class="lineNum">     646 </span><span class="lineCov">        136 :       commit_stack_14_retAddr &lt;= 41'h0;</span></a>
+<a name="647"><span class="lineNum">     647 </span><span class="lineCov">        136 :       commit_stack_14_ctr &lt;= 8'h0;</span></a>
+<a name="648"><span class="lineNum">     648 </span><span class="lineCov">        136 :       commit_stack_15_retAddr &lt;= 41'h0;</span></a>
+<a name="649"><span class="lineNum">     649 </span><span class="lineCov">        136 :       commit_stack_15_ctr &lt;= 8'h0;</span></a>
+<a name="650"><span class="lineNum">     650 </span><span class="lineCov">        136 :       spec_queue_0_retAddr &lt;= 41'h0;</span></a>
+<a name="651"><span class="lineNum">     651 </span><span class="lineCov">        136 :       spec_queue_0_ctr &lt;= 8'h0;</span></a>
+<a name="652"><span class="lineNum">     652 </span><span class="lineCov">        136 :       spec_queue_1_retAddr &lt;= 41'h0;</span></a>
+<a name="653"><span class="lineNum">     653 </span><span class="lineCov">        136 :       spec_queue_1_ctr &lt;= 8'h0;</span></a>
+<a name="654"><span class="lineNum">     654 </span><span class="lineCov">        136 :       spec_queue_2_retAddr &lt;= 41'h0;</span></a>
+<a name="655"><span class="lineNum">     655 </span><span class="lineCov">        136 :       spec_queue_2_ctr &lt;= 8'h0;</span></a>
+<a name="656"><span class="lineNum">     656 </span><span class="lineCov">        136 :       spec_queue_3_retAddr &lt;= 41'h0;</span></a>
+<a name="657"><span class="lineNum">     657 </span><span class="lineCov">        136 :       spec_queue_3_ctr &lt;= 8'h0;</span></a>
+<a name="658"><span class="lineNum">     658 </span><span class="lineCov">        136 :       spec_queue_4_retAddr &lt;= 41'h0;</span></a>
+<a name="659"><span class="lineNum">     659 </span><span class="lineCov">        136 :       spec_queue_4_ctr &lt;= 8'h0;</span></a>
+<a name="660"><span class="lineNum">     660 </span><span class="lineCov">        136 :       spec_queue_5_retAddr &lt;= 41'h0;</span></a>
+<a name="661"><span class="lineNum">     661 </span><span class="lineCov">        136 :       spec_queue_5_ctr &lt;= 8'h0;</span></a>
+<a name="662"><span class="lineNum">     662 </span><span class="lineCov">        136 :       spec_queue_6_retAddr &lt;= 41'h0;</span></a>
+<a name="663"><span class="lineNum">     663 </span><span class="lineCov">        136 :       spec_queue_6_ctr &lt;= 8'h0;</span></a>
+<a name="664"><span class="lineNum">     664 </span><span class="lineCov">        136 :       spec_queue_7_retAddr &lt;= 41'h0;</span></a>
+<a name="665"><span class="lineNum">     665 </span><span class="lineCov">        136 :       spec_queue_7_ctr &lt;= 8'h0;</span></a>
+<a name="666"><span class="lineNum">     666 </span><span class="lineCov">        136 :       spec_queue_8_retAddr &lt;= 41'h0;</span></a>
+<a name="667"><span class="lineNum">     667 </span><span class="lineCov">        136 :       spec_queue_8_ctr &lt;= 8'h0;</span></a>
+<a name="668"><span class="lineNum">     668 </span><span class="lineCov">        136 :       spec_queue_9_retAddr &lt;= 41'h0;</span></a>
+<a name="669"><span class="lineNum">     669 </span><span class="lineCov">        136 :       spec_queue_9_ctr &lt;= 8'h0;</span></a>
+<a name="670"><span class="lineNum">     670 </span><span class="lineCov">        136 :       spec_queue_10_retAddr &lt;= 41'h0;</span></a>
+<a name="671"><span class="lineNum">     671 </span><span class="lineCov">        136 :       spec_queue_10_ctr &lt;= 8'h0;</span></a>
+<a name="672"><span class="lineNum">     672 </span><span class="lineCov">        136 :       spec_queue_11_retAddr &lt;= 41'h0;</span></a>
+<a name="673"><span class="lineNum">     673 </span><span class="lineCov">        136 :       spec_queue_11_ctr &lt;= 8'h0;</span></a>
+<a name="674"><span class="lineNum">     674 </span><span class="lineCov">        136 :       spec_queue_12_retAddr &lt;= 41'h0;</span></a>
+<a name="675"><span class="lineNum">     675 </span><span class="lineCov">        136 :       spec_queue_12_ctr &lt;= 8'h0;</span></a>
+<a name="676"><span class="lineNum">     676 </span><span class="lineCov">        136 :       spec_queue_13_retAddr &lt;= 41'h0;</span></a>
+<a name="677"><span class="lineNum">     677 </span><span class="lineCov">        136 :       spec_queue_13_ctr &lt;= 8'h0;</span></a>
+<a name="678"><span class="lineNum">     678 </span><span class="lineCov">        136 :       spec_queue_14_retAddr &lt;= 41'h0;</span></a>
+<a name="679"><span class="lineNum">     679 </span><span class="lineCov">        136 :       spec_queue_14_ctr &lt;= 8'h0;</span></a>
+<a name="680"><span class="lineNum">     680 </span><span class="lineCov">        136 :       spec_queue_15_retAddr &lt;= 41'h0;</span></a>
+<a name="681"><span class="lineNum">     681 </span><span class="lineCov">        136 :       spec_queue_15_ctr &lt;= 8'h0;</span></a>
+<a name="682"><span class="lineNum">     682 </span><span class="lineCov">        136 :       spec_queue_16_retAddr &lt;= 41'h0;</span></a>
+<a name="683"><span class="lineNum">     683 </span><span class="lineCov">        136 :       spec_queue_16_ctr &lt;= 8'h0;</span></a>
+<a name="684"><span class="lineNum">     684 </span><span class="lineCov">        136 :       spec_queue_17_retAddr &lt;= 41'h0;</span></a>
+<a name="685"><span class="lineNum">     685 </span><span class="lineCov">        136 :       spec_queue_17_ctr &lt;= 8'h0;</span></a>
+<a name="686"><span class="lineNum">     686 </span><span class="lineCov">        136 :       spec_queue_18_retAddr &lt;= 41'h0;</span></a>
+<a name="687"><span class="lineNum">     687 </span><span class="lineCov">        136 :       spec_queue_18_ctr &lt;= 8'h0;</span></a>
+<a name="688"><span class="lineNum">     688 </span><span class="lineCov">        136 :       spec_queue_19_retAddr &lt;= 41'h0;</span></a>
+<a name="689"><span class="lineNum">     689 </span><span class="lineCov">        136 :       spec_queue_19_ctr &lt;= 8'h0;</span></a>
+<a name="690"><span class="lineNum">     690 </span><span class="lineCov">        136 :       spec_queue_20_retAddr &lt;= 41'h0;</span></a>
+<a name="691"><span class="lineNum">     691 </span><span class="lineCov">        136 :       spec_queue_20_ctr &lt;= 8'h0;</span></a>
+<a name="692"><span class="lineNum">     692 </span><span class="lineCov">        136 :       spec_queue_21_retAddr &lt;= 41'h0;</span></a>
+<a name="693"><span class="lineNum">     693 </span><span class="lineCov">        136 :       spec_queue_21_ctr &lt;= 8'h0;</span></a>
+<a name="694"><span class="lineNum">     694 </span><span class="lineCov">        136 :       spec_queue_22_retAddr &lt;= 41'h0;</span></a>
+<a name="695"><span class="lineNum">     695 </span><span class="lineCov">        136 :       spec_queue_22_ctr &lt;= 8'h0;</span></a>
+<a name="696"><span class="lineNum">     696 </span><span class="lineCov">        136 :       spec_queue_23_retAddr &lt;= 41'h0;</span></a>
+<a name="697"><span class="lineNum">     697 </span><span class="lineCov">        136 :       spec_queue_23_ctr &lt;= 8'h0;</span></a>
+<a name="698"><span class="lineNum">     698 </span><span class="lineCov">        136 :       spec_queue_24_retAddr &lt;= 41'h0;</span></a>
+<a name="699"><span class="lineNum">     699 </span><span class="lineCov">        136 :       spec_queue_24_ctr &lt;= 8'h0;</span></a>
+<a name="700"><span class="lineNum">     700 </span><span class="lineCov">        136 :       spec_queue_25_retAddr &lt;= 41'h0;</span></a>
+<a name="701"><span class="lineNum">     701 </span><span class="lineCov">        136 :       spec_queue_25_ctr &lt;= 8'h0;</span></a>
+<a name="702"><span class="lineNum">     702 </span><span class="lineCov">        136 :       spec_queue_26_retAddr &lt;= 41'h0;</span></a>
+<a name="703"><span class="lineNum">     703 </span><span class="lineCov">        136 :       spec_queue_26_ctr &lt;= 8'h0;</span></a>
+<a name="704"><span class="lineNum">     704 </span><span class="lineCov">        136 :       spec_queue_27_retAddr &lt;= 41'h0;</span></a>
+<a name="705"><span class="lineNum">     705 </span><span class="lineCov">        136 :       spec_queue_27_ctr &lt;= 8'h0;</span></a>
+<a name="706"><span class="lineNum">     706 </span><span class="lineCov">        136 :       spec_queue_28_retAddr &lt;= 41'h0;</span></a>
+<a name="707"><span class="lineNum">     707 </span><span class="lineCov">        136 :       spec_queue_28_ctr &lt;= 8'h0;</span></a>
+<a name="708"><span class="lineNum">     708 </span><span class="lineCov">        136 :       spec_queue_29_retAddr &lt;= 41'h0;</span></a>
+<a name="709"><span class="lineNum">     709 </span><span class="lineCov">        136 :       spec_queue_29_ctr &lt;= 8'h0;</span></a>
+<a name="710"><span class="lineNum">     710 </span><span class="lineCov">        136 :       spec_queue_30_retAddr &lt;= 41'h0;</span></a>
+<a name="711"><span class="lineNum">     711 </span><span class="lineCov">        136 :       spec_queue_30_ctr &lt;= 8'h0;</span></a>
+<a name="712"><span class="lineNum">     712 </span><span class="lineCov">        136 :       spec_queue_31_retAddr &lt;= 41'h0;</span></a>
+<a name="713"><span class="lineNum">     713 </span><span class="lineCov">        136 :       spec_queue_31_ctr &lt;= 8'h0;</span></a>
+<a name="714"><span class="lineNum">     714 </span><span class="lineCov">        136 :       spec_nos_0_flag &lt;= 1'h0;</span></a>
+<a name="715"><span class="lineNum">     715 </span><span class="lineCov">        136 :       spec_nos_0_value &lt;= 5'h0;</span></a>
+<a name="716"><span class="lineNum">     716 </span><span class="lineCov">        136 :       spec_nos_1_flag &lt;= 1'h0;</span></a>
+<a name="717"><span class="lineNum">     717 </span><span class="lineCov">        136 :       spec_nos_1_value &lt;= 5'h0;</span></a>
+<a name="718"><span class="lineNum">     718 </span><span class="lineCov">        136 :       spec_nos_2_flag &lt;= 1'h0;</span></a>
+<a name="719"><span class="lineNum">     719 </span><span class="lineCov">        136 :       spec_nos_2_value &lt;= 5'h0;</span></a>
+<a name="720"><span class="lineNum">     720 </span><span class="lineCov">        136 :       spec_nos_3_flag &lt;= 1'h0;</span></a>
+<a name="721"><span class="lineNum">     721 </span><span class="lineCov">        136 :       spec_nos_3_value &lt;= 5'h0;</span></a>
+<a name="722"><span class="lineNum">     722 </span><span class="lineCov">        136 :       spec_nos_4_flag &lt;= 1'h0;</span></a>
+<a name="723"><span class="lineNum">     723 </span><span class="lineCov">        136 :       spec_nos_4_value &lt;= 5'h0;</span></a>
+<a name="724"><span class="lineNum">     724 </span><span class="lineCov">        136 :       spec_nos_5_flag &lt;= 1'h0;</span></a>
+<a name="725"><span class="lineNum">     725 </span><span class="lineCov">        136 :       spec_nos_5_value &lt;= 5'h0;</span></a>
+<a name="726"><span class="lineNum">     726 </span><span class="lineCov">        136 :       spec_nos_6_flag &lt;= 1'h0;</span></a>
+<a name="727"><span class="lineNum">     727 </span><span class="lineCov">        136 :       spec_nos_6_value &lt;= 5'h0;</span></a>
+<a name="728"><span class="lineNum">     728 </span><span class="lineCov">        136 :       spec_nos_7_flag &lt;= 1'h0;</span></a>
+<a name="729"><span class="lineNum">     729 </span><span class="lineCov">        136 :       spec_nos_7_value &lt;= 5'h0;</span></a>
+<a name="730"><span class="lineNum">     730 </span><span class="lineCov">        136 :       spec_nos_8_flag &lt;= 1'h0;</span></a>
+<a name="731"><span class="lineNum">     731 </span><span class="lineCov">        136 :       spec_nos_8_value &lt;= 5'h0;</span></a>
+<a name="732"><span class="lineNum">     732 </span><span class="lineCov">        136 :       spec_nos_9_flag &lt;= 1'h0;</span></a>
+<a name="733"><span class="lineNum">     733 </span><span class="lineCov">        136 :       spec_nos_9_value &lt;= 5'h0;</span></a>
+<a name="734"><span class="lineNum">     734 </span><span class="lineCov">        136 :       spec_nos_10_flag &lt;= 1'h0;</span></a>
+<a name="735"><span class="lineNum">     735 </span><span class="lineCov">        136 :       spec_nos_10_value &lt;= 5'h0;</span></a>
+<a name="736"><span class="lineNum">     736 </span><span class="lineCov">        136 :       spec_nos_11_flag &lt;= 1'h0;</span></a>
+<a name="737"><span class="lineNum">     737 </span><span class="lineCov">        136 :       spec_nos_11_value &lt;= 5'h0;</span></a>
+<a name="738"><span class="lineNum">     738 </span><span class="lineCov">        136 :       spec_nos_12_flag &lt;= 1'h0;</span></a>
+<a name="739"><span class="lineNum">     739 </span><span class="lineCov">        136 :       spec_nos_12_value &lt;= 5'h0;</span></a>
+<a name="740"><span class="lineNum">     740 </span><span class="lineCov">        136 :       spec_nos_13_flag &lt;= 1'h0;</span></a>
+<a name="741"><span class="lineNum">     741 </span><span class="lineCov">        136 :       spec_nos_13_value &lt;= 5'h0;</span></a>
+<a name="742"><span class="lineNum">     742 </span><span class="lineCov">        136 :       spec_nos_14_flag &lt;= 1'h0;</span></a>
+<a name="743"><span class="lineNum">     743 </span><span class="lineCov">        136 :       spec_nos_14_value &lt;= 5'h0;</span></a>
+<a name="744"><span class="lineNum">     744 </span><span class="lineCov">        136 :       spec_nos_15_flag &lt;= 1'h0;</span></a>
+<a name="745"><span class="lineNum">     745 </span><span class="lineCov">        136 :       spec_nos_15_value &lt;= 5'h0;</span></a>
+<a name="746"><span class="lineNum">     746 </span><span class="lineCov">        136 :       spec_nos_16_flag &lt;= 1'h0;</span></a>
+<a name="747"><span class="lineNum">     747 </span><span class="lineCov">        136 :       spec_nos_16_value &lt;= 5'h0;</span></a>
+<a name="748"><span class="lineNum">     748 </span><span class="lineCov">        136 :       spec_nos_17_flag &lt;= 1'h0;</span></a>
+<a name="749"><span class="lineNum">     749 </span><span class="lineCov">        136 :       spec_nos_17_value &lt;= 5'h0;</span></a>
+<a name="750"><span class="lineNum">     750 </span><span class="lineCov">        136 :       spec_nos_18_flag &lt;= 1'h0;</span></a>
+<a name="751"><span class="lineNum">     751 </span><span class="lineCov">        136 :       spec_nos_18_value &lt;= 5'h0;</span></a>
+<a name="752"><span class="lineNum">     752 </span><span class="lineCov">        136 :       spec_nos_19_flag &lt;= 1'h0;</span></a>
+<a name="753"><span class="lineNum">     753 </span><span class="lineCov">        136 :       spec_nos_19_value &lt;= 5'h0;</span></a>
+<a name="754"><span class="lineNum">     754 </span><span class="lineCov">        136 :       spec_nos_20_flag &lt;= 1'h0;</span></a>
+<a name="755"><span class="lineNum">     755 </span><span class="lineCov">        136 :       spec_nos_20_value &lt;= 5'h0;</span></a>
+<a name="756"><span class="lineNum">     756 </span><span class="lineCov">        136 :       spec_nos_21_flag &lt;= 1'h0;</span></a>
+<a name="757"><span class="lineNum">     757 </span><span class="lineCov">        136 :       spec_nos_21_value &lt;= 5'h0;</span></a>
+<a name="758"><span class="lineNum">     758 </span><span class="lineCov">        136 :       spec_nos_22_flag &lt;= 1'h0;</span></a>
+<a name="759"><span class="lineNum">     759 </span><span class="lineCov">        136 :       spec_nos_22_value &lt;= 5'h0;</span></a>
+<a name="760"><span class="lineNum">     760 </span><span class="lineCov">        136 :       spec_nos_23_flag &lt;= 1'h0;</span></a>
+<a name="761"><span class="lineNum">     761 </span><span class="lineCov">        136 :       spec_nos_23_value &lt;= 5'h0;</span></a>
+<a name="762"><span class="lineNum">     762 </span><span class="lineCov">        136 :       spec_nos_24_flag &lt;= 1'h0;</span></a>
+<a name="763"><span class="lineNum">     763 </span><span class="lineCov">        136 :       spec_nos_24_value &lt;= 5'h0;</span></a>
+<a name="764"><span class="lineNum">     764 </span><span class="lineCov">        136 :       spec_nos_25_flag &lt;= 1'h0;</span></a>
+<a name="765"><span class="lineNum">     765 </span><span class="lineCov">        136 :       spec_nos_25_value &lt;= 5'h0;</span></a>
+<a name="766"><span class="lineNum">     766 </span><span class="lineCov">        136 :       spec_nos_26_flag &lt;= 1'h0;</span></a>
+<a name="767"><span class="lineNum">     767 </span><span class="lineCov">        136 :       spec_nos_26_value &lt;= 5'h0;</span></a>
+<a name="768"><span class="lineNum">     768 </span><span class="lineCov">        136 :       spec_nos_27_flag &lt;= 1'h0;</span></a>
+<a name="769"><span class="lineNum">     769 </span><span class="lineCov">        136 :       spec_nos_27_value &lt;= 5'h0;</span></a>
+<a name="770"><span class="lineNum">     770 </span><span class="lineCov">        136 :       spec_nos_28_flag &lt;= 1'h0;</span></a>
+<a name="771"><span class="lineNum">     771 </span><span class="lineCov">        136 :       spec_nos_28_value &lt;= 5'h0;</span></a>
+<a name="772"><span class="lineNum">     772 </span><span class="lineCov">        136 :       spec_nos_29_flag &lt;= 1'h0;</span></a>
+<a name="773"><span class="lineNum">     773 </span><span class="lineCov">        136 :       spec_nos_29_value &lt;= 5'h0;</span></a>
+<a name="774"><span class="lineNum">     774 </span><span class="lineCov">        136 :       spec_nos_30_flag &lt;= 1'h0;</span></a>
+<a name="775"><span class="lineNum">     775 </span><span class="lineCov">        136 :       spec_nos_30_value &lt;= 5'h0;</span></a>
+<a name="776"><span class="lineNum">     776 </span><span class="lineCov">        136 :       spec_nos_31_flag &lt;= 1'h0;</span></a>
+<a name="777"><span class="lineNum">     777 </span><span class="lineCov">        136 :       spec_nos_31_value &lt;= 5'h0;</span></a>
+<a name="778"><span class="lineNum">     778 </span><span class="lineCov">        136 :       nsp &lt;= 4'h0;</span></a>
+<a name="779"><span class="lineNum">     779 </span><span class="lineCov">        136 :       ssp &lt;= 4'h0;</span></a>
+<a name="780"><span class="lineNum">     780 </span><span class="lineCov">        136 :       sctr &lt;= 3'h0;</span></a>
+<a name="781"><span class="lineNum">     781 </span><span class="lineCov">        136 :       TOSR_flag &lt;= 1'h1;</span></a>
+<a name="782"><span class="lineNum">     782 </span><span class="lineCov">        136 :       TOSR_value &lt;= 5'h1F;</span></a>
+<a name="783"><span class="lineNum">     783 </span><span class="lineCov">        136 :       TOSW_flag &lt;= 1'h0;</span></a>
+<a name="784"><span class="lineNum">     784 </span><span class="lineCov">        136 :       TOSW_value &lt;= 5'h0;</span></a>
+<a name="785"><span class="lineNum">     785 </span><span class="lineCov">        136 :       BOS_flag &lt;= 1'h0;</span></a>
+<a name="786"><span class="lineNum">     786 </span><span class="lineCov">        136 :       BOS_value &lt;= 5'h0;</span></a>
+<a name="787"><span class="lineNum">     787 </span><span class="lineCov">        136 :       spec_overflowed &lt;= 1'h0;</span></a>
+<a name="788"><span class="lineNum">     788 </span><span class="lineCov">        136 :       writeBypassValid &lt;= 1'h0;</span></a>
+<a name="789"><span class="lineNum">     789 </span><span class="lineCov">        136 :       timingTop_retAddr &lt;= 41'h0;</span></a>
+<a name="790"><span class="lineNum">     790 </span>            :     end</a>
+<a name="791"><span class="lineNum">     791 </span><span class="lineCov">      63729 :     else begin</span></a>
+<a name="792"><span class="lineNum">     792 </span><span class="lineNoCov">          0 :       if (~io_commit_push_valid | _GEN_56 | ~_GEN_57) begin</span></a>
+<a name="793"><span class="lineNum">     793 </span>            :       end</a>
+<a name="794"><span class="lineNum">     794 </span>            :       else</a>
+<a name="795"><span class="lineNum">     795 </span><span class="lineNoCov">          0 :         commit_stack_0_retAddr &lt;= _GEN_0[io_commit_meta_TOSW_value];</span></a>
+<a name="796"><span class="lineNum">     796 </span><span class="lineCov">         14 :       if (io_commit_push_valid) begin</span></a>
+<a name="797"><span class="lineNum">     797 </span><span class="lineNoCov">          0 :         if (_GEN_56) begin</span></a>
+<a name="798"><span class="lineNum">     798 </span><span class="lineCov">         14 :           if (_GEN_25)</span></a>
+<a name="799"><span class="lineNum">     799 </span><span class="lineCov">          7 :             commit_stack_0_ctr &lt;= _commit_stack_ctr_T_2;</span></a>
+<a name="800"><span class="lineNum">     800 </span><span class="lineNoCov">          0 :           else if (_GEN_26)</span></a>
+<a name="801"><span class="lineNum">     801 </span><span class="lineNoCov">          0 :             commit_stack_0_ctr &lt;= _commit_stack_ctr_T;</span></a>
+<a name="802"><span class="lineNum">     802 </span><span class="lineNoCov">          0 :           if (_GEN_27)</span></a>
+<a name="803"><span class="lineNum">     803 </span><span class="lineNoCov">          0 :             commit_stack_1_ctr &lt;= _commit_stack_ctr_T_2;</span></a>
+<a name="804"><span class="lineNum">     804 </span><span class="lineNoCov">          0 :           else if (_GEN_28)</span></a>
+<a name="805"><span class="lineNum">     805 </span><span class="lineNoCov">          0 :             commit_stack_1_ctr &lt;= _commit_stack_ctr_T;</span></a>
+<a name="806"><span class="lineNum">     806 </span><span class="lineNoCov">          0 :           if (_GEN_29)</span></a>
+<a name="807"><span class="lineNum">     807 </span><span class="lineNoCov">          0 :             commit_stack_2_ctr &lt;= _commit_stack_ctr_T_2;</span></a>
+<a name="808"><span class="lineNum">     808 </span><span class="lineNoCov">          0 :           else if (_GEN_30)</span></a>
+<a name="809"><span class="lineNum">     809 </span><span class="lineNoCov">          0 :             commit_stack_2_ctr &lt;= _commit_stack_ctr_T;</span></a>
+<a name="810"><span class="lineNum">     810 </span><span class="lineNoCov">          0 :           if (_GEN_31)</span></a>
+<a name="811"><span class="lineNum">     811 </span><span class="lineNoCov">          0 :             commit_stack_3_ctr &lt;= _commit_stack_ctr_T_2;</span></a>
+<a name="812"><span class="lineNum">     812 </span><span class="lineNoCov">          0 :           else if (_GEN_32)</span></a>
+<a name="813"><span class="lineNum">     813 </span><span class="lineNoCov">          0 :             commit_stack_3_ctr &lt;= _commit_stack_ctr_T;</span></a>
+<a name="814"><span class="lineNum">     814 </span><span class="lineNoCov">          0 :           if (_GEN_33)</span></a>
+<a name="815"><span class="lineNum">     815 </span><span class="lineNoCov">          0 :             commit_stack_4_ctr &lt;= _commit_stack_ctr_T_2;</span></a>
+<a name="816"><span class="lineNum">     816 </span><span class="lineNoCov">          0 :           else if (_GEN_34)</span></a>
+<a name="817"><span class="lineNum">     817 </span><span class="lineNoCov">          0 :             commit_stack_4_ctr &lt;= _commit_stack_ctr_T;</span></a>
+<a name="818"><span class="lineNum">     818 </span><span class="lineNoCov">          0 :           if (_GEN_35)</span></a>
+<a name="819"><span class="lineNum">     819 </span><span class="lineNoCov">          0 :             commit_stack_5_ctr &lt;= _commit_stack_ctr_T_2;</span></a>
+<a name="820"><span class="lineNum">     820 </span><span class="lineNoCov">          0 :           else if (_GEN_36)</span></a>
+<a name="821"><span class="lineNum">     821 </span><span class="lineNoCov">          0 :             commit_stack_5_ctr &lt;= _commit_stack_ctr_T;</span></a>
+<a name="822"><span class="lineNum">     822 </span><span class="lineNoCov">          0 :           if (_GEN_37)</span></a>
+<a name="823"><span class="lineNum">     823 </span><span class="lineNoCov">          0 :             commit_stack_6_ctr &lt;= _commit_stack_ctr_T_2;</span></a>
+<a name="824"><span class="lineNum">     824 </span><span class="lineNoCov">          0 :           else if (_GEN_38)</span></a>
+<a name="825"><span class="lineNum">     825 </span><span class="lineNoCov">          0 :             commit_stack_6_ctr &lt;= _commit_stack_ctr_T;</span></a>
+<a name="826"><span class="lineNum">     826 </span><span class="lineNoCov">          0 :           if (_GEN_39)</span></a>
+<a name="827"><span class="lineNum">     827 </span><span class="lineNoCov">          0 :             commit_stack_7_ctr &lt;= _commit_stack_ctr_T_2;</span></a>
+<a name="828"><span class="lineNum">     828 </span><span class="lineNoCov">          0 :           else if (_GEN_40)</span></a>
+<a name="829"><span class="lineNum">     829 </span><span class="lineNoCov">          0 :             commit_stack_7_ctr &lt;= _commit_stack_ctr_T;</span></a>
+<a name="830"><span class="lineNum">     830 </span><span class="lineNoCov">          0 :           if (_GEN_41)</span></a>
+<a name="831"><span class="lineNum">     831 </span><span class="lineNoCov">          0 :             commit_stack_8_ctr &lt;= _commit_stack_ctr_T_2;</span></a>
+<a name="832"><span class="lineNum">     832 </span><span class="lineNoCov">          0 :           else if (_GEN_42)</span></a>
+<a name="833"><span class="lineNum">     833 </span><span class="lineNoCov">          0 :             commit_stack_8_ctr &lt;= _commit_stack_ctr_T;</span></a>
+<a name="834"><span class="lineNum">     834 </span><span class="lineNoCov">          0 :           if (_GEN_43)</span></a>
+<a name="835"><span class="lineNum">     835 </span><span class="lineNoCov">          0 :             commit_stack_9_ctr &lt;= _commit_stack_ctr_T_2;</span></a>
+<a name="836"><span class="lineNum">     836 </span><span class="lineNoCov">          0 :           else if (_GEN_44)</span></a>
+<a name="837"><span class="lineNum">     837 </span><span class="lineNoCov">          0 :             commit_stack_9_ctr &lt;= _commit_stack_ctr_T;</span></a>
+<a name="838"><span class="lineNum">     838 </span><span class="lineNoCov">          0 :           if (_GEN_45)</span></a>
+<a name="839"><span class="lineNum">     839 </span><span class="lineNoCov">          0 :             commit_stack_10_ctr &lt;= _commit_stack_ctr_T_2;</span></a>
+<a name="840"><span class="lineNum">     840 </span><span class="lineNoCov">          0 :           else if (_GEN_46)</span></a>
+<a name="841"><span class="lineNum">     841 </span><span class="lineNoCov">          0 :             commit_stack_10_ctr &lt;= _commit_stack_ctr_T;</span></a>
+<a name="842"><span class="lineNum">     842 </span><span class="lineNoCov">          0 :           if (_GEN_47)</span></a>
+<a name="843"><span class="lineNum">     843 </span><span class="lineNoCov">          0 :             commit_stack_11_ctr &lt;= _commit_stack_ctr_T_2;</span></a>
+<a name="844"><span class="lineNum">     844 </span><span class="lineNoCov">          0 :           else if (_GEN_48)</span></a>
+<a name="845"><span class="lineNum">     845 </span><span class="lineNoCov">          0 :             commit_stack_11_ctr &lt;= _commit_stack_ctr_T;</span></a>
+<a name="846"><span class="lineNum">     846 </span><span class="lineNoCov">          0 :           if (_GEN_49)</span></a>
+<a name="847"><span class="lineNum">     847 </span><span class="lineNoCov">          0 :             commit_stack_12_ctr &lt;= _commit_stack_ctr_T_2;</span></a>
+<a name="848"><span class="lineNum">     848 </span><span class="lineNoCov">          0 :           else if (_GEN_50)</span></a>
+<a name="849"><span class="lineNum">     849 </span><span class="lineNoCov">          0 :             commit_stack_12_ctr &lt;= _commit_stack_ctr_T;</span></a>
+<a name="850"><span class="lineNum">     850 </span><span class="lineNoCov">          0 :           if (_GEN_51)</span></a>
+<a name="851"><span class="lineNum">     851 </span><span class="lineNoCov">          0 :             commit_stack_13_ctr &lt;= _commit_stack_ctr_T_2;</span></a>
+<a name="852"><span class="lineNum">     852 </span><span class="lineNoCov">          0 :           else if (_GEN_52)</span></a>
+<a name="853"><span class="lineNum">     853 </span><span class="lineNoCov">          0 :             commit_stack_13_ctr &lt;= _commit_stack_ctr_T;</span></a>
+<a name="854"><span class="lineNum">     854 </span><span class="lineNoCov">          0 :           if (_GEN_53)</span></a>
+<a name="855"><span class="lineNum">     855 </span><span class="lineNoCov">          0 :             commit_stack_14_ctr &lt;= _commit_stack_ctr_T_2;</span></a>
+<a name="856"><span class="lineNum">     856 </span><span class="lineNoCov">          0 :           else if (_GEN_54)</span></a>
+<a name="857"><span class="lineNum">     857 </span><span class="lineNoCov">          0 :             commit_stack_14_ctr &lt;= _commit_stack_ctr_T;</span></a>
+<a name="858"><span class="lineNum">     858 </span><span class="lineNoCov">          0 :           if (&amp;io_commit_meta_ssp)</span></a>
+<a name="859"><span class="lineNum">     859 </span><span class="lineNoCov">          0 :             commit_stack_15_ctr &lt;= _commit_stack_ctr_T_2;</span></a>
+<a name="860"><span class="lineNum">     860 </span><span class="lineNoCov">          0 :           else if (_GEN_55)</span></a>
+<a name="861"><span class="lineNum">     861 </span><span class="lineNoCov">          0 :             commit_stack_15_ctr &lt;= _commit_stack_ctr_T;</span></a>
+<a name="862"><span class="lineNum">     862 </span><span class="lineCov">          7 :           nsp &lt;= io_commit_meta_ssp;</span></a>
+<a name="863"><span class="lineNum">     863 </span>            :         end</a>
+<a name="864"><span class="lineNum">     864 </span><span class="lineNoCov">          0 :         else begin</span></a>
+<a name="865"><span class="lineNum">     865 </span><span class="lineNoCov">          0 :           if (_GEN_57)</span></a>
+<a name="866"><span class="lineNum">     866 </span><span class="lineNoCov">          0 :             commit_stack_0_ctr &lt;= 8'h0;</span></a>
+<a name="867"><span class="lineNum">     867 </span><span class="lineNoCov">          0 :           else if (_GEN_26)</span></a>
+<a name="868"><span class="lineNum">     868 </span><span class="lineNoCov">          0 :             commit_stack_0_ctr &lt;= _commit_stack_ctr_T;</span></a>
+<a name="869"><span class="lineNum">     869 </span><span class="lineNoCov">          0 :           if (_GEN_58)</span></a>
+<a name="870"><span class="lineNum">     870 </span><span class="lineNoCov">          0 :             commit_stack_1_ctr &lt;= 8'h0;</span></a>
+<a name="871"><span class="lineNum">     871 </span><span class="lineNoCov">          0 :           else if (_GEN_28)</span></a>
+<a name="872"><span class="lineNum">     872 </span><span class="lineNoCov">          0 :             commit_stack_1_ctr &lt;= _commit_stack_ctr_T;</span></a>
+<a name="873"><span class="lineNum">     873 </span><span class="lineNoCov">          0 :           if (_GEN_59)</span></a>
+<a name="874"><span class="lineNum">     874 </span><span class="lineNoCov">          0 :             commit_stack_2_ctr &lt;= 8'h0;</span></a>
+<a name="875"><span class="lineNum">     875 </span><span class="lineNoCov">          0 :           else if (_GEN_30)</span></a>
+<a name="876"><span class="lineNum">     876 </span><span class="lineNoCov">          0 :             commit_stack_2_ctr &lt;= _commit_stack_ctr_T;</span></a>
+<a name="877"><span class="lineNum">     877 </span><span class="lineNoCov">          0 :           if (_GEN_60)</span></a>
+<a name="878"><span class="lineNum">     878 </span><span class="lineNoCov">          0 :             commit_stack_3_ctr &lt;= 8'h0;</span></a>
+<a name="879"><span class="lineNum">     879 </span><span class="lineNoCov">          0 :           else if (_GEN_32)</span></a>
+<a name="880"><span class="lineNum">     880 </span><span class="lineNoCov">          0 :             commit_stack_3_ctr &lt;= _commit_stack_ctr_T;</span></a>
+<a name="881"><span class="lineNum">     881 </span><span class="lineNoCov">          0 :           if (_GEN_61)</span></a>
+<a name="882"><span class="lineNum">     882 </span><span class="lineNoCov">          0 :             commit_stack_4_ctr &lt;= 8'h0;</span></a>
+<a name="883"><span class="lineNum">     883 </span><span class="lineNoCov">          0 :           else if (_GEN_34)</span></a>
+<a name="884"><span class="lineNum">     884 </span><span class="lineNoCov">          0 :             commit_stack_4_ctr &lt;= _commit_stack_ctr_T;</span></a>
+<a name="885"><span class="lineNum">     885 </span><span class="lineNoCov">          0 :           if (_GEN_62)</span></a>
+<a name="886"><span class="lineNum">     886 </span><span class="lineNoCov">          0 :             commit_stack_5_ctr &lt;= 8'h0;</span></a>
+<a name="887"><span class="lineNum">     887 </span><span class="lineNoCov">          0 :           else if (_GEN_36)</span></a>
+<a name="888"><span class="lineNum">     888 </span><span class="lineNoCov">          0 :             commit_stack_5_ctr &lt;= _commit_stack_ctr_T;</span></a>
+<a name="889"><span class="lineNum">     889 </span><span class="lineNoCov">          0 :           if (_GEN_63)</span></a>
+<a name="890"><span class="lineNum">     890 </span><span class="lineNoCov">          0 :             commit_stack_6_ctr &lt;= 8'h0;</span></a>
+<a name="891"><span class="lineNum">     891 </span><span class="lineNoCov">          0 :           else if (_GEN_38)</span></a>
+<a name="892"><span class="lineNum">     892 </span><span class="lineNoCov">          0 :             commit_stack_6_ctr &lt;= _commit_stack_ctr_T;</span></a>
+<a name="893"><span class="lineNum">     893 </span><span class="lineNoCov">          0 :           if (_GEN_64)</span></a>
+<a name="894"><span class="lineNum">     894 </span><span class="lineNoCov">          0 :             commit_stack_7_ctr &lt;= 8'h0;</span></a>
+<a name="895"><span class="lineNum">     895 </span><span class="lineNoCov">          0 :           else if (_GEN_40)</span></a>
+<a name="896"><span class="lineNum">     896 </span><span class="lineNoCov">          0 :             commit_stack_7_ctr &lt;= _commit_stack_ctr_T;</span></a>
+<a name="897"><span class="lineNum">     897 </span><span class="lineNoCov">          0 :           if (_GEN_65)</span></a>
+<a name="898"><span class="lineNum">     898 </span><span class="lineNoCov">          0 :             commit_stack_8_ctr &lt;= 8'h0;</span></a>
+<a name="899"><span class="lineNum">     899 </span><span class="lineNoCov">          0 :           else if (_GEN_42)</span></a>
+<a name="900"><span class="lineNum">     900 </span><span class="lineNoCov">          0 :             commit_stack_8_ctr &lt;= _commit_stack_ctr_T;</span></a>
+<a name="901"><span class="lineNum">     901 </span><span class="lineNoCov">          0 :           if (_GEN_66)</span></a>
+<a name="902"><span class="lineNum">     902 </span><span class="lineNoCov">          0 :             commit_stack_9_ctr &lt;= 8'h0;</span></a>
+<a name="903"><span class="lineNum">     903 </span><span class="lineNoCov">          0 :           else if (_GEN_44)</span></a>
+<a name="904"><span class="lineNum">     904 </span><span class="lineNoCov">          0 :             commit_stack_9_ctr &lt;= _commit_stack_ctr_T;</span></a>
+<a name="905"><span class="lineNum">     905 </span><span class="lineNoCov">          0 :           if (_GEN_67)</span></a>
+<a name="906"><span class="lineNum">     906 </span><span class="lineNoCov">          0 :             commit_stack_10_ctr &lt;= 8'h0;</span></a>
+<a name="907"><span class="lineNum">     907 </span><span class="lineNoCov">          0 :           else if (_GEN_46)</span></a>
+<a name="908"><span class="lineNum">     908 </span><span class="lineNoCov">          0 :             commit_stack_10_ctr &lt;= _commit_stack_ctr_T;</span></a>
+<a name="909"><span class="lineNum">     909 </span><span class="lineNoCov">          0 :           if (_GEN_68)</span></a>
+<a name="910"><span class="lineNum">     910 </span><span class="lineNoCov">          0 :             commit_stack_11_ctr &lt;= 8'h0;</span></a>
+<a name="911"><span class="lineNum">     911 </span><span class="lineNoCov">          0 :           else if (_GEN_48)</span></a>
+<a name="912"><span class="lineNum">     912 </span><span class="lineNoCov">          0 :             commit_stack_11_ctr &lt;= _commit_stack_ctr_T;</span></a>
+<a name="913"><span class="lineNum">     913 </span><span class="lineNoCov">          0 :           if (_GEN_69)</span></a>
+<a name="914"><span class="lineNum">     914 </span><span class="lineNoCov">          0 :             commit_stack_12_ctr &lt;= 8'h0;</span></a>
+<a name="915"><span class="lineNum">     915 </span><span class="lineNoCov">          0 :           else if (_GEN_50)</span></a>
+<a name="916"><span class="lineNum">     916 </span><span class="lineNoCov">          0 :             commit_stack_12_ctr &lt;= _commit_stack_ctr_T;</span></a>
+<a name="917"><span class="lineNum">     917 </span><span class="lineNoCov">          0 :           if (_GEN_70)</span></a>
+<a name="918"><span class="lineNum">     918 </span><span class="lineNoCov">          0 :             commit_stack_13_ctr &lt;= 8'h0;</span></a>
+<a name="919"><span class="lineNum">     919 </span><span class="lineNoCov">          0 :           else if (_GEN_52)</span></a>
+<a name="920"><span class="lineNum">     920 </span><span class="lineNoCov">          0 :             commit_stack_13_ctr &lt;= _commit_stack_ctr_T;</span></a>
+<a name="921"><span class="lineNum">     921 </span><span class="lineNoCov">          0 :           if (_GEN_71)</span></a>
+<a name="922"><span class="lineNum">     922 </span><span class="lineNoCov">          0 :             commit_stack_14_ctr &lt;= 8'h0;</span></a>
+<a name="923"><span class="lineNum">     923 </span><span class="lineNoCov">          0 :           else if (_GEN_54)</span></a>
+<a name="924"><span class="lineNum">     924 </span><span class="lineNoCov">          0 :             commit_stack_14_ctr &lt;= _commit_stack_ctr_T;</span></a>
+<a name="925"><span class="lineNum">     925 </span><span class="lineNoCov">          0 :           if (&amp;_nsp_T_2)</span></a>
+<a name="926"><span class="lineNum">     926 </span><span class="lineNoCov">          0 :             commit_stack_15_ctr &lt;= 8'h0;</span></a>
+<a name="927"><span class="lineNum">     927 </span><span class="lineNoCov">          0 :           else if (_GEN_55)</span></a>
+<a name="928"><span class="lineNum">     928 </span><span class="lineNoCov">          0 :             commit_stack_15_ctr &lt;= _commit_stack_ctr_T;</span></a>
+<a name="929"><span class="lineNum">     929 </span><span class="lineNoCov">          0 :           nsp &lt;= _nsp_T_2;</span></a>
+<a name="930"><span class="lineNum">     930 </span>            :         end</a>
+<a name="931"><span class="lineNum">     931 </span>            :       end</a>
+<a name="932"><span class="lineNum">     932 </span><span class="lineCov">      63722 :       else begin</span></a>
+<a name="933"><span class="lineNum">     933 </span><span class="lineNoCov">          0 :         if (_GEN_26)</span></a>
+<a name="934"><span class="lineNum">     934 </span><span class="lineNoCov">          0 :           commit_stack_0_ctr &lt;= _commit_stack_ctr_T;</span></a>
+<a name="935"><span class="lineNum">     935 </span><span class="lineNoCov">          0 :         if (_GEN_28)</span></a>
+<a name="936"><span class="lineNum">     936 </span><span class="lineNoCov">          0 :           commit_stack_1_ctr &lt;= _commit_stack_ctr_T;</span></a>
+<a name="937"><span class="lineNum">     937 </span><span class="lineNoCov">          0 :         if (_GEN_30)</span></a>
+<a name="938"><span class="lineNum">     938 </span><span class="lineNoCov">          0 :           commit_stack_2_ctr &lt;= _commit_stack_ctr_T;</span></a>
+<a name="939"><span class="lineNum">     939 </span><span class="lineNoCov">          0 :         if (_GEN_32)</span></a>
+<a name="940"><span class="lineNum">     940 </span><span class="lineNoCov">          0 :           commit_stack_3_ctr &lt;= _commit_stack_ctr_T;</span></a>
+<a name="941"><span class="lineNum">     941 </span><span class="lineNoCov">          0 :         if (_GEN_34)</span></a>
+<a name="942"><span class="lineNum">     942 </span><span class="lineNoCov">          0 :           commit_stack_4_ctr &lt;= _commit_stack_ctr_T;</span></a>
+<a name="943"><span class="lineNum">     943 </span><span class="lineNoCov">          0 :         if (_GEN_36)</span></a>
+<a name="944"><span class="lineNum">     944 </span><span class="lineNoCov">          0 :           commit_stack_5_ctr &lt;= _commit_stack_ctr_T;</span></a>
+<a name="945"><span class="lineNum">     945 </span><span class="lineNoCov">          0 :         if (_GEN_38)</span></a>
+<a name="946"><span class="lineNum">     946 </span><span class="lineNoCov">          0 :           commit_stack_6_ctr &lt;= _commit_stack_ctr_T;</span></a>
+<a name="947"><span class="lineNum">     947 </span><span class="lineNoCov">          0 :         if (_GEN_40)</span></a>
+<a name="948"><span class="lineNum">     948 </span><span class="lineNoCov">          0 :           commit_stack_7_ctr &lt;= _commit_stack_ctr_T;</span></a>
+<a name="949"><span class="lineNum">     949 </span><span class="lineNoCov">          0 :         if (_GEN_42)</span></a>
+<a name="950"><span class="lineNum">     950 </span><span class="lineNoCov">          0 :           commit_stack_8_ctr &lt;= _commit_stack_ctr_T;</span></a>
+<a name="951"><span class="lineNum">     951 </span><span class="lineNoCov">          0 :         if (_GEN_44)</span></a>
+<a name="952"><span class="lineNum">     952 </span><span class="lineNoCov">          0 :           commit_stack_9_ctr &lt;= _commit_stack_ctr_T;</span></a>
+<a name="953"><span class="lineNum">     953 </span><span class="lineNoCov">          0 :         if (_GEN_46)</span></a>
+<a name="954"><span class="lineNum">     954 </span><span class="lineNoCov">          0 :           commit_stack_10_ctr &lt;= _commit_stack_ctr_T;</span></a>
+<a name="955"><span class="lineNum">     955 </span><span class="lineNoCov">          0 :         if (_GEN_48)</span></a>
+<a name="956"><span class="lineNum">     956 </span><span class="lineNoCov">          0 :           commit_stack_11_ctr &lt;= _commit_stack_ctr_T;</span></a>
+<a name="957"><span class="lineNum">     957 </span><span class="lineNoCov">          0 :         if (_GEN_50)</span></a>
+<a name="958"><span class="lineNum">     958 </span><span class="lineNoCov">          0 :           commit_stack_12_ctr &lt;= _commit_stack_ctr_T;</span></a>
+<a name="959"><span class="lineNum">     959 </span><span class="lineNoCov">          0 :         if (_GEN_52)</span></a>
+<a name="960"><span class="lineNum">     960 </span><span class="lineNoCov">          0 :           commit_stack_13_ctr &lt;= _commit_stack_ctr_T;</span></a>
+<a name="961"><span class="lineNum">     961 </span><span class="lineNoCov">          0 :         if (_GEN_54)</span></a>
+<a name="962"><span class="lineNum">     962 </span><span class="lineNoCov">          0 :           commit_stack_14_ctr &lt;= _commit_stack_ctr_T;</span></a>
+<a name="963"><span class="lineNum">     963 </span><span class="lineNoCov">          0 :         if (_GEN_55)</span></a>
+<a name="964"><span class="lineNum">     964 </span><span class="lineNoCov">          0 :           commit_stack_15_ctr &lt;= _commit_stack_ctr_T;</span></a>
+<a name="965"><span class="lineNum">     965 </span><span class="lineNoCov">          0 :         if (io_commit_pop_valid) begin</span></a>
+<a name="966"><span class="lineNum">     966 </span><span class="lineNoCov">          0 :           if (|_GEN_24)</span></a>
+<a name="967"><span class="lineNum">     967 </span><span class="lineNoCov">          0 :             nsp &lt;= io_commit_meta_ssp;</span></a>
+<a name="968"><span class="lineNum">     968 </span>            :           else</a>
+<a name="969"><span class="lineNum">     969 </span><span class="lineNoCov">          0 :             nsp &lt;= 4'(io_commit_meta_ssp - 4'h1);</span></a>
+<a name="970"><span class="lineNum">     970 </span>            :         end</a>
+<a name="971"><span class="lineNum">     971 </span>            :       end</a>
+<a name="972"><span class="lineNum">     972 </span><span class="lineNoCov">          0 :       if (~io_commit_push_valid | _GEN_56 | ~_GEN_58) begin</span></a>
+<a name="973"><span class="lineNum">     973 </span>            :       end</a>
+<a name="974"><span class="lineNum">     974 </span>            :       else</a>
+<a name="975"><span class="lineNum">     975 </span><span class="lineNoCov">          0 :         commit_stack_1_retAddr &lt;= _GEN_0[io_commit_meta_TOSW_value];</span></a>
+<a name="976"><span class="lineNum">     976 </span><span class="lineNoCov">          0 :       if (~io_commit_push_valid | _GEN_56 | ~_GEN_59) begin</span></a>
+<a name="977"><span class="lineNum">     977 </span>            :       end</a>
+<a name="978"><span class="lineNum">     978 </span>            :       else</a>
+<a name="979"><span class="lineNum">     979 </span><span class="lineNoCov">          0 :         commit_stack_2_retAddr &lt;= _GEN_0[io_commit_meta_TOSW_value];</span></a>
+<a name="980"><span class="lineNum">     980 </span><span class="lineNoCov">          0 :       if (~io_commit_push_valid | _GEN_56 | ~_GEN_60) begin</span></a>
+<a name="981"><span class="lineNum">     981 </span>            :       end</a>
+<a name="982"><span class="lineNum">     982 </span>            :       else</a>
+<a name="983"><span class="lineNum">     983 </span><span class="lineNoCov">          0 :         commit_stack_3_retAddr &lt;= _GEN_0[io_commit_meta_TOSW_value];</span></a>
+<a name="984"><span class="lineNum">     984 </span><span class="lineNoCov">          0 :       if (~io_commit_push_valid | _GEN_56 | ~_GEN_61) begin</span></a>
+<a name="985"><span class="lineNum">     985 </span>            :       end</a>
+<a name="986"><span class="lineNum">     986 </span>            :       else</a>
+<a name="987"><span class="lineNum">     987 </span><span class="lineNoCov">          0 :         commit_stack_4_retAddr &lt;= _GEN_0[io_commit_meta_TOSW_value];</span></a>
+<a name="988"><span class="lineNum">     988 </span><span class="lineNoCov">          0 :       if (~io_commit_push_valid | _GEN_56 | ~_GEN_62) begin</span></a>
+<a name="989"><span class="lineNum">     989 </span>            :       end</a>
+<a name="990"><span class="lineNum">     990 </span>            :       else</a>
+<a name="991"><span class="lineNum">     991 </span><span class="lineNoCov">          0 :         commit_stack_5_retAddr &lt;= _GEN_0[io_commit_meta_TOSW_value];</span></a>
+<a name="992"><span class="lineNum">     992 </span><span class="lineNoCov">          0 :       if (~io_commit_push_valid | _GEN_56 | ~_GEN_63) begin</span></a>
+<a name="993"><span class="lineNum">     993 </span>            :       end</a>
+<a name="994"><span class="lineNum">     994 </span>            :       else</a>
+<a name="995"><span class="lineNum">     995 </span><span class="lineNoCov">          0 :         commit_stack_6_retAddr &lt;= _GEN_0[io_commit_meta_TOSW_value];</span></a>
+<a name="996"><span class="lineNum">     996 </span><span class="lineNoCov">          0 :       if (~io_commit_push_valid | _GEN_56 | ~_GEN_64) begin</span></a>
+<a name="997"><span class="lineNum">     997 </span>            :       end</a>
+<a name="998"><span class="lineNum">     998 </span>            :       else</a>
+<a name="999"><span class="lineNum">     999 </span><span class="lineNoCov">          0 :         commit_stack_7_retAddr &lt;= _GEN_0[io_commit_meta_TOSW_value];</span></a>
+<a name="1000"><span class="lineNum">    1000 </span><span class="lineNoCov">          0 :       if (~io_commit_push_valid | _GEN_56 | ~_GEN_65) begin</span></a>
+<a name="1001"><span class="lineNum">    1001 </span>            :       end</a>
+<a name="1002"><span class="lineNum">    1002 </span>            :       else</a>
+<a name="1003"><span class="lineNum">    1003 </span><span class="lineNoCov">          0 :         commit_stack_8_retAddr &lt;= _GEN_0[io_commit_meta_TOSW_value];</span></a>
+<a name="1004"><span class="lineNum">    1004 </span><span class="lineNoCov">          0 :       if (~io_commit_push_valid | _GEN_56 | ~_GEN_66) begin</span></a>
+<a name="1005"><span class="lineNum">    1005 </span>            :       end</a>
+<a name="1006"><span class="lineNum">    1006 </span>            :       else</a>
+<a name="1007"><span class="lineNum">    1007 </span><span class="lineNoCov">          0 :         commit_stack_9_retAddr &lt;= _GEN_0[io_commit_meta_TOSW_value];</span></a>
+<a name="1008"><span class="lineNum">    1008 </span><span class="lineNoCov">          0 :       if (~io_commit_push_valid | _GEN_56 | ~_GEN_67) begin</span></a>
+<a name="1009"><span class="lineNum">    1009 </span>            :       end</a>
+<a name="1010"><span class="lineNum">    1010 </span>            :       else</a>
+<a name="1011"><span class="lineNum">    1011 </span><span class="lineNoCov">          0 :         commit_stack_10_retAddr &lt;= _GEN_0[io_commit_meta_TOSW_value];</span></a>
+<a name="1012"><span class="lineNum">    1012 </span><span class="lineNoCov">          0 :       if (~io_commit_push_valid | _GEN_56 | ~_GEN_68) begin</span></a>
+<a name="1013"><span class="lineNum">    1013 </span>            :       end</a>
+<a name="1014"><span class="lineNum">    1014 </span>            :       else</a>
+<a name="1015"><span class="lineNum">    1015 </span><span class="lineNoCov">          0 :         commit_stack_11_retAddr &lt;= _GEN_0[io_commit_meta_TOSW_value];</span></a>
+<a name="1016"><span class="lineNum">    1016 </span><span class="lineNoCov">          0 :       if (~io_commit_push_valid | _GEN_56 | ~_GEN_69) begin</span></a>
+<a name="1017"><span class="lineNum">    1017 </span>            :       end</a>
+<a name="1018"><span class="lineNum">    1018 </span>            :       else</a>
+<a name="1019"><span class="lineNum">    1019 </span><span class="lineNoCov">          0 :         commit_stack_12_retAddr &lt;= _GEN_0[io_commit_meta_TOSW_value];</span></a>
+<a name="1020"><span class="lineNum">    1020 </span><span class="lineNoCov">          0 :       if (~io_commit_push_valid | _GEN_56 | ~_GEN_70) begin</span></a>
+<a name="1021"><span class="lineNum">    1021 </span>            :       end</a>
+<a name="1022"><span class="lineNum">    1022 </span>            :       else</a>
+<a name="1023"><span class="lineNum">    1023 </span><span class="lineNoCov">          0 :         commit_stack_13_retAddr &lt;= _GEN_0[io_commit_meta_TOSW_value];</span></a>
+<a name="1024"><span class="lineNum">    1024 </span><span class="lineNoCov">          0 :       if (~io_commit_push_valid | _GEN_56 | ~_GEN_71) begin</span></a>
+<a name="1025"><span class="lineNum">    1025 </span>            :       end</a>
+<a name="1026"><span class="lineNum">    1026 </span>            :       else</a>
+<a name="1027"><span class="lineNum">    1027 </span><span class="lineNoCov">          0 :         commit_stack_14_retAddr &lt;= _GEN_0[io_commit_meta_TOSW_value];</span></a>
+<a name="1028"><span class="lineNum">    1028 </span><span class="lineNoCov">          0 :       if (~io_commit_push_valid | _GEN_56 | ~(&amp;_nsp_T_2)) begin</span></a>
+<a name="1029"><span class="lineNum">    1029 </span>            :       end</a>
+<a name="1030"><span class="lineNum">    1030 </span>            :       else</a>
+<a name="1031"><span class="lineNum">    1031 </span><span class="lineNoCov">          0 :         commit_stack_15_retAddr &lt;= _GEN_0[io_commit_meta_TOSW_value];</span></a>
+<a name="1032"><span class="lineNum">    1032 </span><span class="lineCov">          2 :       if (realPush &amp; realWriteAddr_value == 5'h0) begin</span></a>
+<a name="1033"><span class="lineNum">    1033 </span><span class="lineCov">          1 :         spec_queue_0_retAddr &lt;= realWriteEntry_retAddr;</span></a>
+<a name="1034"><span class="lineNum">    1034 </span><span class="lineNoCov">          0 :         if (_GEN_9)</span></a>
+<a name="1035"><span class="lineNum">    1035 </span><span class="lineCov">          1 :           spec_queue_0_ctr &lt;= realWriteEntry_next_ctr;</span></a>
+<a name="1036"><span class="lineNum">    1036 </span>            :         else</a>
+<a name="1037"><span class="lineNum">    1037 </span><span class="lineNoCov">          0 :           spec_queue_0_ctr &lt;= s3_missPushEntry_ctr;</span></a>
+<a name="1038"><span class="lineNum">    1038 </span><span class="lineCov">          1 :         spec_nos_0_flag &lt;= realNos_flag;</span></a>
+<a name="1039"><span class="lineNum">    1039 </span><span class="lineCov">          1 :         spec_nos_0_value &lt;= realNos_value;</span></a>
+<a name="1040"><span class="lineNum">    1040 </span>            :       end</a>
+<a name="1041"><span class="lineNum">    1041 </span><span class="lineNoCov">          0 :       if (realPush &amp; realWriteAddr_value == 5'h1) begin</span></a>
+<a name="1042"><span class="lineNum">    1042 </span><span class="lineNoCov">          0 :         spec_queue_1_retAddr &lt;= realWriteEntry_retAddr;</span></a>
+<a name="1043"><span class="lineNum">    1043 </span><span class="lineNoCov">          0 :         if (_GEN_9)</span></a>
+<a name="1044"><span class="lineNum">    1044 </span><span class="lineNoCov">          0 :           spec_queue_1_ctr &lt;= realWriteEntry_next_ctr;</span></a>
+<a name="1045"><span class="lineNum">    1045 </span>            :         else</a>
+<a name="1046"><span class="lineNum">    1046 </span><span class="lineNoCov">          0 :           spec_queue_1_ctr &lt;= s3_missPushEntry_ctr;</span></a>
+<a name="1047"><span class="lineNum">    1047 </span><span class="lineNoCov">          0 :         spec_nos_1_flag &lt;= realNos_flag;</span></a>
+<a name="1048"><span class="lineNum">    1048 </span><span class="lineNoCov">          0 :         spec_nos_1_value &lt;= realNos_value;</span></a>
+<a name="1049"><span class="lineNum">    1049 </span>            :       end</a>
+<a name="1050"><span class="lineNum">    1050 </span><span class="lineNoCov">          0 :       if (realPush &amp; realWriteAddr_value == 5'h2) begin</span></a>
+<a name="1051"><span class="lineNum">    1051 </span><span class="lineNoCov">          0 :         spec_queue_2_retAddr &lt;= realWriteEntry_retAddr;</span></a>
+<a name="1052"><span class="lineNum">    1052 </span><span class="lineNoCov">          0 :         if (_GEN_9)</span></a>
+<a name="1053"><span class="lineNum">    1053 </span><span class="lineNoCov">          0 :           spec_queue_2_ctr &lt;= realWriteEntry_next_ctr;</span></a>
+<a name="1054"><span class="lineNum">    1054 </span>            :         else</a>
+<a name="1055"><span class="lineNum">    1055 </span><span class="lineNoCov">          0 :           spec_queue_2_ctr &lt;= s3_missPushEntry_ctr;</span></a>
+<a name="1056"><span class="lineNum">    1056 </span><span class="lineNoCov">          0 :         spec_nos_2_flag &lt;= realNos_flag;</span></a>
+<a name="1057"><span class="lineNum">    1057 </span><span class="lineNoCov">          0 :         spec_nos_2_value &lt;= realNos_value;</span></a>
+<a name="1058"><span class="lineNum">    1058 </span>            :       end</a>
+<a name="1059"><span class="lineNum">    1059 </span><span class="lineNoCov">          0 :       if (realPush &amp; realWriteAddr_value == 5'h3) begin</span></a>
+<a name="1060"><span class="lineNum">    1060 </span><span class="lineNoCov">          0 :         spec_queue_3_retAddr &lt;= realWriteEntry_retAddr;</span></a>
+<a name="1061"><span class="lineNum">    1061 </span><span class="lineNoCov">          0 :         if (_GEN_9)</span></a>
+<a name="1062"><span class="lineNum">    1062 </span><span class="lineNoCov">          0 :           spec_queue_3_ctr &lt;= realWriteEntry_next_ctr;</span></a>
+<a name="1063"><span class="lineNum">    1063 </span>            :         else</a>
+<a name="1064"><span class="lineNum">    1064 </span><span class="lineNoCov">          0 :           spec_queue_3_ctr &lt;= s3_missPushEntry_ctr;</span></a>
+<a name="1065"><span class="lineNum">    1065 </span><span class="lineNoCov">          0 :         spec_nos_3_flag &lt;= realNos_flag;</span></a>
+<a name="1066"><span class="lineNum">    1066 </span><span class="lineNoCov">          0 :         spec_nos_3_value &lt;= realNos_value;</span></a>
+<a name="1067"><span class="lineNum">    1067 </span>            :       end</a>
+<a name="1068"><span class="lineNum">    1068 </span><span class="lineNoCov">          0 :       if (realPush &amp; realWriteAddr_value == 5'h4) begin</span></a>
+<a name="1069"><span class="lineNum">    1069 </span><span class="lineNoCov">          0 :         spec_queue_4_retAddr &lt;= realWriteEntry_retAddr;</span></a>
+<a name="1070"><span class="lineNum">    1070 </span><span class="lineNoCov">          0 :         if (_GEN_9)</span></a>
+<a name="1071"><span class="lineNum">    1071 </span><span class="lineNoCov">          0 :           spec_queue_4_ctr &lt;= realWriteEntry_next_ctr;</span></a>
+<a name="1072"><span class="lineNum">    1072 </span>            :         else</a>
+<a name="1073"><span class="lineNum">    1073 </span><span class="lineNoCov">          0 :           spec_queue_4_ctr &lt;= s3_missPushEntry_ctr;</span></a>
+<a name="1074"><span class="lineNum">    1074 </span><span class="lineNoCov">          0 :         spec_nos_4_flag &lt;= realNos_flag;</span></a>
+<a name="1075"><span class="lineNum">    1075 </span><span class="lineNoCov">          0 :         spec_nos_4_value &lt;= realNos_value;</span></a>
+<a name="1076"><span class="lineNum">    1076 </span>            :       end</a>
+<a name="1077"><span class="lineNum">    1077 </span><span class="lineCov">          2 :       if (realPush &amp; realWriteAddr_value == 5'h5) begin</span></a>
+<a name="1078"><span class="lineNum">    1078 </span><span class="lineCov">          1 :         spec_queue_5_retAddr &lt;= realWriteEntry_retAddr;</span></a>
+<a name="1079"><span class="lineNum">    1079 </span><span class="lineNoCov">          0 :         if (_GEN_9)</span></a>
+<a name="1080"><span class="lineNum">    1080 </span><span class="lineCov">          1 :           spec_queue_5_ctr &lt;= realWriteEntry_next_ctr;</span></a>
+<a name="1081"><span class="lineNum">    1081 </span>            :         else</a>
+<a name="1082"><span class="lineNum">    1082 </span><span class="lineNoCov">          0 :           spec_queue_5_ctr &lt;= s3_missPushEntry_ctr;</span></a>
+<a name="1083"><span class="lineNum">    1083 </span><span class="lineCov">          1 :         spec_nos_5_flag &lt;= realNos_flag;</span></a>
+<a name="1084"><span class="lineNum">    1084 </span><span class="lineCov">          1 :         spec_nos_5_value &lt;= realNos_value;</span></a>
+<a name="1085"><span class="lineNum">    1085 </span>            :       end</a>
+<a name="1086"><span class="lineNum">    1086 </span><span class="lineNoCov">          0 :       if (realPush &amp; realWriteAddr_value == 5'h6) begin</span></a>
+<a name="1087"><span class="lineNum">    1087 </span><span class="lineNoCov">          0 :         spec_queue_6_retAddr &lt;= realWriteEntry_retAddr;</span></a>
+<a name="1088"><span class="lineNum">    1088 </span><span class="lineNoCov">          0 :         if (_GEN_9)</span></a>
+<a name="1089"><span class="lineNum">    1089 </span><span class="lineNoCov">          0 :           spec_queue_6_ctr &lt;= realWriteEntry_next_ctr;</span></a>
+<a name="1090"><span class="lineNum">    1090 </span>            :         else</a>
+<a name="1091"><span class="lineNum">    1091 </span><span class="lineNoCov">          0 :           spec_queue_6_ctr &lt;= s3_missPushEntry_ctr;</span></a>
+<a name="1092"><span class="lineNum">    1092 </span><span class="lineNoCov">          0 :         spec_nos_6_flag &lt;= realNos_flag;</span></a>
+<a name="1093"><span class="lineNum">    1093 </span><span class="lineNoCov">          0 :         spec_nos_6_value &lt;= realNos_value;</span></a>
+<a name="1094"><span class="lineNum">    1094 </span>            :       end</a>
+<a name="1095"><span class="lineNum">    1095 </span><span class="lineCov">          2 :       if (realPush &amp; realWriteAddr_value == 5'h7) begin</span></a>
+<a name="1096"><span class="lineNum">    1096 </span><span class="lineCov">          1 :         spec_queue_7_retAddr &lt;= realWriteEntry_retAddr;</span></a>
+<a name="1097"><span class="lineNum">    1097 </span><span class="lineNoCov">          0 :         if (_GEN_9)</span></a>
+<a name="1098"><span class="lineNum">    1098 </span><span class="lineCov">          1 :           spec_queue_7_ctr &lt;= realWriteEntry_next_ctr;</span></a>
+<a name="1099"><span class="lineNum">    1099 </span>            :         else</a>
+<a name="1100"><span class="lineNum">    1100 </span><span class="lineNoCov">          0 :           spec_queue_7_ctr &lt;= s3_missPushEntry_ctr;</span></a>
+<a name="1101"><span class="lineNum">    1101 </span><span class="lineCov">          1 :         spec_nos_7_flag &lt;= realNos_flag;</span></a>
+<a name="1102"><span class="lineNum">    1102 </span><span class="lineCov">          1 :         spec_nos_7_value &lt;= realNos_value;</span></a>
+<a name="1103"><span class="lineNum">    1103 </span>            :       end</a>
+<a name="1104"><span class="lineNum">    1104 </span><span class="lineNoCov">          0 :       if (realPush &amp; realWriteAddr_value == 5'h8) begin</span></a>
+<a name="1105"><span class="lineNum">    1105 </span><span class="lineNoCov">          0 :         spec_queue_8_retAddr &lt;= realWriteEntry_retAddr;</span></a>
+<a name="1106"><span class="lineNum">    1106 </span><span class="lineNoCov">          0 :         if (_GEN_9)</span></a>
+<a name="1107"><span class="lineNum">    1107 </span><span class="lineNoCov">          0 :           spec_queue_8_ctr &lt;= realWriteEntry_next_ctr;</span></a>
+<a name="1108"><span class="lineNum">    1108 </span>            :         else</a>
+<a name="1109"><span class="lineNum">    1109 </span><span class="lineNoCov">          0 :           spec_queue_8_ctr &lt;= s3_missPushEntry_ctr;</span></a>
+<a name="1110"><span class="lineNum">    1110 </span><span class="lineNoCov">          0 :         spec_nos_8_flag &lt;= realNos_flag;</span></a>
+<a name="1111"><span class="lineNum">    1111 </span><span class="lineNoCov">          0 :         spec_nos_8_value &lt;= realNos_value;</span></a>
+<a name="1112"><span class="lineNum">    1112 </span>            :       end</a>
+<a name="1113"><span class="lineNum">    1113 </span><span class="lineNoCov">          0 :       if (realPush &amp; realWriteAddr_value == 5'h9) begin</span></a>
+<a name="1114"><span class="lineNum">    1114 </span><span class="lineNoCov">          0 :         spec_queue_9_retAddr &lt;= realWriteEntry_retAddr;</span></a>
+<a name="1115"><span class="lineNum">    1115 </span><span class="lineNoCov">          0 :         if (_GEN_9)</span></a>
+<a name="1116"><span class="lineNum">    1116 </span><span class="lineNoCov">          0 :           spec_queue_9_ctr &lt;= realWriteEntry_next_ctr;</span></a>
+<a name="1117"><span class="lineNum">    1117 </span>            :         else</a>
+<a name="1118"><span class="lineNum">    1118 </span><span class="lineNoCov">          0 :           spec_queue_9_ctr &lt;= s3_missPushEntry_ctr;</span></a>
+<a name="1119"><span class="lineNum">    1119 </span><span class="lineNoCov">          0 :         spec_nos_9_flag &lt;= realNos_flag;</span></a>
+<a name="1120"><span class="lineNum">    1120 </span><span class="lineNoCov">          0 :         spec_nos_9_value &lt;= realNos_value;</span></a>
+<a name="1121"><span class="lineNum">    1121 </span>            :       end</a>
+<a name="1122"><span class="lineNum">    1122 </span><span class="lineNoCov">          0 :       if (realPush &amp; realWriteAddr_value == 5'hA) begin</span></a>
+<a name="1123"><span class="lineNum">    1123 </span><span class="lineNoCov">          0 :         spec_queue_10_retAddr &lt;= realWriteEntry_retAddr;</span></a>
+<a name="1124"><span class="lineNum">    1124 </span><span class="lineNoCov">          0 :         if (_GEN_9)</span></a>
+<a name="1125"><span class="lineNum">    1125 </span><span class="lineNoCov">          0 :           spec_queue_10_ctr &lt;= realWriteEntry_next_ctr;</span></a>
+<a name="1126"><span class="lineNum">    1126 </span>            :         else</a>
+<a name="1127"><span class="lineNum">    1127 </span><span class="lineNoCov">          0 :           spec_queue_10_ctr &lt;= s3_missPushEntry_ctr;</span></a>
+<a name="1128"><span class="lineNum">    1128 </span><span class="lineNoCov">          0 :         spec_nos_10_flag &lt;= realNos_flag;</span></a>
+<a name="1129"><span class="lineNum">    1129 </span><span class="lineNoCov">          0 :         spec_nos_10_value &lt;= realNos_value;</span></a>
+<a name="1130"><span class="lineNum">    1130 </span>            :       end</a>
+<a name="1131"><span class="lineNum">    1131 </span><span class="lineNoCov">          0 :       if (realPush &amp; realWriteAddr_value == 5'hB) begin</span></a>
+<a name="1132"><span class="lineNum">    1132 </span><span class="lineNoCov">          0 :         spec_queue_11_retAddr &lt;= realWriteEntry_retAddr;</span></a>
+<a name="1133"><span class="lineNum">    1133 </span><span class="lineNoCov">          0 :         if (_GEN_9)</span></a>
+<a name="1134"><span class="lineNum">    1134 </span><span class="lineNoCov">          0 :           spec_queue_11_ctr &lt;= realWriteEntry_next_ctr;</span></a>
+<a name="1135"><span class="lineNum">    1135 </span>            :         else</a>
+<a name="1136"><span class="lineNum">    1136 </span><span class="lineNoCov">          0 :           spec_queue_11_ctr &lt;= s3_missPushEntry_ctr;</span></a>
+<a name="1137"><span class="lineNum">    1137 </span><span class="lineNoCov">          0 :         spec_nos_11_flag &lt;= realNos_flag;</span></a>
+<a name="1138"><span class="lineNum">    1138 </span><span class="lineNoCov">          0 :         spec_nos_11_value &lt;= realNos_value;</span></a>
+<a name="1139"><span class="lineNum">    1139 </span>            :       end</a>
+<a name="1140"><span class="lineNum">    1140 </span><span class="lineNoCov">          0 :       if (realPush &amp; realWriteAddr_value == 5'hC) begin</span></a>
+<a name="1141"><span class="lineNum">    1141 </span><span class="lineNoCov">          0 :         spec_queue_12_retAddr &lt;= realWriteEntry_retAddr;</span></a>
+<a name="1142"><span class="lineNum">    1142 </span><span class="lineNoCov">          0 :         if (_GEN_9)</span></a>
+<a name="1143"><span class="lineNum">    1143 </span><span class="lineNoCov">          0 :           spec_queue_12_ctr &lt;= realWriteEntry_next_ctr;</span></a>
+<a name="1144"><span class="lineNum">    1144 </span>            :         else</a>
+<a name="1145"><span class="lineNum">    1145 </span><span class="lineNoCov">          0 :           spec_queue_12_ctr &lt;= s3_missPushEntry_ctr;</span></a>
+<a name="1146"><span class="lineNum">    1146 </span><span class="lineNoCov">          0 :         spec_nos_12_flag &lt;= realNos_flag;</span></a>
+<a name="1147"><span class="lineNum">    1147 </span><span class="lineNoCov">          0 :         spec_nos_12_value &lt;= realNos_value;</span></a>
+<a name="1148"><span class="lineNum">    1148 </span>            :       end</a>
+<a name="1149"><span class="lineNum">    1149 </span><span class="lineCov">          2 :       if (realPush &amp; realWriteAddr_value == 5'hD) begin</span></a>
+<a name="1150"><span class="lineNum">    1150 </span><span class="lineCov">          1 :         spec_queue_13_retAddr &lt;= realWriteEntry_retAddr;</span></a>
+<a name="1151"><span class="lineNum">    1151 </span><span class="lineNoCov">          0 :         if (_GEN_9)</span></a>
+<a name="1152"><span class="lineNum">    1152 </span><span class="lineCov">          1 :           spec_queue_13_ctr &lt;= realWriteEntry_next_ctr;</span></a>
+<a name="1153"><span class="lineNum">    1153 </span>            :         else</a>
+<a name="1154"><span class="lineNum">    1154 </span><span class="lineNoCov">          0 :           spec_queue_13_ctr &lt;= s3_missPushEntry_ctr;</span></a>
+<a name="1155"><span class="lineNum">    1155 </span><span class="lineCov">          1 :         spec_nos_13_flag &lt;= realNos_flag;</span></a>
+<a name="1156"><span class="lineNum">    1156 </span><span class="lineCov">          1 :         spec_nos_13_value &lt;= realNos_value;</span></a>
+<a name="1157"><span class="lineNum">    1157 </span>            :       end</a>
+<a name="1158"><span class="lineNum">    1158 </span><span class="lineNoCov">          0 :       if (realPush &amp; realWriteAddr_value == 5'hE) begin</span></a>
+<a name="1159"><span class="lineNum">    1159 </span><span class="lineNoCov">          0 :         spec_queue_14_retAddr &lt;= realWriteEntry_retAddr;</span></a>
+<a name="1160"><span class="lineNum">    1160 </span><span class="lineNoCov">          0 :         if (_GEN_9)</span></a>
+<a name="1161"><span class="lineNum">    1161 </span><span class="lineNoCov">          0 :           spec_queue_14_ctr &lt;= realWriteEntry_next_ctr;</span></a>
+<a name="1162"><span class="lineNum">    1162 </span>            :         else</a>
+<a name="1163"><span class="lineNum">    1163 </span><span class="lineNoCov">          0 :           spec_queue_14_ctr &lt;= s3_missPushEntry_ctr;</span></a>
+<a name="1164"><span class="lineNum">    1164 </span><span class="lineNoCov">          0 :         spec_nos_14_flag &lt;= realNos_flag;</span></a>
+<a name="1165"><span class="lineNum">    1165 </span><span class="lineNoCov">          0 :         spec_nos_14_value &lt;= realNos_value;</span></a>
+<a name="1166"><span class="lineNum">    1166 </span>            :       end</a>
+<a name="1167"><span class="lineNum">    1167 </span><span class="lineCov">          2 :       if (realPush &amp; realWriteAddr_value == 5'hF) begin</span></a>
+<a name="1168"><span class="lineNum">    1168 </span><span class="lineCov">          1 :         spec_queue_15_retAddr &lt;= realWriteEntry_retAddr;</span></a>
+<a name="1169"><span class="lineNum">    1169 </span><span class="lineNoCov">          0 :         if (_GEN_9)</span></a>
+<a name="1170"><span class="lineNum">    1170 </span><span class="lineCov">          1 :           spec_queue_15_ctr &lt;= realWriteEntry_next_ctr;</span></a>
+<a name="1171"><span class="lineNum">    1171 </span>            :         else</a>
+<a name="1172"><span class="lineNum">    1172 </span><span class="lineNoCov">          0 :           spec_queue_15_ctr &lt;= s3_missPushEntry_ctr;</span></a>
+<a name="1173"><span class="lineNum">    1173 </span><span class="lineCov">          1 :         spec_nos_15_flag &lt;= realNos_flag;</span></a>
+<a name="1174"><span class="lineNum">    1174 </span><span class="lineCov">          1 :         spec_nos_15_value &lt;= realNos_value;</span></a>
+<a name="1175"><span class="lineNum">    1175 </span>            :       end</a>
+<a name="1176"><span class="lineNum">    1176 </span><span class="lineNoCov">          0 :       if (realPush &amp; realWriteAddr_value == 5'h10) begin</span></a>
+<a name="1177"><span class="lineNum">    1177 </span><span class="lineNoCov">          0 :         spec_queue_16_retAddr &lt;= realWriteEntry_retAddr;</span></a>
+<a name="1178"><span class="lineNum">    1178 </span><span class="lineNoCov">          0 :         if (_GEN_9)</span></a>
+<a name="1179"><span class="lineNum">    1179 </span><span class="lineNoCov">          0 :           spec_queue_16_ctr &lt;= realWriteEntry_next_ctr;</span></a>
+<a name="1180"><span class="lineNum">    1180 </span>            :         else</a>
+<a name="1181"><span class="lineNum">    1181 </span><span class="lineNoCov">          0 :           spec_queue_16_ctr &lt;= s3_missPushEntry_ctr;</span></a>
+<a name="1182"><span class="lineNum">    1182 </span><span class="lineNoCov">          0 :         spec_nos_16_flag &lt;= realNos_flag;</span></a>
+<a name="1183"><span class="lineNum">    1183 </span><span class="lineNoCov">          0 :         spec_nos_16_value &lt;= realNos_value;</span></a>
+<a name="1184"><span class="lineNum">    1184 </span>            :       end</a>
+<a name="1185"><span class="lineNum">    1185 </span><span class="lineCov">          2 :       if (realPush &amp; realWriteAddr_value == 5'h11) begin</span></a>
+<a name="1186"><span class="lineNum">    1186 </span><span class="lineCov">          1 :         spec_queue_17_retAddr &lt;= realWriteEntry_retAddr;</span></a>
+<a name="1187"><span class="lineNum">    1187 </span><span class="lineNoCov">          0 :         if (_GEN_9)</span></a>
+<a name="1188"><span class="lineNum">    1188 </span><span class="lineCov">          1 :           spec_queue_17_ctr &lt;= realWriteEntry_next_ctr;</span></a>
+<a name="1189"><span class="lineNum">    1189 </span>            :         else</a>
+<a name="1190"><span class="lineNum">    1190 </span><span class="lineNoCov">          0 :           spec_queue_17_ctr &lt;= s3_missPushEntry_ctr;</span></a>
+<a name="1191"><span class="lineNum">    1191 </span><span class="lineCov">          1 :         spec_nos_17_flag &lt;= realNos_flag;</span></a>
+<a name="1192"><span class="lineNum">    1192 </span><span class="lineCov">          1 :         spec_nos_17_value &lt;= realNos_value;</span></a>
+<a name="1193"><span class="lineNum">    1193 </span>            :       end</a>
+<a name="1194"><span class="lineNum">    1194 </span><span class="lineNoCov">          0 :       if (realPush &amp; realWriteAddr_value == 5'h12) begin</span></a>
+<a name="1195"><span class="lineNum">    1195 </span><span class="lineNoCov">          0 :         spec_queue_18_retAddr &lt;= realWriteEntry_retAddr;</span></a>
+<a name="1196"><span class="lineNum">    1196 </span><span class="lineNoCov">          0 :         if (_GEN_9)</span></a>
+<a name="1197"><span class="lineNum">    1197 </span><span class="lineNoCov">          0 :           spec_queue_18_ctr &lt;= realWriteEntry_next_ctr;</span></a>
+<a name="1198"><span class="lineNum">    1198 </span>            :         else</a>
+<a name="1199"><span class="lineNum">    1199 </span><span class="lineNoCov">          0 :           spec_queue_18_ctr &lt;= s3_missPushEntry_ctr;</span></a>
+<a name="1200"><span class="lineNum">    1200 </span><span class="lineNoCov">          0 :         spec_nos_18_flag &lt;= realNos_flag;</span></a>
+<a name="1201"><span class="lineNum">    1201 </span><span class="lineNoCov">          0 :         spec_nos_18_value &lt;= realNos_value;</span></a>
+<a name="1202"><span class="lineNum">    1202 </span>            :       end</a>
+<a name="1203"><span class="lineNum">    1203 </span><span class="lineNoCov">          0 :       if (realPush &amp; realWriteAddr_value == 5'h13) begin</span></a>
+<a name="1204"><span class="lineNum">    1204 </span><span class="lineNoCov">          0 :         spec_queue_19_retAddr &lt;= realWriteEntry_retAddr;</span></a>
+<a name="1205"><span class="lineNum">    1205 </span><span class="lineNoCov">          0 :         if (_GEN_9)</span></a>
+<a name="1206"><span class="lineNum">    1206 </span><span class="lineNoCov">          0 :           spec_queue_19_ctr &lt;= realWriteEntry_next_ctr;</span></a>
+<a name="1207"><span class="lineNum">    1207 </span>            :         else</a>
+<a name="1208"><span class="lineNum">    1208 </span><span class="lineNoCov">          0 :           spec_queue_19_ctr &lt;= s3_missPushEntry_ctr;</span></a>
+<a name="1209"><span class="lineNum">    1209 </span><span class="lineNoCov">          0 :         spec_nos_19_flag &lt;= realNos_flag;</span></a>
+<a name="1210"><span class="lineNum">    1210 </span><span class="lineNoCov">          0 :         spec_nos_19_value &lt;= realNos_value;</span></a>
+<a name="1211"><span class="lineNum">    1211 </span>            :       end</a>
+<a name="1212"><span class="lineNum">    1212 </span><span class="lineNoCov">          0 :       if (realPush &amp; realWriteAddr_value == 5'h14) begin</span></a>
+<a name="1213"><span class="lineNum">    1213 </span><span class="lineNoCov">          0 :         spec_queue_20_retAddr &lt;= realWriteEntry_retAddr;</span></a>
+<a name="1214"><span class="lineNum">    1214 </span><span class="lineNoCov">          0 :         if (_GEN_9)</span></a>
+<a name="1215"><span class="lineNum">    1215 </span><span class="lineNoCov">          0 :           spec_queue_20_ctr &lt;= realWriteEntry_next_ctr;</span></a>
+<a name="1216"><span class="lineNum">    1216 </span>            :         else</a>
+<a name="1217"><span class="lineNum">    1217 </span><span class="lineNoCov">          0 :           spec_queue_20_ctr &lt;= s3_missPushEntry_ctr;</span></a>
+<a name="1218"><span class="lineNum">    1218 </span><span class="lineNoCov">          0 :         spec_nos_20_flag &lt;= realNos_flag;</span></a>
+<a name="1219"><span class="lineNum">    1219 </span><span class="lineNoCov">          0 :         spec_nos_20_value &lt;= realNos_value;</span></a>
+<a name="1220"><span class="lineNum">    1220 </span>            :       end</a>
+<a name="1221"><span class="lineNum">    1221 </span><span class="lineNoCov">          0 :       if (realPush &amp; realWriteAddr_value == 5'h15) begin</span></a>
+<a name="1222"><span class="lineNum">    1222 </span><span class="lineNoCov">          0 :         spec_queue_21_retAddr &lt;= realWriteEntry_retAddr;</span></a>
+<a name="1223"><span class="lineNum">    1223 </span><span class="lineNoCov">          0 :         if (_GEN_9)</span></a>
+<a name="1224"><span class="lineNum">    1224 </span><span class="lineNoCov">          0 :           spec_queue_21_ctr &lt;= realWriteEntry_next_ctr;</span></a>
+<a name="1225"><span class="lineNum">    1225 </span>            :         else</a>
+<a name="1226"><span class="lineNum">    1226 </span><span class="lineNoCov">          0 :           spec_queue_21_ctr &lt;= s3_missPushEntry_ctr;</span></a>
+<a name="1227"><span class="lineNum">    1227 </span><span class="lineNoCov">          0 :         spec_nos_21_flag &lt;= realNos_flag;</span></a>
+<a name="1228"><span class="lineNum">    1228 </span><span class="lineNoCov">          0 :         spec_nos_21_value &lt;= realNos_value;</span></a>
+<a name="1229"><span class="lineNum">    1229 </span>            :       end</a>
+<a name="1230"><span class="lineNum">    1230 </span><span class="lineNoCov">          0 :       if (realPush &amp; realWriteAddr_value == 5'h16) begin</span></a>
+<a name="1231"><span class="lineNum">    1231 </span><span class="lineNoCov">          0 :         spec_queue_22_retAddr &lt;= realWriteEntry_retAddr;</span></a>
+<a name="1232"><span class="lineNum">    1232 </span><span class="lineNoCov">          0 :         if (_GEN_9)</span></a>
+<a name="1233"><span class="lineNum">    1233 </span><span class="lineNoCov">          0 :           spec_queue_22_ctr &lt;= realWriteEntry_next_ctr;</span></a>
+<a name="1234"><span class="lineNum">    1234 </span>            :         else</a>
+<a name="1235"><span class="lineNum">    1235 </span><span class="lineNoCov">          0 :           spec_queue_22_ctr &lt;= s3_missPushEntry_ctr;</span></a>
+<a name="1236"><span class="lineNum">    1236 </span><span class="lineNoCov">          0 :         spec_nos_22_flag &lt;= realNos_flag;</span></a>
+<a name="1237"><span class="lineNum">    1237 </span><span class="lineNoCov">          0 :         spec_nos_22_value &lt;= realNos_value;</span></a>
+<a name="1238"><span class="lineNum">    1238 </span>            :       end</a>
+<a name="1239"><span class="lineNum">    1239 </span><span class="lineNoCov">          0 :       if (realPush &amp; realWriteAddr_value == 5'h17) begin</span></a>
+<a name="1240"><span class="lineNum">    1240 </span><span class="lineNoCov">          0 :         spec_queue_23_retAddr &lt;= realWriteEntry_retAddr;</span></a>
+<a name="1241"><span class="lineNum">    1241 </span><span class="lineNoCov">          0 :         if (_GEN_9)</span></a>
+<a name="1242"><span class="lineNum">    1242 </span><span class="lineNoCov">          0 :           spec_queue_23_ctr &lt;= realWriteEntry_next_ctr;</span></a>
+<a name="1243"><span class="lineNum">    1243 </span>            :         else</a>
+<a name="1244"><span class="lineNum">    1244 </span><span class="lineNoCov">          0 :           spec_queue_23_ctr &lt;= s3_missPushEntry_ctr;</span></a>
+<a name="1245"><span class="lineNum">    1245 </span><span class="lineNoCov">          0 :         spec_nos_23_flag &lt;= realNos_flag;</span></a>
+<a name="1246"><span class="lineNum">    1246 </span><span class="lineNoCov">          0 :         spec_nos_23_value &lt;= realNos_value;</span></a>
+<a name="1247"><span class="lineNum">    1247 </span>            :       end</a>
+<a name="1248"><span class="lineNum">    1248 </span><span class="lineCov">          2 :       if (realPush &amp; realWriteAddr_value == 5'h18) begin</span></a>
+<a name="1249"><span class="lineNum">    1249 </span><span class="lineCov">          1 :         spec_queue_24_retAddr &lt;= realWriteEntry_retAddr;</span></a>
+<a name="1250"><span class="lineNum">    1250 </span><span class="lineNoCov">          0 :         if (_GEN_9)</span></a>
+<a name="1251"><span class="lineNum">    1251 </span><span class="lineCov">          1 :           spec_queue_24_ctr &lt;= realWriteEntry_next_ctr;</span></a>
+<a name="1252"><span class="lineNum">    1252 </span>            :         else</a>
+<a name="1253"><span class="lineNum">    1253 </span><span class="lineNoCov">          0 :           spec_queue_24_ctr &lt;= s3_missPushEntry_ctr;</span></a>
+<a name="1254"><span class="lineNum">    1254 </span><span class="lineCov">          1 :         spec_nos_24_flag &lt;= realNos_flag;</span></a>
+<a name="1255"><span class="lineNum">    1255 </span><span class="lineCov">          1 :         spec_nos_24_value &lt;= realNos_value;</span></a>
+<a name="1256"><span class="lineNum">    1256 </span>            :       end</a>
+<a name="1257"><span class="lineNum">    1257 </span><span class="lineNoCov">          0 :       if (realPush &amp; realWriteAddr_value == 5'h19) begin</span></a>
+<a name="1258"><span class="lineNum">    1258 </span><span class="lineNoCov">          0 :         spec_queue_25_retAddr &lt;= realWriteEntry_retAddr;</span></a>
+<a name="1259"><span class="lineNum">    1259 </span><span class="lineNoCov">          0 :         if (_GEN_9)</span></a>
+<a name="1260"><span class="lineNum">    1260 </span><span class="lineNoCov">          0 :           spec_queue_25_ctr &lt;= realWriteEntry_next_ctr;</span></a>
+<a name="1261"><span class="lineNum">    1261 </span>            :         else</a>
+<a name="1262"><span class="lineNum">    1262 </span><span class="lineNoCov">          0 :           spec_queue_25_ctr &lt;= s3_missPushEntry_ctr;</span></a>
+<a name="1263"><span class="lineNum">    1263 </span><span class="lineNoCov">          0 :         spec_nos_25_flag &lt;= realNos_flag;</span></a>
+<a name="1264"><span class="lineNum">    1264 </span><span class="lineNoCov">          0 :         spec_nos_25_value &lt;= realNos_value;</span></a>
+<a name="1265"><span class="lineNum">    1265 </span>            :       end</a>
+<a name="1266"><span class="lineNum">    1266 </span><span class="lineNoCov">          0 :       if (realPush &amp; realWriteAddr_value == 5'h1A) begin</span></a>
+<a name="1267"><span class="lineNum">    1267 </span><span class="lineNoCov">          0 :         spec_queue_26_retAddr &lt;= realWriteEntry_retAddr;</span></a>
+<a name="1268"><span class="lineNum">    1268 </span><span class="lineNoCov">          0 :         if (_GEN_9)</span></a>
+<a name="1269"><span class="lineNum">    1269 </span><span class="lineNoCov">          0 :           spec_queue_26_ctr &lt;= realWriteEntry_next_ctr;</span></a>
+<a name="1270"><span class="lineNum">    1270 </span>            :         else</a>
+<a name="1271"><span class="lineNum">    1271 </span><span class="lineNoCov">          0 :           spec_queue_26_ctr &lt;= s3_missPushEntry_ctr;</span></a>
+<a name="1272"><span class="lineNum">    1272 </span><span class="lineNoCov">          0 :         spec_nos_26_flag &lt;= realNos_flag;</span></a>
+<a name="1273"><span class="lineNum">    1273 </span><span class="lineNoCov">          0 :         spec_nos_26_value &lt;= realNos_value;</span></a>
+<a name="1274"><span class="lineNum">    1274 </span>            :       end</a>
+<a name="1275"><span class="lineNum">    1275 </span><span class="lineNoCov">          0 :       if (realPush &amp; realWriteAddr_value == 5'h1B) begin</span></a>
+<a name="1276"><span class="lineNum">    1276 </span><span class="lineNoCov">          0 :         spec_queue_27_retAddr &lt;= realWriteEntry_retAddr;</span></a>
+<a name="1277"><span class="lineNum">    1277 </span><span class="lineNoCov">          0 :         if (_GEN_9)</span></a>
+<a name="1278"><span class="lineNum">    1278 </span><span class="lineNoCov">          0 :           spec_queue_27_ctr &lt;= realWriteEntry_next_ctr;</span></a>
+<a name="1279"><span class="lineNum">    1279 </span>            :         else</a>
+<a name="1280"><span class="lineNum">    1280 </span><span class="lineNoCov">          0 :           spec_queue_27_ctr &lt;= s3_missPushEntry_ctr;</span></a>
+<a name="1281"><span class="lineNum">    1281 </span><span class="lineNoCov">          0 :         spec_nos_27_flag &lt;= realNos_flag;</span></a>
+<a name="1282"><span class="lineNum">    1282 </span><span class="lineNoCov">          0 :         spec_nos_27_value &lt;= realNos_value;</span></a>
+<a name="1283"><span class="lineNum">    1283 </span>            :       end</a>
+<a name="1284"><span class="lineNum">    1284 </span><span class="lineCov">          2 :       if (realPush &amp; realWriteAddr_value == 5'h1C) begin</span></a>
+<a name="1285"><span class="lineNum">    1285 </span><span class="lineCov">          1 :         spec_queue_28_retAddr &lt;= realWriteEntry_retAddr;</span></a>
+<a name="1286"><span class="lineNum">    1286 </span><span class="lineNoCov">          0 :         if (_GEN_9)</span></a>
+<a name="1287"><span class="lineNum">    1287 </span><span class="lineCov">          1 :           spec_queue_28_ctr &lt;= realWriteEntry_next_ctr;</span></a>
+<a name="1288"><span class="lineNum">    1288 </span>            :         else</a>
+<a name="1289"><span class="lineNum">    1289 </span><span class="lineNoCov">          0 :           spec_queue_28_ctr &lt;= s3_missPushEntry_ctr;</span></a>
+<a name="1290"><span class="lineNum">    1290 </span><span class="lineCov">          1 :         spec_nos_28_flag &lt;= realNos_flag;</span></a>
+<a name="1291"><span class="lineNum">    1291 </span><span class="lineCov">          1 :         spec_nos_28_value &lt;= realNos_value;</span></a>
+<a name="1292"><span class="lineNum">    1292 </span>            :       end</a>
+<a name="1293"><span class="lineNum">    1293 </span><span class="lineNoCov">          0 :       if (realPush &amp; realWriteAddr_value == 5'h1D) begin</span></a>
+<a name="1294"><span class="lineNum">    1294 </span><span class="lineNoCov">          0 :         spec_queue_29_retAddr &lt;= realWriteEntry_retAddr;</span></a>
+<a name="1295"><span class="lineNum">    1295 </span><span class="lineNoCov">          0 :         if (_GEN_9)</span></a>
+<a name="1296"><span class="lineNum">    1296 </span><span class="lineNoCov">          0 :           spec_queue_29_ctr &lt;= realWriteEntry_next_ctr;</span></a>
+<a name="1297"><span class="lineNum">    1297 </span>            :         else</a>
+<a name="1298"><span class="lineNum">    1298 </span><span class="lineNoCov">          0 :           spec_queue_29_ctr &lt;= s3_missPushEntry_ctr;</span></a>
+<a name="1299"><span class="lineNum">    1299 </span><span class="lineNoCov">          0 :         spec_nos_29_flag &lt;= realNos_flag;</span></a>
+<a name="1300"><span class="lineNum">    1300 </span><span class="lineNoCov">          0 :         spec_nos_29_value &lt;= realNos_value;</span></a>
+<a name="1301"><span class="lineNum">    1301 </span>            :       end</a>
+<a name="1302"><span class="lineNum">    1302 </span><span class="lineNoCov">          0 :       if (realPush &amp; realWriteAddr_value == 5'h1E) begin</span></a>
+<a name="1303"><span class="lineNum">    1303 </span><span class="lineNoCov">          0 :         spec_queue_30_retAddr &lt;= realWriteEntry_retAddr;</span></a>
+<a name="1304"><span class="lineNum">    1304 </span><span class="lineNoCov">          0 :         if (_GEN_9)</span></a>
+<a name="1305"><span class="lineNum">    1305 </span><span class="lineNoCov">          0 :           spec_queue_30_ctr &lt;= realWriteEntry_next_ctr;</span></a>
+<a name="1306"><span class="lineNum">    1306 </span>            :         else</a>
+<a name="1307"><span class="lineNum">    1307 </span><span class="lineNoCov">          0 :           spec_queue_30_ctr &lt;= s3_missPushEntry_ctr;</span></a>
+<a name="1308"><span class="lineNum">    1308 </span><span class="lineNoCov">          0 :         spec_nos_30_flag &lt;= realNos_flag;</span></a>
+<a name="1309"><span class="lineNum">    1309 </span><span class="lineNoCov">          0 :         spec_nos_30_value &lt;= realNos_value;</span></a>
+<a name="1310"><span class="lineNum">    1310 </span>            :       end</a>
+<a name="1311"><span class="lineNum">    1311 </span><span class="lineNoCov">          0 :       if (realPush &amp; (&amp;realWriteAddr_value)) begin</span></a>
+<a name="1312"><span class="lineNum">    1312 </span><span class="lineNoCov">          0 :         spec_queue_31_retAddr &lt;= realWriteEntry_retAddr;</span></a>
+<a name="1313"><span class="lineNum">    1313 </span><span class="lineNoCov">          0 :         if (_GEN_9)</span></a>
+<a name="1314"><span class="lineNum">    1314 </span><span class="lineNoCov">          0 :           spec_queue_31_ctr &lt;= realWriteEntry_next_ctr;</span></a>
+<a name="1315"><span class="lineNum">    1315 </span>            :         else</a>
+<a name="1316"><span class="lineNum">    1316 </span><span class="lineNoCov">          0 :           spec_queue_31_ctr &lt;= s3_missPushEntry_ctr;</span></a>
+<a name="1317"><span class="lineNum">    1317 </span><span class="lineNoCov">          0 :         spec_nos_31_flag &lt;= realNos_flag;</span></a>
+<a name="1318"><span class="lineNum">    1318 </span><span class="lineNoCov">          0 :         spec_nos_31_value &lt;= realNos_value;</span></a>
+<a name="1319"><span class="lineNum">    1319 </span>            :       end</a>
+<a name="1320"><span class="lineNum">    1320 </span><span class="lineCov">         64 :       if (io_redirect_valid) begin</span></a>
+<a name="1321"><span class="lineNum">    1321 </span><span class="lineCov">         32 :         ssp &lt;=</span></a>
+<a name="1322"><span class="lineNum">    1322 </span><span class="lineCov">         32 :           ~io_redirect_isRet | (|io_redirect_meta_sctr)</span></a>
+<a name="1323"><span class="lineNum">    1323 </span><span class="lineCov">         32 :             ? (~io_redirect_isCall | _GEN_10</span></a>
+<a name="1324"><span class="lineNum">    1324 </span><span class="lineCov">         32 :                  ? io_redirect_meta_ssp</span></a>
+<a name="1325"><span class="lineNum">    1325 </span><span class="lineCov">         32 :                  : 4'(io_redirect_meta_ssp + 4'h1))</span></a>
+<a name="1326"><span class="lineNum">    1326 </span><span class="lineCov">         32 :             : inflightValid_8 ? 4'(io_redirect_meta_ssp - 4'h1) : _sctr_T_16;</span></a>
+<a name="1327"><span class="lineNum">    1327 </span><span class="lineCov">         32 :         sctr &lt;=</span></a>
+<a name="1328"><span class="lineNum">    1328 </span><span class="lineCov">         32 :           io_redirect_isRet</span></a>
+<a name="1329"><span class="lineNum">    1329 </span><span class="lineCov">         32 :             ? ((|io_redirect_meta_sctr)</span></a>
+<a name="1330"><span class="lineNum">    1330 </span><span class="lineCov">         32 :                  ? 3'(io_redirect_meta_sctr - 3'h1)</span></a>
+<a name="1331"><span class="lineNum">    1331 </span><span class="lineCov">         32 :                  : inflightValid_8</span></a>
+<a name="1332"><span class="lineNum">    1332 </span><span class="lineCov">         32 :                      ? _GEN_2[io_redirect_meta_NOS_value][2:0]</span></a>
+<a name="1333"><span class="lineNum">    1333 </span><span class="lineCov">         32 :                      : _GEN_5[_sctr_T_16][2:0])</span></a>
+<a name="1334"><span class="lineNum">    1334 </span><span class="lineCov">         32 :             : io_redirect_isCall ? (_GEN_10 ? _sctr_T_12 : 3'h0) : io_redirect_meta_sctr;</span></a>
+<a name="1335"><span class="lineNum">    1335 </span><span class="lineCov">         32 :         TOSR_flag &lt;=</span></a>
+<a name="1336"><span class="lineNum">    1336 </span><span class="lineCov">         32 :           _GEN_11</span></a>
+<a name="1337"><span class="lineNum">    1337 </span><span class="lineCov">         32 :             ? io_redirect_meta_NOS_flag</span></a>
+<a name="1338"><span class="lineNum">    1338 </span><span class="lineCov">         32 :             : io_redirect_isCall</span></a>
+<a name="1339"><span class="lineNum">    1339 </span><span class="lineCov">         32 :                 ? io_redirect_meta_TOSW_flag</span></a>
+<a name="1340"><span class="lineNum">    1340 </span><span class="lineCov">         32 :                 : io_redirect_meta_TOSR_flag;</span></a>
+<a name="1341"><span class="lineNum">    1341 </span><span class="lineCov">         32 :         TOSR_value &lt;=</span></a>
+<a name="1342"><span class="lineNum">    1342 </span><span class="lineCov">         32 :           _GEN_11</span></a>
+<a name="1343"><span class="lineNum">    1343 </span><span class="lineCov">         32 :             ? io_redirect_meta_NOS_value</span></a>
+<a name="1344"><span class="lineNum">    1344 </span><span class="lineCov">         32 :             : io_redirect_isCall</span></a>
+<a name="1345"><span class="lineNum">    1345 </span><span class="lineCov">         32 :                 ? io_redirect_meta_TOSW_value</span></a>
+<a name="1346"><span class="lineNum">    1346 </span><span class="lineCov">         32 :                 : io_redirect_meta_TOSR_value;</span></a>
+<a name="1347"><span class="lineNum">    1347 </span><span class="lineCov">         32 :         TOSW_flag &lt;= io_redirect_isCall ? _GEN_76[5] : io_redirect_meta_TOSW_flag;</span></a>
+<a name="1348"><span class="lineNum">    1348 </span><span class="lineCov">         32 :         TOSW_value &lt;= io_redirect_isCall ? _GEN_76[4:0] : io_redirect_meta_TOSW_value;</span></a>
+<a name="1349"><span class="lineNum">    1349 </span>            :       end</a>
+<a name="1350"><span class="lineNum">    1350 </span><span class="lineCov">          2 :       else if (io_s3_cancel) begin</span></a>
+<a name="1351"><span class="lineNum">    1351 </span><span class="lineCov">          1 :         ssp &lt;=</span></a>
+<a name="1352"><span class="lineNum">    1352 </span><span class="lineCov">          1 :           ~io_s3_missed_push | _GEN_79</span></a>
+<a name="1353"><span class="lineNum">    1353 </span><span class="lineCov">          1 :             ? (~io_s3_missed_pop | (|io_s3_meta_sctr)</span></a>
+<a name="1354"><span class="lineNum">    1354 </span><span class="lineCov">          1 :                  ? io_s3_meta_ssp</span></a>
+<a name="1355"><span class="lineNum">    1355 </span><span class="lineCov">          1 :                  : inflightValid_6 ? 4'(io_s3_meta_ssp - 4'h1) : _sctr_T_8)</span></a>
+<a name="1356"><span class="lineNum">    1356 </span><span class="lineCov">          1 :             : 4'(io_s3_meta_ssp + 4'h1);</span></a>
+<a name="1357"><span class="lineNum">    1357 </span><span class="lineCov">          1 :         sctr &lt;=</span></a>
+<a name="1358"><span class="lineNum">    1358 </span><span class="lineCov">          1 :           io_s3_missed_push</span></a>
+<a name="1359"><span class="lineNum">    1359 </span><span class="lineCov">          1 :             ? (_GEN_79 ? _sctr_T_10 : 3'h0)</span></a>
+<a name="1360"><span class="lineNum">    1360 </span><span class="lineCov">          1 :             : io_s3_missed_pop</span></a>
+<a name="1361"><span class="lineNum">    1361 </span><span class="lineCov">          1 :                 ? ((|io_s3_meta_sctr)</span></a>
+<a name="1362"><span class="lineNum">    1362 </span><span class="lineCov">          1 :                      ? 3'(io_s3_meta_sctr - 3'h1)</span></a>
+<a name="1363"><span class="lineNum">    1363 </span><span class="lineCov">          1 :                      : inflightValid_6</span></a>
+<a name="1364"><span class="lineNum">    1364 </span><span class="lineCov">          1 :                          ? _GEN_2[io_s3_meta_NOS_value][2:0]</span></a>
+<a name="1365"><span class="lineNum">    1365 </span><span class="lineCov">          1 :                          : _GEN_5[_sctr_T_8][2:0])</span></a>
+<a name="1366"><span class="lineNum">    1366 </span><span class="lineCov">          1 :                 : io_s3_meta_sctr;</span></a>
+<a name="1367"><span class="lineNum">    1367 </span><span class="lineCov">          1 :         TOSR_flag &lt;=</span></a>
+<a name="1368"><span class="lineNum">    1368 </span><span class="lineCov">          1 :           io_s3_missed_push</span></a>
+<a name="1369"><span class="lineNum">    1369 </span><span class="lineCov">          1 :             ? io_s3_meta_TOSW_flag</span></a>
+<a name="1370"><span class="lineNum">    1370 </span><span class="lineCov">          1 :             : _GEN_77 ? io_s3_meta_NOS_flag : io_s3_meta_TOSR_flag;</span></a>
+<a name="1371"><span class="lineNum">    1371 </span><span class="lineCov">          1 :         TOSR_value &lt;=</span></a>
+<a name="1372"><span class="lineNum">    1372 </span><span class="lineCov">          1 :           io_s3_missed_push</span></a>
+<a name="1373"><span class="lineNum">    1373 </span><span class="lineCov">          1 :             ? io_s3_meta_TOSW_value</span></a>
+<a name="1374"><span class="lineNum">    1374 </span><span class="lineCov">          1 :             : _GEN_77 ? io_s3_meta_NOS_value : io_s3_meta_TOSR_value;</span></a>
+<a name="1375"><span class="lineNum">    1375 </span><span class="lineCov">          1 :         TOSW_flag &lt;= io_s3_missed_push ? _GEN_78[5] : io_s3_meta_TOSW_flag;</span></a>
+<a name="1376"><span class="lineNum">    1376 </span><span class="lineCov">          1 :         TOSW_value &lt;= io_s3_missed_push ? _GEN_78[4:0] : io_s3_meta_TOSW_value;</span></a>
+<a name="1377"><span class="lineNum">    1377 </span>            :       end</a>
+<a name="1378"><span class="lineNum">    1378 </span><span class="lineCov">      63696 :       else begin</span></a>
+<a name="1379"><span class="lineNum">    1379 </span><span class="lineCov">     127392 :         if (~io_spec_pop_valid | (|sctr)) begin</span></a>
+<a name="1380"><span class="lineNum">    1380 </span><span class="lineNoCov">          0 :           if (~io_spec_push_valid | _GEN_12) begin</span></a>
+<a name="1381"><span class="lineNum">    1381 </span>            :           end</a>
+<a name="1382"><span class="lineNum">    1382 </span>            :           else</a>
+<a name="1383"><span class="lineNum">    1383 </span><span class="lineNoCov">          0 :             ssp &lt;= 4'(ssp + 4'h1);</span></a>
+<a name="1384"><span class="lineNum">    1384 </span>            :         end</a>
+<a name="1385"><span class="lineNum">    1385 </span><span class="lineNoCov">          0 :         else if (inflightValid_4)</span></a>
+<a name="1386"><span class="lineNum">    1386 </span><span class="lineNoCov">          0 :           ssp &lt;= 4'(ssp - 4'h1);</span></a>
+<a name="1387"><span class="lineNum">    1387 </span>            :         else</a>
+<a name="1388"><span class="lineNum">    1388 </span><span class="lineNoCov">          0 :           ssp &lt;= _sctr_T_4;</span></a>
+<a name="1389"><span class="lineNum">    1389 </span><span class="lineNoCov">          0 :         if (io_spec_pop_valid) begin</span></a>
+<a name="1390"><span class="lineNum">    1390 </span><span class="lineNoCov">          0 :           if (|sctr)</span></a>
+<a name="1391"><span class="lineNum">    1391 </span><span class="lineNoCov">          0 :             sctr &lt;= 3'(sctr - 3'h1);</span></a>
+<a name="1392"><span class="lineNum">    1392 </span>            :           else</a>
+<a name="1393"><span class="lineNum">    1393 </span><span class="lineNoCov">          0 :             sctr &lt;= inflightValid_4 ? _GEN_2[topNos_value][2:0] : _GEN_5[_sctr_T_4][2:0];</span></a>
+<a name="1394"><span class="lineNum">    1394 </span>            :         end</a>
+<a name="1395"><span class="lineNum">    1395 </span><span class="lineNoCov">          0 :         else if (io_spec_push_valid) begin</span></a>
+<a name="1396"><span class="lineNum">    1396 </span><span class="lineNoCov">          0 :           if (_GEN_12)</span></a>
+<a name="1397"><span class="lineNum">    1397 </span><span class="lineNoCov">          0 :             sctr &lt;= _sctr_T;</span></a>
+<a name="1398"><span class="lineNum">    1398 </span>            :           else</a>
+<a name="1399"><span class="lineNum">    1399 </span><span class="lineNoCov">          0 :             sctr &lt;= 3'h0;</span></a>
+<a name="1400"><span class="lineNum">    1400 </span>            :         end</a>
+<a name="1401"><span class="lineNum">    1401 </span><span class="lineNoCov">          0 :         if (io_spec_pop_valid &amp; (TOSR_flag ^ BOS_flag ^ _GEN)</span></a>
+<a name="1402"><span class="lineNum">    1402 </span><span class="lineNoCov">          0 :             &amp; (TOSR_flag ^ TOSW_flag ^ TOSR_value &lt; TOSW_value)) begin</span></a>
+<a name="1403"><span class="lineNum">    1403 </span><span class="lineNoCov">          0 :           TOSR_flag &lt;= topNos_flag;</span></a>
+<a name="1404"><span class="lineNum">    1404 </span><span class="lineNoCov">          0 :           if (writeBypassValid)</span></a>
+<a name="1405"><span class="lineNum">    1405 </span><span class="lineNoCov">          0 :             TOSR_value &lt;= writeBypassNos_value;</span></a>
+<a name="1406"><span class="lineNum">    1406 </span>            :           else</a>
+<a name="1407"><span class="lineNum">    1407 </span><span class="lineNoCov">          0 :             TOSR_value &lt;= _GEN_8;</span></a>
+<a name="1408"><span class="lineNum">    1408 </span>            :         end</a>
+<a name="1409"><span class="lineNum">    1409 </span><span class="lineNoCov">          0 :         else if (io_spec_push_valid) begin</span></a>
+<a name="1410"><span class="lineNum">    1410 </span><span class="lineNoCov">          0 :           TOSR_flag &lt;= TOSW_flag;</span></a>
+<a name="1411"><span class="lineNum">    1411 </span><span class="lineNoCov">          0 :           TOSR_value &lt;= TOSW_value;</span></a>
+<a name="1412"><span class="lineNum">    1412 </span>            :         end</a>
+<a name="1413"><span class="lineNum">    1413 </span><span class="lineNoCov">          0 :         if (io_spec_push_valid) begin</span></a>
+<a name="1414"><span class="lineNum">    1414 </span><span class="lineNoCov">          0 :           TOSW_flag &lt;= _GEN_80[5];</span></a>
+<a name="1415"><span class="lineNum">    1415 </span><span class="lineNoCov">          0 :           TOSW_value &lt;= _GEN_80[4:0];</span></a>
+<a name="1416"><span class="lineNum">    1416 </span>            :         end</a>
+<a name="1417"><span class="lineNum">    1417 </span>            :       end</a>
+<a name="1418"><span class="lineNum">    1418 </span><span class="lineNoCov">          0 :       if (_GEN_75) begin</span></a>
+<a name="1419"><span class="lineNum">    1419 </span><span class="lineNoCov">          0 :         BOS_flag &lt;= _BOS_new_ptr_T_16[5];</span></a>
+<a name="1420"><span class="lineNum">    1420 </span><span class="lineNoCov">          0 :         BOS_value &lt;= _BOS_new_ptr_T_16[4:0];</span></a>
+<a name="1421"><span class="lineNum">    1421 </span>            :       end</a>
+<a name="1422"><span class="lineNum">    1422 </span><span class="lineCov">         14 :       else if (_GEN_73) begin</span></a>
+<a name="1423"><span class="lineNum">    1423 </span><span class="lineCov">          7 :         BOS_flag &lt;= _BOS_new_ptr_T_11[5];</span></a>
+<a name="1424"><span class="lineNum">    1424 </span><span class="lineCov">          7 :         BOS_value &lt;= _BOS_new_ptr_T_11[4:0];</span></a>
+<a name="1425"><span class="lineNum">    1425 </span>            :       end</a>
+<a name="1426"><span class="lineNum">    1426 </span><span class="lineNoCov">          0 :       else if (io_s3_cancel &amp; io_s3_missed_push &amp; _GEN_23) begin</span></a>
+<a name="1427"><span class="lineNum">    1427 </span><span class="lineNoCov">          0 :         BOS_flag &lt;= _BOS_new_ptr_T_6[5];</span></a>
+<a name="1428"><span class="lineNum">    1428 </span><span class="lineNoCov">          0 :         BOS_value &lt;= _BOS_new_ptr_T_6[4:0];</span></a>
+<a name="1429"><span class="lineNum">    1429 </span>            :       end</a>
+<a name="1430"><span class="lineNum">    1430 </span><span class="lineNoCov">          0 :       else if (_GEN_21) begin</span></a>
+<a name="1431"><span class="lineNum">    1431 </span><span class="lineNoCov">          0 :         BOS_flag &lt;= _BOS_new_ptr_T_1[5];</span></a>
+<a name="1432"><span class="lineNum">    1432 </span><span class="lineNoCov">          0 :         BOS_value &lt;= _BOS_new_ptr_T_1[4:0];</span></a>
+<a name="1433"><span class="lineNum">    1433 </span>            :       end</a>
+<a name="1434"><span class="lineNum">    1434 </span><span class="lineCov">      63729 :       spec_overflowed &lt;=</span></a>
+<a name="1435"><span class="lineNum">    1435 </span><span class="lineCov">      63729 :         _GEN_75 | ~_GEN_73</span></a>
+<a name="1436"><span class="lineNum">    1436 </span><span class="lineCov">      63729 :         &amp; (io_s3_cancel &amp; io_s3_missed_push</span></a>
+<a name="1437"><span class="lineNum">    1437 </span><span class="lineCov">      63729 :              ? _GEN_23 | _GEN_21 | spec_overflowed</span></a>
+<a name="1438"><span class="lineNum">    1438 </span><span class="lineCov">      63729 :              : _GEN_21 | spec_overflowed);</span></a>
+<a name="1439"><span class="lineNum">    1439 </span><span class="lineCov">      63729 :       writeBypassValid &lt;= writeBypassValidWire;</span></a>
+<a name="1440"><span class="lineNum">    1440 </span><span class="lineCov">      63729 :       timingTop_retAddr &lt;=</span></a>
+<a name="1441"><span class="lineNum">    1441 </span><span class="lineCov">      63729 :         writeBypassValidWire</span></a>
+<a name="1442"><span class="lineNum">    1442 </span><span class="lineCov">      63729 :           ? (_realPush_T_4 | io_spec_push_valid</span></a>
+<a name="1443"><span class="lineNum">    1443 </span><span class="lineCov">      63729 :                ? writeEntry_retAddr</span></a>
+<a name="1444"><span class="lineNum">    1444 </span><span class="lineCov">      63729 :                : writeBypassEntry_retAddr)</span></a>
+<a name="1445"><span class="lineNum">    1445 </span><span class="lineCov">      63729 :           : io_redirect_valid &amp; io_redirect_isRet</span></a>
+<a name="1446"><span class="lineNum">    1446 </span><span class="lineCov">      63729 :               ? ((io_redirect_meta_NOS_flag ^ BOS_flag ^ _GEN_13)</span></a>
+<a name="1447"><span class="lineNum">    1447 </span><span class="lineCov">      63729 :                  &amp; (io_redirect_meta_NOS_flag ^ io_redirect_meta_TOSW_flag</span></a>
+<a name="1448"><span class="lineNum">    1448 </span><span class="lineCov">      63729 :                     ^ io_redirect_meta_NOS_value &lt; io_redirect_meta_TOSW_value)</span></a>
+<a name="1449"><span class="lineNum">    1449 </span><span class="lineCov">      63729 :                    ? _GEN_0[io_redirect_meta_NOS_value]</span></a>
+<a name="1450"><span class="lineNum">    1450 </span><span class="lineCov">      63729 :                    : _GEN_3[(|io_redirect_meta_sctr)</span></a>
+<a name="1451"><span class="lineNum">    1451 </span><span class="lineCov">      63729 :                               ? io_redirect_meta_ssp</span></a>
+<a name="1452"><span class="lineNum">    1452 </span><span class="lineCov">      63729 :                               : _GEN_14</span></a>
+<a name="1453"><span class="lineNum">    1453 </span><span class="lineCov">      63729 :                                 &amp; (io_redirect_meta_NOS_flag ^ TOSW_flag</span></a>
+<a name="1454"><span class="lineNum">    1454 </span><span class="lineCov">      63729 :                                    ^ io_redirect_meta_NOS_value &lt; TOSW_value)</span></a>
+<a name="1455"><span class="lineNum">    1455 </span><span class="lineCov">      63729 :                                   ? 4'(io_redirect_meta_ssp - 4'h1)</span></a>
+<a name="1456"><span class="lineNum">    1456 </span><span class="lineCov">      63729 :                                   : 4'(io_redirect_meta_ssp - 4'h1)])</span></a>
+<a name="1457"><span class="lineNum">    1457 </span><span class="lineCov">      63729 :               : io_redirect_valid</span></a>
+<a name="1458"><span class="lineNum">    1458 </span><span class="lineCov">      63729 :                   ? ((differentFlag_15 ^ ~compare_15) &amp; (differentFlag_16 ^ compare_16)</span></a>
+<a name="1459"><span class="lineNum">    1459 </span><span class="lineCov">      63729 :                        ? _GEN_0[io_redirect_meta_TOSR_value]</span></a>
+<a name="1460"><span class="lineNum">    1460 </span><span class="lineCov">      63729 :                        : _GEN_3[io_redirect_meta_ssp])</span></a>
+<a name="1461"><span class="lineNum">    1461 </span><span class="lineCov">      63729 :                   : io_spec_pop_valid</span></a>
+<a name="1462"><span class="lineNum">    1462 </span><span class="lineCov">      63729 :                       ? ((topNos_flag ^ BOS_flag ^ _GEN_15)</span></a>
+<a name="1463"><span class="lineNum">    1463 </span><span class="lineCov">      63729 :                          &amp; (topNos_flag ^ TOSW_flag ^ topNos_value &lt; TOSW_value)</span></a>
+<a name="1464"><span class="lineNum">    1464 </span><span class="lineCov">      63729 :                            ? _GEN_0[topNos_value]</span></a>
+<a name="1465"><span class="lineNum">    1465 </span><span class="lineCov">      63729 :                            : _GEN_3[(|sctr)</span></a>
+<a name="1466"><span class="lineNum">    1466 </span><span class="lineCov">      63729 :                                       ? ssp</span></a>
+<a name="1467"><span class="lineNum">    1467 </span><span class="lineCov">      63729 :                                       : _GEN_16</span></a>
+<a name="1468"><span class="lineNum">    1468 </span><span class="lineCov">      63729 :                                         &amp; (topNos_flag ^ TOSW_flag</span></a>
+<a name="1469"><span class="lineNum">    1469 </span><span class="lineCov">      63729 :                                            ^ topNos_value &lt; TOSW_value)</span></a>
+<a name="1470"><span class="lineNum">    1470 </span><span class="lineCov">      63729 :                                           ? 4'(ssp - 4'h1)</span></a>
+<a name="1471"><span class="lineNum">    1471 </span><span class="lineCov">      63729 :                                           : 4'(ssp - 4'h1)])</span></a>
+<a name="1472"><span class="lineNum">    1472 </span><span class="lineCov">      63729 :                       : realPush</span></a>
+<a name="1473"><span class="lineNum">    1473 </span><span class="lineCov">      63729 :                           ? realWriteEntry_retAddr</span></a>
+<a name="1474"><span class="lineNum">    1474 </span><span class="lineCov">      63729 :                           : io_s3_cancel</span></a>
+<a name="1475"><span class="lineNum">    1475 </span><span class="lineCov">      63729 :                               ? (io_s3_missed_push</span></a>
+<a name="1476"><span class="lineNum">    1476 </span><span class="lineCov">      63729 :                                    ? io_s3_pushAddr</span></a>
+<a name="1477"><span class="lineNum">    1477 </span><span class="lineCov">      63729 :                                    : io_s3_missed_pop</span></a>
+<a name="1478"><span class="lineNum">    1478 </span><span class="lineCov">      63729 :                                        ? ((io_s3_meta_NOS_flag ^ BOS_flag ^ _GEN_17)</span></a>
+<a name="1479"><span class="lineNum">    1479 </span><span class="lineCov">      63729 :                                           &amp; (io_s3_meta_NOS_flag ^ io_s3_meta_TOSW_flag</span></a>
+<a name="1480"><span class="lineNum">    1480 </span><span class="lineCov">      63729 :                                              ^ io_s3_meta_NOS_value &lt; io_s3_meta_TOSW_value)</span></a>
+<a name="1481"><span class="lineNum">    1481 </span><span class="lineCov">      63729 :                                             ? _GEN_0[io_s3_meta_NOS_value]</span></a>
+<a name="1482"><span class="lineNum">    1482 </span><span class="lineCov">      63729 :                                             : _GEN_3[(|io_s3_meta_sctr)</span></a>
+<a name="1483"><span class="lineNum">    1483 </span><span class="lineCov">      63729 :                                                        ? io_s3_meta_ssp</span></a>
+<a name="1484"><span class="lineNum">    1484 </span><span class="lineCov">      63729 :                                                        : _GEN_18</span></a>
+<a name="1485"><span class="lineNum">    1485 </span><span class="lineCov">      63729 :                                                          &amp; (io_s3_meta_NOS_flag</span></a>
+<a name="1486"><span class="lineNum">    1486 </span><span class="lineCov">      63729 :                                                             ^ io_s3_meta_TOSW_flag</span></a>
+<a name="1487"><span class="lineNum">    1487 </span><span class="lineCov">      63729 :                                                             ^ io_s3_meta_NOS_value &lt; io_s3_meta_TOSW_value)</span></a>
+<a name="1488"><span class="lineNum">    1488 </span><span class="lineCov">      63729 :                                                            ? 4'(io_s3_meta_ssp - 4'h1)</span></a>
+<a name="1489"><span class="lineNum">    1489 </span><span class="lineCov">      63729 :                                                            : 4'(io_s3_meta_ssp - 4'h1)])</span></a>
+<a name="1490"><span class="lineNum">    1490 </span><span class="lineCov">      63729 :                                        : (differentFlag_10 ^ ~compare_10)</span></a>
+<a name="1491"><span class="lineNum">    1491 </span><span class="lineCov">      63729 :                                          &amp; (differentFlag_11 ^ compare_11)</span></a>
+<a name="1492"><span class="lineNum">    1492 </span><span class="lineCov">      63729 :                                            ? _GEN_0[io_s3_meta_TOSR_value]</span></a>
+<a name="1493"><span class="lineNum">    1493 </span><span class="lineCov">      63729 :                                            : _GEN_3[io_s3_meta_ssp])</span></a>
+<a name="1494"><span class="lineNum">    1494 </span><span class="lineCov">      63729 :                               : (TOSR_flag ^ BOS_flag ^ _GEN)</span></a>
+<a name="1495"><span class="lineNum">    1495 </span><span class="lineCov">      63729 :                                 &amp; (TOSR_flag ^ TOSW_flag ^ TOSR_value &lt; TOSW_value)</span></a>
+<a name="1496"><span class="lineNum">    1496 </span><span class="lineCov">      63729 :                                   ? _GEN_1</span></a>
+<a name="1497"><span class="lineNum">    1497 </span><span class="lineCov">      63729 :                                   : _GEN_4;</span></a>
+<a name="1498"><span class="lineNum">    1498 </span>            :     end</a>
+<a name="1499"><span class="lineNum">    1499 </span>            :   end // always @(posedge, posedge)</a>
+<a name="1500"><span class="lineNum">    1500 </span><span class="lineCov">        115 :   wire [7:0]        writeEntry_ctr =</span></a>
+<a name="1501"><span class="lineNum">    1501 </span>            :     {5'h0,</a>
+<a name="1502"><span class="lineNum">    1502 </span>            :      _realPush_T_4</a>
+<a name="1503"><span class="lineNum">    1503 </span>            :        ? (_writeEntry_ctr_T_1</a>
+<a name="1504"><span class="lineNum">    1504 </span>            :           &amp; (redirectTopEntry_inflightValid</a>
+<a name="1505"><span class="lineNum">    1505 </span>            :                ? _GEN_2[io_redirect_meta_TOSR_value]</a>
+<a name="1506"><span class="lineNum">    1506 </span>            :                : _GEN_5[io_redirect_meta_ssp]) &lt; 8'h7</a>
+<a name="1507"><span class="lineNum">    1507 </span>            :             ? _sctr_T_12</a>
+<a name="1508"><span class="lineNum">    1508 </span>            :             : 3'h0)</a>
+<a name="1509"><span class="lineNum">    1509 </span>            :        : _writeEntry_ctr_T_7</a>
+<a name="1510"><span class="lineNum">    1510 </span>            :          &amp; (writeBypassValid</a>
+<a name="1511"><span class="lineNum">    1511 </span>            :               ? writeBypassEntry_ctr</a>
+<a name="1512"><span class="lineNum">    1512 </span>            :               : topEntry_inflightValid ? _GEN_2[TOSR_value] : _GEN_5[ssp]) &lt; 8'h7</a>
+<a name="1513"><span class="lineNum">    1513 </span>            :            ? _sctr_T</a>
+<a name="1514"><span class="lineNum">    1514 </span>            :            : 3'h0};</a>
+<a name="1515"><span class="lineNum">    1515 </span><span class="lineCov">     127694 :   always @(posedge clock) begin</span></a>
+<a name="1516"><span class="lineNum">    1516 </span><span class="lineCov">          4 :     if (io_spec_push_valid | _realPush_T_4) begin</span></a>
+<a name="1517"><span class="lineNum">    1517 </span><span class="lineCov">          2 :       writeBypassEntry_retAddr &lt;= writeEntry_retAddr;</span></a>
+<a name="1518"><span class="lineNum">    1518 </span><span class="lineCov">          2 :       writeBypassEntry_ctr &lt;= writeEntry_ctr;</span></a>
+<a name="1519"><span class="lineNum">    1519 </span><span class="lineCov">          2 :       writeBypassNos_flag &lt;= _realPush_T_4 ? io_redirect_meta_NOS_flag : TOSR_flag;</span></a>
+<a name="1520"><span class="lineNum">    1520 </span><span class="lineCov">          2 :       writeBypassNos_value &lt;= _realPush_T_4 ? io_redirect_meta_NOS_value : TOSR_value;</span></a>
+<a name="1521"><span class="lineNum">    1521 </span>            :     end</a>
+<a name="1522"><span class="lineNum">    1522 </span><span class="lineCov">       8152 :     if (io_s2_fire | io_redirect_isCall) begin</span></a>
+<a name="1523"><span class="lineNum">    1523 </span><span class="lineCov">       4076 :       realWriteEntry_next_retAddr &lt;= writeEntry_retAddr;</span></a>
+<a name="1524"><span class="lineNum">    1524 </span><span class="lineCov">       4076 :       realWriteEntry_next_ctr &lt;= writeEntry_ctr;</span></a>
+<a name="1525"><span class="lineNum">    1525 </span>            :     end</a>
+<a name="1526"><span class="lineNum">    1526 </span><span class="lineCov">       8152 :     if (io_s2_fire | _realPush_T_4)</span></a>
+<a name="1527"><span class="lineNum">    1527 </span><span class="lineCov">       4076 :       realWriteAddr_next_value &lt;=</span></a>
+<a name="1528"><span class="lineNum">    1528 </span><span class="lineCov">       4076 :         _realPush_T_4 ? io_redirect_meta_TOSW_value : TOSW_value;</span></a>
+<a name="1529"><span class="lineNum">    1529 </span><span class="lineCov">       8152 :     if (io_s2_fire | _realPush_T_4) begin</span></a>
+<a name="1530"><span class="lineNum">    1530 </span><span class="lineCov">       4076 :       realNos_next_flag &lt;= _realPush_T_4 ? io_redirect_meta_TOSR_flag : TOSR_flag;</span></a>
+<a name="1531"><span class="lineNum">    1531 </span><span class="lineCov">       4076 :       realNos_next_value &lt;= _realPush_T_4 ? io_redirect_meta_TOSR_value : TOSR_value;</span></a>
+<a name="1532"><span class="lineNum">    1532 </span>            :     end</a>
+<a name="1533"><span class="lineNum">    1533 </span><span class="lineCov">       8150 :     if (io_s2_fire)</span></a>
+<a name="1534"><span class="lineNum">    1534 </span><span class="lineCov">       4075 :       realPush_r &lt;= io_spec_push_valid;</span></a>
+<a name="1535"><span class="lineNum">    1535 </span><span class="lineCov">      63847 :     realPush_REG &lt;= _realPush_T_4;</span></a>
+<a name="1536"><span class="lineNum">    1536 </span>            :   end // always @(posedge)</a>
+<a name="1537"><span class="lineNum">    1537 </span>            :   `ifdef ENABLE_INITIAL_REG_</a>
+<a name="1538"><span class="lineNum">    1538 </span>            :     `ifdef FIRRTL_BEFORE_INITIAL</a>
+<a name="1539"><span class="lineNum">    1539 </span>            :       `FIRRTL_BEFORE_INITIAL</a>
+<a name="1540"><span class="lineNum">    1540 </span>            :     `endif // FIRRTL_BEFORE_INITIAL</a>
+<a name="1541"><span class="lineNum">    1541 </span>            :     logic [31:0] _RANDOM[0:85];</a>
+<a name="1542"><span class="lineNum">    1542 </span><span class="lineCov">         58 :     initial begin</span></a>
+<a name="1543"><span class="lineNum">    1543 </span>            :       `ifdef INIT_RANDOM_PROLOG_</a>
+<a name="1544"><span class="lineNum">    1544 </span>            :         `INIT_RANDOM_PROLOG_</a>
+<a name="1545"><span class="lineNum">    1545 </span>            :       `endif // INIT_RANDOM_PROLOG_</a>
+<a name="1546"><span class="lineNum">    1546 </span>            :       `ifdef RANDOMIZE_REG_INIT</a>
+<a name="1547"><span class="lineNum">    1547 </span>            :         for (logic [6:0] i = 7'h0; i &lt; 7'h56; i += 7'h1) begin</a>
+<a name="1548"><span class="lineNum">    1548 </span>            :           _RANDOM[i] = `RANDOM;</a>
+<a name="1549"><span class="lineNum">    1549 </span>            :         end</a>
+<a name="1550"><span class="lineNum">    1550 </span>            :         commit_stack_0_retAddr = {_RANDOM[7'h0], _RANDOM[7'h1][8:0]};</a>
+<a name="1551"><span class="lineNum">    1551 </span>            :         commit_stack_0_ctr = _RANDOM[7'h1][16:9];</a>
+<a name="1552"><span class="lineNum">    1552 </span>            :         commit_stack_1_retAddr = {_RANDOM[7'h1][31:17], _RANDOM[7'h2][25:0]};</a>
+<a name="1553"><span class="lineNum">    1553 </span>            :         commit_stack_1_ctr = {_RANDOM[7'h2][31:26], _RANDOM[7'h3][1:0]};</a>
+<a name="1554"><span class="lineNum">    1554 </span>            :         commit_stack_2_retAddr = {_RANDOM[7'h3][31:2], _RANDOM[7'h4][10:0]};</a>
+<a name="1555"><span class="lineNum">    1555 </span>            :         commit_stack_2_ctr = _RANDOM[7'h4][18:11];</a>
+<a name="1556"><span class="lineNum">    1556 </span>            :         commit_stack_3_retAddr = {_RANDOM[7'h4][31:19], _RANDOM[7'h5][27:0]};</a>
+<a name="1557"><span class="lineNum">    1557 </span>            :         commit_stack_3_ctr = {_RANDOM[7'h5][31:28], _RANDOM[7'h6][3:0]};</a>
+<a name="1558"><span class="lineNum">    1558 </span>            :         commit_stack_4_retAddr = {_RANDOM[7'h6][31:4], _RANDOM[7'h7][12:0]};</a>
+<a name="1559"><span class="lineNum">    1559 </span>            :         commit_stack_4_ctr = _RANDOM[7'h7][20:13];</a>
+<a name="1560"><span class="lineNum">    1560 </span>            :         commit_stack_5_retAddr = {_RANDOM[7'h7][31:21], _RANDOM[7'h8][29:0]};</a>
+<a name="1561"><span class="lineNum">    1561 </span>            :         commit_stack_5_ctr = {_RANDOM[7'h8][31:30], _RANDOM[7'h9][5:0]};</a>
+<a name="1562"><span class="lineNum">    1562 </span>            :         commit_stack_6_retAddr = {_RANDOM[7'h9][31:6], _RANDOM[7'hA][14:0]};</a>
+<a name="1563"><span class="lineNum">    1563 </span>            :         commit_stack_6_ctr = _RANDOM[7'hA][22:15];</a>
+<a name="1564"><span class="lineNum">    1564 </span>            :         commit_stack_7_retAddr = {_RANDOM[7'hA][31:23], _RANDOM[7'hB]};</a>
+<a name="1565"><span class="lineNum">    1565 </span>            :         commit_stack_7_ctr = _RANDOM[7'hC][7:0];</a>
+<a name="1566"><span class="lineNum">    1566 </span>            :         commit_stack_8_retAddr = {_RANDOM[7'hC][31:8], _RANDOM[7'hD][16:0]};</a>
+<a name="1567"><span class="lineNum">    1567 </span>            :         commit_stack_8_ctr = _RANDOM[7'hD][24:17];</a>
+<a name="1568"><span class="lineNum">    1568 </span>            :         commit_stack_9_retAddr =</a>
+<a name="1569"><span class="lineNum">    1569 </span>            :           {_RANDOM[7'hD][31:25], _RANDOM[7'hE], _RANDOM[7'hF][1:0]};</a>
+<a name="1570"><span class="lineNum">    1570 </span>            :         commit_stack_9_ctr = _RANDOM[7'hF][9:2];</a>
+<a name="1571"><span class="lineNum">    1571 </span>            :         commit_stack_10_retAddr = {_RANDOM[7'hF][31:10], _RANDOM[7'h10][18:0]};</a>
+<a name="1572"><span class="lineNum">    1572 </span>            :         commit_stack_10_ctr = _RANDOM[7'h10][26:19];</a>
+<a name="1573"><span class="lineNum">    1573 </span>            :         commit_stack_11_retAddr =</a>
+<a name="1574"><span class="lineNum">    1574 </span>            :           {_RANDOM[7'h10][31:27], _RANDOM[7'h11], _RANDOM[7'h12][3:0]};</a>
+<a name="1575"><span class="lineNum">    1575 </span>            :         commit_stack_11_ctr = _RANDOM[7'h12][11:4];</a>
+<a name="1576"><span class="lineNum">    1576 </span>            :         commit_stack_12_retAddr = {_RANDOM[7'h12][31:12], _RANDOM[7'h13][20:0]};</a>
+<a name="1577"><span class="lineNum">    1577 </span>            :         commit_stack_12_ctr = _RANDOM[7'h13][28:21];</a>
+<a name="1578"><span class="lineNum">    1578 </span>            :         commit_stack_13_retAddr =</a>
+<a name="1579"><span class="lineNum">    1579 </span>            :           {_RANDOM[7'h13][31:29], _RANDOM[7'h14], _RANDOM[7'h15][5:0]};</a>
+<a name="1580"><span class="lineNum">    1580 </span>            :         commit_stack_13_ctr = _RANDOM[7'h15][13:6];</a>
+<a name="1581"><span class="lineNum">    1581 </span>            :         commit_stack_14_retAddr = {_RANDOM[7'h15][31:14], _RANDOM[7'h16][22:0]};</a>
+<a name="1582"><span class="lineNum">    1582 </span>            :         commit_stack_14_ctr = _RANDOM[7'h16][30:23];</a>
+<a name="1583"><span class="lineNum">    1583 </span>            :         commit_stack_15_retAddr =</a>
+<a name="1584"><span class="lineNum">    1584 </span>            :           {_RANDOM[7'h16][31], _RANDOM[7'h17], _RANDOM[7'h18][7:0]};</a>
+<a name="1585"><span class="lineNum">    1585 </span>            :         commit_stack_15_ctr = _RANDOM[7'h18][15:8];</a>
+<a name="1586"><span class="lineNum">    1586 </span>            :         spec_queue_0_retAddr = {_RANDOM[7'h18][31:16], _RANDOM[7'h19][24:0]};</a>
+<a name="1587"><span class="lineNum">    1587 </span>            :         spec_queue_0_ctr = {_RANDOM[7'h19][31:25], _RANDOM[7'h1A][0]};</a>
+<a name="1588"><span class="lineNum">    1588 </span>            :         spec_queue_1_retAddr = {_RANDOM[7'h1A][31:1], _RANDOM[7'h1B][9:0]};</a>
+<a name="1589"><span class="lineNum">    1589 </span>            :         spec_queue_1_ctr = _RANDOM[7'h1B][17:10];</a>
+<a name="1590"><span class="lineNum">    1590 </span>            :         spec_queue_2_retAddr = {_RANDOM[7'h1B][31:18], _RANDOM[7'h1C][26:0]};</a>
+<a name="1591"><span class="lineNum">    1591 </span>            :         spec_queue_2_ctr = {_RANDOM[7'h1C][31:27], _RANDOM[7'h1D][2:0]};</a>
+<a name="1592"><span class="lineNum">    1592 </span>            :         spec_queue_3_retAddr = {_RANDOM[7'h1D][31:3], _RANDOM[7'h1E][11:0]};</a>
+<a name="1593"><span class="lineNum">    1593 </span>            :         spec_queue_3_ctr = _RANDOM[7'h1E][19:12];</a>
+<a name="1594"><span class="lineNum">    1594 </span>            :         spec_queue_4_retAddr = {_RANDOM[7'h1E][31:20], _RANDOM[7'h1F][28:0]};</a>
+<a name="1595"><span class="lineNum">    1595 </span>            :         spec_queue_4_ctr = {_RANDOM[7'h1F][31:29], _RANDOM[7'h20][4:0]};</a>
+<a name="1596"><span class="lineNum">    1596 </span>            :         spec_queue_5_retAddr = {_RANDOM[7'h20][31:5], _RANDOM[7'h21][13:0]};</a>
+<a name="1597"><span class="lineNum">    1597 </span>            :         spec_queue_5_ctr = _RANDOM[7'h21][21:14];</a>
+<a name="1598"><span class="lineNum">    1598 </span>            :         spec_queue_6_retAddr = {_RANDOM[7'h21][31:22], _RANDOM[7'h22][30:0]};</a>
+<a name="1599"><span class="lineNum">    1599 </span>            :         spec_queue_6_ctr = {_RANDOM[7'h22][31], _RANDOM[7'h23][6:0]};</a>
+<a name="1600"><span class="lineNum">    1600 </span>            :         spec_queue_7_retAddr = {_RANDOM[7'h23][31:7], _RANDOM[7'h24][15:0]};</a>
+<a name="1601"><span class="lineNum">    1601 </span>            :         spec_queue_7_ctr = _RANDOM[7'h24][23:16];</a>
+<a name="1602"><span class="lineNum">    1602 </span>            :         spec_queue_8_retAddr = {_RANDOM[7'h24][31:24], _RANDOM[7'h25], _RANDOM[7'h26][0]};</a>
+<a name="1603"><span class="lineNum">    1603 </span>            :         spec_queue_8_ctr = _RANDOM[7'h26][8:1];</a>
+<a name="1604"><span class="lineNum">    1604 </span>            :         spec_queue_9_retAddr = {_RANDOM[7'h26][31:9], _RANDOM[7'h27][17:0]};</a>
+<a name="1605"><span class="lineNum">    1605 </span>            :         spec_queue_9_ctr = _RANDOM[7'h27][25:18];</a>
+<a name="1606"><span class="lineNum">    1606 </span>            :         spec_queue_10_retAddr =</a>
+<a name="1607"><span class="lineNum">    1607 </span>            :           {_RANDOM[7'h27][31:26], _RANDOM[7'h28], _RANDOM[7'h29][2:0]};</a>
+<a name="1608"><span class="lineNum">    1608 </span>            :         spec_queue_10_ctr = _RANDOM[7'h29][10:3];</a>
+<a name="1609"><span class="lineNum">    1609 </span>            :         spec_queue_11_retAddr = {_RANDOM[7'h29][31:11], _RANDOM[7'h2A][19:0]};</a>
+<a name="1610"><span class="lineNum">    1610 </span>            :         spec_queue_11_ctr = _RANDOM[7'h2A][27:20];</a>
+<a name="1611"><span class="lineNum">    1611 </span>            :         spec_queue_12_retAddr =</a>
+<a name="1612"><span class="lineNum">    1612 </span>            :           {_RANDOM[7'h2A][31:28], _RANDOM[7'h2B], _RANDOM[7'h2C][4:0]};</a>
+<a name="1613"><span class="lineNum">    1613 </span>            :         spec_queue_12_ctr = _RANDOM[7'h2C][12:5];</a>
+<a name="1614"><span class="lineNum">    1614 </span>            :         spec_queue_13_retAddr = {_RANDOM[7'h2C][31:13], _RANDOM[7'h2D][21:0]};</a>
+<a name="1615"><span class="lineNum">    1615 </span>            :         spec_queue_13_ctr = _RANDOM[7'h2D][29:22];</a>
+<a name="1616"><span class="lineNum">    1616 </span>            :         spec_queue_14_retAddr =</a>
+<a name="1617"><span class="lineNum">    1617 </span>            :           {_RANDOM[7'h2D][31:30], _RANDOM[7'h2E], _RANDOM[7'h2F][6:0]};</a>
+<a name="1618"><span class="lineNum">    1618 </span>            :         spec_queue_14_ctr = _RANDOM[7'h2F][14:7];</a>
+<a name="1619"><span class="lineNum">    1619 </span>            :         spec_queue_15_retAddr = {_RANDOM[7'h2F][31:15], _RANDOM[7'h30][23:0]};</a>
+<a name="1620"><span class="lineNum">    1620 </span>            :         spec_queue_15_ctr = _RANDOM[7'h30][31:24];</a>
+<a name="1621"><span class="lineNum">    1621 </span>            :         spec_queue_16_retAddr = {_RANDOM[7'h31], _RANDOM[7'h32][8:0]};</a>
+<a name="1622"><span class="lineNum">    1622 </span>            :         spec_queue_16_ctr = _RANDOM[7'h32][16:9];</a>
+<a name="1623"><span class="lineNum">    1623 </span>            :         spec_queue_17_retAddr = {_RANDOM[7'h32][31:17], _RANDOM[7'h33][25:0]};</a>
+<a name="1624"><span class="lineNum">    1624 </span>            :         spec_queue_17_ctr = {_RANDOM[7'h33][31:26], _RANDOM[7'h34][1:0]};</a>
+<a name="1625"><span class="lineNum">    1625 </span>            :         spec_queue_18_retAddr = {_RANDOM[7'h34][31:2], _RANDOM[7'h35][10:0]};</a>
+<a name="1626"><span class="lineNum">    1626 </span>            :         spec_queue_18_ctr = _RANDOM[7'h35][18:11];</a>
+<a name="1627"><span class="lineNum">    1627 </span>            :         spec_queue_19_retAddr = {_RANDOM[7'h35][31:19], _RANDOM[7'h36][27:0]};</a>
+<a name="1628"><span class="lineNum">    1628 </span>            :         spec_queue_19_ctr = {_RANDOM[7'h36][31:28], _RANDOM[7'h37][3:0]};</a>
+<a name="1629"><span class="lineNum">    1629 </span>            :         spec_queue_20_retAddr = {_RANDOM[7'h37][31:4], _RANDOM[7'h38][12:0]};</a>
+<a name="1630"><span class="lineNum">    1630 </span>            :         spec_queue_20_ctr = _RANDOM[7'h38][20:13];</a>
+<a name="1631"><span class="lineNum">    1631 </span>            :         spec_queue_21_retAddr = {_RANDOM[7'h38][31:21], _RANDOM[7'h39][29:0]};</a>
+<a name="1632"><span class="lineNum">    1632 </span>            :         spec_queue_21_ctr = {_RANDOM[7'h39][31:30], _RANDOM[7'h3A][5:0]};</a>
+<a name="1633"><span class="lineNum">    1633 </span>            :         spec_queue_22_retAddr = {_RANDOM[7'h3A][31:6], _RANDOM[7'h3B][14:0]};</a>
+<a name="1634"><span class="lineNum">    1634 </span>            :         spec_queue_22_ctr = _RANDOM[7'h3B][22:15];</a>
+<a name="1635"><span class="lineNum">    1635 </span>            :         spec_queue_23_retAddr = {_RANDOM[7'h3B][31:23], _RANDOM[7'h3C]};</a>
+<a name="1636"><span class="lineNum">    1636 </span>            :         spec_queue_23_ctr = _RANDOM[7'h3D][7:0];</a>
+<a name="1637"><span class="lineNum">    1637 </span>            :         spec_queue_24_retAddr = {_RANDOM[7'h3D][31:8], _RANDOM[7'h3E][16:0]};</a>
+<a name="1638"><span class="lineNum">    1638 </span>            :         spec_queue_24_ctr = _RANDOM[7'h3E][24:17];</a>
+<a name="1639"><span class="lineNum">    1639 </span>            :         spec_queue_25_retAddr =</a>
+<a name="1640"><span class="lineNum">    1640 </span>            :           {_RANDOM[7'h3E][31:25], _RANDOM[7'h3F], _RANDOM[7'h40][1:0]};</a>
+<a name="1641"><span class="lineNum">    1641 </span>            :         spec_queue_25_ctr = _RANDOM[7'h40][9:2];</a>
+<a name="1642"><span class="lineNum">    1642 </span>            :         spec_queue_26_retAddr = {_RANDOM[7'h40][31:10], _RANDOM[7'h41][18:0]};</a>
+<a name="1643"><span class="lineNum">    1643 </span>            :         spec_queue_26_ctr = _RANDOM[7'h41][26:19];</a>
+<a name="1644"><span class="lineNum">    1644 </span>            :         spec_queue_27_retAddr =</a>
+<a name="1645"><span class="lineNum">    1645 </span>            :           {_RANDOM[7'h41][31:27], _RANDOM[7'h42], _RANDOM[7'h43][3:0]};</a>
+<a name="1646"><span class="lineNum">    1646 </span>            :         spec_queue_27_ctr = _RANDOM[7'h43][11:4];</a>
+<a name="1647"><span class="lineNum">    1647 </span>            :         spec_queue_28_retAddr = {_RANDOM[7'h43][31:12], _RANDOM[7'h44][20:0]};</a>
+<a name="1648"><span class="lineNum">    1648 </span>            :         spec_queue_28_ctr = _RANDOM[7'h44][28:21];</a>
+<a name="1649"><span class="lineNum">    1649 </span>            :         spec_queue_29_retAddr =</a>
+<a name="1650"><span class="lineNum">    1650 </span>            :           {_RANDOM[7'h44][31:29], _RANDOM[7'h45], _RANDOM[7'h46][5:0]};</a>
+<a name="1651"><span class="lineNum">    1651 </span>            :         spec_queue_29_ctr = _RANDOM[7'h46][13:6];</a>
+<a name="1652"><span class="lineNum">    1652 </span>            :         spec_queue_30_retAddr = {_RANDOM[7'h46][31:14], _RANDOM[7'h47][22:0]};</a>
+<a name="1653"><span class="lineNum">    1653 </span>            :         spec_queue_30_ctr = _RANDOM[7'h47][30:23];</a>
+<a name="1654"><span class="lineNum">    1654 </span>            :         spec_queue_31_retAddr = {_RANDOM[7'h47][31], _RANDOM[7'h48], _RANDOM[7'h49][7:0]};</a>
+<a name="1655"><span class="lineNum">    1655 </span>            :         spec_queue_31_ctr = _RANDOM[7'h49][15:8];</a>
+<a name="1656"><span class="lineNum">    1656 </span>            :         spec_nos_0_flag = _RANDOM[7'h49][16];</a>
+<a name="1657"><span class="lineNum">    1657 </span>            :         spec_nos_0_value = _RANDOM[7'h49][21:17];</a>
+<a name="1658"><span class="lineNum">    1658 </span>            :         spec_nos_1_flag = _RANDOM[7'h49][22];</a>
+<a name="1659"><span class="lineNum">    1659 </span>            :         spec_nos_1_value = _RANDOM[7'h49][27:23];</a>
+<a name="1660"><span class="lineNum">    1660 </span>            :         spec_nos_2_flag = _RANDOM[7'h49][28];</a>
+<a name="1661"><span class="lineNum">    1661 </span>            :         spec_nos_2_value = {_RANDOM[7'h49][31:29], _RANDOM[7'h4A][1:0]};</a>
+<a name="1662"><span class="lineNum">    1662 </span>            :         spec_nos_3_flag = _RANDOM[7'h4A][2];</a>
+<a name="1663"><span class="lineNum">    1663 </span>            :         spec_nos_3_value = _RANDOM[7'h4A][7:3];</a>
+<a name="1664"><span class="lineNum">    1664 </span>            :         spec_nos_4_flag = _RANDOM[7'h4A][8];</a>
+<a name="1665"><span class="lineNum">    1665 </span>            :         spec_nos_4_value = _RANDOM[7'h4A][13:9];</a>
+<a name="1666"><span class="lineNum">    1666 </span>            :         spec_nos_5_flag = _RANDOM[7'h4A][14];</a>
+<a name="1667"><span class="lineNum">    1667 </span>            :         spec_nos_5_value = _RANDOM[7'h4A][19:15];</a>
+<a name="1668"><span class="lineNum">    1668 </span>            :         spec_nos_6_flag = _RANDOM[7'h4A][20];</a>
+<a name="1669"><span class="lineNum">    1669 </span>            :         spec_nos_6_value = _RANDOM[7'h4A][25:21];</a>
+<a name="1670"><span class="lineNum">    1670 </span>            :         spec_nos_7_flag = _RANDOM[7'h4A][26];</a>
+<a name="1671"><span class="lineNum">    1671 </span>            :         spec_nos_7_value = _RANDOM[7'h4A][31:27];</a>
+<a name="1672"><span class="lineNum">    1672 </span>            :         spec_nos_8_flag = _RANDOM[7'h4B][0];</a>
+<a name="1673"><span class="lineNum">    1673 </span>            :         spec_nos_8_value = _RANDOM[7'h4B][5:1];</a>
+<a name="1674"><span class="lineNum">    1674 </span>            :         spec_nos_9_flag = _RANDOM[7'h4B][6];</a>
+<a name="1675"><span class="lineNum">    1675 </span>            :         spec_nos_9_value = _RANDOM[7'h4B][11:7];</a>
+<a name="1676"><span class="lineNum">    1676 </span>            :         spec_nos_10_flag = _RANDOM[7'h4B][12];</a>
+<a name="1677"><span class="lineNum">    1677 </span>            :         spec_nos_10_value = _RANDOM[7'h4B][17:13];</a>
+<a name="1678"><span class="lineNum">    1678 </span>            :         spec_nos_11_flag = _RANDOM[7'h4B][18];</a>
+<a name="1679"><span class="lineNum">    1679 </span>            :         spec_nos_11_value = _RANDOM[7'h4B][23:19];</a>
+<a name="1680"><span class="lineNum">    1680 </span>            :         spec_nos_12_flag = _RANDOM[7'h4B][24];</a>
+<a name="1681"><span class="lineNum">    1681 </span>            :         spec_nos_12_value = _RANDOM[7'h4B][29:25];</a>
+<a name="1682"><span class="lineNum">    1682 </span>            :         spec_nos_13_flag = _RANDOM[7'h4B][30];</a>
+<a name="1683"><span class="lineNum">    1683 </span>            :         spec_nos_13_value = {_RANDOM[7'h4B][31], _RANDOM[7'h4C][3:0]};</a>
+<a name="1684"><span class="lineNum">    1684 </span>            :         spec_nos_14_flag = _RANDOM[7'h4C][4];</a>
+<a name="1685"><span class="lineNum">    1685 </span>            :         spec_nos_14_value = _RANDOM[7'h4C][9:5];</a>
+<a name="1686"><span class="lineNum">    1686 </span>            :         spec_nos_15_flag = _RANDOM[7'h4C][10];</a>
+<a name="1687"><span class="lineNum">    1687 </span>            :         spec_nos_15_value = _RANDOM[7'h4C][15:11];</a>
+<a name="1688"><span class="lineNum">    1688 </span>            :         spec_nos_16_flag = _RANDOM[7'h4C][16];</a>
+<a name="1689"><span class="lineNum">    1689 </span>            :         spec_nos_16_value = _RANDOM[7'h4C][21:17];</a>
+<a name="1690"><span class="lineNum">    1690 </span>            :         spec_nos_17_flag = _RANDOM[7'h4C][22];</a>
+<a name="1691"><span class="lineNum">    1691 </span>            :         spec_nos_17_value = _RANDOM[7'h4C][27:23];</a>
+<a name="1692"><span class="lineNum">    1692 </span>            :         spec_nos_18_flag = _RANDOM[7'h4C][28];</a>
+<a name="1693"><span class="lineNum">    1693 </span>            :         spec_nos_18_value = {_RANDOM[7'h4C][31:29], _RANDOM[7'h4D][1:0]};</a>
+<a name="1694"><span class="lineNum">    1694 </span>            :         spec_nos_19_flag = _RANDOM[7'h4D][2];</a>
+<a name="1695"><span class="lineNum">    1695 </span>            :         spec_nos_19_value = _RANDOM[7'h4D][7:3];</a>
+<a name="1696"><span class="lineNum">    1696 </span>            :         spec_nos_20_flag = _RANDOM[7'h4D][8];</a>
+<a name="1697"><span class="lineNum">    1697 </span>            :         spec_nos_20_value = _RANDOM[7'h4D][13:9];</a>
+<a name="1698"><span class="lineNum">    1698 </span>            :         spec_nos_21_flag = _RANDOM[7'h4D][14];</a>
+<a name="1699"><span class="lineNum">    1699 </span>            :         spec_nos_21_value = _RANDOM[7'h4D][19:15];</a>
+<a name="1700"><span class="lineNum">    1700 </span>            :         spec_nos_22_flag = _RANDOM[7'h4D][20];</a>
+<a name="1701"><span class="lineNum">    1701 </span>            :         spec_nos_22_value = _RANDOM[7'h4D][25:21];</a>
+<a name="1702"><span class="lineNum">    1702 </span>            :         spec_nos_23_flag = _RANDOM[7'h4D][26];</a>
+<a name="1703"><span class="lineNum">    1703 </span>            :         spec_nos_23_value = _RANDOM[7'h4D][31:27];</a>
+<a name="1704"><span class="lineNum">    1704 </span>            :         spec_nos_24_flag = _RANDOM[7'h4E][0];</a>
+<a name="1705"><span class="lineNum">    1705 </span>            :         spec_nos_24_value = _RANDOM[7'h4E][5:1];</a>
+<a name="1706"><span class="lineNum">    1706 </span>            :         spec_nos_25_flag = _RANDOM[7'h4E][6];</a>
+<a name="1707"><span class="lineNum">    1707 </span>            :         spec_nos_25_value = _RANDOM[7'h4E][11:7];</a>
+<a name="1708"><span class="lineNum">    1708 </span>            :         spec_nos_26_flag = _RANDOM[7'h4E][12];</a>
+<a name="1709"><span class="lineNum">    1709 </span>            :         spec_nos_26_value = _RANDOM[7'h4E][17:13];</a>
+<a name="1710"><span class="lineNum">    1710 </span>            :         spec_nos_27_flag = _RANDOM[7'h4E][18];</a>
+<a name="1711"><span class="lineNum">    1711 </span>            :         spec_nos_27_value = _RANDOM[7'h4E][23:19];</a>
+<a name="1712"><span class="lineNum">    1712 </span>            :         spec_nos_28_flag = _RANDOM[7'h4E][24];</a>
+<a name="1713"><span class="lineNum">    1713 </span>            :         spec_nos_28_value = _RANDOM[7'h4E][29:25];</a>
+<a name="1714"><span class="lineNum">    1714 </span>            :         spec_nos_29_flag = _RANDOM[7'h4E][30];</a>
+<a name="1715"><span class="lineNum">    1715 </span>            :         spec_nos_29_value = {_RANDOM[7'h4E][31], _RANDOM[7'h4F][3:0]};</a>
+<a name="1716"><span class="lineNum">    1716 </span>            :         spec_nos_30_flag = _RANDOM[7'h4F][4];</a>
+<a name="1717"><span class="lineNum">    1717 </span>            :         spec_nos_30_value = _RANDOM[7'h4F][9:5];</a>
+<a name="1718"><span class="lineNum">    1718 </span>            :         spec_nos_31_flag = _RANDOM[7'h4F][10];</a>
+<a name="1719"><span class="lineNum">    1719 </span>            :         spec_nos_31_value = _RANDOM[7'h4F][15:11];</a>
+<a name="1720"><span class="lineNum">    1720 </span>            :         nsp = _RANDOM[7'h4F][19:16];</a>
+<a name="1721"><span class="lineNum">    1721 </span>            :         ssp = _RANDOM[7'h4F][23:20];</a>
+<a name="1722"><span class="lineNum">    1722 </span>            :         sctr = _RANDOM[7'h4F][26:24];</a>
+<a name="1723"><span class="lineNum">    1723 </span>            :         TOSR_flag = _RANDOM[7'h4F][27];</a>
+<a name="1724"><span class="lineNum">    1724 </span>            :         TOSR_value = {_RANDOM[7'h4F][31:28], _RANDOM[7'h50][0]};</a>
+<a name="1725"><span class="lineNum">    1725 </span>            :         TOSW_flag = _RANDOM[7'h50][1];</a>
+<a name="1726"><span class="lineNum">    1726 </span>            :         TOSW_value = _RANDOM[7'h50][6:2];</a>
+<a name="1727"><span class="lineNum">    1727 </span>            :         BOS_flag = _RANDOM[7'h50][7];</a>
+<a name="1728"><span class="lineNum">    1728 </span>            :         BOS_value = _RANDOM[7'h50][12:8];</a>
+<a name="1729"><span class="lineNum">    1729 </span>            :         spec_overflowed = _RANDOM[7'h50][13];</a>
+<a name="1730"><span class="lineNum">    1730 </span>            :         writeBypassEntry_retAddr = {_RANDOM[7'h50][31:14], _RANDOM[7'h51][22:0]};</a>
+<a name="1731"><span class="lineNum">    1731 </span>            :         writeBypassEntry_ctr = _RANDOM[7'h51][30:23];</a>
+<a name="1732"><span class="lineNum">    1732 </span>            :         writeBypassNos_flag = _RANDOM[7'h51][31];</a>
+<a name="1733"><span class="lineNum">    1733 </span>            :         writeBypassNos_value = _RANDOM[7'h52][4:0];</a>
+<a name="1734"><span class="lineNum">    1734 </span>            :         writeBypassValid = _RANDOM[7'h52][5];</a>
+<a name="1735"><span class="lineNum">    1735 </span>            :         timingTop_retAddr = {_RANDOM[7'h52][31:6], _RANDOM[7'h53][14:0]};</a>
+<a name="1736"><span class="lineNum">    1736 </span>            :         realWriteEntry_next_retAddr =</a>
+<a name="1737"><span class="lineNum">    1737 </span>            :           {_RANDOM[7'h53][31:29], _RANDOM[7'h54], _RANDOM[7'h55][5:0]};</a>
+<a name="1738"><span class="lineNum">    1738 </span>            :         realWriteEntry_next_ctr = _RANDOM[7'h55][13:6];</a>
+<a name="1739"><span class="lineNum">    1739 </span>            :         realWriteAddr_next_value = _RANDOM[7'h55][19:15];</a>
+<a name="1740"><span class="lineNum">    1740 </span>            :         realNos_next_flag = _RANDOM[7'h55][20];</a>
+<a name="1741"><span class="lineNum">    1741 </span>            :         realNos_next_value = _RANDOM[7'h55][25:21];</a>
+<a name="1742"><span class="lineNum">    1742 </span>            :         realPush_r = _RANDOM[7'h55][26];</a>
+<a name="1743"><span class="lineNum">    1743 </span>            :         realPush_REG = _RANDOM[7'h55][27];</a>
+<a name="1744"><span class="lineNum">    1744 </span>            :       `endif // RANDOMIZE_REG_INIT</a>
+<a name="1745"><span class="lineNum">    1745 </span><span class="lineCov">         17 :       if (reset) begin</span></a>
+<a name="1746"><span class="lineNum">    1746 </span><span class="lineCov">         12 :         commit_stack_0_retAddr = 41'h0;</span></a>
+<a name="1747"><span class="lineNum">    1747 </span><span class="lineCov">         12 :         commit_stack_0_ctr = 8'h0;</span></a>
+<a name="1748"><span class="lineNum">    1748 </span><span class="lineCov">         12 :         commit_stack_1_retAddr = 41'h0;</span></a>
+<a name="1749"><span class="lineNum">    1749 </span><span class="lineCov">         12 :         commit_stack_1_ctr = 8'h0;</span></a>
+<a name="1750"><span class="lineNum">    1750 </span><span class="lineCov">         12 :         commit_stack_2_retAddr = 41'h0;</span></a>
+<a name="1751"><span class="lineNum">    1751 </span><span class="lineCov">         12 :         commit_stack_2_ctr = 8'h0;</span></a>
+<a name="1752"><span class="lineNum">    1752 </span><span class="lineCov">         12 :         commit_stack_3_retAddr = 41'h0;</span></a>
+<a name="1753"><span class="lineNum">    1753 </span><span class="lineCov">         12 :         commit_stack_3_ctr = 8'h0;</span></a>
+<a name="1754"><span class="lineNum">    1754 </span><span class="lineCov">         12 :         commit_stack_4_retAddr = 41'h0;</span></a>
+<a name="1755"><span class="lineNum">    1755 </span><span class="lineCov">         12 :         commit_stack_4_ctr = 8'h0;</span></a>
+<a name="1756"><span class="lineNum">    1756 </span><span class="lineCov">         12 :         commit_stack_5_retAddr = 41'h0;</span></a>
+<a name="1757"><span class="lineNum">    1757 </span><span class="lineCov">         12 :         commit_stack_5_ctr = 8'h0;</span></a>
+<a name="1758"><span class="lineNum">    1758 </span><span class="lineCov">         12 :         commit_stack_6_retAddr = 41'h0;</span></a>
+<a name="1759"><span class="lineNum">    1759 </span><span class="lineCov">         12 :         commit_stack_6_ctr = 8'h0;</span></a>
+<a name="1760"><span class="lineNum">    1760 </span><span class="lineCov">         12 :         commit_stack_7_retAddr = 41'h0;</span></a>
+<a name="1761"><span class="lineNum">    1761 </span><span class="lineCov">         12 :         commit_stack_7_ctr = 8'h0;</span></a>
+<a name="1762"><span class="lineNum">    1762 </span><span class="lineCov">         12 :         commit_stack_8_retAddr = 41'h0;</span></a>
+<a name="1763"><span class="lineNum">    1763 </span><span class="lineCov">         12 :         commit_stack_8_ctr = 8'h0;</span></a>
+<a name="1764"><span class="lineNum">    1764 </span><span class="lineCov">         12 :         commit_stack_9_retAddr = 41'h0;</span></a>
+<a name="1765"><span class="lineNum">    1765 </span><span class="lineCov">         12 :         commit_stack_9_ctr = 8'h0;</span></a>
+<a name="1766"><span class="lineNum">    1766 </span><span class="lineCov">         12 :         commit_stack_10_retAddr = 41'h0;</span></a>
+<a name="1767"><span class="lineNum">    1767 </span><span class="lineCov">         12 :         commit_stack_10_ctr = 8'h0;</span></a>
+<a name="1768"><span class="lineNum">    1768 </span><span class="lineCov">         12 :         commit_stack_11_retAddr = 41'h0;</span></a>
+<a name="1769"><span class="lineNum">    1769 </span><span class="lineCov">         12 :         commit_stack_11_ctr = 8'h0;</span></a>
+<a name="1770"><span class="lineNum">    1770 </span><span class="lineCov">         12 :         commit_stack_12_retAddr = 41'h0;</span></a>
+<a name="1771"><span class="lineNum">    1771 </span><span class="lineCov">         12 :         commit_stack_12_ctr = 8'h0;</span></a>
+<a name="1772"><span class="lineNum">    1772 </span><span class="lineCov">         12 :         commit_stack_13_retAddr = 41'h0;</span></a>
+<a name="1773"><span class="lineNum">    1773 </span><span class="lineCov">         12 :         commit_stack_13_ctr = 8'h0;</span></a>
+<a name="1774"><span class="lineNum">    1774 </span><span class="lineCov">         12 :         commit_stack_14_retAddr = 41'h0;</span></a>
+<a name="1775"><span class="lineNum">    1775 </span><span class="lineCov">         12 :         commit_stack_14_ctr = 8'h0;</span></a>
+<a name="1776"><span class="lineNum">    1776 </span><span class="lineCov">         12 :         commit_stack_15_retAddr = 41'h0;</span></a>
+<a name="1777"><span class="lineNum">    1777 </span><span class="lineCov">         12 :         commit_stack_15_ctr = 8'h0;</span></a>
+<a name="1778"><span class="lineNum">    1778 </span><span class="lineCov">         12 :         spec_queue_0_retAddr = 41'h0;</span></a>
+<a name="1779"><span class="lineNum">    1779 </span><span class="lineCov">         12 :         spec_queue_0_ctr = 8'h0;</span></a>
+<a name="1780"><span class="lineNum">    1780 </span><span class="lineCov">         12 :         spec_queue_1_retAddr = 41'h0;</span></a>
+<a name="1781"><span class="lineNum">    1781 </span><span class="lineCov">         12 :         spec_queue_1_ctr = 8'h0;</span></a>
+<a name="1782"><span class="lineNum">    1782 </span><span class="lineCov">         12 :         spec_queue_2_retAddr = 41'h0;</span></a>
+<a name="1783"><span class="lineNum">    1783 </span><span class="lineCov">         12 :         spec_queue_2_ctr = 8'h0;</span></a>
+<a name="1784"><span class="lineNum">    1784 </span><span class="lineCov">         12 :         spec_queue_3_retAddr = 41'h0;</span></a>
+<a name="1785"><span class="lineNum">    1785 </span><span class="lineCov">         12 :         spec_queue_3_ctr = 8'h0;</span></a>
+<a name="1786"><span class="lineNum">    1786 </span><span class="lineCov">         12 :         spec_queue_4_retAddr = 41'h0;</span></a>
+<a name="1787"><span class="lineNum">    1787 </span><span class="lineCov">         12 :         spec_queue_4_ctr = 8'h0;</span></a>
+<a name="1788"><span class="lineNum">    1788 </span><span class="lineCov">         12 :         spec_queue_5_retAddr = 41'h0;</span></a>
+<a name="1789"><span class="lineNum">    1789 </span><span class="lineCov">         12 :         spec_queue_5_ctr = 8'h0;</span></a>
+<a name="1790"><span class="lineNum">    1790 </span><span class="lineCov">         12 :         spec_queue_6_retAddr = 41'h0;</span></a>
+<a name="1791"><span class="lineNum">    1791 </span><span class="lineCov">         12 :         spec_queue_6_ctr = 8'h0;</span></a>
+<a name="1792"><span class="lineNum">    1792 </span><span class="lineCov">         12 :         spec_queue_7_retAddr = 41'h0;</span></a>
+<a name="1793"><span class="lineNum">    1793 </span><span class="lineCov">         12 :         spec_queue_7_ctr = 8'h0;</span></a>
+<a name="1794"><span class="lineNum">    1794 </span><span class="lineCov">         12 :         spec_queue_8_retAddr = 41'h0;</span></a>
+<a name="1795"><span class="lineNum">    1795 </span><span class="lineCov">         12 :         spec_queue_8_ctr = 8'h0;</span></a>
+<a name="1796"><span class="lineNum">    1796 </span><span class="lineCov">         12 :         spec_queue_9_retAddr = 41'h0;</span></a>
+<a name="1797"><span class="lineNum">    1797 </span><span class="lineCov">         12 :         spec_queue_9_ctr = 8'h0;</span></a>
+<a name="1798"><span class="lineNum">    1798 </span><span class="lineCov">         12 :         spec_queue_10_retAddr = 41'h0;</span></a>
+<a name="1799"><span class="lineNum">    1799 </span><span class="lineCov">         12 :         spec_queue_10_ctr = 8'h0;</span></a>
+<a name="1800"><span class="lineNum">    1800 </span><span class="lineCov">         12 :         spec_queue_11_retAddr = 41'h0;</span></a>
+<a name="1801"><span class="lineNum">    1801 </span><span class="lineCov">         12 :         spec_queue_11_ctr = 8'h0;</span></a>
+<a name="1802"><span class="lineNum">    1802 </span><span class="lineCov">         12 :         spec_queue_12_retAddr = 41'h0;</span></a>
+<a name="1803"><span class="lineNum">    1803 </span><span class="lineCov">         12 :         spec_queue_12_ctr = 8'h0;</span></a>
+<a name="1804"><span class="lineNum">    1804 </span><span class="lineCov">         12 :         spec_queue_13_retAddr = 41'h0;</span></a>
+<a name="1805"><span class="lineNum">    1805 </span><span class="lineCov">         12 :         spec_queue_13_ctr = 8'h0;</span></a>
+<a name="1806"><span class="lineNum">    1806 </span><span class="lineCov">         12 :         spec_queue_14_retAddr = 41'h0;</span></a>
+<a name="1807"><span class="lineNum">    1807 </span><span class="lineCov">         12 :         spec_queue_14_ctr = 8'h0;</span></a>
+<a name="1808"><span class="lineNum">    1808 </span><span class="lineCov">         12 :         spec_queue_15_retAddr = 41'h0;</span></a>
+<a name="1809"><span class="lineNum">    1809 </span><span class="lineCov">         12 :         spec_queue_15_ctr = 8'h0;</span></a>
+<a name="1810"><span class="lineNum">    1810 </span><span class="lineCov">         12 :         spec_queue_16_retAddr = 41'h0;</span></a>
+<a name="1811"><span class="lineNum">    1811 </span><span class="lineCov">         12 :         spec_queue_16_ctr = 8'h0;</span></a>
+<a name="1812"><span class="lineNum">    1812 </span><span class="lineCov">         12 :         spec_queue_17_retAddr = 41'h0;</span></a>
+<a name="1813"><span class="lineNum">    1813 </span><span class="lineCov">         12 :         spec_queue_17_ctr = 8'h0;</span></a>
+<a name="1814"><span class="lineNum">    1814 </span><span class="lineCov">         12 :         spec_queue_18_retAddr = 41'h0;</span></a>
+<a name="1815"><span class="lineNum">    1815 </span><span class="lineCov">         12 :         spec_queue_18_ctr = 8'h0;</span></a>
+<a name="1816"><span class="lineNum">    1816 </span><span class="lineCov">         12 :         spec_queue_19_retAddr = 41'h0;</span></a>
+<a name="1817"><span class="lineNum">    1817 </span><span class="lineCov">         12 :         spec_queue_19_ctr = 8'h0;</span></a>
+<a name="1818"><span class="lineNum">    1818 </span><span class="lineCov">         12 :         spec_queue_20_retAddr = 41'h0;</span></a>
+<a name="1819"><span class="lineNum">    1819 </span><span class="lineCov">         12 :         spec_queue_20_ctr = 8'h0;</span></a>
+<a name="1820"><span class="lineNum">    1820 </span><span class="lineCov">         12 :         spec_queue_21_retAddr = 41'h0;</span></a>
+<a name="1821"><span class="lineNum">    1821 </span><span class="lineCov">         12 :         spec_queue_21_ctr = 8'h0;</span></a>
+<a name="1822"><span class="lineNum">    1822 </span><span class="lineCov">         12 :         spec_queue_22_retAddr = 41'h0;</span></a>
+<a name="1823"><span class="lineNum">    1823 </span><span class="lineCov">         12 :         spec_queue_22_ctr = 8'h0;</span></a>
+<a name="1824"><span class="lineNum">    1824 </span><span class="lineCov">         12 :         spec_queue_23_retAddr = 41'h0;</span></a>
+<a name="1825"><span class="lineNum">    1825 </span><span class="lineCov">         12 :         spec_queue_23_ctr = 8'h0;</span></a>
+<a name="1826"><span class="lineNum">    1826 </span><span class="lineCov">         12 :         spec_queue_24_retAddr = 41'h0;</span></a>
+<a name="1827"><span class="lineNum">    1827 </span><span class="lineCov">         12 :         spec_queue_24_ctr = 8'h0;</span></a>
+<a name="1828"><span class="lineNum">    1828 </span><span class="lineCov">         12 :         spec_queue_25_retAddr = 41'h0;</span></a>
+<a name="1829"><span class="lineNum">    1829 </span><span class="lineCov">         12 :         spec_queue_25_ctr = 8'h0;</span></a>
+<a name="1830"><span class="lineNum">    1830 </span><span class="lineCov">         12 :         spec_queue_26_retAddr = 41'h0;</span></a>
+<a name="1831"><span class="lineNum">    1831 </span><span class="lineCov">         12 :         spec_queue_26_ctr = 8'h0;</span></a>
+<a name="1832"><span class="lineNum">    1832 </span><span class="lineCov">         12 :         spec_queue_27_retAddr = 41'h0;</span></a>
+<a name="1833"><span class="lineNum">    1833 </span><span class="lineCov">         12 :         spec_queue_27_ctr = 8'h0;</span></a>
+<a name="1834"><span class="lineNum">    1834 </span><span class="lineCov">         12 :         spec_queue_28_retAddr = 41'h0;</span></a>
+<a name="1835"><span class="lineNum">    1835 </span><span class="lineCov">         12 :         spec_queue_28_ctr = 8'h0;</span></a>
+<a name="1836"><span class="lineNum">    1836 </span><span class="lineCov">         12 :         spec_queue_29_retAddr = 41'h0;</span></a>
+<a name="1837"><span class="lineNum">    1837 </span><span class="lineCov">         12 :         spec_queue_29_ctr = 8'h0;</span></a>
+<a name="1838"><span class="lineNum">    1838 </span><span class="lineCov">         12 :         spec_queue_30_retAddr = 41'h0;</span></a>
+<a name="1839"><span class="lineNum">    1839 </span><span class="lineCov">         12 :         spec_queue_30_ctr = 8'h0;</span></a>
+<a name="1840"><span class="lineNum">    1840 </span><span class="lineCov">         12 :         spec_queue_31_retAddr = 41'h0;</span></a>
+<a name="1841"><span class="lineNum">    1841 </span><span class="lineCov">         12 :         spec_queue_31_ctr = 8'h0;</span></a>
+<a name="1842"><span class="lineNum">    1842 </span><span class="lineCov">         12 :         spec_nos_0_flag = 1'h0;</span></a>
+<a name="1843"><span class="lineNum">    1843 </span><span class="lineCov">         12 :         spec_nos_0_value = 5'h0;</span></a>
+<a name="1844"><span class="lineNum">    1844 </span><span class="lineCov">         12 :         spec_nos_1_flag = 1'h0;</span></a>
+<a name="1845"><span class="lineNum">    1845 </span><span class="lineCov">         12 :         spec_nos_1_value = 5'h0;</span></a>
+<a name="1846"><span class="lineNum">    1846 </span><span class="lineCov">         12 :         spec_nos_2_flag = 1'h0;</span></a>
+<a name="1847"><span class="lineNum">    1847 </span><span class="lineCov">         12 :         spec_nos_2_value = 5'h0;</span></a>
+<a name="1848"><span class="lineNum">    1848 </span><span class="lineCov">         12 :         spec_nos_3_flag = 1'h0;</span></a>
+<a name="1849"><span class="lineNum">    1849 </span><span class="lineCov">         12 :         spec_nos_3_value = 5'h0;</span></a>
+<a name="1850"><span class="lineNum">    1850 </span><span class="lineCov">         12 :         spec_nos_4_flag = 1'h0;</span></a>
+<a name="1851"><span class="lineNum">    1851 </span><span class="lineCov">         12 :         spec_nos_4_value = 5'h0;</span></a>
+<a name="1852"><span class="lineNum">    1852 </span><span class="lineCov">         12 :         spec_nos_5_flag = 1'h0;</span></a>
+<a name="1853"><span class="lineNum">    1853 </span><span class="lineCov">         12 :         spec_nos_5_value = 5'h0;</span></a>
+<a name="1854"><span class="lineNum">    1854 </span><span class="lineCov">         12 :         spec_nos_6_flag = 1'h0;</span></a>
+<a name="1855"><span class="lineNum">    1855 </span><span class="lineCov">         12 :         spec_nos_6_value = 5'h0;</span></a>
+<a name="1856"><span class="lineNum">    1856 </span><span class="lineCov">         12 :         spec_nos_7_flag = 1'h0;</span></a>
+<a name="1857"><span class="lineNum">    1857 </span><span class="lineCov">         12 :         spec_nos_7_value = 5'h0;</span></a>
+<a name="1858"><span class="lineNum">    1858 </span><span class="lineCov">         12 :         spec_nos_8_flag = 1'h0;</span></a>
+<a name="1859"><span class="lineNum">    1859 </span><span class="lineCov">         12 :         spec_nos_8_value = 5'h0;</span></a>
+<a name="1860"><span class="lineNum">    1860 </span><span class="lineCov">         12 :         spec_nos_9_flag = 1'h0;</span></a>
+<a name="1861"><span class="lineNum">    1861 </span><span class="lineCov">         12 :         spec_nos_9_value = 5'h0;</span></a>
+<a name="1862"><span class="lineNum">    1862 </span><span class="lineCov">         12 :         spec_nos_10_flag = 1'h0;</span></a>
+<a name="1863"><span class="lineNum">    1863 </span><span class="lineCov">         12 :         spec_nos_10_value = 5'h0;</span></a>
+<a name="1864"><span class="lineNum">    1864 </span><span class="lineCov">         12 :         spec_nos_11_flag = 1'h0;</span></a>
+<a name="1865"><span class="lineNum">    1865 </span><span class="lineCov">         12 :         spec_nos_11_value = 5'h0;</span></a>
+<a name="1866"><span class="lineNum">    1866 </span><span class="lineCov">         12 :         spec_nos_12_flag = 1'h0;</span></a>
+<a name="1867"><span class="lineNum">    1867 </span><span class="lineCov">         12 :         spec_nos_12_value = 5'h0;</span></a>
+<a name="1868"><span class="lineNum">    1868 </span><span class="lineCov">         12 :         spec_nos_13_flag = 1'h0;</span></a>
+<a name="1869"><span class="lineNum">    1869 </span><span class="lineCov">         12 :         spec_nos_13_value = 5'h0;</span></a>
+<a name="1870"><span class="lineNum">    1870 </span><span class="lineCov">         12 :         spec_nos_14_flag = 1'h0;</span></a>
+<a name="1871"><span class="lineNum">    1871 </span><span class="lineCov">         12 :         spec_nos_14_value = 5'h0;</span></a>
+<a name="1872"><span class="lineNum">    1872 </span><span class="lineCov">         12 :         spec_nos_15_flag = 1'h0;</span></a>
+<a name="1873"><span class="lineNum">    1873 </span><span class="lineCov">         12 :         spec_nos_15_value = 5'h0;</span></a>
+<a name="1874"><span class="lineNum">    1874 </span><span class="lineCov">         12 :         spec_nos_16_flag = 1'h0;</span></a>
+<a name="1875"><span class="lineNum">    1875 </span><span class="lineCov">         12 :         spec_nos_16_value = 5'h0;</span></a>
+<a name="1876"><span class="lineNum">    1876 </span><span class="lineCov">         12 :         spec_nos_17_flag = 1'h0;</span></a>
+<a name="1877"><span class="lineNum">    1877 </span><span class="lineCov">         12 :         spec_nos_17_value = 5'h0;</span></a>
+<a name="1878"><span class="lineNum">    1878 </span><span class="lineCov">         12 :         spec_nos_18_flag = 1'h0;</span></a>
+<a name="1879"><span class="lineNum">    1879 </span><span class="lineCov">         12 :         spec_nos_18_value = 5'h0;</span></a>
+<a name="1880"><span class="lineNum">    1880 </span><span class="lineCov">         12 :         spec_nos_19_flag = 1'h0;</span></a>
+<a name="1881"><span class="lineNum">    1881 </span><span class="lineCov">         12 :         spec_nos_19_value = 5'h0;</span></a>
+<a name="1882"><span class="lineNum">    1882 </span><span class="lineCov">         12 :         spec_nos_20_flag = 1'h0;</span></a>
+<a name="1883"><span class="lineNum">    1883 </span><span class="lineCov">         12 :         spec_nos_20_value = 5'h0;</span></a>
+<a name="1884"><span class="lineNum">    1884 </span><span class="lineCov">         12 :         spec_nos_21_flag = 1'h0;</span></a>
+<a name="1885"><span class="lineNum">    1885 </span><span class="lineCov">         12 :         spec_nos_21_value = 5'h0;</span></a>
+<a name="1886"><span class="lineNum">    1886 </span><span class="lineCov">         12 :         spec_nos_22_flag = 1'h0;</span></a>
+<a name="1887"><span class="lineNum">    1887 </span><span class="lineCov">         12 :         spec_nos_22_value = 5'h0;</span></a>
+<a name="1888"><span class="lineNum">    1888 </span><span class="lineCov">         12 :         spec_nos_23_flag = 1'h0;</span></a>
+<a name="1889"><span class="lineNum">    1889 </span><span class="lineCov">         12 :         spec_nos_23_value = 5'h0;</span></a>
+<a name="1890"><span class="lineNum">    1890 </span><span class="lineCov">         12 :         spec_nos_24_flag = 1'h0;</span></a>
+<a name="1891"><span class="lineNum">    1891 </span><span class="lineCov">         12 :         spec_nos_24_value = 5'h0;</span></a>
+<a name="1892"><span class="lineNum">    1892 </span><span class="lineCov">         12 :         spec_nos_25_flag = 1'h0;</span></a>
+<a name="1893"><span class="lineNum">    1893 </span><span class="lineCov">         12 :         spec_nos_25_value = 5'h0;</span></a>
+<a name="1894"><span class="lineNum">    1894 </span><span class="lineCov">         12 :         spec_nos_26_flag = 1'h0;</span></a>
+<a name="1895"><span class="lineNum">    1895 </span><span class="lineCov">         12 :         spec_nos_26_value = 5'h0;</span></a>
+<a name="1896"><span class="lineNum">    1896 </span><span class="lineCov">         12 :         spec_nos_27_flag = 1'h0;</span></a>
+<a name="1897"><span class="lineNum">    1897 </span><span class="lineCov">         12 :         spec_nos_27_value = 5'h0;</span></a>
+<a name="1898"><span class="lineNum">    1898 </span><span class="lineCov">         12 :         spec_nos_28_flag = 1'h0;</span></a>
+<a name="1899"><span class="lineNum">    1899 </span><span class="lineCov">         12 :         spec_nos_28_value = 5'h0;</span></a>
+<a name="1900"><span class="lineNum">    1900 </span><span class="lineCov">         12 :         spec_nos_29_flag = 1'h0;</span></a>
+<a name="1901"><span class="lineNum">    1901 </span><span class="lineCov">         12 :         spec_nos_29_value = 5'h0;</span></a>
+<a name="1902"><span class="lineNum">    1902 </span><span class="lineCov">         12 :         spec_nos_30_flag = 1'h0;</span></a>
+<a name="1903"><span class="lineNum">    1903 </span><span class="lineCov">         12 :         spec_nos_30_value = 5'h0;</span></a>
+<a name="1904"><span class="lineNum">    1904 </span><span class="lineCov">         12 :         spec_nos_31_flag = 1'h0;</span></a>
+<a name="1905"><span class="lineNum">    1905 </span><span class="lineCov">         12 :         spec_nos_31_value = 5'h0;</span></a>
+<a name="1906"><span class="lineNum">    1906 </span><span class="lineCov">         12 :         nsp = 4'h0;</span></a>
+<a name="1907"><span class="lineNum">    1907 </span><span class="lineCov">         12 :         ssp = 4'h0;</span></a>
+<a name="1908"><span class="lineNum">    1908 </span><span class="lineCov">         12 :         sctr = 3'h0;</span></a>
+<a name="1909"><span class="lineNum">    1909 </span><span class="lineCov">         12 :         TOSR_flag = 1'h1;</span></a>
+<a name="1910"><span class="lineNum">    1910 </span><span class="lineCov">         12 :         TOSR_value = 5'h1F;</span></a>
+<a name="1911"><span class="lineNum">    1911 </span><span class="lineCov">         12 :         TOSW_flag = 1'h0;</span></a>
+<a name="1912"><span class="lineNum">    1912 </span><span class="lineCov">         12 :         TOSW_value = 5'h0;</span></a>
+<a name="1913"><span class="lineNum">    1913 </span><span class="lineCov">         12 :         BOS_flag = 1'h0;</span></a>
+<a name="1914"><span class="lineNum">    1914 </span><span class="lineCov">         12 :         BOS_value = 5'h0;</span></a>
+<a name="1915"><span class="lineNum">    1915 </span><span class="lineCov">         12 :         spec_overflowed = 1'h0;</span></a>
+<a name="1916"><span class="lineNum">    1916 </span><span class="lineCov">         12 :         writeBypassValid = 1'h0;</span></a>
+<a name="1917"><span class="lineNum">    1917 </span><span class="lineCov">         12 :         timingTop_retAddr = 41'h0;</span></a>
+<a name="1918"><span class="lineNum">    1918 </span>            :       end</a>
+<a name="1919"><span class="lineNum">    1919 </span>            :     end // initial</a>
+<a name="1920"><span class="lineNum">    1920 </span>            :     `ifdef FIRRTL_AFTER_INITIAL</a>
+<a name="1921"><span class="lineNum">    1921 </span>            :       `FIRRTL_AFTER_INITIAL</a>
+<a name="1922"><span class="lineNum">    1922 </span>            :     `endif // FIRRTL_AFTER_INITIAL</a>
+<a name="1923"><span class="lineNum">    1923 </span>            :   `endif // ENABLE_INITIAL_REG_</a>
+<a name="1924"><span class="lineNum">    1924 </span>            :   assign io_spec_pop_addr = timingTop_retAddr;</a>
+<a name="1925"><span class="lineNum">    1925 </span>            :   assign io_ssp = ssp;</a>
+<a name="1926"><span class="lineNum">    1926 </span>            :   assign io_sctr = sctr;</a>
+<a name="1927"><span class="lineNum">    1927 </span>            :   assign io_TOSR_flag = TOSR_flag;</a>
+<a name="1928"><span class="lineNum">    1928 </span>            :   assign io_TOSR_value = TOSR_value;</a>
+<a name="1929"><span class="lineNum">    1929 </span>            :   assign io_TOSW_flag = TOSW_flag;</a>
+<a name="1930"><span class="lineNum">    1930 </span>            :   assign io_TOSW_value = TOSW_value;</a>
+<a name="1931"><span class="lineNum">    1931 </span>            :   assign io_NOS_flag = topNos_flag;</a>
+<a name="1932"><span class="lineNum">    1932 </span>            :   assign io_NOS_value = topNos_value;</a>
+<a name="1933"><span class="lineNum">    1933 </span>            : endmodule</a>
+<a name="1934"><span class="lineNum">    1934 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SCTable.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SCTable.sv.func-sort-c.html
new file mode 100644
index 0000000..a8fbb77
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SCTable.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/SCTable.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - SCTable.sv<span style="font-size: 80%;"> (<a href="SCTable.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">34</td>
+            <td class="headerCovTableEntry">34</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="SCTable.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SCTable.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SCTable.sv.func.html
new file mode 100644
index 0000000..768b28b
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SCTable.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/SCTable.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - SCTable.sv<span style="font-size: 80%;"> (<a href="SCTable.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">34</td>
+            <td class="headerCovTableEntry">34</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="SCTable.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SCTable.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SCTable.sv.gcov.html
new file mode 100644
index 0000000..88f2280
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SCTable.sv.gcov.html
@@ -0,0 +1,320 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/SCTable.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - SCTable.sv<span style="font-size: 80%;"> (source / <a href="SCTable.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">34</td>
+            <td class="headerCovTableEntry">34</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : module SCTable(</a>
+<a name="59"><span class="lineNum">      59 </span><span class="lineCov">     127786 :   input         clock,</span></a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">         62 :   input         reset,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">         73 :   input         io_req_valid,</span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">      35066 :   input  [40:0] io_req_bits_pc,</span></a>
+<a name="63"><span class="lineNum">      63 </span><span class="lineCov">        165 :   output [5:0]  io_resp_ctrs_0_0,</span></a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">        184 :   output [5:0]  io_resp_ctrs_0_1,</span></a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">        162 :   output [5:0]  io_resp_ctrs_1_0,</span></a>
+<a name="66"><span class="lineNum">      66 </span><span class="lineCov">        162 :   output [5:0]  io_resp_ctrs_1_1,</span></a>
+<a name="67"><span class="lineNum">      67 </span><span class="lineCov">        618 :   input  [40:0] io_update_pc,</span></a>
+<a name="68"><span class="lineNum">      68 </span><span class="lineCov">         35 :   input         io_update_mask_0,</span></a>
+<a name="69"><span class="lineNum">      69 </span><span class="lineCov">         32 :   input         io_update_mask_1,</span></a>
+<a name="70"><span class="lineNum">      70 </span><span class="lineCov">        101 :   input  [5:0]  io_update_oldCtrs_0,</span></a>
+<a name="71"><span class="lineNum">      71 </span><span class="lineCov">        102 :   input  [5:0]  io_update_oldCtrs_1,</span></a>
+<a name="72"><span class="lineNum">      72 </span><span class="lineCov">         11 :   input         io_update_tagePreds_0,</span></a>
+<a name="73"><span class="lineNum">      73 </span><span class="lineCov">         19 :   input         io_update_tagePreds_1,</span></a>
+<a name="74"><span class="lineNum">      74 </span><span class="lineCov">         20 :   input         io_update_takens_0,</span></a>
+<a name="75"><span class="lineNum">      75 </span><span class="lineCov">         21 :   input         io_update_takens_1</span></a>
+<a name="76"><span class="lineNum">      76 </span>            : );</a>
+<a name="77"><span class="lineNum">      77 </span>            : </a>
+<a name="78"><span class="lineNum">      78 </span>            :   wire        _wrbypasses_1_io_hit;</a>
+<a name="79"><span class="lineNum">      79 </span>            :   wire        _wrbypasses_1_io_hit_data_0_valid;</a>
+<a name="80"><span class="lineNum">      80 </span>            :   wire [5:0]  _wrbypasses_1_io_hit_data_0_bits;</a>
+<a name="81"><span class="lineNum">      81 </span>            :   wire        _wrbypasses_1_io_hit_data_1_valid;</a>
+<a name="82"><span class="lineNum">      82 </span>            :   wire [5:0]  _wrbypasses_1_io_hit_data_1_bits;</a>
+<a name="83"><span class="lineNum">      83 </span>            :   wire        _wrbypasses_0_io_hit;</a>
+<a name="84"><span class="lineNum">      84 </span>            :   wire        _wrbypasses_0_io_hit_data_0_valid;</a>
+<a name="85"><span class="lineNum">      85 </span>            :   wire [5:0]  _wrbypasses_0_io_hit_data_0_bits;</a>
+<a name="86"><span class="lineNum">      86 </span>            :   wire        _wrbypasses_0_io_hit_data_1_valid;</a>
+<a name="87"><span class="lineNum">      87 </span>            :   wire [5:0]  _wrbypasses_0_io_hit_data_1_bits;</a>
+<a name="88"><span class="lineNum">      88 </span>            :   wire [5:0]  _table_io_r_resp_data_0;</a>
+<a name="89"><span class="lineNum">      89 </span>            :   wire [5:0]  _table_io_r_resp_data_1;</a>
+<a name="90"><span class="lineNum">      90 </span>            :   wire [5:0]  _table_io_r_resp_data_2;</a>
+<a name="91"><span class="lineNum">      91 </span>            :   wire [5:0]  _table_io_r_resp_data_3;</a>
+<a name="92"><span class="lineNum">      92 </span><span class="lineCov">       9416 :   reg  [40:0] s1_pc;</span></a>
+<a name="93"><span class="lineNum">      93 </span><span class="lineCov">         26 :   wire        updateWayMask_0 =</span></a>
+<a name="94"><span class="lineNum">      94 </span>            :     io_update_mask_0 &amp; ~(io_update_pc[1]) &amp; ~io_update_tagePreds_0 | io_update_mask_1</a>
+<a name="95"><span class="lineNum">      95 </span>            :     &amp; io_update_pc[1] &amp; ~io_update_tagePreds_1;</a>
+<a name="96"><span class="lineNum">      96 </span><span class="lineCov">         24 :   wire        updateWayMask_1 =</span></a>
+<a name="97"><span class="lineNum">      97 </span>            :     io_update_mask_0 &amp; ~(io_update_pc[1]) &amp; io_update_tagePreds_0 | io_update_mask_1</a>
+<a name="98"><span class="lineNum">      98 </span>            :     &amp; io_update_pc[1] &amp; io_update_tagePreds_1;</a>
+<a name="99"><span class="lineNum">      99 </span><span class="lineCov">         24 :   wire        updateWayMask_2 =</span></a>
+<a name="100"><span class="lineNum">     100 </span>            :     io_update_mask_0 &amp; io_update_pc[1] &amp; ~io_update_tagePreds_0 | io_update_mask_1</a>
+<a name="101"><span class="lineNum">     101 </span>            :     &amp; ~(io_update_pc[1]) &amp; ~io_update_tagePreds_1;</a>
+<a name="102"><span class="lineNum">     102 </span><span class="lineCov">         17 :   wire        updateWayMask_3 =</span></a>
+<a name="103"><span class="lineNum">     103 </span>            :     io_update_mask_0 &amp; io_update_pc[1] &amp; io_update_tagePreds_0 | io_update_mask_1</a>
+<a name="104"><span class="lineNum">     104 </span>            :     &amp; ~(io_update_pc[1]) &amp; io_update_tagePreds_1;</a>
+<a name="105"><span class="lineNum">     105 </span><span class="lineCov">         18 :   wire        ctrPos =</span></a>
+<a name="106"><span class="lineNum">     106 </span>            :     ~(io_update_pc[1]) &amp; io_update_tagePreds_0 | io_update_pc[1] &amp; io_update_tagePreds_1;</a>
+<a name="107"><span class="lineNum">     107 </span><span class="lineCov">        126 :   wire [5:0]  oldCtr =</span></a>
+<a name="108"><span class="lineNum">     108 </span>            :     (~(io_update_pc[1]) &amp; _wrbypasses_0_io_hit | io_update_pc[1] &amp; _wrbypasses_1_io_hit)</a>
+<a name="109"><span class="lineNum">     109 </span>            :     &amp; (ctrPos</a>
+<a name="110"><span class="lineNum">     110 </span>            :          ? ~(io_update_pc[1]) &amp; _wrbypasses_0_io_hit_data_1_valid | io_update_pc[1]</a>
+<a name="111"><span class="lineNum">     111 </span>            :            &amp; _wrbypasses_1_io_hit_data_1_valid</a>
+<a name="112"><span class="lineNum">     112 </span>            :          : ~(io_update_pc[1]) &amp; _wrbypasses_0_io_hit_data_0_valid | io_update_pc[1]</a>
+<a name="113"><span class="lineNum">     113 </span>            :            &amp; _wrbypasses_1_io_hit_data_0_valid)</a>
+<a name="114"><span class="lineNum">     114 </span>            :       ? (ctrPos</a>
+<a name="115"><span class="lineNum">     115 </span>            :            ? (io_update_pc[1] ? 6'h0 : _wrbypasses_0_io_hit_data_1_bits)</a>
+<a name="116"><span class="lineNum">     116 </span>            :              | (io_update_pc[1] ? _wrbypasses_1_io_hit_data_1_bits : 6'h0)</a>
+<a name="117"><span class="lineNum">     117 </span>            :            : (io_update_pc[1] ? 6'h0 : _wrbypasses_0_io_hit_data_0_bits)</a>
+<a name="118"><span class="lineNum">     118 </span>            :              | (io_update_pc[1] ? _wrbypasses_1_io_hit_data_0_bits : 6'h0))</a>
+<a name="119"><span class="lineNum">     119 </span>            :       : (io_update_pc[1] ? 6'h0 : io_update_oldCtrs_0)</a>
+<a name="120"><span class="lineNum">     120 </span>            :         | (io_update_pc[1] ? io_update_oldCtrs_1 : 6'h0);</a>
+<a name="121"><span class="lineNum">     121 </span><span class="lineCov">         17 :   wire        taken =</span></a>
+<a name="122"><span class="lineNum">     122 </span>            :     ~(io_update_pc[1]) &amp; io_update_takens_0 | io_update_pc[1] &amp; io_update_takens_1;</a>
+<a name="123"><span class="lineNum">     123 </span><span class="lineCov">        117 :   wire [5:0]  update_wdata_0 =</span></a>
+<a name="124"><span class="lineNum">     124 </span>            :     oldCtr == 6'h1F &amp; taken</a>
+<a name="125"><span class="lineNum">     125 </span>            :       ? 6'h1F</a>
+<a name="126"><span class="lineNum">     126 </span>            :       : oldCtr == 6'h20 &amp; ~taken ? 6'h20 : taken ? 6'(oldCtr + 6'h1) : 6'(oldCtr - 6'h1);</a>
+<a name="127"><span class="lineNum">     127 </span><span class="lineCov">         16 :   wire        ctrPos_1 =</span></a>
+<a name="128"><span class="lineNum">     128 </span>            :     io_update_pc[1] &amp; io_update_tagePreds_0 | ~(io_update_pc[1]) &amp; io_update_tagePreds_1;</a>
+<a name="129"><span class="lineNum">     129 </span><span class="lineCov">        123 :   wire [5:0]  oldCtr_1 =</span></a>
+<a name="130"><span class="lineNum">     130 </span>            :     (io_update_pc[1] &amp; _wrbypasses_0_io_hit | ~(io_update_pc[1]) &amp; _wrbypasses_1_io_hit)</a>
+<a name="131"><span class="lineNum">     131 </span>            :     &amp; (ctrPos_1</a>
+<a name="132"><span class="lineNum">     132 </span>            :          ? io_update_pc[1] &amp; _wrbypasses_0_io_hit_data_1_valid | ~(io_update_pc[1])</a>
+<a name="133"><span class="lineNum">     133 </span>            :            &amp; _wrbypasses_1_io_hit_data_1_valid</a>
+<a name="134"><span class="lineNum">     134 </span>            :          : io_update_pc[1] &amp; _wrbypasses_0_io_hit_data_0_valid | ~(io_update_pc[1])</a>
+<a name="135"><span class="lineNum">     135 </span>            :            &amp; _wrbypasses_1_io_hit_data_0_valid)</a>
+<a name="136"><span class="lineNum">     136 </span>            :       ? (ctrPos_1</a>
+<a name="137"><span class="lineNum">     137 </span>            :            ? (io_update_pc[1] ? _wrbypasses_0_io_hit_data_1_bits : 6'h0)</a>
+<a name="138"><span class="lineNum">     138 </span>            :              | (io_update_pc[1] ? 6'h0 : _wrbypasses_1_io_hit_data_1_bits)</a>
+<a name="139"><span class="lineNum">     139 </span>            :            : (io_update_pc[1] ? _wrbypasses_0_io_hit_data_0_bits : 6'h0)</a>
+<a name="140"><span class="lineNum">     140 </span>            :              | (io_update_pc[1] ? 6'h0 : _wrbypasses_1_io_hit_data_0_bits))</a>
+<a name="141"><span class="lineNum">     141 </span>            :       : (io_update_pc[1] ? io_update_oldCtrs_0 : 6'h0)</a>
+<a name="142"><span class="lineNum">     142 </span>            :         | (io_update_pc[1] ? 6'h0 : io_update_oldCtrs_1);</a>
+<a name="143"><span class="lineNum">     143 </span><span class="lineCov">         18 :   wire        taken_1 =</span></a>
+<a name="144"><span class="lineNum">     144 </span>            :     io_update_pc[1] &amp; io_update_takens_0 | ~(io_update_pc[1]) &amp; io_update_takens_1;</a>
+<a name="145"><span class="lineNum">     145 </span><span class="lineCov">        131 :   wire [5:0]  update_wdata_1 =</span></a>
+<a name="146"><span class="lineNum">     146 </span>            :     oldCtr_1 == 6'h1F &amp; taken_1</a>
+<a name="147"><span class="lineNum">     147 </span>            :       ? 6'h1F</a>
+<a name="148"><span class="lineNum">     148 </span>            :       : oldCtr_1 == 6'h20 &amp; ~taken_1</a>
+<a name="149"><span class="lineNum">     149 </span>            :           ? 6'h20</a>
+<a name="150"><span class="lineNum">     150 </span>            :           : taken_1 ? 6'(oldCtr_1 + 6'h1) : 6'(oldCtr_1 - 6'h1);</a>
+<a name="151"><span class="lineNum">     151 </span>            :   wire [5:0]  _GEN = io_update_pc[1] ? 6'h0 : update_wdata_0;</a>
+<a name="152"><span class="lineNum">     152 </span>            :   wire [5:0]  _GEN_0 = io_update_pc[1] ? update_wdata_1 : 6'h0;</a>
+<a name="153"><span class="lineNum">     153 </span>            :   wire [5:0]  _GEN_1 = io_update_pc[1] ? update_wdata_0 : 6'h0;</a>
+<a name="154"><span class="lineNum">     154 </span>            :   wire [5:0]  _GEN_2 = io_update_pc[1] ? 6'h0 : update_wdata_1;</a>
+<a name="155"><span class="lineNum">     155 </span><span class="lineCov">     127694 :   always @(posedge clock) begin</span></a>
+<a name="156"><span class="lineNum">     156 </span><span class="lineCov">       8350 :     if (io_req_valid)</span></a>
+<a name="157"><span class="lineNum">     157 </span><span class="lineCov">       4175 :       s1_pc &lt;= io_req_bits_pc;</span></a>
+<a name="158"><span class="lineNum">     158 </span>            :   end // always @(posedge)</a>
+<a name="159"><span class="lineNum">     159 </span>            :   `ifdef ENABLE_INITIAL_REG_</a>
+<a name="160"><span class="lineNum">     160 </span>            :     `ifdef FIRRTL_BEFORE_INITIAL</a>
+<a name="161"><span class="lineNum">     161 </span>            :       `FIRRTL_BEFORE_INITIAL</a>
+<a name="162"><span class="lineNum">     162 </span>            :     `endif // FIRRTL_BEFORE_INITIAL</a>
+<a name="163"><span class="lineNum">     163 </span>            :     logic [31:0] _RANDOM[0:1];</a>
+<a name="164"><span class="lineNum">     164 </span><span class="lineCov">         58 :     initial begin</span></a>
+<a name="165"><span class="lineNum">     165 </span>            :       `ifdef INIT_RANDOM_PROLOG_</a>
+<a name="166"><span class="lineNum">     166 </span>            :         `INIT_RANDOM_PROLOG_</a>
+<a name="167"><span class="lineNum">     167 </span>            :       `endif // INIT_RANDOM_PROLOG_</a>
+<a name="168"><span class="lineNum">     168 </span>            :       `ifdef RANDOMIZE_REG_INIT</a>
+<a name="169"><span class="lineNum">     169 </span>            :         for (logic [1:0] i = 2'h0; i &lt; 2'h2; i += 2'h1) begin</a>
+<a name="170"><span class="lineNum">     170 </span>            :           _RANDOM[i[0]] = `RANDOM;</a>
+<a name="171"><span class="lineNum">     171 </span>            :         end</a>
+<a name="172"><span class="lineNum">     172 </span>            :         s1_pc = {_RANDOM[1'h0][31:8], _RANDOM[1'h1][16:0]};</a>
+<a name="173"><span class="lineNum">     173 </span>            :       `endif // RANDOMIZE_REG_INIT</a>
+<a name="174"><span class="lineNum">     174 </span>            :     end // initial</a>
+<a name="175"><span class="lineNum">     175 </span>            :     `ifdef FIRRTL_AFTER_INITIAL</a>
+<a name="176"><span class="lineNum">     176 </span>            :       `FIRRTL_AFTER_INITIAL</a>
+<a name="177"><span class="lineNum">     177 </span>            :     `endif // FIRRTL_AFTER_INITIAL</a>
+<a name="178"><span class="lineNum">     178 </span>            :   `endif // ENABLE_INITIAL_REG_</a>
+<a name="179"><span class="lineNum">     179 </span>            :   SRAMTemplate_35 table_0 (</a>
+<a name="180"><span class="lineNum">     180 </span>            :     .clock                 (clock),</a>
+<a name="181"><span class="lineNum">     181 </span>            :     .reset                 (reset),</a>
+<a name="182"><span class="lineNum">     182 </span>            :     .io_r_req_valid        (io_req_valid),</a>
+<a name="183"><span class="lineNum">     183 </span>            :     .io_r_req_bits_setIdx  (io_req_bits_pc[8:1]),</a>
+<a name="184"><span class="lineNum">     184 </span>            :     .io_r_resp_data_0      (_table_io_r_resp_data_0),</a>
+<a name="185"><span class="lineNum">     185 </span>            :     .io_r_resp_data_1      (_table_io_r_resp_data_1),</a>
+<a name="186"><span class="lineNum">     186 </span>            :     .io_r_resp_data_2      (_table_io_r_resp_data_2),</a>
+<a name="187"><span class="lineNum">     187 </span>            :     .io_r_resp_data_3      (_table_io_r_resp_data_3),</a>
+<a name="188"><span class="lineNum">     188 </span>            :     .io_w_req_valid        (io_update_mask_0 | io_update_mask_1),</a>
+<a name="189"><span class="lineNum">     189 </span>            :     .io_w_req_bits_setIdx  (io_update_pc[8:1]),</a>
+<a name="190"><span class="lineNum">     190 </span>            :     .io_w_req_bits_data_0  (update_wdata_0),</a>
+<a name="191"><span class="lineNum">     191 </span>            :     .io_w_req_bits_data_1  (update_wdata_0),</a>
+<a name="192"><span class="lineNum">     192 </span>            :     .io_w_req_bits_data_2  (update_wdata_1),</a>
+<a name="193"><span class="lineNum">     193 </span>            :     .io_w_req_bits_data_3  (update_wdata_1),</a>
+<a name="194"><span class="lineNum">     194 </span>            :     .io_w_req_bits_waymask</a>
+<a name="195"><span class="lineNum">     195 </span>            :       ({updateWayMask_3, updateWayMask_2, updateWayMask_1, updateWayMask_0})</a>
+<a name="196"><span class="lineNum">     196 </span>            :   );</a>
+<a name="197"><span class="lineNum">     197 </span>            :   WrBypass_33 wrbypasses_0 (</a>
+<a name="198"><span class="lineNum">     198 </span>            :     .clock               (clock),</a>
+<a name="199"><span class="lineNum">     199 </span>            :     .reset               (reset),</a>
+<a name="200"><span class="lineNum">     200 </span>            :     .io_wen              (io_update_mask_0),</a>
+<a name="201"><span class="lineNum">     201 </span>            :     .io_write_idx        (io_update_pc[8:1]),</a>
+<a name="202"><span class="lineNum">     202 </span>            :     .io_write_data_0     (_GEN | _GEN_0),</a>
+<a name="203"><span class="lineNum">     203 </span>            :     .io_write_data_1     (_GEN | _GEN_0),</a>
+<a name="204"><span class="lineNum">     204 </span>            :     .io_write_way_mask_0</a>
+<a name="205"><span class="lineNum">     205 </span>            :       (~(io_update_pc[1]) &amp; updateWayMask_0 | io_update_pc[1] &amp; updateWayMask_2),</a>
+<a name="206"><span class="lineNum">     206 </span>            :     .io_write_way_mask_1</a>
+<a name="207"><span class="lineNum">     207 </span>            :       (~(io_update_pc[1]) &amp; updateWayMask_1 | io_update_pc[1] &amp; updateWayMask_3),</a>
+<a name="208"><span class="lineNum">     208 </span>            :     .io_hit              (_wrbypasses_0_io_hit),</a>
+<a name="209"><span class="lineNum">     209 </span>            :     .io_hit_data_0_valid (_wrbypasses_0_io_hit_data_0_valid),</a>
+<a name="210"><span class="lineNum">     210 </span>            :     .io_hit_data_0_bits  (_wrbypasses_0_io_hit_data_0_bits),</a>
+<a name="211"><span class="lineNum">     211 </span>            :     .io_hit_data_1_valid (_wrbypasses_0_io_hit_data_1_valid),</a>
+<a name="212"><span class="lineNum">     212 </span>            :     .io_hit_data_1_bits  (_wrbypasses_0_io_hit_data_1_bits)</a>
+<a name="213"><span class="lineNum">     213 </span>            :   );</a>
+<a name="214"><span class="lineNum">     214 </span>            :   WrBypass_33 wrbypasses_1 (</a>
+<a name="215"><span class="lineNum">     215 </span>            :     .clock               (clock),</a>
+<a name="216"><span class="lineNum">     216 </span>            :     .reset               (reset),</a>
+<a name="217"><span class="lineNum">     217 </span>            :     .io_wen              (io_update_mask_1),</a>
+<a name="218"><span class="lineNum">     218 </span>            :     .io_write_idx        (io_update_pc[8:1]),</a>
+<a name="219"><span class="lineNum">     219 </span>            :     .io_write_data_0     (_GEN_1 | _GEN_2),</a>
+<a name="220"><span class="lineNum">     220 </span>            :     .io_write_data_1     (_GEN_1 | _GEN_2),</a>
+<a name="221"><span class="lineNum">     221 </span>            :     .io_write_way_mask_0</a>
+<a name="222"><span class="lineNum">     222 </span>            :       (io_update_pc[1] &amp; updateWayMask_0 | ~(io_update_pc[1]) &amp; updateWayMask_2),</a>
+<a name="223"><span class="lineNum">     223 </span>            :     .io_write_way_mask_1</a>
+<a name="224"><span class="lineNum">     224 </span>            :       (io_update_pc[1] &amp; updateWayMask_1 | ~(io_update_pc[1]) &amp; updateWayMask_3),</a>
+<a name="225"><span class="lineNum">     225 </span>            :     .io_hit              (_wrbypasses_1_io_hit),</a>
+<a name="226"><span class="lineNum">     226 </span>            :     .io_hit_data_0_valid (_wrbypasses_1_io_hit_data_0_valid),</a>
+<a name="227"><span class="lineNum">     227 </span>            :     .io_hit_data_0_bits  (_wrbypasses_1_io_hit_data_0_bits),</a>
+<a name="228"><span class="lineNum">     228 </span>            :     .io_hit_data_1_valid (_wrbypasses_1_io_hit_data_1_valid),</a>
+<a name="229"><span class="lineNum">     229 </span>            :     .io_hit_data_1_bits  (_wrbypasses_1_io_hit_data_1_bits)</a>
+<a name="230"><span class="lineNum">     230 </span>            :   );</a>
+<a name="231"><span class="lineNum">     231 </span>            :   assign io_resp_ctrs_0_0 =</a>
+<a name="232"><span class="lineNum">     232 </span>            :     (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_0)</a>
+<a name="233"><span class="lineNum">     233 </span>            :     | (s1_pc[1] ? _table_io_r_resp_data_2 : 6'h0);</a>
+<a name="234"><span class="lineNum">     234 </span>            :   assign io_resp_ctrs_0_1 =</a>
+<a name="235"><span class="lineNum">     235 </span>            :     (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_1)</a>
+<a name="236"><span class="lineNum">     236 </span>            :     | (s1_pc[1] ? _table_io_r_resp_data_3 : 6'h0);</a>
+<a name="237"><span class="lineNum">     237 </span>            :   assign io_resp_ctrs_1_0 =</a>
+<a name="238"><span class="lineNum">     238 </span>            :     (s1_pc[1] ? _table_io_r_resp_data_0 : 6'h0)</a>
+<a name="239"><span class="lineNum">     239 </span>            :     | (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_2);</a>
+<a name="240"><span class="lineNum">     240 </span>            :   assign io_resp_ctrs_1_1 =</a>
+<a name="241"><span class="lineNum">     241 </span>            :     (s1_pc[1] ? _table_io_r_resp_data_1 : 6'h0)</a>
+<a name="242"><span class="lineNum">     242 </span>            :     | (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_3);</a>
+<a name="243"><span class="lineNum">     243 </span>            : endmodule</a>
+<a name="244"><span class="lineNum">     244 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SCTable_1.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SCTable_1.sv.func-sort-c.html
new file mode 100644
index 0000000..af82f50
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SCTable_1.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/SCTable_1.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - SCTable_1.sv<span style="font-size: 80%;"> (<a href="SCTable_1.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">37</td>
+            <td class="headerCovTableEntry">37</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="SCTable_1.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SCTable_1.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SCTable_1.sv.func.html
new file mode 100644
index 0000000..1905d48
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SCTable_1.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/SCTable_1.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - SCTable_1.sv<span style="font-size: 80%;"> (<a href="SCTable_1.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">37</td>
+            <td class="headerCovTableEntry">37</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="SCTable_1.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SCTable_1.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SCTable_1.sv.gcov.html
new file mode 100644
index 0000000..40566c0
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SCTable_1.sv.gcov.html
@@ -0,0 +1,326 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/SCTable_1.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - SCTable_1.sv<span style="font-size: 80%;"> (source / <a href="SCTable_1.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">37</td>
+            <td class="headerCovTableEntry">37</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : module SCTable_1(</a>
+<a name="59"><span class="lineNum">      59 </span><span class="lineCov">     127786 :   input         clock,</span></a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">         62 :   input         reset,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">         73 :   input         io_req_valid,</span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">      35066 :   input  [40:0] io_req_bits_pc,</span></a>
+<a name="63"><span class="lineNum">      63 </span><span class="lineCov">        474 :   input  [3:0]  io_req_bits_folded_hist_hist_12_folded_hist,</span></a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">        168 :   output [5:0]  io_resp_ctrs_0_0,</span></a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">        162 :   output [5:0]  io_resp_ctrs_0_1,</span></a>
+<a name="66"><span class="lineNum">      66 </span><span class="lineCov">        172 :   output [5:0]  io_resp_ctrs_1_0,</span></a>
+<a name="67"><span class="lineNum">      67 </span><span class="lineCov">        167 :   output [5:0]  io_resp_ctrs_1_1,</span></a>
+<a name="68"><span class="lineNum">      68 </span><span class="lineCov">        622 :   input  [40:0] io_update_pc,</span></a>
+<a name="69"><span class="lineNum">      69 </span><span class="lineCov">         56 :   input  [3:0]  io_update_folded_hist_hist_12_folded_hist,</span></a>
+<a name="70"><span class="lineNum">      70 </span><span class="lineCov">         31 :   input         io_update_mask_0,</span></a>
+<a name="71"><span class="lineNum">      71 </span><span class="lineCov">         32 :   input         io_update_mask_1,</span></a>
+<a name="72"><span class="lineNum">      72 </span><span class="lineCov">         87 :   input  [5:0]  io_update_oldCtrs_0,</span></a>
+<a name="73"><span class="lineNum">      73 </span><span class="lineCov">         97 :   input  [5:0]  io_update_oldCtrs_1,</span></a>
+<a name="74"><span class="lineNum">      74 </span><span class="lineCov">         13 :   input         io_update_tagePreds_0,</span></a>
+<a name="75"><span class="lineNum">      75 </span><span class="lineCov">         17 :   input         io_update_tagePreds_1,</span></a>
+<a name="76"><span class="lineNum">      76 </span><span class="lineCov">         18 :   input         io_update_takens_0,</span></a>
+<a name="77"><span class="lineNum">      77 </span><span class="lineCov">         16 :   input         io_update_takens_1</span></a>
+<a name="78"><span class="lineNum">      78 </span>            : );</a>
+<a name="79"><span class="lineNum">      79 </span>            : </a>
+<a name="80"><span class="lineNum">      80 </span>            :   wire        _wrbypasses_1_io_hit;</a>
+<a name="81"><span class="lineNum">      81 </span>            :   wire        _wrbypasses_1_io_hit_data_0_valid;</a>
+<a name="82"><span class="lineNum">      82 </span>            :   wire [5:0]  _wrbypasses_1_io_hit_data_0_bits;</a>
+<a name="83"><span class="lineNum">      83 </span>            :   wire        _wrbypasses_1_io_hit_data_1_valid;</a>
+<a name="84"><span class="lineNum">      84 </span>            :   wire [5:0]  _wrbypasses_1_io_hit_data_1_bits;</a>
+<a name="85"><span class="lineNum">      85 </span>            :   wire        _wrbypasses_0_io_hit;</a>
+<a name="86"><span class="lineNum">      86 </span>            :   wire        _wrbypasses_0_io_hit_data_0_valid;</a>
+<a name="87"><span class="lineNum">      87 </span>            :   wire [5:0]  _wrbypasses_0_io_hit_data_0_bits;</a>
+<a name="88"><span class="lineNum">      88 </span>            :   wire        _wrbypasses_0_io_hit_data_1_valid;</a>
+<a name="89"><span class="lineNum">      89 </span>            :   wire [5:0]  _wrbypasses_0_io_hit_data_1_bits;</a>
+<a name="90"><span class="lineNum">      90 </span>            :   wire [5:0]  _table_io_r_resp_data_0;</a>
+<a name="91"><span class="lineNum">      91 </span>            :   wire [5:0]  _table_io_r_resp_data_1;</a>
+<a name="92"><span class="lineNum">      92 </span>            :   wire [5:0]  _table_io_r_resp_data_2;</a>
+<a name="93"><span class="lineNum">      93 </span>            :   wire [5:0]  _table_io_r_resp_data_3;</a>
+<a name="94"><span class="lineNum">      94 </span><span class="lineCov">       9412 :   reg  [40:0] s1_pc;</span></a>
+<a name="95"><span class="lineNum">      95 </span><span class="lineCov">         29 :   wire        updateWayMask_0 =</span></a>
+<a name="96"><span class="lineNum">      96 </span>            :     io_update_mask_0 &amp; ~(io_update_pc[1]) &amp; ~io_update_tagePreds_0 | io_update_mask_1</a>
+<a name="97"><span class="lineNum">      97 </span>            :     &amp; io_update_pc[1] &amp; ~io_update_tagePreds_1;</a>
+<a name="98"><span class="lineNum">      98 </span><span class="lineCov">         17 :   wire        updateWayMask_1 =</span></a>
+<a name="99"><span class="lineNum">      99 </span>            :     io_update_mask_0 &amp; ~(io_update_pc[1]) &amp; io_update_tagePreds_0 | io_update_mask_1</a>
+<a name="100"><span class="lineNum">     100 </span>            :     &amp; io_update_pc[1] &amp; io_update_tagePreds_1;</a>
+<a name="101"><span class="lineNum">     101 </span><span class="lineCov">         27 :   wire        updateWayMask_2 =</span></a>
+<a name="102"><span class="lineNum">     102 </span>            :     io_update_mask_0 &amp; io_update_pc[1] &amp; ~io_update_tagePreds_0 | io_update_mask_1</a>
+<a name="103"><span class="lineNum">     103 </span>            :     &amp; ~(io_update_pc[1]) &amp; ~io_update_tagePreds_1;</a>
+<a name="104"><span class="lineNum">     104 </span><span class="lineCov">         23 :   wire        updateWayMask_3 =</span></a>
+<a name="105"><span class="lineNum">     105 </span>            :     io_update_mask_0 &amp; io_update_pc[1] &amp; io_update_tagePreds_0 | io_update_mask_1</a>
+<a name="106"><span class="lineNum">     106 </span>            :     &amp; ~(io_update_pc[1]) &amp; io_update_tagePreds_1;</a>
+<a name="107"><span class="lineNum">     107 </span><span class="lineCov">        121 :   wire [7:0]  update_idx =</span></a>
+<a name="108"><span class="lineNum">     108 </span>            :     {io_update_pc[8:5], io_update_pc[4:1] ^ io_update_folded_hist_hist_12_folded_hist};</a>
+<a name="109"><span class="lineNum">     109 </span><span class="lineCov">         16 :   wire        ctrPos =</span></a>
+<a name="110"><span class="lineNum">     110 </span>            :     ~(io_update_pc[1]) &amp; io_update_tagePreds_0 | io_update_pc[1] &amp; io_update_tagePreds_1;</a>
+<a name="111"><span class="lineNum">     111 </span><span class="lineCov">        103 :   wire [5:0]  oldCtr =</span></a>
+<a name="112"><span class="lineNum">     112 </span>            :     (~(io_update_pc[1]) &amp; _wrbypasses_0_io_hit | io_update_pc[1] &amp; _wrbypasses_1_io_hit)</a>
+<a name="113"><span class="lineNum">     113 </span>            :     &amp; (ctrPos</a>
+<a name="114"><span class="lineNum">     114 </span>            :          ? ~(io_update_pc[1]) &amp; _wrbypasses_0_io_hit_data_1_valid | io_update_pc[1]</a>
+<a name="115"><span class="lineNum">     115 </span>            :            &amp; _wrbypasses_1_io_hit_data_1_valid</a>
+<a name="116"><span class="lineNum">     116 </span>            :          : ~(io_update_pc[1]) &amp; _wrbypasses_0_io_hit_data_0_valid | io_update_pc[1]</a>
+<a name="117"><span class="lineNum">     117 </span>            :            &amp; _wrbypasses_1_io_hit_data_0_valid)</a>
+<a name="118"><span class="lineNum">     118 </span>            :       ? (ctrPos</a>
+<a name="119"><span class="lineNum">     119 </span>            :            ? (io_update_pc[1] ? 6'h0 : _wrbypasses_0_io_hit_data_1_bits)</a>
+<a name="120"><span class="lineNum">     120 </span>            :              | (io_update_pc[1] ? _wrbypasses_1_io_hit_data_1_bits : 6'h0)</a>
+<a name="121"><span class="lineNum">     121 </span>            :            : (io_update_pc[1] ? 6'h0 : _wrbypasses_0_io_hit_data_0_bits)</a>
+<a name="122"><span class="lineNum">     122 </span>            :              | (io_update_pc[1] ? _wrbypasses_1_io_hit_data_0_bits : 6'h0))</a>
+<a name="123"><span class="lineNum">     123 </span>            :       : (io_update_pc[1] ? 6'h0 : io_update_oldCtrs_0)</a>
+<a name="124"><span class="lineNum">     124 </span>            :         | (io_update_pc[1] ? io_update_oldCtrs_1 : 6'h0);</a>
+<a name="125"><span class="lineNum">     125 </span><span class="lineCov">         13 :   wire        taken =</span></a>
+<a name="126"><span class="lineNum">     126 </span>            :     ~(io_update_pc[1]) &amp; io_update_takens_0 | io_update_pc[1] &amp; io_update_takens_1;</a>
+<a name="127"><span class="lineNum">     127 </span><span class="lineCov">        127 :   wire [5:0]  update_wdata_0 =</span></a>
+<a name="128"><span class="lineNum">     128 </span>            :     oldCtr == 6'h1F &amp; taken</a>
+<a name="129"><span class="lineNum">     129 </span>            :       ? 6'h1F</a>
+<a name="130"><span class="lineNum">     130 </span>            :       : oldCtr == 6'h20 &amp; ~taken ? 6'h20 : taken ? 6'(oldCtr + 6'h1) : 6'(oldCtr - 6'h1);</a>
+<a name="131"><span class="lineNum">     131 </span><span class="lineCov">         15 :   wire        ctrPos_1 =</span></a>
+<a name="132"><span class="lineNum">     132 </span>            :     io_update_pc[1] &amp; io_update_tagePreds_0 | ~(io_update_pc[1]) &amp; io_update_tagePreds_1;</a>
+<a name="133"><span class="lineNum">     133 </span><span class="lineCov">        110 :   wire [5:0]  oldCtr_1 =</span></a>
+<a name="134"><span class="lineNum">     134 </span>            :     (io_update_pc[1] &amp; _wrbypasses_0_io_hit | ~(io_update_pc[1]) &amp; _wrbypasses_1_io_hit)</a>
+<a name="135"><span class="lineNum">     135 </span>            :     &amp; (ctrPos_1</a>
+<a name="136"><span class="lineNum">     136 </span>            :          ? io_update_pc[1] &amp; _wrbypasses_0_io_hit_data_1_valid | ~(io_update_pc[1])</a>
+<a name="137"><span class="lineNum">     137 </span>            :            &amp; _wrbypasses_1_io_hit_data_1_valid</a>
+<a name="138"><span class="lineNum">     138 </span>            :          : io_update_pc[1] &amp; _wrbypasses_0_io_hit_data_0_valid | ~(io_update_pc[1])</a>
+<a name="139"><span class="lineNum">     139 </span>            :            &amp; _wrbypasses_1_io_hit_data_0_valid)</a>
+<a name="140"><span class="lineNum">     140 </span>            :       ? (ctrPos_1</a>
+<a name="141"><span class="lineNum">     141 </span>            :            ? (io_update_pc[1] ? _wrbypasses_0_io_hit_data_1_bits : 6'h0)</a>
+<a name="142"><span class="lineNum">     142 </span>            :              | (io_update_pc[1] ? 6'h0 : _wrbypasses_1_io_hit_data_1_bits)</a>
+<a name="143"><span class="lineNum">     143 </span>            :            : (io_update_pc[1] ? _wrbypasses_0_io_hit_data_0_bits : 6'h0)</a>
+<a name="144"><span class="lineNum">     144 </span>            :              | (io_update_pc[1] ? 6'h0 : _wrbypasses_1_io_hit_data_0_bits))</a>
+<a name="145"><span class="lineNum">     145 </span>            :       : (io_update_pc[1] ? io_update_oldCtrs_0 : 6'h0)</a>
+<a name="146"><span class="lineNum">     146 </span>            :         | (io_update_pc[1] ? 6'h0 : io_update_oldCtrs_1);</a>
+<a name="147"><span class="lineNum">     147 </span><span class="lineCov">         17 :   wire        taken_1 =</span></a>
+<a name="148"><span class="lineNum">     148 </span>            :     io_update_pc[1] &amp; io_update_takens_0 | ~(io_update_pc[1]) &amp; io_update_takens_1;</a>
+<a name="149"><span class="lineNum">     149 </span><span class="lineCov">        123 :   wire [5:0]  update_wdata_1 =</span></a>
+<a name="150"><span class="lineNum">     150 </span>            :     oldCtr_1 == 6'h1F &amp; taken_1</a>
+<a name="151"><span class="lineNum">     151 </span>            :       ? 6'h1F</a>
+<a name="152"><span class="lineNum">     152 </span>            :       : oldCtr_1 == 6'h20 &amp; ~taken_1</a>
+<a name="153"><span class="lineNum">     153 </span>            :           ? 6'h20</a>
+<a name="154"><span class="lineNum">     154 </span>            :           : taken_1 ? 6'(oldCtr_1 + 6'h1) : 6'(oldCtr_1 - 6'h1);</a>
+<a name="155"><span class="lineNum">     155 </span>            :   wire [5:0]  _GEN = io_update_pc[1] ? 6'h0 : update_wdata_0;</a>
+<a name="156"><span class="lineNum">     156 </span>            :   wire [5:0]  _GEN_0 = io_update_pc[1] ? update_wdata_1 : 6'h0;</a>
+<a name="157"><span class="lineNum">     157 </span>            :   wire [5:0]  _GEN_1 = io_update_pc[1] ? update_wdata_0 : 6'h0;</a>
+<a name="158"><span class="lineNum">     158 </span>            :   wire [5:0]  _GEN_2 = io_update_pc[1] ? 6'h0 : update_wdata_1;</a>
+<a name="159"><span class="lineNum">     159 </span><span class="lineCov">     127694 :   always @(posedge clock) begin</span></a>
+<a name="160"><span class="lineNum">     160 </span><span class="lineCov">       8350 :     if (io_req_valid)</span></a>
+<a name="161"><span class="lineNum">     161 </span><span class="lineCov">       4175 :       s1_pc &lt;= io_req_bits_pc;</span></a>
+<a name="162"><span class="lineNum">     162 </span>            :   end // always @(posedge)</a>
+<a name="163"><span class="lineNum">     163 </span>            :   `ifdef ENABLE_INITIAL_REG_</a>
+<a name="164"><span class="lineNum">     164 </span>            :     `ifdef FIRRTL_BEFORE_INITIAL</a>
+<a name="165"><span class="lineNum">     165 </span>            :       `FIRRTL_BEFORE_INITIAL</a>
+<a name="166"><span class="lineNum">     166 </span>            :     `endif // FIRRTL_BEFORE_INITIAL</a>
+<a name="167"><span class="lineNum">     167 </span>            :     logic [31:0] _RANDOM[0:1];</a>
+<a name="168"><span class="lineNum">     168 </span><span class="lineCov">         58 :     initial begin</span></a>
+<a name="169"><span class="lineNum">     169 </span>            :       `ifdef INIT_RANDOM_PROLOG_</a>
+<a name="170"><span class="lineNum">     170 </span>            :         `INIT_RANDOM_PROLOG_</a>
+<a name="171"><span class="lineNum">     171 </span>            :       `endif // INIT_RANDOM_PROLOG_</a>
+<a name="172"><span class="lineNum">     172 </span>            :       `ifdef RANDOMIZE_REG_INIT</a>
+<a name="173"><span class="lineNum">     173 </span>            :         for (logic [1:0] i = 2'h0; i &lt; 2'h2; i += 2'h1) begin</a>
+<a name="174"><span class="lineNum">     174 </span>            :           _RANDOM[i[0]] = `RANDOM;</a>
+<a name="175"><span class="lineNum">     175 </span>            :         end</a>
+<a name="176"><span class="lineNum">     176 </span>            :         s1_pc = {_RANDOM[1'h0][31:8], _RANDOM[1'h1][16:0]};</a>
+<a name="177"><span class="lineNum">     177 </span>            :       `endif // RANDOMIZE_REG_INIT</a>
+<a name="178"><span class="lineNum">     178 </span>            :     end // initial</a>
+<a name="179"><span class="lineNum">     179 </span>            :     `ifdef FIRRTL_AFTER_INITIAL</a>
+<a name="180"><span class="lineNum">     180 </span>            :       `FIRRTL_AFTER_INITIAL</a>
+<a name="181"><span class="lineNum">     181 </span>            :     `endif // FIRRTL_AFTER_INITIAL</a>
+<a name="182"><span class="lineNum">     182 </span>            :   `endif // ENABLE_INITIAL_REG_</a>
+<a name="183"><span class="lineNum">     183 </span>            :   SRAMTemplate_35 table_0 (</a>
+<a name="184"><span class="lineNum">     184 </span>            :     .clock                 (clock),</a>
+<a name="185"><span class="lineNum">     185 </span>            :     .reset                 (reset),</a>
+<a name="186"><span class="lineNum">     186 </span>            :     .io_r_req_valid        (io_req_valid),</a>
+<a name="187"><span class="lineNum">     187 </span>            :     .io_r_req_bits_setIdx</a>
+<a name="188"><span class="lineNum">     188 </span>            :       ({io_req_bits_pc[8:5],</a>
+<a name="189"><span class="lineNum">     189 </span>            :         io_req_bits_pc[4:1] ^ io_req_bits_folded_hist_hist_12_folded_hist}),</a>
+<a name="190"><span class="lineNum">     190 </span>            :     .io_r_resp_data_0      (_table_io_r_resp_data_0),</a>
+<a name="191"><span class="lineNum">     191 </span>            :     .io_r_resp_data_1      (_table_io_r_resp_data_1),</a>
+<a name="192"><span class="lineNum">     192 </span>            :     .io_r_resp_data_2      (_table_io_r_resp_data_2),</a>
+<a name="193"><span class="lineNum">     193 </span>            :     .io_r_resp_data_3      (_table_io_r_resp_data_3),</a>
+<a name="194"><span class="lineNum">     194 </span>            :     .io_w_req_valid        (io_update_mask_0 | io_update_mask_1),</a>
+<a name="195"><span class="lineNum">     195 </span>            :     .io_w_req_bits_setIdx  (update_idx),</a>
+<a name="196"><span class="lineNum">     196 </span>            :     .io_w_req_bits_data_0  (update_wdata_0),</a>
+<a name="197"><span class="lineNum">     197 </span>            :     .io_w_req_bits_data_1  (update_wdata_0),</a>
+<a name="198"><span class="lineNum">     198 </span>            :     .io_w_req_bits_data_2  (update_wdata_1),</a>
+<a name="199"><span class="lineNum">     199 </span>            :     .io_w_req_bits_data_3  (update_wdata_1),</a>
+<a name="200"><span class="lineNum">     200 </span>            :     .io_w_req_bits_waymask</a>
+<a name="201"><span class="lineNum">     201 </span>            :       ({updateWayMask_3, updateWayMask_2, updateWayMask_1, updateWayMask_0})</a>
+<a name="202"><span class="lineNum">     202 </span>            :   );</a>
+<a name="203"><span class="lineNum">     203 </span>            :   WrBypass_33 wrbypasses_0 (</a>
+<a name="204"><span class="lineNum">     204 </span>            :     .clock               (clock),</a>
+<a name="205"><span class="lineNum">     205 </span>            :     .reset               (reset),</a>
+<a name="206"><span class="lineNum">     206 </span>            :     .io_wen              (io_update_mask_0),</a>
+<a name="207"><span class="lineNum">     207 </span>            :     .io_write_idx        (update_idx),</a>
+<a name="208"><span class="lineNum">     208 </span>            :     .io_write_data_0     (_GEN | _GEN_0),</a>
+<a name="209"><span class="lineNum">     209 </span>            :     .io_write_data_1     (_GEN | _GEN_0),</a>
+<a name="210"><span class="lineNum">     210 </span>            :     .io_write_way_mask_0</a>
+<a name="211"><span class="lineNum">     211 </span>            :       (~(io_update_pc[1]) &amp; updateWayMask_0 | io_update_pc[1] &amp; updateWayMask_2),</a>
+<a name="212"><span class="lineNum">     212 </span>            :     .io_write_way_mask_1</a>
+<a name="213"><span class="lineNum">     213 </span>            :       (~(io_update_pc[1]) &amp; updateWayMask_1 | io_update_pc[1] &amp; updateWayMask_3),</a>
+<a name="214"><span class="lineNum">     214 </span>            :     .io_hit              (_wrbypasses_0_io_hit),</a>
+<a name="215"><span class="lineNum">     215 </span>            :     .io_hit_data_0_valid (_wrbypasses_0_io_hit_data_0_valid),</a>
+<a name="216"><span class="lineNum">     216 </span>            :     .io_hit_data_0_bits  (_wrbypasses_0_io_hit_data_0_bits),</a>
+<a name="217"><span class="lineNum">     217 </span>            :     .io_hit_data_1_valid (_wrbypasses_0_io_hit_data_1_valid),</a>
+<a name="218"><span class="lineNum">     218 </span>            :     .io_hit_data_1_bits  (_wrbypasses_0_io_hit_data_1_bits)</a>
+<a name="219"><span class="lineNum">     219 </span>            :   );</a>
+<a name="220"><span class="lineNum">     220 </span>            :   WrBypass_33 wrbypasses_1 (</a>
+<a name="221"><span class="lineNum">     221 </span>            :     .clock               (clock),</a>
+<a name="222"><span class="lineNum">     222 </span>            :     .reset               (reset),</a>
+<a name="223"><span class="lineNum">     223 </span>            :     .io_wen              (io_update_mask_1),</a>
+<a name="224"><span class="lineNum">     224 </span>            :     .io_write_idx        (update_idx),</a>
+<a name="225"><span class="lineNum">     225 </span>            :     .io_write_data_0     (_GEN_1 | _GEN_2),</a>
+<a name="226"><span class="lineNum">     226 </span>            :     .io_write_data_1     (_GEN_1 | _GEN_2),</a>
+<a name="227"><span class="lineNum">     227 </span>            :     .io_write_way_mask_0</a>
+<a name="228"><span class="lineNum">     228 </span>            :       (io_update_pc[1] &amp; updateWayMask_0 | ~(io_update_pc[1]) &amp; updateWayMask_2),</a>
+<a name="229"><span class="lineNum">     229 </span>            :     .io_write_way_mask_1</a>
+<a name="230"><span class="lineNum">     230 </span>            :       (io_update_pc[1] &amp; updateWayMask_1 | ~(io_update_pc[1]) &amp; updateWayMask_3),</a>
+<a name="231"><span class="lineNum">     231 </span>            :     .io_hit              (_wrbypasses_1_io_hit),</a>
+<a name="232"><span class="lineNum">     232 </span>            :     .io_hit_data_0_valid (_wrbypasses_1_io_hit_data_0_valid),</a>
+<a name="233"><span class="lineNum">     233 </span>            :     .io_hit_data_0_bits  (_wrbypasses_1_io_hit_data_0_bits),</a>
+<a name="234"><span class="lineNum">     234 </span>            :     .io_hit_data_1_valid (_wrbypasses_1_io_hit_data_1_valid),</a>
+<a name="235"><span class="lineNum">     235 </span>            :     .io_hit_data_1_bits  (_wrbypasses_1_io_hit_data_1_bits)</a>
+<a name="236"><span class="lineNum">     236 </span>            :   );</a>
+<a name="237"><span class="lineNum">     237 </span>            :   assign io_resp_ctrs_0_0 =</a>
+<a name="238"><span class="lineNum">     238 </span>            :     (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_0)</a>
+<a name="239"><span class="lineNum">     239 </span>            :     | (s1_pc[1] ? _table_io_r_resp_data_2 : 6'h0);</a>
+<a name="240"><span class="lineNum">     240 </span>            :   assign io_resp_ctrs_0_1 =</a>
+<a name="241"><span class="lineNum">     241 </span>            :     (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_1)</a>
+<a name="242"><span class="lineNum">     242 </span>            :     | (s1_pc[1] ? _table_io_r_resp_data_3 : 6'h0);</a>
+<a name="243"><span class="lineNum">     243 </span>            :   assign io_resp_ctrs_1_0 =</a>
+<a name="244"><span class="lineNum">     244 </span>            :     (s1_pc[1] ? _table_io_r_resp_data_0 : 6'h0)</a>
+<a name="245"><span class="lineNum">     245 </span>            :     | (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_2);</a>
+<a name="246"><span class="lineNum">     246 </span>            :   assign io_resp_ctrs_1_1 =</a>
+<a name="247"><span class="lineNum">     247 </span>            :     (s1_pc[1] ? _table_io_r_resp_data_1 : 6'h0)</a>
+<a name="248"><span class="lineNum">     248 </span>            :     | (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_3);</a>
+<a name="249"><span class="lineNum">     249 </span>            : endmodule</a>
+<a name="250"><span class="lineNum">     250 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SCTable_2.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SCTable_2.sv.func-sort-c.html
new file mode 100644
index 0000000..0a4ca74
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SCTable_2.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/SCTable_2.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - SCTable_2.sv<span style="font-size: 80%;"> (<a href="SCTable_2.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">37</td>
+            <td class="headerCovTableEntry">37</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="SCTable_2.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SCTable_2.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SCTable_2.sv.func.html
new file mode 100644
index 0000000..3bf36fb
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SCTable_2.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/SCTable_2.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - SCTable_2.sv<span style="font-size: 80%;"> (<a href="SCTable_2.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">37</td>
+            <td class="headerCovTableEntry">37</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="SCTable_2.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SCTable_2.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SCTable_2.sv.gcov.html
new file mode 100644
index 0000000..f649eba
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SCTable_2.sv.gcov.html
@@ -0,0 +1,324 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/SCTable_2.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - SCTable_2.sv<span style="font-size: 80%;"> (source / <a href="SCTable_2.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">37</td>
+            <td class="headerCovTableEntry">37</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : module SCTable_2(</a>
+<a name="59"><span class="lineNum">      59 </span><span class="lineCov">     127786 :   input         clock,</span></a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">         62 :   input         reset,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">         73 :   input         io_req_valid,</span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">      35066 :   input  [40:0] io_req_bits_pc,</span></a>
+<a name="63"><span class="lineNum">      63 </span><span class="lineCov">        858 :   input  [7:0]  io_req_bits_folded_hist_hist_11_folded_hist,</span></a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">        172 :   output [5:0]  io_resp_ctrs_0_0,</span></a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">        159 :   output [5:0]  io_resp_ctrs_0_1,</span></a>
+<a name="66"><span class="lineNum">      66 </span><span class="lineCov">        181 :   output [5:0]  io_resp_ctrs_1_0,</span></a>
+<a name="67"><span class="lineNum">      67 </span><span class="lineCov">        181 :   output [5:0]  io_resp_ctrs_1_1,</span></a>
+<a name="68"><span class="lineNum">      68 </span><span class="lineCov">        648 :   input  [40:0] io_update_pc,</span></a>
+<a name="69"><span class="lineNum">      69 </span><span class="lineCov">        123 :   input  [7:0]  io_update_folded_hist_hist_11_folded_hist,</span></a>
+<a name="70"><span class="lineNum">      70 </span><span class="lineCov">         31 :   input         io_update_mask_0,</span></a>
+<a name="71"><span class="lineNum">      71 </span><span class="lineCov">         34 :   input         io_update_mask_1,</span></a>
+<a name="72"><span class="lineNum">      72 </span><span class="lineCov">         96 :   input  [5:0]  io_update_oldCtrs_0,</span></a>
+<a name="73"><span class="lineNum">      73 </span><span class="lineCov">         79 :   input  [5:0]  io_update_oldCtrs_1,</span></a>
+<a name="74"><span class="lineNum">      74 </span><span class="lineCov">         15 :   input         io_update_tagePreds_0,</span></a>
+<a name="75"><span class="lineNum">      75 </span><span class="lineCov">         16 :   input         io_update_tagePreds_1,</span></a>
+<a name="76"><span class="lineNum">      76 </span><span class="lineCov">         18 :   input         io_update_takens_0,</span></a>
+<a name="77"><span class="lineNum">      77 </span><span class="lineCov">         19 :   input         io_update_takens_1</span></a>
+<a name="78"><span class="lineNum">      78 </span>            : );</a>
+<a name="79"><span class="lineNum">      79 </span>            : </a>
+<a name="80"><span class="lineNum">      80 </span>            :   wire        _wrbypasses_1_io_hit;</a>
+<a name="81"><span class="lineNum">      81 </span>            :   wire        _wrbypasses_1_io_hit_data_0_valid;</a>
+<a name="82"><span class="lineNum">      82 </span>            :   wire [5:0]  _wrbypasses_1_io_hit_data_0_bits;</a>
+<a name="83"><span class="lineNum">      83 </span>            :   wire        _wrbypasses_1_io_hit_data_1_valid;</a>
+<a name="84"><span class="lineNum">      84 </span>            :   wire [5:0]  _wrbypasses_1_io_hit_data_1_bits;</a>
+<a name="85"><span class="lineNum">      85 </span>            :   wire        _wrbypasses_0_io_hit;</a>
+<a name="86"><span class="lineNum">      86 </span>            :   wire        _wrbypasses_0_io_hit_data_0_valid;</a>
+<a name="87"><span class="lineNum">      87 </span>            :   wire [5:0]  _wrbypasses_0_io_hit_data_0_bits;</a>
+<a name="88"><span class="lineNum">      88 </span>            :   wire        _wrbypasses_0_io_hit_data_1_valid;</a>
+<a name="89"><span class="lineNum">      89 </span>            :   wire [5:0]  _wrbypasses_0_io_hit_data_1_bits;</a>
+<a name="90"><span class="lineNum">      90 </span>            :   wire [5:0]  _table_io_r_resp_data_0;</a>
+<a name="91"><span class="lineNum">      91 </span>            :   wire [5:0]  _table_io_r_resp_data_1;</a>
+<a name="92"><span class="lineNum">      92 </span>            :   wire [5:0]  _table_io_r_resp_data_2;</a>
+<a name="93"><span class="lineNum">      93 </span>            :   wire [5:0]  _table_io_r_resp_data_3;</a>
+<a name="94"><span class="lineNum">      94 </span><span class="lineCov">       9377 :   reg  [40:0] s1_pc;</span></a>
+<a name="95"><span class="lineNum">      95 </span><span class="lineCov">         18 :   wire        updateWayMask_0 =</span></a>
+<a name="96"><span class="lineNum">      96 </span>            :     io_update_mask_0 &amp; ~(io_update_pc[1]) &amp; ~io_update_tagePreds_0 | io_update_mask_1</a>
+<a name="97"><span class="lineNum">      97 </span>            :     &amp; io_update_pc[1] &amp; ~io_update_tagePreds_1;</a>
+<a name="98"><span class="lineNum">      98 </span><span class="lineCov">         23 :   wire        updateWayMask_1 =</span></a>
+<a name="99"><span class="lineNum">      99 </span>            :     io_update_mask_0 &amp; ~(io_update_pc[1]) &amp; io_update_tagePreds_0 | io_update_mask_1</a>
+<a name="100"><span class="lineNum">     100 </span>            :     &amp; io_update_pc[1] &amp; io_update_tagePreds_1;</a>
+<a name="101"><span class="lineNum">     101 </span><span class="lineCov">         24 :   wire        updateWayMask_2 =</span></a>
+<a name="102"><span class="lineNum">     102 </span>            :     io_update_mask_0 &amp; io_update_pc[1] &amp; ~io_update_tagePreds_0 | io_update_mask_1</a>
+<a name="103"><span class="lineNum">     103 </span>            :     &amp; ~(io_update_pc[1]) &amp; ~io_update_tagePreds_1;</a>
+<a name="104"><span class="lineNum">     104 </span><span class="lineCov">         23 :   wire        updateWayMask_3 =</span></a>
+<a name="105"><span class="lineNum">     105 </span>            :     io_update_mask_0 &amp; io_update_pc[1] &amp; io_update_tagePreds_0 | io_update_mask_1</a>
+<a name="106"><span class="lineNum">     106 </span>            :     &amp; ~(io_update_pc[1]) &amp; io_update_tagePreds_1;</a>
+<a name="107"><span class="lineNum">     107 </span><span class="lineCov">        118 :   wire [7:0]  update_idx = io_update_pc[8:1] ^ io_update_folded_hist_hist_11_folded_hist;</span></a>
+<a name="108"><span class="lineNum">     108 </span><span class="lineCov">         12 :   wire        ctrPos =</span></a>
+<a name="109"><span class="lineNum">     109 </span>            :     ~(io_update_pc[1]) &amp; io_update_tagePreds_0 | io_update_pc[1] &amp; io_update_tagePreds_1;</a>
+<a name="110"><span class="lineNum">     110 </span><span class="lineCov">        145 :   wire [5:0]  oldCtr =</span></a>
+<a name="111"><span class="lineNum">     111 </span>            :     (~(io_update_pc[1]) &amp; _wrbypasses_0_io_hit | io_update_pc[1] &amp; _wrbypasses_1_io_hit)</a>
+<a name="112"><span class="lineNum">     112 </span>            :     &amp; (ctrPos</a>
+<a name="113"><span class="lineNum">     113 </span>            :          ? ~(io_update_pc[1]) &amp; _wrbypasses_0_io_hit_data_1_valid | io_update_pc[1]</a>
+<a name="114"><span class="lineNum">     114 </span>            :            &amp; _wrbypasses_1_io_hit_data_1_valid</a>
+<a name="115"><span class="lineNum">     115 </span>            :          : ~(io_update_pc[1]) &amp; _wrbypasses_0_io_hit_data_0_valid | io_update_pc[1]</a>
+<a name="116"><span class="lineNum">     116 </span>            :            &amp; _wrbypasses_1_io_hit_data_0_valid)</a>
+<a name="117"><span class="lineNum">     117 </span>            :       ? (ctrPos</a>
+<a name="118"><span class="lineNum">     118 </span>            :            ? (io_update_pc[1] ? 6'h0 : _wrbypasses_0_io_hit_data_1_bits)</a>
+<a name="119"><span class="lineNum">     119 </span>            :              | (io_update_pc[1] ? _wrbypasses_1_io_hit_data_1_bits : 6'h0)</a>
+<a name="120"><span class="lineNum">     120 </span>            :            : (io_update_pc[1] ? 6'h0 : _wrbypasses_0_io_hit_data_0_bits)</a>
+<a name="121"><span class="lineNum">     121 </span>            :              | (io_update_pc[1] ? _wrbypasses_1_io_hit_data_0_bits : 6'h0))</a>
+<a name="122"><span class="lineNum">     122 </span>            :       : (io_update_pc[1] ? 6'h0 : io_update_oldCtrs_0)</a>
+<a name="123"><span class="lineNum">     123 </span>            :         | (io_update_pc[1] ? io_update_oldCtrs_1 : 6'h0);</a>
+<a name="124"><span class="lineNum">     124 </span><span class="lineCov">         19 :   wire        taken =</span></a>
+<a name="125"><span class="lineNum">     125 </span>            :     ~(io_update_pc[1]) &amp; io_update_takens_0 | io_update_pc[1] &amp; io_update_takens_1;</a>
+<a name="126"><span class="lineNum">     126 </span><span class="lineCov">        135 :   wire [5:0]  update_wdata_0 =</span></a>
+<a name="127"><span class="lineNum">     127 </span>            :     oldCtr == 6'h1F &amp; taken</a>
+<a name="128"><span class="lineNum">     128 </span>            :       ? 6'h1F</a>
+<a name="129"><span class="lineNum">     129 </span>            :       : oldCtr == 6'h20 &amp; ~taken ? 6'h20 : taken ? 6'(oldCtr + 6'h1) : 6'(oldCtr - 6'h1);</a>
+<a name="130"><span class="lineNum">     130 </span><span class="lineCov">         15 :   wire        ctrPos_1 =</span></a>
+<a name="131"><span class="lineNum">     131 </span>            :     io_update_pc[1] &amp; io_update_tagePreds_0 | ~(io_update_pc[1]) &amp; io_update_tagePreds_1;</a>
+<a name="132"><span class="lineNum">     132 </span><span class="lineCov">        133 :   wire [5:0]  oldCtr_1 =</span></a>
+<a name="133"><span class="lineNum">     133 </span>            :     (io_update_pc[1] &amp; _wrbypasses_0_io_hit | ~(io_update_pc[1]) &amp; _wrbypasses_1_io_hit)</a>
+<a name="134"><span class="lineNum">     134 </span>            :     &amp; (ctrPos_1</a>
+<a name="135"><span class="lineNum">     135 </span>            :          ? io_update_pc[1] &amp; _wrbypasses_0_io_hit_data_1_valid | ~(io_update_pc[1])</a>
+<a name="136"><span class="lineNum">     136 </span>            :            &amp; _wrbypasses_1_io_hit_data_1_valid</a>
+<a name="137"><span class="lineNum">     137 </span>            :          : io_update_pc[1] &amp; _wrbypasses_0_io_hit_data_0_valid | ~(io_update_pc[1])</a>
+<a name="138"><span class="lineNum">     138 </span>            :            &amp; _wrbypasses_1_io_hit_data_0_valid)</a>
+<a name="139"><span class="lineNum">     139 </span>            :       ? (ctrPos_1</a>
+<a name="140"><span class="lineNum">     140 </span>            :            ? (io_update_pc[1] ? _wrbypasses_0_io_hit_data_1_bits : 6'h0)</a>
+<a name="141"><span class="lineNum">     141 </span>            :              | (io_update_pc[1] ? 6'h0 : _wrbypasses_1_io_hit_data_1_bits)</a>
+<a name="142"><span class="lineNum">     142 </span>            :            : (io_update_pc[1] ? _wrbypasses_0_io_hit_data_0_bits : 6'h0)</a>
+<a name="143"><span class="lineNum">     143 </span>            :              | (io_update_pc[1] ? 6'h0 : _wrbypasses_1_io_hit_data_0_bits))</a>
+<a name="144"><span class="lineNum">     144 </span>            :       : (io_update_pc[1] ? io_update_oldCtrs_0 : 6'h0)</a>
+<a name="145"><span class="lineNum">     145 </span>            :         | (io_update_pc[1] ? 6'h0 : io_update_oldCtrs_1);</a>
+<a name="146"><span class="lineNum">     146 </span><span class="lineCov">         18 :   wire        taken_1 =</span></a>
+<a name="147"><span class="lineNum">     147 </span>            :     io_update_pc[1] &amp; io_update_takens_0 | ~(io_update_pc[1]) &amp; io_update_takens_1;</a>
+<a name="148"><span class="lineNum">     148 </span><span class="lineCov">        136 :   wire [5:0]  update_wdata_1 =</span></a>
+<a name="149"><span class="lineNum">     149 </span>            :     oldCtr_1 == 6'h1F &amp; taken_1</a>
+<a name="150"><span class="lineNum">     150 </span>            :       ? 6'h1F</a>
+<a name="151"><span class="lineNum">     151 </span>            :       : oldCtr_1 == 6'h20 &amp; ~taken_1</a>
+<a name="152"><span class="lineNum">     152 </span>            :           ? 6'h20</a>
+<a name="153"><span class="lineNum">     153 </span>            :           : taken_1 ? 6'(oldCtr_1 + 6'h1) : 6'(oldCtr_1 - 6'h1);</a>
+<a name="154"><span class="lineNum">     154 </span>            :   wire [5:0]  _GEN = io_update_pc[1] ? 6'h0 : update_wdata_0;</a>
+<a name="155"><span class="lineNum">     155 </span>            :   wire [5:0]  _GEN_0 = io_update_pc[1] ? update_wdata_1 : 6'h0;</a>
+<a name="156"><span class="lineNum">     156 </span>            :   wire [5:0]  _GEN_1 = io_update_pc[1] ? update_wdata_0 : 6'h0;</a>
+<a name="157"><span class="lineNum">     157 </span>            :   wire [5:0]  _GEN_2 = io_update_pc[1] ? 6'h0 : update_wdata_1;</a>
+<a name="158"><span class="lineNum">     158 </span><span class="lineCov">     127694 :   always @(posedge clock) begin</span></a>
+<a name="159"><span class="lineNum">     159 </span><span class="lineCov">       8350 :     if (io_req_valid)</span></a>
+<a name="160"><span class="lineNum">     160 </span><span class="lineCov">       4175 :       s1_pc &lt;= io_req_bits_pc;</span></a>
+<a name="161"><span class="lineNum">     161 </span>            :   end // always @(posedge)</a>
+<a name="162"><span class="lineNum">     162 </span>            :   `ifdef ENABLE_INITIAL_REG_</a>
+<a name="163"><span class="lineNum">     163 </span>            :     `ifdef FIRRTL_BEFORE_INITIAL</a>
+<a name="164"><span class="lineNum">     164 </span>            :       `FIRRTL_BEFORE_INITIAL</a>
+<a name="165"><span class="lineNum">     165 </span>            :     `endif // FIRRTL_BEFORE_INITIAL</a>
+<a name="166"><span class="lineNum">     166 </span>            :     logic [31:0] _RANDOM[0:1];</a>
+<a name="167"><span class="lineNum">     167 </span><span class="lineCov">         58 :     initial begin</span></a>
+<a name="168"><span class="lineNum">     168 </span>            :       `ifdef INIT_RANDOM_PROLOG_</a>
+<a name="169"><span class="lineNum">     169 </span>            :         `INIT_RANDOM_PROLOG_</a>
+<a name="170"><span class="lineNum">     170 </span>            :       `endif // INIT_RANDOM_PROLOG_</a>
+<a name="171"><span class="lineNum">     171 </span>            :       `ifdef RANDOMIZE_REG_INIT</a>
+<a name="172"><span class="lineNum">     172 </span>            :         for (logic [1:0] i = 2'h0; i &lt; 2'h2; i += 2'h1) begin</a>
+<a name="173"><span class="lineNum">     173 </span>            :           _RANDOM[i[0]] = `RANDOM;</a>
+<a name="174"><span class="lineNum">     174 </span>            :         end</a>
+<a name="175"><span class="lineNum">     175 </span>            :         s1_pc = {_RANDOM[1'h0][31:8], _RANDOM[1'h1][16:0]};</a>
+<a name="176"><span class="lineNum">     176 </span>            :       `endif // RANDOMIZE_REG_INIT</a>
+<a name="177"><span class="lineNum">     177 </span>            :     end // initial</a>
+<a name="178"><span class="lineNum">     178 </span>            :     `ifdef FIRRTL_AFTER_INITIAL</a>
+<a name="179"><span class="lineNum">     179 </span>            :       `FIRRTL_AFTER_INITIAL</a>
+<a name="180"><span class="lineNum">     180 </span>            :     `endif // FIRRTL_AFTER_INITIAL</a>
+<a name="181"><span class="lineNum">     181 </span>            :   `endif // ENABLE_INITIAL_REG_</a>
+<a name="182"><span class="lineNum">     182 </span>            :   SRAMTemplate_35 table_0 (</a>
+<a name="183"><span class="lineNum">     183 </span>            :     .clock                 (clock),</a>
+<a name="184"><span class="lineNum">     184 </span>            :     .reset                 (reset),</a>
+<a name="185"><span class="lineNum">     185 </span>            :     .io_r_req_valid        (io_req_valid),</a>
+<a name="186"><span class="lineNum">     186 </span>            :     .io_r_req_bits_setIdx</a>
+<a name="187"><span class="lineNum">     187 </span>            :       (io_req_bits_pc[8:1] ^ io_req_bits_folded_hist_hist_11_folded_hist),</a>
+<a name="188"><span class="lineNum">     188 </span>            :     .io_r_resp_data_0      (_table_io_r_resp_data_0),</a>
+<a name="189"><span class="lineNum">     189 </span>            :     .io_r_resp_data_1      (_table_io_r_resp_data_1),</a>
+<a name="190"><span class="lineNum">     190 </span>            :     .io_r_resp_data_2      (_table_io_r_resp_data_2),</a>
+<a name="191"><span class="lineNum">     191 </span>            :     .io_r_resp_data_3      (_table_io_r_resp_data_3),</a>
+<a name="192"><span class="lineNum">     192 </span>            :     .io_w_req_valid        (io_update_mask_0 | io_update_mask_1),</a>
+<a name="193"><span class="lineNum">     193 </span>            :     .io_w_req_bits_setIdx  (update_idx),</a>
+<a name="194"><span class="lineNum">     194 </span>            :     .io_w_req_bits_data_0  (update_wdata_0),</a>
+<a name="195"><span class="lineNum">     195 </span>            :     .io_w_req_bits_data_1  (update_wdata_0),</a>
+<a name="196"><span class="lineNum">     196 </span>            :     .io_w_req_bits_data_2  (update_wdata_1),</a>
+<a name="197"><span class="lineNum">     197 </span>            :     .io_w_req_bits_data_3  (update_wdata_1),</a>
+<a name="198"><span class="lineNum">     198 </span>            :     .io_w_req_bits_waymask</a>
+<a name="199"><span class="lineNum">     199 </span>            :       ({updateWayMask_3, updateWayMask_2, updateWayMask_1, updateWayMask_0})</a>
+<a name="200"><span class="lineNum">     200 </span>            :   );</a>
+<a name="201"><span class="lineNum">     201 </span>            :   WrBypass_33 wrbypasses_0 (</a>
+<a name="202"><span class="lineNum">     202 </span>            :     .clock               (clock),</a>
+<a name="203"><span class="lineNum">     203 </span>            :     .reset               (reset),</a>
+<a name="204"><span class="lineNum">     204 </span>            :     .io_wen              (io_update_mask_0),</a>
+<a name="205"><span class="lineNum">     205 </span>            :     .io_write_idx        (update_idx),</a>
+<a name="206"><span class="lineNum">     206 </span>            :     .io_write_data_0     (_GEN | _GEN_0),</a>
+<a name="207"><span class="lineNum">     207 </span>            :     .io_write_data_1     (_GEN | _GEN_0),</a>
+<a name="208"><span class="lineNum">     208 </span>            :     .io_write_way_mask_0</a>
+<a name="209"><span class="lineNum">     209 </span>            :       (~(io_update_pc[1]) &amp; updateWayMask_0 | io_update_pc[1] &amp; updateWayMask_2),</a>
+<a name="210"><span class="lineNum">     210 </span>            :     .io_write_way_mask_1</a>
+<a name="211"><span class="lineNum">     211 </span>            :       (~(io_update_pc[1]) &amp; updateWayMask_1 | io_update_pc[1] &amp; updateWayMask_3),</a>
+<a name="212"><span class="lineNum">     212 </span>            :     .io_hit              (_wrbypasses_0_io_hit),</a>
+<a name="213"><span class="lineNum">     213 </span>            :     .io_hit_data_0_valid (_wrbypasses_0_io_hit_data_0_valid),</a>
+<a name="214"><span class="lineNum">     214 </span>            :     .io_hit_data_0_bits  (_wrbypasses_0_io_hit_data_0_bits),</a>
+<a name="215"><span class="lineNum">     215 </span>            :     .io_hit_data_1_valid (_wrbypasses_0_io_hit_data_1_valid),</a>
+<a name="216"><span class="lineNum">     216 </span>            :     .io_hit_data_1_bits  (_wrbypasses_0_io_hit_data_1_bits)</a>
+<a name="217"><span class="lineNum">     217 </span>            :   );</a>
+<a name="218"><span class="lineNum">     218 </span>            :   WrBypass_33 wrbypasses_1 (</a>
+<a name="219"><span class="lineNum">     219 </span>            :     .clock               (clock),</a>
+<a name="220"><span class="lineNum">     220 </span>            :     .reset               (reset),</a>
+<a name="221"><span class="lineNum">     221 </span>            :     .io_wen              (io_update_mask_1),</a>
+<a name="222"><span class="lineNum">     222 </span>            :     .io_write_idx        (update_idx),</a>
+<a name="223"><span class="lineNum">     223 </span>            :     .io_write_data_0     (_GEN_1 | _GEN_2),</a>
+<a name="224"><span class="lineNum">     224 </span>            :     .io_write_data_1     (_GEN_1 | _GEN_2),</a>
+<a name="225"><span class="lineNum">     225 </span>            :     .io_write_way_mask_0</a>
+<a name="226"><span class="lineNum">     226 </span>            :       (io_update_pc[1] &amp; updateWayMask_0 | ~(io_update_pc[1]) &amp; updateWayMask_2),</a>
+<a name="227"><span class="lineNum">     227 </span>            :     .io_write_way_mask_1</a>
+<a name="228"><span class="lineNum">     228 </span>            :       (io_update_pc[1] &amp; updateWayMask_1 | ~(io_update_pc[1]) &amp; updateWayMask_3),</a>
+<a name="229"><span class="lineNum">     229 </span>            :     .io_hit              (_wrbypasses_1_io_hit),</a>
+<a name="230"><span class="lineNum">     230 </span>            :     .io_hit_data_0_valid (_wrbypasses_1_io_hit_data_0_valid),</a>
+<a name="231"><span class="lineNum">     231 </span>            :     .io_hit_data_0_bits  (_wrbypasses_1_io_hit_data_0_bits),</a>
+<a name="232"><span class="lineNum">     232 </span>            :     .io_hit_data_1_valid (_wrbypasses_1_io_hit_data_1_valid),</a>
+<a name="233"><span class="lineNum">     233 </span>            :     .io_hit_data_1_bits  (_wrbypasses_1_io_hit_data_1_bits)</a>
+<a name="234"><span class="lineNum">     234 </span>            :   );</a>
+<a name="235"><span class="lineNum">     235 </span>            :   assign io_resp_ctrs_0_0 =</a>
+<a name="236"><span class="lineNum">     236 </span>            :     (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_0)</a>
+<a name="237"><span class="lineNum">     237 </span>            :     | (s1_pc[1] ? _table_io_r_resp_data_2 : 6'h0);</a>
+<a name="238"><span class="lineNum">     238 </span>            :   assign io_resp_ctrs_0_1 =</a>
+<a name="239"><span class="lineNum">     239 </span>            :     (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_1)</a>
+<a name="240"><span class="lineNum">     240 </span>            :     | (s1_pc[1] ? _table_io_r_resp_data_3 : 6'h0);</a>
+<a name="241"><span class="lineNum">     241 </span>            :   assign io_resp_ctrs_1_0 =</a>
+<a name="242"><span class="lineNum">     242 </span>            :     (s1_pc[1] ? _table_io_r_resp_data_0 : 6'h0)</a>
+<a name="243"><span class="lineNum">     243 </span>            :     | (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_2);</a>
+<a name="244"><span class="lineNum">     244 </span>            :   assign io_resp_ctrs_1_1 =</a>
+<a name="245"><span class="lineNum">     245 </span>            :     (s1_pc[1] ? _table_io_r_resp_data_1 : 6'h0)</a>
+<a name="246"><span class="lineNum">     246 </span>            :     | (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_3);</a>
+<a name="247"><span class="lineNum">     247 </span>            : endmodule</a>
+<a name="248"><span class="lineNum">     248 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SCTable_3.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SCTable_3.sv.func-sort-c.html
new file mode 100644
index 0000000..ef1b52b
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SCTable_3.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/SCTable_3.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - SCTable_3.sv<span style="font-size: 80%;"> (<a href="SCTable_3.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">37</td>
+            <td class="headerCovTableEntry">37</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="SCTable_3.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SCTable_3.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SCTable_3.sv.func.html
new file mode 100644
index 0000000..c657b64
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SCTable_3.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/SCTable_3.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - SCTable_3.sv<span style="font-size: 80%;"> (<a href="SCTable_3.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">37</td>
+            <td class="headerCovTableEntry">37</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="SCTable_3.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SCTable_3.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SCTable_3.sv.gcov.html
new file mode 100644
index 0000000..2a29f2c
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SCTable_3.sv.gcov.html
@@ -0,0 +1,324 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/SCTable_3.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - SCTable_3.sv<span style="font-size: 80%;"> (source / <a href="SCTable_3.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">37</td>
+            <td class="headerCovTableEntry">37</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : module SCTable_3(</a>
+<a name="59"><span class="lineNum">      59 </span><span class="lineCov">     127786 :   input         clock,</span></a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">         62 :   input         reset,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">         73 :   input         io_req_valid,</span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">      35066 :   input  [40:0] io_req_bits_pc,</span></a>
+<a name="63"><span class="lineNum">      63 </span><span class="lineCov">        811 :   input  [7:0]  io_req_bits_folded_hist_hist_2_folded_hist,</span></a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">        160 :   output [5:0]  io_resp_ctrs_0_0,</span></a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">        170 :   output [5:0]  io_resp_ctrs_0_1,</span></a>
+<a name="66"><span class="lineNum">      66 </span><span class="lineCov">        155 :   output [5:0]  io_resp_ctrs_1_0,</span></a>
+<a name="67"><span class="lineNum">      67 </span><span class="lineCov">        170 :   output [5:0]  io_resp_ctrs_1_1,</span></a>
+<a name="68"><span class="lineNum">      68 </span><span class="lineCov">        637 :   input  [40:0] io_update_pc,</span></a>
+<a name="69"><span class="lineNum">      69 </span><span class="lineCov">        112 :   input  [7:0]  io_update_folded_hist_hist_2_folded_hist,</span></a>
+<a name="70"><span class="lineNum">      70 </span><span class="lineCov">         30 :   input         io_update_mask_0,</span></a>
+<a name="71"><span class="lineNum">      71 </span><span class="lineCov">         29 :   input         io_update_mask_1,</span></a>
+<a name="72"><span class="lineNum">      72 </span><span class="lineCov">         95 :   input  [5:0]  io_update_oldCtrs_0,</span></a>
+<a name="73"><span class="lineNum">      73 </span><span class="lineCov">         85 :   input  [5:0]  io_update_oldCtrs_1,</span></a>
+<a name="74"><span class="lineNum">      74 </span><span class="lineCov">         18 :   input         io_update_tagePreds_0,</span></a>
+<a name="75"><span class="lineNum">      75 </span><span class="lineCov">         18 :   input         io_update_tagePreds_1,</span></a>
+<a name="76"><span class="lineNum">      76 </span><span class="lineCov">         17 :   input         io_update_takens_0,</span></a>
+<a name="77"><span class="lineNum">      77 </span><span class="lineCov">         17 :   input         io_update_takens_1</span></a>
+<a name="78"><span class="lineNum">      78 </span>            : );</a>
+<a name="79"><span class="lineNum">      79 </span>            : </a>
+<a name="80"><span class="lineNum">      80 </span>            :   wire        _wrbypasses_1_io_hit;</a>
+<a name="81"><span class="lineNum">      81 </span>            :   wire        _wrbypasses_1_io_hit_data_0_valid;</a>
+<a name="82"><span class="lineNum">      82 </span>            :   wire [5:0]  _wrbypasses_1_io_hit_data_0_bits;</a>
+<a name="83"><span class="lineNum">      83 </span>            :   wire        _wrbypasses_1_io_hit_data_1_valid;</a>
+<a name="84"><span class="lineNum">      84 </span>            :   wire [5:0]  _wrbypasses_1_io_hit_data_1_bits;</a>
+<a name="85"><span class="lineNum">      85 </span>            :   wire        _wrbypasses_0_io_hit;</a>
+<a name="86"><span class="lineNum">      86 </span>            :   wire        _wrbypasses_0_io_hit_data_0_valid;</a>
+<a name="87"><span class="lineNum">      87 </span>            :   wire [5:0]  _wrbypasses_0_io_hit_data_0_bits;</a>
+<a name="88"><span class="lineNum">      88 </span>            :   wire        _wrbypasses_0_io_hit_data_1_valid;</a>
+<a name="89"><span class="lineNum">      89 </span>            :   wire [5:0]  _wrbypasses_0_io_hit_data_1_bits;</a>
+<a name="90"><span class="lineNum">      90 </span>            :   wire [5:0]  _table_io_r_resp_data_0;</a>
+<a name="91"><span class="lineNum">      91 </span>            :   wire [5:0]  _table_io_r_resp_data_1;</a>
+<a name="92"><span class="lineNum">      92 </span>            :   wire [5:0]  _table_io_r_resp_data_2;</a>
+<a name="93"><span class="lineNum">      93 </span>            :   wire [5:0]  _table_io_r_resp_data_3;</a>
+<a name="94"><span class="lineNum">      94 </span><span class="lineCov">       9383 :   reg  [40:0] s1_pc;</span></a>
+<a name="95"><span class="lineNum">      95 </span><span class="lineCov">         22 :   wire        updateWayMask_0 =</span></a>
+<a name="96"><span class="lineNum">      96 </span>            :     io_update_mask_0 &amp; ~(io_update_pc[1]) &amp; ~io_update_tagePreds_0 | io_update_mask_1</a>
+<a name="97"><span class="lineNum">      97 </span>            :     &amp; io_update_pc[1] &amp; ~io_update_tagePreds_1;</a>
+<a name="98"><span class="lineNum">      98 </span><span class="lineCov">         19 :   wire        updateWayMask_1 =</span></a>
+<a name="99"><span class="lineNum">      99 </span>            :     io_update_mask_0 &amp; ~(io_update_pc[1]) &amp; io_update_tagePreds_0 | io_update_mask_1</a>
+<a name="100"><span class="lineNum">     100 </span>            :     &amp; io_update_pc[1] &amp; io_update_tagePreds_1;</a>
+<a name="101"><span class="lineNum">     101 </span><span class="lineCov">         20 :   wire        updateWayMask_2 =</span></a>
+<a name="102"><span class="lineNum">     102 </span>            :     io_update_mask_0 &amp; io_update_pc[1] &amp; ~io_update_tagePreds_0 | io_update_mask_1</a>
+<a name="103"><span class="lineNum">     103 </span>            :     &amp; ~(io_update_pc[1]) &amp; ~io_update_tagePreds_1;</a>
+<a name="104"><span class="lineNum">     104 </span><span class="lineCov">         19 :   wire        updateWayMask_3 =</span></a>
+<a name="105"><span class="lineNum">     105 </span>            :     io_update_mask_0 &amp; io_update_pc[1] &amp; io_update_tagePreds_0 | io_update_mask_1</a>
+<a name="106"><span class="lineNum">     106 </span>            :     &amp; ~(io_update_pc[1]) &amp; io_update_tagePreds_1;</a>
+<a name="107"><span class="lineNum">     107 </span><span class="lineCov">        131 :   wire [7:0]  update_idx = io_update_pc[8:1] ^ io_update_folded_hist_hist_2_folded_hist;</span></a>
+<a name="108"><span class="lineNum">     108 </span><span class="lineCov">         12 :   wire        ctrPos =</span></a>
+<a name="109"><span class="lineNum">     109 </span>            :     ~(io_update_pc[1]) &amp; io_update_tagePreds_0 | io_update_pc[1] &amp; io_update_tagePreds_1;</a>
+<a name="110"><span class="lineNum">     110 </span><span class="lineCov">        125 :   wire [5:0]  oldCtr =</span></a>
+<a name="111"><span class="lineNum">     111 </span>            :     (~(io_update_pc[1]) &amp; _wrbypasses_0_io_hit | io_update_pc[1] &amp; _wrbypasses_1_io_hit)</a>
+<a name="112"><span class="lineNum">     112 </span>            :     &amp; (ctrPos</a>
+<a name="113"><span class="lineNum">     113 </span>            :          ? ~(io_update_pc[1]) &amp; _wrbypasses_0_io_hit_data_1_valid | io_update_pc[1]</a>
+<a name="114"><span class="lineNum">     114 </span>            :            &amp; _wrbypasses_1_io_hit_data_1_valid</a>
+<a name="115"><span class="lineNum">     115 </span>            :          : ~(io_update_pc[1]) &amp; _wrbypasses_0_io_hit_data_0_valid | io_update_pc[1]</a>
+<a name="116"><span class="lineNum">     116 </span>            :            &amp; _wrbypasses_1_io_hit_data_0_valid)</a>
+<a name="117"><span class="lineNum">     117 </span>            :       ? (ctrPos</a>
+<a name="118"><span class="lineNum">     118 </span>            :            ? (io_update_pc[1] ? 6'h0 : _wrbypasses_0_io_hit_data_1_bits)</a>
+<a name="119"><span class="lineNum">     119 </span>            :              | (io_update_pc[1] ? _wrbypasses_1_io_hit_data_1_bits : 6'h0)</a>
+<a name="120"><span class="lineNum">     120 </span>            :            : (io_update_pc[1] ? 6'h0 : _wrbypasses_0_io_hit_data_0_bits)</a>
+<a name="121"><span class="lineNum">     121 </span>            :              | (io_update_pc[1] ? _wrbypasses_1_io_hit_data_0_bits : 6'h0))</a>
+<a name="122"><span class="lineNum">     122 </span>            :       : (io_update_pc[1] ? 6'h0 : io_update_oldCtrs_0)</a>
+<a name="123"><span class="lineNum">     123 </span>            :         | (io_update_pc[1] ? io_update_oldCtrs_1 : 6'h0);</a>
+<a name="124"><span class="lineNum">     124 </span><span class="lineCov">         15 :   wire        taken =</span></a>
+<a name="125"><span class="lineNum">     125 </span>            :     ~(io_update_pc[1]) &amp; io_update_takens_0 | io_update_pc[1] &amp; io_update_takens_1;</a>
+<a name="126"><span class="lineNum">     126 </span><span class="lineCov">        101 :   wire [5:0]  update_wdata_0 =</span></a>
+<a name="127"><span class="lineNum">     127 </span>            :     oldCtr == 6'h1F &amp; taken</a>
+<a name="128"><span class="lineNum">     128 </span>            :       ? 6'h1F</a>
+<a name="129"><span class="lineNum">     129 </span>            :       : oldCtr == 6'h20 &amp; ~taken ? 6'h20 : taken ? 6'(oldCtr + 6'h1) : 6'(oldCtr - 6'h1);</a>
+<a name="130"><span class="lineNum">     130 </span><span class="lineCov">         18 :   wire        ctrPos_1 =</span></a>
+<a name="131"><span class="lineNum">     131 </span>            :     io_update_pc[1] &amp; io_update_tagePreds_0 | ~(io_update_pc[1]) &amp; io_update_tagePreds_1;</a>
+<a name="132"><span class="lineNum">     132 </span><span class="lineCov">        139 :   wire [5:0]  oldCtr_1 =</span></a>
+<a name="133"><span class="lineNum">     133 </span>            :     (io_update_pc[1] &amp; _wrbypasses_0_io_hit | ~(io_update_pc[1]) &amp; _wrbypasses_1_io_hit)</a>
+<a name="134"><span class="lineNum">     134 </span>            :     &amp; (ctrPos_1</a>
+<a name="135"><span class="lineNum">     135 </span>            :          ? io_update_pc[1] &amp; _wrbypasses_0_io_hit_data_1_valid | ~(io_update_pc[1])</a>
+<a name="136"><span class="lineNum">     136 </span>            :            &amp; _wrbypasses_1_io_hit_data_1_valid</a>
+<a name="137"><span class="lineNum">     137 </span>            :          : io_update_pc[1] &amp; _wrbypasses_0_io_hit_data_0_valid | ~(io_update_pc[1])</a>
+<a name="138"><span class="lineNum">     138 </span>            :            &amp; _wrbypasses_1_io_hit_data_0_valid)</a>
+<a name="139"><span class="lineNum">     139 </span>            :       ? (ctrPos_1</a>
+<a name="140"><span class="lineNum">     140 </span>            :            ? (io_update_pc[1] ? _wrbypasses_0_io_hit_data_1_bits : 6'h0)</a>
+<a name="141"><span class="lineNum">     141 </span>            :              | (io_update_pc[1] ? 6'h0 : _wrbypasses_1_io_hit_data_1_bits)</a>
+<a name="142"><span class="lineNum">     142 </span>            :            : (io_update_pc[1] ? _wrbypasses_0_io_hit_data_0_bits : 6'h0)</a>
+<a name="143"><span class="lineNum">     143 </span>            :              | (io_update_pc[1] ? 6'h0 : _wrbypasses_1_io_hit_data_0_bits))</a>
+<a name="144"><span class="lineNum">     144 </span>            :       : (io_update_pc[1] ? io_update_oldCtrs_0 : 6'h0)</a>
+<a name="145"><span class="lineNum">     145 </span>            :         | (io_update_pc[1] ? 6'h0 : io_update_oldCtrs_1);</a>
+<a name="146"><span class="lineNum">     146 </span><span class="lineCov">         11 :   wire        taken_1 =</span></a>
+<a name="147"><span class="lineNum">     147 </span>            :     io_update_pc[1] &amp; io_update_takens_0 | ~(io_update_pc[1]) &amp; io_update_takens_1;</a>
+<a name="148"><span class="lineNum">     148 </span><span class="lineCov">         97 :   wire [5:0]  update_wdata_1 =</span></a>
+<a name="149"><span class="lineNum">     149 </span>            :     oldCtr_1 == 6'h1F &amp; taken_1</a>
+<a name="150"><span class="lineNum">     150 </span>            :       ? 6'h1F</a>
+<a name="151"><span class="lineNum">     151 </span>            :       : oldCtr_1 == 6'h20 &amp; ~taken_1</a>
+<a name="152"><span class="lineNum">     152 </span>            :           ? 6'h20</a>
+<a name="153"><span class="lineNum">     153 </span>            :           : taken_1 ? 6'(oldCtr_1 + 6'h1) : 6'(oldCtr_1 - 6'h1);</a>
+<a name="154"><span class="lineNum">     154 </span>            :   wire [5:0]  _GEN = io_update_pc[1] ? 6'h0 : update_wdata_0;</a>
+<a name="155"><span class="lineNum">     155 </span>            :   wire [5:0]  _GEN_0 = io_update_pc[1] ? update_wdata_1 : 6'h0;</a>
+<a name="156"><span class="lineNum">     156 </span>            :   wire [5:0]  _GEN_1 = io_update_pc[1] ? update_wdata_0 : 6'h0;</a>
+<a name="157"><span class="lineNum">     157 </span>            :   wire [5:0]  _GEN_2 = io_update_pc[1] ? 6'h0 : update_wdata_1;</a>
+<a name="158"><span class="lineNum">     158 </span><span class="lineCov">     127694 :   always @(posedge clock) begin</span></a>
+<a name="159"><span class="lineNum">     159 </span><span class="lineCov">       8350 :     if (io_req_valid)</span></a>
+<a name="160"><span class="lineNum">     160 </span><span class="lineCov">       4175 :       s1_pc &lt;= io_req_bits_pc;</span></a>
+<a name="161"><span class="lineNum">     161 </span>            :   end // always @(posedge)</a>
+<a name="162"><span class="lineNum">     162 </span>            :   `ifdef ENABLE_INITIAL_REG_</a>
+<a name="163"><span class="lineNum">     163 </span>            :     `ifdef FIRRTL_BEFORE_INITIAL</a>
+<a name="164"><span class="lineNum">     164 </span>            :       `FIRRTL_BEFORE_INITIAL</a>
+<a name="165"><span class="lineNum">     165 </span>            :     `endif // FIRRTL_BEFORE_INITIAL</a>
+<a name="166"><span class="lineNum">     166 </span>            :     logic [31:0] _RANDOM[0:1];</a>
+<a name="167"><span class="lineNum">     167 </span><span class="lineCov">         58 :     initial begin</span></a>
+<a name="168"><span class="lineNum">     168 </span>            :       `ifdef INIT_RANDOM_PROLOG_</a>
+<a name="169"><span class="lineNum">     169 </span>            :         `INIT_RANDOM_PROLOG_</a>
+<a name="170"><span class="lineNum">     170 </span>            :       `endif // INIT_RANDOM_PROLOG_</a>
+<a name="171"><span class="lineNum">     171 </span>            :       `ifdef RANDOMIZE_REG_INIT</a>
+<a name="172"><span class="lineNum">     172 </span>            :         for (logic [1:0] i = 2'h0; i &lt; 2'h2; i += 2'h1) begin</a>
+<a name="173"><span class="lineNum">     173 </span>            :           _RANDOM[i[0]] = `RANDOM;</a>
+<a name="174"><span class="lineNum">     174 </span>            :         end</a>
+<a name="175"><span class="lineNum">     175 </span>            :         s1_pc = {_RANDOM[1'h0][31:8], _RANDOM[1'h1][16:0]};</a>
+<a name="176"><span class="lineNum">     176 </span>            :       `endif // RANDOMIZE_REG_INIT</a>
+<a name="177"><span class="lineNum">     177 </span>            :     end // initial</a>
+<a name="178"><span class="lineNum">     178 </span>            :     `ifdef FIRRTL_AFTER_INITIAL</a>
+<a name="179"><span class="lineNum">     179 </span>            :       `FIRRTL_AFTER_INITIAL</a>
+<a name="180"><span class="lineNum">     180 </span>            :     `endif // FIRRTL_AFTER_INITIAL</a>
+<a name="181"><span class="lineNum">     181 </span>            :   `endif // ENABLE_INITIAL_REG_</a>
+<a name="182"><span class="lineNum">     182 </span>            :   SRAMTemplate_35 table_0 (</a>
+<a name="183"><span class="lineNum">     183 </span>            :     .clock                 (clock),</a>
+<a name="184"><span class="lineNum">     184 </span>            :     .reset                 (reset),</a>
+<a name="185"><span class="lineNum">     185 </span>            :     .io_r_req_valid        (io_req_valid),</a>
+<a name="186"><span class="lineNum">     186 </span>            :     .io_r_req_bits_setIdx</a>
+<a name="187"><span class="lineNum">     187 </span>            :       (io_req_bits_pc[8:1] ^ io_req_bits_folded_hist_hist_2_folded_hist),</a>
+<a name="188"><span class="lineNum">     188 </span>            :     .io_r_resp_data_0      (_table_io_r_resp_data_0),</a>
+<a name="189"><span class="lineNum">     189 </span>            :     .io_r_resp_data_1      (_table_io_r_resp_data_1),</a>
+<a name="190"><span class="lineNum">     190 </span>            :     .io_r_resp_data_2      (_table_io_r_resp_data_2),</a>
+<a name="191"><span class="lineNum">     191 </span>            :     .io_r_resp_data_3      (_table_io_r_resp_data_3),</a>
+<a name="192"><span class="lineNum">     192 </span>            :     .io_w_req_valid        (io_update_mask_0 | io_update_mask_1),</a>
+<a name="193"><span class="lineNum">     193 </span>            :     .io_w_req_bits_setIdx  (update_idx),</a>
+<a name="194"><span class="lineNum">     194 </span>            :     .io_w_req_bits_data_0  (update_wdata_0),</a>
+<a name="195"><span class="lineNum">     195 </span>            :     .io_w_req_bits_data_1  (update_wdata_0),</a>
+<a name="196"><span class="lineNum">     196 </span>            :     .io_w_req_bits_data_2  (update_wdata_1),</a>
+<a name="197"><span class="lineNum">     197 </span>            :     .io_w_req_bits_data_3  (update_wdata_1),</a>
+<a name="198"><span class="lineNum">     198 </span>            :     .io_w_req_bits_waymask</a>
+<a name="199"><span class="lineNum">     199 </span>            :       ({updateWayMask_3, updateWayMask_2, updateWayMask_1, updateWayMask_0})</a>
+<a name="200"><span class="lineNum">     200 </span>            :   );</a>
+<a name="201"><span class="lineNum">     201 </span>            :   WrBypass_33 wrbypasses_0 (</a>
+<a name="202"><span class="lineNum">     202 </span>            :     .clock               (clock),</a>
+<a name="203"><span class="lineNum">     203 </span>            :     .reset               (reset),</a>
+<a name="204"><span class="lineNum">     204 </span>            :     .io_wen              (io_update_mask_0),</a>
+<a name="205"><span class="lineNum">     205 </span>            :     .io_write_idx        (update_idx),</a>
+<a name="206"><span class="lineNum">     206 </span>            :     .io_write_data_0     (_GEN | _GEN_0),</a>
+<a name="207"><span class="lineNum">     207 </span>            :     .io_write_data_1     (_GEN | _GEN_0),</a>
+<a name="208"><span class="lineNum">     208 </span>            :     .io_write_way_mask_0</a>
+<a name="209"><span class="lineNum">     209 </span>            :       (~(io_update_pc[1]) &amp; updateWayMask_0 | io_update_pc[1] &amp; updateWayMask_2),</a>
+<a name="210"><span class="lineNum">     210 </span>            :     .io_write_way_mask_1</a>
+<a name="211"><span class="lineNum">     211 </span>            :       (~(io_update_pc[1]) &amp; updateWayMask_1 | io_update_pc[1] &amp; updateWayMask_3),</a>
+<a name="212"><span class="lineNum">     212 </span>            :     .io_hit              (_wrbypasses_0_io_hit),</a>
+<a name="213"><span class="lineNum">     213 </span>            :     .io_hit_data_0_valid (_wrbypasses_0_io_hit_data_0_valid),</a>
+<a name="214"><span class="lineNum">     214 </span>            :     .io_hit_data_0_bits  (_wrbypasses_0_io_hit_data_0_bits),</a>
+<a name="215"><span class="lineNum">     215 </span>            :     .io_hit_data_1_valid (_wrbypasses_0_io_hit_data_1_valid),</a>
+<a name="216"><span class="lineNum">     216 </span>            :     .io_hit_data_1_bits  (_wrbypasses_0_io_hit_data_1_bits)</a>
+<a name="217"><span class="lineNum">     217 </span>            :   );</a>
+<a name="218"><span class="lineNum">     218 </span>            :   WrBypass_33 wrbypasses_1 (</a>
+<a name="219"><span class="lineNum">     219 </span>            :     .clock               (clock),</a>
+<a name="220"><span class="lineNum">     220 </span>            :     .reset               (reset),</a>
+<a name="221"><span class="lineNum">     221 </span>            :     .io_wen              (io_update_mask_1),</a>
+<a name="222"><span class="lineNum">     222 </span>            :     .io_write_idx        (update_idx),</a>
+<a name="223"><span class="lineNum">     223 </span>            :     .io_write_data_0     (_GEN_1 | _GEN_2),</a>
+<a name="224"><span class="lineNum">     224 </span>            :     .io_write_data_1     (_GEN_1 | _GEN_2),</a>
+<a name="225"><span class="lineNum">     225 </span>            :     .io_write_way_mask_0</a>
+<a name="226"><span class="lineNum">     226 </span>            :       (io_update_pc[1] &amp; updateWayMask_0 | ~(io_update_pc[1]) &amp; updateWayMask_2),</a>
+<a name="227"><span class="lineNum">     227 </span>            :     .io_write_way_mask_1</a>
+<a name="228"><span class="lineNum">     228 </span>            :       (io_update_pc[1] &amp; updateWayMask_1 | ~(io_update_pc[1]) &amp; updateWayMask_3),</a>
+<a name="229"><span class="lineNum">     229 </span>            :     .io_hit              (_wrbypasses_1_io_hit),</a>
+<a name="230"><span class="lineNum">     230 </span>            :     .io_hit_data_0_valid (_wrbypasses_1_io_hit_data_0_valid),</a>
+<a name="231"><span class="lineNum">     231 </span>            :     .io_hit_data_0_bits  (_wrbypasses_1_io_hit_data_0_bits),</a>
+<a name="232"><span class="lineNum">     232 </span>            :     .io_hit_data_1_valid (_wrbypasses_1_io_hit_data_1_valid),</a>
+<a name="233"><span class="lineNum">     233 </span>            :     .io_hit_data_1_bits  (_wrbypasses_1_io_hit_data_1_bits)</a>
+<a name="234"><span class="lineNum">     234 </span>            :   );</a>
+<a name="235"><span class="lineNum">     235 </span>            :   assign io_resp_ctrs_0_0 =</a>
+<a name="236"><span class="lineNum">     236 </span>            :     (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_0)</a>
+<a name="237"><span class="lineNum">     237 </span>            :     | (s1_pc[1] ? _table_io_r_resp_data_2 : 6'h0);</a>
+<a name="238"><span class="lineNum">     238 </span>            :   assign io_resp_ctrs_0_1 =</a>
+<a name="239"><span class="lineNum">     239 </span>            :     (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_1)</a>
+<a name="240"><span class="lineNum">     240 </span>            :     | (s1_pc[1] ? _table_io_r_resp_data_3 : 6'h0);</a>
+<a name="241"><span class="lineNum">     241 </span>            :   assign io_resp_ctrs_1_0 =</a>
+<a name="242"><span class="lineNum">     242 </span>            :     (s1_pc[1] ? _table_io_r_resp_data_0 : 6'h0)</a>
+<a name="243"><span class="lineNum">     243 </span>            :     | (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_2);</a>
+<a name="244"><span class="lineNum">     244 </span>            :   assign io_resp_ctrs_1_1 =</a>
+<a name="245"><span class="lineNum">     245 </span>            :     (s1_pc[1] ? _table_io_r_resp_data_1 : 6'h0)</a>
+<a name="246"><span class="lineNum">     246 </span>            :     | (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_3);</a>
+<a name="247"><span class="lineNum">     247 </span>            : endmodule</a>
+<a name="248"><span class="lineNum">     248 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SRAMTemplate_13.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SRAMTemplate_13.sv.func-sort-c.html
new file mode 100644
index 0000000..0773a2a
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SRAMTemplate_13.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/SRAMTemplate_13.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - SRAMTemplate_13.sv<span style="font-size: 80%;"> (<a href="SRAMTemplate_13.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">183</td>
+            <td class="headerCovTableEntry">183</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="SRAMTemplate_13.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SRAMTemplate_13.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SRAMTemplate_13.sv.func.html
new file mode 100644
index 0000000..e9262df
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SRAMTemplate_13.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/SRAMTemplate_13.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - SRAMTemplate_13.sv<span style="font-size: 80%;"> (<a href="SRAMTemplate_13.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">183</td>
+            <td class="headerCovTableEntry">183</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="SRAMTemplate_13.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SRAMTemplate_13.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SRAMTemplate_13.sv.gcov.html
new file mode 100644
index 0000000..a91c334
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SRAMTemplate_13.sv.gcov.html
@@ -0,0 +1,519 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/SRAMTemplate_13.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - SRAMTemplate_13.sv<span style="font-size: 80%;"> (source / <a href="SRAMTemplate_13.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">183</td>
+            <td class="headerCovTableEntry">183</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : module SRAMTemplate_13(</a>
+<a name="59"><span class="lineNum">      59 </span><span class="lineCov">     127786 :   input         clock,</span></a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">         62 :   input         reset,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">         90 :   output        io_r_req_ready,</span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">         78 :   input         io_r_req_valid,</span></a>
+<a name="63"><span class="lineNum">      63 </span><span class="lineCov">       8587 :   input  [8:0]  io_r_req_bits_setIdx,</span></a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">         84 :   output        io_r_resp_data_0_entry_valid,</span></a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">        158 :   output [3:0]  io_r_resp_data_0_entry_brSlots_0_offset,</span></a>
+<a name="66"><span class="lineNum">      66 </span><span class="lineCov">        380 :   output [11:0] io_r_resp_data_0_entry_brSlots_0_lower,</span></a>
+<a name="67"><span class="lineNum">      67 </span><span class="lineCov">         90 :   output [1:0]  io_r_resp_data_0_entry_brSlots_0_tarStat,</span></a>
+<a name="68"><span class="lineNum">      68 </span><span class="lineCov">         67 :   output        io_r_resp_data_0_entry_brSlots_0_sharing,</span></a>
+<a name="69"><span class="lineNum">      69 </span><span class="lineCov">         60 :   output        io_r_resp_data_0_entry_brSlots_0_valid,</span></a>
+<a name="70"><span class="lineNum">      70 </span><span class="lineCov">        318 :   output [3:0]  io_r_resp_data_0_entry_tailSlot_offset,</span></a>
+<a name="71"><span class="lineNum">      71 </span><span class="lineCov">        723 :   output [19:0] io_r_resp_data_0_entry_tailSlot_lower,</span></a>
+<a name="72"><span class="lineNum">      72 </span><span class="lineCov">        153 :   output [1:0]  io_r_resp_data_0_entry_tailSlot_tarStat,</span></a>
+<a name="73"><span class="lineNum">      73 </span><span class="lineCov">         77 :   output        io_r_resp_data_0_entry_tailSlot_sharing,</span></a>
+<a name="74"><span class="lineNum">      74 </span><span class="lineCov">         78 :   output        io_r_resp_data_0_entry_tailSlot_valid,</span></a>
+<a name="75"><span class="lineNum">      75 </span><span class="lineCov">        319 :   output [3:0]  io_r_resp_data_0_entry_pftAddr,</span></a>
+<a name="76"><span class="lineNum">      76 </span><span class="lineCov">         71 :   output        io_r_resp_data_0_entry_carry,</span></a>
+<a name="77"><span class="lineNum">      77 </span><span class="lineCov">         70 :   output        io_r_resp_data_0_entry_isCall,</span></a>
+<a name="78"><span class="lineNum">      78 </span><span class="lineCov">         63 :   output        io_r_resp_data_0_entry_isRet,</span></a>
+<a name="79"><span class="lineNum">      79 </span><span class="lineCov">         72 :   output        io_r_resp_data_0_entry_isJalr,</span></a>
+<a name="80"><span class="lineNum">      80 </span><span class="lineCov">         63 :   output        io_r_resp_data_0_entry_last_may_be_rvi_call,</span></a>
+<a name="81"><span class="lineNum">      81 </span><span class="lineCov">         70 :   output        io_r_resp_data_0_entry_always_taken_0,</span></a>
+<a name="82"><span class="lineNum">      82 </span><span class="lineCov">         64 :   output        io_r_resp_data_0_entry_always_taken_1,</span></a>
+<a name="83"><span class="lineNum">      83 </span><span class="lineCov">        708 :   output [19:0] io_r_resp_data_0_tag,</span></a>
+<a name="84"><span class="lineNum">      84 </span><span class="lineCov">         25 :   output        io_r_resp_data_1_entry_valid,</span></a>
+<a name="85"><span class="lineNum">      85 </span><span class="lineCov">        119 :   output [3:0]  io_r_resp_data_1_entry_brSlots_0_offset,</span></a>
+<a name="86"><span class="lineNum">      86 </span><span class="lineCov">        353 :   output [11:0] io_r_resp_data_1_entry_brSlots_0_lower,</span></a>
+<a name="87"><span class="lineNum">      87 </span><span class="lineCov">         65 :   output [1:0]  io_r_resp_data_1_entry_brSlots_0_tarStat,</span></a>
+<a name="88"><span class="lineNum">      88 </span><span class="lineCov">         24 :   output        io_r_resp_data_1_entry_brSlots_0_sharing,</span></a>
+<a name="89"><span class="lineNum">      89 </span><span class="lineCov">         28 :   output        io_r_resp_data_1_entry_brSlots_0_valid,</span></a>
+<a name="90"><span class="lineNum">      90 </span><span class="lineCov">        117 :   output [3:0]  io_r_resp_data_1_entry_tailSlot_offset,</span></a>
+<a name="91"><span class="lineNum">      91 </span><span class="lineCov">        592 :   output [19:0] io_r_resp_data_1_entry_tailSlot_lower,</span></a>
+<a name="92"><span class="lineNum">      92 </span><span class="lineCov">         63 :   output [1:0]  io_r_resp_data_1_entry_tailSlot_tarStat,</span></a>
+<a name="93"><span class="lineNum">      93 </span><span class="lineCov">         30 :   output        io_r_resp_data_1_entry_tailSlot_sharing,</span></a>
+<a name="94"><span class="lineNum">      94 </span><span class="lineCov">         29 :   output        io_r_resp_data_1_entry_tailSlot_valid,</span></a>
+<a name="95"><span class="lineNum">      95 </span><span class="lineCov">        134 :   output [3:0]  io_r_resp_data_1_entry_pftAddr,</span></a>
+<a name="96"><span class="lineNum">      96 </span><span class="lineCov">         32 :   output        io_r_resp_data_1_entry_carry,</span></a>
+<a name="97"><span class="lineNum">      97 </span><span class="lineCov">         29 :   output        io_r_resp_data_1_entry_isCall,</span></a>
+<a name="98"><span class="lineNum">      98 </span><span class="lineCov">         19 :   output        io_r_resp_data_1_entry_isRet,</span></a>
+<a name="99"><span class="lineNum">      99 </span><span class="lineCov">         29 :   output        io_r_resp_data_1_entry_isJalr,</span></a>
+<a name="100"><span class="lineNum">     100 </span><span class="lineCov">         31 :   output        io_r_resp_data_1_entry_last_may_be_rvi_call,</span></a>
+<a name="101"><span class="lineNum">     101 </span><span class="lineCov">         28 :   output        io_r_resp_data_1_entry_always_taken_0,</span></a>
+<a name="102"><span class="lineNum">     102 </span><span class="lineCov">         29 :   output        io_r_resp_data_1_entry_always_taken_1,</span></a>
+<a name="103"><span class="lineNum">     103 </span><span class="lineCov">        608 :   output [19:0] io_r_resp_data_1_tag,</span></a>
+<a name="104"><span class="lineNum">     104 </span><span class="lineCov">         29 :   output        io_r_resp_data_2_entry_valid,</span></a>
+<a name="105"><span class="lineNum">     105 </span><span class="lineCov">        114 :   output [3:0]  io_r_resp_data_2_entry_brSlots_0_offset,</span></a>
+<a name="106"><span class="lineNum">     106 </span><span class="lineCov">        347 :   output [11:0] io_r_resp_data_2_entry_brSlots_0_lower,</span></a>
+<a name="107"><span class="lineNum">     107 </span><span class="lineCov">         69 :   output [1:0]  io_r_resp_data_2_entry_brSlots_0_tarStat,</span></a>
+<a name="108"><span class="lineNum">     108 </span><span class="lineCov">         33 :   output        io_r_resp_data_2_entry_brSlots_0_sharing,</span></a>
+<a name="109"><span class="lineNum">     109 </span><span class="lineCov">         33 :   output        io_r_resp_data_2_entry_brSlots_0_valid,</span></a>
+<a name="110"><span class="lineNum">     110 </span><span class="lineCov">        131 :   output [3:0]  io_r_resp_data_2_entry_tailSlot_offset,</span></a>
+<a name="111"><span class="lineNum">     111 </span><span class="lineCov">        589 :   output [19:0] io_r_resp_data_2_entry_tailSlot_lower,</span></a>
+<a name="112"><span class="lineNum">     112 </span><span class="lineCov">         53 :   output [1:0]  io_r_resp_data_2_entry_tailSlot_tarStat,</span></a>
+<a name="113"><span class="lineNum">     113 </span><span class="lineCov">         23 :   output        io_r_resp_data_2_entry_tailSlot_sharing,</span></a>
+<a name="114"><span class="lineNum">     114 </span><span class="lineCov">         24 :   output        io_r_resp_data_2_entry_tailSlot_valid,</span></a>
+<a name="115"><span class="lineNum">     115 </span><span class="lineCov">        115 :   output [3:0]  io_r_resp_data_2_entry_pftAddr,</span></a>
+<a name="116"><span class="lineNum">     116 </span><span class="lineCov">         28 :   output        io_r_resp_data_2_entry_carry,</span></a>
+<a name="117"><span class="lineNum">     117 </span><span class="lineCov">         35 :   output        io_r_resp_data_2_entry_isCall,</span></a>
+<a name="118"><span class="lineNum">     118 </span><span class="lineCov">         24 :   output        io_r_resp_data_2_entry_isRet,</span></a>
+<a name="119"><span class="lineNum">     119 </span><span class="lineCov">         33 :   output        io_r_resp_data_2_entry_isJalr,</span></a>
+<a name="120"><span class="lineNum">     120 </span><span class="lineCov">         32 :   output        io_r_resp_data_2_entry_last_may_be_rvi_call,</span></a>
+<a name="121"><span class="lineNum">     121 </span><span class="lineCov">         24 :   output        io_r_resp_data_2_entry_always_taken_0,</span></a>
+<a name="122"><span class="lineNum">     122 </span><span class="lineCov">         24 :   output        io_r_resp_data_2_entry_always_taken_1,</span></a>
+<a name="123"><span class="lineNum">     123 </span><span class="lineCov">        600 :   output [19:0] io_r_resp_data_2_tag,</span></a>
+<a name="124"><span class="lineNum">     124 </span><span class="lineCov">         28 :   output        io_r_resp_data_3_entry_valid,</span></a>
+<a name="125"><span class="lineNum">     125 </span><span class="lineCov">        117 :   output [3:0]  io_r_resp_data_3_entry_brSlots_0_offset,</span></a>
+<a name="126"><span class="lineNum">     126 </span><span class="lineCov">        363 :   output [11:0] io_r_resp_data_3_entry_brSlots_0_lower,</span></a>
+<a name="127"><span class="lineNum">     127 </span><span class="lineCov">         55 :   output [1:0]  io_r_resp_data_3_entry_brSlots_0_tarStat,</span></a>
+<a name="128"><span class="lineNum">     128 </span><span class="lineCov">         26 :   output        io_r_resp_data_3_entry_brSlots_0_sharing,</span></a>
+<a name="129"><span class="lineNum">     129 </span><span class="lineCov">         30 :   output        io_r_resp_data_3_entry_brSlots_0_valid,</span></a>
+<a name="130"><span class="lineNum">     130 </span><span class="lineCov">        115 :   output [3:0]  io_r_resp_data_3_entry_tailSlot_offset,</span></a>
+<a name="131"><span class="lineNum">     131 </span><span class="lineCov">        598 :   output [19:0] io_r_resp_data_3_entry_tailSlot_lower,</span></a>
+<a name="132"><span class="lineNum">     132 </span><span class="lineCov">         55 :   output [1:0]  io_r_resp_data_3_entry_tailSlot_tarStat,</span></a>
+<a name="133"><span class="lineNum">     133 </span><span class="lineCov">         31 :   output        io_r_resp_data_3_entry_tailSlot_sharing,</span></a>
+<a name="134"><span class="lineNum">     134 </span><span class="lineCov">         27 :   output        io_r_resp_data_3_entry_tailSlot_valid,</span></a>
+<a name="135"><span class="lineNum">     135 </span><span class="lineCov">        113 :   output [3:0]  io_r_resp_data_3_entry_pftAddr,</span></a>
+<a name="136"><span class="lineNum">     136 </span><span class="lineCov">         34 :   output        io_r_resp_data_3_entry_carry,</span></a>
+<a name="137"><span class="lineNum">     137 </span><span class="lineCov">         30 :   output        io_r_resp_data_3_entry_isCall,</span></a>
+<a name="138"><span class="lineNum">     138 </span><span class="lineCov">         34 :   output        io_r_resp_data_3_entry_isRet,</span></a>
+<a name="139"><span class="lineNum">     139 </span><span class="lineCov">         35 :   output        io_r_resp_data_3_entry_isJalr,</span></a>
+<a name="140"><span class="lineNum">     140 </span><span class="lineCov">         30 :   output        io_r_resp_data_3_entry_last_may_be_rvi_call,</span></a>
+<a name="141"><span class="lineNum">     141 </span><span class="lineCov">         28 :   output        io_r_resp_data_3_entry_always_taken_0,</span></a>
+<a name="142"><span class="lineNum">     142 </span><span class="lineCov">         25 :   output        io_r_resp_data_3_entry_always_taken_1,</span></a>
+<a name="143"><span class="lineNum">     143 </span><span class="lineCov">        591 :   output [19:0] io_r_resp_data_3_tag,</span></a>
+<a name="144"><span class="lineNum">     144 </span><span class="lineCov">         78 :   input         io_w_req_valid,</span></a>
+<a name="145"><span class="lineNum">     145 </span><span class="lineCov">        250 :   input  [8:0]  io_w_req_bits_setIdx,</span></a>
+<a name="146"><span class="lineNum">     146 </span><span class="lineCov">         27 :   input         io_w_req_bits_data_0_entry_valid,</span></a>
+<a name="147"><span class="lineNum">     147 </span><span class="lineCov">        110 :   input  [3:0]  io_w_req_bits_data_0_entry_brSlots_0_offset,</span></a>
+<a name="148"><span class="lineNum">     148 </span><span class="lineCov">        363 :   input  [11:0] io_w_req_bits_data_0_entry_brSlots_0_lower,</span></a>
+<a name="149"><span class="lineNum">     149 </span><span class="lineCov">         49 :   input  [1:0]  io_w_req_bits_data_0_entry_brSlots_0_tarStat,</span></a>
+<a name="150"><span class="lineNum">     150 </span><span class="lineCov">         28 :   input         io_w_req_bits_data_0_entry_brSlots_0_sharing,</span></a>
+<a name="151"><span class="lineNum">     151 </span><span class="lineCov">         30 :   input         io_w_req_bits_data_0_entry_brSlots_0_valid,</span></a>
+<a name="152"><span class="lineNum">     152 </span><span class="lineCov">        107 :   input  [3:0]  io_w_req_bits_data_0_entry_tailSlot_offset,</span></a>
+<a name="153"><span class="lineNum">     153 </span><span class="lineCov">        576 :   input  [19:0] io_w_req_bits_data_0_entry_tailSlot_lower,</span></a>
+<a name="154"><span class="lineNum">     154 </span><span class="lineCov">         54 :   input  [1:0]  io_w_req_bits_data_0_entry_tailSlot_tarStat,</span></a>
+<a name="155"><span class="lineNum">     155 </span><span class="lineCov">         32 :   input         io_w_req_bits_data_0_entry_tailSlot_sharing,</span></a>
+<a name="156"><span class="lineNum">     156 </span><span class="lineCov">         31 :   input         io_w_req_bits_data_0_entry_tailSlot_valid,</span></a>
+<a name="157"><span class="lineNum">     157 </span><span class="lineCov">        118 :   input  [3:0]  io_w_req_bits_data_0_entry_pftAddr,</span></a>
+<a name="158"><span class="lineNum">     158 </span><span class="lineCov">         25 :   input         io_w_req_bits_data_0_entry_carry,</span></a>
+<a name="159"><span class="lineNum">     159 </span><span class="lineCov">         31 :   input         io_w_req_bits_data_0_entry_isCall,</span></a>
+<a name="160"><span class="lineNum">     160 </span><span class="lineCov">         26 :   input         io_w_req_bits_data_0_entry_isRet,</span></a>
+<a name="161"><span class="lineNum">     161 </span><span class="lineCov">         24 :   input         io_w_req_bits_data_0_entry_isJalr,</span></a>
+<a name="162"><span class="lineNum">     162 </span><span class="lineCov">         28 :   input         io_w_req_bits_data_0_entry_last_may_be_rvi_call,</span></a>
+<a name="163"><span class="lineNum">     163 </span><span class="lineCov">         28 :   input         io_w_req_bits_data_0_entry_always_taken_0,</span></a>
+<a name="164"><span class="lineNum">     164 </span><span class="lineCov">         31 :   input         io_w_req_bits_data_0_entry_always_taken_1,</span></a>
+<a name="165"><span class="lineNum">     165 </span><span class="lineCov">        566 :   input  [19:0] io_w_req_bits_data_0_tag,</span></a>
+<a name="166"><span class="lineNum">     166 </span><span class="lineCov">         27 :   input         io_w_req_bits_data_1_entry_valid,</span></a>
+<a name="167"><span class="lineNum">     167 </span><span class="lineCov">        110 :   input  [3:0]  io_w_req_bits_data_1_entry_brSlots_0_offset,</span></a>
+<a name="168"><span class="lineNum">     168 </span><span class="lineCov">        363 :   input  [11:0] io_w_req_bits_data_1_entry_brSlots_0_lower,</span></a>
+<a name="169"><span class="lineNum">     169 </span><span class="lineCov">         49 :   input  [1:0]  io_w_req_bits_data_1_entry_brSlots_0_tarStat,</span></a>
+<a name="170"><span class="lineNum">     170 </span><span class="lineCov">         28 :   input         io_w_req_bits_data_1_entry_brSlots_0_sharing,</span></a>
+<a name="171"><span class="lineNum">     171 </span><span class="lineCov">         30 :   input         io_w_req_bits_data_1_entry_brSlots_0_valid,</span></a>
+<a name="172"><span class="lineNum">     172 </span><span class="lineCov">        107 :   input  [3:0]  io_w_req_bits_data_1_entry_tailSlot_offset,</span></a>
+<a name="173"><span class="lineNum">     173 </span><span class="lineCov">        576 :   input  [19:0] io_w_req_bits_data_1_entry_tailSlot_lower,</span></a>
+<a name="174"><span class="lineNum">     174 </span><span class="lineCov">         54 :   input  [1:0]  io_w_req_bits_data_1_entry_tailSlot_tarStat,</span></a>
+<a name="175"><span class="lineNum">     175 </span><span class="lineCov">         32 :   input         io_w_req_bits_data_1_entry_tailSlot_sharing,</span></a>
+<a name="176"><span class="lineNum">     176 </span><span class="lineCov">         31 :   input         io_w_req_bits_data_1_entry_tailSlot_valid,</span></a>
+<a name="177"><span class="lineNum">     177 </span><span class="lineCov">        118 :   input  [3:0]  io_w_req_bits_data_1_entry_pftAddr,</span></a>
+<a name="178"><span class="lineNum">     178 </span><span class="lineCov">         25 :   input         io_w_req_bits_data_1_entry_carry,</span></a>
+<a name="179"><span class="lineNum">     179 </span><span class="lineCov">         31 :   input         io_w_req_bits_data_1_entry_isCall,</span></a>
+<a name="180"><span class="lineNum">     180 </span><span class="lineCov">         26 :   input         io_w_req_bits_data_1_entry_isRet,</span></a>
+<a name="181"><span class="lineNum">     181 </span><span class="lineCov">         24 :   input         io_w_req_bits_data_1_entry_isJalr,</span></a>
+<a name="182"><span class="lineNum">     182 </span><span class="lineCov">         28 :   input         io_w_req_bits_data_1_entry_last_may_be_rvi_call,</span></a>
+<a name="183"><span class="lineNum">     183 </span><span class="lineCov">         28 :   input         io_w_req_bits_data_1_entry_always_taken_0,</span></a>
+<a name="184"><span class="lineNum">     184 </span><span class="lineCov">         31 :   input         io_w_req_bits_data_1_entry_always_taken_1,</span></a>
+<a name="185"><span class="lineNum">     185 </span><span class="lineCov">        566 :   input  [19:0] io_w_req_bits_data_1_tag,</span></a>
+<a name="186"><span class="lineNum">     186 </span><span class="lineCov">         27 :   input         io_w_req_bits_data_2_entry_valid,</span></a>
+<a name="187"><span class="lineNum">     187 </span><span class="lineCov">        110 :   input  [3:0]  io_w_req_bits_data_2_entry_brSlots_0_offset,</span></a>
+<a name="188"><span class="lineNum">     188 </span><span class="lineCov">        363 :   input  [11:0] io_w_req_bits_data_2_entry_brSlots_0_lower,</span></a>
+<a name="189"><span class="lineNum">     189 </span><span class="lineCov">         49 :   input  [1:0]  io_w_req_bits_data_2_entry_brSlots_0_tarStat,</span></a>
+<a name="190"><span class="lineNum">     190 </span><span class="lineCov">         28 :   input         io_w_req_bits_data_2_entry_brSlots_0_sharing,</span></a>
+<a name="191"><span class="lineNum">     191 </span><span class="lineCov">         30 :   input         io_w_req_bits_data_2_entry_brSlots_0_valid,</span></a>
+<a name="192"><span class="lineNum">     192 </span><span class="lineCov">        107 :   input  [3:0]  io_w_req_bits_data_2_entry_tailSlot_offset,</span></a>
+<a name="193"><span class="lineNum">     193 </span><span class="lineCov">        576 :   input  [19:0] io_w_req_bits_data_2_entry_tailSlot_lower,</span></a>
+<a name="194"><span class="lineNum">     194 </span><span class="lineCov">         54 :   input  [1:0]  io_w_req_bits_data_2_entry_tailSlot_tarStat,</span></a>
+<a name="195"><span class="lineNum">     195 </span><span class="lineCov">         32 :   input         io_w_req_bits_data_2_entry_tailSlot_sharing,</span></a>
+<a name="196"><span class="lineNum">     196 </span><span class="lineCov">         31 :   input         io_w_req_bits_data_2_entry_tailSlot_valid,</span></a>
+<a name="197"><span class="lineNum">     197 </span><span class="lineCov">        118 :   input  [3:0]  io_w_req_bits_data_2_entry_pftAddr,</span></a>
+<a name="198"><span class="lineNum">     198 </span><span class="lineCov">         25 :   input         io_w_req_bits_data_2_entry_carry,</span></a>
+<a name="199"><span class="lineNum">     199 </span><span class="lineCov">         31 :   input         io_w_req_bits_data_2_entry_isCall,</span></a>
+<a name="200"><span class="lineNum">     200 </span><span class="lineCov">         26 :   input         io_w_req_bits_data_2_entry_isRet,</span></a>
+<a name="201"><span class="lineNum">     201 </span><span class="lineCov">         24 :   input         io_w_req_bits_data_2_entry_isJalr,</span></a>
+<a name="202"><span class="lineNum">     202 </span><span class="lineCov">         28 :   input         io_w_req_bits_data_2_entry_last_may_be_rvi_call,</span></a>
+<a name="203"><span class="lineNum">     203 </span><span class="lineCov">         28 :   input         io_w_req_bits_data_2_entry_always_taken_0,</span></a>
+<a name="204"><span class="lineNum">     204 </span><span class="lineCov">         31 :   input         io_w_req_bits_data_2_entry_always_taken_1,</span></a>
+<a name="205"><span class="lineNum">     205 </span><span class="lineCov">        566 :   input  [19:0] io_w_req_bits_data_2_tag,</span></a>
+<a name="206"><span class="lineNum">     206 </span><span class="lineCov">         27 :   input         io_w_req_bits_data_3_entry_valid,</span></a>
+<a name="207"><span class="lineNum">     207 </span><span class="lineCov">        110 :   input  [3:0]  io_w_req_bits_data_3_entry_brSlots_0_offset,</span></a>
+<a name="208"><span class="lineNum">     208 </span><span class="lineCov">        363 :   input  [11:0] io_w_req_bits_data_3_entry_brSlots_0_lower,</span></a>
+<a name="209"><span class="lineNum">     209 </span><span class="lineCov">         49 :   input  [1:0]  io_w_req_bits_data_3_entry_brSlots_0_tarStat,</span></a>
+<a name="210"><span class="lineNum">     210 </span><span class="lineCov">         28 :   input         io_w_req_bits_data_3_entry_brSlots_0_sharing,</span></a>
+<a name="211"><span class="lineNum">     211 </span><span class="lineCov">         30 :   input         io_w_req_bits_data_3_entry_brSlots_0_valid,</span></a>
+<a name="212"><span class="lineNum">     212 </span><span class="lineCov">        107 :   input  [3:0]  io_w_req_bits_data_3_entry_tailSlot_offset,</span></a>
+<a name="213"><span class="lineNum">     213 </span><span class="lineCov">        576 :   input  [19:0] io_w_req_bits_data_3_entry_tailSlot_lower,</span></a>
+<a name="214"><span class="lineNum">     214 </span><span class="lineCov">         54 :   input  [1:0]  io_w_req_bits_data_3_entry_tailSlot_tarStat,</span></a>
+<a name="215"><span class="lineNum">     215 </span><span class="lineCov">         32 :   input         io_w_req_bits_data_3_entry_tailSlot_sharing,</span></a>
+<a name="216"><span class="lineNum">     216 </span><span class="lineCov">         31 :   input         io_w_req_bits_data_3_entry_tailSlot_valid,</span></a>
+<a name="217"><span class="lineNum">     217 </span><span class="lineCov">        118 :   input  [3:0]  io_w_req_bits_data_3_entry_pftAddr,</span></a>
+<a name="218"><span class="lineNum">     218 </span><span class="lineCov">         25 :   input         io_w_req_bits_data_3_entry_carry,</span></a>
+<a name="219"><span class="lineNum">     219 </span><span class="lineCov">         31 :   input         io_w_req_bits_data_3_entry_isCall,</span></a>
+<a name="220"><span class="lineNum">     220 </span><span class="lineCov">         26 :   input         io_w_req_bits_data_3_entry_isRet,</span></a>
+<a name="221"><span class="lineNum">     221 </span><span class="lineCov">         24 :   input         io_w_req_bits_data_3_entry_isJalr,</span></a>
+<a name="222"><span class="lineNum">     222 </span><span class="lineCov">         28 :   input         io_w_req_bits_data_3_entry_last_may_be_rvi_call,</span></a>
+<a name="223"><span class="lineNum">     223 </span><span class="lineCov">         28 :   input         io_w_req_bits_data_3_entry_always_taken_0,</span></a>
+<a name="224"><span class="lineNum">     224 </span><span class="lineCov">         31 :   input         io_w_req_bits_data_3_entry_always_taken_1,</span></a>
+<a name="225"><span class="lineNum">     225 </span><span class="lineCov">        566 :   input  [19:0] io_w_req_bits_data_3_tag,</span></a>
+<a name="226"><span class="lineNum">     226 </span><span class="lineCov">        229 :   input  [3:0]  io_w_req_bits_waymask</span></a>
+<a name="227"><span class="lineNum">     227 </span>            : );</a>
+<a name="228"><span class="lineNum">     228 </span>            : </a>
+<a name="229"><span class="lineNum">     229 </span><span class="lineCov">      30005 :   wire [8:0]   setIdx;</span></a>
+<a name="230"><span class="lineNum">     230 </span><span class="lineCov">         86 :   wire         realRen;</span></a>
+<a name="231"><span class="lineNum">     231 </span><span class="lineCov">         89 :   wire         wen;</span></a>
+<a name="232"><span class="lineNum">     232 </span>            :   wire [319:0] _array_RW0_rdata;</a>
+<a name="233"><span class="lineNum">     233 </span>            :   reg          _resetState;</a>
+<a name="234"><span class="lineNum">     234 </span>            :   reg  [8:0]   _resetSet;</a>
+<a name="235"><span class="lineNum">     235 </span>            :   assign wen = io_w_req_valid | _resetState;</a>
+<a name="236"><span class="lineNum">     236 </span>            :   assign realRen = io_r_req_valid &amp; ~wen;</a>
+<a name="237"><span class="lineNum">     237 </span>            :   assign setIdx = _resetState ? _resetSet : io_w_req_bits_setIdx;</a>
+<a name="238"><span class="lineNum">     238 </span><span class="lineCov">     127730 :   always @(posedge clock or posedge reset) begin</span></a>
+<a name="239"><span class="lineNum">     239 </span><span class="lineCov">        272 :     if (reset) begin</span></a>
+<a name="240"><span class="lineNum">     240 </span><span class="lineCov">        136 :       _resetState &lt;= 1'h1;</span></a>
+<a name="241"><span class="lineNum">     241 </span><span class="lineCov">        136 :       _resetSet &lt;= 9'h0;</span></a>
+<a name="242"><span class="lineNum">     242 </span>            :     end</a>
+<a name="243"><span class="lineNum">     243 </span><span class="lineCov">      63729 :     else begin</span></a>
+<a name="244"><span class="lineNum">     244 </span><span class="lineCov">      63729 :       _resetState &lt;= ~(_resetState &amp; (&amp;_resetSet)) &amp; _resetState;</span></a>
+<a name="245"><span class="lineNum">     245 </span><span class="lineCov">      29908 :       if (_resetState)</span></a>
+<a name="246"><span class="lineNum">     246 </span><span class="lineCov">      14954 :         _resetSet &lt;= 9'(_resetSet + 9'h1);</span></a>
+<a name="247"><span class="lineNum">     247 </span>            :     end</a>
+<a name="248"><span class="lineNum">     248 </span>            :   end // always @(posedge, posedge)</a>
+<a name="249"><span class="lineNum">     249 </span>            :   `ifdef ENABLE_INITIAL_REG_</a>
+<a name="250"><span class="lineNum">     250 </span>            :     `ifdef FIRRTL_BEFORE_INITIAL</a>
+<a name="251"><span class="lineNum">     251 </span>            :       `FIRRTL_BEFORE_INITIAL</a>
+<a name="252"><span class="lineNum">     252 </span>            :     `endif // FIRRTL_BEFORE_INITIAL</a>
+<a name="253"><span class="lineNum">     253 </span>            :     logic [31:0] _RANDOM[0:0];</a>
+<a name="254"><span class="lineNum">     254 </span><span class="lineCov">         58 :     initial begin</span></a>
+<a name="255"><span class="lineNum">     255 </span>            :       `ifdef INIT_RANDOM_PROLOG_</a>
+<a name="256"><span class="lineNum">     256 </span>            :         `INIT_RANDOM_PROLOG_</a>
+<a name="257"><span class="lineNum">     257 </span>            :       `endif // INIT_RANDOM_PROLOG_</a>
+<a name="258"><span class="lineNum">     258 </span>            :       `ifdef RANDOMIZE_REG_INIT</a>
+<a name="259"><span class="lineNum">     259 </span>            :         _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;</a>
+<a name="260"><span class="lineNum">     260 </span>            :         _resetState = _RANDOM[/*Zero width*/ 1'b0][0];</a>
+<a name="261"><span class="lineNum">     261 </span>            :         _resetSet = _RANDOM[/*Zero width*/ 1'b0][9:1];</a>
+<a name="262"><span class="lineNum">     262 </span>            :       `endif // RANDOMIZE_REG_INIT</a>
+<a name="263"><span class="lineNum">     263 </span><span class="lineCov">         17 :       if (reset) begin</span></a>
+<a name="264"><span class="lineNum">     264 </span><span class="lineCov">         12 :         _resetState = 1'h1;</span></a>
+<a name="265"><span class="lineNum">     265 </span><span class="lineCov">         12 :         _resetSet = 9'h0;</span></a>
+<a name="266"><span class="lineNum">     266 </span>            :       end</a>
+<a name="267"><span class="lineNum">     267 </span>            :     end // initial</a>
+<a name="268"><span class="lineNum">     268 </span>            :     `ifdef FIRRTL_AFTER_INITIAL</a>
+<a name="269"><span class="lineNum">     269 </span>            :       `FIRRTL_AFTER_INITIAL</a>
+<a name="270"><span class="lineNum">     270 </span>            :     `endif // FIRRTL_AFTER_INITIAL</a>
+<a name="271"><span class="lineNum">     271 </span>            :   `endif // ENABLE_INITIAL_REG_</a>
+<a name="272"><span class="lineNum">     272 </span>            :   array_3 array (</a>
+<a name="273"><span class="lineNum">     273 </span>            :     .RW0_addr  (wen ? setIdx : io_r_req_bits_setIdx),</a>
+<a name="274"><span class="lineNum">     274 </span>            :     .RW0_en    (realRen | wen),</a>
+<a name="275"><span class="lineNum">     275 </span>            :     .RW0_clk   (clock),</a>
+<a name="276"><span class="lineNum">     276 </span>            :     .RW0_wmode (wen),</a>
+<a name="277"><span class="lineNum">     277 </span>            :     .RW0_wdata</a>
+<a name="278"><span class="lineNum">     278 </span>            :       ({~_resetState &amp; io_w_req_bits_data_3_entry_valid,</a>
+<a name="279"><span class="lineNum">     279 </span>            :         _resetState ? 4'h0 : io_w_req_bits_data_3_entry_brSlots_0_offset,</a>
+<a name="280"><span class="lineNum">     280 </span>            :         _resetState ? 12'h0 : io_w_req_bits_data_3_entry_brSlots_0_lower,</a>
+<a name="281"><span class="lineNum">     281 </span>            :         _resetState ? 2'h0 : io_w_req_bits_data_3_entry_brSlots_0_tarStat,</a>
+<a name="282"><span class="lineNum">     282 </span>            :         ~_resetState &amp; io_w_req_bits_data_3_entry_brSlots_0_sharing,</a>
+<a name="283"><span class="lineNum">     283 </span>            :         ~_resetState &amp; io_w_req_bits_data_3_entry_brSlots_0_valid,</a>
+<a name="284"><span class="lineNum">     284 </span>            :         _resetState ? 4'h0 : io_w_req_bits_data_3_entry_tailSlot_offset,</a>
+<a name="285"><span class="lineNum">     285 </span>            :         _resetState ? 20'h0 : io_w_req_bits_data_3_entry_tailSlot_lower,</a>
+<a name="286"><span class="lineNum">     286 </span>            :         _resetState ? 2'h0 : io_w_req_bits_data_3_entry_tailSlot_tarStat,</a>
+<a name="287"><span class="lineNum">     287 </span>            :         ~_resetState &amp; io_w_req_bits_data_3_entry_tailSlot_sharing,</a>
+<a name="288"><span class="lineNum">     288 </span>            :         ~_resetState &amp; io_w_req_bits_data_3_entry_tailSlot_valid,</a>
+<a name="289"><span class="lineNum">     289 </span>            :         _resetState ? 4'h0 : io_w_req_bits_data_3_entry_pftAddr,</a>
+<a name="290"><span class="lineNum">     290 </span>            :         ~_resetState &amp; io_w_req_bits_data_3_entry_carry,</a>
+<a name="291"><span class="lineNum">     291 </span>            :         ~_resetState &amp; io_w_req_bits_data_3_entry_isCall,</a>
+<a name="292"><span class="lineNum">     292 </span>            :         ~_resetState &amp; io_w_req_bits_data_3_entry_isRet,</a>
+<a name="293"><span class="lineNum">     293 </span>            :         ~_resetState &amp; io_w_req_bits_data_3_entry_isJalr,</a>
+<a name="294"><span class="lineNum">     294 </span>            :         ~_resetState &amp; io_w_req_bits_data_3_entry_last_may_be_rvi_call,</a>
+<a name="295"><span class="lineNum">     295 </span>            :         ~_resetState &amp; io_w_req_bits_data_3_entry_always_taken_1,</a>
+<a name="296"><span class="lineNum">     296 </span>            :         ~_resetState &amp; io_w_req_bits_data_3_entry_always_taken_0,</a>
+<a name="297"><span class="lineNum">     297 </span>            :         _resetState ? 20'h0 : io_w_req_bits_data_3_tag,</a>
+<a name="298"><span class="lineNum">     298 </span>            :         ~_resetState &amp; io_w_req_bits_data_2_entry_valid,</a>
+<a name="299"><span class="lineNum">     299 </span>            :         _resetState ? 4'h0 : io_w_req_bits_data_2_entry_brSlots_0_offset,</a>
+<a name="300"><span class="lineNum">     300 </span>            :         _resetState ? 12'h0 : io_w_req_bits_data_2_entry_brSlots_0_lower,</a>
+<a name="301"><span class="lineNum">     301 </span>            :         _resetState ? 2'h0 : io_w_req_bits_data_2_entry_brSlots_0_tarStat,</a>
+<a name="302"><span class="lineNum">     302 </span>            :         ~_resetState &amp; io_w_req_bits_data_2_entry_brSlots_0_sharing,</a>
+<a name="303"><span class="lineNum">     303 </span>            :         ~_resetState &amp; io_w_req_bits_data_2_entry_brSlots_0_valid,</a>
+<a name="304"><span class="lineNum">     304 </span>            :         _resetState ? 4'h0 : io_w_req_bits_data_2_entry_tailSlot_offset,</a>
+<a name="305"><span class="lineNum">     305 </span>            :         _resetState ? 20'h0 : io_w_req_bits_data_2_entry_tailSlot_lower,</a>
+<a name="306"><span class="lineNum">     306 </span>            :         _resetState ? 2'h0 : io_w_req_bits_data_2_entry_tailSlot_tarStat,</a>
+<a name="307"><span class="lineNum">     307 </span>            :         ~_resetState &amp; io_w_req_bits_data_2_entry_tailSlot_sharing,</a>
+<a name="308"><span class="lineNum">     308 </span>            :         ~_resetState &amp; io_w_req_bits_data_2_entry_tailSlot_valid,</a>
+<a name="309"><span class="lineNum">     309 </span>            :         _resetState ? 4'h0 : io_w_req_bits_data_2_entry_pftAddr,</a>
+<a name="310"><span class="lineNum">     310 </span>            :         ~_resetState &amp; io_w_req_bits_data_2_entry_carry,</a>
+<a name="311"><span class="lineNum">     311 </span>            :         ~_resetState &amp; io_w_req_bits_data_2_entry_isCall,</a>
+<a name="312"><span class="lineNum">     312 </span>            :         ~_resetState &amp; io_w_req_bits_data_2_entry_isRet,</a>
+<a name="313"><span class="lineNum">     313 </span>            :         ~_resetState &amp; io_w_req_bits_data_2_entry_isJalr,</a>
+<a name="314"><span class="lineNum">     314 </span>            :         ~_resetState &amp; io_w_req_bits_data_2_entry_last_may_be_rvi_call,</a>
+<a name="315"><span class="lineNum">     315 </span>            :         ~_resetState &amp; io_w_req_bits_data_2_entry_always_taken_1,</a>
+<a name="316"><span class="lineNum">     316 </span>            :         ~_resetState &amp; io_w_req_bits_data_2_entry_always_taken_0,</a>
+<a name="317"><span class="lineNum">     317 </span>            :         _resetState ? 20'h0 : io_w_req_bits_data_2_tag,</a>
+<a name="318"><span class="lineNum">     318 </span>            :         ~_resetState &amp; io_w_req_bits_data_1_entry_valid,</a>
+<a name="319"><span class="lineNum">     319 </span>            :         _resetState ? 4'h0 : io_w_req_bits_data_1_entry_brSlots_0_offset,</a>
+<a name="320"><span class="lineNum">     320 </span>            :         _resetState ? 12'h0 : io_w_req_bits_data_1_entry_brSlots_0_lower,</a>
+<a name="321"><span class="lineNum">     321 </span>            :         _resetState ? 2'h0 : io_w_req_bits_data_1_entry_brSlots_0_tarStat,</a>
+<a name="322"><span class="lineNum">     322 </span>            :         ~_resetState &amp; io_w_req_bits_data_1_entry_brSlots_0_sharing,</a>
+<a name="323"><span class="lineNum">     323 </span>            :         ~_resetState &amp; io_w_req_bits_data_1_entry_brSlots_0_valid,</a>
+<a name="324"><span class="lineNum">     324 </span>            :         _resetState ? 4'h0 : io_w_req_bits_data_1_entry_tailSlot_offset,</a>
+<a name="325"><span class="lineNum">     325 </span>            :         _resetState ? 20'h0 : io_w_req_bits_data_1_entry_tailSlot_lower,</a>
+<a name="326"><span class="lineNum">     326 </span>            :         _resetState ? 2'h0 : io_w_req_bits_data_1_entry_tailSlot_tarStat,</a>
+<a name="327"><span class="lineNum">     327 </span>            :         ~_resetState &amp; io_w_req_bits_data_1_entry_tailSlot_sharing,</a>
+<a name="328"><span class="lineNum">     328 </span>            :         ~_resetState &amp; io_w_req_bits_data_1_entry_tailSlot_valid,</a>
+<a name="329"><span class="lineNum">     329 </span>            :         _resetState ? 4'h0 : io_w_req_bits_data_1_entry_pftAddr,</a>
+<a name="330"><span class="lineNum">     330 </span>            :         ~_resetState &amp; io_w_req_bits_data_1_entry_carry,</a>
+<a name="331"><span class="lineNum">     331 </span>            :         ~_resetState &amp; io_w_req_bits_data_1_entry_isCall,</a>
+<a name="332"><span class="lineNum">     332 </span>            :         ~_resetState &amp; io_w_req_bits_data_1_entry_isRet,</a>
+<a name="333"><span class="lineNum">     333 </span>            :         ~_resetState &amp; io_w_req_bits_data_1_entry_isJalr,</a>
+<a name="334"><span class="lineNum">     334 </span>            :         ~_resetState &amp; io_w_req_bits_data_1_entry_last_may_be_rvi_call,</a>
+<a name="335"><span class="lineNum">     335 </span>            :         ~_resetState &amp; io_w_req_bits_data_1_entry_always_taken_1,</a>
+<a name="336"><span class="lineNum">     336 </span>            :         ~_resetState &amp; io_w_req_bits_data_1_entry_always_taken_0,</a>
+<a name="337"><span class="lineNum">     337 </span>            :         _resetState ? 20'h0 : io_w_req_bits_data_1_tag,</a>
+<a name="338"><span class="lineNum">     338 </span>            :         ~_resetState &amp; io_w_req_bits_data_0_entry_valid,</a>
+<a name="339"><span class="lineNum">     339 </span>            :         _resetState ? 4'h0 : io_w_req_bits_data_0_entry_brSlots_0_offset,</a>
+<a name="340"><span class="lineNum">     340 </span>            :         _resetState ? 12'h0 : io_w_req_bits_data_0_entry_brSlots_0_lower,</a>
+<a name="341"><span class="lineNum">     341 </span>            :         _resetState ? 2'h0 : io_w_req_bits_data_0_entry_brSlots_0_tarStat,</a>
+<a name="342"><span class="lineNum">     342 </span>            :         ~_resetState &amp; io_w_req_bits_data_0_entry_brSlots_0_sharing,</a>
+<a name="343"><span class="lineNum">     343 </span>            :         ~_resetState &amp; io_w_req_bits_data_0_entry_brSlots_0_valid,</a>
+<a name="344"><span class="lineNum">     344 </span>            :         _resetState ? 4'h0 : io_w_req_bits_data_0_entry_tailSlot_offset,</a>
+<a name="345"><span class="lineNum">     345 </span>            :         _resetState ? 20'h0 : io_w_req_bits_data_0_entry_tailSlot_lower,</a>
+<a name="346"><span class="lineNum">     346 </span>            :         _resetState ? 2'h0 : io_w_req_bits_data_0_entry_tailSlot_tarStat,</a>
+<a name="347"><span class="lineNum">     347 </span>            :         ~_resetState &amp; io_w_req_bits_data_0_entry_tailSlot_sharing,</a>
+<a name="348"><span class="lineNum">     348 </span>            :         ~_resetState &amp; io_w_req_bits_data_0_entry_tailSlot_valid,</a>
+<a name="349"><span class="lineNum">     349 </span>            :         _resetState ? 4'h0 : io_w_req_bits_data_0_entry_pftAddr,</a>
+<a name="350"><span class="lineNum">     350 </span>            :         ~_resetState &amp; io_w_req_bits_data_0_entry_carry,</a>
+<a name="351"><span class="lineNum">     351 </span>            :         ~_resetState &amp; io_w_req_bits_data_0_entry_isCall,</a>
+<a name="352"><span class="lineNum">     352 </span>            :         ~_resetState &amp; io_w_req_bits_data_0_entry_isRet,</a>
+<a name="353"><span class="lineNum">     353 </span>            :         ~_resetState &amp; io_w_req_bits_data_0_entry_isJalr,</a>
+<a name="354"><span class="lineNum">     354 </span>            :         ~_resetState &amp; io_w_req_bits_data_0_entry_last_may_be_rvi_call,</a>
+<a name="355"><span class="lineNum">     355 </span>            :         ~_resetState &amp; io_w_req_bits_data_0_entry_always_taken_1,</a>
+<a name="356"><span class="lineNum">     356 </span>            :         ~_resetState &amp; io_w_req_bits_data_0_entry_always_taken_0,</a>
+<a name="357"><span class="lineNum">     357 </span>            :         _resetState ? 20'h0 : io_w_req_bits_data_0_tag}),</a>
+<a name="358"><span class="lineNum">     358 </span>            :     .RW0_rdata (_array_RW0_rdata),</a>
+<a name="359"><span class="lineNum">     359 </span>            :     .RW0_wmask (_resetState ? 4'hF : io_w_req_bits_waymask)</a>
+<a name="360"><span class="lineNum">     360 </span>            :   );</a>
+<a name="361"><span class="lineNum">     361 </span>            :   assign io_r_req_ready = ~_resetState &amp; ~wen;</a>
+<a name="362"><span class="lineNum">     362 </span>            :   assign io_r_resp_data_0_entry_valid = _array_RW0_rdata[79];</a>
+<a name="363"><span class="lineNum">     363 </span>            :   assign io_r_resp_data_0_entry_brSlots_0_offset = _array_RW0_rdata[78:75];</a>
+<a name="364"><span class="lineNum">     364 </span>            :   assign io_r_resp_data_0_entry_brSlots_0_lower = _array_RW0_rdata[74:63];</a>
+<a name="365"><span class="lineNum">     365 </span>            :   assign io_r_resp_data_0_entry_brSlots_0_tarStat = _array_RW0_rdata[62:61];</a>
+<a name="366"><span class="lineNum">     366 </span>            :   assign io_r_resp_data_0_entry_brSlots_0_sharing = _array_RW0_rdata[60];</a>
+<a name="367"><span class="lineNum">     367 </span>            :   assign io_r_resp_data_0_entry_brSlots_0_valid = _array_RW0_rdata[59];</a>
+<a name="368"><span class="lineNum">     368 </span>            :   assign io_r_resp_data_0_entry_tailSlot_offset = _array_RW0_rdata[58:55];</a>
+<a name="369"><span class="lineNum">     369 </span>            :   assign io_r_resp_data_0_entry_tailSlot_lower = _array_RW0_rdata[54:35];</a>
+<a name="370"><span class="lineNum">     370 </span>            :   assign io_r_resp_data_0_entry_tailSlot_tarStat = _array_RW0_rdata[34:33];</a>
+<a name="371"><span class="lineNum">     371 </span>            :   assign io_r_resp_data_0_entry_tailSlot_sharing = _array_RW0_rdata[32];</a>
+<a name="372"><span class="lineNum">     372 </span>            :   assign io_r_resp_data_0_entry_tailSlot_valid = _array_RW0_rdata[31];</a>
+<a name="373"><span class="lineNum">     373 </span>            :   assign io_r_resp_data_0_entry_pftAddr = _array_RW0_rdata[30:27];</a>
+<a name="374"><span class="lineNum">     374 </span>            :   assign io_r_resp_data_0_entry_carry = _array_RW0_rdata[26];</a>
+<a name="375"><span class="lineNum">     375 </span>            :   assign io_r_resp_data_0_entry_isCall = _array_RW0_rdata[25];</a>
+<a name="376"><span class="lineNum">     376 </span>            :   assign io_r_resp_data_0_entry_isRet = _array_RW0_rdata[24];</a>
+<a name="377"><span class="lineNum">     377 </span>            :   assign io_r_resp_data_0_entry_isJalr = _array_RW0_rdata[23];</a>
+<a name="378"><span class="lineNum">     378 </span>            :   assign io_r_resp_data_0_entry_last_may_be_rvi_call = _array_RW0_rdata[22];</a>
+<a name="379"><span class="lineNum">     379 </span>            :   assign io_r_resp_data_0_entry_always_taken_0 = _array_RW0_rdata[20];</a>
+<a name="380"><span class="lineNum">     380 </span>            :   assign io_r_resp_data_0_entry_always_taken_1 = _array_RW0_rdata[21];</a>
+<a name="381"><span class="lineNum">     381 </span>            :   assign io_r_resp_data_0_tag = _array_RW0_rdata[19:0];</a>
+<a name="382"><span class="lineNum">     382 </span>            :   assign io_r_resp_data_1_entry_valid = _array_RW0_rdata[159];</a>
+<a name="383"><span class="lineNum">     383 </span>            :   assign io_r_resp_data_1_entry_brSlots_0_offset = _array_RW0_rdata[158:155];</a>
+<a name="384"><span class="lineNum">     384 </span>            :   assign io_r_resp_data_1_entry_brSlots_0_lower = _array_RW0_rdata[154:143];</a>
+<a name="385"><span class="lineNum">     385 </span>            :   assign io_r_resp_data_1_entry_brSlots_0_tarStat = _array_RW0_rdata[142:141];</a>
+<a name="386"><span class="lineNum">     386 </span>            :   assign io_r_resp_data_1_entry_brSlots_0_sharing = _array_RW0_rdata[140];</a>
+<a name="387"><span class="lineNum">     387 </span>            :   assign io_r_resp_data_1_entry_brSlots_0_valid = _array_RW0_rdata[139];</a>
+<a name="388"><span class="lineNum">     388 </span>            :   assign io_r_resp_data_1_entry_tailSlot_offset = _array_RW0_rdata[138:135];</a>
+<a name="389"><span class="lineNum">     389 </span>            :   assign io_r_resp_data_1_entry_tailSlot_lower = _array_RW0_rdata[134:115];</a>
+<a name="390"><span class="lineNum">     390 </span>            :   assign io_r_resp_data_1_entry_tailSlot_tarStat = _array_RW0_rdata[114:113];</a>
+<a name="391"><span class="lineNum">     391 </span>            :   assign io_r_resp_data_1_entry_tailSlot_sharing = _array_RW0_rdata[112];</a>
+<a name="392"><span class="lineNum">     392 </span>            :   assign io_r_resp_data_1_entry_tailSlot_valid = _array_RW0_rdata[111];</a>
+<a name="393"><span class="lineNum">     393 </span>            :   assign io_r_resp_data_1_entry_pftAddr = _array_RW0_rdata[110:107];</a>
+<a name="394"><span class="lineNum">     394 </span>            :   assign io_r_resp_data_1_entry_carry = _array_RW0_rdata[106];</a>
+<a name="395"><span class="lineNum">     395 </span>            :   assign io_r_resp_data_1_entry_isCall = _array_RW0_rdata[105];</a>
+<a name="396"><span class="lineNum">     396 </span>            :   assign io_r_resp_data_1_entry_isRet = _array_RW0_rdata[104];</a>
+<a name="397"><span class="lineNum">     397 </span>            :   assign io_r_resp_data_1_entry_isJalr = _array_RW0_rdata[103];</a>
+<a name="398"><span class="lineNum">     398 </span>            :   assign io_r_resp_data_1_entry_last_may_be_rvi_call = _array_RW0_rdata[102];</a>
+<a name="399"><span class="lineNum">     399 </span>            :   assign io_r_resp_data_1_entry_always_taken_0 = _array_RW0_rdata[100];</a>
+<a name="400"><span class="lineNum">     400 </span>            :   assign io_r_resp_data_1_entry_always_taken_1 = _array_RW0_rdata[101];</a>
+<a name="401"><span class="lineNum">     401 </span>            :   assign io_r_resp_data_1_tag = _array_RW0_rdata[99:80];</a>
+<a name="402"><span class="lineNum">     402 </span>            :   assign io_r_resp_data_2_entry_valid = _array_RW0_rdata[239];</a>
+<a name="403"><span class="lineNum">     403 </span>            :   assign io_r_resp_data_2_entry_brSlots_0_offset = _array_RW0_rdata[238:235];</a>
+<a name="404"><span class="lineNum">     404 </span>            :   assign io_r_resp_data_2_entry_brSlots_0_lower = _array_RW0_rdata[234:223];</a>
+<a name="405"><span class="lineNum">     405 </span>            :   assign io_r_resp_data_2_entry_brSlots_0_tarStat = _array_RW0_rdata[222:221];</a>
+<a name="406"><span class="lineNum">     406 </span>            :   assign io_r_resp_data_2_entry_brSlots_0_sharing = _array_RW0_rdata[220];</a>
+<a name="407"><span class="lineNum">     407 </span>            :   assign io_r_resp_data_2_entry_brSlots_0_valid = _array_RW0_rdata[219];</a>
+<a name="408"><span class="lineNum">     408 </span>            :   assign io_r_resp_data_2_entry_tailSlot_offset = _array_RW0_rdata[218:215];</a>
+<a name="409"><span class="lineNum">     409 </span>            :   assign io_r_resp_data_2_entry_tailSlot_lower = _array_RW0_rdata[214:195];</a>
+<a name="410"><span class="lineNum">     410 </span>            :   assign io_r_resp_data_2_entry_tailSlot_tarStat = _array_RW0_rdata[194:193];</a>
+<a name="411"><span class="lineNum">     411 </span>            :   assign io_r_resp_data_2_entry_tailSlot_sharing = _array_RW0_rdata[192];</a>
+<a name="412"><span class="lineNum">     412 </span>            :   assign io_r_resp_data_2_entry_tailSlot_valid = _array_RW0_rdata[191];</a>
+<a name="413"><span class="lineNum">     413 </span>            :   assign io_r_resp_data_2_entry_pftAddr = _array_RW0_rdata[190:187];</a>
+<a name="414"><span class="lineNum">     414 </span>            :   assign io_r_resp_data_2_entry_carry = _array_RW0_rdata[186];</a>
+<a name="415"><span class="lineNum">     415 </span>            :   assign io_r_resp_data_2_entry_isCall = _array_RW0_rdata[185];</a>
+<a name="416"><span class="lineNum">     416 </span>            :   assign io_r_resp_data_2_entry_isRet = _array_RW0_rdata[184];</a>
+<a name="417"><span class="lineNum">     417 </span>            :   assign io_r_resp_data_2_entry_isJalr = _array_RW0_rdata[183];</a>
+<a name="418"><span class="lineNum">     418 </span>            :   assign io_r_resp_data_2_entry_last_may_be_rvi_call = _array_RW0_rdata[182];</a>
+<a name="419"><span class="lineNum">     419 </span>            :   assign io_r_resp_data_2_entry_always_taken_0 = _array_RW0_rdata[180];</a>
+<a name="420"><span class="lineNum">     420 </span>            :   assign io_r_resp_data_2_entry_always_taken_1 = _array_RW0_rdata[181];</a>
+<a name="421"><span class="lineNum">     421 </span>            :   assign io_r_resp_data_2_tag = _array_RW0_rdata[179:160];</a>
+<a name="422"><span class="lineNum">     422 </span>            :   assign io_r_resp_data_3_entry_valid = _array_RW0_rdata[319];</a>
+<a name="423"><span class="lineNum">     423 </span>            :   assign io_r_resp_data_3_entry_brSlots_0_offset = _array_RW0_rdata[318:315];</a>
+<a name="424"><span class="lineNum">     424 </span>            :   assign io_r_resp_data_3_entry_brSlots_0_lower = _array_RW0_rdata[314:303];</a>
+<a name="425"><span class="lineNum">     425 </span>            :   assign io_r_resp_data_3_entry_brSlots_0_tarStat = _array_RW0_rdata[302:301];</a>
+<a name="426"><span class="lineNum">     426 </span>            :   assign io_r_resp_data_3_entry_brSlots_0_sharing = _array_RW0_rdata[300];</a>
+<a name="427"><span class="lineNum">     427 </span>            :   assign io_r_resp_data_3_entry_brSlots_0_valid = _array_RW0_rdata[299];</a>
+<a name="428"><span class="lineNum">     428 </span>            :   assign io_r_resp_data_3_entry_tailSlot_offset = _array_RW0_rdata[298:295];</a>
+<a name="429"><span class="lineNum">     429 </span>            :   assign io_r_resp_data_3_entry_tailSlot_lower = _array_RW0_rdata[294:275];</a>
+<a name="430"><span class="lineNum">     430 </span>            :   assign io_r_resp_data_3_entry_tailSlot_tarStat = _array_RW0_rdata[274:273];</a>
+<a name="431"><span class="lineNum">     431 </span>            :   assign io_r_resp_data_3_entry_tailSlot_sharing = _array_RW0_rdata[272];</a>
+<a name="432"><span class="lineNum">     432 </span>            :   assign io_r_resp_data_3_entry_tailSlot_valid = _array_RW0_rdata[271];</a>
+<a name="433"><span class="lineNum">     433 </span>            :   assign io_r_resp_data_3_entry_pftAddr = _array_RW0_rdata[270:267];</a>
+<a name="434"><span class="lineNum">     434 </span>            :   assign io_r_resp_data_3_entry_carry = _array_RW0_rdata[266];</a>
+<a name="435"><span class="lineNum">     435 </span>            :   assign io_r_resp_data_3_entry_isCall = _array_RW0_rdata[265];</a>
+<a name="436"><span class="lineNum">     436 </span>            :   assign io_r_resp_data_3_entry_isRet = _array_RW0_rdata[264];</a>
+<a name="437"><span class="lineNum">     437 </span>            :   assign io_r_resp_data_3_entry_isJalr = _array_RW0_rdata[263];</a>
+<a name="438"><span class="lineNum">     438 </span>            :   assign io_r_resp_data_3_entry_last_may_be_rvi_call = _array_RW0_rdata[262];</a>
+<a name="439"><span class="lineNum">     439 </span>            :   assign io_r_resp_data_3_entry_always_taken_0 = _array_RW0_rdata[260];</a>
+<a name="440"><span class="lineNum">     440 </span>            :   assign io_r_resp_data_3_entry_always_taken_1 = _array_RW0_rdata[261];</a>
+<a name="441"><span class="lineNum">     441 </span>            :   assign io_r_resp_data_3_tag = _array_RW0_rdata[259:240];</a>
+<a name="442"><span class="lineNum">     442 </span>            : endmodule</a>
+<a name="443"><span class="lineNum">     443 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SRAMTemplate_14.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SRAMTemplate_14.sv.func-sort-c.html
new file mode 100644
index 0000000..3e63fd5
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SRAMTemplate_14.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/SRAMTemplate_14.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - SRAMTemplate_14.sv<span style="font-size: 80%;"> (<a href="SRAMTemplate_14.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">95</td>
+            <td class="headerCovTableEntry">95</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="SRAMTemplate_14.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SRAMTemplate_14.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SRAMTemplate_14.sv.func.html
new file mode 100644
index 0000000..4cf299b
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SRAMTemplate_14.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/SRAMTemplate_14.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - SRAMTemplate_14.sv<span style="font-size: 80%;"> (<a href="SRAMTemplate_14.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">95</td>
+            <td class="headerCovTableEntry">95</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="SRAMTemplate_14.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SRAMTemplate_14.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SRAMTemplate_14.sv.gcov.html
new file mode 100644
index 0000000..a495267
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SRAMTemplate_14.sv.gcov.html
@@ -0,0 +1,324 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/SRAMTemplate_14.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - SRAMTemplate_14.sv<span style="font-size: 80%;"> (source / <a href="SRAMTemplate_14.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">95</td>
+            <td class="headerCovTableEntry">95</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : module SRAMTemplate_14(</a>
+<a name="59"><span class="lineNum">      59 </span><span class="lineCov">     127786 :   input         clock,</span></a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">         62 :   input         reset,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">        201 :   output        io_r_req_ready,</span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">        309 :   input         io_r_req_valid,</span></a>
+<a name="63"><span class="lineNum">      63 </span><span class="lineCov">      25930 :   input  [7:0]  io_r_req_bits_setIdx,</span></a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">        114 :   output        io_r_resp_data_0,</span></a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">        118 :   output        io_r_resp_data_1,</span></a>
+<a name="66"><span class="lineNum">      66 </span><span class="lineCov">        116 :   output        io_r_resp_data_2,</span></a>
+<a name="67"><span class="lineNum">      67 </span><span class="lineCov">        107 :   output        io_r_resp_data_3,</span></a>
+<a name="68"><span class="lineNum">      68 </span><span class="lineCov">        124 :   output        io_r_resp_data_4,</span></a>
+<a name="69"><span class="lineNum">      69 </span><span class="lineCov">        115 :   output        io_r_resp_data_5,</span></a>
+<a name="70"><span class="lineNum">      70 </span><span class="lineCov">        124 :   output        io_r_resp_data_6,</span></a>
+<a name="71"><span class="lineNum">      71 </span><span class="lineCov">        120 :   output        io_r_resp_data_7,</span></a>
+<a name="72"><span class="lineNum">      72 </span><span class="lineCov">        116 :   output        io_r_resp_data_8,</span></a>
+<a name="73"><span class="lineNum">      73 </span><span class="lineCov">        122 :   output        io_r_resp_data_9,</span></a>
+<a name="74"><span class="lineNum">      74 </span><span class="lineCov">        115 :   output        io_r_resp_data_10,</span></a>
+<a name="75"><span class="lineNum">      75 </span><span class="lineCov">        125 :   output        io_r_resp_data_11,</span></a>
+<a name="76"><span class="lineNum">      76 </span><span class="lineCov">        110 :   output        io_r_resp_data_12,</span></a>
+<a name="77"><span class="lineNum">      77 </span><span class="lineCov">        118 :   output        io_r_resp_data_13,</span></a>
+<a name="78"><span class="lineNum">      78 </span><span class="lineCov">        102 :   output        io_r_resp_data_14,</span></a>
+<a name="79"><span class="lineNum">      79 </span><span class="lineCov">        120 :   output        io_r_resp_data_15,</span></a>
+<a name="80"><span class="lineNum">      80 </span><span class="lineCov">        125 :   input         io_w_req_valid,</span></a>
+<a name="81"><span class="lineNum">      81 </span><span class="lineCov">        228 :   input  [7:0]  io_w_req_bits_setIdx,</span></a>
+<a name="82"><span class="lineNum">      82 </span><span class="lineCov">         53 :   input         io_w_req_bits_data_0,</span></a>
+<a name="83"><span class="lineNum">      83 </span><span class="lineCov">         65 :   input         io_w_req_bits_data_1,</span></a>
+<a name="84"><span class="lineNum">      84 </span><span class="lineCov">         53 :   input         io_w_req_bits_data_2,</span></a>
+<a name="85"><span class="lineNum">      85 </span><span class="lineCov">         65 :   input         io_w_req_bits_data_3,</span></a>
+<a name="86"><span class="lineNum">      86 </span><span class="lineCov">         53 :   input         io_w_req_bits_data_4,</span></a>
+<a name="87"><span class="lineNum">      87 </span><span class="lineCov">         65 :   input         io_w_req_bits_data_5,</span></a>
+<a name="88"><span class="lineNum">      88 </span><span class="lineCov">         53 :   input         io_w_req_bits_data_6,</span></a>
+<a name="89"><span class="lineNum">      89 </span><span class="lineCov">         65 :   input         io_w_req_bits_data_7,</span></a>
+<a name="90"><span class="lineNum">      90 </span><span class="lineCov">         53 :   input         io_w_req_bits_data_8,</span></a>
+<a name="91"><span class="lineNum">      91 </span><span class="lineCov">         65 :   input         io_w_req_bits_data_9,</span></a>
+<a name="92"><span class="lineNum">      92 </span><span class="lineCov">         53 :   input         io_w_req_bits_data_10,</span></a>
+<a name="93"><span class="lineNum">      93 </span><span class="lineCov">         65 :   input         io_w_req_bits_data_11,</span></a>
+<a name="94"><span class="lineNum">      94 </span><span class="lineCov">         53 :   input         io_w_req_bits_data_12,</span></a>
+<a name="95"><span class="lineNum">      95 </span><span class="lineCov">         65 :   input         io_w_req_bits_data_13,</span></a>
+<a name="96"><span class="lineNum">      96 </span><span class="lineCov">         53 :   input         io_w_req_bits_data_14,</span></a>
+<a name="97"><span class="lineNum">      97 </span><span class="lineCov">         65 :   input         io_w_req_bits_data_15,</span></a>
+<a name="98"><span class="lineNum">      98 </span><span class="lineCov">        930 :   input  [15:0] io_w_req_bits_waymask,</span></a>
+<a name="99"><span class="lineNum">      99 </span><span class="lineCov">        146 :   input         extra_reset</span></a>
+<a name="100"><span class="lineNum">     100 </span>            : );</a>
+<a name="101"><span class="lineNum">     101 </span>            : </a>
+<a name="102"><span class="lineNum">     102 </span><span class="lineCov">      60355 :   wire [7:0]  setIdx;</span></a>
+<a name="103"><span class="lineNum">     103 </span><span class="lineCov">        294 :   wire        realRen;</span></a>
+<a name="104"><span class="lineNum">     104 </span><span class="lineCov">        195 :   wire        wen;</span></a>
+<a name="105"><span class="lineNum">     105 </span>            :   wire [15:0] _array_RW0_rdata;</a>
+<a name="106"><span class="lineNum">     106 </span>            :   reg         _resetState;</a>
+<a name="107"><span class="lineNum">     107 </span>            :   reg  [7:0]  _resetSet;</a>
+<a name="108"><span class="lineNum">     108 </span>            :   assign wen = io_w_req_valid | _resetState;</a>
+<a name="109"><span class="lineNum">     109 </span>            :   assign realRen = io_r_req_valid &amp; ~wen;</a>
+<a name="110"><span class="lineNum">     110 </span>            :   assign setIdx = _resetState ? _resetSet : io_w_req_bits_setIdx;</a>
+<a name="111"><span class="lineNum">     111 </span><span class="lineCov">        336 :   reg         rdata_last_r;</span></a>
+<a name="112"><span class="lineNum">     112 </span><span class="lineCov">        127 :   reg         rdata_hold_data_0;</span></a>
+<a name="113"><span class="lineNum">     113 </span><span class="lineCov">        144 :   reg         rdata_hold_data_1;</span></a>
+<a name="114"><span class="lineNum">     114 </span><span class="lineCov">        137 :   reg         rdata_hold_data_2;</span></a>
+<a name="115"><span class="lineNum">     115 </span><span class="lineCov">        118 :   reg         rdata_hold_data_3;</span></a>
+<a name="116"><span class="lineNum">     116 </span><span class="lineCov">        136 :   reg         rdata_hold_data_4;</span></a>
+<a name="117"><span class="lineNum">     117 </span><span class="lineCov">        119 :   reg         rdata_hold_data_5;</span></a>
+<a name="118"><span class="lineNum">     118 </span><span class="lineCov">        125 :   reg         rdata_hold_data_6;</span></a>
+<a name="119"><span class="lineNum">     119 </span><span class="lineCov">        140 :   reg         rdata_hold_data_7;</span></a>
+<a name="120"><span class="lineNum">     120 </span><span class="lineCov">        136 :   reg         rdata_hold_data_8;</span></a>
+<a name="121"><span class="lineNum">     121 </span><span class="lineCov">        138 :   reg         rdata_hold_data_9;</span></a>
+<a name="122"><span class="lineNum">     122 </span><span class="lineCov">        135 :   reg         rdata_hold_data_10;</span></a>
+<a name="123"><span class="lineNum">     123 </span><span class="lineCov">        155 :   reg         rdata_hold_data_11;</span></a>
+<a name="124"><span class="lineNum">     124 </span><span class="lineCov">        132 :   reg         rdata_hold_data_12;</span></a>
+<a name="125"><span class="lineNum">     125 </span><span class="lineCov">        131 :   reg         rdata_hold_data_13;</span></a>
+<a name="126"><span class="lineNum">     126 </span><span class="lineCov">        121 :   reg         rdata_hold_data_14;</span></a>
+<a name="127"><span class="lineNum">     127 </span><span class="lineCov">        146 :   reg         rdata_hold_data_15;</span></a>
+<a name="128"><span class="lineNum">     128 </span><span class="lineCov">     510920 :   always @(posedge clock or posedge reset) begin</span></a>
+<a name="129"><span class="lineNum">     129 </span><span class="lineCov">       1088 :     if (reset) begin</span></a>
+<a name="130"><span class="lineNum">     130 </span><span class="lineCov">        544 :       _resetState &lt;= 1'h1;</span></a>
+<a name="131"><span class="lineNum">     131 </span><span class="lineCov">        544 :       _resetSet &lt;= 8'h0;</span></a>
+<a name="132"><span class="lineNum">     132 </span><span class="lineCov">        544 :       rdata_last_r &lt;= 1'h0;</span></a>
+<a name="133"><span class="lineNum">     133 </span>            :     end</a>
+<a name="134"><span class="lineNum">     134 </span><span class="lineCov">     254916 :     else begin</span></a>
+<a name="135"><span class="lineNum">     135 </span><span class="lineCov">     254916 :       _resetState &lt;= extra_reset | ~(_resetState &amp; (&amp;_resetSet)) &amp; _resetState;</span></a>
+<a name="136"><span class="lineNum">     136 </span><span class="lineCov">      60256 :       if (_resetState)</span></a>
+<a name="137"><span class="lineNum">     137 </span><span class="lineCov">      30128 :         _resetSet &lt;= 8'(_resetSet + 8'h1);</span></a>
+<a name="138"><span class="lineNum">     138 </span><span class="lineCov">      33598 :       if (realRen | rdata_last_r)</span></a>
+<a name="139"><span class="lineNum">     139 </span><span class="lineCov">      16799 :         rdata_last_r &lt;= realRen;</span></a>
+<a name="140"><span class="lineNum">     140 </span>            :     end</a>
+<a name="141"><span class="lineNum">     141 </span>            :   end // always @(posedge, posedge)</a>
+<a name="142"><span class="lineNum">     142 </span><span class="lineCov">     510776 :   always @(posedge clock) begin</span></a>
+<a name="143"><span class="lineNum">     143 </span><span class="lineCov">      33238 :     if (rdata_last_r) begin</span></a>
+<a name="144"><span class="lineNum">     144 </span><span class="lineCov">      16619 :       rdata_hold_data_0 &lt;= _array_RW0_rdata[0];</span></a>
+<a name="145"><span class="lineNum">     145 </span><span class="lineCov">      16619 :       rdata_hold_data_1 &lt;= _array_RW0_rdata[1];</span></a>
+<a name="146"><span class="lineNum">     146 </span><span class="lineCov">      16619 :       rdata_hold_data_2 &lt;= _array_RW0_rdata[2];</span></a>
+<a name="147"><span class="lineNum">     147 </span><span class="lineCov">      16619 :       rdata_hold_data_3 &lt;= _array_RW0_rdata[3];</span></a>
+<a name="148"><span class="lineNum">     148 </span><span class="lineCov">      16619 :       rdata_hold_data_4 &lt;= _array_RW0_rdata[4];</span></a>
+<a name="149"><span class="lineNum">     149 </span><span class="lineCov">      16619 :       rdata_hold_data_5 &lt;= _array_RW0_rdata[5];</span></a>
+<a name="150"><span class="lineNum">     150 </span><span class="lineCov">      16619 :       rdata_hold_data_6 &lt;= _array_RW0_rdata[6];</span></a>
+<a name="151"><span class="lineNum">     151 </span><span class="lineCov">      16619 :       rdata_hold_data_7 &lt;= _array_RW0_rdata[7];</span></a>
+<a name="152"><span class="lineNum">     152 </span><span class="lineCov">      16619 :       rdata_hold_data_8 &lt;= _array_RW0_rdata[8];</span></a>
+<a name="153"><span class="lineNum">     153 </span><span class="lineCov">      16619 :       rdata_hold_data_9 &lt;= _array_RW0_rdata[9];</span></a>
+<a name="154"><span class="lineNum">     154 </span><span class="lineCov">      16619 :       rdata_hold_data_10 &lt;= _array_RW0_rdata[10];</span></a>
+<a name="155"><span class="lineNum">     155 </span><span class="lineCov">      16619 :       rdata_hold_data_11 &lt;= _array_RW0_rdata[11];</span></a>
+<a name="156"><span class="lineNum">     156 </span><span class="lineCov">      16619 :       rdata_hold_data_12 &lt;= _array_RW0_rdata[12];</span></a>
+<a name="157"><span class="lineNum">     157 </span><span class="lineCov">      16619 :       rdata_hold_data_13 &lt;= _array_RW0_rdata[13];</span></a>
+<a name="158"><span class="lineNum">     158 </span><span class="lineCov">      16619 :       rdata_hold_data_14 &lt;= _array_RW0_rdata[14];</span></a>
+<a name="159"><span class="lineNum">     159 </span><span class="lineCov">      16619 :       rdata_hold_data_15 &lt;= _array_RW0_rdata[15];</span></a>
+<a name="160"><span class="lineNum">     160 </span>            :     end</a>
+<a name="161"><span class="lineNum">     161 </span>            :   end // always @(posedge)</a>
+<a name="162"><span class="lineNum">     162 </span>            :   `ifdef ENABLE_INITIAL_REG_</a>
+<a name="163"><span class="lineNum">     163 </span>            :     `ifdef FIRRTL_BEFORE_INITIAL</a>
+<a name="164"><span class="lineNum">     164 </span>            :       `FIRRTL_BEFORE_INITIAL</a>
+<a name="165"><span class="lineNum">     165 </span>            :     `endif // FIRRTL_BEFORE_INITIAL</a>
+<a name="166"><span class="lineNum">     166 </span>            :     logic [31:0] _RANDOM[0:33];</a>
+<a name="167"><span class="lineNum">     167 </span><span class="lineCov">        232 :     initial begin</span></a>
+<a name="168"><span class="lineNum">     168 </span>            :       `ifdef INIT_RANDOM_PROLOG_</a>
+<a name="169"><span class="lineNum">     169 </span>            :         `INIT_RANDOM_PROLOG_</a>
+<a name="170"><span class="lineNum">     170 </span>            :       `endif // INIT_RANDOM_PROLOG_</a>
+<a name="171"><span class="lineNum">     171 </span>            :       `ifdef RANDOMIZE_REG_INIT</a>
+<a name="172"><span class="lineNum">     172 </span>            :         for (logic [5:0] i = 6'h0; i &lt; 6'h22; i += 6'h1) begin</a>
+<a name="173"><span class="lineNum">     173 </span>            :           _RANDOM[i] = `RANDOM;</a>
+<a name="174"><span class="lineNum">     174 </span>            :         end</a>
+<a name="175"><span class="lineNum">     175 </span>            :         _resetState = _RANDOM[6'h0][0];</a>
+<a name="176"><span class="lineNum">     176 </span>            :         _resetSet = _RANDOM[6'h0][8:1];</a>
+<a name="177"><span class="lineNum">     177 </span>            :         rdata_last_r = _RANDOM[6'h21][10];</a>
+<a name="178"><span class="lineNum">     178 </span>            :         rdata_hold_data_0 = _RANDOM[6'h21][11];</a>
+<a name="179"><span class="lineNum">     179 </span>            :         rdata_hold_data_1 = _RANDOM[6'h21][12];</a>
+<a name="180"><span class="lineNum">     180 </span>            :         rdata_hold_data_2 = _RANDOM[6'h21][13];</a>
+<a name="181"><span class="lineNum">     181 </span>            :         rdata_hold_data_3 = _RANDOM[6'h21][14];</a>
+<a name="182"><span class="lineNum">     182 </span>            :         rdata_hold_data_4 = _RANDOM[6'h21][15];</a>
+<a name="183"><span class="lineNum">     183 </span>            :         rdata_hold_data_5 = _RANDOM[6'h21][16];</a>
+<a name="184"><span class="lineNum">     184 </span>            :         rdata_hold_data_6 = _RANDOM[6'h21][17];</a>
+<a name="185"><span class="lineNum">     185 </span>            :         rdata_hold_data_7 = _RANDOM[6'h21][18];</a>
+<a name="186"><span class="lineNum">     186 </span>            :         rdata_hold_data_8 = _RANDOM[6'h21][19];</a>
+<a name="187"><span class="lineNum">     187 </span>            :         rdata_hold_data_9 = _RANDOM[6'h21][20];</a>
+<a name="188"><span class="lineNum">     188 </span>            :         rdata_hold_data_10 = _RANDOM[6'h21][21];</a>
+<a name="189"><span class="lineNum">     189 </span>            :         rdata_hold_data_11 = _RANDOM[6'h21][22];</a>
+<a name="190"><span class="lineNum">     190 </span>            :         rdata_hold_data_12 = _RANDOM[6'h21][23];</a>
+<a name="191"><span class="lineNum">     191 </span>            :         rdata_hold_data_13 = _RANDOM[6'h21][24];</a>
+<a name="192"><span class="lineNum">     192 </span>            :         rdata_hold_data_14 = _RANDOM[6'h21][25];</a>
+<a name="193"><span class="lineNum">     193 </span>            :         rdata_hold_data_15 = _RANDOM[6'h21][26];</a>
+<a name="194"><span class="lineNum">     194 </span>            :       `endif // RANDOMIZE_REG_INIT</a>
+<a name="195"><span class="lineNum">     195 </span><span class="lineCov">         68 :       if (reset) begin</span></a>
+<a name="196"><span class="lineNum">     196 </span><span class="lineCov">         48 :         _resetState = 1'h1;</span></a>
+<a name="197"><span class="lineNum">     197 </span><span class="lineCov">         48 :         _resetSet = 8'h0;</span></a>
+<a name="198"><span class="lineNum">     198 </span><span class="lineCov">         48 :         rdata_last_r = 1'h0;</span></a>
+<a name="199"><span class="lineNum">     199 </span>            :       end</a>
+<a name="200"><span class="lineNum">     200 </span>            :     end // initial</a>
+<a name="201"><span class="lineNum">     201 </span>            :     `ifdef FIRRTL_AFTER_INITIAL</a>
+<a name="202"><span class="lineNum">     202 </span>            :       `FIRRTL_AFTER_INITIAL</a>
+<a name="203"><span class="lineNum">     203 </span>            :     `endif // FIRRTL_AFTER_INITIAL</a>
+<a name="204"><span class="lineNum">     204 </span>            :   `endif // ENABLE_INITIAL_REG_</a>
+<a name="205"><span class="lineNum">     205 </span>            :   array_4 array (</a>
+<a name="206"><span class="lineNum">     206 </span>            :     .RW0_addr  (wen ? setIdx : io_r_req_bits_setIdx),</a>
+<a name="207"><span class="lineNum">     207 </span>            :     .RW0_en    (realRen | wen),</a>
+<a name="208"><span class="lineNum">     208 </span>            :     .RW0_clk   (clock),</a>
+<a name="209"><span class="lineNum">     209 </span>            :     .RW0_wmode (wen),</a>
+<a name="210"><span class="lineNum">     210 </span>            :     .RW0_wdata</a>
+<a name="211"><span class="lineNum">     211 </span>            :       ({~_resetState &amp; io_w_req_bits_data_15,</a>
+<a name="212"><span class="lineNum">     212 </span>            :         ~_resetState &amp; io_w_req_bits_data_14,</a>
+<a name="213"><span class="lineNum">     213 </span>            :         ~_resetState &amp; io_w_req_bits_data_13,</a>
+<a name="214"><span class="lineNum">     214 </span>            :         ~_resetState &amp; io_w_req_bits_data_12,</a>
+<a name="215"><span class="lineNum">     215 </span>            :         ~_resetState &amp; io_w_req_bits_data_11,</a>
+<a name="216"><span class="lineNum">     216 </span>            :         ~_resetState &amp; io_w_req_bits_data_10,</a>
+<a name="217"><span class="lineNum">     217 </span>            :         ~_resetState &amp; io_w_req_bits_data_9,</a>
+<a name="218"><span class="lineNum">     218 </span>            :         ~_resetState &amp; io_w_req_bits_data_8,</a>
+<a name="219"><span class="lineNum">     219 </span>            :         ~_resetState &amp; io_w_req_bits_data_7,</a>
+<a name="220"><span class="lineNum">     220 </span>            :         ~_resetState &amp; io_w_req_bits_data_6,</a>
+<a name="221"><span class="lineNum">     221 </span>            :         ~_resetState &amp; io_w_req_bits_data_5,</a>
+<a name="222"><span class="lineNum">     222 </span>            :         ~_resetState &amp; io_w_req_bits_data_4,</a>
+<a name="223"><span class="lineNum">     223 </span>            :         ~_resetState &amp; io_w_req_bits_data_3,</a>
+<a name="224"><span class="lineNum">     224 </span>            :         ~_resetState &amp; io_w_req_bits_data_2,</a>
+<a name="225"><span class="lineNum">     225 </span>            :         ~_resetState &amp; io_w_req_bits_data_1,</a>
+<a name="226"><span class="lineNum">     226 </span>            :         ~_resetState &amp; io_w_req_bits_data_0}),</a>
+<a name="227"><span class="lineNum">     227 </span>            :     .RW0_rdata (_array_RW0_rdata),</a>
+<a name="228"><span class="lineNum">     228 </span>            :     .RW0_wmask (_resetState ? 16'hFFFF : io_w_req_bits_waymask)</a>
+<a name="229"><span class="lineNum">     229 </span>            :   );</a>
+<a name="230"><span class="lineNum">     230 </span>            :   assign io_r_req_ready = ~_resetState &amp; ~wen;</a>
+<a name="231"><span class="lineNum">     231 </span>            :   assign io_r_resp_data_0 = rdata_last_r ? _array_RW0_rdata[0] : rdata_hold_data_0;</a>
+<a name="232"><span class="lineNum">     232 </span>            :   assign io_r_resp_data_1 = rdata_last_r ? _array_RW0_rdata[1] : rdata_hold_data_1;</a>
+<a name="233"><span class="lineNum">     233 </span>            :   assign io_r_resp_data_2 = rdata_last_r ? _array_RW0_rdata[2] : rdata_hold_data_2;</a>
+<a name="234"><span class="lineNum">     234 </span>            :   assign io_r_resp_data_3 = rdata_last_r ? _array_RW0_rdata[3] : rdata_hold_data_3;</a>
+<a name="235"><span class="lineNum">     235 </span>            :   assign io_r_resp_data_4 = rdata_last_r ? _array_RW0_rdata[4] : rdata_hold_data_4;</a>
+<a name="236"><span class="lineNum">     236 </span>            :   assign io_r_resp_data_5 = rdata_last_r ? _array_RW0_rdata[5] : rdata_hold_data_5;</a>
+<a name="237"><span class="lineNum">     237 </span>            :   assign io_r_resp_data_6 = rdata_last_r ? _array_RW0_rdata[6] : rdata_hold_data_6;</a>
+<a name="238"><span class="lineNum">     238 </span>            :   assign io_r_resp_data_7 = rdata_last_r ? _array_RW0_rdata[7] : rdata_hold_data_7;</a>
+<a name="239"><span class="lineNum">     239 </span>            :   assign io_r_resp_data_8 = rdata_last_r ? _array_RW0_rdata[8] : rdata_hold_data_8;</a>
+<a name="240"><span class="lineNum">     240 </span>            :   assign io_r_resp_data_9 = rdata_last_r ? _array_RW0_rdata[9] : rdata_hold_data_9;</a>
+<a name="241"><span class="lineNum">     241 </span>            :   assign io_r_resp_data_10 = rdata_last_r ? _array_RW0_rdata[10] : rdata_hold_data_10;</a>
+<a name="242"><span class="lineNum">     242 </span>            :   assign io_r_resp_data_11 = rdata_last_r ? _array_RW0_rdata[11] : rdata_hold_data_11;</a>
+<a name="243"><span class="lineNum">     243 </span>            :   assign io_r_resp_data_12 = rdata_last_r ? _array_RW0_rdata[12] : rdata_hold_data_12;</a>
+<a name="244"><span class="lineNum">     244 </span>            :   assign io_r_resp_data_13 = rdata_last_r ? _array_RW0_rdata[13] : rdata_hold_data_13;</a>
+<a name="245"><span class="lineNum">     245 </span>            :   assign io_r_resp_data_14 = rdata_last_r ? _array_RW0_rdata[14] : rdata_hold_data_14;</a>
+<a name="246"><span class="lineNum">     246 </span>            :   assign io_r_resp_data_15 = rdata_last_r ? _array_RW0_rdata[15] : rdata_hold_data_15;</a>
+<a name="247"><span class="lineNum">     247 </span>            : endmodule</a>
+<a name="248"><span class="lineNum">     248 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SRAMTemplate_15.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SRAMTemplate_15.sv.func-sort-c.html
new file mode 100644
index 0000000..fff3ec4
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SRAMTemplate_15.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/SRAMTemplate_15.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - SRAMTemplate_15.sv<span style="font-size: 80%;"> (<a href="SRAMTemplate_15.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">44</td>
+            <td class="headerCovTableEntry">44</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="SRAMTemplate_15.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SRAMTemplate_15.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SRAMTemplate_15.sv.func.html
new file mode 100644
index 0000000..70127ac
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SRAMTemplate_15.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/SRAMTemplate_15.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - SRAMTemplate_15.sv<span style="font-size: 80%;"> (<a href="SRAMTemplate_15.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">44</td>
+            <td class="headerCovTableEntry">44</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="SRAMTemplate_15.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
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+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SRAMTemplate_15.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SRAMTemplate_15.sv.gcov.html
new file mode 100644
index 0000000..4eca1a8
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SRAMTemplate_15.sv.gcov.html
@@ -0,0 +1,241 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
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+<html lang="en">
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+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/SRAMTemplate_15.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - SRAMTemplate_15.sv<span style="font-size: 80%;"> (source / <a href="SRAMTemplate_15.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">44</td>
+            <td class="headerCovTableEntry">44</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : module SRAMTemplate_15(</a>
+<a name="59"><span class="lineNum">      59 </span><span class="lineCov">     127786 :   input        clock,</span></a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">         62 :   input        reset,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">        883 :   output       io_r_req_ready,</span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">        630 :   input        io_r_req_valid,</span></a>
+<a name="63"><span class="lineNum">      63 </span><span class="lineCov">      26102 :   input  [8:0] io_r_req_bits_setIdx,</span></a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">        341 :   output       io_r_resp_data_0_valid,</span></a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">       2670 :   output [7:0] io_r_resp_data_0_tag,</span></a>
+<a name="66"><span class="lineNum">      66 </span><span class="lineCov">       1013 :   output [2:0] io_r_resp_data_0_ctr,</span></a>
+<a name="67"><span class="lineNum">      67 </span><span class="lineCov">        339 :   output       io_r_resp_data_1_valid,</span></a>
+<a name="68"><span class="lineNum">      68 </span><span class="lineCov">       2650 :   output [7:0] io_r_resp_data_1_tag,</span></a>
+<a name="69"><span class="lineNum">      69 </span><span class="lineCov">       1006 :   output [2:0] io_r_resp_data_1_ctr,</span></a>
+<a name="70"><span class="lineNum">      70 </span><span class="lineCov">        331 :   input        io_w_req_valid,</span></a>
+<a name="71"><span class="lineNum">      71 </span><span class="lineCov">        261 :   input  [8:0] io_w_req_bits_setIdx,</span></a>
+<a name="72"><span class="lineNum">      72 </span><span class="lineCov">        123 :   input  [7:0] io_w_req_bits_data_0_tag,</span></a>
+<a name="73"><span class="lineNum">      73 </span><span class="lineCov">         41 :   input  [2:0] io_w_req_bits_data_0_ctr,</span></a>
+<a name="74"><span class="lineNum">      74 </span><span class="lineCov">        123 :   input  [7:0] io_w_req_bits_data_1_tag,</span></a>
+<a name="75"><span class="lineNum">      75 </span><span class="lineCov">         45 :   input  [2:0] io_w_req_bits_data_1_ctr,</span></a>
+<a name="76"><span class="lineNum">      76 </span><span class="lineCov">         63 :   input  [1:0] io_w_req_bits_waymask</span></a>
+<a name="77"><span class="lineNum">      77 </span>            : );</a>
+<a name="78"><span class="lineNum">      78 </span>            : </a>
+<a name="79"><span class="lineNum">      79 </span><span class="lineCov">     478847 :   wire [8:0]  setIdx;</span></a>
+<a name="80"><span class="lineNum">      80 </span><span class="lineCov">        627 :   wire        realRen;</span></a>
+<a name="81"><span class="lineNum">      81 </span><span class="lineCov">        872 :   wire        wen;</span></a>
+<a name="82"><span class="lineNum">      82 </span>            :   wire [23:0] _array_RW0_rdata;</a>
+<a name="83"><span class="lineNum">      83 </span>            :   reg         _resetState;</a>
+<a name="84"><span class="lineNum">      84 </span>            :   reg  [8:0]  _resetSet;</a>
+<a name="85"><span class="lineNum">      85 </span>            :   assign wen = io_w_req_valid | _resetState;</a>
+<a name="86"><span class="lineNum">      86 </span>            :   assign realRen = io_r_req_valid &amp; ~wen;</a>
+<a name="87"><span class="lineNum">      87 </span>            :   assign setIdx = _resetState ? _resetSet : io_w_req_bits_setIdx;</a>
+<a name="88"><span class="lineNum">      88 </span><span class="lineCov">        767 :   reg         rdata_last_r;</span></a>
+<a name="89"><span class="lineNum">      89 </span><span class="lineCov">       4860 :   reg  [11:0] rdata_hold_data_0;</span></a>
+<a name="90"><span class="lineNum">      90 </span><span class="lineCov">       4748 :   reg  [11:0] rdata_hold_data_1;</span></a>
+<a name="91"><span class="lineNum">      91 </span>            :   wire [11:0] _rdata_T_0 = rdata_last_r ? _array_RW0_rdata[11:0] : rdata_hold_data_0;</a>
+<a name="92"><span class="lineNum">      92 </span>            :   wire [11:0] _rdata_T_1 = rdata_last_r ? _array_RW0_rdata[23:12] : rdata_hold_data_1;</a>
+<a name="93"><span class="lineNum">      93 </span><span class="lineCov">    2043680 :   always @(posedge clock or posedge reset) begin</span></a>
+<a name="94"><span class="lineNum">      94 </span><span class="lineCov">       4352 :     if (reset) begin</span></a>
+<a name="95"><span class="lineNum">      95 </span><span class="lineCov">       2176 :       _resetState &lt;= 1'h1;</span></a>
+<a name="96"><span class="lineNum">      96 </span><span class="lineCov">       2176 :       _resetSet &lt;= 9'h0;</span></a>
+<a name="97"><span class="lineNum">      97 </span><span class="lineCov">       2176 :       rdata_last_r &lt;= 1'h0;</span></a>
+<a name="98"><span class="lineNum">      98 </span>            :     end</a>
+<a name="99"><span class="lineNum">      99 </span><span class="lineCov">    1019664 :     else begin</span></a>
+<a name="100"><span class="lineNum">     100 </span><span class="lineCov">    1019664 :       _resetState &lt;= ~(_resetState &amp; (&amp;_resetSet)) &amp; _resetState;</span></a>
+<a name="101"><span class="lineNum">     101 </span><span class="lineCov">     478514 :       if (_resetState)</span></a>
+<a name="102"><span class="lineNum">     102 </span><span class="lineCov">     239257 :         _resetSet &lt;= 9'(_resetSet + 9'h1);</span></a>
+<a name="103"><span class="lineNum">     103 </span><span class="lineCov">      33968 :       if (realRen | rdata_last_r)</span></a>
+<a name="104"><span class="lineNum">     104 </span><span class="lineCov">      16984 :         rdata_last_r &lt;= realRen;</span></a>
+<a name="105"><span class="lineNum">     105 </span>            :     end</a>
+<a name="106"><span class="lineNum">     106 </span>            :   end // always @(posedge, posedge)</a>
+<a name="107"><span class="lineNum">     107 </span><span class="lineCov">    2043104 :   always @(posedge clock) begin</span></a>
+<a name="108"><span class="lineNum">     108 </span><span class="lineCov">      33448 :     if (rdata_last_r) begin</span></a>
+<a name="109"><span class="lineNum">     109 </span><span class="lineCov">      16724 :       rdata_hold_data_0 &lt;= _array_RW0_rdata[11:0];</span></a>
+<a name="110"><span class="lineNum">     110 </span><span class="lineCov">      16724 :       rdata_hold_data_1 &lt;= _array_RW0_rdata[23:12];</span></a>
+<a name="111"><span class="lineNum">     111 </span>            :     end</a>
+<a name="112"><span class="lineNum">     112 </span>            :   end // always @(posedge)</a>
+<a name="113"><span class="lineNum">     113 </span>            :   `ifdef ENABLE_INITIAL_REG_</a>
+<a name="114"><span class="lineNum">     114 </span>            :     `ifdef FIRRTL_BEFORE_INITIAL</a>
+<a name="115"><span class="lineNum">     115 </span>            :       `FIRRTL_BEFORE_INITIAL</a>
+<a name="116"><span class="lineNum">     116 </span>            :     `endif // FIRRTL_BEFORE_INITIAL</a>
+<a name="117"><span class="lineNum">     117 </span>            :     logic [31:0] _RANDOM[0:5];</a>
+<a name="118"><span class="lineNum">     118 </span><span class="lineCov">        928 :     initial begin</span></a>
+<a name="119"><span class="lineNum">     119 </span>            :       `ifdef INIT_RANDOM_PROLOG_</a>
+<a name="120"><span class="lineNum">     120 </span>            :         `INIT_RANDOM_PROLOG_</a>
+<a name="121"><span class="lineNum">     121 </span>            :       `endif // INIT_RANDOM_PROLOG_</a>
+<a name="122"><span class="lineNum">     122 </span>            :       `ifdef RANDOMIZE_REG_INIT</a>
+<a name="123"><span class="lineNum">     123 </span>            :         for (logic [2:0] i = 3'h0; i &lt; 3'h6; i += 3'h1) begin</a>
+<a name="124"><span class="lineNum">     124 </span>            :           _RANDOM[i] = `RANDOM;</a>
+<a name="125"><span class="lineNum">     125 </span>            :         end</a>
+<a name="126"><span class="lineNum">     126 </span>            :         _resetState = _RANDOM[3'h0][0];</a>
+<a name="127"><span class="lineNum">     127 </span>            :         _resetSet = _RANDOM[3'h0][9:1];</a>
+<a name="128"><span class="lineNum">     128 </span>            :         rdata_last_r = _RANDOM[3'h4][31];</a>
+<a name="129"><span class="lineNum">     129 </span>            :         rdata_hold_data_0 = _RANDOM[3'h5][11:0];</a>
+<a name="130"><span class="lineNum">     130 </span>            :         rdata_hold_data_1 = _RANDOM[3'h5][23:12];</a>
+<a name="131"><span class="lineNum">     131 </span>            :       `endif // RANDOMIZE_REG_INIT</a>
+<a name="132"><span class="lineNum">     132 </span><span class="lineCov">        272 :       if (reset) begin</span></a>
+<a name="133"><span class="lineNum">     133 </span><span class="lineCov">        192 :         _resetState = 1'h1;</span></a>
+<a name="134"><span class="lineNum">     134 </span><span class="lineCov">        192 :         _resetSet = 9'h0;</span></a>
+<a name="135"><span class="lineNum">     135 </span><span class="lineCov">        192 :         rdata_last_r = 1'h0;</span></a>
+<a name="136"><span class="lineNum">     136 </span>            :       end</a>
+<a name="137"><span class="lineNum">     137 </span>            :     end // initial</a>
+<a name="138"><span class="lineNum">     138 </span>            :     `ifdef FIRRTL_AFTER_INITIAL</a>
+<a name="139"><span class="lineNum">     139 </span>            :       `FIRRTL_AFTER_INITIAL</a>
+<a name="140"><span class="lineNum">     140 </span>            :     `endif // FIRRTL_AFTER_INITIAL</a>
+<a name="141"><span class="lineNum">     141 </span>            :   `endif // ENABLE_INITIAL_REG_</a>
+<a name="142"><span class="lineNum">     142 </span>            :   array_5 array (</a>
+<a name="143"><span class="lineNum">     143 </span>            :     .RW0_addr  (wen ? setIdx : io_r_req_bits_setIdx),</a>
+<a name="144"><span class="lineNum">     144 </span>            :     .RW0_en    (realRen | wen),</a>
+<a name="145"><span class="lineNum">     145 </span>            :     .RW0_clk   (clock),</a>
+<a name="146"><span class="lineNum">     146 </span>            :     .RW0_wmode (wen),</a>
+<a name="147"><span class="lineNum">     147 </span>            :     .RW0_wdata</a>
+<a name="148"><span class="lineNum">     148 </span>            :       ({~_resetState,</a>
+<a name="149"><span class="lineNum">     149 </span>            :         _resetState ? 8'h0 : io_w_req_bits_data_1_tag,</a>
+<a name="150"><span class="lineNum">     150 </span>            :         _resetState ? 3'h0 : io_w_req_bits_data_1_ctr,</a>
+<a name="151"><span class="lineNum">     151 </span>            :         ~_resetState,</a>
+<a name="152"><span class="lineNum">     152 </span>            :         _resetState ? 8'h0 : io_w_req_bits_data_0_tag,</a>
+<a name="153"><span class="lineNum">     153 </span>            :         _resetState ? 3'h0 : io_w_req_bits_data_0_ctr}),</a>
+<a name="154"><span class="lineNum">     154 </span>            :     .RW0_rdata (_array_RW0_rdata),</a>
+<a name="155"><span class="lineNum">     155 </span>            :     .RW0_wmask (_resetState ? 2'h3 : io_w_req_bits_waymask)</a>
+<a name="156"><span class="lineNum">     156 </span>            :   );</a>
+<a name="157"><span class="lineNum">     157 </span>            :   assign io_r_req_ready = ~_resetState &amp; ~wen;</a>
+<a name="158"><span class="lineNum">     158 </span>            :   assign io_r_resp_data_0_valid = _rdata_T_0[11];</a>
+<a name="159"><span class="lineNum">     159 </span>            :   assign io_r_resp_data_0_tag = _rdata_T_0[10:3];</a>
+<a name="160"><span class="lineNum">     160 </span>            :   assign io_r_resp_data_0_ctr = _rdata_T_0[2:0];</a>
+<a name="161"><span class="lineNum">     161 </span>            :   assign io_r_resp_data_1_valid = _rdata_T_1[11];</a>
+<a name="162"><span class="lineNum">     162 </span>            :   assign io_r_resp_data_1_tag = _rdata_T_1[10:3];</a>
+<a name="163"><span class="lineNum">     163 </span>            :   assign io_r_resp_data_1_ctr = _rdata_T_1[2:0];</a>
+<a name="164"><span class="lineNum">     164 </span>            : endmodule</a>
+<a name="165"><span class="lineNum">     165 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SRAMTemplate_34.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SRAMTemplate_34.sv.func-sort-c.html
new file mode 100644
index 0000000..6c5f8ff
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SRAMTemplate_34.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/SRAMTemplate_34.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - SRAMTemplate_34.sv<span style="font-size: 80%;"> (<a href="SRAMTemplate_34.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">77</td>
+            <td class="headerCovTableEntry">90</td>
+            <td class="headerCovTableEntryMed">85.6 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="SRAMTemplate_34.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SRAMTemplate_34.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SRAMTemplate_34.sv.func.html
new file mode 100644
index 0000000..23add38
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SRAMTemplate_34.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/SRAMTemplate_34.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - SRAMTemplate_34.sv<span style="font-size: 80%;"> (<a href="SRAMTemplate_34.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">77</td>
+            <td class="headerCovTableEntry">90</td>
+            <td class="headerCovTableEntryMed">85.6 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="SRAMTemplate_34.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SRAMTemplate_34.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SRAMTemplate_34.sv.gcov.html
new file mode 100644
index 0000000..1eb76a0
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SRAMTemplate_34.sv.gcov.html
@@ -0,0 +1,305 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/SRAMTemplate_34.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - SRAMTemplate_34.sv<span style="font-size: 80%;"> (source / <a href="SRAMTemplate_34.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">77</td>
+            <td class="headerCovTableEntry">90</td>
+            <td class="headerCovTableEntryMed">85.6 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : module SRAMTemplate_34(</a>
+<a name="59"><span class="lineNum">      59 </span><span class="lineCov">     127786 :   input        clock,</span></a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">         62 :   input        reset,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">         76 :   input        io_r_req_valid,</span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">       8636 :   input  [8:0] io_r_req_bits_setIdx,</span></a>
+<a name="63"><span class="lineNum">      63 </span><span class="lineCov">         62 :   output [1:0] io_r_resp_data_0,</span></a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">         59 :   output [1:0] io_r_resp_data_1,</span></a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">         62 :   output [1:0] io_r_resp_data_2,</span></a>
+<a name="66"><span class="lineNum">      66 </span><span class="lineCov">         49 :   output [1:0] io_r_resp_data_3,</span></a>
+<a name="67"><span class="lineNum">      67 </span><span class="lineCov">         65 :   output [1:0] io_r_resp_data_4,</span></a>
+<a name="68"><span class="lineNum">      68 </span><span class="lineCov">         56 :   output [1:0] io_r_resp_data_5,</span></a>
+<a name="69"><span class="lineNum">      69 </span><span class="lineCov">         58 :   output [1:0] io_r_resp_data_6,</span></a>
+<a name="70"><span class="lineNum">      70 </span><span class="lineCov">         62 :   output [1:0] io_r_resp_data_7,</span></a>
+<a name="71"><span class="lineNum">      71 </span><span class="lineCov">         59 :   input        io_w_req_valid,</span></a>
+<a name="72"><span class="lineNum">      72 </span><span class="lineCov">      29781 :   input  [8:0] io_w_req_bits_setIdx,</span></a>
+<a name="73"><span class="lineNum">      73 </span><span class="lineCov">         76 :   input  [1:0] io_w_req_bits_data_0,</span></a>
+<a name="74"><span class="lineNum">      74 </span><span class="lineCov">         64 :   input  [1:0] io_w_req_bits_data_1,</span></a>
+<a name="75"><span class="lineNum">      75 </span><span class="lineCov">         76 :   input  [1:0] io_w_req_bits_data_2,</span></a>
+<a name="76"><span class="lineNum">      76 </span><span class="lineCov">         64 :   input  [1:0] io_w_req_bits_data_3,</span></a>
+<a name="77"><span class="lineNum">      77 </span><span class="lineCov">         76 :   input  [1:0] io_w_req_bits_data_4,</span></a>
+<a name="78"><span class="lineNum">      78 </span><span class="lineCov">         64 :   input  [1:0] io_w_req_bits_data_5,</span></a>
+<a name="79"><span class="lineNum">      79 </span><span class="lineCov">         76 :   input  [1:0] io_w_req_bits_data_6,</span></a>
+<a name="80"><span class="lineNum">      80 </span><span class="lineCov">         64 :   input  [1:0] io_w_req_bits_data_7,</span></a>
+<a name="81"><span class="lineNum">      81 </span><span class="lineCov">     238101 :   input  [7:0] io_w_req_bits_waymask</span></a>
+<a name="82"><span class="lineNum">      82 </span>            : );</a>
+<a name="83"><span class="lineNum">      83 </span>            : </a>
+<a name="84"><span class="lineNum">      84 </span>            :   wire [15:0] _array_R0_data;</a>
+<a name="85"><span class="lineNum">      85 </span><span class="lineCov">         36 :   reg  [1:0]  bypass_wdata_r_0;</span></a>
+<a name="86"><span class="lineNum">      86 </span><span class="lineCov">         32 :   reg  [1:0]  bypass_wdata_r_1;</span></a>
+<a name="87"><span class="lineNum">      87 </span><span class="lineCov">         29 :   reg  [1:0]  bypass_wdata_r_2;</span></a>
+<a name="88"><span class="lineNum">      88 </span><span class="lineCov">         38 :   reg  [1:0]  bypass_wdata_r_3;</span></a>
+<a name="89"><span class="lineNum">      89 </span><span class="lineCov">         30 :   reg  [1:0]  bypass_wdata_r_4;</span></a>
+<a name="90"><span class="lineNum">      90 </span><span class="lineCov">         29 :   reg  [1:0]  bypass_wdata_r_5;</span></a>
+<a name="91"><span class="lineNum">      91 </span><span class="lineCov">         29 :   reg  [1:0]  bypass_wdata_r_6;</span></a>
+<a name="92"><span class="lineNum">      92 </span><span class="lineCov">         27 :   reg  [1:0]  bypass_wdata_r_7;</span></a>
+<a name="93"><span class="lineNum">      93 </span><span class="lineCov">         12 :   wire        bypass_mask_need_check = io_r_req_valid &amp; io_w_req_valid;</span></a>
+<a name="94"><span class="lineNum">      94 </span><span class="lineCov">         22 :   reg         bypass_mask_need_check_reg_last_r;</span></a>
+<a name="95"><span class="lineNum">      95 </span><span class="lineCov">        130 :   reg  [8:0]  bypass_mask_waddr_reg;</span></a>
+<a name="96"><span class="lineNum">      96 </span><span class="lineCov">        150 :   reg  [8:0]  bypass_mask_raddr_reg;</span></a>
+<a name="97"><span class="lineNum">      97 </span><span class="lineCov">        110 :   reg  [7:0]  bypass_mask_wmask_reg;</span></a>
+<a name="98"><span class="lineNum">      98 </span><span class="lineCov">        116 :   wire [7:0]  bypass_mask =</span></a>
+<a name="99"><span class="lineNum">      99 </span>            :     {8{bypass_mask_need_check_reg_last_r</a>
+<a name="100"><span class="lineNum">     100 </span>            :          &amp; bypass_mask_waddr_reg == bypass_mask_raddr_reg}} &amp; bypass_mask_wmask_reg;</a>
+<a name="101"><span class="lineNum">     101 </span><span class="lineCov">         61 :   wire [1:0]  mem_rdata_0 = bypass_mask[0] ? bypass_wdata_r_0 : _array_R0_data[1:0];</span></a>
+<a name="102"><span class="lineNum">     102 </span><span class="lineCov">         63 :   wire [1:0]  mem_rdata_1 = bypass_mask[1] ? bypass_wdata_r_1 : _array_R0_data[3:2];</span></a>
+<a name="103"><span class="lineNum">     103 </span><span class="lineCov">         46 :   wire [1:0]  mem_rdata_2 = bypass_mask[2] ? bypass_wdata_r_2 : _array_R0_data[5:4];</span></a>
+<a name="104"><span class="lineNum">     104 </span><span class="lineCov">         61 :   wire [1:0]  mem_rdata_3 = bypass_mask[3] ? bypass_wdata_r_3 : _array_R0_data[7:6];</span></a>
+<a name="105"><span class="lineNum">     105 </span><span class="lineCov">         68 :   wire [1:0]  mem_rdata_4 = bypass_mask[4] ? bypass_wdata_r_4 : _array_R0_data[9:8];</span></a>
+<a name="106"><span class="lineNum">     106 </span><span class="lineCov">         61 :   wire [1:0]  mem_rdata_5 = bypass_mask[5] ? bypass_wdata_r_5 : _array_R0_data[11:10];</span></a>
+<a name="107"><span class="lineNum">     107 </span><span class="lineCov">         60 :   wire [1:0]  mem_rdata_6 = bypass_mask[6] ? bypass_wdata_r_6 : _array_R0_data[13:12];</span></a>
+<a name="108"><span class="lineNum">     108 </span><span class="lineCov">         53 :   wire [1:0]  mem_rdata_7 = bypass_mask[7] ? bypass_wdata_r_7 : _array_R0_data[15:14];</span></a>
+<a name="109"><span class="lineNum">     109 </span><span class="lineCov">         85 :   reg         rdata_last_r;</span></a>
+<a name="110"><span class="lineNum">     110 </span><span class="lineCov">         63 :   reg  [1:0]  rdata_hold_data_0;</span></a>
+<a name="111"><span class="lineNum">     111 </span><span class="lineCov">         59 :   reg  [1:0]  rdata_hold_data_1;</span></a>
+<a name="112"><span class="lineNum">     112 </span><span class="lineCov">         68 :   reg  [1:0]  rdata_hold_data_2;</span></a>
+<a name="113"><span class="lineNum">     113 </span><span class="lineCov">         61 :   reg  [1:0]  rdata_hold_data_3;</span></a>
+<a name="114"><span class="lineNum">     114 </span><span class="lineCov">         77 :   reg  [1:0]  rdata_hold_data_4;</span></a>
+<a name="115"><span class="lineNum">     115 </span><span class="lineCov">         75 :   reg  [1:0]  rdata_hold_data_5;</span></a>
+<a name="116"><span class="lineNum">     116 </span><span class="lineCov">         71 :   reg  [1:0]  rdata_hold_data_6;</span></a>
+<a name="117"><span class="lineNum">     117 </span><span class="lineCov">         75 :   reg  [1:0]  rdata_hold_data_7;</span></a>
+<a name="118"><span class="lineNum">     118 </span><span class="lineCov">     127694 :   always @(posedge clock) begin</span></a>
+<a name="119"><span class="lineNum">     119 </span><span class="lineNoCov">          0 :     if (io_w_req_valid &amp; io_r_req_valid) begin</span></a>
+<a name="120"><span class="lineNum">     120 </span><span class="lineNoCov">          0 :       bypass_wdata_r_0 &lt;= io_w_req_bits_data_0;</span></a>
+<a name="121"><span class="lineNum">     121 </span><span class="lineNoCov">          0 :       bypass_wdata_r_1 &lt;= io_w_req_bits_data_1;</span></a>
+<a name="122"><span class="lineNum">     122 </span><span class="lineNoCov">          0 :       bypass_wdata_r_2 &lt;= io_w_req_bits_data_2;</span></a>
+<a name="123"><span class="lineNum">     123 </span><span class="lineNoCov">          0 :       bypass_wdata_r_3 &lt;= io_w_req_bits_data_3;</span></a>
+<a name="124"><span class="lineNum">     124 </span><span class="lineNoCov">          0 :       bypass_wdata_r_4 &lt;= io_w_req_bits_data_4;</span></a>
+<a name="125"><span class="lineNum">     125 </span><span class="lineNoCov">          0 :       bypass_wdata_r_5 &lt;= io_w_req_bits_data_5;</span></a>
+<a name="126"><span class="lineNum">     126 </span><span class="lineNoCov">          0 :       bypass_wdata_r_6 &lt;= io_w_req_bits_data_6;</span></a>
+<a name="127"><span class="lineNum">     127 </span><span class="lineNoCov">          0 :       bypass_wdata_r_7 &lt;= io_w_req_bits_data_7;</span></a>
+<a name="128"><span class="lineNum">     128 </span>            :     end</a>
+<a name="129"><span class="lineNum">     129 </span><span class="lineNoCov">          0 :     if (bypass_mask_need_check) begin</span></a>
+<a name="130"><span class="lineNum">     130 </span><span class="lineNoCov">          0 :       bypass_mask_waddr_reg &lt;= io_w_req_bits_setIdx;</span></a>
+<a name="131"><span class="lineNum">     131 </span><span class="lineNoCov">          0 :       bypass_mask_raddr_reg &lt;= io_r_req_bits_setIdx;</span></a>
+<a name="132"><span class="lineNum">     132 </span><span class="lineNoCov">          0 :       bypass_mask_wmask_reg &lt;= io_w_req_bits_waymask;</span></a>
+<a name="133"><span class="lineNum">     133 </span>            :     end</a>
+<a name="134"><span class="lineNum">     134 </span><span class="lineCov">       8312 :     if (rdata_last_r) begin</span></a>
+<a name="135"><span class="lineNum">     135 </span><span class="lineCov">       4156 :       rdata_hold_data_0 &lt;= mem_rdata_0;</span></a>
+<a name="136"><span class="lineNum">     136 </span><span class="lineCov">       4156 :       rdata_hold_data_1 &lt;= mem_rdata_1;</span></a>
+<a name="137"><span class="lineNum">     137 </span><span class="lineCov">       4156 :       rdata_hold_data_2 &lt;= mem_rdata_2;</span></a>
+<a name="138"><span class="lineNum">     138 </span><span class="lineCov">       4156 :       rdata_hold_data_3 &lt;= mem_rdata_3;</span></a>
+<a name="139"><span class="lineNum">     139 </span><span class="lineCov">       4156 :       rdata_hold_data_4 &lt;= mem_rdata_4;</span></a>
+<a name="140"><span class="lineNum">     140 </span><span class="lineCov">       4156 :       rdata_hold_data_5 &lt;= mem_rdata_5;</span></a>
+<a name="141"><span class="lineNum">     141 </span><span class="lineCov">       4156 :       rdata_hold_data_6 &lt;= mem_rdata_6;</span></a>
+<a name="142"><span class="lineNum">     142 </span><span class="lineCov">       4156 :       rdata_hold_data_7 &lt;= mem_rdata_7;</span></a>
+<a name="143"><span class="lineNum">     143 </span>            :     end</a>
+<a name="144"><span class="lineNum">     144 </span>            :   end // always @(posedge)</a>
+<a name="145"><span class="lineNum">     145 </span><span class="lineCov">     127730 :   always @(posedge clock or posedge reset) begin</span></a>
+<a name="146"><span class="lineNum">     146 </span><span class="lineCov">        272 :     if (reset) begin</span></a>
+<a name="147"><span class="lineNum">     147 </span><span class="lineCov">        136 :       bypass_mask_need_check_reg_last_r &lt;= 1'h0;</span></a>
+<a name="148"><span class="lineNum">     148 </span><span class="lineCov">        136 :       rdata_last_r &lt;= 1'h0;</span></a>
+<a name="149"><span class="lineNum">     149 </span>            :     end</a>
+<a name="150"><span class="lineNum">     150 </span><span class="lineCov">      63729 :     else begin</span></a>
+<a name="151"><span class="lineNum">     151 </span><span class="lineCov">         12 :       if (bypass_mask_need_check | bypass_mask_need_check_reg_last_r)</span></a>
+<a name="152"><span class="lineNum">     152 </span><span class="lineCov">          6 :         bypass_mask_need_check_reg_last_r &lt;= bypass_mask_need_check;</span></a>
+<a name="153"><span class="lineNum">     153 </span><span class="lineCov">       8402 :       if (io_r_req_valid | rdata_last_r)</span></a>
+<a name="154"><span class="lineNum">     154 </span><span class="lineCov">       4201 :         rdata_last_r &lt;= io_r_req_valid;</span></a>
+<a name="155"><span class="lineNum">     155 </span>            :     end</a>
+<a name="156"><span class="lineNum">     156 </span>            :   end // always @(posedge, posedge)</a>
+<a name="157"><span class="lineNum">     157 </span>            :   `ifdef ENABLE_INITIAL_REG_</a>
+<a name="158"><span class="lineNum">     158 </span>            :     `ifdef FIRRTL_BEFORE_INITIAL</a>
+<a name="159"><span class="lineNum">     159 </span>            :       `FIRRTL_BEFORE_INITIAL</a>
+<a name="160"><span class="lineNum">     160 </span>            :     `endif // FIRRTL_BEFORE_INITIAL</a>
+<a name="161"><span class="lineNum">     161 </span>            :     logic [31:0] _RANDOM[0:1];</a>
+<a name="162"><span class="lineNum">     162 </span><span class="lineCov">         58 :     initial begin</span></a>
+<a name="163"><span class="lineNum">     163 </span>            :       `ifdef INIT_RANDOM_PROLOG_</a>
+<a name="164"><span class="lineNum">     164 </span>            :         `INIT_RANDOM_PROLOG_</a>
+<a name="165"><span class="lineNum">     165 </span>            :       `endif // INIT_RANDOM_PROLOG_</a>
+<a name="166"><span class="lineNum">     166 </span>            :       `ifdef RANDOMIZE_REG_INIT</a>
+<a name="167"><span class="lineNum">     167 </span>            :         for (logic [1:0] i = 2'h0; i &lt; 2'h2; i += 2'h1) begin</a>
+<a name="168"><span class="lineNum">     168 </span>            :           _RANDOM[i[0]] = `RANDOM;</a>
+<a name="169"><span class="lineNum">     169 </span>            :         end</a>
+<a name="170"><span class="lineNum">     170 </span>            :         bypass_wdata_r_0 = _RANDOM[1'h0][1:0];</a>
+<a name="171"><span class="lineNum">     171 </span>            :         bypass_wdata_r_1 = _RANDOM[1'h0][3:2];</a>
+<a name="172"><span class="lineNum">     172 </span>            :         bypass_wdata_r_2 = _RANDOM[1'h0][5:4];</a>
+<a name="173"><span class="lineNum">     173 </span>            :         bypass_wdata_r_3 = _RANDOM[1'h0][7:6];</a>
+<a name="174"><span class="lineNum">     174 </span>            :         bypass_wdata_r_4 = _RANDOM[1'h0][9:8];</a>
+<a name="175"><span class="lineNum">     175 </span>            :         bypass_wdata_r_5 = _RANDOM[1'h0][11:10];</a>
+<a name="176"><span class="lineNum">     176 </span>            :         bypass_wdata_r_6 = _RANDOM[1'h0][13:12];</a>
+<a name="177"><span class="lineNum">     177 </span>            :         bypass_wdata_r_7 = _RANDOM[1'h0][15:14];</a>
+<a name="178"><span class="lineNum">     178 </span>            :         bypass_mask_need_check_reg_last_r = _RANDOM[1'h0][16];</a>
+<a name="179"><span class="lineNum">     179 </span>            :         bypass_mask_waddr_reg = _RANDOM[1'h0][25:17];</a>
+<a name="180"><span class="lineNum">     180 </span>            :         bypass_mask_raddr_reg = {_RANDOM[1'h0][31:26], _RANDOM[1'h1][2:0]};</a>
+<a name="181"><span class="lineNum">     181 </span>            :         bypass_mask_wmask_reg = _RANDOM[1'h1][10:3];</a>
+<a name="182"><span class="lineNum">     182 </span>            :         rdata_last_r = _RANDOM[1'h1][11];</a>
+<a name="183"><span class="lineNum">     183 </span>            :         rdata_hold_data_0 = _RANDOM[1'h1][13:12];</a>
+<a name="184"><span class="lineNum">     184 </span>            :         rdata_hold_data_1 = _RANDOM[1'h1][15:14];</a>
+<a name="185"><span class="lineNum">     185 </span>            :         rdata_hold_data_2 = _RANDOM[1'h1][17:16];</a>
+<a name="186"><span class="lineNum">     186 </span>            :         rdata_hold_data_3 = _RANDOM[1'h1][19:18];</a>
+<a name="187"><span class="lineNum">     187 </span>            :         rdata_hold_data_4 = _RANDOM[1'h1][21:20];</a>
+<a name="188"><span class="lineNum">     188 </span>            :         rdata_hold_data_5 = _RANDOM[1'h1][23:22];</a>
+<a name="189"><span class="lineNum">     189 </span>            :         rdata_hold_data_6 = _RANDOM[1'h1][25:24];</a>
+<a name="190"><span class="lineNum">     190 </span>            :         rdata_hold_data_7 = _RANDOM[1'h1][27:26];</a>
+<a name="191"><span class="lineNum">     191 </span>            :       `endif // RANDOMIZE_REG_INIT</a>
+<a name="192"><span class="lineNum">     192 </span><span class="lineCov">         17 :       if (reset) begin</span></a>
+<a name="193"><span class="lineNum">     193 </span><span class="lineCov">         12 :         bypass_mask_need_check_reg_last_r = 1'h0;</span></a>
+<a name="194"><span class="lineNum">     194 </span><span class="lineCov">         12 :         rdata_last_r = 1'h0;</span></a>
+<a name="195"><span class="lineNum">     195 </span>            :       end</a>
+<a name="196"><span class="lineNum">     196 </span>            :     end // initial</a>
+<a name="197"><span class="lineNum">     197 </span>            :     `ifdef FIRRTL_AFTER_INITIAL</a>
+<a name="198"><span class="lineNum">     198 </span>            :       `FIRRTL_AFTER_INITIAL</a>
+<a name="199"><span class="lineNum">     199 </span>            :     `endif // FIRRTL_AFTER_INITIAL</a>
+<a name="200"><span class="lineNum">     200 </span>            :   `endif // ENABLE_INITIAL_REG_</a>
+<a name="201"><span class="lineNum">     201 </span>            :   array_6 array (</a>
+<a name="202"><span class="lineNum">     202 </span>            :     .R0_addr (io_r_req_bits_setIdx),</a>
+<a name="203"><span class="lineNum">     203 </span>            :     .R0_en   (io_r_req_valid),</a>
+<a name="204"><span class="lineNum">     204 </span>            :     .R0_clk  (clock),</a>
+<a name="205"><span class="lineNum">     205 </span>            :     .R0_data (_array_R0_data),</a>
+<a name="206"><span class="lineNum">     206 </span>            :     .W0_addr (io_w_req_bits_setIdx),</a>
+<a name="207"><span class="lineNum">     207 </span>            :     .W0_en   (io_w_req_valid),</a>
+<a name="208"><span class="lineNum">     208 </span>            :     .W0_clk  (clock),</a>
+<a name="209"><span class="lineNum">     209 </span>            :     .W0_data</a>
+<a name="210"><span class="lineNum">     210 </span>            :       ({io_w_req_bits_data_7,</a>
+<a name="211"><span class="lineNum">     211 </span>            :         io_w_req_bits_data_6,</a>
+<a name="212"><span class="lineNum">     212 </span>            :         io_w_req_bits_data_5,</a>
+<a name="213"><span class="lineNum">     213 </span>            :         io_w_req_bits_data_4,</a>
+<a name="214"><span class="lineNum">     214 </span>            :         io_w_req_bits_data_3,</a>
+<a name="215"><span class="lineNum">     215 </span>            :         io_w_req_bits_data_2,</a>
+<a name="216"><span class="lineNum">     216 </span>            :         io_w_req_bits_data_1,</a>
+<a name="217"><span class="lineNum">     217 </span>            :         io_w_req_bits_data_0}),</a>
+<a name="218"><span class="lineNum">     218 </span>            :     .W0_mask (io_w_req_bits_waymask)</a>
+<a name="219"><span class="lineNum">     219 </span>            :   );</a>
+<a name="220"><span class="lineNum">     220 </span>            :   assign io_r_resp_data_0 = rdata_last_r ? mem_rdata_0 : rdata_hold_data_0;</a>
+<a name="221"><span class="lineNum">     221 </span>            :   assign io_r_resp_data_1 = rdata_last_r ? mem_rdata_1 : rdata_hold_data_1;</a>
+<a name="222"><span class="lineNum">     222 </span>            :   assign io_r_resp_data_2 = rdata_last_r ? mem_rdata_2 : rdata_hold_data_2;</a>
+<a name="223"><span class="lineNum">     223 </span>            :   assign io_r_resp_data_3 = rdata_last_r ? mem_rdata_3 : rdata_hold_data_3;</a>
+<a name="224"><span class="lineNum">     224 </span>            :   assign io_r_resp_data_4 = rdata_last_r ? mem_rdata_4 : rdata_hold_data_4;</a>
+<a name="225"><span class="lineNum">     225 </span>            :   assign io_r_resp_data_5 = rdata_last_r ? mem_rdata_5 : rdata_hold_data_5;</a>
+<a name="226"><span class="lineNum">     226 </span>            :   assign io_r_resp_data_6 = rdata_last_r ? mem_rdata_6 : rdata_hold_data_6;</a>
+<a name="227"><span class="lineNum">     227 </span>            :   assign io_r_resp_data_7 = rdata_last_r ? mem_rdata_7 : rdata_hold_data_7;</a>
+<a name="228"><span class="lineNum">     228 </span>            : endmodule</a>
+<a name="229"><span class="lineNum">     229 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SRAMTemplate_35.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SRAMTemplate_35.sv.func-sort-c.html
new file mode 100644
index 0000000..97dc734
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SRAMTemplate_35.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/SRAMTemplate_35.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - SRAMTemplate_35.sv<span style="font-size: 80%;"> (<a href="SRAMTemplate_35.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">60</td>
+            <td class="headerCovTableEntry">69</td>
+            <td class="headerCovTableEntryMed">87.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="SRAMTemplate_35.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SRAMTemplate_35.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SRAMTemplate_35.sv.func.html
new file mode 100644
index 0000000..ecc0292
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SRAMTemplate_35.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/SRAMTemplate_35.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - SRAMTemplate_35.sv<span style="font-size: 80%;"> (<a href="SRAMTemplate_35.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">60</td>
+            <td class="headerCovTableEntry">69</td>
+            <td class="headerCovTableEntryMed">87.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="SRAMTemplate_35.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SRAMTemplate_35.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SRAMTemplate_35.sv.gcov.html
new file mode 100644
index 0000000..f68a974
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SRAMTemplate_35.sv.gcov.html
@@ -0,0 +1,272 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/SRAMTemplate_35.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - SRAMTemplate_35.sv<span style="font-size: 80%;"> (source / <a href="SRAMTemplate_35.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">60</td>
+            <td class="headerCovTableEntry">69</td>
+            <td class="headerCovTableEntryMed">87.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : module SRAMTemplate_35(</a>
+<a name="59"><span class="lineNum">      59 </span><span class="lineCov">     127786 :   input        clock,</span></a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">         62 :   input        reset,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">         73 :   input        io_r_req_valid,</span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">      32986 :   input  [7:0] io_r_req_bits_setIdx,</span></a>
+<a name="63"><span class="lineNum">      63 </span><span class="lineCov">        641 :   output [5:0] io_r_resp_data_0,</span></a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">        677 :   output [5:0] io_r_resp_data_1,</span></a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">        697 :   output [5:0] io_r_resp_data_2,</span></a>
+<a name="66"><span class="lineNum">      66 </span><span class="lineCov">        680 :   output [5:0] io_r_resp_data_3,</span></a>
+<a name="67"><span class="lineNum">      67 </span><span class="lineCov">        150 :   input        io_w_req_valid,</span></a>
+<a name="68"><span class="lineNum">      68 </span><span class="lineCov">        131 :   input  [7:0] io_w_req_bits_setIdx,</span></a>
+<a name="69"><span class="lineNum">      69 </span><span class="lineCov">        101 :   input  [5:0] io_w_req_bits_data_0,</span></a>
+<a name="70"><span class="lineNum">      70 </span><span class="lineCov">        101 :   input  [5:0] io_w_req_bits_data_1,</span></a>
+<a name="71"><span class="lineNum">      71 </span><span class="lineCov">         97 :   input  [5:0] io_w_req_bits_data_2,</span></a>
+<a name="72"><span class="lineNum">      72 </span><span class="lineCov">         97 :   input  [5:0] io_w_req_bits_data_3,</span></a>
+<a name="73"><span class="lineNum">      73 </span><span class="lineCov">        354 :   input  [3:0] io_w_req_bits_waymask</span></a>
+<a name="74"><span class="lineNum">      74 </span>            : );</a>
+<a name="75"><span class="lineNum">      75 </span>            : </a>
+<a name="76"><span class="lineNum">      76 </span>            :   wire [23:0] _array_R0_data;</a>
+<a name="77"><span class="lineNum">      77 </span>            :   reg         _resetState;</a>
+<a name="78"><span class="lineNum">      78 </span>            :   reg  [7:0]  _resetSet;</a>
+<a name="79"><span class="lineNum">      79 </span><span class="lineCov">        349 :   reg  [5:0]  bypass_wdata_r_0;</span></a>
+<a name="80"><span class="lineNum">      80 </span><span class="lineCov">        351 :   reg  [5:0]  bypass_wdata_r_1;</span></a>
+<a name="81"><span class="lineNum">      81 </span><span class="lineCov">        339 :   reg  [5:0]  bypass_wdata_r_2;</span></a>
+<a name="82"><span class="lineNum">      82 </span><span class="lineCov">        350 :   reg  [5:0]  bypass_wdata_r_3;</span></a>
+<a name="83"><span class="lineNum">      83 </span><span class="lineCov">         59 :   wire        bypass_mask_need_check = io_r_req_valid &amp; io_w_req_valid;</span></a>
+<a name="84"><span class="lineNum">      84 </span><span class="lineCov">         96 :   reg         bypass_mask_need_check_reg_last_r;</span></a>
+<a name="85"><span class="lineNum">      85 </span><span class="lineCov">        444 :   reg  [7:0]  bypass_mask_waddr_reg;</span></a>
+<a name="86"><span class="lineNum">      86 </span><span class="lineCov">        475 :   reg  [7:0]  bypass_mask_raddr_reg;</span></a>
+<a name="87"><span class="lineNum">      87 </span><span class="lineCov">        205 :   reg  [3:0]  bypass_mask_wmask_reg;</span></a>
+<a name="88"><span class="lineNum">      88 </span><span class="lineCov">        242 :   wire [3:0]  bypass_mask =</span></a>
+<a name="89"><span class="lineNum">      89 </span>            :     {4{bypass_mask_need_check_reg_last_r</a>
+<a name="90"><span class="lineNum">      90 </span>            :          &amp; bypass_mask_waddr_reg == bypass_mask_raddr_reg}} &amp; bypass_mask_wmask_reg;</a>
+<a name="91"><span class="lineNum">      91 </span><span class="lineCov">        675 :   wire [5:0]  mem_rdata_0 = bypass_mask[0] ? bypass_wdata_r_0 : _array_R0_data[5:0];</span></a>
+<a name="92"><span class="lineNum">      92 </span><span class="lineCov">        684 :   wire [5:0]  mem_rdata_1 = bypass_mask[1] ? bypass_wdata_r_1 : _array_R0_data[11:6];</span></a>
+<a name="93"><span class="lineNum">      93 </span><span class="lineCov">        694 :   wire [5:0]  mem_rdata_2 = bypass_mask[2] ? bypass_wdata_r_2 : _array_R0_data[17:12];</span></a>
+<a name="94"><span class="lineNum">      94 </span><span class="lineCov">        722 :   wire [5:0]  mem_rdata_3 = bypass_mask[3] ? bypass_wdata_r_3 : _array_R0_data[23:18];</span></a>
+<a name="95"><span class="lineNum">      95 </span><span class="lineCov">        352 :   reg         rdata_last_r;</span></a>
+<a name="96"><span class="lineNum">      96 </span><span class="lineCov">        768 :   reg  [5:0]  rdata_hold_data_0;</span></a>
+<a name="97"><span class="lineNum">      97 </span><span class="lineCov">        790 :   reg  [5:0]  rdata_hold_data_1;</span></a>
+<a name="98"><span class="lineNum">      98 </span><span class="lineCov">        815 :   reg  [5:0]  rdata_hold_data_2;</span></a>
+<a name="99"><span class="lineNum">      99 </span><span class="lineCov">        792 :   reg  [5:0]  rdata_hold_data_3;</span></a>
+<a name="100"><span class="lineNum">     100 </span><span class="lineCov">     510920 :   always @(posedge clock or posedge reset) begin</span></a>
+<a name="101"><span class="lineNum">     101 </span><span class="lineCov">       1088 :     if (reset) begin</span></a>
+<a name="102"><span class="lineNum">     102 </span><span class="lineCov">        544 :       _resetState &lt;= 1'h1;</span></a>
+<a name="103"><span class="lineNum">     103 </span><span class="lineCov">        544 :       _resetSet &lt;= 8'h0;</span></a>
+<a name="104"><span class="lineNum">     104 </span><span class="lineCov">        544 :       bypass_mask_need_check_reg_last_r &lt;= 1'h0;</span></a>
+<a name="105"><span class="lineNum">     105 </span><span class="lineCov">        544 :       rdata_last_r &lt;= 1'h0;</span></a>
+<a name="106"><span class="lineNum">     106 </span>            :     end</a>
+<a name="107"><span class="lineNum">     107 </span><span class="lineCov">     254916 :     else begin</span></a>
+<a name="108"><span class="lineNum">     108 </span><span class="lineCov">     254916 :       _resetState &lt;= ~(_resetState &amp; (&amp;_resetSet)) &amp; _resetState;</span></a>
+<a name="109"><span class="lineNum">     109 </span><span class="lineCov">      60246 :       if (_resetState)</span></a>
+<a name="110"><span class="lineNum">     110 </span><span class="lineCov">      30123 :         _resetSet &lt;= 8'(_resetSet + 8'h1);</span></a>
+<a name="111"><span class="lineNum">     111 </span><span class="lineCov">         82 :       if (bypass_mask_need_check | bypass_mask_need_check_reg_last_r)</span></a>
+<a name="112"><span class="lineNum">     112 </span><span class="lineCov">         41 :         bypass_mask_need_check_reg_last_r &lt;= bypass_mask_need_check;</span></a>
+<a name="113"><span class="lineNum">     113 </span><span class="lineCov">      33602 :       if (io_r_req_valid | rdata_last_r)</span></a>
+<a name="114"><span class="lineNum">     114 </span><span class="lineCov">      16801 :         rdata_last_r &lt;= io_r_req_valid;</span></a>
+<a name="115"><span class="lineNum">     115 </span>            :     end</a>
+<a name="116"><span class="lineNum">     116 </span>            :   end // always @(posedge, posedge)</a>
+<a name="117"><span class="lineNum">     117 </span><span class="lineCov">     510776 :   always @(posedge clock) begin</span></a>
+<a name="118"><span class="lineNum">     118 </span><span class="lineNoCov">          0 :     if (io_w_req_valid &amp; io_r_req_valid) begin</span></a>
+<a name="119"><span class="lineNum">     119 </span><span class="lineNoCov">          0 :       bypass_wdata_r_0 &lt;= io_w_req_bits_data_0;</span></a>
+<a name="120"><span class="lineNum">     120 </span><span class="lineNoCov">          0 :       bypass_wdata_r_1 &lt;= io_w_req_bits_data_1;</span></a>
+<a name="121"><span class="lineNum">     121 </span><span class="lineNoCov">          0 :       bypass_wdata_r_2 &lt;= io_w_req_bits_data_2;</span></a>
+<a name="122"><span class="lineNum">     122 </span><span class="lineNoCov">          0 :       bypass_wdata_r_3 &lt;= io_w_req_bits_data_3;</span></a>
+<a name="123"><span class="lineNum">     123 </span>            :     end</a>
+<a name="124"><span class="lineNum">     124 </span><span class="lineNoCov">          0 :     if (bypass_mask_need_check) begin</span></a>
+<a name="125"><span class="lineNum">     125 </span><span class="lineNoCov">          0 :       bypass_mask_waddr_reg &lt;= io_w_req_bits_setIdx;</span></a>
+<a name="126"><span class="lineNum">     126 </span><span class="lineNoCov">          0 :       bypass_mask_raddr_reg &lt;= io_r_req_bits_setIdx;</span></a>
+<a name="127"><span class="lineNum">     127 </span><span class="lineNoCov">          0 :       bypass_mask_wmask_reg &lt;= io_w_req_bits_waymask;</span></a>
+<a name="128"><span class="lineNum">     128 </span>            :     end</a>
+<a name="129"><span class="lineNum">     129 </span><span class="lineCov">      33242 :     if (rdata_last_r) begin</span></a>
+<a name="130"><span class="lineNum">     130 </span><span class="lineCov">      16621 :       rdata_hold_data_0 &lt;= mem_rdata_0;</span></a>
+<a name="131"><span class="lineNum">     131 </span><span class="lineCov">      16621 :       rdata_hold_data_1 &lt;= mem_rdata_1;</span></a>
+<a name="132"><span class="lineNum">     132 </span><span class="lineCov">      16621 :       rdata_hold_data_2 &lt;= mem_rdata_2;</span></a>
+<a name="133"><span class="lineNum">     133 </span><span class="lineCov">      16621 :       rdata_hold_data_3 &lt;= mem_rdata_3;</span></a>
+<a name="134"><span class="lineNum">     134 </span>            :     end</a>
+<a name="135"><span class="lineNum">     135 </span>            :   end // always @(posedge)</a>
+<a name="136"><span class="lineNum">     136 </span>            :   `ifdef ENABLE_INITIAL_REG_</a>
+<a name="137"><span class="lineNum">     137 </span>            :     `ifdef FIRRTL_BEFORE_INITIAL</a>
+<a name="138"><span class="lineNum">     138 </span>            :       `FIRRTL_BEFORE_INITIAL</a>
+<a name="139"><span class="lineNum">     139 </span>            :     `endif // FIRRTL_BEFORE_INITIAL</a>
+<a name="140"><span class="lineNum">     140 </span>            :     logic [31:0] _RANDOM[0:2];</a>
+<a name="141"><span class="lineNum">     141 </span><span class="lineCov">        232 :     initial begin</span></a>
+<a name="142"><span class="lineNum">     142 </span>            :       `ifdef INIT_RANDOM_PROLOG_</a>
+<a name="143"><span class="lineNum">     143 </span>            :         `INIT_RANDOM_PROLOG_</a>
+<a name="144"><span class="lineNum">     144 </span>            :       `endif // INIT_RANDOM_PROLOG_</a>
+<a name="145"><span class="lineNum">     145 </span>            :       `ifdef RANDOMIZE_REG_INIT</a>
+<a name="146"><span class="lineNum">     146 </span>            :         for (logic [1:0] i = 2'h0; i &lt; 2'h3; i += 2'h1) begin</a>
+<a name="147"><span class="lineNum">     147 </span>            :           _RANDOM[i] = `RANDOM;</a>
+<a name="148"><span class="lineNum">     148 </span>            :         end</a>
+<a name="149"><span class="lineNum">     149 </span>            :         _resetState = _RANDOM[2'h0][0];</a>
+<a name="150"><span class="lineNum">     150 </span>            :         _resetSet = _RANDOM[2'h0][8:1];</a>
+<a name="151"><span class="lineNum">     151 </span>            :         bypass_wdata_r_0 = _RANDOM[2'h0][14:9];</a>
+<a name="152"><span class="lineNum">     152 </span>            :         bypass_wdata_r_1 = _RANDOM[2'h0][20:15];</a>
+<a name="153"><span class="lineNum">     153 </span>            :         bypass_wdata_r_2 = _RANDOM[2'h0][26:21];</a>
+<a name="154"><span class="lineNum">     154 </span>            :         bypass_wdata_r_3 = {_RANDOM[2'h0][31:27], _RANDOM[2'h1][0]};</a>
+<a name="155"><span class="lineNum">     155 </span>            :         bypass_mask_need_check_reg_last_r = _RANDOM[2'h1][1];</a>
+<a name="156"><span class="lineNum">     156 </span>            :         bypass_mask_waddr_reg = _RANDOM[2'h1][9:2];</a>
+<a name="157"><span class="lineNum">     157 </span>            :         bypass_mask_raddr_reg = _RANDOM[2'h1][17:10];</a>
+<a name="158"><span class="lineNum">     158 </span>            :         bypass_mask_wmask_reg = _RANDOM[2'h1][21:18];</a>
+<a name="159"><span class="lineNum">     159 </span>            :         rdata_last_r = _RANDOM[2'h1][22];</a>
+<a name="160"><span class="lineNum">     160 </span>            :         rdata_hold_data_0 = _RANDOM[2'h1][28:23];</a>
+<a name="161"><span class="lineNum">     161 </span>            :         rdata_hold_data_1 = {_RANDOM[2'h1][31:29], _RANDOM[2'h2][2:0]};</a>
+<a name="162"><span class="lineNum">     162 </span>            :         rdata_hold_data_2 = _RANDOM[2'h2][8:3];</a>
+<a name="163"><span class="lineNum">     163 </span>            :         rdata_hold_data_3 = _RANDOM[2'h2][14:9];</a>
+<a name="164"><span class="lineNum">     164 </span>            :       `endif // RANDOMIZE_REG_INIT</a>
+<a name="165"><span class="lineNum">     165 </span><span class="lineCov">         68 :       if (reset) begin</span></a>
+<a name="166"><span class="lineNum">     166 </span><span class="lineCov">         48 :         _resetState = 1'h1;</span></a>
+<a name="167"><span class="lineNum">     167 </span><span class="lineCov">         48 :         _resetSet = 8'h0;</span></a>
+<a name="168"><span class="lineNum">     168 </span><span class="lineCov">         48 :         bypass_mask_need_check_reg_last_r = 1'h0;</span></a>
+<a name="169"><span class="lineNum">     169 </span><span class="lineCov">         48 :         rdata_last_r = 1'h0;</span></a>
+<a name="170"><span class="lineNum">     170 </span>            :       end</a>
+<a name="171"><span class="lineNum">     171 </span>            :     end // initial</a>
+<a name="172"><span class="lineNum">     172 </span>            :     `ifdef FIRRTL_AFTER_INITIAL</a>
+<a name="173"><span class="lineNum">     173 </span>            :       `FIRRTL_AFTER_INITIAL</a>
+<a name="174"><span class="lineNum">     174 </span>            :     `endif // FIRRTL_AFTER_INITIAL</a>
+<a name="175"><span class="lineNum">     175 </span>            :   `endif // ENABLE_INITIAL_REG_</a>
+<a name="176"><span class="lineNum">     176 </span>            :   array_7 array (</a>
+<a name="177"><span class="lineNum">     177 </span>            :     .R0_addr (io_r_req_bits_setIdx),</a>
+<a name="178"><span class="lineNum">     178 </span>            :     .R0_en   (io_r_req_valid),</a>
+<a name="179"><span class="lineNum">     179 </span>            :     .R0_clk  (clock),</a>
+<a name="180"><span class="lineNum">     180 </span>            :     .R0_data (_array_R0_data),</a>
+<a name="181"><span class="lineNum">     181 </span>            :     .W0_addr (_resetState ? _resetSet : io_w_req_bits_setIdx),</a>
+<a name="182"><span class="lineNum">     182 </span>            :     .W0_en   (io_w_req_valid | _resetState),</a>
+<a name="183"><span class="lineNum">     183 </span>            :     .W0_clk  (clock),</a>
+<a name="184"><span class="lineNum">     184 </span>            :     .W0_data</a>
+<a name="185"><span class="lineNum">     185 </span>            :       ({_resetState ? 6'h0 : io_w_req_bits_data_3,</a>
+<a name="186"><span class="lineNum">     186 </span>            :         _resetState ? 6'h0 : io_w_req_bits_data_2,</a>
+<a name="187"><span class="lineNum">     187 </span>            :         _resetState ? 6'h0 : io_w_req_bits_data_1,</a>
+<a name="188"><span class="lineNum">     188 </span>            :         _resetState ? 6'h0 : io_w_req_bits_data_0}),</a>
+<a name="189"><span class="lineNum">     189 </span>            :     .W0_mask (_resetState ? 4'hF : io_w_req_bits_waymask)</a>
+<a name="190"><span class="lineNum">     190 </span>            :   );</a>
+<a name="191"><span class="lineNum">     191 </span>            :   assign io_r_resp_data_0 = rdata_last_r ? mem_rdata_0 : rdata_hold_data_0;</a>
+<a name="192"><span class="lineNum">     192 </span>            :   assign io_r_resp_data_1 = rdata_last_r ? mem_rdata_1 : rdata_hold_data_1;</a>
+<a name="193"><span class="lineNum">     193 </span>            :   assign io_r_resp_data_2 = rdata_last_r ? mem_rdata_2 : rdata_hold_data_2;</a>
+<a name="194"><span class="lineNum">     194 </span>            :   assign io_r_resp_data_3 = rdata_last_r ? mem_rdata_3 : rdata_hold_data_3;</a>
+<a name="195"><span class="lineNum">     195 </span>            : endmodule</a>
+<a name="196"><span class="lineNum">     196 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SRAMTemplate_39.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SRAMTemplate_39.sv.func-sort-c.html
new file mode 100644
index 0000000..951688d
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SRAMTemplate_39.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/SRAMTemplate_39.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - SRAMTemplate_39.sv<span style="font-size: 80%;"> (<a href="SRAMTemplate_39.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">37</td>
+            <td class="headerCovTableEntry">37</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="SRAMTemplate_39.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SRAMTemplate_39.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SRAMTemplate_39.sv.func.html
new file mode 100644
index 0000000..3e64dbb
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SRAMTemplate_39.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/SRAMTemplate_39.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - SRAMTemplate_39.sv<span style="font-size: 80%;"> (<a href="SRAMTemplate_39.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">37</td>
+            <td class="headerCovTableEntry">37</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="SRAMTemplate_39.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SRAMTemplate_39.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SRAMTemplate_39.sv.gcov.html
new file mode 100644
index 0000000..b818003
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SRAMTemplate_39.sv.gcov.html
@@ -0,0 +1,225 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/SRAMTemplate_39.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - SRAMTemplate_39.sv<span style="font-size: 80%;"> (source / <a href="SRAMTemplate_39.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">37</td>
+            <td class="headerCovTableEntry">37</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : module SRAMTemplate_39(</a>
+<a name="59"><span class="lineNum">      59 </span><span class="lineCov">     127786 :   input         clock,</span></a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">         62 :   input         reset,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">        254 :   input         io_r_req_valid,</span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">      24520 :   input  [6:0]  io_r_req_bits_setIdx,</span></a>
+<a name="63"><span class="lineNum">      63 </span><span class="lineCov">        100 :   output        io_r_resp_data_0_valid,</span></a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">        846 :   output [8:0]  io_r_resp_data_0_tag,</span></a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">        197 :   output [1:0]  io_r_resp_data_0_ctr,</span></a>
+<a name="66"><span class="lineNum">      66 </span><span class="lineCov">       4028 :   output [40:0] io_r_resp_data_0_target,</span></a>
+<a name="67"><span class="lineNum">      67 </span><span class="lineCov">         80 :   input         io_w_req_valid,</span></a>
+<a name="68"><span class="lineNum">      68 </span><span class="lineCov">         91 :   input  [6:0]  io_w_req_bits_setIdx,</span></a>
+<a name="69"><span class="lineNum">      69 </span><span class="lineCov">        127 :   input  [8:0]  io_w_req_bits_data_0_tag,</span></a>
+<a name="70"><span class="lineNum">      70 </span><span class="lineCov">         36 :   input  [1:0]  io_w_req_bits_data_0_ctr,</span></a>
+<a name="71"><span class="lineNum">      71 </span><span class="lineCov">        642 :   input  [40:0] io_w_req_bits_data_0_target</span></a>
+<a name="72"><span class="lineNum">      72 </span>            : );</a>
+<a name="73"><span class="lineNum">      73 </span>            : </a>
+<a name="74"><span class="lineNum">      74 </span><span class="lineCov">      30522 :   wire [6:0]  setIdx;</span></a>
+<a name="75"><span class="lineNum">      75 </span><span class="lineCov">        258 :   wire        realRen;</span></a>
+<a name="76"><span class="lineNum">      76 </span><span class="lineCov">        209 :   wire        wen;</span></a>
+<a name="77"><span class="lineNum">      77 </span>            :   wire [52:0] _array_0_RW0_rdata;</a>
+<a name="78"><span class="lineNum">      78 </span>            :   reg         _resetState;</a>
+<a name="79"><span class="lineNum">      79 </span>            :   reg  [6:0]  _resetSet;</a>
+<a name="80"><span class="lineNum">      80 </span>            :   assign wen = io_w_req_valid | _resetState;</a>
+<a name="81"><span class="lineNum">      81 </span>            :   assign realRen = io_r_req_valid &amp; ~wen;</a>
+<a name="82"><span class="lineNum">      82 </span>            :   assign setIdx = _resetState ? _resetSet : io_w_req_bits_setIdx;</a>
+<a name="83"><span class="lineNum">      83 </span><span class="lineCov">        296 :   reg         rdata_last_r;</span></a>
+<a name="84"><span class="lineNum">      84 </span><span class="lineCov">       6121 :   reg  [52:0] rdata_hold_data_0;</span></a>
+<a name="85"><span class="lineNum">      85 </span>            :   wire [52:0] _rdata_T_0 = rdata_last_r ? _array_0_RW0_rdata : rdata_hold_data_0;</a>
+<a name="86"><span class="lineNum">      86 </span><span class="lineCov">     510920 :   always @(posedge clock or posedge reset) begin</span></a>
+<a name="87"><span class="lineNum">      87 </span><span class="lineCov">       1088 :     if (reset) begin</span></a>
+<a name="88"><span class="lineNum">      88 </span><span class="lineCov">        544 :       _resetState &lt;= 1'h1;</span></a>
+<a name="89"><span class="lineNum">      89 </span><span class="lineCov">        544 :       _resetSet &lt;= 7'h0;</span></a>
+<a name="90"><span class="lineNum">      90 </span><span class="lineCov">        544 :       rdata_last_r &lt;= 1'h0;</span></a>
+<a name="91"><span class="lineNum">      91 </span>            :     end</a>
+<a name="92"><span class="lineNum">      92 </span><span class="lineCov">     254916 :     else begin</span></a>
+<a name="93"><span class="lineNum">      93 </span><span class="lineCov">     254916 :       _resetState &lt;= ~(_resetState &amp; (&amp;_resetSet)) &amp; _resetState;</span></a>
+<a name="94"><span class="lineNum">      94 </span><span class="lineCov">      30538 :       if (_resetState)</span></a>
+<a name="95"><span class="lineNum">      95 </span><span class="lineCov">      15269 :         _resetSet &lt;= 7'(_resetSet + 7'h1);</span></a>
+<a name="96"><span class="lineNum">      96 </span><span class="lineCov">      16920 :       if (realRen | rdata_last_r)</span></a>
+<a name="97"><span class="lineNum">      97 </span><span class="lineCov">       8460 :         rdata_last_r &lt;= realRen;</span></a>
+<a name="98"><span class="lineNum">      98 </span>            :     end</a>
+<a name="99"><span class="lineNum">      99 </span>            :   end // always @(posedge, posedge)</a>
+<a name="100"><span class="lineNum">     100 </span><span class="lineCov">     510776 :   always @(posedge clock) begin</span></a>
+<a name="101"><span class="lineNum">     101 </span><span class="lineCov">      16660 :     if (rdata_last_r)</span></a>
+<a name="102"><span class="lineNum">     102 </span><span class="lineCov">       8330 :       rdata_hold_data_0 &lt;= _array_0_RW0_rdata;</span></a>
+<a name="103"><span class="lineNum">     103 </span>            :   end // always @(posedge)</a>
+<a name="104"><span class="lineNum">     104 </span>            :   `ifdef ENABLE_INITIAL_REG_</a>
+<a name="105"><span class="lineNum">     105 </span>            :     `ifdef FIRRTL_BEFORE_INITIAL</a>
+<a name="106"><span class="lineNum">     106 </span>            :       `FIRRTL_BEFORE_INITIAL</a>
+<a name="107"><span class="lineNum">     107 </span>            :     `endif // FIRRTL_BEFORE_INITIAL</a>
+<a name="108"><span class="lineNum">     108 </span>            :     logic [31:0] _RANDOM[0:4];</a>
+<a name="109"><span class="lineNum">     109 </span><span class="lineCov">        232 :     initial begin</span></a>
+<a name="110"><span class="lineNum">     110 </span>            :       `ifdef INIT_RANDOM_PROLOG_</a>
+<a name="111"><span class="lineNum">     111 </span>            :         `INIT_RANDOM_PROLOG_</a>
+<a name="112"><span class="lineNum">     112 </span>            :       `endif // INIT_RANDOM_PROLOG_</a>
+<a name="113"><span class="lineNum">     113 </span>            :       `ifdef RANDOMIZE_REG_INIT</a>
+<a name="114"><span class="lineNum">     114 </span>            :         for (logic [2:0] i = 3'h0; i &lt; 3'h5; i += 3'h1) begin</a>
+<a name="115"><span class="lineNum">     115 </span>            :           _RANDOM[i] = `RANDOM;</a>
+<a name="116"><span class="lineNum">     116 </span>            :         end</a>
+<a name="117"><span class="lineNum">     117 </span>            :         _resetState = _RANDOM[3'h0][0];</a>
+<a name="118"><span class="lineNum">     118 </span>            :         _resetSet = _RANDOM[3'h0][7:1];</a>
+<a name="119"><span class="lineNum">     119 </span>            :         rdata_last_r = _RANDOM[3'h2][24];</a>
+<a name="120"><span class="lineNum">     120 </span>            :         rdata_hold_data_0 = {_RANDOM[3'h2][31:25], _RANDOM[3'h3], _RANDOM[3'h4][13:0]};</a>
+<a name="121"><span class="lineNum">     121 </span>            :       `endif // RANDOMIZE_REG_INIT</a>
+<a name="122"><span class="lineNum">     122 </span><span class="lineCov">         68 :       if (reset) begin</span></a>
+<a name="123"><span class="lineNum">     123 </span><span class="lineCov">         48 :         _resetState = 1'h1;</span></a>
+<a name="124"><span class="lineNum">     124 </span><span class="lineCov">         48 :         _resetSet = 7'h0;</span></a>
+<a name="125"><span class="lineNum">     125 </span><span class="lineCov">         48 :         rdata_last_r = 1'h0;</span></a>
+<a name="126"><span class="lineNum">     126 </span>            :       end</a>
+<a name="127"><span class="lineNum">     127 </span>            :     end // initial</a>
+<a name="128"><span class="lineNum">     128 </span>            :     `ifdef FIRRTL_AFTER_INITIAL</a>
+<a name="129"><span class="lineNum">     129 </span>            :       `FIRRTL_AFTER_INITIAL</a>
+<a name="130"><span class="lineNum">     130 </span>            :     `endif // FIRRTL_AFTER_INITIAL</a>
+<a name="131"><span class="lineNum">     131 </span>            :   `endif // ENABLE_INITIAL_REG_</a>
+<a name="132"><span class="lineNum">     132 </span>            :   array_0_0 array_0 (</a>
+<a name="133"><span class="lineNum">     133 </span>            :     .RW0_addr  (wen ? setIdx : io_r_req_bits_setIdx),</a>
+<a name="134"><span class="lineNum">     134 </span>            :     .RW0_en    (realRen | wen),</a>
+<a name="135"><span class="lineNum">     135 </span>            :     .RW0_clk   (clock),</a>
+<a name="136"><span class="lineNum">     136 </span>            :     .RW0_wmode (wen),</a>
+<a name="137"><span class="lineNum">     137 </span>            :     .RW0_wdata</a>
+<a name="138"><span class="lineNum">     138 </span>            :       ({~_resetState,</a>
+<a name="139"><span class="lineNum">     139 </span>            :         _resetState ? 9'h0 : io_w_req_bits_data_0_tag,</a>
+<a name="140"><span class="lineNum">     140 </span>            :         _resetState ? 2'h0 : io_w_req_bits_data_0_ctr,</a>
+<a name="141"><span class="lineNum">     141 </span>            :         _resetState ? 41'h0 : io_w_req_bits_data_0_target}),</a>
+<a name="142"><span class="lineNum">     142 </span>            :     .RW0_rdata (_array_0_RW0_rdata)</a>
+<a name="143"><span class="lineNum">     143 </span>            :   );</a>
+<a name="144"><span class="lineNum">     144 </span>            :   assign io_r_resp_data_0_valid = _rdata_T_0[52];</a>
+<a name="145"><span class="lineNum">     145 </span>            :   assign io_r_resp_data_0_tag = _rdata_T_0[51:43];</a>
+<a name="146"><span class="lineNum">     146 </span>            :   assign io_r_resp_data_0_ctr = _rdata_T_0[42:41];</a>
+<a name="147"><span class="lineNum">     147 </span>            :   assign io_r_resp_data_0_target = _rdata_T_0[40:0];</a>
+<a name="148"><span class="lineNum">     148 </span>            : endmodule</a>
+<a name="149"><span class="lineNum">     149 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SRAMTemplate_43.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SRAMTemplate_43.sv.func-sort-c.html
new file mode 100644
index 0000000..c71b1f9
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SRAMTemplate_43.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/SRAMTemplate_43.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - SRAMTemplate_43.sv<span style="font-size: 80%;"> (<a href="SRAMTemplate_43.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">47</td>
+            <td class="headerCovTableEntry">47</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="SRAMTemplate_43.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SRAMTemplate_43.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SRAMTemplate_43.sv.func.html
new file mode 100644
index 0000000..8901f64
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SRAMTemplate_43.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/SRAMTemplate_43.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - SRAMTemplate_43.sv<span style="font-size: 80%;"> (<a href="SRAMTemplate_43.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">47</td>
+            <td class="headerCovTableEntry">47</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="SRAMTemplate_43.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SRAMTemplate_43.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SRAMTemplate_43.sv.gcov.html
new file mode 100644
index 0000000..c6fbb40
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/SRAMTemplate_43.sv.gcov.html
@@ -0,0 +1,247 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/SRAMTemplate_43.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - SRAMTemplate_43.sv<span style="font-size: 80%;"> (source / <a href="SRAMTemplate_43.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">47</td>
+            <td class="headerCovTableEntry">47</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : module SRAMTemplate_43(</a>
+<a name="59"><span class="lineNum">      59 </span><span class="lineCov">     127786 :   input         clock,</span></a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">         62 :   input         reset,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">        394 :   input         io_r_req_valid,</span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">       8451 :   input  [6:0]  io_r_req_bits_setIdx,</span></a>
+<a name="63"><span class="lineNum">      63 </span><span class="lineCov">        163 :   output        io_r_resp_data_0_valid,</span></a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">       1362 :   output [8:0]  io_r_resp_data_0_tag,</span></a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">        279 :   output [1:0]  io_r_resp_data_0_ctr,</span></a>
+<a name="66"><span class="lineNum">      66 </span><span class="lineCov">       6059 :   output [40:0] io_r_resp_data_0_target,</span></a>
+<a name="67"><span class="lineNum">      67 </span><span class="lineCov">        143 :   output        io_r_resp_data_1_valid,</span></a>
+<a name="68"><span class="lineNum">      68 </span><span class="lineCov">       1335 :   output [8:0]  io_r_resp_data_1_tag,</span></a>
+<a name="69"><span class="lineNum">      69 </span><span class="lineCov">        298 :   output [1:0]  io_r_resp_data_1_ctr,</span></a>
+<a name="70"><span class="lineNum">      70 </span><span class="lineCov">       6041 :   output [40:0] io_r_resp_data_1_target,</span></a>
+<a name="71"><span class="lineNum">      71 </span><span class="lineCov">        129 :   input         io_w_req_valid,</span></a>
+<a name="72"><span class="lineNum">      72 </span><span class="lineCov">         95 :   input  [6:0]  io_w_req_bits_setIdx,</span></a>
+<a name="73"><span class="lineNum">      73 </span><span class="lineCov">        122 :   input  [8:0]  io_w_req_bits_data_0_tag,</span></a>
+<a name="74"><span class="lineNum">      74 </span><span class="lineCov">         33 :   input  [1:0]  io_w_req_bits_data_0_ctr,</span></a>
+<a name="75"><span class="lineNum">      75 </span><span class="lineCov">        607 :   input  [40:0] io_w_req_bits_data_0_target,</span></a>
+<a name="76"><span class="lineNum">      76 </span><span class="lineCov">        122 :   input  [8:0]  io_w_req_bits_data_1_tag,</span></a>
+<a name="77"><span class="lineNum">      77 </span><span class="lineCov">         33 :   input  [1:0]  io_w_req_bits_data_1_ctr,</span></a>
+<a name="78"><span class="lineNum">      78 </span><span class="lineCov">        607 :   input  [40:0] io_w_req_bits_data_1_target,</span></a>
+<a name="79"><span class="lineNum">      79 </span><span class="lineCov">     255572 :   input  [1:0]  io_w_req_bits_waymask</span></a>
+<a name="80"><span class="lineNum">      80 </span>            : );</a>
+<a name="81"><span class="lineNum">      81 </span>            : </a>
+<a name="82"><span class="lineNum">      82 </span><span class="lineCov">      45847 :   wire [6:0]   setIdx;</span></a>
+<a name="83"><span class="lineNum">      83 </span><span class="lineCov">        396 :   wire         realRen;</span></a>
+<a name="84"><span class="lineNum">      84 </span><span class="lineCov">        327 :   wire         wen;</span></a>
+<a name="85"><span class="lineNum">      85 </span>            :   wire [105:0] _array_RW0_rdata;</a>
+<a name="86"><span class="lineNum">      86 </span>            :   reg          _resetState;</a>
+<a name="87"><span class="lineNum">      87 </span>            :   reg  [6:0]   _resetSet;</a>
+<a name="88"><span class="lineNum">      88 </span>            :   assign wen = io_w_req_valid | _resetState;</a>
+<a name="89"><span class="lineNum">      89 </span>            :   assign realRen = io_r_req_valid &amp; ~wen;</a>
+<a name="90"><span class="lineNum">      90 </span>            :   assign setIdx = _resetState ? _resetSet : io_w_req_bits_setIdx;</a>
+<a name="91"><span class="lineNum">      91 </span><span class="lineCov">        446 :   reg          rdata_last_r;</span></a>
+<a name="92"><span class="lineNum">      92 </span><span class="lineCov">       9156 :   reg  [52:0]  rdata_hold_data_0;</span></a>
+<a name="93"><span class="lineNum">      93 </span><span class="lineCov">       9286 :   reg  [52:0]  rdata_hold_data_1;</span></a>
+<a name="94"><span class="lineNum">      94 </span>            :   wire [52:0]  _rdata_T_0 = rdata_last_r ? _array_RW0_rdata[52:0] : rdata_hold_data_0;</a>
+<a name="95"><span class="lineNum">      95 </span>            :   wire [52:0]  _rdata_T_1 = rdata_last_r ? _array_RW0_rdata[105:53] : rdata_hold_data_1;</a>
+<a name="96"><span class="lineNum">      96 </span><span class="lineCov">     766380 :   always @(posedge clock or posedge reset) begin</span></a>
+<a name="97"><span class="lineNum">      97 </span><span class="lineCov">       1632 :     if (reset) begin</span></a>
+<a name="98"><span class="lineNum">      98 </span><span class="lineCov">        816 :       _resetState &lt;= 1'h1;</span></a>
+<a name="99"><span class="lineNum">      99 </span><span class="lineCov">        816 :       _resetSet &lt;= 7'h0;</span></a>
+<a name="100"><span class="lineNum">     100 </span><span class="lineCov">        816 :       rdata_last_r &lt;= 1'h0;</span></a>
+<a name="101"><span class="lineNum">     101 </span>            :     end</a>
+<a name="102"><span class="lineNum">     102 </span><span class="lineCov">     382374 :     else begin</span></a>
+<a name="103"><span class="lineNum">     103 </span><span class="lineCov">     382374 :       _resetState &lt;= ~(_resetState &amp; (&amp;_resetSet)) &amp; _resetState;</span></a>
+<a name="104"><span class="lineNum">     104 </span><span class="lineCov">      45808 :       if (_resetState)</span></a>
+<a name="105"><span class="lineNum">     105 </span><span class="lineCov">      22904 :         _resetSet &lt;= 7'(_resetSet + 7'h1);</span></a>
+<a name="106"><span class="lineNum">     106 </span><span class="lineCov">      25366 :       if (realRen | rdata_last_r)</span></a>
+<a name="107"><span class="lineNum">     107 </span><span class="lineCov">      12683 :         rdata_last_r &lt;= realRen;</span></a>
+<a name="108"><span class="lineNum">     108 </span>            :     end</a>
+<a name="109"><span class="lineNum">     109 </span>            :   end // always @(posedge, posedge)</a>
+<a name="110"><span class="lineNum">     110 </span><span class="lineCov">     766164 :   always @(posedge clock) begin</span></a>
+<a name="111"><span class="lineNum">     111 </span><span class="lineCov">      24976 :     if (rdata_last_r) begin</span></a>
+<a name="112"><span class="lineNum">     112 </span><span class="lineCov">      12488 :       rdata_hold_data_0 &lt;= _array_RW0_rdata[52:0];</span></a>
+<a name="113"><span class="lineNum">     113 </span><span class="lineCov">      12488 :       rdata_hold_data_1 &lt;= _array_RW0_rdata[105:53];</span></a>
+<a name="114"><span class="lineNum">     114 </span>            :     end</a>
+<a name="115"><span class="lineNum">     115 </span>            :   end // always @(posedge)</a>
+<a name="116"><span class="lineNum">     116 </span>            :   `ifdef ENABLE_INITIAL_REG_</a>
+<a name="117"><span class="lineNum">     117 </span>            :     `ifdef FIRRTL_BEFORE_INITIAL</a>
+<a name="118"><span class="lineNum">     118 </span>            :       `FIRRTL_BEFORE_INITIAL</a>
+<a name="119"><span class="lineNum">     119 </span>            :     `endif // FIRRTL_BEFORE_INITIAL</a>
+<a name="120"><span class="lineNum">     120 </span>            :     logic [31:0] _RANDOM[0:8];</a>
+<a name="121"><span class="lineNum">     121 </span><span class="lineCov">        348 :     initial begin</span></a>
+<a name="122"><span class="lineNum">     122 </span>            :       `ifdef INIT_RANDOM_PROLOG_</a>
+<a name="123"><span class="lineNum">     123 </span>            :         `INIT_RANDOM_PROLOG_</a>
+<a name="124"><span class="lineNum">     124 </span>            :       `endif // INIT_RANDOM_PROLOG_</a>
+<a name="125"><span class="lineNum">     125 </span>            :       `ifdef RANDOMIZE_REG_INIT</a>
+<a name="126"><span class="lineNum">     126 </span>            :         for (logic [3:0] i = 4'h0; i &lt; 4'h9; i += 4'h1) begin</a>
+<a name="127"><span class="lineNum">     127 </span>            :           _RANDOM[i] = `RANDOM;</a>
+<a name="128"><span class="lineNum">     128 </span>            :         end</a>
+<a name="129"><span class="lineNum">     129 </span>            :         _resetState = _RANDOM[4'h0][0];</a>
+<a name="130"><span class="lineNum">     130 </span>            :         _resetSet = _RANDOM[4'h0][7:1];</a>
+<a name="131"><span class="lineNum">     131 </span>            :         rdata_last_r = _RANDOM[4'h4][25];</a>
+<a name="132"><span class="lineNum">     132 </span>            :         rdata_hold_data_0 = {_RANDOM[4'h4][31:26], _RANDOM[4'h5], _RANDOM[4'h6][14:0]};</a>
+<a name="133"><span class="lineNum">     133 </span>            :         rdata_hold_data_1 = {_RANDOM[4'h6][31:15], _RANDOM[4'h7], _RANDOM[4'h8][3:0]};</a>
+<a name="134"><span class="lineNum">     134 </span>            :       `endif // RANDOMIZE_REG_INIT</a>
+<a name="135"><span class="lineNum">     135 </span><span class="lineCov">        102 :       if (reset) begin</span></a>
+<a name="136"><span class="lineNum">     136 </span><span class="lineCov">         72 :         _resetState = 1'h1;</span></a>
+<a name="137"><span class="lineNum">     137 </span><span class="lineCov">         72 :         _resetSet = 7'h0;</span></a>
+<a name="138"><span class="lineNum">     138 </span><span class="lineCov">         72 :         rdata_last_r = 1'h0;</span></a>
+<a name="139"><span class="lineNum">     139 </span>            :       end</a>
+<a name="140"><span class="lineNum">     140 </span>            :     end // initial</a>
+<a name="141"><span class="lineNum">     141 </span>            :     `ifdef FIRRTL_AFTER_INITIAL</a>
+<a name="142"><span class="lineNum">     142 </span>            :       `FIRRTL_AFTER_INITIAL</a>
+<a name="143"><span class="lineNum">     143 </span>            :     `endif // FIRRTL_AFTER_INITIAL</a>
+<a name="144"><span class="lineNum">     144 </span>            :   `endif // ENABLE_INITIAL_REG_</a>
+<a name="145"><span class="lineNum">     145 </span>            :   array_8 array (</a>
+<a name="146"><span class="lineNum">     146 </span>            :     .RW0_addr  (wen ? setIdx : io_r_req_bits_setIdx),</a>
+<a name="147"><span class="lineNum">     147 </span>            :     .RW0_en    (realRen | wen),</a>
+<a name="148"><span class="lineNum">     148 </span>            :     .RW0_clk   (clock),</a>
+<a name="149"><span class="lineNum">     149 </span>            :     .RW0_wmode (wen),</a>
+<a name="150"><span class="lineNum">     150 </span>            :     .RW0_wdata</a>
+<a name="151"><span class="lineNum">     151 </span>            :       ({~_resetState,</a>
+<a name="152"><span class="lineNum">     152 </span>            :         _resetState ? 9'h0 : io_w_req_bits_data_1_tag,</a>
+<a name="153"><span class="lineNum">     153 </span>            :         _resetState ? 2'h0 : io_w_req_bits_data_1_ctr,</a>
+<a name="154"><span class="lineNum">     154 </span>            :         _resetState ? 41'h0 : io_w_req_bits_data_1_target,</a>
+<a name="155"><span class="lineNum">     155 </span>            :         ~_resetState,</a>
+<a name="156"><span class="lineNum">     156 </span>            :         _resetState ? 9'h0 : io_w_req_bits_data_0_tag,</a>
+<a name="157"><span class="lineNum">     157 </span>            :         _resetState ? 2'h0 : io_w_req_bits_data_0_ctr,</a>
+<a name="158"><span class="lineNum">     158 </span>            :         _resetState ? 41'h0 : io_w_req_bits_data_0_target}),</a>
+<a name="159"><span class="lineNum">     159 </span>            :     .RW0_rdata (_array_RW0_rdata),</a>
+<a name="160"><span class="lineNum">     160 </span>            :     .RW0_wmask (_resetState ? 2'h3 : io_w_req_bits_waymask)</a>
+<a name="161"><span class="lineNum">     161 </span>            :   );</a>
+<a name="162"><span class="lineNum">     162 </span>            :   assign io_r_resp_data_0_valid = _rdata_T_0[52];</a>
+<a name="163"><span class="lineNum">     163 </span>            :   assign io_r_resp_data_0_tag = _rdata_T_0[51:43];</a>
+<a name="164"><span class="lineNum">     164 </span>            :   assign io_r_resp_data_0_ctr = _rdata_T_0[42:41];</a>
+<a name="165"><span class="lineNum">     165 </span>            :   assign io_r_resp_data_0_target = _rdata_T_0[40:0];</a>
+<a name="166"><span class="lineNum">     166 </span>            :   assign io_r_resp_data_1_valid = _rdata_T_1[52];</a>
+<a name="167"><span class="lineNum">     167 </span>            :   assign io_r_resp_data_1_tag = _rdata_T_1[51:43];</a>
+<a name="168"><span class="lineNum">     168 </span>            :   assign io_r_resp_data_1_ctr = _rdata_T_1[42:41];</a>
+<a name="169"><span class="lineNum">     169 </span>            :   assign io_r_resp_data_1_target = _rdata_T_1[40:0];</a>
+<a name="170"><span class="lineNum">     170 </span>            : endmodule</a>
+<a name="171"><span class="lineNum">     171 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/TageBTable.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/TageBTable.sv.func-sort-c.html
new file mode 100644
index 0000000..4606557
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+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/TageBTable.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/TageBTable.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - TageBTable.sv<span style="font-size: 80%;"> (<a href="TageBTable.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">35</td>
+            <td class="headerCovTableEntry">35</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="TageBTable.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/TageBTable.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/TageBTable.sv.func.html
new file mode 100644
index 0000000..1649ac2
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/TageBTable.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/TageBTable.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - TageBTable.sv<span style="font-size: 80%;"> (<a href="TageBTable.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">35</td>
+            <td class="headerCovTableEntry">35</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="TageBTable.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/TageBTable.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/TageBTable.sv.gcov.html
new file mode 100644
index 0000000..de26141
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/TageBTable.sv.gcov.html
@@ -0,0 +1,264 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/TageBTable.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - TageBTable.sv<span style="font-size: 80%;"> (source / <a href="TageBTable.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">35</td>
+            <td class="headerCovTableEntry">35</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : module TageBTable(</a>
+<a name="59"><span class="lineNum">      59 </span><span class="lineCov">     127786 :   input         clock,</span></a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">         62 :   input         reset,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">         52 :   output        io_req_ready,</span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">         76 :   input         io_req_valid,</span></a>
+<a name="63"><span class="lineNum">      63 </span><span class="lineCov">      10224 :   input  [40:0] io_req_bits,</span></a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">         52 :   output [1:0]  io_s1_cnt_0,</span></a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">         62 :   output [1:0]  io_s1_cnt_1,</span></a>
+<a name="66"><span class="lineNum">      66 </span><span class="lineCov">         28 :   input         io_update_mask_0,</span></a>
+<a name="67"><span class="lineNum">      67 </span><span class="lineCov">         26 :   input         io_update_mask_1,</span></a>
+<a name="68"><span class="lineNum">      68 </span><span class="lineCov">        689 :   input  [40:0] io_update_pc,</span></a>
+<a name="69"><span class="lineNum">      69 </span><span class="lineCov">         29 :   input  [1:0]  io_update_cnt_0,</span></a>
+<a name="70"><span class="lineNum">      70 </span><span class="lineCov">         29 :   input  [1:0]  io_update_cnt_1,</span></a>
+<a name="71"><span class="lineNum">      71 </span><span class="lineCov">         13 :   input         io_update_takens_0,</span></a>
+<a name="72"><span class="lineNum">      72 </span><span class="lineCov">         18 :   input         io_update_takens_1</span></a>
+<a name="73"><span class="lineNum">      73 </span>            : );</a>
+<a name="74"><span class="lineNum">      74 </span>            : </a>
+<a name="75"><span class="lineNum">      75 </span><span class="lineCov">         35 :   wire [1:0]  newCtrs_1;</span></a>
+<a name="76"><span class="lineNum">      76 </span><span class="lineCov">         37 :   wire [1:0]  newCtrs_0;</span></a>
+<a name="77"><span class="lineNum">      77 </span>            :   wire        _wrbypass_io_hit;</a>
+<a name="78"><span class="lineNum">      78 </span>            :   wire        _wrbypass_io_hit_data_0_valid;</a>
+<a name="79"><span class="lineNum">      79 </span>            :   wire [1:0]  _wrbypass_io_hit_data_0_bits;</a>
+<a name="80"><span class="lineNum">      80 </span>            :   wire        _wrbypass_io_hit_data_1_valid;</a>
+<a name="81"><span class="lineNum">      81 </span>            :   wire [1:0]  _wrbypass_io_hit_data_1_bits;</a>
+<a name="82"><span class="lineNum">      82 </span>            :   wire [1:0]  _bt_io_r_resp_data_0;</a>
+<a name="83"><span class="lineNum">      83 </span>            :   wire [1:0]  _bt_io_r_resp_data_1;</a>
+<a name="84"><span class="lineNum">      84 </span><span class="lineCov">         56 :   reg         doing_reset;</span></a>
+<a name="85"><span class="lineNum">      85 </span><span class="lineCov">     119199 :   reg  [10:0] resetRow;</span></a>
+<a name="86"><span class="lineNum">      86 </span><span class="lineCov">       8456 :   reg  [10:0] s1_idx;</span></a>
+<a name="87"><span class="lineNum">      87 </span>            :   wire        _wrbypass_io_wen_T = io_update_mask_0 | io_update_mask_1;</a>
+<a name="88"><span class="lineNum">      88 </span><span class="lineCov">         32 :   wire [1:0]  oldCtrs_0 =</span></a>
+<a name="89"><span class="lineNum">      89 </span>            :     _wrbypass_io_hit</a>
+<a name="90"><span class="lineNum">      90 </span>            :     &amp; (io_update_pc[1] ? _wrbypass_io_hit_data_1_valid : _wrbypass_io_hit_data_0_valid)</a>
+<a name="91"><span class="lineNum">      91 </span>            :       ? (io_update_pc[1] ? _wrbypass_io_hit_data_1_bits : _wrbypass_io_hit_data_0_bits)</a>
+<a name="92"><span class="lineNum">      92 </span>            :       : io_update_pc[1] ? io_update_cnt_1 : io_update_cnt_0;</a>
+<a name="93"><span class="lineNum">      93 </span><span class="lineCov">         44 :   wire [1:0]  oldCtrs_1 =</span></a>
+<a name="94"><span class="lineNum">      94 </span>            :     _wrbypass_io_hit</a>
+<a name="95"><span class="lineNum">      95 </span>            :     &amp; (io_update_pc[1] ? _wrbypass_io_hit_data_0_valid : _wrbypass_io_hit_data_1_valid)</a>
+<a name="96"><span class="lineNum">      96 </span>            :       ? (io_update_pc[1] ? _wrbypass_io_hit_data_0_bits : _wrbypass_io_hit_data_1_bits)</a>
+<a name="97"><span class="lineNum">      97 </span>            :       : io_update_pc[1] ? io_update_cnt_0 : io_update_cnt_1;</a>
+<a name="98"><span class="lineNum">      98 </span>            :   wire        _GEN = io_update_pc[1] ? io_update_takens_1 : io_update_takens_0;</a>
+<a name="99"><span class="lineNum">      99 </span>            :   assign newCtrs_0 =</a>
+<a name="100"><span class="lineNum">     100 </span>            :     (&amp;oldCtrs_0) &amp; _GEN</a>
+<a name="101"><span class="lineNum">     101 </span>            :       ? 2'h3</a>
+<a name="102"><span class="lineNum">     102 </span>            :       : oldCtrs_0 == 2'h0 &amp; ~_GEN</a>
+<a name="103"><span class="lineNum">     103 </span>            :           ? 2'h0</a>
+<a name="104"><span class="lineNum">     104 </span>            :           : _GEN ? 2'(oldCtrs_0 + 2'h1) : 2'(oldCtrs_0 - 2'h1);</a>
+<a name="105"><span class="lineNum">     105 </span>            :   wire        _GEN_0 = io_update_pc[1] ? io_update_takens_0 : io_update_takens_1;</a>
+<a name="106"><span class="lineNum">     106 </span>            :   assign newCtrs_1 =</a>
+<a name="107"><span class="lineNum">     107 </span>            :     (&amp;oldCtrs_1) &amp; _GEN_0</a>
+<a name="108"><span class="lineNum">     108 </span>            :       ? 2'h3</a>
+<a name="109"><span class="lineNum">     109 </span>            :       : oldCtrs_1 == 2'h0 &amp; ~_GEN_0</a>
+<a name="110"><span class="lineNum">     110 </span>            :           ? 2'h0</a>
+<a name="111"><span class="lineNum">     111 </span>            :           : _GEN_0 ? 2'(oldCtrs_1 + 2'h1) : 2'(oldCtrs_1 - 2'h1);</a>
+<a name="112"><span class="lineNum">     112 </span><span class="lineCov">     127730 :   always @(posedge clock or posedge reset) begin</span></a>
+<a name="113"><span class="lineNum">     113 </span><span class="lineCov">        272 :     if (reset) begin</span></a>
+<a name="114"><span class="lineNum">     114 </span><span class="lineCov">        136 :       doing_reset &lt;= 1'h1;</span></a>
+<a name="115"><span class="lineNum">     115 </span><span class="lineCov">        136 :       resetRow &lt;= 11'h0;</span></a>
+<a name="116"><span class="lineNum">     116 </span>            :     end</a>
+<a name="117"><span class="lineNum">     117 </span><span class="lineCov">      63729 :     else begin</span></a>
+<a name="118"><span class="lineNum">     118 </span><span class="lineCov">      63729 :       doing_reset &lt;= resetRow != 11'h7FF &amp; doing_reset;</span></a>
+<a name="119"><span class="lineNum">     119 </span><span class="lineCov">      63729 :       resetRow &lt;= 11'(resetRow + {10'h0, doing_reset});</span></a>
+<a name="120"><span class="lineNum">     120 </span>            :     end</a>
+<a name="121"><span class="lineNum">     121 </span>            :   end // always @(posedge, posedge)</a>
+<a name="122"><span class="lineNum">     122 </span><span class="lineCov">     127694 :   always @(posedge clock) begin</span></a>
+<a name="123"><span class="lineNum">     123 </span><span class="lineCov">       8350 :     if (io_req_valid)</span></a>
+<a name="124"><span class="lineNum">     124 </span><span class="lineCov">       4175 :       s1_idx &lt;= io_req_bits[11:1];</span></a>
+<a name="125"><span class="lineNum">     125 </span>            :   end // always @(posedge)</a>
+<a name="126"><span class="lineNum">     126 </span>            :   `ifdef ENABLE_INITIAL_REG_</a>
+<a name="127"><span class="lineNum">     127 </span>            :     `ifdef FIRRTL_BEFORE_INITIAL</a>
+<a name="128"><span class="lineNum">     128 </span>            :       `FIRRTL_BEFORE_INITIAL</a>
+<a name="129"><span class="lineNum">     129 </span>            :     `endif // FIRRTL_BEFORE_INITIAL</a>
+<a name="130"><span class="lineNum">     130 </span>            :     logic [31:0] _RANDOM[0:0];</a>
+<a name="131"><span class="lineNum">     131 </span><span class="lineCov">         58 :     initial begin</span></a>
+<a name="132"><span class="lineNum">     132 </span>            :       `ifdef INIT_RANDOM_PROLOG_</a>
+<a name="133"><span class="lineNum">     133 </span>            :         `INIT_RANDOM_PROLOG_</a>
+<a name="134"><span class="lineNum">     134 </span>            :       `endif // INIT_RANDOM_PROLOG_</a>
+<a name="135"><span class="lineNum">     135 </span>            :       `ifdef RANDOMIZE_REG_INIT</a>
+<a name="136"><span class="lineNum">     136 </span>            :         _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;</a>
+<a name="137"><span class="lineNum">     137 </span>            :         doing_reset = _RANDOM[/*Zero width*/ 1'b0][0];</a>
+<a name="138"><span class="lineNum">     138 </span>            :         resetRow = _RANDOM[/*Zero width*/ 1'b0][11:1];</a>
+<a name="139"><span class="lineNum">     139 </span>            :         s1_idx = _RANDOM[/*Zero width*/ 1'b0][22:12];</a>
+<a name="140"><span class="lineNum">     140 </span>            :       `endif // RANDOMIZE_REG_INIT</a>
+<a name="141"><span class="lineNum">     141 </span><span class="lineCov">         17 :       if (reset) begin</span></a>
+<a name="142"><span class="lineNum">     142 </span><span class="lineCov">         12 :         doing_reset = 1'h1;</span></a>
+<a name="143"><span class="lineNum">     143 </span><span class="lineCov">         12 :         resetRow = 11'h0;</span></a>
+<a name="144"><span class="lineNum">     144 </span>            :       end</a>
+<a name="145"><span class="lineNum">     145 </span>            :     end // initial</a>
+<a name="146"><span class="lineNum">     146 </span>            :     `ifdef FIRRTL_AFTER_INITIAL</a>
+<a name="147"><span class="lineNum">     147 </span>            :       `FIRRTL_AFTER_INITIAL</a>
+<a name="148"><span class="lineNum">     148 </span>            :     `endif // FIRRTL_AFTER_INITIAL</a>
+<a name="149"><span class="lineNum">     149 </span>            :   `endif // ENABLE_INITIAL_REG_</a>
+<a name="150"><span class="lineNum">     150 </span>            :   FoldedSRAMTemplate_20 bt (</a>
+<a name="151"><span class="lineNum">     151 </span>            :     .clock                 (clock),</a>
+<a name="152"><span class="lineNum">     152 </span>            :     .reset                 (reset),</a>
+<a name="153"><span class="lineNum">     153 </span>            :     .io_r_req_valid        (io_req_valid),</a>
+<a name="154"><span class="lineNum">     154 </span>            :     .io_r_req_bits_setIdx  (io_req_bits[11:1]),</a>
+<a name="155"><span class="lineNum">     155 </span>            :     .io_r_resp_data_0      (_bt_io_r_resp_data_0),</a>
+<a name="156"><span class="lineNum">     156 </span>            :     .io_r_resp_data_1      (_bt_io_r_resp_data_1),</a>
+<a name="157"><span class="lineNum">     157 </span>            :     .io_w_req_valid        (_wrbypass_io_wen_T | doing_reset),</a>
+<a name="158"><span class="lineNum">     158 </span>            :     .io_w_req_bits_setIdx  (doing_reset ? resetRow : io_update_pc[11:1]),</a>
+<a name="159"><span class="lineNum">     159 </span>            :     .io_w_req_bits_data_0  (doing_reset ? 2'h2 : newCtrs_0),</a>
+<a name="160"><span class="lineNum">     160 </span>            :     .io_w_req_bits_data_1  (doing_reset ? 2'h2 : newCtrs_1),</a>
+<a name="161"><span class="lineNum">     161 </span>            :     .io_w_req_bits_waymask</a>
+<a name="162"><span class="lineNum">     162 </span>            :       (doing_reset</a>
+<a name="163"><span class="lineNum">     163 </span>            :          ? 2'h3</a>
+<a name="164"><span class="lineNum">     164 </span>            :          : {io_update_mask_0 &amp; io_update_pc[1] | io_update_mask_1 &amp; ~(io_update_pc[1]),</a>
+<a name="165"><span class="lineNum">     165 </span>            :             io_update_mask_0 &amp; ~(io_update_pc[1]) | io_update_mask_1 &amp; io_update_pc[1]})</a>
+<a name="166"><span class="lineNum">     166 </span>            :   );</a>
+<a name="167"><span class="lineNum">     167 </span>            :   WrBypass_32 wrbypass (</a>
+<a name="168"><span class="lineNum">     168 </span>            :     .clock               (clock),</a>
+<a name="169"><span class="lineNum">     169 </span>            :     .reset               (reset),</a>
+<a name="170"><span class="lineNum">     170 </span>            :     .io_wen              (_wrbypass_io_wen_T),</a>
+<a name="171"><span class="lineNum">     171 </span>            :     .io_write_idx        (io_update_pc[11:1]),</a>
+<a name="172"><span class="lineNum">     172 </span>            :     .io_write_data_0     (io_update_pc[1] ? newCtrs_1 : newCtrs_0),</a>
+<a name="173"><span class="lineNum">     173 </span>            :     .io_write_data_1     (io_update_pc[1] ? newCtrs_0 : newCtrs_1),</a>
+<a name="174"><span class="lineNum">     174 </span>            :     .io_write_way_mask_0 (io_update_mask_0),</a>
+<a name="175"><span class="lineNum">     175 </span>            :     .io_write_way_mask_1 (io_update_mask_1),</a>
+<a name="176"><span class="lineNum">     176 </span>            :     .io_hit              (_wrbypass_io_hit),</a>
+<a name="177"><span class="lineNum">     177 </span>            :     .io_hit_data_0_valid (_wrbypass_io_hit_data_0_valid),</a>
+<a name="178"><span class="lineNum">     178 </span>            :     .io_hit_data_0_bits  (_wrbypass_io_hit_data_0_bits),</a>
+<a name="179"><span class="lineNum">     179 </span>            :     .io_hit_data_1_valid (_wrbypass_io_hit_data_1_valid),</a>
+<a name="180"><span class="lineNum">     180 </span>            :     .io_hit_data_1_bits  (_wrbypass_io_hit_data_1_bits)</a>
+<a name="181"><span class="lineNum">     181 </span>            :   );</a>
+<a name="182"><span class="lineNum">     182 </span>            :   assign io_req_ready = ~doing_reset;</a>
+<a name="183"><span class="lineNum">     183 </span>            :   assign io_s1_cnt_0 =</a>
+<a name="184"><span class="lineNum">     184 </span>            :     (s1_idx[0] ? 2'h0 : _bt_io_r_resp_data_0) | (s1_idx[0] ? _bt_io_r_resp_data_1 : 2'h0);</a>
+<a name="185"><span class="lineNum">     185 </span>            :   assign io_s1_cnt_1 =</a>
+<a name="186"><span class="lineNum">     186 </span>            :     (s1_idx[0] ? _bt_io_r_resp_data_0 : 2'h0) | (s1_idx[0] ? 2'h0 : _bt_io_r_resp_data_1);</a>
+<a name="187"><span class="lineNum">     187 </span>            : endmodule</a>
+<a name="188"><span class="lineNum">     188 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/TageTable.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/TageTable.sv.func-sort-c.html
new file mode 100644
index 0000000..78d4f05
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/TageTable.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/TageTable.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - TageTable.sv<span style="font-size: 80%;"> (<a href="TageTable.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">102</td>
+            <td class="headerCovTableEntry">102</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="TageTable.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/TageTable.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/TageTable.sv.func.html
new file mode 100644
index 0000000..d8aca45
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/TageTable.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/TageTable.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - TageTable.sv<span style="font-size: 80%;"> (<a href="TageTable.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">102</td>
+            <td class="headerCovTableEntry">102</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="TageTable.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/TageTable.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/TageTable.sv.gcov.html
new file mode 100644
index 0000000..db5254f
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/TageTable.sv.gcov.html
@@ -0,0 +1,828 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/TageTable.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - TageTable.sv<span style="font-size: 80%;"> (source / <a href="TageTable.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">102</td>
+            <td class="headerCovTableEntry">102</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : module TageTable(</a>
+<a name="59"><span class="lineNum">      59 </span><span class="lineCov">     127786 :   input         clock,</span></a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">         62 :   input         reset,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">         58 :   output        io_req_ready,</span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">         76 :   input         io_req_valid,</span></a>
+<a name="63"><span class="lineNum">      63 </span><span class="lineCov">      10224 :   input  [40:0] io_req_bits_pc,</span></a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">        295 :   input  [7:0]  io_req_bits_folded_hist_hist_14_folded_hist,</span></a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">        760 :   input  [6:0]  io_req_bits_folded_hist_hist_7_folded_hist,</span></a>
+<a name="66"><span class="lineNum">      66 </span><span class="lineCov">         16 :   output        io_resps_0_valid,</span></a>
+<a name="67"><span class="lineNum">      67 </span><span class="lineCov">        109 :   output [2:0]  io_resps_0_bits_ctr,</span></a>
+<a name="68"><span class="lineNum">      68 </span><span class="lineCov">         34 :   output        io_resps_0_bits_u,</span></a>
+<a name="69"><span class="lineNum">      69 </span><span class="lineCov">         27 :   output        io_resps_0_bits_unconf,</span></a>
+<a name="70"><span class="lineNum">      70 </span><span class="lineCov">         12 :   output        io_resps_1_valid,</span></a>
+<a name="71"><span class="lineNum">      71 </span><span class="lineCov">        110 :   output [2:0]  io_resps_1_bits_ctr,</span></a>
+<a name="72"><span class="lineNum">      72 </span><span class="lineCov">         34 :   output        io_resps_1_bits_u,</span></a>
+<a name="73"><span class="lineNum">      73 </span><span class="lineCov">         31 :   output        io_resps_1_bits_unconf,</span></a>
+<a name="74"><span class="lineNum">      74 </span><span class="lineCov">        615 :   input  [40:0] io_update_pc,</span></a>
+<a name="75"><span class="lineNum">      75 </span><span class="lineCov">        122 :   input  [7:0]  io_update_folded_hist_hist_14_folded_hist,</span></a>
+<a name="76"><span class="lineNum">      76 </span><span class="lineCov">        102 :   input  [6:0]  io_update_folded_hist_hist_7_folded_hist,</span></a>
+<a name="77"><span class="lineNum">      77 </span><span class="lineCov">         32 :   input         io_update_mask_0,</span></a>
+<a name="78"><span class="lineNum">      78 </span><span class="lineCov">         40 :   input         io_update_mask_1,</span></a>
+<a name="79"><span class="lineNum">      79 </span><span class="lineCov">         13 :   input         io_update_takens_0,</span></a>
+<a name="80"><span class="lineNum">      80 </span><span class="lineCov">         20 :   input         io_update_takens_1,</span></a>
+<a name="81"><span class="lineNum">      81 </span><span class="lineCov">         15 :   input         io_update_alloc_0,</span></a>
+<a name="82"><span class="lineNum">      82 </span><span class="lineCov">         15 :   input         io_update_alloc_1,</span></a>
+<a name="83"><span class="lineNum">      83 </span><span class="lineCov">         42 :   input  [2:0]  io_update_oldCtrs_0,</span></a>
+<a name="84"><span class="lineNum">      84 </span><span class="lineCov">         38 :   input  [2:0]  io_update_oldCtrs_1,</span></a>
+<a name="85"><span class="lineNum">      85 </span><span class="lineCov">         14 :   input         io_update_uMask_0,</span></a>
+<a name="86"><span class="lineNum">      86 </span><span class="lineCov">         13 :   input         io_update_uMask_1,</span></a>
+<a name="87"><span class="lineNum">      87 </span><span class="lineCov">         11 :   input         io_update_us_0,</span></a>
+<a name="88"><span class="lineNum">      88 </span><span class="lineCov">         12 :   input         io_update_us_1,</span></a>
+<a name="89"><span class="lineNum">      89 </span><span class="lineCov">         38 :   input         io_update_reset_u_0,</span></a>
+<a name="90"><span class="lineNum">      90 </span><span class="lineCov">         31 :   input         io_update_reset_u_1</span></a>
+<a name="91"><span class="lineNum">      91 </span>            : );</a>
+<a name="92"><span class="lineNum">      92 </span>            : </a>
+<a name="93"><span class="lineNum">      93 </span><span class="lineCov">         15 :   wire        per_bank_not_silent_update_3_1;</span></a>
+<a name="94"><span class="lineNum">      94 </span><span class="lineCov">         18 :   wire        per_bank_not_silent_update_3_0;</span></a>
+<a name="95"><span class="lineNum">      95 </span><span class="lineCov">         16 :   wire        per_bank_not_silent_update_2_1;</span></a>
+<a name="96"><span class="lineNum">      96 </span><span class="lineCov">         19 :   wire        per_bank_not_silent_update_2_0;</span></a>
+<a name="97"><span class="lineNum">      97 </span><span class="lineCov">         15 :   wire        per_bank_not_silent_update_1_1;</span></a>
+<a name="98"><span class="lineNum">      98 </span><span class="lineCov">         14 :   wire        per_bank_not_silent_update_1_0;</span></a>
+<a name="99"><span class="lineNum">      99 </span><span class="lineCov">         14 :   wire        per_bank_not_silent_update_0_1;</span></a>
+<a name="100"><span class="lineNum">     100 </span><span class="lineCov">         16 :   wire        per_bank_not_silent_update_0_0;</span></a>
+<a name="101"><span class="lineNum">     101 </span><span class="lineCov">         52 :   reg         powerOnResetState;</span></a>
+<a name="102"><span class="lineNum">     102 </span>            :   wire        _resp_invalid_by_write_T_6;</a>
+<a name="103"><span class="lineNum">     103 </span>            :   wire        _bank_wrbypasses_3_1_io_hit;</a>
+<a name="104"><span class="lineNum">     104 </span>            :   wire        _bank_wrbypasses_3_1_io_hit_data_0_valid;</a>
+<a name="105"><span class="lineNum">     105 </span>            :   wire [2:0]  _bank_wrbypasses_3_1_io_hit_data_0_bits;</a>
+<a name="106"><span class="lineNum">     106 </span>            :   wire        _bank_wrbypasses_3_0_io_hit;</a>
+<a name="107"><span class="lineNum">     107 </span>            :   wire        _bank_wrbypasses_3_0_io_hit_data_0_valid;</a>
+<a name="108"><span class="lineNum">     108 </span>            :   wire [2:0]  _bank_wrbypasses_3_0_io_hit_data_0_bits;</a>
+<a name="109"><span class="lineNum">     109 </span>            :   wire        _bank_wrbypasses_2_1_io_hit;</a>
+<a name="110"><span class="lineNum">     110 </span>            :   wire        _bank_wrbypasses_2_1_io_hit_data_0_valid;</a>
+<a name="111"><span class="lineNum">     111 </span>            :   wire [2:0]  _bank_wrbypasses_2_1_io_hit_data_0_bits;</a>
+<a name="112"><span class="lineNum">     112 </span>            :   wire        _bank_wrbypasses_2_0_io_hit;</a>
+<a name="113"><span class="lineNum">     113 </span>            :   wire        _bank_wrbypasses_2_0_io_hit_data_0_valid;</a>
+<a name="114"><span class="lineNum">     114 </span>            :   wire [2:0]  _bank_wrbypasses_2_0_io_hit_data_0_bits;</a>
+<a name="115"><span class="lineNum">     115 </span>            :   wire        _bank_wrbypasses_1_1_io_hit;</a>
+<a name="116"><span class="lineNum">     116 </span>            :   wire        _bank_wrbypasses_1_1_io_hit_data_0_valid;</a>
+<a name="117"><span class="lineNum">     117 </span>            :   wire [2:0]  _bank_wrbypasses_1_1_io_hit_data_0_bits;</a>
+<a name="118"><span class="lineNum">     118 </span>            :   wire        _bank_wrbypasses_1_0_io_hit;</a>
+<a name="119"><span class="lineNum">     119 </span>            :   wire        _bank_wrbypasses_1_0_io_hit_data_0_valid;</a>
+<a name="120"><span class="lineNum">     120 </span>            :   wire [2:0]  _bank_wrbypasses_1_0_io_hit_data_0_bits;</a>
+<a name="121"><span class="lineNum">     121 </span>            :   wire        _bank_wrbypasses_0_1_io_hit;</a>
+<a name="122"><span class="lineNum">     122 </span>            :   wire        _bank_wrbypasses_0_1_io_hit_data_0_valid;</a>
+<a name="123"><span class="lineNum">     123 </span>            :   wire [2:0]  _bank_wrbypasses_0_1_io_hit_data_0_bits;</a>
+<a name="124"><span class="lineNum">     124 </span>            :   wire        _bank_wrbypasses_0_0_io_hit;</a>
+<a name="125"><span class="lineNum">     125 </span>            :   wire        _bank_wrbypasses_0_0_io_hit_data_0_valid;</a>
+<a name="126"><span class="lineNum">     126 </span>            :   wire [2:0]  _bank_wrbypasses_0_0_io_hit_data_0_bits;</a>
+<a name="127"><span class="lineNum">     127 </span>            :   wire        _table_banks_3_io_r_req_ready;</a>
+<a name="128"><span class="lineNum">     128 </span>            :   wire        _table_banks_3_io_r_resp_data_0_valid;</a>
+<a name="129"><span class="lineNum">     129 </span>            :   wire [7:0]  _table_banks_3_io_r_resp_data_0_tag;</a>
+<a name="130"><span class="lineNum">     130 </span>            :   wire [2:0]  _table_banks_3_io_r_resp_data_0_ctr;</a>
+<a name="131"><span class="lineNum">     131 </span>            :   wire        _table_banks_3_io_r_resp_data_1_valid;</a>
+<a name="132"><span class="lineNum">     132 </span>            :   wire [7:0]  _table_banks_3_io_r_resp_data_1_tag;</a>
+<a name="133"><span class="lineNum">     133 </span>            :   wire [2:0]  _table_banks_3_io_r_resp_data_1_ctr;</a>
+<a name="134"><span class="lineNum">     134 </span>            :   wire        _table_banks_2_io_r_req_ready;</a>
+<a name="135"><span class="lineNum">     135 </span>            :   wire        _table_banks_2_io_r_resp_data_0_valid;</a>
+<a name="136"><span class="lineNum">     136 </span>            :   wire [7:0]  _table_banks_2_io_r_resp_data_0_tag;</a>
+<a name="137"><span class="lineNum">     137 </span>            :   wire [2:0]  _table_banks_2_io_r_resp_data_0_ctr;</a>
+<a name="138"><span class="lineNum">     138 </span>            :   wire        _table_banks_2_io_r_resp_data_1_valid;</a>
+<a name="139"><span class="lineNum">     139 </span>            :   wire [7:0]  _table_banks_2_io_r_resp_data_1_tag;</a>
+<a name="140"><span class="lineNum">     140 </span>            :   wire [2:0]  _table_banks_2_io_r_resp_data_1_ctr;</a>
+<a name="141"><span class="lineNum">     141 </span>            :   wire        _table_banks_1_io_r_req_ready;</a>
+<a name="142"><span class="lineNum">     142 </span>            :   wire        _table_banks_1_io_r_resp_data_0_valid;</a>
+<a name="143"><span class="lineNum">     143 </span>            :   wire [7:0]  _table_banks_1_io_r_resp_data_0_tag;</a>
+<a name="144"><span class="lineNum">     144 </span>            :   wire [2:0]  _table_banks_1_io_r_resp_data_0_ctr;</a>
+<a name="145"><span class="lineNum">     145 </span>            :   wire        _table_banks_1_io_r_resp_data_1_valid;</a>
+<a name="146"><span class="lineNum">     146 </span>            :   wire [7:0]  _table_banks_1_io_r_resp_data_1_tag;</a>
+<a name="147"><span class="lineNum">     147 </span>            :   wire [2:0]  _table_banks_1_io_r_resp_data_1_ctr;</a>
+<a name="148"><span class="lineNum">     148 </span>            :   wire        _table_banks_0_io_r_req_ready;</a>
+<a name="149"><span class="lineNum">     149 </span>            :   wire        _table_banks_0_io_r_resp_data_0_valid;</a>
+<a name="150"><span class="lineNum">     150 </span>            :   wire [7:0]  _table_banks_0_io_r_resp_data_0_tag;</a>
+<a name="151"><span class="lineNum">     151 </span>            :   wire [2:0]  _table_banks_0_io_r_resp_data_0_ctr;</a>
+<a name="152"><span class="lineNum">     152 </span>            :   wire        _table_banks_0_io_r_resp_data_1_valid;</a>
+<a name="153"><span class="lineNum">     153 </span>            :   wire [7:0]  _table_banks_0_io_r_resp_data_1_tag;</a>
+<a name="154"><span class="lineNum">     154 </span>            :   wire [2:0]  _table_banks_0_io_r_resp_data_1_ctr;</a>
+<a name="155"><span class="lineNum">     155 </span>            :   wire        _us_io_r_req_ready;</a>
+<a name="156"><span class="lineNum">     156 </span>            :   wire        _us_io_r_resp_data_0;</a>
+<a name="157"><span class="lineNum">     157 </span>            :   wire        _us_io_r_resp_data_1;</a>
+<a name="158"><span class="lineNum">     158 </span>            :   wire        _us_extra_reset_T_1 = io_update_mask_0 | io_update_mask_1;</a>
+<a name="159"><span class="lineNum">     159 </span>            :   wire [7:0]  _GEN = io_req_bits_pc[8:1] ^ io_req_bits_folded_hist_hist_14_folded_hist;</a>
+<a name="160"><span class="lineNum">     160 </span><span class="lineCov">         69 :   wire        s0_bank_req_1h_0 = _GEN[1:0] == 2'h0;</span></a>
+<a name="161"><span class="lineNum">     161 </span><span class="lineCov">         66 :   wire        s0_bank_req_1h_1 = _GEN[1:0] == 2'h1;</span></a>
+<a name="162"><span class="lineNum">     162 </span><span class="lineCov">         47 :   wire        s0_bank_req_1h_2 = _GEN[1:0] == 2'h2;</span></a>
+<a name="163"><span class="lineNum">     163 </span>            :   wire        _s1_bank_req_1h_T = ~powerOnResetState &amp; io_req_valid;</a>
+<a name="164"><span class="lineNum">     164 </span>            :   wire [8:0]  _table_banks_3_io_r_req_bits_setIdx_T = {io_req_bits_pc[11:9], _GEN[7:2]};</a>
+<a name="165"><span class="lineNum">     165 </span><span class="lineCov">       9328 :   reg  [39:0] s1_unhashed_idx;</span></a>
+<a name="166"><span class="lineNum">     166 </span><span class="lineCov">       8020 :   reg  [7:0]  s1_tag;</span></a>
+<a name="167"><span class="lineNum">     167 </span><span class="lineCov">         39 :   reg         s1_bank_req_1h_0;</span></a>
+<a name="168"><span class="lineNum">     168 </span><span class="lineCov">         55 :   reg         s1_bank_req_1h_1;</span></a>
+<a name="169"><span class="lineNum">     169 </span><span class="lineCov">         45 :   reg         s1_bank_req_1h_2;</span></a>
+<a name="170"><span class="lineNum">     170 </span><span class="lineCov">         30 :   reg         s1_bank_req_1h_3;</span></a>
+<a name="171"><span class="lineNum">     171 </span><span class="lineCov">         31 :   reg         s1_bank_has_write_on_this_req_0;</span></a>
+<a name="172"><span class="lineNum">     172 </span><span class="lineCov">         27 :   reg         s1_bank_has_write_on_this_req_1;</span></a>
+<a name="173"><span class="lineNum">     173 </span><span class="lineCov">         26 :   reg         s1_bank_has_write_on_this_req_2;</span></a>
+<a name="174"><span class="lineNum">     174 </span><span class="lineCov">         26 :   reg         s1_bank_has_write_on_this_req_3;</span></a>
+<a name="175"><span class="lineNum">     175 </span>            :   wire [2:0]  _resp_selected_T_6 =</a>
+<a name="176"><span class="lineNum">     176 </span>            :     (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_ctr : 3'h0)</a>
+<a name="177"><span class="lineNum">     177 </span>            :     | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 3'h0)</a>
+<a name="178"><span class="lineNum">     178 </span>            :     | (s1_bank_req_1h_2 ? _table_banks_2_io_r_resp_data_0_ctr : 3'h0)</a>
+<a name="179"><span class="lineNum">     179 </span>            :     | (s1_bank_req_1h_3 ? _table_banks_3_io_r_resp_data_0_ctr : 3'h0);</a>
+<a name="180"><span class="lineNum">     180 </span>            :   wire [2:0]  _resp_selected_T_27 =</a>
+<a name="181"><span class="lineNum">     181 </span>            :     (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_1_ctr : 3'h0)</a>
+<a name="182"><span class="lineNum">     182 </span>            :     | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_1_ctr : 3'h0)</a>
+<a name="183"><span class="lineNum">     183 </span>            :     | (s1_bank_req_1h_2 ? _table_banks_2_io_r_resp_data_1_ctr : 3'h0)</a>
+<a name="184"><span class="lineNum">     184 </span>            :     | (s1_bank_req_1h_3 ? _table_banks_3_io_r_resp_data_1_ctr : 3'h0);</a>
+<a name="185"><span class="lineNum">     185 </span>            :   wire        _unconf_selected_T_6 =</a>
+<a name="186"><span class="lineNum">     186 </span>            :     s1_bank_req_1h_0</a>
+<a name="187"><span class="lineNum">     187 </span>            :     &amp; (_table_banks_0_io_r_resp_data_0_ctr == 3'h4</a>
+<a name="188"><span class="lineNum">     188 </span>            :        | _table_banks_0_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_1</a>
+<a name="189"><span class="lineNum">     189 </span>            :     &amp; (_table_banks_1_io_r_resp_data_0_ctr == 3'h4</a>
+<a name="190"><span class="lineNum">     190 </span>            :        | _table_banks_1_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_2</a>
+<a name="191"><span class="lineNum">     191 </span>            :     &amp; (_table_banks_2_io_r_resp_data_0_ctr == 3'h4</a>
+<a name="192"><span class="lineNum">     192 </span>            :        | _table_banks_2_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_3</a>
+<a name="193"><span class="lineNum">     193 </span>            :     &amp; (_table_banks_3_io_r_resp_data_0_ctr == 3'h4</a>
+<a name="194"><span class="lineNum">     194 </span>            :        | _table_banks_3_io_r_resp_data_0_ctr == 3'h3);</a>
+<a name="195"><span class="lineNum">     195 </span>            :   wire        _unconf_selected_T_13 =</a>
+<a name="196"><span class="lineNum">     196 </span>            :     s1_bank_req_1h_0</a>
+<a name="197"><span class="lineNum">     197 </span>            :     &amp; (_table_banks_0_io_r_resp_data_1_ctr == 3'h4</a>
+<a name="198"><span class="lineNum">     198 </span>            :        | _table_banks_0_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_1</a>
+<a name="199"><span class="lineNum">     199 </span>            :     &amp; (_table_banks_1_io_r_resp_data_1_ctr == 3'h4</a>
+<a name="200"><span class="lineNum">     200 </span>            :        | _table_banks_1_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_2</a>
+<a name="201"><span class="lineNum">     201 </span>            :     &amp; (_table_banks_2_io_r_resp_data_1_ctr == 3'h4</a>
+<a name="202"><span class="lineNum">     202 </span>            :        | _table_banks_2_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_3</a>
+<a name="203"><span class="lineNum">     203 </span>            :     &amp; (_table_banks_3_io_r_resp_data_1_ctr == 3'h4</a>
+<a name="204"><span class="lineNum">     204 </span>            :        | _table_banks_3_io_r_resp_data_1_ctr == 3'h3);</a>
+<a name="205"><span class="lineNum">     205 </span>            :   wire        _hit_selected_T_6 =</a>
+<a name="206"><span class="lineNum">     206 </span>            :     s1_bank_req_1h_0 &amp; _table_banks_0_io_r_resp_data_0_tag == s1_tag</a>
+<a name="207"><span class="lineNum">     207 </span>            :     &amp; _table_banks_0_io_r_resp_data_0_valid &amp; ~_resp_invalid_by_write_T_6</a>
+<a name="208"><span class="lineNum">     208 </span>            :     | s1_bank_req_1h_1 &amp; _table_banks_1_io_r_resp_data_0_tag == s1_tag</a>
+<a name="209"><span class="lineNum">     209 </span>            :     &amp; _table_banks_1_io_r_resp_data_0_valid &amp; ~_resp_invalid_by_write_T_6</a>
+<a name="210"><span class="lineNum">     210 </span>            :     | s1_bank_req_1h_2 &amp; _table_banks_2_io_r_resp_data_0_tag == s1_tag</a>
+<a name="211"><span class="lineNum">     211 </span>            :     &amp; _table_banks_2_io_r_resp_data_0_valid &amp; ~_resp_invalid_by_write_T_6</a>
+<a name="212"><span class="lineNum">     212 </span>            :     | s1_bank_req_1h_3 &amp; _table_banks_3_io_r_resp_data_0_tag == s1_tag</a>
+<a name="213"><span class="lineNum">     213 </span>            :     &amp; _table_banks_3_io_r_resp_data_0_valid &amp; ~_resp_invalid_by_write_T_6;</a>
+<a name="214"><span class="lineNum">     214 </span>            :   wire        _hit_selected_T_13 =</a>
+<a name="215"><span class="lineNum">     215 </span>            :     s1_bank_req_1h_0 &amp; _table_banks_0_io_r_resp_data_1_tag == s1_tag</a>
+<a name="216"><span class="lineNum">     216 </span>            :     &amp; _table_banks_0_io_r_resp_data_1_valid &amp; ~_resp_invalid_by_write_T_6</a>
+<a name="217"><span class="lineNum">     217 </span>            :     | s1_bank_req_1h_1 &amp; _table_banks_1_io_r_resp_data_1_tag == s1_tag</a>
+<a name="218"><span class="lineNum">     218 </span>            :     &amp; _table_banks_1_io_r_resp_data_1_valid &amp; ~_resp_invalid_by_write_T_6</a>
+<a name="219"><span class="lineNum">     219 </span>            :     | s1_bank_req_1h_2 &amp; _table_banks_2_io_r_resp_data_1_tag == s1_tag</a>
+<a name="220"><span class="lineNum">     220 </span>            :     &amp; _table_banks_2_io_r_resp_data_1_valid &amp; ~_resp_invalid_by_write_T_6</a>
+<a name="221"><span class="lineNum">     221 </span>            :     | s1_bank_req_1h_3 &amp; _table_banks_3_io_r_resp_data_1_tag == s1_tag</a>
+<a name="222"><span class="lineNum">     222 </span>            :     &amp; _table_banks_3_io_r_resp_data_1_valid &amp; ~_resp_invalid_by_write_T_6;</a>
+<a name="223"><span class="lineNum">     223 </span>            :   assign _resp_invalid_by_write_T_6 =</a>
+<a name="224"><span class="lineNum">     224 </span>            :     s1_bank_req_1h_0 &amp; s1_bank_has_write_on_this_req_0 | s1_bank_req_1h_1</a>
+<a name="225"><span class="lineNum">     225 </span>            :     &amp; s1_bank_has_write_on_this_req_1 | s1_bank_req_1h_2 &amp; s1_bank_has_write_on_this_req_2</a>
+<a name="226"><span class="lineNum">     226 </span>            :     | s1_bank_req_1h_3 &amp; s1_bank_has_write_on_this_req_3;</a>
+<a name="227"><span class="lineNum">     227 </span>            :   wire [7:0]  _GEN_0 = io_update_pc[8:1] ^ io_update_folded_hist_hist_14_folded_hist;</a>
+<a name="228"><span class="lineNum">     228 </span><span class="lineCov">        112 :   wire [7:0]  update_tag = _GEN_0 ^ {io_update_folded_hist_hist_7_folded_hist, 1'h0};</span></a>
+<a name="229"><span class="lineNum">     229 </span><span class="lineCov">         13 :   wire        update_req_bank_1h_0 = _GEN_0[1:0] == 2'h0;</span></a>
+<a name="230"><span class="lineNum">     230 </span><span class="lineCov">         19 :   wire        update_req_bank_1h_1 = _GEN_0[1:0] == 2'h1;</span></a>
+<a name="231"><span class="lineNum">     231 </span><span class="lineCov">         16 :   wire        update_req_bank_1h_2 = _GEN_0[1:0] == 2'h2;</span></a>
+<a name="232"><span class="lineNum">     232 </span><span class="lineCov">        122 :   wire [8:0]  update_idx_in_bank = {io_update_pc[11:9], _GEN_0[7:2]};</span></a>
+<a name="233"><span class="lineNum">     233 </span><span class="lineCov">         65 :   wire [1:0]  per_bank_update_way_mask_0 =</span></a>
+<a name="234"><span class="lineNum">     234 </span>            :     {(io_update_pc[1] &amp; io_update_mask_0 | ~(io_update_pc[1]) &amp; io_update_mask_1)</a>
+<a name="235"><span class="lineNum">     235 </span>            :        &amp; per_bank_not_silent_update_0_1,</a>
+<a name="236"><span class="lineNum">     236 </span>            :      (~(io_update_pc[1]) &amp; io_update_mask_0 | io_update_pc[1] &amp; io_update_mask_1)</a>
+<a name="237"><span class="lineNum">     237 </span>            :        &amp; per_bank_not_silent_update_0_0};</a>
+<a name="238"><span class="lineNum">     238 </span><span class="lineCov">         68 :   wire [1:0]  per_bank_update_way_mask_1 =</span></a>
+<a name="239"><span class="lineNum">     239 </span>            :     {(io_update_pc[1] &amp; io_update_mask_0 | ~(io_update_pc[1]) &amp; io_update_mask_1)</a>
+<a name="240"><span class="lineNum">     240 </span>            :        &amp; per_bank_not_silent_update_1_1,</a>
+<a name="241"><span class="lineNum">     241 </span>            :      (~(io_update_pc[1]) &amp; io_update_mask_0 | io_update_pc[1] &amp; io_update_mask_1)</a>
+<a name="242"><span class="lineNum">     242 </span>            :        &amp; per_bank_not_silent_update_1_0};</a>
+<a name="243"><span class="lineNum">     243 </span><span class="lineCov">         68 :   wire [1:0]  per_bank_update_way_mask_2 =</span></a>
+<a name="244"><span class="lineNum">     244 </span>            :     {(io_update_pc[1] &amp; io_update_mask_0 | ~(io_update_pc[1]) &amp; io_update_mask_1)</a>
+<a name="245"><span class="lineNum">     245 </span>            :        &amp; per_bank_not_silent_update_2_1,</a>
+<a name="246"><span class="lineNum">     246 </span>            :      (~(io_update_pc[1]) &amp; io_update_mask_0 | io_update_pc[1] &amp; io_update_mask_1)</a>
+<a name="247"><span class="lineNum">     247 </span>            :        &amp; per_bank_not_silent_update_2_0};</a>
+<a name="248"><span class="lineNum">     248 </span><span class="lineCov">         71 :   wire [1:0]  per_bank_update_way_mask_3 =</span></a>
+<a name="249"><span class="lineNum">     249 </span>            :     {(io_update_pc[1] &amp; io_update_mask_0 | ~(io_update_pc[1]) &amp; io_update_mask_1)</a>
+<a name="250"><span class="lineNum">     250 </span>            :        &amp; per_bank_not_silent_update_3_1,</a>
+<a name="251"><span class="lineNum">     251 </span>            :      (~(io_update_pc[1]) &amp; io_update_mask_0 | io_update_pc[1] &amp; io_update_mask_1)</a>
+<a name="252"><span class="lineNum">     252 </span>            :        &amp; per_bank_not_silent_update_3_0};</a>
+<a name="253"><span class="lineNum">     253 </span>            :   wire        _s1_bank_has_write_on_this_req_WIRE_0 =</a>
+<a name="254"><span class="lineNum">     254 </span>            :     (|per_bank_update_way_mask_0) &amp; update_req_bank_1h_0;</a>
+<a name="255"><span class="lineNum">     255 </span>            :   wire        _s1_bank_has_write_on_this_req_WIRE_1 =</a>
+<a name="256"><span class="lineNum">     256 </span>            :     (|per_bank_update_way_mask_1) &amp; update_req_bank_1h_1;</a>
+<a name="257"><span class="lineNum">     257 </span>            :   wire        _s1_bank_has_write_on_this_req_WIRE_2 =</a>
+<a name="258"><span class="lineNum">     258 </span>            :     (|per_bank_update_way_mask_2) &amp; update_req_bank_1h_2;</a>
+<a name="259"><span class="lineNum">     259 </span>            :   wire        _s1_bank_has_write_on_this_req_WIRE_3 =</a>
+<a name="260"><span class="lineNum">     260 </span>            :     (|per_bank_update_way_mask_3) &amp; (&amp;(_GEN_0[1:0]));</a>
+<a name="261"><span class="lineNum">     261 </span>            :   wire [2:0]  _wrbypass_io_T_6 =</a>
+<a name="262"><span class="lineNum">     262 </span>            :     (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_0_0_io_hit_data_0_bits)</a>
+<a name="263"><span class="lineNum">     263 </span>            :     | (io_update_pc[1] ? _bank_wrbypasses_0_1_io_hit_data_0_bits : 3'h0);</a>
+<a name="264"><span class="lineNum">     264 </span><span class="lineCov">         22 :   wire        wrbypass_data_valid =</span></a>
+<a name="265"><span class="lineNum">     265 </span>            :     (~(io_update_pc[1]) &amp; _bank_wrbypasses_0_0_io_hit | io_update_pc[1]</a>
+<a name="266"><span class="lineNum">     266 </span>            :      &amp; _bank_wrbypasses_0_1_io_hit)</a>
+<a name="267"><span class="lineNum">     267 </span>            :     &amp; (~(io_update_pc[1]) &amp; _bank_wrbypasses_0_0_io_hit_data_0_valid | io_update_pc[1]</a>
+<a name="268"><span class="lineNum">     268 </span>            :        &amp; _bank_wrbypasses_0_1_io_hit_data_0_valid);</a>
+<a name="269"><span class="lineNum">     269 </span>            :   wire        _GEN_1 = io_update_pc[1] ? io_update_takens_1 : io_update_takens_0;</a>
+<a name="270"><span class="lineNum">     270 </span>            :   wire [2:0]  _GEN_2 = io_update_pc[1] ? io_update_oldCtrs_1 : io_update_oldCtrs_0;</a>
+<a name="271"><span class="lineNum">     271 </span>            :   wire        _GEN_3 = (|_GEN_2) | _GEN_1;</a>
+<a name="272"><span class="lineNum">     272 </span>            :   wire        _GEN_4 = io_update_pc[1] ? io_update_alloc_1 : io_update_alloc_0;</a>
+<a name="273"><span class="lineNum">     273 </span><span class="lineCov">         46 :   wire [2:0]  per_bank_update_wdata_0_0_ctr =</span></a>
+<a name="274"><span class="lineNum">     274 </span>            :     _GEN_4</a>
+<a name="275"><span class="lineNum">     275 </span>            :       ? (_GEN_1 ? 3'h4 : 3'h3)</a>
+<a name="276"><span class="lineNum">     276 </span>            :       : wrbypass_data_valid</a>
+<a name="277"><span class="lineNum">     277 </span>            :           ? ((&amp;_wrbypass_io_T_6) &amp; _GEN_1</a>
+<a name="278"><span class="lineNum">     278 </span>            :                ? 3'h7</a>
+<a name="279"><span class="lineNum">     279 </span>            :                : _wrbypass_io_T_6 == 3'h0 &amp; ~_GEN_1</a>
+<a name="280"><span class="lineNum">     280 </span>            :                    ? 3'h0</a>
+<a name="281"><span class="lineNum">     281 </span>            :                    : _GEN_1 ? 3'(_wrbypass_io_T_6 + 3'h1) : 3'(_wrbypass_io_T_6 - 3'h1))</a>
+<a name="282"><span class="lineNum">     282 </span>            :           : (&amp;_GEN_2) &amp; _GEN_1</a>
+<a name="283"><span class="lineNum">     283 </span>            :               ? 3'h7</a>
+<a name="284"><span class="lineNum">     284 </span>            :               : _GEN_3 ? (_GEN_1 ? 3'(_GEN_2 + 3'h1) : 3'(_GEN_2 - 3'h1)) : 3'h0;</a>
+<a name="285"><span class="lineNum">     285 </span>            :   assign per_bank_not_silent_update_0_0 =</a>
+<a name="286"><span class="lineNum">     286 </span>            :     (wrbypass_data_valid</a>
+<a name="287"><span class="lineNum">     287 </span>            :        ? ~((&amp;_wrbypass_io_T_6) &amp; _GEN_1 | _wrbypass_io_T_6 == 3'h0 &amp; ~_GEN_1)</a>
+<a name="288"><span class="lineNum">     288 </span>            :        : ~((&amp;_GEN_2) &amp; _GEN_1 | _GEN_2 == 3'h0 &amp; ~_GEN_1)) | _GEN_4;</a>
+<a name="289"><span class="lineNum">     289 </span>            :   wire [2:0]  _wrbypass_io_T_28 =</a>
+<a name="290"><span class="lineNum">     290 </span>            :     (io_update_pc[1] ? _bank_wrbypasses_0_0_io_hit_data_0_bits : 3'h0)</a>
+<a name="291"><span class="lineNum">     291 </span>            :     | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_0_1_io_hit_data_0_bits);</a>
+<a name="292"><span class="lineNum">     292 </span><span class="lineCov">         18 :   wire        wrbypass_data_valid_1 =</span></a>
+<a name="293"><span class="lineNum">     293 </span>            :     (io_update_pc[1] &amp; _bank_wrbypasses_0_0_io_hit | ~(io_update_pc[1])</a>
+<a name="294"><span class="lineNum">     294 </span>            :      &amp; _bank_wrbypasses_0_1_io_hit)</a>
+<a name="295"><span class="lineNum">     295 </span>            :     &amp; (io_update_pc[1] &amp; _bank_wrbypasses_0_0_io_hit_data_0_valid | ~(io_update_pc[1])</a>
+<a name="296"><span class="lineNum">     296 </span>            :        &amp; _bank_wrbypasses_0_1_io_hit_data_0_valid);</a>
+<a name="297"><span class="lineNum">     297 </span>            :   wire        _GEN_5 = io_update_pc[1] ? io_update_takens_0 : io_update_takens_1;</a>
+<a name="298"><span class="lineNum">     298 </span>            :   wire [2:0]  _GEN_6 = io_update_pc[1] ? io_update_oldCtrs_0 : io_update_oldCtrs_1;</a>
+<a name="299"><span class="lineNum">     299 </span>            :   wire        _GEN_7 = io_update_pc[1] ? io_update_alloc_0 : io_update_alloc_1;</a>
+<a name="300"><span class="lineNum">     300 </span><span class="lineCov">         43 :   wire [2:0]  per_bank_update_wdata_0_1_ctr =</span></a>
+<a name="301"><span class="lineNum">     301 </span>            :     _GEN_7</a>
+<a name="302"><span class="lineNum">     302 </span>            :       ? (_GEN_5 ? 3'h4 : 3'h3)</a>
+<a name="303"><span class="lineNum">     303 </span>            :       : wrbypass_data_valid_1</a>
+<a name="304"><span class="lineNum">     304 </span>            :           ? ((&amp;_wrbypass_io_T_28) &amp; _GEN_5</a>
+<a name="305"><span class="lineNum">     305 </span>            :                ? 3'h7</a>
+<a name="306"><span class="lineNum">     306 </span>            :                : _wrbypass_io_T_28 == 3'h0 &amp; ~_GEN_5</a>
+<a name="307"><span class="lineNum">     307 </span>            :                    ? 3'h0</a>
+<a name="308"><span class="lineNum">     308 </span>            :                    : _GEN_5 ? 3'(_wrbypass_io_T_28 + 3'h1) : 3'(_wrbypass_io_T_28 - 3'h1))</a>
+<a name="309"><span class="lineNum">     309 </span>            :           : (&amp;_GEN_6) &amp; _GEN_5</a>
+<a name="310"><span class="lineNum">     310 </span>            :               ? 3'h7</a>
+<a name="311"><span class="lineNum">     311 </span>            :               : _GEN_6 == 3'h0 &amp; ~_GEN_5</a>
+<a name="312"><span class="lineNum">     312 </span>            :                   ? 3'h0</a>
+<a name="313"><span class="lineNum">     313 </span>            :                   : _GEN_5 ? 3'(_GEN_6 + 3'h1) : 3'(_GEN_6 - 3'h1);</a>
+<a name="314"><span class="lineNum">     314 </span>            :   assign per_bank_not_silent_update_0_1 =</a>
+<a name="315"><span class="lineNum">     315 </span>            :     (wrbypass_data_valid_1</a>
+<a name="316"><span class="lineNum">     316 </span>            :        ? ~((&amp;_wrbypass_io_T_28) &amp; _GEN_5 | _wrbypass_io_T_28 == 3'h0 &amp; ~_GEN_5)</a>
+<a name="317"><span class="lineNum">     317 </span>            :        : ~((&amp;_GEN_6) &amp; _GEN_5 | _GEN_6 == 3'h0 &amp; ~_GEN_5)) | _GEN_7;</a>
+<a name="318"><span class="lineNum">     318 </span>            :   wire [2:0]  _wrbypass_io_T_50 =</a>
+<a name="319"><span class="lineNum">     319 </span>            :     (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_1_0_io_hit_data_0_bits)</a>
+<a name="320"><span class="lineNum">     320 </span>            :     | (io_update_pc[1] ? _bank_wrbypasses_1_1_io_hit_data_0_bits : 3'h0);</a>
+<a name="321"><span class="lineNum">     321 </span><span class="lineCov">         21 :   wire        wrbypass_data_valid_2 =</span></a>
+<a name="322"><span class="lineNum">     322 </span>            :     (~(io_update_pc[1]) &amp; _bank_wrbypasses_1_0_io_hit | io_update_pc[1]</a>
+<a name="323"><span class="lineNum">     323 </span>            :      &amp; _bank_wrbypasses_1_1_io_hit)</a>
+<a name="324"><span class="lineNum">     324 </span>            :     &amp; (~(io_update_pc[1]) &amp; _bank_wrbypasses_1_0_io_hit_data_0_valid | io_update_pc[1]</a>
+<a name="325"><span class="lineNum">     325 </span>            :        &amp; _bank_wrbypasses_1_1_io_hit_data_0_valid);</a>
+<a name="326"><span class="lineNum">     326 </span><span class="lineCov">         50 :   wire [2:0]  per_bank_update_wdata_1_0_ctr =</span></a>
+<a name="327"><span class="lineNum">     327 </span>            :     _GEN_4</a>
+<a name="328"><span class="lineNum">     328 </span>            :       ? (_GEN_1 ? 3'h4 : 3'h3)</a>
+<a name="329"><span class="lineNum">     329 </span>            :       : wrbypass_data_valid_2</a>
+<a name="330"><span class="lineNum">     330 </span>            :           ? ((&amp;_wrbypass_io_T_50) &amp; _GEN_1</a>
+<a name="331"><span class="lineNum">     331 </span>            :                ? 3'h7</a>
+<a name="332"><span class="lineNum">     332 </span>            :                : _wrbypass_io_T_50 == 3'h0 &amp; ~_GEN_1</a>
+<a name="333"><span class="lineNum">     333 </span>            :                    ? 3'h0</a>
+<a name="334"><span class="lineNum">     334 </span>            :                    : _GEN_1 ? 3'(_wrbypass_io_T_50 + 3'h1) : 3'(_wrbypass_io_T_50 - 3'h1))</a>
+<a name="335"><span class="lineNum">     335 </span>            :           : (&amp;_GEN_2) &amp; _GEN_1</a>
+<a name="336"><span class="lineNum">     336 </span>            :               ? 3'h7</a>
+<a name="337"><span class="lineNum">     337 </span>            :               : _GEN_3 ? (_GEN_1 ? 3'(_GEN_2 + 3'h1) : 3'(_GEN_2 - 3'h1)) : 3'h0;</a>
+<a name="338"><span class="lineNum">     338 </span>            :   assign per_bank_not_silent_update_1_0 =</a>
+<a name="339"><span class="lineNum">     339 </span>            :     (wrbypass_data_valid_2</a>
+<a name="340"><span class="lineNum">     340 </span>            :        ? ~((&amp;_wrbypass_io_T_50) &amp; _GEN_1 | _wrbypass_io_T_50 == 3'h0 &amp; ~_GEN_1)</a>
+<a name="341"><span class="lineNum">     341 </span>            :        : ~((&amp;_GEN_2) &amp; _GEN_1 | _GEN_2 == 3'h0 &amp; ~_GEN_1)) | _GEN_4;</a>
+<a name="342"><span class="lineNum">     342 </span>            :   wire [2:0]  _wrbypass_io_T_72 =</a>
+<a name="343"><span class="lineNum">     343 </span>            :     (io_update_pc[1] ? _bank_wrbypasses_1_0_io_hit_data_0_bits : 3'h0)</a>
+<a name="344"><span class="lineNum">     344 </span>            :     | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_1_1_io_hit_data_0_bits);</a>
+<a name="345"><span class="lineNum">     345 </span><span class="lineCov">         12 :   wire        wrbypass_data_valid_3 =</span></a>
+<a name="346"><span class="lineNum">     346 </span>            :     (io_update_pc[1] &amp; _bank_wrbypasses_1_0_io_hit | ~(io_update_pc[1])</a>
+<a name="347"><span class="lineNum">     347 </span>            :      &amp; _bank_wrbypasses_1_1_io_hit)</a>
+<a name="348"><span class="lineNum">     348 </span>            :     &amp; (io_update_pc[1] &amp; _bank_wrbypasses_1_0_io_hit_data_0_valid | ~(io_update_pc[1])</a>
+<a name="349"><span class="lineNum">     349 </span>            :        &amp; _bank_wrbypasses_1_1_io_hit_data_0_valid);</a>
+<a name="350"><span class="lineNum">     350 </span><span class="lineCov">         48 :   wire [2:0]  per_bank_update_wdata_1_1_ctr =</span></a>
+<a name="351"><span class="lineNum">     351 </span>            :     _GEN_7</a>
+<a name="352"><span class="lineNum">     352 </span>            :       ? (_GEN_5 ? 3'h4 : 3'h3)</a>
+<a name="353"><span class="lineNum">     353 </span>            :       : wrbypass_data_valid_3</a>
+<a name="354"><span class="lineNum">     354 </span>            :           ? ((&amp;_wrbypass_io_T_72) &amp; _GEN_5</a>
+<a name="355"><span class="lineNum">     355 </span>            :                ? 3'h7</a>
+<a name="356"><span class="lineNum">     356 </span>            :                : _wrbypass_io_T_72 == 3'h0 &amp; ~_GEN_5</a>
+<a name="357"><span class="lineNum">     357 </span>            :                    ? 3'h0</a>
+<a name="358"><span class="lineNum">     358 </span>            :                    : _GEN_5 ? 3'(_wrbypass_io_T_72 + 3'h1) : 3'(_wrbypass_io_T_72 - 3'h1))</a>
+<a name="359"><span class="lineNum">     359 </span>            :           : (&amp;_GEN_6) &amp; _GEN_5</a>
+<a name="360"><span class="lineNum">     360 </span>            :               ? 3'h7</a>
+<a name="361"><span class="lineNum">     361 </span>            :               : _GEN_6 == 3'h0 &amp; ~_GEN_5</a>
+<a name="362"><span class="lineNum">     362 </span>            :                   ? 3'h0</a>
+<a name="363"><span class="lineNum">     363 </span>            :                   : _GEN_5 ? 3'(_GEN_6 + 3'h1) : 3'(_GEN_6 - 3'h1);</a>
+<a name="364"><span class="lineNum">     364 </span>            :   assign per_bank_not_silent_update_1_1 =</a>
+<a name="365"><span class="lineNum">     365 </span>            :     (wrbypass_data_valid_3</a>
+<a name="366"><span class="lineNum">     366 </span>            :        ? ~((&amp;_wrbypass_io_T_72) &amp; _GEN_5 | _wrbypass_io_T_72 == 3'h0 &amp; ~_GEN_5)</a>
+<a name="367"><span class="lineNum">     367 </span>            :        : ~((&amp;_GEN_6) &amp; _GEN_5 | _GEN_6 == 3'h0 &amp; ~_GEN_5)) | _GEN_7;</a>
+<a name="368"><span class="lineNum">     368 </span>            :   wire [2:0]  _wrbypass_io_T_94 =</a>
+<a name="369"><span class="lineNum">     369 </span>            :     (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_2_0_io_hit_data_0_bits)</a>
+<a name="370"><span class="lineNum">     370 </span>            :     | (io_update_pc[1] ? _bank_wrbypasses_2_1_io_hit_data_0_bits : 3'h0);</a>
+<a name="371"><span class="lineNum">     371 </span><span class="lineCov">         20 :   wire        wrbypass_data_valid_4 =</span></a>
+<a name="372"><span class="lineNum">     372 </span>            :     (~(io_update_pc[1]) &amp; _bank_wrbypasses_2_0_io_hit | io_update_pc[1]</a>
+<a name="373"><span class="lineNum">     373 </span>            :      &amp; _bank_wrbypasses_2_1_io_hit)</a>
+<a name="374"><span class="lineNum">     374 </span>            :     &amp; (~(io_update_pc[1]) &amp; _bank_wrbypasses_2_0_io_hit_data_0_valid | io_update_pc[1]</a>
+<a name="375"><span class="lineNum">     375 </span>            :        &amp; _bank_wrbypasses_2_1_io_hit_data_0_valid);</a>
+<a name="376"><span class="lineNum">     376 </span><span class="lineCov">         55 :   wire [2:0]  per_bank_update_wdata_2_0_ctr =</span></a>
+<a name="377"><span class="lineNum">     377 </span>            :     _GEN_4</a>
+<a name="378"><span class="lineNum">     378 </span>            :       ? (_GEN_1 ? 3'h4 : 3'h3)</a>
+<a name="379"><span class="lineNum">     379 </span>            :       : wrbypass_data_valid_4</a>
+<a name="380"><span class="lineNum">     380 </span>            :           ? ((&amp;_wrbypass_io_T_94) &amp; _GEN_1</a>
+<a name="381"><span class="lineNum">     381 </span>            :                ? 3'h7</a>
+<a name="382"><span class="lineNum">     382 </span>            :                : _wrbypass_io_T_94 == 3'h0 &amp; ~_GEN_1</a>
+<a name="383"><span class="lineNum">     383 </span>            :                    ? 3'h0</a>
+<a name="384"><span class="lineNum">     384 </span>            :                    : _GEN_1 ? 3'(_wrbypass_io_T_94 + 3'h1) : 3'(_wrbypass_io_T_94 - 3'h1))</a>
+<a name="385"><span class="lineNum">     385 </span>            :           : (&amp;_GEN_2) &amp; _GEN_1</a>
+<a name="386"><span class="lineNum">     386 </span>            :               ? 3'h7</a>
+<a name="387"><span class="lineNum">     387 </span>            :               : _GEN_3 ? (_GEN_1 ? 3'(_GEN_2 + 3'h1) : 3'(_GEN_2 - 3'h1)) : 3'h0;</a>
+<a name="388"><span class="lineNum">     388 </span>            :   assign per_bank_not_silent_update_2_0 =</a>
+<a name="389"><span class="lineNum">     389 </span>            :     (wrbypass_data_valid_4</a>
+<a name="390"><span class="lineNum">     390 </span>            :        ? ~((&amp;_wrbypass_io_T_94) &amp; _GEN_1 | _wrbypass_io_T_94 == 3'h0 &amp; ~_GEN_1)</a>
+<a name="391"><span class="lineNum">     391 </span>            :        : ~((&amp;_GEN_2) &amp; _GEN_1 | _GEN_2 == 3'h0 &amp; ~_GEN_1)) | _GEN_4;</a>
+<a name="392"><span class="lineNum">     392 </span>            :   wire [2:0]  _wrbypass_io_T_116 =</a>
+<a name="393"><span class="lineNum">     393 </span>            :     (io_update_pc[1] ? _bank_wrbypasses_2_0_io_hit_data_0_bits : 3'h0)</a>
+<a name="394"><span class="lineNum">     394 </span>            :     | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_2_1_io_hit_data_0_bits);</a>
+<a name="395"><span class="lineNum">     395 </span><span class="lineCov">         20 :   wire        wrbypass_data_valid_5 =</span></a>
+<a name="396"><span class="lineNum">     396 </span>            :     (io_update_pc[1] &amp; _bank_wrbypasses_2_0_io_hit | ~(io_update_pc[1])</a>
+<a name="397"><span class="lineNum">     397 </span>            :      &amp; _bank_wrbypasses_2_1_io_hit)</a>
+<a name="398"><span class="lineNum">     398 </span>            :     &amp; (io_update_pc[1] &amp; _bank_wrbypasses_2_0_io_hit_data_0_valid | ~(io_update_pc[1])</a>
+<a name="399"><span class="lineNum">     399 </span>            :        &amp; _bank_wrbypasses_2_1_io_hit_data_0_valid);</a>
+<a name="400"><span class="lineNum">     400 </span><span class="lineCov">         54 :   wire [2:0]  per_bank_update_wdata_2_1_ctr =</span></a>
+<a name="401"><span class="lineNum">     401 </span>            :     _GEN_7</a>
+<a name="402"><span class="lineNum">     402 </span>            :       ? (_GEN_5 ? 3'h4 : 3'h3)</a>
+<a name="403"><span class="lineNum">     403 </span>            :       : wrbypass_data_valid_5</a>
+<a name="404"><span class="lineNum">     404 </span>            :           ? ((&amp;_wrbypass_io_T_116) &amp; _GEN_5</a>
+<a name="405"><span class="lineNum">     405 </span>            :                ? 3'h7</a>
+<a name="406"><span class="lineNum">     406 </span>            :                : _wrbypass_io_T_116 == 3'h0 &amp; ~_GEN_5</a>
+<a name="407"><span class="lineNum">     407 </span>            :                    ? 3'h0</a>
+<a name="408"><span class="lineNum">     408 </span>            :                    : _GEN_5</a>
+<a name="409"><span class="lineNum">     409 </span>            :                        ? 3'(_wrbypass_io_T_116 + 3'h1)</a>
+<a name="410"><span class="lineNum">     410 </span>            :                        : 3'(_wrbypass_io_T_116 - 3'h1))</a>
+<a name="411"><span class="lineNum">     411 </span>            :           : (&amp;_GEN_6) &amp; _GEN_5</a>
+<a name="412"><span class="lineNum">     412 </span>            :               ? 3'h7</a>
+<a name="413"><span class="lineNum">     413 </span>            :               : _GEN_6 == 3'h0 &amp; ~_GEN_5</a>
+<a name="414"><span class="lineNum">     414 </span>            :                   ? 3'h0</a>
+<a name="415"><span class="lineNum">     415 </span>            :                   : _GEN_5 ? 3'(_GEN_6 + 3'h1) : 3'(_GEN_6 - 3'h1);</a>
+<a name="416"><span class="lineNum">     416 </span>            :   assign per_bank_not_silent_update_2_1 =</a>
+<a name="417"><span class="lineNum">     417 </span>            :     (wrbypass_data_valid_5</a>
+<a name="418"><span class="lineNum">     418 </span>            :        ? ~((&amp;_wrbypass_io_T_116) &amp; _GEN_5 | _wrbypass_io_T_116 == 3'h0 &amp; ~_GEN_5)</a>
+<a name="419"><span class="lineNum">     419 </span>            :        : ~((&amp;_GEN_6) &amp; _GEN_5 | _GEN_6 == 3'h0 &amp; ~_GEN_5)) | _GEN_7;</a>
+<a name="420"><span class="lineNum">     420 </span>            :   wire [2:0]  _wrbypass_io_T_138 =</a>
+<a name="421"><span class="lineNum">     421 </span>            :     (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_3_0_io_hit_data_0_bits)</a>
+<a name="422"><span class="lineNum">     422 </span>            :     | (io_update_pc[1] ? _bank_wrbypasses_3_1_io_hit_data_0_bits : 3'h0);</a>
+<a name="423"><span class="lineNum">     423 </span><span class="lineCov">         22 :   wire        wrbypass_data_valid_6 =</span></a>
+<a name="424"><span class="lineNum">     424 </span>            :     (~(io_update_pc[1]) &amp; _bank_wrbypasses_3_0_io_hit | io_update_pc[1]</a>
+<a name="425"><span class="lineNum">     425 </span>            :      &amp; _bank_wrbypasses_3_1_io_hit)</a>
+<a name="426"><span class="lineNum">     426 </span>            :     &amp; (~(io_update_pc[1]) &amp; _bank_wrbypasses_3_0_io_hit_data_0_valid | io_update_pc[1]</a>
+<a name="427"><span class="lineNum">     427 </span>            :        &amp; _bank_wrbypasses_3_1_io_hit_data_0_valid);</a>
+<a name="428"><span class="lineNum">     428 </span><span class="lineCov">         56 :   wire [2:0]  per_bank_update_wdata_3_0_ctr =</span></a>
+<a name="429"><span class="lineNum">     429 </span>            :     _GEN_4</a>
+<a name="430"><span class="lineNum">     430 </span>            :       ? (_GEN_1 ? 3'h4 : 3'h3)</a>
+<a name="431"><span class="lineNum">     431 </span>            :       : wrbypass_data_valid_6</a>
+<a name="432"><span class="lineNum">     432 </span>            :           ? ((&amp;_wrbypass_io_T_138) &amp; _GEN_1</a>
+<a name="433"><span class="lineNum">     433 </span>            :                ? 3'h7</a>
+<a name="434"><span class="lineNum">     434 </span>            :                : _wrbypass_io_T_138 == 3'h0 &amp; ~_GEN_1</a>
+<a name="435"><span class="lineNum">     435 </span>            :                    ? 3'h0</a>
+<a name="436"><span class="lineNum">     436 </span>            :                    : _GEN_1</a>
+<a name="437"><span class="lineNum">     437 </span>            :                        ? 3'(_wrbypass_io_T_138 + 3'h1)</a>
+<a name="438"><span class="lineNum">     438 </span>            :                        : 3'(_wrbypass_io_T_138 - 3'h1))</a>
+<a name="439"><span class="lineNum">     439 </span>            :           : (&amp;_GEN_2) &amp; _GEN_1</a>
+<a name="440"><span class="lineNum">     440 </span>            :               ? 3'h7</a>
+<a name="441"><span class="lineNum">     441 </span>            :               : _GEN_3 ? (_GEN_1 ? 3'(_GEN_2 + 3'h1) : 3'(_GEN_2 - 3'h1)) : 3'h0;</a>
+<a name="442"><span class="lineNum">     442 </span>            :   assign per_bank_not_silent_update_3_0 =</a>
+<a name="443"><span class="lineNum">     443 </span>            :     (wrbypass_data_valid_6</a>
+<a name="444"><span class="lineNum">     444 </span>            :        ? ~((&amp;_wrbypass_io_T_138) &amp; _GEN_1 | _wrbypass_io_T_138 == 3'h0 &amp; ~_GEN_1)</a>
+<a name="445"><span class="lineNum">     445 </span>            :        : ~((&amp;_GEN_2) &amp; _GEN_1 | _GEN_2 == 3'h0 &amp; ~_GEN_1)) | _GEN_4;</a>
+<a name="446"><span class="lineNum">     446 </span>            :   wire [2:0]  _wrbypass_io_T_160 =</a>
+<a name="447"><span class="lineNum">     447 </span>            :     (io_update_pc[1] ? _bank_wrbypasses_3_0_io_hit_data_0_bits : 3'h0)</a>
+<a name="448"><span class="lineNum">     448 </span>            :     | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_3_1_io_hit_data_0_bits);</a>
+<a name="449"><span class="lineNum">     449 </span><span class="lineCov">         16 :   wire        wrbypass_data_valid_7 =</span></a>
+<a name="450"><span class="lineNum">     450 </span>            :     (io_update_pc[1] &amp; _bank_wrbypasses_3_0_io_hit | ~(io_update_pc[1])</a>
+<a name="451"><span class="lineNum">     451 </span>            :      &amp; _bank_wrbypasses_3_1_io_hit)</a>
+<a name="452"><span class="lineNum">     452 </span>            :     &amp; (io_update_pc[1] &amp; _bank_wrbypasses_3_0_io_hit_data_0_valid | ~(io_update_pc[1])</a>
+<a name="453"><span class="lineNum">     453 </span>            :        &amp; _bank_wrbypasses_3_1_io_hit_data_0_valid);</a>
+<a name="454"><span class="lineNum">     454 </span><span class="lineCov">         48 :   wire [2:0]  per_bank_update_wdata_3_1_ctr =</span></a>
+<a name="455"><span class="lineNum">     455 </span>            :     _GEN_7</a>
+<a name="456"><span class="lineNum">     456 </span>            :       ? (_GEN_5 ? 3'h4 : 3'h3)</a>
+<a name="457"><span class="lineNum">     457 </span>            :       : wrbypass_data_valid_7</a>
+<a name="458"><span class="lineNum">     458 </span>            :           ? ((&amp;_wrbypass_io_T_160) &amp; _GEN_5</a>
+<a name="459"><span class="lineNum">     459 </span>            :                ? 3'h7</a>
+<a name="460"><span class="lineNum">     460 </span>            :                : _wrbypass_io_T_160 == 3'h0 &amp; ~_GEN_5</a>
+<a name="461"><span class="lineNum">     461 </span>            :                    ? 3'h0</a>
+<a name="462"><span class="lineNum">     462 </span>            :                    : _GEN_5</a>
+<a name="463"><span class="lineNum">     463 </span>            :                        ? 3'(_wrbypass_io_T_160 + 3'h1)</a>
+<a name="464"><span class="lineNum">     464 </span>            :                        : 3'(_wrbypass_io_T_160 - 3'h1))</a>
+<a name="465"><span class="lineNum">     465 </span>            :           : (&amp;_GEN_6) &amp; _GEN_5</a>
+<a name="466"><span class="lineNum">     466 </span>            :               ? 3'h7</a>
+<a name="467"><span class="lineNum">     467 </span>            :               : _GEN_6 == 3'h0 &amp; ~_GEN_5</a>
+<a name="468"><span class="lineNum">     468 </span>            :                   ? 3'h0</a>
+<a name="469"><span class="lineNum">     469 </span>            :                   : _GEN_5 ? 3'(_GEN_6 + 3'h1) : 3'(_GEN_6 - 3'h1);</a>
+<a name="470"><span class="lineNum">     470 </span>            :   assign per_bank_not_silent_update_3_1 =</a>
+<a name="471"><span class="lineNum">     471 </span>            :     (wrbypass_data_valid_7</a>
+<a name="472"><span class="lineNum">     472 </span>            :        ? ~((&amp;_wrbypass_io_T_160) &amp; _GEN_5 | _wrbypass_io_T_160 == 3'h0 &amp; ~_GEN_5)</a>
+<a name="473"><span class="lineNum">     473 </span>            :        : ~((&amp;_GEN_6) &amp; _GEN_5 | _GEN_6 == 3'h0 &amp; ~_GEN_5)) | _GEN_7;</a>
+<a name="474"><span class="lineNum">     474 </span><span class="lineCov">     127694 :   always @(posedge clock) begin</span></a>
+<a name="475"><span class="lineNum">     475 </span><span class="lineCov">       8350 :     if (_s1_bank_req_1h_T) begin</span></a>
+<a name="476"><span class="lineNum">     476 </span><span class="lineCov">       4175 :       s1_unhashed_idx &lt;= io_req_bits_pc[40:1];</span></a>
+<a name="477"><span class="lineNum">     477 </span><span class="lineCov">       4175 :       s1_tag &lt;= _GEN ^ {io_req_bits_folded_hist_hist_7_folded_hist, 1'h0};</span></a>
+<a name="478"><span class="lineNum">     478 </span><span class="lineCov">       4175 :       s1_bank_req_1h_0 &lt;= s0_bank_req_1h_0;</span></a>
+<a name="479"><span class="lineNum">     479 </span><span class="lineCov">       4175 :       s1_bank_req_1h_1 &lt;= s0_bank_req_1h_1;</span></a>
+<a name="480"><span class="lineNum">     480 </span><span class="lineCov">       4175 :       s1_bank_req_1h_2 &lt;= s0_bank_req_1h_2;</span></a>
+<a name="481"><span class="lineNum">     481 </span><span class="lineCov">       4175 :       s1_bank_req_1h_3 &lt;= &amp;(_GEN[1:0]);</span></a>
+<a name="482"><span class="lineNum">     482 </span>            :     end</a>
+<a name="483"><span class="lineNum">     483 </span><span class="lineCov">       8350 :     if (io_req_valid) begin</span></a>
+<a name="484"><span class="lineNum">     484 </span><span class="lineCov">       4175 :       s1_bank_has_write_on_this_req_0 &lt;= _s1_bank_has_write_on_this_req_WIRE_0;</span></a>
+<a name="485"><span class="lineNum">     485 </span><span class="lineCov">       4175 :       s1_bank_has_write_on_this_req_1 &lt;= _s1_bank_has_write_on_this_req_WIRE_1;</span></a>
+<a name="486"><span class="lineNum">     486 </span><span class="lineCov">       4175 :       s1_bank_has_write_on_this_req_2 &lt;= _s1_bank_has_write_on_this_req_WIRE_2;</span></a>
+<a name="487"><span class="lineNum">     487 </span><span class="lineCov">       4175 :       s1_bank_has_write_on_this_req_3 &lt;= _s1_bank_has_write_on_this_req_WIRE_3;</span></a>
+<a name="488"><span class="lineNum">     488 </span>            :     end</a>
+<a name="489"><span class="lineNum">     489 </span>            :   end // always @(posedge)</a>
+<a name="490"><span class="lineNum">     490 </span><span class="lineCov">     127730 :   always @(posedge clock or posedge reset) begin</span></a>
+<a name="491"><span class="lineNum">     491 </span><span class="lineCov">        272 :     if (reset)</span></a>
+<a name="492"><span class="lineNum">     492 </span><span class="lineCov">        136 :       powerOnResetState &lt;= 1'h1;</span></a>
+<a name="493"><span class="lineNum">     493 </span>            :     else</a>
+<a name="494"><span class="lineNum">     494 </span><span class="lineCov">      63729 :       powerOnResetState &lt;=</span></a>
+<a name="495"><span class="lineNum">     495 </span><span class="lineCov">      63729 :         ~(_us_io_r_req_ready &amp; _table_banks_0_io_r_req_ready</span></a>
+<a name="496"><span class="lineNum">     496 </span><span class="lineCov">      63729 :           &amp; _table_banks_1_io_r_req_ready &amp; _table_banks_2_io_r_req_ready</span></a>
+<a name="497"><span class="lineNum">     497 </span><span class="lineCov">      63729 :           &amp; _table_banks_3_io_r_req_ready) &amp; powerOnResetState;</span></a>
+<a name="498"><span class="lineNum">     498 </span>            :   end // always @(posedge, posedge)</a>
+<a name="499"><span class="lineNum">     499 </span>            :   `ifdef ENABLE_INITIAL_REG_</a>
+<a name="500"><span class="lineNum">     500 </span>            :     `ifdef FIRRTL_BEFORE_INITIAL</a>
+<a name="501"><span class="lineNum">     501 </span>            :       `FIRRTL_BEFORE_INITIAL</a>
+<a name="502"><span class="lineNum">     502 </span>            :     `endif // FIRRTL_BEFORE_INITIAL</a>
+<a name="503"><span class="lineNum">     503 </span>            :     logic [31:0] _RANDOM[0:3];</a>
+<a name="504"><span class="lineNum">     504 </span><span class="lineCov">         58 :     initial begin</span></a>
+<a name="505"><span class="lineNum">     505 </span>            :       `ifdef INIT_RANDOM_PROLOG_</a>
+<a name="506"><span class="lineNum">     506 </span>            :         `INIT_RANDOM_PROLOG_</a>
+<a name="507"><span class="lineNum">     507 </span>            :       `endif // INIT_RANDOM_PROLOG_</a>
+<a name="508"><span class="lineNum">     508 </span>            :       `ifdef RANDOMIZE_REG_INIT</a>
+<a name="509"><span class="lineNum">     509 </span>            :         for (logic [2:0] i = 3'h0; i &lt; 3'h4; i += 3'h1) begin</a>
+<a name="510"><span class="lineNum">     510 </span>            :           _RANDOM[i[1:0]] = `RANDOM;</a>
+<a name="511"><span class="lineNum">     511 </span>            :         end</a>
+<a name="512"><span class="lineNum">     512 </span>            :         s1_unhashed_idx = {_RANDOM[2'h0], _RANDOM[2'h1][7:0]};</a>
+<a name="513"><span class="lineNum">     513 </span>            :         s1_tag = _RANDOM[2'h1][26:19];</a>
+<a name="514"><span class="lineNum">     514 </span>            :         s1_bank_req_1h_0 = _RANDOM[2'h3][4];</a>
+<a name="515"><span class="lineNum">     515 </span>            :         s1_bank_req_1h_1 = _RANDOM[2'h3][5];</a>
+<a name="516"><span class="lineNum">     516 </span>            :         s1_bank_req_1h_2 = _RANDOM[2'h3][6];</a>
+<a name="517"><span class="lineNum">     517 </span>            :         s1_bank_req_1h_3 = _RANDOM[2'h3][7];</a>
+<a name="518"><span class="lineNum">     518 </span>            :         s1_bank_has_write_on_this_req_0 = _RANDOM[2'h3][8];</a>
+<a name="519"><span class="lineNum">     519 </span>            :         s1_bank_has_write_on_this_req_1 = _RANDOM[2'h3][9];</a>
+<a name="520"><span class="lineNum">     520 </span>            :         s1_bank_has_write_on_this_req_2 = _RANDOM[2'h3][10];</a>
+<a name="521"><span class="lineNum">     521 </span>            :         s1_bank_has_write_on_this_req_3 = _RANDOM[2'h3][11];</a>
+<a name="522"><span class="lineNum">     522 </span>            :         powerOnResetState = _RANDOM[2'h3][12];</a>
+<a name="523"><span class="lineNum">     523 </span>            :       `endif // RANDOMIZE_REG_INIT</a>
+<a name="524"><span class="lineNum">     524 </span><span class="lineCov">         17 :       if (reset)</span></a>
+<a name="525"><span class="lineNum">     525 </span><span class="lineCov">         12 :         powerOnResetState = 1'h1;</span></a>
+<a name="526"><span class="lineNum">     526 </span>            :     end // initial</a>
+<a name="527"><span class="lineNum">     527 </span>            :     `ifdef FIRRTL_AFTER_INITIAL</a>
+<a name="528"><span class="lineNum">     528 </span>            :       `FIRRTL_AFTER_INITIAL</a>
+<a name="529"><span class="lineNum">     529 </span>            :     `endif // FIRRTL_AFTER_INITIAL</a>
+<a name="530"><span class="lineNum">     530 </span>            :   `endif // ENABLE_INITIAL_REG_</a>
+<a name="531"><span class="lineNum">     531 </span>            :   FoldedSRAMTemplate us (</a>
+<a name="532"><span class="lineNum">     532 </span>            :     .clock                 (clock),</a>
+<a name="533"><span class="lineNum">     533 </span>            :     .reset                 (reset),</a>
+<a name="534"><span class="lineNum">     534 </span>            :     .io_r_req_ready        (_us_io_r_req_ready),</a>
+<a name="535"><span class="lineNum">     535 </span>            :     .io_r_req_valid        (_s1_bank_req_1h_T),</a>
+<a name="536"><span class="lineNum">     536 </span>            :     .io_r_req_bits_setIdx  ({io_req_bits_pc[11:9], _GEN}),</a>
+<a name="537"><span class="lineNum">     537 </span>            :     .io_r_resp_data_0      (_us_io_r_resp_data_0),</a>
+<a name="538"><span class="lineNum">     538 </span>            :     .io_r_resp_data_1      (_us_io_r_resp_data_1),</a>
+<a name="539"><span class="lineNum">     539 </span>            :     .io_w_req_valid</a>
+<a name="540"><span class="lineNum">     540 </span>            :       (_us_extra_reset_T_1 &amp; (io_update_uMask_0 | io_update_uMask_1)),</a>
+<a name="541"><span class="lineNum">     541 </span>            :     .io_w_req_bits_setIdx  ({io_update_pc[11:9], _GEN_0}),</a>
+<a name="542"><span class="lineNum">     542 </span>            :     .io_w_req_bits_data_0</a>
+<a name="543"><span class="lineNum">     543 </span>            :       (~(io_update_pc[1]) &amp; io_update_us_0 | io_update_pc[1] &amp; io_update_us_1),</a>
+<a name="544"><span class="lineNum">     544 </span>            :     .io_w_req_bits_data_1</a>
+<a name="545"><span class="lineNum">     545 </span>            :       (io_update_pc[1] &amp; io_update_us_0 | ~(io_update_pc[1]) &amp; io_update_us_1),</a>
+<a name="546"><span class="lineNum">     546 </span>            :     .io_w_req_bits_waymask</a>
+<a name="547"><span class="lineNum">     547 </span>            :       ({io_update_pc[1] &amp; io_update_uMask_0 | ~(io_update_pc[1]) &amp; io_update_uMask_1,</a>
+<a name="548"><span class="lineNum">     548 </span>            :         ~(io_update_pc[1]) &amp; io_update_uMask_0 | io_update_pc[1] &amp; io_update_uMask_1}),</a>
+<a name="549"><span class="lineNum">     549 </span>            :     .extra_reset</a>
+<a name="550"><span class="lineNum">     550 </span>            :       ((io_update_reset_u_0 | io_update_reset_u_1) &amp; _us_extra_reset_T_1)</a>
+<a name="551"><span class="lineNum">     551 </span>            :   );</a>
+<a name="552"><span class="lineNum">     552 </span>            :   FoldedSRAMTemplate_1 table_banks_0 (</a>
+<a name="553"><span class="lineNum">     553 </span>            :     .clock                    (clock),</a>
+<a name="554"><span class="lineNum">     554 </span>            :     .reset                    (reset),</a>
+<a name="555"><span class="lineNum">     555 </span>            :     .io_r_req_ready           (_table_banks_0_io_r_req_ready),</a>
+<a name="556"><span class="lineNum">     556 </span>            :     .io_r_req_valid           (_s1_bank_req_1h_T &amp; s0_bank_req_1h_0),</a>
+<a name="557"><span class="lineNum">     557 </span>            :     .io_r_req_bits_setIdx     (_table_banks_3_io_r_req_bits_setIdx_T),</a>
+<a name="558"><span class="lineNum">     558 </span>            :     .io_r_resp_data_0_valid   (_table_banks_0_io_r_resp_data_0_valid),</a>
+<a name="559"><span class="lineNum">     559 </span>            :     .io_r_resp_data_0_tag     (_table_banks_0_io_r_resp_data_0_tag),</a>
+<a name="560"><span class="lineNum">     560 </span>            :     .io_r_resp_data_0_ctr     (_table_banks_0_io_r_resp_data_0_ctr),</a>
+<a name="561"><span class="lineNum">     561 </span>            :     .io_r_resp_data_1_valid   (_table_banks_0_io_r_resp_data_1_valid),</a>
+<a name="562"><span class="lineNum">     562 </span>            :     .io_r_resp_data_1_tag     (_table_banks_0_io_r_resp_data_1_tag),</a>
+<a name="563"><span class="lineNum">     563 </span>            :     .io_r_resp_data_1_ctr     (_table_banks_0_io_r_resp_data_1_ctr),</a>
+<a name="564"><span class="lineNum">     564 </span>            :     .io_w_req_valid           (_s1_bank_has_write_on_this_req_WIRE_0),</a>
+<a name="565"><span class="lineNum">     565 </span>            :     .io_w_req_bits_setIdx     (update_idx_in_bank),</a>
+<a name="566"><span class="lineNum">     566 </span>            :     .io_w_req_bits_data_0_tag (update_tag),</a>
+<a name="567"><span class="lineNum">     567 </span>            :     .io_w_req_bits_data_0_ctr (per_bank_update_wdata_0_0_ctr),</a>
+<a name="568"><span class="lineNum">     568 </span>            :     .io_w_req_bits_data_1_tag (update_tag),</a>
+<a name="569"><span class="lineNum">     569 </span>            :     .io_w_req_bits_data_1_ctr (per_bank_update_wdata_0_1_ctr),</a>
+<a name="570"><span class="lineNum">     570 </span>            :     .io_w_req_bits_waymask    (per_bank_update_way_mask_0)</a>
+<a name="571"><span class="lineNum">     571 </span>            :   );</a>
+<a name="572"><span class="lineNum">     572 </span>            :   FoldedSRAMTemplate_1 table_banks_1 (</a>
+<a name="573"><span class="lineNum">     573 </span>            :     .clock                    (clock),</a>
+<a name="574"><span class="lineNum">     574 </span>            :     .reset                    (reset),</a>
+<a name="575"><span class="lineNum">     575 </span>            :     .io_r_req_ready           (_table_banks_1_io_r_req_ready),</a>
+<a name="576"><span class="lineNum">     576 </span>            :     .io_r_req_valid           (_s1_bank_req_1h_T &amp; s0_bank_req_1h_1),</a>
+<a name="577"><span class="lineNum">     577 </span>            :     .io_r_req_bits_setIdx     (_table_banks_3_io_r_req_bits_setIdx_T),</a>
+<a name="578"><span class="lineNum">     578 </span>            :     .io_r_resp_data_0_valid   (_table_banks_1_io_r_resp_data_0_valid),</a>
+<a name="579"><span class="lineNum">     579 </span>            :     .io_r_resp_data_0_tag     (_table_banks_1_io_r_resp_data_0_tag),</a>
+<a name="580"><span class="lineNum">     580 </span>            :     .io_r_resp_data_0_ctr     (_table_banks_1_io_r_resp_data_0_ctr),</a>
+<a name="581"><span class="lineNum">     581 </span>            :     .io_r_resp_data_1_valid   (_table_banks_1_io_r_resp_data_1_valid),</a>
+<a name="582"><span class="lineNum">     582 </span>            :     .io_r_resp_data_1_tag     (_table_banks_1_io_r_resp_data_1_tag),</a>
+<a name="583"><span class="lineNum">     583 </span>            :     .io_r_resp_data_1_ctr     (_table_banks_1_io_r_resp_data_1_ctr),</a>
+<a name="584"><span class="lineNum">     584 </span>            :     .io_w_req_valid           (_s1_bank_has_write_on_this_req_WIRE_1),</a>
+<a name="585"><span class="lineNum">     585 </span>            :     .io_w_req_bits_setIdx     (update_idx_in_bank),</a>
+<a name="586"><span class="lineNum">     586 </span>            :     .io_w_req_bits_data_0_tag (update_tag),</a>
+<a name="587"><span class="lineNum">     587 </span>            :     .io_w_req_bits_data_0_ctr (per_bank_update_wdata_1_0_ctr),</a>
+<a name="588"><span class="lineNum">     588 </span>            :     .io_w_req_bits_data_1_tag (update_tag),</a>
+<a name="589"><span class="lineNum">     589 </span>            :     .io_w_req_bits_data_1_ctr (per_bank_update_wdata_1_1_ctr),</a>
+<a name="590"><span class="lineNum">     590 </span>            :     .io_w_req_bits_waymask    (per_bank_update_way_mask_1)</a>
+<a name="591"><span class="lineNum">     591 </span>            :   );</a>
+<a name="592"><span class="lineNum">     592 </span>            :   FoldedSRAMTemplate_1 table_banks_2 (</a>
+<a name="593"><span class="lineNum">     593 </span>            :     .clock                    (clock),</a>
+<a name="594"><span class="lineNum">     594 </span>            :     .reset                    (reset),</a>
+<a name="595"><span class="lineNum">     595 </span>            :     .io_r_req_ready           (_table_banks_2_io_r_req_ready),</a>
+<a name="596"><span class="lineNum">     596 </span>            :     .io_r_req_valid           (_s1_bank_req_1h_T &amp; s0_bank_req_1h_2),</a>
+<a name="597"><span class="lineNum">     597 </span>            :     .io_r_req_bits_setIdx     (_table_banks_3_io_r_req_bits_setIdx_T),</a>
+<a name="598"><span class="lineNum">     598 </span>            :     .io_r_resp_data_0_valid   (_table_banks_2_io_r_resp_data_0_valid),</a>
+<a name="599"><span class="lineNum">     599 </span>            :     .io_r_resp_data_0_tag     (_table_banks_2_io_r_resp_data_0_tag),</a>
+<a name="600"><span class="lineNum">     600 </span>            :     .io_r_resp_data_0_ctr     (_table_banks_2_io_r_resp_data_0_ctr),</a>
+<a name="601"><span class="lineNum">     601 </span>            :     .io_r_resp_data_1_valid   (_table_banks_2_io_r_resp_data_1_valid),</a>
+<a name="602"><span class="lineNum">     602 </span>            :     .io_r_resp_data_1_tag     (_table_banks_2_io_r_resp_data_1_tag),</a>
+<a name="603"><span class="lineNum">     603 </span>            :     .io_r_resp_data_1_ctr     (_table_banks_2_io_r_resp_data_1_ctr),</a>
+<a name="604"><span class="lineNum">     604 </span>            :     .io_w_req_valid           (_s1_bank_has_write_on_this_req_WIRE_2),</a>
+<a name="605"><span class="lineNum">     605 </span>            :     .io_w_req_bits_setIdx     (update_idx_in_bank),</a>
+<a name="606"><span class="lineNum">     606 </span>            :     .io_w_req_bits_data_0_tag (update_tag),</a>
+<a name="607"><span class="lineNum">     607 </span>            :     .io_w_req_bits_data_0_ctr (per_bank_update_wdata_2_0_ctr),</a>
+<a name="608"><span class="lineNum">     608 </span>            :     .io_w_req_bits_data_1_tag (update_tag),</a>
+<a name="609"><span class="lineNum">     609 </span>            :     .io_w_req_bits_data_1_ctr (per_bank_update_wdata_2_1_ctr),</a>
+<a name="610"><span class="lineNum">     610 </span>            :     .io_w_req_bits_waymask    (per_bank_update_way_mask_2)</a>
+<a name="611"><span class="lineNum">     611 </span>            :   );</a>
+<a name="612"><span class="lineNum">     612 </span>            :   FoldedSRAMTemplate_1 table_banks_3 (</a>
+<a name="613"><span class="lineNum">     613 </span>            :     .clock                    (clock),</a>
+<a name="614"><span class="lineNum">     614 </span>            :     .reset                    (reset),</a>
+<a name="615"><span class="lineNum">     615 </span>            :     .io_r_req_ready           (_table_banks_3_io_r_req_ready),</a>
+<a name="616"><span class="lineNum">     616 </span>            :     .io_r_req_valid           (_s1_bank_req_1h_T &amp; (&amp;(_GEN[1:0]))),</a>
+<a name="617"><span class="lineNum">     617 </span>            :     .io_r_req_bits_setIdx     (_table_banks_3_io_r_req_bits_setIdx_T),</a>
+<a name="618"><span class="lineNum">     618 </span>            :     .io_r_resp_data_0_valid   (_table_banks_3_io_r_resp_data_0_valid),</a>
+<a name="619"><span class="lineNum">     619 </span>            :     .io_r_resp_data_0_tag     (_table_banks_3_io_r_resp_data_0_tag),</a>
+<a name="620"><span class="lineNum">     620 </span>            :     .io_r_resp_data_0_ctr     (_table_banks_3_io_r_resp_data_0_ctr),</a>
+<a name="621"><span class="lineNum">     621 </span>            :     .io_r_resp_data_1_valid   (_table_banks_3_io_r_resp_data_1_valid),</a>
+<a name="622"><span class="lineNum">     622 </span>            :     .io_r_resp_data_1_tag     (_table_banks_3_io_r_resp_data_1_tag),</a>
+<a name="623"><span class="lineNum">     623 </span>            :     .io_r_resp_data_1_ctr     (_table_banks_3_io_r_resp_data_1_ctr),</a>
+<a name="624"><span class="lineNum">     624 </span>            :     .io_w_req_valid           (_s1_bank_has_write_on_this_req_WIRE_3),</a>
+<a name="625"><span class="lineNum">     625 </span>            :     .io_w_req_bits_setIdx     (update_idx_in_bank),</a>
+<a name="626"><span class="lineNum">     626 </span>            :     .io_w_req_bits_data_0_tag (update_tag),</a>
+<a name="627"><span class="lineNum">     627 </span>            :     .io_w_req_bits_data_0_ctr (per_bank_update_wdata_3_0_ctr),</a>
+<a name="628"><span class="lineNum">     628 </span>            :     .io_w_req_bits_data_1_tag (update_tag),</a>
+<a name="629"><span class="lineNum">     629 </span>            :     .io_w_req_bits_data_1_ctr (per_bank_update_wdata_3_1_ctr),</a>
+<a name="630"><span class="lineNum">     630 </span>            :     .io_w_req_bits_waymask    (per_bank_update_way_mask_3)</a>
+<a name="631"><span class="lineNum">     631 </span>            :   );</a>
+<a name="632"><span class="lineNum">     632 </span>            :   WrBypass bank_wrbypasses_0_0 (</a>
+<a name="633"><span class="lineNum">     633 </span>            :     .clock               (clock),</a>
+<a name="634"><span class="lineNum">     634 </span>            :     .reset               (reset),</a>
+<a name="635"><span class="lineNum">     635 </span>            :     .io_wen              (io_update_mask_0 &amp; update_req_bank_1h_0),</a>
+<a name="636"><span class="lineNum">     636 </span>            :     .io_write_idx        (update_idx_in_bank),</a>
+<a name="637"><span class="lineNum">     637 </span>            :     .io_write_data_0</a>
+<a name="638"><span class="lineNum">     638 </span>            :       ((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_0_0_ctr)</a>
+<a name="639"><span class="lineNum">     639 </span>            :        | (io_update_pc[1] ? per_bank_update_wdata_0_1_ctr : 3'h0)),</a>
+<a name="640"><span class="lineNum">     640 </span>            :     .io_hit              (_bank_wrbypasses_0_0_io_hit),</a>
+<a name="641"><span class="lineNum">     641 </span>            :     .io_hit_data_0_valid (_bank_wrbypasses_0_0_io_hit_data_0_valid),</a>
+<a name="642"><span class="lineNum">     642 </span>            :     .io_hit_data_0_bits  (_bank_wrbypasses_0_0_io_hit_data_0_bits)</a>
+<a name="643"><span class="lineNum">     643 </span>            :   );</a>
+<a name="644"><span class="lineNum">     644 </span>            :   WrBypass bank_wrbypasses_0_1 (</a>
+<a name="645"><span class="lineNum">     645 </span>            :     .clock               (clock),</a>
+<a name="646"><span class="lineNum">     646 </span>            :     .reset               (reset),</a>
+<a name="647"><span class="lineNum">     647 </span>            :     .io_wen              (io_update_mask_1 &amp; update_req_bank_1h_0),</a>
+<a name="648"><span class="lineNum">     648 </span>            :     .io_write_idx        (update_idx_in_bank),</a>
+<a name="649"><span class="lineNum">     649 </span>            :     .io_write_data_0</a>
+<a name="650"><span class="lineNum">     650 </span>            :       ((io_update_pc[1] ? per_bank_update_wdata_0_0_ctr : 3'h0)</a>
+<a name="651"><span class="lineNum">     651 </span>            :        | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_0_1_ctr)),</a>
+<a name="652"><span class="lineNum">     652 </span>            :     .io_hit              (_bank_wrbypasses_0_1_io_hit),</a>
+<a name="653"><span class="lineNum">     653 </span>            :     .io_hit_data_0_valid (_bank_wrbypasses_0_1_io_hit_data_0_valid),</a>
+<a name="654"><span class="lineNum">     654 </span>            :     .io_hit_data_0_bits  (_bank_wrbypasses_0_1_io_hit_data_0_bits)</a>
+<a name="655"><span class="lineNum">     655 </span>            :   );</a>
+<a name="656"><span class="lineNum">     656 </span>            :   WrBypass bank_wrbypasses_1_0 (</a>
+<a name="657"><span class="lineNum">     657 </span>            :     .clock               (clock),</a>
+<a name="658"><span class="lineNum">     658 </span>            :     .reset               (reset),</a>
+<a name="659"><span class="lineNum">     659 </span>            :     .io_wen              (io_update_mask_0 &amp; update_req_bank_1h_1),</a>
+<a name="660"><span class="lineNum">     660 </span>            :     .io_write_idx        (update_idx_in_bank),</a>
+<a name="661"><span class="lineNum">     661 </span>            :     .io_write_data_0</a>
+<a name="662"><span class="lineNum">     662 </span>            :       ((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_1_0_ctr)</a>
+<a name="663"><span class="lineNum">     663 </span>            :        | (io_update_pc[1] ? per_bank_update_wdata_1_1_ctr : 3'h0)),</a>
+<a name="664"><span class="lineNum">     664 </span>            :     .io_hit              (_bank_wrbypasses_1_0_io_hit),</a>
+<a name="665"><span class="lineNum">     665 </span>            :     .io_hit_data_0_valid (_bank_wrbypasses_1_0_io_hit_data_0_valid),</a>
+<a name="666"><span class="lineNum">     666 </span>            :     .io_hit_data_0_bits  (_bank_wrbypasses_1_0_io_hit_data_0_bits)</a>
+<a name="667"><span class="lineNum">     667 </span>            :   );</a>
+<a name="668"><span class="lineNum">     668 </span>            :   WrBypass bank_wrbypasses_1_1 (</a>
+<a name="669"><span class="lineNum">     669 </span>            :     .clock               (clock),</a>
+<a name="670"><span class="lineNum">     670 </span>            :     .reset               (reset),</a>
+<a name="671"><span class="lineNum">     671 </span>            :     .io_wen              (io_update_mask_1 &amp; update_req_bank_1h_1),</a>
+<a name="672"><span class="lineNum">     672 </span>            :     .io_write_idx        (update_idx_in_bank),</a>
+<a name="673"><span class="lineNum">     673 </span>            :     .io_write_data_0</a>
+<a name="674"><span class="lineNum">     674 </span>            :       ((io_update_pc[1] ? per_bank_update_wdata_1_0_ctr : 3'h0)</a>
+<a name="675"><span class="lineNum">     675 </span>            :        | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_1_1_ctr)),</a>
+<a name="676"><span class="lineNum">     676 </span>            :     .io_hit              (_bank_wrbypasses_1_1_io_hit),</a>
+<a name="677"><span class="lineNum">     677 </span>            :     .io_hit_data_0_valid (_bank_wrbypasses_1_1_io_hit_data_0_valid),</a>
+<a name="678"><span class="lineNum">     678 </span>            :     .io_hit_data_0_bits  (_bank_wrbypasses_1_1_io_hit_data_0_bits)</a>
+<a name="679"><span class="lineNum">     679 </span>            :   );</a>
+<a name="680"><span class="lineNum">     680 </span>            :   WrBypass bank_wrbypasses_2_0 (</a>
+<a name="681"><span class="lineNum">     681 </span>            :     .clock               (clock),</a>
+<a name="682"><span class="lineNum">     682 </span>            :     .reset               (reset),</a>
+<a name="683"><span class="lineNum">     683 </span>            :     .io_wen              (io_update_mask_0 &amp; update_req_bank_1h_2),</a>
+<a name="684"><span class="lineNum">     684 </span>            :     .io_write_idx        (update_idx_in_bank),</a>
+<a name="685"><span class="lineNum">     685 </span>            :     .io_write_data_0</a>
+<a name="686"><span class="lineNum">     686 </span>            :       ((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_2_0_ctr)</a>
+<a name="687"><span class="lineNum">     687 </span>            :        | (io_update_pc[1] ? per_bank_update_wdata_2_1_ctr : 3'h0)),</a>
+<a name="688"><span class="lineNum">     688 </span>            :     .io_hit              (_bank_wrbypasses_2_0_io_hit),</a>
+<a name="689"><span class="lineNum">     689 </span>            :     .io_hit_data_0_valid (_bank_wrbypasses_2_0_io_hit_data_0_valid),</a>
+<a name="690"><span class="lineNum">     690 </span>            :     .io_hit_data_0_bits  (_bank_wrbypasses_2_0_io_hit_data_0_bits)</a>
+<a name="691"><span class="lineNum">     691 </span>            :   );</a>
+<a name="692"><span class="lineNum">     692 </span>            :   WrBypass bank_wrbypasses_2_1 (</a>
+<a name="693"><span class="lineNum">     693 </span>            :     .clock               (clock),</a>
+<a name="694"><span class="lineNum">     694 </span>            :     .reset               (reset),</a>
+<a name="695"><span class="lineNum">     695 </span>            :     .io_wen              (io_update_mask_1 &amp; update_req_bank_1h_2),</a>
+<a name="696"><span class="lineNum">     696 </span>            :     .io_write_idx        (update_idx_in_bank),</a>
+<a name="697"><span class="lineNum">     697 </span>            :     .io_write_data_0</a>
+<a name="698"><span class="lineNum">     698 </span>            :       ((io_update_pc[1] ? per_bank_update_wdata_2_0_ctr : 3'h0)</a>
+<a name="699"><span class="lineNum">     699 </span>            :        | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_2_1_ctr)),</a>
+<a name="700"><span class="lineNum">     700 </span>            :     .io_hit              (_bank_wrbypasses_2_1_io_hit),</a>
+<a name="701"><span class="lineNum">     701 </span>            :     .io_hit_data_0_valid (_bank_wrbypasses_2_1_io_hit_data_0_valid),</a>
+<a name="702"><span class="lineNum">     702 </span>            :     .io_hit_data_0_bits  (_bank_wrbypasses_2_1_io_hit_data_0_bits)</a>
+<a name="703"><span class="lineNum">     703 </span>            :   );</a>
+<a name="704"><span class="lineNum">     704 </span>            :   WrBypass bank_wrbypasses_3_0 (</a>
+<a name="705"><span class="lineNum">     705 </span>            :     .clock               (clock),</a>
+<a name="706"><span class="lineNum">     706 </span>            :     .reset               (reset),</a>
+<a name="707"><span class="lineNum">     707 </span>            :     .io_wen              (io_update_mask_0 &amp; (&amp;(_GEN_0[1:0]))),</a>
+<a name="708"><span class="lineNum">     708 </span>            :     .io_write_idx        (update_idx_in_bank),</a>
+<a name="709"><span class="lineNum">     709 </span>            :     .io_write_data_0</a>
+<a name="710"><span class="lineNum">     710 </span>            :       ((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_3_0_ctr)</a>
+<a name="711"><span class="lineNum">     711 </span>            :        | (io_update_pc[1] ? per_bank_update_wdata_3_1_ctr : 3'h0)),</a>
+<a name="712"><span class="lineNum">     712 </span>            :     .io_hit              (_bank_wrbypasses_3_0_io_hit),</a>
+<a name="713"><span class="lineNum">     713 </span>            :     .io_hit_data_0_valid (_bank_wrbypasses_3_0_io_hit_data_0_valid),</a>
+<a name="714"><span class="lineNum">     714 </span>            :     .io_hit_data_0_bits  (_bank_wrbypasses_3_0_io_hit_data_0_bits)</a>
+<a name="715"><span class="lineNum">     715 </span>            :   );</a>
+<a name="716"><span class="lineNum">     716 </span>            :   WrBypass bank_wrbypasses_3_1 (</a>
+<a name="717"><span class="lineNum">     717 </span>            :     .clock               (clock),</a>
+<a name="718"><span class="lineNum">     718 </span>            :     .reset               (reset),</a>
+<a name="719"><span class="lineNum">     719 </span>            :     .io_wen              (io_update_mask_1 &amp; (&amp;(_GEN_0[1:0]))),</a>
+<a name="720"><span class="lineNum">     720 </span>            :     .io_write_idx        (update_idx_in_bank),</a>
+<a name="721"><span class="lineNum">     721 </span>            :     .io_write_data_0</a>
+<a name="722"><span class="lineNum">     722 </span>            :       ((io_update_pc[1] ? per_bank_update_wdata_3_0_ctr : 3'h0)</a>
+<a name="723"><span class="lineNum">     723 </span>            :        | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_3_1_ctr)),</a>
+<a name="724"><span class="lineNum">     724 </span>            :     .io_hit              (_bank_wrbypasses_3_1_io_hit),</a>
+<a name="725"><span class="lineNum">     725 </span>            :     .io_hit_data_0_valid (_bank_wrbypasses_3_1_io_hit_data_0_valid),</a>
+<a name="726"><span class="lineNum">     726 </span>            :     .io_hit_data_0_bits  (_bank_wrbypasses_3_1_io_hit_data_0_bits)</a>
+<a name="727"><span class="lineNum">     727 </span>            :   );</a>
+<a name="728"><span class="lineNum">     728 </span>            :   assign io_req_ready = ~powerOnResetState;</a>
+<a name="729"><span class="lineNum">     729 </span>            :   assign io_resps_0_valid =</a>
+<a name="730"><span class="lineNum">     730 </span>            :     ~(s1_unhashed_idx[0]) &amp; _hit_selected_T_6 | s1_unhashed_idx[0] &amp; _hit_selected_T_13;</a>
+<a name="731"><span class="lineNum">     731 </span>            :   assign io_resps_0_bits_ctr =</a>
+<a name="732"><span class="lineNum">     732 </span>            :     (s1_unhashed_idx[0] ? 3'h0 : _resp_selected_T_6)</a>
+<a name="733"><span class="lineNum">     733 </span>            :     | (s1_unhashed_idx[0] ? _resp_selected_T_27 : 3'h0);</a>
+<a name="734"><span class="lineNum">     734 </span>            :   assign io_resps_0_bits_u =</a>
+<a name="735"><span class="lineNum">     735 </span>            :     ~(s1_unhashed_idx[0]) &amp; _us_io_r_resp_data_0 | s1_unhashed_idx[0]</a>
+<a name="736"><span class="lineNum">     736 </span>            :     &amp; _us_io_r_resp_data_1;</a>
+<a name="737"><span class="lineNum">     737 </span>            :   assign io_resps_0_bits_unconf =</a>
+<a name="738"><span class="lineNum">     738 </span>            :     ~(s1_unhashed_idx[0]) &amp; _unconf_selected_T_6 | s1_unhashed_idx[0]</a>
+<a name="739"><span class="lineNum">     739 </span>            :     &amp; _unconf_selected_T_13;</a>
+<a name="740"><span class="lineNum">     740 </span>            :   assign io_resps_1_valid =</a>
+<a name="741"><span class="lineNum">     741 </span>            :     s1_unhashed_idx[0] &amp; _hit_selected_T_6 | ~(s1_unhashed_idx[0]) &amp; _hit_selected_T_13;</a>
+<a name="742"><span class="lineNum">     742 </span>            :   assign io_resps_1_bits_ctr =</a>
+<a name="743"><span class="lineNum">     743 </span>            :     (s1_unhashed_idx[0] ? _resp_selected_T_6 : 3'h0)</a>
+<a name="744"><span class="lineNum">     744 </span>            :     | (s1_unhashed_idx[0] ? 3'h0 : _resp_selected_T_27);</a>
+<a name="745"><span class="lineNum">     745 </span>            :   assign io_resps_1_bits_u =</a>
+<a name="746"><span class="lineNum">     746 </span>            :     s1_unhashed_idx[0] &amp; _us_io_r_resp_data_0 | ~(s1_unhashed_idx[0])</a>
+<a name="747"><span class="lineNum">     747 </span>            :     &amp; _us_io_r_resp_data_1;</a>
+<a name="748"><span class="lineNum">     748 </span>            :   assign io_resps_1_bits_unconf =</a>
+<a name="749"><span class="lineNum">     749 </span>            :     s1_unhashed_idx[0] &amp; _unconf_selected_T_6 | ~(s1_unhashed_idx[0])</a>
+<a name="750"><span class="lineNum">     750 </span>            :     &amp; _unconf_selected_T_13;</a>
+<a name="751"><span class="lineNum">     751 </span>            : endmodule</a>
+<a name="752"><span class="lineNum">     752 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/TageTable_1.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/TageTable_1.sv.func-sort-c.html
new file mode 100644
index 0000000..b067070
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/TageTable_1.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/TageTable_1.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - TageTable_1.sv<span style="font-size: 80%;"> (<a href="TageTable_1.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">107</td>
+            <td class="headerCovTableEntry">107</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="TageTable_1.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/TageTable_1.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/TageTable_1.sv.func.html
new file mode 100644
index 0000000..e7f7529
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/TageTable_1.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/TageTable_1.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - TageTable_1.sv<span style="font-size: 80%;"> (<a href="TageTable_1.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">107</td>
+            <td class="headerCovTableEntry">107</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="TageTable_1.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/TageTable_1.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/TageTable_1.sv.gcov.html
new file mode 100644
index 0000000..ce364b5
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/TageTable_1.sv.gcov.html
@@ -0,0 +1,830 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/TageTable_1.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - TageTable_1.sv<span style="font-size: 80%;"> (source / <a href="TageTable_1.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">107</td>
+            <td class="headerCovTableEntry">107</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : module TageTable_1(</a>
+<a name="59"><span class="lineNum">      59 </span><span class="lineCov">     127786 :   input         clock,</span></a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">         62 :   input         reset,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">         57 :   output        io_req_ready,</span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">         76 :   input         io_req_valid,</span></a>
+<a name="63"><span class="lineNum">      63 </span><span class="lineCov">      10224 :   input  [40:0] io_req_bits_pc,</span></a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">        828 :   input  [6:0]  io_req_bits_folded_hist_hist_15_folded_hist,</span></a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">        300 :   input  [7:0]  io_req_bits_folded_hist_hist_4_folded_hist,</span></a>
+<a name="66"><span class="lineNum">      66 </span><span class="lineCov">       1122 :   input  [10:0] io_req_bits_folded_hist_hist_1_folded_hist,</span></a>
+<a name="67"><span class="lineNum">      67 </span><span class="lineCov">         15 :   output        io_resps_0_valid,</span></a>
+<a name="68"><span class="lineNum">      68 </span><span class="lineCov">         91 :   output [2:0]  io_resps_0_bits_ctr,</span></a>
+<a name="69"><span class="lineNum">      69 </span><span class="lineCov">         24 :   output        io_resps_0_bits_u,</span></a>
+<a name="70"><span class="lineNum">      70 </span><span class="lineCov">         24 :   output        io_resps_0_bits_unconf,</span></a>
+<a name="71"><span class="lineNum">      71 </span><span class="lineCov">         18 :   output        io_resps_1_valid,</span></a>
+<a name="72"><span class="lineNum">      72 </span><span class="lineCov">         95 :   output [2:0]  io_resps_1_bits_ctr,</span></a>
+<a name="73"><span class="lineNum">      73 </span><span class="lineCov">         30 :   output        io_resps_1_bits_u,</span></a>
+<a name="74"><span class="lineNum">      74 </span><span class="lineCov">         30 :   output        io_resps_1_bits_unconf,</span></a>
+<a name="75"><span class="lineNum">      75 </span><span class="lineCov">        599 :   input  [40:0] io_update_pc,</span></a>
+<a name="76"><span class="lineNum">      76 </span><span class="lineCov">         99 :   input  [6:0]  io_update_folded_hist_hist_15_folded_hist,</span></a>
+<a name="77"><span class="lineNum">      77 </span><span class="lineCov">        113 :   input  [7:0]  io_update_folded_hist_hist_4_folded_hist,</span></a>
+<a name="78"><span class="lineNum">      78 </span><span class="lineCov">        166 :   input  [10:0] io_update_folded_hist_hist_1_folded_hist,</span></a>
+<a name="79"><span class="lineNum">      79 </span><span class="lineCov">         22 :   input         io_update_mask_0,</span></a>
+<a name="80"><span class="lineNum">      80 </span><span class="lineCov">         26 :   input         io_update_mask_1,</span></a>
+<a name="81"><span class="lineNum">      81 </span><span class="lineCov">         18 :   input         io_update_takens_0,</span></a>
+<a name="82"><span class="lineNum">      82 </span><span class="lineCov">         13 :   input         io_update_takens_1,</span></a>
+<a name="83"><span class="lineNum">      83 </span><span class="lineCov">         15 :   input         io_update_alloc_0,</span></a>
+<a name="84"><span class="lineNum">      84 </span><span class="lineCov">         17 :   input         io_update_alloc_1,</span></a>
+<a name="85"><span class="lineNum">      85 </span><span class="lineCov">         47 :   input  [2:0]  io_update_oldCtrs_0,</span></a>
+<a name="86"><span class="lineNum">      86 </span><span class="lineCov">         38 :   input  [2:0]  io_update_oldCtrs_1,</span></a>
+<a name="87"><span class="lineNum">      87 </span><span class="lineCov">         15 :   input         io_update_uMask_0,</span></a>
+<a name="88"><span class="lineNum">      88 </span><span class="lineCov">         13 :   input         io_update_uMask_1,</span></a>
+<a name="89"><span class="lineNum">      89 </span><span class="lineCov">         14 :   input         io_update_us_0,</span></a>
+<a name="90"><span class="lineNum">      90 </span><span class="lineCov">         15 :   input         io_update_us_1,</span></a>
+<a name="91"><span class="lineNum">      91 </span><span class="lineCov">         29 :   input         io_update_reset_u_0,</span></a>
+<a name="92"><span class="lineNum">      92 </span><span class="lineCov">         36 :   input         io_update_reset_u_1</span></a>
+<a name="93"><span class="lineNum">      93 </span>            : );</a>
+<a name="94"><span class="lineNum">      94 </span>            : </a>
+<a name="95"><span class="lineNum">      95 </span><span class="lineCov">         15 :   wire        per_bank_not_silent_update_3_1;</span></a>
+<a name="96"><span class="lineNum">      96 </span><span class="lineCov">         15 :   wire        per_bank_not_silent_update_3_0;</span></a>
+<a name="97"><span class="lineNum">      97 </span><span class="lineCov">         15 :   wire        per_bank_not_silent_update_2_1;</span></a>
+<a name="98"><span class="lineNum">      98 </span><span class="lineCov">         16 :   wire        per_bank_not_silent_update_2_0;</span></a>
+<a name="99"><span class="lineNum">      99 </span><span class="lineCov">         18 :   wire        per_bank_not_silent_update_1_1;</span></a>
+<a name="100"><span class="lineNum">     100 </span><span class="lineCov">         17 :   wire        per_bank_not_silent_update_1_0;</span></a>
+<a name="101"><span class="lineNum">     101 </span><span class="lineCov">         16 :   wire        per_bank_not_silent_update_0_1;</span></a>
+<a name="102"><span class="lineNum">     102 </span><span class="lineCov">         13 :   wire        per_bank_not_silent_update_0_0;</span></a>
+<a name="103"><span class="lineNum">     103 </span><span class="lineCov">         55 :   reg         powerOnResetState;</span></a>
+<a name="104"><span class="lineNum">     104 </span>            :   wire        _resp_invalid_by_write_T_6;</a>
+<a name="105"><span class="lineNum">     105 </span>            :   wire        _bank_wrbypasses_3_1_io_hit;</a>
+<a name="106"><span class="lineNum">     106 </span>            :   wire        _bank_wrbypasses_3_1_io_hit_data_0_valid;</a>
+<a name="107"><span class="lineNum">     107 </span>            :   wire [2:0]  _bank_wrbypasses_3_1_io_hit_data_0_bits;</a>
+<a name="108"><span class="lineNum">     108 </span>            :   wire        _bank_wrbypasses_3_0_io_hit;</a>
+<a name="109"><span class="lineNum">     109 </span>            :   wire        _bank_wrbypasses_3_0_io_hit_data_0_valid;</a>
+<a name="110"><span class="lineNum">     110 </span>            :   wire [2:0]  _bank_wrbypasses_3_0_io_hit_data_0_bits;</a>
+<a name="111"><span class="lineNum">     111 </span>            :   wire        _bank_wrbypasses_2_1_io_hit;</a>
+<a name="112"><span class="lineNum">     112 </span>            :   wire        _bank_wrbypasses_2_1_io_hit_data_0_valid;</a>
+<a name="113"><span class="lineNum">     113 </span>            :   wire [2:0]  _bank_wrbypasses_2_1_io_hit_data_0_bits;</a>
+<a name="114"><span class="lineNum">     114 </span>            :   wire        _bank_wrbypasses_2_0_io_hit;</a>
+<a name="115"><span class="lineNum">     115 </span>            :   wire        _bank_wrbypasses_2_0_io_hit_data_0_valid;</a>
+<a name="116"><span class="lineNum">     116 </span>            :   wire [2:0]  _bank_wrbypasses_2_0_io_hit_data_0_bits;</a>
+<a name="117"><span class="lineNum">     117 </span>            :   wire        _bank_wrbypasses_1_1_io_hit;</a>
+<a name="118"><span class="lineNum">     118 </span>            :   wire        _bank_wrbypasses_1_1_io_hit_data_0_valid;</a>
+<a name="119"><span class="lineNum">     119 </span>            :   wire [2:0]  _bank_wrbypasses_1_1_io_hit_data_0_bits;</a>
+<a name="120"><span class="lineNum">     120 </span>            :   wire        _bank_wrbypasses_1_0_io_hit;</a>
+<a name="121"><span class="lineNum">     121 </span>            :   wire        _bank_wrbypasses_1_0_io_hit_data_0_valid;</a>
+<a name="122"><span class="lineNum">     122 </span>            :   wire [2:0]  _bank_wrbypasses_1_0_io_hit_data_0_bits;</a>
+<a name="123"><span class="lineNum">     123 </span>            :   wire        _bank_wrbypasses_0_1_io_hit;</a>
+<a name="124"><span class="lineNum">     124 </span>            :   wire        _bank_wrbypasses_0_1_io_hit_data_0_valid;</a>
+<a name="125"><span class="lineNum">     125 </span>            :   wire [2:0]  _bank_wrbypasses_0_1_io_hit_data_0_bits;</a>
+<a name="126"><span class="lineNum">     126 </span>            :   wire        _bank_wrbypasses_0_0_io_hit;</a>
+<a name="127"><span class="lineNum">     127 </span>            :   wire        _bank_wrbypasses_0_0_io_hit_data_0_valid;</a>
+<a name="128"><span class="lineNum">     128 </span>            :   wire [2:0]  _bank_wrbypasses_0_0_io_hit_data_0_bits;</a>
+<a name="129"><span class="lineNum">     129 </span>            :   wire        _table_banks_3_io_r_req_ready;</a>
+<a name="130"><span class="lineNum">     130 </span>            :   wire        _table_banks_3_io_r_resp_data_0_valid;</a>
+<a name="131"><span class="lineNum">     131 </span>            :   wire [7:0]  _table_banks_3_io_r_resp_data_0_tag;</a>
+<a name="132"><span class="lineNum">     132 </span>            :   wire [2:0]  _table_banks_3_io_r_resp_data_0_ctr;</a>
+<a name="133"><span class="lineNum">     133 </span>            :   wire        _table_banks_3_io_r_resp_data_1_valid;</a>
+<a name="134"><span class="lineNum">     134 </span>            :   wire [7:0]  _table_banks_3_io_r_resp_data_1_tag;</a>
+<a name="135"><span class="lineNum">     135 </span>            :   wire [2:0]  _table_banks_3_io_r_resp_data_1_ctr;</a>
+<a name="136"><span class="lineNum">     136 </span>            :   wire        _table_banks_2_io_r_req_ready;</a>
+<a name="137"><span class="lineNum">     137 </span>            :   wire        _table_banks_2_io_r_resp_data_0_valid;</a>
+<a name="138"><span class="lineNum">     138 </span>            :   wire [7:0]  _table_banks_2_io_r_resp_data_0_tag;</a>
+<a name="139"><span class="lineNum">     139 </span>            :   wire [2:0]  _table_banks_2_io_r_resp_data_0_ctr;</a>
+<a name="140"><span class="lineNum">     140 </span>            :   wire        _table_banks_2_io_r_resp_data_1_valid;</a>
+<a name="141"><span class="lineNum">     141 </span>            :   wire [7:0]  _table_banks_2_io_r_resp_data_1_tag;</a>
+<a name="142"><span class="lineNum">     142 </span>            :   wire [2:0]  _table_banks_2_io_r_resp_data_1_ctr;</a>
+<a name="143"><span class="lineNum">     143 </span>            :   wire        _table_banks_1_io_r_req_ready;</a>
+<a name="144"><span class="lineNum">     144 </span>            :   wire        _table_banks_1_io_r_resp_data_0_valid;</a>
+<a name="145"><span class="lineNum">     145 </span>            :   wire [7:0]  _table_banks_1_io_r_resp_data_0_tag;</a>
+<a name="146"><span class="lineNum">     146 </span>            :   wire [2:0]  _table_banks_1_io_r_resp_data_0_ctr;</a>
+<a name="147"><span class="lineNum">     147 </span>            :   wire        _table_banks_1_io_r_resp_data_1_valid;</a>
+<a name="148"><span class="lineNum">     148 </span>            :   wire [7:0]  _table_banks_1_io_r_resp_data_1_tag;</a>
+<a name="149"><span class="lineNum">     149 </span>            :   wire [2:0]  _table_banks_1_io_r_resp_data_1_ctr;</a>
+<a name="150"><span class="lineNum">     150 </span>            :   wire        _table_banks_0_io_r_req_ready;</a>
+<a name="151"><span class="lineNum">     151 </span>            :   wire        _table_banks_0_io_r_resp_data_0_valid;</a>
+<a name="152"><span class="lineNum">     152 </span>            :   wire [7:0]  _table_banks_0_io_r_resp_data_0_tag;</a>
+<a name="153"><span class="lineNum">     153 </span>            :   wire [2:0]  _table_banks_0_io_r_resp_data_0_ctr;</a>
+<a name="154"><span class="lineNum">     154 </span>            :   wire        _table_banks_0_io_r_resp_data_1_valid;</a>
+<a name="155"><span class="lineNum">     155 </span>            :   wire [7:0]  _table_banks_0_io_r_resp_data_1_tag;</a>
+<a name="156"><span class="lineNum">     156 </span>            :   wire [2:0]  _table_banks_0_io_r_resp_data_1_ctr;</a>
+<a name="157"><span class="lineNum">     157 </span>            :   wire        _us_io_r_req_ready;</a>
+<a name="158"><span class="lineNum">     158 </span>            :   wire        _us_io_r_resp_data_0;</a>
+<a name="159"><span class="lineNum">     159 </span>            :   wire        _us_io_r_resp_data_1;</a>
+<a name="160"><span class="lineNum">     160 </span>            :   wire        _us_extra_reset_T_1 = io_update_mask_0 | io_update_mask_1;</a>
+<a name="161"><span class="lineNum">     161 </span><span class="lineCov">       8858 :   wire [10:0] s0_idx = io_req_bits_pc[11:1] ^ io_req_bits_folded_hist_hist_1_folded_hist;</span></a>
+<a name="162"><span class="lineNum">     162 </span><span class="lineCov">         70 :   wire        s0_bank_req_1h_0 = s0_idx[1:0] == 2'h0;</span></a>
+<a name="163"><span class="lineNum">     163 </span><span class="lineCov">         67 :   wire        s0_bank_req_1h_1 = s0_idx[1:0] == 2'h1;</span></a>
+<a name="164"><span class="lineNum">     164 </span><span class="lineCov">         51 :   wire        s0_bank_req_1h_2 = s0_idx[1:0] == 2'h2;</span></a>
+<a name="165"><span class="lineNum">     165 </span>            :   wire        _s1_bank_req_1h_T = ~powerOnResetState &amp; io_req_valid;</a>
+<a name="166"><span class="lineNum">     166 </span><span class="lineCov">       9360 :   reg  [39:0] s1_unhashed_idx;</span></a>
+<a name="167"><span class="lineNum">     167 </span><span class="lineCov">       7984 :   reg  [7:0]  s1_tag;</span></a>
+<a name="168"><span class="lineNum">     168 </span><span class="lineCov">         42 :   reg         s1_bank_req_1h_0;</span></a>
+<a name="169"><span class="lineNum">     169 </span><span class="lineCov">         46 :   reg         s1_bank_req_1h_1;</span></a>
+<a name="170"><span class="lineNum">     170 </span><span class="lineCov">         39 :   reg         s1_bank_req_1h_2;</span></a>
+<a name="171"><span class="lineNum">     171 </span><span class="lineCov">         32 :   reg         s1_bank_req_1h_3;</span></a>
+<a name="172"><span class="lineNum">     172 </span><span class="lineCov">         29 :   reg         s1_bank_has_write_on_this_req_0;</span></a>
+<a name="173"><span class="lineNum">     173 </span><span class="lineCov">         26 :   reg         s1_bank_has_write_on_this_req_1;</span></a>
+<a name="174"><span class="lineNum">     174 </span><span class="lineCov">         28 :   reg         s1_bank_has_write_on_this_req_2;</span></a>
+<a name="175"><span class="lineNum">     175 </span><span class="lineCov">         28 :   reg         s1_bank_has_write_on_this_req_3;</span></a>
+<a name="176"><span class="lineNum">     176 </span>            :   wire [2:0]  _resp_selected_T_6 =</a>
+<a name="177"><span class="lineNum">     177 </span>            :     (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_ctr : 3'h0)</a>
+<a name="178"><span class="lineNum">     178 </span>            :     | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 3'h0)</a>
+<a name="179"><span class="lineNum">     179 </span>            :     | (s1_bank_req_1h_2 ? _table_banks_2_io_r_resp_data_0_ctr : 3'h0)</a>
+<a name="180"><span class="lineNum">     180 </span>            :     | (s1_bank_req_1h_3 ? _table_banks_3_io_r_resp_data_0_ctr : 3'h0);</a>
+<a name="181"><span class="lineNum">     181 </span>            :   wire [2:0]  _resp_selected_T_27 =</a>
+<a name="182"><span class="lineNum">     182 </span>            :     (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_1_ctr : 3'h0)</a>
+<a name="183"><span class="lineNum">     183 </span>            :     | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_1_ctr : 3'h0)</a>
+<a name="184"><span class="lineNum">     184 </span>            :     | (s1_bank_req_1h_2 ? _table_banks_2_io_r_resp_data_1_ctr : 3'h0)</a>
+<a name="185"><span class="lineNum">     185 </span>            :     | (s1_bank_req_1h_3 ? _table_banks_3_io_r_resp_data_1_ctr : 3'h0);</a>
+<a name="186"><span class="lineNum">     186 </span>            :   wire        _unconf_selected_T_6 =</a>
+<a name="187"><span class="lineNum">     187 </span>            :     s1_bank_req_1h_0</a>
+<a name="188"><span class="lineNum">     188 </span>            :     &amp; (_table_banks_0_io_r_resp_data_0_ctr == 3'h4</a>
+<a name="189"><span class="lineNum">     189 </span>            :        | _table_banks_0_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_1</a>
+<a name="190"><span class="lineNum">     190 </span>            :     &amp; (_table_banks_1_io_r_resp_data_0_ctr == 3'h4</a>
+<a name="191"><span class="lineNum">     191 </span>            :        | _table_banks_1_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_2</a>
+<a name="192"><span class="lineNum">     192 </span>            :     &amp; (_table_banks_2_io_r_resp_data_0_ctr == 3'h4</a>
+<a name="193"><span class="lineNum">     193 </span>            :        | _table_banks_2_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_3</a>
+<a name="194"><span class="lineNum">     194 </span>            :     &amp; (_table_banks_3_io_r_resp_data_0_ctr == 3'h4</a>
+<a name="195"><span class="lineNum">     195 </span>            :        | _table_banks_3_io_r_resp_data_0_ctr == 3'h3);</a>
+<a name="196"><span class="lineNum">     196 </span>            :   wire        _unconf_selected_T_13 =</a>
+<a name="197"><span class="lineNum">     197 </span>            :     s1_bank_req_1h_0</a>
+<a name="198"><span class="lineNum">     198 </span>            :     &amp; (_table_banks_0_io_r_resp_data_1_ctr == 3'h4</a>
+<a name="199"><span class="lineNum">     199 </span>            :        | _table_banks_0_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_1</a>
+<a name="200"><span class="lineNum">     200 </span>            :     &amp; (_table_banks_1_io_r_resp_data_1_ctr == 3'h4</a>
+<a name="201"><span class="lineNum">     201 </span>            :        | _table_banks_1_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_2</a>
+<a name="202"><span class="lineNum">     202 </span>            :     &amp; (_table_banks_2_io_r_resp_data_1_ctr == 3'h4</a>
+<a name="203"><span class="lineNum">     203 </span>            :        | _table_banks_2_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_3</a>
+<a name="204"><span class="lineNum">     204 </span>            :     &amp; (_table_banks_3_io_r_resp_data_1_ctr == 3'h4</a>
+<a name="205"><span class="lineNum">     205 </span>            :        | _table_banks_3_io_r_resp_data_1_ctr == 3'h3);</a>
+<a name="206"><span class="lineNum">     206 </span>            :   wire        _hit_selected_T_6 =</a>
+<a name="207"><span class="lineNum">     207 </span>            :     s1_bank_req_1h_0 &amp; _table_banks_0_io_r_resp_data_0_tag == s1_tag</a>
+<a name="208"><span class="lineNum">     208 </span>            :     &amp; _table_banks_0_io_r_resp_data_0_valid &amp; ~_resp_invalid_by_write_T_6</a>
+<a name="209"><span class="lineNum">     209 </span>            :     | s1_bank_req_1h_1 &amp; _table_banks_1_io_r_resp_data_0_tag == s1_tag</a>
+<a name="210"><span class="lineNum">     210 </span>            :     &amp; _table_banks_1_io_r_resp_data_0_valid &amp; ~_resp_invalid_by_write_T_6</a>
+<a name="211"><span class="lineNum">     211 </span>            :     | s1_bank_req_1h_2 &amp; _table_banks_2_io_r_resp_data_0_tag == s1_tag</a>
+<a name="212"><span class="lineNum">     212 </span>            :     &amp; _table_banks_2_io_r_resp_data_0_valid &amp; ~_resp_invalid_by_write_T_6</a>
+<a name="213"><span class="lineNum">     213 </span>            :     | s1_bank_req_1h_3 &amp; _table_banks_3_io_r_resp_data_0_tag == s1_tag</a>
+<a name="214"><span class="lineNum">     214 </span>            :     &amp; _table_banks_3_io_r_resp_data_0_valid &amp; ~_resp_invalid_by_write_T_6;</a>
+<a name="215"><span class="lineNum">     215 </span>            :   wire        _hit_selected_T_13 =</a>
+<a name="216"><span class="lineNum">     216 </span>            :     s1_bank_req_1h_0 &amp; _table_banks_0_io_r_resp_data_1_tag == s1_tag</a>
+<a name="217"><span class="lineNum">     217 </span>            :     &amp; _table_banks_0_io_r_resp_data_1_valid &amp; ~_resp_invalid_by_write_T_6</a>
+<a name="218"><span class="lineNum">     218 </span>            :     | s1_bank_req_1h_1 &amp; _table_banks_1_io_r_resp_data_1_tag == s1_tag</a>
+<a name="219"><span class="lineNum">     219 </span>            :     &amp; _table_banks_1_io_r_resp_data_1_valid &amp; ~_resp_invalid_by_write_T_6</a>
+<a name="220"><span class="lineNum">     220 </span>            :     | s1_bank_req_1h_2 &amp; _table_banks_2_io_r_resp_data_1_tag == s1_tag</a>
+<a name="221"><span class="lineNum">     221 </span>            :     &amp; _table_banks_2_io_r_resp_data_1_valid &amp; ~_resp_invalid_by_write_T_6</a>
+<a name="222"><span class="lineNum">     222 </span>            :     | s1_bank_req_1h_3 &amp; _table_banks_3_io_r_resp_data_1_tag == s1_tag</a>
+<a name="223"><span class="lineNum">     223 </span>            :     &amp; _table_banks_3_io_r_resp_data_1_valid &amp; ~_resp_invalid_by_write_T_6;</a>
+<a name="224"><span class="lineNum">     224 </span>            :   assign _resp_invalid_by_write_T_6 =</a>
+<a name="225"><span class="lineNum">     225 </span>            :     s1_bank_req_1h_0 &amp; s1_bank_has_write_on_this_req_0 | s1_bank_req_1h_1</a>
+<a name="226"><span class="lineNum">     226 </span>            :     &amp; s1_bank_has_write_on_this_req_1 | s1_bank_req_1h_2 &amp; s1_bank_has_write_on_this_req_2</a>
+<a name="227"><span class="lineNum">     227 </span>            :     | s1_bank_req_1h_3 &amp; s1_bank_has_write_on_this_req_3;</a>
+<a name="228"><span class="lineNum">     228 </span><span class="lineCov">        158 :   wire [10:0] update_idx = io_update_pc[11:1] ^ io_update_folded_hist_hist_1_folded_hist;</span></a>
+<a name="229"><span class="lineNum">     229 </span><span class="lineCov">        114 :   wire [7:0]  update_tag =</span></a>
+<a name="230"><span class="lineNum">     230 </span>            :     io_update_pc[8:1] ^ io_update_folded_hist_hist_4_folded_hist</a>
+<a name="231"><span class="lineNum">     231 </span>            :     ^ {io_update_folded_hist_hist_15_folded_hist, 1'h0};</a>
+<a name="232"><span class="lineNum">     232 </span><span class="lineCov">         17 :   wire        update_req_bank_1h_0 = update_idx[1:0] == 2'h0;</span></a>
+<a name="233"><span class="lineNum">     233 </span><span class="lineCov">         12 :   wire        update_req_bank_1h_1 = update_idx[1:0] == 2'h1;</span></a>
+<a name="234"><span class="lineNum">     234 </span><span class="lineCov">         17 :   wire        update_req_bank_1h_2 = update_idx[1:0] == 2'h2;</span></a>
+<a name="235"><span class="lineNum">     235 </span><span class="lineCov">         48 :   wire [1:0]  per_bank_update_way_mask_0 =</span></a>
+<a name="236"><span class="lineNum">     236 </span>            :     {(io_update_pc[1] &amp; io_update_mask_0 | ~(io_update_pc[1]) &amp; io_update_mask_1)</a>
+<a name="237"><span class="lineNum">     237 </span>            :        &amp; per_bank_not_silent_update_0_1,</a>
+<a name="238"><span class="lineNum">     238 </span>            :      (~(io_update_pc[1]) &amp; io_update_mask_0 | io_update_pc[1] &amp; io_update_mask_1)</a>
+<a name="239"><span class="lineNum">     239 </span>            :        &amp; per_bank_not_silent_update_0_0};</a>
+<a name="240"><span class="lineNum">     240 </span><span class="lineCov">         52 :   wire [1:0]  per_bank_update_way_mask_1 =</span></a>
+<a name="241"><span class="lineNum">     241 </span>            :     {(io_update_pc[1] &amp; io_update_mask_0 | ~(io_update_pc[1]) &amp; io_update_mask_1)</a>
+<a name="242"><span class="lineNum">     242 </span>            :        &amp; per_bank_not_silent_update_1_1,</a>
+<a name="243"><span class="lineNum">     243 </span>            :      (~(io_update_pc[1]) &amp; io_update_mask_0 | io_update_pc[1] &amp; io_update_mask_1)</a>
+<a name="244"><span class="lineNum">     244 </span>            :        &amp; per_bank_not_silent_update_1_0};</a>
+<a name="245"><span class="lineNum">     245 </span><span class="lineCov">         54 :   wire [1:0]  per_bank_update_way_mask_2 =</span></a>
+<a name="246"><span class="lineNum">     246 </span>            :     {(io_update_pc[1] &amp; io_update_mask_0 | ~(io_update_pc[1]) &amp; io_update_mask_1)</a>
+<a name="247"><span class="lineNum">     247 </span>            :        &amp; per_bank_not_silent_update_2_1,</a>
+<a name="248"><span class="lineNum">     248 </span>            :      (~(io_update_pc[1]) &amp; io_update_mask_0 | io_update_pc[1] &amp; io_update_mask_1)</a>
+<a name="249"><span class="lineNum">     249 </span>            :        &amp; per_bank_not_silent_update_2_0};</a>
+<a name="250"><span class="lineNum">     250 </span><span class="lineCov">         54 :   wire [1:0]  per_bank_update_way_mask_3 =</span></a>
+<a name="251"><span class="lineNum">     251 </span>            :     {(io_update_pc[1] &amp; io_update_mask_0 | ~(io_update_pc[1]) &amp; io_update_mask_1)</a>
+<a name="252"><span class="lineNum">     252 </span>            :        &amp; per_bank_not_silent_update_3_1,</a>
+<a name="253"><span class="lineNum">     253 </span>            :      (~(io_update_pc[1]) &amp; io_update_mask_0 | io_update_pc[1] &amp; io_update_mask_1)</a>
+<a name="254"><span class="lineNum">     254 </span>            :        &amp; per_bank_not_silent_update_3_0};</a>
+<a name="255"><span class="lineNum">     255 </span>            :   wire        _s1_bank_has_write_on_this_req_WIRE_0 =</a>
+<a name="256"><span class="lineNum">     256 </span>            :     (|per_bank_update_way_mask_0) &amp; update_req_bank_1h_0;</a>
+<a name="257"><span class="lineNum">     257 </span>            :   wire        _s1_bank_has_write_on_this_req_WIRE_1 =</a>
+<a name="258"><span class="lineNum">     258 </span>            :     (|per_bank_update_way_mask_1) &amp; update_req_bank_1h_1;</a>
+<a name="259"><span class="lineNum">     259 </span>            :   wire        _s1_bank_has_write_on_this_req_WIRE_2 =</a>
+<a name="260"><span class="lineNum">     260 </span>            :     (|per_bank_update_way_mask_2) &amp; update_req_bank_1h_2;</a>
+<a name="261"><span class="lineNum">     261 </span>            :   wire        _s1_bank_has_write_on_this_req_WIRE_3 =</a>
+<a name="262"><span class="lineNum">     262 </span>            :     (|per_bank_update_way_mask_3) &amp; (&amp;(update_idx[1:0]));</a>
+<a name="263"><span class="lineNum">     263 </span>            :   wire [2:0]  _wrbypass_io_T_6 =</a>
+<a name="264"><span class="lineNum">     264 </span>            :     (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_0_0_io_hit_data_0_bits)</a>
+<a name="265"><span class="lineNum">     265 </span>            :     | (io_update_pc[1] ? _bank_wrbypasses_0_1_io_hit_data_0_bits : 3'h0);</a>
+<a name="266"><span class="lineNum">     266 </span><span class="lineCov">         17 :   wire        wrbypass_data_valid =</span></a>
+<a name="267"><span class="lineNum">     267 </span>            :     (~(io_update_pc[1]) &amp; _bank_wrbypasses_0_0_io_hit | io_update_pc[1]</a>
+<a name="268"><span class="lineNum">     268 </span>            :      &amp; _bank_wrbypasses_0_1_io_hit)</a>
+<a name="269"><span class="lineNum">     269 </span>            :     &amp; (~(io_update_pc[1]) &amp; _bank_wrbypasses_0_0_io_hit_data_0_valid | io_update_pc[1]</a>
+<a name="270"><span class="lineNum">     270 </span>            :        &amp; _bank_wrbypasses_0_1_io_hit_data_0_valid);</a>
+<a name="271"><span class="lineNum">     271 </span>            :   wire        _GEN = io_update_pc[1] ? io_update_takens_1 : io_update_takens_0;</a>
+<a name="272"><span class="lineNum">     272 </span>            :   wire [2:0]  _GEN_0 = io_update_pc[1] ? io_update_oldCtrs_1 : io_update_oldCtrs_0;</a>
+<a name="273"><span class="lineNum">     273 </span>            :   wire        _GEN_1 = (|_GEN_0) | _GEN;</a>
+<a name="274"><span class="lineNum">     274 </span>            :   wire        _GEN_2 = io_update_pc[1] ? io_update_alloc_1 : io_update_alloc_0;</a>
+<a name="275"><span class="lineNum">     275 </span><span class="lineCov">         46 :   wire [2:0]  per_bank_update_wdata_0_0_ctr =</span></a>
+<a name="276"><span class="lineNum">     276 </span>            :     _GEN_2</a>
+<a name="277"><span class="lineNum">     277 </span>            :       ? (_GEN ? 3'h4 : 3'h3)</a>
+<a name="278"><span class="lineNum">     278 </span>            :       : wrbypass_data_valid</a>
+<a name="279"><span class="lineNum">     279 </span>            :           ? ((&amp;_wrbypass_io_T_6) &amp; _GEN</a>
+<a name="280"><span class="lineNum">     280 </span>            :                ? 3'h7</a>
+<a name="281"><span class="lineNum">     281 </span>            :                : _wrbypass_io_T_6 == 3'h0 &amp; ~_GEN</a>
+<a name="282"><span class="lineNum">     282 </span>            :                    ? 3'h0</a>
+<a name="283"><span class="lineNum">     283 </span>            :                    : _GEN ? 3'(_wrbypass_io_T_6 + 3'h1) : 3'(_wrbypass_io_T_6 - 3'h1))</a>
+<a name="284"><span class="lineNum">     284 </span>            :           : (&amp;_GEN_0) &amp; _GEN</a>
+<a name="285"><span class="lineNum">     285 </span>            :               ? 3'h7</a>
+<a name="286"><span class="lineNum">     286 </span>            :               : _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0;</a>
+<a name="287"><span class="lineNum">     287 </span>            :   assign per_bank_not_silent_update_0_0 =</a>
+<a name="288"><span class="lineNum">     288 </span>            :     (wrbypass_data_valid</a>
+<a name="289"><span class="lineNum">     289 </span>            :        ? ~((&amp;_wrbypass_io_T_6) &amp; _GEN | _wrbypass_io_T_6 == 3'h0 &amp; ~_GEN)</a>
+<a name="290"><span class="lineNum">     290 </span>            :        : ~((&amp;_GEN_0) &amp; _GEN | _GEN_0 == 3'h0 &amp; ~_GEN)) | _GEN_2;</a>
+<a name="291"><span class="lineNum">     291 </span>            :   wire [2:0]  _wrbypass_io_T_28 =</a>
+<a name="292"><span class="lineNum">     292 </span>            :     (io_update_pc[1] ? _bank_wrbypasses_0_0_io_hit_data_0_bits : 3'h0)</a>
+<a name="293"><span class="lineNum">     293 </span>            :     | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_0_1_io_hit_data_0_bits);</a>
+<a name="294"><span class="lineNum">     294 </span><span class="lineCov">         19 :   wire        wrbypass_data_valid_1 =</span></a>
+<a name="295"><span class="lineNum">     295 </span>            :     (io_update_pc[1] &amp; _bank_wrbypasses_0_0_io_hit | ~(io_update_pc[1])</a>
+<a name="296"><span class="lineNum">     296 </span>            :      &amp; _bank_wrbypasses_0_1_io_hit)</a>
+<a name="297"><span class="lineNum">     297 </span>            :     &amp; (io_update_pc[1] &amp; _bank_wrbypasses_0_0_io_hit_data_0_valid | ~(io_update_pc[1])</a>
+<a name="298"><span class="lineNum">     298 </span>            :        &amp; _bank_wrbypasses_0_1_io_hit_data_0_valid);</a>
+<a name="299"><span class="lineNum">     299 </span>            :   wire        _GEN_3 = io_update_pc[1] ? io_update_takens_0 : io_update_takens_1;</a>
+<a name="300"><span class="lineNum">     300 </span>            :   wire [2:0]  _GEN_4 = io_update_pc[1] ? io_update_oldCtrs_0 : io_update_oldCtrs_1;</a>
+<a name="301"><span class="lineNum">     301 </span>            :   wire        _GEN_5 = io_update_pc[1] ? io_update_alloc_0 : io_update_alloc_1;</a>
+<a name="302"><span class="lineNum">     302 </span><span class="lineCov">         44 :   wire [2:0]  per_bank_update_wdata_0_1_ctr =</span></a>
+<a name="303"><span class="lineNum">     303 </span>            :     _GEN_5</a>
+<a name="304"><span class="lineNum">     304 </span>            :       ? (_GEN_3 ? 3'h4 : 3'h3)</a>
+<a name="305"><span class="lineNum">     305 </span>            :       : wrbypass_data_valid_1</a>
+<a name="306"><span class="lineNum">     306 </span>            :           ? ((&amp;_wrbypass_io_T_28) &amp; _GEN_3</a>
+<a name="307"><span class="lineNum">     307 </span>            :                ? 3'h7</a>
+<a name="308"><span class="lineNum">     308 </span>            :                : _wrbypass_io_T_28 == 3'h0 &amp; ~_GEN_3</a>
+<a name="309"><span class="lineNum">     309 </span>            :                    ? 3'h0</a>
+<a name="310"><span class="lineNum">     310 </span>            :                    : _GEN_3 ? 3'(_wrbypass_io_T_28 + 3'h1) : 3'(_wrbypass_io_T_28 - 3'h1))</a>
+<a name="311"><span class="lineNum">     311 </span>            :           : (&amp;_GEN_4) &amp; _GEN_3</a>
+<a name="312"><span class="lineNum">     312 </span>            :               ? 3'h7</a>
+<a name="313"><span class="lineNum">     313 </span>            :               : _GEN_4 == 3'h0 &amp; ~_GEN_3</a>
+<a name="314"><span class="lineNum">     314 </span>            :                   ? 3'h0</a>
+<a name="315"><span class="lineNum">     315 </span>            :                   : _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1);</a>
+<a name="316"><span class="lineNum">     316 </span>            :   assign per_bank_not_silent_update_0_1 =</a>
+<a name="317"><span class="lineNum">     317 </span>            :     (wrbypass_data_valid_1</a>
+<a name="318"><span class="lineNum">     318 </span>            :        ? ~((&amp;_wrbypass_io_T_28) &amp; _GEN_3 | _wrbypass_io_T_28 == 3'h0 &amp; ~_GEN_3)</a>
+<a name="319"><span class="lineNum">     319 </span>            :        : ~((&amp;_GEN_4) &amp; _GEN_3 | _GEN_4 == 3'h0 &amp; ~_GEN_3)) | _GEN_5;</a>
+<a name="320"><span class="lineNum">     320 </span>            :   wire [2:0]  _wrbypass_io_T_50 =</a>
+<a name="321"><span class="lineNum">     321 </span>            :     (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_1_0_io_hit_data_0_bits)</a>
+<a name="322"><span class="lineNum">     322 </span>            :     | (io_update_pc[1] ? _bank_wrbypasses_1_1_io_hit_data_0_bits : 3'h0);</a>
+<a name="323"><span class="lineNum">     323 </span><span class="lineCov">         17 :   wire        wrbypass_data_valid_2 =</span></a>
+<a name="324"><span class="lineNum">     324 </span>            :     (~(io_update_pc[1]) &amp; _bank_wrbypasses_1_0_io_hit | io_update_pc[1]</a>
+<a name="325"><span class="lineNum">     325 </span>            :      &amp; _bank_wrbypasses_1_1_io_hit)</a>
+<a name="326"><span class="lineNum">     326 </span>            :     &amp; (~(io_update_pc[1]) &amp; _bank_wrbypasses_1_0_io_hit_data_0_valid | io_update_pc[1]</a>
+<a name="327"><span class="lineNum">     327 </span>            :        &amp; _bank_wrbypasses_1_1_io_hit_data_0_valid);</a>
+<a name="328"><span class="lineNum">     328 </span><span class="lineCov">         35 :   wire [2:0]  per_bank_update_wdata_1_0_ctr =</span></a>
+<a name="329"><span class="lineNum">     329 </span>            :     _GEN_2</a>
+<a name="330"><span class="lineNum">     330 </span>            :       ? (_GEN ? 3'h4 : 3'h3)</a>
+<a name="331"><span class="lineNum">     331 </span>            :       : wrbypass_data_valid_2</a>
+<a name="332"><span class="lineNum">     332 </span>            :           ? ((&amp;_wrbypass_io_T_50) &amp; _GEN</a>
+<a name="333"><span class="lineNum">     333 </span>            :                ? 3'h7</a>
+<a name="334"><span class="lineNum">     334 </span>            :                : _wrbypass_io_T_50 == 3'h0 &amp; ~_GEN</a>
+<a name="335"><span class="lineNum">     335 </span>            :                    ? 3'h0</a>
+<a name="336"><span class="lineNum">     336 </span>            :                    : _GEN ? 3'(_wrbypass_io_T_50 + 3'h1) : 3'(_wrbypass_io_T_50 - 3'h1))</a>
+<a name="337"><span class="lineNum">     337 </span>            :           : (&amp;_GEN_0) &amp; _GEN</a>
+<a name="338"><span class="lineNum">     338 </span>            :               ? 3'h7</a>
+<a name="339"><span class="lineNum">     339 </span>            :               : _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0;</a>
+<a name="340"><span class="lineNum">     340 </span>            :   assign per_bank_not_silent_update_1_0 =</a>
+<a name="341"><span class="lineNum">     341 </span>            :     (wrbypass_data_valid_2</a>
+<a name="342"><span class="lineNum">     342 </span>            :        ? ~((&amp;_wrbypass_io_T_50) &amp; _GEN | _wrbypass_io_T_50 == 3'h0 &amp; ~_GEN)</a>
+<a name="343"><span class="lineNum">     343 </span>            :        : ~((&amp;_GEN_0) &amp; _GEN | _GEN_0 == 3'h0 &amp; ~_GEN)) | _GEN_2;</a>
+<a name="344"><span class="lineNum">     344 </span>            :   wire [2:0]  _wrbypass_io_T_72 =</a>
+<a name="345"><span class="lineNum">     345 </span>            :     (io_update_pc[1] ? _bank_wrbypasses_1_0_io_hit_data_0_bits : 3'h0)</a>
+<a name="346"><span class="lineNum">     346 </span>            :     | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_1_1_io_hit_data_0_bits);</a>
+<a name="347"><span class="lineNum">     347 </span><span class="lineCov">         23 :   wire        wrbypass_data_valid_3 =</span></a>
+<a name="348"><span class="lineNum">     348 </span>            :     (io_update_pc[1] &amp; _bank_wrbypasses_1_0_io_hit | ~(io_update_pc[1])</a>
+<a name="349"><span class="lineNum">     349 </span>            :      &amp; _bank_wrbypasses_1_1_io_hit)</a>
+<a name="350"><span class="lineNum">     350 </span>            :     &amp; (io_update_pc[1] &amp; _bank_wrbypasses_1_0_io_hit_data_0_valid | ~(io_update_pc[1])</a>
+<a name="351"><span class="lineNum">     351 </span>            :        &amp; _bank_wrbypasses_1_1_io_hit_data_0_valid);</a>
+<a name="352"><span class="lineNum">     352 </span><span class="lineCov">         48 :   wire [2:0]  per_bank_update_wdata_1_1_ctr =</span></a>
+<a name="353"><span class="lineNum">     353 </span>            :     _GEN_5</a>
+<a name="354"><span class="lineNum">     354 </span>            :       ? (_GEN_3 ? 3'h4 : 3'h3)</a>
+<a name="355"><span class="lineNum">     355 </span>            :       : wrbypass_data_valid_3</a>
+<a name="356"><span class="lineNum">     356 </span>            :           ? ((&amp;_wrbypass_io_T_72) &amp; _GEN_3</a>
+<a name="357"><span class="lineNum">     357 </span>            :                ? 3'h7</a>
+<a name="358"><span class="lineNum">     358 </span>            :                : _wrbypass_io_T_72 == 3'h0 &amp; ~_GEN_3</a>
+<a name="359"><span class="lineNum">     359 </span>            :                    ? 3'h0</a>
+<a name="360"><span class="lineNum">     360 </span>            :                    : _GEN_3 ? 3'(_wrbypass_io_T_72 + 3'h1) : 3'(_wrbypass_io_T_72 - 3'h1))</a>
+<a name="361"><span class="lineNum">     361 </span>            :           : (&amp;_GEN_4) &amp; _GEN_3</a>
+<a name="362"><span class="lineNum">     362 </span>            :               ? 3'h7</a>
+<a name="363"><span class="lineNum">     363 </span>            :               : _GEN_4 == 3'h0 &amp; ~_GEN_3</a>
+<a name="364"><span class="lineNum">     364 </span>            :                   ? 3'h0</a>
+<a name="365"><span class="lineNum">     365 </span>            :                   : _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1);</a>
+<a name="366"><span class="lineNum">     366 </span>            :   assign per_bank_not_silent_update_1_1 =</a>
+<a name="367"><span class="lineNum">     367 </span>            :     (wrbypass_data_valid_3</a>
+<a name="368"><span class="lineNum">     368 </span>            :        ? ~((&amp;_wrbypass_io_T_72) &amp; _GEN_3 | _wrbypass_io_T_72 == 3'h0 &amp; ~_GEN_3)</a>
+<a name="369"><span class="lineNum">     369 </span>            :        : ~((&amp;_GEN_4) &amp; _GEN_3 | _GEN_4 == 3'h0 &amp; ~_GEN_3)) | _GEN_5;</a>
+<a name="370"><span class="lineNum">     370 </span>            :   wire [2:0]  _wrbypass_io_T_94 =</a>
+<a name="371"><span class="lineNum">     371 </span>            :     (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_2_0_io_hit_data_0_bits)</a>
+<a name="372"><span class="lineNum">     372 </span>            :     | (io_update_pc[1] ? _bank_wrbypasses_2_1_io_hit_data_0_bits : 3'h0);</a>
+<a name="373"><span class="lineNum">     373 </span><span class="lineCov">         14 :   wire        wrbypass_data_valid_4 =</span></a>
+<a name="374"><span class="lineNum">     374 </span>            :     (~(io_update_pc[1]) &amp; _bank_wrbypasses_2_0_io_hit | io_update_pc[1]</a>
+<a name="375"><span class="lineNum">     375 </span>            :      &amp; _bank_wrbypasses_2_1_io_hit)</a>
+<a name="376"><span class="lineNum">     376 </span>            :     &amp; (~(io_update_pc[1]) &amp; _bank_wrbypasses_2_0_io_hit_data_0_valid | io_update_pc[1]</a>
+<a name="377"><span class="lineNum">     377 </span>            :        &amp; _bank_wrbypasses_2_1_io_hit_data_0_valid);</a>
+<a name="378"><span class="lineNum">     378 </span><span class="lineCov">         45 :   wire [2:0]  per_bank_update_wdata_2_0_ctr =</span></a>
+<a name="379"><span class="lineNum">     379 </span>            :     _GEN_2</a>
+<a name="380"><span class="lineNum">     380 </span>            :       ? (_GEN ? 3'h4 : 3'h3)</a>
+<a name="381"><span class="lineNum">     381 </span>            :       : wrbypass_data_valid_4</a>
+<a name="382"><span class="lineNum">     382 </span>            :           ? ((&amp;_wrbypass_io_T_94) &amp; _GEN</a>
+<a name="383"><span class="lineNum">     383 </span>            :                ? 3'h7</a>
+<a name="384"><span class="lineNum">     384 </span>            :                : _wrbypass_io_T_94 == 3'h0 &amp; ~_GEN</a>
+<a name="385"><span class="lineNum">     385 </span>            :                    ? 3'h0</a>
+<a name="386"><span class="lineNum">     386 </span>            :                    : _GEN ? 3'(_wrbypass_io_T_94 + 3'h1) : 3'(_wrbypass_io_T_94 - 3'h1))</a>
+<a name="387"><span class="lineNum">     387 </span>            :           : (&amp;_GEN_0) &amp; _GEN</a>
+<a name="388"><span class="lineNum">     388 </span>            :               ? 3'h7</a>
+<a name="389"><span class="lineNum">     389 </span>            :               : _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0;</a>
+<a name="390"><span class="lineNum">     390 </span>            :   assign per_bank_not_silent_update_2_0 =</a>
+<a name="391"><span class="lineNum">     391 </span>            :     (wrbypass_data_valid_4</a>
+<a name="392"><span class="lineNum">     392 </span>            :        ? ~((&amp;_wrbypass_io_T_94) &amp; _GEN | _wrbypass_io_T_94 == 3'h0 &amp; ~_GEN)</a>
+<a name="393"><span class="lineNum">     393 </span>            :        : ~((&amp;_GEN_0) &amp; _GEN | _GEN_0 == 3'h0 &amp; ~_GEN)) | _GEN_2;</a>
+<a name="394"><span class="lineNum">     394 </span>            :   wire [2:0]  _wrbypass_io_T_116 =</a>
+<a name="395"><span class="lineNum">     395 </span>            :     (io_update_pc[1] ? _bank_wrbypasses_2_0_io_hit_data_0_bits : 3'h0)</a>
+<a name="396"><span class="lineNum">     396 </span>            :     | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_2_1_io_hit_data_0_bits);</a>
+<a name="397"><span class="lineNum">     397 </span><span class="lineCov">         13 :   wire        wrbypass_data_valid_5 =</span></a>
+<a name="398"><span class="lineNum">     398 </span>            :     (io_update_pc[1] &amp; _bank_wrbypasses_2_0_io_hit | ~(io_update_pc[1])</a>
+<a name="399"><span class="lineNum">     399 </span>            :      &amp; _bank_wrbypasses_2_1_io_hit)</a>
+<a name="400"><span class="lineNum">     400 </span>            :     &amp; (io_update_pc[1] &amp; _bank_wrbypasses_2_0_io_hit_data_0_valid | ~(io_update_pc[1])</a>
+<a name="401"><span class="lineNum">     401 </span>            :        &amp; _bank_wrbypasses_2_1_io_hit_data_0_valid);</a>
+<a name="402"><span class="lineNum">     402 </span><span class="lineCov">         44 :   wire [2:0]  per_bank_update_wdata_2_1_ctr =</span></a>
+<a name="403"><span class="lineNum">     403 </span>            :     _GEN_5</a>
+<a name="404"><span class="lineNum">     404 </span>            :       ? (_GEN_3 ? 3'h4 : 3'h3)</a>
+<a name="405"><span class="lineNum">     405 </span>            :       : wrbypass_data_valid_5</a>
+<a name="406"><span class="lineNum">     406 </span>            :           ? ((&amp;_wrbypass_io_T_116) &amp; _GEN_3</a>
+<a name="407"><span class="lineNum">     407 </span>            :                ? 3'h7</a>
+<a name="408"><span class="lineNum">     408 </span>            :                : _wrbypass_io_T_116 == 3'h0 &amp; ~_GEN_3</a>
+<a name="409"><span class="lineNum">     409 </span>            :                    ? 3'h0</a>
+<a name="410"><span class="lineNum">     410 </span>            :                    : _GEN_3</a>
+<a name="411"><span class="lineNum">     411 </span>            :                        ? 3'(_wrbypass_io_T_116 + 3'h1)</a>
+<a name="412"><span class="lineNum">     412 </span>            :                        : 3'(_wrbypass_io_T_116 - 3'h1))</a>
+<a name="413"><span class="lineNum">     413 </span>            :           : (&amp;_GEN_4) &amp; _GEN_3</a>
+<a name="414"><span class="lineNum">     414 </span>            :               ? 3'h7</a>
+<a name="415"><span class="lineNum">     415 </span>            :               : _GEN_4 == 3'h0 &amp; ~_GEN_3</a>
+<a name="416"><span class="lineNum">     416 </span>            :                   ? 3'h0</a>
+<a name="417"><span class="lineNum">     417 </span>            :                   : _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1);</a>
+<a name="418"><span class="lineNum">     418 </span>            :   assign per_bank_not_silent_update_2_1 =</a>
+<a name="419"><span class="lineNum">     419 </span>            :     (wrbypass_data_valid_5</a>
+<a name="420"><span class="lineNum">     420 </span>            :        ? ~((&amp;_wrbypass_io_T_116) &amp; _GEN_3 | _wrbypass_io_T_116 == 3'h0 &amp; ~_GEN_3)</a>
+<a name="421"><span class="lineNum">     421 </span>            :        : ~((&amp;_GEN_4) &amp; _GEN_3 | _GEN_4 == 3'h0 &amp; ~_GEN_3)) | _GEN_5;</a>
+<a name="422"><span class="lineNum">     422 </span>            :   wire [2:0]  _wrbypass_io_T_138 =</a>
+<a name="423"><span class="lineNum">     423 </span>            :     (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_3_0_io_hit_data_0_bits)</a>
+<a name="424"><span class="lineNum">     424 </span>            :     | (io_update_pc[1] ? _bank_wrbypasses_3_1_io_hit_data_0_bits : 3'h0);</a>
+<a name="425"><span class="lineNum">     425 </span><span class="lineCov">         19 :   wire        wrbypass_data_valid_6 =</span></a>
+<a name="426"><span class="lineNum">     426 </span>            :     (~(io_update_pc[1]) &amp; _bank_wrbypasses_3_0_io_hit | io_update_pc[1]</a>
+<a name="427"><span class="lineNum">     427 </span>            :      &amp; _bank_wrbypasses_3_1_io_hit)</a>
+<a name="428"><span class="lineNum">     428 </span>            :     &amp; (~(io_update_pc[1]) &amp; _bank_wrbypasses_3_0_io_hit_data_0_valid | io_update_pc[1]</a>
+<a name="429"><span class="lineNum">     429 </span>            :        &amp; _bank_wrbypasses_3_1_io_hit_data_0_valid);</a>
+<a name="430"><span class="lineNum">     430 </span><span class="lineCov">         50 :   wire [2:0]  per_bank_update_wdata_3_0_ctr =</span></a>
+<a name="431"><span class="lineNum">     431 </span>            :     _GEN_2</a>
+<a name="432"><span class="lineNum">     432 </span>            :       ? (_GEN ? 3'h4 : 3'h3)</a>
+<a name="433"><span class="lineNum">     433 </span>            :       : wrbypass_data_valid_6</a>
+<a name="434"><span class="lineNum">     434 </span>            :           ? ((&amp;_wrbypass_io_T_138) &amp; _GEN</a>
+<a name="435"><span class="lineNum">     435 </span>            :                ? 3'h7</a>
+<a name="436"><span class="lineNum">     436 </span>            :                : _wrbypass_io_T_138 == 3'h0 &amp; ~_GEN</a>
+<a name="437"><span class="lineNum">     437 </span>            :                    ? 3'h0</a>
+<a name="438"><span class="lineNum">     438 </span>            :                    : _GEN ? 3'(_wrbypass_io_T_138 + 3'h1) : 3'(_wrbypass_io_T_138 - 3'h1))</a>
+<a name="439"><span class="lineNum">     439 </span>            :           : (&amp;_GEN_0) &amp; _GEN</a>
+<a name="440"><span class="lineNum">     440 </span>            :               ? 3'h7</a>
+<a name="441"><span class="lineNum">     441 </span>            :               : _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0;</a>
+<a name="442"><span class="lineNum">     442 </span>            :   assign per_bank_not_silent_update_3_0 =</a>
+<a name="443"><span class="lineNum">     443 </span>            :     (wrbypass_data_valid_6</a>
+<a name="444"><span class="lineNum">     444 </span>            :        ? ~((&amp;_wrbypass_io_T_138) &amp; _GEN | _wrbypass_io_T_138 == 3'h0 &amp; ~_GEN)</a>
+<a name="445"><span class="lineNum">     445 </span>            :        : ~((&amp;_GEN_0) &amp; _GEN | _GEN_0 == 3'h0 &amp; ~_GEN)) | _GEN_2;</a>
+<a name="446"><span class="lineNum">     446 </span>            :   wire [2:0]  _wrbypass_io_T_160 =</a>
+<a name="447"><span class="lineNum">     447 </span>            :     (io_update_pc[1] ? _bank_wrbypasses_3_0_io_hit_data_0_bits : 3'h0)</a>
+<a name="448"><span class="lineNum">     448 </span>            :     | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_3_1_io_hit_data_0_bits);</a>
+<a name="449"><span class="lineNum">     449 </span><span class="lineCov">         28 :   wire        wrbypass_data_valid_7 =</span></a>
+<a name="450"><span class="lineNum">     450 </span>            :     (io_update_pc[1] &amp; _bank_wrbypasses_3_0_io_hit | ~(io_update_pc[1])</a>
+<a name="451"><span class="lineNum">     451 </span>            :      &amp; _bank_wrbypasses_3_1_io_hit)</a>
+<a name="452"><span class="lineNum">     452 </span>            :     &amp; (io_update_pc[1] &amp; _bank_wrbypasses_3_0_io_hit_data_0_valid | ~(io_update_pc[1])</a>
+<a name="453"><span class="lineNum">     453 </span>            :        &amp; _bank_wrbypasses_3_1_io_hit_data_0_valid);</a>
+<a name="454"><span class="lineNum">     454 </span><span class="lineCov">         46 :   wire [2:0]  per_bank_update_wdata_3_1_ctr =</span></a>
+<a name="455"><span class="lineNum">     455 </span>            :     _GEN_5</a>
+<a name="456"><span class="lineNum">     456 </span>            :       ? (_GEN_3 ? 3'h4 : 3'h3)</a>
+<a name="457"><span class="lineNum">     457 </span>            :       : wrbypass_data_valid_7</a>
+<a name="458"><span class="lineNum">     458 </span>            :           ? ((&amp;_wrbypass_io_T_160) &amp; _GEN_3</a>
+<a name="459"><span class="lineNum">     459 </span>            :                ? 3'h7</a>
+<a name="460"><span class="lineNum">     460 </span>            :                : _wrbypass_io_T_160 == 3'h0 &amp; ~_GEN_3</a>
+<a name="461"><span class="lineNum">     461 </span>            :                    ? 3'h0</a>
+<a name="462"><span class="lineNum">     462 </span>            :                    : _GEN_3</a>
+<a name="463"><span class="lineNum">     463 </span>            :                        ? 3'(_wrbypass_io_T_160 + 3'h1)</a>
+<a name="464"><span class="lineNum">     464 </span>            :                        : 3'(_wrbypass_io_T_160 - 3'h1))</a>
+<a name="465"><span class="lineNum">     465 </span>            :           : (&amp;_GEN_4) &amp; _GEN_3</a>
+<a name="466"><span class="lineNum">     466 </span>            :               ? 3'h7</a>
+<a name="467"><span class="lineNum">     467 </span>            :               : _GEN_4 == 3'h0 &amp; ~_GEN_3</a>
+<a name="468"><span class="lineNum">     468 </span>            :                   ? 3'h0</a>
+<a name="469"><span class="lineNum">     469 </span>            :                   : _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1);</a>
+<a name="470"><span class="lineNum">     470 </span>            :   assign per_bank_not_silent_update_3_1 =</a>
+<a name="471"><span class="lineNum">     471 </span>            :     (wrbypass_data_valid_7</a>
+<a name="472"><span class="lineNum">     472 </span>            :        ? ~((&amp;_wrbypass_io_T_160) &amp; _GEN_3 | _wrbypass_io_T_160 == 3'h0 &amp; ~_GEN_3)</a>
+<a name="473"><span class="lineNum">     473 </span>            :        : ~((&amp;_GEN_4) &amp; _GEN_3 | _GEN_4 == 3'h0 &amp; ~_GEN_3)) | _GEN_5;</a>
+<a name="474"><span class="lineNum">     474 </span><span class="lineCov">     127694 :   always @(posedge clock) begin</span></a>
+<a name="475"><span class="lineNum">     475 </span><span class="lineCov">       8350 :     if (_s1_bank_req_1h_T) begin</span></a>
+<a name="476"><span class="lineNum">     476 </span><span class="lineCov">       4175 :       s1_unhashed_idx &lt;= io_req_bits_pc[40:1];</span></a>
+<a name="477"><span class="lineNum">     477 </span><span class="lineCov">       4175 :       s1_tag &lt;=</span></a>
+<a name="478"><span class="lineNum">     478 </span><span class="lineCov">       4175 :         io_req_bits_pc[8:1] ^ io_req_bits_folded_hist_hist_4_folded_hist</span></a>
+<a name="479"><span class="lineNum">     479 </span><span class="lineCov">       4175 :         ^ {io_req_bits_folded_hist_hist_15_folded_hist, 1'h0};</span></a>
+<a name="480"><span class="lineNum">     480 </span><span class="lineCov">       4175 :       s1_bank_req_1h_0 &lt;= s0_bank_req_1h_0;</span></a>
+<a name="481"><span class="lineNum">     481 </span><span class="lineCov">       4175 :       s1_bank_req_1h_1 &lt;= s0_bank_req_1h_1;</span></a>
+<a name="482"><span class="lineNum">     482 </span><span class="lineCov">       4175 :       s1_bank_req_1h_2 &lt;= s0_bank_req_1h_2;</span></a>
+<a name="483"><span class="lineNum">     483 </span><span class="lineCov">       4175 :       s1_bank_req_1h_3 &lt;= &amp;(s0_idx[1:0]);</span></a>
+<a name="484"><span class="lineNum">     484 </span>            :     end</a>
+<a name="485"><span class="lineNum">     485 </span><span class="lineCov">       8350 :     if (io_req_valid) begin</span></a>
+<a name="486"><span class="lineNum">     486 </span><span class="lineCov">       4175 :       s1_bank_has_write_on_this_req_0 &lt;= _s1_bank_has_write_on_this_req_WIRE_0;</span></a>
+<a name="487"><span class="lineNum">     487 </span><span class="lineCov">       4175 :       s1_bank_has_write_on_this_req_1 &lt;= _s1_bank_has_write_on_this_req_WIRE_1;</span></a>
+<a name="488"><span class="lineNum">     488 </span><span class="lineCov">       4175 :       s1_bank_has_write_on_this_req_2 &lt;= _s1_bank_has_write_on_this_req_WIRE_2;</span></a>
+<a name="489"><span class="lineNum">     489 </span><span class="lineCov">       4175 :       s1_bank_has_write_on_this_req_3 &lt;= _s1_bank_has_write_on_this_req_WIRE_3;</span></a>
+<a name="490"><span class="lineNum">     490 </span>            :     end</a>
+<a name="491"><span class="lineNum">     491 </span>            :   end // always @(posedge)</a>
+<a name="492"><span class="lineNum">     492 </span><span class="lineCov">     127730 :   always @(posedge clock or posedge reset) begin</span></a>
+<a name="493"><span class="lineNum">     493 </span><span class="lineCov">        272 :     if (reset)</span></a>
+<a name="494"><span class="lineNum">     494 </span><span class="lineCov">        136 :       powerOnResetState &lt;= 1'h1;</span></a>
+<a name="495"><span class="lineNum">     495 </span>            :     else</a>
+<a name="496"><span class="lineNum">     496 </span><span class="lineCov">      63729 :       powerOnResetState &lt;=</span></a>
+<a name="497"><span class="lineNum">     497 </span><span class="lineCov">      63729 :         ~(_us_io_r_req_ready &amp; _table_banks_0_io_r_req_ready</span></a>
+<a name="498"><span class="lineNum">     498 </span><span class="lineCov">      63729 :           &amp; _table_banks_1_io_r_req_ready &amp; _table_banks_2_io_r_req_ready</span></a>
+<a name="499"><span class="lineNum">     499 </span><span class="lineCov">      63729 :           &amp; _table_banks_3_io_r_req_ready) &amp; powerOnResetState;</span></a>
+<a name="500"><span class="lineNum">     500 </span>            :   end // always @(posedge, posedge)</a>
+<a name="501"><span class="lineNum">     501 </span>            :   `ifdef ENABLE_INITIAL_REG_</a>
+<a name="502"><span class="lineNum">     502 </span>            :     `ifdef FIRRTL_BEFORE_INITIAL</a>
+<a name="503"><span class="lineNum">     503 </span>            :       `FIRRTL_BEFORE_INITIAL</a>
+<a name="504"><span class="lineNum">     504 </span>            :     `endif // FIRRTL_BEFORE_INITIAL</a>
+<a name="505"><span class="lineNum">     505 </span>            :     logic [31:0] _RANDOM[0:3];</a>
+<a name="506"><span class="lineNum">     506 </span><span class="lineCov">         58 :     initial begin</span></a>
+<a name="507"><span class="lineNum">     507 </span>            :       `ifdef INIT_RANDOM_PROLOG_</a>
+<a name="508"><span class="lineNum">     508 </span>            :         `INIT_RANDOM_PROLOG_</a>
+<a name="509"><span class="lineNum">     509 </span>            :       `endif // INIT_RANDOM_PROLOG_</a>
+<a name="510"><span class="lineNum">     510 </span>            :       `ifdef RANDOMIZE_REG_INIT</a>
+<a name="511"><span class="lineNum">     511 </span>            :         for (logic [2:0] i = 3'h0; i &lt; 3'h4; i += 3'h1) begin</a>
+<a name="512"><span class="lineNum">     512 </span>            :           _RANDOM[i[1:0]] = `RANDOM;</a>
+<a name="513"><span class="lineNum">     513 </span>            :         end</a>
+<a name="514"><span class="lineNum">     514 </span>            :         s1_unhashed_idx = {_RANDOM[2'h0], _RANDOM[2'h1][7:0]};</a>
+<a name="515"><span class="lineNum">     515 </span>            :         s1_tag = _RANDOM[2'h1][26:19];</a>
+<a name="516"><span class="lineNum">     516 </span>            :         s1_bank_req_1h_0 = _RANDOM[2'h3][4];</a>
+<a name="517"><span class="lineNum">     517 </span>            :         s1_bank_req_1h_1 = _RANDOM[2'h3][5];</a>
+<a name="518"><span class="lineNum">     518 </span>            :         s1_bank_req_1h_2 = _RANDOM[2'h3][6];</a>
+<a name="519"><span class="lineNum">     519 </span>            :         s1_bank_req_1h_3 = _RANDOM[2'h3][7];</a>
+<a name="520"><span class="lineNum">     520 </span>            :         s1_bank_has_write_on_this_req_0 = _RANDOM[2'h3][8];</a>
+<a name="521"><span class="lineNum">     521 </span>            :         s1_bank_has_write_on_this_req_1 = _RANDOM[2'h3][9];</a>
+<a name="522"><span class="lineNum">     522 </span>            :         s1_bank_has_write_on_this_req_2 = _RANDOM[2'h3][10];</a>
+<a name="523"><span class="lineNum">     523 </span>            :         s1_bank_has_write_on_this_req_3 = _RANDOM[2'h3][11];</a>
+<a name="524"><span class="lineNum">     524 </span>            :         powerOnResetState = _RANDOM[2'h3][12];</a>
+<a name="525"><span class="lineNum">     525 </span>            :       `endif // RANDOMIZE_REG_INIT</a>
+<a name="526"><span class="lineNum">     526 </span><span class="lineCov">         17 :       if (reset)</span></a>
+<a name="527"><span class="lineNum">     527 </span><span class="lineCov">         12 :         powerOnResetState = 1'h1;</span></a>
+<a name="528"><span class="lineNum">     528 </span>            :     end // initial</a>
+<a name="529"><span class="lineNum">     529 </span>            :     `ifdef FIRRTL_AFTER_INITIAL</a>
+<a name="530"><span class="lineNum">     530 </span>            :       `FIRRTL_AFTER_INITIAL</a>
+<a name="531"><span class="lineNum">     531 </span>            :     `endif // FIRRTL_AFTER_INITIAL</a>
+<a name="532"><span class="lineNum">     532 </span>            :   `endif // ENABLE_INITIAL_REG_</a>
+<a name="533"><span class="lineNum">     533 </span>            :   FoldedSRAMTemplate us (</a>
+<a name="534"><span class="lineNum">     534 </span>            :     .clock                 (clock),</a>
+<a name="535"><span class="lineNum">     535 </span>            :     .reset                 (reset),</a>
+<a name="536"><span class="lineNum">     536 </span>            :     .io_r_req_ready        (_us_io_r_req_ready),</a>
+<a name="537"><span class="lineNum">     537 </span>            :     .io_r_req_valid        (_s1_bank_req_1h_T),</a>
+<a name="538"><span class="lineNum">     538 </span>            :     .io_r_req_bits_setIdx  (s0_idx),</a>
+<a name="539"><span class="lineNum">     539 </span>            :     .io_r_resp_data_0      (_us_io_r_resp_data_0),</a>
+<a name="540"><span class="lineNum">     540 </span>            :     .io_r_resp_data_1      (_us_io_r_resp_data_1),</a>
+<a name="541"><span class="lineNum">     541 </span>            :     .io_w_req_valid</a>
+<a name="542"><span class="lineNum">     542 </span>            :       (_us_extra_reset_T_1 &amp; (io_update_uMask_0 | io_update_uMask_1)),</a>
+<a name="543"><span class="lineNum">     543 </span>            :     .io_w_req_bits_setIdx  (update_idx),</a>
+<a name="544"><span class="lineNum">     544 </span>            :     .io_w_req_bits_data_0</a>
+<a name="545"><span class="lineNum">     545 </span>            :       (~(io_update_pc[1]) &amp; io_update_us_0 | io_update_pc[1] &amp; io_update_us_1),</a>
+<a name="546"><span class="lineNum">     546 </span>            :     .io_w_req_bits_data_1</a>
+<a name="547"><span class="lineNum">     547 </span>            :       (io_update_pc[1] &amp; io_update_us_0 | ~(io_update_pc[1]) &amp; io_update_us_1),</a>
+<a name="548"><span class="lineNum">     548 </span>            :     .io_w_req_bits_waymask</a>
+<a name="549"><span class="lineNum">     549 </span>            :       ({io_update_pc[1] &amp; io_update_uMask_0 | ~(io_update_pc[1]) &amp; io_update_uMask_1,</a>
+<a name="550"><span class="lineNum">     550 </span>            :         ~(io_update_pc[1]) &amp; io_update_uMask_0 | io_update_pc[1] &amp; io_update_uMask_1}),</a>
+<a name="551"><span class="lineNum">     551 </span>            :     .extra_reset</a>
+<a name="552"><span class="lineNum">     552 </span>            :       ((io_update_reset_u_0 | io_update_reset_u_1) &amp; _us_extra_reset_T_1)</a>
+<a name="553"><span class="lineNum">     553 </span>            :   );</a>
+<a name="554"><span class="lineNum">     554 </span>            :   FoldedSRAMTemplate_1 table_banks_0 (</a>
+<a name="555"><span class="lineNum">     555 </span>            :     .clock                    (clock),</a>
+<a name="556"><span class="lineNum">     556 </span>            :     .reset                    (reset),</a>
+<a name="557"><span class="lineNum">     557 </span>            :     .io_r_req_ready           (_table_banks_0_io_r_req_ready),</a>
+<a name="558"><span class="lineNum">     558 </span>            :     .io_r_req_valid           (_s1_bank_req_1h_T &amp; s0_bank_req_1h_0),</a>
+<a name="559"><span class="lineNum">     559 </span>            :     .io_r_req_bits_setIdx     (s0_idx[10:2]),</a>
+<a name="560"><span class="lineNum">     560 </span>            :     .io_r_resp_data_0_valid   (_table_banks_0_io_r_resp_data_0_valid),</a>
+<a name="561"><span class="lineNum">     561 </span>            :     .io_r_resp_data_0_tag     (_table_banks_0_io_r_resp_data_0_tag),</a>
+<a name="562"><span class="lineNum">     562 </span>            :     .io_r_resp_data_0_ctr     (_table_banks_0_io_r_resp_data_0_ctr),</a>
+<a name="563"><span class="lineNum">     563 </span>            :     .io_r_resp_data_1_valid   (_table_banks_0_io_r_resp_data_1_valid),</a>
+<a name="564"><span class="lineNum">     564 </span>            :     .io_r_resp_data_1_tag     (_table_banks_0_io_r_resp_data_1_tag),</a>
+<a name="565"><span class="lineNum">     565 </span>            :     .io_r_resp_data_1_ctr     (_table_banks_0_io_r_resp_data_1_ctr),</a>
+<a name="566"><span class="lineNum">     566 </span>            :     .io_w_req_valid           (_s1_bank_has_write_on_this_req_WIRE_0),</a>
+<a name="567"><span class="lineNum">     567 </span>            :     .io_w_req_bits_setIdx     (update_idx[10:2]),</a>
+<a name="568"><span class="lineNum">     568 </span>            :     .io_w_req_bits_data_0_tag (update_tag),</a>
+<a name="569"><span class="lineNum">     569 </span>            :     .io_w_req_bits_data_0_ctr (per_bank_update_wdata_0_0_ctr),</a>
+<a name="570"><span class="lineNum">     570 </span>            :     .io_w_req_bits_data_1_tag (update_tag),</a>
+<a name="571"><span class="lineNum">     571 </span>            :     .io_w_req_bits_data_1_ctr (per_bank_update_wdata_0_1_ctr),</a>
+<a name="572"><span class="lineNum">     572 </span>            :     .io_w_req_bits_waymask    (per_bank_update_way_mask_0)</a>
+<a name="573"><span class="lineNum">     573 </span>            :   );</a>
+<a name="574"><span class="lineNum">     574 </span>            :   FoldedSRAMTemplate_1 table_banks_1 (</a>
+<a name="575"><span class="lineNum">     575 </span>            :     .clock                    (clock),</a>
+<a name="576"><span class="lineNum">     576 </span>            :     .reset                    (reset),</a>
+<a name="577"><span class="lineNum">     577 </span>            :     .io_r_req_ready           (_table_banks_1_io_r_req_ready),</a>
+<a name="578"><span class="lineNum">     578 </span>            :     .io_r_req_valid           (_s1_bank_req_1h_T &amp; s0_bank_req_1h_1),</a>
+<a name="579"><span class="lineNum">     579 </span>            :     .io_r_req_bits_setIdx     (s0_idx[10:2]),</a>
+<a name="580"><span class="lineNum">     580 </span>            :     .io_r_resp_data_0_valid   (_table_banks_1_io_r_resp_data_0_valid),</a>
+<a name="581"><span class="lineNum">     581 </span>            :     .io_r_resp_data_0_tag     (_table_banks_1_io_r_resp_data_0_tag),</a>
+<a name="582"><span class="lineNum">     582 </span>            :     .io_r_resp_data_0_ctr     (_table_banks_1_io_r_resp_data_0_ctr),</a>
+<a name="583"><span class="lineNum">     583 </span>            :     .io_r_resp_data_1_valid   (_table_banks_1_io_r_resp_data_1_valid),</a>
+<a name="584"><span class="lineNum">     584 </span>            :     .io_r_resp_data_1_tag     (_table_banks_1_io_r_resp_data_1_tag),</a>
+<a name="585"><span class="lineNum">     585 </span>            :     .io_r_resp_data_1_ctr     (_table_banks_1_io_r_resp_data_1_ctr),</a>
+<a name="586"><span class="lineNum">     586 </span>            :     .io_w_req_valid           (_s1_bank_has_write_on_this_req_WIRE_1),</a>
+<a name="587"><span class="lineNum">     587 </span>            :     .io_w_req_bits_setIdx     (update_idx[10:2]),</a>
+<a name="588"><span class="lineNum">     588 </span>            :     .io_w_req_bits_data_0_tag (update_tag),</a>
+<a name="589"><span class="lineNum">     589 </span>            :     .io_w_req_bits_data_0_ctr (per_bank_update_wdata_1_0_ctr),</a>
+<a name="590"><span class="lineNum">     590 </span>            :     .io_w_req_bits_data_1_tag (update_tag),</a>
+<a name="591"><span class="lineNum">     591 </span>            :     .io_w_req_bits_data_1_ctr (per_bank_update_wdata_1_1_ctr),</a>
+<a name="592"><span class="lineNum">     592 </span>            :     .io_w_req_bits_waymask    (per_bank_update_way_mask_1)</a>
+<a name="593"><span class="lineNum">     593 </span>            :   );</a>
+<a name="594"><span class="lineNum">     594 </span>            :   FoldedSRAMTemplate_1 table_banks_2 (</a>
+<a name="595"><span class="lineNum">     595 </span>            :     .clock                    (clock),</a>
+<a name="596"><span class="lineNum">     596 </span>            :     .reset                    (reset),</a>
+<a name="597"><span class="lineNum">     597 </span>            :     .io_r_req_ready           (_table_banks_2_io_r_req_ready),</a>
+<a name="598"><span class="lineNum">     598 </span>            :     .io_r_req_valid           (_s1_bank_req_1h_T &amp; s0_bank_req_1h_2),</a>
+<a name="599"><span class="lineNum">     599 </span>            :     .io_r_req_bits_setIdx     (s0_idx[10:2]),</a>
+<a name="600"><span class="lineNum">     600 </span>            :     .io_r_resp_data_0_valid   (_table_banks_2_io_r_resp_data_0_valid),</a>
+<a name="601"><span class="lineNum">     601 </span>            :     .io_r_resp_data_0_tag     (_table_banks_2_io_r_resp_data_0_tag),</a>
+<a name="602"><span class="lineNum">     602 </span>            :     .io_r_resp_data_0_ctr     (_table_banks_2_io_r_resp_data_0_ctr),</a>
+<a name="603"><span class="lineNum">     603 </span>            :     .io_r_resp_data_1_valid   (_table_banks_2_io_r_resp_data_1_valid),</a>
+<a name="604"><span class="lineNum">     604 </span>            :     .io_r_resp_data_1_tag     (_table_banks_2_io_r_resp_data_1_tag),</a>
+<a name="605"><span class="lineNum">     605 </span>            :     .io_r_resp_data_1_ctr     (_table_banks_2_io_r_resp_data_1_ctr),</a>
+<a name="606"><span class="lineNum">     606 </span>            :     .io_w_req_valid           (_s1_bank_has_write_on_this_req_WIRE_2),</a>
+<a name="607"><span class="lineNum">     607 </span>            :     .io_w_req_bits_setIdx     (update_idx[10:2]),</a>
+<a name="608"><span class="lineNum">     608 </span>            :     .io_w_req_bits_data_0_tag (update_tag),</a>
+<a name="609"><span class="lineNum">     609 </span>            :     .io_w_req_bits_data_0_ctr (per_bank_update_wdata_2_0_ctr),</a>
+<a name="610"><span class="lineNum">     610 </span>            :     .io_w_req_bits_data_1_tag (update_tag),</a>
+<a name="611"><span class="lineNum">     611 </span>            :     .io_w_req_bits_data_1_ctr (per_bank_update_wdata_2_1_ctr),</a>
+<a name="612"><span class="lineNum">     612 </span>            :     .io_w_req_bits_waymask    (per_bank_update_way_mask_2)</a>
+<a name="613"><span class="lineNum">     613 </span>            :   );</a>
+<a name="614"><span class="lineNum">     614 </span>            :   FoldedSRAMTemplate_1 table_banks_3 (</a>
+<a name="615"><span class="lineNum">     615 </span>            :     .clock                    (clock),</a>
+<a name="616"><span class="lineNum">     616 </span>            :     .reset                    (reset),</a>
+<a name="617"><span class="lineNum">     617 </span>            :     .io_r_req_ready           (_table_banks_3_io_r_req_ready),</a>
+<a name="618"><span class="lineNum">     618 </span>            :     .io_r_req_valid           (_s1_bank_req_1h_T &amp; (&amp;(s0_idx[1:0]))),</a>
+<a name="619"><span class="lineNum">     619 </span>            :     .io_r_req_bits_setIdx     (s0_idx[10:2]),</a>
+<a name="620"><span class="lineNum">     620 </span>            :     .io_r_resp_data_0_valid   (_table_banks_3_io_r_resp_data_0_valid),</a>
+<a name="621"><span class="lineNum">     621 </span>            :     .io_r_resp_data_0_tag     (_table_banks_3_io_r_resp_data_0_tag),</a>
+<a name="622"><span class="lineNum">     622 </span>            :     .io_r_resp_data_0_ctr     (_table_banks_3_io_r_resp_data_0_ctr),</a>
+<a name="623"><span class="lineNum">     623 </span>            :     .io_r_resp_data_1_valid   (_table_banks_3_io_r_resp_data_1_valid),</a>
+<a name="624"><span class="lineNum">     624 </span>            :     .io_r_resp_data_1_tag     (_table_banks_3_io_r_resp_data_1_tag),</a>
+<a name="625"><span class="lineNum">     625 </span>            :     .io_r_resp_data_1_ctr     (_table_banks_3_io_r_resp_data_1_ctr),</a>
+<a name="626"><span class="lineNum">     626 </span>            :     .io_w_req_valid           (_s1_bank_has_write_on_this_req_WIRE_3),</a>
+<a name="627"><span class="lineNum">     627 </span>            :     .io_w_req_bits_setIdx     (update_idx[10:2]),</a>
+<a name="628"><span class="lineNum">     628 </span>            :     .io_w_req_bits_data_0_tag (update_tag),</a>
+<a name="629"><span class="lineNum">     629 </span>            :     .io_w_req_bits_data_0_ctr (per_bank_update_wdata_3_0_ctr),</a>
+<a name="630"><span class="lineNum">     630 </span>            :     .io_w_req_bits_data_1_tag (update_tag),</a>
+<a name="631"><span class="lineNum">     631 </span>            :     .io_w_req_bits_data_1_ctr (per_bank_update_wdata_3_1_ctr),</a>
+<a name="632"><span class="lineNum">     632 </span>            :     .io_w_req_bits_waymask    (per_bank_update_way_mask_3)</a>
+<a name="633"><span class="lineNum">     633 </span>            :   );</a>
+<a name="634"><span class="lineNum">     634 </span>            :   WrBypass bank_wrbypasses_0_0 (</a>
+<a name="635"><span class="lineNum">     635 </span>            :     .clock               (clock),</a>
+<a name="636"><span class="lineNum">     636 </span>            :     .reset               (reset),</a>
+<a name="637"><span class="lineNum">     637 </span>            :     .io_wen              (io_update_mask_0 &amp; update_req_bank_1h_0),</a>
+<a name="638"><span class="lineNum">     638 </span>            :     .io_write_idx        (update_idx[10:2]),</a>
+<a name="639"><span class="lineNum">     639 </span>            :     .io_write_data_0</a>
+<a name="640"><span class="lineNum">     640 </span>            :       ((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_0_0_ctr)</a>
+<a name="641"><span class="lineNum">     641 </span>            :        | (io_update_pc[1] ? per_bank_update_wdata_0_1_ctr : 3'h0)),</a>
+<a name="642"><span class="lineNum">     642 </span>            :     .io_hit              (_bank_wrbypasses_0_0_io_hit),</a>
+<a name="643"><span class="lineNum">     643 </span>            :     .io_hit_data_0_valid (_bank_wrbypasses_0_0_io_hit_data_0_valid),</a>
+<a name="644"><span class="lineNum">     644 </span>            :     .io_hit_data_0_bits  (_bank_wrbypasses_0_0_io_hit_data_0_bits)</a>
+<a name="645"><span class="lineNum">     645 </span>            :   );</a>
+<a name="646"><span class="lineNum">     646 </span>            :   WrBypass bank_wrbypasses_0_1 (</a>
+<a name="647"><span class="lineNum">     647 </span>            :     .clock               (clock),</a>
+<a name="648"><span class="lineNum">     648 </span>            :     .reset               (reset),</a>
+<a name="649"><span class="lineNum">     649 </span>            :     .io_wen              (io_update_mask_1 &amp; update_req_bank_1h_0),</a>
+<a name="650"><span class="lineNum">     650 </span>            :     .io_write_idx        (update_idx[10:2]),</a>
+<a name="651"><span class="lineNum">     651 </span>            :     .io_write_data_0</a>
+<a name="652"><span class="lineNum">     652 </span>            :       ((io_update_pc[1] ? per_bank_update_wdata_0_0_ctr : 3'h0)</a>
+<a name="653"><span class="lineNum">     653 </span>            :        | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_0_1_ctr)),</a>
+<a name="654"><span class="lineNum">     654 </span>            :     .io_hit              (_bank_wrbypasses_0_1_io_hit),</a>
+<a name="655"><span class="lineNum">     655 </span>            :     .io_hit_data_0_valid (_bank_wrbypasses_0_1_io_hit_data_0_valid),</a>
+<a name="656"><span class="lineNum">     656 </span>            :     .io_hit_data_0_bits  (_bank_wrbypasses_0_1_io_hit_data_0_bits)</a>
+<a name="657"><span class="lineNum">     657 </span>            :   );</a>
+<a name="658"><span class="lineNum">     658 </span>            :   WrBypass bank_wrbypasses_1_0 (</a>
+<a name="659"><span class="lineNum">     659 </span>            :     .clock               (clock),</a>
+<a name="660"><span class="lineNum">     660 </span>            :     .reset               (reset),</a>
+<a name="661"><span class="lineNum">     661 </span>            :     .io_wen              (io_update_mask_0 &amp; update_req_bank_1h_1),</a>
+<a name="662"><span class="lineNum">     662 </span>            :     .io_write_idx        (update_idx[10:2]),</a>
+<a name="663"><span class="lineNum">     663 </span>            :     .io_write_data_0</a>
+<a name="664"><span class="lineNum">     664 </span>            :       ((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_1_0_ctr)</a>
+<a name="665"><span class="lineNum">     665 </span>            :        | (io_update_pc[1] ? per_bank_update_wdata_1_1_ctr : 3'h0)),</a>
+<a name="666"><span class="lineNum">     666 </span>            :     .io_hit              (_bank_wrbypasses_1_0_io_hit),</a>
+<a name="667"><span class="lineNum">     667 </span>            :     .io_hit_data_0_valid (_bank_wrbypasses_1_0_io_hit_data_0_valid),</a>
+<a name="668"><span class="lineNum">     668 </span>            :     .io_hit_data_0_bits  (_bank_wrbypasses_1_0_io_hit_data_0_bits)</a>
+<a name="669"><span class="lineNum">     669 </span>            :   );</a>
+<a name="670"><span class="lineNum">     670 </span>            :   WrBypass bank_wrbypasses_1_1 (</a>
+<a name="671"><span class="lineNum">     671 </span>            :     .clock               (clock),</a>
+<a name="672"><span class="lineNum">     672 </span>            :     .reset               (reset),</a>
+<a name="673"><span class="lineNum">     673 </span>            :     .io_wen              (io_update_mask_1 &amp; update_req_bank_1h_1),</a>
+<a name="674"><span class="lineNum">     674 </span>            :     .io_write_idx        (update_idx[10:2]),</a>
+<a name="675"><span class="lineNum">     675 </span>            :     .io_write_data_0</a>
+<a name="676"><span class="lineNum">     676 </span>            :       ((io_update_pc[1] ? per_bank_update_wdata_1_0_ctr : 3'h0)</a>
+<a name="677"><span class="lineNum">     677 </span>            :        | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_1_1_ctr)),</a>
+<a name="678"><span class="lineNum">     678 </span>            :     .io_hit              (_bank_wrbypasses_1_1_io_hit),</a>
+<a name="679"><span class="lineNum">     679 </span>            :     .io_hit_data_0_valid (_bank_wrbypasses_1_1_io_hit_data_0_valid),</a>
+<a name="680"><span class="lineNum">     680 </span>            :     .io_hit_data_0_bits  (_bank_wrbypasses_1_1_io_hit_data_0_bits)</a>
+<a name="681"><span class="lineNum">     681 </span>            :   );</a>
+<a name="682"><span class="lineNum">     682 </span>            :   WrBypass bank_wrbypasses_2_0 (</a>
+<a name="683"><span class="lineNum">     683 </span>            :     .clock               (clock),</a>
+<a name="684"><span class="lineNum">     684 </span>            :     .reset               (reset),</a>
+<a name="685"><span class="lineNum">     685 </span>            :     .io_wen              (io_update_mask_0 &amp; update_req_bank_1h_2),</a>
+<a name="686"><span class="lineNum">     686 </span>            :     .io_write_idx        (update_idx[10:2]),</a>
+<a name="687"><span class="lineNum">     687 </span>            :     .io_write_data_0</a>
+<a name="688"><span class="lineNum">     688 </span>            :       ((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_2_0_ctr)</a>
+<a name="689"><span class="lineNum">     689 </span>            :        | (io_update_pc[1] ? per_bank_update_wdata_2_1_ctr : 3'h0)),</a>
+<a name="690"><span class="lineNum">     690 </span>            :     .io_hit              (_bank_wrbypasses_2_0_io_hit),</a>
+<a name="691"><span class="lineNum">     691 </span>            :     .io_hit_data_0_valid (_bank_wrbypasses_2_0_io_hit_data_0_valid),</a>
+<a name="692"><span class="lineNum">     692 </span>            :     .io_hit_data_0_bits  (_bank_wrbypasses_2_0_io_hit_data_0_bits)</a>
+<a name="693"><span class="lineNum">     693 </span>            :   );</a>
+<a name="694"><span class="lineNum">     694 </span>            :   WrBypass bank_wrbypasses_2_1 (</a>
+<a name="695"><span class="lineNum">     695 </span>            :     .clock               (clock),</a>
+<a name="696"><span class="lineNum">     696 </span>            :     .reset               (reset),</a>
+<a name="697"><span class="lineNum">     697 </span>            :     .io_wen              (io_update_mask_1 &amp; update_req_bank_1h_2),</a>
+<a name="698"><span class="lineNum">     698 </span>            :     .io_write_idx        (update_idx[10:2]),</a>
+<a name="699"><span class="lineNum">     699 </span>            :     .io_write_data_0</a>
+<a name="700"><span class="lineNum">     700 </span>            :       ((io_update_pc[1] ? per_bank_update_wdata_2_0_ctr : 3'h0)</a>
+<a name="701"><span class="lineNum">     701 </span>            :        | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_2_1_ctr)),</a>
+<a name="702"><span class="lineNum">     702 </span>            :     .io_hit              (_bank_wrbypasses_2_1_io_hit),</a>
+<a name="703"><span class="lineNum">     703 </span>            :     .io_hit_data_0_valid (_bank_wrbypasses_2_1_io_hit_data_0_valid),</a>
+<a name="704"><span class="lineNum">     704 </span>            :     .io_hit_data_0_bits  (_bank_wrbypasses_2_1_io_hit_data_0_bits)</a>
+<a name="705"><span class="lineNum">     705 </span>            :   );</a>
+<a name="706"><span class="lineNum">     706 </span>            :   WrBypass bank_wrbypasses_3_0 (</a>
+<a name="707"><span class="lineNum">     707 </span>            :     .clock               (clock),</a>
+<a name="708"><span class="lineNum">     708 </span>            :     .reset               (reset),</a>
+<a name="709"><span class="lineNum">     709 </span>            :     .io_wen              (io_update_mask_0 &amp; (&amp;(update_idx[1:0]))),</a>
+<a name="710"><span class="lineNum">     710 </span>            :     .io_write_idx        (update_idx[10:2]),</a>
+<a name="711"><span class="lineNum">     711 </span>            :     .io_write_data_0</a>
+<a name="712"><span class="lineNum">     712 </span>            :       ((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_3_0_ctr)</a>
+<a name="713"><span class="lineNum">     713 </span>            :        | (io_update_pc[1] ? per_bank_update_wdata_3_1_ctr : 3'h0)),</a>
+<a name="714"><span class="lineNum">     714 </span>            :     .io_hit              (_bank_wrbypasses_3_0_io_hit),</a>
+<a name="715"><span class="lineNum">     715 </span>            :     .io_hit_data_0_valid (_bank_wrbypasses_3_0_io_hit_data_0_valid),</a>
+<a name="716"><span class="lineNum">     716 </span>            :     .io_hit_data_0_bits  (_bank_wrbypasses_3_0_io_hit_data_0_bits)</a>
+<a name="717"><span class="lineNum">     717 </span>            :   );</a>
+<a name="718"><span class="lineNum">     718 </span>            :   WrBypass bank_wrbypasses_3_1 (</a>
+<a name="719"><span class="lineNum">     719 </span>            :     .clock               (clock),</a>
+<a name="720"><span class="lineNum">     720 </span>            :     .reset               (reset),</a>
+<a name="721"><span class="lineNum">     721 </span>            :     .io_wen              (io_update_mask_1 &amp; (&amp;(update_idx[1:0]))),</a>
+<a name="722"><span class="lineNum">     722 </span>            :     .io_write_idx        (update_idx[10:2]),</a>
+<a name="723"><span class="lineNum">     723 </span>            :     .io_write_data_0</a>
+<a name="724"><span class="lineNum">     724 </span>            :       ((io_update_pc[1] ? per_bank_update_wdata_3_0_ctr : 3'h0)</a>
+<a name="725"><span class="lineNum">     725 </span>            :        | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_3_1_ctr)),</a>
+<a name="726"><span class="lineNum">     726 </span>            :     .io_hit              (_bank_wrbypasses_3_1_io_hit),</a>
+<a name="727"><span class="lineNum">     727 </span>            :     .io_hit_data_0_valid (_bank_wrbypasses_3_1_io_hit_data_0_valid),</a>
+<a name="728"><span class="lineNum">     728 </span>            :     .io_hit_data_0_bits  (_bank_wrbypasses_3_1_io_hit_data_0_bits)</a>
+<a name="729"><span class="lineNum">     729 </span>            :   );</a>
+<a name="730"><span class="lineNum">     730 </span>            :   assign io_req_ready = ~powerOnResetState;</a>
+<a name="731"><span class="lineNum">     731 </span>            :   assign io_resps_0_valid =</a>
+<a name="732"><span class="lineNum">     732 </span>            :     ~(s1_unhashed_idx[0]) &amp; _hit_selected_T_6 | s1_unhashed_idx[0] &amp; _hit_selected_T_13;</a>
+<a name="733"><span class="lineNum">     733 </span>            :   assign io_resps_0_bits_ctr =</a>
+<a name="734"><span class="lineNum">     734 </span>            :     (s1_unhashed_idx[0] ? 3'h0 : _resp_selected_T_6)</a>
+<a name="735"><span class="lineNum">     735 </span>            :     | (s1_unhashed_idx[0] ? _resp_selected_T_27 : 3'h0);</a>
+<a name="736"><span class="lineNum">     736 </span>            :   assign io_resps_0_bits_u =</a>
+<a name="737"><span class="lineNum">     737 </span>            :     ~(s1_unhashed_idx[0]) &amp; _us_io_r_resp_data_0 | s1_unhashed_idx[0]</a>
+<a name="738"><span class="lineNum">     738 </span>            :     &amp; _us_io_r_resp_data_1;</a>
+<a name="739"><span class="lineNum">     739 </span>            :   assign io_resps_0_bits_unconf =</a>
+<a name="740"><span class="lineNum">     740 </span>            :     ~(s1_unhashed_idx[0]) &amp; _unconf_selected_T_6 | s1_unhashed_idx[0]</a>
+<a name="741"><span class="lineNum">     741 </span>            :     &amp; _unconf_selected_T_13;</a>
+<a name="742"><span class="lineNum">     742 </span>            :   assign io_resps_1_valid =</a>
+<a name="743"><span class="lineNum">     743 </span>            :     s1_unhashed_idx[0] &amp; _hit_selected_T_6 | ~(s1_unhashed_idx[0]) &amp; _hit_selected_T_13;</a>
+<a name="744"><span class="lineNum">     744 </span>            :   assign io_resps_1_bits_ctr =</a>
+<a name="745"><span class="lineNum">     745 </span>            :     (s1_unhashed_idx[0] ? _resp_selected_T_6 : 3'h0)</a>
+<a name="746"><span class="lineNum">     746 </span>            :     | (s1_unhashed_idx[0] ? 3'h0 : _resp_selected_T_27);</a>
+<a name="747"><span class="lineNum">     747 </span>            :   assign io_resps_1_bits_u =</a>
+<a name="748"><span class="lineNum">     748 </span>            :     s1_unhashed_idx[0] &amp; _us_io_r_resp_data_0 | ~(s1_unhashed_idx[0])</a>
+<a name="749"><span class="lineNum">     749 </span>            :     &amp; _us_io_r_resp_data_1;</a>
+<a name="750"><span class="lineNum">     750 </span>            :   assign io_resps_1_bits_unconf =</a>
+<a name="751"><span class="lineNum">     751 </span>            :     s1_unhashed_idx[0] &amp; _unconf_selected_T_6 | ~(s1_unhashed_idx[0])</a>
+<a name="752"><span class="lineNum">     752 </span>            :     &amp; _unconf_selected_T_13;</a>
+<a name="753"><span class="lineNum">     753 </span>            : endmodule</a>
+<a name="754"><span class="lineNum">     754 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/TageTable_2.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/TageTable_2.sv.func-sort-c.html
new file mode 100644
index 0000000..5f817cb
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/TageTable_2.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/TageTable_2.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - TageTable_2.sv<span style="font-size: 80%;"> (<a href="TageTable_2.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">107</td>
+            <td class="headerCovTableEntry">107</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="TageTable_2.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/TageTable_2.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/TageTable_2.sv.func.html
new file mode 100644
index 0000000..10c1c60
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/TageTable_2.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/TageTable_2.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - TageTable_2.sv<span style="font-size: 80%;"> (<a href="TageTable_2.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">107</td>
+            <td class="headerCovTableEntry">107</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="TageTable_2.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/TageTable_2.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/TageTable_2.sv.gcov.html
new file mode 100644
index 0000000..90b4703
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/TageTable_2.sv.gcov.html
@@ -0,0 +1,830 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/TageTable_2.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - TageTable_2.sv<span style="font-size: 80%;"> (source / <a href="TageTable_2.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">107</td>
+            <td class="headerCovTableEntry">107</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : module TageTable_2(</a>
+<a name="59"><span class="lineNum">      59 </span><span class="lineCov">     127786 :   input         clock,</span></a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">         62 :   input         reset,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">         54 :   output        io_req_ready,</span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">         76 :   input         io_req_valid,</span></a>
+<a name="63"><span class="lineNum">      63 </span><span class="lineCov">      10224 :   input  [40:0] io_req_bits_pc,</span></a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">       1182 :   input  [10:0] io_req_bits_folded_hist_hist_17_folded_hist,</span></a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">        844 :   input  [6:0]  io_req_bits_folded_hist_hist_9_folded_hist,</span></a>
+<a name="66"><span class="lineNum">      66 </span><span class="lineCov">        263 :   input  [7:0]  io_req_bits_folded_hist_hist_3_folded_hist,</span></a>
+<a name="67"><span class="lineNum">      67 </span><span class="lineCov">         17 :   output        io_resps_0_valid,</span></a>
+<a name="68"><span class="lineNum">      68 </span><span class="lineCov">         96 :   output [2:0]  io_resps_0_bits_ctr,</span></a>
+<a name="69"><span class="lineNum">      69 </span><span class="lineCov">         32 :   output        io_resps_0_bits_u,</span></a>
+<a name="70"><span class="lineNum">      70 </span><span class="lineCov">         30 :   output        io_resps_0_bits_unconf,</span></a>
+<a name="71"><span class="lineNum">      71 </span><span class="lineCov">         15 :   output        io_resps_1_valid,</span></a>
+<a name="72"><span class="lineNum">      72 </span><span class="lineCov">        103 :   output [2:0]  io_resps_1_bits_ctr,</span></a>
+<a name="73"><span class="lineNum">      73 </span><span class="lineCov">         33 :   output        io_resps_1_bits_u,</span></a>
+<a name="74"><span class="lineNum">      74 </span><span class="lineCov">         24 :   output        io_resps_1_bits_unconf,</span></a>
+<a name="75"><span class="lineNum">      75 </span><span class="lineCov">        623 :   input  [40:0] io_update_pc,</span></a>
+<a name="76"><span class="lineNum">      76 </span><span class="lineCov">        176 :   input  [10:0] io_update_folded_hist_hist_17_folded_hist,</span></a>
+<a name="77"><span class="lineNum">      77 </span><span class="lineCov">         99 :   input  [6:0]  io_update_folded_hist_hist_9_folded_hist,</span></a>
+<a name="78"><span class="lineNum">      78 </span><span class="lineCov">        134 :   input  [7:0]  io_update_folded_hist_hist_3_folded_hist,</span></a>
+<a name="79"><span class="lineNum">      79 </span><span class="lineCov">         29 :   input         io_update_mask_0,</span></a>
+<a name="80"><span class="lineNum">      80 </span><span class="lineCov">         30 :   input         io_update_mask_1,</span></a>
+<a name="81"><span class="lineNum">      81 </span><span class="lineCov">         16 :   input         io_update_takens_0,</span></a>
+<a name="82"><span class="lineNum">      82 </span><span class="lineCov">         15 :   input         io_update_takens_1,</span></a>
+<a name="83"><span class="lineNum">      83 </span><span class="lineCov">         10 :   input         io_update_alloc_0,</span></a>
+<a name="84"><span class="lineNum">      84 </span><span class="lineCov">         20 :   input         io_update_alloc_1,</span></a>
+<a name="85"><span class="lineNum">      85 </span><span class="lineCov">         45 :   input  [2:0]  io_update_oldCtrs_0,</span></a>
+<a name="86"><span class="lineNum">      86 </span><span class="lineCov">         45 :   input  [2:0]  io_update_oldCtrs_1,</span></a>
+<a name="87"><span class="lineNum">      87 </span><span class="lineCov">         19 :   input         io_update_uMask_0,</span></a>
+<a name="88"><span class="lineNum">      88 </span><span class="lineCov">         12 :   input         io_update_uMask_1,</span></a>
+<a name="89"><span class="lineNum">      89 </span><span class="lineCov">         18 :   input         io_update_us_0,</span></a>
+<a name="90"><span class="lineNum">      90 </span><span class="lineCov">         21 :   input         io_update_us_1,</span></a>
+<a name="91"><span class="lineNum">      91 </span><span class="lineCov">         26 :   input         io_update_reset_u_0,</span></a>
+<a name="92"><span class="lineNum">      92 </span><span class="lineCov">         33 :   input         io_update_reset_u_1</span></a>
+<a name="93"><span class="lineNum">      93 </span>            : );</a>
+<a name="94"><span class="lineNum">      94 </span>            : </a>
+<a name="95"><span class="lineNum">      95 </span><span class="lineCov">         18 :   wire        per_bank_not_silent_update_3_1;</span></a>
+<a name="96"><span class="lineNum">      96 </span><span class="lineCov">         16 :   wire        per_bank_not_silent_update_3_0;</span></a>
+<a name="97"><span class="lineNum">      97 </span><span class="lineCov">         15 :   wire        per_bank_not_silent_update_2_1;</span></a>
+<a name="98"><span class="lineNum">      98 </span><span class="lineCov">          9 :   wire        per_bank_not_silent_update_2_0;</span></a>
+<a name="99"><span class="lineNum">      99 </span><span class="lineCov">         12 :   wire        per_bank_not_silent_update_1_1;</span></a>
+<a name="100"><span class="lineNum">     100 </span><span class="lineCov">         17 :   wire        per_bank_not_silent_update_1_0;</span></a>
+<a name="101"><span class="lineNum">     101 </span><span class="lineCov">         13 :   wire        per_bank_not_silent_update_0_1;</span></a>
+<a name="102"><span class="lineNum">     102 </span><span class="lineCov">          8 :   wire        per_bank_not_silent_update_0_0;</span></a>
+<a name="103"><span class="lineNum">     103 </span><span class="lineCov">         54 :   reg         powerOnResetState;</span></a>
+<a name="104"><span class="lineNum">     104 </span>            :   wire        _resp_invalid_by_write_T_6;</a>
+<a name="105"><span class="lineNum">     105 </span>            :   wire        _bank_wrbypasses_3_1_io_hit;</a>
+<a name="106"><span class="lineNum">     106 </span>            :   wire        _bank_wrbypasses_3_1_io_hit_data_0_valid;</a>
+<a name="107"><span class="lineNum">     107 </span>            :   wire [2:0]  _bank_wrbypasses_3_1_io_hit_data_0_bits;</a>
+<a name="108"><span class="lineNum">     108 </span>            :   wire        _bank_wrbypasses_3_0_io_hit;</a>
+<a name="109"><span class="lineNum">     109 </span>            :   wire        _bank_wrbypasses_3_0_io_hit_data_0_valid;</a>
+<a name="110"><span class="lineNum">     110 </span>            :   wire [2:0]  _bank_wrbypasses_3_0_io_hit_data_0_bits;</a>
+<a name="111"><span class="lineNum">     111 </span>            :   wire        _bank_wrbypasses_2_1_io_hit;</a>
+<a name="112"><span class="lineNum">     112 </span>            :   wire        _bank_wrbypasses_2_1_io_hit_data_0_valid;</a>
+<a name="113"><span class="lineNum">     113 </span>            :   wire [2:0]  _bank_wrbypasses_2_1_io_hit_data_0_bits;</a>
+<a name="114"><span class="lineNum">     114 </span>            :   wire        _bank_wrbypasses_2_0_io_hit;</a>
+<a name="115"><span class="lineNum">     115 </span>            :   wire        _bank_wrbypasses_2_0_io_hit_data_0_valid;</a>
+<a name="116"><span class="lineNum">     116 </span>            :   wire [2:0]  _bank_wrbypasses_2_0_io_hit_data_0_bits;</a>
+<a name="117"><span class="lineNum">     117 </span>            :   wire        _bank_wrbypasses_1_1_io_hit;</a>
+<a name="118"><span class="lineNum">     118 </span>            :   wire        _bank_wrbypasses_1_1_io_hit_data_0_valid;</a>
+<a name="119"><span class="lineNum">     119 </span>            :   wire [2:0]  _bank_wrbypasses_1_1_io_hit_data_0_bits;</a>
+<a name="120"><span class="lineNum">     120 </span>            :   wire        _bank_wrbypasses_1_0_io_hit;</a>
+<a name="121"><span class="lineNum">     121 </span>            :   wire        _bank_wrbypasses_1_0_io_hit_data_0_valid;</a>
+<a name="122"><span class="lineNum">     122 </span>            :   wire [2:0]  _bank_wrbypasses_1_0_io_hit_data_0_bits;</a>
+<a name="123"><span class="lineNum">     123 </span>            :   wire        _bank_wrbypasses_0_1_io_hit;</a>
+<a name="124"><span class="lineNum">     124 </span>            :   wire        _bank_wrbypasses_0_1_io_hit_data_0_valid;</a>
+<a name="125"><span class="lineNum">     125 </span>            :   wire [2:0]  _bank_wrbypasses_0_1_io_hit_data_0_bits;</a>
+<a name="126"><span class="lineNum">     126 </span>            :   wire        _bank_wrbypasses_0_0_io_hit;</a>
+<a name="127"><span class="lineNum">     127 </span>            :   wire        _bank_wrbypasses_0_0_io_hit_data_0_valid;</a>
+<a name="128"><span class="lineNum">     128 </span>            :   wire [2:0]  _bank_wrbypasses_0_0_io_hit_data_0_bits;</a>
+<a name="129"><span class="lineNum">     129 </span>            :   wire        _table_banks_3_io_r_req_ready;</a>
+<a name="130"><span class="lineNum">     130 </span>            :   wire        _table_banks_3_io_r_resp_data_0_valid;</a>
+<a name="131"><span class="lineNum">     131 </span>            :   wire [7:0]  _table_banks_3_io_r_resp_data_0_tag;</a>
+<a name="132"><span class="lineNum">     132 </span>            :   wire [2:0]  _table_banks_3_io_r_resp_data_0_ctr;</a>
+<a name="133"><span class="lineNum">     133 </span>            :   wire        _table_banks_3_io_r_resp_data_1_valid;</a>
+<a name="134"><span class="lineNum">     134 </span>            :   wire [7:0]  _table_banks_3_io_r_resp_data_1_tag;</a>
+<a name="135"><span class="lineNum">     135 </span>            :   wire [2:0]  _table_banks_3_io_r_resp_data_1_ctr;</a>
+<a name="136"><span class="lineNum">     136 </span>            :   wire        _table_banks_2_io_r_req_ready;</a>
+<a name="137"><span class="lineNum">     137 </span>            :   wire        _table_banks_2_io_r_resp_data_0_valid;</a>
+<a name="138"><span class="lineNum">     138 </span>            :   wire [7:0]  _table_banks_2_io_r_resp_data_0_tag;</a>
+<a name="139"><span class="lineNum">     139 </span>            :   wire [2:0]  _table_banks_2_io_r_resp_data_0_ctr;</a>
+<a name="140"><span class="lineNum">     140 </span>            :   wire        _table_banks_2_io_r_resp_data_1_valid;</a>
+<a name="141"><span class="lineNum">     141 </span>            :   wire [7:0]  _table_banks_2_io_r_resp_data_1_tag;</a>
+<a name="142"><span class="lineNum">     142 </span>            :   wire [2:0]  _table_banks_2_io_r_resp_data_1_ctr;</a>
+<a name="143"><span class="lineNum">     143 </span>            :   wire        _table_banks_1_io_r_req_ready;</a>
+<a name="144"><span class="lineNum">     144 </span>            :   wire        _table_banks_1_io_r_resp_data_0_valid;</a>
+<a name="145"><span class="lineNum">     145 </span>            :   wire [7:0]  _table_banks_1_io_r_resp_data_0_tag;</a>
+<a name="146"><span class="lineNum">     146 </span>            :   wire [2:0]  _table_banks_1_io_r_resp_data_0_ctr;</a>
+<a name="147"><span class="lineNum">     147 </span>            :   wire        _table_banks_1_io_r_resp_data_1_valid;</a>
+<a name="148"><span class="lineNum">     148 </span>            :   wire [7:0]  _table_banks_1_io_r_resp_data_1_tag;</a>
+<a name="149"><span class="lineNum">     149 </span>            :   wire [2:0]  _table_banks_1_io_r_resp_data_1_ctr;</a>
+<a name="150"><span class="lineNum">     150 </span>            :   wire        _table_banks_0_io_r_req_ready;</a>
+<a name="151"><span class="lineNum">     151 </span>            :   wire        _table_banks_0_io_r_resp_data_0_valid;</a>
+<a name="152"><span class="lineNum">     152 </span>            :   wire [7:0]  _table_banks_0_io_r_resp_data_0_tag;</a>
+<a name="153"><span class="lineNum">     153 </span>            :   wire [2:0]  _table_banks_0_io_r_resp_data_0_ctr;</a>
+<a name="154"><span class="lineNum">     154 </span>            :   wire        _table_banks_0_io_r_resp_data_1_valid;</a>
+<a name="155"><span class="lineNum">     155 </span>            :   wire [7:0]  _table_banks_0_io_r_resp_data_1_tag;</a>
+<a name="156"><span class="lineNum">     156 </span>            :   wire [2:0]  _table_banks_0_io_r_resp_data_1_ctr;</a>
+<a name="157"><span class="lineNum">     157 </span>            :   wire        _us_io_r_req_ready;</a>
+<a name="158"><span class="lineNum">     158 </span>            :   wire        _us_io_r_resp_data_0;</a>
+<a name="159"><span class="lineNum">     159 </span>            :   wire        _us_io_r_resp_data_1;</a>
+<a name="160"><span class="lineNum">     160 </span>            :   wire        _us_extra_reset_T_1 = io_update_mask_0 | io_update_mask_1;</a>
+<a name="161"><span class="lineNum">     161 </span><span class="lineCov">       8862 :   wire [10:0] s0_idx = io_req_bits_pc[11:1] ^ io_req_bits_folded_hist_hist_17_folded_hist;</span></a>
+<a name="162"><span class="lineNum">     162 </span><span class="lineCov">         68 :   wire        s0_bank_req_1h_0 = s0_idx[1:0] == 2'h0;</span></a>
+<a name="163"><span class="lineNum">     163 </span><span class="lineCov">         62 :   wire        s0_bank_req_1h_1 = s0_idx[1:0] == 2'h1;</span></a>
+<a name="164"><span class="lineNum">     164 </span><span class="lineCov">         58 :   wire        s0_bank_req_1h_2 = s0_idx[1:0] == 2'h2;</span></a>
+<a name="165"><span class="lineNum">     165 </span>            :   wire        _s1_bank_req_1h_T = ~powerOnResetState &amp; io_req_valid;</a>
+<a name="166"><span class="lineNum">     166 </span><span class="lineCov">       9335 :   reg  [39:0] s1_unhashed_idx;</span></a>
+<a name="167"><span class="lineNum">     167 </span><span class="lineCov">       7999 :   reg  [7:0]  s1_tag;</span></a>
+<a name="168"><span class="lineNum">     168 </span><span class="lineCov">         36 :   reg         s1_bank_req_1h_0;</span></a>
+<a name="169"><span class="lineNum">     169 </span><span class="lineCov">         44 :   reg         s1_bank_req_1h_1;</span></a>
+<a name="170"><span class="lineNum">     170 </span><span class="lineCov">         37 :   reg         s1_bank_req_1h_2;</span></a>
+<a name="171"><span class="lineNum">     171 </span><span class="lineCov">         34 :   reg         s1_bank_req_1h_3;</span></a>
+<a name="172"><span class="lineNum">     172 </span><span class="lineCov">         29 :   reg         s1_bank_has_write_on_this_req_0;</span></a>
+<a name="173"><span class="lineNum">     173 </span><span class="lineCov">         36 :   reg         s1_bank_has_write_on_this_req_1;</span></a>
+<a name="174"><span class="lineNum">     174 </span><span class="lineCov">         25 :   reg         s1_bank_has_write_on_this_req_2;</span></a>
+<a name="175"><span class="lineNum">     175 </span><span class="lineCov">         31 :   reg         s1_bank_has_write_on_this_req_3;</span></a>
+<a name="176"><span class="lineNum">     176 </span>            :   wire [2:0]  _resp_selected_T_6 =</a>
+<a name="177"><span class="lineNum">     177 </span>            :     (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_ctr : 3'h0)</a>
+<a name="178"><span class="lineNum">     178 </span>            :     | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 3'h0)</a>
+<a name="179"><span class="lineNum">     179 </span>            :     | (s1_bank_req_1h_2 ? _table_banks_2_io_r_resp_data_0_ctr : 3'h0)</a>
+<a name="180"><span class="lineNum">     180 </span>            :     | (s1_bank_req_1h_3 ? _table_banks_3_io_r_resp_data_0_ctr : 3'h0);</a>
+<a name="181"><span class="lineNum">     181 </span>            :   wire [2:0]  _resp_selected_T_27 =</a>
+<a name="182"><span class="lineNum">     182 </span>            :     (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_1_ctr : 3'h0)</a>
+<a name="183"><span class="lineNum">     183 </span>            :     | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_1_ctr : 3'h0)</a>
+<a name="184"><span class="lineNum">     184 </span>            :     | (s1_bank_req_1h_2 ? _table_banks_2_io_r_resp_data_1_ctr : 3'h0)</a>
+<a name="185"><span class="lineNum">     185 </span>            :     | (s1_bank_req_1h_3 ? _table_banks_3_io_r_resp_data_1_ctr : 3'h0);</a>
+<a name="186"><span class="lineNum">     186 </span>            :   wire        _unconf_selected_T_6 =</a>
+<a name="187"><span class="lineNum">     187 </span>            :     s1_bank_req_1h_0</a>
+<a name="188"><span class="lineNum">     188 </span>            :     &amp; (_table_banks_0_io_r_resp_data_0_ctr == 3'h4</a>
+<a name="189"><span class="lineNum">     189 </span>            :        | _table_banks_0_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_1</a>
+<a name="190"><span class="lineNum">     190 </span>            :     &amp; (_table_banks_1_io_r_resp_data_0_ctr == 3'h4</a>
+<a name="191"><span class="lineNum">     191 </span>            :        | _table_banks_1_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_2</a>
+<a name="192"><span class="lineNum">     192 </span>            :     &amp; (_table_banks_2_io_r_resp_data_0_ctr == 3'h4</a>
+<a name="193"><span class="lineNum">     193 </span>            :        | _table_banks_2_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_3</a>
+<a name="194"><span class="lineNum">     194 </span>            :     &amp; (_table_banks_3_io_r_resp_data_0_ctr == 3'h4</a>
+<a name="195"><span class="lineNum">     195 </span>            :        | _table_banks_3_io_r_resp_data_0_ctr == 3'h3);</a>
+<a name="196"><span class="lineNum">     196 </span>            :   wire        _unconf_selected_T_13 =</a>
+<a name="197"><span class="lineNum">     197 </span>            :     s1_bank_req_1h_0</a>
+<a name="198"><span class="lineNum">     198 </span>            :     &amp; (_table_banks_0_io_r_resp_data_1_ctr == 3'h4</a>
+<a name="199"><span class="lineNum">     199 </span>            :        | _table_banks_0_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_1</a>
+<a name="200"><span class="lineNum">     200 </span>            :     &amp; (_table_banks_1_io_r_resp_data_1_ctr == 3'h4</a>
+<a name="201"><span class="lineNum">     201 </span>            :        | _table_banks_1_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_2</a>
+<a name="202"><span class="lineNum">     202 </span>            :     &amp; (_table_banks_2_io_r_resp_data_1_ctr == 3'h4</a>
+<a name="203"><span class="lineNum">     203 </span>            :        | _table_banks_2_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_3</a>
+<a name="204"><span class="lineNum">     204 </span>            :     &amp; (_table_banks_3_io_r_resp_data_1_ctr == 3'h4</a>
+<a name="205"><span class="lineNum">     205 </span>            :        | _table_banks_3_io_r_resp_data_1_ctr == 3'h3);</a>
+<a name="206"><span class="lineNum">     206 </span>            :   wire        _hit_selected_T_6 =</a>
+<a name="207"><span class="lineNum">     207 </span>            :     s1_bank_req_1h_0 &amp; _table_banks_0_io_r_resp_data_0_tag == s1_tag</a>
+<a name="208"><span class="lineNum">     208 </span>            :     &amp; _table_banks_0_io_r_resp_data_0_valid &amp; ~_resp_invalid_by_write_T_6</a>
+<a name="209"><span class="lineNum">     209 </span>            :     | s1_bank_req_1h_1 &amp; _table_banks_1_io_r_resp_data_0_tag == s1_tag</a>
+<a name="210"><span class="lineNum">     210 </span>            :     &amp; _table_banks_1_io_r_resp_data_0_valid &amp; ~_resp_invalid_by_write_T_6</a>
+<a name="211"><span class="lineNum">     211 </span>            :     | s1_bank_req_1h_2 &amp; _table_banks_2_io_r_resp_data_0_tag == s1_tag</a>
+<a name="212"><span class="lineNum">     212 </span>            :     &amp; _table_banks_2_io_r_resp_data_0_valid &amp; ~_resp_invalid_by_write_T_6</a>
+<a name="213"><span class="lineNum">     213 </span>            :     | s1_bank_req_1h_3 &amp; _table_banks_3_io_r_resp_data_0_tag == s1_tag</a>
+<a name="214"><span class="lineNum">     214 </span>            :     &amp; _table_banks_3_io_r_resp_data_0_valid &amp; ~_resp_invalid_by_write_T_6;</a>
+<a name="215"><span class="lineNum">     215 </span>            :   wire        _hit_selected_T_13 =</a>
+<a name="216"><span class="lineNum">     216 </span>            :     s1_bank_req_1h_0 &amp; _table_banks_0_io_r_resp_data_1_tag == s1_tag</a>
+<a name="217"><span class="lineNum">     217 </span>            :     &amp; _table_banks_0_io_r_resp_data_1_valid &amp; ~_resp_invalid_by_write_T_6</a>
+<a name="218"><span class="lineNum">     218 </span>            :     | s1_bank_req_1h_1 &amp; _table_banks_1_io_r_resp_data_1_tag == s1_tag</a>
+<a name="219"><span class="lineNum">     219 </span>            :     &amp; _table_banks_1_io_r_resp_data_1_valid &amp; ~_resp_invalid_by_write_T_6</a>
+<a name="220"><span class="lineNum">     220 </span>            :     | s1_bank_req_1h_2 &amp; _table_banks_2_io_r_resp_data_1_tag == s1_tag</a>
+<a name="221"><span class="lineNum">     221 </span>            :     &amp; _table_banks_2_io_r_resp_data_1_valid &amp; ~_resp_invalid_by_write_T_6</a>
+<a name="222"><span class="lineNum">     222 </span>            :     | s1_bank_req_1h_3 &amp; _table_banks_3_io_r_resp_data_1_tag == s1_tag</a>
+<a name="223"><span class="lineNum">     223 </span>            :     &amp; _table_banks_3_io_r_resp_data_1_valid &amp; ~_resp_invalid_by_write_T_6;</a>
+<a name="224"><span class="lineNum">     224 </span>            :   assign _resp_invalid_by_write_T_6 =</a>
+<a name="225"><span class="lineNum">     225 </span>            :     s1_bank_req_1h_0 &amp; s1_bank_has_write_on_this_req_0 | s1_bank_req_1h_1</a>
+<a name="226"><span class="lineNum">     226 </span>            :     &amp; s1_bank_has_write_on_this_req_1 | s1_bank_req_1h_2 &amp; s1_bank_has_write_on_this_req_2</a>
+<a name="227"><span class="lineNum">     227 </span>            :     | s1_bank_req_1h_3 &amp; s1_bank_has_write_on_this_req_3;</a>
+<a name="228"><span class="lineNum">     228 </span><span class="lineCov">        173 :   wire [10:0] update_idx = io_update_pc[11:1] ^ io_update_folded_hist_hist_17_folded_hist;</span></a>
+<a name="229"><span class="lineNum">     229 </span><span class="lineCov">        130 :   wire [7:0]  update_tag =</span></a>
+<a name="230"><span class="lineNum">     230 </span>            :     io_update_pc[8:1] ^ io_update_folded_hist_hist_3_folded_hist</a>
+<a name="231"><span class="lineNum">     231 </span>            :     ^ {io_update_folded_hist_hist_9_folded_hist, 1'h0};</a>
+<a name="232"><span class="lineNum">     232 </span><span class="lineCov">         18 :   wire        update_req_bank_1h_0 = update_idx[1:0] == 2'h0;</span></a>
+<a name="233"><span class="lineNum">     233 </span><span class="lineCov">         19 :   wire        update_req_bank_1h_1 = update_idx[1:0] == 2'h1;</span></a>
+<a name="234"><span class="lineNum">     234 </span><span class="lineCov">         17 :   wire        update_req_bank_1h_2 = update_idx[1:0] == 2'h2;</span></a>
+<a name="235"><span class="lineNum">     235 </span><span class="lineCov">         57 :   wire [1:0]  per_bank_update_way_mask_0 =</span></a>
+<a name="236"><span class="lineNum">     236 </span>            :     {(io_update_pc[1] &amp; io_update_mask_0 | ~(io_update_pc[1]) &amp; io_update_mask_1)</a>
+<a name="237"><span class="lineNum">     237 </span>            :        &amp; per_bank_not_silent_update_0_1,</a>
+<a name="238"><span class="lineNum">     238 </span>            :      (~(io_update_pc[1]) &amp; io_update_mask_0 | io_update_pc[1] &amp; io_update_mask_1)</a>
+<a name="239"><span class="lineNum">     239 </span>            :        &amp; per_bank_not_silent_update_0_0};</a>
+<a name="240"><span class="lineNum">     240 </span><span class="lineCov">         57 :   wire [1:0]  per_bank_update_way_mask_1 =</span></a>
+<a name="241"><span class="lineNum">     241 </span>            :     {(io_update_pc[1] &amp; io_update_mask_0 | ~(io_update_pc[1]) &amp; io_update_mask_1)</a>
+<a name="242"><span class="lineNum">     242 </span>            :        &amp; per_bank_not_silent_update_1_1,</a>
+<a name="243"><span class="lineNum">     243 </span>            :      (~(io_update_pc[1]) &amp; io_update_mask_0 | io_update_pc[1] &amp; io_update_mask_1)</a>
+<a name="244"><span class="lineNum">     244 </span>            :        &amp; per_bank_not_silent_update_1_0};</a>
+<a name="245"><span class="lineNum">     245 </span><span class="lineCov">         62 :   wire [1:0]  per_bank_update_way_mask_2 =</span></a>
+<a name="246"><span class="lineNum">     246 </span>            :     {(io_update_pc[1] &amp; io_update_mask_0 | ~(io_update_pc[1]) &amp; io_update_mask_1)</a>
+<a name="247"><span class="lineNum">     247 </span>            :        &amp; per_bank_not_silent_update_2_1,</a>
+<a name="248"><span class="lineNum">     248 </span>            :      (~(io_update_pc[1]) &amp; io_update_mask_0 | io_update_pc[1] &amp; io_update_mask_1)</a>
+<a name="249"><span class="lineNum">     249 </span>            :        &amp; per_bank_not_silent_update_2_0};</a>
+<a name="250"><span class="lineNum">     250 </span><span class="lineCov">         68 :   wire [1:0]  per_bank_update_way_mask_3 =</span></a>
+<a name="251"><span class="lineNum">     251 </span>            :     {(io_update_pc[1] &amp; io_update_mask_0 | ~(io_update_pc[1]) &amp; io_update_mask_1)</a>
+<a name="252"><span class="lineNum">     252 </span>            :        &amp; per_bank_not_silent_update_3_1,</a>
+<a name="253"><span class="lineNum">     253 </span>            :      (~(io_update_pc[1]) &amp; io_update_mask_0 | io_update_pc[1] &amp; io_update_mask_1)</a>
+<a name="254"><span class="lineNum">     254 </span>            :        &amp; per_bank_not_silent_update_3_0};</a>
+<a name="255"><span class="lineNum">     255 </span>            :   wire        _s1_bank_has_write_on_this_req_WIRE_0 =</a>
+<a name="256"><span class="lineNum">     256 </span>            :     (|per_bank_update_way_mask_0) &amp; update_req_bank_1h_0;</a>
+<a name="257"><span class="lineNum">     257 </span>            :   wire        _s1_bank_has_write_on_this_req_WIRE_1 =</a>
+<a name="258"><span class="lineNum">     258 </span>            :     (|per_bank_update_way_mask_1) &amp; update_req_bank_1h_1;</a>
+<a name="259"><span class="lineNum">     259 </span>            :   wire        _s1_bank_has_write_on_this_req_WIRE_2 =</a>
+<a name="260"><span class="lineNum">     260 </span>            :     (|per_bank_update_way_mask_2) &amp; update_req_bank_1h_2;</a>
+<a name="261"><span class="lineNum">     261 </span>            :   wire        _s1_bank_has_write_on_this_req_WIRE_3 =</a>
+<a name="262"><span class="lineNum">     262 </span>            :     (|per_bank_update_way_mask_3) &amp; (&amp;(update_idx[1:0]));</a>
+<a name="263"><span class="lineNum">     263 </span>            :   wire [2:0]  _wrbypass_io_T_6 =</a>
+<a name="264"><span class="lineNum">     264 </span>            :     (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_0_0_io_hit_data_0_bits)</a>
+<a name="265"><span class="lineNum">     265 </span>            :     | (io_update_pc[1] ? _bank_wrbypasses_0_1_io_hit_data_0_bits : 3'h0);</a>
+<a name="266"><span class="lineNum">     266 </span><span class="lineCov">         14 :   wire        wrbypass_data_valid =</span></a>
+<a name="267"><span class="lineNum">     267 </span>            :     (~(io_update_pc[1]) &amp; _bank_wrbypasses_0_0_io_hit | io_update_pc[1]</a>
+<a name="268"><span class="lineNum">     268 </span>            :      &amp; _bank_wrbypasses_0_1_io_hit)</a>
+<a name="269"><span class="lineNum">     269 </span>            :     &amp; (~(io_update_pc[1]) &amp; _bank_wrbypasses_0_0_io_hit_data_0_valid | io_update_pc[1]</a>
+<a name="270"><span class="lineNum">     270 </span>            :        &amp; _bank_wrbypasses_0_1_io_hit_data_0_valid);</a>
+<a name="271"><span class="lineNum">     271 </span>            :   wire        _GEN = io_update_pc[1] ? io_update_takens_1 : io_update_takens_0;</a>
+<a name="272"><span class="lineNum">     272 </span>            :   wire [2:0]  _GEN_0 = io_update_pc[1] ? io_update_oldCtrs_1 : io_update_oldCtrs_0;</a>
+<a name="273"><span class="lineNum">     273 </span>            :   wire        _GEN_1 = (|_GEN_0) | _GEN;</a>
+<a name="274"><span class="lineNum">     274 </span>            :   wire        _GEN_2 = io_update_pc[1] ? io_update_alloc_1 : io_update_alloc_0;</a>
+<a name="275"><span class="lineNum">     275 </span><span class="lineCov">         57 :   wire [2:0]  per_bank_update_wdata_0_0_ctr =</span></a>
+<a name="276"><span class="lineNum">     276 </span>            :     _GEN_2</a>
+<a name="277"><span class="lineNum">     277 </span>            :       ? (_GEN ? 3'h4 : 3'h3)</a>
+<a name="278"><span class="lineNum">     278 </span>            :       : wrbypass_data_valid</a>
+<a name="279"><span class="lineNum">     279 </span>            :           ? ((&amp;_wrbypass_io_T_6) &amp; _GEN</a>
+<a name="280"><span class="lineNum">     280 </span>            :                ? 3'h7</a>
+<a name="281"><span class="lineNum">     281 </span>            :                : _wrbypass_io_T_6 == 3'h0 &amp; ~_GEN</a>
+<a name="282"><span class="lineNum">     282 </span>            :                    ? 3'h0</a>
+<a name="283"><span class="lineNum">     283 </span>            :                    : _GEN ? 3'(_wrbypass_io_T_6 + 3'h1) : 3'(_wrbypass_io_T_6 - 3'h1))</a>
+<a name="284"><span class="lineNum">     284 </span>            :           : (&amp;_GEN_0) &amp; _GEN</a>
+<a name="285"><span class="lineNum">     285 </span>            :               ? 3'h7</a>
+<a name="286"><span class="lineNum">     286 </span>            :               : _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0;</a>
+<a name="287"><span class="lineNum">     287 </span>            :   assign per_bank_not_silent_update_0_0 =</a>
+<a name="288"><span class="lineNum">     288 </span>            :     (wrbypass_data_valid</a>
+<a name="289"><span class="lineNum">     289 </span>            :        ? ~((&amp;_wrbypass_io_T_6) &amp; _GEN | _wrbypass_io_T_6 == 3'h0 &amp; ~_GEN)</a>
+<a name="290"><span class="lineNum">     290 </span>            :        : ~((&amp;_GEN_0) &amp; _GEN | _GEN_0 == 3'h0 &amp; ~_GEN)) | _GEN_2;</a>
+<a name="291"><span class="lineNum">     291 </span>            :   wire [2:0]  _wrbypass_io_T_28 =</a>
+<a name="292"><span class="lineNum">     292 </span>            :     (io_update_pc[1] ? _bank_wrbypasses_0_0_io_hit_data_0_bits : 3'h0)</a>
+<a name="293"><span class="lineNum">     293 </span>            :     | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_0_1_io_hit_data_0_bits);</a>
+<a name="294"><span class="lineNum">     294 </span><span class="lineCov">         21 :   wire        wrbypass_data_valid_1 =</span></a>
+<a name="295"><span class="lineNum">     295 </span>            :     (io_update_pc[1] &amp; _bank_wrbypasses_0_0_io_hit | ~(io_update_pc[1])</a>
+<a name="296"><span class="lineNum">     296 </span>            :      &amp; _bank_wrbypasses_0_1_io_hit)</a>
+<a name="297"><span class="lineNum">     297 </span>            :     &amp; (io_update_pc[1] &amp; _bank_wrbypasses_0_0_io_hit_data_0_valid | ~(io_update_pc[1])</a>
+<a name="298"><span class="lineNum">     298 </span>            :        &amp; _bank_wrbypasses_0_1_io_hit_data_0_valid);</a>
+<a name="299"><span class="lineNum">     299 </span>            :   wire        _GEN_3 = io_update_pc[1] ? io_update_takens_0 : io_update_takens_1;</a>
+<a name="300"><span class="lineNum">     300 </span>            :   wire [2:0]  _GEN_4 = io_update_pc[1] ? io_update_oldCtrs_0 : io_update_oldCtrs_1;</a>
+<a name="301"><span class="lineNum">     301 </span>            :   wire        _GEN_5 = io_update_pc[1] ? io_update_alloc_0 : io_update_alloc_1;</a>
+<a name="302"><span class="lineNum">     302 </span><span class="lineCov">         51 :   wire [2:0]  per_bank_update_wdata_0_1_ctr =</span></a>
+<a name="303"><span class="lineNum">     303 </span>            :     _GEN_5</a>
+<a name="304"><span class="lineNum">     304 </span>            :       ? (_GEN_3 ? 3'h4 : 3'h3)</a>
+<a name="305"><span class="lineNum">     305 </span>            :       : wrbypass_data_valid_1</a>
+<a name="306"><span class="lineNum">     306 </span>            :           ? ((&amp;_wrbypass_io_T_28) &amp; _GEN_3</a>
+<a name="307"><span class="lineNum">     307 </span>            :                ? 3'h7</a>
+<a name="308"><span class="lineNum">     308 </span>            :                : _wrbypass_io_T_28 == 3'h0 &amp; ~_GEN_3</a>
+<a name="309"><span class="lineNum">     309 </span>            :                    ? 3'h0</a>
+<a name="310"><span class="lineNum">     310 </span>            :                    : _GEN_3 ? 3'(_wrbypass_io_T_28 + 3'h1) : 3'(_wrbypass_io_T_28 - 3'h1))</a>
+<a name="311"><span class="lineNum">     311 </span>            :           : (&amp;_GEN_4) &amp; _GEN_3</a>
+<a name="312"><span class="lineNum">     312 </span>            :               ? 3'h7</a>
+<a name="313"><span class="lineNum">     313 </span>            :               : _GEN_4 == 3'h0 &amp; ~_GEN_3</a>
+<a name="314"><span class="lineNum">     314 </span>            :                   ? 3'h0</a>
+<a name="315"><span class="lineNum">     315 </span>            :                   : _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1);</a>
+<a name="316"><span class="lineNum">     316 </span>            :   assign per_bank_not_silent_update_0_1 =</a>
+<a name="317"><span class="lineNum">     317 </span>            :     (wrbypass_data_valid_1</a>
+<a name="318"><span class="lineNum">     318 </span>            :        ? ~((&amp;_wrbypass_io_T_28) &amp; _GEN_3 | _wrbypass_io_T_28 == 3'h0 &amp; ~_GEN_3)</a>
+<a name="319"><span class="lineNum">     319 </span>            :        : ~((&amp;_GEN_4) &amp; _GEN_3 | _GEN_4 == 3'h0 &amp; ~_GEN_3)) | _GEN_5;</a>
+<a name="320"><span class="lineNum">     320 </span>            :   wire [2:0]  _wrbypass_io_T_50 =</a>
+<a name="321"><span class="lineNum">     321 </span>            :     (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_1_0_io_hit_data_0_bits)</a>
+<a name="322"><span class="lineNum">     322 </span>            :     | (io_update_pc[1] ? _bank_wrbypasses_1_1_io_hit_data_0_bits : 3'h0);</a>
+<a name="323"><span class="lineNum">     323 </span><span class="lineCov">         15 :   wire        wrbypass_data_valid_2 =</span></a>
+<a name="324"><span class="lineNum">     324 </span>            :     (~(io_update_pc[1]) &amp; _bank_wrbypasses_1_0_io_hit | io_update_pc[1]</a>
+<a name="325"><span class="lineNum">     325 </span>            :      &amp; _bank_wrbypasses_1_1_io_hit)</a>
+<a name="326"><span class="lineNum">     326 </span>            :     &amp; (~(io_update_pc[1]) &amp; _bank_wrbypasses_1_0_io_hit_data_0_valid | io_update_pc[1]</a>
+<a name="327"><span class="lineNum">     327 </span>            :        &amp; _bank_wrbypasses_1_1_io_hit_data_0_valid);</a>
+<a name="328"><span class="lineNum">     328 </span><span class="lineCov">         44 :   wire [2:0]  per_bank_update_wdata_1_0_ctr =</span></a>
+<a name="329"><span class="lineNum">     329 </span>            :     _GEN_2</a>
+<a name="330"><span class="lineNum">     330 </span>            :       ? (_GEN ? 3'h4 : 3'h3)</a>
+<a name="331"><span class="lineNum">     331 </span>            :       : wrbypass_data_valid_2</a>
+<a name="332"><span class="lineNum">     332 </span>            :           ? ((&amp;_wrbypass_io_T_50) &amp; _GEN</a>
+<a name="333"><span class="lineNum">     333 </span>            :                ? 3'h7</a>
+<a name="334"><span class="lineNum">     334 </span>            :                : _wrbypass_io_T_50 == 3'h0 &amp; ~_GEN</a>
+<a name="335"><span class="lineNum">     335 </span>            :                    ? 3'h0</a>
+<a name="336"><span class="lineNum">     336 </span>            :                    : _GEN ? 3'(_wrbypass_io_T_50 + 3'h1) : 3'(_wrbypass_io_T_50 - 3'h1))</a>
+<a name="337"><span class="lineNum">     337 </span>            :           : (&amp;_GEN_0) &amp; _GEN</a>
+<a name="338"><span class="lineNum">     338 </span>            :               ? 3'h7</a>
+<a name="339"><span class="lineNum">     339 </span>            :               : _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0;</a>
+<a name="340"><span class="lineNum">     340 </span>            :   assign per_bank_not_silent_update_1_0 =</a>
+<a name="341"><span class="lineNum">     341 </span>            :     (wrbypass_data_valid_2</a>
+<a name="342"><span class="lineNum">     342 </span>            :        ? ~((&amp;_wrbypass_io_T_50) &amp; _GEN | _wrbypass_io_T_50 == 3'h0 &amp; ~_GEN)</a>
+<a name="343"><span class="lineNum">     343 </span>            :        : ~((&amp;_GEN_0) &amp; _GEN | _GEN_0 == 3'h0 &amp; ~_GEN)) | _GEN_2;</a>
+<a name="344"><span class="lineNum">     344 </span>            :   wire [2:0]  _wrbypass_io_T_72 =</a>
+<a name="345"><span class="lineNum">     345 </span>            :     (io_update_pc[1] ? _bank_wrbypasses_1_0_io_hit_data_0_bits : 3'h0)</a>
+<a name="346"><span class="lineNum">     346 </span>            :     | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_1_1_io_hit_data_0_bits);</a>
+<a name="347"><span class="lineNum">     347 </span><span class="lineCov">         17 :   wire        wrbypass_data_valid_3 =</span></a>
+<a name="348"><span class="lineNum">     348 </span>            :     (io_update_pc[1] &amp; _bank_wrbypasses_1_0_io_hit | ~(io_update_pc[1])</a>
+<a name="349"><span class="lineNum">     349 </span>            :      &amp; _bank_wrbypasses_1_1_io_hit)</a>
+<a name="350"><span class="lineNum">     350 </span>            :     &amp; (io_update_pc[1] &amp; _bank_wrbypasses_1_0_io_hit_data_0_valid | ~(io_update_pc[1])</a>
+<a name="351"><span class="lineNum">     351 </span>            :        &amp; _bank_wrbypasses_1_1_io_hit_data_0_valid);</a>
+<a name="352"><span class="lineNum">     352 </span><span class="lineCov">         45 :   wire [2:0]  per_bank_update_wdata_1_1_ctr =</span></a>
+<a name="353"><span class="lineNum">     353 </span>            :     _GEN_5</a>
+<a name="354"><span class="lineNum">     354 </span>            :       ? (_GEN_3 ? 3'h4 : 3'h3)</a>
+<a name="355"><span class="lineNum">     355 </span>            :       : wrbypass_data_valid_3</a>
+<a name="356"><span class="lineNum">     356 </span>            :           ? ((&amp;_wrbypass_io_T_72) &amp; _GEN_3</a>
+<a name="357"><span class="lineNum">     357 </span>            :                ? 3'h7</a>
+<a name="358"><span class="lineNum">     358 </span>            :                : _wrbypass_io_T_72 == 3'h0 &amp; ~_GEN_3</a>
+<a name="359"><span class="lineNum">     359 </span>            :                    ? 3'h0</a>
+<a name="360"><span class="lineNum">     360 </span>            :                    : _GEN_3 ? 3'(_wrbypass_io_T_72 + 3'h1) : 3'(_wrbypass_io_T_72 - 3'h1))</a>
+<a name="361"><span class="lineNum">     361 </span>            :           : (&amp;_GEN_4) &amp; _GEN_3</a>
+<a name="362"><span class="lineNum">     362 </span>            :               ? 3'h7</a>
+<a name="363"><span class="lineNum">     363 </span>            :               : _GEN_4 == 3'h0 &amp; ~_GEN_3</a>
+<a name="364"><span class="lineNum">     364 </span>            :                   ? 3'h0</a>
+<a name="365"><span class="lineNum">     365 </span>            :                   : _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1);</a>
+<a name="366"><span class="lineNum">     366 </span>            :   assign per_bank_not_silent_update_1_1 =</a>
+<a name="367"><span class="lineNum">     367 </span>            :     (wrbypass_data_valid_3</a>
+<a name="368"><span class="lineNum">     368 </span>            :        ? ~((&amp;_wrbypass_io_T_72) &amp; _GEN_3 | _wrbypass_io_T_72 == 3'h0 &amp; ~_GEN_3)</a>
+<a name="369"><span class="lineNum">     369 </span>            :        : ~((&amp;_GEN_4) &amp; _GEN_3 | _GEN_4 == 3'h0 &amp; ~_GEN_3)) | _GEN_5;</a>
+<a name="370"><span class="lineNum">     370 </span>            :   wire [2:0]  _wrbypass_io_T_94 =</a>
+<a name="371"><span class="lineNum">     371 </span>            :     (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_2_0_io_hit_data_0_bits)</a>
+<a name="372"><span class="lineNum">     372 </span>            :     | (io_update_pc[1] ? _bank_wrbypasses_2_1_io_hit_data_0_bits : 3'h0);</a>
+<a name="373"><span class="lineNum">     373 </span><span class="lineCov">         18 :   wire        wrbypass_data_valid_4 =</span></a>
+<a name="374"><span class="lineNum">     374 </span>            :     (~(io_update_pc[1]) &amp; _bank_wrbypasses_2_0_io_hit | io_update_pc[1]</a>
+<a name="375"><span class="lineNum">     375 </span>            :      &amp; _bank_wrbypasses_2_1_io_hit)</a>
+<a name="376"><span class="lineNum">     376 </span>            :     &amp; (~(io_update_pc[1]) &amp; _bank_wrbypasses_2_0_io_hit_data_0_valid | io_update_pc[1]</a>
+<a name="377"><span class="lineNum">     377 </span>            :        &amp; _bank_wrbypasses_2_1_io_hit_data_0_valid);</a>
+<a name="378"><span class="lineNum">     378 </span><span class="lineCov">         47 :   wire [2:0]  per_bank_update_wdata_2_0_ctr =</span></a>
+<a name="379"><span class="lineNum">     379 </span>            :     _GEN_2</a>
+<a name="380"><span class="lineNum">     380 </span>            :       ? (_GEN ? 3'h4 : 3'h3)</a>
+<a name="381"><span class="lineNum">     381 </span>            :       : wrbypass_data_valid_4</a>
+<a name="382"><span class="lineNum">     382 </span>            :           ? ((&amp;_wrbypass_io_T_94) &amp; _GEN</a>
+<a name="383"><span class="lineNum">     383 </span>            :                ? 3'h7</a>
+<a name="384"><span class="lineNum">     384 </span>            :                : _wrbypass_io_T_94 == 3'h0 &amp; ~_GEN</a>
+<a name="385"><span class="lineNum">     385 </span>            :                    ? 3'h0</a>
+<a name="386"><span class="lineNum">     386 </span>            :                    : _GEN ? 3'(_wrbypass_io_T_94 + 3'h1) : 3'(_wrbypass_io_T_94 - 3'h1))</a>
+<a name="387"><span class="lineNum">     387 </span>            :           : (&amp;_GEN_0) &amp; _GEN</a>
+<a name="388"><span class="lineNum">     388 </span>            :               ? 3'h7</a>
+<a name="389"><span class="lineNum">     389 </span>            :               : _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0;</a>
+<a name="390"><span class="lineNum">     390 </span>            :   assign per_bank_not_silent_update_2_0 =</a>
+<a name="391"><span class="lineNum">     391 </span>            :     (wrbypass_data_valid_4</a>
+<a name="392"><span class="lineNum">     392 </span>            :        ? ~((&amp;_wrbypass_io_T_94) &amp; _GEN | _wrbypass_io_T_94 == 3'h0 &amp; ~_GEN)</a>
+<a name="393"><span class="lineNum">     393 </span>            :        : ~((&amp;_GEN_0) &amp; _GEN | _GEN_0 == 3'h0 &amp; ~_GEN)) | _GEN_2;</a>
+<a name="394"><span class="lineNum">     394 </span>            :   wire [2:0]  _wrbypass_io_T_116 =</a>
+<a name="395"><span class="lineNum">     395 </span>            :     (io_update_pc[1] ? _bank_wrbypasses_2_0_io_hit_data_0_bits : 3'h0)</a>
+<a name="396"><span class="lineNum">     396 </span>            :     | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_2_1_io_hit_data_0_bits);</a>
+<a name="397"><span class="lineNum">     397 </span><span class="lineCov">         15 :   wire        wrbypass_data_valid_5 =</span></a>
+<a name="398"><span class="lineNum">     398 </span>            :     (io_update_pc[1] &amp; _bank_wrbypasses_2_0_io_hit | ~(io_update_pc[1])</a>
+<a name="399"><span class="lineNum">     399 </span>            :      &amp; _bank_wrbypasses_2_1_io_hit)</a>
+<a name="400"><span class="lineNum">     400 </span>            :     &amp; (io_update_pc[1] &amp; _bank_wrbypasses_2_0_io_hit_data_0_valid | ~(io_update_pc[1])</a>
+<a name="401"><span class="lineNum">     401 </span>            :        &amp; _bank_wrbypasses_2_1_io_hit_data_0_valid);</a>
+<a name="402"><span class="lineNum">     402 </span><span class="lineCov">         43 :   wire [2:0]  per_bank_update_wdata_2_1_ctr =</span></a>
+<a name="403"><span class="lineNum">     403 </span>            :     _GEN_5</a>
+<a name="404"><span class="lineNum">     404 </span>            :       ? (_GEN_3 ? 3'h4 : 3'h3)</a>
+<a name="405"><span class="lineNum">     405 </span>            :       : wrbypass_data_valid_5</a>
+<a name="406"><span class="lineNum">     406 </span>            :           ? ((&amp;_wrbypass_io_T_116) &amp; _GEN_3</a>
+<a name="407"><span class="lineNum">     407 </span>            :                ? 3'h7</a>
+<a name="408"><span class="lineNum">     408 </span>            :                : _wrbypass_io_T_116 == 3'h0 &amp; ~_GEN_3</a>
+<a name="409"><span class="lineNum">     409 </span>            :                    ? 3'h0</a>
+<a name="410"><span class="lineNum">     410 </span>            :                    : _GEN_3</a>
+<a name="411"><span class="lineNum">     411 </span>            :                        ? 3'(_wrbypass_io_T_116 + 3'h1)</a>
+<a name="412"><span class="lineNum">     412 </span>            :                        : 3'(_wrbypass_io_T_116 - 3'h1))</a>
+<a name="413"><span class="lineNum">     413 </span>            :           : (&amp;_GEN_4) &amp; _GEN_3</a>
+<a name="414"><span class="lineNum">     414 </span>            :               ? 3'h7</a>
+<a name="415"><span class="lineNum">     415 </span>            :               : _GEN_4 == 3'h0 &amp; ~_GEN_3</a>
+<a name="416"><span class="lineNum">     416 </span>            :                   ? 3'h0</a>
+<a name="417"><span class="lineNum">     417 </span>            :                   : _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1);</a>
+<a name="418"><span class="lineNum">     418 </span>            :   assign per_bank_not_silent_update_2_1 =</a>
+<a name="419"><span class="lineNum">     419 </span>            :     (wrbypass_data_valid_5</a>
+<a name="420"><span class="lineNum">     420 </span>            :        ? ~((&amp;_wrbypass_io_T_116) &amp; _GEN_3 | _wrbypass_io_T_116 == 3'h0 &amp; ~_GEN_3)</a>
+<a name="421"><span class="lineNum">     421 </span>            :        : ~((&amp;_GEN_4) &amp; _GEN_3 | _GEN_4 == 3'h0 &amp; ~_GEN_3)) | _GEN_5;</a>
+<a name="422"><span class="lineNum">     422 </span>            :   wire [2:0]  _wrbypass_io_T_138 =</a>
+<a name="423"><span class="lineNum">     423 </span>            :     (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_3_0_io_hit_data_0_bits)</a>
+<a name="424"><span class="lineNum">     424 </span>            :     | (io_update_pc[1] ? _bank_wrbypasses_3_1_io_hit_data_0_bits : 3'h0);</a>
+<a name="425"><span class="lineNum">     425 </span><span class="lineCov">         18 :   wire        wrbypass_data_valid_6 =</span></a>
+<a name="426"><span class="lineNum">     426 </span>            :     (~(io_update_pc[1]) &amp; _bank_wrbypasses_3_0_io_hit | io_update_pc[1]</a>
+<a name="427"><span class="lineNum">     427 </span>            :      &amp; _bank_wrbypasses_3_1_io_hit)</a>
+<a name="428"><span class="lineNum">     428 </span>            :     &amp; (~(io_update_pc[1]) &amp; _bank_wrbypasses_3_0_io_hit_data_0_valid | io_update_pc[1]</a>
+<a name="429"><span class="lineNum">     429 </span>            :        &amp; _bank_wrbypasses_3_1_io_hit_data_0_valid);</a>
+<a name="430"><span class="lineNum">     430 </span><span class="lineCov">         57 :   wire [2:0]  per_bank_update_wdata_3_0_ctr =</span></a>
+<a name="431"><span class="lineNum">     431 </span>            :     _GEN_2</a>
+<a name="432"><span class="lineNum">     432 </span>            :       ? (_GEN ? 3'h4 : 3'h3)</a>
+<a name="433"><span class="lineNum">     433 </span>            :       : wrbypass_data_valid_6</a>
+<a name="434"><span class="lineNum">     434 </span>            :           ? ((&amp;_wrbypass_io_T_138) &amp; _GEN</a>
+<a name="435"><span class="lineNum">     435 </span>            :                ? 3'h7</a>
+<a name="436"><span class="lineNum">     436 </span>            :                : _wrbypass_io_T_138 == 3'h0 &amp; ~_GEN</a>
+<a name="437"><span class="lineNum">     437 </span>            :                    ? 3'h0</a>
+<a name="438"><span class="lineNum">     438 </span>            :                    : _GEN ? 3'(_wrbypass_io_T_138 + 3'h1) : 3'(_wrbypass_io_T_138 - 3'h1))</a>
+<a name="439"><span class="lineNum">     439 </span>            :           : (&amp;_GEN_0) &amp; _GEN</a>
+<a name="440"><span class="lineNum">     440 </span>            :               ? 3'h7</a>
+<a name="441"><span class="lineNum">     441 </span>            :               : _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0;</a>
+<a name="442"><span class="lineNum">     442 </span>            :   assign per_bank_not_silent_update_3_0 =</a>
+<a name="443"><span class="lineNum">     443 </span>            :     (wrbypass_data_valid_6</a>
+<a name="444"><span class="lineNum">     444 </span>            :        ? ~((&amp;_wrbypass_io_T_138) &amp; _GEN | _wrbypass_io_T_138 == 3'h0 &amp; ~_GEN)</a>
+<a name="445"><span class="lineNum">     445 </span>            :        : ~((&amp;_GEN_0) &amp; _GEN | _GEN_0 == 3'h0 &amp; ~_GEN)) | _GEN_2;</a>
+<a name="446"><span class="lineNum">     446 </span>            :   wire [2:0]  _wrbypass_io_T_160 =</a>
+<a name="447"><span class="lineNum">     447 </span>            :     (io_update_pc[1] ? _bank_wrbypasses_3_0_io_hit_data_0_bits : 3'h0)</a>
+<a name="448"><span class="lineNum">     448 </span>            :     | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_3_1_io_hit_data_0_bits);</a>
+<a name="449"><span class="lineNum">     449 </span><span class="lineCov">         22 :   wire        wrbypass_data_valid_7 =</span></a>
+<a name="450"><span class="lineNum">     450 </span>            :     (io_update_pc[1] &amp; _bank_wrbypasses_3_0_io_hit | ~(io_update_pc[1])</a>
+<a name="451"><span class="lineNum">     451 </span>            :      &amp; _bank_wrbypasses_3_1_io_hit)</a>
+<a name="452"><span class="lineNum">     452 </span>            :     &amp; (io_update_pc[1] &amp; _bank_wrbypasses_3_0_io_hit_data_0_valid | ~(io_update_pc[1])</a>
+<a name="453"><span class="lineNum">     453 </span>            :        &amp; _bank_wrbypasses_3_1_io_hit_data_0_valid);</a>
+<a name="454"><span class="lineNum">     454 </span><span class="lineCov">         50 :   wire [2:0]  per_bank_update_wdata_3_1_ctr =</span></a>
+<a name="455"><span class="lineNum">     455 </span>            :     _GEN_5</a>
+<a name="456"><span class="lineNum">     456 </span>            :       ? (_GEN_3 ? 3'h4 : 3'h3)</a>
+<a name="457"><span class="lineNum">     457 </span>            :       : wrbypass_data_valid_7</a>
+<a name="458"><span class="lineNum">     458 </span>            :           ? ((&amp;_wrbypass_io_T_160) &amp; _GEN_3</a>
+<a name="459"><span class="lineNum">     459 </span>            :                ? 3'h7</a>
+<a name="460"><span class="lineNum">     460 </span>            :                : _wrbypass_io_T_160 == 3'h0 &amp; ~_GEN_3</a>
+<a name="461"><span class="lineNum">     461 </span>            :                    ? 3'h0</a>
+<a name="462"><span class="lineNum">     462 </span>            :                    : _GEN_3</a>
+<a name="463"><span class="lineNum">     463 </span>            :                        ? 3'(_wrbypass_io_T_160 + 3'h1)</a>
+<a name="464"><span class="lineNum">     464 </span>            :                        : 3'(_wrbypass_io_T_160 - 3'h1))</a>
+<a name="465"><span class="lineNum">     465 </span>            :           : (&amp;_GEN_4) &amp; _GEN_3</a>
+<a name="466"><span class="lineNum">     466 </span>            :               ? 3'h7</a>
+<a name="467"><span class="lineNum">     467 </span>            :               : _GEN_4 == 3'h0 &amp; ~_GEN_3</a>
+<a name="468"><span class="lineNum">     468 </span>            :                   ? 3'h0</a>
+<a name="469"><span class="lineNum">     469 </span>            :                   : _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1);</a>
+<a name="470"><span class="lineNum">     470 </span>            :   assign per_bank_not_silent_update_3_1 =</a>
+<a name="471"><span class="lineNum">     471 </span>            :     (wrbypass_data_valid_7</a>
+<a name="472"><span class="lineNum">     472 </span>            :        ? ~((&amp;_wrbypass_io_T_160) &amp; _GEN_3 | _wrbypass_io_T_160 == 3'h0 &amp; ~_GEN_3)</a>
+<a name="473"><span class="lineNum">     473 </span>            :        : ~((&amp;_GEN_4) &amp; _GEN_3 | _GEN_4 == 3'h0 &amp; ~_GEN_3)) | _GEN_5;</a>
+<a name="474"><span class="lineNum">     474 </span><span class="lineCov">     127694 :   always @(posedge clock) begin</span></a>
+<a name="475"><span class="lineNum">     475 </span><span class="lineCov">       8350 :     if (_s1_bank_req_1h_T) begin</span></a>
+<a name="476"><span class="lineNum">     476 </span><span class="lineCov">       4175 :       s1_unhashed_idx &lt;= io_req_bits_pc[40:1];</span></a>
+<a name="477"><span class="lineNum">     477 </span><span class="lineCov">       4175 :       s1_tag &lt;=</span></a>
+<a name="478"><span class="lineNum">     478 </span><span class="lineCov">       4175 :         io_req_bits_pc[8:1] ^ io_req_bits_folded_hist_hist_3_folded_hist</span></a>
+<a name="479"><span class="lineNum">     479 </span><span class="lineCov">       4175 :         ^ {io_req_bits_folded_hist_hist_9_folded_hist, 1'h0};</span></a>
+<a name="480"><span class="lineNum">     480 </span><span class="lineCov">       4175 :       s1_bank_req_1h_0 &lt;= s0_bank_req_1h_0;</span></a>
+<a name="481"><span class="lineNum">     481 </span><span class="lineCov">       4175 :       s1_bank_req_1h_1 &lt;= s0_bank_req_1h_1;</span></a>
+<a name="482"><span class="lineNum">     482 </span><span class="lineCov">       4175 :       s1_bank_req_1h_2 &lt;= s0_bank_req_1h_2;</span></a>
+<a name="483"><span class="lineNum">     483 </span><span class="lineCov">       4175 :       s1_bank_req_1h_3 &lt;= &amp;(s0_idx[1:0]);</span></a>
+<a name="484"><span class="lineNum">     484 </span>            :     end</a>
+<a name="485"><span class="lineNum">     485 </span><span class="lineCov">       8350 :     if (io_req_valid) begin</span></a>
+<a name="486"><span class="lineNum">     486 </span><span class="lineCov">       4175 :       s1_bank_has_write_on_this_req_0 &lt;= _s1_bank_has_write_on_this_req_WIRE_0;</span></a>
+<a name="487"><span class="lineNum">     487 </span><span class="lineCov">       4175 :       s1_bank_has_write_on_this_req_1 &lt;= _s1_bank_has_write_on_this_req_WIRE_1;</span></a>
+<a name="488"><span class="lineNum">     488 </span><span class="lineCov">       4175 :       s1_bank_has_write_on_this_req_2 &lt;= _s1_bank_has_write_on_this_req_WIRE_2;</span></a>
+<a name="489"><span class="lineNum">     489 </span><span class="lineCov">       4175 :       s1_bank_has_write_on_this_req_3 &lt;= _s1_bank_has_write_on_this_req_WIRE_3;</span></a>
+<a name="490"><span class="lineNum">     490 </span>            :     end</a>
+<a name="491"><span class="lineNum">     491 </span>            :   end // always @(posedge)</a>
+<a name="492"><span class="lineNum">     492 </span><span class="lineCov">     127730 :   always @(posedge clock or posedge reset) begin</span></a>
+<a name="493"><span class="lineNum">     493 </span><span class="lineCov">        272 :     if (reset)</span></a>
+<a name="494"><span class="lineNum">     494 </span><span class="lineCov">        136 :       powerOnResetState &lt;= 1'h1;</span></a>
+<a name="495"><span class="lineNum">     495 </span>            :     else</a>
+<a name="496"><span class="lineNum">     496 </span><span class="lineCov">      63729 :       powerOnResetState &lt;=</span></a>
+<a name="497"><span class="lineNum">     497 </span><span class="lineCov">      63729 :         ~(_us_io_r_req_ready &amp; _table_banks_0_io_r_req_ready</span></a>
+<a name="498"><span class="lineNum">     498 </span><span class="lineCov">      63729 :           &amp; _table_banks_1_io_r_req_ready &amp; _table_banks_2_io_r_req_ready</span></a>
+<a name="499"><span class="lineNum">     499 </span><span class="lineCov">      63729 :           &amp; _table_banks_3_io_r_req_ready) &amp; powerOnResetState;</span></a>
+<a name="500"><span class="lineNum">     500 </span>            :   end // always @(posedge, posedge)</a>
+<a name="501"><span class="lineNum">     501 </span>            :   `ifdef ENABLE_INITIAL_REG_</a>
+<a name="502"><span class="lineNum">     502 </span>            :     `ifdef FIRRTL_BEFORE_INITIAL</a>
+<a name="503"><span class="lineNum">     503 </span>            :       `FIRRTL_BEFORE_INITIAL</a>
+<a name="504"><span class="lineNum">     504 </span>            :     `endif // FIRRTL_BEFORE_INITIAL</a>
+<a name="505"><span class="lineNum">     505 </span>            :     logic [31:0] _RANDOM[0:3];</a>
+<a name="506"><span class="lineNum">     506 </span><span class="lineCov">         58 :     initial begin</span></a>
+<a name="507"><span class="lineNum">     507 </span>            :       `ifdef INIT_RANDOM_PROLOG_</a>
+<a name="508"><span class="lineNum">     508 </span>            :         `INIT_RANDOM_PROLOG_</a>
+<a name="509"><span class="lineNum">     509 </span>            :       `endif // INIT_RANDOM_PROLOG_</a>
+<a name="510"><span class="lineNum">     510 </span>            :       `ifdef RANDOMIZE_REG_INIT</a>
+<a name="511"><span class="lineNum">     511 </span>            :         for (logic [2:0] i = 3'h0; i &lt; 3'h4; i += 3'h1) begin</a>
+<a name="512"><span class="lineNum">     512 </span>            :           _RANDOM[i[1:0]] = `RANDOM;</a>
+<a name="513"><span class="lineNum">     513 </span>            :         end</a>
+<a name="514"><span class="lineNum">     514 </span>            :         s1_unhashed_idx = {_RANDOM[2'h0], _RANDOM[2'h1][7:0]};</a>
+<a name="515"><span class="lineNum">     515 </span>            :         s1_tag = _RANDOM[2'h1][26:19];</a>
+<a name="516"><span class="lineNum">     516 </span>            :         s1_bank_req_1h_0 = _RANDOM[2'h3][4];</a>
+<a name="517"><span class="lineNum">     517 </span>            :         s1_bank_req_1h_1 = _RANDOM[2'h3][5];</a>
+<a name="518"><span class="lineNum">     518 </span>            :         s1_bank_req_1h_2 = _RANDOM[2'h3][6];</a>
+<a name="519"><span class="lineNum">     519 </span>            :         s1_bank_req_1h_3 = _RANDOM[2'h3][7];</a>
+<a name="520"><span class="lineNum">     520 </span>            :         s1_bank_has_write_on_this_req_0 = _RANDOM[2'h3][8];</a>
+<a name="521"><span class="lineNum">     521 </span>            :         s1_bank_has_write_on_this_req_1 = _RANDOM[2'h3][9];</a>
+<a name="522"><span class="lineNum">     522 </span>            :         s1_bank_has_write_on_this_req_2 = _RANDOM[2'h3][10];</a>
+<a name="523"><span class="lineNum">     523 </span>            :         s1_bank_has_write_on_this_req_3 = _RANDOM[2'h3][11];</a>
+<a name="524"><span class="lineNum">     524 </span>            :         powerOnResetState = _RANDOM[2'h3][12];</a>
+<a name="525"><span class="lineNum">     525 </span>            :       `endif // RANDOMIZE_REG_INIT</a>
+<a name="526"><span class="lineNum">     526 </span><span class="lineCov">         17 :       if (reset)</span></a>
+<a name="527"><span class="lineNum">     527 </span><span class="lineCov">         12 :         powerOnResetState = 1'h1;</span></a>
+<a name="528"><span class="lineNum">     528 </span>            :     end // initial</a>
+<a name="529"><span class="lineNum">     529 </span>            :     `ifdef FIRRTL_AFTER_INITIAL</a>
+<a name="530"><span class="lineNum">     530 </span>            :       `FIRRTL_AFTER_INITIAL</a>
+<a name="531"><span class="lineNum">     531 </span>            :     `endif // FIRRTL_AFTER_INITIAL</a>
+<a name="532"><span class="lineNum">     532 </span>            :   `endif // ENABLE_INITIAL_REG_</a>
+<a name="533"><span class="lineNum">     533 </span>            :   FoldedSRAMTemplate us (</a>
+<a name="534"><span class="lineNum">     534 </span>            :     .clock                 (clock),</a>
+<a name="535"><span class="lineNum">     535 </span>            :     .reset                 (reset),</a>
+<a name="536"><span class="lineNum">     536 </span>            :     .io_r_req_ready        (_us_io_r_req_ready),</a>
+<a name="537"><span class="lineNum">     537 </span>            :     .io_r_req_valid        (_s1_bank_req_1h_T),</a>
+<a name="538"><span class="lineNum">     538 </span>            :     .io_r_req_bits_setIdx  (s0_idx),</a>
+<a name="539"><span class="lineNum">     539 </span>            :     .io_r_resp_data_0      (_us_io_r_resp_data_0),</a>
+<a name="540"><span class="lineNum">     540 </span>            :     .io_r_resp_data_1      (_us_io_r_resp_data_1),</a>
+<a name="541"><span class="lineNum">     541 </span>            :     .io_w_req_valid</a>
+<a name="542"><span class="lineNum">     542 </span>            :       (_us_extra_reset_T_1 &amp; (io_update_uMask_0 | io_update_uMask_1)),</a>
+<a name="543"><span class="lineNum">     543 </span>            :     .io_w_req_bits_setIdx  (update_idx),</a>
+<a name="544"><span class="lineNum">     544 </span>            :     .io_w_req_bits_data_0</a>
+<a name="545"><span class="lineNum">     545 </span>            :       (~(io_update_pc[1]) &amp; io_update_us_0 | io_update_pc[1] &amp; io_update_us_1),</a>
+<a name="546"><span class="lineNum">     546 </span>            :     .io_w_req_bits_data_1</a>
+<a name="547"><span class="lineNum">     547 </span>            :       (io_update_pc[1] &amp; io_update_us_0 | ~(io_update_pc[1]) &amp; io_update_us_1),</a>
+<a name="548"><span class="lineNum">     548 </span>            :     .io_w_req_bits_waymask</a>
+<a name="549"><span class="lineNum">     549 </span>            :       ({io_update_pc[1] &amp; io_update_uMask_0 | ~(io_update_pc[1]) &amp; io_update_uMask_1,</a>
+<a name="550"><span class="lineNum">     550 </span>            :         ~(io_update_pc[1]) &amp; io_update_uMask_0 | io_update_pc[1] &amp; io_update_uMask_1}),</a>
+<a name="551"><span class="lineNum">     551 </span>            :     .extra_reset</a>
+<a name="552"><span class="lineNum">     552 </span>            :       ((io_update_reset_u_0 | io_update_reset_u_1) &amp; _us_extra_reset_T_1)</a>
+<a name="553"><span class="lineNum">     553 </span>            :   );</a>
+<a name="554"><span class="lineNum">     554 </span>            :   FoldedSRAMTemplate_1 table_banks_0 (</a>
+<a name="555"><span class="lineNum">     555 </span>            :     .clock                    (clock),</a>
+<a name="556"><span class="lineNum">     556 </span>            :     .reset                    (reset),</a>
+<a name="557"><span class="lineNum">     557 </span>            :     .io_r_req_ready           (_table_banks_0_io_r_req_ready),</a>
+<a name="558"><span class="lineNum">     558 </span>            :     .io_r_req_valid           (_s1_bank_req_1h_T &amp; s0_bank_req_1h_0),</a>
+<a name="559"><span class="lineNum">     559 </span>            :     .io_r_req_bits_setIdx     (s0_idx[10:2]),</a>
+<a name="560"><span class="lineNum">     560 </span>            :     .io_r_resp_data_0_valid   (_table_banks_0_io_r_resp_data_0_valid),</a>
+<a name="561"><span class="lineNum">     561 </span>            :     .io_r_resp_data_0_tag     (_table_banks_0_io_r_resp_data_0_tag),</a>
+<a name="562"><span class="lineNum">     562 </span>            :     .io_r_resp_data_0_ctr     (_table_banks_0_io_r_resp_data_0_ctr),</a>
+<a name="563"><span class="lineNum">     563 </span>            :     .io_r_resp_data_1_valid   (_table_banks_0_io_r_resp_data_1_valid),</a>
+<a name="564"><span class="lineNum">     564 </span>            :     .io_r_resp_data_1_tag     (_table_banks_0_io_r_resp_data_1_tag),</a>
+<a name="565"><span class="lineNum">     565 </span>            :     .io_r_resp_data_1_ctr     (_table_banks_0_io_r_resp_data_1_ctr),</a>
+<a name="566"><span class="lineNum">     566 </span>            :     .io_w_req_valid           (_s1_bank_has_write_on_this_req_WIRE_0),</a>
+<a name="567"><span class="lineNum">     567 </span>            :     .io_w_req_bits_setIdx     (update_idx[10:2]),</a>
+<a name="568"><span class="lineNum">     568 </span>            :     .io_w_req_bits_data_0_tag (update_tag),</a>
+<a name="569"><span class="lineNum">     569 </span>            :     .io_w_req_bits_data_0_ctr (per_bank_update_wdata_0_0_ctr),</a>
+<a name="570"><span class="lineNum">     570 </span>            :     .io_w_req_bits_data_1_tag (update_tag),</a>
+<a name="571"><span class="lineNum">     571 </span>            :     .io_w_req_bits_data_1_ctr (per_bank_update_wdata_0_1_ctr),</a>
+<a name="572"><span class="lineNum">     572 </span>            :     .io_w_req_bits_waymask    (per_bank_update_way_mask_0)</a>
+<a name="573"><span class="lineNum">     573 </span>            :   );</a>
+<a name="574"><span class="lineNum">     574 </span>            :   FoldedSRAMTemplate_1 table_banks_1 (</a>
+<a name="575"><span class="lineNum">     575 </span>            :     .clock                    (clock),</a>
+<a name="576"><span class="lineNum">     576 </span>            :     .reset                    (reset),</a>
+<a name="577"><span class="lineNum">     577 </span>            :     .io_r_req_ready           (_table_banks_1_io_r_req_ready),</a>
+<a name="578"><span class="lineNum">     578 </span>            :     .io_r_req_valid           (_s1_bank_req_1h_T &amp; s0_bank_req_1h_1),</a>
+<a name="579"><span class="lineNum">     579 </span>            :     .io_r_req_bits_setIdx     (s0_idx[10:2]),</a>
+<a name="580"><span class="lineNum">     580 </span>            :     .io_r_resp_data_0_valid   (_table_banks_1_io_r_resp_data_0_valid),</a>
+<a name="581"><span class="lineNum">     581 </span>            :     .io_r_resp_data_0_tag     (_table_banks_1_io_r_resp_data_0_tag),</a>
+<a name="582"><span class="lineNum">     582 </span>            :     .io_r_resp_data_0_ctr     (_table_banks_1_io_r_resp_data_0_ctr),</a>
+<a name="583"><span class="lineNum">     583 </span>            :     .io_r_resp_data_1_valid   (_table_banks_1_io_r_resp_data_1_valid),</a>
+<a name="584"><span class="lineNum">     584 </span>            :     .io_r_resp_data_1_tag     (_table_banks_1_io_r_resp_data_1_tag),</a>
+<a name="585"><span class="lineNum">     585 </span>            :     .io_r_resp_data_1_ctr     (_table_banks_1_io_r_resp_data_1_ctr),</a>
+<a name="586"><span class="lineNum">     586 </span>            :     .io_w_req_valid           (_s1_bank_has_write_on_this_req_WIRE_1),</a>
+<a name="587"><span class="lineNum">     587 </span>            :     .io_w_req_bits_setIdx     (update_idx[10:2]),</a>
+<a name="588"><span class="lineNum">     588 </span>            :     .io_w_req_bits_data_0_tag (update_tag),</a>
+<a name="589"><span class="lineNum">     589 </span>            :     .io_w_req_bits_data_0_ctr (per_bank_update_wdata_1_0_ctr),</a>
+<a name="590"><span class="lineNum">     590 </span>            :     .io_w_req_bits_data_1_tag (update_tag),</a>
+<a name="591"><span class="lineNum">     591 </span>            :     .io_w_req_bits_data_1_ctr (per_bank_update_wdata_1_1_ctr),</a>
+<a name="592"><span class="lineNum">     592 </span>            :     .io_w_req_bits_waymask    (per_bank_update_way_mask_1)</a>
+<a name="593"><span class="lineNum">     593 </span>            :   );</a>
+<a name="594"><span class="lineNum">     594 </span>            :   FoldedSRAMTemplate_1 table_banks_2 (</a>
+<a name="595"><span class="lineNum">     595 </span>            :     .clock                    (clock),</a>
+<a name="596"><span class="lineNum">     596 </span>            :     .reset                    (reset),</a>
+<a name="597"><span class="lineNum">     597 </span>            :     .io_r_req_ready           (_table_banks_2_io_r_req_ready),</a>
+<a name="598"><span class="lineNum">     598 </span>            :     .io_r_req_valid           (_s1_bank_req_1h_T &amp; s0_bank_req_1h_2),</a>
+<a name="599"><span class="lineNum">     599 </span>            :     .io_r_req_bits_setIdx     (s0_idx[10:2]),</a>
+<a name="600"><span class="lineNum">     600 </span>            :     .io_r_resp_data_0_valid   (_table_banks_2_io_r_resp_data_0_valid),</a>
+<a name="601"><span class="lineNum">     601 </span>            :     .io_r_resp_data_0_tag     (_table_banks_2_io_r_resp_data_0_tag),</a>
+<a name="602"><span class="lineNum">     602 </span>            :     .io_r_resp_data_0_ctr     (_table_banks_2_io_r_resp_data_0_ctr),</a>
+<a name="603"><span class="lineNum">     603 </span>            :     .io_r_resp_data_1_valid   (_table_banks_2_io_r_resp_data_1_valid),</a>
+<a name="604"><span class="lineNum">     604 </span>            :     .io_r_resp_data_1_tag     (_table_banks_2_io_r_resp_data_1_tag),</a>
+<a name="605"><span class="lineNum">     605 </span>            :     .io_r_resp_data_1_ctr     (_table_banks_2_io_r_resp_data_1_ctr),</a>
+<a name="606"><span class="lineNum">     606 </span>            :     .io_w_req_valid           (_s1_bank_has_write_on_this_req_WIRE_2),</a>
+<a name="607"><span class="lineNum">     607 </span>            :     .io_w_req_bits_setIdx     (update_idx[10:2]),</a>
+<a name="608"><span class="lineNum">     608 </span>            :     .io_w_req_bits_data_0_tag (update_tag),</a>
+<a name="609"><span class="lineNum">     609 </span>            :     .io_w_req_bits_data_0_ctr (per_bank_update_wdata_2_0_ctr),</a>
+<a name="610"><span class="lineNum">     610 </span>            :     .io_w_req_bits_data_1_tag (update_tag),</a>
+<a name="611"><span class="lineNum">     611 </span>            :     .io_w_req_bits_data_1_ctr (per_bank_update_wdata_2_1_ctr),</a>
+<a name="612"><span class="lineNum">     612 </span>            :     .io_w_req_bits_waymask    (per_bank_update_way_mask_2)</a>
+<a name="613"><span class="lineNum">     613 </span>            :   );</a>
+<a name="614"><span class="lineNum">     614 </span>            :   FoldedSRAMTemplate_1 table_banks_3 (</a>
+<a name="615"><span class="lineNum">     615 </span>            :     .clock                    (clock),</a>
+<a name="616"><span class="lineNum">     616 </span>            :     .reset                    (reset),</a>
+<a name="617"><span class="lineNum">     617 </span>            :     .io_r_req_ready           (_table_banks_3_io_r_req_ready),</a>
+<a name="618"><span class="lineNum">     618 </span>            :     .io_r_req_valid           (_s1_bank_req_1h_T &amp; (&amp;(s0_idx[1:0]))),</a>
+<a name="619"><span class="lineNum">     619 </span>            :     .io_r_req_bits_setIdx     (s0_idx[10:2]),</a>
+<a name="620"><span class="lineNum">     620 </span>            :     .io_r_resp_data_0_valid   (_table_banks_3_io_r_resp_data_0_valid),</a>
+<a name="621"><span class="lineNum">     621 </span>            :     .io_r_resp_data_0_tag     (_table_banks_3_io_r_resp_data_0_tag),</a>
+<a name="622"><span class="lineNum">     622 </span>            :     .io_r_resp_data_0_ctr     (_table_banks_3_io_r_resp_data_0_ctr),</a>
+<a name="623"><span class="lineNum">     623 </span>            :     .io_r_resp_data_1_valid   (_table_banks_3_io_r_resp_data_1_valid),</a>
+<a name="624"><span class="lineNum">     624 </span>            :     .io_r_resp_data_1_tag     (_table_banks_3_io_r_resp_data_1_tag),</a>
+<a name="625"><span class="lineNum">     625 </span>            :     .io_r_resp_data_1_ctr     (_table_banks_3_io_r_resp_data_1_ctr),</a>
+<a name="626"><span class="lineNum">     626 </span>            :     .io_w_req_valid           (_s1_bank_has_write_on_this_req_WIRE_3),</a>
+<a name="627"><span class="lineNum">     627 </span>            :     .io_w_req_bits_setIdx     (update_idx[10:2]),</a>
+<a name="628"><span class="lineNum">     628 </span>            :     .io_w_req_bits_data_0_tag (update_tag),</a>
+<a name="629"><span class="lineNum">     629 </span>            :     .io_w_req_bits_data_0_ctr (per_bank_update_wdata_3_0_ctr),</a>
+<a name="630"><span class="lineNum">     630 </span>            :     .io_w_req_bits_data_1_tag (update_tag),</a>
+<a name="631"><span class="lineNum">     631 </span>            :     .io_w_req_bits_data_1_ctr (per_bank_update_wdata_3_1_ctr),</a>
+<a name="632"><span class="lineNum">     632 </span>            :     .io_w_req_bits_waymask    (per_bank_update_way_mask_3)</a>
+<a name="633"><span class="lineNum">     633 </span>            :   );</a>
+<a name="634"><span class="lineNum">     634 </span>            :   WrBypass bank_wrbypasses_0_0 (</a>
+<a name="635"><span class="lineNum">     635 </span>            :     .clock               (clock),</a>
+<a name="636"><span class="lineNum">     636 </span>            :     .reset               (reset),</a>
+<a name="637"><span class="lineNum">     637 </span>            :     .io_wen              (io_update_mask_0 &amp; update_req_bank_1h_0),</a>
+<a name="638"><span class="lineNum">     638 </span>            :     .io_write_idx        (update_idx[10:2]),</a>
+<a name="639"><span class="lineNum">     639 </span>            :     .io_write_data_0</a>
+<a name="640"><span class="lineNum">     640 </span>            :       ((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_0_0_ctr)</a>
+<a name="641"><span class="lineNum">     641 </span>            :        | (io_update_pc[1] ? per_bank_update_wdata_0_1_ctr : 3'h0)),</a>
+<a name="642"><span class="lineNum">     642 </span>            :     .io_hit              (_bank_wrbypasses_0_0_io_hit),</a>
+<a name="643"><span class="lineNum">     643 </span>            :     .io_hit_data_0_valid (_bank_wrbypasses_0_0_io_hit_data_0_valid),</a>
+<a name="644"><span class="lineNum">     644 </span>            :     .io_hit_data_0_bits  (_bank_wrbypasses_0_0_io_hit_data_0_bits)</a>
+<a name="645"><span class="lineNum">     645 </span>            :   );</a>
+<a name="646"><span class="lineNum">     646 </span>            :   WrBypass bank_wrbypasses_0_1 (</a>
+<a name="647"><span class="lineNum">     647 </span>            :     .clock               (clock),</a>
+<a name="648"><span class="lineNum">     648 </span>            :     .reset               (reset),</a>
+<a name="649"><span class="lineNum">     649 </span>            :     .io_wen              (io_update_mask_1 &amp; update_req_bank_1h_0),</a>
+<a name="650"><span class="lineNum">     650 </span>            :     .io_write_idx        (update_idx[10:2]),</a>
+<a name="651"><span class="lineNum">     651 </span>            :     .io_write_data_0</a>
+<a name="652"><span class="lineNum">     652 </span>            :       ((io_update_pc[1] ? per_bank_update_wdata_0_0_ctr : 3'h0)</a>
+<a name="653"><span class="lineNum">     653 </span>            :        | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_0_1_ctr)),</a>
+<a name="654"><span class="lineNum">     654 </span>            :     .io_hit              (_bank_wrbypasses_0_1_io_hit),</a>
+<a name="655"><span class="lineNum">     655 </span>            :     .io_hit_data_0_valid (_bank_wrbypasses_0_1_io_hit_data_0_valid),</a>
+<a name="656"><span class="lineNum">     656 </span>            :     .io_hit_data_0_bits  (_bank_wrbypasses_0_1_io_hit_data_0_bits)</a>
+<a name="657"><span class="lineNum">     657 </span>            :   );</a>
+<a name="658"><span class="lineNum">     658 </span>            :   WrBypass bank_wrbypasses_1_0 (</a>
+<a name="659"><span class="lineNum">     659 </span>            :     .clock               (clock),</a>
+<a name="660"><span class="lineNum">     660 </span>            :     .reset               (reset),</a>
+<a name="661"><span class="lineNum">     661 </span>            :     .io_wen              (io_update_mask_0 &amp; update_req_bank_1h_1),</a>
+<a name="662"><span class="lineNum">     662 </span>            :     .io_write_idx        (update_idx[10:2]),</a>
+<a name="663"><span class="lineNum">     663 </span>            :     .io_write_data_0</a>
+<a name="664"><span class="lineNum">     664 </span>            :       ((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_1_0_ctr)</a>
+<a name="665"><span class="lineNum">     665 </span>            :        | (io_update_pc[1] ? per_bank_update_wdata_1_1_ctr : 3'h0)),</a>
+<a name="666"><span class="lineNum">     666 </span>            :     .io_hit              (_bank_wrbypasses_1_0_io_hit),</a>
+<a name="667"><span class="lineNum">     667 </span>            :     .io_hit_data_0_valid (_bank_wrbypasses_1_0_io_hit_data_0_valid),</a>
+<a name="668"><span class="lineNum">     668 </span>            :     .io_hit_data_0_bits  (_bank_wrbypasses_1_0_io_hit_data_0_bits)</a>
+<a name="669"><span class="lineNum">     669 </span>            :   );</a>
+<a name="670"><span class="lineNum">     670 </span>            :   WrBypass bank_wrbypasses_1_1 (</a>
+<a name="671"><span class="lineNum">     671 </span>            :     .clock               (clock),</a>
+<a name="672"><span class="lineNum">     672 </span>            :     .reset               (reset),</a>
+<a name="673"><span class="lineNum">     673 </span>            :     .io_wen              (io_update_mask_1 &amp; update_req_bank_1h_1),</a>
+<a name="674"><span class="lineNum">     674 </span>            :     .io_write_idx        (update_idx[10:2]),</a>
+<a name="675"><span class="lineNum">     675 </span>            :     .io_write_data_0</a>
+<a name="676"><span class="lineNum">     676 </span>            :       ((io_update_pc[1] ? per_bank_update_wdata_1_0_ctr : 3'h0)</a>
+<a name="677"><span class="lineNum">     677 </span>            :        | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_1_1_ctr)),</a>
+<a name="678"><span class="lineNum">     678 </span>            :     .io_hit              (_bank_wrbypasses_1_1_io_hit),</a>
+<a name="679"><span class="lineNum">     679 </span>            :     .io_hit_data_0_valid (_bank_wrbypasses_1_1_io_hit_data_0_valid),</a>
+<a name="680"><span class="lineNum">     680 </span>            :     .io_hit_data_0_bits  (_bank_wrbypasses_1_1_io_hit_data_0_bits)</a>
+<a name="681"><span class="lineNum">     681 </span>            :   );</a>
+<a name="682"><span class="lineNum">     682 </span>            :   WrBypass bank_wrbypasses_2_0 (</a>
+<a name="683"><span class="lineNum">     683 </span>            :     .clock               (clock),</a>
+<a name="684"><span class="lineNum">     684 </span>            :     .reset               (reset),</a>
+<a name="685"><span class="lineNum">     685 </span>            :     .io_wen              (io_update_mask_0 &amp; update_req_bank_1h_2),</a>
+<a name="686"><span class="lineNum">     686 </span>            :     .io_write_idx        (update_idx[10:2]),</a>
+<a name="687"><span class="lineNum">     687 </span>            :     .io_write_data_0</a>
+<a name="688"><span class="lineNum">     688 </span>            :       ((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_2_0_ctr)</a>
+<a name="689"><span class="lineNum">     689 </span>            :        | (io_update_pc[1] ? per_bank_update_wdata_2_1_ctr : 3'h0)),</a>
+<a name="690"><span class="lineNum">     690 </span>            :     .io_hit              (_bank_wrbypasses_2_0_io_hit),</a>
+<a name="691"><span class="lineNum">     691 </span>            :     .io_hit_data_0_valid (_bank_wrbypasses_2_0_io_hit_data_0_valid),</a>
+<a name="692"><span class="lineNum">     692 </span>            :     .io_hit_data_0_bits  (_bank_wrbypasses_2_0_io_hit_data_0_bits)</a>
+<a name="693"><span class="lineNum">     693 </span>            :   );</a>
+<a name="694"><span class="lineNum">     694 </span>            :   WrBypass bank_wrbypasses_2_1 (</a>
+<a name="695"><span class="lineNum">     695 </span>            :     .clock               (clock),</a>
+<a name="696"><span class="lineNum">     696 </span>            :     .reset               (reset),</a>
+<a name="697"><span class="lineNum">     697 </span>            :     .io_wen              (io_update_mask_1 &amp; update_req_bank_1h_2),</a>
+<a name="698"><span class="lineNum">     698 </span>            :     .io_write_idx        (update_idx[10:2]),</a>
+<a name="699"><span class="lineNum">     699 </span>            :     .io_write_data_0</a>
+<a name="700"><span class="lineNum">     700 </span>            :       ((io_update_pc[1] ? per_bank_update_wdata_2_0_ctr : 3'h0)</a>
+<a name="701"><span class="lineNum">     701 </span>            :        | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_2_1_ctr)),</a>
+<a name="702"><span class="lineNum">     702 </span>            :     .io_hit              (_bank_wrbypasses_2_1_io_hit),</a>
+<a name="703"><span class="lineNum">     703 </span>            :     .io_hit_data_0_valid (_bank_wrbypasses_2_1_io_hit_data_0_valid),</a>
+<a name="704"><span class="lineNum">     704 </span>            :     .io_hit_data_0_bits  (_bank_wrbypasses_2_1_io_hit_data_0_bits)</a>
+<a name="705"><span class="lineNum">     705 </span>            :   );</a>
+<a name="706"><span class="lineNum">     706 </span>            :   WrBypass bank_wrbypasses_3_0 (</a>
+<a name="707"><span class="lineNum">     707 </span>            :     .clock               (clock),</a>
+<a name="708"><span class="lineNum">     708 </span>            :     .reset               (reset),</a>
+<a name="709"><span class="lineNum">     709 </span>            :     .io_wen              (io_update_mask_0 &amp; (&amp;(update_idx[1:0]))),</a>
+<a name="710"><span class="lineNum">     710 </span>            :     .io_write_idx        (update_idx[10:2]),</a>
+<a name="711"><span class="lineNum">     711 </span>            :     .io_write_data_0</a>
+<a name="712"><span class="lineNum">     712 </span>            :       ((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_3_0_ctr)</a>
+<a name="713"><span class="lineNum">     713 </span>            :        | (io_update_pc[1] ? per_bank_update_wdata_3_1_ctr : 3'h0)),</a>
+<a name="714"><span class="lineNum">     714 </span>            :     .io_hit              (_bank_wrbypasses_3_0_io_hit),</a>
+<a name="715"><span class="lineNum">     715 </span>            :     .io_hit_data_0_valid (_bank_wrbypasses_3_0_io_hit_data_0_valid),</a>
+<a name="716"><span class="lineNum">     716 </span>            :     .io_hit_data_0_bits  (_bank_wrbypasses_3_0_io_hit_data_0_bits)</a>
+<a name="717"><span class="lineNum">     717 </span>            :   );</a>
+<a name="718"><span class="lineNum">     718 </span>            :   WrBypass bank_wrbypasses_3_1 (</a>
+<a name="719"><span class="lineNum">     719 </span>            :     .clock               (clock),</a>
+<a name="720"><span class="lineNum">     720 </span>            :     .reset               (reset),</a>
+<a name="721"><span class="lineNum">     721 </span>            :     .io_wen              (io_update_mask_1 &amp; (&amp;(update_idx[1:0]))),</a>
+<a name="722"><span class="lineNum">     722 </span>            :     .io_write_idx        (update_idx[10:2]),</a>
+<a name="723"><span class="lineNum">     723 </span>            :     .io_write_data_0</a>
+<a name="724"><span class="lineNum">     724 </span>            :       ((io_update_pc[1] ? per_bank_update_wdata_3_0_ctr : 3'h0)</a>
+<a name="725"><span class="lineNum">     725 </span>            :        | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_3_1_ctr)),</a>
+<a name="726"><span class="lineNum">     726 </span>            :     .io_hit              (_bank_wrbypasses_3_1_io_hit),</a>
+<a name="727"><span class="lineNum">     727 </span>            :     .io_hit_data_0_valid (_bank_wrbypasses_3_1_io_hit_data_0_valid),</a>
+<a name="728"><span class="lineNum">     728 </span>            :     .io_hit_data_0_bits  (_bank_wrbypasses_3_1_io_hit_data_0_bits)</a>
+<a name="729"><span class="lineNum">     729 </span>            :   );</a>
+<a name="730"><span class="lineNum">     730 </span>            :   assign io_req_ready = ~powerOnResetState;</a>
+<a name="731"><span class="lineNum">     731 </span>            :   assign io_resps_0_valid =</a>
+<a name="732"><span class="lineNum">     732 </span>            :     ~(s1_unhashed_idx[0]) &amp; _hit_selected_T_6 | s1_unhashed_idx[0] &amp; _hit_selected_T_13;</a>
+<a name="733"><span class="lineNum">     733 </span>            :   assign io_resps_0_bits_ctr =</a>
+<a name="734"><span class="lineNum">     734 </span>            :     (s1_unhashed_idx[0] ? 3'h0 : _resp_selected_T_6)</a>
+<a name="735"><span class="lineNum">     735 </span>            :     | (s1_unhashed_idx[0] ? _resp_selected_T_27 : 3'h0);</a>
+<a name="736"><span class="lineNum">     736 </span>            :   assign io_resps_0_bits_u =</a>
+<a name="737"><span class="lineNum">     737 </span>            :     ~(s1_unhashed_idx[0]) &amp; _us_io_r_resp_data_0 | s1_unhashed_idx[0]</a>
+<a name="738"><span class="lineNum">     738 </span>            :     &amp; _us_io_r_resp_data_1;</a>
+<a name="739"><span class="lineNum">     739 </span>            :   assign io_resps_0_bits_unconf =</a>
+<a name="740"><span class="lineNum">     740 </span>            :     ~(s1_unhashed_idx[0]) &amp; _unconf_selected_T_6 | s1_unhashed_idx[0]</a>
+<a name="741"><span class="lineNum">     741 </span>            :     &amp; _unconf_selected_T_13;</a>
+<a name="742"><span class="lineNum">     742 </span>            :   assign io_resps_1_valid =</a>
+<a name="743"><span class="lineNum">     743 </span>            :     s1_unhashed_idx[0] &amp; _hit_selected_T_6 | ~(s1_unhashed_idx[0]) &amp; _hit_selected_T_13;</a>
+<a name="744"><span class="lineNum">     744 </span>            :   assign io_resps_1_bits_ctr =</a>
+<a name="745"><span class="lineNum">     745 </span>            :     (s1_unhashed_idx[0] ? _resp_selected_T_6 : 3'h0)</a>
+<a name="746"><span class="lineNum">     746 </span>            :     | (s1_unhashed_idx[0] ? 3'h0 : _resp_selected_T_27);</a>
+<a name="747"><span class="lineNum">     747 </span>            :   assign io_resps_1_bits_u =</a>
+<a name="748"><span class="lineNum">     748 </span>            :     s1_unhashed_idx[0] &amp; _us_io_r_resp_data_0 | ~(s1_unhashed_idx[0])</a>
+<a name="749"><span class="lineNum">     749 </span>            :     &amp; _us_io_r_resp_data_1;</a>
+<a name="750"><span class="lineNum">     750 </span>            :   assign io_resps_1_bits_unconf =</a>
+<a name="751"><span class="lineNum">     751 </span>            :     s1_unhashed_idx[0] &amp; _unconf_selected_T_6 | ~(s1_unhashed_idx[0])</a>
+<a name="752"><span class="lineNum">     752 </span>            :     &amp; _unconf_selected_T_13;</a>
+<a name="753"><span class="lineNum">     753 </span>            : endmodule</a>
+<a name="754"><span class="lineNum">     754 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/TageTable_3.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/TageTable_3.sv.func-sort-c.html
new file mode 100644
index 0000000..448963a
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/TageTable_3.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/TageTable_3.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - TageTable_3.sv<span style="font-size: 80%;"> (<a href="TageTable_3.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">107</td>
+            <td class="headerCovTableEntry">107</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="TageTable_3.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/TageTable_3.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/TageTable_3.sv.func.html
new file mode 100644
index 0000000..693d778
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/TageTable_3.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/TageTable_3.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - TageTable_3.sv<span style="font-size: 80%;"> (<a href="TageTable_3.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">107</td>
+            <td class="headerCovTableEntry">107</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="TageTable_3.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/TageTable_3.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/TageTable_3.sv.gcov.html
new file mode 100644
index 0000000..f5e9e99
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/TageTable_3.sv.gcov.html
@@ -0,0 +1,830 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/TageTable_3.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - TageTable_3.sv<span style="font-size: 80%;"> (source / <a href="TageTable_3.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">107</td>
+            <td class="headerCovTableEntry">107</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : module TageTable_3(</a>
+<a name="59"><span class="lineNum">      59 </span><span class="lineCov">     127786 :   input         clock,</span></a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">         62 :   input         reset,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">         54 :   output        io_req_ready,</span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">         76 :   input         io_req_valid,</span></a>
+<a name="63"><span class="lineNum">      63 </span><span class="lineCov">      10224 :   input  [40:0] io_req_bits_pc,</span></a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">       1102 :   input  [10:0] io_req_bits_folded_hist_hist_16_folded_hist,</span></a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">        930 :   input  [7:0]  io_req_bits_folded_hist_hist_8_folded_hist,</span></a>
+<a name="66"><span class="lineNum">      66 </span><span class="lineCov">        711 :   input  [6:0]  io_req_bits_folded_hist_hist_5_folded_hist,</span></a>
+<a name="67"><span class="lineNum">      67 </span><span class="lineCov">         14 :   output        io_resps_0_valid,</span></a>
+<a name="68"><span class="lineNum">      68 </span><span class="lineCov">        100 :   output [2:0]  io_resps_0_bits_ctr,</span></a>
+<a name="69"><span class="lineNum">      69 </span><span class="lineCov">         29 :   output        io_resps_0_bits_u,</span></a>
+<a name="70"><span class="lineNum">      70 </span><span class="lineCov">         26 :   output        io_resps_0_bits_unconf,</span></a>
+<a name="71"><span class="lineNum">      71 </span><span class="lineCov">         16 :   output        io_resps_1_valid,</span></a>
+<a name="72"><span class="lineNum">      72 </span><span class="lineCov">        107 :   output [2:0]  io_resps_1_bits_ctr,</span></a>
+<a name="73"><span class="lineNum">      73 </span><span class="lineCov">         29 :   output        io_resps_1_bits_u,</span></a>
+<a name="74"><span class="lineNum">      74 </span><span class="lineCov">         23 :   output        io_resps_1_bits_unconf,</span></a>
+<a name="75"><span class="lineNum">      75 </span><span class="lineCov">        641 :   input  [40:0] io_update_pc,</span></a>
+<a name="76"><span class="lineNum">      76 </span><span class="lineCov">        185 :   input  [10:0] io_update_folded_hist_hist_16_folded_hist,</span></a>
+<a name="77"><span class="lineNum">      77 </span><span class="lineCov">        121 :   input  [7:0]  io_update_folded_hist_hist_8_folded_hist,</span></a>
+<a name="78"><span class="lineNum">      78 </span><span class="lineCov">        102 :   input  [6:0]  io_update_folded_hist_hist_5_folded_hist,</span></a>
+<a name="79"><span class="lineNum">      79 </span><span class="lineCov">         30 :   input         io_update_mask_0,</span></a>
+<a name="80"><span class="lineNum">      80 </span><span class="lineCov">         31 :   input         io_update_mask_1,</span></a>
+<a name="81"><span class="lineNum">      81 </span><span class="lineCov">         12 :   input         io_update_takens_0,</span></a>
+<a name="82"><span class="lineNum">      82 </span><span class="lineCov">         17 :   input         io_update_takens_1,</span></a>
+<a name="83"><span class="lineNum">      83 </span><span class="lineCov">         15 :   input         io_update_alloc_0,</span></a>
+<a name="84"><span class="lineNum">      84 </span><span class="lineCov">         16 :   input         io_update_alloc_1,</span></a>
+<a name="85"><span class="lineNum">      85 </span><span class="lineCov">         49 :   input  [2:0]  io_update_oldCtrs_0,</span></a>
+<a name="86"><span class="lineNum">      86 </span><span class="lineCov">         52 :   input  [2:0]  io_update_oldCtrs_1,</span></a>
+<a name="87"><span class="lineNum">      87 </span><span class="lineCov">         17 :   input         io_update_uMask_0,</span></a>
+<a name="88"><span class="lineNum">      88 </span><span class="lineCov">         14 :   input         io_update_uMask_1,</span></a>
+<a name="89"><span class="lineNum">      89 </span><span class="lineCov">         16 :   input         io_update_us_0,</span></a>
+<a name="90"><span class="lineNum">      90 </span><span class="lineCov">         22 :   input         io_update_us_1,</span></a>
+<a name="91"><span class="lineNum">      91 </span><span class="lineCov">         28 :   input         io_update_reset_u_0,</span></a>
+<a name="92"><span class="lineNum">      92 </span><span class="lineCov">         23 :   input         io_update_reset_u_1</span></a>
+<a name="93"><span class="lineNum">      93 </span>            : );</a>
+<a name="94"><span class="lineNum">      94 </span>            : </a>
+<a name="95"><span class="lineNum">      95 </span><span class="lineCov">         18 :   wire        per_bank_not_silent_update_3_1;</span></a>
+<a name="96"><span class="lineNum">      96 </span><span class="lineCov">         16 :   wire        per_bank_not_silent_update_3_0;</span></a>
+<a name="97"><span class="lineNum">      97 </span><span class="lineCov">         18 :   wire        per_bank_not_silent_update_2_1;</span></a>
+<a name="98"><span class="lineNum">      98 </span><span class="lineCov">         16 :   wire        per_bank_not_silent_update_2_0;</span></a>
+<a name="99"><span class="lineNum">      99 </span><span class="lineCov">         15 :   wire        per_bank_not_silent_update_1_1;</span></a>
+<a name="100"><span class="lineNum">     100 </span><span class="lineCov">         12 :   wire        per_bank_not_silent_update_1_0;</span></a>
+<a name="101"><span class="lineNum">     101 </span><span class="lineCov">         19 :   wire        per_bank_not_silent_update_0_1;</span></a>
+<a name="102"><span class="lineNum">     102 </span><span class="lineCov">         13 :   wire        per_bank_not_silent_update_0_0;</span></a>
+<a name="103"><span class="lineNum">     103 </span><span class="lineCov">         54 :   reg         powerOnResetState;</span></a>
+<a name="104"><span class="lineNum">     104 </span>            :   wire        _resp_invalid_by_write_T_6;</a>
+<a name="105"><span class="lineNum">     105 </span>            :   wire        _bank_wrbypasses_3_1_io_hit;</a>
+<a name="106"><span class="lineNum">     106 </span>            :   wire        _bank_wrbypasses_3_1_io_hit_data_0_valid;</a>
+<a name="107"><span class="lineNum">     107 </span>            :   wire [2:0]  _bank_wrbypasses_3_1_io_hit_data_0_bits;</a>
+<a name="108"><span class="lineNum">     108 </span>            :   wire        _bank_wrbypasses_3_0_io_hit;</a>
+<a name="109"><span class="lineNum">     109 </span>            :   wire        _bank_wrbypasses_3_0_io_hit_data_0_valid;</a>
+<a name="110"><span class="lineNum">     110 </span>            :   wire [2:0]  _bank_wrbypasses_3_0_io_hit_data_0_bits;</a>
+<a name="111"><span class="lineNum">     111 </span>            :   wire        _bank_wrbypasses_2_1_io_hit;</a>
+<a name="112"><span class="lineNum">     112 </span>            :   wire        _bank_wrbypasses_2_1_io_hit_data_0_valid;</a>
+<a name="113"><span class="lineNum">     113 </span>            :   wire [2:0]  _bank_wrbypasses_2_1_io_hit_data_0_bits;</a>
+<a name="114"><span class="lineNum">     114 </span>            :   wire        _bank_wrbypasses_2_0_io_hit;</a>
+<a name="115"><span class="lineNum">     115 </span>            :   wire        _bank_wrbypasses_2_0_io_hit_data_0_valid;</a>
+<a name="116"><span class="lineNum">     116 </span>            :   wire [2:0]  _bank_wrbypasses_2_0_io_hit_data_0_bits;</a>
+<a name="117"><span class="lineNum">     117 </span>            :   wire        _bank_wrbypasses_1_1_io_hit;</a>
+<a name="118"><span class="lineNum">     118 </span>            :   wire        _bank_wrbypasses_1_1_io_hit_data_0_valid;</a>
+<a name="119"><span class="lineNum">     119 </span>            :   wire [2:0]  _bank_wrbypasses_1_1_io_hit_data_0_bits;</a>
+<a name="120"><span class="lineNum">     120 </span>            :   wire        _bank_wrbypasses_1_0_io_hit;</a>
+<a name="121"><span class="lineNum">     121 </span>            :   wire        _bank_wrbypasses_1_0_io_hit_data_0_valid;</a>
+<a name="122"><span class="lineNum">     122 </span>            :   wire [2:0]  _bank_wrbypasses_1_0_io_hit_data_0_bits;</a>
+<a name="123"><span class="lineNum">     123 </span>            :   wire        _bank_wrbypasses_0_1_io_hit;</a>
+<a name="124"><span class="lineNum">     124 </span>            :   wire        _bank_wrbypasses_0_1_io_hit_data_0_valid;</a>
+<a name="125"><span class="lineNum">     125 </span>            :   wire [2:0]  _bank_wrbypasses_0_1_io_hit_data_0_bits;</a>
+<a name="126"><span class="lineNum">     126 </span>            :   wire        _bank_wrbypasses_0_0_io_hit;</a>
+<a name="127"><span class="lineNum">     127 </span>            :   wire        _bank_wrbypasses_0_0_io_hit_data_0_valid;</a>
+<a name="128"><span class="lineNum">     128 </span>            :   wire [2:0]  _bank_wrbypasses_0_0_io_hit_data_0_bits;</a>
+<a name="129"><span class="lineNum">     129 </span>            :   wire        _table_banks_3_io_r_req_ready;</a>
+<a name="130"><span class="lineNum">     130 </span>            :   wire        _table_banks_3_io_r_resp_data_0_valid;</a>
+<a name="131"><span class="lineNum">     131 </span>            :   wire [7:0]  _table_banks_3_io_r_resp_data_0_tag;</a>
+<a name="132"><span class="lineNum">     132 </span>            :   wire [2:0]  _table_banks_3_io_r_resp_data_0_ctr;</a>
+<a name="133"><span class="lineNum">     133 </span>            :   wire        _table_banks_3_io_r_resp_data_1_valid;</a>
+<a name="134"><span class="lineNum">     134 </span>            :   wire [7:0]  _table_banks_3_io_r_resp_data_1_tag;</a>
+<a name="135"><span class="lineNum">     135 </span>            :   wire [2:0]  _table_banks_3_io_r_resp_data_1_ctr;</a>
+<a name="136"><span class="lineNum">     136 </span>            :   wire        _table_banks_2_io_r_req_ready;</a>
+<a name="137"><span class="lineNum">     137 </span>            :   wire        _table_banks_2_io_r_resp_data_0_valid;</a>
+<a name="138"><span class="lineNum">     138 </span>            :   wire [7:0]  _table_banks_2_io_r_resp_data_0_tag;</a>
+<a name="139"><span class="lineNum">     139 </span>            :   wire [2:0]  _table_banks_2_io_r_resp_data_0_ctr;</a>
+<a name="140"><span class="lineNum">     140 </span>            :   wire        _table_banks_2_io_r_resp_data_1_valid;</a>
+<a name="141"><span class="lineNum">     141 </span>            :   wire [7:0]  _table_banks_2_io_r_resp_data_1_tag;</a>
+<a name="142"><span class="lineNum">     142 </span>            :   wire [2:0]  _table_banks_2_io_r_resp_data_1_ctr;</a>
+<a name="143"><span class="lineNum">     143 </span>            :   wire        _table_banks_1_io_r_req_ready;</a>
+<a name="144"><span class="lineNum">     144 </span>            :   wire        _table_banks_1_io_r_resp_data_0_valid;</a>
+<a name="145"><span class="lineNum">     145 </span>            :   wire [7:0]  _table_banks_1_io_r_resp_data_0_tag;</a>
+<a name="146"><span class="lineNum">     146 </span>            :   wire [2:0]  _table_banks_1_io_r_resp_data_0_ctr;</a>
+<a name="147"><span class="lineNum">     147 </span>            :   wire        _table_banks_1_io_r_resp_data_1_valid;</a>
+<a name="148"><span class="lineNum">     148 </span>            :   wire [7:0]  _table_banks_1_io_r_resp_data_1_tag;</a>
+<a name="149"><span class="lineNum">     149 </span>            :   wire [2:0]  _table_banks_1_io_r_resp_data_1_ctr;</a>
+<a name="150"><span class="lineNum">     150 </span>            :   wire        _table_banks_0_io_r_req_ready;</a>
+<a name="151"><span class="lineNum">     151 </span>            :   wire        _table_banks_0_io_r_resp_data_0_valid;</a>
+<a name="152"><span class="lineNum">     152 </span>            :   wire [7:0]  _table_banks_0_io_r_resp_data_0_tag;</a>
+<a name="153"><span class="lineNum">     153 </span>            :   wire [2:0]  _table_banks_0_io_r_resp_data_0_ctr;</a>
+<a name="154"><span class="lineNum">     154 </span>            :   wire        _table_banks_0_io_r_resp_data_1_valid;</a>
+<a name="155"><span class="lineNum">     155 </span>            :   wire [7:0]  _table_banks_0_io_r_resp_data_1_tag;</a>
+<a name="156"><span class="lineNum">     156 </span>            :   wire [2:0]  _table_banks_0_io_r_resp_data_1_ctr;</a>
+<a name="157"><span class="lineNum">     157 </span>            :   wire        _us_io_r_req_ready;</a>
+<a name="158"><span class="lineNum">     158 </span>            :   wire        _us_io_r_resp_data_0;</a>
+<a name="159"><span class="lineNum">     159 </span>            :   wire        _us_io_r_resp_data_1;</a>
+<a name="160"><span class="lineNum">     160 </span>            :   wire        _us_extra_reset_T_1 = io_update_mask_0 | io_update_mask_1;</a>
+<a name="161"><span class="lineNum">     161 </span><span class="lineCov">      26388 :   wire [10:0] s0_idx = io_req_bits_pc[11:1] ^ io_req_bits_folded_hist_hist_16_folded_hist;</span></a>
+<a name="162"><span class="lineNum">     162 </span><span class="lineCov">         74 :   wire        s0_bank_req_1h_0 = s0_idx[1:0] == 2'h0;</span></a>
+<a name="163"><span class="lineNum">     163 </span><span class="lineCov">         56 :   wire        s0_bank_req_1h_1 = s0_idx[1:0] == 2'h1;</span></a>
+<a name="164"><span class="lineNum">     164 </span><span class="lineCov">         47 :   wire        s0_bank_req_1h_2 = s0_idx[1:0] == 2'h2;</span></a>
+<a name="165"><span class="lineNum">     165 </span>            :   wire        _s1_bank_req_1h_T = ~powerOnResetState &amp; io_req_valid;</a>
+<a name="166"><span class="lineNum">     166 </span><span class="lineCov">       9319 :   reg  [39:0] s1_unhashed_idx;</span></a>
+<a name="167"><span class="lineNum">     167 </span><span class="lineCov">       8003 :   reg  [7:0]  s1_tag;</span></a>
+<a name="168"><span class="lineNum">     168 </span><span class="lineCov">         42 :   reg         s1_bank_req_1h_0;</span></a>
+<a name="169"><span class="lineNum">     169 </span><span class="lineCov">         44 :   reg         s1_bank_req_1h_1;</span></a>
+<a name="170"><span class="lineNum">     170 </span><span class="lineCov">         38 :   reg         s1_bank_req_1h_2;</span></a>
+<a name="171"><span class="lineNum">     171 </span><span class="lineCov">         34 :   reg         s1_bank_req_1h_3;</span></a>
+<a name="172"><span class="lineNum">     172 </span><span class="lineCov">         31 :   reg         s1_bank_has_write_on_this_req_0;</span></a>
+<a name="173"><span class="lineNum">     173 </span><span class="lineCov">         31 :   reg         s1_bank_has_write_on_this_req_1;</span></a>
+<a name="174"><span class="lineNum">     174 </span><span class="lineCov">         29 :   reg         s1_bank_has_write_on_this_req_2;</span></a>
+<a name="175"><span class="lineNum">     175 </span><span class="lineCov">         31 :   reg         s1_bank_has_write_on_this_req_3;</span></a>
+<a name="176"><span class="lineNum">     176 </span>            :   wire [2:0]  _resp_selected_T_6 =</a>
+<a name="177"><span class="lineNum">     177 </span>            :     (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_ctr : 3'h0)</a>
+<a name="178"><span class="lineNum">     178 </span>            :     | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 3'h0)</a>
+<a name="179"><span class="lineNum">     179 </span>            :     | (s1_bank_req_1h_2 ? _table_banks_2_io_r_resp_data_0_ctr : 3'h0)</a>
+<a name="180"><span class="lineNum">     180 </span>            :     | (s1_bank_req_1h_3 ? _table_banks_3_io_r_resp_data_0_ctr : 3'h0);</a>
+<a name="181"><span class="lineNum">     181 </span>            :   wire [2:0]  _resp_selected_T_27 =</a>
+<a name="182"><span class="lineNum">     182 </span>            :     (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_1_ctr : 3'h0)</a>
+<a name="183"><span class="lineNum">     183 </span>            :     | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_1_ctr : 3'h0)</a>
+<a name="184"><span class="lineNum">     184 </span>            :     | (s1_bank_req_1h_2 ? _table_banks_2_io_r_resp_data_1_ctr : 3'h0)</a>
+<a name="185"><span class="lineNum">     185 </span>            :     | (s1_bank_req_1h_3 ? _table_banks_3_io_r_resp_data_1_ctr : 3'h0);</a>
+<a name="186"><span class="lineNum">     186 </span>            :   wire        _unconf_selected_T_6 =</a>
+<a name="187"><span class="lineNum">     187 </span>            :     s1_bank_req_1h_0</a>
+<a name="188"><span class="lineNum">     188 </span>            :     &amp; (_table_banks_0_io_r_resp_data_0_ctr == 3'h4</a>
+<a name="189"><span class="lineNum">     189 </span>            :        | _table_banks_0_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_1</a>
+<a name="190"><span class="lineNum">     190 </span>            :     &amp; (_table_banks_1_io_r_resp_data_0_ctr == 3'h4</a>
+<a name="191"><span class="lineNum">     191 </span>            :        | _table_banks_1_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_2</a>
+<a name="192"><span class="lineNum">     192 </span>            :     &amp; (_table_banks_2_io_r_resp_data_0_ctr == 3'h4</a>
+<a name="193"><span class="lineNum">     193 </span>            :        | _table_banks_2_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_3</a>
+<a name="194"><span class="lineNum">     194 </span>            :     &amp; (_table_banks_3_io_r_resp_data_0_ctr == 3'h4</a>
+<a name="195"><span class="lineNum">     195 </span>            :        | _table_banks_3_io_r_resp_data_0_ctr == 3'h3);</a>
+<a name="196"><span class="lineNum">     196 </span>            :   wire        _unconf_selected_T_13 =</a>
+<a name="197"><span class="lineNum">     197 </span>            :     s1_bank_req_1h_0</a>
+<a name="198"><span class="lineNum">     198 </span>            :     &amp; (_table_banks_0_io_r_resp_data_1_ctr == 3'h4</a>
+<a name="199"><span class="lineNum">     199 </span>            :        | _table_banks_0_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_1</a>
+<a name="200"><span class="lineNum">     200 </span>            :     &amp; (_table_banks_1_io_r_resp_data_1_ctr == 3'h4</a>
+<a name="201"><span class="lineNum">     201 </span>            :        | _table_banks_1_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_2</a>
+<a name="202"><span class="lineNum">     202 </span>            :     &amp; (_table_banks_2_io_r_resp_data_1_ctr == 3'h4</a>
+<a name="203"><span class="lineNum">     203 </span>            :        | _table_banks_2_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_3</a>
+<a name="204"><span class="lineNum">     204 </span>            :     &amp; (_table_banks_3_io_r_resp_data_1_ctr == 3'h4</a>
+<a name="205"><span class="lineNum">     205 </span>            :        | _table_banks_3_io_r_resp_data_1_ctr == 3'h3);</a>
+<a name="206"><span class="lineNum">     206 </span>            :   wire        _hit_selected_T_6 =</a>
+<a name="207"><span class="lineNum">     207 </span>            :     s1_bank_req_1h_0 &amp; _table_banks_0_io_r_resp_data_0_tag == s1_tag</a>
+<a name="208"><span class="lineNum">     208 </span>            :     &amp; _table_banks_0_io_r_resp_data_0_valid &amp; ~_resp_invalid_by_write_T_6</a>
+<a name="209"><span class="lineNum">     209 </span>            :     | s1_bank_req_1h_1 &amp; _table_banks_1_io_r_resp_data_0_tag == s1_tag</a>
+<a name="210"><span class="lineNum">     210 </span>            :     &amp; _table_banks_1_io_r_resp_data_0_valid &amp; ~_resp_invalid_by_write_T_6</a>
+<a name="211"><span class="lineNum">     211 </span>            :     | s1_bank_req_1h_2 &amp; _table_banks_2_io_r_resp_data_0_tag == s1_tag</a>
+<a name="212"><span class="lineNum">     212 </span>            :     &amp; _table_banks_2_io_r_resp_data_0_valid &amp; ~_resp_invalid_by_write_T_6</a>
+<a name="213"><span class="lineNum">     213 </span>            :     | s1_bank_req_1h_3 &amp; _table_banks_3_io_r_resp_data_0_tag == s1_tag</a>
+<a name="214"><span class="lineNum">     214 </span>            :     &amp; _table_banks_3_io_r_resp_data_0_valid &amp; ~_resp_invalid_by_write_T_6;</a>
+<a name="215"><span class="lineNum">     215 </span>            :   wire        _hit_selected_T_13 =</a>
+<a name="216"><span class="lineNum">     216 </span>            :     s1_bank_req_1h_0 &amp; _table_banks_0_io_r_resp_data_1_tag == s1_tag</a>
+<a name="217"><span class="lineNum">     217 </span>            :     &amp; _table_banks_0_io_r_resp_data_1_valid &amp; ~_resp_invalid_by_write_T_6</a>
+<a name="218"><span class="lineNum">     218 </span>            :     | s1_bank_req_1h_1 &amp; _table_banks_1_io_r_resp_data_1_tag == s1_tag</a>
+<a name="219"><span class="lineNum">     219 </span>            :     &amp; _table_banks_1_io_r_resp_data_1_valid &amp; ~_resp_invalid_by_write_T_6</a>
+<a name="220"><span class="lineNum">     220 </span>            :     | s1_bank_req_1h_2 &amp; _table_banks_2_io_r_resp_data_1_tag == s1_tag</a>
+<a name="221"><span class="lineNum">     221 </span>            :     &amp; _table_banks_2_io_r_resp_data_1_valid &amp; ~_resp_invalid_by_write_T_6</a>
+<a name="222"><span class="lineNum">     222 </span>            :     | s1_bank_req_1h_3 &amp; _table_banks_3_io_r_resp_data_1_tag == s1_tag</a>
+<a name="223"><span class="lineNum">     223 </span>            :     &amp; _table_banks_3_io_r_resp_data_1_valid &amp; ~_resp_invalid_by_write_T_6;</a>
+<a name="224"><span class="lineNum">     224 </span>            :   assign _resp_invalid_by_write_T_6 =</a>
+<a name="225"><span class="lineNum">     225 </span>            :     s1_bank_req_1h_0 &amp; s1_bank_has_write_on_this_req_0 | s1_bank_req_1h_1</a>
+<a name="226"><span class="lineNum">     226 </span>            :     &amp; s1_bank_has_write_on_this_req_1 | s1_bank_req_1h_2 &amp; s1_bank_has_write_on_this_req_2</a>
+<a name="227"><span class="lineNum">     227 </span>            :     | s1_bank_req_1h_3 &amp; s1_bank_has_write_on_this_req_3;</a>
+<a name="228"><span class="lineNum">     228 </span><span class="lineCov">        323 :   wire [10:0] update_idx = io_update_pc[11:1] ^ io_update_folded_hist_hist_16_folded_hist;</span></a>
+<a name="229"><span class="lineNum">     229 </span><span class="lineCov">        123 :   wire [7:0]  update_tag =</span></a>
+<a name="230"><span class="lineNum">     230 </span>            :     io_update_pc[8:1] ^ io_update_folded_hist_hist_8_folded_hist</a>
+<a name="231"><span class="lineNum">     231 </span>            :     ^ {io_update_folded_hist_hist_5_folded_hist, 1'h0};</a>
+<a name="232"><span class="lineNum">     232 </span><span class="lineCov">         13 :   wire        update_req_bank_1h_0 = update_idx[1:0] == 2'h0;</span></a>
+<a name="233"><span class="lineNum">     233 </span><span class="lineCov">         19 :   wire        update_req_bank_1h_1 = update_idx[1:0] == 2'h1;</span></a>
+<a name="234"><span class="lineNum">     234 </span><span class="lineCov">         17 :   wire        update_req_bank_1h_2 = update_idx[1:0] == 2'h2;</span></a>
+<a name="235"><span class="lineNum">     235 </span><span class="lineCov">         68 :   wire [1:0]  per_bank_update_way_mask_0 =</span></a>
+<a name="236"><span class="lineNum">     236 </span>            :     {(io_update_pc[1] &amp; io_update_mask_0 | ~(io_update_pc[1]) &amp; io_update_mask_1)</a>
+<a name="237"><span class="lineNum">     237 </span>            :        &amp; per_bank_not_silent_update_0_1,</a>
+<a name="238"><span class="lineNum">     238 </span>            :      (~(io_update_pc[1]) &amp; io_update_mask_0 | io_update_pc[1] &amp; io_update_mask_1)</a>
+<a name="239"><span class="lineNum">     239 </span>            :        &amp; per_bank_not_silent_update_0_0};</a>
+<a name="240"><span class="lineNum">     240 </span><span class="lineCov">         57 :   wire [1:0]  per_bank_update_way_mask_1 =</span></a>
+<a name="241"><span class="lineNum">     241 </span>            :     {(io_update_pc[1] &amp; io_update_mask_0 | ~(io_update_pc[1]) &amp; io_update_mask_1)</a>
+<a name="242"><span class="lineNum">     242 </span>            :        &amp; per_bank_not_silent_update_1_1,</a>
+<a name="243"><span class="lineNum">     243 </span>            :      (~(io_update_pc[1]) &amp; io_update_mask_0 | io_update_pc[1] &amp; io_update_mask_1)</a>
+<a name="244"><span class="lineNum">     244 </span>            :        &amp; per_bank_not_silent_update_1_0};</a>
+<a name="245"><span class="lineNum">     245 </span><span class="lineCov">         69 :   wire [1:0]  per_bank_update_way_mask_2 =</span></a>
+<a name="246"><span class="lineNum">     246 </span>            :     {(io_update_pc[1] &amp; io_update_mask_0 | ~(io_update_pc[1]) &amp; io_update_mask_1)</a>
+<a name="247"><span class="lineNum">     247 </span>            :        &amp; per_bank_not_silent_update_2_1,</a>
+<a name="248"><span class="lineNum">     248 </span>            :      (~(io_update_pc[1]) &amp; io_update_mask_0 | io_update_pc[1] &amp; io_update_mask_1)</a>
+<a name="249"><span class="lineNum">     249 </span>            :        &amp; per_bank_not_silent_update_2_0};</a>
+<a name="250"><span class="lineNum">     250 </span><span class="lineCov">         63 :   wire [1:0]  per_bank_update_way_mask_3 =</span></a>
+<a name="251"><span class="lineNum">     251 </span>            :     {(io_update_pc[1] &amp; io_update_mask_0 | ~(io_update_pc[1]) &amp; io_update_mask_1)</a>
+<a name="252"><span class="lineNum">     252 </span>            :        &amp; per_bank_not_silent_update_3_1,</a>
+<a name="253"><span class="lineNum">     253 </span>            :      (~(io_update_pc[1]) &amp; io_update_mask_0 | io_update_pc[1] &amp; io_update_mask_1)</a>
+<a name="254"><span class="lineNum">     254 </span>            :        &amp; per_bank_not_silent_update_3_0};</a>
+<a name="255"><span class="lineNum">     255 </span>            :   wire        _s1_bank_has_write_on_this_req_WIRE_0 =</a>
+<a name="256"><span class="lineNum">     256 </span>            :     (|per_bank_update_way_mask_0) &amp; update_req_bank_1h_0;</a>
+<a name="257"><span class="lineNum">     257 </span>            :   wire        _s1_bank_has_write_on_this_req_WIRE_1 =</a>
+<a name="258"><span class="lineNum">     258 </span>            :     (|per_bank_update_way_mask_1) &amp; update_req_bank_1h_1;</a>
+<a name="259"><span class="lineNum">     259 </span>            :   wire        _s1_bank_has_write_on_this_req_WIRE_2 =</a>
+<a name="260"><span class="lineNum">     260 </span>            :     (|per_bank_update_way_mask_2) &amp; update_req_bank_1h_2;</a>
+<a name="261"><span class="lineNum">     261 </span>            :   wire        _s1_bank_has_write_on_this_req_WIRE_3 =</a>
+<a name="262"><span class="lineNum">     262 </span>            :     (|per_bank_update_way_mask_3) &amp; (&amp;(update_idx[1:0]));</a>
+<a name="263"><span class="lineNum">     263 </span>            :   wire [2:0]  _wrbypass_io_T_6 =</a>
+<a name="264"><span class="lineNum">     264 </span>            :     (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_0_0_io_hit_data_0_bits)</a>
+<a name="265"><span class="lineNum">     265 </span>            :     | (io_update_pc[1] ? _bank_wrbypasses_0_1_io_hit_data_0_bits : 3'h0);</a>
+<a name="266"><span class="lineNum">     266 </span><span class="lineCov">         17 :   wire        wrbypass_data_valid =</span></a>
+<a name="267"><span class="lineNum">     267 </span>            :     (~(io_update_pc[1]) &amp; _bank_wrbypasses_0_0_io_hit | io_update_pc[1]</a>
+<a name="268"><span class="lineNum">     268 </span>            :      &amp; _bank_wrbypasses_0_1_io_hit)</a>
+<a name="269"><span class="lineNum">     269 </span>            :     &amp; (~(io_update_pc[1]) &amp; _bank_wrbypasses_0_0_io_hit_data_0_valid | io_update_pc[1]</a>
+<a name="270"><span class="lineNum">     270 </span>            :        &amp; _bank_wrbypasses_0_1_io_hit_data_0_valid);</a>
+<a name="271"><span class="lineNum">     271 </span>            :   wire        _GEN = io_update_pc[1] ? io_update_takens_1 : io_update_takens_0;</a>
+<a name="272"><span class="lineNum">     272 </span>            :   wire [2:0]  _GEN_0 = io_update_pc[1] ? io_update_oldCtrs_1 : io_update_oldCtrs_0;</a>
+<a name="273"><span class="lineNum">     273 </span>            :   wire        _GEN_1 = (|_GEN_0) | _GEN;</a>
+<a name="274"><span class="lineNum">     274 </span>            :   wire        _GEN_2 = io_update_pc[1] ? io_update_alloc_1 : io_update_alloc_0;</a>
+<a name="275"><span class="lineNum">     275 </span><span class="lineCov">         41 :   wire [2:0]  per_bank_update_wdata_0_0_ctr =</span></a>
+<a name="276"><span class="lineNum">     276 </span>            :     _GEN_2</a>
+<a name="277"><span class="lineNum">     277 </span>            :       ? (_GEN ? 3'h4 : 3'h3)</a>
+<a name="278"><span class="lineNum">     278 </span>            :       : wrbypass_data_valid</a>
+<a name="279"><span class="lineNum">     279 </span>            :           ? ((&amp;_wrbypass_io_T_6) &amp; _GEN</a>
+<a name="280"><span class="lineNum">     280 </span>            :                ? 3'h7</a>
+<a name="281"><span class="lineNum">     281 </span>            :                : _wrbypass_io_T_6 == 3'h0 &amp; ~_GEN</a>
+<a name="282"><span class="lineNum">     282 </span>            :                    ? 3'h0</a>
+<a name="283"><span class="lineNum">     283 </span>            :                    : _GEN ? 3'(_wrbypass_io_T_6 + 3'h1) : 3'(_wrbypass_io_T_6 - 3'h1))</a>
+<a name="284"><span class="lineNum">     284 </span>            :           : (&amp;_GEN_0) &amp; _GEN</a>
+<a name="285"><span class="lineNum">     285 </span>            :               ? 3'h7</a>
+<a name="286"><span class="lineNum">     286 </span>            :               : _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0;</a>
+<a name="287"><span class="lineNum">     287 </span>            :   assign per_bank_not_silent_update_0_0 =</a>
+<a name="288"><span class="lineNum">     288 </span>            :     (wrbypass_data_valid</a>
+<a name="289"><span class="lineNum">     289 </span>            :        ? ~((&amp;_wrbypass_io_T_6) &amp; _GEN | _wrbypass_io_T_6 == 3'h0 &amp; ~_GEN)</a>
+<a name="290"><span class="lineNum">     290 </span>            :        : ~((&amp;_GEN_0) &amp; _GEN | _GEN_0 == 3'h0 &amp; ~_GEN)) | _GEN_2;</a>
+<a name="291"><span class="lineNum">     291 </span>            :   wire [2:0]  _wrbypass_io_T_28 =</a>
+<a name="292"><span class="lineNum">     292 </span>            :     (io_update_pc[1] ? _bank_wrbypasses_0_0_io_hit_data_0_bits : 3'h0)</a>
+<a name="293"><span class="lineNum">     293 </span>            :     | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_0_1_io_hit_data_0_bits);</a>
+<a name="294"><span class="lineNum">     294 </span><span class="lineCov">         13 :   wire        wrbypass_data_valid_1 =</span></a>
+<a name="295"><span class="lineNum">     295 </span>            :     (io_update_pc[1] &amp; _bank_wrbypasses_0_0_io_hit | ~(io_update_pc[1])</a>
+<a name="296"><span class="lineNum">     296 </span>            :      &amp; _bank_wrbypasses_0_1_io_hit)</a>
+<a name="297"><span class="lineNum">     297 </span>            :     &amp; (io_update_pc[1] &amp; _bank_wrbypasses_0_0_io_hit_data_0_valid | ~(io_update_pc[1])</a>
+<a name="298"><span class="lineNum">     298 </span>            :        &amp; _bank_wrbypasses_0_1_io_hit_data_0_valid);</a>
+<a name="299"><span class="lineNum">     299 </span>            :   wire        _GEN_3 = io_update_pc[1] ? io_update_takens_0 : io_update_takens_1;</a>
+<a name="300"><span class="lineNum">     300 </span>            :   wire [2:0]  _GEN_4 = io_update_pc[1] ? io_update_oldCtrs_0 : io_update_oldCtrs_1;</a>
+<a name="301"><span class="lineNum">     301 </span>            :   wire        _GEN_5 = io_update_pc[1] ? io_update_alloc_0 : io_update_alloc_1;</a>
+<a name="302"><span class="lineNum">     302 </span><span class="lineCov">         55 :   wire [2:0]  per_bank_update_wdata_0_1_ctr =</span></a>
+<a name="303"><span class="lineNum">     303 </span>            :     _GEN_5</a>
+<a name="304"><span class="lineNum">     304 </span>            :       ? (_GEN_3 ? 3'h4 : 3'h3)</a>
+<a name="305"><span class="lineNum">     305 </span>            :       : wrbypass_data_valid_1</a>
+<a name="306"><span class="lineNum">     306 </span>            :           ? ((&amp;_wrbypass_io_T_28) &amp; _GEN_3</a>
+<a name="307"><span class="lineNum">     307 </span>            :                ? 3'h7</a>
+<a name="308"><span class="lineNum">     308 </span>            :                : _wrbypass_io_T_28 == 3'h0 &amp; ~_GEN_3</a>
+<a name="309"><span class="lineNum">     309 </span>            :                    ? 3'h0</a>
+<a name="310"><span class="lineNum">     310 </span>            :                    : _GEN_3 ? 3'(_wrbypass_io_T_28 + 3'h1) : 3'(_wrbypass_io_T_28 - 3'h1))</a>
+<a name="311"><span class="lineNum">     311 </span>            :           : (&amp;_GEN_4) &amp; _GEN_3</a>
+<a name="312"><span class="lineNum">     312 </span>            :               ? 3'h7</a>
+<a name="313"><span class="lineNum">     313 </span>            :               : _GEN_4 == 3'h0 &amp; ~_GEN_3</a>
+<a name="314"><span class="lineNum">     314 </span>            :                   ? 3'h0</a>
+<a name="315"><span class="lineNum">     315 </span>            :                   : _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1);</a>
+<a name="316"><span class="lineNum">     316 </span>            :   assign per_bank_not_silent_update_0_1 =</a>
+<a name="317"><span class="lineNum">     317 </span>            :     (wrbypass_data_valid_1</a>
+<a name="318"><span class="lineNum">     318 </span>            :        ? ~((&amp;_wrbypass_io_T_28) &amp; _GEN_3 | _wrbypass_io_T_28 == 3'h0 &amp; ~_GEN_3)</a>
+<a name="319"><span class="lineNum">     319 </span>            :        : ~((&amp;_GEN_4) &amp; _GEN_3 | _GEN_4 == 3'h0 &amp; ~_GEN_3)) | _GEN_5;</a>
+<a name="320"><span class="lineNum">     320 </span>            :   wire [2:0]  _wrbypass_io_T_50 =</a>
+<a name="321"><span class="lineNum">     321 </span>            :     (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_1_0_io_hit_data_0_bits)</a>
+<a name="322"><span class="lineNum">     322 </span>            :     | (io_update_pc[1] ? _bank_wrbypasses_1_1_io_hit_data_0_bits : 3'h0);</a>
+<a name="323"><span class="lineNum">     323 </span><span class="lineCov">         19 :   wire        wrbypass_data_valid_2 =</span></a>
+<a name="324"><span class="lineNum">     324 </span>            :     (~(io_update_pc[1]) &amp; _bank_wrbypasses_1_0_io_hit | io_update_pc[1]</a>
+<a name="325"><span class="lineNum">     325 </span>            :      &amp; _bank_wrbypasses_1_1_io_hit)</a>
+<a name="326"><span class="lineNum">     326 </span>            :     &amp; (~(io_update_pc[1]) &amp; _bank_wrbypasses_1_0_io_hit_data_0_valid | io_update_pc[1]</a>
+<a name="327"><span class="lineNum">     327 </span>            :        &amp; _bank_wrbypasses_1_1_io_hit_data_0_valid);</a>
+<a name="328"><span class="lineNum">     328 </span><span class="lineCov">         49 :   wire [2:0]  per_bank_update_wdata_1_0_ctr =</span></a>
+<a name="329"><span class="lineNum">     329 </span>            :     _GEN_2</a>
+<a name="330"><span class="lineNum">     330 </span>            :       ? (_GEN ? 3'h4 : 3'h3)</a>
+<a name="331"><span class="lineNum">     331 </span>            :       : wrbypass_data_valid_2</a>
+<a name="332"><span class="lineNum">     332 </span>            :           ? ((&amp;_wrbypass_io_T_50) &amp; _GEN</a>
+<a name="333"><span class="lineNum">     333 </span>            :                ? 3'h7</a>
+<a name="334"><span class="lineNum">     334 </span>            :                : _wrbypass_io_T_50 == 3'h0 &amp; ~_GEN</a>
+<a name="335"><span class="lineNum">     335 </span>            :                    ? 3'h0</a>
+<a name="336"><span class="lineNum">     336 </span>            :                    : _GEN ? 3'(_wrbypass_io_T_50 + 3'h1) : 3'(_wrbypass_io_T_50 - 3'h1))</a>
+<a name="337"><span class="lineNum">     337 </span>            :           : (&amp;_GEN_0) &amp; _GEN</a>
+<a name="338"><span class="lineNum">     338 </span>            :               ? 3'h7</a>
+<a name="339"><span class="lineNum">     339 </span>            :               : _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0;</a>
+<a name="340"><span class="lineNum">     340 </span>            :   assign per_bank_not_silent_update_1_0 =</a>
+<a name="341"><span class="lineNum">     341 </span>            :     (wrbypass_data_valid_2</a>
+<a name="342"><span class="lineNum">     342 </span>            :        ? ~((&amp;_wrbypass_io_T_50) &amp; _GEN | _wrbypass_io_T_50 == 3'h0 &amp; ~_GEN)</a>
+<a name="343"><span class="lineNum">     343 </span>            :        : ~((&amp;_GEN_0) &amp; _GEN | _GEN_0 == 3'h0 &amp; ~_GEN)) | _GEN_2;</a>
+<a name="344"><span class="lineNum">     344 </span>            :   wire [2:0]  _wrbypass_io_T_72 =</a>
+<a name="345"><span class="lineNum">     345 </span>            :     (io_update_pc[1] ? _bank_wrbypasses_1_0_io_hit_data_0_bits : 3'h0)</a>
+<a name="346"><span class="lineNum">     346 </span>            :     | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_1_1_io_hit_data_0_bits);</a>
+<a name="347"><span class="lineNum">     347 </span><span class="lineCov">         18 :   wire        wrbypass_data_valid_3 =</span></a>
+<a name="348"><span class="lineNum">     348 </span>            :     (io_update_pc[1] &amp; _bank_wrbypasses_1_0_io_hit | ~(io_update_pc[1])</a>
+<a name="349"><span class="lineNum">     349 </span>            :      &amp; _bank_wrbypasses_1_1_io_hit)</a>
+<a name="350"><span class="lineNum">     350 </span>            :     &amp; (io_update_pc[1] &amp; _bank_wrbypasses_1_0_io_hit_data_0_valid | ~(io_update_pc[1])</a>
+<a name="351"><span class="lineNum">     351 </span>            :        &amp; _bank_wrbypasses_1_1_io_hit_data_0_valid);</a>
+<a name="352"><span class="lineNum">     352 </span><span class="lineCov">         48 :   wire [2:0]  per_bank_update_wdata_1_1_ctr =</span></a>
+<a name="353"><span class="lineNum">     353 </span>            :     _GEN_5</a>
+<a name="354"><span class="lineNum">     354 </span>            :       ? (_GEN_3 ? 3'h4 : 3'h3)</a>
+<a name="355"><span class="lineNum">     355 </span>            :       : wrbypass_data_valid_3</a>
+<a name="356"><span class="lineNum">     356 </span>            :           ? ((&amp;_wrbypass_io_T_72) &amp; _GEN_3</a>
+<a name="357"><span class="lineNum">     357 </span>            :                ? 3'h7</a>
+<a name="358"><span class="lineNum">     358 </span>            :                : _wrbypass_io_T_72 == 3'h0 &amp; ~_GEN_3</a>
+<a name="359"><span class="lineNum">     359 </span>            :                    ? 3'h0</a>
+<a name="360"><span class="lineNum">     360 </span>            :                    : _GEN_3 ? 3'(_wrbypass_io_T_72 + 3'h1) : 3'(_wrbypass_io_T_72 - 3'h1))</a>
+<a name="361"><span class="lineNum">     361 </span>            :           : (&amp;_GEN_4) &amp; _GEN_3</a>
+<a name="362"><span class="lineNum">     362 </span>            :               ? 3'h7</a>
+<a name="363"><span class="lineNum">     363 </span>            :               : _GEN_4 == 3'h0 &amp; ~_GEN_3</a>
+<a name="364"><span class="lineNum">     364 </span>            :                   ? 3'h0</a>
+<a name="365"><span class="lineNum">     365 </span>            :                   : _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1);</a>
+<a name="366"><span class="lineNum">     366 </span>            :   assign per_bank_not_silent_update_1_1 =</a>
+<a name="367"><span class="lineNum">     367 </span>            :     (wrbypass_data_valid_3</a>
+<a name="368"><span class="lineNum">     368 </span>            :        ? ~((&amp;_wrbypass_io_T_72) &amp; _GEN_3 | _wrbypass_io_T_72 == 3'h0 &amp; ~_GEN_3)</a>
+<a name="369"><span class="lineNum">     369 </span>            :        : ~((&amp;_GEN_4) &amp; _GEN_3 | _GEN_4 == 3'h0 &amp; ~_GEN_3)) | _GEN_5;</a>
+<a name="370"><span class="lineNum">     370 </span>            :   wire [2:0]  _wrbypass_io_T_94 =</a>
+<a name="371"><span class="lineNum">     371 </span>            :     (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_2_0_io_hit_data_0_bits)</a>
+<a name="372"><span class="lineNum">     372 </span>            :     | (io_update_pc[1] ? _bank_wrbypasses_2_1_io_hit_data_0_bits : 3'h0);</a>
+<a name="373"><span class="lineNum">     373 </span><span class="lineCov">         17 :   wire        wrbypass_data_valid_4 =</span></a>
+<a name="374"><span class="lineNum">     374 </span>            :     (~(io_update_pc[1]) &amp; _bank_wrbypasses_2_0_io_hit | io_update_pc[1]</a>
+<a name="375"><span class="lineNum">     375 </span>            :      &amp; _bank_wrbypasses_2_1_io_hit)</a>
+<a name="376"><span class="lineNum">     376 </span>            :     &amp; (~(io_update_pc[1]) &amp; _bank_wrbypasses_2_0_io_hit_data_0_valid | io_update_pc[1]</a>
+<a name="377"><span class="lineNum">     377 </span>            :        &amp; _bank_wrbypasses_2_1_io_hit_data_0_valid);</a>
+<a name="378"><span class="lineNum">     378 </span><span class="lineCov">         51 :   wire [2:0]  per_bank_update_wdata_2_0_ctr =</span></a>
+<a name="379"><span class="lineNum">     379 </span>            :     _GEN_2</a>
+<a name="380"><span class="lineNum">     380 </span>            :       ? (_GEN ? 3'h4 : 3'h3)</a>
+<a name="381"><span class="lineNum">     381 </span>            :       : wrbypass_data_valid_4</a>
+<a name="382"><span class="lineNum">     382 </span>            :           ? ((&amp;_wrbypass_io_T_94) &amp; _GEN</a>
+<a name="383"><span class="lineNum">     383 </span>            :                ? 3'h7</a>
+<a name="384"><span class="lineNum">     384 </span>            :                : _wrbypass_io_T_94 == 3'h0 &amp; ~_GEN</a>
+<a name="385"><span class="lineNum">     385 </span>            :                    ? 3'h0</a>
+<a name="386"><span class="lineNum">     386 </span>            :                    : _GEN ? 3'(_wrbypass_io_T_94 + 3'h1) : 3'(_wrbypass_io_T_94 - 3'h1))</a>
+<a name="387"><span class="lineNum">     387 </span>            :           : (&amp;_GEN_0) &amp; _GEN</a>
+<a name="388"><span class="lineNum">     388 </span>            :               ? 3'h7</a>
+<a name="389"><span class="lineNum">     389 </span>            :               : _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0;</a>
+<a name="390"><span class="lineNum">     390 </span>            :   assign per_bank_not_silent_update_2_0 =</a>
+<a name="391"><span class="lineNum">     391 </span>            :     (wrbypass_data_valid_4</a>
+<a name="392"><span class="lineNum">     392 </span>            :        ? ~((&amp;_wrbypass_io_T_94) &amp; _GEN | _wrbypass_io_T_94 == 3'h0 &amp; ~_GEN)</a>
+<a name="393"><span class="lineNum">     393 </span>            :        : ~((&amp;_GEN_0) &amp; _GEN | _GEN_0 == 3'h0 &amp; ~_GEN)) | _GEN_2;</a>
+<a name="394"><span class="lineNum">     394 </span>            :   wire [2:0]  _wrbypass_io_T_116 =</a>
+<a name="395"><span class="lineNum">     395 </span>            :     (io_update_pc[1] ? _bank_wrbypasses_2_0_io_hit_data_0_bits : 3'h0)</a>
+<a name="396"><span class="lineNum">     396 </span>            :     | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_2_1_io_hit_data_0_bits);</a>
+<a name="397"><span class="lineNum">     397 </span><span class="lineCov">         17 :   wire        wrbypass_data_valid_5 =</span></a>
+<a name="398"><span class="lineNum">     398 </span>            :     (io_update_pc[1] &amp; _bank_wrbypasses_2_0_io_hit | ~(io_update_pc[1])</a>
+<a name="399"><span class="lineNum">     399 </span>            :      &amp; _bank_wrbypasses_2_1_io_hit)</a>
+<a name="400"><span class="lineNum">     400 </span>            :     &amp; (io_update_pc[1] &amp; _bank_wrbypasses_2_0_io_hit_data_0_valid | ~(io_update_pc[1])</a>
+<a name="401"><span class="lineNum">     401 </span>            :        &amp; _bank_wrbypasses_2_1_io_hit_data_0_valid);</a>
+<a name="402"><span class="lineNum">     402 </span><span class="lineCov">         48 :   wire [2:0]  per_bank_update_wdata_2_1_ctr =</span></a>
+<a name="403"><span class="lineNum">     403 </span>            :     _GEN_5</a>
+<a name="404"><span class="lineNum">     404 </span>            :       ? (_GEN_3 ? 3'h4 : 3'h3)</a>
+<a name="405"><span class="lineNum">     405 </span>            :       : wrbypass_data_valid_5</a>
+<a name="406"><span class="lineNum">     406 </span>            :           ? ((&amp;_wrbypass_io_T_116) &amp; _GEN_3</a>
+<a name="407"><span class="lineNum">     407 </span>            :                ? 3'h7</a>
+<a name="408"><span class="lineNum">     408 </span>            :                : _wrbypass_io_T_116 == 3'h0 &amp; ~_GEN_3</a>
+<a name="409"><span class="lineNum">     409 </span>            :                    ? 3'h0</a>
+<a name="410"><span class="lineNum">     410 </span>            :                    : _GEN_3</a>
+<a name="411"><span class="lineNum">     411 </span>            :                        ? 3'(_wrbypass_io_T_116 + 3'h1)</a>
+<a name="412"><span class="lineNum">     412 </span>            :                        : 3'(_wrbypass_io_T_116 - 3'h1))</a>
+<a name="413"><span class="lineNum">     413 </span>            :           : (&amp;_GEN_4) &amp; _GEN_3</a>
+<a name="414"><span class="lineNum">     414 </span>            :               ? 3'h7</a>
+<a name="415"><span class="lineNum">     415 </span>            :               : _GEN_4 == 3'h0 &amp; ~_GEN_3</a>
+<a name="416"><span class="lineNum">     416 </span>            :                   ? 3'h0</a>
+<a name="417"><span class="lineNum">     417 </span>            :                   : _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1);</a>
+<a name="418"><span class="lineNum">     418 </span>            :   assign per_bank_not_silent_update_2_1 =</a>
+<a name="419"><span class="lineNum">     419 </span>            :     (wrbypass_data_valid_5</a>
+<a name="420"><span class="lineNum">     420 </span>            :        ? ~((&amp;_wrbypass_io_T_116) &amp; _GEN_3 | _wrbypass_io_T_116 == 3'h0 &amp; ~_GEN_3)</a>
+<a name="421"><span class="lineNum">     421 </span>            :        : ~((&amp;_GEN_4) &amp; _GEN_3 | _GEN_4 == 3'h0 &amp; ~_GEN_3)) | _GEN_5;</a>
+<a name="422"><span class="lineNum">     422 </span>            :   wire [2:0]  _wrbypass_io_T_138 =</a>
+<a name="423"><span class="lineNum">     423 </span>            :     (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_3_0_io_hit_data_0_bits)</a>
+<a name="424"><span class="lineNum">     424 </span>            :     | (io_update_pc[1] ? _bank_wrbypasses_3_1_io_hit_data_0_bits : 3'h0);</a>
+<a name="425"><span class="lineNum">     425 </span><span class="lineCov">         27 :   wire        wrbypass_data_valid_6 =</span></a>
+<a name="426"><span class="lineNum">     426 </span>            :     (~(io_update_pc[1]) &amp; _bank_wrbypasses_3_0_io_hit | io_update_pc[1]</a>
+<a name="427"><span class="lineNum">     427 </span>            :      &amp; _bank_wrbypasses_3_1_io_hit)</a>
+<a name="428"><span class="lineNum">     428 </span>            :     &amp; (~(io_update_pc[1]) &amp; _bank_wrbypasses_3_0_io_hit_data_0_valid | io_update_pc[1]</a>
+<a name="429"><span class="lineNum">     429 </span>            :        &amp; _bank_wrbypasses_3_1_io_hit_data_0_valid);</a>
+<a name="430"><span class="lineNum">     430 </span><span class="lineCov">         41 :   wire [2:0]  per_bank_update_wdata_3_0_ctr =</span></a>
+<a name="431"><span class="lineNum">     431 </span>            :     _GEN_2</a>
+<a name="432"><span class="lineNum">     432 </span>            :       ? (_GEN ? 3'h4 : 3'h3)</a>
+<a name="433"><span class="lineNum">     433 </span>            :       : wrbypass_data_valid_6</a>
+<a name="434"><span class="lineNum">     434 </span>            :           ? ((&amp;_wrbypass_io_T_138) &amp; _GEN</a>
+<a name="435"><span class="lineNum">     435 </span>            :                ? 3'h7</a>
+<a name="436"><span class="lineNum">     436 </span>            :                : _wrbypass_io_T_138 == 3'h0 &amp; ~_GEN</a>
+<a name="437"><span class="lineNum">     437 </span>            :                    ? 3'h0</a>
+<a name="438"><span class="lineNum">     438 </span>            :                    : _GEN ? 3'(_wrbypass_io_T_138 + 3'h1) : 3'(_wrbypass_io_T_138 - 3'h1))</a>
+<a name="439"><span class="lineNum">     439 </span>            :           : (&amp;_GEN_0) &amp; _GEN</a>
+<a name="440"><span class="lineNum">     440 </span>            :               ? 3'h7</a>
+<a name="441"><span class="lineNum">     441 </span>            :               : _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0;</a>
+<a name="442"><span class="lineNum">     442 </span>            :   assign per_bank_not_silent_update_3_0 =</a>
+<a name="443"><span class="lineNum">     443 </span>            :     (wrbypass_data_valid_6</a>
+<a name="444"><span class="lineNum">     444 </span>            :        ? ~((&amp;_wrbypass_io_T_138) &amp; _GEN | _wrbypass_io_T_138 == 3'h0 &amp; ~_GEN)</a>
+<a name="445"><span class="lineNum">     445 </span>            :        : ~((&amp;_GEN_0) &amp; _GEN | _GEN_0 == 3'h0 &amp; ~_GEN)) | _GEN_2;</a>
+<a name="446"><span class="lineNum">     446 </span>            :   wire [2:0]  _wrbypass_io_T_160 =</a>
+<a name="447"><span class="lineNum">     447 </span>            :     (io_update_pc[1] ? _bank_wrbypasses_3_0_io_hit_data_0_bits : 3'h0)</a>
+<a name="448"><span class="lineNum">     448 </span>            :     | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_3_1_io_hit_data_0_bits);</a>
+<a name="449"><span class="lineNum">     449 </span><span class="lineCov">         20 :   wire        wrbypass_data_valid_7 =</span></a>
+<a name="450"><span class="lineNum">     450 </span>            :     (io_update_pc[1] &amp; _bank_wrbypasses_3_0_io_hit | ~(io_update_pc[1])</a>
+<a name="451"><span class="lineNum">     451 </span>            :      &amp; _bank_wrbypasses_3_1_io_hit)</a>
+<a name="452"><span class="lineNum">     452 </span>            :     &amp; (io_update_pc[1] &amp; _bank_wrbypasses_3_0_io_hit_data_0_valid | ~(io_update_pc[1])</a>
+<a name="453"><span class="lineNum">     453 </span>            :        &amp; _bank_wrbypasses_3_1_io_hit_data_0_valid);</a>
+<a name="454"><span class="lineNum">     454 </span><span class="lineCov">         45 :   wire [2:0]  per_bank_update_wdata_3_1_ctr =</span></a>
+<a name="455"><span class="lineNum">     455 </span>            :     _GEN_5</a>
+<a name="456"><span class="lineNum">     456 </span>            :       ? (_GEN_3 ? 3'h4 : 3'h3)</a>
+<a name="457"><span class="lineNum">     457 </span>            :       : wrbypass_data_valid_7</a>
+<a name="458"><span class="lineNum">     458 </span>            :           ? ((&amp;_wrbypass_io_T_160) &amp; _GEN_3</a>
+<a name="459"><span class="lineNum">     459 </span>            :                ? 3'h7</a>
+<a name="460"><span class="lineNum">     460 </span>            :                : _wrbypass_io_T_160 == 3'h0 &amp; ~_GEN_3</a>
+<a name="461"><span class="lineNum">     461 </span>            :                    ? 3'h0</a>
+<a name="462"><span class="lineNum">     462 </span>            :                    : _GEN_3</a>
+<a name="463"><span class="lineNum">     463 </span>            :                        ? 3'(_wrbypass_io_T_160 + 3'h1)</a>
+<a name="464"><span class="lineNum">     464 </span>            :                        : 3'(_wrbypass_io_T_160 - 3'h1))</a>
+<a name="465"><span class="lineNum">     465 </span>            :           : (&amp;_GEN_4) &amp; _GEN_3</a>
+<a name="466"><span class="lineNum">     466 </span>            :               ? 3'h7</a>
+<a name="467"><span class="lineNum">     467 </span>            :               : _GEN_4 == 3'h0 &amp; ~_GEN_3</a>
+<a name="468"><span class="lineNum">     468 </span>            :                   ? 3'h0</a>
+<a name="469"><span class="lineNum">     469 </span>            :                   : _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1);</a>
+<a name="470"><span class="lineNum">     470 </span>            :   assign per_bank_not_silent_update_3_1 =</a>
+<a name="471"><span class="lineNum">     471 </span>            :     (wrbypass_data_valid_7</a>
+<a name="472"><span class="lineNum">     472 </span>            :        ? ~((&amp;_wrbypass_io_T_160) &amp; _GEN_3 | _wrbypass_io_T_160 == 3'h0 &amp; ~_GEN_3)</a>
+<a name="473"><span class="lineNum">     473 </span>            :        : ~((&amp;_GEN_4) &amp; _GEN_3 | _GEN_4 == 3'h0 &amp; ~_GEN_3)) | _GEN_5;</a>
+<a name="474"><span class="lineNum">     474 </span><span class="lineCov">     127694 :   always @(posedge clock) begin</span></a>
+<a name="475"><span class="lineNum">     475 </span><span class="lineCov">       8350 :     if (_s1_bank_req_1h_T) begin</span></a>
+<a name="476"><span class="lineNum">     476 </span><span class="lineCov">       4175 :       s1_unhashed_idx &lt;= io_req_bits_pc[40:1];</span></a>
+<a name="477"><span class="lineNum">     477 </span><span class="lineCov">       4175 :       s1_tag &lt;=</span></a>
+<a name="478"><span class="lineNum">     478 </span><span class="lineCov">       4175 :         io_req_bits_pc[8:1] ^ io_req_bits_folded_hist_hist_8_folded_hist</span></a>
+<a name="479"><span class="lineNum">     479 </span><span class="lineCov">       4175 :         ^ {io_req_bits_folded_hist_hist_5_folded_hist, 1'h0};</span></a>
+<a name="480"><span class="lineNum">     480 </span><span class="lineCov">       4175 :       s1_bank_req_1h_0 &lt;= s0_bank_req_1h_0;</span></a>
+<a name="481"><span class="lineNum">     481 </span><span class="lineCov">       4175 :       s1_bank_req_1h_1 &lt;= s0_bank_req_1h_1;</span></a>
+<a name="482"><span class="lineNum">     482 </span><span class="lineCov">       4175 :       s1_bank_req_1h_2 &lt;= s0_bank_req_1h_2;</span></a>
+<a name="483"><span class="lineNum">     483 </span><span class="lineCov">       4175 :       s1_bank_req_1h_3 &lt;= &amp;(s0_idx[1:0]);</span></a>
+<a name="484"><span class="lineNum">     484 </span>            :     end</a>
+<a name="485"><span class="lineNum">     485 </span><span class="lineCov">       8350 :     if (io_req_valid) begin</span></a>
+<a name="486"><span class="lineNum">     486 </span><span class="lineCov">       4175 :       s1_bank_has_write_on_this_req_0 &lt;= _s1_bank_has_write_on_this_req_WIRE_0;</span></a>
+<a name="487"><span class="lineNum">     487 </span><span class="lineCov">       4175 :       s1_bank_has_write_on_this_req_1 &lt;= _s1_bank_has_write_on_this_req_WIRE_1;</span></a>
+<a name="488"><span class="lineNum">     488 </span><span class="lineCov">       4175 :       s1_bank_has_write_on_this_req_2 &lt;= _s1_bank_has_write_on_this_req_WIRE_2;</span></a>
+<a name="489"><span class="lineNum">     489 </span><span class="lineCov">       4175 :       s1_bank_has_write_on_this_req_3 &lt;= _s1_bank_has_write_on_this_req_WIRE_3;</span></a>
+<a name="490"><span class="lineNum">     490 </span>            :     end</a>
+<a name="491"><span class="lineNum">     491 </span>            :   end // always @(posedge)</a>
+<a name="492"><span class="lineNum">     492 </span><span class="lineCov">     127730 :   always @(posedge clock or posedge reset) begin</span></a>
+<a name="493"><span class="lineNum">     493 </span><span class="lineCov">        272 :     if (reset)</span></a>
+<a name="494"><span class="lineNum">     494 </span><span class="lineCov">        136 :       powerOnResetState &lt;= 1'h1;</span></a>
+<a name="495"><span class="lineNum">     495 </span>            :     else</a>
+<a name="496"><span class="lineNum">     496 </span><span class="lineCov">      63729 :       powerOnResetState &lt;=</span></a>
+<a name="497"><span class="lineNum">     497 </span><span class="lineCov">      63729 :         ~(_us_io_r_req_ready &amp; _table_banks_0_io_r_req_ready</span></a>
+<a name="498"><span class="lineNum">     498 </span><span class="lineCov">      63729 :           &amp; _table_banks_1_io_r_req_ready &amp; _table_banks_2_io_r_req_ready</span></a>
+<a name="499"><span class="lineNum">     499 </span><span class="lineCov">      63729 :           &amp; _table_banks_3_io_r_req_ready) &amp; powerOnResetState;</span></a>
+<a name="500"><span class="lineNum">     500 </span>            :   end // always @(posedge, posedge)</a>
+<a name="501"><span class="lineNum">     501 </span>            :   `ifdef ENABLE_INITIAL_REG_</a>
+<a name="502"><span class="lineNum">     502 </span>            :     `ifdef FIRRTL_BEFORE_INITIAL</a>
+<a name="503"><span class="lineNum">     503 </span>            :       `FIRRTL_BEFORE_INITIAL</a>
+<a name="504"><span class="lineNum">     504 </span>            :     `endif // FIRRTL_BEFORE_INITIAL</a>
+<a name="505"><span class="lineNum">     505 </span>            :     logic [31:0] _RANDOM[0:3];</a>
+<a name="506"><span class="lineNum">     506 </span><span class="lineCov">         58 :     initial begin</span></a>
+<a name="507"><span class="lineNum">     507 </span>            :       `ifdef INIT_RANDOM_PROLOG_</a>
+<a name="508"><span class="lineNum">     508 </span>            :         `INIT_RANDOM_PROLOG_</a>
+<a name="509"><span class="lineNum">     509 </span>            :       `endif // INIT_RANDOM_PROLOG_</a>
+<a name="510"><span class="lineNum">     510 </span>            :       `ifdef RANDOMIZE_REG_INIT</a>
+<a name="511"><span class="lineNum">     511 </span>            :         for (logic [2:0] i = 3'h0; i &lt; 3'h4; i += 3'h1) begin</a>
+<a name="512"><span class="lineNum">     512 </span>            :           _RANDOM[i[1:0]] = `RANDOM;</a>
+<a name="513"><span class="lineNum">     513 </span>            :         end</a>
+<a name="514"><span class="lineNum">     514 </span>            :         s1_unhashed_idx = {_RANDOM[2'h0], _RANDOM[2'h1][7:0]};</a>
+<a name="515"><span class="lineNum">     515 </span>            :         s1_tag = _RANDOM[2'h1][26:19];</a>
+<a name="516"><span class="lineNum">     516 </span>            :         s1_bank_req_1h_0 = _RANDOM[2'h3][4];</a>
+<a name="517"><span class="lineNum">     517 </span>            :         s1_bank_req_1h_1 = _RANDOM[2'h3][5];</a>
+<a name="518"><span class="lineNum">     518 </span>            :         s1_bank_req_1h_2 = _RANDOM[2'h3][6];</a>
+<a name="519"><span class="lineNum">     519 </span>            :         s1_bank_req_1h_3 = _RANDOM[2'h3][7];</a>
+<a name="520"><span class="lineNum">     520 </span>            :         s1_bank_has_write_on_this_req_0 = _RANDOM[2'h3][8];</a>
+<a name="521"><span class="lineNum">     521 </span>            :         s1_bank_has_write_on_this_req_1 = _RANDOM[2'h3][9];</a>
+<a name="522"><span class="lineNum">     522 </span>            :         s1_bank_has_write_on_this_req_2 = _RANDOM[2'h3][10];</a>
+<a name="523"><span class="lineNum">     523 </span>            :         s1_bank_has_write_on_this_req_3 = _RANDOM[2'h3][11];</a>
+<a name="524"><span class="lineNum">     524 </span>            :         powerOnResetState = _RANDOM[2'h3][12];</a>
+<a name="525"><span class="lineNum">     525 </span>            :       `endif // RANDOMIZE_REG_INIT</a>
+<a name="526"><span class="lineNum">     526 </span><span class="lineCov">         17 :       if (reset)</span></a>
+<a name="527"><span class="lineNum">     527 </span><span class="lineCov">         12 :         powerOnResetState = 1'h1;</span></a>
+<a name="528"><span class="lineNum">     528 </span>            :     end // initial</a>
+<a name="529"><span class="lineNum">     529 </span>            :     `ifdef FIRRTL_AFTER_INITIAL</a>
+<a name="530"><span class="lineNum">     530 </span>            :       `FIRRTL_AFTER_INITIAL</a>
+<a name="531"><span class="lineNum">     531 </span>            :     `endif // FIRRTL_AFTER_INITIAL</a>
+<a name="532"><span class="lineNum">     532 </span>            :   `endif // ENABLE_INITIAL_REG_</a>
+<a name="533"><span class="lineNum">     533 </span>            :   FoldedSRAMTemplate us (</a>
+<a name="534"><span class="lineNum">     534 </span>            :     .clock                 (clock),</a>
+<a name="535"><span class="lineNum">     535 </span>            :     .reset                 (reset),</a>
+<a name="536"><span class="lineNum">     536 </span>            :     .io_r_req_ready        (_us_io_r_req_ready),</a>
+<a name="537"><span class="lineNum">     537 </span>            :     .io_r_req_valid        (_s1_bank_req_1h_T),</a>
+<a name="538"><span class="lineNum">     538 </span>            :     .io_r_req_bits_setIdx  (s0_idx),</a>
+<a name="539"><span class="lineNum">     539 </span>            :     .io_r_resp_data_0      (_us_io_r_resp_data_0),</a>
+<a name="540"><span class="lineNum">     540 </span>            :     .io_r_resp_data_1      (_us_io_r_resp_data_1),</a>
+<a name="541"><span class="lineNum">     541 </span>            :     .io_w_req_valid</a>
+<a name="542"><span class="lineNum">     542 </span>            :       (_us_extra_reset_T_1 &amp; (io_update_uMask_0 | io_update_uMask_1)),</a>
+<a name="543"><span class="lineNum">     543 </span>            :     .io_w_req_bits_setIdx  (update_idx),</a>
+<a name="544"><span class="lineNum">     544 </span>            :     .io_w_req_bits_data_0</a>
+<a name="545"><span class="lineNum">     545 </span>            :       (~(io_update_pc[1]) &amp; io_update_us_0 | io_update_pc[1] &amp; io_update_us_1),</a>
+<a name="546"><span class="lineNum">     546 </span>            :     .io_w_req_bits_data_1</a>
+<a name="547"><span class="lineNum">     547 </span>            :       (io_update_pc[1] &amp; io_update_us_0 | ~(io_update_pc[1]) &amp; io_update_us_1),</a>
+<a name="548"><span class="lineNum">     548 </span>            :     .io_w_req_bits_waymask</a>
+<a name="549"><span class="lineNum">     549 </span>            :       ({io_update_pc[1] &amp; io_update_uMask_0 | ~(io_update_pc[1]) &amp; io_update_uMask_1,</a>
+<a name="550"><span class="lineNum">     550 </span>            :         ~(io_update_pc[1]) &amp; io_update_uMask_0 | io_update_pc[1] &amp; io_update_uMask_1}),</a>
+<a name="551"><span class="lineNum">     551 </span>            :     .extra_reset</a>
+<a name="552"><span class="lineNum">     552 </span>            :       ((io_update_reset_u_0 | io_update_reset_u_1) &amp; _us_extra_reset_T_1)</a>
+<a name="553"><span class="lineNum">     553 </span>            :   );</a>
+<a name="554"><span class="lineNum">     554 </span>            :   FoldedSRAMTemplate_1 table_banks_0 (</a>
+<a name="555"><span class="lineNum">     555 </span>            :     .clock                    (clock),</a>
+<a name="556"><span class="lineNum">     556 </span>            :     .reset                    (reset),</a>
+<a name="557"><span class="lineNum">     557 </span>            :     .io_r_req_ready           (_table_banks_0_io_r_req_ready),</a>
+<a name="558"><span class="lineNum">     558 </span>            :     .io_r_req_valid           (_s1_bank_req_1h_T &amp; s0_bank_req_1h_0),</a>
+<a name="559"><span class="lineNum">     559 </span>            :     .io_r_req_bits_setIdx     (s0_idx[10:2]),</a>
+<a name="560"><span class="lineNum">     560 </span>            :     .io_r_resp_data_0_valid   (_table_banks_0_io_r_resp_data_0_valid),</a>
+<a name="561"><span class="lineNum">     561 </span>            :     .io_r_resp_data_0_tag     (_table_banks_0_io_r_resp_data_0_tag),</a>
+<a name="562"><span class="lineNum">     562 </span>            :     .io_r_resp_data_0_ctr     (_table_banks_0_io_r_resp_data_0_ctr),</a>
+<a name="563"><span class="lineNum">     563 </span>            :     .io_r_resp_data_1_valid   (_table_banks_0_io_r_resp_data_1_valid),</a>
+<a name="564"><span class="lineNum">     564 </span>            :     .io_r_resp_data_1_tag     (_table_banks_0_io_r_resp_data_1_tag),</a>
+<a name="565"><span class="lineNum">     565 </span>            :     .io_r_resp_data_1_ctr     (_table_banks_0_io_r_resp_data_1_ctr),</a>
+<a name="566"><span class="lineNum">     566 </span>            :     .io_w_req_valid           (_s1_bank_has_write_on_this_req_WIRE_0),</a>
+<a name="567"><span class="lineNum">     567 </span>            :     .io_w_req_bits_setIdx     (update_idx[10:2]),</a>
+<a name="568"><span class="lineNum">     568 </span>            :     .io_w_req_bits_data_0_tag (update_tag),</a>
+<a name="569"><span class="lineNum">     569 </span>            :     .io_w_req_bits_data_0_ctr (per_bank_update_wdata_0_0_ctr),</a>
+<a name="570"><span class="lineNum">     570 </span>            :     .io_w_req_bits_data_1_tag (update_tag),</a>
+<a name="571"><span class="lineNum">     571 </span>            :     .io_w_req_bits_data_1_ctr (per_bank_update_wdata_0_1_ctr),</a>
+<a name="572"><span class="lineNum">     572 </span>            :     .io_w_req_bits_waymask    (per_bank_update_way_mask_0)</a>
+<a name="573"><span class="lineNum">     573 </span>            :   );</a>
+<a name="574"><span class="lineNum">     574 </span>            :   FoldedSRAMTemplate_1 table_banks_1 (</a>
+<a name="575"><span class="lineNum">     575 </span>            :     .clock                    (clock),</a>
+<a name="576"><span class="lineNum">     576 </span>            :     .reset                    (reset),</a>
+<a name="577"><span class="lineNum">     577 </span>            :     .io_r_req_ready           (_table_banks_1_io_r_req_ready),</a>
+<a name="578"><span class="lineNum">     578 </span>            :     .io_r_req_valid           (_s1_bank_req_1h_T &amp; s0_bank_req_1h_1),</a>
+<a name="579"><span class="lineNum">     579 </span>            :     .io_r_req_bits_setIdx     (s0_idx[10:2]),</a>
+<a name="580"><span class="lineNum">     580 </span>            :     .io_r_resp_data_0_valid   (_table_banks_1_io_r_resp_data_0_valid),</a>
+<a name="581"><span class="lineNum">     581 </span>            :     .io_r_resp_data_0_tag     (_table_banks_1_io_r_resp_data_0_tag),</a>
+<a name="582"><span class="lineNum">     582 </span>            :     .io_r_resp_data_0_ctr     (_table_banks_1_io_r_resp_data_0_ctr),</a>
+<a name="583"><span class="lineNum">     583 </span>            :     .io_r_resp_data_1_valid   (_table_banks_1_io_r_resp_data_1_valid),</a>
+<a name="584"><span class="lineNum">     584 </span>            :     .io_r_resp_data_1_tag     (_table_banks_1_io_r_resp_data_1_tag),</a>
+<a name="585"><span class="lineNum">     585 </span>            :     .io_r_resp_data_1_ctr     (_table_banks_1_io_r_resp_data_1_ctr),</a>
+<a name="586"><span class="lineNum">     586 </span>            :     .io_w_req_valid           (_s1_bank_has_write_on_this_req_WIRE_1),</a>
+<a name="587"><span class="lineNum">     587 </span>            :     .io_w_req_bits_setIdx     (update_idx[10:2]),</a>
+<a name="588"><span class="lineNum">     588 </span>            :     .io_w_req_bits_data_0_tag (update_tag),</a>
+<a name="589"><span class="lineNum">     589 </span>            :     .io_w_req_bits_data_0_ctr (per_bank_update_wdata_1_0_ctr),</a>
+<a name="590"><span class="lineNum">     590 </span>            :     .io_w_req_bits_data_1_tag (update_tag),</a>
+<a name="591"><span class="lineNum">     591 </span>            :     .io_w_req_bits_data_1_ctr (per_bank_update_wdata_1_1_ctr),</a>
+<a name="592"><span class="lineNum">     592 </span>            :     .io_w_req_bits_waymask    (per_bank_update_way_mask_1)</a>
+<a name="593"><span class="lineNum">     593 </span>            :   );</a>
+<a name="594"><span class="lineNum">     594 </span>            :   FoldedSRAMTemplate_1 table_banks_2 (</a>
+<a name="595"><span class="lineNum">     595 </span>            :     .clock                    (clock),</a>
+<a name="596"><span class="lineNum">     596 </span>            :     .reset                    (reset),</a>
+<a name="597"><span class="lineNum">     597 </span>            :     .io_r_req_ready           (_table_banks_2_io_r_req_ready),</a>
+<a name="598"><span class="lineNum">     598 </span>            :     .io_r_req_valid           (_s1_bank_req_1h_T &amp; s0_bank_req_1h_2),</a>
+<a name="599"><span class="lineNum">     599 </span>            :     .io_r_req_bits_setIdx     (s0_idx[10:2]),</a>
+<a name="600"><span class="lineNum">     600 </span>            :     .io_r_resp_data_0_valid   (_table_banks_2_io_r_resp_data_0_valid),</a>
+<a name="601"><span class="lineNum">     601 </span>            :     .io_r_resp_data_0_tag     (_table_banks_2_io_r_resp_data_0_tag),</a>
+<a name="602"><span class="lineNum">     602 </span>            :     .io_r_resp_data_0_ctr     (_table_banks_2_io_r_resp_data_0_ctr),</a>
+<a name="603"><span class="lineNum">     603 </span>            :     .io_r_resp_data_1_valid   (_table_banks_2_io_r_resp_data_1_valid),</a>
+<a name="604"><span class="lineNum">     604 </span>            :     .io_r_resp_data_1_tag     (_table_banks_2_io_r_resp_data_1_tag),</a>
+<a name="605"><span class="lineNum">     605 </span>            :     .io_r_resp_data_1_ctr     (_table_banks_2_io_r_resp_data_1_ctr),</a>
+<a name="606"><span class="lineNum">     606 </span>            :     .io_w_req_valid           (_s1_bank_has_write_on_this_req_WIRE_2),</a>
+<a name="607"><span class="lineNum">     607 </span>            :     .io_w_req_bits_setIdx     (update_idx[10:2]),</a>
+<a name="608"><span class="lineNum">     608 </span>            :     .io_w_req_bits_data_0_tag (update_tag),</a>
+<a name="609"><span class="lineNum">     609 </span>            :     .io_w_req_bits_data_0_ctr (per_bank_update_wdata_2_0_ctr),</a>
+<a name="610"><span class="lineNum">     610 </span>            :     .io_w_req_bits_data_1_tag (update_tag),</a>
+<a name="611"><span class="lineNum">     611 </span>            :     .io_w_req_bits_data_1_ctr (per_bank_update_wdata_2_1_ctr),</a>
+<a name="612"><span class="lineNum">     612 </span>            :     .io_w_req_bits_waymask    (per_bank_update_way_mask_2)</a>
+<a name="613"><span class="lineNum">     613 </span>            :   );</a>
+<a name="614"><span class="lineNum">     614 </span>            :   FoldedSRAMTemplate_1 table_banks_3 (</a>
+<a name="615"><span class="lineNum">     615 </span>            :     .clock                    (clock),</a>
+<a name="616"><span class="lineNum">     616 </span>            :     .reset                    (reset),</a>
+<a name="617"><span class="lineNum">     617 </span>            :     .io_r_req_ready           (_table_banks_3_io_r_req_ready),</a>
+<a name="618"><span class="lineNum">     618 </span>            :     .io_r_req_valid           (_s1_bank_req_1h_T &amp; (&amp;(s0_idx[1:0]))),</a>
+<a name="619"><span class="lineNum">     619 </span>            :     .io_r_req_bits_setIdx     (s0_idx[10:2]),</a>
+<a name="620"><span class="lineNum">     620 </span>            :     .io_r_resp_data_0_valid   (_table_banks_3_io_r_resp_data_0_valid),</a>
+<a name="621"><span class="lineNum">     621 </span>            :     .io_r_resp_data_0_tag     (_table_banks_3_io_r_resp_data_0_tag),</a>
+<a name="622"><span class="lineNum">     622 </span>            :     .io_r_resp_data_0_ctr     (_table_banks_3_io_r_resp_data_0_ctr),</a>
+<a name="623"><span class="lineNum">     623 </span>            :     .io_r_resp_data_1_valid   (_table_banks_3_io_r_resp_data_1_valid),</a>
+<a name="624"><span class="lineNum">     624 </span>            :     .io_r_resp_data_1_tag     (_table_banks_3_io_r_resp_data_1_tag),</a>
+<a name="625"><span class="lineNum">     625 </span>            :     .io_r_resp_data_1_ctr     (_table_banks_3_io_r_resp_data_1_ctr),</a>
+<a name="626"><span class="lineNum">     626 </span>            :     .io_w_req_valid           (_s1_bank_has_write_on_this_req_WIRE_3),</a>
+<a name="627"><span class="lineNum">     627 </span>            :     .io_w_req_bits_setIdx     (update_idx[10:2]),</a>
+<a name="628"><span class="lineNum">     628 </span>            :     .io_w_req_bits_data_0_tag (update_tag),</a>
+<a name="629"><span class="lineNum">     629 </span>            :     .io_w_req_bits_data_0_ctr (per_bank_update_wdata_3_0_ctr),</a>
+<a name="630"><span class="lineNum">     630 </span>            :     .io_w_req_bits_data_1_tag (update_tag),</a>
+<a name="631"><span class="lineNum">     631 </span>            :     .io_w_req_bits_data_1_ctr (per_bank_update_wdata_3_1_ctr),</a>
+<a name="632"><span class="lineNum">     632 </span>            :     .io_w_req_bits_waymask    (per_bank_update_way_mask_3)</a>
+<a name="633"><span class="lineNum">     633 </span>            :   );</a>
+<a name="634"><span class="lineNum">     634 </span>            :   WrBypass bank_wrbypasses_0_0 (</a>
+<a name="635"><span class="lineNum">     635 </span>            :     .clock               (clock),</a>
+<a name="636"><span class="lineNum">     636 </span>            :     .reset               (reset),</a>
+<a name="637"><span class="lineNum">     637 </span>            :     .io_wen              (io_update_mask_0 &amp; update_req_bank_1h_0),</a>
+<a name="638"><span class="lineNum">     638 </span>            :     .io_write_idx        (update_idx[10:2]),</a>
+<a name="639"><span class="lineNum">     639 </span>            :     .io_write_data_0</a>
+<a name="640"><span class="lineNum">     640 </span>            :       ((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_0_0_ctr)</a>
+<a name="641"><span class="lineNum">     641 </span>            :        | (io_update_pc[1] ? per_bank_update_wdata_0_1_ctr : 3'h0)),</a>
+<a name="642"><span class="lineNum">     642 </span>            :     .io_hit              (_bank_wrbypasses_0_0_io_hit),</a>
+<a name="643"><span class="lineNum">     643 </span>            :     .io_hit_data_0_valid (_bank_wrbypasses_0_0_io_hit_data_0_valid),</a>
+<a name="644"><span class="lineNum">     644 </span>            :     .io_hit_data_0_bits  (_bank_wrbypasses_0_0_io_hit_data_0_bits)</a>
+<a name="645"><span class="lineNum">     645 </span>            :   );</a>
+<a name="646"><span class="lineNum">     646 </span>            :   WrBypass bank_wrbypasses_0_1 (</a>
+<a name="647"><span class="lineNum">     647 </span>            :     .clock               (clock),</a>
+<a name="648"><span class="lineNum">     648 </span>            :     .reset               (reset),</a>
+<a name="649"><span class="lineNum">     649 </span>            :     .io_wen              (io_update_mask_1 &amp; update_req_bank_1h_0),</a>
+<a name="650"><span class="lineNum">     650 </span>            :     .io_write_idx        (update_idx[10:2]),</a>
+<a name="651"><span class="lineNum">     651 </span>            :     .io_write_data_0</a>
+<a name="652"><span class="lineNum">     652 </span>            :       ((io_update_pc[1] ? per_bank_update_wdata_0_0_ctr : 3'h0)</a>
+<a name="653"><span class="lineNum">     653 </span>            :        | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_0_1_ctr)),</a>
+<a name="654"><span class="lineNum">     654 </span>            :     .io_hit              (_bank_wrbypasses_0_1_io_hit),</a>
+<a name="655"><span class="lineNum">     655 </span>            :     .io_hit_data_0_valid (_bank_wrbypasses_0_1_io_hit_data_0_valid),</a>
+<a name="656"><span class="lineNum">     656 </span>            :     .io_hit_data_0_bits  (_bank_wrbypasses_0_1_io_hit_data_0_bits)</a>
+<a name="657"><span class="lineNum">     657 </span>            :   );</a>
+<a name="658"><span class="lineNum">     658 </span>            :   WrBypass bank_wrbypasses_1_0 (</a>
+<a name="659"><span class="lineNum">     659 </span>            :     .clock               (clock),</a>
+<a name="660"><span class="lineNum">     660 </span>            :     .reset               (reset),</a>
+<a name="661"><span class="lineNum">     661 </span>            :     .io_wen              (io_update_mask_0 &amp; update_req_bank_1h_1),</a>
+<a name="662"><span class="lineNum">     662 </span>            :     .io_write_idx        (update_idx[10:2]),</a>
+<a name="663"><span class="lineNum">     663 </span>            :     .io_write_data_0</a>
+<a name="664"><span class="lineNum">     664 </span>            :       ((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_1_0_ctr)</a>
+<a name="665"><span class="lineNum">     665 </span>            :        | (io_update_pc[1] ? per_bank_update_wdata_1_1_ctr : 3'h0)),</a>
+<a name="666"><span class="lineNum">     666 </span>            :     .io_hit              (_bank_wrbypasses_1_0_io_hit),</a>
+<a name="667"><span class="lineNum">     667 </span>            :     .io_hit_data_0_valid (_bank_wrbypasses_1_0_io_hit_data_0_valid),</a>
+<a name="668"><span class="lineNum">     668 </span>            :     .io_hit_data_0_bits  (_bank_wrbypasses_1_0_io_hit_data_0_bits)</a>
+<a name="669"><span class="lineNum">     669 </span>            :   );</a>
+<a name="670"><span class="lineNum">     670 </span>            :   WrBypass bank_wrbypasses_1_1 (</a>
+<a name="671"><span class="lineNum">     671 </span>            :     .clock               (clock),</a>
+<a name="672"><span class="lineNum">     672 </span>            :     .reset               (reset),</a>
+<a name="673"><span class="lineNum">     673 </span>            :     .io_wen              (io_update_mask_1 &amp; update_req_bank_1h_1),</a>
+<a name="674"><span class="lineNum">     674 </span>            :     .io_write_idx        (update_idx[10:2]),</a>
+<a name="675"><span class="lineNum">     675 </span>            :     .io_write_data_0</a>
+<a name="676"><span class="lineNum">     676 </span>            :       ((io_update_pc[1] ? per_bank_update_wdata_1_0_ctr : 3'h0)</a>
+<a name="677"><span class="lineNum">     677 </span>            :        | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_1_1_ctr)),</a>
+<a name="678"><span class="lineNum">     678 </span>            :     .io_hit              (_bank_wrbypasses_1_1_io_hit),</a>
+<a name="679"><span class="lineNum">     679 </span>            :     .io_hit_data_0_valid (_bank_wrbypasses_1_1_io_hit_data_0_valid),</a>
+<a name="680"><span class="lineNum">     680 </span>            :     .io_hit_data_0_bits  (_bank_wrbypasses_1_1_io_hit_data_0_bits)</a>
+<a name="681"><span class="lineNum">     681 </span>            :   );</a>
+<a name="682"><span class="lineNum">     682 </span>            :   WrBypass bank_wrbypasses_2_0 (</a>
+<a name="683"><span class="lineNum">     683 </span>            :     .clock               (clock),</a>
+<a name="684"><span class="lineNum">     684 </span>            :     .reset               (reset),</a>
+<a name="685"><span class="lineNum">     685 </span>            :     .io_wen              (io_update_mask_0 &amp; update_req_bank_1h_2),</a>
+<a name="686"><span class="lineNum">     686 </span>            :     .io_write_idx        (update_idx[10:2]),</a>
+<a name="687"><span class="lineNum">     687 </span>            :     .io_write_data_0</a>
+<a name="688"><span class="lineNum">     688 </span>            :       ((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_2_0_ctr)</a>
+<a name="689"><span class="lineNum">     689 </span>            :        | (io_update_pc[1] ? per_bank_update_wdata_2_1_ctr : 3'h0)),</a>
+<a name="690"><span class="lineNum">     690 </span>            :     .io_hit              (_bank_wrbypasses_2_0_io_hit),</a>
+<a name="691"><span class="lineNum">     691 </span>            :     .io_hit_data_0_valid (_bank_wrbypasses_2_0_io_hit_data_0_valid),</a>
+<a name="692"><span class="lineNum">     692 </span>            :     .io_hit_data_0_bits  (_bank_wrbypasses_2_0_io_hit_data_0_bits)</a>
+<a name="693"><span class="lineNum">     693 </span>            :   );</a>
+<a name="694"><span class="lineNum">     694 </span>            :   WrBypass bank_wrbypasses_2_1 (</a>
+<a name="695"><span class="lineNum">     695 </span>            :     .clock               (clock),</a>
+<a name="696"><span class="lineNum">     696 </span>            :     .reset               (reset),</a>
+<a name="697"><span class="lineNum">     697 </span>            :     .io_wen              (io_update_mask_1 &amp; update_req_bank_1h_2),</a>
+<a name="698"><span class="lineNum">     698 </span>            :     .io_write_idx        (update_idx[10:2]),</a>
+<a name="699"><span class="lineNum">     699 </span>            :     .io_write_data_0</a>
+<a name="700"><span class="lineNum">     700 </span>            :       ((io_update_pc[1] ? per_bank_update_wdata_2_0_ctr : 3'h0)</a>
+<a name="701"><span class="lineNum">     701 </span>            :        | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_2_1_ctr)),</a>
+<a name="702"><span class="lineNum">     702 </span>            :     .io_hit              (_bank_wrbypasses_2_1_io_hit),</a>
+<a name="703"><span class="lineNum">     703 </span>            :     .io_hit_data_0_valid (_bank_wrbypasses_2_1_io_hit_data_0_valid),</a>
+<a name="704"><span class="lineNum">     704 </span>            :     .io_hit_data_0_bits  (_bank_wrbypasses_2_1_io_hit_data_0_bits)</a>
+<a name="705"><span class="lineNum">     705 </span>            :   );</a>
+<a name="706"><span class="lineNum">     706 </span>            :   WrBypass bank_wrbypasses_3_0 (</a>
+<a name="707"><span class="lineNum">     707 </span>            :     .clock               (clock),</a>
+<a name="708"><span class="lineNum">     708 </span>            :     .reset               (reset),</a>
+<a name="709"><span class="lineNum">     709 </span>            :     .io_wen              (io_update_mask_0 &amp; (&amp;(update_idx[1:0]))),</a>
+<a name="710"><span class="lineNum">     710 </span>            :     .io_write_idx        (update_idx[10:2]),</a>
+<a name="711"><span class="lineNum">     711 </span>            :     .io_write_data_0</a>
+<a name="712"><span class="lineNum">     712 </span>            :       ((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_3_0_ctr)</a>
+<a name="713"><span class="lineNum">     713 </span>            :        | (io_update_pc[1] ? per_bank_update_wdata_3_1_ctr : 3'h0)),</a>
+<a name="714"><span class="lineNum">     714 </span>            :     .io_hit              (_bank_wrbypasses_3_0_io_hit),</a>
+<a name="715"><span class="lineNum">     715 </span>            :     .io_hit_data_0_valid (_bank_wrbypasses_3_0_io_hit_data_0_valid),</a>
+<a name="716"><span class="lineNum">     716 </span>            :     .io_hit_data_0_bits  (_bank_wrbypasses_3_0_io_hit_data_0_bits)</a>
+<a name="717"><span class="lineNum">     717 </span>            :   );</a>
+<a name="718"><span class="lineNum">     718 </span>            :   WrBypass bank_wrbypasses_3_1 (</a>
+<a name="719"><span class="lineNum">     719 </span>            :     .clock               (clock),</a>
+<a name="720"><span class="lineNum">     720 </span>            :     .reset               (reset),</a>
+<a name="721"><span class="lineNum">     721 </span>            :     .io_wen              (io_update_mask_1 &amp; (&amp;(update_idx[1:0]))),</a>
+<a name="722"><span class="lineNum">     722 </span>            :     .io_write_idx        (update_idx[10:2]),</a>
+<a name="723"><span class="lineNum">     723 </span>            :     .io_write_data_0</a>
+<a name="724"><span class="lineNum">     724 </span>            :       ((io_update_pc[1] ? per_bank_update_wdata_3_0_ctr : 3'h0)</a>
+<a name="725"><span class="lineNum">     725 </span>            :        | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_3_1_ctr)),</a>
+<a name="726"><span class="lineNum">     726 </span>            :     .io_hit              (_bank_wrbypasses_3_1_io_hit),</a>
+<a name="727"><span class="lineNum">     727 </span>            :     .io_hit_data_0_valid (_bank_wrbypasses_3_1_io_hit_data_0_valid),</a>
+<a name="728"><span class="lineNum">     728 </span>            :     .io_hit_data_0_bits  (_bank_wrbypasses_3_1_io_hit_data_0_bits)</a>
+<a name="729"><span class="lineNum">     729 </span>            :   );</a>
+<a name="730"><span class="lineNum">     730 </span>            :   assign io_req_ready = ~powerOnResetState;</a>
+<a name="731"><span class="lineNum">     731 </span>            :   assign io_resps_0_valid =</a>
+<a name="732"><span class="lineNum">     732 </span>            :     ~(s1_unhashed_idx[0]) &amp; _hit_selected_T_6 | s1_unhashed_idx[0] &amp; _hit_selected_T_13;</a>
+<a name="733"><span class="lineNum">     733 </span>            :   assign io_resps_0_bits_ctr =</a>
+<a name="734"><span class="lineNum">     734 </span>            :     (s1_unhashed_idx[0] ? 3'h0 : _resp_selected_T_6)</a>
+<a name="735"><span class="lineNum">     735 </span>            :     | (s1_unhashed_idx[0] ? _resp_selected_T_27 : 3'h0);</a>
+<a name="736"><span class="lineNum">     736 </span>            :   assign io_resps_0_bits_u =</a>
+<a name="737"><span class="lineNum">     737 </span>            :     ~(s1_unhashed_idx[0]) &amp; _us_io_r_resp_data_0 | s1_unhashed_idx[0]</a>
+<a name="738"><span class="lineNum">     738 </span>            :     &amp; _us_io_r_resp_data_1;</a>
+<a name="739"><span class="lineNum">     739 </span>            :   assign io_resps_0_bits_unconf =</a>
+<a name="740"><span class="lineNum">     740 </span>            :     ~(s1_unhashed_idx[0]) &amp; _unconf_selected_T_6 | s1_unhashed_idx[0]</a>
+<a name="741"><span class="lineNum">     741 </span>            :     &amp; _unconf_selected_T_13;</a>
+<a name="742"><span class="lineNum">     742 </span>            :   assign io_resps_1_valid =</a>
+<a name="743"><span class="lineNum">     743 </span>            :     s1_unhashed_idx[0] &amp; _hit_selected_T_6 | ~(s1_unhashed_idx[0]) &amp; _hit_selected_T_13;</a>
+<a name="744"><span class="lineNum">     744 </span>            :   assign io_resps_1_bits_ctr =</a>
+<a name="745"><span class="lineNum">     745 </span>            :     (s1_unhashed_idx[0] ? _resp_selected_T_6 : 3'h0)</a>
+<a name="746"><span class="lineNum">     746 </span>            :     | (s1_unhashed_idx[0] ? 3'h0 : _resp_selected_T_27);</a>
+<a name="747"><span class="lineNum">     747 </span>            :   assign io_resps_1_bits_u =</a>
+<a name="748"><span class="lineNum">     748 </span>            :     s1_unhashed_idx[0] &amp; _us_io_r_resp_data_0 | ~(s1_unhashed_idx[0])</a>
+<a name="749"><span class="lineNum">     749 </span>            :     &amp; _us_io_r_resp_data_1;</a>
+<a name="750"><span class="lineNum">     750 </span>            :   assign io_resps_1_bits_unconf =</a>
+<a name="751"><span class="lineNum">     751 </span>            :     s1_unhashed_idx[0] &amp; _unconf_selected_T_6 | ~(s1_unhashed_idx[0])</a>
+<a name="752"><span class="lineNum">     752 </span>            :     &amp; _unconf_selected_T_13;</a>
+<a name="753"><span class="lineNum">     753 </span>            : endmodule</a>
+<a name="754"><span class="lineNum">     754 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/Tage_SC.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/Tage_SC.sv.func-sort-c.html
new file mode 100644
index 0000000..e3e0592
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/Tage_SC.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/Tage_SC.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - Tage_SC.sv<span style="font-size: 80%;"> (<a href="Tage_SC.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">1491</td>
+            <td class="headerCovTableEntry">3621</td>
+            <td class="headerCovTableEntryLo">41.2 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="Tage_SC.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/Tage_SC.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/Tage_SC.sv.func.html
new file mode 100644
index 0000000..a051f5c
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/Tage_SC.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/Tage_SC.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - Tage_SC.sv<span style="font-size: 80%;"> (<a href="Tage_SC.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">1491</td>
+            <td class="headerCovTableEntry">3621</td>
+            <td class="headerCovTableEntryLo">41.2 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="Tage_SC.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/Tage_SC.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/Tage_SC.sv.gcov.html
new file mode 100644
index 0000000..06062cf
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/Tage_SC.sv.gcov.html
@@ -0,0 +1,5986 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/Tage_SC.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - Tage_SC.sv<span style="font-size: 80%;"> (source / <a href="Tage_SC.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">1491</td>
+            <td class="headerCovTableEntry">3621</td>
+            <td class="headerCovTableEntryLo">41.2 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : module Tage_SC(</a>
+<a name="59"><span class="lineNum">      59 </span><span class="lineCov">     127786 :   input          clock,</span></a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">         62 :   input          reset,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">       1105 :   input  [35:0]  io_reset_vector,</span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">      10337 :   input  [40:0]  io_in_bits_s0_pc_0,</span></a>
+<a name="63"><span class="lineNum">      63 </span><span class="lineCov">      10224 :   input  [40:0]  io_in_bits_s0_pc_1,</span></a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">      35066 :   input  [40:0]  io_in_bits_s0_pc_3,</span></a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">       1182 :   input  [10:0]  io_in_bits_folded_hist_1_hist_17_folded_hist,</span></a>
+<a name="66"><span class="lineNum">      66 </span><span class="lineCov">       1102 :   input  [10:0]  io_in_bits_folded_hist_1_hist_16_folded_hist,</span></a>
+<a name="67"><span class="lineNum">      67 </span><span class="lineCov">        828 :   input  [6:0]   io_in_bits_folded_hist_1_hist_15_folded_hist,</span></a>
+<a name="68"><span class="lineNum">      68 </span><span class="lineCov">        295 :   input  [7:0]   io_in_bits_folded_hist_1_hist_14_folded_hist,</span></a>
+<a name="69"><span class="lineNum">      69 </span><span class="lineCov">        844 :   input  [6:0]   io_in_bits_folded_hist_1_hist_9_folded_hist,</span></a>
+<a name="70"><span class="lineNum">      70 </span><span class="lineCov">        930 :   input  [7:0]   io_in_bits_folded_hist_1_hist_8_folded_hist,</span></a>
+<a name="71"><span class="lineNum">      71 </span><span class="lineCov">        760 :   input  [6:0]   io_in_bits_folded_hist_1_hist_7_folded_hist,</span></a>
+<a name="72"><span class="lineNum">      72 </span><span class="lineCov">        711 :   input  [6:0]   io_in_bits_folded_hist_1_hist_5_folded_hist,</span></a>
+<a name="73"><span class="lineNum">      73 </span><span class="lineCov">        300 :   input  [7:0]   io_in_bits_folded_hist_1_hist_4_folded_hist,</span></a>
+<a name="74"><span class="lineNum">      74 </span><span class="lineCov">        263 :   input  [7:0]   io_in_bits_folded_hist_1_hist_3_folded_hist,</span></a>
+<a name="75"><span class="lineNum">      75 </span><span class="lineCov">       1122 :   input  [10:0]  io_in_bits_folded_hist_1_hist_1_folded_hist,</span></a>
+<a name="76"><span class="lineNum">      76 </span><span class="lineCov">        474 :   input  [3:0]   io_in_bits_folded_hist_3_hist_12_folded_hist,</span></a>
+<a name="77"><span class="lineNum">      77 </span><span class="lineCov">        858 :   input  [7:0]   io_in_bits_folded_hist_3_hist_11_folded_hist,</span></a>
+<a name="78"><span class="lineNum">      78 </span><span class="lineCov">        811 :   input  [7:0]   io_in_bits_folded_hist_3_hist_2_folded_hist,</span></a>
+<a name="79"><span class="lineNum">      79 </span><span class="lineCov">         75 :   output         io_out_s2_full_pred_0_br_taken_mask_0,</span></a>
+<a name="80"><span class="lineNum">      80 </span><span class="lineCov">         68 :   output         io_out_s2_full_pred_0_br_taken_mask_1,</span></a>
+<a name="81"><span class="lineNum">      81 </span><span class="lineCov">         61 :   output         io_out_s2_full_pred_1_br_taken_mask_0,</span></a>
+<a name="82"><span class="lineNum">      82 </span><span class="lineCov">         64 :   output         io_out_s2_full_pred_1_br_taken_mask_1,</span></a>
+<a name="83"><span class="lineNum">      83 </span><span class="lineCov">         64 :   output         io_out_s2_full_pred_2_br_taken_mask_0,</span></a>
+<a name="84"><span class="lineNum">      84 </span><span class="lineCov">         55 :   output         io_out_s2_full_pred_2_br_taken_mask_1,</span></a>
+<a name="85"><span class="lineNum">      85 </span><span class="lineCov">         75 :   output         io_out_s2_full_pred_3_br_taken_mask_0,</span></a>
+<a name="86"><span class="lineNum">      86 </span><span class="lineCov">         67 :   output         io_out_s2_full_pred_3_br_taken_mask_1,</span></a>
+<a name="87"><span class="lineNum">      87 </span><span class="lineCov">         75 :   output         io_out_s3_full_pred_0_br_taken_mask_0,</span></a>
+<a name="88"><span class="lineNum">      88 </span><span class="lineCov">         64 :   output         io_out_s3_full_pred_0_br_taken_mask_1,</span></a>
+<a name="89"><span class="lineNum">      89 </span><span class="lineCov">         82 :   output         io_out_s3_full_pred_1_br_taken_mask_0,</span></a>
+<a name="90"><span class="lineNum">      90 </span><span class="lineCov">         62 :   output         io_out_s3_full_pred_1_br_taken_mask_1,</span></a>
+<a name="91"><span class="lineNum">      91 </span><span class="lineCov">         84 :   output         io_out_s3_full_pred_2_br_taken_mask_0,</span></a>
+<a name="92"><span class="lineNum">      92 </span><span class="lineCov">         66 :   output         io_out_s3_full_pred_2_br_taken_mask_1,</span></a>
+<a name="93"><span class="lineNum">      93 </span><span class="lineCov">         70 :   output         io_out_s3_full_pred_3_br_taken_mask_0,</span></a>
+<a name="94"><span class="lineNum">      94 </span><span class="lineCov">         69 :   output         io_out_s3_full_pred_3_br_taken_mask_1,</span></a>
+<a name="95"><span class="lineNum">      95 </span><span class="lineCov">       4775 :   output [222:0] io_out_last_stage_meta,</span></a>
+<a name="96"><span class="lineNum">      96 </span><span class="lineCov">         79 :   input          io_ctrl_tage_enable,</span></a>
+<a name="97"><span class="lineNum">      97 </span><span class="lineCov">         88 :   input          io_ctrl_sc_enable,</span></a>
+<a name="98"><span class="lineNum">      98 </span><span class="lineCov">         75 :   input          io_s0_fire_0,</span></a>
+<a name="99"><span class="lineNum">      99 </span><span class="lineCov">         76 :   input          io_s0_fire_1,</span></a>
+<a name="100"><span class="lineNum">     100 </span><span class="lineCov">         73 :   input          io_s0_fire_3,</span></a>
+<a name="101"><span class="lineNum">     101 </span><span class="lineCov">        133 :   input          io_s1_fire_0,</span></a>
+<a name="102"><span class="lineNum">     102 </span><span class="lineCov">        131 :   input          io_s1_fire_1,</span></a>
+<a name="103"><span class="lineNum">     103 </span><span class="lineCov">        135 :   input          io_s1_fire_2,</span></a>
+<a name="104"><span class="lineNum">     104 </span><span class="lineCov">        133 :   input          io_s1_fire_3,</span></a>
+<a name="105"><span class="lineNum">     105 </span><span class="lineCov">        127 :   input          io_s2_fire_0,</span></a>
+<a name="106"><span class="lineNum">     106 </span><span class="lineCov">        127 :   input          io_s2_fire_1,</span></a>
+<a name="107"><span class="lineNum">     107 </span><span class="lineCov">        127 :   input          io_s2_fire_2,</span></a>
+<a name="108"><span class="lineNum">     108 </span><span class="lineCov">        127 :   input          io_s2_fire_3,</span></a>
+<a name="109"><span class="lineNum">     109 </span><span class="lineCov">         43 :   output         io_s1_ready,</span></a>
+<a name="110"><span class="lineNum">     110 </span><span class="lineCov">        105 :   input          io_update_valid,</span></a>
+<a name="111"><span class="lineNum">     111 </span><span class="lineCov">       1143 :   input  [40:0]  io_update_bits_pc,</span></a>
+<a name="112"><span class="lineNum">     112 </span><span class="lineCov">        310 :   input  [10:0]  io_update_bits_spec_info_folded_hist_hist_17_folded_hist,</span></a>
+<a name="113"><span class="lineNum">     113 </span><span class="lineCov">        322 :   input  [10:0]  io_update_bits_spec_info_folded_hist_hist_16_folded_hist,</span></a>
+<a name="114"><span class="lineNum">     114 </span><span class="lineCov">        196 :   input  [6:0]   io_update_bits_spec_info_folded_hist_hist_15_folded_hist,</span></a>
+<a name="115"><span class="lineNum">     115 </span><span class="lineCov">        243 :   input  [7:0]   io_update_bits_spec_info_folded_hist_hist_14_folded_hist,</span></a>
+<a name="116"><span class="lineNum">     116 </span><span class="lineCov">        108 :   input  [3:0]   io_update_bits_spec_info_folded_hist_hist_12_folded_hist,</span></a>
+<a name="117"><span class="lineNum">     117 </span><span class="lineCov">        240 :   input  [7:0]   io_update_bits_spec_info_folded_hist_hist_11_folded_hist,</span></a>
+<a name="118"><span class="lineNum">     118 </span><span class="lineCov">        197 :   input  [6:0]   io_update_bits_spec_info_folded_hist_hist_9_folded_hist,</span></a>
+<a name="119"><span class="lineNum">     119 </span><span class="lineCov">        244 :   input  [7:0]   io_update_bits_spec_info_folded_hist_hist_8_folded_hist,</span></a>
+<a name="120"><span class="lineNum">     120 </span><span class="lineCov">        217 :   input  [6:0]   io_update_bits_spec_info_folded_hist_hist_7_folded_hist,</span></a>
+<a name="121"><span class="lineNum">     121 </span><span class="lineCov">        202 :   input  [6:0]   io_update_bits_spec_info_folded_hist_hist_5_folded_hist,</span></a>
+<a name="122"><span class="lineNum">     122 </span><span class="lineCov">        219 :   input  [7:0]   io_update_bits_spec_info_folded_hist_hist_4_folded_hist,</span></a>
+<a name="123"><span class="lineNum">     123 </span><span class="lineCov">        233 :   input  [7:0]   io_update_bits_spec_info_folded_hist_hist_3_folded_hist,</span></a>
+<a name="124"><span class="lineNum">     124 </span><span class="lineCov">        231 :   input  [7:0]   io_update_bits_spec_info_folded_hist_hist_2_folded_hist,</span></a>
+<a name="125"><span class="lineNum">     125 </span><span class="lineCov">        339 :   input  [10:0]  io_update_bits_spec_info_folded_hist_hist_1_folded_hist,</span></a>
+<a name="126"><span class="lineNum">     126 </span><span class="lineCov">         35 :   input          io_update_bits_ftb_entry_brSlots_0_valid,</span></a>
+<a name="127"><span class="lineNum">     127 </span><span class="lineCov">         33 :   input          io_update_bits_ftb_entry_tailSlot_sharing,</span></a>
+<a name="128"><span class="lineNum">     128 </span><span class="lineCov">         28 :   input          io_update_bits_ftb_entry_tailSlot_valid,</span></a>
+<a name="129"><span class="lineNum">     129 </span><span class="lineCov">         32 :   input          io_update_bits_ftb_entry_always_taken_0,</span></a>
+<a name="130"><span class="lineNum">     130 </span><span class="lineCov">         33 :   input          io_update_bits_ftb_entry_always_taken_1,</span></a>
+<a name="131"><span class="lineNum">     131 </span><span class="lineCov">         24 :   input          io_update_bits_br_taken_mask_0,</span></a>
+<a name="132"><span class="lineNum">     132 </span><span class="lineCov">         40 :   input          io_update_bits_br_taken_mask_1,</span></a>
+<a name="133"><span class="lineNum">     133 </span><span class="lineCov">         45 :   input          io_update_bits_mispred_mask_0,</span></a>
+<a name="134"><span class="lineNum">     134 </span><span class="lineCov">         30 :   input          io_update_bits_mispred_mask_1,</span></a>
+<a name="135"><span class="lineNum">     135 </span><span class="lineCov">       4432 :   input  [222:0] io_update_bits_meta,</span></a>
+<a name="136"><span class="lineNum">     136 </span><span class="lineCov">        176 :   output [5:0]   io_perf_0_value,</span></a>
+<a name="137"><span class="lineNum">     137 </span><span class="lineCov">        149 :   output [5:0]   io_perf_1_value,</span></a>
+<a name="138"><span class="lineNum">     138 </span><span class="lineCov">        142 :   output [5:0]   io_perf_2_value</span></a>
+<a name="139"><span class="lineNum">     139 </span>            : );</a>
+<a name="140"><span class="lineNum">     140 </span>            : </a>
+<a name="141"><span class="lineNum">     141 </span><span class="lineCov">        204 :   reg  [5:0]  r_3_3;</span></a>
+<a name="142"><span class="lineNum">     142 </span><span class="lineCov">        196 :   reg  [5:0]  r_3_2;</span></a>
+<a name="143"><span class="lineNum">     143 </span><span class="lineCov">        226 :   reg  [5:0]  r_3_1;</span></a>
+<a name="144"><span class="lineNum">     144 </span><span class="lineCov">        193 :   reg  [5:0]  r_3_0;</span></a>
+<a name="145"><span class="lineNum">     145 </span><span class="lineCov">         31 :   reg         resp_meta_scMeta_scPreds_1_r;</span></a>
+<a name="146"><span class="lineNum">     146 </span><span class="lineCov">         30 :   reg         resp_meta_scMeta_scUsed_1_r;</span></a>
+<a name="147"><span class="lineNum">     147 </span><span class="lineCov">         32 :   reg         resp_meta_scMeta_tageTakens_1_r;</span></a>
+<a name="148"><span class="lineNum">     148 </span><span class="lineCov">        213 :   reg  [5:0]  r_2_3;</span></a>
+<a name="149"><span class="lineNum">     149 </span><span class="lineCov">        193 :   reg  [5:0]  r_2_2;</span></a>
+<a name="150"><span class="lineNum">     150 </span><span class="lineCov">        177 :   reg  [5:0]  r_2_1;</span></a>
+<a name="151"><span class="lineNum">     151 </span><span class="lineCov">        214 :   reg  [5:0]  r_2_0;</span></a>
+<a name="152"><span class="lineNum">     152 </span><span class="lineCov">         33 :   reg         resp_meta_scMeta_scPreds_0_r;</span></a>
+<a name="153"><span class="lineNum">     153 </span><span class="lineCov">         36 :   reg         resp_meta_scMeta_scUsed_0_r;</span></a>
+<a name="154"><span class="lineNum">     154 </span><span class="lineCov">         33 :   reg         resp_meta_scMeta_tageTakens_0_r;</span></a>
+<a name="155"><span class="lineNum">     155 </span><span class="lineCov">         69 :   reg  [1:0]  resp_meta_basecnts_1_r;</span></a>
+<a name="156"><span class="lineNum">     156 </span><span class="lineCov">         31 :   reg         resp_meta_takens_1_r;</span></a>
+<a name="157"><span class="lineNum">     157 </span><span class="lineCov">         34 :   reg         resp_meta_altDiffers_1_r;</span></a>
+<a name="158"><span class="lineNum">     158 </span><span class="lineCov">         36 :   reg         resp_meta_altUsed_1_r;</span></a>
+<a name="159"><span class="lineNum">     159 </span><span class="lineCov">        131 :   reg  [3:0]  resp_meta_allocates_1_r;</span></a>
+<a name="160"><span class="lineNum">     160 </span><span class="lineCov">         28 :   reg         resp_meta_providerResps_1_r_unconf;</span></a>
+<a name="161"><span class="lineNum">     161 </span><span class="lineCov">         38 :   reg         resp_meta_providerResps_1_r_u;</span></a>
+<a name="162"><span class="lineNum">     162 </span><span class="lineCov">         98 :   reg  [2:0]  resp_meta_providerResps_1_r_ctr;</span></a>
+<a name="163"><span class="lineNum">     163 </span><span class="lineCov">         72 :   reg  [1:0]  resp_meta_providers_1_bits_r;</span></a>
+<a name="164"><span class="lineNum">     164 </span><span class="lineCov">         32 :   reg         resp_meta_providers_1_valid_r;</span></a>
+<a name="165"><span class="lineNum">     165 </span><span class="lineCov">         58 :   reg  [1:0]  resp_meta_basecnts_0_r;</span></a>
+<a name="166"><span class="lineNum">     166 </span><span class="lineCov">         30 :   reg         resp_meta_takens_0_r;</span></a>
+<a name="167"><span class="lineNum">     167 </span><span class="lineCov">         34 :   reg         resp_meta_altDiffers_0_r;</span></a>
+<a name="168"><span class="lineNum">     168 </span><span class="lineCov">         33 :   reg         resp_meta_altUsed_0_r;</span></a>
+<a name="169"><span class="lineNum">     169 </span><span class="lineCov">        134 :   reg  [3:0]  resp_meta_allocates_0_r;</span></a>
+<a name="170"><span class="lineNum">     170 </span><span class="lineCov">         39 :   reg         resp_meta_providerResps_0_r_unconf;</span></a>
+<a name="171"><span class="lineNum">     171 </span><span class="lineCov">         38 :   reg         resp_meta_providerResps_0_r_u;</span></a>
+<a name="172"><span class="lineNum">     172 </span><span class="lineCov">        101 :   reg  [2:0]  resp_meta_providerResps_0_r_ctr;</span></a>
+<a name="173"><span class="lineNum">     173 </span><span class="lineCov">         64 :   reg  [1:0]  resp_meta_providers_0_bits_r;</span></a>
+<a name="174"><span class="lineNum">     174 </span><span class="lineCov">         33 :   reg         resp_meta_providers_0_valid_r;</span></a>
+<a name="175"><span class="lineNum">     175 </span>            :   wire [5:0]  _scTables_3_io_resp_ctrs_0_0;</a>
+<a name="176"><span class="lineNum">     176 </span>            :   wire [5:0]  _scTables_3_io_resp_ctrs_0_1;</a>
+<a name="177"><span class="lineNum">     177 </span>            :   wire [5:0]  _scTables_3_io_resp_ctrs_1_0;</a>
+<a name="178"><span class="lineNum">     178 </span>            :   wire [5:0]  _scTables_3_io_resp_ctrs_1_1;</a>
+<a name="179"><span class="lineNum">     179 </span>            :   wire [5:0]  _scTables_2_io_resp_ctrs_0_0;</a>
+<a name="180"><span class="lineNum">     180 </span>            :   wire [5:0]  _scTables_2_io_resp_ctrs_0_1;</a>
+<a name="181"><span class="lineNum">     181 </span>            :   wire [5:0]  _scTables_2_io_resp_ctrs_1_0;</a>
+<a name="182"><span class="lineNum">     182 </span>            :   wire [5:0]  _scTables_2_io_resp_ctrs_1_1;</a>
+<a name="183"><span class="lineNum">     183 </span>            :   wire [5:0]  _scTables_1_io_resp_ctrs_0_0;</a>
+<a name="184"><span class="lineNum">     184 </span>            :   wire [5:0]  _scTables_1_io_resp_ctrs_0_1;</a>
+<a name="185"><span class="lineNum">     185 </span>            :   wire [5:0]  _scTables_1_io_resp_ctrs_1_0;</a>
+<a name="186"><span class="lineNum">     186 </span>            :   wire [5:0]  _scTables_1_io_resp_ctrs_1_1;</a>
+<a name="187"><span class="lineNum">     187 </span>            :   wire [5:0]  _scTables_0_io_resp_ctrs_0_0;</a>
+<a name="188"><span class="lineNum">     188 </span>            :   wire [5:0]  _scTables_0_io_resp_ctrs_0_1;</a>
+<a name="189"><span class="lineNum">     189 </span>            :   wire [5:0]  _scTables_0_io_resp_ctrs_1_0;</a>
+<a name="190"><span class="lineNum">     190 </span>            :   wire [5:0]  _scTables_0_io_resp_ctrs_1_1;</a>
+<a name="191"><span class="lineNum">     191 </span>            :   wire        _bt_io_req_ready;</a>
+<a name="192"><span class="lineNum">     192 </span>            :   wire [1:0]  _bt_io_s1_cnt_0;</a>
+<a name="193"><span class="lineNum">     193 </span>            :   wire [1:0]  _bt_io_s1_cnt_1;</a>
+<a name="194"><span class="lineNum">     194 </span>            :   wire        _tables_3_io_req_ready;</a>
+<a name="195"><span class="lineNum">     195 </span>            :   wire        _tables_3_io_resps_0_valid;</a>
+<a name="196"><span class="lineNum">     196 </span>            :   wire [2:0]  _tables_3_io_resps_0_bits_ctr;</a>
+<a name="197"><span class="lineNum">     197 </span>            :   wire        _tables_3_io_resps_0_bits_u;</a>
+<a name="198"><span class="lineNum">     198 </span>            :   wire        _tables_3_io_resps_0_bits_unconf;</a>
+<a name="199"><span class="lineNum">     199 </span>            :   wire        _tables_3_io_resps_1_valid;</a>
+<a name="200"><span class="lineNum">     200 </span>            :   wire [2:0]  _tables_3_io_resps_1_bits_ctr;</a>
+<a name="201"><span class="lineNum">     201 </span>            :   wire        _tables_3_io_resps_1_bits_u;</a>
+<a name="202"><span class="lineNum">     202 </span>            :   wire        _tables_3_io_resps_1_bits_unconf;</a>
+<a name="203"><span class="lineNum">     203 </span>            :   wire        _tables_2_io_req_ready;</a>
+<a name="204"><span class="lineNum">     204 </span>            :   wire        _tables_2_io_resps_0_valid;</a>
+<a name="205"><span class="lineNum">     205 </span>            :   wire [2:0]  _tables_2_io_resps_0_bits_ctr;</a>
+<a name="206"><span class="lineNum">     206 </span>            :   wire        _tables_2_io_resps_0_bits_u;</a>
+<a name="207"><span class="lineNum">     207 </span>            :   wire        _tables_2_io_resps_0_bits_unconf;</a>
+<a name="208"><span class="lineNum">     208 </span>            :   wire        _tables_2_io_resps_1_valid;</a>
+<a name="209"><span class="lineNum">     209 </span>            :   wire [2:0]  _tables_2_io_resps_1_bits_ctr;</a>
+<a name="210"><span class="lineNum">     210 </span>            :   wire        _tables_2_io_resps_1_bits_u;</a>
+<a name="211"><span class="lineNum">     211 </span>            :   wire        _tables_2_io_resps_1_bits_unconf;</a>
+<a name="212"><span class="lineNum">     212 </span>            :   wire        _tables_1_io_req_ready;</a>
+<a name="213"><span class="lineNum">     213 </span>            :   wire        _tables_1_io_resps_0_valid;</a>
+<a name="214"><span class="lineNum">     214 </span>            :   wire [2:0]  _tables_1_io_resps_0_bits_ctr;</a>
+<a name="215"><span class="lineNum">     215 </span>            :   wire        _tables_1_io_resps_0_bits_u;</a>
+<a name="216"><span class="lineNum">     216 </span>            :   wire        _tables_1_io_resps_0_bits_unconf;</a>
+<a name="217"><span class="lineNum">     217 </span>            :   wire        _tables_1_io_resps_1_valid;</a>
+<a name="218"><span class="lineNum">     218 </span>            :   wire [2:0]  _tables_1_io_resps_1_bits_ctr;</a>
+<a name="219"><span class="lineNum">     219 </span>            :   wire        _tables_1_io_resps_1_bits_u;</a>
+<a name="220"><span class="lineNum">     220 </span>            :   wire        _tables_1_io_resps_1_bits_unconf;</a>
+<a name="221"><span class="lineNum">     221 </span>            :   wire        _tables_0_io_req_ready;</a>
+<a name="222"><span class="lineNum">     222 </span>            :   wire        _tables_0_io_resps_0_valid;</a>
+<a name="223"><span class="lineNum">     223 </span>            :   wire [2:0]  _tables_0_io_resps_0_bits_ctr;</a>
+<a name="224"><span class="lineNum">     224 </span>            :   wire        _tables_0_io_resps_0_bits_u;</a>
+<a name="225"><span class="lineNum">     225 </span>            :   wire        _tables_0_io_resps_0_bits_unconf;</a>
+<a name="226"><span class="lineNum">     226 </span>            :   wire        _tables_0_io_resps_1_valid;</a>
+<a name="227"><span class="lineNum">     227 </span>            :   wire [2:0]  _tables_0_io_resps_1_bits_ctr;</a>
+<a name="228"><span class="lineNum">     228 </span>            :   wire        _tables_0_io_resps_1_bits_u;</a>
+<a name="229"><span class="lineNum">     229 </span>            :   wire        _tables_0_io_resps_1_bits_unconf;</a>
+<a name="230"><span class="lineNum">     230 </span>            :   wire [35:0] _reset_vector_delay_io_out;</a>
+<a name="231"><span class="lineNum">     231 </span><span class="lineCov">      10114 :   reg  [40:0] s1_pc_dup_0;</span></a>
+<a name="232"><span class="lineNum">     232 </span><span class="lineCov">         79 :   reg         REG;</span></a>
+<a name="233"><span class="lineNum">     233 </span><span class="lineCov">        102 :   reg         REG_1;</span></a>
+<a name="234"><span class="lineNum">     234 </span><span class="lineCov">        173 :   reg  [6:0]  bankTickCtrDistanceToTops_0;</span></a>
+<a name="235"><span class="lineNum">     235 </span><span class="lineCov">        169 :   reg  [6:0]  bankTickCtrDistanceToTops_1;</span></a>
+<a name="236"><span class="lineNum">     236 </span><span class="lineCov">        152 :   reg  [6:0]  bankTickCtrs_0;</span></a>
+<a name="237"><span class="lineNum">     237 </span><span class="lineCov">        161 :   reg  [6:0]  bankTickCtrs_1;</span></a>
+<a name="238"><span class="lineNum">     238 </span><span class="lineCov">         88 :   reg  [3:0]  useAltOnNaCtrs_0_0;</span></a>
+<a name="239"><span class="lineNum">     239 </span><span class="lineCov">        100 :   reg  [3:0]  useAltOnNaCtrs_0_1;</span></a>
+<a name="240"><span class="lineNum">     240 </span><span class="lineCov">         87 :   reg  [3:0]  useAltOnNaCtrs_0_2;</span></a>
+<a name="241"><span class="lineNum">     241 </span><span class="lineCov">         84 :   reg  [3:0]  useAltOnNaCtrs_0_3;</span></a>
+<a name="242"><span class="lineNum">     242 </span><span class="lineCov">         91 :   reg  [3:0]  useAltOnNaCtrs_0_4;</span></a>
+<a name="243"><span class="lineNum">     243 </span><span class="lineCov">         85 :   reg  [3:0]  useAltOnNaCtrs_0_5;</span></a>
+<a name="244"><span class="lineNum">     244 </span><span class="lineCov">         93 :   reg  [3:0]  useAltOnNaCtrs_0_6;</span></a>
+<a name="245"><span class="lineNum">     245 </span><span class="lineCov">         85 :   reg  [3:0]  useAltOnNaCtrs_0_7;</span></a>
+<a name="246"><span class="lineNum">     246 </span><span class="lineCov">         94 :   reg  [3:0]  useAltOnNaCtrs_0_8;</span></a>
+<a name="247"><span class="lineNum">     247 </span><span class="lineCov">         91 :   reg  [3:0]  useAltOnNaCtrs_0_9;</span></a>
+<a name="248"><span class="lineNum">     248 </span><span class="lineCov">         90 :   reg  [3:0]  useAltOnNaCtrs_0_10;</span></a>
+<a name="249"><span class="lineNum">     249 </span><span class="lineCov">         92 :   reg  [3:0]  useAltOnNaCtrs_0_11;</span></a>
+<a name="250"><span class="lineNum">     250 </span><span class="lineCov">         93 :   reg  [3:0]  useAltOnNaCtrs_0_12;</span></a>
+<a name="251"><span class="lineNum">     251 </span><span class="lineCov">        108 :   reg  [3:0]  useAltOnNaCtrs_0_13;</span></a>
+<a name="252"><span class="lineNum">     252 </span><span class="lineCov">         99 :   reg  [3:0]  useAltOnNaCtrs_0_14;</span></a>
+<a name="253"><span class="lineNum">     253 </span><span class="lineCov">         92 :   reg  [3:0]  useAltOnNaCtrs_0_15;</span></a>
+<a name="254"><span class="lineNum">     254 </span><span class="lineCov">         96 :   reg  [3:0]  useAltOnNaCtrs_0_16;</span></a>
+<a name="255"><span class="lineNum">     255 </span><span class="lineCov">         83 :   reg  [3:0]  useAltOnNaCtrs_0_17;</span></a>
+<a name="256"><span class="lineNum">     256 </span><span class="lineCov">         89 :   reg  [3:0]  useAltOnNaCtrs_0_18;</span></a>
+<a name="257"><span class="lineNum">     257 </span><span class="lineCov">         90 :   reg  [3:0]  useAltOnNaCtrs_0_19;</span></a>
+<a name="258"><span class="lineNum">     258 </span><span class="lineCov">         94 :   reg  [3:0]  useAltOnNaCtrs_0_20;</span></a>
+<a name="259"><span class="lineNum">     259 </span><span class="lineCov">         91 :   reg  [3:0]  useAltOnNaCtrs_0_21;</span></a>
+<a name="260"><span class="lineNum">     260 </span><span class="lineCov">        102 :   reg  [3:0]  useAltOnNaCtrs_0_22;</span></a>
+<a name="261"><span class="lineNum">     261 </span><span class="lineCov">         96 :   reg  [3:0]  useAltOnNaCtrs_0_23;</span></a>
+<a name="262"><span class="lineNum">     262 </span><span class="lineCov">         97 :   reg  [3:0]  useAltOnNaCtrs_0_24;</span></a>
+<a name="263"><span class="lineNum">     263 </span><span class="lineCov">         91 :   reg  [3:0]  useAltOnNaCtrs_0_25;</span></a>
+<a name="264"><span class="lineNum">     264 </span><span class="lineCov">         92 :   reg  [3:0]  useAltOnNaCtrs_0_26;</span></a>
+<a name="265"><span class="lineNum">     265 </span><span class="lineCov">         99 :   reg  [3:0]  useAltOnNaCtrs_0_27;</span></a>
+<a name="266"><span class="lineNum">     266 </span><span class="lineCov">         95 :   reg  [3:0]  useAltOnNaCtrs_0_28;</span></a>
+<a name="267"><span class="lineNum">     267 </span><span class="lineCov">         91 :   reg  [3:0]  useAltOnNaCtrs_0_29;</span></a>
+<a name="268"><span class="lineNum">     268 </span><span class="lineCov">         97 :   reg  [3:0]  useAltOnNaCtrs_0_30;</span></a>
+<a name="269"><span class="lineNum">     269 </span><span class="lineCov">         86 :   reg  [3:0]  useAltOnNaCtrs_0_31;</span></a>
+<a name="270"><span class="lineNum">     270 </span><span class="lineCov">         88 :   reg  [3:0]  useAltOnNaCtrs_0_32;</span></a>
+<a name="271"><span class="lineNum">     271 </span><span class="lineCov">         91 :   reg  [3:0]  useAltOnNaCtrs_0_33;</span></a>
+<a name="272"><span class="lineNum">     272 </span><span class="lineCov">         97 :   reg  [3:0]  useAltOnNaCtrs_0_34;</span></a>
+<a name="273"><span class="lineNum">     273 </span><span class="lineCov">         89 :   reg  [3:0]  useAltOnNaCtrs_0_35;</span></a>
+<a name="274"><span class="lineNum">     274 </span><span class="lineCov">         83 :   reg  [3:0]  useAltOnNaCtrs_0_36;</span></a>
+<a name="275"><span class="lineNum">     275 </span><span class="lineCov">         89 :   reg  [3:0]  useAltOnNaCtrs_0_37;</span></a>
+<a name="276"><span class="lineNum">     276 </span><span class="lineCov">        101 :   reg  [3:0]  useAltOnNaCtrs_0_38;</span></a>
+<a name="277"><span class="lineNum">     277 </span><span class="lineCov">         88 :   reg  [3:0]  useAltOnNaCtrs_0_39;</span></a>
+<a name="278"><span class="lineNum">     278 </span><span class="lineCov">         95 :   reg  [3:0]  useAltOnNaCtrs_0_40;</span></a>
+<a name="279"><span class="lineNum">     279 </span><span class="lineCov">         96 :   reg  [3:0]  useAltOnNaCtrs_0_41;</span></a>
+<a name="280"><span class="lineNum">     280 </span><span class="lineCov">         97 :   reg  [3:0]  useAltOnNaCtrs_0_42;</span></a>
+<a name="281"><span class="lineNum">     281 </span><span class="lineCov">         90 :   reg  [3:0]  useAltOnNaCtrs_0_43;</span></a>
+<a name="282"><span class="lineNum">     282 </span><span class="lineCov">         82 :   reg  [3:0]  useAltOnNaCtrs_0_44;</span></a>
+<a name="283"><span class="lineNum">     283 </span><span class="lineCov">         90 :   reg  [3:0]  useAltOnNaCtrs_0_45;</span></a>
+<a name="284"><span class="lineNum">     284 </span><span class="lineCov">         89 :   reg  [3:0]  useAltOnNaCtrs_0_46;</span></a>
+<a name="285"><span class="lineNum">     285 </span><span class="lineCov">         85 :   reg  [3:0]  useAltOnNaCtrs_0_47;</span></a>
+<a name="286"><span class="lineNum">     286 </span><span class="lineCov">         94 :   reg  [3:0]  useAltOnNaCtrs_0_48;</span></a>
+<a name="287"><span class="lineNum">     287 </span><span class="lineCov">         86 :   reg  [3:0]  useAltOnNaCtrs_0_49;</span></a>
+<a name="288"><span class="lineNum">     288 </span><span class="lineCov">         90 :   reg  [3:0]  useAltOnNaCtrs_0_50;</span></a>
+<a name="289"><span class="lineNum">     289 </span><span class="lineCov">         87 :   reg  [3:0]  useAltOnNaCtrs_0_51;</span></a>
+<a name="290"><span class="lineNum">     290 </span><span class="lineCov">         99 :   reg  [3:0]  useAltOnNaCtrs_0_52;</span></a>
+<a name="291"><span class="lineNum">     291 </span><span class="lineCov">         96 :   reg  [3:0]  useAltOnNaCtrs_0_53;</span></a>
+<a name="292"><span class="lineNum">     292 </span><span class="lineCov">         95 :   reg  [3:0]  useAltOnNaCtrs_0_54;</span></a>
+<a name="293"><span class="lineNum">     293 </span><span class="lineCov">         88 :   reg  [3:0]  useAltOnNaCtrs_0_55;</span></a>
+<a name="294"><span class="lineNum">     294 </span><span class="lineCov">         77 :   reg  [3:0]  useAltOnNaCtrs_0_56;</span></a>
+<a name="295"><span class="lineNum">     295 </span><span class="lineCov">         96 :   reg  [3:0]  useAltOnNaCtrs_0_57;</span></a>
+<a name="296"><span class="lineNum">     296 </span><span class="lineCov">         87 :   reg  [3:0]  useAltOnNaCtrs_0_58;</span></a>
+<a name="297"><span class="lineNum">     297 </span><span class="lineCov">         89 :   reg  [3:0]  useAltOnNaCtrs_0_59;</span></a>
+<a name="298"><span class="lineNum">     298 </span><span class="lineCov">         91 :   reg  [3:0]  useAltOnNaCtrs_0_60;</span></a>
+<a name="299"><span class="lineNum">     299 </span><span class="lineCov">         84 :   reg  [3:0]  useAltOnNaCtrs_0_61;</span></a>
+<a name="300"><span class="lineNum">     300 </span><span class="lineCov">         96 :   reg  [3:0]  useAltOnNaCtrs_0_62;</span></a>
+<a name="301"><span class="lineNum">     301 </span><span class="lineCov">         89 :   reg  [3:0]  useAltOnNaCtrs_0_63;</span></a>
+<a name="302"><span class="lineNum">     302 </span><span class="lineCov">         86 :   reg  [3:0]  useAltOnNaCtrs_0_64;</span></a>
+<a name="303"><span class="lineNum">     303 </span><span class="lineCov">         76 :   reg  [3:0]  useAltOnNaCtrs_0_65;</span></a>
+<a name="304"><span class="lineNum">     304 </span><span class="lineCov">         99 :   reg  [3:0]  useAltOnNaCtrs_0_66;</span></a>
+<a name="305"><span class="lineNum">     305 </span><span class="lineCov">         98 :   reg  [3:0]  useAltOnNaCtrs_0_67;</span></a>
+<a name="306"><span class="lineNum">     306 </span><span class="lineCov">         94 :   reg  [3:0]  useAltOnNaCtrs_0_68;</span></a>
+<a name="307"><span class="lineNum">     307 </span><span class="lineCov">         94 :   reg  [3:0]  useAltOnNaCtrs_0_69;</span></a>
+<a name="308"><span class="lineNum">     308 </span><span class="lineCov">         97 :   reg  [3:0]  useAltOnNaCtrs_0_70;</span></a>
+<a name="309"><span class="lineNum">     309 </span><span class="lineCov">         98 :   reg  [3:0]  useAltOnNaCtrs_0_71;</span></a>
+<a name="310"><span class="lineNum">     310 </span><span class="lineCov">         90 :   reg  [3:0]  useAltOnNaCtrs_0_72;</span></a>
+<a name="311"><span class="lineNum">     311 </span><span class="lineCov">        100 :   reg  [3:0]  useAltOnNaCtrs_0_73;</span></a>
+<a name="312"><span class="lineNum">     312 </span><span class="lineCov">         86 :   reg  [3:0]  useAltOnNaCtrs_0_74;</span></a>
+<a name="313"><span class="lineNum">     313 </span><span class="lineCov">         90 :   reg  [3:0]  useAltOnNaCtrs_0_75;</span></a>
+<a name="314"><span class="lineNum">     314 </span><span class="lineCov">         89 :   reg  [3:0]  useAltOnNaCtrs_0_76;</span></a>
+<a name="315"><span class="lineNum">     315 </span><span class="lineCov">         85 :   reg  [3:0]  useAltOnNaCtrs_0_77;</span></a>
+<a name="316"><span class="lineNum">     316 </span><span class="lineCov">         86 :   reg  [3:0]  useAltOnNaCtrs_0_78;</span></a>
+<a name="317"><span class="lineNum">     317 </span><span class="lineCov">         90 :   reg  [3:0]  useAltOnNaCtrs_0_79;</span></a>
+<a name="318"><span class="lineNum">     318 </span><span class="lineCov">         82 :   reg  [3:0]  useAltOnNaCtrs_0_80;</span></a>
+<a name="319"><span class="lineNum">     319 </span><span class="lineCov">         93 :   reg  [3:0]  useAltOnNaCtrs_0_81;</span></a>
+<a name="320"><span class="lineNum">     320 </span><span class="lineCov">         91 :   reg  [3:0]  useAltOnNaCtrs_0_82;</span></a>
+<a name="321"><span class="lineNum">     321 </span><span class="lineCov">         83 :   reg  [3:0]  useAltOnNaCtrs_0_83;</span></a>
+<a name="322"><span class="lineNum">     322 </span><span class="lineCov">         82 :   reg  [3:0]  useAltOnNaCtrs_0_84;</span></a>
+<a name="323"><span class="lineNum">     323 </span><span class="lineCov">         87 :   reg  [3:0]  useAltOnNaCtrs_0_85;</span></a>
+<a name="324"><span class="lineNum">     324 </span><span class="lineCov">         96 :   reg  [3:0]  useAltOnNaCtrs_0_86;</span></a>
+<a name="325"><span class="lineNum">     325 </span><span class="lineCov">        101 :   reg  [3:0]  useAltOnNaCtrs_0_87;</span></a>
+<a name="326"><span class="lineNum">     326 </span><span class="lineCov">         83 :   reg  [3:0]  useAltOnNaCtrs_0_88;</span></a>
+<a name="327"><span class="lineNum">     327 </span><span class="lineCov">         90 :   reg  [3:0]  useAltOnNaCtrs_0_89;</span></a>
+<a name="328"><span class="lineNum">     328 </span><span class="lineCov">        103 :   reg  [3:0]  useAltOnNaCtrs_0_90;</span></a>
+<a name="329"><span class="lineNum">     329 </span><span class="lineCov">         84 :   reg  [3:0]  useAltOnNaCtrs_0_91;</span></a>
+<a name="330"><span class="lineNum">     330 </span><span class="lineCov">         89 :   reg  [3:0]  useAltOnNaCtrs_0_92;</span></a>
+<a name="331"><span class="lineNum">     331 </span><span class="lineCov">         98 :   reg  [3:0]  useAltOnNaCtrs_0_93;</span></a>
+<a name="332"><span class="lineNum">     332 </span><span class="lineCov">         76 :   reg  [3:0]  useAltOnNaCtrs_0_94;</span></a>
+<a name="333"><span class="lineNum">     333 </span><span class="lineCov">         88 :   reg  [3:0]  useAltOnNaCtrs_0_95;</span></a>
+<a name="334"><span class="lineNum">     334 </span><span class="lineCov">         97 :   reg  [3:0]  useAltOnNaCtrs_0_96;</span></a>
+<a name="335"><span class="lineNum">     335 </span><span class="lineCov">         79 :   reg  [3:0]  useAltOnNaCtrs_0_97;</span></a>
+<a name="336"><span class="lineNum">     336 </span><span class="lineCov">         98 :   reg  [3:0]  useAltOnNaCtrs_0_98;</span></a>
+<a name="337"><span class="lineNum">     337 </span><span class="lineCov">         93 :   reg  [3:0]  useAltOnNaCtrs_0_99;</span></a>
+<a name="338"><span class="lineNum">     338 </span><span class="lineCov">         85 :   reg  [3:0]  useAltOnNaCtrs_0_100;</span></a>
+<a name="339"><span class="lineNum">     339 </span><span class="lineCov">         99 :   reg  [3:0]  useAltOnNaCtrs_0_101;</span></a>
+<a name="340"><span class="lineNum">     340 </span><span class="lineCov">         90 :   reg  [3:0]  useAltOnNaCtrs_0_102;</span></a>
+<a name="341"><span class="lineNum">     341 </span><span class="lineCov">         98 :   reg  [3:0]  useAltOnNaCtrs_0_103;</span></a>
+<a name="342"><span class="lineNum">     342 </span><span class="lineCov">         96 :   reg  [3:0]  useAltOnNaCtrs_0_104;</span></a>
+<a name="343"><span class="lineNum">     343 </span><span class="lineCov">         83 :   reg  [3:0]  useAltOnNaCtrs_0_105;</span></a>
+<a name="344"><span class="lineNum">     344 </span><span class="lineCov">         88 :   reg  [3:0]  useAltOnNaCtrs_0_106;</span></a>
+<a name="345"><span class="lineNum">     345 </span><span class="lineCov">         96 :   reg  [3:0]  useAltOnNaCtrs_0_107;</span></a>
+<a name="346"><span class="lineNum">     346 </span><span class="lineCov">        105 :   reg  [3:0]  useAltOnNaCtrs_0_108;</span></a>
+<a name="347"><span class="lineNum">     347 </span><span class="lineCov">         91 :   reg  [3:0]  useAltOnNaCtrs_0_109;</span></a>
+<a name="348"><span class="lineNum">     348 </span><span class="lineCov">         98 :   reg  [3:0]  useAltOnNaCtrs_0_110;</span></a>
+<a name="349"><span class="lineNum">     349 </span><span class="lineCov">        104 :   reg  [3:0]  useAltOnNaCtrs_0_111;</span></a>
+<a name="350"><span class="lineNum">     350 </span><span class="lineCov">         89 :   reg  [3:0]  useAltOnNaCtrs_0_112;</span></a>
+<a name="351"><span class="lineNum">     351 </span><span class="lineCov">         78 :   reg  [3:0]  useAltOnNaCtrs_0_113;</span></a>
+<a name="352"><span class="lineNum">     352 </span><span class="lineCov">         89 :   reg  [3:0]  useAltOnNaCtrs_0_114;</span></a>
+<a name="353"><span class="lineNum">     353 </span><span class="lineCov">         84 :   reg  [3:0]  useAltOnNaCtrs_0_115;</span></a>
+<a name="354"><span class="lineNum">     354 </span><span class="lineCov">         81 :   reg  [3:0]  useAltOnNaCtrs_0_116;</span></a>
+<a name="355"><span class="lineNum">     355 </span><span class="lineCov">         98 :   reg  [3:0]  useAltOnNaCtrs_0_117;</span></a>
+<a name="356"><span class="lineNum">     356 </span><span class="lineCov">         88 :   reg  [3:0]  useAltOnNaCtrs_0_118;</span></a>
+<a name="357"><span class="lineNum">     357 </span><span class="lineCov">         86 :   reg  [3:0]  useAltOnNaCtrs_0_119;</span></a>
+<a name="358"><span class="lineNum">     358 </span><span class="lineCov">         83 :   reg  [3:0]  useAltOnNaCtrs_0_120;</span></a>
+<a name="359"><span class="lineNum">     359 </span><span class="lineCov">         86 :   reg  [3:0]  useAltOnNaCtrs_0_121;</span></a>
+<a name="360"><span class="lineNum">     360 </span><span class="lineCov">         92 :   reg  [3:0]  useAltOnNaCtrs_0_122;</span></a>
+<a name="361"><span class="lineNum">     361 </span><span class="lineCov">         87 :   reg  [3:0]  useAltOnNaCtrs_0_123;</span></a>
+<a name="362"><span class="lineNum">     362 </span><span class="lineCov">         87 :   reg  [3:0]  useAltOnNaCtrs_0_124;</span></a>
+<a name="363"><span class="lineNum">     363 </span><span class="lineCov">         90 :   reg  [3:0]  useAltOnNaCtrs_0_125;</span></a>
+<a name="364"><span class="lineNum">     364 </span><span class="lineCov">         92 :   reg  [3:0]  useAltOnNaCtrs_0_126;</span></a>
+<a name="365"><span class="lineNum">     365 </span><span class="lineCov">        102 :   reg  [3:0]  useAltOnNaCtrs_0_127;</span></a>
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+<a name="367"><span class="lineNum">     367 </span><span class="lineCov">         86 :   reg  [3:0]  useAltOnNaCtrs_1_1;</span></a>
+<a name="368"><span class="lineNum">     368 </span><span class="lineCov">         92 :   reg  [3:0]  useAltOnNaCtrs_1_2;</span></a>
+<a name="369"><span class="lineNum">     369 </span><span class="lineCov">         96 :   reg  [3:0]  useAltOnNaCtrs_1_3;</span></a>
+<a name="370"><span class="lineNum">     370 </span><span class="lineCov">        101 :   reg  [3:0]  useAltOnNaCtrs_1_4;</span></a>
+<a name="371"><span class="lineNum">     371 </span><span class="lineCov">         93 :   reg  [3:0]  useAltOnNaCtrs_1_5;</span></a>
+<a name="372"><span class="lineNum">     372 </span><span class="lineCov">         98 :   reg  [3:0]  useAltOnNaCtrs_1_6;</span></a>
+<a name="373"><span class="lineNum">     373 </span><span class="lineCov">         83 :   reg  [3:0]  useAltOnNaCtrs_1_7;</span></a>
+<a name="374"><span class="lineNum">     374 </span><span class="lineCov">         98 :   reg  [3:0]  useAltOnNaCtrs_1_8;</span></a>
+<a name="375"><span class="lineNum">     375 </span><span class="lineCov">         95 :   reg  [3:0]  useAltOnNaCtrs_1_9;</span></a>
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+<a name="377"><span class="lineNum">     377 </span><span class="lineCov">         90 :   reg  [3:0]  useAltOnNaCtrs_1_11;</span></a>
+<a name="378"><span class="lineNum">     378 </span><span class="lineCov">         90 :   reg  [3:0]  useAltOnNaCtrs_1_12;</span></a>
+<a name="379"><span class="lineNum">     379 </span><span class="lineCov">        100 :   reg  [3:0]  useAltOnNaCtrs_1_13;</span></a>
+<a name="380"><span class="lineNum">     380 </span><span class="lineCov">        104 :   reg  [3:0]  useAltOnNaCtrs_1_14;</span></a>
+<a name="381"><span class="lineNum">     381 </span><span class="lineCov">         95 :   reg  [3:0]  useAltOnNaCtrs_1_15;</span></a>
+<a name="382"><span class="lineNum">     382 </span><span class="lineCov">         86 :   reg  [3:0]  useAltOnNaCtrs_1_16;</span></a>
+<a name="383"><span class="lineNum">     383 </span><span class="lineCov">         98 :   reg  [3:0]  useAltOnNaCtrs_1_17;</span></a>
+<a name="384"><span class="lineNum">     384 </span><span class="lineCov">         92 :   reg  [3:0]  useAltOnNaCtrs_1_18;</span></a>
+<a name="385"><span class="lineNum">     385 </span><span class="lineCov">         89 :   reg  [3:0]  useAltOnNaCtrs_1_19;</span></a>
+<a name="386"><span class="lineNum">     386 </span><span class="lineCov">        103 :   reg  [3:0]  useAltOnNaCtrs_1_20;</span></a>
+<a name="387"><span class="lineNum">     387 </span><span class="lineCov">         94 :   reg  [3:0]  useAltOnNaCtrs_1_21;</span></a>
+<a name="388"><span class="lineNum">     388 </span><span class="lineCov">         96 :   reg  [3:0]  useAltOnNaCtrs_1_22;</span></a>
+<a name="389"><span class="lineNum">     389 </span><span class="lineCov">         98 :   reg  [3:0]  useAltOnNaCtrs_1_23;</span></a>
+<a name="390"><span class="lineNum">     390 </span><span class="lineCov">         91 :   reg  [3:0]  useAltOnNaCtrs_1_24;</span></a>
+<a name="391"><span class="lineNum">     391 </span><span class="lineCov">        100 :   reg  [3:0]  useAltOnNaCtrs_1_25;</span></a>
+<a name="392"><span class="lineNum">     392 </span><span class="lineCov">         90 :   reg  [3:0]  useAltOnNaCtrs_1_26;</span></a>
+<a name="393"><span class="lineNum">     393 </span><span class="lineCov">        103 :   reg  [3:0]  useAltOnNaCtrs_1_27;</span></a>
+<a name="394"><span class="lineNum">     394 </span><span class="lineCov">         87 :   reg  [3:0]  useAltOnNaCtrs_1_28;</span></a>
+<a name="395"><span class="lineNum">     395 </span><span class="lineCov">         97 :   reg  [3:0]  useAltOnNaCtrs_1_29;</span></a>
+<a name="396"><span class="lineNum">     396 </span><span class="lineCov">         97 :   reg  [3:0]  useAltOnNaCtrs_1_30;</span></a>
+<a name="397"><span class="lineNum">     397 </span><span class="lineCov">         88 :   reg  [3:0]  useAltOnNaCtrs_1_31;</span></a>
+<a name="398"><span class="lineNum">     398 </span><span class="lineCov">         92 :   reg  [3:0]  useAltOnNaCtrs_1_32;</span></a>
+<a name="399"><span class="lineNum">     399 </span><span class="lineCov">         97 :   reg  [3:0]  useAltOnNaCtrs_1_33;</span></a>
+<a name="400"><span class="lineNum">     400 </span><span class="lineCov">        103 :   reg  [3:0]  useAltOnNaCtrs_1_34;</span></a>
+<a name="401"><span class="lineNum">     401 </span><span class="lineCov">         86 :   reg  [3:0]  useAltOnNaCtrs_1_35;</span></a>
+<a name="402"><span class="lineNum">     402 </span><span class="lineCov">         88 :   reg  [3:0]  useAltOnNaCtrs_1_36;</span></a>
+<a name="403"><span class="lineNum">     403 </span><span class="lineCov">         94 :   reg  [3:0]  useAltOnNaCtrs_1_37;</span></a>
+<a name="404"><span class="lineNum">     404 </span><span class="lineCov">         94 :   reg  [3:0]  useAltOnNaCtrs_1_38;</span></a>
+<a name="405"><span class="lineNum">     405 </span><span class="lineCov">         99 :   reg  [3:0]  useAltOnNaCtrs_1_39;</span></a>
+<a name="406"><span class="lineNum">     406 </span><span class="lineCov">         84 :   reg  [3:0]  useAltOnNaCtrs_1_40;</span></a>
+<a name="407"><span class="lineNum">     407 </span><span class="lineCov">         82 :   reg  [3:0]  useAltOnNaCtrs_1_41;</span></a>
+<a name="408"><span class="lineNum">     408 </span><span class="lineCov">        100 :   reg  [3:0]  useAltOnNaCtrs_1_42;</span></a>
+<a name="409"><span class="lineNum">     409 </span><span class="lineCov">         85 :   reg  [3:0]  useAltOnNaCtrs_1_43;</span></a>
+<a name="410"><span class="lineNum">     410 </span><span class="lineCov">        101 :   reg  [3:0]  useAltOnNaCtrs_1_44;</span></a>
+<a name="411"><span class="lineNum">     411 </span><span class="lineCov">        106 :   reg  [3:0]  useAltOnNaCtrs_1_45;</span></a>
+<a name="412"><span class="lineNum">     412 </span><span class="lineCov">         91 :   reg  [3:0]  useAltOnNaCtrs_1_46;</span></a>
+<a name="413"><span class="lineNum">     413 </span><span class="lineCov">         88 :   reg  [3:0]  useAltOnNaCtrs_1_47;</span></a>
+<a name="414"><span class="lineNum">     414 </span><span class="lineCov">         88 :   reg  [3:0]  useAltOnNaCtrs_1_48;</span></a>
+<a name="415"><span class="lineNum">     415 </span><span class="lineCov">         84 :   reg  [3:0]  useAltOnNaCtrs_1_49;</span></a>
+<a name="416"><span class="lineNum">     416 </span><span class="lineCov">         76 :   reg  [3:0]  useAltOnNaCtrs_1_50;</span></a>
+<a name="417"><span class="lineNum">     417 </span><span class="lineCov">         89 :   reg  [3:0]  useAltOnNaCtrs_1_51;</span></a>
+<a name="418"><span class="lineNum">     418 </span><span class="lineCov">         83 :   reg  [3:0]  useAltOnNaCtrs_1_52;</span></a>
+<a name="419"><span class="lineNum">     419 </span><span class="lineCov">        100 :   reg  [3:0]  useAltOnNaCtrs_1_53;</span></a>
+<a name="420"><span class="lineNum">     420 </span><span class="lineCov">         96 :   reg  [3:0]  useAltOnNaCtrs_1_54;</span></a>
+<a name="421"><span class="lineNum">     421 </span><span class="lineCov">         92 :   reg  [3:0]  useAltOnNaCtrs_1_55;</span></a>
+<a name="422"><span class="lineNum">     422 </span><span class="lineCov">        102 :   reg  [3:0]  useAltOnNaCtrs_1_56;</span></a>
+<a name="423"><span class="lineNum">     423 </span><span class="lineCov">         98 :   reg  [3:0]  useAltOnNaCtrs_1_57;</span></a>
+<a name="424"><span class="lineNum">     424 </span><span class="lineCov">         89 :   reg  [3:0]  useAltOnNaCtrs_1_58;</span></a>
+<a name="425"><span class="lineNum">     425 </span><span class="lineCov">         93 :   reg  [3:0]  useAltOnNaCtrs_1_59;</span></a>
+<a name="426"><span class="lineNum">     426 </span><span class="lineCov">         82 :   reg  [3:0]  useAltOnNaCtrs_1_60;</span></a>
+<a name="427"><span class="lineNum">     427 </span><span class="lineCov">         86 :   reg  [3:0]  useAltOnNaCtrs_1_61;</span></a>
+<a name="428"><span class="lineNum">     428 </span><span class="lineCov">         96 :   reg  [3:0]  useAltOnNaCtrs_1_62;</span></a>
+<a name="429"><span class="lineNum">     429 </span><span class="lineCov">         86 :   reg  [3:0]  useAltOnNaCtrs_1_63;</span></a>
+<a name="430"><span class="lineNum">     430 </span><span class="lineCov">         97 :   reg  [3:0]  useAltOnNaCtrs_1_64;</span></a>
+<a name="431"><span class="lineNum">     431 </span><span class="lineCov">        106 :   reg  [3:0]  useAltOnNaCtrs_1_65;</span></a>
+<a name="432"><span class="lineNum">     432 </span><span class="lineCov">        100 :   reg  [3:0]  useAltOnNaCtrs_1_66;</span></a>
+<a name="433"><span class="lineNum">     433 </span><span class="lineCov">         92 :   reg  [3:0]  useAltOnNaCtrs_1_67;</span></a>
+<a name="434"><span class="lineNum">     434 </span><span class="lineCov">         94 :   reg  [3:0]  useAltOnNaCtrs_1_68;</span></a>
+<a name="435"><span class="lineNum">     435 </span><span class="lineCov">         95 :   reg  [3:0]  useAltOnNaCtrs_1_69;</span></a>
+<a name="436"><span class="lineNum">     436 </span><span class="lineCov">         83 :   reg  [3:0]  useAltOnNaCtrs_1_70;</span></a>
+<a name="437"><span class="lineNum">     437 </span><span class="lineCov">         96 :   reg  [3:0]  useAltOnNaCtrs_1_71;</span></a>
+<a name="438"><span class="lineNum">     438 </span><span class="lineCov">         94 :   reg  [3:0]  useAltOnNaCtrs_1_72;</span></a>
+<a name="439"><span class="lineNum">     439 </span><span class="lineCov">         81 :   reg  [3:0]  useAltOnNaCtrs_1_73;</span></a>
+<a name="440"><span class="lineNum">     440 </span><span class="lineCov">         84 :   reg  [3:0]  useAltOnNaCtrs_1_74;</span></a>
+<a name="441"><span class="lineNum">     441 </span><span class="lineCov">         87 :   reg  [3:0]  useAltOnNaCtrs_1_75;</span></a>
+<a name="442"><span class="lineNum">     442 </span><span class="lineCov">         92 :   reg  [3:0]  useAltOnNaCtrs_1_76;</span></a>
+<a name="443"><span class="lineNum">     443 </span><span class="lineCov">         89 :   reg  [3:0]  useAltOnNaCtrs_1_77;</span></a>
+<a name="444"><span class="lineNum">     444 </span><span class="lineCov">         98 :   reg  [3:0]  useAltOnNaCtrs_1_78;</span></a>
+<a name="445"><span class="lineNum">     445 </span><span class="lineCov">         82 :   reg  [3:0]  useAltOnNaCtrs_1_79;</span></a>
+<a name="446"><span class="lineNum">     446 </span><span class="lineCov">         74 :   reg  [3:0]  useAltOnNaCtrs_1_80;</span></a>
+<a name="447"><span class="lineNum">     447 </span><span class="lineCov">         99 :   reg  [3:0]  useAltOnNaCtrs_1_81;</span></a>
+<a name="448"><span class="lineNum">     448 </span><span class="lineCov">         92 :   reg  [3:0]  useAltOnNaCtrs_1_82;</span></a>
+<a name="449"><span class="lineNum">     449 </span><span class="lineCov">         84 :   reg  [3:0]  useAltOnNaCtrs_1_83;</span></a>
+<a name="450"><span class="lineNum">     450 </span><span class="lineCov">         94 :   reg  [3:0]  useAltOnNaCtrs_1_84;</span></a>
+<a name="451"><span class="lineNum">     451 </span><span class="lineCov">        101 :   reg  [3:0]  useAltOnNaCtrs_1_85;</span></a>
+<a name="452"><span class="lineNum">     452 </span><span class="lineCov">         97 :   reg  [3:0]  useAltOnNaCtrs_1_86;</span></a>
+<a name="453"><span class="lineNum">     453 </span><span class="lineCov">         97 :   reg  [3:0]  useAltOnNaCtrs_1_87;</span></a>
+<a name="454"><span class="lineNum">     454 </span><span class="lineCov">         92 :   reg  [3:0]  useAltOnNaCtrs_1_88;</span></a>
+<a name="455"><span class="lineNum">     455 </span><span class="lineCov">         91 :   reg  [3:0]  useAltOnNaCtrs_1_89;</span></a>
+<a name="456"><span class="lineNum">     456 </span><span class="lineCov">         92 :   reg  [3:0]  useAltOnNaCtrs_1_90;</span></a>
+<a name="457"><span class="lineNum">     457 </span><span class="lineCov">         89 :   reg  [3:0]  useAltOnNaCtrs_1_91;</span></a>
+<a name="458"><span class="lineNum">     458 </span><span class="lineCov">        106 :   reg  [3:0]  useAltOnNaCtrs_1_92;</span></a>
+<a name="459"><span class="lineNum">     459 </span><span class="lineCov">         92 :   reg  [3:0]  useAltOnNaCtrs_1_93;</span></a>
+<a name="460"><span class="lineNum">     460 </span><span class="lineCov">         86 :   reg  [3:0]  useAltOnNaCtrs_1_94;</span></a>
+<a name="461"><span class="lineNum">     461 </span><span class="lineCov">         94 :   reg  [3:0]  useAltOnNaCtrs_1_95;</span></a>
+<a name="462"><span class="lineNum">     462 </span><span class="lineCov">        103 :   reg  [3:0]  useAltOnNaCtrs_1_96;</span></a>
+<a name="463"><span class="lineNum">     463 </span><span class="lineCov">         87 :   reg  [3:0]  useAltOnNaCtrs_1_97;</span></a>
+<a name="464"><span class="lineNum">     464 </span><span class="lineCov">         90 :   reg  [3:0]  useAltOnNaCtrs_1_98;</span></a>
+<a name="465"><span class="lineNum">     465 </span><span class="lineCov">         99 :   reg  [3:0]  useAltOnNaCtrs_1_99;</span></a>
+<a name="466"><span class="lineNum">     466 </span><span class="lineCov">         99 :   reg  [3:0]  useAltOnNaCtrs_1_100;</span></a>
+<a name="467"><span class="lineNum">     467 </span><span class="lineCov">         91 :   reg  [3:0]  useAltOnNaCtrs_1_101;</span></a>
+<a name="468"><span class="lineNum">     468 </span><span class="lineCov">        101 :   reg  [3:0]  useAltOnNaCtrs_1_102;</span></a>
+<a name="469"><span class="lineNum">     469 </span><span class="lineCov">         85 :   reg  [3:0]  useAltOnNaCtrs_1_103;</span></a>
+<a name="470"><span class="lineNum">     470 </span><span class="lineCov">         96 :   reg  [3:0]  useAltOnNaCtrs_1_104;</span></a>
+<a name="471"><span class="lineNum">     471 </span><span class="lineCov">         95 :   reg  [3:0]  useAltOnNaCtrs_1_105;</span></a>
+<a name="472"><span class="lineNum">     472 </span><span class="lineCov">         90 :   reg  [3:0]  useAltOnNaCtrs_1_106;</span></a>
+<a name="473"><span class="lineNum">     473 </span><span class="lineCov">         87 :   reg  [3:0]  useAltOnNaCtrs_1_107;</span></a>
+<a name="474"><span class="lineNum">     474 </span><span class="lineCov">         95 :   reg  [3:0]  useAltOnNaCtrs_1_108;</span></a>
+<a name="475"><span class="lineNum">     475 </span><span class="lineCov">         74 :   reg  [3:0]  useAltOnNaCtrs_1_109;</span></a>
+<a name="476"><span class="lineNum">     476 </span><span class="lineCov">         94 :   reg  [3:0]  useAltOnNaCtrs_1_110;</span></a>
+<a name="477"><span class="lineNum">     477 </span><span class="lineCov">         89 :   reg  [3:0]  useAltOnNaCtrs_1_111;</span></a>
+<a name="478"><span class="lineNum">     478 </span><span class="lineCov">         88 :   reg  [3:0]  useAltOnNaCtrs_1_112;</span></a>
+<a name="479"><span class="lineNum">     479 </span><span class="lineCov">         89 :   reg  [3:0]  useAltOnNaCtrs_1_113;</span></a>
+<a name="480"><span class="lineNum">     480 </span><span class="lineCov">         88 :   reg  [3:0]  useAltOnNaCtrs_1_114;</span></a>
+<a name="481"><span class="lineNum">     481 </span><span class="lineCov">         92 :   reg  [3:0]  useAltOnNaCtrs_1_115;</span></a>
+<a name="482"><span class="lineNum">     482 </span><span class="lineCov">         99 :   reg  [3:0]  useAltOnNaCtrs_1_116;</span></a>
+<a name="483"><span class="lineNum">     483 </span><span class="lineCov">        112 :   reg  [3:0]  useAltOnNaCtrs_1_117;</span></a>
+<a name="484"><span class="lineNum">     484 </span><span class="lineCov">        105 :   reg  [3:0]  useAltOnNaCtrs_1_118;</span></a>
+<a name="485"><span class="lineNum">     485 </span><span class="lineCov">        105 :   reg  [3:0]  useAltOnNaCtrs_1_119;</span></a>
+<a name="486"><span class="lineNum">     486 </span><span class="lineCov">         97 :   reg  [3:0]  useAltOnNaCtrs_1_120;</span></a>
+<a name="487"><span class="lineNum">     487 </span><span class="lineCov">         95 :   reg  [3:0]  useAltOnNaCtrs_1_121;</span></a>
+<a name="488"><span class="lineNum">     488 </span><span class="lineCov">         94 :   reg  [3:0]  useAltOnNaCtrs_1_122;</span></a>
+<a name="489"><span class="lineNum">     489 </span><span class="lineCov">         79 :   reg  [3:0]  useAltOnNaCtrs_1_123;</span></a>
+<a name="490"><span class="lineNum">     490 </span><span class="lineCov">         89 :   reg  [3:0]  useAltOnNaCtrs_1_124;</span></a>
+<a name="491"><span class="lineNum">     491 </span><span class="lineCov">         86 :   reg  [3:0]  useAltOnNaCtrs_1_125;</span></a>
+<a name="492"><span class="lineNum">     492 </span><span class="lineCov">        104 :   reg  [3:0]  useAltOnNaCtrs_1_126;</span></a>
+<a name="493"><span class="lineNum">     493 </span><span class="lineCov">         95 :   reg  [3:0]  useAltOnNaCtrs_1_127;</span></a>
+<a name="494"><span class="lineNum">     494 </span><span class="lineCov">         29 :   reg         s2_provideds_0;</span></a>
+<a name="495"><span class="lineNum">     495 </span><span class="lineCov">         31 :   reg         s2_provideds_1;</span></a>
+<a name="496"><span class="lineNum">     496 </span><span class="lineCov">         60 :   reg  [1:0]  s2_providers_0;</span></a>
+<a name="497"><span class="lineNum">     497 </span><span class="lineCov">         64 :   reg  [1:0]  s2_providers_1;</span></a>
+<a name="498"><span class="lineNum">     498 </span><span class="lineCov">        101 :   reg  [2:0]  s2_providerResps_0_ctr;</span></a>
+<a name="499"><span class="lineNum">     499 </span><span class="lineCov">         28 :   reg         s2_providerResps_0_u;</span></a>
+<a name="500"><span class="lineNum">     500 </span><span class="lineCov">         34 :   reg         s2_providerResps_0_unconf;</span></a>
+<a name="501"><span class="lineNum">     501 </span><span class="lineCov">        102 :   reg  [2:0]  s2_providerResps_1_ctr;</span></a>
+<a name="502"><span class="lineNum">     502 </span><span class="lineCov">         26 :   reg         s2_providerResps_1_u;</span></a>
+<a name="503"><span class="lineNum">     503 </span><span class="lineCov">         34 :   reg         s2_providerResps_1_unconf;</span></a>
+<a name="504"><span class="lineNum">     504 </span><span class="lineCov">         31 :   reg         s2_altUsed_0;</span></a>
+<a name="505"><span class="lineNum">     505 </span><span class="lineCov">         30 :   reg         s2_altUsed_1;</span></a>
+<a name="506"><span class="lineNum">     506 </span><span class="lineCov">         27 :   reg         s2_tageTakens_dup_0_0;</span></a>
+<a name="507"><span class="lineNum">     507 </span><span class="lineCov">         26 :   reg         s2_tageTakens_dup_0_1;</span></a>
+<a name="508"><span class="lineNum">     508 </span><span class="lineCov">         28 :   reg         s2_tageTakens_dup_1_0;</span></a>
+<a name="509"><span class="lineNum">     509 </span><span class="lineCov">         34 :   reg         s2_tageTakens_dup_1_1;</span></a>
+<a name="510"><span class="lineNum">     510 </span><span class="lineCov">         28 :   reg         s2_tageTakens_dup_2_0;</span></a>
+<a name="511"><span class="lineNum">     511 </span><span class="lineCov">         39 :   reg         s2_tageTakens_dup_2_1;</span></a>
+<a name="512"><span class="lineNum">     512 </span><span class="lineCov">         28 :   reg         s2_tageTakens_dup_3_0;</span></a>
+<a name="513"><span class="lineNum">     513 </span><span class="lineCov">         33 :   reg         s2_tageTakens_dup_3_1;</span></a>
+<a name="514"><span class="lineNum">     514 </span><span class="lineCov">         30 :   reg         s2_finalAltPreds_0;</span></a>
+<a name="515"><span class="lineNum">     515 </span><span class="lineCov">         35 :   reg         s2_finalAltPreds_1;</span></a>
+<a name="516"><span class="lineNum">     516 </span><span class="lineCov">         71 :   reg  [1:0]  s2_basecnts_0;</span></a>
+<a name="517"><span class="lineNum">     517 </span><span class="lineCov">         58 :   reg  [1:0]  s2_basecnts_1;</span></a>
+<a name="518"><span class="lineNum">     518 </span><span class="lineCov">         19 :   wire        updateValids_0 =</span></a>
+<a name="519"><span class="lineNum">     519 </span>            :     io_update_bits_ftb_entry_brSlots_0_valid &amp; io_update_valid</a>
+<a name="520"><span class="lineNum">     520 </span>            :     &amp; ~io_update_bits_ftb_entry_always_taken_0;</a>
+<a name="521"><span class="lineNum">     521 </span><span class="lineCov">         21 :   wire        updateValids_1 =</span></a>
+<a name="522"><span class="lineNum">     522 </span>            :     io_update_bits_ftb_entry_tailSlot_valid &amp; io_update_bits_ftb_entry_tailSlot_sharing</a>
+<a name="523"><span class="lineNum">     523 </span>            :     &amp; io_update_valid &amp; ~io_update_bits_ftb_entry_always_taken_1</a>
+<a name="524"><span class="lineNum">     524 </span>            :     &amp; ~io_update_bits_br_taken_mask_0;</a>
+<a name="525"><span class="lineNum">     525 </span><span class="lineCov">        122 :   reg  [3:0]  allocatableSlots;</span></a>
+<a name="526"><span class="lineNum">     526 </span><span class="lineCov">         90 :   reg         tage_enable_dup_REG;</span></a>
+<a name="527"><span class="lineNum">     527 </span><span class="lineCov">         15 :   wire        updateTaken = updateValids_0 &amp; io_update_bits_br_taken_mask_0;</span></a>
+<a name="528"><span class="lineNum">     528 </span><span class="lineCov">         32 :   wire        updateProviderCorrect = io_update_bits_meta[76] == updateTaken;</span></a>
+<a name="529"><span class="lineNum">     529 </span><span class="lineCov">         22 :   wire        needToAllocate =</span></a>
+<a name="530"><span class="lineNum">     530 </span>            :     updateValids_0 &amp; io_update_bits_mispred_mask_0</a>
+<a name="531"><span class="lineNum">     531 </span>            :     &amp; ~(io_update_bits_meta[70] &amp; updateProviderCorrect &amp; io_update_bits_meta[84]);</a>
+<a name="532"><span class="lineNum">     532 </span><span class="lineCov">    2001218 :   reg  [63:0] allocLFSR_lfsr;</span></a>
+<a name="533"><span class="lineNum">     533 </span>            :   wire [3:0]  _longerHistoryTableMask_T_1 = 4'h1 &lt;&lt; io_update_bits_meta[83:82];</a>
+<a name="534"><span class="lineNum">     534 </span>            :   wire [2:0]  _GEN = _longerHistoryTableMask_T_1[2:0] | _longerHistoryTableMask_T_1[3:1];</a>
+<a name="535"><span class="lineNum">     535 </span><span class="lineCov">        100 :   wire [3:0]  longerHistoryTableMask =</span></a>
+<a name="536"><span class="lineNum">     536 </span>            :     ~({&amp;(io_update_bits_meta[83:82]),</a>
+<a name="537"><span class="lineNum">     537 </span>            :        _GEN[2],</a>
+<a name="538"><span class="lineNum">     538 </span>            :        _GEN[1] | (&amp;(io_update_bits_meta[83:82])),</a>
+<a name="539"><span class="lineNum">     539 </span>            :        _GEN[0] | io_update_bits_meta[83:82] == 2'h2 | (&amp;(io_update_bits_meta[83:82]))}</a>
+<a name="540"><span class="lineNum">     540 </span>            :       &amp; {4{io_update_bits_meta[84]}});</a>
+<a name="541"><span class="lineNum">     541 </span>            :   wire        _firstEntry_T = io_update_bits_meta[56] &amp; longerHistoryTableMask[0];</a>
+<a name="542"><span class="lineNum">     542 </span>            :   wire        _firstEntry_T_1 = io_update_bits_meta[57] &amp; longerHistoryTableMask[1];</a>
+<a name="543"><span class="lineNum">     543 </span>            :   wire        _firstEntry_T_2 = io_update_bits_meta[58] &amp; longerHistoryTableMask[2];</a>
+<a name="544"><span class="lineNum">     544 </span><span class="lineCov">        121 :   reg  [3:0]  allocatableSlots_1;</span></a>
+<a name="545"><span class="lineNum">     545 </span><span class="lineCov">         93 :   reg         tage_enable_dup_REG_1;</span></a>
+<a name="546"><span class="lineNum">     546 </span><span class="lineCov">         13 :   wire        updateTaken_1 = updateValids_1 &amp; io_update_bits_br_taken_mask_1;</span></a>
+<a name="547"><span class="lineNum">     547 </span><span class="lineCov">         34 :   wire        updateProviderCorrect_1 = io_update_bits_meta[81] == updateTaken_1;</span></a>
+<a name="548"><span class="lineNum">     548 </span><span class="lineCov">         14 :   wire        needToAllocate_1 =</span></a>
+<a name="549"><span class="lineNum">     549 </span>            :     updateValids_1 &amp; io_update_bits_mispred_mask_1</a>
+<a name="550"><span class="lineNum">     550 </span>            :     &amp; ~(io_update_bits_meta[71] &amp; updateProviderCorrect_1 &amp; io_update_bits_meta[87]);</a>
+<a name="551"><span class="lineNum">     551 </span><span class="lineCov">    2001199 :   reg  [63:0] allocLFSR_lfsr_1;</span></a>
+<a name="552"><span class="lineNum">     552 </span>            :   wire [3:0]  _longerHistoryTableMask_T_11 = 4'h1 &lt;&lt; io_update_bits_meta[86:85];</a>
+<a name="553"><span class="lineNum">     553 </span>            :   wire [2:0]  _GEN_0 =</a>
+<a name="554"><span class="lineNum">     554 </span>            :     _longerHistoryTableMask_T_11[2:0] | _longerHistoryTableMask_T_11[3:1];</a>
+<a name="555"><span class="lineNum">     555 </span><span class="lineCov">        111 :   wire [3:0]  longerHistoryTableMask_1 =</span></a>
+<a name="556"><span class="lineNum">     556 </span>            :     ~({&amp;(io_update_bits_meta[86:85]),</a>
+<a name="557"><span class="lineNum">     557 </span>            :        _GEN_0[2],</a>
+<a name="558"><span class="lineNum">     558 </span>            :        _GEN_0[1] | (&amp;(io_update_bits_meta[86:85])),</a>
+<a name="559"><span class="lineNum">     559 </span>            :        _GEN_0[0] | io_update_bits_meta[86:85] == 2'h2 | (&amp;(io_update_bits_meta[86:85]))}</a>
+<a name="560"><span class="lineNum">     560 </span>            :       &amp; {4{io_update_bits_meta[87]}});</a>
+<a name="561"><span class="lineNum">     561 </span>            :   wire        _firstEntry_T_6 = io_update_bits_meta[60] &amp; longerHistoryTableMask_1[0];</a>
+<a name="562"><span class="lineNum">     562 </span>            :   wire        _firstEntry_T_7 = io_update_bits_meta[61] &amp; longerHistoryTableMask_1[1];</a>
+<a name="563"><span class="lineNum">     563 </span>            :   wire        _firstEntry_T_8 = io_update_bits_meta[62] &amp; longerHistoryTableMask_1[2];</a>
+<a name="564"><span class="lineNum">     564 </span><span class="lineCov">         38 :   reg         tables_0_io_update_reset_u_0_REG;</span></a>
+<a name="565"><span class="lineNum">     565 </span><span class="lineCov">         32 :   reg         tables_0_io_update_mask_0_REG;</span></a>
+<a name="566"><span class="lineNum">     566 </span><span class="lineCov">         13 :   reg         tables_0_io_update_takens_0_r;</span></a>
+<a name="567"><span class="lineNum">     567 </span><span class="lineCov">         15 :   reg         tables_0_io_update_alloc_0_r;</span></a>
+<a name="568"><span class="lineNum">     568 </span><span class="lineCov">         42 :   reg  [2:0]  tables_0_io_update_oldCtrs_0_r;</span></a>
+<a name="569"><span class="lineNum">     569 </span><span class="lineCov">         14 :   reg         tables_0_io_update_uMask_0_r;</span></a>
+<a name="570"><span class="lineNum">     570 </span><span class="lineCov">         11 :   reg         tables_0_io_update_us_0_r;</span></a>
+<a name="571"><span class="lineNum">     571 </span><span class="lineCov">         29 :   reg         tables_1_io_update_reset_u_0_REG;</span></a>
+<a name="572"><span class="lineNum">     572 </span><span class="lineCov">         22 :   reg         tables_1_io_update_mask_0_REG;</span></a>
+<a name="573"><span class="lineNum">     573 </span><span class="lineCov">         18 :   reg         tables_1_io_update_takens_0_r;</span></a>
+<a name="574"><span class="lineNum">     574 </span><span class="lineCov">         15 :   reg         tables_1_io_update_alloc_0_r;</span></a>
+<a name="575"><span class="lineNum">     575 </span><span class="lineCov">         47 :   reg  [2:0]  tables_1_io_update_oldCtrs_0_r;</span></a>
+<a name="576"><span class="lineNum">     576 </span><span class="lineCov">         15 :   reg         tables_1_io_update_uMask_0_r;</span></a>
+<a name="577"><span class="lineNum">     577 </span><span class="lineCov">         14 :   reg         tables_1_io_update_us_0_r;</span></a>
+<a name="578"><span class="lineNum">     578 </span><span class="lineCov">         26 :   reg         tables_2_io_update_reset_u_0_REG;</span></a>
+<a name="579"><span class="lineNum">     579 </span><span class="lineCov">         29 :   reg         tables_2_io_update_mask_0_REG;</span></a>
+<a name="580"><span class="lineNum">     580 </span><span class="lineCov">         16 :   reg         tables_2_io_update_takens_0_r;</span></a>
+<a name="581"><span class="lineNum">     581 </span><span class="lineCov">         10 :   reg         tables_2_io_update_alloc_0_r;</span></a>
+<a name="582"><span class="lineNum">     582 </span><span class="lineCov">         45 :   reg  [2:0]  tables_2_io_update_oldCtrs_0_r;</span></a>
+<a name="583"><span class="lineNum">     583 </span><span class="lineCov">         19 :   reg         tables_2_io_update_uMask_0_r;</span></a>
+<a name="584"><span class="lineNum">     584 </span><span class="lineCov">         18 :   reg         tables_2_io_update_us_0_r;</span></a>
+<a name="585"><span class="lineNum">     585 </span><span class="lineCov">         28 :   reg         tables_3_io_update_reset_u_0_REG;</span></a>
+<a name="586"><span class="lineNum">     586 </span><span class="lineCov">         30 :   reg         tables_3_io_update_mask_0_REG;</span></a>
+<a name="587"><span class="lineNum">     587 </span><span class="lineCov">         12 :   reg         tables_3_io_update_takens_0_r;</span></a>
+<a name="588"><span class="lineNum">     588 </span><span class="lineCov">         15 :   reg         tables_3_io_update_alloc_0_r;</span></a>
+<a name="589"><span class="lineNum">     589 </span><span class="lineCov">         49 :   reg  [2:0]  tables_3_io_update_oldCtrs_0_r;</span></a>
+<a name="590"><span class="lineNum">     590 </span><span class="lineCov">         17 :   reg         tables_3_io_update_uMask_0_r;</span></a>
+<a name="591"><span class="lineNum">     591 </span><span class="lineCov">         16 :   reg         tables_3_io_update_us_0_r;</span></a>
+<a name="592"><span class="lineNum">     592 </span><span class="lineCov">         31 :   reg         tables_0_io_update_reset_u_1_REG;</span></a>
+<a name="593"><span class="lineNum">     593 </span><span class="lineCov">         40 :   reg         tables_0_io_update_mask_1_REG;</span></a>
+<a name="594"><span class="lineNum">     594 </span><span class="lineCov">         20 :   reg         tables_0_io_update_takens_1_r;</span></a>
+<a name="595"><span class="lineNum">     595 </span><span class="lineCov">         15 :   reg         tables_0_io_update_alloc_1_r;</span></a>
+<a name="596"><span class="lineNum">     596 </span><span class="lineCov">         38 :   reg  [2:0]  tables_0_io_update_oldCtrs_1_r;</span></a>
+<a name="597"><span class="lineNum">     597 </span><span class="lineCov">         13 :   reg         tables_0_io_update_uMask_1_r;</span></a>
+<a name="598"><span class="lineNum">     598 </span><span class="lineCov">         12 :   reg         tables_0_io_update_us_1_r;</span></a>
+<a name="599"><span class="lineNum">     599 </span><span class="lineCov">        615 :   reg  [40:0] tables_0_io_update_pc_r_1;</span></a>
+<a name="600"><span class="lineNum">     600 </span><span class="lineCov">        122 :   reg  [7:0]  tables_0_io_update_folded_hist_r_1_hist_14_folded_hist;</span></a>
+<a name="601"><span class="lineNum">     601 </span><span class="lineCov">        102 :   reg  [6:0]  tables_0_io_update_folded_hist_r_1_hist_7_folded_hist;</span></a>
+<a name="602"><span class="lineNum">     602 </span><span class="lineCov">         36 :   reg         tables_1_io_update_reset_u_1_REG;</span></a>
+<a name="603"><span class="lineNum">     603 </span><span class="lineCov">         26 :   reg         tables_1_io_update_mask_1_REG;</span></a>
+<a name="604"><span class="lineNum">     604 </span><span class="lineCov">         13 :   reg         tables_1_io_update_takens_1_r;</span></a>
+<a name="605"><span class="lineNum">     605 </span><span class="lineCov">         17 :   reg         tables_1_io_update_alloc_1_r;</span></a>
+<a name="606"><span class="lineNum">     606 </span><span class="lineCov">         38 :   reg  [2:0]  tables_1_io_update_oldCtrs_1_r;</span></a>
+<a name="607"><span class="lineNum">     607 </span><span class="lineCov">         13 :   reg         tables_1_io_update_uMask_1_r;</span></a>
+<a name="608"><span class="lineNum">     608 </span><span class="lineCov">         15 :   reg         tables_1_io_update_us_1_r;</span></a>
+<a name="609"><span class="lineNum">     609 </span><span class="lineCov">        599 :   reg  [40:0] tables_1_io_update_pc_r_1;</span></a>
+<a name="610"><span class="lineNum">     610 </span><span class="lineCov">         99 :   reg  [6:0]  tables_1_io_update_folded_hist_r_1_hist_15_folded_hist;</span></a>
+<a name="611"><span class="lineNum">     611 </span><span class="lineCov">        113 :   reg  [7:0]  tables_1_io_update_folded_hist_r_1_hist_4_folded_hist;</span></a>
+<a name="612"><span class="lineNum">     612 </span><span class="lineCov">        166 :   reg  [10:0] tables_1_io_update_folded_hist_r_1_hist_1_folded_hist;</span></a>
+<a name="613"><span class="lineNum">     613 </span><span class="lineCov">         33 :   reg         tables_2_io_update_reset_u_1_REG;</span></a>
+<a name="614"><span class="lineNum">     614 </span><span class="lineCov">         30 :   reg         tables_2_io_update_mask_1_REG;</span></a>
+<a name="615"><span class="lineNum">     615 </span><span class="lineCov">         15 :   reg         tables_2_io_update_takens_1_r;</span></a>
+<a name="616"><span class="lineNum">     616 </span><span class="lineCov">         20 :   reg         tables_2_io_update_alloc_1_r;</span></a>
+<a name="617"><span class="lineNum">     617 </span><span class="lineCov">         45 :   reg  [2:0]  tables_2_io_update_oldCtrs_1_r;</span></a>
+<a name="618"><span class="lineNum">     618 </span><span class="lineCov">         12 :   reg         tables_2_io_update_uMask_1_r;</span></a>
+<a name="619"><span class="lineNum">     619 </span><span class="lineCov">         21 :   reg         tables_2_io_update_us_1_r;</span></a>
+<a name="620"><span class="lineNum">     620 </span><span class="lineCov">        623 :   reg  [40:0] tables_2_io_update_pc_r_1;</span></a>
+<a name="621"><span class="lineNum">     621 </span><span class="lineCov">        176 :   reg  [10:0] tables_2_io_update_folded_hist_r_1_hist_17_folded_hist;</span></a>
+<a name="622"><span class="lineNum">     622 </span><span class="lineCov">         99 :   reg  [6:0]  tables_2_io_update_folded_hist_r_1_hist_9_folded_hist;</span></a>
+<a name="623"><span class="lineNum">     623 </span><span class="lineCov">        134 :   reg  [7:0]  tables_2_io_update_folded_hist_r_1_hist_3_folded_hist;</span></a>
+<a name="624"><span class="lineNum">     624 </span><span class="lineCov">         23 :   reg         tables_3_io_update_reset_u_1_REG;</span></a>
+<a name="625"><span class="lineNum">     625 </span><span class="lineCov">         31 :   reg         tables_3_io_update_mask_1_REG;</span></a>
+<a name="626"><span class="lineNum">     626 </span><span class="lineCov">         17 :   reg         tables_3_io_update_takens_1_r;</span></a>
+<a name="627"><span class="lineNum">     627 </span><span class="lineCov">         16 :   reg         tables_3_io_update_alloc_1_r;</span></a>
+<a name="628"><span class="lineNum">     628 </span><span class="lineCov">         52 :   reg  [2:0]  tables_3_io_update_oldCtrs_1_r;</span></a>
+<a name="629"><span class="lineNum">     629 </span><span class="lineCov">         14 :   reg         tables_3_io_update_uMask_1_r;</span></a>
+<a name="630"><span class="lineNum">     630 </span><span class="lineCov">         22 :   reg         tables_3_io_update_us_1_r;</span></a>
+<a name="631"><span class="lineNum">     631 </span><span class="lineCov">        641 :   reg  [40:0] tables_3_io_update_pc_r_1;</span></a>
+<a name="632"><span class="lineNum">     632 </span><span class="lineCov">        185 :   reg  [10:0] tables_3_io_update_folded_hist_r_1_hist_16_folded_hist;</span></a>
+<a name="633"><span class="lineNum">     633 </span><span class="lineCov">        121 :   reg  [7:0]  tables_3_io_update_folded_hist_r_1_hist_8_folded_hist;</span></a>
+<a name="634"><span class="lineNum">     634 </span><span class="lineCov">        102 :   reg  [6:0]  tables_3_io_update_folded_hist_r_1_hist_5_folded_hist;</span></a>
+<a name="635"><span class="lineNum">     635 </span><span class="lineCov">         28 :   reg         REG_2_0;</span></a>
+<a name="636"><span class="lineNum">     636 </span><span class="lineCov">         26 :   reg         REG_2_1;</span></a>
+<a name="637"><span class="lineNum">     637 </span><span class="lineCov">         29 :   reg  [1:0]  r_0;</span></a>
+<a name="638"><span class="lineNum">     638 </span><span class="lineCov">         29 :   reg  [1:0]  r_1;</span></a>
+<a name="639"><span class="lineNum">     639 </span><span class="lineCov">        689 :   reg  [40:0] bt_io_update_pc_r;</span></a>
+<a name="640"><span class="lineNum">     640 </span><span class="lineCov">         13 :   reg         r_1_0;</span></a>
+<a name="641"><span class="lineNum">     641 </span><span class="lineCov">         18 :   reg         r_1_1;</span></a>
+<a name="642"><span class="lineNum">     642 </span><span class="lineCov">        110 :   reg  [4:0]  scThresholds_0_ctr;</span></a>
+<a name="643"><span class="lineNum">     643 </span><span class="lineCov">        182 :   reg  [7:0]  scThresholds_0_thres;</span></a>
+<a name="644"><span class="lineNum">     644 </span><span class="lineCov">        113 :   reg  [4:0]  scThresholds_1_ctr;</span></a>
+<a name="645"><span class="lineNum">     645 </span><span class="lineCov">        174 :   reg  [7:0]  scThresholds_1_thres;</span></a>
+<a name="646"><span class="lineNum">     646 </span><span class="lineCov">        258 :   reg  [8:0]  s2_scTableSums_0;</span></a>
+<a name="647"><span class="lineNum">     647 </span><span class="lineCov">        292 :   reg  [8:0]  s2_scTableSums_1;</span></a>
+<a name="648"><span class="lineNum">     648 </span><span class="lineCov">         99 :   reg  [2:0]  s2_tagePrvdCtrCentered_r;</span></a>
+<a name="649"><span class="lineNum">     649 </span><span class="lineCov">        195 :   reg  [5:0]  s2_scResps_r_0_ctrs_0_0;</span></a>
+<a name="650"><span class="lineNum">     650 </span><span class="lineCov">        191 :   reg  [5:0]  s2_scResps_r_0_ctrs_0_1;</span></a>
+<a name="651"><span class="lineNum">     651 </span><span class="lineCov">        194 :   reg  [5:0]  s2_scResps_r_1_ctrs_0_0;</span></a>
+<a name="652"><span class="lineNum">     652 </span><span class="lineCov">        197 :   reg  [5:0]  s2_scResps_r_1_ctrs_0_1;</span></a>
+<a name="653"><span class="lineNum">     653 </span><span class="lineCov">        184 :   reg  [5:0]  s2_scResps_r_2_ctrs_0_0;</span></a>
+<a name="654"><span class="lineNum">     654 </span><span class="lineCov">        191 :   reg  [5:0]  s2_scResps_r_2_ctrs_0_1;</span></a>
+<a name="655"><span class="lineNum">     655 </span><span class="lineCov">        189 :   reg  [5:0]  s2_scResps_r_3_ctrs_0_0;</span></a>
+<a name="656"><span class="lineNum">     656 </span><span class="lineCov">        195 :   reg  [5:0]  s2_scResps_r_3_ctrs_0_1;</span></a>
+<a name="657"><span class="lineNum">     657 </span><span class="lineCov">         35 :   reg         s3_pred_dup_0;</span></a>
+<a name="658"><span class="lineNum">     658 </span><span class="lineCov">         30 :   reg         s3_pred_dup_1;</span></a>
+<a name="659"><span class="lineNum">     659 </span><span class="lineCov">         26 :   reg         s3_pred_dup_2;</span></a>
+<a name="660"><span class="lineNum">     660 </span><span class="lineCov">         37 :   reg         s3_pred_dup_3;</span></a>
+<a name="661"><span class="lineNum">     661 </span><span class="lineCov">        108 :   reg         sc_enable_dup_REG;</span></a>
+<a name="662"><span class="lineNum">     662 </span>            :   wire        _GEN_1 = updateValids_0 &amp; io_update_bits_meta[50];</a>
+<a name="663"><span class="lineNum">     663 </span>            :   wire [7:0]  _sum_T_8 =</a>
+<a name="664"><span class="lineNum">     664 </span>            :     8'({io_update_bits_meta[5], io_update_bits_meta[5:0], 1'h1}</a>
+<a name="665"><span class="lineNum">     665 </span>            :        + {io_update_bits_meta[11], io_update_bits_meta[11:6], 1'h1});</a>
+<a name="666"><span class="lineNum">     666 </span>            :   wire [7:0]  _sum_T_9 =</a>
+<a name="667"><span class="lineNum">     667 </span>            :     8'({io_update_bits_meta[17], io_update_bits_meta[17:12], 1'h1}</a>
+<a name="668"><span class="lineNum">     668 </span>            :        + {io_update_bits_meta[23], io_update_bits_meta[23:18], 1'h1});</a>
+<a name="669"><span class="lineNum">     669 </span>            :   wire [8:0]  _sum_T_10 = 9'({_sum_T_8[7], _sum_T_8} + {_sum_T_9[7], _sum_T_9});</a>
+<a name="670"><span class="lineNum">     670 </span>            :   wire [2:0]  _sumAboveThreshold_T = io_update_bits_meta[76:74] ^ 3'h4;</a>
+<a name="671"><span class="lineNum">     671 </span><span class="lineCov">        265 :   wire [9:0]  sum =</span></a>
+<a name="672"><span class="lineNum">     672 </span>            :     10'({_sum_T_10[8], _sum_T_10}</a>
+<a name="673"><span class="lineNum">     673 </span>            :         + {{3{_sumAboveThreshold_T[2]}}, _sumAboveThreshold_T, 4'h8});</a>
+<a name="674"><span class="lineNum">     674 </span>            :   wire        _update_on_mispred_0_T =</a>
+<a name="675"><span class="lineNum">     675 </span>            :     io_update_bits_meta[48] != io_update_bits_br_taken_mask_0;</a>
+<a name="676"><span class="lineNum">     676 </span><span class="lineCov">        293 :   reg  [8:0]  s2_scTableSums_1_0;</span></a>
+<a name="677"><span class="lineNum">     677 </span><span class="lineCov">        285 :   reg  [8:0]  s2_scTableSums_1_1;</span></a>
+<a name="678"><span class="lineNum">     678 </span><span class="lineCov">        104 :   reg  [2:0]  s2_tagePrvdCtrCentered_r_1;</span></a>
+<a name="679"><span class="lineNum">     679 </span><span class="lineCov">        168 :   reg  [5:0]  s2_scResps_r_1_0_ctrs_1_0;</span></a>
+<a name="680"><span class="lineNum">     680 </span><span class="lineCov">        184 :   reg  [5:0]  s2_scResps_r_1_0_ctrs_1_1;</span></a>
+<a name="681"><span class="lineNum">     681 </span><span class="lineCov">        191 :   reg  [5:0]  s2_scResps_r_1_1_ctrs_1_0;</span></a>
+<a name="682"><span class="lineNum">     682 </span><span class="lineCov">        188 :   reg  [5:0]  s2_scResps_r_1_1_ctrs_1_1;</span></a>
+<a name="683"><span class="lineNum">     683 </span><span class="lineCov">        191 :   reg  [5:0]  s2_scResps_r_1_2_ctrs_1_0;</span></a>
+<a name="684"><span class="lineNum">     684 </span><span class="lineCov">        191 :   reg  [5:0]  s2_scResps_r_1_2_ctrs_1_1;</span></a>
+<a name="685"><span class="lineNum">     685 </span><span class="lineCov">        191 :   reg  [5:0]  s2_scResps_r_1_3_ctrs_1_0;</span></a>
+<a name="686"><span class="lineNum">     686 </span><span class="lineCov">        167 :   reg  [5:0]  s2_scResps_r_1_3_ctrs_1_1;</span></a>
+<a name="687"><span class="lineNum">     687 </span><span class="lineCov">         33 :   reg         s3_pred_dup_0_1;</span></a>
+<a name="688"><span class="lineNum">     688 </span><span class="lineCov">         31 :   reg         s3_pred_dup_1_1;</span></a>
+<a name="689"><span class="lineNum">     689 </span><span class="lineCov">         38 :   reg         s3_pred_dup_2_1;</span></a>
+<a name="690"><span class="lineNum">     690 </span><span class="lineCov">         36 :   reg         s3_pred_dup_3_1;</span></a>
+<a name="691"><span class="lineNum">     691 </span><span class="lineCov">        101 :   reg         sc_enable_dup_REG_1;</span></a>
+<a name="692"><span class="lineNum">     692 </span>            :   wire        _GEN_2 = updateValids_1 &amp; io_update_bits_meta[51];</a>
+<a name="693"><span class="lineNum">     693 </span>            :   wire [7:0]  _sum_T_22 =</a>
+<a name="694"><span class="lineNum">     694 </span>            :     8'({io_update_bits_meta[29], io_update_bits_meta[29:24], 1'h1}</a>
+<a name="695"><span class="lineNum">     695 </span>            :        + {io_update_bits_meta[35], io_update_bits_meta[35:30], 1'h1});</a>
+<a name="696"><span class="lineNum">     696 </span>            :   wire [7:0]  _sum_T_23 =</a>
+<a name="697"><span class="lineNum">     697 </span>            :     8'({io_update_bits_meta[41], io_update_bits_meta[41:36], 1'h1}</a>
+<a name="698"><span class="lineNum">     698 </span>            :        + {io_update_bits_meta[47], io_update_bits_meta[47:42], 1'h1});</a>
+<a name="699"><span class="lineNum">     699 </span>            :   wire [8:0]  _sum_T_24 = 9'({_sum_T_22[7], _sum_T_22} + {_sum_T_23[7], _sum_T_23});</a>
+<a name="700"><span class="lineNum">     700 </span>            :   wire [2:0]  _sumAboveThreshold_T_19 = io_update_bits_meta[81:79] ^ 3'h4;</a>
+<a name="701"><span class="lineNum">     701 </span><span class="lineCov">        282 :   wire [9:0]  sum_1 =</span></a>
+<a name="702"><span class="lineNum">     702 </span>            :     10'({_sum_T_24[8], _sum_T_24}</a>
+<a name="703"><span class="lineNum">     703 </span>            :         + {{3{_sumAboveThreshold_T_19[2]}}, _sumAboveThreshold_T_19, 4'h8});</a>
+<a name="704"><span class="lineNum">     704 </span>            :   wire        _update_on_mispred_1_T =</a>
+<a name="705"><span class="lineNum">     705 </span>            :     io_update_bits_meta[49] != io_update_bits_br_taken_mask_1;</a>
+<a name="706"><span class="lineNum">     706 </span><span class="lineCov">         35 :   reg         scTables_0_io_update_mask_0_REG;</span></a>
+<a name="707"><span class="lineNum">     707 </span><span class="lineCov">         11 :   reg         scTables_0_io_update_tagePreds_0_r;</span></a>
+<a name="708"><span class="lineNum">     708 </span><span class="lineCov">         20 :   reg         scTables_0_io_update_takens_0_r;</span></a>
+<a name="709"><span class="lineNum">     709 </span><span class="lineCov">        101 :   reg  [5:0]  scTables_0_io_update_oldCtrs_0_r;</span></a>
+<a name="710"><span class="lineNum">     710 </span><span class="lineCov">         31 :   reg         scTables_1_io_update_mask_0_REG;</span></a>
+<a name="711"><span class="lineNum">     711 </span><span class="lineCov">         13 :   reg         scTables_1_io_update_tagePreds_0_r;</span></a>
+<a name="712"><span class="lineNum">     712 </span><span class="lineCov">         18 :   reg         scTables_1_io_update_takens_0_r;</span></a>
+<a name="713"><span class="lineNum">     713 </span><span class="lineCov">         87 :   reg  [5:0]  scTables_1_io_update_oldCtrs_0_r;</span></a>
+<a name="714"><span class="lineNum">     714 </span><span class="lineCov">         31 :   reg         scTables_2_io_update_mask_0_REG;</span></a>
+<a name="715"><span class="lineNum">     715 </span><span class="lineCov">         15 :   reg         scTables_2_io_update_tagePreds_0_r;</span></a>
+<a name="716"><span class="lineNum">     716 </span><span class="lineCov">         18 :   reg         scTables_2_io_update_takens_0_r;</span></a>
+<a name="717"><span class="lineNum">     717 </span><span class="lineCov">         96 :   reg  [5:0]  scTables_2_io_update_oldCtrs_0_r;</span></a>
+<a name="718"><span class="lineNum">     718 </span><span class="lineCov">         30 :   reg         scTables_3_io_update_mask_0_REG;</span></a>
+<a name="719"><span class="lineNum">     719 </span><span class="lineCov">         18 :   reg         scTables_3_io_update_tagePreds_0_r;</span></a>
+<a name="720"><span class="lineNum">     720 </span><span class="lineCov">         17 :   reg         scTables_3_io_update_takens_0_r;</span></a>
+<a name="721"><span class="lineNum">     721 </span><span class="lineCov">         95 :   reg  [5:0]  scTables_3_io_update_oldCtrs_0_r;</span></a>
+<a name="722"><span class="lineNum">     722 </span><span class="lineCov">         32 :   reg         scTables_0_io_update_mask_1_REG;</span></a>
+<a name="723"><span class="lineNum">     723 </span><span class="lineCov">         19 :   reg         scTables_0_io_update_tagePreds_1_r;</span></a>
+<a name="724"><span class="lineNum">     724 </span><span class="lineCov">         21 :   reg         scTables_0_io_update_takens_1_r;</span></a>
+<a name="725"><span class="lineNum">     725 </span><span class="lineCov">        102 :   reg  [5:0]  scTables_0_io_update_oldCtrs_1_r;</span></a>
+<a name="726"><span class="lineNum">     726 </span><span class="lineCov">        618 :   reg  [40:0] scTables_0_io_update_pc_r_1;</span></a>
+<a name="727"><span class="lineNum">     727 </span><span class="lineCov">         32 :   reg         scTables_1_io_update_mask_1_REG;</span></a>
+<a name="728"><span class="lineNum">     728 </span><span class="lineCov">         17 :   reg         scTables_1_io_update_tagePreds_1_r;</span></a>
+<a name="729"><span class="lineNum">     729 </span><span class="lineCov">         16 :   reg         scTables_1_io_update_takens_1_r;</span></a>
+<a name="730"><span class="lineNum">     730 </span><span class="lineCov">         97 :   reg  [5:0]  scTables_1_io_update_oldCtrs_1_r;</span></a>
+<a name="731"><span class="lineNum">     731 </span><span class="lineCov">        622 :   reg  [40:0] scTables_1_io_update_pc_r_1;</span></a>
+<a name="732"><span class="lineNum">     732 </span><span class="lineCov">         56 :   reg  [3:0]  scTables_1_io_update_folded_hist_r_1_hist_12_folded_hist;</span></a>
+<a name="733"><span class="lineNum">     733 </span><span class="lineCov">         34 :   reg         scTables_2_io_update_mask_1_REG;</span></a>
+<a name="734"><span class="lineNum">     734 </span><span class="lineCov">         16 :   reg         scTables_2_io_update_tagePreds_1_r;</span></a>
+<a name="735"><span class="lineNum">     735 </span><span class="lineCov">         19 :   reg         scTables_2_io_update_takens_1_r;</span></a>
+<a name="736"><span class="lineNum">     736 </span><span class="lineCov">         79 :   reg  [5:0]  scTables_2_io_update_oldCtrs_1_r;</span></a>
+<a name="737"><span class="lineNum">     737 </span><span class="lineCov">        648 :   reg  [40:0] scTables_2_io_update_pc_r_1;</span></a>
+<a name="738"><span class="lineNum">     738 </span><span class="lineCov">        123 :   reg  [7:0]  scTables_2_io_update_folded_hist_r_1_hist_11_folded_hist;</span></a>
+<a name="739"><span class="lineNum">     739 </span><span class="lineCov">         29 :   reg         scTables_3_io_update_mask_1_REG;</span></a>
+<a name="740"><span class="lineNum">     740 </span><span class="lineCov">         18 :   reg         scTables_3_io_update_tagePreds_1_r;</span></a>
+<a name="741"><span class="lineNum">     741 </span><span class="lineCov">         17 :   reg         scTables_3_io_update_takens_1_r;</span></a>
+<a name="742"><span class="lineNum">     742 </span><span class="lineCov">         85 :   reg  [5:0]  scTables_3_io_update_oldCtrs_1_r;</span></a>
+<a name="743"><span class="lineNum">     743 </span><span class="lineCov">        637 :   reg  [40:0] scTables_3_io_update_pc_r_1;</span></a>
+<a name="744"><span class="lineNum">     744 </span><span class="lineCov">        112 :   reg  [7:0]  scTables_3_io_update_folded_hist_r_1_hist_2_folded_hist;</span></a>
+<a name="745"><span class="lineNum">     745 </span><span class="lineCov">         84 :   reg  [1:0]  io_perf_0_value_REG;</span></a>
+<a name="746"><span class="lineNum">     746 </span><span class="lineCov">        112 :   reg  [1:0]  io_perf_0_value_REG_1;</span></a>
+<a name="747"><span class="lineNum">     747 </span><span class="lineCov">         58 :   reg  [1:0]  io_perf_1_value_REG;</span></a>
+<a name="748"><span class="lineNum">     748 </span><span class="lineCov">         95 :   reg  [1:0]  io_perf_1_value_REG_1;</span></a>
+<a name="749"><span class="lineNum">     749 </span><span class="lineCov">         69 :   reg  [1:0]  io_perf_2_value_REG;</span></a>
+<a name="750"><span class="lineNum">     750 </span><span class="lineCov">         72 :   reg  [1:0]  io_perf_2_value_REG_1;</span></a>
+<a name="751"><span class="lineNum">     751 </span>            :   wire [7:0]  _s1_scTableSums_T_8 =</a>
+<a name="752"><span class="lineNum">     752 </span>            :     8'({_scTables_0_io_resp_ctrs_0_0[5], _scTables_0_io_resp_ctrs_0_0, 1'h1}</a>
+<a name="753"><span class="lineNum">     753 </span>            :        + {_scTables_1_io_resp_ctrs_0_0[5], _scTables_1_io_resp_ctrs_0_0, 1'h1});</a>
+<a name="754"><span class="lineNum">     754 </span>            :   wire [7:0]  _s1_scTableSums_T_9 =</a>
+<a name="755"><span class="lineNum">     755 </span>            :     8'({_scTables_2_io_resp_ctrs_0_0[5], _scTables_2_io_resp_ctrs_0_0, 1'h1}</a>
+<a name="756"><span class="lineNum">     756 </span>            :        + {_scTables_3_io_resp_ctrs_0_0[5], _scTables_3_io_resp_ctrs_0_0, 1'h1});</a>
+<a name="757"><span class="lineNum">     757 </span>            :   wire [7:0]  _s1_scTableSums_T_19 =</a>
+<a name="758"><span class="lineNum">     758 </span>            :     8'({_scTables_0_io_resp_ctrs_0_1[5], _scTables_0_io_resp_ctrs_0_1, 1'h1}</a>
+<a name="759"><span class="lineNum">     759 </span>            :        + {_scTables_1_io_resp_ctrs_0_1[5], _scTables_1_io_resp_ctrs_0_1, 1'h1});</a>
+<a name="760"><span class="lineNum">     760 </span>            :   wire [7:0]  _s1_scTableSums_T_20 =</a>
+<a name="761"><span class="lineNum">     761 </span>            :     8'({_scTables_2_io_resp_ctrs_0_1[5], _scTables_2_io_resp_ctrs_0_1, 1'h1}</a>
+<a name="762"><span class="lineNum">     762 </span>            :        + {_scTables_3_io_resp_ctrs_0_1[5], _scTables_3_io_resp_ctrs_0_1, 1'h1});</a>
+<a name="763"><span class="lineNum">     763 </span>            :   wire [7:0]  _s1_scTableSums_T_30 =</a>
+<a name="764"><span class="lineNum">     764 </span>            :     8'({_scTables_0_io_resp_ctrs_1_0[5], _scTables_0_io_resp_ctrs_1_0, 1'h1}</a>
+<a name="765"><span class="lineNum">     765 </span>            :        + {_scTables_1_io_resp_ctrs_1_0[5], _scTables_1_io_resp_ctrs_1_0, 1'h1});</a>
+<a name="766"><span class="lineNum">     766 </span>            :   wire [7:0]  _s1_scTableSums_T_31 =</a>
+<a name="767"><span class="lineNum">     767 </span>            :     8'({_scTables_2_io_resp_ctrs_1_0[5], _scTables_2_io_resp_ctrs_1_0, 1'h1}</a>
+<a name="768"><span class="lineNum">     768 </span>            :        + {_scTables_3_io_resp_ctrs_1_0[5], _scTables_3_io_resp_ctrs_1_0, 1'h1});</a>
+<a name="769"><span class="lineNum">     769 </span>            :   wire [7:0]  _s1_scTableSums_T_41 =</a>
+<a name="770"><span class="lineNum">     770 </span>            :     8'({_scTables_0_io_resp_ctrs_1_1[5], _scTables_0_io_resp_ctrs_1_1, 1'h1}</a>
+<a name="771"><span class="lineNum">     771 </span>            :        + {_scTables_1_io_resp_ctrs_1_1[5], _scTables_1_io_resp_ctrs_1_1, 1'h1});</a>
+<a name="772"><span class="lineNum">     772 </span>            :   wire [7:0]  _s1_scTableSums_T_42 =</a>
+<a name="773"><span class="lineNum">     773 </span>            :     8'({_scTables_2_io_resp_ctrs_1_1[5], _scTables_2_io_resp_ctrs_1_1, 1'h1}</a>
+<a name="774"><span class="lineNum">     774 </span>            :        + {_scTables_3_io_resp_ctrs_1_1[5], _scTables_3_io_resp_ctrs_1_1, 1'h1});</a>
+<a name="775"><span class="lineNum">     775 </span><span class="lineCov">         32 :   wire        useAltCtr =</span></a>
+<a name="776"><span class="lineNum">     776 </span>            :     s1_pc_dup_0[7:1] == 7'h0 &amp; useAltOnNaCtrs_0_0[3] | s1_pc_dup_0[7:1] == 7'h1</a>
+<a name="777"><span class="lineNum">     777 </span>            :     &amp; useAltOnNaCtrs_0_1[3] | s1_pc_dup_0[7:1] == 7'h2 &amp; useAltOnNaCtrs_0_2[3]</a>
+<a name="778"><span class="lineNum">     778 </span>            :     | s1_pc_dup_0[7:1] == 7'h3 &amp; useAltOnNaCtrs_0_3[3] | s1_pc_dup_0[7:1] == 7'h4</a>
+<a name="779"><span class="lineNum">     779 </span>            :     &amp; useAltOnNaCtrs_0_4[3] | s1_pc_dup_0[7:1] == 7'h5 &amp; useAltOnNaCtrs_0_5[3]</a>
+<a name="780"><span class="lineNum">     780 </span>            :     | s1_pc_dup_0[7:1] == 7'h6 &amp; useAltOnNaCtrs_0_6[3] | s1_pc_dup_0[7:1] == 7'h7</a>
+<a name="781"><span class="lineNum">     781 </span>            :     &amp; useAltOnNaCtrs_0_7[3] | s1_pc_dup_0[7:1] == 7'h8 &amp; useAltOnNaCtrs_0_8[3]</a>
+<a name="782"><span class="lineNum">     782 </span>            :     | s1_pc_dup_0[7:1] == 7'h9 &amp; useAltOnNaCtrs_0_9[3] | s1_pc_dup_0[7:1] == 7'hA</a>
+<a name="783"><span class="lineNum">     783 </span>            :     &amp; useAltOnNaCtrs_0_10[3] | s1_pc_dup_0[7:1] == 7'hB &amp; useAltOnNaCtrs_0_11[3]</a>
+<a name="784"><span class="lineNum">     784 </span>            :     | s1_pc_dup_0[7:1] == 7'hC &amp; useAltOnNaCtrs_0_12[3] | s1_pc_dup_0[7:1] == 7'hD</a>
+<a name="785"><span class="lineNum">     785 </span>            :     &amp; useAltOnNaCtrs_0_13[3] | s1_pc_dup_0[7:1] == 7'hE &amp; useAltOnNaCtrs_0_14[3]</a>
+<a name="786"><span class="lineNum">     786 </span>            :     | s1_pc_dup_0[7:1] == 7'hF &amp; useAltOnNaCtrs_0_15[3] | s1_pc_dup_0[7:1] == 7'h10</a>
+<a name="787"><span class="lineNum">     787 </span>            :     &amp; useAltOnNaCtrs_0_16[3] | s1_pc_dup_0[7:1] == 7'h11 &amp; useAltOnNaCtrs_0_17[3]</a>
+<a name="788"><span class="lineNum">     788 </span>            :     | s1_pc_dup_0[7:1] == 7'h12 &amp; useAltOnNaCtrs_0_18[3] | s1_pc_dup_0[7:1] == 7'h13</a>
+<a name="789"><span class="lineNum">     789 </span>            :     &amp; useAltOnNaCtrs_0_19[3] | s1_pc_dup_0[7:1] == 7'h14 &amp; useAltOnNaCtrs_0_20[3]</a>
+<a name="790"><span class="lineNum">     790 </span>            :     | s1_pc_dup_0[7:1] == 7'h15 &amp; useAltOnNaCtrs_0_21[3] | s1_pc_dup_0[7:1] == 7'h16</a>
+<a name="791"><span class="lineNum">     791 </span>            :     &amp; useAltOnNaCtrs_0_22[3] | s1_pc_dup_0[7:1] == 7'h17 &amp; useAltOnNaCtrs_0_23[3]</a>
+<a name="792"><span class="lineNum">     792 </span>            :     | s1_pc_dup_0[7:1] == 7'h18 &amp; useAltOnNaCtrs_0_24[3] | s1_pc_dup_0[7:1] == 7'h19</a>
+<a name="793"><span class="lineNum">     793 </span>            :     &amp; useAltOnNaCtrs_0_25[3] | s1_pc_dup_0[7:1] == 7'h1A &amp; useAltOnNaCtrs_0_26[3]</a>
+<a name="794"><span class="lineNum">     794 </span>            :     | s1_pc_dup_0[7:1] == 7'h1B &amp; useAltOnNaCtrs_0_27[3] | s1_pc_dup_0[7:1] == 7'h1C</a>
+<a name="795"><span class="lineNum">     795 </span>            :     &amp; useAltOnNaCtrs_0_28[3] | s1_pc_dup_0[7:1] == 7'h1D &amp; useAltOnNaCtrs_0_29[3]</a>
+<a name="796"><span class="lineNum">     796 </span>            :     | s1_pc_dup_0[7:1] == 7'h1E &amp; useAltOnNaCtrs_0_30[3] | s1_pc_dup_0[7:1] == 7'h1F</a>
+<a name="797"><span class="lineNum">     797 </span>            :     &amp; useAltOnNaCtrs_0_31[3] | s1_pc_dup_0[7:1] == 7'h20 &amp; useAltOnNaCtrs_0_32[3]</a>
+<a name="798"><span class="lineNum">     798 </span>            :     | s1_pc_dup_0[7:1] == 7'h21 &amp; useAltOnNaCtrs_0_33[3] | s1_pc_dup_0[7:1] == 7'h22</a>
+<a name="799"><span class="lineNum">     799 </span>            :     &amp; useAltOnNaCtrs_0_34[3] | s1_pc_dup_0[7:1] == 7'h23 &amp; useAltOnNaCtrs_0_35[3]</a>
+<a name="800"><span class="lineNum">     800 </span>            :     | s1_pc_dup_0[7:1] == 7'h24 &amp; useAltOnNaCtrs_0_36[3] | s1_pc_dup_0[7:1] == 7'h25</a>
+<a name="801"><span class="lineNum">     801 </span>            :     &amp; useAltOnNaCtrs_0_37[3] | s1_pc_dup_0[7:1] == 7'h26 &amp; useAltOnNaCtrs_0_38[3]</a>
+<a name="802"><span class="lineNum">     802 </span>            :     | s1_pc_dup_0[7:1] == 7'h27 &amp; useAltOnNaCtrs_0_39[3] | s1_pc_dup_0[7:1] == 7'h28</a>
+<a name="803"><span class="lineNum">     803 </span>            :     &amp; useAltOnNaCtrs_0_40[3] | s1_pc_dup_0[7:1] == 7'h29 &amp; useAltOnNaCtrs_0_41[3]</a>
+<a name="804"><span class="lineNum">     804 </span>            :     | s1_pc_dup_0[7:1] == 7'h2A &amp; useAltOnNaCtrs_0_42[3] | s1_pc_dup_0[7:1] == 7'h2B</a>
+<a name="805"><span class="lineNum">     805 </span>            :     &amp; useAltOnNaCtrs_0_43[3] | s1_pc_dup_0[7:1] == 7'h2C &amp; useAltOnNaCtrs_0_44[3]</a>
+<a name="806"><span class="lineNum">     806 </span>            :     | s1_pc_dup_0[7:1] == 7'h2D &amp; useAltOnNaCtrs_0_45[3] | s1_pc_dup_0[7:1] == 7'h2E</a>
+<a name="807"><span class="lineNum">     807 </span>            :     &amp; useAltOnNaCtrs_0_46[3] | s1_pc_dup_0[7:1] == 7'h2F &amp; useAltOnNaCtrs_0_47[3]</a>
+<a name="808"><span class="lineNum">     808 </span>            :     | s1_pc_dup_0[7:1] == 7'h30 &amp; useAltOnNaCtrs_0_48[3] | s1_pc_dup_0[7:1] == 7'h31</a>
+<a name="809"><span class="lineNum">     809 </span>            :     &amp; useAltOnNaCtrs_0_49[3] | s1_pc_dup_0[7:1] == 7'h32 &amp; useAltOnNaCtrs_0_50[3]</a>
+<a name="810"><span class="lineNum">     810 </span>            :     | s1_pc_dup_0[7:1] == 7'h33 &amp; useAltOnNaCtrs_0_51[3] | s1_pc_dup_0[7:1] == 7'h34</a>
+<a name="811"><span class="lineNum">     811 </span>            :     &amp; useAltOnNaCtrs_0_52[3] | s1_pc_dup_0[7:1] == 7'h35 &amp; useAltOnNaCtrs_0_53[3]</a>
+<a name="812"><span class="lineNum">     812 </span>            :     | s1_pc_dup_0[7:1] == 7'h36 &amp; useAltOnNaCtrs_0_54[3] | s1_pc_dup_0[7:1] == 7'h37</a>
+<a name="813"><span class="lineNum">     813 </span>            :     &amp; useAltOnNaCtrs_0_55[3] | s1_pc_dup_0[7:1] == 7'h38 &amp; useAltOnNaCtrs_0_56[3]</a>
+<a name="814"><span class="lineNum">     814 </span>            :     | s1_pc_dup_0[7:1] == 7'h39 &amp; useAltOnNaCtrs_0_57[3] | s1_pc_dup_0[7:1] == 7'h3A</a>
+<a name="815"><span class="lineNum">     815 </span>            :     &amp; useAltOnNaCtrs_0_58[3] | s1_pc_dup_0[7:1] == 7'h3B &amp; useAltOnNaCtrs_0_59[3]</a>
+<a name="816"><span class="lineNum">     816 </span>            :     | s1_pc_dup_0[7:1] == 7'h3C &amp; useAltOnNaCtrs_0_60[3] | s1_pc_dup_0[7:1] == 7'h3D</a>
+<a name="817"><span class="lineNum">     817 </span>            :     &amp; useAltOnNaCtrs_0_61[3] | s1_pc_dup_0[7:1] == 7'h3E &amp; useAltOnNaCtrs_0_62[3]</a>
+<a name="818"><span class="lineNum">     818 </span>            :     | s1_pc_dup_0[7:1] == 7'h3F &amp; useAltOnNaCtrs_0_63[3] | s1_pc_dup_0[7:1] == 7'h40</a>
+<a name="819"><span class="lineNum">     819 </span>            :     &amp; useAltOnNaCtrs_0_64[3] | s1_pc_dup_0[7:1] == 7'h41 &amp; useAltOnNaCtrs_0_65[3]</a>
+<a name="820"><span class="lineNum">     820 </span>            :     | s1_pc_dup_0[7:1] == 7'h42 &amp; useAltOnNaCtrs_0_66[3] | s1_pc_dup_0[7:1] == 7'h43</a>
+<a name="821"><span class="lineNum">     821 </span>            :     &amp; useAltOnNaCtrs_0_67[3] | s1_pc_dup_0[7:1] == 7'h44 &amp; useAltOnNaCtrs_0_68[3]</a>
+<a name="822"><span class="lineNum">     822 </span>            :     | s1_pc_dup_0[7:1] == 7'h45 &amp; useAltOnNaCtrs_0_69[3] | s1_pc_dup_0[7:1] == 7'h46</a>
+<a name="823"><span class="lineNum">     823 </span>            :     &amp; useAltOnNaCtrs_0_70[3] | s1_pc_dup_0[7:1] == 7'h47 &amp; useAltOnNaCtrs_0_71[3]</a>
+<a name="824"><span class="lineNum">     824 </span>            :     | s1_pc_dup_0[7:1] == 7'h48 &amp; useAltOnNaCtrs_0_72[3] | s1_pc_dup_0[7:1] == 7'h49</a>
+<a name="825"><span class="lineNum">     825 </span>            :     &amp; useAltOnNaCtrs_0_73[3] | s1_pc_dup_0[7:1] == 7'h4A &amp; useAltOnNaCtrs_0_74[3]</a>
+<a name="826"><span class="lineNum">     826 </span>            :     | s1_pc_dup_0[7:1] == 7'h4B &amp; useAltOnNaCtrs_0_75[3] | s1_pc_dup_0[7:1] == 7'h4C</a>
+<a name="827"><span class="lineNum">     827 </span>            :     &amp; useAltOnNaCtrs_0_76[3] | s1_pc_dup_0[7:1] == 7'h4D &amp; useAltOnNaCtrs_0_77[3]</a>
+<a name="828"><span class="lineNum">     828 </span>            :     | s1_pc_dup_0[7:1] == 7'h4E &amp; useAltOnNaCtrs_0_78[3] | s1_pc_dup_0[7:1] == 7'h4F</a>
+<a name="829"><span class="lineNum">     829 </span>            :     &amp; useAltOnNaCtrs_0_79[3] | s1_pc_dup_0[7:1] == 7'h50 &amp; useAltOnNaCtrs_0_80[3]</a>
+<a name="830"><span class="lineNum">     830 </span>            :     | s1_pc_dup_0[7:1] == 7'h51 &amp; useAltOnNaCtrs_0_81[3] | s1_pc_dup_0[7:1] == 7'h52</a>
+<a name="831"><span class="lineNum">     831 </span>            :     &amp; useAltOnNaCtrs_0_82[3] | s1_pc_dup_0[7:1] == 7'h53 &amp; useAltOnNaCtrs_0_83[3]</a>
+<a name="832"><span class="lineNum">     832 </span>            :     | s1_pc_dup_0[7:1] == 7'h54 &amp; useAltOnNaCtrs_0_84[3] | s1_pc_dup_0[7:1] == 7'h55</a>
+<a name="833"><span class="lineNum">     833 </span>            :     &amp; useAltOnNaCtrs_0_85[3] | s1_pc_dup_0[7:1] == 7'h56 &amp; useAltOnNaCtrs_0_86[3]</a>
+<a name="834"><span class="lineNum">     834 </span>            :     | s1_pc_dup_0[7:1] == 7'h57 &amp; useAltOnNaCtrs_0_87[3] | s1_pc_dup_0[7:1] == 7'h58</a>
+<a name="835"><span class="lineNum">     835 </span>            :     &amp; useAltOnNaCtrs_0_88[3] | s1_pc_dup_0[7:1] == 7'h59 &amp; useAltOnNaCtrs_0_89[3]</a>
+<a name="836"><span class="lineNum">     836 </span>            :     | s1_pc_dup_0[7:1] == 7'h5A &amp; useAltOnNaCtrs_0_90[3] | s1_pc_dup_0[7:1] == 7'h5B</a>
+<a name="837"><span class="lineNum">     837 </span>            :     &amp; useAltOnNaCtrs_0_91[3] | s1_pc_dup_0[7:1] == 7'h5C &amp; useAltOnNaCtrs_0_92[3]</a>
+<a name="838"><span class="lineNum">     838 </span>            :     | s1_pc_dup_0[7:1] == 7'h5D &amp; useAltOnNaCtrs_0_93[3] | s1_pc_dup_0[7:1] == 7'h5E</a>
+<a name="839"><span class="lineNum">     839 </span>            :     &amp; useAltOnNaCtrs_0_94[3] | s1_pc_dup_0[7:1] == 7'h5F &amp; useAltOnNaCtrs_0_95[3]</a>
+<a name="840"><span class="lineNum">     840 </span>            :     | s1_pc_dup_0[7:1] == 7'h60 &amp; useAltOnNaCtrs_0_96[3] | s1_pc_dup_0[7:1] == 7'h61</a>
+<a name="841"><span class="lineNum">     841 </span>            :     &amp; useAltOnNaCtrs_0_97[3] | s1_pc_dup_0[7:1] == 7'h62 &amp; useAltOnNaCtrs_0_98[3]</a>
+<a name="842"><span class="lineNum">     842 </span>            :     | s1_pc_dup_0[7:1] == 7'h63 &amp; useAltOnNaCtrs_0_99[3] | s1_pc_dup_0[7:1] == 7'h64</a>
+<a name="843"><span class="lineNum">     843 </span>            :     &amp; useAltOnNaCtrs_0_100[3] | s1_pc_dup_0[7:1] == 7'h65 &amp; useAltOnNaCtrs_0_101[3]</a>
+<a name="844"><span class="lineNum">     844 </span>            :     | s1_pc_dup_0[7:1] == 7'h66 &amp; useAltOnNaCtrs_0_102[3] | s1_pc_dup_0[7:1] == 7'h67</a>
+<a name="845"><span class="lineNum">     845 </span>            :     &amp; useAltOnNaCtrs_0_103[3] | s1_pc_dup_0[7:1] == 7'h68 &amp; useAltOnNaCtrs_0_104[3]</a>
+<a name="846"><span class="lineNum">     846 </span>            :     | s1_pc_dup_0[7:1] == 7'h69 &amp; useAltOnNaCtrs_0_105[3] | s1_pc_dup_0[7:1] == 7'h6A</a>
+<a name="847"><span class="lineNum">     847 </span>            :     &amp; useAltOnNaCtrs_0_106[3] | s1_pc_dup_0[7:1] == 7'h6B &amp; useAltOnNaCtrs_0_107[3]</a>
+<a name="848"><span class="lineNum">     848 </span>            :     | s1_pc_dup_0[7:1] == 7'h6C &amp; useAltOnNaCtrs_0_108[3] | s1_pc_dup_0[7:1] == 7'h6D</a>
+<a name="849"><span class="lineNum">     849 </span>            :     &amp; useAltOnNaCtrs_0_109[3] | s1_pc_dup_0[7:1] == 7'h6E &amp; useAltOnNaCtrs_0_110[3]</a>
+<a name="850"><span class="lineNum">     850 </span>            :     | s1_pc_dup_0[7:1] == 7'h6F &amp; useAltOnNaCtrs_0_111[3] | s1_pc_dup_0[7:1] == 7'h70</a>
+<a name="851"><span class="lineNum">     851 </span>            :     &amp; useAltOnNaCtrs_0_112[3] | s1_pc_dup_0[7:1] == 7'h71 &amp; useAltOnNaCtrs_0_113[3]</a>
+<a name="852"><span class="lineNum">     852 </span>            :     | s1_pc_dup_0[7:1] == 7'h72 &amp; useAltOnNaCtrs_0_114[3] | s1_pc_dup_0[7:1] == 7'h73</a>
+<a name="853"><span class="lineNum">     853 </span>            :     &amp; useAltOnNaCtrs_0_115[3] | s1_pc_dup_0[7:1] == 7'h74 &amp; useAltOnNaCtrs_0_116[3]</a>
+<a name="854"><span class="lineNum">     854 </span>            :     | s1_pc_dup_0[7:1] == 7'h75 &amp; useAltOnNaCtrs_0_117[3] | s1_pc_dup_0[7:1] == 7'h76</a>
+<a name="855"><span class="lineNum">     855 </span>            :     &amp; useAltOnNaCtrs_0_118[3] | s1_pc_dup_0[7:1] == 7'h77 &amp; useAltOnNaCtrs_0_119[3]</a>
+<a name="856"><span class="lineNum">     856 </span>            :     | s1_pc_dup_0[7:1] == 7'h78 &amp; useAltOnNaCtrs_0_120[3] | s1_pc_dup_0[7:1] == 7'h79</a>
+<a name="857"><span class="lineNum">     857 </span>            :     &amp; useAltOnNaCtrs_0_121[3] | s1_pc_dup_0[7:1] == 7'h7A &amp; useAltOnNaCtrs_0_122[3]</a>
+<a name="858"><span class="lineNum">     858 </span>            :     | s1_pc_dup_0[7:1] == 7'h7B &amp; useAltOnNaCtrs_0_123[3] | s1_pc_dup_0[7:1] == 7'h7C</a>
+<a name="859"><span class="lineNum">     859 </span>            :     &amp; useAltOnNaCtrs_0_124[3] | s1_pc_dup_0[7:1] == 7'h7D &amp; useAltOnNaCtrs_0_125[3]</a>
+<a name="860"><span class="lineNum">     860 </span>            :     | s1_pc_dup_0[7:1] == 7'h7E &amp; useAltOnNaCtrs_0_126[3] | (&amp;(s1_pc_dup_0[7:1]))</a>
+<a name="861"><span class="lineNum">     861 </span>            :     &amp; useAltOnNaCtrs_0_127[3];</a>
+<a name="862"><span class="lineNum">     862 </span>            :   wire        _providerInfo_T = _tables_3_io_resps_0_valid | _tables_2_io_resps_0_valid;</a>
+<a name="863"><span class="lineNum">     863 </span><span class="lineCov">        103 :   wire [2:0]  providerInfo_resp_ctr =</span></a>
+<a name="864"><span class="lineNum">     864 </span>            :     _providerInfo_T</a>
+<a name="865"><span class="lineNum">     865 </span>            :       ? (_tables_3_io_resps_0_valid</a>
+<a name="866"><span class="lineNum">     866 </span>            :            ? _tables_3_io_resps_0_bits_ctr</a>
+<a name="867"><span class="lineNum">     867 </span>            :            : _tables_2_io_resps_0_bits_ctr)</a>
+<a name="868"><span class="lineNum">     868 </span>            :       : _tables_1_io_resps_0_valid</a>
+<a name="869"><span class="lineNum">     869 </span>            :           ? _tables_1_io_resps_0_bits_ctr</a>
+<a name="870"><span class="lineNum">     870 </span>            :           : _tables_0_io_resps_0_bits_ctr;</a>
+<a name="871"><span class="lineNum">     871 </span><span class="lineCov">         16 :   wire        provided =</span></a>
+<a name="872"><span class="lineNum">     872 </span>            :     _tables_0_io_resps_0_valid | _tables_1_io_resps_0_valid | _tables_2_io_resps_0_valid</a>
+<a name="873"><span class="lineNum">     873 </span>            :     | _tables_3_io_resps_0_valid;</a>
+<a name="874"><span class="lineNum">     874 </span><span class="lineCov">         17 :   wire        s1_altUsed_0 =</span></a>
+<a name="875"><span class="lineNum">     875 </span>            :     ~provided</a>
+<a name="876"><span class="lineNum">     876 </span>            :     | (_providerInfo_T</a>
+<a name="877"><span class="lineNum">     877 </span>            :          ? (_tables_3_io_resps_0_valid</a>
+<a name="878"><span class="lineNum">     878 </span>            :               ? _tables_3_io_resps_0_bits_unconf &amp; useAltCtr</a>
+<a name="879"><span class="lineNum">     879 </span>            :               : _tables_2_io_resps_0_bits_unconf &amp; useAltCtr)</a>
+<a name="880"><span class="lineNum">     880 </span>            :          : _tables_1_io_resps_0_valid</a>
+<a name="881"><span class="lineNum">     881 </span>            :              ? _tables_1_io_resps_0_bits_unconf &amp; useAltCtr</a>
+<a name="882"><span class="lineNum">     882 </span>            :              : _tables_0_io_resps_0_bits_unconf &amp; useAltCtr);</a>
+<a name="883"><span class="lineNum">     883 </span><span class="lineCov">         25 :   wire        s1_tageTakens_0 =</span></a>
+<a name="884"><span class="lineNum">     884 </span>            :     s1_altUsed_0 ? _bt_io_s1_cnt_0[1] : providerInfo_resp_ctr[2];</a>
+<a name="885"><span class="lineNum">     885 </span><span class="lineCov">         18 :   wire        baseupdate_0 = updateValids_0 &amp; io_update_bits_meta[70];</span></a>
+<a name="886"><span class="lineNum">     886 </span>            :   wire        _GEN_3 = io_update_bits_meta[83:82] == 2'h0;</a>
+<a name="887"><span class="lineNum">     887 </span>            :   wire        _GEN_4 = updateValids_0 &amp; io_update_bits_meta[84];</a>
+<a name="888"><span class="lineNum">     888 </span>            :   wire        _GEN_5 = io_update_bits_meta[83:82] == 2'h1;</a>
+<a name="889"><span class="lineNum">     889 </span>            :   wire        _GEN_6 = io_update_bits_meta[83:82] == 2'h2;</a>
+<a name="890"><span class="lineNum">     890 </span><span class="lineCov">      25359 :   wire [1:0]  maskedEntry =</span></a>
+<a name="891"><span class="lineNum">     891 </span>            :     io_update_bits_meta[56] &amp; longerHistoryTableMask[0] &amp; allocLFSR_lfsr[0]</a>
+<a name="892"><span class="lineNum">     892 </span>            :       ? 2'h0</a>
+<a name="893"><span class="lineNum">     893 </span>            :       : io_update_bits_meta[57] &amp; longerHistoryTableMask[1] &amp; allocLFSR_lfsr[1]</a>
+<a name="894"><span class="lineNum">     894 </span>            :           ? 2'h1</a>
+<a name="895"><span class="lineNum">     895 </span>            :           : {1'h1,</a>
+<a name="896"><span class="lineNum">     896 </span>            :              ~(io_update_bits_meta[58] &amp; longerHistoryTableMask[2] &amp; allocLFSR_lfsr[2])};</a>
+<a name="897"><span class="lineNum">     897 </span>            :   wire [3:0]  _allocate_T =</a>
+<a name="898"><span class="lineNum">     898 </span>            :     (io_update_bits_meta[59:56] &amp; longerHistoryTableMask) &gt;&gt; maskedEntry;</a>
+<a name="899"><span class="lineNum">     899 </span><span class="lineCov">      21731 :   wire [1:0]  allocate =</span></a>
+<a name="900"><span class="lineNum">     900 </span>            :     _allocate_T[0]</a>
+<a name="901"><span class="lineNum">     901 </span>            :       ? maskedEntry</a>
+<a name="902"><span class="lineNum">     902 </span>            :       : _firstEntry_T ? 2'h0 : _firstEntry_T_1 ? 2'h1 : {1'h1, ~_firstEntry_T_2};</a>
+<a name="903"><span class="lineNum">     903 </span>            :   wire        _GEN_7 = allocate == 2'h0;</a>
+<a name="904"><span class="lineNum">     904 </span>            :   wire        _GEN_8 = needToAllocate &amp; (|(io_update_bits_meta[59:56])) &amp; _GEN_7;</a>
+<a name="905"><span class="lineNum">     905 </span><span class="lineCov">         13 :   wire        updateMask_0_0 = _GEN_8 | _GEN_4 &amp; _GEN_3;</span></a>
+<a name="906"><span class="lineNum">     906 </span>            :   wire        _GEN_9 = allocate == 2'h1;</a>
+<a name="907"><span class="lineNum">     907 </span>            :   wire        _GEN_10 = needToAllocate &amp; (|(io_update_bits_meta[59:56])) &amp; _GEN_9;</a>
+<a name="908"><span class="lineNum">     908 </span><span class="lineCov">         11 :   wire        updateMask_0_1 = _GEN_10 | _GEN_4 &amp; _GEN_5;</span></a>
+<a name="909"><span class="lineNum">     909 </span>            :   wire        _GEN_11 = allocate == 2'h2;</a>
+<a name="910"><span class="lineNum">     910 </span>            :   wire        _GEN_12 = needToAllocate &amp; (|(io_update_bits_meta[59:56])) &amp; _GEN_11;</a>
+<a name="911"><span class="lineNum">     911 </span><span class="lineCov">         20 :   wire        updateMask_0_2 = _GEN_12 | _GEN_4 &amp; _GEN_6;</span></a>
+<a name="912"><span class="lineNum">     912 </span>            :   wire        _GEN_13 = needToAllocate &amp; (|(io_update_bits_meta[59:56])) &amp; (&amp;allocate);</a>
+<a name="913"><span class="lineNum">     913 </span><span class="lineCov">         17 :   wire        updateMask_0_3 = _GEN_13 | _GEN_4 &amp; (&amp;(io_update_bits_meta[83:82]));</span></a>
+<a name="914"><span class="lineNum">     914 </span>            :   wire        _GEN_14 = needToAllocate &amp; (|(io_update_bits_meta[59:56]));</a>
+<a name="915"><span class="lineNum">     915 </span><span class="lineCov">         12 :   wire        updateResetU_0 = needToAllocate &amp; (&amp;bankTickCtrs_0);</span></a>
+<a name="916"><span class="lineNum">     916 </span><span class="lineCov">         33 :   wire        useAltCtr_1 =</span></a>
+<a name="917"><span class="lineNum">     917 </span>            :     s1_pc_dup_0[7:1] == 7'h0 &amp; useAltOnNaCtrs_1_0[3] | s1_pc_dup_0[7:1] == 7'h1</a>
+<a name="918"><span class="lineNum">     918 </span>            :     &amp; useAltOnNaCtrs_1_1[3] | s1_pc_dup_0[7:1] == 7'h2 &amp; useAltOnNaCtrs_1_2[3]</a>
+<a name="919"><span class="lineNum">     919 </span>            :     | s1_pc_dup_0[7:1] == 7'h3 &amp; useAltOnNaCtrs_1_3[3] | s1_pc_dup_0[7:1] == 7'h4</a>
+<a name="920"><span class="lineNum">     920 </span>            :     &amp; useAltOnNaCtrs_1_4[3] | s1_pc_dup_0[7:1] == 7'h5 &amp; useAltOnNaCtrs_1_5[3]</a>
+<a name="921"><span class="lineNum">     921 </span>            :     | s1_pc_dup_0[7:1] == 7'h6 &amp; useAltOnNaCtrs_1_6[3] | s1_pc_dup_0[7:1] == 7'h7</a>
+<a name="922"><span class="lineNum">     922 </span>            :     &amp; useAltOnNaCtrs_1_7[3] | s1_pc_dup_0[7:1] == 7'h8 &amp; useAltOnNaCtrs_1_8[3]</a>
+<a name="923"><span class="lineNum">     923 </span>            :     | s1_pc_dup_0[7:1] == 7'h9 &amp; useAltOnNaCtrs_1_9[3] | s1_pc_dup_0[7:1] == 7'hA</a>
+<a name="924"><span class="lineNum">     924 </span>            :     &amp; useAltOnNaCtrs_1_10[3] | s1_pc_dup_0[7:1] == 7'hB &amp; useAltOnNaCtrs_1_11[3]</a>
+<a name="925"><span class="lineNum">     925 </span>            :     | s1_pc_dup_0[7:1] == 7'hC &amp; useAltOnNaCtrs_1_12[3] | s1_pc_dup_0[7:1] == 7'hD</a>
+<a name="926"><span class="lineNum">     926 </span>            :     &amp; useAltOnNaCtrs_1_13[3] | s1_pc_dup_0[7:1] == 7'hE &amp; useAltOnNaCtrs_1_14[3]</a>
+<a name="927"><span class="lineNum">     927 </span>            :     | s1_pc_dup_0[7:1] == 7'hF &amp; useAltOnNaCtrs_1_15[3] | s1_pc_dup_0[7:1] == 7'h10</a>
+<a name="928"><span class="lineNum">     928 </span>            :     &amp; useAltOnNaCtrs_1_16[3] | s1_pc_dup_0[7:1] == 7'h11 &amp; useAltOnNaCtrs_1_17[3]</a>
+<a name="929"><span class="lineNum">     929 </span>            :     | s1_pc_dup_0[7:1] == 7'h12 &amp; useAltOnNaCtrs_1_18[3] | s1_pc_dup_0[7:1] == 7'h13</a>
+<a name="930"><span class="lineNum">     930 </span>            :     &amp; useAltOnNaCtrs_1_19[3] | s1_pc_dup_0[7:1] == 7'h14 &amp; useAltOnNaCtrs_1_20[3]</a>
+<a name="931"><span class="lineNum">     931 </span>            :     | s1_pc_dup_0[7:1] == 7'h15 &amp; useAltOnNaCtrs_1_21[3] | s1_pc_dup_0[7:1] == 7'h16</a>
+<a name="932"><span class="lineNum">     932 </span>            :     &amp; useAltOnNaCtrs_1_22[3] | s1_pc_dup_0[7:1] == 7'h17 &amp; useAltOnNaCtrs_1_23[3]</a>
+<a name="933"><span class="lineNum">     933 </span>            :     | s1_pc_dup_0[7:1] == 7'h18 &amp; useAltOnNaCtrs_1_24[3] | s1_pc_dup_0[7:1] == 7'h19</a>
+<a name="934"><span class="lineNum">     934 </span>            :     &amp; useAltOnNaCtrs_1_25[3] | s1_pc_dup_0[7:1] == 7'h1A &amp; useAltOnNaCtrs_1_26[3]</a>
+<a name="935"><span class="lineNum">     935 </span>            :     | s1_pc_dup_0[7:1] == 7'h1B &amp; useAltOnNaCtrs_1_27[3] | s1_pc_dup_0[7:1] == 7'h1C</a>
+<a name="936"><span class="lineNum">     936 </span>            :     &amp; useAltOnNaCtrs_1_28[3] | s1_pc_dup_0[7:1] == 7'h1D &amp; useAltOnNaCtrs_1_29[3]</a>
+<a name="937"><span class="lineNum">     937 </span>            :     | s1_pc_dup_0[7:1] == 7'h1E &amp; useAltOnNaCtrs_1_30[3] | s1_pc_dup_0[7:1] == 7'h1F</a>
+<a name="938"><span class="lineNum">     938 </span>            :     &amp; useAltOnNaCtrs_1_31[3] | s1_pc_dup_0[7:1] == 7'h20 &amp; useAltOnNaCtrs_1_32[3]</a>
+<a name="939"><span class="lineNum">     939 </span>            :     | s1_pc_dup_0[7:1] == 7'h21 &amp; useAltOnNaCtrs_1_33[3] | s1_pc_dup_0[7:1] == 7'h22</a>
+<a name="940"><span class="lineNum">     940 </span>            :     &amp; useAltOnNaCtrs_1_34[3] | s1_pc_dup_0[7:1] == 7'h23 &amp; useAltOnNaCtrs_1_35[3]</a>
+<a name="941"><span class="lineNum">     941 </span>            :     | s1_pc_dup_0[7:1] == 7'h24 &amp; useAltOnNaCtrs_1_36[3] | s1_pc_dup_0[7:1] == 7'h25</a>
+<a name="942"><span class="lineNum">     942 </span>            :     &amp; useAltOnNaCtrs_1_37[3] | s1_pc_dup_0[7:1] == 7'h26 &amp; useAltOnNaCtrs_1_38[3]</a>
+<a name="943"><span class="lineNum">     943 </span>            :     | s1_pc_dup_0[7:1] == 7'h27 &amp; useAltOnNaCtrs_1_39[3] | s1_pc_dup_0[7:1] == 7'h28</a>
+<a name="944"><span class="lineNum">     944 </span>            :     &amp; useAltOnNaCtrs_1_40[3] | s1_pc_dup_0[7:1] == 7'h29 &amp; useAltOnNaCtrs_1_41[3]</a>
+<a name="945"><span class="lineNum">     945 </span>            :     | s1_pc_dup_0[7:1] == 7'h2A &amp; useAltOnNaCtrs_1_42[3] | s1_pc_dup_0[7:1] == 7'h2B</a>
+<a name="946"><span class="lineNum">     946 </span>            :     &amp; useAltOnNaCtrs_1_43[3] | s1_pc_dup_0[7:1] == 7'h2C &amp; useAltOnNaCtrs_1_44[3]</a>
+<a name="947"><span class="lineNum">     947 </span>            :     | s1_pc_dup_0[7:1] == 7'h2D &amp; useAltOnNaCtrs_1_45[3] | s1_pc_dup_0[7:1] == 7'h2E</a>
+<a name="948"><span class="lineNum">     948 </span>            :     &amp; useAltOnNaCtrs_1_46[3] | s1_pc_dup_0[7:1] == 7'h2F &amp; useAltOnNaCtrs_1_47[3]</a>
+<a name="949"><span class="lineNum">     949 </span>            :     | s1_pc_dup_0[7:1] == 7'h30 &amp; useAltOnNaCtrs_1_48[3] | s1_pc_dup_0[7:1] == 7'h31</a>
+<a name="950"><span class="lineNum">     950 </span>            :     &amp; useAltOnNaCtrs_1_49[3] | s1_pc_dup_0[7:1] == 7'h32 &amp; useAltOnNaCtrs_1_50[3]</a>
+<a name="951"><span class="lineNum">     951 </span>            :     | s1_pc_dup_0[7:1] == 7'h33 &amp; useAltOnNaCtrs_1_51[3] | s1_pc_dup_0[7:1] == 7'h34</a>
+<a name="952"><span class="lineNum">     952 </span>            :     &amp; useAltOnNaCtrs_1_52[3] | s1_pc_dup_0[7:1] == 7'h35 &amp; useAltOnNaCtrs_1_53[3]</a>
+<a name="953"><span class="lineNum">     953 </span>            :     | s1_pc_dup_0[7:1] == 7'h36 &amp; useAltOnNaCtrs_1_54[3] | s1_pc_dup_0[7:1] == 7'h37</a>
+<a name="954"><span class="lineNum">     954 </span>            :     &amp; useAltOnNaCtrs_1_55[3] | s1_pc_dup_0[7:1] == 7'h38 &amp; useAltOnNaCtrs_1_56[3]</a>
+<a name="955"><span class="lineNum">     955 </span>            :     | s1_pc_dup_0[7:1] == 7'h39 &amp; useAltOnNaCtrs_1_57[3] | s1_pc_dup_0[7:1] == 7'h3A</a>
+<a name="956"><span class="lineNum">     956 </span>            :     &amp; useAltOnNaCtrs_1_58[3] | s1_pc_dup_0[7:1] == 7'h3B &amp; useAltOnNaCtrs_1_59[3]</a>
+<a name="957"><span class="lineNum">     957 </span>            :     | s1_pc_dup_0[7:1] == 7'h3C &amp; useAltOnNaCtrs_1_60[3] | s1_pc_dup_0[7:1] == 7'h3D</a>
+<a name="958"><span class="lineNum">     958 </span>            :     &amp; useAltOnNaCtrs_1_61[3] | s1_pc_dup_0[7:1] == 7'h3E &amp; useAltOnNaCtrs_1_62[3]</a>
+<a name="959"><span class="lineNum">     959 </span>            :     | s1_pc_dup_0[7:1] == 7'h3F &amp; useAltOnNaCtrs_1_63[3] | s1_pc_dup_0[7:1] == 7'h40</a>
+<a name="960"><span class="lineNum">     960 </span>            :     &amp; useAltOnNaCtrs_1_64[3] | s1_pc_dup_0[7:1] == 7'h41 &amp; useAltOnNaCtrs_1_65[3]</a>
+<a name="961"><span class="lineNum">     961 </span>            :     | s1_pc_dup_0[7:1] == 7'h42 &amp; useAltOnNaCtrs_1_66[3] | s1_pc_dup_0[7:1] == 7'h43</a>
+<a name="962"><span class="lineNum">     962 </span>            :     &amp; useAltOnNaCtrs_1_67[3] | s1_pc_dup_0[7:1] == 7'h44 &amp; useAltOnNaCtrs_1_68[3]</a>
+<a name="963"><span class="lineNum">     963 </span>            :     | s1_pc_dup_0[7:1] == 7'h45 &amp; useAltOnNaCtrs_1_69[3] | s1_pc_dup_0[7:1] == 7'h46</a>
+<a name="964"><span class="lineNum">     964 </span>            :     &amp; useAltOnNaCtrs_1_70[3] | s1_pc_dup_0[7:1] == 7'h47 &amp; useAltOnNaCtrs_1_71[3]</a>
+<a name="965"><span class="lineNum">     965 </span>            :     | s1_pc_dup_0[7:1] == 7'h48 &amp; useAltOnNaCtrs_1_72[3] | s1_pc_dup_0[7:1] == 7'h49</a>
+<a name="966"><span class="lineNum">     966 </span>            :     &amp; useAltOnNaCtrs_1_73[3] | s1_pc_dup_0[7:1] == 7'h4A &amp; useAltOnNaCtrs_1_74[3]</a>
+<a name="967"><span class="lineNum">     967 </span>            :     | s1_pc_dup_0[7:1] == 7'h4B &amp; useAltOnNaCtrs_1_75[3] | s1_pc_dup_0[7:1] == 7'h4C</a>
+<a name="968"><span class="lineNum">     968 </span>            :     &amp; useAltOnNaCtrs_1_76[3] | s1_pc_dup_0[7:1] == 7'h4D &amp; useAltOnNaCtrs_1_77[3]</a>
+<a name="969"><span class="lineNum">     969 </span>            :     | s1_pc_dup_0[7:1] == 7'h4E &amp; useAltOnNaCtrs_1_78[3] | s1_pc_dup_0[7:1] == 7'h4F</a>
+<a name="970"><span class="lineNum">     970 </span>            :     &amp; useAltOnNaCtrs_1_79[3] | s1_pc_dup_0[7:1] == 7'h50 &amp; useAltOnNaCtrs_1_80[3]</a>
+<a name="971"><span class="lineNum">     971 </span>            :     | s1_pc_dup_0[7:1] == 7'h51 &amp; useAltOnNaCtrs_1_81[3] | s1_pc_dup_0[7:1] == 7'h52</a>
+<a name="972"><span class="lineNum">     972 </span>            :     &amp; useAltOnNaCtrs_1_82[3] | s1_pc_dup_0[7:1] == 7'h53 &amp; useAltOnNaCtrs_1_83[3]</a>
+<a name="973"><span class="lineNum">     973 </span>            :     | s1_pc_dup_0[7:1] == 7'h54 &amp; useAltOnNaCtrs_1_84[3] | s1_pc_dup_0[7:1] == 7'h55</a>
+<a name="974"><span class="lineNum">     974 </span>            :     &amp; useAltOnNaCtrs_1_85[3] | s1_pc_dup_0[7:1] == 7'h56 &amp; useAltOnNaCtrs_1_86[3]</a>
+<a name="975"><span class="lineNum">     975 </span>            :     | s1_pc_dup_0[7:1] == 7'h57 &amp; useAltOnNaCtrs_1_87[3] | s1_pc_dup_0[7:1] == 7'h58</a>
+<a name="976"><span class="lineNum">     976 </span>            :     &amp; useAltOnNaCtrs_1_88[3] | s1_pc_dup_0[7:1] == 7'h59 &amp; useAltOnNaCtrs_1_89[3]</a>
+<a name="977"><span class="lineNum">     977 </span>            :     | s1_pc_dup_0[7:1] == 7'h5A &amp; useAltOnNaCtrs_1_90[3] | s1_pc_dup_0[7:1] == 7'h5B</a>
+<a name="978"><span class="lineNum">     978 </span>            :     &amp; useAltOnNaCtrs_1_91[3] | s1_pc_dup_0[7:1] == 7'h5C &amp; useAltOnNaCtrs_1_92[3]</a>
+<a name="979"><span class="lineNum">     979 </span>            :     | s1_pc_dup_0[7:1] == 7'h5D &amp; useAltOnNaCtrs_1_93[3] | s1_pc_dup_0[7:1] == 7'h5E</a>
+<a name="980"><span class="lineNum">     980 </span>            :     &amp; useAltOnNaCtrs_1_94[3] | s1_pc_dup_0[7:1] == 7'h5F &amp; useAltOnNaCtrs_1_95[3]</a>
+<a name="981"><span class="lineNum">     981 </span>            :     | s1_pc_dup_0[7:1] == 7'h60 &amp; useAltOnNaCtrs_1_96[3] | s1_pc_dup_0[7:1] == 7'h61</a>
+<a name="982"><span class="lineNum">     982 </span>            :     &amp; useAltOnNaCtrs_1_97[3] | s1_pc_dup_0[7:1] == 7'h62 &amp; useAltOnNaCtrs_1_98[3]</a>
+<a name="983"><span class="lineNum">     983 </span>            :     | s1_pc_dup_0[7:1] == 7'h63 &amp; useAltOnNaCtrs_1_99[3] | s1_pc_dup_0[7:1] == 7'h64</a>
+<a name="984"><span class="lineNum">     984 </span>            :     &amp; useAltOnNaCtrs_1_100[3] | s1_pc_dup_0[7:1] == 7'h65 &amp; useAltOnNaCtrs_1_101[3]</a>
+<a name="985"><span class="lineNum">     985 </span>            :     | s1_pc_dup_0[7:1] == 7'h66 &amp; useAltOnNaCtrs_1_102[3] | s1_pc_dup_0[7:1] == 7'h67</a>
+<a name="986"><span class="lineNum">     986 </span>            :     &amp; useAltOnNaCtrs_1_103[3] | s1_pc_dup_0[7:1] == 7'h68 &amp; useAltOnNaCtrs_1_104[3]</a>
+<a name="987"><span class="lineNum">     987 </span>            :     | s1_pc_dup_0[7:1] == 7'h69 &amp; useAltOnNaCtrs_1_105[3] | s1_pc_dup_0[7:1] == 7'h6A</a>
+<a name="988"><span class="lineNum">     988 </span>            :     &amp; useAltOnNaCtrs_1_106[3] | s1_pc_dup_0[7:1] == 7'h6B &amp; useAltOnNaCtrs_1_107[3]</a>
+<a name="989"><span class="lineNum">     989 </span>            :     | s1_pc_dup_0[7:1] == 7'h6C &amp; useAltOnNaCtrs_1_108[3] | s1_pc_dup_0[7:1] == 7'h6D</a>
+<a name="990"><span class="lineNum">     990 </span>            :     &amp; useAltOnNaCtrs_1_109[3] | s1_pc_dup_0[7:1] == 7'h6E &amp; useAltOnNaCtrs_1_110[3]</a>
+<a name="991"><span class="lineNum">     991 </span>            :     | s1_pc_dup_0[7:1] == 7'h6F &amp; useAltOnNaCtrs_1_111[3] | s1_pc_dup_0[7:1] == 7'h70</a>
+<a name="992"><span class="lineNum">     992 </span>            :     &amp; useAltOnNaCtrs_1_112[3] | s1_pc_dup_0[7:1] == 7'h71 &amp; useAltOnNaCtrs_1_113[3]</a>
+<a name="993"><span class="lineNum">     993 </span>            :     | s1_pc_dup_0[7:1] == 7'h72 &amp; useAltOnNaCtrs_1_114[3] | s1_pc_dup_0[7:1] == 7'h73</a>
+<a name="994"><span class="lineNum">     994 </span>            :     &amp; useAltOnNaCtrs_1_115[3] | s1_pc_dup_0[7:1] == 7'h74 &amp; useAltOnNaCtrs_1_116[3]</a>
+<a name="995"><span class="lineNum">     995 </span>            :     | s1_pc_dup_0[7:1] == 7'h75 &amp; useAltOnNaCtrs_1_117[3] | s1_pc_dup_0[7:1] == 7'h76</a>
+<a name="996"><span class="lineNum">     996 </span>            :     &amp; useAltOnNaCtrs_1_118[3] | s1_pc_dup_0[7:1] == 7'h77 &amp; useAltOnNaCtrs_1_119[3]</a>
+<a name="997"><span class="lineNum">     997 </span>            :     | s1_pc_dup_0[7:1] == 7'h78 &amp; useAltOnNaCtrs_1_120[3] | s1_pc_dup_0[7:1] == 7'h79</a>
+<a name="998"><span class="lineNum">     998 </span>            :     &amp; useAltOnNaCtrs_1_121[3] | s1_pc_dup_0[7:1] == 7'h7A &amp; useAltOnNaCtrs_1_122[3]</a>
+<a name="999"><span class="lineNum">     999 </span>            :     | s1_pc_dup_0[7:1] == 7'h7B &amp; useAltOnNaCtrs_1_123[3] | s1_pc_dup_0[7:1] == 7'h7C</a>
+<a name="1000"><span class="lineNum">    1000 </span>            :     &amp; useAltOnNaCtrs_1_124[3] | s1_pc_dup_0[7:1] == 7'h7D &amp; useAltOnNaCtrs_1_125[3]</a>
+<a name="1001"><span class="lineNum">    1001 </span>            :     | s1_pc_dup_0[7:1] == 7'h7E &amp; useAltOnNaCtrs_1_126[3] | (&amp;(s1_pc_dup_0[7:1]))</a>
+<a name="1002"><span class="lineNum">    1002 </span>            :     &amp; useAltOnNaCtrs_1_127[3];</a>
+<a name="1003"><span class="lineNum">    1003 </span>            :   wire        _providerInfo_T_5 = _tables_3_io_resps_1_valid | _tables_2_io_resps_1_valid;</a>
+<a name="1004"><span class="lineNum">    1004 </span><span class="lineCov">        112 :   wire [2:0]  s1_providerResps_1_ctr =</span></a>
+<a name="1005"><span class="lineNum">    1005 </span>            :     _providerInfo_T_5</a>
+<a name="1006"><span class="lineNum">    1006 </span>            :       ? (_tables_3_io_resps_1_valid</a>
+<a name="1007"><span class="lineNum">    1007 </span>            :            ? _tables_3_io_resps_1_bits_ctr</a>
+<a name="1008"><span class="lineNum">    1008 </span>            :            : _tables_2_io_resps_1_bits_ctr)</a>
+<a name="1009"><span class="lineNum">    1009 </span>            :       : _tables_1_io_resps_1_valid</a>
+<a name="1010"><span class="lineNum">    1010 </span>            :           ? _tables_1_io_resps_1_bits_ctr</a>
+<a name="1011"><span class="lineNum">    1011 </span>            :           : _tables_0_io_resps_1_bits_ctr;</a>
+<a name="1012"><span class="lineNum">    1012 </span><span class="lineCov">         14 :   wire        provided_1 =</span></a>
+<a name="1013"><span class="lineNum">    1013 </span>            :     _tables_0_io_resps_1_valid | _tables_1_io_resps_1_valid | _tables_2_io_resps_1_valid</a>
+<a name="1014"><span class="lineNum">    1014 </span>            :     | _tables_3_io_resps_1_valid;</a>
+<a name="1015"><span class="lineNum">    1015 </span><span class="lineCov">         13 :   wire        s1_altUsed_1 =</span></a>
+<a name="1016"><span class="lineNum">    1016 </span>            :     ~provided_1</a>
+<a name="1017"><span class="lineNum">    1017 </span>            :     | (_providerInfo_T_5</a>
+<a name="1018"><span class="lineNum">    1018 </span>            :          ? (_tables_3_io_resps_1_valid</a>
+<a name="1019"><span class="lineNum">    1019 </span>            :               ? _tables_3_io_resps_1_bits_unconf &amp; useAltCtr_1</a>
+<a name="1020"><span class="lineNum">    1020 </span>            :               : _tables_2_io_resps_1_bits_unconf &amp; useAltCtr_1)</a>
+<a name="1021"><span class="lineNum">    1021 </span>            :          : _tables_1_io_resps_1_valid</a>
+<a name="1022"><span class="lineNum">    1022 </span>            :              ? _tables_1_io_resps_1_bits_unconf &amp; useAltCtr_1</a>
+<a name="1023"><span class="lineNum">    1023 </span>            :              : _tables_0_io_resps_1_bits_unconf &amp; useAltCtr_1);</a>
+<a name="1024"><span class="lineNum">    1024 </span><span class="lineCov">         33 :   wire        s1_tageTakens_1 =</span></a>
+<a name="1025"><span class="lineNum">    1025 </span>            :     s1_altUsed_1 ? _bt_io_s1_cnt_1[1] : s1_providerResps_1_ctr[2];</a>
+<a name="1026"><span class="lineNum">    1026 </span><span class="lineCov">         17 :   wire        baseupdate_1 = updateValids_1 &amp; io_update_bits_meta[71];</span></a>
+<a name="1027"><span class="lineNum">    1027 </span>            :   wire        _GEN_15 = io_update_bits_meta[86:85] == 2'h0;</a>
+<a name="1028"><span class="lineNum">    1028 </span>            :   wire        _GEN_16 = updateValids_1 &amp; io_update_bits_meta[87];</a>
+<a name="1029"><span class="lineNum">    1029 </span>            :   wire        _GEN_17 = io_update_bits_meta[86:85] == 2'h1;</a>
+<a name="1030"><span class="lineNum">    1030 </span>            :   wire        _GEN_18 = io_update_bits_meta[86:85] == 2'h2;</a>
+<a name="1031"><span class="lineNum">    1031 </span><span class="lineCov">      25309 :   wire [1:0]  maskedEntry_1 =</span></a>
+<a name="1032"><span class="lineNum">    1032 </span>            :     io_update_bits_meta[60] &amp; longerHistoryTableMask_1[0] &amp; allocLFSR_lfsr_1[0]</a>
+<a name="1033"><span class="lineNum">    1033 </span>            :       ? 2'h0</a>
+<a name="1034"><span class="lineNum">    1034 </span>            :       : io_update_bits_meta[61] &amp; longerHistoryTableMask_1[1] &amp; allocLFSR_lfsr_1[1]</a>
+<a name="1035"><span class="lineNum">    1035 </span>            :           ? 2'h1</a>
+<a name="1036"><span class="lineNum">    1036 </span>            :           : {1'h1,</a>
+<a name="1037"><span class="lineNum">    1037 </span>            :              ~(io_update_bits_meta[62] &amp; longerHistoryTableMask_1[2]</a>
+<a name="1038"><span class="lineNum">    1038 </span>            :                &amp; allocLFSR_lfsr_1[2])};</a>
+<a name="1039"><span class="lineNum">    1039 </span>            :   wire [3:0]  _allocate_T_2 =</a>
+<a name="1040"><span class="lineNum">    1040 </span>            :     (io_update_bits_meta[63:60] &amp; longerHistoryTableMask_1) &gt;&gt; maskedEntry_1;</a>
+<a name="1041"><span class="lineNum">    1041 </span><span class="lineCov">      17630 :   wire [1:0]  allocate_1 =</span></a>
+<a name="1042"><span class="lineNum">    1042 </span>            :     _allocate_T_2[0]</a>
+<a name="1043"><span class="lineNum">    1043 </span>            :       ? maskedEntry_1</a>
+<a name="1044"><span class="lineNum">    1044 </span>            :       : _firstEntry_T_6 ? 2'h0 : _firstEntry_T_7 ? 2'h1 : {1'h1, ~_firstEntry_T_8};</a>
+<a name="1045"><span class="lineNum">    1045 </span>            :   wire        _GEN_19 = allocate_1 == 2'h0;</a>
+<a name="1046"><span class="lineNum">    1046 </span>            :   wire        _GEN_20 = needToAllocate_1 &amp; (|(io_update_bits_meta[63:60])) &amp; _GEN_19;</a>
+<a name="1047"><span class="lineNum">    1047 </span><span class="lineCov">         18 :   wire        updateMask_1_0 = _GEN_20 | _GEN_16 &amp; _GEN_15;</span></a>
+<a name="1048"><span class="lineNum">    1048 </span>            :   wire        _GEN_21 = allocate_1 == 2'h1;</a>
+<a name="1049"><span class="lineNum">    1049 </span>            :   wire        _GEN_22 = needToAllocate_1 &amp; (|(io_update_bits_meta[63:60])) &amp; _GEN_21;</a>
+<a name="1050"><span class="lineNum">    1050 </span><span class="lineCov">         19 :   wire        updateMask_1_1 = _GEN_22 | _GEN_16 &amp; _GEN_17;</span></a>
+<a name="1051"><span class="lineNum">    1051 </span>            :   wire        _GEN_23 = allocate_1 == 2'h2;</a>
+<a name="1052"><span class="lineNum">    1052 </span>            :   wire        _GEN_24 = needToAllocate_1 &amp; (|(io_update_bits_meta[63:60])) &amp; _GEN_23;</a>
+<a name="1053"><span class="lineNum">    1053 </span><span class="lineCov">         15 :   wire        updateMask_1_2 = _GEN_24 | _GEN_16 &amp; _GEN_18;</span></a>
+<a name="1054"><span class="lineNum">    1054 </span>            :   wire        _GEN_25 =</a>
+<a name="1055"><span class="lineNum">    1055 </span>            :     needToAllocate_1 &amp; (|(io_update_bits_meta[63:60])) &amp; (&amp;allocate_1);</a>
+<a name="1056"><span class="lineNum">    1056 </span><span class="lineCov">         15 :   wire        updateMask_1_3 = _GEN_25 | _GEN_16 &amp; (&amp;(io_update_bits_meta[86:85]));</span></a>
+<a name="1057"><span class="lineNum">    1057 </span>            :   wire        _GEN_26 = needToAllocate_1 &amp; (|(io_update_bits_meta[63:60]));</a>
+<a name="1058"><span class="lineNum">    1058 </span><span class="lineCov">         14 :   wire        updateResetU_1 = needToAllocate_1 &amp; (&amp;bankTickCtrs_1);</span></a>
+<a name="1059"><span class="lineNum">    1059 </span>            :   wire [2:0]  _s2_tagePrvdCtrCentered_T = s2_tagePrvdCtrCentered_r ^ 3'h4;</a>
+<a name="1060"><span class="lineNum">    1060 </span>            :   wire [9:0]  _GEN_27 =</a>
+<a name="1061"><span class="lineNum">    1061 </span>            :     {{3{_s2_tagePrvdCtrCentered_T[2]}}, _s2_tagePrvdCtrCentered_T, 4'h8};</a>
+<a name="1062"><span class="lineNum">    1062 </span><span class="lineCov">        317 :   wire [9:0]  s2_totalSums_0 = 10'({s2_scTableSums_0[8], s2_scTableSums_0} + _GEN_27);</span></a>
+<a name="1063"><span class="lineNum">    1063 </span><span class="lineCov">        332 :   wire [9:0]  s2_totalSums_1 = 10'({s2_scTableSums_1[8], s2_scTableSums_1} + _GEN_27);</span></a>
+<a name="1064"><span class="lineNum">    1064 </span>            :   wire [8:0]  _GEN_28 = {1'h0, scThresholds_0_thres};</a>
+<a name="1065"><span class="lineNum">    1065 </span>            :   wire [8:0]  _GEN_29 =</a>
+<a name="1066"><span class="lineNum">    1066 </span>            :     {{2{_s2_tagePrvdCtrCentered_T[2]}}, _s2_tagePrvdCtrCentered_T, 4'h8};</a>
+<a name="1067"><span class="lineNum">    1067 </span>            :   wire        _GEN_30 =</a>
+<a name="1068"><span class="lineNum">    1068 </span>            :     s2_tageTakens_dup_3_0</a>
+<a name="1069"><span class="lineNum">    1069 </span>            :       ? $signed(s2_totalSums_1) &gt; -10'sh1</a>
+<a name="1070"><span class="lineNum">    1070 </span>            :       : $signed(s2_totalSums_0) &gt; -10'sh1;</a>
+<a name="1071"><span class="lineNum">    1071 </span><span class="lineCov">         27 :   wire        s2_pred =</span></a>
+<a name="1072"><span class="lineNum">    1072 </span>            :     s2_provideds_0</a>
+<a name="1073"><span class="lineNum">    1073 </span>            :     &amp; (s2_tageTakens_dup_3_0</a>
+<a name="1074"><span class="lineNum">    1074 </span>            :          ? $signed(s2_scTableSums_1) &gt; $signed(9'(_GEN_28 - _GEN_29))</a>
+<a name="1075"><span class="lineNum">    1075 </span>            :            &amp; ~(s2_totalSums_1[9])</a>
+<a name="1076"><span class="lineNum">    1076 </span>            :            | $signed(s2_scTableSums_1) &lt; $signed(9'(9'(9'h0 - _GEN_28) - _GEN_29))</a>
+<a name="1077"><span class="lineNum">    1077 </span>            :            &amp; s2_totalSums_1[9]</a>
+<a name="1078"><span class="lineNum">    1078 </span>            :          : $signed(s2_scTableSums_0) &gt; $signed(9'(_GEN_28 - _GEN_29))</a>
+<a name="1079"><span class="lineNum">    1079 </span>            :            &amp; ~(s2_totalSums_0[9])</a>
+<a name="1080"><span class="lineNum">    1080 </span>            :            | $signed(s2_scTableSums_0) &lt; $signed(9'(9'(9'h0 - _GEN_28) - _GEN_29))</a>
+<a name="1081"><span class="lineNum">    1081 </span>            :            &amp; s2_totalSums_0[9])</a>
+<a name="1082"><span class="lineNum">    1082 </span>            :       ? _GEN_30</a>
+<a name="1083"><span class="lineNum">    1083 </span>            :       : s2_tageTakens_dup_3_0;</a>
+<a name="1084"><span class="lineNum">    1084 </span>            :   wire [12:0] _GEN_31 = {1'h0, 12'({1'h0, scThresholds_0_thres, 3'h0} + 12'h15)};</a>
+<a name="1085"><span class="lineNum">    1085 </span>            :   wire [12:0] _GEN_32 = {{6{_sumAboveThreshold_T[2]}}, _sumAboveThreshold_T, 4'h8};</a>
+<a name="1086"><span class="lineNum">    1086 </span>            :   wire [12:0] _GEN_33 = {{3{sum[9]}}, sum};</a>
+<a name="1087"><span class="lineNum">    1087 </span><span class="lineCov">        278 :   wire [10:0] sumAboveThreshold_totalSum =</span></a>
+<a name="1088"><span class="lineNum">    1088 </span>            :     11'({sum[9], sum} + {{4{_sumAboveThreshold_T[2]}}, _sumAboveThreshold_T, 4'h8});</a>
+<a name="1089"><span class="lineNum">    1089 </span>            :   wire        _GEN_34 =</a>
+<a name="1090"><span class="lineNum">    1090 </span>            :     _update_on_mispred_0_T</a>
+<a name="1091"><span class="lineNum">    1091 </span>            :     | ~($signed(_GEN_33) &gt; $signed(13'(_GEN_31 - _GEN_32))</a>
+<a name="1092"><span class="lineNum">    1092 </span>            :         &amp; ~(sumAboveThreshold_totalSum[10])</a>
+<a name="1093"><span class="lineNum">    1093 </span>            :         | $signed(_GEN_33) &lt; $signed(13'(13'(13'h0 - _GEN_31) - _GEN_32))</a>
+<a name="1094"><span class="lineNum">    1094 </span>            :         &amp; sumAboveThreshold_totalSum[10]);</a>
+<a name="1095"><span class="lineNum">    1095 </span><span class="lineCov">         13 :   wire        scUpdateMask_0_3 = _GEN_1 &amp; _GEN_34;</span></a>
+<a name="1096"><span class="lineNum">    1096 </span>            :   wire        _GEN_35 = _GEN_1 &amp; _GEN_34;</a>
+<a name="1097"><span class="lineNum">    1097 </span>            :   wire [2:0]  _s2_tagePrvdCtrCentered_T_2 = s2_tagePrvdCtrCentered_r_1 ^ 3'h4;</a>
+<a name="1098"><span class="lineNum">    1098 </span>            :   wire [9:0]  _GEN_36 =</a>
+<a name="1099"><span class="lineNum">    1099 </span>            :     {{3{_s2_tagePrvdCtrCentered_T_2[2]}}, _s2_tagePrvdCtrCentered_T_2, 4'h8};</a>
+<a name="1100"><span class="lineNum">    1100 </span><span class="lineCov">        326 :   wire [9:0]  s2_totalSums_0_1 =</span></a>
+<a name="1101"><span class="lineNum">    1101 </span>            :     10'({s2_scTableSums_1_0[8], s2_scTableSums_1_0} + _GEN_36);</a>
+<a name="1102"><span class="lineNum">    1102 </span><span class="lineCov">        312 :   wire [9:0]  s2_totalSums_1_1 =</span></a>
+<a name="1103"><span class="lineNum">    1103 </span>            :     10'({s2_scTableSums_1_1[8], s2_scTableSums_1_1} + _GEN_36);</a>
+<a name="1104"><span class="lineNum">    1104 </span>            :   wire [8:0]  _GEN_37 = {1'h0, scThresholds_1_thres};</a>
+<a name="1105"><span class="lineNum">    1105 </span>            :   wire [8:0]  _GEN_38 =</a>
+<a name="1106"><span class="lineNum">    1106 </span>            :     {{2{_s2_tagePrvdCtrCentered_T_2[2]}}, _s2_tagePrvdCtrCentered_T_2, 4'h8};</a>
+<a name="1107"><span class="lineNum">    1107 </span>            :   wire        _GEN_39 =</a>
+<a name="1108"><span class="lineNum">    1108 </span>            :     s2_tageTakens_dup_3_1</a>
+<a name="1109"><span class="lineNum">    1109 </span>            :       ? $signed(s2_totalSums_1_1) &gt; -10'sh1</a>
+<a name="1110"><span class="lineNum">    1110 </span>            :       : $signed(s2_totalSums_0_1) &gt; -10'sh1;</a>
+<a name="1111"><span class="lineNum">    1111 </span><span class="lineCov">         42 :   wire        s2_pred_1 =</span></a>
+<a name="1112"><span class="lineNum">    1112 </span>            :     s2_provideds_1</a>
+<a name="1113"><span class="lineNum">    1113 </span>            :     &amp; (s2_tageTakens_dup_3_1</a>
+<a name="1114"><span class="lineNum">    1114 </span>            :          ? $signed(s2_scTableSums_1_1) &gt; $signed(9'(_GEN_37 - _GEN_38))</a>
+<a name="1115"><span class="lineNum">    1115 </span>            :            &amp; ~(s2_totalSums_1_1[9])</a>
+<a name="1116"><span class="lineNum">    1116 </span>            :            | $signed(s2_scTableSums_1_1) &lt; $signed(9'(9'(9'h0 - _GEN_37) - _GEN_38))</a>
+<a name="1117"><span class="lineNum">    1117 </span>            :            &amp; s2_totalSums_1_1[9]</a>
+<a name="1118"><span class="lineNum">    1118 </span>            :          : $signed(s2_scTableSums_1_0) &gt; $signed(9'(_GEN_37 - _GEN_38))</a>
+<a name="1119"><span class="lineNum">    1119 </span>            :            &amp; ~(s2_totalSums_0_1[9])</a>
+<a name="1120"><span class="lineNum">    1120 </span>            :            | $signed(s2_scTableSums_1_0) &lt; $signed(9'(9'(9'h0 - _GEN_37) - _GEN_38))</a>
+<a name="1121"><span class="lineNum">    1121 </span>            :            &amp; s2_totalSums_0_1[9])</a>
+<a name="1122"><span class="lineNum">    1122 </span>            :       ? _GEN_39</a>
+<a name="1123"><span class="lineNum">    1123 </span>            :       : s2_tageTakens_dup_3_1;</a>
+<a name="1124"><span class="lineNum">    1124 </span>            :   wire [12:0] _GEN_40 = {1'h0, 12'({1'h0, scThresholds_1_thres, 3'h0} + 12'h15)};</a>
+<a name="1125"><span class="lineNum">    1125 </span>            :   wire [12:0] _GEN_41 = {{6{_sumAboveThreshold_T_19[2]}}, _sumAboveThreshold_T_19, 4'h8};</a>
+<a name="1126"><span class="lineNum">    1126 </span>            :   wire [12:0] _GEN_42 = {{3{sum_1[9]}}, sum_1};</a>
+<a name="1127"><span class="lineNum">    1127 </span><span class="lineCov">        331 :   wire [10:0] sumAboveThreshold_totalSum_1 =</span></a>
+<a name="1128"><span class="lineNum">    1128 </span>            :     11'({sum_1[9], sum_1}</a>
+<a name="1129"><span class="lineNum">    1129 </span>            :         + {{4{_sumAboveThreshold_T_19[2]}}, _sumAboveThreshold_T_19, 4'h8});</a>
+<a name="1130"><span class="lineNum">    1130 </span>            :   wire        _GEN_43 =</a>
+<a name="1131"><span class="lineNum">    1131 </span>            :     _update_on_mispred_1_T</a>
+<a name="1132"><span class="lineNum">    1132 </span>            :     | ~($signed(_GEN_42) &gt; $signed(13'(_GEN_40 - _GEN_41))</a>
+<a name="1133"><span class="lineNum">    1133 </span>            :         &amp; ~(sumAboveThreshold_totalSum_1[10])</a>
+<a name="1134"><span class="lineNum">    1134 </span>            :         | $signed(_GEN_42) &lt; $signed(13'(13'(13'h0 - _GEN_40) - _GEN_41))</a>
+<a name="1135"><span class="lineNum">    1135 </span>            :         &amp; sumAboveThreshold_totalSum_1[10]);</a>
+<a name="1136"><span class="lineNum">    1136 </span><span class="lineCov">         14 :   wire        scUpdateMask_1_3 = _GEN_2 &amp; _GEN_43;</span></a>
+<a name="1137"><span class="lineNum">    1137 </span>            :   wire        _GEN_44 = _GEN_2 &amp; _GEN_43;</a>
+<a name="1138"><span class="lineNum">    1138 </span><span class="lineCov">         29 :   wire [1:0]  providerInfo_tableIdx =</span></a>
+<a name="1139"><span class="lineNum">    1139 </span>            :     _providerInfo_T</a>
+<a name="1140"><span class="lineNum">    1140 </span>            :       ? {1'h1, _tables_3_io_resps_0_valid}</a>
+<a name="1141"><span class="lineNum">    1141 </span>            :       : {1'h0, _tables_1_io_resps_0_valid};</a>
+<a name="1142"><span class="lineNum">    1142 </span>            :   wire [3:0]  _allocatableSlots_T_14 = 4'h1 &lt;&lt; providerInfo_tableIdx;</a>
+<a name="1143"><span class="lineNum">    1143 </span>            :   wire [2:0]  _GEN_45 = _allocatableSlots_T_14[2:0] | _allocatableSlots_T_14[3:1];</a>
+<a name="1144"><span class="lineNum">    1144 </span><span class="lineCov">         32 :   wire [1:0]  s1_providers_1 =</span></a>
+<a name="1145"><span class="lineNum">    1145 </span>            :     _providerInfo_T_5</a>
+<a name="1146"><span class="lineNum">    1146 </span>            :       ? {1'h1, _tables_3_io_resps_1_valid}</a>
+<a name="1147"><span class="lineNum">    1147 </span>            :       : {1'h0, _tables_1_io_resps_1_valid};</a>
+<a name="1148"><span class="lineNum">    1148 </span>            :   wire [3:0]  _allocatableSlots_T_39 = 4'h1 &lt;&lt; s1_providers_1;</a>
+<a name="1149"><span class="lineNum">    1149 </span>            :   wire [2:0]  _GEN_46 = _allocatableSlots_T_39[2:0] | _allocatableSlots_T_39[3:1];</a>
+<a name="1150"><span class="lineNum">    1150 </span><span class="lineCov">     127694 :   always @(posedge clock) begin</span></a>
+<a name="1151"><span class="lineNum">    1151 </span><span class="lineCov">        120 :     if (REG_1)</span></a>
+<a name="1152"><span class="lineNum">    1152 </span><span class="lineCov">         60 :       s1_pc_dup_0 &lt;= {5'h0, _reset_vector_delay_io_out};</span></a>
+<a name="1153"><span class="lineNum">    1153 </span><span class="lineCov">       8350 :     else if (io_s0_fire_0)</span></a>
+<a name="1154"><span class="lineNum">    1154 </span><span class="lineCov">       4175 :       s1_pc_dup_0 &lt;= io_in_bits_s0_pc_0;</span></a>
+<a name="1155"><span class="lineNum">    1155 </span><span class="lineCov">      63847 :     REG &lt;= reset;</span></a>
+<a name="1156"><span class="lineNum">    1156 </span><span class="lineCov">      63847 :     REG_1 &lt;= REG &amp; ~reset;</span></a>
+<a name="1157"><span class="lineNum">    1157 </span><span class="lineCov">       8252 :     if (io_s1_fire_1) begin</span></a>
+<a name="1158"><span class="lineNum">    1158 </span><span class="lineCov">       4126 :       s2_provideds_0 &lt;= provided;</span></a>
+<a name="1159"><span class="lineNum">    1159 </span><span class="lineCov">       4126 :       s2_provideds_1 &lt;= provided_1;</span></a>
+<a name="1160"><span class="lineNum">    1160 </span><span class="lineCov">       4126 :       s2_providers_0 &lt;= providerInfo_tableIdx;</span></a>
+<a name="1161"><span class="lineNum">    1161 </span><span class="lineCov">       4126 :       s2_providers_1 &lt;= s1_providers_1;</span></a>
+<a name="1162"><span class="lineNum">    1162 </span><span class="lineCov">       4126 :       s2_providerResps_0_ctr &lt;= providerInfo_resp_ctr;</span></a>
+<a name="1163"><span class="lineNum">    1163 </span><span class="lineCov">       4126 :       s2_providerResps_0_u &lt;=</span></a>
+<a name="1164"><span class="lineNum">    1164 </span><span class="lineCov">       4126 :         _providerInfo_T</span></a>
+<a name="1165"><span class="lineNum">    1165 </span><span class="lineCov">       4126 :           ? (_tables_3_io_resps_0_valid</span></a>
+<a name="1166"><span class="lineNum">    1166 </span><span class="lineCov">       4126 :                ? _tables_3_io_resps_0_bits_u</span></a>
+<a name="1167"><span class="lineNum">    1167 </span><span class="lineCov">       4126 :                : _tables_2_io_resps_0_bits_u)</span></a>
+<a name="1168"><span class="lineNum">    1168 </span><span class="lineCov">       4126 :           : _tables_1_io_resps_0_valid</span></a>
+<a name="1169"><span class="lineNum">    1169 </span><span class="lineCov">       4126 :               ? _tables_1_io_resps_0_bits_u</span></a>
+<a name="1170"><span class="lineNum">    1170 </span><span class="lineCov">       4126 :               : _tables_0_io_resps_0_bits_u;</span></a>
+<a name="1171"><span class="lineNum">    1171 </span><span class="lineCov">       4126 :       s2_providerResps_0_unconf &lt;=</span></a>
+<a name="1172"><span class="lineNum">    1172 </span><span class="lineCov">       4126 :         _providerInfo_T</span></a>
+<a name="1173"><span class="lineNum">    1173 </span><span class="lineCov">       4126 :           ? (_tables_3_io_resps_0_valid</span></a>
+<a name="1174"><span class="lineNum">    1174 </span><span class="lineCov">       4126 :                ? _tables_3_io_resps_0_bits_unconf</span></a>
+<a name="1175"><span class="lineNum">    1175 </span><span class="lineCov">       4126 :                : _tables_2_io_resps_0_bits_unconf)</span></a>
+<a name="1176"><span class="lineNum">    1176 </span><span class="lineCov">       4126 :           : _tables_1_io_resps_0_valid</span></a>
+<a name="1177"><span class="lineNum">    1177 </span><span class="lineCov">       4126 :               ? _tables_1_io_resps_0_bits_unconf</span></a>
+<a name="1178"><span class="lineNum">    1178 </span><span class="lineCov">       4126 :               : _tables_0_io_resps_0_bits_unconf;</span></a>
+<a name="1179"><span class="lineNum">    1179 </span><span class="lineCov">       4126 :       s2_providerResps_1_ctr &lt;= s1_providerResps_1_ctr;</span></a>
+<a name="1180"><span class="lineNum">    1180 </span><span class="lineCov">       4126 :       s2_providerResps_1_u &lt;=</span></a>
+<a name="1181"><span class="lineNum">    1181 </span><span class="lineCov">       4126 :         _providerInfo_T_5</span></a>
+<a name="1182"><span class="lineNum">    1182 </span><span class="lineCov">       4126 :           ? (_tables_3_io_resps_1_valid</span></a>
+<a name="1183"><span class="lineNum">    1183 </span><span class="lineCov">       4126 :                ? _tables_3_io_resps_1_bits_u</span></a>
+<a name="1184"><span class="lineNum">    1184 </span><span class="lineCov">       4126 :                : _tables_2_io_resps_1_bits_u)</span></a>
+<a name="1185"><span class="lineNum">    1185 </span><span class="lineCov">       4126 :           : _tables_1_io_resps_1_valid</span></a>
+<a name="1186"><span class="lineNum">    1186 </span><span class="lineCov">       4126 :               ? _tables_1_io_resps_1_bits_u</span></a>
+<a name="1187"><span class="lineNum">    1187 </span><span class="lineCov">       4126 :               : _tables_0_io_resps_1_bits_u;</span></a>
+<a name="1188"><span class="lineNum">    1188 </span><span class="lineCov">       4126 :       s2_providerResps_1_unconf &lt;=</span></a>
+<a name="1189"><span class="lineNum">    1189 </span><span class="lineCov">       4126 :         _providerInfo_T_5</span></a>
+<a name="1190"><span class="lineNum">    1190 </span><span class="lineCov">       4126 :           ? (_tables_3_io_resps_1_valid</span></a>
+<a name="1191"><span class="lineNum">    1191 </span><span class="lineCov">       4126 :                ? _tables_3_io_resps_1_bits_unconf</span></a>
+<a name="1192"><span class="lineNum">    1192 </span><span class="lineCov">       4126 :                : _tables_2_io_resps_1_bits_unconf)</span></a>
+<a name="1193"><span class="lineNum">    1193 </span><span class="lineCov">       4126 :           : _tables_1_io_resps_1_valid</span></a>
+<a name="1194"><span class="lineNum">    1194 </span><span class="lineCov">       4126 :               ? _tables_1_io_resps_1_bits_unconf</span></a>
+<a name="1195"><span class="lineNum">    1195 </span><span class="lineCov">       4126 :               : _tables_0_io_resps_1_bits_unconf;</span></a>
+<a name="1196"><span class="lineNum">    1196 </span><span class="lineCov">       4126 :       s2_altUsed_0 &lt;= s1_altUsed_0;</span></a>
+<a name="1197"><span class="lineNum">    1197 </span><span class="lineCov">       4126 :       s2_altUsed_1 &lt;= s1_altUsed_1;</span></a>
+<a name="1198"><span class="lineNum">    1198 </span><span class="lineCov">       4126 :       s2_tageTakens_dup_1_0 &lt;= s1_tageTakens_0;</span></a>
+<a name="1199"><span class="lineNum">    1199 </span><span class="lineCov">       4126 :       s2_tageTakens_dup_1_1 &lt;= s1_tageTakens_1;</span></a>
+<a name="1200"><span class="lineNum">    1200 </span><span class="lineCov">       4126 :       s2_finalAltPreds_0 &lt;= _bt_io_s1_cnt_0[1];</span></a>
+<a name="1201"><span class="lineNum">    1201 </span><span class="lineCov">       4126 :       s2_finalAltPreds_1 &lt;= _bt_io_s1_cnt_1[1];</span></a>
+<a name="1202"><span class="lineNum">    1202 </span><span class="lineCov">       4126 :       s2_basecnts_0 &lt;= _bt_io_s1_cnt_0;</span></a>
+<a name="1203"><span class="lineNum">    1203 </span><span class="lineCov">       4126 :       s2_basecnts_1 &lt;= _bt_io_s1_cnt_1;</span></a>
+<a name="1204"><span class="lineNum">    1204 </span><span class="lineCov">       4126 :       allocatableSlots &lt;=</span></a>
+<a name="1205"><span class="lineNum">    1205 </span><span class="lineCov">       4126 :         {~_tables_3_io_resps_0_valid &amp; ~_tables_3_io_resps_0_bits_u,</span></a>
+<a name="1206"><span class="lineNum">    1206 </span><span class="lineCov">       4126 :          ~_tables_2_io_resps_0_valid &amp; ~_tables_2_io_resps_0_bits_u,</span></a>
+<a name="1207"><span class="lineNum">    1207 </span><span class="lineCov">       4126 :          ~_tables_1_io_resps_0_valid &amp; ~_tables_1_io_resps_0_bits_u,</span></a>
+<a name="1208"><span class="lineNum">    1208 </span><span class="lineCov">       4126 :          ~_tables_0_io_resps_0_valid &amp; ~_tables_0_io_resps_0_bits_u}</span></a>
+<a name="1209"><span class="lineNum">    1209 </span><span class="lineCov">       4126 :         &amp; ~({&amp;providerInfo_tableIdx,</span></a>
+<a name="1210"><span class="lineNum">    1210 </span><span class="lineCov">       4126 :              _GEN_45[2],</span></a>
+<a name="1211"><span class="lineNum">    1211 </span><span class="lineCov">       4126 :              _GEN_45[1] | (&amp;providerInfo_tableIdx),</span></a>
+<a name="1212"><span class="lineNum">    1212 </span><span class="lineCov">       4126 :              _GEN_45[0] | providerInfo_tableIdx == 2'h2 | (&amp;providerInfo_tableIdx)}</span></a>
+<a name="1213"><span class="lineNum">    1213 </span><span class="lineCov">       4126 :             &amp; {4{provided}});</span></a>
+<a name="1214"><span class="lineNum">    1214 </span><span class="lineCov">       4126 :       allocatableSlots_1 &lt;=</span></a>
+<a name="1215"><span class="lineNum">    1215 </span><span class="lineCov">       4126 :         {~_tables_3_io_resps_1_valid &amp; ~_tables_3_io_resps_1_bits_u,</span></a>
+<a name="1216"><span class="lineNum">    1216 </span><span class="lineCov">       4126 :          ~_tables_2_io_resps_1_valid &amp; ~_tables_2_io_resps_1_bits_u,</span></a>
+<a name="1217"><span class="lineNum">    1217 </span><span class="lineCov">       4126 :          ~_tables_1_io_resps_1_valid &amp; ~_tables_1_io_resps_1_bits_u,</span></a>
+<a name="1218"><span class="lineNum">    1218 </span><span class="lineCov">       4126 :          ~_tables_0_io_resps_1_valid &amp; ~_tables_0_io_resps_1_bits_u}</span></a>
+<a name="1219"><span class="lineNum">    1219 </span><span class="lineCov">       4126 :         &amp; ~({&amp;s1_providers_1,</span></a>
+<a name="1220"><span class="lineNum">    1220 </span><span class="lineCov">       4126 :              _GEN_46[2],</span></a>
+<a name="1221"><span class="lineNum">    1221 </span><span class="lineCov">       4126 :              _GEN_46[1] | (&amp;s1_providers_1),</span></a>
+<a name="1222"><span class="lineNum">    1222 </span><span class="lineCov">       4126 :              _GEN_46[0] | s1_providers_1 == 2'h2 | (&amp;s1_providers_1)} &amp; {4{provided_1}});</span></a>
+<a name="1223"><span class="lineNum">    1223 </span>            :     end</a>
+<a name="1224"><span class="lineNum">    1224 </span><span class="lineCov">       8252 :     if (io_s1_fire_0) begin</span></a>
+<a name="1225"><span class="lineNum">    1225 </span><span class="lineCov">       4126 :       s2_tageTakens_dup_0_0 &lt;= s1_tageTakens_0;</span></a>
+<a name="1226"><span class="lineNum">    1226 </span><span class="lineCov">       4126 :       s2_tageTakens_dup_0_1 &lt;= s1_tageTakens_1;</span></a>
+<a name="1227"><span class="lineNum">    1227 </span>            :     end</a>
+<a name="1228"><span class="lineNum">    1228 </span><span class="lineCov">       8252 :     if (io_s1_fire_2) begin</span></a>
+<a name="1229"><span class="lineNum">    1229 </span><span class="lineCov">       4126 :       s2_tageTakens_dup_2_0 &lt;= s1_tageTakens_0;</span></a>
+<a name="1230"><span class="lineNum">    1230 </span><span class="lineCov">       4126 :       s2_tageTakens_dup_2_1 &lt;= s1_tageTakens_1;</span></a>
+<a name="1231"><span class="lineNum">    1231 </span>            :     end</a>
+<a name="1232"><span class="lineNum">    1232 </span><span class="lineCov">       8252 :     if (io_s1_fire_3) begin</span></a>
+<a name="1233"><span class="lineNum">    1233 </span><span class="lineCov">       4126 :       s2_tageTakens_dup_3_0 &lt;= s1_tageTakens_0;</span></a>
+<a name="1234"><span class="lineNum">    1234 </span><span class="lineCov">       4126 :       s2_tageTakens_dup_3_1 &lt;= s1_tageTakens_1;</span></a>
+<a name="1235"><span class="lineNum">    1235 </span><span class="lineCov">       4126 :       s2_scTableSums_0 &lt;=</span></a>
+<a name="1236"><span class="lineNum">    1236 </span><span class="lineCov">       4126 :         9'({_s1_scTableSums_T_8[7], _s1_scTableSums_T_8}</span></a>
+<a name="1237"><span class="lineNum">    1237 </span><span class="lineCov">       4126 :            + {_s1_scTableSums_T_9[7], _s1_scTableSums_T_9});</span></a>
+<a name="1238"><span class="lineNum">    1238 </span><span class="lineCov">       4126 :       s2_scTableSums_1 &lt;=</span></a>
+<a name="1239"><span class="lineNum">    1239 </span><span class="lineCov">       4126 :         9'({_s1_scTableSums_T_19[7], _s1_scTableSums_T_19}</span></a>
+<a name="1240"><span class="lineNum">    1240 </span><span class="lineCov">       4126 :            + {_s1_scTableSums_T_20[7], _s1_scTableSums_T_20});</span></a>
+<a name="1241"><span class="lineNum">    1241 </span><span class="lineCov">       4126 :       s2_tagePrvdCtrCentered_r &lt;= providerInfo_resp_ctr;</span></a>
+<a name="1242"><span class="lineNum">    1242 </span><span class="lineCov">       4126 :       s2_scResps_r_0_ctrs_0_0 &lt;= _scTables_0_io_resp_ctrs_0_0;</span></a>
+<a name="1243"><span class="lineNum">    1243 </span><span class="lineCov">       4126 :       s2_scResps_r_0_ctrs_0_1 &lt;= _scTables_0_io_resp_ctrs_0_1;</span></a>
+<a name="1244"><span class="lineNum">    1244 </span><span class="lineCov">       4126 :       s2_scResps_r_1_ctrs_0_0 &lt;= _scTables_1_io_resp_ctrs_0_0;</span></a>
+<a name="1245"><span class="lineNum">    1245 </span><span class="lineCov">       4126 :       s2_scResps_r_1_ctrs_0_1 &lt;= _scTables_1_io_resp_ctrs_0_1;</span></a>
+<a name="1246"><span class="lineNum">    1246 </span><span class="lineCov">       4126 :       s2_scResps_r_2_ctrs_0_0 &lt;= _scTables_2_io_resp_ctrs_0_0;</span></a>
+<a name="1247"><span class="lineNum">    1247 </span><span class="lineCov">       4126 :       s2_scResps_r_2_ctrs_0_1 &lt;= _scTables_2_io_resp_ctrs_0_1;</span></a>
+<a name="1248"><span class="lineNum">    1248 </span><span class="lineCov">       4126 :       s2_scResps_r_3_ctrs_0_0 &lt;= _scTables_3_io_resp_ctrs_0_0;</span></a>
+<a name="1249"><span class="lineNum">    1249 </span><span class="lineCov">       4126 :       s2_scResps_r_3_ctrs_0_1 &lt;= _scTables_3_io_resp_ctrs_0_1;</span></a>
+<a name="1250"><span class="lineNum">    1250 </span><span class="lineCov">       4126 :       s2_scTableSums_1_0 &lt;=</span></a>
+<a name="1251"><span class="lineNum">    1251 </span><span class="lineCov">       4126 :         9'({_s1_scTableSums_T_30[7], _s1_scTableSums_T_30}</span></a>
+<a name="1252"><span class="lineNum">    1252 </span><span class="lineCov">       4126 :            + {_s1_scTableSums_T_31[7], _s1_scTableSums_T_31});</span></a>
+<a name="1253"><span class="lineNum">    1253 </span><span class="lineCov">       4126 :       s2_scTableSums_1_1 &lt;=</span></a>
+<a name="1254"><span class="lineNum">    1254 </span><span class="lineCov">       4126 :         9'({_s1_scTableSums_T_41[7], _s1_scTableSums_T_41}</span></a>
+<a name="1255"><span class="lineNum">    1255 </span><span class="lineCov">       4126 :            + {_s1_scTableSums_T_42[7], _s1_scTableSums_T_42});</span></a>
+<a name="1256"><span class="lineNum">    1256 </span><span class="lineCov">       4126 :       s2_tagePrvdCtrCentered_r_1 &lt;= s1_providerResps_1_ctr;</span></a>
+<a name="1257"><span class="lineNum">    1257 </span><span class="lineCov">       4126 :       s2_scResps_r_1_0_ctrs_1_0 &lt;= _scTables_0_io_resp_ctrs_1_0;</span></a>
+<a name="1258"><span class="lineNum">    1258 </span><span class="lineCov">       4126 :       s2_scResps_r_1_0_ctrs_1_1 &lt;= _scTables_0_io_resp_ctrs_1_1;</span></a>
+<a name="1259"><span class="lineNum">    1259 </span><span class="lineCov">       4126 :       s2_scResps_r_1_1_ctrs_1_0 &lt;= _scTables_1_io_resp_ctrs_1_0;</span></a>
+<a name="1260"><span class="lineNum">    1260 </span><span class="lineCov">       4126 :       s2_scResps_r_1_1_ctrs_1_1 &lt;= _scTables_1_io_resp_ctrs_1_1;</span></a>
+<a name="1261"><span class="lineNum">    1261 </span><span class="lineCov">       4126 :       s2_scResps_r_1_2_ctrs_1_0 &lt;= _scTables_2_io_resp_ctrs_1_0;</span></a>
+<a name="1262"><span class="lineNum">    1262 </span><span class="lineCov">       4126 :       s2_scResps_r_1_2_ctrs_1_1 &lt;= _scTables_2_io_resp_ctrs_1_1;</span></a>
+<a name="1263"><span class="lineNum">    1263 </span><span class="lineCov">       4126 :       s2_scResps_r_1_3_ctrs_1_0 &lt;= _scTables_3_io_resp_ctrs_1_0;</span></a>
+<a name="1264"><span class="lineNum">    1264 </span><span class="lineCov">       4126 :       s2_scResps_r_1_3_ctrs_1_1 &lt;= _scTables_3_io_resp_ctrs_1_1;</span></a>
+<a name="1265"><span class="lineNum">    1265 </span>            :     end</a>
+<a name="1266"><span class="lineNum">    1266 </span><span class="lineCov">       8150 :     if (io_s2_fire_1) begin</span></a>
+<a name="1267"><span class="lineNum">    1267 </span><span class="lineCov">       4075 :       resp_meta_providers_0_valid_r &lt;= s2_provideds_0;</span></a>
+<a name="1268"><span class="lineNum">    1268 </span><span class="lineCov">       4075 :       resp_meta_providers_0_bits_r &lt;= s2_providers_0;</span></a>
+<a name="1269"><span class="lineNum">    1269 </span><span class="lineCov">       4075 :       resp_meta_providerResps_0_r_ctr &lt;= s2_providerResps_0_ctr;</span></a>
+<a name="1270"><span class="lineNum">    1270 </span><span class="lineCov">       4075 :       resp_meta_providerResps_0_r_u &lt;= s2_providerResps_0_u;</span></a>
+<a name="1271"><span class="lineNum">    1271 </span><span class="lineCov">       4075 :       resp_meta_providerResps_0_r_unconf &lt;= s2_providerResps_0_unconf;</span></a>
+<a name="1272"><span class="lineNum">    1272 </span><span class="lineCov">       4075 :       resp_meta_allocates_0_r &lt;= allocatableSlots;</span></a>
+<a name="1273"><span class="lineNum">    1273 </span><span class="lineCov">       4075 :       resp_meta_altUsed_0_r &lt;= s2_altUsed_0;</span></a>
+<a name="1274"><span class="lineNum">    1274 </span><span class="lineCov">       4075 :       resp_meta_altDiffers_0_r &lt;= s2_finalAltPreds_0 != s2_providerResps_0_ctr[2];</span></a>
+<a name="1275"><span class="lineNum">    1275 </span><span class="lineCov">       4075 :       resp_meta_takens_0_r &lt;= s2_tageTakens_dup_0_0;</span></a>
+<a name="1276"><span class="lineNum">    1276 </span><span class="lineCov">       4075 :       resp_meta_basecnts_0_r &lt;= s2_basecnts_0;</span></a>
+<a name="1277"><span class="lineNum">    1277 </span><span class="lineCov">       4075 :       resp_meta_providers_1_valid_r &lt;= s2_provideds_1;</span></a>
+<a name="1278"><span class="lineNum">    1278 </span><span class="lineCov">       4075 :       resp_meta_providers_1_bits_r &lt;= s2_providers_1;</span></a>
+<a name="1279"><span class="lineNum">    1279 </span><span class="lineCov">       4075 :       resp_meta_providerResps_1_r_ctr &lt;= s2_providerResps_1_ctr;</span></a>
+<a name="1280"><span class="lineNum">    1280 </span><span class="lineCov">       4075 :       resp_meta_providerResps_1_r_u &lt;= s2_providerResps_1_u;</span></a>
+<a name="1281"><span class="lineNum">    1281 </span><span class="lineCov">       4075 :       resp_meta_providerResps_1_r_unconf &lt;= s2_providerResps_1_unconf;</span></a>
+<a name="1282"><span class="lineNum">    1282 </span><span class="lineCov">       4075 :       resp_meta_allocates_1_r &lt;= allocatableSlots_1;</span></a>
+<a name="1283"><span class="lineNum">    1283 </span><span class="lineCov">       4075 :       resp_meta_altUsed_1_r &lt;= s2_altUsed_1;</span></a>
+<a name="1284"><span class="lineNum">    1284 </span><span class="lineCov">       4075 :       resp_meta_altDiffers_1_r &lt;= s2_finalAltPreds_1 != s2_providerResps_1_ctr[2];</span></a>
+<a name="1285"><span class="lineNum">    1285 </span><span class="lineCov">       4075 :       resp_meta_takens_1_r &lt;= s2_tageTakens_dup_0_1;</span></a>
+<a name="1286"><span class="lineNum">    1286 </span><span class="lineCov">       4075 :       resp_meta_basecnts_1_r &lt;= s2_basecnts_1;</span></a>
+<a name="1287"><span class="lineNum">    1287 </span><span class="lineCov">       4075 :       s3_pred_dup_1 &lt;= s2_pred;</span></a>
+<a name="1288"><span class="lineNum">    1288 </span><span class="lineCov">       4075 :       s3_pred_dup_1_1 &lt;= s2_pred_1;</span></a>
+<a name="1289"><span class="lineNum">    1289 </span>            :     end</a>
+<a name="1290"><span class="lineNum">    1290 </span><span class="lineCov">      63847 :     tage_enable_dup_REG &lt;= io_ctrl_tage_enable;</span></a>
+<a name="1291"><span class="lineNum">    1291 </span><span class="lineCov">      63847 :     tage_enable_dup_REG_1 &lt;= io_ctrl_tage_enable;</span></a>
+<a name="1292"><span class="lineNum">    1292 </span><span class="lineCov">      63847 :     tables_0_io_update_reset_u_0_REG &lt;= updateResetU_0;</span></a>
+<a name="1293"><span class="lineNum">    1293 </span><span class="lineCov">      63847 :     tables_0_io_update_mask_0_REG &lt;= updateMask_0_0;</span></a>
+<a name="1294"><span class="lineNum">    1294 </span><span class="lineCov">          2 :     if (updateMask_0_0 | updateMask_1_0) begin</span></a>
+<a name="1295"><span class="lineNum">    1295 </span><span class="lineCov">          1 :       tables_0_io_update_takens_0_r &lt;= updateTaken;</span></a>
+<a name="1296"><span class="lineNum">    1296 </span><span class="lineCov">          1 :       tables_0_io_update_alloc_0_r &lt;= _GEN_14 &amp; _GEN_7;</span></a>
+<a name="1297"><span class="lineNum">    1297 </span><span class="lineCov">          1 :       tables_0_io_update_oldCtrs_0_r &lt;= io_update_bits_meta[76:74];</span></a>
+<a name="1298"><span class="lineNum">    1298 </span><span class="lineCov">          1 :       tables_0_io_update_uMask_0_r &lt;=</span></a>
+<a name="1299"><span class="lineNum">    1299 </span><span class="lineCov">          1 :         _GEN_8 | updateValids_0 &amp; io_update_bits_meta[84] &amp; _GEN_3</span></a>
+<a name="1300"><span class="lineNum">    1300 </span><span class="lineCov">          1 :         &amp; io_update_bits_meta[68];</span></a>
+<a name="1301"><span class="lineNum">    1301 </span><span class="lineCov">          1 :       tables_0_io_update_us_0_r &lt;= ~_GEN_8 &amp; updateProviderCorrect;</span></a>
+<a name="1302"><span class="lineNum">    1302 </span><span class="lineCov">          1 :       tables_0_io_update_takens_1_r &lt;= updateTaken_1;</span></a>
+<a name="1303"><span class="lineNum">    1303 </span><span class="lineCov">          1 :       tables_0_io_update_alloc_1_r &lt;= _GEN_26 &amp; _GEN_19;</span></a>
+<a name="1304"><span class="lineNum">    1304 </span><span class="lineCov">          1 :       tables_0_io_update_oldCtrs_1_r &lt;= io_update_bits_meta[81:79];</span></a>
+<a name="1305"><span class="lineNum">    1305 </span><span class="lineCov">          1 :       tables_0_io_update_uMask_1_r &lt;=</span></a>
+<a name="1306"><span class="lineNum">    1306 </span><span class="lineCov">          1 :         _GEN_20 | updateValids_1 &amp; io_update_bits_meta[87] &amp; _GEN_15</span></a>
+<a name="1307"><span class="lineNum">    1307 </span><span class="lineCov">          1 :         &amp; io_update_bits_meta[69];</span></a>
+<a name="1308"><span class="lineNum">    1308 </span><span class="lineCov">          1 :       tables_0_io_update_us_1_r &lt;= ~_GEN_20 &amp; updateProviderCorrect_1;</span></a>
+<a name="1309"><span class="lineNum">    1309 </span><span class="lineCov">          1 :       tables_0_io_update_pc_r_1 &lt;= io_update_bits_pc;</span></a>
+<a name="1310"><span class="lineNum">    1310 </span><span class="lineCov">          1 :       tables_0_io_update_folded_hist_r_1_hist_14_folded_hist &lt;=</span></a>
+<a name="1311"><span class="lineNum">    1311 </span><span class="lineCov">          1 :         io_update_bits_spec_info_folded_hist_hist_14_folded_hist;</span></a>
+<a name="1312"><span class="lineNum">    1312 </span><span class="lineCov">          1 :       tables_0_io_update_folded_hist_r_1_hist_7_folded_hist &lt;=</span></a>
+<a name="1313"><span class="lineNum">    1313 </span><span class="lineCov">          1 :         io_update_bits_spec_info_folded_hist_hist_7_folded_hist;</span></a>
+<a name="1314"><span class="lineNum">    1314 </span>            :     end</a>
+<a name="1315"><span class="lineNum">    1315 </span><span class="lineCov">      63847 :     tables_1_io_update_reset_u_0_REG &lt;= updateResetU_0;</span></a>
+<a name="1316"><span class="lineNum">    1316 </span><span class="lineCov">      63847 :     tables_1_io_update_mask_0_REG &lt;= updateMask_0_1;</span></a>
+<a name="1317"><span class="lineNum">    1317 </span><span class="lineNoCov">          0 :     if (updateMask_0_1 | updateMask_1_1) begin</span></a>
+<a name="1318"><span class="lineNum">    1318 </span><span class="lineNoCov">          0 :       tables_1_io_update_takens_0_r &lt;= updateTaken;</span></a>
+<a name="1319"><span class="lineNum">    1319 </span><span class="lineNoCov">          0 :       tables_1_io_update_alloc_0_r &lt;= _GEN_14 &amp; _GEN_9;</span></a>
+<a name="1320"><span class="lineNum">    1320 </span><span class="lineNoCov">          0 :       tables_1_io_update_oldCtrs_0_r &lt;= io_update_bits_meta[76:74];</span></a>
+<a name="1321"><span class="lineNum">    1321 </span><span class="lineNoCov">          0 :       tables_1_io_update_uMask_0_r &lt;=</span></a>
+<a name="1322"><span class="lineNum">    1322 </span><span class="lineNoCov">          0 :         _GEN_10 | updateValids_0 &amp; io_update_bits_meta[84] &amp; _GEN_5</span></a>
+<a name="1323"><span class="lineNum">    1323 </span><span class="lineNoCov">          0 :         &amp; io_update_bits_meta[68];</span></a>
+<a name="1324"><span class="lineNum">    1324 </span><span class="lineNoCov">          0 :       tables_1_io_update_us_0_r &lt;= ~_GEN_10 &amp; updateProviderCorrect;</span></a>
+<a name="1325"><span class="lineNum">    1325 </span><span class="lineNoCov">          0 :       tables_1_io_update_takens_1_r &lt;= updateTaken_1;</span></a>
+<a name="1326"><span class="lineNum">    1326 </span><span class="lineNoCov">          0 :       tables_1_io_update_alloc_1_r &lt;= _GEN_26 &amp; _GEN_21;</span></a>
+<a name="1327"><span class="lineNum">    1327 </span><span class="lineNoCov">          0 :       tables_1_io_update_oldCtrs_1_r &lt;= io_update_bits_meta[81:79];</span></a>
+<a name="1328"><span class="lineNum">    1328 </span><span class="lineNoCov">          0 :       tables_1_io_update_uMask_1_r &lt;=</span></a>
+<a name="1329"><span class="lineNum">    1329 </span><span class="lineNoCov">          0 :         _GEN_22 | updateValids_1 &amp; io_update_bits_meta[87] &amp; _GEN_17</span></a>
+<a name="1330"><span class="lineNum">    1330 </span><span class="lineNoCov">          0 :         &amp; io_update_bits_meta[69];</span></a>
+<a name="1331"><span class="lineNum">    1331 </span><span class="lineNoCov">          0 :       tables_1_io_update_us_1_r &lt;= ~_GEN_22 &amp; updateProviderCorrect_1;</span></a>
+<a name="1332"><span class="lineNum">    1332 </span><span class="lineNoCov">          0 :       tables_1_io_update_pc_r_1 &lt;= io_update_bits_pc;</span></a>
+<a name="1333"><span class="lineNum">    1333 </span><span class="lineNoCov">          0 :       tables_1_io_update_folded_hist_r_1_hist_15_folded_hist &lt;=</span></a>
+<a name="1334"><span class="lineNum">    1334 </span><span class="lineNoCov">          0 :         io_update_bits_spec_info_folded_hist_hist_15_folded_hist;</span></a>
+<a name="1335"><span class="lineNum">    1335 </span><span class="lineNoCov">          0 :       tables_1_io_update_folded_hist_r_1_hist_4_folded_hist &lt;=</span></a>
+<a name="1336"><span class="lineNum">    1336 </span><span class="lineNoCov">          0 :         io_update_bits_spec_info_folded_hist_hist_4_folded_hist;</span></a>
+<a name="1337"><span class="lineNum">    1337 </span><span class="lineNoCov">          0 :       tables_1_io_update_folded_hist_r_1_hist_1_folded_hist &lt;=</span></a>
+<a name="1338"><span class="lineNum">    1338 </span><span class="lineNoCov">          0 :         io_update_bits_spec_info_folded_hist_hist_1_folded_hist;</span></a>
+<a name="1339"><span class="lineNum">    1339 </span>            :     end</a>
+<a name="1340"><span class="lineNum">    1340 </span><span class="lineCov">      63847 :     tables_2_io_update_reset_u_0_REG &lt;= updateResetU_0;</span></a>
+<a name="1341"><span class="lineNum">    1341 </span><span class="lineCov">      63847 :     tables_2_io_update_mask_0_REG &lt;= updateMask_0_2;</span></a>
+<a name="1342"><span class="lineNum">    1342 </span><span class="lineCov">          4 :     if (updateMask_0_2 | updateMask_1_2) begin</span></a>
+<a name="1343"><span class="lineNum">    1343 </span><span class="lineCov">          2 :       tables_2_io_update_takens_0_r &lt;= updateTaken;</span></a>
+<a name="1344"><span class="lineNum">    1344 </span><span class="lineCov">          2 :       tables_2_io_update_alloc_0_r &lt;= _GEN_14 &amp; _GEN_11;</span></a>
+<a name="1345"><span class="lineNum">    1345 </span><span class="lineCov">          2 :       tables_2_io_update_oldCtrs_0_r &lt;= io_update_bits_meta[76:74];</span></a>
+<a name="1346"><span class="lineNum">    1346 </span><span class="lineCov">          2 :       tables_2_io_update_uMask_0_r &lt;=</span></a>
+<a name="1347"><span class="lineNum">    1347 </span><span class="lineCov">          2 :         _GEN_12 | updateValids_0 &amp; io_update_bits_meta[84] &amp; _GEN_6</span></a>
+<a name="1348"><span class="lineNum">    1348 </span><span class="lineCov">          2 :         &amp; io_update_bits_meta[68];</span></a>
+<a name="1349"><span class="lineNum">    1349 </span><span class="lineCov">          2 :       tables_2_io_update_us_0_r &lt;= ~_GEN_12 &amp; updateProviderCorrect;</span></a>
+<a name="1350"><span class="lineNum">    1350 </span><span class="lineCov">          2 :       tables_2_io_update_takens_1_r &lt;= updateTaken_1;</span></a>
+<a name="1351"><span class="lineNum">    1351 </span><span class="lineCov">          2 :       tables_2_io_update_alloc_1_r &lt;= _GEN_26 &amp; _GEN_23;</span></a>
+<a name="1352"><span class="lineNum">    1352 </span><span class="lineCov">          2 :       tables_2_io_update_oldCtrs_1_r &lt;= io_update_bits_meta[81:79];</span></a>
+<a name="1353"><span class="lineNum">    1353 </span><span class="lineCov">          2 :       tables_2_io_update_uMask_1_r &lt;=</span></a>
+<a name="1354"><span class="lineNum">    1354 </span><span class="lineCov">          2 :         _GEN_24 | updateValids_1 &amp; io_update_bits_meta[87] &amp; _GEN_18</span></a>
+<a name="1355"><span class="lineNum">    1355 </span><span class="lineCov">          2 :         &amp; io_update_bits_meta[69];</span></a>
+<a name="1356"><span class="lineNum">    1356 </span><span class="lineCov">          2 :       tables_2_io_update_us_1_r &lt;= ~_GEN_24 &amp; updateProviderCorrect_1;</span></a>
+<a name="1357"><span class="lineNum">    1357 </span><span class="lineCov">          2 :       tables_2_io_update_pc_r_1 &lt;= io_update_bits_pc;</span></a>
+<a name="1358"><span class="lineNum">    1358 </span><span class="lineCov">          2 :       tables_2_io_update_folded_hist_r_1_hist_17_folded_hist &lt;=</span></a>
+<a name="1359"><span class="lineNum">    1359 </span><span class="lineCov">          2 :         io_update_bits_spec_info_folded_hist_hist_17_folded_hist;</span></a>
+<a name="1360"><span class="lineNum">    1360 </span><span class="lineCov">          2 :       tables_2_io_update_folded_hist_r_1_hist_9_folded_hist &lt;=</span></a>
+<a name="1361"><span class="lineNum">    1361 </span><span class="lineCov">          2 :         io_update_bits_spec_info_folded_hist_hist_9_folded_hist;</span></a>
+<a name="1362"><span class="lineNum">    1362 </span><span class="lineCov">          2 :       tables_2_io_update_folded_hist_r_1_hist_3_folded_hist &lt;=</span></a>
+<a name="1363"><span class="lineNum">    1363 </span><span class="lineCov">          2 :         io_update_bits_spec_info_folded_hist_hist_3_folded_hist;</span></a>
+<a name="1364"><span class="lineNum">    1364 </span>            :     end</a>
+<a name="1365"><span class="lineNum">    1365 </span><span class="lineCov">      63847 :     tables_3_io_update_reset_u_0_REG &lt;= updateResetU_0;</span></a>
+<a name="1366"><span class="lineNum">    1366 </span><span class="lineCov">      63847 :     tables_3_io_update_mask_0_REG &lt;= updateMask_0_3;</span></a>
+<a name="1367"><span class="lineNum">    1367 </span><span class="lineCov">          4 :     if (updateMask_0_3 | updateMask_1_3) begin</span></a>
+<a name="1368"><span class="lineNum">    1368 </span><span class="lineCov">          2 :       tables_3_io_update_takens_0_r &lt;= updateTaken;</span></a>
+<a name="1369"><span class="lineNum">    1369 </span><span class="lineCov">          2 :       tables_3_io_update_alloc_0_r &lt;= _GEN_14 &amp; (&amp;allocate);</span></a>
+<a name="1370"><span class="lineNum">    1370 </span><span class="lineCov">          2 :       tables_3_io_update_oldCtrs_0_r &lt;= io_update_bits_meta[76:74];</span></a>
+<a name="1371"><span class="lineNum">    1371 </span><span class="lineCov">          2 :       tables_3_io_update_uMask_0_r &lt;=</span></a>
+<a name="1372"><span class="lineNum">    1372 </span><span class="lineCov">          2 :         _GEN_13 | updateValids_0 &amp; io_update_bits_meta[84]</span></a>
+<a name="1373"><span class="lineNum">    1373 </span><span class="lineCov">          2 :         &amp; (&amp;(io_update_bits_meta[83:82])) &amp; io_update_bits_meta[68];</span></a>
+<a name="1374"><span class="lineNum">    1374 </span><span class="lineCov">          2 :       tables_3_io_update_us_0_r &lt;= ~_GEN_13 &amp; updateProviderCorrect;</span></a>
+<a name="1375"><span class="lineNum">    1375 </span><span class="lineCov">          2 :       tables_3_io_update_takens_1_r &lt;= updateTaken_1;</span></a>
+<a name="1376"><span class="lineNum">    1376 </span><span class="lineCov">          2 :       tables_3_io_update_alloc_1_r &lt;= _GEN_26 &amp; (&amp;allocate_1);</span></a>
+<a name="1377"><span class="lineNum">    1377 </span><span class="lineCov">          2 :       tables_3_io_update_oldCtrs_1_r &lt;= io_update_bits_meta[81:79];</span></a>
+<a name="1378"><span class="lineNum">    1378 </span><span class="lineCov">          2 :       tables_3_io_update_uMask_1_r &lt;=</span></a>
+<a name="1379"><span class="lineNum">    1379 </span><span class="lineCov">          2 :         _GEN_25 | updateValids_1 &amp; io_update_bits_meta[87]</span></a>
+<a name="1380"><span class="lineNum">    1380 </span><span class="lineCov">          2 :         &amp; (&amp;(io_update_bits_meta[86:85])) &amp; io_update_bits_meta[69];</span></a>
+<a name="1381"><span class="lineNum">    1381 </span><span class="lineCov">          2 :       tables_3_io_update_us_1_r &lt;= ~_GEN_25 &amp; updateProviderCorrect_1;</span></a>
+<a name="1382"><span class="lineNum">    1382 </span><span class="lineCov">          2 :       tables_3_io_update_pc_r_1 &lt;= io_update_bits_pc;</span></a>
+<a name="1383"><span class="lineNum">    1383 </span><span class="lineCov">          2 :       tables_3_io_update_folded_hist_r_1_hist_16_folded_hist &lt;=</span></a>
+<a name="1384"><span class="lineNum">    1384 </span><span class="lineCov">          2 :         io_update_bits_spec_info_folded_hist_hist_16_folded_hist;</span></a>
+<a name="1385"><span class="lineNum">    1385 </span><span class="lineCov">          2 :       tables_3_io_update_folded_hist_r_1_hist_8_folded_hist &lt;=</span></a>
+<a name="1386"><span class="lineNum">    1386 </span><span class="lineCov">          2 :         io_update_bits_spec_info_folded_hist_hist_8_folded_hist;</span></a>
+<a name="1387"><span class="lineNum">    1387 </span><span class="lineCov">          2 :       tables_3_io_update_folded_hist_r_1_hist_5_folded_hist &lt;=</span></a>
+<a name="1388"><span class="lineNum">    1388 </span><span class="lineCov">          2 :         io_update_bits_spec_info_folded_hist_hist_5_folded_hist;</span></a>
+<a name="1389"><span class="lineNum">    1389 </span>            :     end</a>
+<a name="1390"><span class="lineNum">    1390 </span><span class="lineCov">      63847 :     tables_0_io_update_reset_u_1_REG &lt;= updateResetU_1;</span></a>
+<a name="1391"><span class="lineNum">    1391 </span><span class="lineCov">      63847 :     tables_0_io_update_mask_1_REG &lt;= updateMask_1_0;</span></a>
+<a name="1392"><span class="lineNum">    1392 </span><span class="lineCov">      63847 :     tables_1_io_update_reset_u_1_REG &lt;= updateResetU_1;</span></a>
+<a name="1393"><span class="lineNum">    1393 </span><span class="lineCov">      63847 :     tables_1_io_update_mask_1_REG &lt;= updateMask_1_1;</span></a>
+<a name="1394"><span class="lineNum">    1394 </span><span class="lineCov">      63847 :     tables_2_io_update_reset_u_1_REG &lt;= updateResetU_1;</span></a>
+<a name="1395"><span class="lineNum">    1395 </span><span class="lineCov">      63847 :     tables_2_io_update_mask_1_REG &lt;= updateMask_1_2;</span></a>
+<a name="1396"><span class="lineNum">    1396 </span><span class="lineCov">      63847 :     tables_3_io_update_reset_u_1_REG &lt;= updateResetU_1;</span></a>
+<a name="1397"><span class="lineNum">    1397 </span><span class="lineCov">      63847 :     tables_3_io_update_mask_1_REG &lt;= updateMask_1_3;</span></a>
+<a name="1398"><span class="lineNum">    1398 </span><span class="lineCov">      63847 :     REG_2_0 &lt;= baseupdate_0;</span></a>
+<a name="1399"><span class="lineNum">    1399 </span><span class="lineCov">      63847 :     REG_2_1 &lt;= baseupdate_1;</span></a>
+<a name="1400"><span class="lineNum">    1400 </span><span class="lineCov">          6 :     if (baseupdate_0 | baseupdate_1) begin</span></a>
+<a name="1401"><span class="lineNum">    1401 </span><span class="lineCov">          3 :       r_0 &lt;= io_update_bits_meta[65:64];</span></a>
+<a name="1402"><span class="lineNum">    1402 </span><span class="lineCov">          3 :       r_1 &lt;= io_update_bits_meta[67:66];</span></a>
+<a name="1403"><span class="lineNum">    1403 </span><span class="lineCov">          3 :       bt_io_update_pc_r &lt;= io_update_bits_pc;</span></a>
+<a name="1404"><span class="lineNum">    1404 </span><span class="lineCov">          3 :       r_1_0 &lt;= updateTaken;</span></a>
+<a name="1405"><span class="lineNum">    1405 </span><span class="lineCov">          3 :       r_1_1 &lt;= updateTaken_1;</span></a>
+<a name="1406"><span class="lineNum">    1406 </span>            :     end</a>
+<a name="1407"><span class="lineNum">    1407 </span><span class="lineCov">       8150 :     if (io_s2_fire_3) begin</span></a>
+<a name="1408"><span class="lineNum">    1408 </span><span class="lineCov">       4075 :       resp_meta_scMeta_tageTakens_0_r &lt;= s2_tageTakens_dup_3_0;</span></a>
+<a name="1409"><span class="lineNum">    1409 </span><span class="lineCov">       4075 :       resp_meta_scMeta_scUsed_0_r &lt;= s2_provideds_0;</span></a>
+<a name="1410"><span class="lineNum">    1410 </span><span class="lineCov">       4075 :       resp_meta_scMeta_scPreds_0_r &lt;= _GEN_30;</span></a>
+<a name="1411"><span class="lineNum">    1411 </span><span class="lineCov">       4075 :       r_2_0 &lt;= s2_tageTakens_dup_3_0 ? s2_scResps_r_0_ctrs_0_1 : s2_scResps_r_0_ctrs_0_0;</span></a>
+<a name="1412"><span class="lineNum">    1412 </span><span class="lineCov">       4075 :       r_2_1 &lt;= s2_tageTakens_dup_3_0 ? s2_scResps_r_1_ctrs_0_1 : s2_scResps_r_1_ctrs_0_0;</span></a>
+<a name="1413"><span class="lineNum">    1413 </span><span class="lineCov">       4075 :       r_2_2 &lt;= s2_tageTakens_dup_3_0 ? s2_scResps_r_2_ctrs_0_1 : s2_scResps_r_2_ctrs_0_0;</span></a>
+<a name="1414"><span class="lineNum">    1414 </span><span class="lineCov">       4075 :       r_2_3 &lt;= s2_tageTakens_dup_3_0 ? s2_scResps_r_3_ctrs_0_1 : s2_scResps_r_3_ctrs_0_0;</span></a>
+<a name="1415"><span class="lineNum">    1415 </span><span class="lineCov">       4075 :       s3_pred_dup_3 &lt;= s2_pred;</span></a>
+<a name="1416"><span class="lineNum">    1416 </span><span class="lineCov">       4075 :       resp_meta_scMeta_tageTakens_1_r &lt;= s2_tageTakens_dup_3_1;</span></a>
+<a name="1417"><span class="lineNum">    1417 </span><span class="lineCov">       4075 :       resp_meta_scMeta_scUsed_1_r &lt;= s2_provideds_1;</span></a>
+<a name="1418"><span class="lineNum">    1418 </span><span class="lineCov">       4075 :       resp_meta_scMeta_scPreds_1_r &lt;= _GEN_39;</span></a>
+<a name="1419"><span class="lineNum">    1419 </span><span class="lineCov">       4075 :       r_3_0 &lt;=</span></a>
+<a name="1420"><span class="lineNum">    1420 </span><span class="lineCov">       4075 :         s2_tageTakens_dup_3_1 ? s2_scResps_r_1_0_ctrs_1_1 : s2_scResps_r_1_0_ctrs_1_0;</span></a>
+<a name="1421"><span class="lineNum">    1421 </span><span class="lineCov">       4075 :       r_3_1 &lt;=</span></a>
+<a name="1422"><span class="lineNum">    1422 </span><span class="lineCov">       4075 :         s2_tageTakens_dup_3_1 ? s2_scResps_r_1_1_ctrs_1_1 : s2_scResps_r_1_1_ctrs_1_0;</span></a>
+<a name="1423"><span class="lineNum">    1423 </span><span class="lineCov">       4075 :       r_3_2 &lt;=</span></a>
+<a name="1424"><span class="lineNum">    1424 </span><span class="lineCov">       4075 :         s2_tageTakens_dup_3_1 ? s2_scResps_r_1_2_ctrs_1_1 : s2_scResps_r_1_2_ctrs_1_0;</span></a>
+<a name="1425"><span class="lineNum">    1425 </span><span class="lineCov">       4075 :       r_3_3 &lt;=</span></a>
+<a name="1426"><span class="lineNum">    1426 </span><span class="lineCov">       4075 :         s2_tageTakens_dup_3_1 ? s2_scResps_r_1_3_ctrs_1_1 : s2_scResps_r_1_3_ctrs_1_0;</span></a>
+<a name="1427"><span class="lineNum">    1427 </span><span class="lineCov">       4075 :       s3_pred_dup_3_1 &lt;= s2_pred_1;</span></a>
+<a name="1428"><span class="lineNum">    1428 </span>            :     end</a>
+<a name="1429"><span class="lineNum">    1429 </span><span class="lineCov">       8150 :     if (io_s2_fire_0) begin</span></a>
+<a name="1430"><span class="lineNum">    1430 </span><span class="lineCov">       4075 :       s3_pred_dup_0 &lt;= s2_pred;</span></a>
+<a name="1431"><span class="lineNum">    1431 </span><span class="lineCov">       4075 :       s3_pred_dup_0_1 &lt;= s2_pred_1;</span></a>
+<a name="1432"><span class="lineNum">    1432 </span>            :     end</a>
+<a name="1433"><span class="lineNum">    1433 </span><span class="lineCov">       8150 :     if (io_s2_fire_2) begin</span></a>
+<a name="1434"><span class="lineNum">    1434 </span><span class="lineCov">       4075 :       s3_pred_dup_2 &lt;= s2_pred;</span></a>
+<a name="1435"><span class="lineNum">    1435 </span><span class="lineCov">       4075 :       s3_pred_dup_2_1 &lt;= s2_pred_1;</span></a>
+<a name="1436"><span class="lineNum">    1436 </span>            :     end</a>
+<a name="1437"><span class="lineNum">    1437 </span><span class="lineCov">      63847 :     sc_enable_dup_REG &lt;= io_ctrl_sc_enable;</span></a>
+<a name="1438"><span class="lineNum">    1438 </span><span class="lineCov">      63847 :     sc_enable_dup_REG_1 &lt;= io_ctrl_sc_enable;</span></a>
+<a name="1439"><span class="lineNum">    1439 </span><span class="lineCov">      63847 :     scTables_0_io_update_mask_0_REG &lt;= scUpdateMask_0_3;</span></a>
+<a name="1440"><span class="lineNum">    1440 </span><span class="lineCov">          4 :     if (scUpdateMask_0_3 | scUpdateMask_1_3) begin</span></a>
+<a name="1441"><span class="lineNum">    1441 </span><span class="lineCov">          2 :       scTables_0_io_update_tagePreds_0_r &lt;= io_update_bits_meta[52];</span></a>
+<a name="1442"><span class="lineNum">    1442 </span><span class="lineCov">          2 :       scTables_0_io_update_takens_0_r &lt;= io_update_bits_br_taken_mask_0;</span></a>
+<a name="1443"><span class="lineNum">    1443 </span><span class="lineCov">          2 :       scTables_0_io_update_oldCtrs_0_r &lt;= io_update_bits_meta[5:0];</span></a>
+<a name="1444"><span class="lineNum">    1444 </span><span class="lineCov">          2 :       scTables_0_io_update_tagePreds_1_r &lt;= io_update_bits_meta[53];</span></a>
+<a name="1445"><span class="lineNum">    1445 </span><span class="lineCov">          2 :       scTables_0_io_update_takens_1_r &lt;= io_update_bits_br_taken_mask_1;</span></a>
+<a name="1446"><span class="lineNum">    1446 </span><span class="lineCov">          2 :       scTables_0_io_update_oldCtrs_1_r &lt;= io_update_bits_meta[29:24];</span></a>
+<a name="1447"><span class="lineNum">    1447 </span><span class="lineCov">          2 :       scTables_0_io_update_pc_r_1 &lt;= io_update_bits_pc;</span></a>
+<a name="1448"><span class="lineNum">    1448 </span>            :     end</a>
+<a name="1449"><span class="lineNum">    1449 </span><span class="lineCov">      63847 :     scTables_1_io_update_mask_0_REG &lt;= scUpdateMask_0_3;</span></a>
+<a name="1450"><span class="lineNum">    1450 </span><span class="lineCov">          4 :     if (scUpdateMask_0_3 | scUpdateMask_1_3) begin</span></a>
+<a name="1451"><span class="lineNum">    1451 </span><span class="lineCov">          2 :       scTables_1_io_update_tagePreds_0_r &lt;= io_update_bits_meta[52];</span></a>
+<a name="1452"><span class="lineNum">    1452 </span><span class="lineCov">          2 :       scTables_1_io_update_takens_0_r &lt;= io_update_bits_br_taken_mask_0;</span></a>
+<a name="1453"><span class="lineNum">    1453 </span><span class="lineCov">          2 :       scTables_1_io_update_oldCtrs_0_r &lt;= io_update_bits_meta[11:6];</span></a>
+<a name="1454"><span class="lineNum">    1454 </span><span class="lineCov">          2 :       scTables_1_io_update_tagePreds_1_r &lt;= io_update_bits_meta[53];</span></a>
+<a name="1455"><span class="lineNum">    1455 </span><span class="lineCov">          2 :       scTables_1_io_update_takens_1_r &lt;= io_update_bits_br_taken_mask_1;</span></a>
+<a name="1456"><span class="lineNum">    1456 </span><span class="lineCov">          2 :       scTables_1_io_update_oldCtrs_1_r &lt;= io_update_bits_meta[35:30];</span></a>
+<a name="1457"><span class="lineNum">    1457 </span><span class="lineCov">          2 :       scTables_1_io_update_pc_r_1 &lt;= io_update_bits_pc;</span></a>
+<a name="1458"><span class="lineNum">    1458 </span><span class="lineCov">          2 :       scTables_1_io_update_folded_hist_r_1_hist_12_folded_hist &lt;=</span></a>
+<a name="1459"><span class="lineNum">    1459 </span><span class="lineCov">          2 :         io_update_bits_spec_info_folded_hist_hist_12_folded_hist;</span></a>
+<a name="1460"><span class="lineNum">    1460 </span>            :     end</a>
+<a name="1461"><span class="lineNum">    1461 </span><span class="lineCov">      63847 :     scTables_2_io_update_mask_0_REG &lt;= scUpdateMask_0_3;</span></a>
+<a name="1462"><span class="lineNum">    1462 </span><span class="lineCov">          4 :     if (scUpdateMask_0_3 | scUpdateMask_1_3) begin</span></a>
+<a name="1463"><span class="lineNum">    1463 </span><span class="lineCov">          2 :       scTables_2_io_update_tagePreds_0_r &lt;= io_update_bits_meta[52];</span></a>
+<a name="1464"><span class="lineNum">    1464 </span><span class="lineCov">          2 :       scTables_2_io_update_takens_0_r &lt;= io_update_bits_br_taken_mask_0;</span></a>
+<a name="1465"><span class="lineNum">    1465 </span><span class="lineCov">          2 :       scTables_2_io_update_oldCtrs_0_r &lt;= io_update_bits_meta[17:12];</span></a>
+<a name="1466"><span class="lineNum">    1466 </span><span class="lineCov">          2 :       scTables_2_io_update_tagePreds_1_r &lt;= io_update_bits_meta[53];</span></a>
+<a name="1467"><span class="lineNum">    1467 </span><span class="lineCov">          2 :       scTables_2_io_update_takens_1_r &lt;= io_update_bits_br_taken_mask_1;</span></a>
+<a name="1468"><span class="lineNum">    1468 </span><span class="lineCov">          2 :       scTables_2_io_update_oldCtrs_1_r &lt;= io_update_bits_meta[41:36];</span></a>
+<a name="1469"><span class="lineNum">    1469 </span><span class="lineCov">          2 :       scTables_2_io_update_pc_r_1 &lt;= io_update_bits_pc;</span></a>
+<a name="1470"><span class="lineNum">    1470 </span><span class="lineCov">          2 :       scTables_2_io_update_folded_hist_r_1_hist_11_folded_hist &lt;=</span></a>
+<a name="1471"><span class="lineNum">    1471 </span><span class="lineCov">          2 :         io_update_bits_spec_info_folded_hist_hist_11_folded_hist;</span></a>
+<a name="1472"><span class="lineNum">    1472 </span>            :     end</a>
+<a name="1473"><span class="lineNum">    1473 </span><span class="lineCov">      63847 :     scTables_3_io_update_mask_0_REG &lt;= scUpdateMask_0_3;</span></a>
+<a name="1474"><span class="lineNum">    1474 </span><span class="lineCov">          4 :     if (scUpdateMask_0_3 | scUpdateMask_1_3) begin</span></a>
+<a name="1475"><span class="lineNum">    1475 </span><span class="lineCov">          2 :       scTables_3_io_update_tagePreds_0_r &lt;= io_update_bits_meta[52];</span></a>
+<a name="1476"><span class="lineNum">    1476 </span><span class="lineCov">          2 :       scTables_3_io_update_takens_0_r &lt;= io_update_bits_br_taken_mask_0;</span></a>
+<a name="1477"><span class="lineNum">    1477 </span><span class="lineCov">          2 :       scTables_3_io_update_oldCtrs_0_r &lt;= io_update_bits_meta[23:18];</span></a>
+<a name="1478"><span class="lineNum">    1478 </span><span class="lineCov">          2 :       scTables_3_io_update_tagePreds_1_r &lt;= io_update_bits_meta[53];</span></a>
+<a name="1479"><span class="lineNum">    1479 </span><span class="lineCov">          2 :       scTables_3_io_update_takens_1_r &lt;= io_update_bits_br_taken_mask_1;</span></a>
+<a name="1480"><span class="lineNum">    1480 </span><span class="lineCov">          2 :       scTables_3_io_update_oldCtrs_1_r &lt;= io_update_bits_meta[47:42];</span></a>
+<a name="1481"><span class="lineNum">    1481 </span><span class="lineCov">          2 :       scTables_3_io_update_pc_r_1 &lt;= io_update_bits_pc;</span></a>
+<a name="1482"><span class="lineNum">    1482 </span><span class="lineCov">          2 :       scTables_3_io_update_folded_hist_r_1_hist_2_folded_hist &lt;=</span></a>
+<a name="1483"><span class="lineNum">    1483 </span><span class="lineCov">          2 :         io_update_bits_spec_info_folded_hist_hist_2_folded_hist;</span></a>
+<a name="1484"><span class="lineNum">    1484 </span>            :     end</a>
+<a name="1485"><span class="lineNum">    1485 </span><span class="lineCov">      63847 :     scTables_0_io_update_mask_1_REG &lt;= scUpdateMask_1_3;</span></a>
+<a name="1486"><span class="lineNum">    1486 </span><span class="lineCov">      63847 :     scTables_1_io_update_mask_1_REG &lt;= scUpdateMask_1_3;</span></a>
+<a name="1487"><span class="lineNum">    1487 </span><span class="lineCov">      63847 :     scTables_2_io_update_mask_1_REG &lt;= scUpdateMask_1_3;</span></a>
+<a name="1488"><span class="lineNum">    1488 </span><span class="lineCov">      63847 :     scTables_3_io_update_mask_1_REG &lt;= scUpdateMask_1_3;</span></a>
+<a name="1489"><span class="lineNum">    1489 </span><span class="lineCov">      63847 :     io_perf_0_value_REG &lt;=</span></a>
+<a name="1490"><span class="lineNum">    1490 </span><span class="lineCov">      63847 :       2'({1'h0, io_update_bits_meta[84]} + {1'h0, io_update_bits_meta[87]});</span></a>
+<a name="1491"><span class="lineNum">    1491 </span><span class="lineCov">      63847 :     io_perf_0_value_REG_1 &lt;= io_perf_0_value_REG;</span></a>
+<a name="1492"><span class="lineNum">    1492 </span><span class="lineCov">      63847 :     io_perf_1_value_REG &lt;=</span></a>
+<a name="1493"><span class="lineNum">    1493 </span><span class="lineCov">      63847 :       2'({1'h0, _GEN_35 &amp; _update_on_mispred_0_T}</span></a>
+<a name="1494"><span class="lineNum">    1494 </span><span class="lineCov">      63847 :          + {1'h0, _GEN_44 &amp; _update_on_mispred_1_T});</span></a>
+<a name="1495"><span class="lineNum">    1495 </span><span class="lineCov">      63847 :     io_perf_1_value_REG_1 &lt;= io_perf_1_value_REG;</span></a>
+<a name="1496"><span class="lineNum">    1496 </span><span class="lineCov">      63847 :     io_perf_2_value_REG &lt;=</span></a>
+<a name="1497"><span class="lineNum">    1497 </span><span class="lineCov">      63847 :       2'({1'h0, _GEN_35 &amp; io_update_bits_meta[48] == io_update_bits_br_taken_mask_0}</span></a>
+<a name="1498"><span class="lineNum">    1498 </span><span class="lineCov">      63847 :          + {1'h0, _GEN_44 &amp; io_update_bits_meta[49] == io_update_bits_br_taken_mask_1});</span></a>
+<a name="1499"><span class="lineNum">    1499 </span><span class="lineCov">      63847 :     io_perf_2_value_REG_1 &lt;= io_perf_2_value_REG;</span></a>
+<a name="1500"><span class="lineNum">    1500 </span>            :   end // always @(posedge)</a>
+<a name="1501"><span class="lineNum">    1501 </span>            :   wire [3:0]  _allocFailureMask_T = ~(io_update_bits_meta[59:56]);</a>
+<a name="1502"><span class="lineNum">    1502 </span>            :   wire [1:0]  _GEN_47 = {1'h0, _allocFailureMask_T[0] &amp; longerHistoryTableMask[0]};</a>
+<a name="1503"><span class="lineNum">    1503 </span>            :   wire [1:0]  _GEN_48 = {1'h0, _allocFailureMask_T[1] &amp; longerHistoryTableMask[1]};</a>
+<a name="1504"><span class="lineNum">    1504 </span>            :   wire [1:0]  _GEN_49 = {1'h0, _allocFailureMask_T[2] &amp; longerHistoryTableMask[2]};</a>
+<a name="1505"><span class="lineNum">    1505 </span>            :   wire [1:0]  _GEN_50 = {1'h0, _allocFailureMask_T[3] &amp; longerHistoryTableMask[3]};</a>
+<a name="1506"><span class="lineNum">    1506 </span>            :   wire [1:0]  _GEN_51 = {1'h0, _firstEntry_T};</a>
+<a name="1507"><span class="lineNum">    1507 </span>            :   wire [1:0]  _GEN_52 = {1'h0, _firstEntry_T_1};</a>
+<a name="1508"><span class="lineNum">    1508 </span>            :   wire [1:0]  _GEN_53 = {1'h0, _firstEntry_T_2};</a>
+<a name="1509"><span class="lineNum">    1509 </span>            :   wire [1:0]  _GEN_54 = {1'h0, io_update_bits_meta[59] &amp; longerHistoryTableMask[3]};</a>
+<a name="1510"><span class="lineNum">    1510 </span><span class="lineCov">         30 :   wire        tickInc =</span></a>
+<a name="1511"><span class="lineNum">    1511 </span>            :     3'({1'h0, 2'(_GEN_47 + _GEN_48)}</a>
+<a name="1512"><span class="lineNum">    1512 </span>            :        + {1'h0,</a>
+<a name="1513"><span class="lineNum">    1513 </span>            :           2'(_GEN_49</a>
+<a name="1514"><span class="lineNum">    1514 </span>            :              + _GEN_50)}) &gt; 3'({1'h0, 2'(_GEN_51 + _GEN_52)}</a>
+<a name="1515"><span class="lineNum">    1515 </span>            :                                + {1'h0, 2'(_GEN_53 + _GEN_54)});</a>
+<a name="1516"><span class="lineNum">    1516 </span>            :   wire [6:0]  _GEN_55 =</a>
+<a name="1517"><span class="lineNum">    1517 </span>            :     {4'h0,</a>
+<a name="1518"><span class="lineNum">    1518 </span>            :      3'(3'({1'h0, 2'(_GEN_47 + _GEN_48)} + {1'h0, 2'(_GEN_49 + _GEN_50)})</a>
+<a name="1519"><span class="lineNum">    1519 </span>            :         - (3'({1'h0, 2'(_GEN_51 + _GEN_52)} + {1'h0, 2'(_GEN_53 + _GEN_54)})))};</a>
+<a name="1520"><span class="lineNum">    1520 </span><span class="lineCov">         28 :   wire        tickDec =</span></a>
+<a name="1521"><span class="lineNum">    1521 </span>            :     3'({1'h0, 2'(_GEN_51 + _GEN_52)}</a>
+<a name="1522"><span class="lineNum">    1522 </span>            :        + {1'h0,</a>
+<a name="1523"><span class="lineNum">    1523 </span>            :           2'(_GEN_53</a>
+<a name="1524"><span class="lineNum">    1524 </span>            :              + _GEN_54)}) &gt; 3'({1'h0, 2'(_GEN_47 + _GEN_48)}</a>
+<a name="1525"><span class="lineNum">    1525 </span>            :                                + {1'h0, 2'(_GEN_49 + _GEN_50)});</a>
+<a name="1526"><span class="lineNum">    1526 </span>            :   wire [6:0]  _GEN_56 =</a>
+<a name="1527"><span class="lineNum">    1527 </span>            :     {4'h0,</a>
+<a name="1528"><span class="lineNum">    1528 </span>            :      3'(3'({1'h0, 2'(_GEN_51 + _GEN_52)} + {1'h0, 2'(_GEN_53 + _GEN_54)})</a>
+<a name="1529"><span class="lineNum">    1529 </span>            :         - (3'({1'h0, 2'(_GEN_47 + _GEN_48)} + {1'h0, 2'(_GEN_49 + _GEN_50)})))};</a>
+<a name="1530"><span class="lineNum">    1530 </span>            :   wire [3:0]  _allocFailureMask_T_1 = ~(io_update_bits_meta[63:60]);</a>
+<a name="1531"><span class="lineNum">    1531 </span>            :   wire [1:0]  _GEN_57 = {1'h0, _allocFailureMask_T_1[0] &amp; longerHistoryTableMask_1[0]};</a>
+<a name="1532"><span class="lineNum">    1532 </span>            :   wire [1:0]  _GEN_58 = {1'h0, _allocFailureMask_T_1[1] &amp; longerHistoryTableMask_1[1]};</a>
+<a name="1533"><span class="lineNum">    1533 </span>            :   wire [1:0]  _GEN_59 = {1'h0, _allocFailureMask_T_1[2] &amp; longerHistoryTableMask_1[2]};</a>
+<a name="1534"><span class="lineNum">    1534 </span>            :   wire [1:0]  _GEN_60 = {1'h0, _allocFailureMask_T_1[3] &amp; longerHistoryTableMask_1[3]};</a>
+<a name="1535"><span class="lineNum">    1535 </span>            :   wire [1:0]  _GEN_61 = {1'h0, _firstEntry_T_6};</a>
+<a name="1536"><span class="lineNum">    1536 </span>            :   wire [1:0]  _GEN_62 = {1'h0, _firstEntry_T_7};</a>
+<a name="1537"><span class="lineNum">    1537 </span>            :   wire [1:0]  _GEN_63 = {1'h0, _firstEntry_T_8};</a>
+<a name="1538"><span class="lineNum">    1538 </span>            :   wire [1:0]  _GEN_64 = {1'h0, io_update_bits_meta[63] &amp; longerHistoryTableMask_1[3]};</a>
+<a name="1539"><span class="lineNum">    1539 </span><span class="lineCov">         30 :   wire        tickInc_1 =</span></a>
+<a name="1540"><span class="lineNum">    1540 </span>            :     3'({1'h0, 2'(_GEN_57 + _GEN_58)}</a>
+<a name="1541"><span class="lineNum">    1541 </span>            :        + {1'h0,</a>
+<a name="1542"><span class="lineNum">    1542 </span>            :           2'(_GEN_59</a>
+<a name="1543"><span class="lineNum">    1543 </span>            :              + _GEN_60)}) &gt; 3'({1'h0, 2'(_GEN_61 + _GEN_62)}</a>
+<a name="1544"><span class="lineNum">    1544 </span>            :                                + {1'h0, 2'(_GEN_63 + _GEN_64)});</a>
+<a name="1545"><span class="lineNum">    1545 </span>            :   wire [6:0]  _GEN_65 =</a>
+<a name="1546"><span class="lineNum">    1546 </span>            :     {4'h0,</a>
+<a name="1547"><span class="lineNum">    1547 </span>            :      3'(3'({1'h0, 2'(_GEN_57 + _GEN_58)} + {1'h0, 2'(_GEN_59 + _GEN_60)})</a>
+<a name="1548"><span class="lineNum">    1548 </span>            :         - (3'({1'h0, 2'(_GEN_61 + _GEN_62)} + {1'h0, 2'(_GEN_63 + _GEN_64)})))};</a>
+<a name="1549"><span class="lineNum">    1549 </span><span class="lineCov">         28 :   wire        tickDec_1 =</span></a>
+<a name="1550"><span class="lineNum">    1550 </span>            :     3'({1'h0, 2'(_GEN_61 + _GEN_62)}</a>
+<a name="1551"><span class="lineNum">    1551 </span>            :        + {1'h0,</a>
+<a name="1552"><span class="lineNum">    1552 </span>            :           2'(_GEN_63</a>
+<a name="1553"><span class="lineNum">    1553 </span>            :              + _GEN_64)}) &gt; 3'({1'h0, 2'(_GEN_57 + _GEN_58)}</a>
+<a name="1554"><span class="lineNum">    1554 </span>            :                                + {1'h0, 2'(_GEN_59 + _GEN_60)});</a>
+<a name="1555"><span class="lineNum">    1555 </span>            :   wire [6:0]  _GEN_66 =</a>
+<a name="1556"><span class="lineNum">    1556 </span>            :     {4'h0,</a>
+<a name="1557"><span class="lineNum">    1557 </span>            :      3'(3'({1'h0, 2'(_GEN_61 + _GEN_62)} + {1'h0, 2'(_GEN_63 + _GEN_64)})</a>
+<a name="1558"><span class="lineNum">    1558 </span>            :         - (3'({1'h0, 2'(_GEN_57 + _GEN_58)} + {1'h0, 2'(_GEN_59 + _GEN_60)})))};</a>
+<a name="1559"><span class="lineNum">    1559 </span>            :   wire        _newThres_newCtr_T = (&amp;scThresholds_0_ctr) &amp; _update_on_mispred_0_T;</a>
+<a name="1560"><span class="lineNum">    1560 </span>            :   wire        _newThres_newCtr_T_2 = scThresholds_0_ctr == 5'h0 &amp; ~_update_on_mispred_0_T;</a>
+<a name="1561"><span class="lineNum">    1561 </span>            :   wire [4:0]  _newThres_newCtr_T_3 = 5'(scThresholds_0_ctr + 5'h1);</a>
+<a name="1562"><span class="lineNum">    1562 </span>            :   wire [4:0]  _newThres_newCtr_T_5 = 5'(scThresholds_0_ctr - 5'h1);</a>
+<a name="1563"><span class="lineNum">    1563 </span>            :   wire        _GEN_67 = io_update_bits_meta[48] == io_update_bits_br_taken_mask_0;</a>
+<a name="1564"><span class="lineNum">    1564 </span><span class="lineCov">        159 :   wire [4:0]  newThres_newCtr =</span></a>
+<a name="1565"><span class="lineNum">    1565 </span>            :     _newThres_newCtr_T</a>
+<a name="1566"><span class="lineNum">    1566 </span>            :       ? 5'h1F</a>
+<a name="1567"><span class="lineNum">    1567 </span>            :       : _newThres_newCtr_T_2</a>
+<a name="1568"><span class="lineNum">    1568 </span>            :           ? 5'h0</a>
+<a name="1569"><span class="lineNum">    1569 </span>            :           : _GEN_67 ? _newThres_newCtr_T_5 : _newThres_newCtr_T_3;</a>
+<a name="1570"><span class="lineNum">    1570 </span>            :   wire        _newThres_res_ctr_T_4 = newThres_newCtr == 5'h0;</a>
+<a name="1571"><span class="lineNum">    1571 </span>            :   wire        _newThres_newCtr_T_9 = (&amp;scThresholds_1_ctr) &amp; _update_on_mispred_1_T;</a>
+<a name="1572"><span class="lineNum">    1572 </span>            :   wire        _newThres_newCtr_T_11 =</a>
+<a name="1573"><span class="lineNum">    1573 </span>            :     scThresholds_1_ctr == 5'h0 &amp; ~_update_on_mispred_1_T;</a>
+<a name="1574"><span class="lineNum">    1574 </span>            :   wire [4:0]  _newThres_newCtr_T_12 = 5'(scThresholds_1_ctr + 5'h1);</a>
+<a name="1575"><span class="lineNum">    1575 </span>            :   wire [4:0]  _newThres_newCtr_T_14 = 5'(scThresholds_1_ctr - 5'h1);</a>
+<a name="1576"><span class="lineNum">    1576 </span>            :   wire        _GEN_68 = io_update_bits_meta[49] == io_update_bits_br_taken_mask_1;</a>
+<a name="1577"><span class="lineNum">    1577 </span><span class="lineCov">        208 :   wire [4:0]  newThres_newCtr_1 =</span></a>
+<a name="1578"><span class="lineNum">    1578 </span>            :     _newThres_newCtr_T_9</a>
+<a name="1579"><span class="lineNum">    1579 </span>            :       ? 5'h1F</a>
+<a name="1580"><span class="lineNum">    1580 </span>            :       : _newThres_newCtr_T_11</a>
+<a name="1581"><span class="lineNum">    1581 </span>            :           ? 5'h0</a>
+<a name="1582"><span class="lineNum">    1582 </span>            :           : _GEN_68 ? _newThres_newCtr_T_14 : _newThres_newCtr_T_12;</a>
+<a name="1583"><span class="lineNum">    1583 </span>            :   wire        _newThres_res_ctr_T_11 = newThres_newCtr_1 == 5'h0;</a>
+<a name="1584"><span class="lineNum">    1584 </span><span class="lineCov">         99 :   wire [3:0]  updateUseAltCtr =</span></a>
+<a name="1585"><span class="lineNum">    1585 </span>            :     (io_update_bits_pc[7:1] == 7'h0 ? useAltOnNaCtrs_0_0 : 4'h0)</a>
+<a name="1586"><span class="lineNum">    1586 </span>            :     | (io_update_bits_pc[7:1] == 7'h1 ? useAltOnNaCtrs_0_1 : 4'h0)</a>
+<a name="1587"><span class="lineNum">    1587 </span>            :     | (io_update_bits_pc[7:1] == 7'h2 ? useAltOnNaCtrs_0_2 : 4'h0)</a>
+<a name="1588"><span class="lineNum">    1588 </span>            :     | (io_update_bits_pc[7:1] == 7'h3 ? useAltOnNaCtrs_0_3 : 4'h0)</a>
+<a name="1589"><span class="lineNum">    1589 </span>            :     | (io_update_bits_pc[7:1] == 7'h4 ? useAltOnNaCtrs_0_4 : 4'h0)</a>
+<a name="1590"><span class="lineNum">    1590 </span>            :     | (io_update_bits_pc[7:1] == 7'h5 ? useAltOnNaCtrs_0_5 : 4'h0)</a>
+<a name="1591"><span class="lineNum">    1591 </span>            :     | (io_update_bits_pc[7:1] == 7'h6 ? useAltOnNaCtrs_0_6 : 4'h0)</a>
+<a name="1592"><span class="lineNum">    1592 </span>            :     | (io_update_bits_pc[7:1] == 7'h7 ? useAltOnNaCtrs_0_7 : 4'h0)</a>
+<a name="1593"><span class="lineNum">    1593 </span>            :     | (io_update_bits_pc[7:1] == 7'h8 ? useAltOnNaCtrs_0_8 : 4'h0)</a>
+<a name="1594"><span class="lineNum">    1594 </span>            :     | (io_update_bits_pc[7:1] == 7'h9 ? useAltOnNaCtrs_0_9 : 4'h0)</a>
+<a name="1595"><span class="lineNum">    1595 </span>            :     | (io_update_bits_pc[7:1] == 7'hA ? useAltOnNaCtrs_0_10 : 4'h0)</a>
+<a name="1596"><span class="lineNum">    1596 </span>            :     | (io_update_bits_pc[7:1] == 7'hB ? useAltOnNaCtrs_0_11 : 4'h0)</a>
+<a name="1597"><span class="lineNum">    1597 </span>            :     | (io_update_bits_pc[7:1] == 7'hC ? useAltOnNaCtrs_0_12 : 4'h0)</a>
+<a name="1598"><span class="lineNum">    1598 </span>            :     | (io_update_bits_pc[7:1] == 7'hD ? useAltOnNaCtrs_0_13 : 4'h0)</a>
+<a name="1599"><span class="lineNum">    1599 </span>            :     | (io_update_bits_pc[7:1] == 7'hE ? useAltOnNaCtrs_0_14 : 4'h0)</a>
+<a name="1600"><span class="lineNum">    1600 </span>            :     | (io_update_bits_pc[7:1] == 7'hF ? useAltOnNaCtrs_0_15 : 4'h0)</a>
+<a name="1601"><span class="lineNum">    1601 </span>            :     | (io_update_bits_pc[7:1] == 7'h10 ? useAltOnNaCtrs_0_16 : 4'h0)</a>
+<a name="1602"><span class="lineNum">    1602 </span>            :     | (io_update_bits_pc[7:1] == 7'h11 ? useAltOnNaCtrs_0_17 : 4'h0)</a>
+<a name="1603"><span class="lineNum">    1603 </span>            :     | (io_update_bits_pc[7:1] == 7'h12 ? useAltOnNaCtrs_0_18 : 4'h0)</a>
+<a name="1604"><span class="lineNum">    1604 </span>            :     | (io_update_bits_pc[7:1] == 7'h13 ? useAltOnNaCtrs_0_19 : 4'h0)</a>
+<a name="1605"><span class="lineNum">    1605 </span>            :     | (io_update_bits_pc[7:1] == 7'h14 ? useAltOnNaCtrs_0_20 : 4'h0)</a>
+<a name="1606"><span class="lineNum">    1606 </span>            :     | (io_update_bits_pc[7:1] == 7'h15 ? useAltOnNaCtrs_0_21 : 4'h0)</a>
+<a name="1607"><span class="lineNum">    1607 </span>            :     | (io_update_bits_pc[7:1] == 7'h16 ? useAltOnNaCtrs_0_22 : 4'h0)</a>
+<a name="1608"><span class="lineNum">    1608 </span>            :     | (io_update_bits_pc[7:1] == 7'h17 ? useAltOnNaCtrs_0_23 : 4'h0)</a>
+<a name="1609"><span class="lineNum">    1609 </span>            :     | (io_update_bits_pc[7:1] == 7'h18 ? useAltOnNaCtrs_0_24 : 4'h0)</a>
+<a name="1610"><span class="lineNum">    1610 </span>            :     | (io_update_bits_pc[7:1] == 7'h19 ? useAltOnNaCtrs_0_25 : 4'h0)</a>
+<a name="1611"><span class="lineNum">    1611 </span>            :     | (io_update_bits_pc[7:1] == 7'h1A ? useAltOnNaCtrs_0_26 : 4'h0)</a>
+<a name="1612"><span class="lineNum">    1612 </span>            :     | (io_update_bits_pc[7:1] == 7'h1B ? useAltOnNaCtrs_0_27 : 4'h0)</a>
+<a name="1613"><span class="lineNum">    1613 </span>            :     | (io_update_bits_pc[7:1] == 7'h1C ? useAltOnNaCtrs_0_28 : 4'h0)</a>
+<a name="1614"><span class="lineNum">    1614 </span>            :     | (io_update_bits_pc[7:1] == 7'h1D ? useAltOnNaCtrs_0_29 : 4'h0)</a>
+<a name="1615"><span class="lineNum">    1615 </span>            :     | (io_update_bits_pc[7:1] == 7'h1E ? useAltOnNaCtrs_0_30 : 4'h0)</a>
+<a name="1616"><span class="lineNum">    1616 </span>            :     | (io_update_bits_pc[7:1] == 7'h1F ? useAltOnNaCtrs_0_31 : 4'h0)</a>
+<a name="1617"><span class="lineNum">    1617 </span>            :     | (io_update_bits_pc[7:1] == 7'h20 ? useAltOnNaCtrs_0_32 : 4'h0)</a>
+<a name="1618"><span class="lineNum">    1618 </span>            :     | (io_update_bits_pc[7:1] == 7'h21 ? useAltOnNaCtrs_0_33 : 4'h0)</a>
+<a name="1619"><span class="lineNum">    1619 </span>            :     | (io_update_bits_pc[7:1] == 7'h22 ? useAltOnNaCtrs_0_34 : 4'h0)</a>
+<a name="1620"><span class="lineNum">    1620 </span>            :     | (io_update_bits_pc[7:1] == 7'h23 ? useAltOnNaCtrs_0_35 : 4'h0)</a>
+<a name="1621"><span class="lineNum">    1621 </span>            :     | (io_update_bits_pc[7:1] == 7'h24 ? useAltOnNaCtrs_0_36 : 4'h0)</a>
+<a name="1622"><span class="lineNum">    1622 </span>            :     | (io_update_bits_pc[7:1] == 7'h25 ? useAltOnNaCtrs_0_37 : 4'h0)</a>
+<a name="1623"><span class="lineNum">    1623 </span>            :     | (io_update_bits_pc[7:1] == 7'h26 ? useAltOnNaCtrs_0_38 : 4'h0)</a>
+<a name="1624"><span class="lineNum">    1624 </span>            :     | (io_update_bits_pc[7:1] == 7'h27 ? useAltOnNaCtrs_0_39 : 4'h0)</a>
+<a name="1625"><span class="lineNum">    1625 </span>            :     | (io_update_bits_pc[7:1] == 7'h28 ? useAltOnNaCtrs_0_40 : 4'h0)</a>
+<a name="1626"><span class="lineNum">    1626 </span>            :     | (io_update_bits_pc[7:1] == 7'h29 ? useAltOnNaCtrs_0_41 : 4'h0)</a>
+<a name="1627"><span class="lineNum">    1627 </span>            :     | (io_update_bits_pc[7:1] == 7'h2A ? useAltOnNaCtrs_0_42 : 4'h0)</a>
+<a name="1628"><span class="lineNum">    1628 </span>            :     | (io_update_bits_pc[7:1] == 7'h2B ? useAltOnNaCtrs_0_43 : 4'h0)</a>
+<a name="1629"><span class="lineNum">    1629 </span>            :     | (io_update_bits_pc[7:1] == 7'h2C ? useAltOnNaCtrs_0_44 : 4'h0)</a>
+<a name="1630"><span class="lineNum">    1630 </span>            :     | (io_update_bits_pc[7:1] == 7'h2D ? useAltOnNaCtrs_0_45 : 4'h0)</a>
+<a name="1631"><span class="lineNum">    1631 </span>            :     | (io_update_bits_pc[7:1] == 7'h2E ? useAltOnNaCtrs_0_46 : 4'h0)</a>
+<a name="1632"><span class="lineNum">    1632 </span>            :     | (io_update_bits_pc[7:1] == 7'h2F ? useAltOnNaCtrs_0_47 : 4'h0)</a>
+<a name="1633"><span class="lineNum">    1633 </span>            :     | (io_update_bits_pc[7:1] == 7'h30 ? useAltOnNaCtrs_0_48 : 4'h0)</a>
+<a name="1634"><span class="lineNum">    1634 </span>            :     | (io_update_bits_pc[7:1] == 7'h31 ? useAltOnNaCtrs_0_49 : 4'h0)</a>
+<a name="1635"><span class="lineNum">    1635 </span>            :     | (io_update_bits_pc[7:1] == 7'h32 ? useAltOnNaCtrs_0_50 : 4'h0)</a>
+<a name="1636"><span class="lineNum">    1636 </span>            :     | (io_update_bits_pc[7:1] == 7'h33 ? useAltOnNaCtrs_0_51 : 4'h0)</a>
+<a name="1637"><span class="lineNum">    1637 </span>            :     | (io_update_bits_pc[7:1] == 7'h34 ? useAltOnNaCtrs_0_52 : 4'h0)</a>
+<a name="1638"><span class="lineNum">    1638 </span>            :     | (io_update_bits_pc[7:1] == 7'h35 ? useAltOnNaCtrs_0_53 : 4'h0)</a>
+<a name="1639"><span class="lineNum">    1639 </span>            :     | (io_update_bits_pc[7:1] == 7'h36 ? useAltOnNaCtrs_0_54 : 4'h0)</a>
+<a name="1640"><span class="lineNum">    1640 </span>            :     | (io_update_bits_pc[7:1] == 7'h37 ? useAltOnNaCtrs_0_55 : 4'h0)</a>
+<a name="1641"><span class="lineNum">    1641 </span>            :     | (io_update_bits_pc[7:1] == 7'h38 ? useAltOnNaCtrs_0_56 : 4'h0)</a>
+<a name="1642"><span class="lineNum">    1642 </span>            :     | (io_update_bits_pc[7:1] == 7'h39 ? useAltOnNaCtrs_0_57 : 4'h0)</a>
+<a name="1643"><span class="lineNum">    1643 </span>            :     | (io_update_bits_pc[7:1] == 7'h3A ? useAltOnNaCtrs_0_58 : 4'h0)</a>
+<a name="1644"><span class="lineNum">    1644 </span>            :     | (io_update_bits_pc[7:1] == 7'h3B ? useAltOnNaCtrs_0_59 : 4'h0)</a>
+<a name="1645"><span class="lineNum">    1645 </span>            :     | (io_update_bits_pc[7:1] == 7'h3C ? useAltOnNaCtrs_0_60 : 4'h0)</a>
+<a name="1646"><span class="lineNum">    1646 </span>            :     | (io_update_bits_pc[7:1] == 7'h3D ? useAltOnNaCtrs_0_61 : 4'h0)</a>
+<a name="1647"><span class="lineNum">    1647 </span>            :     | (io_update_bits_pc[7:1] == 7'h3E ? useAltOnNaCtrs_0_62 : 4'h0)</a>
+<a name="1648"><span class="lineNum">    1648 </span>            :     | (io_update_bits_pc[7:1] == 7'h3F ? useAltOnNaCtrs_0_63 : 4'h0)</a>
+<a name="1649"><span class="lineNum">    1649 </span>            :     | (io_update_bits_pc[7:1] == 7'h40 ? useAltOnNaCtrs_0_64 : 4'h0)</a>
+<a name="1650"><span class="lineNum">    1650 </span>            :     | (io_update_bits_pc[7:1] == 7'h41 ? useAltOnNaCtrs_0_65 : 4'h0)</a>
+<a name="1651"><span class="lineNum">    1651 </span>            :     | (io_update_bits_pc[7:1] == 7'h42 ? useAltOnNaCtrs_0_66 : 4'h0)</a>
+<a name="1652"><span class="lineNum">    1652 </span>            :     | (io_update_bits_pc[7:1] == 7'h43 ? useAltOnNaCtrs_0_67 : 4'h0)</a>
+<a name="1653"><span class="lineNum">    1653 </span>            :     | (io_update_bits_pc[7:1] == 7'h44 ? useAltOnNaCtrs_0_68 : 4'h0)</a>
+<a name="1654"><span class="lineNum">    1654 </span>            :     | (io_update_bits_pc[7:1] == 7'h45 ? useAltOnNaCtrs_0_69 : 4'h0)</a>
+<a name="1655"><span class="lineNum">    1655 </span>            :     | (io_update_bits_pc[7:1] == 7'h46 ? useAltOnNaCtrs_0_70 : 4'h0)</a>
+<a name="1656"><span class="lineNum">    1656 </span>            :     | (io_update_bits_pc[7:1] == 7'h47 ? useAltOnNaCtrs_0_71 : 4'h0)</a>
+<a name="1657"><span class="lineNum">    1657 </span>            :     | (io_update_bits_pc[7:1] == 7'h48 ? useAltOnNaCtrs_0_72 : 4'h0)</a>
+<a name="1658"><span class="lineNum">    1658 </span>            :     | (io_update_bits_pc[7:1] == 7'h49 ? useAltOnNaCtrs_0_73 : 4'h0)</a>
+<a name="1659"><span class="lineNum">    1659 </span>            :     | (io_update_bits_pc[7:1] == 7'h4A ? useAltOnNaCtrs_0_74 : 4'h0)</a>
+<a name="1660"><span class="lineNum">    1660 </span>            :     | (io_update_bits_pc[7:1] == 7'h4B ? useAltOnNaCtrs_0_75 : 4'h0)</a>
+<a name="1661"><span class="lineNum">    1661 </span>            :     | (io_update_bits_pc[7:1] == 7'h4C ? useAltOnNaCtrs_0_76 : 4'h0)</a>
+<a name="1662"><span class="lineNum">    1662 </span>            :     | (io_update_bits_pc[7:1] == 7'h4D ? useAltOnNaCtrs_0_77 : 4'h0)</a>
+<a name="1663"><span class="lineNum">    1663 </span>            :     | (io_update_bits_pc[7:1] == 7'h4E ? useAltOnNaCtrs_0_78 : 4'h0)</a>
+<a name="1664"><span class="lineNum">    1664 </span>            :     | (io_update_bits_pc[7:1] == 7'h4F ? useAltOnNaCtrs_0_79 : 4'h0)</a>
+<a name="1665"><span class="lineNum">    1665 </span>            :     | (io_update_bits_pc[7:1] == 7'h50 ? useAltOnNaCtrs_0_80 : 4'h0)</a>
+<a name="1666"><span class="lineNum">    1666 </span>            :     | (io_update_bits_pc[7:1] == 7'h51 ? useAltOnNaCtrs_0_81 : 4'h0)</a>
+<a name="1667"><span class="lineNum">    1667 </span>            :     | (io_update_bits_pc[7:1] == 7'h52 ? useAltOnNaCtrs_0_82 : 4'h0)</a>
+<a name="1668"><span class="lineNum">    1668 </span>            :     | (io_update_bits_pc[7:1] == 7'h53 ? useAltOnNaCtrs_0_83 : 4'h0)</a>
+<a name="1669"><span class="lineNum">    1669 </span>            :     | (io_update_bits_pc[7:1] == 7'h54 ? useAltOnNaCtrs_0_84 : 4'h0)</a>
+<a name="1670"><span class="lineNum">    1670 </span>            :     | (io_update_bits_pc[7:1] == 7'h55 ? useAltOnNaCtrs_0_85 : 4'h0)</a>
+<a name="1671"><span class="lineNum">    1671 </span>            :     | (io_update_bits_pc[7:1] == 7'h56 ? useAltOnNaCtrs_0_86 : 4'h0)</a>
+<a name="1672"><span class="lineNum">    1672 </span>            :     | (io_update_bits_pc[7:1] == 7'h57 ? useAltOnNaCtrs_0_87 : 4'h0)</a>
+<a name="1673"><span class="lineNum">    1673 </span>            :     | (io_update_bits_pc[7:1] == 7'h58 ? useAltOnNaCtrs_0_88 : 4'h0)</a>
+<a name="1674"><span class="lineNum">    1674 </span>            :     | (io_update_bits_pc[7:1] == 7'h59 ? useAltOnNaCtrs_0_89 : 4'h0)</a>
+<a name="1675"><span class="lineNum">    1675 </span>            :     | (io_update_bits_pc[7:1] == 7'h5A ? useAltOnNaCtrs_0_90 : 4'h0)</a>
+<a name="1676"><span class="lineNum">    1676 </span>            :     | (io_update_bits_pc[7:1] == 7'h5B ? useAltOnNaCtrs_0_91 : 4'h0)</a>
+<a name="1677"><span class="lineNum">    1677 </span>            :     | (io_update_bits_pc[7:1] == 7'h5C ? useAltOnNaCtrs_0_92 : 4'h0)</a>
+<a name="1678"><span class="lineNum">    1678 </span>            :     | (io_update_bits_pc[7:1] == 7'h5D ? useAltOnNaCtrs_0_93 : 4'h0)</a>
+<a name="1679"><span class="lineNum">    1679 </span>            :     | (io_update_bits_pc[7:1] == 7'h5E ? useAltOnNaCtrs_0_94 : 4'h0)</a>
+<a name="1680"><span class="lineNum">    1680 </span>            :     | (io_update_bits_pc[7:1] == 7'h5F ? useAltOnNaCtrs_0_95 : 4'h0)</a>
+<a name="1681"><span class="lineNum">    1681 </span>            :     | (io_update_bits_pc[7:1] == 7'h60 ? useAltOnNaCtrs_0_96 : 4'h0)</a>
+<a name="1682"><span class="lineNum">    1682 </span>            :     | (io_update_bits_pc[7:1] == 7'h61 ? useAltOnNaCtrs_0_97 : 4'h0)</a>
+<a name="1683"><span class="lineNum">    1683 </span>            :     | (io_update_bits_pc[7:1] == 7'h62 ? useAltOnNaCtrs_0_98 : 4'h0)</a>
+<a name="1684"><span class="lineNum">    1684 </span>            :     | (io_update_bits_pc[7:1] == 7'h63 ? useAltOnNaCtrs_0_99 : 4'h0)</a>
+<a name="1685"><span class="lineNum">    1685 </span>            :     | (io_update_bits_pc[7:1] == 7'h64 ? useAltOnNaCtrs_0_100 : 4'h0)</a>
+<a name="1686"><span class="lineNum">    1686 </span>            :     | (io_update_bits_pc[7:1] == 7'h65 ? useAltOnNaCtrs_0_101 : 4'h0)</a>
+<a name="1687"><span class="lineNum">    1687 </span>            :     | (io_update_bits_pc[7:1] == 7'h66 ? useAltOnNaCtrs_0_102 : 4'h0)</a>
+<a name="1688"><span class="lineNum">    1688 </span>            :     | (io_update_bits_pc[7:1] == 7'h67 ? useAltOnNaCtrs_0_103 : 4'h0)</a>
+<a name="1689"><span class="lineNum">    1689 </span>            :     | (io_update_bits_pc[7:1] == 7'h68 ? useAltOnNaCtrs_0_104 : 4'h0)</a>
+<a name="1690"><span class="lineNum">    1690 </span>            :     | (io_update_bits_pc[7:1] == 7'h69 ? useAltOnNaCtrs_0_105 : 4'h0)</a>
+<a name="1691"><span class="lineNum">    1691 </span>            :     | (io_update_bits_pc[7:1] == 7'h6A ? useAltOnNaCtrs_0_106 : 4'h0)</a>
+<a name="1692"><span class="lineNum">    1692 </span>            :     | (io_update_bits_pc[7:1] == 7'h6B ? useAltOnNaCtrs_0_107 : 4'h0)</a>
+<a name="1693"><span class="lineNum">    1693 </span>            :     | (io_update_bits_pc[7:1] == 7'h6C ? useAltOnNaCtrs_0_108 : 4'h0)</a>
+<a name="1694"><span class="lineNum">    1694 </span>            :     | (io_update_bits_pc[7:1] == 7'h6D ? useAltOnNaCtrs_0_109 : 4'h0)</a>
+<a name="1695"><span class="lineNum">    1695 </span>            :     | (io_update_bits_pc[7:1] == 7'h6E ? useAltOnNaCtrs_0_110 : 4'h0)</a>
+<a name="1696"><span class="lineNum">    1696 </span>            :     | (io_update_bits_pc[7:1] == 7'h6F ? useAltOnNaCtrs_0_111 : 4'h0)</a>
+<a name="1697"><span class="lineNum">    1697 </span>            :     | (io_update_bits_pc[7:1] == 7'h70 ? useAltOnNaCtrs_0_112 : 4'h0)</a>
+<a name="1698"><span class="lineNum">    1698 </span>            :     | (io_update_bits_pc[7:1] == 7'h71 ? useAltOnNaCtrs_0_113 : 4'h0)</a>
+<a name="1699"><span class="lineNum">    1699 </span>            :     | (io_update_bits_pc[7:1] == 7'h72 ? useAltOnNaCtrs_0_114 : 4'h0)</a>
+<a name="1700"><span class="lineNum">    1700 </span>            :     | (io_update_bits_pc[7:1] == 7'h73 ? useAltOnNaCtrs_0_115 : 4'h0)</a>
+<a name="1701"><span class="lineNum">    1701 </span>            :     | (io_update_bits_pc[7:1] == 7'h74 ? useAltOnNaCtrs_0_116 : 4'h0)</a>
+<a name="1702"><span class="lineNum">    1702 </span>            :     | (io_update_bits_pc[7:1] == 7'h75 ? useAltOnNaCtrs_0_117 : 4'h0)</a>
+<a name="1703"><span class="lineNum">    1703 </span>            :     | (io_update_bits_pc[7:1] == 7'h76 ? useAltOnNaCtrs_0_118 : 4'h0)</a>
+<a name="1704"><span class="lineNum">    1704 </span>            :     | (io_update_bits_pc[7:1] == 7'h77 ? useAltOnNaCtrs_0_119 : 4'h0)</a>
+<a name="1705"><span class="lineNum">    1705 </span>            :     | (io_update_bits_pc[7:1] == 7'h78 ? useAltOnNaCtrs_0_120 : 4'h0)</a>
+<a name="1706"><span class="lineNum">    1706 </span>            :     | (io_update_bits_pc[7:1] == 7'h79 ? useAltOnNaCtrs_0_121 : 4'h0)</a>
+<a name="1707"><span class="lineNum">    1707 </span>            :     | (io_update_bits_pc[7:1] == 7'h7A ? useAltOnNaCtrs_0_122 : 4'h0)</a>
+<a name="1708"><span class="lineNum">    1708 </span>            :     | (io_update_bits_pc[7:1] == 7'h7B ? useAltOnNaCtrs_0_123 : 4'h0)</a>
+<a name="1709"><span class="lineNum">    1709 </span>            :     | (io_update_bits_pc[7:1] == 7'h7C ? useAltOnNaCtrs_0_124 : 4'h0)</a>
+<a name="1710"><span class="lineNum">    1710 </span>            :     | (io_update_bits_pc[7:1] == 7'h7D ? useAltOnNaCtrs_0_125 : 4'h0)</a>
+<a name="1711"><span class="lineNum">    1711 </span>            :     | (io_update_bits_pc[7:1] == 7'h7E ? useAltOnNaCtrs_0_126 : 4'h0)</a>
+<a name="1712"><span class="lineNum">    1712 </span>            :     | ((&amp;(io_update_bits_pc[7:1])) ? useAltOnNaCtrs_0_127 : 4'h0);</a>
+<a name="1713"><span class="lineNum">    1713 </span><span class="lineCov">         35 :   wire        updateAltCorrect = io_update_bits_meta[65] == updateTaken;</span></a>
+<a name="1714"><span class="lineNum">    1714 </span>            :   wire        _GEN_69 =</a>
+<a name="1715"><span class="lineNum">    1715 </span>            :     io_update_bits_meta[84]</a>
+<a name="1716"><span class="lineNum">    1716 </span>            :     &amp; (io_update_bits_meta[76:74] == 3'h4 | io_update_bits_meta[76:74] == 3'h3)</a>
+<a name="1717"><span class="lineNum">    1717 </span>            :     &amp; io_update_bits_meta[68];</a>
+<a name="1718"><span class="lineNum">    1718 </span>            :   wire        _newCtr_T = (&amp;updateUseAltCtr) &amp; updateAltCorrect;</a>
+<a name="1719"><span class="lineNum">    1719 </span>            :   wire        _newCtr_T_2 = updateUseAltCtr == 4'h0 &amp; ~updateAltCorrect;</a>
+<a name="1720"><span class="lineNum">    1720 </span>            :   wire [3:0]  _newCtr_T_3 = 4'(updateUseAltCtr + 4'h1);</a>
+<a name="1721"><span class="lineNum">    1721 </span>            :   wire [3:0]  _newCtr_T_5 = 4'(updateUseAltCtr - 4'h1);</a>
+<a name="1722"><span class="lineNum">    1722 </span><span class="lineCov">        119 :   wire [3:0]  updateUseAltCtr_1 =</span></a>
+<a name="1723"><span class="lineNum">    1723 </span>            :     (io_update_bits_pc[7:1] == 7'h0 ? useAltOnNaCtrs_1_0 : 4'h0)</a>
+<a name="1724"><span class="lineNum">    1724 </span>            :     | (io_update_bits_pc[7:1] == 7'h1 ? useAltOnNaCtrs_1_1 : 4'h0)</a>
+<a name="1725"><span class="lineNum">    1725 </span>            :     | (io_update_bits_pc[7:1] == 7'h2 ? useAltOnNaCtrs_1_2 : 4'h0)</a>
+<a name="1726"><span class="lineNum">    1726 </span>            :     | (io_update_bits_pc[7:1] == 7'h3 ? useAltOnNaCtrs_1_3 : 4'h0)</a>
+<a name="1727"><span class="lineNum">    1727 </span>            :     | (io_update_bits_pc[7:1] == 7'h4 ? useAltOnNaCtrs_1_4 : 4'h0)</a>
+<a name="1728"><span class="lineNum">    1728 </span>            :     | (io_update_bits_pc[7:1] == 7'h5 ? useAltOnNaCtrs_1_5 : 4'h0)</a>
+<a name="1729"><span class="lineNum">    1729 </span>            :     | (io_update_bits_pc[7:1] == 7'h6 ? useAltOnNaCtrs_1_6 : 4'h0)</a>
+<a name="1730"><span class="lineNum">    1730 </span>            :     | (io_update_bits_pc[7:1] == 7'h7 ? useAltOnNaCtrs_1_7 : 4'h0)</a>
+<a name="1731"><span class="lineNum">    1731 </span>            :     | (io_update_bits_pc[7:1] == 7'h8 ? useAltOnNaCtrs_1_8 : 4'h0)</a>
+<a name="1732"><span class="lineNum">    1732 </span>            :     | (io_update_bits_pc[7:1] == 7'h9 ? useAltOnNaCtrs_1_9 : 4'h0)</a>
+<a name="1733"><span class="lineNum">    1733 </span>            :     | (io_update_bits_pc[7:1] == 7'hA ? useAltOnNaCtrs_1_10 : 4'h0)</a>
+<a name="1734"><span class="lineNum">    1734 </span>            :     | (io_update_bits_pc[7:1] == 7'hB ? useAltOnNaCtrs_1_11 : 4'h0)</a>
+<a name="1735"><span class="lineNum">    1735 </span>            :     | (io_update_bits_pc[7:1] == 7'hC ? useAltOnNaCtrs_1_12 : 4'h0)</a>
+<a name="1736"><span class="lineNum">    1736 </span>            :     | (io_update_bits_pc[7:1] == 7'hD ? useAltOnNaCtrs_1_13 : 4'h0)</a>
+<a name="1737"><span class="lineNum">    1737 </span>            :     | (io_update_bits_pc[7:1] == 7'hE ? useAltOnNaCtrs_1_14 : 4'h0)</a>
+<a name="1738"><span class="lineNum">    1738 </span>            :     | (io_update_bits_pc[7:1] == 7'hF ? useAltOnNaCtrs_1_15 : 4'h0)</a>
+<a name="1739"><span class="lineNum">    1739 </span>            :     | (io_update_bits_pc[7:1] == 7'h10 ? useAltOnNaCtrs_1_16 : 4'h0)</a>
+<a name="1740"><span class="lineNum">    1740 </span>            :     | (io_update_bits_pc[7:1] == 7'h11 ? useAltOnNaCtrs_1_17 : 4'h0)</a>
+<a name="1741"><span class="lineNum">    1741 </span>            :     | (io_update_bits_pc[7:1] == 7'h12 ? useAltOnNaCtrs_1_18 : 4'h0)</a>
+<a name="1742"><span class="lineNum">    1742 </span>            :     | (io_update_bits_pc[7:1] == 7'h13 ? useAltOnNaCtrs_1_19 : 4'h0)</a>
+<a name="1743"><span class="lineNum">    1743 </span>            :     | (io_update_bits_pc[7:1] == 7'h14 ? useAltOnNaCtrs_1_20 : 4'h0)</a>
+<a name="1744"><span class="lineNum">    1744 </span>            :     | (io_update_bits_pc[7:1] == 7'h15 ? useAltOnNaCtrs_1_21 : 4'h0)</a>
+<a name="1745"><span class="lineNum">    1745 </span>            :     | (io_update_bits_pc[7:1] == 7'h16 ? useAltOnNaCtrs_1_22 : 4'h0)</a>
+<a name="1746"><span class="lineNum">    1746 </span>            :     | (io_update_bits_pc[7:1] == 7'h17 ? useAltOnNaCtrs_1_23 : 4'h0)</a>
+<a name="1747"><span class="lineNum">    1747 </span>            :     | (io_update_bits_pc[7:1] == 7'h18 ? useAltOnNaCtrs_1_24 : 4'h0)</a>
+<a name="1748"><span class="lineNum">    1748 </span>            :     | (io_update_bits_pc[7:1] == 7'h19 ? useAltOnNaCtrs_1_25 : 4'h0)</a>
+<a name="1749"><span class="lineNum">    1749 </span>            :     | (io_update_bits_pc[7:1] == 7'h1A ? useAltOnNaCtrs_1_26 : 4'h0)</a>
+<a name="1750"><span class="lineNum">    1750 </span>            :     | (io_update_bits_pc[7:1] == 7'h1B ? useAltOnNaCtrs_1_27 : 4'h0)</a>
+<a name="1751"><span class="lineNum">    1751 </span>            :     | (io_update_bits_pc[7:1] == 7'h1C ? useAltOnNaCtrs_1_28 : 4'h0)</a>
+<a name="1752"><span class="lineNum">    1752 </span>            :     | (io_update_bits_pc[7:1] == 7'h1D ? useAltOnNaCtrs_1_29 : 4'h0)</a>
+<a name="1753"><span class="lineNum">    1753 </span>            :     | (io_update_bits_pc[7:1] == 7'h1E ? useAltOnNaCtrs_1_30 : 4'h0)</a>
+<a name="1754"><span class="lineNum">    1754 </span>            :     | (io_update_bits_pc[7:1] == 7'h1F ? useAltOnNaCtrs_1_31 : 4'h0)</a>
+<a name="1755"><span class="lineNum">    1755 </span>            :     | (io_update_bits_pc[7:1] == 7'h20 ? useAltOnNaCtrs_1_32 : 4'h0)</a>
+<a name="1756"><span class="lineNum">    1756 </span>            :     | (io_update_bits_pc[7:1] == 7'h21 ? useAltOnNaCtrs_1_33 : 4'h0)</a>
+<a name="1757"><span class="lineNum">    1757 </span>            :     | (io_update_bits_pc[7:1] == 7'h22 ? useAltOnNaCtrs_1_34 : 4'h0)</a>
+<a name="1758"><span class="lineNum">    1758 </span>            :     | (io_update_bits_pc[7:1] == 7'h23 ? useAltOnNaCtrs_1_35 : 4'h0)</a>
+<a name="1759"><span class="lineNum">    1759 </span>            :     | (io_update_bits_pc[7:1] == 7'h24 ? useAltOnNaCtrs_1_36 : 4'h0)</a>
+<a name="1760"><span class="lineNum">    1760 </span>            :     | (io_update_bits_pc[7:1] == 7'h25 ? useAltOnNaCtrs_1_37 : 4'h0)</a>
+<a name="1761"><span class="lineNum">    1761 </span>            :     | (io_update_bits_pc[7:1] == 7'h26 ? useAltOnNaCtrs_1_38 : 4'h0)</a>
+<a name="1762"><span class="lineNum">    1762 </span>            :     | (io_update_bits_pc[7:1] == 7'h27 ? useAltOnNaCtrs_1_39 : 4'h0)</a>
+<a name="1763"><span class="lineNum">    1763 </span>            :     | (io_update_bits_pc[7:1] == 7'h28 ? useAltOnNaCtrs_1_40 : 4'h0)</a>
+<a name="1764"><span class="lineNum">    1764 </span>            :     | (io_update_bits_pc[7:1] == 7'h29 ? useAltOnNaCtrs_1_41 : 4'h0)</a>
+<a name="1765"><span class="lineNum">    1765 </span>            :     | (io_update_bits_pc[7:1] == 7'h2A ? useAltOnNaCtrs_1_42 : 4'h0)</a>
+<a name="1766"><span class="lineNum">    1766 </span>            :     | (io_update_bits_pc[7:1] == 7'h2B ? useAltOnNaCtrs_1_43 : 4'h0)</a>
+<a name="1767"><span class="lineNum">    1767 </span>            :     | (io_update_bits_pc[7:1] == 7'h2C ? useAltOnNaCtrs_1_44 : 4'h0)</a>
+<a name="1768"><span class="lineNum">    1768 </span>            :     | (io_update_bits_pc[7:1] == 7'h2D ? useAltOnNaCtrs_1_45 : 4'h0)</a>
+<a name="1769"><span class="lineNum">    1769 </span>            :     | (io_update_bits_pc[7:1] == 7'h2E ? useAltOnNaCtrs_1_46 : 4'h0)</a>
+<a name="1770"><span class="lineNum">    1770 </span>            :     | (io_update_bits_pc[7:1] == 7'h2F ? useAltOnNaCtrs_1_47 : 4'h0)</a>
+<a name="1771"><span class="lineNum">    1771 </span>            :     | (io_update_bits_pc[7:1] == 7'h30 ? useAltOnNaCtrs_1_48 : 4'h0)</a>
+<a name="1772"><span class="lineNum">    1772 </span>            :     | (io_update_bits_pc[7:1] == 7'h31 ? useAltOnNaCtrs_1_49 : 4'h0)</a>
+<a name="1773"><span class="lineNum">    1773 </span>            :     | (io_update_bits_pc[7:1] == 7'h32 ? useAltOnNaCtrs_1_50 : 4'h0)</a>
+<a name="1774"><span class="lineNum">    1774 </span>            :     | (io_update_bits_pc[7:1] == 7'h33 ? useAltOnNaCtrs_1_51 : 4'h0)</a>
+<a name="1775"><span class="lineNum">    1775 </span>            :     | (io_update_bits_pc[7:1] == 7'h34 ? useAltOnNaCtrs_1_52 : 4'h0)</a>
+<a name="1776"><span class="lineNum">    1776 </span>            :     | (io_update_bits_pc[7:1] == 7'h35 ? useAltOnNaCtrs_1_53 : 4'h0)</a>
+<a name="1777"><span class="lineNum">    1777 </span>            :     | (io_update_bits_pc[7:1] == 7'h36 ? useAltOnNaCtrs_1_54 : 4'h0)</a>
+<a name="1778"><span class="lineNum">    1778 </span>            :     | (io_update_bits_pc[7:1] == 7'h37 ? useAltOnNaCtrs_1_55 : 4'h0)</a>
+<a name="1779"><span class="lineNum">    1779 </span>            :     | (io_update_bits_pc[7:1] == 7'h38 ? useAltOnNaCtrs_1_56 : 4'h0)</a>
+<a name="1780"><span class="lineNum">    1780 </span>            :     | (io_update_bits_pc[7:1] == 7'h39 ? useAltOnNaCtrs_1_57 : 4'h0)</a>
+<a name="1781"><span class="lineNum">    1781 </span>            :     | (io_update_bits_pc[7:1] == 7'h3A ? useAltOnNaCtrs_1_58 : 4'h0)</a>
+<a name="1782"><span class="lineNum">    1782 </span>            :     | (io_update_bits_pc[7:1] == 7'h3B ? useAltOnNaCtrs_1_59 : 4'h0)</a>
+<a name="1783"><span class="lineNum">    1783 </span>            :     | (io_update_bits_pc[7:1] == 7'h3C ? useAltOnNaCtrs_1_60 : 4'h0)</a>
+<a name="1784"><span class="lineNum">    1784 </span>            :     | (io_update_bits_pc[7:1] == 7'h3D ? useAltOnNaCtrs_1_61 : 4'h0)</a>
+<a name="1785"><span class="lineNum">    1785 </span>            :     | (io_update_bits_pc[7:1] == 7'h3E ? useAltOnNaCtrs_1_62 : 4'h0)</a>
+<a name="1786"><span class="lineNum">    1786 </span>            :     | (io_update_bits_pc[7:1] == 7'h3F ? useAltOnNaCtrs_1_63 : 4'h0)</a>
+<a name="1787"><span class="lineNum">    1787 </span>            :     | (io_update_bits_pc[7:1] == 7'h40 ? useAltOnNaCtrs_1_64 : 4'h0)</a>
+<a name="1788"><span class="lineNum">    1788 </span>            :     | (io_update_bits_pc[7:1] == 7'h41 ? useAltOnNaCtrs_1_65 : 4'h0)</a>
+<a name="1789"><span class="lineNum">    1789 </span>            :     | (io_update_bits_pc[7:1] == 7'h42 ? useAltOnNaCtrs_1_66 : 4'h0)</a>
+<a name="1790"><span class="lineNum">    1790 </span>            :     | (io_update_bits_pc[7:1] == 7'h43 ? useAltOnNaCtrs_1_67 : 4'h0)</a>
+<a name="1791"><span class="lineNum">    1791 </span>            :     | (io_update_bits_pc[7:1] == 7'h44 ? useAltOnNaCtrs_1_68 : 4'h0)</a>
+<a name="1792"><span class="lineNum">    1792 </span>            :     | (io_update_bits_pc[7:1] == 7'h45 ? useAltOnNaCtrs_1_69 : 4'h0)</a>
+<a name="1793"><span class="lineNum">    1793 </span>            :     | (io_update_bits_pc[7:1] == 7'h46 ? useAltOnNaCtrs_1_70 : 4'h0)</a>
+<a name="1794"><span class="lineNum">    1794 </span>            :     | (io_update_bits_pc[7:1] == 7'h47 ? useAltOnNaCtrs_1_71 : 4'h0)</a>
+<a name="1795"><span class="lineNum">    1795 </span>            :     | (io_update_bits_pc[7:1] == 7'h48 ? useAltOnNaCtrs_1_72 : 4'h0)</a>
+<a name="1796"><span class="lineNum">    1796 </span>            :     | (io_update_bits_pc[7:1] == 7'h49 ? useAltOnNaCtrs_1_73 : 4'h0)</a>
+<a name="1797"><span class="lineNum">    1797 </span>            :     | (io_update_bits_pc[7:1] == 7'h4A ? useAltOnNaCtrs_1_74 : 4'h0)</a>
+<a name="1798"><span class="lineNum">    1798 </span>            :     | (io_update_bits_pc[7:1] == 7'h4B ? useAltOnNaCtrs_1_75 : 4'h0)</a>
+<a name="1799"><span class="lineNum">    1799 </span>            :     | (io_update_bits_pc[7:1] == 7'h4C ? useAltOnNaCtrs_1_76 : 4'h0)</a>
+<a name="1800"><span class="lineNum">    1800 </span>            :     | (io_update_bits_pc[7:1] == 7'h4D ? useAltOnNaCtrs_1_77 : 4'h0)</a>
+<a name="1801"><span class="lineNum">    1801 </span>            :     | (io_update_bits_pc[7:1] == 7'h4E ? useAltOnNaCtrs_1_78 : 4'h0)</a>
+<a name="1802"><span class="lineNum">    1802 </span>            :     | (io_update_bits_pc[7:1] == 7'h4F ? useAltOnNaCtrs_1_79 : 4'h0)</a>
+<a name="1803"><span class="lineNum">    1803 </span>            :     | (io_update_bits_pc[7:1] == 7'h50 ? useAltOnNaCtrs_1_80 : 4'h0)</a>
+<a name="1804"><span class="lineNum">    1804 </span>            :     | (io_update_bits_pc[7:1] == 7'h51 ? useAltOnNaCtrs_1_81 : 4'h0)</a>
+<a name="1805"><span class="lineNum">    1805 </span>            :     | (io_update_bits_pc[7:1] == 7'h52 ? useAltOnNaCtrs_1_82 : 4'h0)</a>
+<a name="1806"><span class="lineNum">    1806 </span>            :     | (io_update_bits_pc[7:1] == 7'h53 ? useAltOnNaCtrs_1_83 : 4'h0)</a>
+<a name="1807"><span class="lineNum">    1807 </span>            :     | (io_update_bits_pc[7:1] == 7'h54 ? useAltOnNaCtrs_1_84 : 4'h0)</a>
+<a name="1808"><span class="lineNum">    1808 </span>            :     | (io_update_bits_pc[7:1] == 7'h55 ? useAltOnNaCtrs_1_85 : 4'h0)</a>
+<a name="1809"><span class="lineNum">    1809 </span>            :     | (io_update_bits_pc[7:1] == 7'h56 ? useAltOnNaCtrs_1_86 : 4'h0)</a>
+<a name="1810"><span class="lineNum">    1810 </span>            :     | (io_update_bits_pc[7:1] == 7'h57 ? useAltOnNaCtrs_1_87 : 4'h0)</a>
+<a name="1811"><span class="lineNum">    1811 </span>            :     | (io_update_bits_pc[7:1] == 7'h58 ? useAltOnNaCtrs_1_88 : 4'h0)</a>
+<a name="1812"><span class="lineNum">    1812 </span>            :     | (io_update_bits_pc[7:1] == 7'h59 ? useAltOnNaCtrs_1_89 : 4'h0)</a>
+<a name="1813"><span class="lineNum">    1813 </span>            :     | (io_update_bits_pc[7:1] == 7'h5A ? useAltOnNaCtrs_1_90 : 4'h0)</a>
+<a name="1814"><span class="lineNum">    1814 </span>            :     | (io_update_bits_pc[7:1] == 7'h5B ? useAltOnNaCtrs_1_91 : 4'h0)</a>
+<a name="1815"><span class="lineNum">    1815 </span>            :     | (io_update_bits_pc[7:1] == 7'h5C ? useAltOnNaCtrs_1_92 : 4'h0)</a>
+<a name="1816"><span class="lineNum">    1816 </span>            :     | (io_update_bits_pc[7:1] == 7'h5D ? useAltOnNaCtrs_1_93 : 4'h0)</a>
+<a name="1817"><span class="lineNum">    1817 </span>            :     | (io_update_bits_pc[7:1] == 7'h5E ? useAltOnNaCtrs_1_94 : 4'h0)</a>
+<a name="1818"><span class="lineNum">    1818 </span>            :     | (io_update_bits_pc[7:1] == 7'h5F ? useAltOnNaCtrs_1_95 : 4'h0)</a>
+<a name="1819"><span class="lineNum">    1819 </span>            :     | (io_update_bits_pc[7:1] == 7'h60 ? useAltOnNaCtrs_1_96 : 4'h0)</a>
+<a name="1820"><span class="lineNum">    1820 </span>            :     | (io_update_bits_pc[7:1] == 7'h61 ? useAltOnNaCtrs_1_97 : 4'h0)</a>
+<a name="1821"><span class="lineNum">    1821 </span>            :     | (io_update_bits_pc[7:1] == 7'h62 ? useAltOnNaCtrs_1_98 : 4'h0)</a>
+<a name="1822"><span class="lineNum">    1822 </span>            :     | (io_update_bits_pc[7:1] == 7'h63 ? useAltOnNaCtrs_1_99 : 4'h0)</a>
+<a name="1823"><span class="lineNum">    1823 </span>            :     | (io_update_bits_pc[7:1] == 7'h64 ? useAltOnNaCtrs_1_100 : 4'h0)</a>
+<a name="1824"><span class="lineNum">    1824 </span>            :     | (io_update_bits_pc[7:1] == 7'h65 ? useAltOnNaCtrs_1_101 : 4'h0)</a>
+<a name="1825"><span class="lineNum">    1825 </span>            :     | (io_update_bits_pc[7:1] == 7'h66 ? useAltOnNaCtrs_1_102 : 4'h0)</a>
+<a name="1826"><span class="lineNum">    1826 </span>            :     | (io_update_bits_pc[7:1] == 7'h67 ? useAltOnNaCtrs_1_103 : 4'h0)</a>
+<a name="1827"><span class="lineNum">    1827 </span>            :     | (io_update_bits_pc[7:1] == 7'h68 ? useAltOnNaCtrs_1_104 : 4'h0)</a>
+<a name="1828"><span class="lineNum">    1828 </span>            :     | (io_update_bits_pc[7:1] == 7'h69 ? useAltOnNaCtrs_1_105 : 4'h0)</a>
+<a name="1829"><span class="lineNum">    1829 </span>            :     | (io_update_bits_pc[7:1] == 7'h6A ? useAltOnNaCtrs_1_106 : 4'h0)</a>
+<a name="1830"><span class="lineNum">    1830 </span>            :     | (io_update_bits_pc[7:1] == 7'h6B ? useAltOnNaCtrs_1_107 : 4'h0)</a>
+<a name="1831"><span class="lineNum">    1831 </span>            :     | (io_update_bits_pc[7:1] == 7'h6C ? useAltOnNaCtrs_1_108 : 4'h0)</a>
+<a name="1832"><span class="lineNum">    1832 </span>            :     | (io_update_bits_pc[7:1] == 7'h6D ? useAltOnNaCtrs_1_109 : 4'h0)</a>
+<a name="1833"><span class="lineNum">    1833 </span>            :     | (io_update_bits_pc[7:1] == 7'h6E ? useAltOnNaCtrs_1_110 : 4'h0)</a>
+<a name="1834"><span class="lineNum">    1834 </span>            :     | (io_update_bits_pc[7:1] == 7'h6F ? useAltOnNaCtrs_1_111 : 4'h0)</a>
+<a name="1835"><span class="lineNum">    1835 </span>            :     | (io_update_bits_pc[7:1] == 7'h70 ? useAltOnNaCtrs_1_112 : 4'h0)</a>
+<a name="1836"><span class="lineNum">    1836 </span>            :     | (io_update_bits_pc[7:1] == 7'h71 ? useAltOnNaCtrs_1_113 : 4'h0)</a>
+<a name="1837"><span class="lineNum">    1837 </span>            :     | (io_update_bits_pc[7:1] == 7'h72 ? useAltOnNaCtrs_1_114 : 4'h0)</a>
+<a name="1838"><span class="lineNum">    1838 </span>            :     | (io_update_bits_pc[7:1] == 7'h73 ? useAltOnNaCtrs_1_115 : 4'h0)</a>
+<a name="1839"><span class="lineNum">    1839 </span>            :     | (io_update_bits_pc[7:1] == 7'h74 ? useAltOnNaCtrs_1_116 : 4'h0)</a>
+<a name="1840"><span class="lineNum">    1840 </span>            :     | (io_update_bits_pc[7:1] == 7'h75 ? useAltOnNaCtrs_1_117 : 4'h0)</a>
+<a name="1841"><span class="lineNum">    1841 </span>            :     | (io_update_bits_pc[7:1] == 7'h76 ? useAltOnNaCtrs_1_118 : 4'h0)</a>
+<a name="1842"><span class="lineNum">    1842 </span>            :     | (io_update_bits_pc[7:1] == 7'h77 ? useAltOnNaCtrs_1_119 : 4'h0)</a>
+<a name="1843"><span class="lineNum">    1843 </span>            :     | (io_update_bits_pc[7:1] == 7'h78 ? useAltOnNaCtrs_1_120 : 4'h0)</a>
+<a name="1844"><span class="lineNum">    1844 </span>            :     | (io_update_bits_pc[7:1] == 7'h79 ? useAltOnNaCtrs_1_121 : 4'h0)</a>
+<a name="1845"><span class="lineNum">    1845 </span>            :     | (io_update_bits_pc[7:1] == 7'h7A ? useAltOnNaCtrs_1_122 : 4'h0)</a>
+<a name="1846"><span class="lineNum">    1846 </span>            :     | (io_update_bits_pc[7:1] == 7'h7B ? useAltOnNaCtrs_1_123 : 4'h0)</a>
+<a name="1847"><span class="lineNum">    1847 </span>            :     | (io_update_bits_pc[7:1] == 7'h7C ? useAltOnNaCtrs_1_124 : 4'h0)</a>
+<a name="1848"><span class="lineNum">    1848 </span>            :     | (io_update_bits_pc[7:1] == 7'h7D ? useAltOnNaCtrs_1_125 : 4'h0)</a>
+<a name="1849"><span class="lineNum">    1849 </span>            :     | (io_update_bits_pc[7:1] == 7'h7E ? useAltOnNaCtrs_1_126 : 4'h0)</a>
+<a name="1850"><span class="lineNum">    1850 </span>            :     | ((&amp;(io_update_bits_pc[7:1])) ? useAltOnNaCtrs_1_127 : 4'h0);</a>
+<a name="1851"><span class="lineNum">    1851 </span><span class="lineCov">         25 :   wire        updateAltCorrect_1 = io_update_bits_meta[67] == updateTaken_1;</span></a>
+<a name="1852"><span class="lineNum">    1852 </span>            :   wire        _GEN_70 =</a>
+<a name="1853"><span class="lineNum">    1853 </span>            :     io_update_bits_meta[87]</a>
+<a name="1854"><span class="lineNum">    1854 </span>            :     &amp; (io_update_bits_meta[81:79] == 3'h4 | io_update_bits_meta[81:79] == 3'h3)</a>
+<a name="1855"><span class="lineNum">    1855 </span>            :     &amp; io_update_bits_meta[69];</a>
+<a name="1856"><span class="lineNum">    1856 </span>            :   wire        _newCtr_T_9 = (&amp;updateUseAltCtr_1) &amp; updateAltCorrect_1;</a>
+<a name="1857"><span class="lineNum">    1857 </span>            :   wire        _newCtr_T_11 = updateUseAltCtr_1 == 4'h0 &amp; ~updateAltCorrect_1;</a>
+<a name="1858"><span class="lineNum">    1858 </span>            :   wire [3:0]  _newCtr_T_12 = 4'(updateUseAltCtr_1 + 4'h1);</a>
+<a name="1859"><span class="lineNum">    1859 </span>            :   wire [3:0]  _newCtr_T_14 = 4'(updateUseAltCtr_1 - 4'h1);</a>
+<a name="1860"><span class="lineNum">    1860 </span>            :   wire [9:0]  _sumAbs_T_4 = $signed(sum) &lt; 10'sh0 ? 10'(10'h0 - sum) : sum;</a>
+<a name="1861"><span class="lineNum">    1861 </span>            :   wire [9:0]  _sumAbs_T_9 = $signed(sum_1) &lt; 10'sh0 ? 10'(10'h0 - sum_1) : sum_1;</a>
+<a name="1862"><span class="lineNum">    1862 </span><span class="lineCov">     127730 :   always @(posedge clock or posedge reset) begin</span></a>
+<a name="1863"><span class="lineNum">    1863 </span><span class="lineCov">        272 :     if (reset) begin</span></a>
+<a name="1864"><span class="lineNum">    1864 </span><span class="lineCov">        136 :       bankTickCtrDistanceToTops_0 &lt;= 7'h7F;</span></a>
+<a name="1865"><span class="lineNum">    1865 </span><span class="lineCov">        136 :       bankTickCtrDistanceToTops_1 &lt;= 7'h7F;</span></a>
+<a name="1866"><span class="lineNum">    1866 </span><span class="lineCov">        136 :       bankTickCtrs_0 &lt;= 7'h0;</span></a>
+<a name="1867"><span class="lineNum">    1867 </span><span class="lineCov">        136 :       bankTickCtrs_1 &lt;= 7'h0;</span></a>
+<a name="1868"><span class="lineNum">    1868 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_0 &lt;= 4'h8;</span></a>
+<a name="1869"><span class="lineNum">    1869 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_1 &lt;= 4'h8;</span></a>
+<a name="1870"><span class="lineNum">    1870 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_2 &lt;= 4'h8;</span></a>
+<a name="1871"><span class="lineNum">    1871 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_3 &lt;= 4'h8;</span></a>
+<a name="1872"><span class="lineNum">    1872 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_4 &lt;= 4'h8;</span></a>
+<a name="1873"><span class="lineNum">    1873 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_5 &lt;= 4'h8;</span></a>
+<a name="1874"><span class="lineNum">    1874 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_6 &lt;= 4'h8;</span></a>
+<a name="1875"><span class="lineNum">    1875 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_7 &lt;= 4'h8;</span></a>
+<a name="1876"><span class="lineNum">    1876 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_8 &lt;= 4'h8;</span></a>
+<a name="1877"><span class="lineNum">    1877 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_9 &lt;= 4'h8;</span></a>
+<a name="1878"><span class="lineNum">    1878 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_10 &lt;= 4'h8;</span></a>
+<a name="1879"><span class="lineNum">    1879 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_11 &lt;= 4'h8;</span></a>
+<a name="1880"><span class="lineNum">    1880 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_12 &lt;= 4'h8;</span></a>
+<a name="1881"><span class="lineNum">    1881 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_13 &lt;= 4'h8;</span></a>
+<a name="1882"><span class="lineNum">    1882 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_14 &lt;= 4'h8;</span></a>
+<a name="1883"><span class="lineNum">    1883 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_15 &lt;= 4'h8;</span></a>
+<a name="1884"><span class="lineNum">    1884 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_16 &lt;= 4'h8;</span></a>
+<a name="1885"><span class="lineNum">    1885 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_17 &lt;= 4'h8;</span></a>
+<a name="1886"><span class="lineNum">    1886 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_18 &lt;= 4'h8;</span></a>
+<a name="1887"><span class="lineNum">    1887 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_19 &lt;= 4'h8;</span></a>
+<a name="1888"><span class="lineNum">    1888 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_20 &lt;= 4'h8;</span></a>
+<a name="1889"><span class="lineNum">    1889 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_21 &lt;= 4'h8;</span></a>
+<a name="1890"><span class="lineNum">    1890 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_22 &lt;= 4'h8;</span></a>
+<a name="1891"><span class="lineNum">    1891 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_23 &lt;= 4'h8;</span></a>
+<a name="1892"><span class="lineNum">    1892 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_24 &lt;= 4'h8;</span></a>
+<a name="1893"><span class="lineNum">    1893 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_25 &lt;= 4'h8;</span></a>
+<a name="1894"><span class="lineNum">    1894 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_26 &lt;= 4'h8;</span></a>
+<a name="1895"><span class="lineNum">    1895 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_27 &lt;= 4'h8;</span></a>
+<a name="1896"><span class="lineNum">    1896 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_28 &lt;= 4'h8;</span></a>
+<a name="1897"><span class="lineNum">    1897 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_29 &lt;= 4'h8;</span></a>
+<a name="1898"><span class="lineNum">    1898 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_30 &lt;= 4'h8;</span></a>
+<a name="1899"><span class="lineNum">    1899 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_31 &lt;= 4'h8;</span></a>
+<a name="1900"><span class="lineNum">    1900 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_32 &lt;= 4'h8;</span></a>
+<a name="1901"><span class="lineNum">    1901 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_33 &lt;= 4'h8;</span></a>
+<a name="1902"><span class="lineNum">    1902 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_34 &lt;= 4'h8;</span></a>
+<a name="1903"><span class="lineNum">    1903 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_35 &lt;= 4'h8;</span></a>
+<a name="1904"><span class="lineNum">    1904 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_36 &lt;= 4'h8;</span></a>
+<a name="1905"><span class="lineNum">    1905 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_37 &lt;= 4'h8;</span></a>
+<a name="1906"><span class="lineNum">    1906 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_38 &lt;= 4'h8;</span></a>
+<a name="1907"><span class="lineNum">    1907 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_39 &lt;= 4'h8;</span></a>
+<a name="1908"><span class="lineNum">    1908 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_40 &lt;= 4'h8;</span></a>
+<a name="1909"><span class="lineNum">    1909 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_41 &lt;= 4'h8;</span></a>
+<a name="1910"><span class="lineNum">    1910 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_42 &lt;= 4'h8;</span></a>
+<a name="1911"><span class="lineNum">    1911 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_43 &lt;= 4'h8;</span></a>
+<a name="1912"><span class="lineNum">    1912 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_44 &lt;= 4'h8;</span></a>
+<a name="1913"><span class="lineNum">    1913 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_45 &lt;= 4'h8;</span></a>
+<a name="1914"><span class="lineNum">    1914 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_46 &lt;= 4'h8;</span></a>
+<a name="1915"><span class="lineNum">    1915 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_47 &lt;= 4'h8;</span></a>
+<a name="1916"><span class="lineNum">    1916 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_48 &lt;= 4'h8;</span></a>
+<a name="1917"><span class="lineNum">    1917 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_49 &lt;= 4'h8;</span></a>
+<a name="1918"><span class="lineNum">    1918 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_50 &lt;= 4'h8;</span></a>
+<a name="1919"><span class="lineNum">    1919 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_51 &lt;= 4'h8;</span></a>
+<a name="1920"><span class="lineNum">    1920 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_52 &lt;= 4'h8;</span></a>
+<a name="1921"><span class="lineNum">    1921 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_53 &lt;= 4'h8;</span></a>
+<a name="1922"><span class="lineNum">    1922 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_54 &lt;= 4'h8;</span></a>
+<a name="1923"><span class="lineNum">    1923 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_55 &lt;= 4'h8;</span></a>
+<a name="1924"><span class="lineNum">    1924 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_56 &lt;= 4'h8;</span></a>
+<a name="1925"><span class="lineNum">    1925 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_57 &lt;= 4'h8;</span></a>
+<a name="1926"><span class="lineNum">    1926 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_58 &lt;= 4'h8;</span></a>
+<a name="1927"><span class="lineNum">    1927 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_59 &lt;= 4'h8;</span></a>
+<a name="1928"><span class="lineNum">    1928 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_60 &lt;= 4'h8;</span></a>
+<a name="1929"><span class="lineNum">    1929 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_61 &lt;= 4'h8;</span></a>
+<a name="1930"><span class="lineNum">    1930 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_62 &lt;= 4'h8;</span></a>
+<a name="1931"><span class="lineNum">    1931 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_63 &lt;= 4'h8;</span></a>
+<a name="1932"><span class="lineNum">    1932 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_64 &lt;= 4'h8;</span></a>
+<a name="1933"><span class="lineNum">    1933 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_65 &lt;= 4'h8;</span></a>
+<a name="1934"><span class="lineNum">    1934 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_66 &lt;= 4'h8;</span></a>
+<a name="1935"><span class="lineNum">    1935 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_67 &lt;= 4'h8;</span></a>
+<a name="1936"><span class="lineNum">    1936 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_68 &lt;= 4'h8;</span></a>
+<a name="1937"><span class="lineNum">    1937 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_69 &lt;= 4'h8;</span></a>
+<a name="1938"><span class="lineNum">    1938 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_70 &lt;= 4'h8;</span></a>
+<a name="1939"><span class="lineNum">    1939 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_71 &lt;= 4'h8;</span></a>
+<a name="1940"><span class="lineNum">    1940 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_72 &lt;= 4'h8;</span></a>
+<a name="1941"><span class="lineNum">    1941 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_73 &lt;= 4'h8;</span></a>
+<a name="1942"><span class="lineNum">    1942 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_74 &lt;= 4'h8;</span></a>
+<a name="1943"><span class="lineNum">    1943 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_75 &lt;= 4'h8;</span></a>
+<a name="1944"><span class="lineNum">    1944 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_76 &lt;= 4'h8;</span></a>
+<a name="1945"><span class="lineNum">    1945 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_77 &lt;= 4'h8;</span></a>
+<a name="1946"><span class="lineNum">    1946 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_78 &lt;= 4'h8;</span></a>
+<a name="1947"><span class="lineNum">    1947 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_79 &lt;= 4'h8;</span></a>
+<a name="1948"><span class="lineNum">    1948 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_80 &lt;= 4'h8;</span></a>
+<a name="1949"><span class="lineNum">    1949 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_81 &lt;= 4'h8;</span></a>
+<a name="1950"><span class="lineNum">    1950 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_82 &lt;= 4'h8;</span></a>
+<a name="1951"><span class="lineNum">    1951 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_83 &lt;= 4'h8;</span></a>
+<a name="1952"><span class="lineNum">    1952 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_84 &lt;= 4'h8;</span></a>
+<a name="1953"><span class="lineNum">    1953 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_85 &lt;= 4'h8;</span></a>
+<a name="1954"><span class="lineNum">    1954 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_86 &lt;= 4'h8;</span></a>
+<a name="1955"><span class="lineNum">    1955 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_87 &lt;= 4'h8;</span></a>
+<a name="1956"><span class="lineNum">    1956 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_88 &lt;= 4'h8;</span></a>
+<a name="1957"><span class="lineNum">    1957 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_89 &lt;= 4'h8;</span></a>
+<a name="1958"><span class="lineNum">    1958 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_90 &lt;= 4'h8;</span></a>
+<a name="1959"><span class="lineNum">    1959 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_91 &lt;= 4'h8;</span></a>
+<a name="1960"><span class="lineNum">    1960 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_92 &lt;= 4'h8;</span></a>
+<a name="1961"><span class="lineNum">    1961 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_93 &lt;= 4'h8;</span></a>
+<a name="1962"><span class="lineNum">    1962 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_94 &lt;= 4'h8;</span></a>
+<a name="1963"><span class="lineNum">    1963 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_95 &lt;= 4'h8;</span></a>
+<a name="1964"><span class="lineNum">    1964 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_96 &lt;= 4'h8;</span></a>
+<a name="1965"><span class="lineNum">    1965 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_97 &lt;= 4'h8;</span></a>
+<a name="1966"><span class="lineNum">    1966 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_98 &lt;= 4'h8;</span></a>
+<a name="1967"><span class="lineNum">    1967 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_99 &lt;= 4'h8;</span></a>
+<a name="1968"><span class="lineNum">    1968 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_100 &lt;= 4'h8;</span></a>
+<a name="1969"><span class="lineNum">    1969 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_101 &lt;= 4'h8;</span></a>
+<a name="1970"><span class="lineNum">    1970 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_102 &lt;= 4'h8;</span></a>
+<a name="1971"><span class="lineNum">    1971 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_103 &lt;= 4'h8;</span></a>
+<a name="1972"><span class="lineNum">    1972 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_104 &lt;= 4'h8;</span></a>
+<a name="1973"><span class="lineNum">    1973 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_105 &lt;= 4'h8;</span></a>
+<a name="1974"><span class="lineNum">    1974 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_106 &lt;= 4'h8;</span></a>
+<a name="1975"><span class="lineNum">    1975 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_107 &lt;= 4'h8;</span></a>
+<a name="1976"><span class="lineNum">    1976 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_108 &lt;= 4'h8;</span></a>
+<a name="1977"><span class="lineNum">    1977 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_109 &lt;= 4'h8;</span></a>
+<a name="1978"><span class="lineNum">    1978 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_110 &lt;= 4'h8;</span></a>
+<a name="1979"><span class="lineNum">    1979 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_111 &lt;= 4'h8;</span></a>
+<a name="1980"><span class="lineNum">    1980 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_112 &lt;= 4'h8;</span></a>
+<a name="1981"><span class="lineNum">    1981 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_113 &lt;= 4'h8;</span></a>
+<a name="1982"><span class="lineNum">    1982 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_114 &lt;= 4'h8;</span></a>
+<a name="1983"><span class="lineNum">    1983 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_115 &lt;= 4'h8;</span></a>
+<a name="1984"><span class="lineNum">    1984 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_116 &lt;= 4'h8;</span></a>
+<a name="1985"><span class="lineNum">    1985 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_117 &lt;= 4'h8;</span></a>
+<a name="1986"><span class="lineNum">    1986 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_118 &lt;= 4'h8;</span></a>
+<a name="1987"><span class="lineNum">    1987 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_119 &lt;= 4'h8;</span></a>
+<a name="1988"><span class="lineNum">    1988 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_120 &lt;= 4'h8;</span></a>
+<a name="1989"><span class="lineNum">    1989 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_121 &lt;= 4'h8;</span></a>
+<a name="1990"><span class="lineNum">    1990 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_122 &lt;= 4'h8;</span></a>
+<a name="1991"><span class="lineNum">    1991 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_123 &lt;= 4'h8;</span></a>
+<a name="1992"><span class="lineNum">    1992 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_124 &lt;= 4'h8;</span></a>
+<a name="1993"><span class="lineNum">    1993 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_125 &lt;= 4'h8;</span></a>
+<a name="1994"><span class="lineNum">    1994 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_126 &lt;= 4'h8;</span></a>
+<a name="1995"><span class="lineNum">    1995 </span><span class="lineCov">        136 :       useAltOnNaCtrs_0_127 &lt;= 4'h8;</span></a>
+<a name="1996"><span class="lineNum">    1996 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_0 &lt;= 4'h8;</span></a>
+<a name="1997"><span class="lineNum">    1997 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_1 &lt;= 4'h8;</span></a>
+<a name="1998"><span class="lineNum">    1998 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_2 &lt;= 4'h8;</span></a>
+<a name="1999"><span class="lineNum">    1999 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_3 &lt;= 4'h8;</span></a>
+<a name="2000"><span class="lineNum">    2000 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_4 &lt;= 4'h8;</span></a>
+<a name="2001"><span class="lineNum">    2001 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_5 &lt;= 4'h8;</span></a>
+<a name="2002"><span class="lineNum">    2002 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_6 &lt;= 4'h8;</span></a>
+<a name="2003"><span class="lineNum">    2003 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_7 &lt;= 4'h8;</span></a>
+<a name="2004"><span class="lineNum">    2004 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_8 &lt;= 4'h8;</span></a>
+<a name="2005"><span class="lineNum">    2005 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_9 &lt;= 4'h8;</span></a>
+<a name="2006"><span class="lineNum">    2006 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_10 &lt;= 4'h8;</span></a>
+<a name="2007"><span class="lineNum">    2007 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_11 &lt;= 4'h8;</span></a>
+<a name="2008"><span class="lineNum">    2008 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_12 &lt;= 4'h8;</span></a>
+<a name="2009"><span class="lineNum">    2009 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_13 &lt;= 4'h8;</span></a>
+<a name="2010"><span class="lineNum">    2010 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_14 &lt;= 4'h8;</span></a>
+<a name="2011"><span class="lineNum">    2011 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_15 &lt;= 4'h8;</span></a>
+<a name="2012"><span class="lineNum">    2012 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_16 &lt;= 4'h8;</span></a>
+<a name="2013"><span class="lineNum">    2013 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_17 &lt;= 4'h8;</span></a>
+<a name="2014"><span class="lineNum">    2014 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_18 &lt;= 4'h8;</span></a>
+<a name="2015"><span class="lineNum">    2015 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_19 &lt;= 4'h8;</span></a>
+<a name="2016"><span class="lineNum">    2016 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_20 &lt;= 4'h8;</span></a>
+<a name="2017"><span class="lineNum">    2017 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_21 &lt;= 4'h8;</span></a>
+<a name="2018"><span class="lineNum">    2018 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_22 &lt;= 4'h8;</span></a>
+<a name="2019"><span class="lineNum">    2019 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_23 &lt;= 4'h8;</span></a>
+<a name="2020"><span class="lineNum">    2020 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_24 &lt;= 4'h8;</span></a>
+<a name="2021"><span class="lineNum">    2021 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_25 &lt;= 4'h8;</span></a>
+<a name="2022"><span class="lineNum">    2022 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_26 &lt;= 4'h8;</span></a>
+<a name="2023"><span class="lineNum">    2023 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_27 &lt;= 4'h8;</span></a>
+<a name="2024"><span class="lineNum">    2024 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_28 &lt;= 4'h8;</span></a>
+<a name="2025"><span class="lineNum">    2025 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_29 &lt;= 4'h8;</span></a>
+<a name="2026"><span class="lineNum">    2026 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_30 &lt;= 4'h8;</span></a>
+<a name="2027"><span class="lineNum">    2027 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_31 &lt;= 4'h8;</span></a>
+<a name="2028"><span class="lineNum">    2028 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_32 &lt;= 4'h8;</span></a>
+<a name="2029"><span class="lineNum">    2029 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_33 &lt;= 4'h8;</span></a>
+<a name="2030"><span class="lineNum">    2030 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_34 &lt;= 4'h8;</span></a>
+<a name="2031"><span class="lineNum">    2031 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_35 &lt;= 4'h8;</span></a>
+<a name="2032"><span class="lineNum">    2032 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_36 &lt;= 4'h8;</span></a>
+<a name="2033"><span class="lineNum">    2033 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_37 &lt;= 4'h8;</span></a>
+<a name="2034"><span class="lineNum">    2034 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_38 &lt;= 4'h8;</span></a>
+<a name="2035"><span class="lineNum">    2035 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_39 &lt;= 4'h8;</span></a>
+<a name="2036"><span class="lineNum">    2036 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_40 &lt;= 4'h8;</span></a>
+<a name="2037"><span class="lineNum">    2037 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_41 &lt;= 4'h8;</span></a>
+<a name="2038"><span class="lineNum">    2038 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_42 &lt;= 4'h8;</span></a>
+<a name="2039"><span class="lineNum">    2039 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_43 &lt;= 4'h8;</span></a>
+<a name="2040"><span class="lineNum">    2040 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_44 &lt;= 4'h8;</span></a>
+<a name="2041"><span class="lineNum">    2041 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_45 &lt;= 4'h8;</span></a>
+<a name="2042"><span class="lineNum">    2042 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_46 &lt;= 4'h8;</span></a>
+<a name="2043"><span class="lineNum">    2043 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_47 &lt;= 4'h8;</span></a>
+<a name="2044"><span class="lineNum">    2044 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_48 &lt;= 4'h8;</span></a>
+<a name="2045"><span class="lineNum">    2045 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_49 &lt;= 4'h8;</span></a>
+<a name="2046"><span class="lineNum">    2046 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_50 &lt;= 4'h8;</span></a>
+<a name="2047"><span class="lineNum">    2047 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_51 &lt;= 4'h8;</span></a>
+<a name="2048"><span class="lineNum">    2048 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_52 &lt;= 4'h8;</span></a>
+<a name="2049"><span class="lineNum">    2049 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_53 &lt;= 4'h8;</span></a>
+<a name="2050"><span class="lineNum">    2050 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_54 &lt;= 4'h8;</span></a>
+<a name="2051"><span class="lineNum">    2051 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_55 &lt;= 4'h8;</span></a>
+<a name="2052"><span class="lineNum">    2052 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_56 &lt;= 4'h8;</span></a>
+<a name="2053"><span class="lineNum">    2053 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_57 &lt;= 4'h8;</span></a>
+<a name="2054"><span class="lineNum">    2054 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_58 &lt;= 4'h8;</span></a>
+<a name="2055"><span class="lineNum">    2055 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_59 &lt;= 4'h8;</span></a>
+<a name="2056"><span class="lineNum">    2056 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_60 &lt;= 4'h8;</span></a>
+<a name="2057"><span class="lineNum">    2057 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_61 &lt;= 4'h8;</span></a>
+<a name="2058"><span class="lineNum">    2058 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_62 &lt;= 4'h8;</span></a>
+<a name="2059"><span class="lineNum">    2059 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_63 &lt;= 4'h8;</span></a>
+<a name="2060"><span class="lineNum">    2060 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_64 &lt;= 4'h8;</span></a>
+<a name="2061"><span class="lineNum">    2061 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_65 &lt;= 4'h8;</span></a>
+<a name="2062"><span class="lineNum">    2062 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_66 &lt;= 4'h8;</span></a>
+<a name="2063"><span class="lineNum">    2063 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_67 &lt;= 4'h8;</span></a>
+<a name="2064"><span class="lineNum">    2064 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_68 &lt;= 4'h8;</span></a>
+<a name="2065"><span class="lineNum">    2065 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_69 &lt;= 4'h8;</span></a>
+<a name="2066"><span class="lineNum">    2066 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_70 &lt;= 4'h8;</span></a>
+<a name="2067"><span class="lineNum">    2067 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_71 &lt;= 4'h8;</span></a>
+<a name="2068"><span class="lineNum">    2068 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_72 &lt;= 4'h8;</span></a>
+<a name="2069"><span class="lineNum">    2069 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_73 &lt;= 4'h8;</span></a>
+<a name="2070"><span class="lineNum">    2070 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_74 &lt;= 4'h8;</span></a>
+<a name="2071"><span class="lineNum">    2071 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_75 &lt;= 4'h8;</span></a>
+<a name="2072"><span class="lineNum">    2072 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_76 &lt;= 4'h8;</span></a>
+<a name="2073"><span class="lineNum">    2073 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_77 &lt;= 4'h8;</span></a>
+<a name="2074"><span class="lineNum">    2074 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_78 &lt;= 4'h8;</span></a>
+<a name="2075"><span class="lineNum">    2075 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_79 &lt;= 4'h8;</span></a>
+<a name="2076"><span class="lineNum">    2076 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_80 &lt;= 4'h8;</span></a>
+<a name="2077"><span class="lineNum">    2077 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_81 &lt;= 4'h8;</span></a>
+<a name="2078"><span class="lineNum">    2078 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_82 &lt;= 4'h8;</span></a>
+<a name="2079"><span class="lineNum">    2079 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_83 &lt;= 4'h8;</span></a>
+<a name="2080"><span class="lineNum">    2080 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_84 &lt;= 4'h8;</span></a>
+<a name="2081"><span class="lineNum">    2081 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_85 &lt;= 4'h8;</span></a>
+<a name="2082"><span class="lineNum">    2082 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_86 &lt;= 4'h8;</span></a>
+<a name="2083"><span class="lineNum">    2083 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_87 &lt;= 4'h8;</span></a>
+<a name="2084"><span class="lineNum">    2084 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_88 &lt;= 4'h8;</span></a>
+<a name="2085"><span class="lineNum">    2085 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_89 &lt;= 4'h8;</span></a>
+<a name="2086"><span class="lineNum">    2086 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_90 &lt;= 4'h8;</span></a>
+<a name="2087"><span class="lineNum">    2087 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_91 &lt;= 4'h8;</span></a>
+<a name="2088"><span class="lineNum">    2088 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_92 &lt;= 4'h8;</span></a>
+<a name="2089"><span class="lineNum">    2089 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_93 &lt;= 4'h8;</span></a>
+<a name="2090"><span class="lineNum">    2090 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_94 &lt;= 4'h8;</span></a>
+<a name="2091"><span class="lineNum">    2091 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_95 &lt;= 4'h8;</span></a>
+<a name="2092"><span class="lineNum">    2092 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_96 &lt;= 4'h8;</span></a>
+<a name="2093"><span class="lineNum">    2093 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_97 &lt;= 4'h8;</span></a>
+<a name="2094"><span class="lineNum">    2094 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_98 &lt;= 4'h8;</span></a>
+<a name="2095"><span class="lineNum">    2095 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_99 &lt;= 4'h8;</span></a>
+<a name="2096"><span class="lineNum">    2096 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_100 &lt;= 4'h8;</span></a>
+<a name="2097"><span class="lineNum">    2097 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_101 &lt;= 4'h8;</span></a>
+<a name="2098"><span class="lineNum">    2098 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_102 &lt;= 4'h8;</span></a>
+<a name="2099"><span class="lineNum">    2099 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_103 &lt;= 4'h8;</span></a>
+<a name="2100"><span class="lineNum">    2100 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_104 &lt;= 4'h8;</span></a>
+<a name="2101"><span class="lineNum">    2101 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_105 &lt;= 4'h8;</span></a>
+<a name="2102"><span class="lineNum">    2102 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_106 &lt;= 4'h8;</span></a>
+<a name="2103"><span class="lineNum">    2103 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_107 &lt;= 4'h8;</span></a>
+<a name="2104"><span class="lineNum">    2104 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_108 &lt;= 4'h8;</span></a>
+<a name="2105"><span class="lineNum">    2105 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_109 &lt;= 4'h8;</span></a>
+<a name="2106"><span class="lineNum">    2106 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_110 &lt;= 4'h8;</span></a>
+<a name="2107"><span class="lineNum">    2107 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_111 &lt;= 4'h8;</span></a>
+<a name="2108"><span class="lineNum">    2108 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_112 &lt;= 4'h8;</span></a>
+<a name="2109"><span class="lineNum">    2109 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_113 &lt;= 4'h8;</span></a>
+<a name="2110"><span class="lineNum">    2110 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_114 &lt;= 4'h8;</span></a>
+<a name="2111"><span class="lineNum">    2111 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_115 &lt;= 4'h8;</span></a>
+<a name="2112"><span class="lineNum">    2112 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_116 &lt;= 4'h8;</span></a>
+<a name="2113"><span class="lineNum">    2113 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_117 &lt;= 4'h8;</span></a>
+<a name="2114"><span class="lineNum">    2114 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_118 &lt;= 4'h8;</span></a>
+<a name="2115"><span class="lineNum">    2115 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_119 &lt;= 4'h8;</span></a>
+<a name="2116"><span class="lineNum">    2116 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_120 &lt;= 4'h8;</span></a>
+<a name="2117"><span class="lineNum">    2117 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_121 &lt;= 4'h8;</span></a>
+<a name="2118"><span class="lineNum">    2118 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_122 &lt;= 4'h8;</span></a>
+<a name="2119"><span class="lineNum">    2119 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_123 &lt;= 4'h8;</span></a>
+<a name="2120"><span class="lineNum">    2120 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_124 &lt;= 4'h8;</span></a>
+<a name="2121"><span class="lineNum">    2121 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_125 &lt;= 4'h8;</span></a>
+<a name="2122"><span class="lineNum">    2122 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_126 &lt;= 4'h8;</span></a>
+<a name="2123"><span class="lineNum">    2123 </span><span class="lineCov">        136 :       useAltOnNaCtrs_1_127 &lt;= 4'h8;</span></a>
+<a name="2124"><span class="lineNum">    2124 </span><span class="lineCov">        136 :       allocLFSR_lfsr &lt;= 64'h1234567887654321;</span></a>
+<a name="2125"><span class="lineNum">    2125 </span><span class="lineCov">        136 :       allocLFSR_lfsr_1 &lt;= 64'h1234567887654321;</span></a>
+<a name="2126"><span class="lineNum">    2126 </span><span class="lineCov">        136 :       scThresholds_0_ctr &lt;= 5'h10;</span></a>
+<a name="2127"><span class="lineNum">    2127 </span><span class="lineCov">        136 :       scThresholds_0_thres &lt;= 8'h6;</span></a>
+<a name="2128"><span class="lineNum">    2128 </span><span class="lineCov">        136 :       scThresholds_1_ctr &lt;= 5'h10;</span></a>
+<a name="2129"><span class="lineNum">    2129 </span><span class="lineCov">        136 :       scThresholds_1_thres &lt;= 8'h6;</span></a>
+<a name="2130"><span class="lineNum">    2130 </span>            :     end</a>
+<a name="2131"><span class="lineNum">    2131 </span><span class="lineCov">      63729 :     else begin</span></a>
+<a name="2132"><span class="lineNum">    2132 </span><span class="lineCov">          4 :       if (needToAllocate) begin</span></a>
+<a name="2133"><span class="lineNum">    2133 </span><span class="lineNoCov">          0 :         if (&amp;bankTickCtrs_0) begin</span></a>
+<a name="2134"><span class="lineNum">    2134 </span><span class="lineNoCov">          0 :           bankTickCtrDistanceToTops_0 &lt;= 7'h7F;</span></a>
+<a name="2135"><span class="lineNum">    2135 </span><span class="lineNoCov">          0 :           bankTickCtrs_0 &lt;= 7'h0;</span></a>
+<a name="2136"><span class="lineNum">    2136 </span>            :         end</a>
+<a name="2137"><span class="lineNum">    2137 </span><span class="lineNoCov">          0 :         else if (tickInc) begin</span></a>
+<a name="2138"><span class="lineNum">    2138 </span><span class="lineNoCov">          0 :           if (_GEN_55 &gt;= bankTickCtrDistanceToTops_0 &amp; tickInc) begin</span></a>
+<a name="2139"><span class="lineNum">    2139 </span><span class="lineNoCov">          0 :             bankTickCtrDistanceToTops_0 &lt;= 7'h0;</span></a>
+<a name="2140"><span class="lineNum">    2140 </span><span class="lineNoCov">          0 :             bankTickCtrs_0 &lt;= 7'h7F;</span></a>
+<a name="2141"><span class="lineNum">    2141 </span>            :           end</a>
+<a name="2142"><span class="lineNum">    2142 </span><span class="lineNoCov">          0 :           else begin</span></a>
+<a name="2143"><span class="lineNum">    2143 </span><span class="lineNoCov">          0 :             bankTickCtrDistanceToTops_0 &lt;= 7'(bankTickCtrDistanceToTops_0 - _GEN_55);</span></a>
+<a name="2144"><span class="lineNum">    2144 </span><span class="lineNoCov">          0 :             bankTickCtrs_0 &lt;= 7'(bankTickCtrs_0 + _GEN_55);</span></a>
+<a name="2145"><span class="lineNum">    2145 </span>            :           end</a>
+<a name="2146"><span class="lineNum">    2146 </span>            :         end</a>
+<a name="2147"><span class="lineNum">    2147 </span><span class="lineCov">          1 :         else if (tickDec) begin</span></a>
+<a name="2148"><span class="lineNum">    2148 </span><span class="lineNoCov">          0 :           if (_GEN_56 &gt;= bankTickCtrs_0 &amp; tickDec) begin</span></a>
+<a name="2149"><span class="lineNum">    2149 </span><span class="lineNoCov">          0 :             bankTickCtrDistanceToTops_0 &lt;= 7'h7F;</span></a>
+<a name="2150"><span class="lineNum">    2150 </span><span class="lineNoCov">          0 :             bankTickCtrs_0 &lt;= 7'h0;</span></a>
+<a name="2151"><span class="lineNum">    2151 </span>            :           end</a>
+<a name="2152"><span class="lineNum">    2152 </span><span class="lineCov">          1 :           else begin</span></a>
+<a name="2153"><span class="lineNum">    2153 </span><span class="lineCov">          1 :             bankTickCtrDistanceToTops_0 &lt;= 7'(bankTickCtrDistanceToTops_0 + _GEN_56);</span></a>
+<a name="2154"><span class="lineNum">    2154 </span><span class="lineCov">          1 :             bankTickCtrs_0 &lt;= 7'(bankTickCtrs_0 - _GEN_56);</span></a>
+<a name="2155"><span class="lineNum">    2155 </span>            :           end</a>
+<a name="2156"><span class="lineNum">    2156 </span>            :         end</a>
+<a name="2157"><span class="lineNum">    2157 </span>            :       end</a>
+<a name="2158"><span class="lineNum">    2158 </span><span class="lineCov">          2 :       if (needToAllocate_1) begin</span></a>
+<a name="2159"><span class="lineNum">    2159 </span><span class="lineNoCov">          0 :         if (&amp;bankTickCtrs_1) begin</span></a>
+<a name="2160"><span class="lineNum">    2160 </span><span class="lineNoCov">          0 :           bankTickCtrDistanceToTops_1 &lt;= 7'h7F;</span></a>
+<a name="2161"><span class="lineNum">    2161 </span><span class="lineNoCov">          0 :           bankTickCtrs_1 &lt;= 7'h0;</span></a>
+<a name="2162"><span class="lineNum">    2162 </span>            :         end</a>
+<a name="2163"><span class="lineNum">    2163 </span><span class="lineCov">          2 :         else if (tickInc_1) begin</span></a>
+<a name="2164"><span class="lineNum">    2164 </span><span class="lineNoCov">          0 :           if (_GEN_65 &gt;= bankTickCtrDistanceToTops_1 &amp; tickInc_1) begin</span></a>
+<a name="2165"><span class="lineNum">    2165 </span><span class="lineNoCov">          0 :             bankTickCtrDistanceToTops_1 &lt;= 7'h0;</span></a>
+<a name="2166"><span class="lineNum">    2166 </span><span class="lineNoCov">          0 :             bankTickCtrs_1 &lt;= 7'h7F;</span></a>
+<a name="2167"><span class="lineNum">    2167 </span>            :           end</a>
+<a name="2168"><span class="lineNum">    2168 </span><span class="lineCov">          1 :           else begin</span></a>
+<a name="2169"><span class="lineNum">    2169 </span><span class="lineCov">          1 :             bankTickCtrDistanceToTops_1 &lt;= 7'(bankTickCtrDistanceToTops_1 - _GEN_65);</span></a>
+<a name="2170"><span class="lineNum">    2170 </span><span class="lineCov">          1 :             bankTickCtrs_1 &lt;= 7'(bankTickCtrs_1 + _GEN_65);</span></a>
+<a name="2171"><span class="lineNum">    2171 </span>            :           end</a>
+<a name="2172"><span class="lineNum">    2172 </span>            :         end</a>
+<a name="2173"><span class="lineNum">    2173 </span><span class="lineNoCov">          0 :         else if (tickDec_1) begin</span></a>
+<a name="2174"><span class="lineNum">    2174 </span><span class="lineNoCov">          0 :           if (_GEN_66 &gt;= bankTickCtrs_1 &amp; tickDec_1) begin</span></a>
+<a name="2175"><span class="lineNum">    2175 </span><span class="lineNoCov">          0 :             bankTickCtrDistanceToTops_1 &lt;= 7'h7F;</span></a>
+<a name="2176"><span class="lineNum">    2176 </span><span class="lineNoCov">          0 :             bankTickCtrs_1 &lt;= 7'h0;</span></a>
+<a name="2177"><span class="lineNum">    2177 </span>            :           end</a>
+<a name="2178"><span class="lineNum">    2178 </span><span class="lineNoCov">          0 :           else begin</span></a>
+<a name="2179"><span class="lineNum">    2179 </span><span class="lineNoCov">          0 :             bankTickCtrDistanceToTops_1 &lt;= 7'(bankTickCtrDistanceToTops_1 + _GEN_66);</span></a>
+<a name="2180"><span class="lineNum">    2180 </span><span class="lineNoCov">          0 :             bankTickCtrs_1 &lt;= 7'(bankTickCtrs_1 - _GEN_66);</span></a>
+<a name="2181"><span class="lineNum">    2181 </span>            :           end</a>
+<a name="2182"><span class="lineNum">    2182 </span>            :         end</a>
+<a name="2183"><span class="lineNum">    2183 </span>            :       end</a>
+<a name="2184"><span class="lineNum">    2184 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h0) begin</span></a>
+<a name="2185"><span class="lineNum">    2185 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2186"><span class="lineNum">    2186 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_0 &lt;= 4'hF;</span></a>
+<a name="2187"><span class="lineNum">    2187 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2188"><span class="lineNum">    2188 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_0 &lt;= 4'h0;</span></a>
+<a name="2189"><span class="lineNum">    2189 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2190"><span class="lineNum">    2190 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_0 &lt;= _newCtr_T_3;</span></a>
+<a name="2191"><span class="lineNum">    2191 </span>            :         else</a>
+<a name="2192"><span class="lineNum">    2192 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_0 &lt;= _newCtr_T_5;</span></a>
+<a name="2193"><span class="lineNum">    2193 </span>            :       end</a>
+<a name="2194"><span class="lineNum">    2194 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h1) begin</span></a>
+<a name="2195"><span class="lineNum">    2195 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2196"><span class="lineNum">    2196 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_1 &lt;= 4'hF;</span></a>
+<a name="2197"><span class="lineNum">    2197 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2198"><span class="lineNum">    2198 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_1 &lt;= 4'h0;</span></a>
+<a name="2199"><span class="lineNum">    2199 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2200"><span class="lineNum">    2200 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_1 &lt;= _newCtr_T_3;</span></a>
+<a name="2201"><span class="lineNum">    2201 </span>            :         else</a>
+<a name="2202"><span class="lineNum">    2202 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_1 &lt;= _newCtr_T_5;</span></a>
+<a name="2203"><span class="lineNum">    2203 </span>            :       end</a>
+<a name="2204"><span class="lineNum">    2204 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h2) begin</span></a>
+<a name="2205"><span class="lineNum">    2205 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2206"><span class="lineNum">    2206 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_2 &lt;= 4'hF;</span></a>
+<a name="2207"><span class="lineNum">    2207 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2208"><span class="lineNum">    2208 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_2 &lt;= 4'h0;</span></a>
+<a name="2209"><span class="lineNum">    2209 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2210"><span class="lineNum">    2210 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_2 &lt;= _newCtr_T_3;</span></a>
+<a name="2211"><span class="lineNum">    2211 </span>            :         else</a>
+<a name="2212"><span class="lineNum">    2212 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_2 &lt;= _newCtr_T_5;</span></a>
+<a name="2213"><span class="lineNum">    2213 </span>            :       end</a>
+<a name="2214"><span class="lineNum">    2214 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h3) begin</span></a>
+<a name="2215"><span class="lineNum">    2215 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2216"><span class="lineNum">    2216 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_3 &lt;= 4'hF;</span></a>
+<a name="2217"><span class="lineNum">    2217 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2218"><span class="lineNum">    2218 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_3 &lt;= 4'h0;</span></a>
+<a name="2219"><span class="lineNum">    2219 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2220"><span class="lineNum">    2220 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_3 &lt;= _newCtr_T_3;</span></a>
+<a name="2221"><span class="lineNum">    2221 </span>            :         else</a>
+<a name="2222"><span class="lineNum">    2222 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_3 &lt;= _newCtr_T_5;</span></a>
+<a name="2223"><span class="lineNum">    2223 </span>            :       end</a>
+<a name="2224"><span class="lineNum">    2224 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h4) begin</span></a>
+<a name="2225"><span class="lineNum">    2225 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2226"><span class="lineNum">    2226 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_4 &lt;= 4'hF;</span></a>
+<a name="2227"><span class="lineNum">    2227 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2228"><span class="lineNum">    2228 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_4 &lt;= 4'h0;</span></a>
+<a name="2229"><span class="lineNum">    2229 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2230"><span class="lineNum">    2230 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_4 &lt;= _newCtr_T_3;</span></a>
+<a name="2231"><span class="lineNum">    2231 </span>            :         else</a>
+<a name="2232"><span class="lineNum">    2232 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_4 &lt;= _newCtr_T_5;</span></a>
+<a name="2233"><span class="lineNum">    2233 </span>            :       end</a>
+<a name="2234"><span class="lineNum">    2234 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h5) begin</span></a>
+<a name="2235"><span class="lineNum">    2235 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2236"><span class="lineNum">    2236 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_5 &lt;= 4'hF;</span></a>
+<a name="2237"><span class="lineNum">    2237 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2238"><span class="lineNum">    2238 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_5 &lt;= 4'h0;</span></a>
+<a name="2239"><span class="lineNum">    2239 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2240"><span class="lineNum">    2240 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_5 &lt;= _newCtr_T_3;</span></a>
+<a name="2241"><span class="lineNum">    2241 </span>            :         else</a>
+<a name="2242"><span class="lineNum">    2242 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_5 &lt;= _newCtr_T_5;</span></a>
+<a name="2243"><span class="lineNum">    2243 </span>            :       end</a>
+<a name="2244"><span class="lineNum">    2244 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h6) begin</span></a>
+<a name="2245"><span class="lineNum">    2245 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2246"><span class="lineNum">    2246 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_6 &lt;= 4'hF;</span></a>
+<a name="2247"><span class="lineNum">    2247 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2248"><span class="lineNum">    2248 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_6 &lt;= 4'h0;</span></a>
+<a name="2249"><span class="lineNum">    2249 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2250"><span class="lineNum">    2250 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_6 &lt;= _newCtr_T_3;</span></a>
+<a name="2251"><span class="lineNum">    2251 </span>            :         else</a>
+<a name="2252"><span class="lineNum">    2252 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_6 &lt;= _newCtr_T_5;</span></a>
+<a name="2253"><span class="lineNum">    2253 </span>            :       end</a>
+<a name="2254"><span class="lineNum">    2254 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h7) begin</span></a>
+<a name="2255"><span class="lineNum">    2255 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2256"><span class="lineNum">    2256 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_7 &lt;= 4'hF;</span></a>
+<a name="2257"><span class="lineNum">    2257 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2258"><span class="lineNum">    2258 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_7 &lt;= 4'h0;</span></a>
+<a name="2259"><span class="lineNum">    2259 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2260"><span class="lineNum">    2260 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_7 &lt;= _newCtr_T_3;</span></a>
+<a name="2261"><span class="lineNum">    2261 </span>            :         else</a>
+<a name="2262"><span class="lineNum">    2262 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_7 &lt;= _newCtr_T_5;</span></a>
+<a name="2263"><span class="lineNum">    2263 </span>            :       end</a>
+<a name="2264"><span class="lineNum">    2264 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h8) begin</span></a>
+<a name="2265"><span class="lineNum">    2265 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2266"><span class="lineNum">    2266 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_8 &lt;= 4'hF;</span></a>
+<a name="2267"><span class="lineNum">    2267 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2268"><span class="lineNum">    2268 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_8 &lt;= 4'h0;</span></a>
+<a name="2269"><span class="lineNum">    2269 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2270"><span class="lineNum">    2270 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_8 &lt;= _newCtr_T_3;</span></a>
+<a name="2271"><span class="lineNum">    2271 </span>            :         else</a>
+<a name="2272"><span class="lineNum">    2272 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_8 &lt;= _newCtr_T_5;</span></a>
+<a name="2273"><span class="lineNum">    2273 </span>            :       end</a>
+<a name="2274"><span class="lineNum">    2274 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h9) begin</span></a>
+<a name="2275"><span class="lineNum">    2275 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2276"><span class="lineNum">    2276 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_9 &lt;= 4'hF;</span></a>
+<a name="2277"><span class="lineNum">    2277 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2278"><span class="lineNum">    2278 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_9 &lt;= 4'h0;</span></a>
+<a name="2279"><span class="lineNum">    2279 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2280"><span class="lineNum">    2280 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_9 &lt;= _newCtr_T_3;</span></a>
+<a name="2281"><span class="lineNum">    2281 </span>            :         else</a>
+<a name="2282"><span class="lineNum">    2282 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_9 &lt;= _newCtr_T_5;</span></a>
+<a name="2283"><span class="lineNum">    2283 </span>            :       end</a>
+<a name="2284"><span class="lineNum">    2284 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'hA) begin</span></a>
+<a name="2285"><span class="lineNum">    2285 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2286"><span class="lineNum">    2286 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_10 &lt;= 4'hF;</span></a>
+<a name="2287"><span class="lineNum">    2287 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2288"><span class="lineNum">    2288 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_10 &lt;= 4'h0;</span></a>
+<a name="2289"><span class="lineNum">    2289 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2290"><span class="lineNum">    2290 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_10 &lt;= _newCtr_T_3;</span></a>
+<a name="2291"><span class="lineNum">    2291 </span>            :         else</a>
+<a name="2292"><span class="lineNum">    2292 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_10 &lt;= _newCtr_T_5;</span></a>
+<a name="2293"><span class="lineNum">    2293 </span>            :       end</a>
+<a name="2294"><span class="lineNum">    2294 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'hB) begin</span></a>
+<a name="2295"><span class="lineNum">    2295 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2296"><span class="lineNum">    2296 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_11 &lt;= 4'hF;</span></a>
+<a name="2297"><span class="lineNum">    2297 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2298"><span class="lineNum">    2298 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_11 &lt;= 4'h0;</span></a>
+<a name="2299"><span class="lineNum">    2299 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2300"><span class="lineNum">    2300 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_11 &lt;= _newCtr_T_3;</span></a>
+<a name="2301"><span class="lineNum">    2301 </span>            :         else</a>
+<a name="2302"><span class="lineNum">    2302 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_11 &lt;= _newCtr_T_5;</span></a>
+<a name="2303"><span class="lineNum">    2303 </span>            :       end</a>
+<a name="2304"><span class="lineNum">    2304 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'hC) begin</span></a>
+<a name="2305"><span class="lineNum">    2305 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2306"><span class="lineNum">    2306 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_12 &lt;= 4'hF;</span></a>
+<a name="2307"><span class="lineNum">    2307 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2308"><span class="lineNum">    2308 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_12 &lt;= 4'h0;</span></a>
+<a name="2309"><span class="lineNum">    2309 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2310"><span class="lineNum">    2310 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_12 &lt;= _newCtr_T_3;</span></a>
+<a name="2311"><span class="lineNum">    2311 </span>            :         else</a>
+<a name="2312"><span class="lineNum">    2312 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_12 &lt;= _newCtr_T_5;</span></a>
+<a name="2313"><span class="lineNum">    2313 </span>            :       end</a>
+<a name="2314"><span class="lineNum">    2314 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'hD) begin</span></a>
+<a name="2315"><span class="lineNum">    2315 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2316"><span class="lineNum">    2316 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_13 &lt;= 4'hF;</span></a>
+<a name="2317"><span class="lineNum">    2317 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2318"><span class="lineNum">    2318 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_13 &lt;= 4'h0;</span></a>
+<a name="2319"><span class="lineNum">    2319 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2320"><span class="lineNum">    2320 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_13 &lt;= _newCtr_T_3;</span></a>
+<a name="2321"><span class="lineNum">    2321 </span>            :         else</a>
+<a name="2322"><span class="lineNum">    2322 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_13 &lt;= _newCtr_T_5;</span></a>
+<a name="2323"><span class="lineNum">    2323 </span>            :       end</a>
+<a name="2324"><span class="lineNum">    2324 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'hE) begin</span></a>
+<a name="2325"><span class="lineNum">    2325 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2326"><span class="lineNum">    2326 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_14 &lt;= 4'hF;</span></a>
+<a name="2327"><span class="lineNum">    2327 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2328"><span class="lineNum">    2328 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_14 &lt;= 4'h0;</span></a>
+<a name="2329"><span class="lineNum">    2329 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2330"><span class="lineNum">    2330 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_14 &lt;= _newCtr_T_3;</span></a>
+<a name="2331"><span class="lineNum">    2331 </span>            :         else</a>
+<a name="2332"><span class="lineNum">    2332 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_14 &lt;= _newCtr_T_5;</span></a>
+<a name="2333"><span class="lineNum">    2333 </span>            :       end</a>
+<a name="2334"><span class="lineNum">    2334 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'hF) begin</span></a>
+<a name="2335"><span class="lineNum">    2335 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2336"><span class="lineNum">    2336 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_15 &lt;= 4'hF;</span></a>
+<a name="2337"><span class="lineNum">    2337 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2338"><span class="lineNum">    2338 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_15 &lt;= 4'h0;</span></a>
+<a name="2339"><span class="lineNum">    2339 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2340"><span class="lineNum">    2340 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_15 &lt;= _newCtr_T_3;</span></a>
+<a name="2341"><span class="lineNum">    2341 </span>            :         else</a>
+<a name="2342"><span class="lineNum">    2342 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_15 &lt;= _newCtr_T_5;</span></a>
+<a name="2343"><span class="lineNum">    2343 </span>            :       end</a>
+<a name="2344"><span class="lineNum">    2344 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h10) begin</span></a>
+<a name="2345"><span class="lineNum">    2345 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2346"><span class="lineNum">    2346 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_16 &lt;= 4'hF;</span></a>
+<a name="2347"><span class="lineNum">    2347 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2348"><span class="lineNum">    2348 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_16 &lt;= 4'h0;</span></a>
+<a name="2349"><span class="lineNum">    2349 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2350"><span class="lineNum">    2350 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_16 &lt;= _newCtr_T_3;</span></a>
+<a name="2351"><span class="lineNum">    2351 </span>            :         else</a>
+<a name="2352"><span class="lineNum">    2352 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_16 &lt;= _newCtr_T_5;</span></a>
+<a name="2353"><span class="lineNum">    2353 </span>            :       end</a>
+<a name="2354"><span class="lineNum">    2354 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h11) begin</span></a>
+<a name="2355"><span class="lineNum">    2355 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2356"><span class="lineNum">    2356 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_17 &lt;= 4'hF;</span></a>
+<a name="2357"><span class="lineNum">    2357 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2358"><span class="lineNum">    2358 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_17 &lt;= 4'h0;</span></a>
+<a name="2359"><span class="lineNum">    2359 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2360"><span class="lineNum">    2360 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_17 &lt;= _newCtr_T_3;</span></a>
+<a name="2361"><span class="lineNum">    2361 </span>            :         else</a>
+<a name="2362"><span class="lineNum">    2362 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_17 &lt;= _newCtr_T_5;</span></a>
+<a name="2363"><span class="lineNum">    2363 </span>            :       end</a>
+<a name="2364"><span class="lineNum">    2364 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h12) begin</span></a>
+<a name="2365"><span class="lineNum">    2365 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2366"><span class="lineNum">    2366 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_18 &lt;= 4'hF;</span></a>
+<a name="2367"><span class="lineNum">    2367 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2368"><span class="lineNum">    2368 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_18 &lt;= 4'h0;</span></a>
+<a name="2369"><span class="lineNum">    2369 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2370"><span class="lineNum">    2370 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_18 &lt;= _newCtr_T_3;</span></a>
+<a name="2371"><span class="lineNum">    2371 </span>            :         else</a>
+<a name="2372"><span class="lineNum">    2372 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_18 &lt;= _newCtr_T_5;</span></a>
+<a name="2373"><span class="lineNum">    2373 </span>            :       end</a>
+<a name="2374"><span class="lineNum">    2374 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h13) begin</span></a>
+<a name="2375"><span class="lineNum">    2375 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2376"><span class="lineNum">    2376 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_19 &lt;= 4'hF;</span></a>
+<a name="2377"><span class="lineNum">    2377 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2378"><span class="lineNum">    2378 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_19 &lt;= 4'h0;</span></a>
+<a name="2379"><span class="lineNum">    2379 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2380"><span class="lineNum">    2380 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_19 &lt;= _newCtr_T_3;</span></a>
+<a name="2381"><span class="lineNum">    2381 </span>            :         else</a>
+<a name="2382"><span class="lineNum">    2382 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_19 &lt;= _newCtr_T_5;</span></a>
+<a name="2383"><span class="lineNum">    2383 </span>            :       end</a>
+<a name="2384"><span class="lineNum">    2384 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h14) begin</span></a>
+<a name="2385"><span class="lineNum">    2385 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2386"><span class="lineNum">    2386 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_20 &lt;= 4'hF;</span></a>
+<a name="2387"><span class="lineNum">    2387 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2388"><span class="lineNum">    2388 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_20 &lt;= 4'h0;</span></a>
+<a name="2389"><span class="lineNum">    2389 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2390"><span class="lineNum">    2390 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_20 &lt;= _newCtr_T_3;</span></a>
+<a name="2391"><span class="lineNum">    2391 </span>            :         else</a>
+<a name="2392"><span class="lineNum">    2392 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_20 &lt;= _newCtr_T_5;</span></a>
+<a name="2393"><span class="lineNum">    2393 </span>            :       end</a>
+<a name="2394"><span class="lineNum">    2394 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h15) begin</span></a>
+<a name="2395"><span class="lineNum">    2395 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2396"><span class="lineNum">    2396 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_21 &lt;= 4'hF;</span></a>
+<a name="2397"><span class="lineNum">    2397 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2398"><span class="lineNum">    2398 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_21 &lt;= 4'h0;</span></a>
+<a name="2399"><span class="lineNum">    2399 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2400"><span class="lineNum">    2400 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_21 &lt;= _newCtr_T_3;</span></a>
+<a name="2401"><span class="lineNum">    2401 </span>            :         else</a>
+<a name="2402"><span class="lineNum">    2402 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_21 &lt;= _newCtr_T_5;</span></a>
+<a name="2403"><span class="lineNum">    2403 </span>            :       end</a>
+<a name="2404"><span class="lineNum">    2404 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h16) begin</span></a>
+<a name="2405"><span class="lineNum">    2405 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2406"><span class="lineNum">    2406 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_22 &lt;= 4'hF;</span></a>
+<a name="2407"><span class="lineNum">    2407 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2408"><span class="lineNum">    2408 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_22 &lt;= 4'h0;</span></a>
+<a name="2409"><span class="lineNum">    2409 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2410"><span class="lineNum">    2410 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_22 &lt;= _newCtr_T_3;</span></a>
+<a name="2411"><span class="lineNum">    2411 </span>            :         else</a>
+<a name="2412"><span class="lineNum">    2412 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_22 &lt;= _newCtr_T_5;</span></a>
+<a name="2413"><span class="lineNum">    2413 </span>            :       end</a>
+<a name="2414"><span class="lineNum">    2414 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h17) begin</span></a>
+<a name="2415"><span class="lineNum">    2415 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2416"><span class="lineNum">    2416 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_23 &lt;= 4'hF;</span></a>
+<a name="2417"><span class="lineNum">    2417 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2418"><span class="lineNum">    2418 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_23 &lt;= 4'h0;</span></a>
+<a name="2419"><span class="lineNum">    2419 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2420"><span class="lineNum">    2420 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_23 &lt;= _newCtr_T_3;</span></a>
+<a name="2421"><span class="lineNum">    2421 </span>            :         else</a>
+<a name="2422"><span class="lineNum">    2422 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_23 &lt;= _newCtr_T_5;</span></a>
+<a name="2423"><span class="lineNum">    2423 </span>            :       end</a>
+<a name="2424"><span class="lineNum">    2424 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h18) begin</span></a>
+<a name="2425"><span class="lineNum">    2425 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2426"><span class="lineNum">    2426 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_24 &lt;= 4'hF;</span></a>
+<a name="2427"><span class="lineNum">    2427 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2428"><span class="lineNum">    2428 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_24 &lt;= 4'h0;</span></a>
+<a name="2429"><span class="lineNum">    2429 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2430"><span class="lineNum">    2430 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_24 &lt;= _newCtr_T_3;</span></a>
+<a name="2431"><span class="lineNum">    2431 </span>            :         else</a>
+<a name="2432"><span class="lineNum">    2432 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_24 &lt;= _newCtr_T_5;</span></a>
+<a name="2433"><span class="lineNum">    2433 </span>            :       end</a>
+<a name="2434"><span class="lineNum">    2434 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h19) begin</span></a>
+<a name="2435"><span class="lineNum">    2435 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2436"><span class="lineNum">    2436 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_25 &lt;= 4'hF;</span></a>
+<a name="2437"><span class="lineNum">    2437 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2438"><span class="lineNum">    2438 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_25 &lt;= 4'h0;</span></a>
+<a name="2439"><span class="lineNum">    2439 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2440"><span class="lineNum">    2440 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_25 &lt;= _newCtr_T_3;</span></a>
+<a name="2441"><span class="lineNum">    2441 </span>            :         else</a>
+<a name="2442"><span class="lineNum">    2442 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_25 &lt;= _newCtr_T_5;</span></a>
+<a name="2443"><span class="lineNum">    2443 </span>            :       end</a>
+<a name="2444"><span class="lineNum">    2444 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h1A) begin</span></a>
+<a name="2445"><span class="lineNum">    2445 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2446"><span class="lineNum">    2446 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_26 &lt;= 4'hF;</span></a>
+<a name="2447"><span class="lineNum">    2447 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2448"><span class="lineNum">    2448 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_26 &lt;= 4'h0;</span></a>
+<a name="2449"><span class="lineNum">    2449 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2450"><span class="lineNum">    2450 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_26 &lt;= _newCtr_T_3;</span></a>
+<a name="2451"><span class="lineNum">    2451 </span>            :         else</a>
+<a name="2452"><span class="lineNum">    2452 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_26 &lt;= _newCtr_T_5;</span></a>
+<a name="2453"><span class="lineNum">    2453 </span>            :       end</a>
+<a name="2454"><span class="lineNum">    2454 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h1B) begin</span></a>
+<a name="2455"><span class="lineNum">    2455 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2456"><span class="lineNum">    2456 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_27 &lt;= 4'hF;</span></a>
+<a name="2457"><span class="lineNum">    2457 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2458"><span class="lineNum">    2458 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_27 &lt;= 4'h0;</span></a>
+<a name="2459"><span class="lineNum">    2459 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2460"><span class="lineNum">    2460 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_27 &lt;= _newCtr_T_3;</span></a>
+<a name="2461"><span class="lineNum">    2461 </span>            :         else</a>
+<a name="2462"><span class="lineNum">    2462 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_27 &lt;= _newCtr_T_5;</span></a>
+<a name="2463"><span class="lineNum">    2463 </span>            :       end</a>
+<a name="2464"><span class="lineNum">    2464 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h1C) begin</span></a>
+<a name="2465"><span class="lineNum">    2465 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2466"><span class="lineNum">    2466 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_28 &lt;= 4'hF;</span></a>
+<a name="2467"><span class="lineNum">    2467 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2468"><span class="lineNum">    2468 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_28 &lt;= 4'h0;</span></a>
+<a name="2469"><span class="lineNum">    2469 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2470"><span class="lineNum">    2470 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_28 &lt;= _newCtr_T_3;</span></a>
+<a name="2471"><span class="lineNum">    2471 </span>            :         else</a>
+<a name="2472"><span class="lineNum">    2472 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_28 &lt;= _newCtr_T_5;</span></a>
+<a name="2473"><span class="lineNum">    2473 </span>            :       end</a>
+<a name="2474"><span class="lineNum">    2474 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h1D) begin</span></a>
+<a name="2475"><span class="lineNum">    2475 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2476"><span class="lineNum">    2476 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_29 &lt;= 4'hF;</span></a>
+<a name="2477"><span class="lineNum">    2477 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2478"><span class="lineNum">    2478 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_29 &lt;= 4'h0;</span></a>
+<a name="2479"><span class="lineNum">    2479 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2480"><span class="lineNum">    2480 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_29 &lt;= _newCtr_T_3;</span></a>
+<a name="2481"><span class="lineNum">    2481 </span>            :         else</a>
+<a name="2482"><span class="lineNum">    2482 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_29 &lt;= _newCtr_T_5;</span></a>
+<a name="2483"><span class="lineNum">    2483 </span>            :       end</a>
+<a name="2484"><span class="lineNum">    2484 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h1E) begin</span></a>
+<a name="2485"><span class="lineNum">    2485 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2486"><span class="lineNum">    2486 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_30 &lt;= 4'hF;</span></a>
+<a name="2487"><span class="lineNum">    2487 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2488"><span class="lineNum">    2488 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_30 &lt;= 4'h0;</span></a>
+<a name="2489"><span class="lineNum">    2489 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2490"><span class="lineNum">    2490 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_30 &lt;= _newCtr_T_3;</span></a>
+<a name="2491"><span class="lineNum">    2491 </span>            :         else</a>
+<a name="2492"><span class="lineNum">    2492 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_30 &lt;= _newCtr_T_5;</span></a>
+<a name="2493"><span class="lineNum">    2493 </span>            :       end</a>
+<a name="2494"><span class="lineNum">    2494 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h1F) begin</span></a>
+<a name="2495"><span class="lineNum">    2495 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2496"><span class="lineNum">    2496 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_31 &lt;= 4'hF;</span></a>
+<a name="2497"><span class="lineNum">    2497 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2498"><span class="lineNum">    2498 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_31 &lt;= 4'h0;</span></a>
+<a name="2499"><span class="lineNum">    2499 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2500"><span class="lineNum">    2500 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_31 &lt;= _newCtr_T_3;</span></a>
+<a name="2501"><span class="lineNum">    2501 </span>            :         else</a>
+<a name="2502"><span class="lineNum">    2502 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_31 &lt;= _newCtr_T_5;</span></a>
+<a name="2503"><span class="lineNum">    2503 </span>            :       end</a>
+<a name="2504"><span class="lineNum">    2504 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h20) begin</span></a>
+<a name="2505"><span class="lineNum">    2505 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2506"><span class="lineNum">    2506 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_32 &lt;= 4'hF;</span></a>
+<a name="2507"><span class="lineNum">    2507 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2508"><span class="lineNum">    2508 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_32 &lt;= 4'h0;</span></a>
+<a name="2509"><span class="lineNum">    2509 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2510"><span class="lineNum">    2510 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_32 &lt;= _newCtr_T_3;</span></a>
+<a name="2511"><span class="lineNum">    2511 </span>            :         else</a>
+<a name="2512"><span class="lineNum">    2512 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_32 &lt;= _newCtr_T_5;</span></a>
+<a name="2513"><span class="lineNum">    2513 </span>            :       end</a>
+<a name="2514"><span class="lineNum">    2514 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h21) begin</span></a>
+<a name="2515"><span class="lineNum">    2515 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2516"><span class="lineNum">    2516 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_33 &lt;= 4'hF;</span></a>
+<a name="2517"><span class="lineNum">    2517 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2518"><span class="lineNum">    2518 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_33 &lt;= 4'h0;</span></a>
+<a name="2519"><span class="lineNum">    2519 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2520"><span class="lineNum">    2520 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_33 &lt;= _newCtr_T_3;</span></a>
+<a name="2521"><span class="lineNum">    2521 </span>            :         else</a>
+<a name="2522"><span class="lineNum">    2522 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_33 &lt;= _newCtr_T_5;</span></a>
+<a name="2523"><span class="lineNum">    2523 </span>            :       end</a>
+<a name="2524"><span class="lineNum">    2524 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h22) begin</span></a>
+<a name="2525"><span class="lineNum">    2525 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2526"><span class="lineNum">    2526 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_34 &lt;= 4'hF;</span></a>
+<a name="2527"><span class="lineNum">    2527 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2528"><span class="lineNum">    2528 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_34 &lt;= 4'h0;</span></a>
+<a name="2529"><span class="lineNum">    2529 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2530"><span class="lineNum">    2530 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_34 &lt;= _newCtr_T_3;</span></a>
+<a name="2531"><span class="lineNum">    2531 </span>            :         else</a>
+<a name="2532"><span class="lineNum">    2532 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_34 &lt;= _newCtr_T_5;</span></a>
+<a name="2533"><span class="lineNum">    2533 </span>            :       end</a>
+<a name="2534"><span class="lineNum">    2534 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h23) begin</span></a>
+<a name="2535"><span class="lineNum">    2535 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2536"><span class="lineNum">    2536 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_35 &lt;= 4'hF;</span></a>
+<a name="2537"><span class="lineNum">    2537 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2538"><span class="lineNum">    2538 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_35 &lt;= 4'h0;</span></a>
+<a name="2539"><span class="lineNum">    2539 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2540"><span class="lineNum">    2540 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_35 &lt;= _newCtr_T_3;</span></a>
+<a name="2541"><span class="lineNum">    2541 </span>            :         else</a>
+<a name="2542"><span class="lineNum">    2542 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_35 &lt;= _newCtr_T_5;</span></a>
+<a name="2543"><span class="lineNum">    2543 </span>            :       end</a>
+<a name="2544"><span class="lineNum">    2544 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h24) begin</span></a>
+<a name="2545"><span class="lineNum">    2545 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2546"><span class="lineNum">    2546 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_36 &lt;= 4'hF;</span></a>
+<a name="2547"><span class="lineNum">    2547 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2548"><span class="lineNum">    2548 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_36 &lt;= 4'h0;</span></a>
+<a name="2549"><span class="lineNum">    2549 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2550"><span class="lineNum">    2550 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_36 &lt;= _newCtr_T_3;</span></a>
+<a name="2551"><span class="lineNum">    2551 </span>            :         else</a>
+<a name="2552"><span class="lineNum">    2552 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_36 &lt;= _newCtr_T_5;</span></a>
+<a name="2553"><span class="lineNum">    2553 </span>            :       end</a>
+<a name="2554"><span class="lineNum">    2554 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h25) begin</span></a>
+<a name="2555"><span class="lineNum">    2555 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2556"><span class="lineNum">    2556 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_37 &lt;= 4'hF;</span></a>
+<a name="2557"><span class="lineNum">    2557 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2558"><span class="lineNum">    2558 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_37 &lt;= 4'h0;</span></a>
+<a name="2559"><span class="lineNum">    2559 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2560"><span class="lineNum">    2560 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_37 &lt;= _newCtr_T_3;</span></a>
+<a name="2561"><span class="lineNum">    2561 </span>            :         else</a>
+<a name="2562"><span class="lineNum">    2562 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_37 &lt;= _newCtr_T_5;</span></a>
+<a name="2563"><span class="lineNum">    2563 </span>            :       end</a>
+<a name="2564"><span class="lineNum">    2564 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h26) begin</span></a>
+<a name="2565"><span class="lineNum">    2565 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2566"><span class="lineNum">    2566 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_38 &lt;= 4'hF;</span></a>
+<a name="2567"><span class="lineNum">    2567 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2568"><span class="lineNum">    2568 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_38 &lt;= 4'h0;</span></a>
+<a name="2569"><span class="lineNum">    2569 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2570"><span class="lineNum">    2570 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_38 &lt;= _newCtr_T_3;</span></a>
+<a name="2571"><span class="lineNum">    2571 </span>            :         else</a>
+<a name="2572"><span class="lineNum">    2572 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_38 &lt;= _newCtr_T_5;</span></a>
+<a name="2573"><span class="lineNum">    2573 </span>            :       end</a>
+<a name="2574"><span class="lineNum">    2574 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h27) begin</span></a>
+<a name="2575"><span class="lineNum">    2575 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2576"><span class="lineNum">    2576 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_39 &lt;= 4'hF;</span></a>
+<a name="2577"><span class="lineNum">    2577 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2578"><span class="lineNum">    2578 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_39 &lt;= 4'h0;</span></a>
+<a name="2579"><span class="lineNum">    2579 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2580"><span class="lineNum">    2580 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_39 &lt;= _newCtr_T_3;</span></a>
+<a name="2581"><span class="lineNum">    2581 </span>            :         else</a>
+<a name="2582"><span class="lineNum">    2582 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_39 &lt;= _newCtr_T_5;</span></a>
+<a name="2583"><span class="lineNum">    2583 </span>            :       end</a>
+<a name="2584"><span class="lineNum">    2584 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h28) begin</span></a>
+<a name="2585"><span class="lineNum">    2585 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2586"><span class="lineNum">    2586 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_40 &lt;= 4'hF;</span></a>
+<a name="2587"><span class="lineNum">    2587 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2588"><span class="lineNum">    2588 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_40 &lt;= 4'h0;</span></a>
+<a name="2589"><span class="lineNum">    2589 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2590"><span class="lineNum">    2590 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_40 &lt;= _newCtr_T_3;</span></a>
+<a name="2591"><span class="lineNum">    2591 </span>            :         else</a>
+<a name="2592"><span class="lineNum">    2592 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_40 &lt;= _newCtr_T_5;</span></a>
+<a name="2593"><span class="lineNum">    2593 </span>            :       end</a>
+<a name="2594"><span class="lineNum">    2594 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h29) begin</span></a>
+<a name="2595"><span class="lineNum">    2595 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2596"><span class="lineNum">    2596 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_41 &lt;= 4'hF;</span></a>
+<a name="2597"><span class="lineNum">    2597 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2598"><span class="lineNum">    2598 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_41 &lt;= 4'h0;</span></a>
+<a name="2599"><span class="lineNum">    2599 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2600"><span class="lineNum">    2600 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_41 &lt;= _newCtr_T_3;</span></a>
+<a name="2601"><span class="lineNum">    2601 </span>            :         else</a>
+<a name="2602"><span class="lineNum">    2602 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_41 &lt;= _newCtr_T_5;</span></a>
+<a name="2603"><span class="lineNum">    2603 </span>            :       end</a>
+<a name="2604"><span class="lineNum">    2604 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h2A) begin</span></a>
+<a name="2605"><span class="lineNum">    2605 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2606"><span class="lineNum">    2606 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_42 &lt;= 4'hF;</span></a>
+<a name="2607"><span class="lineNum">    2607 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2608"><span class="lineNum">    2608 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_42 &lt;= 4'h0;</span></a>
+<a name="2609"><span class="lineNum">    2609 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2610"><span class="lineNum">    2610 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_42 &lt;= _newCtr_T_3;</span></a>
+<a name="2611"><span class="lineNum">    2611 </span>            :         else</a>
+<a name="2612"><span class="lineNum">    2612 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_42 &lt;= _newCtr_T_5;</span></a>
+<a name="2613"><span class="lineNum">    2613 </span>            :       end</a>
+<a name="2614"><span class="lineNum">    2614 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h2B) begin</span></a>
+<a name="2615"><span class="lineNum">    2615 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2616"><span class="lineNum">    2616 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_43 &lt;= 4'hF;</span></a>
+<a name="2617"><span class="lineNum">    2617 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2618"><span class="lineNum">    2618 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_43 &lt;= 4'h0;</span></a>
+<a name="2619"><span class="lineNum">    2619 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2620"><span class="lineNum">    2620 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_43 &lt;= _newCtr_T_3;</span></a>
+<a name="2621"><span class="lineNum">    2621 </span>            :         else</a>
+<a name="2622"><span class="lineNum">    2622 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_43 &lt;= _newCtr_T_5;</span></a>
+<a name="2623"><span class="lineNum">    2623 </span>            :       end</a>
+<a name="2624"><span class="lineNum">    2624 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h2C) begin</span></a>
+<a name="2625"><span class="lineNum">    2625 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2626"><span class="lineNum">    2626 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_44 &lt;= 4'hF;</span></a>
+<a name="2627"><span class="lineNum">    2627 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2628"><span class="lineNum">    2628 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_44 &lt;= 4'h0;</span></a>
+<a name="2629"><span class="lineNum">    2629 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2630"><span class="lineNum">    2630 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_44 &lt;= _newCtr_T_3;</span></a>
+<a name="2631"><span class="lineNum">    2631 </span>            :         else</a>
+<a name="2632"><span class="lineNum">    2632 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_44 &lt;= _newCtr_T_5;</span></a>
+<a name="2633"><span class="lineNum">    2633 </span>            :       end</a>
+<a name="2634"><span class="lineNum">    2634 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h2D) begin</span></a>
+<a name="2635"><span class="lineNum">    2635 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2636"><span class="lineNum">    2636 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_45 &lt;= 4'hF;</span></a>
+<a name="2637"><span class="lineNum">    2637 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2638"><span class="lineNum">    2638 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_45 &lt;= 4'h0;</span></a>
+<a name="2639"><span class="lineNum">    2639 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2640"><span class="lineNum">    2640 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_45 &lt;= _newCtr_T_3;</span></a>
+<a name="2641"><span class="lineNum">    2641 </span>            :         else</a>
+<a name="2642"><span class="lineNum">    2642 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_45 &lt;= _newCtr_T_5;</span></a>
+<a name="2643"><span class="lineNum">    2643 </span>            :       end</a>
+<a name="2644"><span class="lineNum">    2644 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h2E) begin</span></a>
+<a name="2645"><span class="lineNum">    2645 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2646"><span class="lineNum">    2646 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_46 &lt;= 4'hF;</span></a>
+<a name="2647"><span class="lineNum">    2647 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2648"><span class="lineNum">    2648 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_46 &lt;= 4'h0;</span></a>
+<a name="2649"><span class="lineNum">    2649 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2650"><span class="lineNum">    2650 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_46 &lt;= _newCtr_T_3;</span></a>
+<a name="2651"><span class="lineNum">    2651 </span>            :         else</a>
+<a name="2652"><span class="lineNum">    2652 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_46 &lt;= _newCtr_T_5;</span></a>
+<a name="2653"><span class="lineNum">    2653 </span>            :       end</a>
+<a name="2654"><span class="lineNum">    2654 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h2F) begin</span></a>
+<a name="2655"><span class="lineNum">    2655 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2656"><span class="lineNum">    2656 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_47 &lt;= 4'hF;</span></a>
+<a name="2657"><span class="lineNum">    2657 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2658"><span class="lineNum">    2658 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_47 &lt;= 4'h0;</span></a>
+<a name="2659"><span class="lineNum">    2659 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2660"><span class="lineNum">    2660 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_47 &lt;= _newCtr_T_3;</span></a>
+<a name="2661"><span class="lineNum">    2661 </span>            :         else</a>
+<a name="2662"><span class="lineNum">    2662 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_47 &lt;= _newCtr_T_5;</span></a>
+<a name="2663"><span class="lineNum">    2663 </span>            :       end</a>
+<a name="2664"><span class="lineNum">    2664 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h30) begin</span></a>
+<a name="2665"><span class="lineNum">    2665 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2666"><span class="lineNum">    2666 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_48 &lt;= 4'hF;</span></a>
+<a name="2667"><span class="lineNum">    2667 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2668"><span class="lineNum">    2668 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_48 &lt;= 4'h0;</span></a>
+<a name="2669"><span class="lineNum">    2669 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2670"><span class="lineNum">    2670 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_48 &lt;= _newCtr_T_3;</span></a>
+<a name="2671"><span class="lineNum">    2671 </span>            :         else</a>
+<a name="2672"><span class="lineNum">    2672 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_48 &lt;= _newCtr_T_5;</span></a>
+<a name="2673"><span class="lineNum">    2673 </span>            :       end</a>
+<a name="2674"><span class="lineNum">    2674 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h31) begin</span></a>
+<a name="2675"><span class="lineNum">    2675 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2676"><span class="lineNum">    2676 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_49 &lt;= 4'hF;</span></a>
+<a name="2677"><span class="lineNum">    2677 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2678"><span class="lineNum">    2678 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_49 &lt;= 4'h0;</span></a>
+<a name="2679"><span class="lineNum">    2679 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2680"><span class="lineNum">    2680 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_49 &lt;= _newCtr_T_3;</span></a>
+<a name="2681"><span class="lineNum">    2681 </span>            :         else</a>
+<a name="2682"><span class="lineNum">    2682 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_49 &lt;= _newCtr_T_5;</span></a>
+<a name="2683"><span class="lineNum">    2683 </span>            :       end</a>
+<a name="2684"><span class="lineNum">    2684 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h32) begin</span></a>
+<a name="2685"><span class="lineNum">    2685 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2686"><span class="lineNum">    2686 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_50 &lt;= 4'hF;</span></a>
+<a name="2687"><span class="lineNum">    2687 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2688"><span class="lineNum">    2688 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_50 &lt;= 4'h0;</span></a>
+<a name="2689"><span class="lineNum">    2689 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2690"><span class="lineNum">    2690 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_50 &lt;= _newCtr_T_3;</span></a>
+<a name="2691"><span class="lineNum">    2691 </span>            :         else</a>
+<a name="2692"><span class="lineNum">    2692 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_50 &lt;= _newCtr_T_5;</span></a>
+<a name="2693"><span class="lineNum">    2693 </span>            :       end</a>
+<a name="2694"><span class="lineNum">    2694 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h33) begin</span></a>
+<a name="2695"><span class="lineNum">    2695 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2696"><span class="lineNum">    2696 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_51 &lt;= 4'hF;</span></a>
+<a name="2697"><span class="lineNum">    2697 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2698"><span class="lineNum">    2698 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_51 &lt;= 4'h0;</span></a>
+<a name="2699"><span class="lineNum">    2699 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2700"><span class="lineNum">    2700 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_51 &lt;= _newCtr_T_3;</span></a>
+<a name="2701"><span class="lineNum">    2701 </span>            :         else</a>
+<a name="2702"><span class="lineNum">    2702 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_51 &lt;= _newCtr_T_5;</span></a>
+<a name="2703"><span class="lineNum">    2703 </span>            :       end</a>
+<a name="2704"><span class="lineNum">    2704 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h34) begin</span></a>
+<a name="2705"><span class="lineNum">    2705 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2706"><span class="lineNum">    2706 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_52 &lt;= 4'hF;</span></a>
+<a name="2707"><span class="lineNum">    2707 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2708"><span class="lineNum">    2708 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_52 &lt;= 4'h0;</span></a>
+<a name="2709"><span class="lineNum">    2709 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2710"><span class="lineNum">    2710 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_52 &lt;= _newCtr_T_3;</span></a>
+<a name="2711"><span class="lineNum">    2711 </span>            :         else</a>
+<a name="2712"><span class="lineNum">    2712 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_52 &lt;= _newCtr_T_5;</span></a>
+<a name="2713"><span class="lineNum">    2713 </span>            :       end</a>
+<a name="2714"><span class="lineNum">    2714 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h35) begin</span></a>
+<a name="2715"><span class="lineNum">    2715 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2716"><span class="lineNum">    2716 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_53 &lt;= 4'hF;</span></a>
+<a name="2717"><span class="lineNum">    2717 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2718"><span class="lineNum">    2718 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_53 &lt;= 4'h0;</span></a>
+<a name="2719"><span class="lineNum">    2719 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2720"><span class="lineNum">    2720 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_53 &lt;= _newCtr_T_3;</span></a>
+<a name="2721"><span class="lineNum">    2721 </span>            :         else</a>
+<a name="2722"><span class="lineNum">    2722 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_53 &lt;= _newCtr_T_5;</span></a>
+<a name="2723"><span class="lineNum">    2723 </span>            :       end</a>
+<a name="2724"><span class="lineNum">    2724 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h36) begin</span></a>
+<a name="2725"><span class="lineNum">    2725 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2726"><span class="lineNum">    2726 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_54 &lt;= 4'hF;</span></a>
+<a name="2727"><span class="lineNum">    2727 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2728"><span class="lineNum">    2728 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_54 &lt;= 4'h0;</span></a>
+<a name="2729"><span class="lineNum">    2729 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2730"><span class="lineNum">    2730 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_54 &lt;= _newCtr_T_3;</span></a>
+<a name="2731"><span class="lineNum">    2731 </span>            :         else</a>
+<a name="2732"><span class="lineNum">    2732 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_54 &lt;= _newCtr_T_5;</span></a>
+<a name="2733"><span class="lineNum">    2733 </span>            :       end</a>
+<a name="2734"><span class="lineNum">    2734 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h37) begin</span></a>
+<a name="2735"><span class="lineNum">    2735 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2736"><span class="lineNum">    2736 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_55 &lt;= 4'hF;</span></a>
+<a name="2737"><span class="lineNum">    2737 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2738"><span class="lineNum">    2738 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_55 &lt;= 4'h0;</span></a>
+<a name="2739"><span class="lineNum">    2739 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2740"><span class="lineNum">    2740 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_55 &lt;= _newCtr_T_3;</span></a>
+<a name="2741"><span class="lineNum">    2741 </span>            :         else</a>
+<a name="2742"><span class="lineNum">    2742 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_55 &lt;= _newCtr_T_5;</span></a>
+<a name="2743"><span class="lineNum">    2743 </span>            :       end</a>
+<a name="2744"><span class="lineNum">    2744 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h38) begin</span></a>
+<a name="2745"><span class="lineNum">    2745 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2746"><span class="lineNum">    2746 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_56 &lt;= 4'hF;</span></a>
+<a name="2747"><span class="lineNum">    2747 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2748"><span class="lineNum">    2748 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_56 &lt;= 4'h0;</span></a>
+<a name="2749"><span class="lineNum">    2749 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2750"><span class="lineNum">    2750 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_56 &lt;= _newCtr_T_3;</span></a>
+<a name="2751"><span class="lineNum">    2751 </span>            :         else</a>
+<a name="2752"><span class="lineNum">    2752 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_56 &lt;= _newCtr_T_5;</span></a>
+<a name="2753"><span class="lineNum">    2753 </span>            :       end</a>
+<a name="2754"><span class="lineNum">    2754 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h39) begin</span></a>
+<a name="2755"><span class="lineNum">    2755 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2756"><span class="lineNum">    2756 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_57 &lt;= 4'hF;</span></a>
+<a name="2757"><span class="lineNum">    2757 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2758"><span class="lineNum">    2758 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_57 &lt;= 4'h0;</span></a>
+<a name="2759"><span class="lineNum">    2759 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2760"><span class="lineNum">    2760 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_57 &lt;= _newCtr_T_3;</span></a>
+<a name="2761"><span class="lineNum">    2761 </span>            :         else</a>
+<a name="2762"><span class="lineNum">    2762 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_57 &lt;= _newCtr_T_5;</span></a>
+<a name="2763"><span class="lineNum">    2763 </span>            :       end</a>
+<a name="2764"><span class="lineNum">    2764 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h3A) begin</span></a>
+<a name="2765"><span class="lineNum">    2765 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2766"><span class="lineNum">    2766 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_58 &lt;= 4'hF;</span></a>
+<a name="2767"><span class="lineNum">    2767 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2768"><span class="lineNum">    2768 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_58 &lt;= 4'h0;</span></a>
+<a name="2769"><span class="lineNum">    2769 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2770"><span class="lineNum">    2770 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_58 &lt;= _newCtr_T_3;</span></a>
+<a name="2771"><span class="lineNum">    2771 </span>            :         else</a>
+<a name="2772"><span class="lineNum">    2772 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_58 &lt;= _newCtr_T_5;</span></a>
+<a name="2773"><span class="lineNum">    2773 </span>            :       end</a>
+<a name="2774"><span class="lineNum">    2774 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h3B) begin</span></a>
+<a name="2775"><span class="lineNum">    2775 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2776"><span class="lineNum">    2776 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_59 &lt;= 4'hF;</span></a>
+<a name="2777"><span class="lineNum">    2777 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2778"><span class="lineNum">    2778 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_59 &lt;= 4'h0;</span></a>
+<a name="2779"><span class="lineNum">    2779 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2780"><span class="lineNum">    2780 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_59 &lt;= _newCtr_T_3;</span></a>
+<a name="2781"><span class="lineNum">    2781 </span>            :         else</a>
+<a name="2782"><span class="lineNum">    2782 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_59 &lt;= _newCtr_T_5;</span></a>
+<a name="2783"><span class="lineNum">    2783 </span>            :       end</a>
+<a name="2784"><span class="lineNum">    2784 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h3C) begin</span></a>
+<a name="2785"><span class="lineNum">    2785 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2786"><span class="lineNum">    2786 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_60 &lt;= 4'hF;</span></a>
+<a name="2787"><span class="lineNum">    2787 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2788"><span class="lineNum">    2788 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_60 &lt;= 4'h0;</span></a>
+<a name="2789"><span class="lineNum">    2789 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2790"><span class="lineNum">    2790 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_60 &lt;= _newCtr_T_3;</span></a>
+<a name="2791"><span class="lineNum">    2791 </span>            :         else</a>
+<a name="2792"><span class="lineNum">    2792 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_60 &lt;= _newCtr_T_5;</span></a>
+<a name="2793"><span class="lineNum">    2793 </span>            :       end</a>
+<a name="2794"><span class="lineNum">    2794 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h3D) begin</span></a>
+<a name="2795"><span class="lineNum">    2795 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2796"><span class="lineNum">    2796 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_61 &lt;= 4'hF;</span></a>
+<a name="2797"><span class="lineNum">    2797 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2798"><span class="lineNum">    2798 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_61 &lt;= 4'h0;</span></a>
+<a name="2799"><span class="lineNum">    2799 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2800"><span class="lineNum">    2800 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_61 &lt;= _newCtr_T_3;</span></a>
+<a name="2801"><span class="lineNum">    2801 </span>            :         else</a>
+<a name="2802"><span class="lineNum">    2802 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_61 &lt;= _newCtr_T_5;</span></a>
+<a name="2803"><span class="lineNum">    2803 </span>            :       end</a>
+<a name="2804"><span class="lineNum">    2804 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h3E) begin</span></a>
+<a name="2805"><span class="lineNum">    2805 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2806"><span class="lineNum">    2806 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_62 &lt;= 4'hF;</span></a>
+<a name="2807"><span class="lineNum">    2807 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2808"><span class="lineNum">    2808 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_62 &lt;= 4'h0;</span></a>
+<a name="2809"><span class="lineNum">    2809 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2810"><span class="lineNum">    2810 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_62 &lt;= _newCtr_T_3;</span></a>
+<a name="2811"><span class="lineNum">    2811 </span>            :         else</a>
+<a name="2812"><span class="lineNum">    2812 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_62 &lt;= _newCtr_T_5;</span></a>
+<a name="2813"><span class="lineNum">    2813 </span>            :       end</a>
+<a name="2814"><span class="lineNum">    2814 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h3F) begin</span></a>
+<a name="2815"><span class="lineNum">    2815 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2816"><span class="lineNum">    2816 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_63 &lt;= 4'hF;</span></a>
+<a name="2817"><span class="lineNum">    2817 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2818"><span class="lineNum">    2818 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_63 &lt;= 4'h0;</span></a>
+<a name="2819"><span class="lineNum">    2819 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2820"><span class="lineNum">    2820 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_63 &lt;= _newCtr_T_3;</span></a>
+<a name="2821"><span class="lineNum">    2821 </span>            :         else</a>
+<a name="2822"><span class="lineNum">    2822 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_63 &lt;= _newCtr_T_5;</span></a>
+<a name="2823"><span class="lineNum">    2823 </span>            :       end</a>
+<a name="2824"><span class="lineNum">    2824 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h40) begin</span></a>
+<a name="2825"><span class="lineNum">    2825 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2826"><span class="lineNum">    2826 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_64 &lt;= 4'hF;</span></a>
+<a name="2827"><span class="lineNum">    2827 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2828"><span class="lineNum">    2828 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_64 &lt;= 4'h0;</span></a>
+<a name="2829"><span class="lineNum">    2829 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2830"><span class="lineNum">    2830 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_64 &lt;= _newCtr_T_3;</span></a>
+<a name="2831"><span class="lineNum">    2831 </span>            :         else</a>
+<a name="2832"><span class="lineNum">    2832 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_64 &lt;= _newCtr_T_5;</span></a>
+<a name="2833"><span class="lineNum">    2833 </span>            :       end</a>
+<a name="2834"><span class="lineNum">    2834 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h41) begin</span></a>
+<a name="2835"><span class="lineNum">    2835 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2836"><span class="lineNum">    2836 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_65 &lt;= 4'hF;</span></a>
+<a name="2837"><span class="lineNum">    2837 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2838"><span class="lineNum">    2838 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_65 &lt;= 4'h0;</span></a>
+<a name="2839"><span class="lineNum">    2839 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2840"><span class="lineNum">    2840 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_65 &lt;= _newCtr_T_3;</span></a>
+<a name="2841"><span class="lineNum">    2841 </span>            :         else</a>
+<a name="2842"><span class="lineNum">    2842 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_65 &lt;= _newCtr_T_5;</span></a>
+<a name="2843"><span class="lineNum">    2843 </span>            :       end</a>
+<a name="2844"><span class="lineNum">    2844 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h42) begin</span></a>
+<a name="2845"><span class="lineNum">    2845 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2846"><span class="lineNum">    2846 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_66 &lt;= 4'hF;</span></a>
+<a name="2847"><span class="lineNum">    2847 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2848"><span class="lineNum">    2848 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_66 &lt;= 4'h0;</span></a>
+<a name="2849"><span class="lineNum">    2849 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2850"><span class="lineNum">    2850 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_66 &lt;= _newCtr_T_3;</span></a>
+<a name="2851"><span class="lineNum">    2851 </span>            :         else</a>
+<a name="2852"><span class="lineNum">    2852 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_66 &lt;= _newCtr_T_5;</span></a>
+<a name="2853"><span class="lineNum">    2853 </span>            :       end</a>
+<a name="2854"><span class="lineNum">    2854 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h43) begin</span></a>
+<a name="2855"><span class="lineNum">    2855 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2856"><span class="lineNum">    2856 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_67 &lt;= 4'hF;</span></a>
+<a name="2857"><span class="lineNum">    2857 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2858"><span class="lineNum">    2858 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_67 &lt;= 4'h0;</span></a>
+<a name="2859"><span class="lineNum">    2859 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2860"><span class="lineNum">    2860 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_67 &lt;= _newCtr_T_3;</span></a>
+<a name="2861"><span class="lineNum">    2861 </span>            :         else</a>
+<a name="2862"><span class="lineNum">    2862 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_67 &lt;= _newCtr_T_5;</span></a>
+<a name="2863"><span class="lineNum">    2863 </span>            :       end</a>
+<a name="2864"><span class="lineNum">    2864 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h44) begin</span></a>
+<a name="2865"><span class="lineNum">    2865 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2866"><span class="lineNum">    2866 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_68 &lt;= 4'hF;</span></a>
+<a name="2867"><span class="lineNum">    2867 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2868"><span class="lineNum">    2868 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_68 &lt;= 4'h0;</span></a>
+<a name="2869"><span class="lineNum">    2869 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2870"><span class="lineNum">    2870 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_68 &lt;= _newCtr_T_3;</span></a>
+<a name="2871"><span class="lineNum">    2871 </span>            :         else</a>
+<a name="2872"><span class="lineNum">    2872 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_68 &lt;= _newCtr_T_5;</span></a>
+<a name="2873"><span class="lineNum">    2873 </span>            :       end</a>
+<a name="2874"><span class="lineNum">    2874 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h45) begin</span></a>
+<a name="2875"><span class="lineNum">    2875 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2876"><span class="lineNum">    2876 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_69 &lt;= 4'hF;</span></a>
+<a name="2877"><span class="lineNum">    2877 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2878"><span class="lineNum">    2878 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_69 &lt;= 4'h0;</span></a>
+<a name="2879"><span class="lineNum">    2879 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2880"><span class="lineNum">    2880 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_69 &lt;= _newCtr_T_3;</span></a>
+<a name="2881"><span class="lineNum">    2881 </span>            :         else</a>
+<a name="2882"><span class="lineNum">    2882 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_69 &lt;= _newCtr_T_5;</span></a>
+<a name="2883"><span class="lineNum">    2883 </span>            :       end</a>
+<a name="2884"><span class="lineNum">    2884 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h46) begin</span></a>
+<a name="2885"><span class="lineNum">    2885 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2886"><span class="lineNum">    2886 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_70 &lt;= 4'hF;</span></a>
+<a name="2887"><span class="lineNum">    2887 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2888"><span class="lineNum">    2888 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_70 &lt;= 4'h0;</span></a>
+<a name="2889"><span class="lineNum">    2889 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2890"><span class="lineNum">    2890 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_70 &lt;= _newCtr_T_3;</span></a>
+<a name="2891"><span class="lineNum">    2891 </span>            :         else</a>
+<a name="2892"><span class="lineNum">    2892 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_70 &lt;= _newCtr_T_5;</span></a>
+<a name="2893"><span class="lineNum">    2893 </span>            :       end</a>
+<a name="2894"><span class="lineNum">    2894 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h47) begin</span></a>
+<a name="2895"><span class="lineNum">    2895 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2896"><span class="lineNum">    2896 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_71 &lt;= 4'hF;</span></a>
+<a name="2897"><span class="lineNum">    2897 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2898"><span class="lineNum">    2898 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_71 &lt;= 4'h0;</span></a>
+<a name="2899"><span class="lineNum">    2899 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2900"><span class="lineNum">    2900 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_71 &lt;= _newCtr_T_3;</span></a>
+<a name="2901"><span class="lineNum">    2901 </span>            :         else</a>
+<a name="2902"><span class="lineNum">    2902 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_71 &lt;= _newCtr_T_5;</span></a>
+<a name="2903"><span class="lineNum">    2903 </span>            :       end</a>
+<a name="2904"><span class="lineNum">    2904 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h48) begin</span></a>
+<a name="2905"><span class="lineNum">    2905 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2906"><span class="lineNum">    2906 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_72 &lt;= 4'hF;</span></a>
+<a name="2907"><span class="lineNum">    2907 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2908"><span class="lineNum">    2908 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_72 &lt;= 4'h0;</span></a>
+<a name="2909"><span class="lineNum">    2909 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2910"><span class="lineNum">    2910 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_72 &lt;= _newCtr_T_3;</span></a>
+<a name="2911"><span class="lineNum">    2911 </span>            :         else</a>
+<a name="2912"><span class="lineNum">    2912 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_72 &lt;= _newCtr_T_5;</span></a>
+<a name="2913"><span class="lineNum">    2913 </span>            :       end</a>
+<a name="2914"><span class="lineNum">    2914 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h49) begin</span></a>
+<a name="2915"><span class="lineNum">    2915 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2916"><span class="lineNum">    2916 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_73 &lt;= 4'hF;</span></a>
+<a name="2917"><span class="lineNum">    2917 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2918"><span class="lineNum">    2918 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_73 &lt;= 4'h0;</span></a>
+<a name="2919"><span class="lineNum">    2919 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2920"><span class="lineNum">    2920 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_73 &lt;= _newCtr_T_3;</span></a>
+<a name="2921"><span class="lineNum">    2921 </span>            :         else</a>
+<a name="2922"><span class="lineNum">    2922 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_73 &lt;= _newCtr_T_5;</span></a>
+<a name="2923"><span class="lineNum">    2923 </span>            :       end</a>
+<a name="2924"><span class="lineNum">    2924 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h4A) begin</span></a>
+<a name="2925"><span class="lineNum">    2925 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2926"><span class="lineNum">    2926 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_74 &lt;= 4'hF;</span></a>
+<a name="2927"><span class="lineNum">    2927 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2928"><span class="lineNum">    2928 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_74 &lt;= 4'h0;</span></a>
+<a name="2929"><span class="lineNum">    2929 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2930"><span class="lineNum">    2930 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_74 &lt;= _newCtr_T_3;</span></a>
+<a name="2931"><span class="lineNum">    2931 </span>            :         else</a>
+<a name="2932"><span class="lineNum">    2932 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_74 &lt;= _newCtr_T_5;</span></a>
+<a name="2933"><span class="lineNum">    2933 </span>            :       end</a>
+<a name="2934"><span class="lineNum">    2934 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h4B) begin</span></a>
+<a name="2935"><span class="lineNum">    2935 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2936"><span class="lineNum">    2936 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_75 &lt;= 4'hF;</span></a>
+<a name="2937"><span class="lineNum">    2937 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2938"><span class="lineNum">    2938 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_75 &lt;= 4'h0;</span></a>
+<a name="2939"><span class="lineNum">    2939 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2940"><span class="lineNum">    2940 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_75 &lt;= _newCtr_T_3;</span></a>
+<a name="2941"><span class="lineNum">    2941 </span>            :         else</a>
+<a name="2942"><span class="lineNum">    2942 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_75 &lt;= _newCtr_T_5;</span></a>
+<a name="2943"><span class="lineNum">    2943 </span>            :       end</a>
+<a name="2944"><span class="lineNum">    2944 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h4C) begin</span></a>
+<a name="2945"><span class="lineNum">    2945 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2946"><span class="lineNum">    2946 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_76 &lt;= 4'hF;</span></a>
+<a name="2947"><span class="lineNum">    2947 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2948"><span class="lineNum">    2948 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_76 &lt;= 4'h0;</span></a>
+<a name="2949"><span class="lineNum">    2949 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2950"><span class="lineNum">    2950 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_76 &lt;= _newCtr_T_3;</span></a>
+<a name="2951"><span class="lineNum">    2951 </span>            :         else</a>
+<a name="2952"><span class="lineNum">    2952 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_76 &lt;= _newCtr_T_5;</span></a>
+<a name="2953"><span class="lineNum">    2953 </span>            :       end</a>
+<a name="2954"><span class="lineNum">    2954 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h4D) begin</span></a>
+<a name="2955"><span class="lineNum">    2955 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2956"><span class="lineNum">    2956 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_77 &lt;= 4'hF;</span></a>
+<a name="2957"><span class="lineNum">    2957 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2958"><span class="lineNum">    2958 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_77 &lt;= 4'h0;</span></a>
+<a name="2959"><span class="lineNum">    2959 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2960"><span class="lineNum">    2960 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_77 &lt;= _newCtr_T_3;</span></a>
+<a name="2961"><span class="lineNum">    2961 </span>            :         else</a>
+<a name="2962"><span class="lineNum">    2962 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_77 &lt;= _newCtr_T_5;</span></a>
+<a name="2963"><span class="lineNum">    2963 </span>            :       end</a>
+<a name="2964"><span class="lineNum">    2964 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h4E) begin</span></a>
+<a name="2965"><span class="lineNum">    2965 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2966"><span class="lineNum">    2966 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_78 &lt;= 4'hF;</span></a>
+<a name="2967"><span class="lineNum">    2967 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2968"><span class="lineNum">    2968 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_78 &lt;= 4'h0;</span></a>
+<a name="2969"><span class="lineNum">    2969 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2970"><span class="lineNum">    2970 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_78 &lt;= _newCtr_T_3;</span></a>
+<a name="2971"><span class="lineNum">    2971 </span>            :         else</a>
+<a name="2972"><span class="lineNum">    2972 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_78 &lt;= _newCtr_T_5;</span></a>
+<a name="2973"><span class="lineNum">    2973 </span>            :       end</a>
+<a name="2974"><span class="lineNum">    2974 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h4F) begin</span></a>
+<a name="2975"><span class="lineNum">    2975 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2976"><span class="lineNum">    2976 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_79 &lt;= 4'hF;</span></a>
+<a name="2977"><span class="lineNum">    2977 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2978"><span class="lineNum">    2978 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_79 &lt;= 4'h0;</span></a>
+<a name="2979"><span class="lineNum">    2979 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2980"><span class="lineNum">    2980 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_79 &lt;= _newCtr_T_3;</span></a>
+<a name="2981"><span class="lineNum">    2981 </span>            :         else</a>
+<a name="2982"><span class="lineNum">    2982 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_79 &lt;= _newCtr_T_5;</span></a>
+<a name="2983"><span class="lineNum">    2983 </span>            :       end</a>
+<a name="2984"><span class="lineNum">    2984 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h50) begin</span></a>
+<a name="2985"><span class="lineNum">    2985 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2986"><span class="lineNum">    2986 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_80 &lt;= 4'hF;</span></a>
+<a name="2987"><span class="lineNum">    2987 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2988"><span class="lineNum">    2988 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_80 &lt;= 4'h0;</span></a>
+<a name="2989"><span class="lineNum">    2989 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="2990"><span class="lineNum">    2990 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_80 &lt;= _newCtr_T_3;</span></a>
+<a name="2991"><span class="lineNum">    2991 </span>            :         else</a>
+<a name="2992"><span class="lineNum">    2992 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_80 &lt;= _newCtr_T_5;</span></a>
+<a name="2993"><span class="lineNum">    2993 </span>            :       end</a>
+<a name="2994"><span class="lineNum">    2994 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h51) begin</span></a>
+<a name="2995"><span class="lineNum">    2995 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="2996"><span class="lineNum">    2996 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_81 &lt;= 4'hF;</span></a>
+<a name="2997"><span class="lineNum">    2997 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="2998"><span class="lineNum">    2998 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_81 &lt;= 4'h0;</span></a>
+<a name="2999"><span class="lineNum">    2999 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="3000"><span class="lineNum">    3000 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_81 &lt;= _newCtr_T_3;</span></a>
+<a name="3001"><span class="lineNum">    3001 </span>            :         else</a>
+<a name="3002"><span class="lineNum">    3002 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_81 &lt;= _newCtr_T_5;</span></a>
+<a name="3003"><span class="lineNum">    3003 </span>            :       end</a>
+<a name="3004"><span class="lineNum">    3004 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h52) begin</span></a>
+<a name="3005"><span class="lineNum">    3005 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="3006"><span class="lineNum">    3006 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_82 &lt;= 4'hF;</span></a>
+<a name="3007"><span class="lineNum">    3007 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="3008"><span class="lineNum">    3008 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_82 &lt;= 4'h0;</span></a>
+<a name="3009"><span class="lineNum">    3009 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="3010"><span class="lineNum">    3010 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_82 &lt;= _newCtr_T_3;</span></a>
+<a name="3011"><span class="lineNum">    3011 </span>            :         else</a>
+<a name="3012"><span class="lineNum">    3012 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_82 &lt;= _newCtr_T_5;</span></a>
+<a name="3013"><span class="lineNum">    3013 </span>            :       end</a>
+<a name="3014"><span class="lineNum">    3014 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h53) begin</span></a>
+<a name="3015"><span class="lineNum">    3015 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="3016"><span class="lineNum">    3016 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_83 &lt;= 4'hF;</span></a>
+<a name="3017"><span class="lineNum">    3017 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="3018"><span class="lineNum">    3018 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_83 &lt;= 4'h0;</span></a>
+<a name="3019"><span class="lineNum">    3019 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="3020"><span class="lineNum">    3020 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_83 &lt;= _newCtr_T_3;</span></a>
+<a name="3021"><span class="lineNum">    3021 </span>            :         else</a>
+<a name="3022"><span class="lineNum">    3022 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_83 &lt;= _newCtr_T_5;</span></a>
+<a name="3023"><span class="lineNum">    3023 </span>            :       end</a>
+<a name="3024"><span class="lineNum">    3024 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h54) begin</span></a>
+<a name="3025"><span class="lineNum">    3025 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="3026"><span class="lineNum">    3026 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_84 &lt;= 4'hF;</span></a>
+<a name="3027"><span class="lineNum">    3027 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="3028"><span class="lineNum">    3028 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_84 &lt;= 4'h0;</span></a>
+<a name="3029"><span class="lineNum">    3029 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="3030"><span class="lineNum">    3030 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_84 &lt;= _newCtr_T_3;</span></a>
+<a name="3031"><span class="lineNum">    3031 </span>            :         else</a>
+<a name="3032"><span class="lineNum">    3032 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_84 &lt;= _newCtr_T_5;</span></a>
+<a name="3033"><span class="lineNum">    3033 </span>            :       end</a>
+<a name="3034"><span class="lineNum">    3034 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h55) begin</span></a>
+<a name="3035"><span class="lineNum">    3035 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="3036"><span class="lineNum">    3036 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_85 &lt;= 4'hF;</span></a>
+<a name="3037"><span class="lineNum">    3037 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="3038"><span class="lineNum">    3038 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_85 &lt;= 4'h0;</span></a>
+<a name="3039"><span class="lineNum">    3039 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="3040"><span class="lineNum">    3040 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_85 &lt;= _newCtr_T_3;</span></a>
+<a name="3041"><span class="lineNum">    3041 </span>            :         else</a>
+<a name="3042"><span class="lineNum">    3042 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_85 &lt;= _newCtr_T_5;</span></a>
+<a name="3043"><span class="lineNum">    3043 </span>            :       end</a>
+<a name="3044"><span class="lineNum">    3044 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h56) begin</span></a>
+<a name="3045"><span class="lineNum">    3045 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="3046"><span class="lineNum">    3046 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_86 &lt;= 4'hF;</span></a>
+<a name="3047"><span class="lineNum">    3047 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="3048"><span class="lineNum">    3048 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_86 &lt;= 4'h0;</span></a>
+<a name="3049"><span class="lineNum">    3049 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="3050"><span class="lineNum">    3050 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_86 &lt;= _newCtr_T_3;</span></a>
+<a name="3051"><span class="lineNum">    3051 </span>            :         else</a>
+<a name="3052"><span class="lineNum">    3052 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_86 &lt;= _newCtr_T_5;</span></a>
+<a name="3053"><span class="lineNum">    3053 </span>            :       end</a>
+<a name="3054"><span class="lineNum">    3054 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h57) begin</span></a>
+<a name="3055"><span class="lineNum">    3055 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="3056"><span class="lineNum">    3056 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_87 &lt;= 4'hF;</span></a>
+<a name="3057"><span class="lineNum">    3057 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="3058"><span class="lineNum">    3058 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_87 &lt;= 4'h0;</span></a>
+<a name="3059"><span class="lineNum">    3059 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="3060"><span class="lineNum">    3060 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_87 &lt;= _newCtr_T_3;</span></a>
+<a name="3061"><span class="lineNum">    3061 </span>            :         else</a>
+<a name="3062"><span class="lineNum">    3062 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_87 &lt;= _newCtr_T_5;</span></a>
+<a name="3063"><span class="lineNum">    3063 </span>            :       end</a>
+<a name="3064"><span class="lineNum">    3064 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h58) begin</span></a>
+<a name="3065"><span class="lineNum">    3065 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="3066"><span class="lineNum">    3066 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_88 &lt;= 4'hF;</span></a>
+<a name="3067"><span class="lineNum">    3067 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="3068"><span class="lineNum">    3068 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_88 &lt;= 4'h0;</span></a>
+<a name="3069"><span class="lineNum">    3069 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="3070"><span class="lineNum">    3070 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_88 &lt;= _newCtr_T_3;</span></a>
+<a name="3071"><span class="lineNum">    3071 </span>            :         else</a>
+<a name="3072"><span class="lineNum">    3072 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_88 &lt;= _newCtr_T_5;</span></a>
+<a name="3073"><span class="lineNum">    3073 </span>            :       end</a>
+<a name="3074"><span class="lineNum">    3074 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h59) begin</span></a>
+<a name="3075"><span class="lineNum">    3075 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="3076"><span class="lineNum">    3076 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_89 &lt;= 4'hF;</span></a>
+<a name="3077"><span class="lineNum">    3077 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="3078"><span class="lineNum">    3078 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_89 &lt;= 4'h0;</span></a>
+<a name="3079"><span class="lineNum">    3079 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="3080"><span class="lineNum">    3080 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_89 &lt;= _newCtr_T_3;</span></a>
+<a name="3081"><span class="lineNum">    3081 </span>            :         else</a>
+<a name="3082"><span class="lineNum">    3082 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_89 &lt;= _newCtr_T_5;</span></a>
+<a name="3083"><span class="lineNum">    3083 </span>            :       end</a>
+<a name="3084"><span class="lineNum">    3084 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h5A) begin</span></a>
+<a name="3085"><span class="lineNum">    3085 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="3086"><span class="lineNum">    3086 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_90 &lt;= 4'hF;</span></a>
+<a name="3087"><span class="lineNum">    3087 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="3088"><span class="lineNum">    3088 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_90 &lt;= 4'h0;</span></a>
+<a name="3089"><span class="lineNum">    3089 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="3090"><span class="lineNum">    3090 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_90 &lt;= _newCtr_T_3;</span></a>
+<a name="3091"><span class="lineNum">    3091 </span>            :         else</a>
+<a name="3092"><span class="lineNum">    3092 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_90 &lt;= _newCtr_T_5;</span></a>
+<a name="3093"><span class="lineNum">    3093 </span>            :       end</a>
+<a name="3094"><span class="lineNum">    3094 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h5B) begin</span></a>
+<a name="3095"><span class="lineNum">    3095 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="3096"><span class="lineNum">    3096 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_91 &lt;= 4'hF;</span></a>
+<a name="3097"><span class="lineNum">    3097 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="3098"><span class="lineNum">    3098 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_91 &lt;= 4'h0;</span></a>
+<a name="3099"><span class="lineNum">    3099 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="3100"><span class="lineNum">    3100 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_91 &lt;= _newCtr_T_3;</span></a>
+<a name="3101"><span class="lineNum">    3101 </span>            :         else</a>
+<a name="3102"><span class="lineNum">    3102 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_91 &lt;= _newCtr_T_5;</span></a>
+<a name="3103"><span class="lineNum">    3103 </span>            :       end</a>
+<a name="3104"><span class="lineNum">    3104 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h5C) begin</span></a>
+<a name="3105"><span class="lineNum">    3105 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="3106"><span class="lineNum">    3106 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_92 &lt;= 4'hF;</span></a>
+<a name="3107"><span class="lineNum">    3107 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="3108"><span class="lineNum">    3108 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_92 &lt;= 4'h0;</span></a>
+<a name="3109"><span class="lineNum">    3109 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="3110"><span class="lineNum">    3110 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_92 &lt;= _newCtr_T_3;</span></a>
+<a name="3111"><span class="lineNum">    3111 </span>            :         else</a>
+<a name="3112"><span class="lineNum">    3112 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_92 &lt;= _newCtr_T_5;</span></a>
+<a name="3113"><span class="lineNum">    3113 </span>            :       end</a>
+<a name="3114"><span class="lineNum">    3114 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h5D) begin</span></a>
+<a name="3115"><span class="lineNum">    3115 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="3116"><span class="lineNum">    3116 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_93 &lt;= 4'hF;</span></a>
+<a name="3117"><span class="lineNum">    3117 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="3118"><span class="lineNum">    3118 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_93 &lt;= 4'h0;</span></a>
+<a name="3119"><span class="lineNum">    3119 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="3120"><span class="lineNum">    3120 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_93 &lt;= _newCtr_T_3;</span></a>
+<a name="3121"><span class="lineNum">    3121 </span>            :         else</a>
+<a name="3122"><span class="lineNum">    3122 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_93 &lt;= _newCtr_T_5;</span></a>
+<a name="3123"><span class="lineNum">    3123 </span>            :       end</a>
+<a name="3124"><span class="lineNum">    3124 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h5E) begin</span></a>
+<a name="3125"><span class="lineNum">    3125 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="3126"><span class="lineNum">    3126 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_94 &lt;= 4'hF;</span></a>
+<a name="3127"><span class="lineNum">    3127 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="3128"><span class="lineNum">    3128 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_94 &lt;= 4'h0;</span></a>
+<a name="3129"><span class="lineNum">    3129 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="3130"><span class="lineNum">    3130 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_94 &lt;= _newCtr_T_3;</span></a>
+<a name="3131"><span class="lineNum">    3131 </span>            :         else</a>
+<a name="3132"><span class="lineNum">    3132 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_94 &lt;= _newCtr_T_5;</span></a>
+<a name="3133"><span class="lineNum">    3133 </span>            :       end</a>
+<a name="3134"><span class="lineNum">    3134 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h5F) begin</span></a>
+<a name="3135"><span class="lineNum">    3135 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="3136"><span class="lineNum">    3136 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_95 &lt;= 4'hF;</span></a>
+<a name="3137"><span class="lineNum">    3137 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="3138"><span class="lineNum">    3138 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_95 &lt;= 4'h0;</span></a>
+<a name="3139"><span class="lineNum">    3139 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="3140"><span class="lineNum">    3140 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_95 &lt;= _newCtr_T_3;</span></a>
+<a name="3141"><span class="lineNum">    3141 </span>            :         else</a>
+<a name="3142"><span class="lineNum">    3142 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_95 &lt;= _newCtr_T_5;</span></a>
+<a name="3143"><span class="lineNum">    3143 </span>            :       end</a>
+<a name="3144"><span class="lineNum">    3144 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h60) begin</span></a>
+<a name="3145"><span class="lineNum">    3145 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="3146"><span class="lineNum">    3146 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_96 &lt;= 4'hF;</span></a>
+<a name="3147"><span class="lineNum">    3147 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="3148"><span class="lineNum">    3148 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_96 &lt;= 4'h0;</span></a>
+<a name="3149"><span class="lineNum">    3149 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="3150"><span class="lineNum">    3150 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_96 &lt;= _newCtr_T_3;</span></a>
+<a name="3151"><span class="lineNum">    3151 </span>            :         else</a>
+<a name="3152"><span class="lineNum">    3152 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_96 &lt;= _newCtr_T_5;</span></a>
+<a name="3153"><span class="lineNum">    3153 </span>            :       end</a>
+<a name="3154"><span class="lineNum">    3154 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h61) begin</span></a>
+<a name="3155"><span class="lineNum">    3155 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="3156"><span class="lineNum">    3156 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_97 &lt;= 4'hF;</span></a>
+<a name="3157"><span class="lineNum">    3157 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="3158"><span class="lineNum">    3158 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_97 &lt;= 4'h0;</span></a>
+<a name="3159"><span class="lineNum">    3159 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="3160"><span class="lineNum">    3160 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_97 &lt;= _newCtr_T_3;</span></a>
+<a name="3161"><span class="lineNum">    3161 </span>            :         else</a>
+<a name="3162"><span class="lineNum">    3162 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_97 &lt;= _newCtr_T_5;</span></a>
+<a name="3163"><span class="lineNum">    3163 </span>            :       end</a>
+<a name="3164"><span class="lineNum">    3164 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h62) begin</span></a>
+<a name="3165"><span class="lineNum">    3165 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="3166"><span class="lineNum">    3166 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_98 &lt;= 4'hF;</span></a>
+<a name="3167"><span class="lineNum">    3167 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="3168"><span class="lineNum">    3168 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_98 &lt;= 4'h0;</span></a>
+<a name="3169"><span class="lineNum">    3169 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="3170"><span class="lineNum">    3170 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_98 &lt;= _newCtr_T_3;</span></a>
+<a name="3171"><span class="lineNum">    3171 </span>            :         else</a>
+<a name="3172"><span class="lineNum">    3172 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_98 &lt;= _newCtr_T_5;</span></a>
+<a name="3173"><span class="lineNum">    3173 </span>            :       end</a>
+<a name="3174"><span class="lineNum">    3174 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h63) begin</span></a>
+<a name="3175"><span class="lineNum">    3175 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="3176"><span class="lineNum">    3176 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_99 &lt;= 4'hF;</span></a>
+<a name="3177"><span class="lineNum">    3177 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="3178"><span class="lineNum">    3178 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_99 &lt;= 4'h0;</span></a>
+<a name="3179"><span class="lineNum">    3179 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="3180"><span class="lineNum">    3180 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_99 &lt;= _newCtr_T_3;</span></a>
+<a name="3181"><span class="lineNum">    3181 </span>            :         else</a>
+<a name="3182"><span class="lineNum">    3182 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_99 &lt;= _newCtr_T_5;</span></a>
+<a name="3183"><span class="lineNum">    3183 </span>            :       end</a>
+<a name="3184"><span class="lineNum">    3184 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h64) begin</span></a>
+<a name="3185"><span class="lineNum">    3185 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="3186"><span class="lineNum">    3186 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_100 &lt;= 4'hF;</span></a>
+<a name="3187"><span class="lineNum">    3187 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="3188"><span class="lineNum">    3188 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_100 &lt;= 4'h0;</span></a>
+<a name="3189"><span class="lineNum">    3189 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="3190"><span class="lineNum">    3190 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_100 &lt;= _newCtr_T_3;</span></a>
+<a name="3191"><span class="lineNum">    3191 </span>            :         else</a>
+<a name="3192"><span class="lineNum">    3192 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_100 &lt;= _newCtr_T_5;</span></a>
+<a name="3193"><span class="lineNum">    3193 </span>            :       end</a>
+<a name="3194"><span class="lineNum">    3194 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h65) begin</span></a>
+<a name="3195"><span class="lineNum">    3195 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="3196"><span class="lineNum">    3196 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_101 &lt;= 4'hF;</span></a>
+<a name="3197"><span class="lineNum">    3197 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="3198"><span class="lineNum">    3198 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_101 &lt;= 4'h0;</span></a>
+<a name="3199"><span class="lineNum">    3199 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="3200"><span class="lineNum">    3200 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_101 &lt;= _newCtr_T_3;</span></a>
+<a name="3201"><span class="lineNum">    3201 </span>            :         else</a>
+<a name="3202"><span class="lineNum">    3202 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_101 &lt;= _newCtr_T_5;</span></a>
+<a name="3203"><span class="lineNum">    3203 </span>            :       end</a>
+<a name="3204"><span class="lineNum">    3204 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h66) begin</span></a>
+<a name="3205"><span class="lineNum">    3205 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="3206"><span class="lineNum">    3206 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_102 &lt;= 4'hF;</span></a>
+<a name="3207"><span class="lineNum">    3207 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="3208"><span class="lineNum">    3208 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_102 &lt;= 4'h0;</span></a>
+<a name="3209"><span class="lineNum">    3209 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="3210"><span class="lineNum">    3210 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_102 &lt;= _newCtr_T_3;</span></a>
+<a name="3211"><span class="lineNum">    3211 </span>            :         else</a>
+<a name="3212"><span class="lineNum">    3212 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_102 &lt;= _newCtr_T_5;</span></a>
+<a name="3213"><span class="lineNum">    3213 </span>            :       end</a>
+<a name="3214"><span class="lineNum">    3214 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h67) begin</span></a>
+<a name="3215"><span class="lineNum">    3215 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="3216"><span class="lineNum">    3216 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_103 &lt;= 4'hF;</span></a>
+<a name="3217"><span class="lineNum">    3217 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="3218"><span class="lineNum">    3218 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_103 &lt;= 4'h0;</span></a>
+<a name="3219"><span class="lineNum">    3219 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="3220"><span class="lineNum">    3220 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_103 &lt;= _newCtr_T_3;</span></a>
+<a name="3221"><span class="lineNum">    3221 </span>            :         else</a>
+<a name="3222"><span class="lineNum">    3222 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_103 &lt;= _newCtr_T_5;</span></a>
+<a name="3223"><span class="lineNum">    3223 </span>            :       end</a>
+<a name="3224"><span class="lineNum">    3224 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h68) begin</span></a>
+<a name="3225"><span class="lineNum">    3225 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="3226"><span class="lineNum">    3226 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_104 &lt;= 4'hF;</span></a>
+<a name="3227"><span class="lineNum">    3227 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="3228"><span class="lineNum">    3228 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_104 &lt;= 4'h0;</span></a>
+<a name="3229"><span class="lineNum">    3229 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="3230"><span class="lineNum">    3230 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_104 &lt;= _newCtr_T_3;</span></a>
+<a name="3231"><span class="lineNum">    3231 </span>            :         else</a>
+<a name="3232"><span class="lineNum">    3232 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_104 &lt;= _newCtr_T_5;</span></a>
+<a name="3233"><span class="lineNum">    3233 </span>            :       end</a>
+<a name="3234"><span class="lineNum">    3234 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h69) begin</span></a>
+<a name="3235"><span class="lineNum">    3235 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="3236"><span class="lineNum">    3236 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_105 &lt;= 4'hF;</span></a>
+<a name="3237"><span class="lineNum">    3237 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="3238"><span class="lineNum">    3238 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_105 &lt;= 4'h0;</span></a>
+<a name="3239"><span class="lineNum">    3239 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="3240"><span class="lineNum">    3240 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_105 &lt;= _newCtr_T_3;</span></a>
+<a name="3241"><span class="lineNum">    3241 </span>            :         else</a>
+<a name="3242"><span class="lineNum">    3242 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_105 &lt;= _newCtr_T_5;</span></a>
+<a name="3243"><span class="lineNum">    3243 </span>            :       end</a>
+<a name="3244"><span class="lineNum">    3244 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h6A) begin</span></a>
+<a name="3245"><span class="lineNum">    3245 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="3246"><span class="lineNum">    3246 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_106 &lt;= 4'hF;</span></a>
+<a name="3247"><span class="lineNum">    3247 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="3248"><span class="lineNum">    3248 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_106 &lt;= 4'h0;</span></a>
+<a name="3249"><span class="lineNum">    3249 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="3250"><span class="lineNum">    3250 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_106 &lt;= _newCtr_T_3;</span></a>
+<a name="3251"><span class="lineNum">    3251 </span>            :         else</a>
+<a name="3252"><span class="lineNum">    3252 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_106 &lt;= _newCtr_T_5;</span></a>
+<a name="3253"><span class="lineNum">    3253 </span>            :       end</a>
+<a name="3254"><span class="lineNum">    3254 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h6B) begin</span></a>
+<a name="3255"><span class="lineNum">    3255 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="3256"><span class="lineNum">    3256 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_107 &lt;= 4'hF;</span></a>
+<a name="3257"><span class="lineNum">    3257 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="3258"><span class="lineNum">    3258 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_107 &lt;= 4'h0;</span></a>
+<a name="3259"><span class="lineNum">    3259 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="3260"><span class="lineNum">    3260 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_107 &lt;= _newCtr_T_3;</span></a>
+<a name="3261"><span class="lineNum">    3261 </span>            :         else</a>
+<a name="3262"><span class="lineNum">    3262 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_107 &lt;= _newCtr_T_5;</span></a>
+<a name="3263"><span class="lineNum">    3263 </span>            :       end</a>
+<a name="3264"><span class="lineNum">    3264 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h6C) begin</span></a>
+<a name="3265"><span class="lineNum">    3265 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="3266"><span class="lineNum">    3266 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_108 &lt;= 4'hF;</span></a>
+<a name="3267"><span class="lineNum">    3267 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="3268"><span class="lineNum">    3268 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_108 &lt;= 4'h0;</span></a>
+<a name="3269"><span class="lineNum">    3269 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="3270"><span class="lineNum">    3270 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_108 &lt;= _newCtr_T_3;</span></a>
+<a name="3271"><span class="lineNum">    3271 </span>            :         else</a>
+<a name="3272"><span class="lineNum">    3272 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_108 &lt;= _newCtr_T_5;</span></a>
+<a name="3273"><span class="lineNum">    3273 </span>            :       end</a>
+<a name="3274"><span class="lineNum">    3274 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h6D) begin</span></a>
+<a name="3275"><span class="lineNum">    3275 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="3276"><span class="lineNum">    3276 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_109 &lt;= 4'hF;</span></a>
+<a name="3277"><span class="lineNum">    3277 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="3278"><span class="lineNum">    3278 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_109 &lt;= 4'h0;</span></a>
+<a name="3279"><span class="lineNum">    3279 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="3280"><span class="lineNum">    3280 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_109 &lt;= _newCtr_T_3;</span></a>
+<a name="3281"><span class="lineNum">    3281 </span>            :         else</a>
+<a name="3282"><span class="lineNum">    3282 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_109 &lt;= _newCtr_T_5;</span></a>
+<a name="3283"><span class="lineNum">    3283 </span>            :       end</a>
+<a name="3284"><span class="lineNum">    3284 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h6E) begin</span></a>
+<a name="3285"><span class="lineNum">    3285 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="3286"><span class="lineNum">    3286 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_110 &lt;= 4'hF;</span></a>
+<a name="3287"><span class="lineNum">    3287 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="3288"><span class="lineNum">    3288 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_110 &lt;= 4'h0;</span></a>
+<a name="3289"><span class="lineNum">    3289 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="3290"><span class="lineNum">    3290 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_110 &lt;= _newCtr_T_3;</span></a>
+<a name="3291"><span class="lineNum">    3291 </span>            :         else</a>
+<a name="3292"><span class="lineNum">    3292 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_110 &lt;= _newCtr_T_5;</span></a>
+<a name="3293"><span class="lineNum">    3293 </span>            :       end</a>
+<a name="3294"><span class="lineNum">    3294 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h6F) begin</span></a>
+<a name="3295"><span class="lineNum">    3295 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="3296"><span class="lineNum">    3296 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_111 &lt;= 4'hF;</span></a>
+<a name="3297"><span class="lineNum">    3297 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="3298"><span class="lineNum">    3298 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_111 &lt;= 4'h0;</span></a>
+<a name="3299"><span class="lineNum">    3299 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="3300"><span class="lineNum">    3300 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_111 &lt;= _newCtr_T_3;</span></a>
+<a name="3301"><span class="lineNum">    3301 </span>            :         else</a>
+<a name="3302"><span class="lineNum">    3302 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_111 &lt;= _newCtr_T_5;</span></a>
+<a name="3303"><span class="lineNum">    3303 </span>            :       end</a>
+<a name="3304"><span class="lineNum">    3304 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h70) begin</span></a>
+<a name="3305"><span class="lineNum">    3305 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="3306"><span class="lineNum">    3306 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_112 &lt;= 4'hF;</span></a>
+<a name="3307"><span class="lineNum">    3307 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="3308"><span class="lineNum">    3308 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_112 &lt;= 4'h0;</span></a>
+<a name="3309"><span class="lineNum">    3309 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="3310"><span class="lineNum">    3310 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_112 &lt;= _newCtr_T_3;</span></a>
+<a name="3311"><span class="lineNum">    3311 </span>            :         else</a>
+<a name="3312"><span class="lineNum">    3312 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_112 &lt;= _newCtr_T_5;</span></a>
+<a name="3313"><span class="lineNum">    3313 </span>            :       end</a>
+<a name="3314"><span class="lineNum">    3314 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h71) begin</span></a>
+<a name="3315"><span class="lineNum">    3315 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="3316"><span class="lineNum">    3316 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_113 &lt;= 4'hF;</span></a>
+<a name="3317"><span class="lineNum">    3317 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="3318"><span class="lineNum">    3318 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_113 &lt;= 4'h0;</span></a>
+<a name="3319"><span class="lineNum">    3319 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="3320"><span class="lineNum">    3320 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_113 &lt;= _newCtr_T_3;</span></a>
+<a name="3321"><span class="lineNum">    3321 </span>            :         else</a>
+<a name="3322"><span class="lineNum">    3322 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_113 &lt;= _newCtr_T_5;</span></a>
+<a name="3323"><span class="lineNum">    3323 </span>            :       end</a>
+<a name="3324"><span class="lineNum">    3324 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h72) begin</span></a>
+<a name="3325"><span class="lineNum">    3325 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="3326"><span class="lineNum">    3326 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_114 &lt;= 4'hF;</span></a>
+<a name="3327"><span class="lineNum">    3327 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="3328"><span class="lineNum">    3328 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_114 &lt;= 4'h0;</span></a>
+<a name="3329"><span class="lineNum">    3329 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="3330"><span class="lineNum">    3330 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_114 &lt;= _newCtr_T_3;</span></a>
+<a name="3331"><span class="lineNum">    3331 </span>            :         else</a>
+<a name="3332"><span class="lineNum">    3332 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_114 &lt;= _newCtr_T_5;</span></a>
+<a name="3333"><span class="lineNum">    3333 </span>            :       end</a>
+<a name="3334"><span class="lineNum">    3334 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h73) begin</span></a>
+<a name="3335"><span class="lineNum">    3335 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="3336"><span class="lineNum">    3336 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_115 &lt;= 4'hF;</span></a>
+<a name="3337"><span class="lineNum">    3337 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="3338"><span class="lineNum">    3338 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_115 &lt;= 4'h0;</span></a>
+<a name="3339"><span class="lineNum">    3339 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="3340"><span class="lineNum">    3340 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_115 &lt;= _newCtr_T_3;</span></a>
+<a name="3341"><span class="lineNum">    3341 </span>            :         else</a>
+<a name="3342"><span class="lineNum">    3342 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_115 &lt;= _newCtr_T_5;</span></a>
+<a name="3343"><span class="lineNum">    3343 </span>            :       end</a>
+<a name="3344"><span class="lineNum">    3344 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h74) begin</span></a>
+<a name="3345"><span class="lineNum">    3345 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="3346"><span class="lineNum">    3346 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_116 &lt;= 4'hF;</span></a>
+<a name="3347"><span class="lineNum">    3347 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="3348"><span class="lineNum">    3348 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_116 &lt;= 4'h0;</span></a>
+<a name="3349"><span class="lineNum">    3349 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="3350"><span class="lineNum">    3350 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_116 &lt;= _newCtr_T_3;</span></a>
+<a name="3351"><span class="lineNum">    3351 </span>            :         else</a>
+<a name="3352"><span class="lineNum">    3352 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_116 &lt;= _newCtr_T_5;</span></a>
+<a name="3353"><span class="lineNum">    3353 </span>            :       end</a>
+<a name="3354"><span class="lineNum">    3354 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h75) begin</span></a>
+<a name="3355"><span class="lineNum">    3355 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="3356"><span class="lineNum">    3356 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_117 &lt;= 4'hF;</span></a>
+<a name="3357"><span class="lineNum">    3357 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="3358"><span class="lineNum">    3358 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_117 &lt;= 4'h0;</span></a>
+<a name="3359"><span class="lineNum">    3359 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="3360"><span class="lineNum">    3360 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_117 &lt;= _newCtr_T_3;</span></a>
+<a name="3361"><span class="lineNum">    3361 </span>            :         else</a>
+<a name="3362"><span class="lineNum">    3362 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_117 &lt;= _newCtr_T_5;</span></a>
+<a name="3363"><span class="lineNum">    3363 </span>            :       end</a>
+<a name="3364"><span class="lineNum">    3364 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h76) begin</span></a>
+<a name="3365"><span class="lineNum">    3365 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="3366"><span class="lineNum">    3366 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_118 &lt;= 4'hF;</span></a>
+<a name="3367"><span class="lineNum">    3367 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="3368"><span class="lineNum">    3368 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_118 &lt;= 4'h0;</span></a>
+<a name="3369"><span class="lineNum">    3369 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="3370"><span class="lineNum">    3370 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_118 &lt;= _newCtr_T_3;</span></a>
+<a name="3371"><span class="lineNum">    3371 </span>            :         else</a>
+<a name="3372"><span class="lineNum">    3372 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_118 &lt;= _newCtr_T_5;</span></a>
+<a name="3373"><span class="lineNum">    3373 </span>            :       end</a>
+<a name="3374"><span class="lineNum">    3374 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h77) begin</span></a>
+<a name="3375"><span class="lineNum">    3375 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="3376"><span class="lineNum">    3376 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_119 &lt;= 4'hF;</span></a>
+<a name="3377"><span class="lineNum">    3377 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="3378"><span class="lineNum">    3378 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_119 &lt;= 4'h0;</span></a>
+<a name="3379"><span class="lineNum">    3379 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="3380"><span class="lineNum">    3380 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_119 &lt;= _newCtr_T_3;</span></a>
+<a name="3381"><span class="lineNum">    3381 </span>            :         else</a>
+<a name="3382"><span class="lineNum">    3382 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_119 &lt;= _newCtr_T_5;</span></a>
+<a name="3383"><span class="lineNum">    3383 </span>            :       end</a>
+<a name="3384"><span class="lineNum">    3384 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h78) begin</span></a>
+<a name="3385"><span class="lineNum">    3385 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="3386"><span class="lineNum">    3386 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_120 &lt;= 4'hF;</span></a>
+<a name="3387"><span class="lineNum">    3387 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="3388"><span class="lineNum">    3388 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_120 &lt;= 4'h0;</span></a>
+<a name="3389"><span class="lineNum">    3389 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="3390"><span class="lineNum">    3390 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_120 &lt;= _newCtr_T_3;</span></a>
+<a name="3391"><span class="lineNum">    3391 </span>            :         else</a>
+<a name="3392"><span class="lineNum">    3392 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_120 &lt;= _newCtr_T_5;</span></a>
+<a name="3393"><span class="lineNum">    3393 </span>            :       end</a>
+<a name="3394"><span class="lineNum">    3394 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h79) begin</span></a>
+<a name="3395"><span class="lineNum">    3395 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="3396"><span class="lineNum">    3396 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_121 &lt;= 4'hF;</span></a>
+<a name="3397"><span class="lineNum">    3397 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="3398"><span class="lineNum">    3398 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_121 &lt;= 4'h0;</span></a>
+<a name="3399"><span class="lineNum">    3399 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="3400"><span class="lineNum">    3400 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_121 &lt;= _newCtr_T_3;</span></a>
+<a name="3401"><span class="lineNum">    3401 </span>            :         else</a>
+<a name="3402"><span class="lineNum">    3402 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_121 &lt;= _newCtr_T_5;</span></a>
+<a name="3403"><span class="lineNum">    3403 </span>            :       end</a>
+<a name="3404"><span class="lineNum">    3404 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h7A) begin</span></a>
+<a name="3405"><span class="lineNum">    3405 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="3406"><span class="lineNum">    3406 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_122 &lt;= 4'hF;</span></a>
+<a name="3407"><span class="lineNum">    3407 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="3408"><span class="lineNum">    3408 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_122 &lt;= 4'h0;</span></a>
+<a name="3409"><span class="lineNum">    3409 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="3410"><span class="lineNum">    3410 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_122 &lt;= _newCtr_T_3;</span></a>
+<a name="3411"><span class="lineNum">    3411 </span>            :         else</a>
+<a name="3412"><span class="lineNum">    3412 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_122 &lt;= _newCtr_T_5;</span></a>
+<a name="3413"><span class="lineNum">    3413 </span>            :       end</a>
+<a name="3414"><span class="lineNum">    3414 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h7B) begin</span></a>
+<a name="3415"><span class="lineNum">    3415 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="3416"><span class="lineNum">    3416 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_123 &lt;= 4'hF;</span></a>
+<a name="3417"><span class="lineNum">    3417 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="3418"><span class="lineNum">    3418 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_123 &lt;= 4'h0;</span></a>
+<a name="3419"><span class="lineNum">    3419 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="3420"><span class="lineNum">    3420 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_123 &lt;= _newCtr_T_3;</span></a>
+<a name="3421"><span class="lineNum">    3421 </span>            :         else</a>
+<a name="3422"><span class="lineNum">    3422 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_123 &lt;= _newCtr_T_5;</span></a>
+<a name="3423"><span class="lineNum">    3423 </span>            :       end</a>
+<a name="3424"><span class="lineNum">    3424 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h7C) begin</span></a>
+<a name="3425"><span class="lineNum">    3425 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="3426"><span class="lineNum">    3426 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_124 &lt;= 4'hF;</span></a>
+<a name="3427"><span class="lineNum">    3427 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="3428"><span class="lineNum">    3428 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_124 &lt;= 4'h0;</span></a>
+<a name="3429"><span class="lineNum">    3429 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="3430"><span class="lineNum">    3430 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_124 &lt;= _newCtr_T_3;</span></a>
+<a name="3431"><span class="lineNum">    3431 </span>            :         else</a>
+<a name="3432"><span class="lineNum">    3432 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_124 &lt;= _newCtr_T_5;</span></a>
+<a name="3433"><span class="lineNum">    3433 </span>            :       end</a>
+<a name="3434"><span class="lineNum">    3434 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h7D) begin</span></a>
+<a name="3435"><span class="lineNum">    3435 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="3436"><span class="lineNum">    3436 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_125 &lt;= 4'hF;</span></a>
+<a name="3437"><span class="lineNum">    3437 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="3438"><span class="lineNum">    3438 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_125 &lt;= 4'h0;</span></a>
+<a name="3439"><span class="lineNum">    3439 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="3440"><span class="lineNum">    3440 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_125 &lt;= _newCtr_T_3;</span></a>
+<a name="3441"><span class="lineNum">    3441 </span>            :         else</a>
+<a name="3442"><span class="lineNum">    3442 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_125 &lt;= _newCtr_T_5;</span></a>
+<a name="3443"><span class="lineNum">    3443 </span>            :       end</a>
+<a name="3444"><span class="lineNum">    3444 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; io_update_bits_pc[7:1] == 7'h7E) begin</span></a>
+<a name="3445"><span class="lineNum">    3445 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="3446"><span class="lineNum">    3446 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_126 &lt;= 4'hF;</span></a>
+<a name="3447"><span class="lineNum">    3447 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="3448"><span class="lineNum">    3448 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_126 &lt;= 4'h0;</span></a>
+<a name="3449"><span class="lineNum">    3449 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="3450"><span class="lineNum">    3450 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_126 &lt;= _newCtr_T_3;</span></a>
+<a name="3451"><span class="lineNum">    3451 </span>            :         else</a>
+<a name="3452"><span class="lineNum">    3452 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_126 &lt;= _newCtr_T_5;</span></a>
+<a name="3453"><span class="lineNum">    3453 </span>            :       end</a>
+<a name="3454"><span class="lineNum">    3454 </span><span class="lineNoCov">          0 :       if (updateValids_0 &amp; _GEN_69 &amp; (&amp;(io_update_bits_pc[7:1]))) begin</span></a>
+<a name="3455"><span class="lineNum">    3455 </span><span class="lineNoCov">          0 :         if (_newCtr_T)</span></a>
+<a name="3456"><span class="lineNum">    3456 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_127 &lt;= 4'hF;</span></a>
+<a name="3457"><span class="lineNum">    3457 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_2)</span></a>
+<a name="3458"><span class="lineNum">    3458 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_127 &lt;= 4'h0;</span></a>
+<a name="3459"><span class="lineNum">    3459 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect)</span></a>
+<a name="3460"><span class="lineNum">    3460 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_127 &lt;= _newCtr_T_3;</span></a>
+<a name="3461"><span class="lineNum">    3461 </span>            :         else</a>
+<a name="3462"><span class="lineNum">    3462 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_0_127 &lt;= _newCtr_T_5;</span></a>
+<a name="3463"><span class="lineNum">    3463 </span>            :       end</a>
+<a name="3464"><span class="lineNum">    3464 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h0) begin</span></a>
+<a name="3465"><span class="lineNum">    3465 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="3466"><span class="lineNum">    3466 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_0 &lt;= 4'hF;</span></a>
+<a name="3467"><span class="lineNum">    3467 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="3468"><span class="lineNum">    3468 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_0 &lt;= 4'h0;</span></a>
+<a name="3469"><span class="lineNum">    3469 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="3470"><span class="lineNum">    3470 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_0 &lt;= _newCtr_T_12;</span></a>
+<a name="3471"><span class="lineNum">    3471 </span>            :         else</a>
+<a name="3472"><span class="lineNum">    3472 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_0 &lt;= _newCtr_T_14;</span></a>
+<a name="3473"><span class="lineNum">    3473 </span>            :       end</a>
+<a name="3474"><span class="lineNum">    3474 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h1) begin</span></a>
+<a name="3475"><span class="lineNum">    3475 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="3476"><span class="lineNum">    3476 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_1 &lt;= 4'hF;</span></a>
+<a name="3477"><span class="lineNum">    3477 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="3478"><span class="lineNum">    3478 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_1 &lt;= 4'h0;</span></a>
+<a name="3479"><span class="lineNum">    3479 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="3480"><span class="lineNum">    3480 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_1 &lt;= _newCtr_T_12;</span></a>
+<a name="3481"><span class="lineNum">    3481 </span>            :         else</a>
+<a name="3482"><span class="lineNum">    3482 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_1 &lt;= _newCtr_T_14;</span></a>
+<a name="3483"><span class="lineNum">    3483 </span>            :       end</a>
+<a name="3484"><span class="lineNum">    3484 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h2) begin</span></a>
+<a name="3485"><span class="lineNum">    3485 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="3486"><span class="lineNum">    3486 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_2 &lt;= 4'hF;</span></a>
+<a name="3487"><span class="lineNum">    3487 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="3488"><span class="lineNum">    3488 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_2 &lt;= 4'h0;</span></a>
+<a name="3489"><span class="lineNum">    3489 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="3490"><span class="lineNum">    3490 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_2 &lt;= _newCtr_T_12;</span></a>
+<a name="3491"><span class="lineNum">    3491 </span>            :         else</a>
+<a name="3492"><span class="lineNum">    3492 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_2 &lt;= _newCtr_T_14;</span></a>
+<a name="3493"><span class="lineNum">    3493 </span>            :       end</a>
+<a name="3494"><span class="lineNum">    3494 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h3) begin</span></a>
+<a name="3495"><span class="lineNum">    3495 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="3496"><span class="lineNum">    3496 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_3 &lt;= 4'hF;</span></a>
+<a name="3497"><span class="lineNum">    3497 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="3498"><span class="lineNum">    3498 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_3 &lt;= 4'h0;</span></a>
+<a name="3499"><span class="lineNum">    3499 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="3500"><span class="lineNum">    3500 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_3 &lt;= _newCtr_T_12;</span></a>
+<a name="3501"><span class="lineNum">    3501 </span>            :         else</a>
+<a name="3502"><span class="lineNum">    3502 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_3 &lt;= _newCtr_T_14;</span></a>
+<a name="3503"><span class="lineNum">    3503 </span>            :       end</a>
+<a name="3504"><span class="lineNum">    3504 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h4) begin</span></a>
+<a name="3505"><span class="lineNum">    3505 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="3506"><span class="lineNum">    3506 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_4 &lt;= 4'hF;</span></a>
+<a name="3507"><span class="lineNum">    3507 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="3508"><span class="lineNum">    3508 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_4 &lt;= 4'h0;</span></a>
+<a name="3509"><span class="lineNum">    3509 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="3510"><span class="lineNum">    3510 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_4 &lt;= _newCtr_T_12;</span></a>
+<a name="3511"><span class="lineNum">    3511 </span>            :         else</a>
+<a name="3512"><span class="lineNum">    3512 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_4 &lt;= _newCtr_T_14;</span></a>
+<a name="3513"><span class="lineNum">    3513 </span>            :       end</a>
+<a name="3514"><span class="lineNum">    3514 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h5) begin</span></a>
+<a name="3515"><span class="lineNum">    3515 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="3516"><span class="lineNum">    3516 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_5 &lt;= 4'hF;</span></a>
+<a name="3517"><span class="lineNum">    3517 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="3518"><span class="lineNum">    3518 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_5 &lt;= 4'h0;</span></a>
+<a name="3519"><span class="lineNum">    3519 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="3520"><span class="lineNum">    3520 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_5 &lt;= _newCtr_T_12;</span></a>
+<a name="3521"><span class="lineNum">    3521 </span>            :         else</a>
+<a name="3522"><span class="lineNum">    3522 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_5 &lt;= _newCtr_T_14;</span></a>
+<a name="3523"><span class="lineNum">    3523 </span>            :       end</a>
+<a name="3524"><span class="lineNum">    3524 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h6) begin</span></a>
+<a name="3525"><span class="lineNum">    3525 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="3526"><span class="lineNum">    3526 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_6 &lt;= 4'hF;</span></a>
+<a name="3527"><span class="lineNum">    3527 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="3528"><span class="lineNum">    3528 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_6 &lt;= 4'h0;</span></a>
+<a name="3529"><span class="lineNum">    3529 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="3530"><span class="lineNum">    3530 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_6 &lt;= _newCtr_T_12;</span></a>
+<a name="3531"><span class="lineNum">    3531 </span>            :         else</a>
+<a name="3532"><span class="lineNum">    3532 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_6 &lt;= _newCtr_T_14;</span></a>
+<a name="3533"><span class="lineNum">    3533 </span>            :       end</a>
+<a name="3534"><span class="lineNum">    3534 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h7) begin</span></a>
+<a name="3535"><span class="lineNum">    3535 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="3536"><span class="lineNum">    3536 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_7 &lt;= 4'hF;</span></a>
+<a name="3537"><span class="lineNum">    3537 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="3538"><span class="lineNum">    3538 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_7 &lt;= 4'h0;</span></a>
+<a name="3539"><span class="lineNum">    3539 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="3540"><span class="lineNum">    3540 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_7 &lt;= _newCtr_T_12;</span></a>
+<a name="3541"><span class="lineNum">    3541 </span>            :         else</a>
+<a name="3542"><span class="lineNum">    3542 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_7 &lt;= _newCtr_T_14;</span></a>
+<a name="3543"><span class="lineNum">    3543 </span>            :       end</a>
+<a name="3544"><span class="lineNum">    3544 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h8) begin</span></a>
+<a name="3545"><span class="lineNum">    3545 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="3546"><span class="lineNum">    3546 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_8 &lt;= 4'hF;</span></a>
+<a name="3547"><span class="lineNum">    3547 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="3548"><span class="lineNum">    3548 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_8 &lt;= 4'h0;</span></a>
+<a name="3549"><span class="lineNum">    3549 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="3550"><span class="lineNum">    3550 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_8 &lt;= _newCtr_T_12;</span></a>
+<a name="3551"><span class="lineNum">    3551 </span>            :         else</a>
+<a name="3552"><span class="lineNum">    3552 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_8 &lt;= _newCtr_T_14;</span></a>
+<a name="3553"><span class="lineNum">    3553 </span>            :       end</a>
+<a name="3554"><span class="lineNum">    3554 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h9) begin</span></a>
+<a name="3555"><span class="lineNum">    3555 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="3556"><span class="lineNum">    3556 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_9 &lt;= 4'hF;</span></a>
+<a name="3557"><span class="lineNum">    3557 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="3558"><span class="lineNum">    3558 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_9 &lt;= 4'h0;</span></a>
+<a name="3559"><span class="lineNum">    3559 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="3560"><span class="lineNum">    3560 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_9 &lt;= _newCtr_T_12;</span></a>
+<a name="3561"><span class="lineNum">    3561 </span>            :         else</a>
+<a name="3562"><span class="lineNum">    3562 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_9 &lt;= _newCtr_T_14;</span></a>
+<a name="3563"><span class="lineNum">    3563 </span>            :       end</a>
+<a name="3564"><span class="lineNum">    3564 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'hA) begin</span></a>
+<a name="3565"><span class="lineNum">    3565 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="3566"><span class="lineNum">    3566 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_10 &lt;= 4'hF;</span></a>
+<a name="3567"><span class="lineNum">    3567 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="3568"><span class="lineNum">    3568 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_10 &lt;= 4'h0;</span></a>
+<a name="3569"><span class="lineNum">    3569 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="3570"><span class="lineNum">    3570 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_10 &lt;= _newCtr_T_12;</span></a>
+<a name="3571"><span class="lineNum">    3571 </span>            :         else</a>
+<a name="3572"><span class="lineNum">    3572 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_10 &lt;= _newCtr_T_14;</span></a>
+<a name="3573"><span class="lineNum">    3573 </span>            :       end</a>
+<a name="3574"><span class="lineNum">    3574 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'hB) begin</span></a>
+<a name="3575"><span class="lineNum">    3575 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="3576"><span class="lineNum">    3576 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_11 &lt;= 4'hF;</span></a>
+<a name="3577"><span class="lineNum">    3577 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="3578"><span class="lineNum">    3578 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_11 &lt;= 4'h0;</span></a>
+<a name="3579"><span class="lineNum">    3579 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="3580"><span class="lineNum">    3580 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_11 &lt;= _newCtr_T_12;</span></a>
+<a name="3581"><span class="lineNum">    3581 </span>            :         else</a>
+<a name="3582"><span class="lineNum">    3582 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_11 &lt;= _newCtr_T_14;</span></a>
+<a name="3583"><span class="lineNum">    3583 </span>            :       end</a>
+<a name="3584"><span class="lineNum">    3584 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'hC) begin</span></a>
+<a name="3585"><span class="lineNum">    3585 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="3586"><span class="lineNum">    3586 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_12 &lt;= 4'hF;</span></a>
+<a name="3587"><span class="lineNum">    3587 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="3588"><span class="lineNum">    3588 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_12 &lt;= 4'h0;</span></a>
+<a name="3589"><span class="lineNum">    3589 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="3590"><span class="lineNum">    3590 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_12 &lt;= _newCtr_T_12;</span></a>
+<a name="3591"><span class="lineNum">    3591 </span>            :         else</a>
+<a name="3592"><span class="lineNum">    3592 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_12 &lt;= _newCtr_T_14;</span></a>
+<a name="3593"><span class="lineNum">    3593 </span>            :       end</a>
+<a name="3594"><span class="lineNum">    3594 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'hD) begin</span></a>
+<a name="3595"><span class="lineNum">    3595 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="3596"><span class="lineNum">    3596 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_13 &lt;= 4'hF;</span></a>
+<a name="3597"><span class="lineNum">    3597 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="3598"><span class="lineNum">    3598 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_13 &lt;= 4'h0;</span></a>
+<a name="3599"><span class="lineNum">    3599 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="3600"><span class="lineNum">    3600 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_13 &lt;= _newCtr_T_12;</span></a>
+<a name="3601"><span class="lineNum">    3601 </span>            :         else</a>
+<a name="3602"><span class="lineNum">    3602 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_13 &lt;= _newCtr_T_14;</span></a>
+<a name="3603"><span class="lineNum">    3603 </span>            :       end</a>
+<a name="3604"><span class="lineNum">    3604 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'hE) begin</span></a>
+<a name="3605"><span class="lineNum">    3605 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="3606"><span class="lineNum">    3606 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_14 &lt;= 4'hF;</span></a>
+<a name="3607"><span class="lineNum">    3607 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="3608"><span class="lineNum">    3608 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_14 &lt;= 4'h0;</span></a>
+<a name="3609"><span class="lineNum">    3609 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="3610"><span class="lineNum">    3610 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_14 &lt;= _newCtr_T_12;</span></a>
+<a name="3611"><span class="lineNum">    3611 </span>            :         else</a>
+<a name="3612"><span class="lineNum">    3612 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_14 &lt;= _newCtr_T_14;</span></a>
+<a name="3613"><span class="lineNum">    3613 </span>            :       end</a>
+<a name="3614"><span class="lineNum">    3614 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'hF) begin</span></a>
+<a name="3615"><span class="lineNum">    3615 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="3616"><span class="lineNum">    3616 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_15 &lt;= 4'hF;</span></a>
+<a name="3617"><span class="lineNum">    3617 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="3618"><span class="lineNum">    3618 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_15 &lt;= 4'h0;</span></a>
+<a name="3619"><span class="lineNum">    3619 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="3620"><span class="lineNum">    3620 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_15 &lt;= _newCtr_T_12;</span></a>
+<a name="3621"><span class="lineNum">    3621 </span>            :         else</a>
+<a name="3622"><span class="lineNum">    3622 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_15 &lt;= _newCtr_T_14;</span></a>
+<a name="3623"><span class="lineNum">    3623 </span>            :       end</a>
+<a name="3624"><span class="lineNum">    3624 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h10) begin</span></a>
+<a name="3625"><span class="lineNum">    3625 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="3626"><span class="lineNum">    3626 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_16 &lt;= 4'hF;</span></a>
+<a name="3627"><span class="lineNum">    3627 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="3628"><span class="lineNum">    3628 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_16 &lt;= 4'h0;</span></a>
+<a name="3629"><span class="lineNum">    3629 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="3630"><span class="lineNum">    3630 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_16 &lt;= _newCtr_T_12;</span></a>
+<a name="3631"><span class="lineNum">    3631 </span>            :         else</a>
+<a name="3632"><span class="lineNum">    3632 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_16 &lt;= _newCtr_T_14;</span></a>
+<a name="3633"><span class="lineNum">    3633 </span>            :       end</a>
+<a name="3634"><span class="lineNum">    3634 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h11) begin</span></a>
+<a name="3635"><span class="lineNum">    3635 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="3636"><span class="lineNum">    3636 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_17 &lt;= 4'hF;</span></a>
+<a name="3637"><span class="lineNum">    3637 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="3638"><span class="lineNum">    3638 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_17 &lt;= 4'h0;</span></a>
+<a name="3639"><span class="lineNum">    3639 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="3640"><span class="lineNum">    3640 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_17 &lt;= _newCtr_T_12;</span></a>
+<a name="3641"><span class="lineNum">    3641 </span>            :         else</a>
+<a name="3642"><span class="lineNum">    3642 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_17 &lt;= _newCtr_T_14;</span></a>
+<a name="3643"><span class="lineNum">    3643 </span>            :       end</a>
+<a name="3644"><span class="lineNum">    3644 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h12) begin</span></a>
+<a name="3645"><span class="lineNum">    3645 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="3646"><span class="lineNum">    3646 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_18 &lt;= 4'hF;</span></a>
+<a name="3647"><span class="lineNum">    3647 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="3648"><span class="lineNum">    3648 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_18 &lt;= 4'h0;</span></a>
+<a name="3649"><span class="lineNum">    3649 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="3650"><span class="lineNum">    3650 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_18 &lt;= _newCtr_T_12;</span></a>
+<a name="3651"><span class="lineNum">    3651 </span>            :         else</a>
+<a name="3652"><span class="lineNum">    3652 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_18 &lt;= _newCtr_T_14;</span></a>
+<a name="3653"><span class="lineNum">    3653 </span>            :       end</a>
+<a name="3654"><span class="lineNum">    3654 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h13) begin</span></a>
+<a name="3655"><span class="lineNum">    3655 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="3656"><span class="lineNum">    3656 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_19 &lt;= 4'hF;</span></a>
+<a name="3657"><span class="lineNum">    3657 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="3658"><span class="lineNum">    3658 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_19 &lt;= 4'h0;</span></a>
+<a name="3659"><span class="lineNum">    3659 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="3660"><span class="lineNum">    3660 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_19 &lt;= _newCtr_T_12;</span></a>
+<a name="3661"><span class="lineNum">    3661 </span>            :         else</a>
+<a name="3662"><span class="lineNum">    3662 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_19 &lt;= _newCtr_T_14;</span></a>
+<a name="3663"><span class="lineNum">    3663 </span>            :       end</a>
+<a name="3664"><span class="lineNum">    3664 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h14) begin</span></a>
+<a name="3665"><span class="lineNum">    3665 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="3666"><span class="lineNum">    3666 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_20 &lt;= 4'hF;</span></a>
+<a name="3667"><span class="lineNum">    3667 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="3668"><span class="lineNum">    3668 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_20 &lt;= 4'h0;</span></a>
+<a name="3669"><span class="lineNum">    3669 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="3670"><span class="lineNum">    3670 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_20 &lt;= _newCtr_T_12;</span></a>
+<a name="3671"><span class="lineNum">    3671 </span>            :         else</a>
+<a name="3672"><span class="lineNum">    3672 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_20 &lt;= _newCtr_T_14;</span></a>
+<a name="3673"><span class="lineNum">    3673 </span>            :       end</a>
+<a name="3674"><span class="lineNum">    3674 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h15) begin</span></a>
+<a name="3675"><span class="lineNum">    3675 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="3676"><span class="lineNum">    3676 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_21 &lt;= 4'hF;</span></a>
+<a name="3677"><span class="lineNum">    3677 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="3678"><span class="lineNum">    3678 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_21 &lt;= 4'h0;</span></a>
+<a name="3679"><span class="lineNum">    3679 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="3680"><span class="lineNum">    3680 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_21 &lt;= _newCtr_T_12;</span></a>
+<a name="3681"><span class="lineNum">    3681 </span>            :         else</a>
+<a name="3682"><span class="lineNum">    3682 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_21 &lt;= _newCtr_T_14;</span></a>
+<a name="3683"><span class="lineNum">    3683 </span>            :       end</a>
+<a name="3684"><span class="lineNum">    3684 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h16) begin</span></a>
+<a name="3685"><span class="lineNum">    3685 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="3686"><span class="lineNum">    3686 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_22 &lt;= 4'hF;</span></a>
+<a name="3687"><span class="lineNum">    3687 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="3688"><span class="lineNum">    3688 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_22 &lt;= 4'h0;</span></a>
+<a name="3689"><span class="lineNum">    3689 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="3690"><span class="lineNum">    3690 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_22 &lt;= _newCtr_T_12;</span></a>
+<a name="3691"><span class="lineNum">    3691 </span>            :         else</a>
+<a name="3692"><span class="lineNum">    3692 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_22 &lt;= _newCtr_T_14;</span></a>
+<a name="3693"><span class="lineNum">    3693 </span>            :       end</a>
+<a name="3694"><span class="lineNum">    3694 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h17) begin</span></a>
+<a name="3695"><span class="lineNum">    3695 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="3696"><span class="lineNum">    3696 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_23 &lt;= 4'hF;</span></a>
+<a name="3697"><span class="lineNum">    3697 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="3698"><span class="lineNum">    3698 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_23 &lt;= 4'h0;</span></a>
+<a name="3699"><span class="lineNum">    3699 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="3700"><span class="lineNum">    3700 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_23 &lt;= _newCtr_T_12;</span></a>
+<a name="3701"><span class="lineNum">    3701 </span>            :         else</a>
+<a name="3702"><span class="lineNum">    3702 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_23 &lt;= _newCtr_T_14;</span></a>
+<a name="3703"><span class="lineNum">    3703 </span>            :       end</a>
+<a name="3704"><span class="lineNum">    3704 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h18) begin</span></a>
+<a name="3705"><span class="lineNum">    3705 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="3706"><span class="lineNum">    3706 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_24 &lt;= 4'hF;</span></a>
+<a name="3707"><span class="lineNum">    3707 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="3708"><span class="lineNum">    3708 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_24 &lt;= 4'h0;</span></a>
+<a name="3709"><span class="lineNum">    3709 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="3710"><span class="lineNum">    3710 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_24 &lt;= _newCtr_T_12;</span></a>
+<a name="3711"><span class="lineNum">    3711 </span>            :         else</a>
+<a name="3712"><span class="lineNum">    3712 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_24 &lt;= _newCtr_T_14;</span></a>
+<a name="3713"><span class="lineNum">    3713 </span>            :       end</a>
+<a name="3714"><span class="lineNum">    3714 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h19) begin</span></a>
+<a name="3715"><span class="lineNum">    3715 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="3716"><span class="lineNum">    3716 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_25 &lt;= 4'hF;</span></a>
+<a name="3717"><span class="lineNum">    3717 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="3718"><span class="lineNum">    3718 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_25 &lt;= 4'h0;</span></a>
+<a name="3719"><span class="lineNum">    3719 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="3720"><span class="lineNum">    3720 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_25 &lt;= _newCtr_T_12;</span></a>
+<a name="3721"><span class="lineNum">    3721 </span>            :         else</a>
+<a name="3722"><span class="lineNum">    3722 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_25 &lt;= _newCtr_T_14;</span></a>
+<a name="3723"><span class="lineNum">    3723 </span>            :       end</a>
+<a name="3724"><span class="lineNum">    3724 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h1A) begin</span></a>
+<a name="3725"><span class="lineNum">    3725 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="3726"><span class="lineNum">    3726 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_26 &lt;= 4'hF;</span></a>
+<a name="3727"><span class="lineNum">    3727 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="3728"><span class="lineNum">    3728 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_26 &lt;= 4'h0;</span></a>
+<a name="3729"><span class="lineNum">    3729 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="3730"><span class="lineNum">    3730 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_26 &lt;= _newCtr_T_12;</span></a>
+<a name="3731"><span class="lineNum">    3731 </span>            :         else</a>
+<a name="3732"><span class="lineNum">    3732 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_26 &lt;= _newCtr_T_14;</span></a>
+<a name="3733"><span class="lineNum">    3733 </span>            :       end</a>
+<a name="3734"><span class="lineNum">    3734 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h1B) begin</span></a>
+<a name="3735"><span class="lineNum">    3735 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="3736"><span class="lineNum">    3736 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_27 &lt;= 4'hF;</span></a>
+<a name="3737"><span class="lineNum">    3737 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="3738"><span class="lineNum">    3738 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_27 &lt;= 4'h0;</span></a>
+<a name="3739"><span class="lineNum">    3739 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="3740"><span class="lineNum">    3740 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_27 &lt;= _newCtr_T_12;</span></a>
+<a name="3741"><span class="lineNum">    3741 </span>            :         else</a>
+<a name="3742"><span class="lineNum">    3742 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_27 &lt;= _newCtr_T_14;</span></a>
+<a name="3743"><span class="lineNum">    3743 </span>            :       end</a>
+<a name="3744"><span class="lineNum">    3744 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h1C) begin</span></a>
+<a name="3745"><span class="lineNum">    3745 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="3746"><span class="lineNum">    3746 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_28 &lt;= 4'hF;</span></a>
+<a name="3747"><span class="lineNum">    3747 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="3748"><span class="lineNum">    3748 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_28 &lt;= 4'h0;</span></a>
+<a name="3749"><span class="lineNum">    3749 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="3750"><span class="lineNum">    3750 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_28 &lt;= _newCtr_T_12;</span></a>
+<a name="3751"><span class="lineNum">    3751 </span>            :         else</a>
+<a name="3752"><span class="lineNum">    3752 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_28 &lt;= _newCtr_T_14;</span></a>
+<a name="3753"><span class="lineNum">    3753 </span>            :       end</a>
+<a name="3754"><span class="lineNum">    3754 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h1D) begin</span></a>
+<a name="3755"><span class="lineNum">    3755 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="3756"><span class="lineNum">    3756 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_29 &lt;= 4'hF;</span></a>
+<a name="3757"><span class="lineNum">    3757 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="3758"><span class="lineNum">    3758 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_29 &lt;= 4'h0;</span></a>
+<a name="3759"><span class="lineNum">    3759 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="3760"><span class="lineNum">    3760 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_29 &lt;= _newCtr_T_12;</span></a>
+<a name="3761"><span class="lineNum">    3761 </span>            :         else</a>
+<a name="3762"><span class="lineNum">    3762 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_29 &lt;= _newCtr_T_14;</span></a>
+<a name="3763"><span class="lineNum">    3763 </span>            :       end</a>
+<a name="3764"><span class="lineNum">    3764 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h1E) begin</span></a>
+<a name="3765"><span class="lineNum">    3765 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="3766"><span class="lineNum">    3766 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_30 &lt;= 4'hF;</span></a>
+<a name="3767"><span class="lineNum">    3767 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="3768"><span class="lineNum">    3768 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_30 &lt;= 4'h0;</span></a>
+<a name="3769"><span class="lineNum">    3769 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="3770"><span class="lineNum">    3770 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_30 &lt;= _newCtr_T_12;</span></a>
+<a name="3771"><span class="lineNum">    3771 </span>            :         else</a>
+<a name="3772"><span class="lineNum">    3772 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_30 &lt;= _newCtr_T_14;</span></a>
+<a name="3773"><span class="lineNum">    3773 </span>            :       end</a>
+<a name="3774"><span class="lineNum">    3774 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h1F) begin</span></a>
+<a name="3775"><span class="lineNum">    3775 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="3776"><span class="lineNum">    3776 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_31 &lt;= 4'hF;</span></a>
+<a name="3777"><span class="lineNum">    3777 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="3778"><span class="lineNum">    3778 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_31 &lt;= 4'h0;</span></a>
+<a name="3779"><span class="lineNum">    3779 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="3780"><span class="lineNum">    3780 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_31 &lt;= _newCtr_T_12;</span></a>
+<a name="3781"><span class="lineNum">    3781 </span>            :         else</a>
+<a name="3782"><span class="lineNum">    3782 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_31 &lt;= _newCtr_T_14;</span></a>
+<a name="3783"><span class="lineNum">    3783 </span>            :       end</a>
+<a name="3784"><span class="lineNum">    3784 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h20) begin</span></a>
+<a name="3785"><span class="lineNum">    3785 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="3786"><span class="lineNum">    3786 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_32 &lt;= 4'hF;</span></a>
+<a name="3787"><span class="lineNum">    3787 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="3788"><span class="lineNum">    3788 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_32 &lt;= 4'h0;</span></a>
+<a name="3789"><span class="lineNum">    3789 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="3790"><span class="lineNum">    3790 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_32 &lt;= _newCtr_T_12;</span></a>
+<a name="3791"><span class="lineNum">    3791 </span>            :         else</a>
+<a name="3792"><span class="lineNum">    3792 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_32 &lt;= _newCtr_T_14;</span></a>
+<a name="3793"><span class="lineNum">    3793 </span>            :       end</a>
+<a name="3794"><span class="lineNum">    3794 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h21) begin</span></a>
+<a name="3795"><span class="lineNum">    3795 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="3796"><span class="lineNum">    3796 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_33 &lt;= 4'hF;</span></a>
+<a name="3797"><span class="lineNum">    3797 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="3798"><span class="lineNum">    3798 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_33 &lt;= 4'h0;</span></a>
+<a name="3799"><span class="lineNum">    3799 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="3800"><span class="lineNum">    3800 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_33 &lt;= _newCtr_T_12;</span></a>
+<a name="3801"><span class="lineNum">    3801 </span>            :         else</a>
+<a name="3802"><span class="lineNum">    3802 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_33 &lt;= _newCtr_T_14;</span></a>
+<a name="3803"><span class="lineNum">    3803 </span>            :       end</a>
+<a name="3804"><span class="lineNum">    3804 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h22) begin</span></a>
+<a name="3805"><span class="lineNum">    3805 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="3806"><span class="lineNum">    3806 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_34 &lt;= 4'hF;</span></a>
+<a name="3807"><span class="lineNum">    3807 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="3808"><span class="lineNum">    3808 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_34 &lt;= 4'h0;</span></a>
+<a name="3809"><span class="lineNum">    3809 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="3810"><span class="lineNum">    3810 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_34 &lt;= _newCtr_T_12;</span></a>
+<a name="3811"><span class="lineNum">    3811 </span>            :         else</a>
+<a name="3812"><span class="lineNum">    3812 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_34 &lt;= _newCtr_T_14;</span></a>
+<a name="3813"><span class="lineNum">    3813 </span>            :       end</a>
+<a name="3814"><span class="lineNum">    3814 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h23) begin</span></a>
+<a name="3815"><span class="lineNum">    3815 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="3816"><span class="lineNum">    3816 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_35 &lt;= 4'hF;</span></a>
+<a name="3817"><span class="lineNum">    3817 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="3818"><span class="lineNum">    3818 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_35 &lt;= 4'h0;</span></a>
+<a name="3819"><span class="lineNum">    3819 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="3820"><span class="lineNum">    3820 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_35 &lt;= _newCtr_T_12;</span></a>
+<a name="3821"><span class="lineNum">    3821 </span>            :         else</a>
+<a name="3822"><span class="lineNum">    3822 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_35 &lt;= _newCtr_T_14;</span></a>
+<a name="3823"><span class="lineNum">    3823 </span>            :       end</a>
+<a name="3824"><span class="lineNum">    3824 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h24) begin</span></a>
+<a name="3825"><span class="lineNum">    3825 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="3826"><span class="lineNum">    3826 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_36 &lt;= 4'hF;</span></a>
+<a name="3827"><span class="lineNum">    3827 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="3828"><span class="lineNum">    3828 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_36 &lt;= 4'h0;</span></a>
+<a name="3829"><span class="lineNum">    3829 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="3830"><span class="lineNum">    3830 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_36 &lt;= _newCtr_T_12;</span></a>
+<a name="3831"><span class="lineNum">    3831 </span>            :         else</a>
+<a name="3832"><span class="lineNum">    3832 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_36 &lt;= _newCtr_T_14;</span></a>
+<a name="3833"><span class="lineNum">    3833 </span>            :       end</a>
+<a name="3834"><span class="lineNum">    3834 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h25) begin</span></a>
+<a name="3835"><span class="lineNum">    3835 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="3836"><span class="lineNum">    3836 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_37 &lt;= 4'hF;</span></a>
+<a name="3837"><span class="lineNum">    3837 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="3838"><span class="lineNum">    3838 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_37 &lt;= 4'h0;</span></a>
+<a name="3839"><span class="lineNum">    3839 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="3840"><span class="lineNum">    3840 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_37 &lt;= _newCtr_T_12;</span></a>
+<a name="3841"><span class="lineNum">    3841 </span>            :         else</a>
+<a name="3842"><span class="lineNum">    3842 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_37 &lt;= _newCtr_T_14;</span></a>
+<a name="3843"><span class="lineNum">    3843 </span>            :       end</a>
+<a name="3844"><span class="lineNum">    3844 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h26) begin</span></a>
+<a name="3845"><span class="lineNum">    3845 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="3846"><span class="lineNum">    3846 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_38 &lt;= 4'hF;</span></a>
+<a name="3847"><span class="lineNum">    3847 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="3848"><span class="lineNum">    3848 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_38 &lt;= 4'h0;</span></a>
+<a name="3849"><span class="lineNum">    3849 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="3850"><span class="lineNum">    3850 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_38 &lt;= _newCtr_T_12;</span></a>
+<a name="3851"><span class="lineNum">    3851 </span>            :         else</a>
+<a name="3852"><span class="lineNum">    3852 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_38 &lt;= _newCtr_T_14;</span></a>
+<a name="3853"><span class="lineNum">    3853 </span>            :       end</a>
+<a name="3854"><span class="lineNum">    3854 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h27) begin</span></a>
+<a name="3855"><span class="lineNum">    3855 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="3856"><span class="lineNum">    3856 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_39 &lt;= 4'hF;</span></a>
+<a name="3857"><span class="lineNum">    3857 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="3858"><span class="lineNum">    3858 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_39 &lt;= 4'h0;</span></a>
+<a name="3859"><span class="lineNum">    3859 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="3860"><span class="lineNum">    3860 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_39 &lt;= _newCtr_T_12;</span></a>
+<a name="3861"><span class="lineNum">    3861 </span>            :         else</a>
+<a name="3862"><span class="lineNum">    3862 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_39 &lt;= _newCtr_T_14;</span></a>
+<a name="3863"><span class="lineNum">    3863 </span>            :       end</a>
+<a name="3864"><span class="lineNum">    3864 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h28) begin</span></a>
+<a name="3865"><span class="lineNum">    3865 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="3866"><span class="lineNum">    3866 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_40 &lt;= 4'hF;</span></a>
+<a name="3867"><span class="lineNum">    3867 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="3868"><span class="lineNum">    3868 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_40 &lt;= 4'h0;</span></a>
+<a name="3869"><span class="lineNum">    3869 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="3870"><span class="lineNum">    3870 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_40 &lt;= _newCtr_T_12;</span></a>
+<a name="3871"><span class="lineNum">    3871 </span>            :         else</a>
+<a name="3872"><span class="lineNum">    3872 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_40 &lt;= _newCtr_T_14;</span></a>
+<a name="3873"><span class="lineNum">    3873 </span>            :       end</a>
+<a name="3874"><span class="lineNum">    3874 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h29) begin</span></a>
+<a name="3875"><span class="lineNum">    3875 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="3876"><span class="lineNum">    3876 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_41 &lt;= 4'hF;</span></a>
+<a name="3877"><span class="lineNum">    3877 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="3878"><span class="lineNum">    3878 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_41 &lt;= 4'h0;</span></a>
+<a name="3879"><span class="lineNum">    3879 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="3880"><span class="lineNum">    3880 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_41 &lt;= _newCtr_T_12;</span></a>
+<a name="3881"><span class="lineNum">    3881 </span>            :         else</a>
+<a name="3882"><span class="lineNum">    3882 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_41 &lt;= _newCtr_T_14;</span></a>
+<a name="3883"><span class="lineNum">    3883 </span>            :       end</a>
+<a name="3884"><span class="lineNum">    3884 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h2A) begin</span></a>
+<a name="3885"><span class="lineNum">    3885 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="3886"><span class="lineNum">    3886 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_42 &lt;= 4'hF;</span></a>
+<a name="3887"><span class="lineNum">    3887 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="3888"><span class="lineNum">    3888 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_42 &lt;= 4'h0;</span></a>
+<a name="3889"><span class="lineNum">    3889 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="3890"><span class="lineNum">    3890 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_42 &lt;= _newCtr_T_12;</span></a>
+<a name="3891"><span class="lineNum">    3891 </span>            :         else</a>
+<a name="3892"><span class="lineNum">    3892 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_42 &lt;= _newCtr_T_14;</span></a>
+<a name="3893"><span class="lineNum">    3893 </span>            :       end</a>
+<a name="3894"><span class="lineNum">    3894 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h2B) begin</span></a>
+<a name="3895"><span class="lineNum">    3895 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="3896"><span class="lineNum">    3896 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_43 &lt;= 4'hF;</span></a>
+<a name="3897"><span class="lineNum">    3897 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="3898"><span class="lineNum">    3898 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_43 &lt;= 4'h0;</span></a>
+<a name="3899"><span class="lineNum">    3899 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="3900"><span class="lineNum">    3900 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_43 &lt;= _newCtr_T_12;</span></a>
+<a name="3901"><span class="lineNum">    3901 </span>            :         else</a>
+<a name="3902"><span class="lineNum">    3902 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_43 &lt;= _newCtr_T_14;</span></a>
+<a name="3903"><span class="lineNum">    3903 </span>            :       end</a>
+<a name="3904"><span class="lineNum">    3904 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h2C) begin</span></a>
+<a name="3905"><span class="lineNum">    3905 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="3906"><span class="lineNum">    3906 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_44 &lt;= 4'hF;</span></a>
+<a name="3907"><span class="lineNum">    3907 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="3908"><span class="lineNum">    3908 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_44 &lt;= 4'h0;</span></a>
+<a name="3909"><span class="lineNum">    3909 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="3910"><span class="lineNum">    3910 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_44 &lt;= _newCtr_T_12;</span></a>
+<a name="3911"><span class="lineNum">    3911 </span>            :         else</a>
+<a name="3912"><span class="lineNum">    3912 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_44 &lt;= _newCtr_T_14;</span></a>
+<a name="3913"><span class="lineNum">    3913 </span>            :       end</a>
+<a name="3914"><span class="lineNum">    3914 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h2D) begin</span></a>
+<a name="3915"><span class="lineNum">    3915 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="3916"><span class="lineNum">    3916 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_45 &lt;= 4'hF;</span></a>
+<a name="3917"><span class="lineNum">    3917 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="3918"><span class="lineNum">    3918 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_45 &lt;= 4'h0;</span></a>
+<a name="3919"><span class="lineNum">    3919 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="3920"><span class="lineNum">    3920 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_45 &lt;= _newCtr_T_12;</span></a>
+<a name="3921"><span class="lineNum">    3921 </span>            :         else</a>
+<a name="3922"><span class="lineNum">    3922 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_45 &lt;= _newCtr_T_14;</span></a>
+<a name="3923"><span class="lineNum">    3923 </span>            :       end</a>
+<a name="3924"><span class="lineNum">    3924 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h2E) begin</span></a>
+<a name="3925"><span class="lineNum">    3925 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="3926"><span class="lineNum">    3926 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_46 &lt;= 4'hF;</span></a>
+<a name="3927"><span class="lineNum">    3927 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="3928"><span class="lineNum">    3928 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_46 &lt;= 4'h0;</span></a>
+<a name="3929"><span class="lineNum">    3929 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="3930"><span class="lineNum">    3930 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_46 &lt;= _newCtr_T_12;</span></a>
+<a name="3931"><span class="lineNum">    3931 </span>            :         else</a>
+<a name="3932"><span class="lineNum">    3932 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_46 &lt;= _newCtr_T_14;</span></a>
+<a name="3933"><span class="lineNum">    3933 </span>            :       end</a>
+<a name="3934"><span class="lineNum">    3934 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h2F) begin</span></a>
+<a name="3935"><span class="lineNum">    3935 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="3936"><span class="lineNum">    3936 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_47 &lt;= 4'hF;</span></a>
+<a name="3937"><span class="lineNum">    3937 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="3938"><span class="lineNum">    3938 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_47 &lt;= 4'h0;</span></a>
+<a name="3939"><span class="lineNum">    3939 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="3940"><span class="lineNum">    3940 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_47 &lt;= _newCtr_T_12;</span></a>
+<a name="3941"><span class="lineNum">    3941 </span>            :         else</a>
+<a name="3942"><span class="lineNum">    3942 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_47 &lt;= _newCtr_T_14;</span></a>
+<a name="3943"><span class="lineNum">    3943 </span>            :       end</a>
+<a name="3944"><span class="lineNum">    3944 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h30) begin</span></a>
+<a name="3945"><span class="lineNum">    3945 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="3946"><span class="lineNum">    3946 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_48 &lt;= 4'hF;</span></a>
+<a name="3947"><span class="lineNum">    3947 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="3948"><span class="lineNum">    3948 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_48 &lt;= 4'h0;</span></a>
+<a name="3949"><span class="lineNum">    3949 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="3950"><span class="lineNum">    3950 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_48 &lt;= _newCtr_T_12;</span></a>
+<a name="3951"><span class="lineNum">    3951 </span>            :         else</a>
+<a name="3952"><span class="lineNum">    3952 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_48 &lt;= _newCtr_T_14;</span></a>
+<a name="3953"><span class="lineNum">    3953 </span>            :       end</a>
+<a name="3954"><span class="lineNum">    3954 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h31) begin</span></a>
+<a name="3955"><span class="lineNum">    3955 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="3956"><span class="lineNum">    3956 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_49 &lt;= 4'hF;</span></a>
+<a name="3957"><span class="lineNum">    3957 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="3958"><span class="lineNum">    3958 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_49 &lt;= 4'h0;</span></a>
+<a name="3959"><span class="lineNum">    3959 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="3960"><span class="lineNum">    3960 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_49 &lt;= _newCtr_T_12;</span></a>
+<a name="3961"><span class="lineNum">    3961 </span>            :         else</a>
+<a name="3962"><span class="lineNum">    3962 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_49 &lt;= _newCtr_T_14;</span></a>
+<a name="3963"><span class="lineNum">    3963 </span>            :       end</a>
+<a name="3964"><span class="lineNum">    3964 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h32) begin</span></a>
+<a name="3965"><span class="lineNum">    3965 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="3966"><span class="lineNum">    3966 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_50 &lt;= 4'hF;</span></a>
+<a name="3967"><span class="lineNum">    3967 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="3968"><span class="lineNum">    3968 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_50 &lt;= 4'h0;</span></a>
+<a name="3969"><span class="lineNum">    3969 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="3970"><span class="lineNum">    3970 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_50 &lt;= _newCtr_T_12;</span></a>
+<a name="3971"><span class="lineNum">    3971 </span>            :         else</a>
+<a name="3972"><span class="lineNum">    3972 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_50 &lt;= _newCtr_T_14;</span></a>
+<a name="3973"><span class="lineNum">    3973 </span>            :       end</a>
+<a name="3974"><span class="lineNum">    3974 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h33) begin</span></a>
+<a name="3975"><span class="lineNum">    3975 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="3976"><span class="lineNum">    3976 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_51 &lt;= 4'hF;</span></a>
+<a name="3977"><span class="lineNum">    3977 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="3978"><span class="lineNum">    3978 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_51 &lt;= 4'h0;</span></a>
+<a name="3979"><span class="lineNum">    3979 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="3980"><span class="lineNum">    3980 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_51 &lt;= _newCtr_T_12;</span></a>
+<a name="3981"><span class="lineNum">    3981 </span>            :         else</a>
+<a name="3982"><span class="lineNum">    3982 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_51 &lt;= _newCtr_T_14;</span></a>
+<a name="3983"><span class="lineNum">    3983 </span>            :       end</a>
+<a name="3984"><span class="lineNum">    3984 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h34) begin</span></a>
+<a name="3985"><span class="lineNum">    3985 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="3986"><span class="lineNum">    3986 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_52 &lt;= 4'hF;</span></a>
+<a name="3987"><span class="lineNum">    3987 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="3988"><span class="lineNum">    3988 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_52 &lt;= 4'h0;</span></a>
+<a name="3989"><span class="lineNum">    3989 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="3990"><span class="lineNum">    3990 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_52 &lt;= _newCtr_T_12;</span></a>
+<a name="3991"><span class="lineNum">    3991 </span>            :         else</a>
+<a name="3992"><span class="lineNum">    3992 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_52 &lt;= _newCtr_T_14;</span></a>
+<a name="3993"><span class="lineNum">    3993 </span>            :       end</a>
+<a name="3994"><span class="lineNum">    3994 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h35) begin</span></a>
+<a name="3995"><span class="lineNum">    3995 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="3996"><span class="lineNum">    3996 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_53 &lt;= 4'hF;</span></a>
+<a name="3997"><span class="lineNum">    3997 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="3998"><span class="lineNum">    3998 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_53 &lt;= 4'h0;</span></a>
+<a name="3999"><span class="lineNum">    3999 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4000"><span class="lineNum">    4000 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_53 &lt;= _newCtr_T_12;</span></a>
+<a name="4001"><span class="lineNum">    4001 </span>            :         else</a>
+<a name="4002"><span class="lineNum">    4002 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_53 &lt;= _newCtr_T_14;</span></a>
+<a name="4003"><span class="lineNum">    4003 </span>            :       end</a>
+<a name="4004"><span class="lineNum">    4004 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h36) begin</span></a>
+<a name="4005"><span class="lineNum">    4005 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4006"><span class="lineNum">    4006 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_54 &lt;= 4'hF;</span></a>
+<a name="4007"><span class="lineNum">    4007 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4008"><span class="lineNum">    4008 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_54 &lt;= 4'h0;</span></a>
+<a name="4009"><span class="lineNum">    4009 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4010"><span class="lineNum">    4010 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_54 &lt;= _newCtr_T_12;</span></a>
+<a name="4011"><span class="lineNum">    4011 </span>            :         else</a>
+<a name="4012"><span class="lineNum">    4012 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_54 &lt;= _newCtr_T_14;</span></a>
+<a name="4013"><span class="lineNum">    4013 </span>            :       end</a>
+<a name="4014"><span class="lineNum">    4014 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h37) begin</span></a>
+<a name="4015"><span class="lineNum">    4015 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4016"><span class="lineNum">    4016 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_55 &lt;= 4'hF;</span></a>
+<a name="4017"><span class="lineNum">    4017 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4018"><span class="lineNum">    4018 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_55 &lt;= 4'h0;</span></a>
+<a name="4019"><span class="lineNum">    4019 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4020"><span class="lineNum">    4020 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_55 &lt;= _newCtr_T_12;</span></a>
+<a name="4021"><span class="lineNum">    4021 </span>            :         else</a>
+<a name="4022"><span class="lineNum">    4022 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_55 &lt;= _newCtr_T_14;</span></a>
+<a name="4023"><span class="lineNum">    4023 </span>            :       end</a>
+<a name="4024"><span class="lineNum">    4024 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h38) begin</span></a>
+<a name="4025"><span class="lineNum">    4025 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4026"><span class="lineNum">    4026 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_56 &lt;= 4'hF;</span></a>
+<a name="4027"><span class="lineNum">    4027 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4028"><span class="lineNum">    4028 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_56 &lt;= 4'h0;</span></a>
+<a name="4029"><span class="lineNum">    4029 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4030"><span class="lineNum">    4030 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_56 &lt;= _newCtr_T_12;</span></a>
+<a name="4031"><span class="lineNum">    4031 </span>            :         else</a>
+<a name="4032"><span class="lineNum">    4032 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_56 &lt;= _newCtr_T_14;</span></a>
+<a name="4033"><span class="lineNum">    4033 </span>            :       end</a>
+<a name="4034"><span class="lineNum">    4034 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h39) begin</span></a>
+<a name="4035"><span class="lineNum">    4035 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4036"><span class="lineNum">    4036 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_57 &lt;= 4'hF;</span></a>
+<a name="4037"><span class="lineNum">    4037 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4038"><span class="lineNum">    4038 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_57 &lt;= 4'h0;</span></a>
+<a name="4039"><span class="lineNum">    4039 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4040"><span class="lineNum">    4040 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_57 &lt;= _newCtr_T_12;</span></a>
+<a name="4041"><span class="lineNum">    4041 </span>            :         else</a>
+<a name="4042"><span class="lineNum">    4042 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_57 &lt;= _newCtr_T_14;</span></a>
+<a name="4043"><span class="lineNum">    4043 </span>            :       end</a>
+<a name="4044"><span class="lineNum">    4044 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h3A) begin</span></a>
+<a name="4045"><span class="lineNum">    4045 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4046"><span class="lineNum">    4046 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_58 &lt;= 4'hF;</span></a>
+<a name="4047"><span class="lineNum">    4047 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4048"><span class="lineNum">    4048 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_58 &lt;= 4'h0;</span></a>
+<a name="4049"><span class="lineNum">    4049 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4050"><span class="lineNum">    4050 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_58 &lt;= _newCtr_T_12;</span></a>
+<a name="4051"><span class="lineNum">    4051 </span>            :         else</a>
+<a name="4052"><span class="lineNum">    4052 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_58 &lt;= _newCtr_T_14;</span></a>
+<a name="4053"><span class="lineNum">    4053 </span>            :       end</a>
+<a name="4054"><span class="lineNum">    4054 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h3B) begin</span></a>
+<a name="4055"><span class="lineNum">    4055 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4056"><span class="lineNum">    4056 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_59 &lt;= 4'hF;</span></a>
+<a name="4057"><span class="lineNum">    4057 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4058"><span class="lineNum">    4058 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_59 &lt;= 4'h0;</span></a>
+<a name="4059"><span class="lineNum">    4059 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4060"><span class="lineNum">    4060 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_59 &lt;= _newCtr_T_12;</span></a>
+<a name="4061"><span class="lineNum">    4061 </span>            :         else</a>
+<a name="4062"><span class="lineNum">    4062 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_59 &lt;= _newCtr_T_14;</span></a>
+<a name="4063"><span class="lineNum">    4063 </span>            :       end</a>
+<a name="4064"><span class="lineNum">    4064 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h3C) begin</span></a>
+<a name="4065"><span class="lineNum">    4065 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4066"><span class="lineNum">    4066 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_60 &lt;= 4'hF;</span></a>
+<a name="4067"><span class="lineNum">    4067 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4068"><span class="lineNum">    4068 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_60 &lt;= 4'h0;</span></a>
+<a name="4069"><span class="lineNum">    4069 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4070"><span class="lineNum">    4070 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_60 &lt;= _newCtr_T_12;</span></a>
+<a name="4071"><span class="lineNum">    4071 </span>            :         else</a>
+<a name="4072"><span class="lineNum">    4072 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_60 &lt;= _newCtr_T_14;</span></a>
+<a name="4073"><span class="lineNum">    4073 </span>            :       end</a>
+<a name="4074"><span class="lineNum">    4074 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h3D) begin</span></a>
+<a name="4075"><span class="lineNum">    4075 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4076"><span class="lineNum">    4076 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_61 &lt;= 4'hF;</span></a>
+<a name="4077"><span class="lineNum">    4077 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4078"><span class="lineNum">    4078 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_61 &lt;= 4'h0;</span></a>
+<a name="4079"><span class="lineNum">    4079 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4080"><span class="lineNum">    4080 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_61 &lt;= _newCtr_T_12;</span></a>
+<a name="4081"><span class="lineNum">    4081 </span>            :         else</a>
+<a name="4082"><span class="lineNum">    4082 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_61 &lt;= _newCtr_T_14;</span></a>
+<a name="4083"><span class="lineNum">    4083 </span>            :       end</a>
+<a name="4084"><span class="lineNum">    4084 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h3E) begin</span></a>
+<a name="4085"><span class="lineNum">    4085 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4086"><span class="lineNum">    4086 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_62 &lt;= 4'hF;</span></a>
+<a name="4087"><span class="lineNum">    4087 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4088"><span class="lineNum">    4088 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_62 &lt;= 4'h0;</span></a>
+<a name="4089"><span class="lineNum">    4089 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4090"><span class="lineNum">    4090 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_62 &lt;= _newCtr_T_12;</span></a>
+<a name="4091"><span class="lineNum">    4091 </span>            :         else</a>
+<a name="4092"><span class="lineNum">    4092 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_62 &lt;= _newCtr_T_14;</span></a>
+<a name="4093"><span class="lineNum">    4093 </span>            :       end</a>
+<a name="4094"><span class="lineNum">    4094 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h3F) begin</span></a>
+<a name="4095"><span class="lineNum">    4095 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4096"><span class="lineNum">    4096 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_63 &lt;= 4'hF;</span></a>
+<a name="4097"><span class="lineNum">    4097 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4098"><span class="lineNum">    4098 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_63 &lt;= 4'h0;</span></a>
+<a name="4099"><span class="lineNum">    4099 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4100"><span class="lineNum">    4100 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_63 &lt;= _newCtr_T_12;</span></a>
+<a name="4101"><span class="lineNum">    4101 </span>            :         else</a>
+<a name="4102"><span class="lineNum">    4102 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_63 &lt;= _newCtr_T_14;</span></a>
+<a name="4103"><span class="lineNum">    4103 </span>            :       end</a>
+<a name="4104"><span class="lineNum">    4104 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h40) begin</span></a>
+<a name="4105"><span class="lineNum">    4105 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4106"><span class="lineNum">    4106 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_64 &lt;= 4'hF;</span></a>
+<a name="4107"><span class="lineNum">    4107 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4108"><span class="lineNum">    4108 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_64 &lt;= 4'h0;</span></a>
+<a name="4109"><span class="lineNum">    4109 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4110"><span class="lineNum">    4110 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_64 &lt;= _newCtr_T_12;</span></a>
+<a name="4111"><span class="lineNum">    4111 </span>            :         else</a>
+<a name="4112"><span class="lineNum">    4112 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_64 &lt;= _newCtr_T_14;</span></a>
+<a name="4113"><span class="lineNum">    4113 </span>            :       end</a>
+<a name="4114"><span class="lineNum">    4114 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h41) begin</span></a>
+<a name="4115"><span class="lineNum">    4115 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4116"><span class="lineNum">    4116 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_65 &lt;= 4'hF;</span></a>
+<a name="4117"><span class="lineNum">    4117 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4118"><span class="lineNum">    4118 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_65 &lt;= 4'h0;</span></a>
+<a name="4119"><span class="lineNum">    4119 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4120"><span class="lineNum">    4120 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_65 &lt;= _newCtr_T_12;</span></a>
+<a name="4121"><span class="lineNum">    4121 </span>            :         else</a>
+<a name="4122"><span class="lineNum">    4122 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_65 &lt;= _newCtr_T_14;</span></a>
+<a name="4123"><span class="lineNum">    4123 </span>            :       end</a>
+<a name="4124"><span class="lineNum">    4124 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h42) begin</span></a>
+<a name="4125"><span class="lineNum">    4125 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4126"><span class="lineNum">    4126 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_66 &lt;= 4'hF;</span></a>
+<a name="4127"><span class="lineNum">    4127 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4128"><span class="lineNum">    4128 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_66 &lt;= 4'h0;</span></a>
+<a name="4129"><span class="lineNum">    4129 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4130"><span class="lineNum">    4130 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_66 &lt;= _newCtr_T_12;</span></a>
+<a name="4131"><span class="lineNum">    4131 </span>            :         else</a>
+<a name="4132"><span class="lineNum">    4132 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_66 &lt;= _newCtr_T_14;</span></a>
+<a name="4133"><span class="lineNum">    4133 </span>            :       end</a>
+<a name="4134"><span class="lineNum">    4134 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h43) begin</span></a>
+<a name="4135"><span class="lineNum">    4135 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4136"><span class="lineNum">    4136 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_67 &lt;= 4'hF;</span></a>
+<a name="4137"><span class="lineNum">    4137 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4138"><span class="lineNum">    4138 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_67 &lt;= 4'h0;</span></a>
+<a name="4139"><span class="lineNum">    4139 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4140"><span class="lineNum">    4140 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_67 &lt;= _newCtr_T_12;</span></a>
+<a name="4141"><span class="lineNum">    4141 </span>            :         else</a>
+<a name="4142"><span class="lineNum">    4142 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_67 &lt;= _newCtr_T_14;</span></a>
+<a name="4143"><span class="lineNum">    4143 </span>            :       end</a>
+<a name="4144"><span class="lineNum">    4144 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h44) begin</span></a>
+<a name="4145"><span class="lineNum">    4145 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4146"><span class="lineNum">    4146 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_68 &lt;= 4'hF;</span></a>
+<a name="4147"><span class="lineNum">    4147 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4148"><span class="lineNum">    4148 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_68 &lt;= 4'h0;</span></a>
+<a name="4149"><span class="lineNum">    4149 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4150"><span class="lineNum">    4150 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_68 &lt;= _newCtr_T_12;</span></a>
+<a name="4151"><span class="lineNum">    4151 </span>            :         else</a>
+<a name="4152"><span class="lineNum">    4152 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_68 &lt;= _newCtr_T_14;</span></a>
+<a name="4153"><span class="lineNum">    4153 </span>            :       end</a>
+<a name="4154"><span class="lineNum">    4154 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h45) begin</span></a>
+<a name="4155"><span class="lineNum">    4155 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4156"><span class="lineNum">    4156 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_69 &lt;= 4'hF;</span></a>
+<a name="4157"><span class="lineNum">    4157 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4158"><span class="lineNum">    4158 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_69 &lt;= 4'h0;</span></a>
+<a name="4159"><span class="lineNum">    4159 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4160"><span class="lineNum">    4160 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_69 &lt;= _newCtr_T_12;</span></a>
+<a name="4161"><span class="lineNum">    4161 </span>            :         else</a>
+<a name="4162"><span class="lineNum">    4162 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_69 &lt;= _newCtr_T_14;</span></a>
+<a name="4163"><span class="lineNum">    4163 </span>            :       end</a>
+<a name="4164"><span class="lineNum">    4164 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h46) begin</span></a>
+<a name="4165"><span class="lineNum">    4165 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4166"><span class="lineNum">    4166 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_70 &lt;= 4'hF;</span></a>
+<a name="4167"><span class="lineNum">    4167 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4168"><span class="lineNum">    4168 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_70 &lt;= 4'h0;</span></a>
+<a name="4169"><span class="lineNum">    4169 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4170"><span class="lineNum">    4170 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_70 &lt;= _newCtr_T_12;</span></a>
+<a name="4171"><span class="lineNum">    4171 </span>            :         else</a>
+<a name="4172"><span class="lineNum">    4172 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_70 &lt;= _newCtr_T_14;</span></a>
+<a name="4173"><span class="lineNum">    4173 </span>            :       end</a>
+<a name="4174"><span class="lineNum">    4174 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h47) begin</span></a>
+<a name="4175"><span class="lineNum">    4175 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4176"><span class="lineNum">    4176 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_71 &lt;= 4'hF;</span></a>
+<a name="4177"><span class="lineNum">    4177 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4178"><span class="lineNum">    4178 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_71 &lt;= 4'h0;</span></a>
+<a name="4179"><span class="lineNum">    4179 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4180"><span class="lineNum">    4180 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_71 &lt;= _newCtr_T_12;</span></a>
+<a name="4181"><span class="lineNum">    4181 </span>            :         else</a>
+<a name="4182"><span class="lineNum">    4182 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_71 &lt;= _newCtr_T_14;</span></a>
+<a name="4183"><span class="lineNum">    4183 </span>            :       end</a>
+<a name="4184"><span class="lineNum">    4184 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h48) begin</span></a>
+<a name="4185"><span class="lineNum">    4185 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4186"><span class="lineNum">    4186 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_72 &lt;= 4'hF;</span></a>
+<a name="4187"><span class="lineNum">    4187 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4188"><span class="lineNum">    4188 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_72 &lt;= 4'h0;</span></a>
+<a name="4189"><span class="lineNum">    4189 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4190"><span class="lineNum">    4190 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_72 &lt;= _newCtr_T_12;</span></a>
+<a name="4191"><span class="lineNum">    4191 </span>            :         else</a>
+<a name="4192"><span class="lineNum">    4192 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_72 &lt;= _newCtr_T_14;</span></a>
+<a name="4193"><span class="lineNum">    4193 </span>            :       end</a>
+<a name="4194"><span class="lineNum">    4194 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h49) begin</span></a>
+<a name="4195"><span class="lineNum">    4195 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4196"><span class="lineNum">    4196 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_73 &lt;= 4'hF;</span></a>
+<a name="4197"><span class="lineNum">    4197 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4198"><span class="lineNum">    4198 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_73 &lt;= 4'h0;</span></a>
+<a name="4199"><span class="lineNum">    4199 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4200"><span class="lineNum">    4200 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_73 &lt;= _newCtr_T_12;</span></a>
+<a name="4201"><span class="lineNum">    4201 </span>            :         else</a>
+<a name="4202"><span class="lineNum">    4202 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_73 &lt;= _newCtr_T_14;</span></a>
+<a name="4203"><span class="lineNum">    4203 </span>            :       end</a>
+<a name="4204"><span class="lineNum">    4204 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h4A) begin</span></a>
+<a name="4205"><span class="lineNum">    4205 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4206"><span class="lineNum">    4206 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_74 &lt;= 4'hF;</span></a>
+<a name="4207"><span class="lineNum">    4207 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4208"><span class="lineNum">    4208 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_74 &lt;= 4'h0;</span></a>
+<a name="4209"><span class="lineNum">    4209 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4210"><span class="lineNum">    4210 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_74 &lt;= _newCtr_T_12;</span></a>
+<a name="4211"><span class="lineNum">    4211 </span>            :         else</a>
+<a name="4212"><span class="lineNum">    4212 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_74 &lt;= _newCtr_T_14;</span></a>
+<a name="4213"><span class="lineNum">    4213 </span>            :       end</a>
+<a name="4214"><span class="lineNum">    4214 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h4B) begin</span></a>
+<a name="4215"><span class="lineNum">    4215 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4216"><span class="lineNum">    4216 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_75 &lt;= 4'hF;</span></a>
+<a name="4217"><span class="lineNum">    4217 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4218"><span class="lineNum">    4218 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_75 &lt;= 4'h0;</span></a>
+<a name="4219"><span class="lineNum">    4219 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4220"><span class="lineNum">    4220 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_75 &lt;= _newCtr_T_12;</span></a>
+<a name="4221"><span class="lineNum">    4221 </span>            :         else</a>
+<a name="4222"><span class="lineNum">    4222 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_75 &lt;= _newCtr_T_14;</span></a>
+<a name="4223"><span class="lineNum">    4223 </span>            :       end</a>
+<a name="4224"><span class="lineNum">    4224 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h4C) begin</span></a>
+<a name="4225"><span class="lineNum">    4225 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4226"><span class="lineNum">    4226 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_76 &lt;= 4'hF;</span></a>
+<a name="4227"><span class="lineNum">    4227 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4228"><span class="lineNum">    4228 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_76 &lt;= 4'h0;</span></a>
+<a name="4229"><span class="lineNum">    4229 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4230"><span class="lineNum">    4230 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_76 &lt;= _newCtr_T_12;</span></a>
+<a name="4231"><span class="lineNum">    4231 </span>            :         else</a>
+<a name="4232"><span class="lineNum">    4232 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_76 &lt;= _newCtr_T_14;</span></a>
+<a name="4233"><span class="lineNum">    4233 </span>            :       end</a>
+<a name="4234"><span class="lineNum">    4234 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h4D) begin</span></a>
+<a name="4235"><span class="lineNum">    4235 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4236"><span class="lineNum">    4236 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_77 &lt;= 4'hF;</span></a>
+<a name="4237"><span class="lineNum">    4237 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4238"><span class="lineNum">    4238 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_77 &lt;= 4'h0;</span></a>
+<a name="4239"><span class="lineNum">    4239 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4240"><span class="lineNum">    4240 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_77 &lt;= _newCtr_T_12;</span></a>
+<a name="4241"><span class="lineNum">    4241 </span>            :         else</a>
+<a name="4242"><span class="lineNum">    4242 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_77 &lt;= _newCtr_T_14;</span></a>
+<a name="4243"><span class="lineNum">    4243 </span>            :       end</a>
+<a name="4244"><span class="lineNum">    4244 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h4E) begin</span></a>
+<a name="4245"><span class="lineNum">    4245 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4246"><span class="lineNum">    4246 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_78 &lt;= 4'hF;</span></a>
+<a name="4247"><span class="lineNum">    4247 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4248"><span class="lineNum">    4248 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_78 &lt;= 4'h0;</span></a>
+<a name="4249"><span class="lineNum">    4249 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4250"><span class="lineNum">    4250 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_78 &lt;= _newCtr_T_12;</span></a>
+<a name="4251"><span class="lineNum">    4251 </span>            :         else</a>
+<a name="4252"><span class="lineNum">    4252 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_78 &lt;= _newCtr_T_14;</span></a>
+<a name="4253"><span class="lineNum">    4253 </span>            :       end</a>
+<a name="4254"><span class="lineNum">    4254 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h4F) begin</span></a>
+<a name="4255"><span class="lineNum">    4255 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4256"><span class="lineNum">    4256 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_79 &lt;= 4'hF;</span></a>
+<a name="4257"><span class="lineNum">    4257 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4258"><span class="lineNum">    4258 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_79 &lt;= 4'h0;</span></a>
+<a name="4259"><span class="lineNum">    4259 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4260"><span class="lineNum">    4260 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_79 &lt;= _newCtr_T_12;</span></a>
+<a name="4261"><span class="lineNum">    4261 </span>            :         else</a>
+<a name="4262"><span class="lineNum">    4262 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_79 &lt;= _newCtr_T_14;</span></a>
+<a name="4263"><span class="lineNum">    4263 </span>            :       end</a>
+<a name="4264"><span class="lineNum">    4264 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h50) begin</span></a>
+<a name="4265"><span class="lineNum">    4265 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4266"><span class="lineNum">    4266 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_80 &lt;= 4'hF;</span></a>
+<a name="4267"><span class="lineNum">    4267 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4268"><span class="lineNum">    4268 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_80 &lt;= 4'h0;</span></a>
+<a name="4269"><span class="lineNum">    4269 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4270"><span class="lineNum">    4270 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_80 &lt;= _newCtr_T_12;</span></a>
+<a name="4271"><span class="lineNum">    4271 </span>            :         else</a>
+<a name="4272"><span class="lineNum">    4272 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_80 &lt;= _newCtr_T_14;</span></a>
+<a name="4273"><span class="lineNum">    4273 </span>            :       end</a>
+<a name="4274"><span class="lineNum">    4274 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h51) begin</span></a>
+<a name="4275"><span class="lineNum">    4275 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4276"><span class="lineNum">    4276 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_81 &lt;= 4'hF;</span></a>
+<a name="4277"><span class="lineNum">    4277 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4278"><span class="lineNum">    4278 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_81 &lt;= 4'h0;</span></a>
+<a name="4279"><span class="lineNum">    4279 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4280"><span class="lineNum">    4280 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_81 &lt;= _newCtr_T_12;</span></a>
+<a name="4281"><span class="lineNum">    4281 </span>            :         else</a>
+<a name="4282"><span class="lineNum">    4282 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_81 &lt;= _newCtr_T_14;</span></a>
+<a name="4283"><span class="lineNum">    4283 </span>            :       end</a>
+<a name="4284"><span class="lineNum">    4284 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h52) begin</span></a>
+<a name="4285"><span class="lineNum">    4285 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4286"><span class="lineNum">    4286 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_82 &lt;= 4'hF;</span></a>
+<a name="4287"><span class="lineNum">    4287 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4288"><span class="lineNum">    4288 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_82 &lt;= 4'h0;</span></a>
+<a name="4289"><span class="lineNum">    4289 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4290"><span class="lineNum">    4290 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_82 &lt;= _newCtr_T_12;</span></a>
+<a name="4291"><span class="lineNum">    4291 </span>            :         else</a>
+<a name="4292"><span class="lineNum">    4292 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_82 &lt;= _newCtr_T_14;</span></a>
+<a name="4293"><span class="lineNum">    4293 </span>            :       end</a>
+<a name="4294"><span class="lineNum">    4294 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h53) begin</span></a>
+<a name="4295"><span class="lineNum">    4295 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4296"><span class="lineNum">    4296 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_83 &lt;= 4'hF;</span></a>
+<a name="4297"><span class="lineNum">    4297 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4298"><span class="lineNum">    4298 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_83 &lt;= 4'h0;</span></a>
+<a name="4299"><span class="lineNum">    4299 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4300"><span class="lineNum">    4300 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_83 &lt;= _newCtr_T_12;</span></a>
+<a name="4301"><span class="lineNum">    4301 </span>            :         else</a>
+<a name="4302"><span class="lineNum">    4302 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_83 &lt;= _newCtr_T_14;</span></a>
+<a name="4303"><span class="lineNum">    4303 </span>            :       end</a>
+<a name="4304"><span class="lineNum">    4304 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h54) begin</span></a>
+<a name="4305"><span class="lineNum">    4305 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4306"><span class="lineNum">    4306 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_84 &lt;= 4'hF;</span></a>
+<a name="4307"><span class="lineNum">    4307 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4308"><span class="lineNum">    4308 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_84 &lt;= 4'h0;</span></a>
+<a name="4309"><span class="lineNum">    4309 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4310"><span class="lineNum">    4310 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_84 &lt;= _newCtr_T_12;</span></a>
+<a name="4311"><span class="lineNum">    4311 </span>            :         else</a>
+<a name="4312"><span class="lineNum">    4312 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_84 &lt;= _newCtr_T_14;</span></a>
+<a name="4313"><span class="lineNum">    4313 </span>            :       end</a>
+<a name="4314"><span class="lineNum">    4314 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h55) begin</span></a>
+<a name="4315"><span class="lineNum">    4315 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4316"><span class="lineNum">    4316 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_85 &lt;= 4'hF;</span></a>
+<a name="4317"><span class="lineNum">    4317 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4318"><span class="lineNum">    4318 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_85 &lt;= 4'h0;</span></a>
+<a name="4319"><span class="lineNum">    4319 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4320"><span class="lineNum">    4320 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_85 &lt;= _newCtr_T_12;</span></a>
+<a name="4321"><span class="lineNum">    4321 </span>            :         else</a>
+<a name="4322"><span class="lineNum">    4322 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_85 &lt;= _newCtr_T_14;</span></a>
+<a name="4323"><span class="lineNum">    4323 </span>            :       end</a>
+<a name="4324"><span class="lineNum">    4324 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h56) begin</span></a>
+<a name="4325"><span class="lineNum">    4325 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4326"><span class="lineNum">    4326 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_86 &lt;= 4'hF;</span></a>
+<a name="4327"><span class="lineNum">    4327 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4328"><span class="lineNum">    4328 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_86 &lt;= 4'h0;</span></a>
+<a name="4329"><span class="lineNum">    4329 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4330"><span class="lineNum">    4330 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_86 &lt;= _newCtr_T_12;</span></a>
+<a name="4331"><span class="lineNum">    4331 </span>            :         else</a>
+<a name="4332"><span class="lineNum">    4332 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_86 &lt;= _newCtr_T_14;</span></a>
+<a name="4333"><span class="lineNum">    4333 </span>            :       end</a>
+<a name="4334"><span class="lineNum">    4334 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h57) begin</span></a>
+<a name="4335"><span class="lineNum">    4335 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4336"><span class="lineNum">    4336 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_87 &lt;= 4'hF;</span></a>
+<a name="4337"><span class="lineNum">    4337 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4338"><span class="lineNum">    4338 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_87 &lt;= 4'h0;</span></a>
+<a name="4339"><span class="lineNum">    4339 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4340"><span class="lineNum">    4340 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_87 &lt;= _newCtr_T_12;</span></a>
+<a name="4341"><span class="lineNum">    4341 </span>            :         else</a>
+<a name="4342"><span class="lineNum">    4342 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_87 &lt;= _newCtr_T_14;</span></a>
+<a name="4343"><span class="lineNum">    4343 </span>            :       end</a>
+<a name="4344"><span class="lineNum">    4344 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h58) begin</span></a>
+<a name="4345"><span class="lineNum">    4345 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4346"><span class="lineNum">    4346 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_88 &lt;= 4'hF;</span></a>
+<a name="4347"><span class="lineNum">    4347 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4348"><span class="lineNum">    4348 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_88 &lt;= 4'h0;</span></a>
+<a name="4349"><span class="lineNum">    4349 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4350"><span class="lineNum">    4350 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_88 &lt;= _newCtr_T_12;</span></a>
+<a name="4351"><span class="lineNum">    4351 </span>            :         else</a>
+<a name="4352"><span class="lineNum">    4352 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_88 &lt;= _newCtr_T_14;</span></a>
+<a name="4353"><span class="lineNum">    4353 </span>            :       end</a>
+<a name="4354"><span class="lineNum">    4354 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h59) begin</span></a>
+<a name="4355"><span class="lineNum">    4355 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4356"><span class="lineNum">    4356 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_89 &lt;= 4'hF;</span></a>
+<a name="4357"><span class="lineNum">    4357 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4358"><span class="lineNum">    4358 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_89 &lt;= 4'h0;</span></a>
+<a name="4359"><span class="lineNum">    4359 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4360"><span class="lineNum">    4360 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_89 &lt;= _newCtr_T_12;</span></a>
+<a name="4361"><span class="lineNum">    4361 </span>            :         else</a>
+<a name="4362"><span class="lineNum">    4362 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_89 &lt;= _newCtr_T_14;</span></a>
+<a name="4363"><span class="lineNum">    4363 </span>            :       end</a>
+<a name="4364"><span class="lineNum">    4364 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h5A) begin</span></a>
+<a name="4365"><span class="lineNum">    4365 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4366"><span class="lineNum">    4366 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_90 &lt;= 4'hF;</span></a>
+<a name="4367"><span class="lineNum">    4367 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4368"><span class="lineNum">    4368 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_90 &lt;= 4'h0;</span></a>
+<a name="4369"><span class="lineNum">    4369 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4370"><span class="lineNum">    4370 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_90 &lt;= _newCtr_T_12;</span></a>
+<a name="4371"><span class="lineNum">    4371 </span>            :         else</a>
+<a name="4372"><span class="lineNum">    4372 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_90 &lt;= _newCtr_T_14;</span></a>
+<a name="4373"><span class="lineNum">    4373 </span>            :       end</a>
+<a name="4374"><span class="lineNum">    4374 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h5B) begin</span></a>
+<a name="4375"><span class="lineNum">    4375 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4376"><span class="lineNum">    4376 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_91 &lt;= 4'hF;</span></a>
+<a name="4377"><span class="lineNum">    4377 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4378"><span class="lineNum">    4378 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_91 &lt;= 4'h0;</span></a>
+<a name="4379"><span class="lineNum">    4379 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4380"><span class="lineNum">    4380 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_91 &lt;= _newCtr_T_12;</span></a>
+<a name="4381"><span class="lineNum">    4381 </span>            :         else</a>
+<a name="4382"><span class="lineNum">    4382 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_91 &lt;= _newCtr_T_14;</span></a>
+<a name="4383"><span class="lineNum">    4383 </span>            :       end</a>
+<a name="4384"><span class="lineNum">    4384 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h5C) begin</span></a>
+<a name="4385"><span class="lineNum">    4385 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4386"><span class="lineNum">    4386 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_92 &lt;= 4'hF;</span></a>
+<a name="4387"><span class="lineNum">    4387 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4388"><span class="lineNum">    4388 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_92 &lt;= 4'h0;</span></a>
+<a name="4389"><span class="lineNum">    4389 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4390"><span class="lineNum">    4390 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_92 &lt;= _newCtr_T_12;</span></a>
+<a name="4391"><span class="lineNum">    4391 </span>            :         else</a>
+<a name="4392"><span class="lineNum">    4392 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_92 &lt;= _newCtr_T_14;</span></a>
+<a name="4393"><span class="lineNum">    4393 </span>            :       end</a>
+<a name="4394"><span class="lineNum">    4394 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h5D) begin</span></a>
+<a name="4395"><span class="lineNum">    4395 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4396"><span class="lineNum">    4396 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_93 &lt;= 4'hF;</span></a>
+<a name="4397"><span class="lineNum">    4397 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4398"><span class="lineNum">    4398 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_93 &lt;= 4'h0;</span></a>
+<a name="4399"><span class="lineNum">    4399 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4400"><span class="lineNum">    4400 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_93 &lt;= _newCtr_T_12;</span></a>
+<a name="4401"><span class="lineNum">    4401 </span>            :         else</a>
+<a name="4402"><span class="lineNum">    4402 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_93 &lt;= _newCtr_T_14;</span></a>
+<a name="4403"><span class="lineNum">    4403 </span>            :       end</a>
+<a name="4404"><span class="lineNum">    4404 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h5E) begin</span></a>
+<a name="4405"><span class="lineNum">    4405 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4406"><span class="lineNum">    4406 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_94 &lt;= 4'hF;</span></a>
+<a name="4407"><span class="lineNum">    4407 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4408"><span class="lineNum">    4408 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_94 &lt;= 4'h0;</span></a>
+<a name="4409"><span class="lineNum">    4409 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4410"><span class="lineNum">    4410 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_94 &lt;= _newCtr_T_12;</span></a>
+<a name="4411"><span class="lineNum">    4411 </span>            :         else</a>
+<a name="4412"><span class="lineNum">    4412 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_94 &lt;= _newCtr_T_14;</span></a>
+<a name="4413"><span class="lineNum">    4413 </span>            :       end</a>
+<a name="4414"><span class="lineNum">    4414 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h5F) begin</span></a>
+<a name="4415"><span class="lineNum">    4415 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4416"><span class="lineNum">    4416 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_95 &lt;= 4'hF;</span></a>
+<a name="4417"><span class="lineNum">    4417 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4418"><span class="lineNum">    4418 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_95 &lt;= 4'h0;</span></a>
+<a name="4419"><span class="lineNum">    4419 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4420"><span class="lineNum">    4420 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_95 &lt;= _newCtr_T_12;</span></a>
+<a name="4421"><span class="lineNum">    4421 </span>            :         else</a>
+<a name="4422"><span class="lineNum">    4422 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_95 &lt;= _newCtr_T_14;</span></a>
+<a name="4423"><span class="lineNum">    4423 </span>            :       end</a>
+<a name="4424"><span class="lineNum">    4424 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h60) begin</span></a>
+<a name="4425"><span class="lineNum">    4425 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4426"><span class="lineNum">    4426 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_96 &lt;= 4'hF;</span></a>
+<a name="4427"><span class="lineNum">    4427 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4428"><span class="lineNum">    4428 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_96 &lt;= 4'h0;</span></a>
+<a name="4429"><span class="lineNum">    4429 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4430"><span class="lineNum">    4430 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_96 &lt;= _newCtr_T_12;</span></a>
+<a name="4431"><span class="lineNum">    4431 </span>            :         else</a>
+<a name="4432"><span class="lineNum">    4432 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_96 &lt;= _newCtr_T_14;</span></a>
+<a name="4433"><span class="lineNum">    4433 </span>            :       end</a>
+<a name="4434"><span class="lineNum">    4434 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h61) begin</span></a>
+<a name="4435"><span class="lineNum">    4435 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4436"><span class="lineNum">    4436 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_97 &lt;= 4'hF;</span></a>
+<a name="4437"><span class="lineNum">    4437 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4438"><span class="lineNum">    4438 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_97 &lt;= 4'h0;</span></a>
+<a name="4439"><span class="lineNum">    4439 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4440"><span class="lineNum">    4440 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_97 &lt;= _newCtr_T_12;</span></a>
+<a name="4441"><span class="lineNum">    4441 </span>            :         else</a>
+<a name="4442"><span class="lineNum">    4442 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_97 &lt;= _newCtr_T_14;</span></a>
+<a name="4443"><span class="lineNum">    4443 </span>            :       end</a>
+<a name="4444"><span class="lineNum">    4444 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h62) begin</span></a>
+<a name="4445"><span class="lineNum">    4445 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4446"><span class="lineNum">    4446 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_98 &lt;= 4'hF;</span></a>
+<a name="4447"><span class="lineNum">    4447 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4448"><span class="lineNum">    4448 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_98 &lt;= 4'h0;</span></a>
+<a name="4449"><span class="lineNum">    4449 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4450"><span class="lineNum">    4450 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_98 &lt;= _newCtr_T_12;</span></a>
+<a name="4451"><span class="lineNum">    4451 </span>            :         else</a>
+<a name="4452"><span class="lineNum">    4452 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_98 &lt;= _newCtr_T_14;</span></a>
+<a name="4453"><span class="lineNum">    4453 </span>            :       end</a>
+<a name="4454"><span class="lineNum">    4454 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h63) begin</span></a>
+<a name="4455"><span class="lineNum">    4455 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4456"><span class="lineNum">    4456 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_99 &lt;= 4'hF;</span></a>
+<a name="4457"><span class="lineNum">    4457 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4458"><span class="lineNum">    4458 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_99 &lt;= 4'h0;</span></a>
+<a name="4459"><span class="lineNum">    4459 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4460"><span class="lineNum">    4460 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_99 &lt;= _newCtr_T_12;</span></a>
+<a name="4461"><span class="lineNum">    4461 </span>            :         else</a>
+<a name="4462"><span class="lineNum">    4462 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_99 &lt;= _newCtr_T_14;</span></a>
+<a name="4463"><span class="lineNum">    4463 </span>            :       end</a>
+<a name="4464"><span class="lineNum">    4464 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h64) begin</span></a>
+<a name="4465"><span class="lineNum">    4465 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4466"><span class="lineNum">    4466 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_100 &lt;= 4'hF;</span></a>
+<a name="4467"><span class="lineNum">    4467 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4468"><span class="lineNum">    4468 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_100 &lt;= 4'h0;</span></a>
+<a name="4469"><span class="lineNum">    4469 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4470"><span class="lineNum">    4470 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_100 &lt;= _newCtr_T_12;</span></a>
+<a name="4471"><span class="lineNum">    4471 </span>            :         else</a>
+<a name="4472"><span class="lineNum">    4472 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_100 &lt;= _newCtr_T_14;</span></a>
+<a name="4473"><span class="lineNum">    4473 </span>            :       end</a>
+<a name="4474"><span class="lineNum">    4474 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h65) begin</span></a>
+<a name="4475"><span class="lineNum">    4475 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4476"><span class="lineNum">    4476 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_101 &lt;= 4'hF;</span></a>
+<a name="4477"><span class="lineNum">    4477 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4478"><span class="lineNum">    4478 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_101 &lt;= 4'h0;</span></a>
+<a name="4479"><span class="lineNum">    4479 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4480"><span class="lineNum">    4480 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_101 &lt;= _newCtr_T_12;</span></a>
+<a name="4481"><span class="lineNum">    4481 </span>            :         else</a>
+<a name="4482"><span class="lineNum">    4482 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_101 &lt;= _newCtr_T_14;</span></a>
+<a name="4483"><span class="lineNum">    4483 </span>            :       end</a>
+<a name="4484"><span class="lineNum">    4484 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h66) begin</span></a>
+<a name="4485"><span class="lineNum">    4485 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4486"><span class="lineNum">    4486 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_102 &lt;= 4'hF;</span></a>
+<a name="4487"><span class="lineNum">    4487 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4488"><span class="lineNum">    4488 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_102 &lt;= 4'h0;</span></a>
+<a name="4489"><span class="lineNum">    4489 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4490"><span class="lineNum">    4490 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_102 &lt;= _newCtr_T_12;</span></a>
+<a name="4491"><span class="lineNum">    4491 </span>            :         else</a>
+<a name="4492"><span class="lineNum">    4492 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_102 &lt;= _newCtr_T_14;</span></a>
+<a name="4493"><span class="lineNum">    4493 </span>            :       end</a>
+<a name="4494"><span class="lineNum">    4494 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h67) begin</span></a>
+<a name="4495"><span class="lineNum">    4495 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4496"><span class="lineNum">    4496 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_103 &lt;= 4'hF;</span></a>
+<a name="4497"><span class="lineNum">    4497 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4498"><span class="lineNum">    4498 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_103 &lt;= 4'h0;</span></a>
+<a name="4499"><span class="lineNum">    4499 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4500"><span class="lineNum">    4500 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_103 &lt;= _newCtr_T_12;</span></a>
+<a name="4501"><span class="lineNum">    4501 </span>            :         else</a>
+<a name="4502"><span class="lineNum">    4502 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_103 &lt;= _newCtr_T_14;</span></a>
+<a name="4503"><span class="lineNum">    4503 </span>            :       end</a>
+<a name="4504"><span class="lineNum">    4504 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h68) begin</span></a>
+<a name="4505"><span class="lineNum">    4505 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4506"><span class="lineNum">    4506 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_104 &lt;= 4'hF;</span></a>
+<a name="4507"><span class="lineNum">    4507 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4508"><span class="lineNum">    4508 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_104 &lt;= 4'h0;</span></a>
+<a name="4509"><span class="lineNum">    4509 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4510"><span class="lineNum">    4510 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_104 &lt;= _newCtr_T_12;</span></a>
+<a name="4511"><span class="lineNum">    4511 </span>            :         else</a>
+<a name="4512"><span class="lineNum">    4512 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_104 &lt;= _newCtr_T_14;</span></a>
+<a name="4513"><span class="lineNum">    4513 </span>            :       end</a>
+<a name="4514"><span class="lineNum">    4514 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h69) begin</span></a>
+<a name="4515"><span class="lineNum">    4515 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4516"><span class="lineNum">    4516 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_105 &lt;= 4'hF;</span></a>
+<a name="4517"><span class="lineNum">    4517 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4518"><span class="lineNum">    4518 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_105 &lt;= 4'h0;</span></a>
+<a name="4519"><span class="lineNum">    4519 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4520"><span class="lineNum">    4520 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_105 &lt;= _newCtr_T_12;</span></a>
+<a name="4521"><span class="lineNum">    4521 </span>            :         else</a>
+<a name="4522"><span class="lineNum">    4522 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_105 &lt;= _newCtr_T_14;</span></a>
+<a name="4523"><span class="lineNum">    4523 </span>            :       end</a>
+<a name="4524"><span class="lineNum">    4524 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h6A) begin</span></a>
+<a name="4525"><span class="lineNum">    4525 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4526"><span class="lineNum">    4526 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_106 &lt;= 4'hF;</span></a>
+<a name="4527"><span class="lineNum">    4527 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4528"><span class="lineNum">    4528 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_106 &lt;= 4'h0;</span></a>
+<a name="4529"><span class="lineNum">    4529 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4530"><span class="lineNum">    4530 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_106 &lt;= _newCtr_T_12;</span></a>
+<a name="4531"><span class="lineNum">    4531 </span>            :         else</a>
+<a name="4532"><span class="lineNum">    4532 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_106 &lt;= _newCtr_T_14;</span></a>
+<a name="4533"><span class="lineNum">    4533 </span>            :       end</a>
+<a name="4534"><span class="lineNum">    4534 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h6B) begin</span></a>
+<a name="4535"><span class="lineNum">    4535 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4536"><span class="lineNum">    4536 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_107 &lt;= 4'hF;</span></a>
+<a name="4537"><span class="lineNum">    4537 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4538"><span class="lineNum">    4538 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_107 &lt;= 4'h0;</span></a>
+<a name="4539"><span class="lineNum">    4539 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4540"><span class="lineNum">    4540 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_107 &lt;= _newCtr_T_12;</span></a>
+<a name="4541"><span class="lineNum">    4541 </span>            :         else</a>
+<a name="4542"><span class="lineNum">    4542 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_107 &lt;= _newCtr_T_14;</span></a>
+<a name="4543"><span class="lineNum">    4543 </span>            :       end</a>
+<a name="4544"><span class="lineNum">    4544 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h6C) begin</span></a>
+<a name="4545"><span class="lineNum">    4545 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4546"><span class="lineNum">    4546 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_108 &lt;= 4'hF;</span></a>
+<a name="4547"><span class="lineNum">    4547 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4548"><span class="lineNum">    4548 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_108 &lt;= 4'h0;</span></a>
+<a name="4549"><span class="lineNum">    4549 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4550"><span class="lineNum">    4550 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_108 &lt;= _newCtr_T_12;</span></a>
+<a name="4551"><span class="lineNum">    4551 </span>            :         else</a>
+<a name="4552"><span class="lineNum">    4552 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_108 &lt;= _newCtr_T_14;</span></a>
+<a name="4553"><span class="lineNum">    4553 </span>            :       end</a>
+<a name="4554"><span class="lineNum">    4554 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h6D) begin</span></a>
+<a name="4555"><span class="lineNum">    4555 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4556"><span class="lineNum">    4556 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_109 &lt;= 4'hF;</span></a>
+<a name="4557"><span class="lineNum">    4557 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4558"><span class="lineNum">    4558 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_109 &lt;= 4'h0;</span></a>
+<a name="4559"><span class="lineNum">    4559 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4560"><span class="lineNum">    4560 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_109 &lt;= _newCtr_T_12;</span></a>
+<a name="4561"><span class="lineNum">    4561 </span>            :         else</a>
+<a name="4562"><span class="lineNum">    4562 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_109 &lt;= _newCtr_T_14;</span></a>
+<a name="4563"><span class="lineNum">    4563 </span>            :       end</a>
+<a name="4564"><span class="lineNum">    4564 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h6E) begin</span></a>
+<a name="4565"><span class="lineNum">    4565 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4566"><span class="lineNum">    4566 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_110 &lt;= 4'hF;</span></a>
+<a name="4567"><span class="lineNum">    4567 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4568"><span class="lineNum">    4568 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_110 &lt;= 4'h0;</span></a>
+<a name="4569"><span class="lineNum">    4569 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4570"><span class="lineNum">    4570 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_110 &lt;= _newCtr_T_12;</span></a>
+<a name="4571"><span class="lineNum">    4571 </span>            :         else</a>
+<a name="4572"><span class="lineNum">    4572 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_110 &lt;= _newCtr_T_14;</span></a>
+<a name="4573"><span class="lineNum">    4573 </span>            :       end</a>
+<a name="4574"><span class="lineNum">    4574 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h6F) begin</span></a>
+<a name="4575"><span class="lineNum">    4575 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4576"><span class="lineNum">    4576 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_111 &lt;= 4'hF;</span></a>
+<a name="4577"><span class="lineNum">    4577 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4578"><span class="lineNum">    4578 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_111 &lt;= 4'h0;</span></a>
+<a name="4579"><span class="lineNum">    4579 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4580"><span class="lineNum">    4580 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_111 &lt;= _newCtr_T_12;</span></a>
+<a name="4581"><span class="lineNum">    4581 </span>            :         else</a>
+<a name="4582"><span class="lineNum">    4582 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_111 &lt;= _newCtr_T_14;</span></a>
+<a name="4583"><span class="lineNum">    4583 </span>            :       end</a>
+<a name="4584"><span class="lineNum">    4584 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h70) begin</span></a>
+<a name="4585"><span class="lineNum">    4585 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4586"><span class="lineNum">    4586 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_112 &lt;= 4'hF;</span></a>
+<a name="4587"><span class="lineNum">    4587 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4588"><span class="lineNum">    4588 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_112 &lt;= 4'h0;</span></a>
+<a name="4589"><span class="lineNum">    4589 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4590"><span class="lineNum">    4590 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_112 &lt;= _newCtr_T_12;</span></a>
+<a name="4591"><span class="lineNum">    4591 </span>            :         else</a>
+<a name="4592"><span class="lineNum">    4592 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_112 &lt;= _newCtr_T_14;</span></a>
+<a name="4593"><span class="lineNum">    4593 </span>            :       end</a>
+<a name="4594"><span class="lineNum">    4594 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h71) begin</span></a>
+<a name="4595"><span class="lineNum">    4595 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4596"><span class="lineNum">    4596 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_113 &lt;= 4'hF;</span></a>
+<a name="4597"><span class="lineNum">    4597 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4598"><span class="lineNum">    4598 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_113 &lt;= 4'h0;</span></a>
+<a name="4599"><span class="lineNum">    4599 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4600"><span class="lineNum">    4600 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_113 &lt;= _newCtr_T_12;</span></a>
+<a name="4601"><span class="lineNum">    4601 </span>            :         else</a>
+<a name="4602"><span class="lineNum">    4602 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_113 &lt;= _newCtr_T_14;</span></a>
+<a name="4603"><span class="lineNum">    4603 </span>            :       end</a>
+<a name="4604"><span class="lineNum">    4604 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h72) begin</span></a>
+<a name="4605"><span class="lineNum">    4605 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4606"><span class="lineNum">    4606 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_114 &lt;= 4'hF;</span></a>
+<a name="4607"><span class="lineNum">    4607 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4608"><span class="lineNum">    4608 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_114 &lt;= 4'h0;</span></a>
+<a name="4609"><span class="lineNum">    4609 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4610"><span class="lineNum">    4610 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_114 &lt;= _newCtr_T_12;</span></a>
+<a name="4611"><span class="lineNum">    4611 </span>            :         else</a>
+<a name="4612"><span class="lineNum">    4612 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_114 &lt;= _newCtr_T_14;</span></a>
+<a name="4613"><span class="lineNum">    4613 </span>            :       end</a>
+<a name="4614"><span class="lineNum">    4614 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h73) begin</span></a>
+<a name="4615"><span class="lineNum">    4615 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4616"><span class="lineNum">    4616 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_115 &lt;= 4'hF;</span></a>
+<a name="4617"><span class="lineNum">    4617 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4618"><span class="lineNum">    4618 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_115 &lt;= 4'h0;</span></a>
+<a name="4619"><span class="lineNum">    4619 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4620"><span class="lineNum">    4620 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_115 &lt;= _newCtr_T_12;</span></a>
+<a name="4621"><span class="lineNum">    4621 </span>            :         else</a>
+<a name="4622"><span class="lineNum">    4622 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_115 &lt;= _newCtr_T_14;</span></a>
+<a name="4623"><span class="lineNum">    4623 </span>            :       end</a>
+<a name="4624"><span class="lineNum">    4624 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h74) begin</span></a>
+<a name="4625"><span class="lineNum">    4625 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4626"><span class="lineNum">    4626 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_116 &lt;= 4'hF;</span></a>
+<a name="4627"><span class="lineNum">    4627 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4628"><span class="lineNum">    4628 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_116 &lt;= 4'h0;</span></a>
+<a name="4629"><span class="lineNum">    4629 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4630"><span class="lineNum">    4630 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_116 &lt;= _newCtr_T_12;</span></a>
+<a name="4631"><span class="lineNum">    4631 </span>            :         else</a>
+<a name="4632"><span class="lineNum">    4632 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_116 &lt;= _newCtr_T_14;</span></a>
+<a name="4633"><span class="lineNum">    4633 </span>            :       end</a>
+<a name="4634"><span class="lineNum">    4634 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h75) begin</span></a>
+<a name="4635"><span class="lineNum">    4635 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4636"><span class="lineNum">    4636 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_117 &lt;= 4'hF;</span></a>
+<a name="4637"><span class="lineNum">    4637 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4638"><span class="lineNum">    4638 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_117 &lt;= 4'h0;</span></a>
+<a name="4639"><span class="lineNum">    4639 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4640"><span class="lineNum">    4640 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_117 &lt;= _newCtr_T_12;</span></a>
+<a name="4641"><span class="lineNum">    4641 </span>            :         else</a>
+<a name="4642"><span class="lineNum">    4642 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_117 &lt;= _newCtr_T_14;</span></a>
+<a name="4643"><span class="lineNum">    4643 </span>            :       end</a>
+<a name="4644"><span class="lineNum">    4644 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h76) begin</span></a>
+<a name="4645"><span class="lineNum">    4645 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4646"><span class="lineNum">    4646 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_118 &lt;= 4'hF;</span></a>
+<a name="4647"><span class="lineNum">    4647 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4648"><span class="lineNum">    4648 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_118 &lt;= 4'h0;</span></a>
+<a name="4649"><span class="lineNum">    4649 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4650"><span class="lineNum">    4650 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_118 &lt;= _newCtr_T_12;</span></a>
+<a name="4651"><span class="lineNum">    4651 </span>            :         else</a>
+<a name="4652"><span class="lineNum">    4652 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_118 &lt;= _newCtr_T_14;</span></a>
+<a name="4653"><span class="lineNum">    4653 </span>            :       end</a>
+<a name="4654"><span class="lineNum">    4654 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h77) begin</span></a>
+<a name="4655"><span class="lineNum">    4655 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4656"><span class="lineNum">    4656 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_119 &lt;= 4'hF;</span></a>
+<a name="4657"><span class="lineNum">    4657 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4658"><span class="lineNum">    4658 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_119 &lt;= 4'h0;</span></a>
+<a name="4659"><span class="lineNum">    4659 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4660"><span class="lineNum">    4660 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_119 &lt;= _newCtr_T_12;</span></a>
+<a name="4661"><span class="lineNum">    4661 </span>            :         else</a>
+<a name="4662"><span class="lineNum">    4662 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_119 &lt;= _newCtr_T_14;</span></a>
+<a name="4663"><span class="lineNum">    4663 </span>            :       end</a>
+<a name="4664"><span class="lineNum">    4664 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h78) begin</span></a>
+<a name="4665"><span class="lineNum">    4665 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4666"><span class="lineNum">    4666 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_120 &lt;= 4'hF;</span></a>
+<a name="4667"><span class="lineNum">    4667 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4668"><span class="lineNum">    4668 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_120 &lt;= 4'h0;</span></a>
+<a name="4669"><span class="lineNum">    4669 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4670"><span class="lineNum">    4670 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_120 &lt;= _newCtr_T_12;</span></a>
+<a name="4671"><span class="lineNum">    4671 </span>            :         else</a>
+<a name="4672"><span class="lineNum">    4672 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_120 &lt;= _newCtr_T_14;</span></a>
+<a name="4673"><span class="lineNum">    4673 </span>            :       end</a>
+<a name="4674"><span class="lineNum">    4674 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h79) begin</span></a>
+<a name="4675"><span class="lineNum">    4675 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4676"><span class="lineNum">    4676 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_121 &lt;= 4'hF;</span></a>
+<a name="4677"><span class="lineNum">    4677 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4678"><span class="lineNum">    4678 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_121 &lt;= 4'h0;</span></a>
+<a name="4679"><span class="lineNum">    4679 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4680"><span class="lineNum">    4680 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_121 &lt;= _newCtr_T_12;</span></a>
+<a name="4681"><span class="lineNum">    4681 </span>            :         else</a>
+<a name="4682"><span class="lineNum">    4682 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_121 &lt;= _newCtr_T_14;</span></a>
+<a name="4683"><span class="lineNum">    4683 </span>            :       end</a>
+<a name="4684"><span class="lineNum">    4684 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h7A) begin</span></a>
+<a name="4685"><span class="lineNum">    4685 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4686"><span class="lineNum">    4686 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_122 &lt;= 4'hF;</span></a>
+<a name="4687"><span class="lineNum">    4687 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4688"><span class="lineNum">    4688 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_122 &lt;= 4'h0;</span></a>
+<a name="4689"><span class="lineNum">    4689 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4690"><span class="lineNum">    4690 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_122 &lt;= _newCtr_T_12;</span></a>
+<a name="4691"><span class="lineNum">    4691 </span>            :         else</a>
+<a name="4692"><span class="lineNum">    4692 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_122 &lt;= _newCtr_T_14;</span></a>
+<a name="4693"><span class="lineNum">    4693 </span>            :       end</a>
+<a name="4694"><span class="lineNum">    4694 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h7B) begin</span></a>
+<a name="4695"><span class="lineNum">    4695 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4696"><span class="lineNum">    4696 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_123 &lt;= 4'hF;</span></a>
+<a name="4697"><span class="lineNum">    4697 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4698"><span class="lineNum">    4698 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_123 &lt;= 4'h0;</span></a>
+<a name="4699"><span class="lineNum">    4699 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4700"><span class="lineNum">    4700 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_123 &lt;= _newCtr_T_12;</span></a>
+<a name="4701"><span class="lineNum">    4701 </span>            :         else</a>
+<a name="4702"><span class="lineNum">    4702 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_123 &lt;= _newCtr_T_14;</span></a>
+<a name="4703"><span class="lineNum">    4703 </span>            :       end</a>
+<a name="4704"><span class="lineNum">    4704 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h7C) begin</span></a>
+<a name="4705"><span class="lineNum">    4705 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4706"><span class="lineNum">    4706 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_124 &lt;= 4'hF;</span></a>
+<a name="4707"><span class="lineNum">    4707 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4708"><span class="lineNum">    4708 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_124 &lt;= 4'h0;</span></a>
+<a name="4709"><span class="lineNum">    4709 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4710"><span class="lineNum">    4710 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_124 &lt;= _newCtr_T_12;</span></a>
+<a name="4711"><span class="lineNum">    4711 </span>            :         else</a>
+<a name="4712"><span class="lineNum">    4712 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_124 &lt;= _newCtr_T_14;</span></a>
+<a name="4713"><span class="lineNum">    4713 </span>            :       end</a>
+<a name="4714"><span class="lineNum">    4714 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h7D) begin</span></a>
+<a name="4715"><span class="lineNum">    4715 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4716"><span class="lineNum">    4716 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_125 &lt;= 4'hF;</span></a>
+<a name="4717"><span class="lineNum">    4717 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4718"><span class="lineNum">    4718 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_125 &lt;= 4'h0;</span></a>
+<a name="4719"><span class="lineNum">    4719 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4720"><span class="lineNum">    4720 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_125 &lt;= _newCtr_T_12;</span></a>
+<a name="4721"><span class="lineNum">    4721 </span>            :         else</a>
+<a name="4722"><span class="lineNum">    4722 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_125 &lt;= _newCtr_T_14;</span></a>
+<a name="4723"><span class="lineNum">    4723 </span>            :       end</a>
+<a name="4724"><span class="lineNum">    4724 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; io_update_bits_pc[7:1] == 7'h7E) begin</span></a>
+<a name="4725"><span class="lineNum">    4725 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4726"><span class="lineNum">    4726 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_126 &lt;= 4'hF;</span></a>
+<a name="4727"><span class="lineNum">    4727 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4728"><span class="lineNum">    4728 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_126 &lt;= 4'h0;</span></a>
+<a name="4729"><span class="lineNum">    4729 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4730"><span class="lineNum">    4730 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_126 &lt;= _newCtr_T_12;</span></a>
+<a name="4731"><span class="lineNum">    4731 </span>            :         else</a>
+<a name="4732"><span class="lineNum">    4732 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_126 &lt;= _newCtr_T_14;</span></a>
+<a name="4733"><span class="lineNum">    4733 </span>            :       end</a>
+<a name="4734"><span class="lineNum">    4734 </span><span class="lineNoCov">          0 :       if (updateValids_1 &amp; _GEN_70 &amp; (&amp;(io_update_bits_pc[7:1]))) begin</span></a>
+<a name="4735"><span class="lineNum">    4735 </span><span class="lineNoCov">          0 :         if (_newCtr_T_9)</span></a>
+<a name="4736"><span class="lineNum">    4736 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_127 &lt;= 4'hF;</span></a>
+<a name="4737"><span class="lineNum">    4737 </span><span class="lineNoCov">          0 :         else if (_newCtr_T_11)</span></a>
+<a name="4738"><span class="lineNum">    4738 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_127 &lt;= 4'h0;</span></a>
+<a name="4739"><span class="lineNum">    4739 </span><span class="lineNoCov">          0 :         else if (updateAltCorrect_1)</span></a>
+<a name="4740"><span class="lineNum">    4740 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_127 &lt;= _newCtr_T_12;</span></a>
+<a name="4741"><span class="lineNum">    4741 </span>            :         else</a>
+<a name="4742"><span class="lineNum">    4742 </span><span class="lineNoCov">          0 :           useAltOnNaCtrs_1_127 &lt;= _newCtr_T_14;</span></a>
+<a name="4743"><span class="lineNum">    4743 </span>            :       end</a>
+<a name="4744"><span class="lineNum">    4744 </span><span class="lineNoCov">          0 :       if (allocLFSR_lfsr == 64'h0)</span></a>
+<a name="4745"><span class="lineNum">    4745 </span><span class="lineNoCov">          0 :         allocLFSR_lfsr &lt;= 64'h1;</span></a>
+<a name="4746"><span class="lineNum">    4746 </span>            :       else</a>
+<a name="4747"><span class="lineNum">    4747 </span><span class="lineCov">      63729 :         allocLFSR_lfsr &lt;=</span></a>
+<a name="4748"><span class="lineNum">    4748 </span><span class="lineCov">      63729 :           {allocLFSR_lfsr[0] ^ allocLFSR_lfsr[1] ^ allocLFSR_lfsr[3] ^ allocLFSR_lfsr[4],</span></a>
+<a name="4749"><span class="lineNum">    4749 </span><span class="lineCov">      63729 :            allocLFSR_lfsr[63:1]};</span></a>
+<a name="4750"><span class="lineNum">    4750 </span><span class="lineNoCov">          0 :       if (allocLFSR_lfsr_1 == 64'h0)</span></a>
+<a name="4751"><span class="lineNum">    4751 </span><span class="lineNoCov">          0 :         allocLFSR_lfsr_1 &lt;= 64'h1;</span></a>
+<a name="4752"><span class="lineNum">    4752 </span>            :       else</a>
+<a name="4753"><span class="lineNum">    4753 </span><span class="lineCov">      63729 :         allocLFSR_lfsr_1 &lt;=</span></a>
+<a name="4754"><span class="lineNum">    4754 </span><span class="lineCov">      63729 :           {allocLFSR_lfsr_1[0] ^ allocLFSR_lfsr_1[1] ^ allocLFSR_lfsr_1[3]</span></a>
+<a name="4755"><span class="lineNum">    4755 </span><span class="lineCov">      63729 :              ^ allocLFSR_lfsr_1[4],</span></a>
+<a name="4756"><span class="lineNum">    4756 </span><span class="lineCov">      63729 :            allocLFSR_lfsr_1[63:1]};</span></a>
+<a name="4757"><span class="lineNum">    4757 </span><span class="lineNoCov">          0 :       if (_GEN_1 &amp; io_update_bits_meta[48] != io_update_bits_meta[52]</span></a>
+<a name="4758"><span class="lineNum">    4758 </span>            :           &amp; _sumAbs_T_4 &gt;= {2'h0, 8'(scThresholds_0_thres - 8'h4)}</a>
+<a name="4759"><span class="lineNum">    4759 </span><span class="lineNoCov">          0 :           &amp; _sumAbs_T_4 &lt;= {2'h0, 8'(scThresholds_0_thres - 8'h2)}) begin</span></a>
+<a name="4760"><span class="lineNum">    4760 </span><span class="lineNoCov">          0 :         if ((&amp;newThres_newCtr) | _newThres_res_ctr_T_4)</span></a>
+<a name="4761"><span class="lineNum">    4761 </span><span class="lineNoCov">          0 :           scThresholds_0_ctr &lt;= 5'h10;</span></a>
+<a name="4762"><span class="lineNum">    4762 </span><span class="lineNoCov">          0 :         else if (_newThres_newCtr_T)</span></a>
+<a name="4763"><span class="lineNum">    4763 </span><span class="lineNoCov">          0 :           scThresholds_0_ctr &lt;= 5'h1F;</span></a>
+<a name="4764"><span class="lineNum">    4764 </span><span class="lineNoCov">          0 :         else if (_newThres_newCtr_T_2)</span></a>
+<a name="4765"><span class="lineNum">    4765 </span><span class="lineNoCov">          0 :           scThresholds_0_ctr &lt;= 5'h0;</span></a>
+<a name="4766"><span class="lineNum">    4766 </span><span class="lineNoCov">          0 :         else if (_GEN_67)</span></a>
+<a name="4767"><span class="lineNum">    4767 </span><span class="lineNoCov">          0 :           scThresholds_0_ctr &lt;= _newThres_newCtr_T_5;</span></a>
+<a name="4768"><span class="lineNum">    4768 </span>            :         else</a>
+<a name="4769"><span class="lineNum">    4769 </span><span class="lineNoCov">          0 :           scThresholds_0_ctr &lt;= _newThres_newCtr_T_3;</span></a>
+<a name="4770"><span class="lineNum">    4770 </span><span class="lineNoCov">          0 :         if ((&amp;newThres_newCtr) &amp; scThresholds_0_thres &lt; 8'h20)</span></a>
+<a name="4771"><span class="lineNum">    4771 </span><span class="lineNoCov">          0 :           scThresholds_0_thres &lt;= 8'(scThresholds_0_thres + 8'h2);</span></a>
+<a name="4772"><span class="lineNum">    4772 </span><span class="lineNoCov">          0 :         else if (_newThres_res_ctr_T_4 &amp; scThresholds_0_thres &gt; 8'h5)</span></a>
+<a name="4773"><span class="lineNum">    4773 </span><span class="lineNoCov">          0 :           scThresholds_0_thres &lt;= 8'(scThresholds_0_thres - 8'h2);</span></a>
+<a name="4774"><span class="lineNum">    4774 </span>            :       end</a>
+<a name="4775"><span class="lineNum">    4775 </span><span class="lineNoCov">          0 :       if (_GEN_2 &amp; io_update_bits_meta[49] != io_update_bits_meta[53]</span></a>
+<a name="4776"><span class="lineNum">    4776 </span>            :           &amp; _sumAbs_T_9 &gt;= {2'h0, 8'(scThresholds_1_thres - 8'h4)}</a>
+<a name="4777"><span class="lineNum">    4777 </span><span class="lineNoCov">          0 :           &amp; _sumAbs_T_9 &lt;= {2'h0, 8'(scThresholds_1_thres - 8'h2)}) begin</span></a>
+<a name="4778"><span class="lineNum">    4778 </span><span class="lineNoCov">          0 :         if ((&amp;newThres_newCtr_1) | _newThres_res_ctr_T_11)</span></a>
+<a name="4779"><span class="lineNum">    4779 </span><span class="lineNoCov">          0 :           scThresholds_1_ctr &lt;= 5'h10;</span></a>
+<a name="4780"><span class="lineNum">    4780 </span><span class="lineNoCov">          0 :         else if (_newThres_newCtr_T_9)</span></a>
+<a name="4781"><span class="lineNum">    4781 </span><span class="lineNoCov">          0 :           scThresholds_1_ctr &lt;= 5'h1F;</span></a>
+<a name="4782"><span class="lineNum">    4782 </span><span class="lineNoCov">          0 :         else if (_newThres_newCtr_T_11)</span></a>
+<a name="4783"><span class="lineNum">    4783 </span><span class="lineNoCov">          0 :           scThresholds_1_ctr &lt;= 5'h0;</span></a>
+<a name="4784"><span class="lineNum">    4784 </span><span class="lineNoCov">          0 :         else if (_GEN_68)</span></a>
+<a name="4785"><span class="lineNum">    4785 </span><span class="lineNoCov">          0 :           scThresholds_1_ctr &lt;= _newThres_newCtr_T_14;</span></a>
+<a name="4786"><span class="lineNum">    4786 </span>            :         else</a>
+<a name="4787"><span class="lineNum">    4787 </span><span class="lineNoCov">          0 :           scThresholds_1_ctr &lt;= _newThres_newCtr_T_12;</span></a>
+<a name="4788"><span class="lineNum">    4788 </span><span class="lineNoCov">          0 :         if ((&amp;newThres_newCtr_1) &amp; scThresholds_1_thres &lt; 8'h20)</span></a>
+<a name="4789"><span class="lineNum">    4789 </span><span class="lineNoCov">          0 :           scThresholds_1_thres &lt;= 8'(scThresholds_1_thres + 8'h2);</span></a>
+<a name="4790"><span class="lineNum">    4790 </span><span class="lineNoCov">          0 :         else if (_newThres_res_ctr_T_11 &amp; scThresholds_1_thres &gt; 8'h5)</span></a>
+<a name="4791"><span class="lineNum">    4791 </span><span class="lineNoCov">          0 :           scThresholds_1_thres &lt;= 8'(scThresholds_1_thres - 8'h2);</span></a>
+<a name="4792"><span class="lineNum">    4792 </span>            :       end</a>
+<a name="4793"><span class="lineNum">    4793 </span>            :     end</a>
+<a name="4794"><span class="lineNum">    4794 </span>            :   end // always @(posedge, posedge)</a>
+<a name="4795"><span class="lineNum">    4795 </span>            :   `ifdef ENABLE_INITIAL_REG_</a>
+<a name="4796"><span class="lineNum">    4796 </span>            :     `ifdef FIRRTL_BEFORE_INITIAL</a>
+<a name="4797"><span class="lineNum">    4797 </span>            :       `FIRRTL_BEFORE_INITIAL</a>
+<a name="4798"><span class="lineNum">    4798 </span>            :     `endif // FIRRTL_BEFORE_INITIAL</a>
+<a name="4799"><span class="lineNum">    4799 </span>            :     logic [31:0] _RANDOM[0:233];</a>
+<a name="4800"><span class="lineNum">    4800 </span><span class="lineCov">         58 :     initial begin</span></a>
+<a name="4801"><span class="lineNum">    4801 </span>            :       `ifdef INIT_RANDOM_PROLOG_</a>
+<a name="4802"><span class="lineNum">    4802 </span>            :         `INIT_RANDOM_PROLOG_</a>
+<a name="4803"><span class="lineNum">    4803 </span>            :       `endif // INIT_RANDOM_PROLOG_</a>
+<a name="4804"><span class="lineNum">    4804 </span>            :       `ifdef RANDOMIZE_REG_INIT</a>
+<a name="4805"><span class="lineNum">    4805 </span>            :         for (logic [7:0] i = 8'h0; i &lt; 8'hEA; i += 8'h1) begin</a>
+<a name="4806"><span class="lineNum">    4806 </span>            :           _RANDOM[i] = `RANDOM;</a>
+<a name="4807"><span class="lineNum">    4807 </span>            :         end</a>
+<a name="4808"><span class="lineNum">    4808 </span>            :         s1_pc_dup_0 = {_RANDOM[8'h0], _RANDOM[8'h1][8:0]};</a>
+<a name="4809"><span class="lineNum">    4809 </span>            :         REG = _RANDOM[8'hF][12];</a>
+<a name="4810"><span class="lineNum">    4810 </span>            :         REG_1 = _RANDOM[8'hF][13];</a>
+<a name="4811"><span class="lineNum">    4811 </span>            :         bankTickCtrDistanceToTops_0 = _RANDOM[8'hF][20:14];</a>
+<a name="4812"><span class="lineNum">    4812 </span>            :         bankTickCtrDistanceToTops_1 = _RANDOM[8'hF][27:21];</a>
+<a name="4813"><span class="lineNum">    4813 </span>            :         bankTickCtrs_0 = {_RANDOM[8'hF][31:28], _RANDOM[8'h10][2:0]};</a>
+<a name="4814"><span class="lineNum">    4814 </span>            :         bankTickCtrs_1 = _RANDOM[8'h10][9:3];</a>
+<a name="4815"><span class="lineNum">    4815 </span>            :         useAltOnNaCtrs_0_0 = _RANDOM[8'h10][13:10];</a>
+<a name="4816"><span class="lineNum">    4816 </span>            :         useAltOnNaCtrs_0_1 = _RANDOM[8'h10][17:14];</a>
+<a name="4817"><span class="lineNum">    4817 </span>            :         useAltOnNaCtrs_0_2 = _RANDOM[8'h10][21:18];</a>
+<a name="4818"><span class="lineNum">    4818 </span>            :         useAltOnNaCtrs_0_3 = _RANDOM[8'h10][25:22];</a>
+<a name="4819"><span class="lineNum">    4819 </span>            :         useAltOnNaCtrs_0_4 = _RANDOM[8'h10][29:26];</a>
+<a name="4820"><span class="lineNum">    4820 </span>            :         useAltOnNaCtrs_0_5 = {_RANDOM[8'h10][31:30], _RANDOM[8'h11][1:0]};</a>
+<a name="4821"><span class="lineNum">    4821 </span>            :         useAltOnNaCtrs_0_6 = _RANDOM[8'h11][5:2];</a>
+<a name="4822"><span class="lineNum">    4822 </span>            :         useAltOnNaCtrs_0_7 = _RANDOM[8'h11][9:6];</a>
+<a name="4823"><span class="lineNum">    4823 </span>            :         useAltOnNaCtrs_0_8 = _RANDOM[8'h11][13:10];</a>
+<a name="4824"><span class="lineNum">    4824 </span>            :         useAltOnNaCtrs_0_9 = _RANDOM[8'h11][17:14];</a>
+<a name="4825"><span class="lineNum">    4825 </span>            :         useAltOnNaCtrs_0_10 = _RANDOM[8'h11][21:18];</a>
+<a name="4826"><span class="lineNum">    4826 </span>            :         useAltOnNaCtrs_0_11 = _RANDOM[8'h11][25:22];</a>
+<a name="4827"><span class="lineNum">    4827 </span>            :         useAltOnNaCtrs_0_12 = _RANDOM[8'h11][29:26];</a>
+<a name="4828"><span class="lineNum">    4828 </span>            :         useAltOnNaCtrs_0_13 = {_RANDOM[8'h11][31:30], _RANDOM[8'h12][1:0]};</a>
+<a name="4829"><span class="lineNum">    4829 </span>            :         useAltOnNaCtrs_0_14 = _RANDOM[8'h12][5:2];</a>
+<a name="4830"><span class="lineNum">    4830 </span>            :         useAltOnNaCtrs_0_15 = _RANDOM[8'h12][9:6];</a>
+<a name="4831"><span class="lineNum">    4831 </span>            :         useAltOnNaCtrs_0_16 = _RANDOM[8'h12][13:10];</a>
+<a name="4832"><span class="lineNum">    4832 </span>            :         useAltOnNaCtrs_0_17 = _RANDOM[8'h12][17:14];</a>
+<a name="4833"><span class="lineNum">    4833 </span>            :         useAltOnNaCtrs_0_18 = _RANDOM[8'h12][21:18];</a>
+<a name="4834"><span class="lineNum">    4834 </span>            :         useAltOnNaCtrs_0_19 = _RANDOM[8'h12][25:22];</a>
+<a name="4835"><span class="lineNum">    4835 </span>            :         useAltOnNaCtrs_0_20 = _RANDOM[8'h12][29:26];</a>
+<a name="4836"><span class="lineNum">    4836 </span>            :         useAltOnNaCtrs_0_21 = {_RANDOM[8'h12][31:30], _RANDOM[8'h13][1:0]};</a>
+<a name="4837"><span class="lineNum">    4837 </span>            :         useAltOnNaCtrs_0_22 = _RANDOM[8'h13][5:2];</a>
+<a name="4838"><span class="lineNum">    4838 </span>            :         useAltOnNaCtrs_0_23 = _RANDOM[8'h13][9:6];</a>
+<a name="4839"><span class="lineNum">    4839 </span>            :         useAltOnNaCtrs_0_24 = _RANDOM[8'h13][13:10];</a>
+<a name="4840"><span class="lineNum">    4840 </span>            :         useAltOnNaCtrs_0_25 = _RANDOM[8'h13][17:14];</a>
+<a name="4841"><span class="lineNum">    4841 </span>            :         useAltOnNaCtrs_0_26 = _RANDOM[8'h13][21:18];</a>
+<a name="4842"><span class="lineNum">    4842 </span>            :         useAltOnNaCtrs_0_27 = _RANDOM[8'h13][25:22];</a>
+<a name="4843"><span class="lineNum">    4843 </span>            :         useAltOnNaCtrs_0_28 = _RANDOM[8'h13][29:26];</a>
+<a name="4844"><span class="lineNum">    4844 </span>            :         useAltOnNaCtrs_0_29 = {_RANDOM[8'h13][31:30], _RANDOM[8'h14][1:0]};</a>
+<a name="4845"><span class="lineNum">    4845 </span>            :         useAltOnNaCtrs_0_30 = _RANDOM[8'h14][5:2];</a>
+<a name="4846"><span class="lineNum">    4846 </span>            :         useAltOnNaCtrs_0_31 = _RANDOM[8'h14][9:6];</a>
+<a name="4847"><span class="lineNum">    4847 </span>            :         useAltOnNaCtrs_0_32 = _RANDOM[8'h14][13:10];</a>
+<a name="4848"><span class="lineNum">    4848 </span>            :         useAltOnNaCtrs_0_33 = _RANDOM[8'h14][17:14];</a>
+<a name="4849"><span class="lineNum">    4849 </span>            :         useAltOnNaCtrs_0_34 = _RANDOM[8'h14][21:18];</a>
+<a name="4850"><span class="lineNum">    4850 </span>            :         useAltOnNaCtrs_0_35 = _RANDOM[8'h14][25:22];</a>
+<a name="4851"><span class="lineNum">    4851 </span>            :         useAltOnNaCtrs_0_36 = _RANDOM[8'h14][29:26];</a>
+<a name="4852"><span class="lineNum">    4852 </span>            :         useAltOnNaCtrs_0_37 = {_RANDOM[8'h14][31:30], _RANDOM[8'h15][1:0]};</a>
+<a name="4853"><span class="lineNum">    4853 </span>            :         useAltOnNaCtrs_0_38 = _RANDOM[8'h15][5:2];</a>
+<a name="4854"><span class="lineNum">    4854 </span>            :         useAltOnNaCtrs_0_39 = _RANDOM[8'h15][9:6];</a>
+<a name="4855"><span class="lineNum">    4855 </span>            :         useAltOnNaCtrs_0_40 = _RANDOM[8'h15][13:10];</a>
+<a name="4856"><span class="lineNum">    4856 </span>            :         useAltOnNaCtrs_0_41 = _RANDOM[8'h15][17:14];</a>
+<a name="4857"><span class="lineNum">    4857 </span>            :         useAltOnNaCtrs_0_42 = _RANDOM[8'h15][21:18];</a>
+<a name="4858"><span class="lineNum">    4858 </span>            :         useAltOnNaCtrs_0_43 = _RANDOM[8'h15][25:22];</a>
+<a name="4859"><span class="lineNum">    4859 </span>            :         useAltOnNaCtrs_0_44 = _RANDOM[8'h15][29:26];</a>
+<a name="4860"><span class="lineNum">    4860 </span>            :         useAltOnNaCtrs_0_45 = {_RANDOM[8'h15][31:30], _RANDOM[8'h16][1:0]};</a>
+<a name="4861"><span class="lineNum">    4861 </span>            :         useAltOnNaCtrs_0_46 = _RANDOM[8'h16][5:2];</a>
+<a name="4862"><span class="lineNum">    4862 </span>            :         useAltOnNaCtrs_0_47 = _RANDOM[8'h16][9:6];</a>
+<a name="4863"><span class="lineNum">    4863 </span>            :         useAltOnNaCtrs_0_48 = _RANDOM[8'h16][13:10];</a>
+<a name="4864"><span class="lineNum">    4864 </span>            :         useAltOnNaCtrs_0_49 = _RANDOM[8'h16][17:14];</a>
+<a name="4865"><span class="lineNum">    4865 </span>            :         useAltOnNaCtrs_0_50 = _RANDOM[8'h16][21:18];</a>
+<a name="4866"><span class="lineNum">    4866 </span>            :         useAltOnNaCtrs_0_51 = _RANDOM[8'h16][25:22];</a>
+<a name="4867"><span class="lineNum">    4867 </span>            :         useAltOnNaCtrs_0_52 = _RANDOM[8'h16][29:26];</a>
+<a name="4868"><span class="lineNum">    4868 </span>            :         useAltOnNaCtrs_0_53 = {_RANDOM[8'h16][31:30], _RANDOM[8'h17][1:0]};</a>
+<a name="4869"><span class="lineNum">    4869 </span>            :         useAltOnNaCtrs_0_54 = _RANDOM[8'h17][5:2];</a>
+<a name="4870"><span class="lineNum">    4870 </span>            :         useAltOnNaCtrs_0_55 = _RANDOM[8'h17][9:6];</a>
+<a name="4871"><span class="lineNum">    4871 </span>            :         useAltOnNaCtrs_0_56 = _RANDOM[8'h17][13:10];</a>
+<a name="4872"><span class="lineNum">    4872 </span>            :         useAltOnNaCtrs_0_57 = _RANDOM[8'h17][17:14];</a>
+<a name="4873"><span class="lineNum">    4873 </span>            :         useAltOnNaCtrs_0_58 = _RANDOM[8'h17][21:18];</a>
+<a name="4874"><span class="lineNum">    4874 </span>            :         useAltOnNaCtrs_0_59 = _RANDOM[8'h17][25:22];</a>
+<a name="4875"><span class="lineNum">    4875 </span>            :         useAltOnNaCtrs_0_60 = _RANDOM[8'h17][29:26];</a>
+<a name="4876"><span class="lineNum">    4876 </span>            :         useAltOnNaCtrs_0_61 = {_RANDOM[8'h17][31:30], _RANDOM[8'h18][1:0]};</a>
+<a name="4877"><span class="lineNum">    4877 </span>            :         useAltOnNaCtrs_0_62 = _RANDOM[8'h18][5:2];</a>
+<a name="4878"><span class="lineNum">    4878 </span>            :         useAltOnNaCtrs_0_63 = _RANDOM[8'h18][9:6];</a>
+<a name="4879"><span class="lineNum">    4879 </span>            :         useAltOnNaCtrs_0_64 = _RANDOM[8'h18][13:10];</a>
+<a name="4880"><span class="lineNum">    4880 </span>            :         useAltOnNaCtrs_0_65 = _RANDOM[8'h18][17:14];</a>
+<a name="4881"><span class="lineNum">    4881 </span>            :         useAltOnNaCtrs_0_66 = _RANDOM[8'h18][21:18];</a>
+<a name="4882"><span class="lineNum">    4882 </span>            :         useAltOnNaCtrs_0_67 = _RANDOM[8'h18][25:22];</a>
+<a name="4883"><span class="lineNum">    4883 </span>            :         useAltOnNaCtrs_0_68 = _RANDOM[8'h18][29:26];</a>
+<a name="4884"><span class="lineNum">    4884 </span>            :         useAltOnNaCtrs_0_69 = {_RANDOM[8'h18][31:30], _RANDOM[8'h19][1:0]};</a>
+<a name="4885"><span class="lineNum">    4885 </span>            :         useAltOnNaCtrs_0_70 = _RANDOM[8'h19][5:2];</a>
+<a name="4886"><span class="lineNum">    4886 </span>            :         useAltOnNaCtrs_0_71 = _RANDOM[8'h19][9:6];</a>
+<a name="4887"><span class="lineNum">    4887 </span>            :         useAltOnNaCtrs_0_72 = _RANDOM[8'h19][13:10];</a>
+<a name="4888"><span class="lineNum">    4888 </span>            :         useAltOnNaCtrs_0_73 = _RANDOM[8'h19][17:14];</a>
+<a name="4889"><span class="lineNum">    4889 </span>            :         useAltOnNaCtrs_0_74 = _RANDOM[8'h19][21:18];</a>
+<a name="4890"><span class="lineNum">    4890 </span>            :         useAltOnNaCtrs_0_75 = _RANDOM[8'h19][25:22];</a>
+<a name="4891"><span class="lineNum">    4891 </span>            :         useAltOnNaCtrs_0_76 = _RANDOM[8'h19][29:26];</a>
+<a name="4892"><span class="lineNum">    4892 </span>            :         useAltOnNaCtrs_0_77 = {_RANDOM[8'h19][31:30], _RANDOM[8'h1A][1:0]};</a>
+<a name="4893"><span class="lineNum">    4893 </span>            :         useAltOnNaCtrs_0_78 = _RANDOM[8'h1A][5:2];</a>
+<a name="4894"><span class="lineNum">    4894 </span>            :         useAltOnNaCtrs_0_79 = _RANDOM[8'h1A][9:6];</a>
+<a name="4895"><span class="lineNum">    4895 </span>            :         useAltOnNaCtrs_0_80 = _RANDOM[8'h1A][13:10];</a>
+<a name="4896"><span class="lineNum">    4896 </span>            :         useAltOnNaCtrs_0_81 = _RANDOM[8'h1A][17:14];</a>
+<a name="4897"><span class="lineNum">    4897 </span>            :         useAltOnNaCtrs_0_82 = _RANDOM[8'h1A][21:18];</a>
+<a name="4898"><span class="lineNum">    4898 </span>            :         useAltOnNaCtrs_0_83 = _RANDOM[8'h1A][25:22];</a>
+<a name="4899"><span class="lineNum">    4899 </span>            :         useAltOnNaCtrs_0_84 = _RANDOM[8'h1A][29:26];</a>
+<a name="4900"><span class="lineNum">    4900 </span>            :         useAltOnNaCtrs_0_85 = {_RANDOM[8'h1A][31:30], _RANDOM[8'h1B][1:0]};</a>
+<a name="4901"><span class="lineNum">    4901 </span>            :         useAltOnNaCtrs_0_86 = _RANDOM[8'h1B][5:2];</a>
+<a name="4902"><span class="lineNum">    4902 </span>            :         useAltOnNaCtrs_0_87 = _RANDOM[8'h1B][9:6];</a>
+<a name="4903"><span class="lineNum">    4903 </span>            :         useAltOnNaCtrs_0_88 = _RANDOM[8'h1B][13:10];</a>
+<a name="4904"><span class="lineNum">    4904 </span>            :         useAltOnNaCtrs_0_89 = _RANDOM[8'h1B][17:14];</a>
+<a name="4905"><span class="lineNum">    4905 </span>            :         useAltOnNaCtrs_0_90 = _RANDOM[8'h1B][21:18];</a>
+<a name="4906"><span class="lineNum">    4906 </span>            :         useAltOnNaCtrs_0_91 = _RANDOM[8'h1B][25:22];</a>
+<a name="4907"><span class="lineNum">    4907 </span>            :         useAltOnNaCtrs_0_92 = _RANDOM[8'h1B][29:26];</a>
+<a name="4908"><span class="lineNum">    4908 </span>            :         useAltOnNaCtrs_0_93 = {_RANDOM[8'h1B][31:30], _RANDOM[8'h1C][1:0]};</a>
+<a name="4909"><span class="lineNum">    4909 </span>            :         useAltOnNaCtrs_0_94 = _RANDOM[8'h1C][5:2];</a>
+<a name="4910"><span class="lineNum">    4910 </span>            :         useAltOnNaCtrs_0_95 = _RANDOM[8'h1C][9:6];</a>
+<a name="4911"><span class="lineNum">    4911 </span>            :         useAltOnNaCtrs_0_96 = _RANDOM[8'h1C][13:10];</a>
+<a name="4912"><span class="lineNum">    4912 </span>            :         useAltOnNaCtrs_0_97 = _RANDOM[8'h1C][17:14];</a>
+<a name="4913"><span class="lineNum">    4913 </span>            :         useAltOnNaCtrs_0_98 = _RANDOM[8'h1C][21:18];</a>
+<a name="4914"><span class="lineNum">    4914 </span>            :         useAltOnNaCtrs_0_99 = _RANDOM[8'h1C][25:22];</a>
+<a name="4915"><span class="lineNum">    4915 </span>            :         useAltOnNaCtrs_0_100 = _RANDOM[8'h1C][29:26];</a>
+<a name="4916"><span class="lineNum">    4916 </span>            :         useAltOnNaCtrs_0_101 = {_RANDOM[8'h1C][31:30], _RANDOM[8'h1D][1:0]};</a>
+<a name="4917"><span class="lineNum">    4917 </span>            :         useAltOnNaCtrs_0_102 = _RANDOM[8'h1D][5:2];</a>
+<a name="4918"><span class="lineNum">    4918 </span>            :         useAltOnNaCtrs_0_103 = _RANDOM[8'h1D][9:6];</a>
+<a name="4919"><span class="lineNum">    4919 </span>            :         useAltOnNaCtrs_0_104 = _RANDOM[8'h1D][13:10];</a>
+<a name="4920"><span class="lineNum">    4920 </span>            :         useAltOnNaCtrs_0_105 = _RANDOM[8'h1D][17:14];</a>
+<a name="4921"><span class="lineNum">    4921 </span>            :         useAltOnNaCtrs_0_106 = _RANDOM[8'h1D][21:18];</a>
+<a name="4922"><span class="lineNum">    4922 </span>            :         useAltOnNaCtrs_0_107 = _RANDOM[8'h1D][25:22];</a>
+<a name="4923"><span class="lineNum">    4923 </span>            :         useAltOnNaCtrs_0_108 = _RANDOM[8'h1D][29:26];</a>
+<a name="4924"><span class="lineNum">    4924 </span>            :         useAltOnNaCtrs_0_109 = {_RANDOM[8'h1D][31:30], _RANDOM[8'h1E][1:0]};</a>
+<a name="4925"><span class="lineNum">    4925 </span>            :         useAltOnNaCtrs_0_110 = _RANDOM[8'h1E][5:2];</a>
+<a name="4926"><span class="lineNum">    4926 </span>            :         useAltOnNaCtrs_0_111 = _RANDOM[8'h1E][9:6];</a>
+<a name="4927"><span class="lineNum">    4927 </span>            :         useAltOnNaCtrs_0_112 = _RANDOM[8'h1E][13:10];</a>
+<a name="4928"><span class="lineNum">    4928 </span>            :         useAltOnNaCtrs_0_113 = _RANDOM[8'h1E][17:14];</a>
+<a name="4929"><span class="lineNum">    4929 </span>            :         useAltOnNaCtrs_0_114 = _RANDOM[8'h1E][21:18];</a>
+<a name="4930"><span class="lineNum">    4930 </span>            :         useAltOnNaCtrs_0_115 = _RANDOM[8'h1E][25:22];</a>
+<a name="4931"><span class="lineNum">    4931 </span>            :         useAltOnNaCtrs_0_116 = _RANDOM[8'h1E][29:26];</a>
+<a name="4932"><span class="lineNum">    4932 </span>            :         useAltOnNaCtrs_0_117 = {_RANDOM[8'h1E][31:30], _RANDOM[8'h1F][1:0]};</a>
+<a name="4933"><span class="lineNum">    4933 </span>            :         useAltOnNaCtrs_0_118 = _RANDOM[8'h1F][5:2];</a>
+<a name="4934"><span class="lineNum">    4934 </span>            :         useAltOnNaCtrs_0_119 = _RANDOM[8'h1F][9:6];</a>
+<a name="4935"><span class="lineNum">    4935 </span>            :         useAltOnNaCtrs_0_120 = _RANDOM[8'h1F][13:10];</a>
+<a name="4936"><span class="lineNum">    4936 </span>            :         useAltOnNaCtrs_0_121 = _RANDOM[8'h1F][17:14];</a>
+<a name="4937"><span class="lineNum">    4937 </span>            :         useAltOnNaCtrs_0_122 = _RANDOM[8'h1F][21:18];</a>
+<a name="4938"><span class="lineNum">    4938 </span>            :         useAltOnNaCtrs_0_123 = _RANDOM[8'h1F][25:22];</a>
+<a name="4939"><span class="lineNum">    4939 </span>            :         useAltOnNaCtrs_0_124 = _RANDOM[8'h1F][29:26];</a>
+<a name="4940"><span class="lineNum">    4940 </span>            :         useAltOnNaCtrs_0_125 = {_RANDOM[8'h1F][31:30], _RANDOM[8'h20][1:0]};</a>
+<a name="4941"><span class="lineNum">    4941 </span>            :         useAltOnNaCtrs_0_126 = _RANDOM[8'h20][5:2];</a>
+<a name="4942"><span class="lineNum">    4942 </span>            :         useAltOnNaCtrs_0_127 = _RANDOM[8'h20][9:6];</a>
+<a name="4943"><span class="lineNum">    4943 </span>            :         useAltOnNaCtrs_1_0 = _RANDOM[8'h20][13:10];</a>
+<a name="4944"><span class="lineNum">    4944 </span>            :         useAltOnNaCtrs_1_1 = _RANDOM[8'h20][17:14];</a>
+<a name="4945"><span class="lineNum">    4945 </span>            :         useAltOnNaCtrs_1_2 = _RANDOM[8'h20][21:18];</a>
+<a name="4946"><span class="lineNum">    4946 </span>            :         useAltOnNaCtrs_1_3 = _RANDOM[8'h20][25:22];</a>
+<a name="4947"><span class="lineNum">    4947 </span>            :         useAltOnNaCtrs_1_4 = _RANDOM[8'h20][29:26];</a>
+<a name="4948"><span class="lineNum">    4948 </span>            :         useAltOnNaCtrs_1_5 = {_RANDOM[8'h20][31:30], _RANDOM[8'h21][1:0]};</a>
+<a name="4949"><span class="lineNum">    4949 </span>            :         useAltOnNaCtrs_1_6 = _RANDOM[8'h21][5:2];</a>
+<a name="4950"><span class="lineNum">    4950 </span>            :         useAltOnNaCtrs_1_7 = _RANDOM[8'h21][9:6];</a>
+<a name="4951"><span class="lineNum">    4951 </span>            :         useAltOnNaCtrs_1_8 = _RANDOM[8'h21][13:10];</a>
+<a name="4952"><span class="lineNum">    4952 </span>            :         useAltOnNaCtrs_1_9 = _RANDOM[8'h21][17:14];</a>
+<a name="4953"><span class="lineNum">    4953 </span>            :         useAltOnNaCtrs_1_10 = _RANDOM[8'h21][21:18];</a>
+<a name="4954"><span class="lineNum">    4954 </span>            :         useAltOnNaCtrs_1_11 = _RANDOM[8'h21][25:22];</a>
+<a name="4955"><span class="lineNum">    4955 </span>            :         useAltOnNaCtrs_1_12 = _RANDOM[8'h21][29:26];</a>
+<a name="4956"><span class="lineNum">    4956 </span>            :         useAltOnNaCtrs_1_13 = {_RANDOM[8'h21][31:30], _RANDOM[8'h22][1:0]};</a>
+<a name="4957"><span class="lineNum">    4957 </span>            :         useAltOnNaCtrs_1_14 = _RANDOM[8'h22][5:2];</a>
+<a name="4958"><span class="lineNum">    4958 </span>            :         useAltOnNaCtrs_1_15 = _RANDOM[8'h22][9:6];</a>
+<a name="4959"><span class="lineNum">    4959 </span>            :         useAltOnNaCtrs_1_16 = _RANDOM[8'h22][13:10];</a>
+<a name="4960"><span class="lineNum">    4960 </span>            :         useAltOnNaCtrs_1_17 = _RANDOM[8'h22][17:14];</a>
+<a name="4961"><span class="lineNum">    4961 </span>            :         useAltOnNaCtrs_1_18 = _RANDOM[8'h22][21:18];</a>
+<a name="4962"><span class="lineNum">    4962 </span>            :         useAltOnNaCtrs_1_19 = _RANDOM[8'h22][25:22];</a>
+<a name="4963"><span class="lineNum">    4963 </span>            :         useAltOnNaCtrs_1_20 = _RANDOM[8'h22][29:26];</a>
+<a name="4964"><span class="lineNum">    4964 </span>            :         useAltOnNaCtrs_1_21 = {_RANDOM[8'h22][31:30], _RANDOM[8'h23][1:0]};</a>
+<a name="4965"><span class="lineNum">    4965 </span>            :         useAltOnNaCtrs_1_22 = _RANDOM[8'h23][5:2];</a>
+<a name="4966"><span class="lineNum">    4966 </span>            :         useAltOnNaCtrs_1_23 = _RANDOM[8'h23][9:6];</a>
+<a name="4967"><span class="lineNum">    4967 </span>            :         useAltOnNaCtrs_1_24 = _RANDOM[8'h23][13:10];</a>
+<a name="4968"><span class="lineNum">    4968 </span>            :         useAltOnNaCtrs_1_25 = _RANDOM[8'h23][17:14];</a>
+<a name="4969"><span class="lineNum">    4969 </span>            :         useAltOnNaCtrs_1_26 = _RANDOM[8'h23][21:18];</a>
+<a name="4970"><span class="lineNum">    4970 </span>            :         useAltOnNaCtrs_1_27 = _RANDOM[8'h23][25:22];</a>
+<a name="4971"><span class="lineNum">    4971 </span>            :         useAltOnNaCtrs_1_28 = _RANDOM[8'h23][29:26];</a>
+<a name="4972"><span class="lineNum">    4972 </span>            :         useAltOnNaCtrs_1_29 = {_RANDOM[8'h23][31:30], _RANDOM[8'h24][1:0]};</a>
+<a name="4973"><span class="lineNum">    4973 </span>            :         useAltOnNaCtrs_1_30 = _RANDOM[8'h24][5:2];</a>
+<a name="4974"><span class="lineNum">    4974 </span>            :         useAltOnNaCtrs_1_31 = _RANDOM[8'h24][9:6];</a>
+<a name="4975"><span class="lineNum">    4975 </span>            :         useAltOnNaCtrs_1_32 = _RANDOM[8'h24][13:10];</a>
+<a name="4976"><span class="lineNum">    4976 </span>            :         useAltOnNaCtrs_1_33 = _RANDOM[8'h24][17:14];</a>
+<a name="4977"><span class="lineNum">    4977 </span>            :         useAltOnNaCtrs_1_34 = _RANDOM[8'h24][21:18];</a>
+<a name="4978"><span class="lineNum">    4978 </span>            :         useAltOnNaCtrs_1_35 = _RANDOM[8'h24][25:22];</a>
+<a name="4979"><span class="lineNum">    4979 </span>            :         useAltOnNaCtrs_1_36 = _RANDOM[8'h24][29:26];</a>
+<a name="4980"><span class="lineNum">    4980 </span>            :         useAltOnNaCtrs_1_37 = {_RANDOM[8'h24][31:30], _RANDOM[8'h25][1:0]};</a>
+<a name="4981"><span class="lineNum">    4981 </span>            :         useAltOnNaCtrs_1_38 = _RANDOM[8'h25][5:2];</a>
+<a name="4982"><span class="lineNum">    4982 </span>            :         useAltOnNaCtrs_1_39 = _RANDOM[8'h25][9:6];</a>
+<a name="4983"><span class="lineNum">    4983 </span>            :         useAltOnNaCtrs_1_40 = _RANDOM[8'h25][13:10];</a>
+<a name="4984"><span class="lineNum">    4984 </span>            :         useAltOnNaCtrs_1_41 = _RANDOM[8'h25][17:14];</a>
+<a name="4985"><span class="lineNum">    4985 </span>            :         useAltOnNaCtrs_1_42 = _RANDOM[8'h25][21:18];</a>
+<a name="4986"><span class="lineNum">    4986 </span>            :         useAltOnNaCtrs_1_43 = _RANDOM[8'h25][25:22];</a>
+<a name="4987"><span class="lineNum">    4987 </span>            :         useAltOnNaCtrs_1_44 = _RANDOM[8'h25][29:26];</a>
+<a name="4988"><span class="lineNum">    4988 </span>            :         useAltOnNaCtrs_1_45 = {_RANDOM[8'h25][31:30], _RANDOM[8'h26][1:0]};</a>
+<a name="4989"><span class="lineNum">    4989 </span>            :         useAltOnNaCtrs_1_46 = _RANDOM[8'h26][5:2];</a>
+<a name="4990"><span class="lineNum">    4990 </span>            :         useAltOnNaCtrs_1_47 = _RANDOM[8'h26][9:6];</a>
+<a name="4991"><span class="lineNum">    4991 </span>            :         useAltOnNaCtrs_1_48 = _RANDOM[8'h26][13:10];</a>
+<a name="4992"><span class="lineNum">    4992 </span>            :         useAltOnNaCtrs_1_49 = _RANDOM[8'h26][17:14];</a>
+<a name="4993"><span class="lineNum">    4993 </span>            :         useAltOnNaCtrs_1_50 = _RANDOM[8'h26][21:18];</a>
+<a name="4994"><span class="lineNum">    4994 </span>            :         useAltOnNaCtrs_1_51 = _RANDOM[8'h26][25:22];</a>
+<a name="4995"><span class="lineNum">    4995 </span>            :         useAltOnNaCtrs_1_52 = _RANDOM[8'h26][29:26];</a>
+<a name="4996"><span class="lineNum">    4996 </span>            :         useAltOnNaCtrs_1_53 = {_RANDOM[8'h26][31:30], _RANDOM[8'h27][1:0]};</a>
+<a name="4997"><span class="lineNum">    4997 </span>            :         useAltOnNaCtrs_1_54 = _RANDOM[8'h27][5:2];</a>
+<a name="4998"><span class="lineNum">    4998 </span>            :         useAltOnNaCtrs_1_55 = _RANDOM[8'h27][9:6];</a>
+<a name="4999"><span class="lineNum">    4999 </span>            :         useAltOnNaCtrs_1_56 = _RANDOM[8'h27][13:10];</a>
+<a name="5000"><span class="lineNum">    5000 </span>            :         useAltOnNaCtrs_1_57 = _RANDOM[8'h27][17:14];</a>
+<a name="5001"><span class="lineNum">    5001 </span>            :         useAltOnNaCtrs_1_58 = _RANDOM[8'h27][21:18];</a>
+<a name="5002"><span class="lineNum">    5002 </span>            :         useAltOnNaCtrs_1_59 = _RANDOM[8'h27][25:22];</a>
+<a name="5003"><span class="lineNum">    5003 </span>            :         useAltOnNaCtrs_1_60 = _RANDOM[8'h27][29:26];</a>
+<a name="5004"><span class="lineNum">    5004 </span>            :         useAltOnNaCtrs_1_61 = {_RANDOM[8'h27][31:30], _RANDOM[8'h28][1:0]};</a>
+<a name="5005"><span class="lineNum">    5005 </span>            :         useAltOnNaCtrs_1_62 = _RANDOM[8'h28][5:2];</a>
+<a name="5006"><span class="lineNum">    5006 </span>            :         useAltOnNaCtrs_1_63 = _RANDOM[8'h28][9:6];</a>
+<a name="5007"><span class="lineNum">    5007 </span>            :         useAltOnNaCtrs_1_64 = _RANDOM[8'h28][13:10];</a>
+<a name="5008"><span class="lineNum">    5008 </span>            :         useAltOnNaCtrs_1_65 = _RANDOM[8'h28][17:14];</a>
+<a name="5009"><span class="lineNum">    5009 </span>            :         useAltOnNaCtrs_1_66 = _RANDOM[8'h28][21:18];</a>
+<a name="5010"><span class="lineNum">    5010 </span>            :         useAltOnNaCtrs_1_67 = _RANDOM[8'h28][25:22];</a>
+<a name="5011"><span class="lineNum">    5011 </span>            :         useAltOnNaCtrs_1_68 = _RANDOM[8'h28][29:26];</a>
+<a name="5012"><span class="lineNum">    5012 </span>            :         useAltOnNaCtrs_1_69 = {_RANDOM[8'h28][31:30], _RANDOM[8'h29][1:0]};</a>
+<a name="5013"><span class="lineNum">    5013 </span>            :         useAltOnNaCtrs_1_70 = _RANDOM[8'h29][5:2];</a>
+<a name="5014"><span class="lineNum">    5014 </span>            :         useAltOnNaCtrs_1_71 = _RANDOM[8'h29][9:6];</a>
+<a name="5015"><span class="lineNum">    5015 </span>            :         useAltOnNaCtrs_1_72 = _RANDOM[8'h29][13:10];</a>
+<a name="5016"><span class="lineNum">    5016 </span>            :         useAltOnNaCtrs_1_73 = _RANDOM[8'h29][17:14];</a>
+<a name="5017"><span class="lineNum">    5017 </span>            :         useAltOnNaCtrs_1_74 = _RANDOM[8'h29][21:18];</a>
+<a name="5018"><span class="lineNum">    5018 </span>            :         useAltOnNaCtrs_1_75 = _RANDOM[8'h29][25:22];</a>
+<a name="5019"><span class="lineNum">    5019 </span>            :         useAltOnNaCtrs_1_76 = _RANDOM[8'h29][29:26];</a>
+<a name="5020"><span class="lineNum">    5020 </span>            :         useAltOnNaCtrs_1_77 = {_RANDOM[8'h29][31:30], _RANDOM[8'h2A][1:0]};</a>
+<a name="5021"><span class="lineNum">    5021 </span>            :         useAltOnNaCtrs_1_78 = _RANDOM[8'h2A][5:2];</a>
+<a name="5022"><span class="lineNum">    5022 </span>            :         useAltOnNaCtrs_1_79 = _RANDOM[8'h2A][9:6];</a>
+<a name="5023"><span class="lineNum">    5023 </span>            :         useAltOnNaCtrs_1_80 = _RANDOM[8'h2A][13:10];</a>
+<a name="5024"><span class="lineNum">    5024 </span>            :         useAltOnNaCtrs_1_81 = _RANDOM[8'h2A][17:14];</a>
+<a name="5025"><span class="lineNum">    5025 </span>            :         useAltOnNaCtrs_1_82 = _RANDOM[8'h2A][21:18];</a>
+<a name="5026"><span class="lineNum">    5026 </span>            :         useAltOnNaCtrs_1_83 = _RANDOM[8'h2A][25:22];</a>
+<a name="5027"><span class="lineNum">    5027 </span>            :         useAltOnNaCtrs_1_84 = _RANDOM[8'h2A][29:26];</a>
+<a name="5028"><span class="lineNum">    5028 </span>            :         useAltOnNaCtrs_1_85 = {_RANDOM[8'h2A][31:30], _RANDOM[8'h2B][1:0]};</a>
+<a name="5029"><span class="lineNum">    5029 </span>            :         useAltOnNaCtrs_1_86 = _RANDOM[8'h2B][5:2];</a>
+<a name="5030"><span class="lineNum">    5030 </span>            :         useAltOnNaCtrs_1_87 = _RANDOM[8'h2B][9:6];</a>
+<a name="5031"><span class="lineNum">    5031 </span>            :         useAltOnNaCtrs_1_88 = _RANDOM[8'h2B][13:10];</a>
+<a name="5032"><span class="lineNum">    5032 </span>            :         useAltOnNaCtrs_1_89 = _RANDOM[8'h2B][17:14];</a>
+<a name="5033"><span class="lineNum">    5033 </span>            :         useAltOnNaCtrs_1_90 = _RANDOM[8'h2B][21:18];</a>
+<a name="5034"><span class="lineNum">    5034 </span>            :         useAltOnNaCtrs_1_91 = _RANDOM[8'h2B][25:22];</a>
+<a name="5035"><span class="lineNum">    5035 </span>            :         useAltOnNaCtrs_1_92 = _RANDOM[8'h2B][29:26];</a>
+<a name="5036"><span class="lineNum">    5036 </span>            :         useAltOnNaCtrs_1_93 = {_RANDOM[8'h2B][31:30], _RANDOM[8'h2C][1:0]};</a>
+<a name="5037"><span class="lineNum">    5037 </span>            :         useAltOnNaCtrs_1_94 = _RANDOM[8'h2C][5:2];</a>
+<a name="5038"><span class="lineNum">    5038 </span>            :         useAltOnNaCtrs_1_95 = _RANDOM[8'h2C][9:6];</a>
+<a name="5039"><span class="lineNum">    5039 </span>            :         useAltOnNaCtrs_1_96 = _RANDOM[8'h2C][13:10];</a>
+<a name="5040"><span class="lineNum">    5040 </span>            :         useAltOnNaCtrs_1_97 = _RANDOM[8'h2C][17:14];</a>
+<a name="5041"><span class="lineNum">    5041 </span>            :         useAltOnNaCtrs_1_98 = _RANDOM[8'h2C][21:18];</a>
+<a name="5042"><span class="lineNum">    5042 </span>            :         useAltOnNaCtrs_1_99 = _RANDOM[8'h2C][25:22];</a>
+<a name="5043"><span class="lineNum">    5043 </span>            :         useAltOnNaCtrs_1_100 = _RANDOM[8'h2C][29:26];</a>
+<a name="5044"><span class="lineNum">    5044 </span>            :         useAltOnNaCtrs_1_101 = {_RANDOM[8'h2C][31:30], _RANDOM[8'h2D][1:0]};</a>
+<a name="5045"><span class="lineNum">    5045 </span>            :         useAltOnNaCtrs_1_102 = _RANDOM[8'h2D][5:2];</a>
+<a name="5046"><span class="lineNum">    5046 </span>            :         useAltOnNaCtrs_1_103 = _RANDOM[8'h2D][9:6];</a>
+<a name="5047"><span class="lineNum">    5047 </span>            :         useAltOnNaCtrs_1_104 = _RANDOM[8'h2D][13:10];</a>
+<a name="5048"><span class="lineNum">    5048 </span>            :         useAltOnNaCtrs_1_105 = _RANDOM[8'h2D][17:14];</a>
+<a name="5049"><span class="lineNum">    5049 </span>            :         useAltOnNaCtrs_1_106 = _RANDOM[8'h2D][21:18];</a>
+<a name="5050"><span class="lineNum">    5050 </span>            :         useAltOnNaCtrs_1_107 = _RANDOM[8'h2D][25:22];</a>
+<a name="5051"><span class="lineNum">    5051 </span>            :         useAltOnNaCtrs_1_108 = _RANDOM[8'h2D][29:26];</a>
+<a name="5052"><span class="lineNum">    5052 </span>            :         useAltOnNaCtrs_1_109 = {_RANDOM[8'h2D][31:30], _RANDOM[8'h2E][1:0]};</a>
+<a name="5053"><span class="lineNum">    5053 </span>            :         useAltOnNaCtrs_1_110 = _RANDOM[8'h2E][5:2];</a>
+<a name="5054"><span class="lineNum">    5054 </span>            :         useAltOnNaCtrs_1_111 = _RANDOM[8'h2E][9:6];</a>
+<a name="5055"><span class="lineNum">    5055 </span>            :         useAltOnNaCtrs_1_112 = _RANDOM[8'h2E][13:10];</a>
+<a name="5056"><span class="lineNum">    5056 </span>            :         useAltOnNaCtrs_1_113 = _RANDOM[8'h2E][17:14];</a>
+<a name="5057"><span class="lineNum">    5057 </span>            :         useAltOnNaCtrs_1_114 = _RANDOM[8'h2E][21:18];</a>
+<a name="5058"><span class="lineNum">    5058 </span>            :         useAltOnNaCtrs_1_115 = _RANDOM[8'h2E][25:22];</a>
+<a name="5059"><span class="lineNum">    5059 </span>            :         useAltOnNaCtrs_1_116 = _RANDOM[8'h2E][29:26];</a>
+<a name="5060"><span class="lineNum">    5060 </span>            :         useAltOnNaCtrs_1_117 = {_RANDOM[8'h2E][31:30], _RANDOM[8'h2F][1:0]};</a>
+<a name="5061"><span class="lineNum">    5061 </span>            :         useAltOnNaCtrs_1_118 = _RANDOM[8'h2F][5:2];</a>
+<a name="5062"><span class="lineNum">    5062 </span>            :         useAltOnNaCtrs_1_119 = _RANDOM[8'h2F][9:6];</a>
+<a name="5063"><span class="lineNum">    5063 </span>            :         useAltOnNaCtrs_1_120 = _RANDOM[8'h2F][13:10];</a>
+<a name="5064"><span class="lineNum">    5064 </span>            :         useAltOnNaCtrs_1_121 = _RANDOM[8'h2F][17:14];</a>
+<a name="5065"><span class="lineNum">    5065 </span>            :         useAltOnNaCtrs_1_122 = _RANDOM[8'h2F][21:18];</a>
+<a name="5066"><span class="lineNum">    5066 </span>            :         useAltOnNaCtrs_1_123 = _RANDOM[8'h2F][25:22];</a>
+<a name="5067"><span class="lineNum">    5067 </span>            :         useAltOnNaCtrs_1_124 = _RANDOM[8'h2F][29:26];</a>
+<a name="5068"><span class="lineNum">    5068 </span>            :         useAltOnNaCtrs_1_125 = {_RANDOM[8'h2F][31:30], _RANDOM[8'h30][1:0]};</a>
+<a name="5069"><span class="lineNum">    5069 </span>            :         useAltOnNaCtrs_1_126 = _RANDOM[8'h30][5:2];</a>
+<a name="5070"><span class="lineNum">    5070 </span>            :         useAltOnNaCtrs_1_127 = _RANDOM[8'h30][9:6];</a>
+<a name="5071"><span class="lineNum">    5071 </span>            :         s2_provideds_0 = _RANDOM[8'h32][28];</a>
+<a name="5072"><span class="lineNum">    5072 </span>            :         s2_provideds_1 = _RANDOM[8'h32][29];</a>
+<a name="5073"><span class="lineNum">    5073 </span>            :         s2_providers_0 = _RANDOM[8'h32][31:30];</a>
+<a name="5074"><span class="lineNum">    5074 </span>            :         s2_providers_1 = _RANDOM[8'h33][1:0];</a>
+<a name="5075"><span class="lineNum">    5075 </span>            :         s2_providerResps_0_ctr = _RANDOM[8'h33][4:2];</a>
+<a name="5076"><span class="lineNum">    5076 </span>            :         s2_providerResps_0_u = _RANDOM[8'h33][5];</a>
+<a name="5077"><span class="lineNum">    5077 </span>            :         s2_providerResps_0_unconf = _RANDOM[8'h33][6];</a>
+<a name="5078"><span class="lineNum">    5078 </span>            :         s2_providerResps_1_ctr = _RANDOM[8'h33][9:7];</a>
+<a name="5079"><span class="lineNum">    5079 </span>            :         s2_providerResps_1_u = _RANDOM[8'h33][10];</a>
+<a name="5080"><span class="lineNum">    5080 </span>            :         s2_providerResps_1_unconf = _RANDOM[8'h33][11];</a>
+<a name="5081"><span class="lineNum">    5081 </span>            :         s2_altUsed_0 = _RANDOM[8'h33][12];</a>
+<a name="5082"><span class="lineNum">    5082 </span>            :         s2_altUsed_1 = _RANDOM[8'h33][13];</a>
+<a name="5083"><span class="lineNum">    5083 </span>            :         s2_tageTakens_dup_0_0 = _RANDOM[8'h33][14];</a>
+<a name="5084"><span class="lineNum">    5084 </span>            :         s2_tageTakens_dup_0_1 = _RANDOM[8'h33][15];</a>
+<a name="5085"><span class="lineNum">    5085 </span>            :         s2_tageTakens_dup_1_0 = _RANDOM[8'h33][16];</a>
+<a name="5086"><span class="lineNum">    5086 </span>            :         s2_tageTakens_dup_1_1 = _RANDOM[8'h33][17];</a>
+<a name="5087"><span class="lineNum">    5087 </span>            :         s2_tageTakens_dup_2_0 = _RANDOM[8'h33][18];</a>
+<a name="5088"><span class="lineNum">    5088 </span>            :         s2_tageTakens_dup_2_1 = _RANDOM[8'h33][19];</a>
+<a name="5089"><span class="lineNum">    5089 </span>            :         s2_tageTakens_dup_3_0 = _RANDOM[8'h33][20];</a>
+<a name="5090"><span class="lineNum">    5090 </span>            :         s2_tageTakens_dup_3_1 = _RANDOM[8'h33][21];</a>
+<a name="5091"><span class="lineNum">    5091 </span>            :         s2_finalAltPreds_0 = _RANDOM[8'h33][22];</a>
+<a name="5092"><span class="lineNum">    5092 </span>            :         s2_finalAltPreds_1 = _RANDOM[8'h33][23];</a>
+<a name="5093"><span class="lineNum">    5093 </span>            :         s2_basecnts_0 = _RANDOM[8'h33][25:24];</a>
+<a name="5094"><span class="lineNum">    5094 </span>            :         s2_basecnts_1 = _RANDOM[8'h33][27:26];</a>
+<a name="5095"><span class="lineNum">    5095 </span>            :         resp_meta_providers_0_valid_r = _RANDOM[8'h33][30];</a>
+<a name="5096"><span class="lineNum">    5096 </span>            :         resp_meta_providers_0_bits_r = {_RANDOM[8'h33][31], _RANDOM[8'h34][0]};</a>
+<a name="5097"><span class="lineNum">    5097 </span>            :         resp_meta_providerResps_0_r_ctr = _RANDOM[8'h34][3:1];</a>
+<a name="5098"><span class="lineNum">    5098 </span>            :         resp_meta_providerResps_0_r_u = _RANDOM[8'h34][4];</a>
+<a name="5099"><span class="lineNum">    5099 </span>            :         resp_meta_providerResps_0_r_unconf = _RANDOM[8'h34][5];</a>
+<a name="5100"><span class="lineNum">    5100 </span>            :         allocatableSlots = _RANDOM[8'h34][9:6];</a>
+<a name="5101"><span class="lineNum">    5101 </span>            :         resp_meta_allocates_0_r = _RANDOM[8'h34][13:10];</a>
+<a name="5102"><span class="lineNum">    5102 </span>            :         resp_meta_altUsed_0_r = _RANDOM[8'h34][14];</a>
+<a name="5103"><span class="lineNum">    5103 </span>            :         resp_meta_altDiffers_0_r = _RANDOM[8'h34][15];</a>
+<a name="5104"><span class="lineNum">    5104 </span>            :         resp_meta_takens_0_r = _RANDOM[8'h34][16];</a>
+<a name="5105"><span class="lineNum">    5105 </span>            :         resp_meta_basecnts_0_r = _RANDOM[8'h34][18:17];</a>
+<a name="5106"><span class="lineNum">    5106 </span>            :         tage_enable_dup_REG = _RANDOM[8'h34][19];</a>
+<a name="5107"><span class="lineNum">    5107 </span>            :         allocLFSR_lfsr = {_RANDOM[8'h34][31:20], _RANDOM[8'h35], _RANDOM[8'h36][19:0]};</a>
+<a name="5108"><span class="lineNum">    5108 </span>            :         resp_meta_providers_1_valid_r = _RANDOM[8'h36][20];</a>
+<a name="5109"><span class="lineNum">    5109 </span>            :         resp_meta_providers_1_bits_r = _RANDOM[8'h36][22:21];</a>
+<a name="5110"><span class="lineNum">    5110 </span>            :         resp_meta_providerResps_1_r_ctr = _RANDOM[8'h36][25:23];</a>
+<a name="5111"><span class="lineNum">    5111 </span>            :         resp_meta_providerResps_1_r_u = _RANDOM[8'h36][26];</a>
+<a name="5112"><span class="lineNum">    5112 </span>            :         resp_meta_providerResps_1_r_unconf = _RANDOM[8'h36][27];</a>
+<a name="5113"><span class="lineNum">    5113 </span>            :         allocatableSlots_1 = _RANDOM[8'h36][31:28];</a>
+<a name="5114"><span class="lineNum">    5114 </span>            :         resp_meta_allocates_1_r = _RANDOM[8'h37][3:0];</a>
+<a name="5115"><span class="lineNum">    5115 </span>            :         resp_meta_altUsed_1_r = _RANDOM[8'h37][4];</a>
+<a name="5116"><span class="lineNum">    5116 </span>            :         resp_meta_altDiffers_1_r = _RANDOM[8'h37][5];</a>
+<a name="5117"><span class="lineNum">    5117 </span>            :         resp_meta_takens_1_r = _RANDOM[8'h37][6];</a>
+<a name="5118"><span class="lineNum">    5118 </span>            :         resp_meta_basecnts_1_r = _RANDOM[8'h37][8:7];</a>
+<a name="5119"><span class="lineNum">    5119 </span>            :         tage_enable_dup_REG_1 = _RANDOM[8'h37][9];</a>
+<a name="5120"><span class="lineNum">    5120 </span>            :         allocLFSR_lfsr_1 = {_RANDOM[8'h37][31:10], _RANDOM[8'h38], _RANDOM[8'h39][9:0]};</a>
+<a name="5121"><span class="lineNum">    5121 </span>            :         tables_0_io_update_reset_u_0_REG = _RANDOM[8'h39][10];</a>
+<a name="5122"><span class="lineNum">    5122 </span>            :         tables_0_io_update_mask_0_REG = _RANDOM[8'h39][11];</a>
+<a name="5123"><span class="lineNum">    5123 </span>            :         tables_0_io_update_takens_0_r = _RANDOM[8'h39][12];</a>
+<a name="5124"><span class="lineNum">    5124 </span>            :         tables_0_io_update_alloc_0_r = _RANDOM[8'h39][13];</a>
+<a name="5125"><span class="lineNum">    5125 </span>            :         tables_0_io_update_oldCtrs_0_r = _RANDOM[8'h39][16:14];</a>
+<a name="5126"><span class="lineNum">    5126 </span>            :         tables_0_io_update_uMask_0_r = _RANDOM[8'h39][17];</a>
+<a name="5127"><span class="lineNum">    5127 </span>            :         tables_0_io_update_us_0_r = _RANDOM[8'h39][18];</a>
+<a name="5128"><span class="lineNum">    5128 </span>            :         tables_1_io_update_reset_u_0_REG = _RANDOM[8'h47][16];</a>
+<a name="5129"><span class="lineNum">    5129 </span>            :         tables_1_io_update_mask_0_REG = _RANDOM[8'h47][17];</a>
+<a name="5130"><span class="lineNum">    5130 </span>            :         tables_1_io_update_takens_0_r = _RANDOM[8'h47][18];</a>
+<a name="5131"><span class="lineNum">    5131 </span>            :         tables_1_io_update_alloc_0_r = _RANDOM[8'h47][19];</a>
+<a name="5132"><span class="lineNum">    5132 </span>            :         tables_1_io_update_oldCtrs_0_r = _RANDOM[8'h47][22:20];</a>
+<a name="5133"><span class="lineNum">    5133 </span>            :         tables_1_io_update_uMask_0_r = _RANDOM[8'h47][23];</a>
+<a name="5134"><span class="lineNum">    5134 </span>            :         tables_1_io_update_us_0_r = _RANDOM[8'h47][24];</a>
+<a name="5135"><span class="lineNum">    5135 </span>            :         tables_2_io_update_reset_u_0_REG = _RANDOM[8'h55][22];</a>
+<a name="5136"><span class="lineNum">    5136 </span>            :         tables_2_io_update_mask_0_REG = _RANDOM[8'h55][23];</a>
+<a name="5137"><span class="lineNum">    5137 </span>            :         tables_2_io_update_takens_0_r = _RANDOM[8'h55][24];</a>
+<a name="5138"><span class="lineNum">    5138 </span>            :         tables_2_io_update_alloc_0_r = _RANDOM[8'h55][25];</a>
+<a name="5139"><span class="lineNum">    5139 </span>            :         tables_2_io_update_oldCtrs_0_r = _RANDOM[8'h55][28:26];</a>
+<a name="5140"><span class="lineNum">    5140 </span>            :         tables_2_io_update_uMask_0_r = _RANDOM[8'h55][29];</a>
+<a name="5141"><span class="lineNum">    5141 </span>            :         tables_2_io_update_us_0_r = _RANDOM[8'h55][30];</a>
+<a name="5142"><span class="lineNum">    5142 </span>            :         tables_3_io_update_reset_u_0_REG = _RANDOM[8'h63][28];</a>
+<a name="5143"><span class="lineNum">    5143 </span>            :         tables_3_io_update_mask_0_REG = _RANDOM[8'h63][29];</a>
+<a name="5144"><span class="lineNum">    5144 </span>            :         tables_3_io_update_takens_0_r = _RANDOM[8'h63][30];</a>
+<a name="5145"><span class="lineNum">    5145 </span>            :         tables_3_io_update_alloc_0_r = _RANDOM[8'h63][31];</a>
+<a name="5146"><span class="lineNum">    5146 </span>            :         tables_3_io_update_oldCtrs_0_r = _RANDOM[8'h64][2:0];</a>
+<a name="5147"><span class="lineNum">    5147 </span>            :         tables_3_io_update_uMask_0_r = _RANDOM[8'h64][3];</a>
+<a name="5148"><span class="lineNum">    5148 </span>            :         tables_3_io_update_us_0_r = _RANDOM[8'h64][4];</a>
+<a name="5149"><span class="lineNum">    5149 </span>            :         tables_0_io_update_reset_u_1_REG = _RANDOM[8'h72][2];</a>
+<a name="5150"><span class="lineNum">    5150 </span>            :         tables_0_io_update_mask_1_REG = _RANDOM[8'h72][3];</a>
+<a name="5151"><span class="lineNum">    5151 </span>            :         tables_0_io_update_takens_1_r = _RANDOM[8'h72][4];</a>
+<a name="5152"><span class="lineNum">    5152 </span>            :         tables_0_io_update_alloc_1_r = _RANDOM[8'h72][5];</a>
+<a name="5153"><span class="lineNum">    5153 </span>            :         tables_0_io_update_oldCtrs_1_r = _RANDOM[8'h72][8:6];</a>
+<a name="5154"><span class="lineNum">    5154 </span>            :         tables_0_io_update_uMask_1_r = _RANDOM[8'h72][9];</a>
+<a name="5155"><span class="lineNum">    5155 </span>            :         tables_0_io_update_us_1_r = _RANDOM[8'h72][10];</a>
+<a name="5156"><span class="lineNum">    5156 </span>            :         tables_0_io_update_pc_r_1 = {_RANDOM[8'h72][31:11], _RANDOM[8'h73][19:0]};</a>
+<a name="5157"><span class="lineNum">    5157 </span>            :         tables_0_io_update_folded_hist_r_1_hist_14_folded_hist = _RANDOM[8'h74][24:17];</a>
+<a name="5158"><span class="lineNum">    5158 </span>            :         tables_0_io_update_folded_hist_r_1_hist_7_folded_hist = _RANDOM[8'h76][12:6];</a>
+<a name="5159"><span class="lineNum">    5159 </span>            :         tables_1_io_update_reset_u_1_REG = _RANDOM[8'h80][8];</a>
+<a name="5160"><span class="lineNum">    5160 </span>            :         tables_1_io_update_mask_1_REG = _RANDOM[8'h80][9];</a>
+<a name="5161"><span class="lineNum">    5161 </span>            :         tables_1_io_update_takens_1_r = _RANDOM[8'h80][10];</a>
+<a name="5162"><span class="lineNum">    5162 </span>            :         tables_1_io_update_alloc_1_r = _RANDOM[8'h80][11];</a>
+<a name="5163"><span class="lineNum">    5163 </span>            :         tables_1_io_update_oldCtrs_1_r = _RANDOM[8'h80][14:12];</a>
+<a name="5164"><span class="lineNum">    5164 </span>            :         tables_1_io_update_uMask_1_r = _RANDOM[8'h80][15];</a>
+<a name="5165"><span class="lineNum">    5165 </span>            :         tables_1_io_update_us_1_r = _RANDOM[8'h80][16];</a>
+<a name="5166"><span class="lineNum">    5166 </span>            :         tables_1_io_update_pc_r_1 = {_RANDOM[8'h80][31:17], _RANDOM[8'h81][25:0]};</a>
+<a name="5167"><span class="lineNum">    5167 </span>            :         tables_1_io_update_folded_hist_r_1_hist_15_folded_hist = _RANDOM[8'h82][22:16];</a>
+<a name="5168"><span class="lineNum">    5168 </span>            :         tables_1_io_update_folded_hist_r_1_hist_4_folded_hist = _RANDOM[8'h85][10:3];</a>
+<a name="5169"><span class="lineNum">    5169 </span>            :         tables_1_io_update_folded_hist_r_1_hist_1_folded_hist =</a>
+<a name="5170"><span class="lineNum">    5170 </span>            :           {_RANDOM[8'h85][31:27], _RANDOM[8'h86][5:0]};</a>
+<a name="5171"><span class="lineNum">    5171 </span>            :         tables_2_io_update_reset_u_1_REG = _RANDOM[8'h8E][14];</a>
+<a name="5172"><span class="lineNum">    5172 </span>            :         tables_2_io_update_mask_1_REG = _RANDOM[8'h8E][15];</a>
+<a name="5173"><span class="lineNum">    5173 </span>            :         tables_2_io_update_takens_1_r = _RANDOM[8'h8E][16];</a>
+<a name="5174"><span class="lineNum">    5174 </span>            :         tables_2_io_update_alloc_1_r = _RANDOM[8'h8E][17];</a>
+<a name="5175"><span class="lineNum">    5175 </span>            :         tables_2_io_update_oldCtrs_1_r = _RANDOM[8'h8E][20:18];</a>
+<a name="5176"><span class="lineNum">    5176 </span>            :         tables_2_io_update_uMask_1_r = _RANDOM[8'h8E][21];</a>
+<a name="5177"><span class="lineNum">    5177 </span>            :         tables_2_io_update_us_1_r = _RANDOM[8'h8E][22];</a>
+<a name="5178"><span class="lineNum">    5178 </span>            :         tables_2_io_update_pc_r_1 = {_RANDOM[8'h8E][31:23], _RANDOM[8'h8F]};</a>
+<a name="5179"><span class="lineNum">    5179 </span>            :         tables_2_io_update_folded_hist_r_1_hist_17_folded_hist = _RANDOM[8'h90][10:0];</a>
+<a name="5180"><span class="lineNum">    5180 </span>            :         tables_2_io_update_folded_hist_r_1_hist_9_folded_hist = _RANDOM[8'h92][9:3];</a>
+<a name="5181"><span class="lineNum">    5181 </span>            :         tables_2_io_update_folded_hist_r_1_hist_3_folded_hist = _RANDOM[8'h93][24:17];</a>
+<a name="5182"><span class="lineNum">    5182 </span>            :         tables_3_io_update_reset_u_1_REG = _RANDOM[8'h9C][20];</a>
+<a name="5183"><span class="lineNum">    5183 </span>            :         tables_3_io_update_mask_1_REG = _RANDOM[8'h9C][21];</a>
+<a name="5184"><span class="lineNum">    5184 </span>            :         tables_3_io_update_takens_1_r = _RANDOM[8'h9C][22];</a>
+<a name="5185"><span class="lineNum">    5185 </span>            :         tables_3_io_update_alloc_1_r = _RANDOM[8'h9C][23];</a>
+<a name="5186"><span class="lineNum">    5186 </span>            :         tables_3_io_update_oldCtrs_1_r = _RANDOM[8'h9C][26:24];</a>
+<a name="5187"><span class="lineNum">    5187 </span>            :         tables_3_io_update_uMask_1_r = _RANDOM[8'h9C][27];</a>
+<a name="5188"><span class="lineNum">    5188 </span>            :         tables_3_io_update_us_1_r = _RANDOM[8'h9C][28];</a>
+<a name="5189"><span class="lineNum">    5189 </span>            :         tables_3_io_update_pc_r_1 =</a>
+<a name="5190"><span class="lineNum">    5190 </span>            :           {_RANDOM[8'h9C][31:29], _RANDOM[8'h9D], _RANDOM[8'h9E][5:0]};</a>
+<a name="5191"><span class="lineNum">    5191 </span>            :         tables_3_io_update_folded_hist_r_1_hist_16_folded_hist = _RANDOM[8'h9E][27:17];</a>
+<a name="5192"><span class="lineNum">    5192 </span>            :         tables_3_io_update_folded_hist_r_1_hist_8_folded_hist = _RANDOM[8'hA0][23:16];</a>
+<a name="5193"><span class="lineNum">    5193 </span>            :         tables_3_io_update_folded_hist_r_1_hist_5_folded_hist = _RANDOM[8'hA1][14:8];</a>
+<a name="5194"><span class="lineNum">    5194 </span>            :         REG_2_0 = _RANDOM[8'hAA][26];</a>
+<a name="5195"><span class="lineNum">    5195 </span>            :         REG_2_1 = _RANDOM[8'hAA][27];</a>
+<a name="5196"><span class="lineNum">    5196 </span>            :         r_0 = _RANDOM[8'hAA][29:28];</a>
+<a name="5197"><span class="lineNum">    5197 </span>            :         r_1 = _RANDOM[8'hAA][31:30];</a>
+<a name="5198"><span class="lineNum">    5198 </span>            :         bt_io_update_pc_r = {_RANDOM[8'hAB], _RANDOM[8'hAC][8:0]};</a>
+<a name="5199"><span class="lineNum">    5199 </span>            :         r_1_0 = _RANDOM[8'hAC][9];</a>
+<a name="5200"><span class="lineNum">    5200 </span>            :         r_1_1 = _RANDOM[8'hAC][10];</a>
+<a name="5201"><span class="lineNum">    5201 </span>            :         scThresholds_0_ctr = _RANDOM[8'hAD][31:27];</a>
+<a name="5202"><span class="lineNum">    5202 </span>            :         scThresholds_0_thres = _RANDOM[8'hAE][7:0];</a>
+<a name="5203"><span class="lineNum">    5203 </span>            :         scThresholds_1_ctr = _RANDOM[8'hAE][12:8];</a>
+<a name="5204"><span class="lineNum">    5204 </span>            :         scThresholds_1_thres = _RANDOM[8'hAE][20:13];</a>
+<a name="5205"><span class="lineNum">    5205 </span>            :         s2_scTableSums_0 = _RANDOM[8'hAE][29:21];</a>
+<a name="5206"><span class="lineNum">    5206 </span>            :         s2_scTableSums_1 = {_RANDOM[8'hAE][31:30], _RANDOM[8'hAF][6:0]};</a>
+<a name="5207"><span class="lineNum">    5207 </span>            :         s2_tagePrvdCtrCentered_r = _RANDOM[8'hAF][9:7];</a>
+<a name="5208"><span class="lineNum">    5208 </span>            :         s2_scResps_r_0_ctrs_0_0 = _RANDOM[8'hAF][15:10];</a>
+<a name="5209"><span class="lineNum">    5209 </span>            :         s2_scResps_r_0_ctrs_0_1 = _RANDOM[8'hAF][21:16];</a>
+<a name="5210"><span class="lineNum">    5210 </span>            :         s2_scResps_r_1_ctrs_0_0 = _RANDOM[8'hB0][7:2];</a>
+<a name="5211"><span class="lineNum">    5211 </span>            :         s2_scResps_r_1_ctrs_0_1 = _RANDOM[8'hB0][13:8];</a>
+<a name="5212"><span class="lineNum">    5212 </span>            :         s2_scResps_r_2_ctrs_0_0 = _RANDOM[8'hB0][31:26];</a>
+<a name="5213"><span class="lineNum">    5213 </span>            :         s2_scResps_r_2_ctrs_0_1 = _RANDOM[8'hB1][5:0];</a>
+<a name="5214"><span class="lineNum">    5214 </span>            :         s2_scResps_r_3_ctrs_0_0 = _RANDOM[8'hB1][23:18];</a>
+<a name="5215"><span class="lineNum">    5215 </span>            :         s2_scResps_r_3_ctrs_0_1 = _RANDOM[8'hB1][29:24];</a>
+<a name="5216"><span class="lineNum">    5216 </span>            :         resp_meta_scMeta_tageTakens_0_r = _RANDOM[8'hB2][12];</a>
+<a name="5217"><span class="lineNum">    5217 </span>            :         resp_meta_scMeta_scUsed_0_r = _RANDOM[8'hB2][13];</a>
+<a name="5218"><span class="lineNum">    5218 </span>            :         resp_meta_scMeta_scPreds_0_r = _RANDOM[8'hB2][14];</a>
+<a name="5219"><span class="lineNum">    5219 </span>            :         r_2_0 = _RANDOM[8'hB2][20:15];</a>
+<a name="5220"><span class="lineNum">    5220 </span>            :         r_2_1 = _RANDOM[8'hB2][26:21];</a>
+<a name="5221"><span class="lineNum">    5221 </span>            :         r_2_2 = {_RANDOM[8'hB2][31:27], _RANDOM[8'hB3][0]};</a>
+<a name="5222"><span class="lineNum">    5222 </span>            :         r_2_3 = _RANDOM[8'hB3][6:1];</a>
+<a name="5223"><span class="lineNum">    5223 </span>            :         s3_pred_dup_0 = _RANDOM[8'hB3][7];</a>
+<a name="5224"><span class="lineNum">    5224 </span>            :         s3_pred_dup_1 = _RANDOM[8'hB3][8];</a>
+<a name="5225"><span class="lineNum">    5225 </span>            :         s3_pred_dup_2 = _RANDOM[8'hB3][9];</a>
+<a name="5226"><span class="lineNum">    5226 </span>            :         s3_pred_dup_3 = _RANDOM[8'hB3][10];</a>
+<a name="5227"><span class="lineNum">    5227 </span>            :         sc_enable_dup_REG = _RANDOM[8'hB3][11];</a>
+<a name="5228"><span class="lineNum">    5228 </span>            :         s2_scTableSums_1_0 = _RANDOM[8'hB3][20:12];</a>
+<a name="5229"><span class="lineNum">    5229 </span>            :         s2_scTableSums_1_1 = _RANDOM[8'hB3][29:21];</a>
+<a name="5230"><span class="lineNum">    5230 </span>            :         s2_tagePrvdCtrCentered_r_1 = {_RANDOM[8'hB3][31:30], _RANDOM[8'hB4][0]};</a>
+<a name="5231"><span class="lineNum">    5231 </span>            :         s2_scResps_r_1_0_ctrs_1_0 = _RANDOM[8'hB4][18:13];</a>
+<a name="5232"><span class="lineNum">    5232 </span>            :         s2_scResps_r_1_0_ctrs_1_1 = _RANDOM[8'hB4][24:19];</a>
+<a name="5233"><span class="lineNum">    5233 </span>            :         s2_scResps_r_1_1_ctrs_1_0 = _RANDOM[8'hB5][10:5];</a>
+<a name="5234"><span class="lineNum">    5234 </span>            :         s2_scResps_r_1_1_ctrs_1_1 = _RANDOM[8'hB5][16:11];</a>
+<a name="5235"><span class="lineNum">    5235 </span>            :         s2_scResps_r_1_2_ctrs_1_0 = {_RANDOM[8'hB5][31:29], _RANDOM[8'hB6][2:0]};</a>
+<a name="5236"><span class="lineNum">    5236 </span>            :         s2_scResps_r_1_2_ctrs_1_1 = _RANDOM[8'hB6][8:3];</a>
+<a name="5237"><span class="lineNum">    5237 </span>            :         s2_scResps_r_1_3_ctrs_1_0 = _RANDOM[8'hB6][26:21];</a>
+<a name="5238"><span class="lineNum">    5238 </span>            :         s2_scResps_r_1_3_ctrs_1_1 = {_RANDOM[8'hB6][31:27], _RANDOM[8'hB7][0]};</a>
+<a name="5239"><span class="lineNum">    5239 </span>            :         resp_meta_scMeta_tageTakens_1_r = _RANDOM[8'hB7][3];</a>
+<a name="5240"><span class="lineNum">    5240 </span>            :         resp_meta_scMeta_scUsed_1_r = _RANDOM[8'hB7][4];</a>
+<a name="5241"><span class="lineNum">    5241 </span>            :         resp_meta_scMeta_scPreds_1_r = _RANDOM[8'hB7][5];</a>
+<a name="5242"><span class="lineNum">    5242 </span>            :         r_3_0 = _RANDOM[8'hB7][11:6];</a>
+<a name="5243"><span class="lineNum">    5243 </span>            :         r_3_1 = _RANDOM[8'hB7][17:12];</a>
+<a name="5244"><span class="lineNum">    5244 </span>            :         r_3_2 = _RANDOM[8'hB7][23:18];</a>
+<a name="5245"><span class="lineNum">    5245 </span>            :         r_3_3 = _RANDOM[8'hB7][29:24];</a>
+<a name="5246"><span class="lineNum">    5246 </span>            :         s3_pred_dup_0_1 = _RANDOM[8'hB7][30];</a>
+<a name="5247"><span class="lineNum">    5247 </span>            :         s3_pred_dup_1_1 = _RANDOM[8'hB7][31];</a>
+<a name="5248"><span class="lineNum">    5248 </span>            :         s3_pred_dup_2_1 = _RANDOM[8'hB8][0];</a>
+<a name="5249"><span class="lineNum">    5249 </span>            :         s3_pred_dup_3_1 = _RANDOM[8'hB8][1];</a>
+<a name="5250"><span class="lineNum">    5250 </span>            :         sc_enable_dup_REG_1 = _RANDOM[8'hB8][2];</a>
+<a name="5251"><span class="lineNum">    5251 </span>            :         scTables_0_io_update_mask_0_REG = _RANDOM[8'hB8][3];</a>
+<a name="5252"><span class="lineNum">    5252 </span>            :         scTables_0_io_update_tagePreds_0_r = _RANDOM[8'hB8][4];</a>
+<a name="5253"><span class="lineNum">    5253 </span>            :         scTables_0_io_update_takens_0_r = _RANDOM[8'hB8][5];</a>
+<a name="5254"><span class="lineNum">    5254 </span>            :         scTables_0_io_update_oldCtrs_0_r = _RANDOM[8'hB8][11:6];</a>
+<a name="5255"><span class="lineNum">    5255 </span>            :         scTables_1_io_update_mask_0_REG = _RANDOM[8'hBE][9];</a>
+<a name="5256"><span class="lineNum">    5256 </span>            :         scTables_1_io_update_tagePreds_0_r = _RANDOM[8'hBE][10];</a>
+<a name="5257"><span class="lineNum">    5257 </span>            :         scTables_1_io_update_takens_0_r = _RANDOM[8'hBE][11];</a>
+<a name="5258"><span class="lineNum">    5258 </span>            :         scTables_1_io_update_oldCtrs_0_r = _RANDOM[8'hBE][17:12];</a>
+<a name="5259"><span class="lineNum">    5259 </span>            :         scTables_2_io_update_mask_0_REG = _RANDOM[8'hC4][15];</a>
+<a name="5260"><span class="lineNum">    5260 </span>            :         scTables_2_io_update_tagePreds_0_r = _RANDOM[8'hC4][16];</a>
+<a name="5261"><span class="lineNum">    5261 </span>            :         scTables_2_io_update_takens_0_r = _RANDOM[8'hC4][17];</a>
+<a name="5262"><span class="lineNum">    5262 </span>            :         scTables_2_io_update_oldCtrs_0_r = _RANDOM[8'hC4][23:18];</a>
+<a name="5263"><span class="lineNum">    5263 </span>            :         scTables_3_io_update_mask_0_REG = _RANDOM[8'hCA][21];</a>
+<a name="5264"><span class="lineNum">    5264 </span>            :         scTables_3_io_update_tagePreds_0_r = _RANDOM[8'hCA][22];</a>
+<a name="5265"><span class="lineNum">    5265 </span>            :         scTables_3_io_update_takens_0_r = _RANDOM[8'hCA][23];</a>
+<a name="5266"><span class="lineNum">    5266 </span>            :         scTables_3_io_update_oldCtrs_0_r = _RANDOM[8'hCA][29:24];</a>
+<a name="5267"><span class="lineNum">    5267 </span>            :         scTables_0_io_update_mask_1_REG = _RANDOM[8'hD0][27];</a>
+<a name="5268"><span class="lineNum">    5268 </span>            :         scTables_0_io_update_tagePreds_1_r = _RANDOM[8'hD0][28];</a>
+<a name="5269"><span class="lineNum">    5269 </span>            :         scTables_0_io_update_takens_1_r = _RANDOM[8'hD0][29];</a>
+<a name="5270"><span class="lineNum">    5270 </span>            :         scTables_0_io_update_oldCtrs_1_r = {_RANDOM[8'hD0][31:30], _RANDOM[8'hD1][3:0]};</a>
+<a name="5271"><span class="lineNum">    5271 </span>            :         scTables_0_io_update_pc_r_1 = {_RANDOM[8'hD1][31:4], _RANDOM[8'hD2][12:0]};</a>
+<a name="5272"><span class="lineNum">    5272 </span>            :         scTables_1_io_update_mask_1_REG = _RANDOM[8'hD7][1];</a>
+<a name="5273"><span class="lineNum">    5273 </span>            :         scTables_1_io_update_tagePreds_1_r = _RANDOM[8'hD7][2];</a>
+<a name="5274"><span class="lineNum">    5274 </span>            :         scTables_1_io_update_takens_1_r = _RANDOM[8'hD7][3];</a>
+<a name="5275"><span class="lineNum">    5275 </span>            :         scTables_1_io_update_oldCtrs_1_r = _RANDOM[8'hD7][9:4];</a>
+<a name="5276"><span class="lineNum">    5276 </span>            :         scTables_1_io_update_pc_r_1 = {_RANDOM[8'hD7][31:10], _RANDOM[8'hD8][18:0]};</a>
+<a name="5277"><span class="lineNum">    5277 </span>            :         scTables_1_io_update_folded_hist_r_1_hist_12_folded_hist = _RANDOM[8'hDA][4:1];</a>
+<a name="5278"><span class="lineNum">    5278 </span>            :         scTables_2_io_update_mask_1_REG = _RANDOM[8'hDD][7];</a>
+<a name="5279"><span class="lineNum">    5279 </span>            :         scTables_2_io_update_tagePreds_1_r = _RANDOM[8'hDD][8];</a>
+<a name="5280"><span class="lineNum">    5280 </span>            :         scTables_2_io_update_takens_1_r = _RANDOM[8'hDD][9];</a>
+<a name="5281"><span class="lineNum">    5281 </span>            :         scTables_2_io_update_oldCtrs_1_r = _RANDOM[8'hDD][15:10];</a>
+<a name="5282"><span class="lineNum">    5282 </span>            :         scTables_2_io_update_pc_r_1 = {_RANDOM[8'hDD][31:16], _RANDOM[8'hDE][24:0]};</a>
+<a name="5283"><span class="lineNum">    5283 </span>            :         scTables_2_io_update_folded_hist_r_1_hist_11_folded_hist = _RANDOM[8'hE0][18:11];</a>
+<a name="5284"><span class="lineNum">    5284 </span>            :         scTables_3_io_update_mask_1_REG = _RANDOM[8'hE3][13];</a>
+<a name="5285"><span class="lineNum">    5285 </span>            :         scTables_3_io_update_tagePreds_1_r = _RANDOM[8'hE3][14];</a>
+<a name="5286"><span class="lineNum">    5286 </span>            :         scTables_3_io_update_takens_1_r = _RANDOM[8'hE3][15];</a>
+<a name="5287"><span class="lineNum">    5287 </span>            :         scTables_3_io_update_oldCtrs_1_r = _RANDOM[8'hE3][21:16];</a>
+<a name="5288"><span class="lineNum">    5288 </span>            :         scTables_3_io_update_pc_r_1 = {_RANDOM[8'hE3][31:22], _RANDOM[8'hE4][30:0]};</a>
+<a name="5289"><span class="lineNum">    5289 </span>            :         scTables_3_io_update_folded_hist_r_1_hist_2_folded_hist = _RANDOM[8'hE8][31:24];</a>
+<a name="5290"><span class="lineNum">    5290 </span>            :         io_perf_0_value_REG = _RANDOM[8'hE9][20:19];</a>
+<a name="5291"><span class="lineNum">    5291 </span>            :         io_perf_0_value_REG_1 = _RANDOM[8'hE9][22:21];</a>
+<a name="5292"><span class="lineNum">    5292 </span>            :         io_perf_1_value_REG = _RANDOM[8'hE9][24:23];</a>
+<a name="5293"><span class="lineNum">    5293 </span>            :         io_perf_1_value_REG_1 = _RANDOM[8'hE9][26:25];</a>
+<a name="5294"><span class="lineNum">    5294 </span>            :         io_perf_2_value_REG = _RANDOM[8'hE9][28:27];</a>
+<a name="5295"><span class="lineNum">    5295 </span>            :         io_perf_2_value_REG_1 = _RANDOM[8'hE9][30:29];</a>
+<a name="5296"><span class="lineNum">    5296 </span>            :       `endif // RANDOMIZE_REG_INIT</a>
+<a name="5297"><span class="lineNum">    5297 </span><span class="lineCov">         17 :       if (reset) begin</span></a>
+<a name="5298"><span class="lineNum">    5298 </span><span class="lineCov">         12 :         bankTickCtrDistanceToTops_0 = 7'h7F;</span></a>
+<a name="5299"><span class="lineNum">    5299 </span><span class="lineCov">         12 :         bankTickCtrDistanceToTops_1 = 7'h7F;</span></a>
+<a name="5300"><span class="lineNum">    5300 </span><span class="lineCov">         12 :         bankTickCtrs_0 = 7'h0;</span></a>
+<a name="5301"><span class="lineNum">    5301 </span><span class="lineCov">         12 :         bankTickCtrs_1 = 7'h0;</span></a>
+<a name="5302"><span class="lineNum">    5302 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_0 = 4'h8;</span></a>
+<a name="5303"><span class="lineNum">    5303 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_1 = 4'h8;</span></a>
+<a name="5304"><span class="lineNum">    5304 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_2 = 4'h8;</span></a>
+<a name="5305"><span class="lineNum">    5305 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_3 = 4'h8;</span></a>
+<a name="5306"><span class="lineNum">    5306 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_4 = 4'h8;</span></a>
+<a name="5307"><span class="lineNum">    5307 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_5 = 4'h8;</span></a>
+<a name="5308"><span class="lineNum">    5308 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_6 = 4'h8;</span></a>
+<a name="5309"><span class="lineNum">    5309 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_7 = 4'h8;</span></a>
+<a name="5310"><span class="lineNum">    5310 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_8 = 4'h8;</span></a>
+<a name="5311"><span class="lineNum">    5311 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_9 = 4'h8;</span></a>
+<a name="5312"><span class="lineNum">    5312 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_10 = 4'h8;</span></a>
+<a name="5313"><span class="lineNum">    5313 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_11 = 4'h8;</span></a>
+<a name="5314"><span class="lineNum">    5314 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_12 = 4'h8;</span></a>
+<a name="5315"><span class="lineNum">    5315 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_13 = 4'h8;</span></a>
+<a name="5316"><span class="lineNum">    5316 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_14 = 4'h8;</span></a>
+<a name="5317"><span class="lineNum">    5317 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_15 = 4'h8;</span></a>
+<a name="5318"><span class="lineNum">    5318 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_16 = 4'h8;</span></a>
+<a name="5319"><span class="lineNum">    5319 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_17 = 4'h8;</span></a>
+<a name="5320"><span class="lineNum">    5320 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_18 = 4'h8;</span></a>
+<a name="5321"><span class="lineNum">    5321 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_19 = 4'h8;</span></a>
+<a name="5322"><span class="lineNum">    5322 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_20 = 4'h8;</span></a>
+<a name="5323"><span class="lineNum">    5323 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_21 = 4'h8;</span></a>
+<a name="5324"><span class="lineNum">    5324 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_22 = 4'h8;</span></a>
+<a name="5325"><span class="lineNum">    5325 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_23 = 4'h8;</span></a>
+<a name="5326"><span class="lineNum">    5326 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_24 = 4'h8;</span></a>
+<a name="5327"><span class="lineNum">    5327 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_25 = 4'h8;</span></a>
+<a name="5328"><span class="lineNum">    5328 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_26 = 4'h8;</span></a>
+<a name="5329"><span class="lineNum">    5329 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_27 = 4'h8;</span></a>
+<a name="5330"><span class="lineNum">    5330 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_28 = 4'h8;</span></a>
+<a name="5331"><span class="lineNum">    5331 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_29 = 4'h8;</span></a>
+<a name="5332"><span class="lineNum">    5332 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_30 = 4'h8;</span></a>
+<a name="5333"><span class="lineNum">    5333 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_31 = 4'h8;</span></a>
+<a name="5334"><span class="lineNum">    5334 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_32 = 4'h8;</span></a>
+<a name="5335"><span class="lineNum">    5335 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_33 = 4'h8;</span></a>
+<a name="5336"><span class="lineNum">    5336 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_34 = 4'h8;</span></a>
+<a name="5337"><span class="lineNum">    5337 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_35 = 4'h8;</span></a>
+<a name="5338"><span class="lineNum">    5338 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_36 = 4'h8;</span></a>
+<a name="5339"><span class="lineNum">    5339 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_37 = 4'h8;</span></a>
+<a name="5340"><span class="lineNum">    5340 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_38 = 4'h8;</span></a>
+<a name="5341"><span class="lineNum">    5341 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_39 = 4'h8;</span></a>
+<a name="5342"><span class="lineNum">    5342 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_40 = 4'h8;</span></a>
+<a name="5343"><span class="lineNum">    5343 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_41 = 4'h8;</span></a>
+<a name="5344"><span class="lineNum">    5344 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_42 = 4'h8;</span></a>
+<a name="5345"><span class="lineNum">    5345 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_43 = 4'h8;</span></a>
+<a name="5346"><span class="lineNum">    5346 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_44 = 4'h8;</span></a>
+<a name="5347"><span class="lineNum">    5347 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_45 = 4'h8;</span></a>
+<a name="5348"><span class="lineNum">    5348 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_46 = 4'h8;</span></a>
+<a name="5349"><span class="lineNum">    5349 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_47 = 4'h8;</span></a>
+<a name="5350"><span class="lineNum">    5350 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_48 = 4'h8;</span></a>
+<a name="5351"><span class="lineNum">    5351 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_49 = 4'h8;</span></a>
+<a name="5352"><span class="lineNum">    5352 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_50 = 4'h8;</span></a>
+<a name="5353"><span class="lineNum">    5353 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_51 = 4'h8;</span></a>
+<a name="5354"><span class="lineNum">    5354 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_52 = 4'h8;</span></a>
+<a name="5355"><span class="lineNum">    5355 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_53 = 4'h8;</span></a>
+<a name="5356"><span class="lineNum">    5356 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_54 = 4'h8;</span></a>
+<a name="5357"><span class="lineNum">    5357 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_55 = 4'h8;</span></a>
+<a name="5358"><span class="lineNum">    5358 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_56 = 4'h8;</span></a>
+<a name="5359"><span class="lineNum">    5359 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_57 = 4'h8;</span></a>
+<a name="5360"><span class="lineNum">    5360 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_58 = 4'h8;</span></a>
+<a name="5361"><span class="lineNum">    5361 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_59 = 4'h8;</span></a>
+<a name="5362"><span class="lineNum">    5362 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_60 = 4'h8;</span></a>
+<a name="5363"><span class="lineNum">    5363 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_61 = 4'h8;</span></a>
+<a name="5364"><span class="lineNum">    5364 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_62 = 4'h8;</span></a>
+<a name="5365"><span class="lineNum">    5365 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_63 = 4'h8;</span></a>
+<a name="5366"><span class="lineNum">    5366 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_64 = 4'h8;</span></a>
+<a name="5367"><span class="lineNum">    5367 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_65 = 4'h8;</span></a>
+<a name="5368"><span class="lineNum">    5368 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_66 = 4'h8;</span></a>
+<a name="5369"><span class="lineNum">    5369 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_67 = 4'h8;</span></a>
+<a name="5370"><span class="lineNum">    5370 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_68 = 4'h8;</span></a>
+<a name="5371"><span class="lineNum">    5371 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_69 = 4'h8;</span></a>
+<a name="5372"><span class="lineNum">    5372 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_70 = 4'h8;</span></a>
+<a name="5373"><span class="lineNum">    5373 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_71 = 4'h8;</span></a>
+<a name="5374"><span class="lineNum">    5374 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_72 = 4'h8;</span></a>
+<a name="5375"><span class="lineNum">    5375 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_73 = 4'h8;</span></a>
+<a name="5376"><span class="lineNum">    5376 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_74 = 4'h8;</span></a>
+<a name="5377"><span class="lineNum">    5377 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_75 = 4'h8;</span></a>
+<a name="5378"><span class="lineNum">    5378 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_76 = 4'h8;</span></a>
+<a name="5379"><span class="lineNum">    5379 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_77 = 4'h8;</span></a>
+<a name="5380"><span class="lineNum">    5380 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_78 = 4'h8;</span></a>
+<a name="5381"><span class="lineNum">    5381 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_79 = 4'h8;</span></a>
+<a name="5382"><span class="lineNum">    5382 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_80 = 4'h8;</span></a>
+<a name="5383"><span class="lineNum">    5383 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_81 = 4'h8;</span></a>
+<a name="5384"><span class="lineNum">    5384 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_82 = 4'h8;</span></a>
+<a name="5385"><span class="lineNum">    5385 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_83 = 4'h8;</span></a>
+<a name="5386"><span class="lineNum">    5386 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_84 = 4'h8;</span></a>
+<a name="5387"><span class="lineNum">    5387 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_85 = 4'h8;</span></a>
+<a name="5388"><span class="lineNum">    5388 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_86 = 4'h8;</span></a>
+<a name="5389"><span class="lineNum">    5389 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_87 = 4'h8;</span></a>
+<a name="5390"><span class="lineNum">    5390 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_88 = 4'h8;</span></a>
+<a name="5391"><span class="lineNum">    5391 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_89 = 4'h8;</span></a>
+<a name="5392"><span class="lineNum">    5392 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_90 = 4'h8;</span></a>
+<a name="5393"><span class="lineNum">    5393 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_91 = 4'h8;</span></a>
+<a name="5394"><span class="lineNum">    5394 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_92 = 4'h8;</span></a>
+<a name="5395"><span class="lineNum">    5395 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_93 = 4'h8;</span></a>
+<a name="5396"><span class="lineNum">    5396 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_94 = 4'h8;</span></a>
+<a name="5397"><span class="lineNum">    5397 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_95 = 4'h8;</span></a>
+<a name="5398"><span class="lineNum">    5398 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_96 = 4'h8;</span></a>
+<a name="5399"><span class="lineNum">    5399 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_97 = 4'h8;</span></a>
+<a name="5400"><span class="lineNum">    5400 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_98 = 4'h8;</span></a>
+<a name="5401"><span class="lineNum">    5401 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_99 = 4'h8;</span></a>
+<a name="5402"><span class="lineNum">    5402 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_100 = 4'h8;</span></a>
+<a name="5403"><span class="lineNum">    5403 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_101 = 4'h8;</span></a>
+<a name="5404"><span class="lineNum">    5404 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_102 = 4'h8;</span></a>
+<a name="5405"><span class="lineNum">    5405 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_103 = 4'h8;</span></a>
+<a name="5406"><span class="lineNum">    5406 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_104 = 4'h8;</span></a>
+<a name="5407"><span class="lineNum">    5407 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_105 = 4'h8;</span></a>
+<a name="5408"><span class="lineNum">    5408 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_106 = 4'h8;</span></a>
+<a name="5409"><span class="lineNum">    5409 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_107 = 4'h8;</span></a>
+<a name="5410"><span class="lineNum">    5410 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_108 = 4'h8;</span></a>
+<a name="5411"><span class="lineNum">    5411 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_109 = 4'h8;</span></a>
+<a name="5412"><span class="lineNum">    5412 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_110 = 4'h8;</span></a>
+<a name="5413"><span class="lineNum">    5413 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_111 = 4'h8;</span></a>
+<a name="5414"><span class="lineNum">    5414 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_112 = 4'h8;</span></a>
+<a name="5415"><span class="lineNum">    5415 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_113 = 4'h8;</span></a>
+<a name="5416"><span class="lineNum">    5416 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_114 = 4'h8;</span></a>
+<a name="5417"><span class="lineNum">    5417 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_115 = 4'h8;</span></a>
+<a name="5418"><span class="lineNum">    5418 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_116 = 4'h8;</span></a>
+<a name="5419"><span class="lineNum">    5419 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_117 = 4'h8;</span></a>
+<a name="5420"><span class="lineNum">    5420 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_118 = 4'h8;</span></a>
+<a name="5421"><span class="lineNum">    5421 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_119 = 4'h8;</span></a>
+<a name="5422"><span class="lineNum">    5422 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_120 = 4'h8;</span></a>
+<a name="5423"><span class="lineNum">    5423 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_121 = 4'h8;</span></a>
+<a name="5424"><span class="lineNum">    5424 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_122 = 4'h8;</span></a>
+<a name="5425"><span class="lineNum">    5425 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_123 = 4'h8;</span></a>
+<a name="5426"><span class="lineNum">    5426 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_124 = 4'h8;</span></a>
+<a name="5427"><span class="lineNum">    5427 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_125 = 4'h8;</span></a>
+<a name="5428"><span class="lineNum">    5428 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_126 = 4'h8;</span></a>
+<a name="5429"><span class="lineNum">    5429 </span><span class="lineCov">         12 :         useAltOnNaCtrs_0_127 = 4'h8;</span></a>
+<a name="5430"><span class="lineNum">    5430 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_0 = 4'h8;</span></a>
+<a name="5431"><span class="lineNum">    5431 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_1 = 4'h8;</span></a>
+<a name="5432"><span class="lineNum">    5432 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_2 = 4'h8;</span></a>
+<a name="5433"><span class="lineNum">    5433 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_3 = 4'h8;</span></a>
+<a name="5434"><span class="lineNum">    5434 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_4 = 4'h8;</span></a>
+<a name="5435"><span class="lineNum">    5435 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_5 = 4'h8;</span></a>
+<a name="5436"><span class="lineNum">    5436 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_6 = 4'h8;</span></a>
+<a name="5437"><span class="lineNum">    5437 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_7 = 4'h8;</span></a>
+<a name="5438"><span class="lineNum">    5438 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_8 = 4'h8;</span></a>
+<a name="5439"><span class="lineNum">    5439 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_9 = 4'h8;</span></a>
+<a name="5440"><span class="lineNum">    5440 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_10 = 4'h8;</span></a>
+<a name="5441"><span class="lineNum">    5441 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_11 = 4'h8;</span></a>
+<a name="5442"><span class="lineNum">    5442 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_12 = 4'h8;</span></a>
+<a name="5443"><span class="lineNum">    5443 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_13 = 4'h8;</span></a>
+<a name="5444"><span class="lineNum">    5444 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_14 = 4'h8;</span></a>
+<a name="5445"><span class="lineNum">    5445 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_15 = 4'h8;</span></a>
+<a name="5446"><span class="lineNum">    5446 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_16 = 4'h8;</span></a>
+<a name="5447"><span class="lineNum">    5447 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_17 = 4'h8;</span></a>
+<a name="5448"><span class="lineNum">    5448 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_18 = 4'h8;</span></a>
+<a name="5449"><span class="lineNum">    5449 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_19 = 4'h8;</span></a>
+<a name="5450"><span class="lineNum">    5450 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_20 = 4'h8;</span></a>
+<a name="5451"><span class="lineNum">    5451 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_21 = 4'h8;</span></a>
+<a name="5452"><span class="lineNum">    5452 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_22 = 4'h8;</span></a>
+<a name="5453"><span class="lineNum">    5453 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_23 = 4'h8;</span></a>
+<a name="5454"><span class="lineNum">    5454 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_24 = 4'h8;</span></a>
+<a name="5455"><span class="lineNum">    5455 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_25 = 4'h8;</span></a>
+<a name="5456"><span class="lineNum">    5456 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_26 = 4'h8;</span></a>
+<a name="5457"><span class="lineNum">    5457 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_27 = 4'h8;</span></a>
+<a name="5458"><span class="lineNum">    5458 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_28 = 4'h8;</span></a>
+<a name="5459"><span class="lineNum">    5459 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_29 = 4'h8;</span></a>
+<a name="5460"><span class="lineNum">    5460 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_30 = 4'h8;</span></a>
+<a name="5461"><span class="lineNum">    5461 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_31 = 4'h8;</span></a>
+<a name="5462"><span class="lineNum">    5462 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_32 = 4'h8;</span></a>
+<a name="5463"><span class="lineNum">    5463 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_33 = 4'h8;</span></a>
+<a name="5464"><span class="lineNum">    5464 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_34 = 4'h8;</span></a>
+<a name="5465"><span class="lineNum">    5465 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_35 = 4'h8;</span></a>
+<a name="5466"><span class="lineNum">    5466 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_36 = 4'h8;</span></a>
+<a name="5467"><span class="lineNum">    5467 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_37 = 4'h8;</span></a>
+<a name="5468"><span class="lineNum">    5468 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_38 = 4'h8;</span></a>
+<a name="5469"><span class="lineNum">    5469 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_39 = 4'h8;</span></a>
+<a name="5470"><span class="lineNum">    5470 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_40 = 4'h8;</span></a>
+<a name="5471"><span class="lineNum">    5471 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_41 = 4'h8;</span></a>
+<a name="5472"><span class="lineNum">    5472 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_42 = 4'h8;</span></a>
+<a name="5473"><span class="lineNum">    5473 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_43 = 4'h8;</span></a>
+<a name="5474"><span class="lineNum">    5474 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_44 = 4'h8;</span></a>
+<a name="5475"><span class="lineNum">    5475 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_45 = 4'h8;</span></a>
+<a name="5476"><span class="lineNum">    5476 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_46 = 4'h8;</span></a>
+<a name="5477"><span class="lineNum">    5477 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_47 = 4'h8;</span></a>
+<a name="5478"><span class="lineNum">    5478 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_48 = 4'h8;</span></a>
+<a name="5479"><span class="lineNum">    5479 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_49 = 4'h8;</span></a>
+<a name="5480"><span class="lineNum">    5480 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_50 = 4'h8;</span></a>
+<a name="5481"><span class="lineNum">    5481 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_51 = 4'h8;</span></a>
+<a name="5482"><span class="lineNum">    5482 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_52 = 4'h8;</span></a>
+<a name="5483"><span class="lineNum">    5483 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_53 = 4'h8;</span></a>
+<a name="5484"><span class="lineNum">    5484 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_54 = 4'h8;</span></a>
+<a name="5485"><span class="lineNum">    5485 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_55 = 4'h8;</span></a>
+<a name="5486"><span class="lineNum">    5486 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_56 = 4'h8;</span></a>
+<a name="5487"><span class="lineNum">    5487 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_57 = 4'h8;</span></a>
+<a name="5488"><span class="lineNum">    5488 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_58 = 4'h8;</span></a>
+<a name="5489"><span class="lineNum">    5489 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_59 = 4'h8;</span></a>
+<a name="5490"><span class="lineNum">    5490 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_60 = 4'h8;</span></a>
+<a name="5491"><span class="lineNum">    5491 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_61 = 4'h8;</span></a>
+<a name="5492"><span class="lineNum">    5492 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_62 = 4'h8;</span></a>
+<a name="5493"><span class="lineNum">    5493 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_63 = 4'h8;</span></a>
+<a name="5494"><span class="lineNum">    5494 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_64 = 4'h8;</span></a>
+<a name="5495"><span class="lineNum">    5495 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_65 = 4'h8;</span></a>
+<a name="5496"><span class="lineNum">    5496 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_66 = 4'h8;</span></a>
+<a name="5497"><span class="lineNum">    5497 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_67 = 4'h8;</span></a>
+<a name="5498"><span class="lineNum">    5498 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_68 = 4'h8;</span></a>
+<a name="5499"><span class="lineNum">    5499 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_69 = 4'h8;</span></a>
+<a name="5500"><span class="lineNum">    5500 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_70 = 4'h8;</span></a>
+<a name="5501"><span class="lineNum">    5501 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_71 = 4'h8;</span></a>
+<a name="5502"><span class="lineNum">    5502 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_72 = 4'h8;</span></a>
+<a name="5503"><span class="lineNum">    5503 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_73 = 4'h8;</span></a>
+<a name="5504"><span class="lineNum">    5504 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_74 = 4'h8;</span></a>
+<a name="5505"><span class="lineNum">    5505 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_75 = 4'h8;</span></a>
+<a name="5506"><span class="lineNum">    5506 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_76 = 4'h8;</span></a>
+<a name="5507"><span class="lineNum">    5507 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_77 = 4'h8;</span></a>
+<a name="5508"><span class="lineNum">    5508 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_78 = 4'h8;</span></a>
+<a name="5509"><span class="lineNum">    5509 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_79 = 4'h8;</span></a>
+<a name="5510"><span class="lineNum">    5510 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_80 = 4'h8;</span></a>
+<a name="5511"><span class="lineNum">    5511 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_81 = 4'h8;</span></a>
+<a name="5512"><span class="lineNum">    5512 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_82 = 4'h8;</span></a>
+<a name="5513"><span class="lineNum">    5513 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_83 = 4'h8;</span></a>
+<a name="5514"><span class="lineNum">    5514 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_84 = 4'h8;</span></a>
+<a name="5515"><span class="lineNum">    5515 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_85 = 4'h8;</span></a>
+<a name="5516"><span class="lineNum">    5516 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_86 = 4'h8;</span></a>
+<a name="5517"><span class="lineNum">    5517 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_87 = 4'h8;</span></a>
+<a name="5518"><span class="lineNum">    5518 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_88 = 4'h8;</span></a>
+<a name="5519"><span class="lineNum">    5519 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_89 = 4'h8;</span></a>
+<a name="5520"><span class="lineNum">    5520 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_90 = 4'h8;</span></a>
+<a name="5521"><span class="lineNum">    5521 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_91 = 4'h8;</span></a>
+<a name="5522"><span class="lineNum">    5522 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_92 = 4'h8;</span></a>
+<a name="5523"><span class="lineNum">    5523 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_93 = 4'h8;</span></a>
+<a name="5524"><span class="lineNum">    5524 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_94 = 4'h8;</span></a>
+<a name="5525"><span class="lineNum">    5525 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_95 = 4'h8;</span></a>
+<a name="5526"><span class="lineNum">    5526 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_96 = 4'h8;</span></a>
+<a name="5527"><span class="lineNum">    5527 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_97 = 4'h8;</span></a>
+<a name="5528"><span class="lineNum">    5528 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_98 = 4'h8;</span></a>
+<a name="5529"><span class="lineNum">    5529 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_99 = 4'h8;</span></a>
+<a name="5530"><span class="lineNum">    5530 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_100 = 4'h8;</span></a>
+<a name="5531"><span class="lineNum">    5531 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_101 = 4'h8;</span></a>
+<a name="5532"><span class="lineNum">    5532 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_102 = 4'h8;</span></a>
+<a name="5533"><span class="lineNum">    5533 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_103 = 4'h8;</span></a>
+<a name="5534"><span class="lineNum">    5534 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_104 = 4'h8;</span></a>
+<a name="5535"><span class="lineNum">    5535 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_105 = 4'h8;</span></a>
+<a name="5536"><span class="lineNum">    5536 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_106 = 4'h8;</span></a>
+<a name="5537"><span class="lineNum">    5537 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_107 = 4'h8;</span></a>
+<a name="5538"><span class="lineNum">    5538 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_108 = 4'h8;</span></a>
+<a name="5539"><span class="lineNum">    5539 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_109 = 4'h8;</span></a>
+<a name="5540"><span class="lineNum">    5540 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_110 = 4'h8;</span></a>
+<a name="5541"><span class="lineNum">    5541 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_111 = 4'h8;</span></a>
+<a name="5542"><span class="lineNum">    5542 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_112 = 4'h8;</span></a>
+<a name="5543"><span class="lineNum">    5543 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_113 = 4'h8;</span></a>
+<a name="5544"><span class="lineNum">    5544 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_114 = 4'h8;</span></a>
+<a name="5545"><span class="lineNum">    5545 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_115 = 4'h8;</span></a>
+<a name="5546"><span class="lineNum">    5546 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_116 = 4'h8;</span></a>
+<a name="5547"><span class="lineNum">    5547 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_117 = 4'h8;</span></a>
+<a name="5548"><span class="lineNum">    5548 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_118 = 4'h8;</span></a>
+<a name="5549"><span class="lineNum">    5549 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_119 = 4'h8;</span></a>
+<a name="5550"><span class="lineNum">    5550 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_120 = 4'h8;</span></a>
+<a name="5551"><span class="lineNum">    5551 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_121 = 4'h8;</span></a>
+<a name="5552"><span class="lineNum">    5552 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_122 = 4'h8;</span></a>
+<a name="5553"><span class="lineNum">    5553 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_123 = 4'h8;</span></a>
+<a name="5554"><span class="lineNum">    5554 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_124 = 4'h8;</span></a>
+<a name="5555"><span class="lineNum">    5555 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_125 = 4'h8;</span></a>
+<a name="5556"><span class="lineNum">    5556 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_126 = 4'h8;</span></a>
+<a name="5557"><span class="lineNum">    5557 </span><span class="lineCov">         12 :         useAltOnNaCtrs_1_127 = 4'h8;</span></a>
+<a name="5558"><span class="lineNum">    5558 </span><span class="lineCov">         12 :         allocLFSR_lfsr = 64'h1234567887654321;</span></a>
+<a name="5559"><span class="lineNum">    5559 </span><span class="lineCov">         12 :         allocLFSR_lfsr_1 = 64'h1234567887654321;</span></a>
+<a name="5560"><span class="lineNum">    5560 </span><span class="lineCov">         12 :         scThresholds_0_ctr = 5'h10;</span></a>
+<a name="5561"><span class="lineNum">    5561 </span><span class="lineCov">         12 :         scThresholds_0_thres = 8'h6;</span></a>
+<a name="5562"><span class="lineNum">    5562 </span><span class="lineCov">         12 :         scThresholds_1_ctr = 5'h10;</span></a>
+<a name="5563"><span class="lineNum">    5563 </span><span class="lineCov">         12 :         scThresholds_1_thres = 8'h6;</span></a>
+<a name="5564"><span class="lineNum">    5564 </span>            :       end</a>
+<a name="5565"><span class="lineNum">    5565 </span>            :     end // initial</a>
+<a name="5566"><span class="lineNum">    5566 </span>            :     `ifdef FIRRTL_AFTER_INITIAL</a>
+<a name="5567"><span class="lineNum">    5567 </span>            :       `FIRRTL_AFTER_INITIAL</a>
+<a name="5568"><span class="lineNum">    5568 </span>            :     `endif // FIRRTL_AFTER_INITIAL</a>
+<a name="5569"><span class="lineNum">    5569 </span>            :   `endif // ENABLE_INITIAL_REG_</a>
+<a name="5570"><span class="lineNum">    5570 </span>            :   DelayN_2 reset_vector_delay (</a>
+<a name="5571"><span class="lineNum">    5571 </span>            :     .clock  (clock),</a>
+<a name="5572"><span class="lineNum">    5572 </span>            :     .io_in  (io_reset_vector),</a>
+<a name="5573"><span class="lineNum">    5573 </span>            :     .io_out (_reset_vector_delay_io_out)</a>
+<a name="5574"><span class="lineNum">    5574 </span>            :   );</a>
+<a name="5575"><span class="lineNum">    5575 </span>            :   TageTable tables_0 (</a>
+<a name="5576"><span class="lineNum">    5576 </span>            :     .clock                                       (clock),</a>
+<a name="5577"><span class="lineNum">    5577 </span>            :     .reset                                       (reset),</a>
+<a name="5578"><span class="lineNum">    5578 </span>            :     .io_req_ready                                (_tables_0_io_req_ready),</a>
+<a name="5579"><span class="lineNum">    5579 </span>            :     .io_req_valid                                (io_s0_fire_1),</a>
+<a name="5580"><span class="lineNum">    5580 </span>            :     .io_req_bits_pc                              (io_in_bits_s0_pc_1),</a>
+<a name="5581"><span class="lineNum">    5581 </span>            :     .io_req_bits_folded_hist_hist_14_folded_hist</a>
+<a name="5582"><span class="lineNum">    5582 </span>            :       (io_in_bits_folded_hist_1_hist_14_folded_hist),</a>
+<a name="5583"><span class="lineNum">    5583 </span>            :     .io_req_bits_folded_hist_hist_7_folded_hist</a>
+<a name="5584"><span class="lineNum">    5584 </span>            :       (io_in_bits_folded_hist_1_hist_7_folded_hist),</a>
+<a name="5585"><span class="lineNum">    5585 </span>            :     .io_resps_0_valid                            (_tables_0_io_resps_0_valid),</a>
+<a name="5586"><span class="lineNum">    5586 </span>            :     .io_resps_0_bits_ctr                         (_tables_0_io_resps_0_bits_ctr),</a>
+<a name="5587"><span class="lineNum">    5587 </span>            :     .io_resps_0_bits_u                           (_tables_0_io_resps_0_bits_u),</a>
+<a name="5588"><span class="lineNum">    5588 </span>            :     .io_resps_0_bits_unconf                      (_tables_0_io_resps_0_bits_unconf),</a>
+<a name="5589"><span class="lineNum">    5589 </span>            :     .io_resps_1_valid                            (_tables_0_io_resps_1_valid),</a>
+<a name="5590"><span class="lineNum">    5590 </span>            :     .io_resps_1_bits_ctr                         (_tables_0_io_resps_1_bits_ctr),</a>
+<a name="5591"><span class="lineNum">    5591 </span>            :     .io_resps_1_bits_u                           (_tables_0_io_resps_1_bits_u),</a>
+<a name="5592"><span class="lineNum">    5592 </span>            :     .io_resps_1_bits_unconf                      (_tables_0_io_resps_1_bits_unconf),</a>
+<a name="5593"><span class="lineNum">    5593 </span>            :     .io_update_pc                                (tables_0_io_update_pc_r_1),</a>
+<a name="5594"><span class="lineNum">    5594 </span>            :     .io_update_folded_hist_hist_14_folded_hist</a>
+<a name="5595"><span class="lineNum">    5595 </span>            :       (tables_0_io_update_folded_hist_r_1_hist_14_folded_hist),</a>
+<a name="5596"><span class="lineNum">    5596 </span>            :     .io_update_folded_hist_hist_7_folded_hist</a>
+<a name="5597"><span class="lineNum">    5597 </span>            :       (tables_0_io_update_folded_hist_r_1_hist_7_folded_hist),</a>
+<a name="5598"><span class="lineNum">    5598 </span>            :     .io_update_mask_0                            (tables_0_io_update_mask_0_REG),</a>
+<a name="5599"><span class="lineNum">    5599 </span>            :     .io_update_mask_1                            (tables_0_io_update_mask_1_REG),</a>
+<a name="5600"><span class="lineNum">    5600 </span>            :     .io_update_takens_0                          (tables_0_io_update_takens_0_r),</a>
+<a name="5601"><span class="lineNum">    5601 </span>            :     .io_update_takens_1                          (tables_0_io_update_takens_1_r),</a>
+<a name="5602"><span class="lineNum">    5602 </span>            :     .io_update_alloc_0                           (tables_0_io_update_alloc_0_r),</a>
+<a name="5603"><span class="lineNum">    5603 </span>            :     .io_update_alloc_1                           (tables_0_io_update_alloc_1_r),</a>
+<a name="5604"><span class="lineNum">    5604 </span>            :     .io_update_oldCtrs_0                         (tables_0_io_update_oldCtrs_0_r),</a>
+<a name="5605"><span class="lineNum">    5605 </span>            :     .io_update_oldCtrs_1                         (tables_0_io_update_oldCtrs_1_r),</a>
+<a name="5606"><span class="lineNum">    5606 </span>            :     .io_update_uMask_0                           (tables_0_io_update_uMask_0_r),</a>
+<a name="5607"><span class="lineNum">    5607 </span>            :     .io_update_uMask_1                           (tables_0_io_update_uMask_1_r),</a>
+<a name="5608"><span class="lineNum">    5608 </span>            :     .io_update_us_0                              (tables_0_io_update_us_0_r),</a>
+<a name="5609"><span class="lineNum">    5609 </span>            :     .io_update_us_1                              (tables_0_io_update_us_1_r),</a>
+<a name="5610"><span class="lineNum">    5610 </span>            :     .io_update_reset_u_0                         (tables_0_io_update_reset_u_0_REG),</a>
+<a name="5611"><span class="lineNum">    5611 </span>            :     .io_update_reset_u_1                         (tables_0_io_update_reset_u_1_REG)</a>
+<a name="5612"><span class="lineNum">    5612 </span>            :   );</a>
+<a name="5613"><span class="lineNum">    5613 </span>            :   TageTable_1 tables_1 (</a>
+<a name="5614"><span class="lineNum">    5614 </span>            :     .clock                                       (clock),</a>
+<a name="5615"><span class="lineNum">    5615 </span>            :     .reset                                       (reset),</a>
+<a name="5616"><span class="lineNum">    5616 </span>            :     .io_req_ready                                (_tables_1_io_req_ready),</a>
+<a name="5617"><span class="lineNum">    5617 </span>            :     .io_req_valid                                (io_s0_fire_1),</a>
+<a name="5618"><span class="lineNum">    5618 </span>            :     .io_req_bits_pc                              (io_in_bits_s0_pc_1),</a>
+<a name="5619"><span class="lineNum">    5619 </span>            :     .io_req_bits_folded_hist_hist_15_folded_hist</a>
+<a name="5620"><span class="lineNum">    5620 </span>            :       (io_in_bits_folded_hist_1_hist_15_folded_hist),</a>
+<a name="5621"><span class="lineNum">    5621 </span>            :     .io_req_bits_folded_hist_hist_4_folded_hist</a>
+<a name="5622"><span class="lineNum">    5622 </span>            :       (io_in_bits_folded_hist_1_hist_4_folded_hist),</a>
+<a name="5623"><span class="lineNum">    5623 </span>            :     .io_req_bits_folded_hist_hist_1_folded_hist</a>
+<a name="5624"><span class="lineNum">    5624 </span>            :       (io_in_bits_folded_hist_1_hist_1_folded_hist),</a>
+<a name="5625"><span class="lineNum">    5625 </span>            :     .io_resps_0_valid                            (_tables_1_io_resps_0_valid),</a>
+<a name="5626"><span class="lineNum">    5626 </span>            :     .io_resps_0_bits_ctr                         (_tables_1_io_resps_0_bits_ctr),</a>
+<a name="5627"><span class="lineNum">    5627 </span>            :     .io_resps_0_bits_u                           (_tables_1_io_resps_0_bits_u),</a>
+<a name="5628"><span class="lineNum">    5628 </span>            :     .io_resps_0_bits_unconf                      (_tables_1_io_resps_0_bits_unconf),</a>
+<a name="5629"><span class="lineNum">    5629 </span>            :     .io_resps_1_valid                            (_tables_1_io_resps_1_valid),</a>
+<a name="5630"><span class="lineNum">    5630 </span>            :     .io_resps_1_bits_ctr                         (_tables_1_io_resps_1_bits_ctr),</a>
+<a name="5631"><span class="lineNum">    5631 </span>            :     .io_resps_1_bits_u                           (_tables_1_io_resps_1_bits_u),</a>
+<a name="5632"><span class="lineNum">    5632 </span>            :     .io_resps_1_bits_unconf                      (_tables_1_io_resps_1_bits_unconf),</a>
+<a name="5633"><span class="lineNum">    5633 </span>            :     .io_update_pc                                (tables_1_io_update_pc_r_1),</a>
+<a name="5634"><span class="lineNum">    5634 </span>            :     .io_update_folded_hist_hist_15_folded_hist</a>
+<a name="5635"><span class="lineNum">    5635 </span>            :       (tables_1_io_update_folded_hist_r_1_hist_15_folded_hist),</a>
+<a name="5636"><span class="lineNum">    5636 </span>            :     .io_update_folded_hist_hist_4_folded_hist</a>
+<a name="5637"><span class="lineNum">    5637 </span>            :       (tables_1_io_update_folded_hist_r_1_hist_4_folded_hist),</a>
+<a name="5638"><span class="lineNum">    5638 </span>            :     .io_update_folded_hist_hist_1_folded_hist</a>
+<a name="5639"><span class="lineNum">    5639 </span>            :       (tables_1_io_update_folded_hist_r_1_hist_1_folded_hist),</a>
+<a name="5640"><span class="lineNum">    5640 </span>            :     .io_update_mask_0                            (tables_1_io_update_mask_0_REG),</a>
+<a name="5641"><span class="lineNum">    5641 </span>            :     .io_update_mask_1                            (tables_1_io_update_mask_1_REG),</a>
+<a name="5642"><span class="lineNum">    5642 </span>            :     .io_update_takens_0                          (tables_1_io_update_takens_0_r),</a>
+<a name="5643"><span class="lineNum">    5643 </span>            :     .io_update_takens_1                          (tables_1_io_update_takens_1_r),</a>
+<a name="5644"><span class="lineNum">    5644 </span>            :     .io_update_alloc_0                           (tables_1_io_update_alloc_0_r),</a>
+<a name="5645"><span class="lineNum">    5645 </span>            :     .io_update_alloc_1                           (tables_1_io_update_alloc_1_r),</a>
+<a name="5646"><span class="lineNum">    5646 </span>            :     .io_update_oldCtrs_0                         (tables_1_io_update_oldCtrs_0_r),</a>
+<a name="5647"><span class="lineNum">    5647 </span>            :     .io_update_oldCtrs_1                         (tables_1_io_update_oldCtrs_1_r),</a>
+<a name="5648"><span class="lineNum">    5648 </span>            :     .io_update_uMask_0                           (tables_1_io_update_uMask_0_r),</a>
+<a name="5649"><span class="lineNum">    5649 </span>            :     .io_update_uMask_1                           (tables_1_io_update_uMask_1_r),</a>
+<a name="5650"><span class="lineNum">    5650 </span>            :     .io_update_us_0                              (tables_1_io_update_us_0_r),</a>
+<a name="5651"><span class="lineNum">    5651 </span>            :     .io_update_us_1                              (tables_1_io_update_us_1_r),</a>
+<a name="5652"><span class="lineNum">    5652 </span>            :     .io_update_reset_u_0                         (tables_1_io_update_reset_u_0_REG),</a>
+<a name="5653"><span class="lineNum">    5653 </span>            :     .io_update_reset_u_1                         (tables_1_io_update_reset_u_1_REG)</a>
+<a name="5654"><span class="lineNum">    5654 </span>            :   );</a>
+<a name="5655"><span class="lineNum">    5655 </span>            :   TageTable_2 tables_2 (</a>
+<a name="5656"><span class="lineNum">    5656 </span>            :     .clock                                       (clock),</a>
+<a name="5657"><span class="lineNum">    5657 </span>            :     .reset                                       (reset),</a>
+<a name="5658"><span class="lineNum">    5658 </span>            :     .io_req_ready                                (_tables_2_io_req_ready),</a>
+<a name="5659"><span class="lineNum">    5659 </span>            :     .io_req_valid                                (io_s0_fire_1),</a>
+<a name="5660"><span class="lineNum">    5660 </span>            :     .io_req_bits_pc                              (io_in_bits_s0_pc_1),</a>
+<a name="5661"><span class="lineNum">    5661 </span>            :     .io_req_bits_folded_hist_hist_17_folded_hist</a>
+<a name="5662"><span class="lineNum">    5662 </span>            :       (io_in_bits_folded_hist_1_hist_17_folded_hist),</a>
+<a name="5663"><span class="lineNum">    5663 </span>            :     .io_req_bits_folded_hist_hist_9_folded_hist</a>
+<a name="5664"><span class="lineNum">    5664 </span>            :       (io_in_bits_folded_hist_1_hist_9_folded_hist),</a>
+<a name="5665"><span class="lineNum">    5665 </span>            :     .io_req_bits_folded_hist_hist_3_folded_hist</a>
+<a name="5666"><span class="lineNum">    5666 </span>            :       (io_in_bits_folded_hist_1_hist_3_folded_hist),</a>
+<a name="5667"><span class="lineNum">    5667 </span>            :     .io_resps_0_valid                            (_tables_2_io_resps_0_valid),</a>
+<a name="5668"><span class="lineNum">    5668 </span>            :     .io_resps_0_bits_ctr                         (_tables_2_io_resps_0_bits_ctr),</a>
+<a name="5669"><span class="lineNum">    5669 </span>            :     .io_resps_0_bits_u                           (_tables_2_io_resps_0_bits_u),</a>
+<a name="5670"><span class="lineNum">    5670 </span>            :     .io_resps_0_bits_unconf                      (_tables_2_io_resps_0_bits_unconf),</a>
+<a name="5671"><span class="lineNum">    5671 </span>            :     .io_resps_1_valid                            (_tables_2_io_resps_1_valid),</a>
+<a name="5672"><span class="lineNum">    5672 </span>            :     .io_resps_1_bits_ctr                         (_tables_2_io_resps_1_bits_ctr),</a>
+<a name="5673"><span class="lineNum">    5673 </span>            :     .io_resps_1_bits_u                           (_tables_2_io_resps_1_bits_u),</a>
+<a name="5674"><span class="lineNum">    5674 </span>            :     .io_resps_1_bits_unconf                      (_tables_2_io_resps_1_bits_unconf),</a>
+<a name="5675"><span class="lineNum">    5675 </span>            :     .io_update_pc                                (tables_2_io_update_pc_r_1),</a>
+<a name="5676"><span class="lineNum">    5676 </span>            :     .io_update_folded_hist_hist_17_folded_hist</a>
+<a name="5677"><span class="lineNum">    5677 </span>            :       (tables_2_io_update_folded_hist_r_1_hist_17_folded_hist),</a>
+<a name="5678"><span class="lineNum">    5678 </span>            :     .io_update_folded_hist_hist_9_folded_hist</a>
+<a name="5679"><span class="lineNum">    5679 </span>            :       (tables_2_io_update_folded_hist_r_1_hist_9_folded_hist),</a>
+<a name="5680"><span class="lineNum">    5680 </span>            :     .io_update_folded_hist_hist_3_folded_hist</a>
+<a name="5681"><span class="lineNum">    5681 </span>            :       (tables_2_io_update_folded_hist_r_1_hist_3_folded_hist),</a>
+<a name="5682"><span class="lineNum">    5682 </span>            :     .io_update_mask_0                            (tables_2_io_update_mask_0_REG),</a>
+<a name="5683"><span class="lineNum">    5683 </span>            :     .io_update_mask_1                            (tables_2_io_update_mask_1_REG),</a>
+<a name="5684"><span class="lineNum">    5684 </span>            :     .io_update_takens_0                          (tables_2_io_update_takens_0_r),</a>
+<a name="5685"><span class="lineNum">    5685 </span>            :     .io_update_takens_1                          (tables_2_io_update_takens_1_r),</a>
+<a name="5686"><span class="lineNum">    5686 </span>            :     .io_update_alloc_0                           (tables_2_io_update_alloc_0_r),</a>
+<a name="5687"><span class="lineNum">    5687 </span>            :     .io_update_alloc_1                           (tables_2_io_update_alloc_1_r),</a>
+<a name="5688"><span class="lineNum">    5688 </span>            :     .io_update_oldCtrs_0                         (tables_2_io_update_oldCtrs_0_r),</a>
+<a name="5689"><span class="lineNum">    5689 </span>            :     .io_update_oldCtrs_1                         (tables_2_io_update_oldCtrs_1_r),</a>
+<a name="5690"><span class="lineNum">    5690 </span>            :     .io_update_uMask_0                           (tables_2_io_update_uMask_0_r),</a>
+<a name="5691"><span class="lineNum">    5691 </span>            :     .io_update_uMask_1                           (tables_2_io_update_uMask_1_r),</a>
+<a name="5692"><span class="lineNum">    5692 </span>            :     .io_update_us_0                              (tables_2_io_update_us_0_r),</a>
+<a name="5693"><span class="lineNum">    5693 </span>            :     .io_update_us_1                              (tables_2_io_update_us_1_r),</a>
+<a name="5694"><span class="lineNum">    5694 </span>            :     .io_update_reset_u_0                         (tables_2_io_update_reset_u_0_REG),</a>
+<a name="5695"><span class="lineNum">    5695 </span>            :     .io_update_reset_u_1                         (tables_2_io_update_reset_u_1_REG)</a>
+<a name="5696"><span class="lineNum">    5696 </span>            :   );</a>
+<a name="5697"><span class="lineNum">    5697 </span>            :   TageTable_3 tables_3 (</a>
+<a name="5698"><span class="lineNum">    5698 </span>            :     .clock                                       (clock),</a>
+<a name="5699"><span class="lineNum">    5699 </span>            :     .reset                                       (reset),</a>
+<a name="5700"><span class="lineNum">    5700 </span>            :     .io_req_ready                                (_tables_3_io_req_ready),</a>
+<a name="5701"><span class="lineNum">    5701 </span>            :     .io_req_valid                                (io_s0_fire_1),</a>
+<a name="5702"><span class="lineNum">    5702 </span>            :     .io_req_bits_pc                              (io_in_bits_s0_pc_1),</a>
+<a name="5703"><span class="lineNum">    5703 </span>            :     .io_req_bits_folded_hist_hist_16_folded_hist</a>
+<a name="5704"><span class="lineNum">    5704 </span>            :       (io_in_bits_folded_hist_1_hist_16_folded_hist),</a>
+<a name="5705"><span class="lineNum">    5705 </span>            :     .io_req_bits_folded_hist_hist_8_folded_hist</a>
+<a name="5706"><span class="lineNum">    5706 </span>            :       (io_in_bits_folded_hist_1_hist_8_folded_hist),</a>
+<a name="5707"><span class="lineNum">    5707 </span>            :     .io_req_bits_folded_hist_hist_5_folded_hist</a>
+<a name="5708"><span class="lineNum">    5708 </span>            :       (io_in_bits_folded_hist_1_hist_5_folded_hist),</a>
+<a name="5709"><span class="lineNum">    5709 </span>            :     .io_resps_0_valid                            (_tables_3_io_resps_0_valid),</a>
+<a name="5710"><span class="lineNum">    5710 </span>            :     .io_resps_0_bits_ctr                         (_tables_3_io_resps_0_bits_ctr),</a>
+<a name="5711"><span class="lineNum">    5711 </span>            :     .io_resps_0_bits_u                           (_tables_3_io_resps_0_bits_u),</a>
+<a name="5712"><span class="lineNum">    5712 </span>            :     .io_resps_0_bits_unconf                      (_tables_3_io_resps_0_bits_unconf),</a>
+<a name="5713"><span class="lineNum">    5713 </span>            :     .io_resps_1_valid                            (_tables_3_io_resps_1_valid),</a>
+<a name="5714"><span class="lineNum">    5714 </span>            :     .io_resps_1_bits_ctr                         (_tables_3_io_resps_1_bits_ctr),</a>
+<a name="5715"><span class="lineNum">    5715 </span>            :     .io_resps_1_bits_u                           (_tables_3_io_resps_1_bits_u),</a>
+<a name="5716"><span class="lineNum">    5716 </span>            :     .io_resps_1_bits_unconf                      (_tables_3_io_resps_1_bits_unconf),</a>
+<a name="5717"><span class="lineNum">    5717 </span>            :     .io_update_pc                                (tables_3_io_update_pc_r_1),</a>
+<a name="5718"><span class="lineNum">    5718 </span>            :     .io_update_folded_hist_hist_16_folded_hist</a>
+<a name="5719"><span class="lineNum">    5719 </span>            :       (tables_3_io_update_folded_hist_r_1_hist_16_folded_hist),</a>
+<a name="5720"><span class="lineNum">    5720 </span>            :     .io_update_folded_hist_hist_8_folded_hist</a>
+<a name="5721"><span class="lineNum">    5721 </span>            :       (tables_3_io_update_folded_hist_r_1_hist_8_folded_hist),</a>
+<a name="5722"><span class="lineNum">    5722 </span>            :     .io_update_folded_hist_hist_5_folded_hist</a>
+<a name="5723"><span class="lineNum">    5723 </span>            :       (tables_3_io_update_folded_hist_r_1_hist_5_folded_hist),</a>
+<a name="5724"><span class="lineNum">    5724 </span>            :     .io_update_mask_0                            (tables_3_io_update_mask_0_REG),</a>
+<a name="5725"><span class="lineNum">    5725 </span>            :     .io_update_mask_1                            (tables_3_io_update_mask_1_REG),</a>
+<a name="5726"><span class="lineNum">    5726 </span>            :     .io_update_takens_0                          (tables_3_io_update_takens_0_r),</a>
+<a name="5727"><span class="lineNum">    5727 </span>            :     .io_update_takens_1                          (tables_3_io_update_takens_1_r),</a>
+<a name="5728"><span class="lineNum">    5728 </span>            :     .io_update_alloc_0                           (tables_3_io_update_alloc_0_r),</a>
+<a name="5729"><span class="lineNum">    5729 </span>            :     .io_update_alloc_1                           (tables_3_io_update_alloc_1_r),</a>
+<a name="5730"><span class="lineNum">    5730 </span>            :     .io_update_oldCtrs_0                         (tables_3_io_update_oldCtrs_0_r),</a>
+<a name="5731"><span class="lineNum">    5731 </span>            :     .io_update_oldCtrs_1                         (tables_3_io_update_oldCtrs_1_r),</a>
+<a name="5732"><span class="lineNum">    5732 </span>            :     .io_update_uMask_0                           (tables_3_io_update_uMask_0_r),</a>
+<a name="5733"><span class="lineNum">    5733 </span>            :     .io_update_uMask_1                           (tables_3_io_update_uMask_1_r),</a>
+<a name="5734"><span class="lineNum">    5734 </span>            :     .io_update_us_0                              (tables_3_io_update_us_0_r),</a>
+<a name="5735"><span class="lineNum">    5735 </span>            :     .io_update_us_1                              (tables_3_io_update_us_1_r),</a>
+<a name="5736"><span class="lineNum">    5736 </span>            :     .io_update_reset_u_0                         (tables_3_io_update_reset_u_0_REG),</a>
+<a name="5737"><span class="lineNum">    5737 </span>            :     .io_update_reset_u_1                         (tables_3_io_update_reset_u_1_REG)</a>
+<a name="5738"><span class="lineNum">    5738 </span>            :   );</a>
+<a name="5739"><span class="lineNum">    5739 </span>            :   TageBTable bt (</a>
+<a name="5740"><span class="lineNum">    5740 </span>            :     .clock              (clock),</a>
+<a name="5741"><span class="lineNum">    5741 </span>            :     .reset              (reset),</a>
+<a name="5742"><span class="lineNum">    5742 </span>            :     .io_req_ready       (_bt_io_req_ready),</a>
+<a name="5743"><span class="lineNum">    5743 </span>            :     .io_req_valid       (io_s0_fire_1),</a>
+<a name="5744"><span class="lineNum">    5744 </span>            :     .io_req_bits        (io_in_bits_s0_pc_1),</a>
+<a name="5745"><span class="lineNum">    5745 </span>            :     .io_s1_cnt_0        (_bt_io_s1_cnt_0),</a>
+<a name="5746"><span class="lineNum">    5746 </span>            :     .io_s1_cnt_1        (_bt_io_s1_cnt_1),</a>
+<a name="5747"><span class="lineNum">    5747 </span>            :     .io_update_mask_0   (REG_2_0),</a>
+<a name="5748"><span class="lineNum">    5748 </span>            :     .io_update_mask_1   (REG_2_1),</a>
+<a name="5749"><span class="lineNum">    5749 </span>            :     .io_update_pc       (bt_io_update_pc_r),</a>
+<a name="5750"><span class="lineNum">    5750 </span>            :     .io_update_cnt_0    (r_0),</a>
+<a name="5751"><span class="lineNum">    5751 </span>            :     .io_update_cnt_1    (r_1),</a>
+<a name="5752"><span class="lineNum">    5752 </span>            :     .io_update_takens_0 (r_1_0),</a>
+<a name="5753"><span class="lineNum">    5753 </span>            :     .io_update_takens_1 (r_1_1)</a>
+<a name="5754"><span class="lineNum">    5754 </span>            :   );</a>
+<a name="5755"><span class="lineNum">    5755 </span>            :   SCTable scTables_0 (</a>
+<a name="5756"><span class="lineNum">    5756 </span>            :     .clock                 (clock),</a>
+<a name="5757"><span class="lineNum">    5757 </span>            :     .reset                 (reset),</a>
+<a name="5758"><span class="lineNum">    5758 </span>            :     .io_req_valid          (io_s0_fire_3),</a>
+<a name="5759"><span class="lineNum">    5759 </span>            :     .io_req_bits_pc        (io_in_bits_s0_pc_3),</a>
+<a name="5760"><span class="lineNum">    5760 </span>            :     .io_resp_ctrs_0_0      (_scTables_0_io_resp_ctrs_0_0),</a>
+<a name="5761"><span class="lineNum">    5761 </span>            :     .io_resp_ctrs_0_1      (_scTables_0_io_resp_ctrs_0_1),</a>
+<a name="5762"><span class="lineNum">    5762 </span>            :     .io_resp_ctrs_1_0      (_scTables_0_io_resp_ctrs_1_0),</a>
+<a name="5763"><span class="lineNum">    5763 </span>            :     .io_resp_ctrs_1_1      (_scTables_0_io_resp_ctrs_1_1),</a>
+<a name="5764"><span class="lineNum">    5764 </span>            :     .io_update_pc          (scTables_0_io_update_pc_r_1),</a>
+<a name="5765"><span class="lineNum">    5765 </span>            :     .io_update_mask_0      (scTables_0_io_update_mask_0_REG),</a>
+<a name="5766"><span class="lineNum">    5766 </span>            :     .io_update_mask_1      (scTables_0_io_update_mask_1_REG),</a>
+<a name="5767"><span class="lineNum">    5767 </span>            :     .io_update_oldCtrs_0   (scTables_0_io_update_oldCtrs_0_r),</a>
+<a name="5768"><span class="lineNum">    5768 </span>            :     .io_update_oldCtrs_1   (scTables_0_io_update_oldCtrs_1_r),</a>
+<a name="5769"><span class="lineNum">    5769 </span>            :     .io_update_tagePreds_0 (scTables_0_io_update_tagePreds_0_r),</a>
+<a name="5770"><span class="lineNum">    5770 </span>            :     .io_update_tagePreds_1 (scTables_0_io_update_tagePreds_1_r),</a>
+<a name="5771"><span class="lineNum">    5771 </span>            :     .io_update_takens_0    (scTables_0_io_update_takens_0_r),</a>
+<a name="5772"><span class="lineNum">    5772 </span>            :     .io_update_takens_1    (scTables_0_io_update_takens_1_r)</a>
+<a name="5773"><span class="lineNum">    5773 </span>            :   );</a>
+<a name="5774"><span class="lineNum">    5774 </span>            :   SCTable_1 scTables_1 (</a>
+<a name="5775"><span class="lineNum">    5775 </span>            :     .clock                                       (clock),</a>
+<a name="5776"><span class="lineNum">    5776 </span>            :     .reset                                       (reset),</a>
+<a name="5777"><span class="lineNum">    5777 </span>            :     .io_req_valid                                (io_s0_fire_3),</a>
+<a name="5778"><span class="lineNum">    5778 </span>            :     .io_req_bits_pc                              (io_in_bits_s0_pc_3),</a>
+<a name="5779"><span class="lineNum">    5779 </span>            :     .io_req_bits_folded_hist_hist_12_folded_hist</a>
+<a name="5780"><span class="lineNum">    5780 </span>            :       (io_in_bits_folded_hist_3_hist_12_folded_hist),</a>
+<a name="5781"><span class="lineNum">    5781 </span>            :     .io_resp_ctrs_0_0                            (_scTables_1_io_resp_ctrs_0_0),</a>
+<a name="5782"><span class="lineNum">    5782 </span>            :     .io_resp_ctrs_0_1                            (_scTables_1_io_resp_ctrs_0_1),</a>
+<a name="5783"><span class="lineNum">    5783 </span>            :     .io_resp_ctrs_1_0                            (_scTables_1_io_resp_ctrs_1_0),</a>
+<a name="5784"><span class="lineNum">    5784 </span>            :     .io_resp_ctrs_1_1                            (_scTables_1_io_resp_ctrs_1_1),</a>
+<a name="5785"><span class="lineNum">    5785 </span>            :     .io_update_pc                                (scTables_1_io_update_pc_r_1),</a>
+<a name="5786"><span class="lineNum">    5786 </span>            :     .io_update_folded_hist_hist_12_folded_hist</a>
+<a name="5787"><span class="lineNum">    5787 </span>            :       (scTables_1_io_update_folded_hist_r_1_hist_12_folded_hist),</a>
+<a name="5788"><span class="lineNum">    5788 </span>            :     .io_update_mask_0                            (scTables_1_io_update_mask_0_REG),</a>
+<a name="5789"><span class="lineNum">    5789 </span>            :     .io_update_mask_1                            (scTables_1_io_update_mask_1_REG),</a>
+<a name="5790"><span class="lineNum">    5790 </span>            :     .io_update_oldCtrs_0                         (scTables_1_io_update_oldCtrs_0_r),</a>
+<a name="5791"><span class="lineNum">    5791 </span>            :     .io_update_oldCtrs_1                         (scTables_1_io_update_oldCtrs_1_r),</a>
+<a name="5792"><span class="lineNum">    5792 </span>            :     .io_update_tagePreds_0                       (scTables_1_io_update_tagePreds_0_r),</a>
+<a name="5793"><span class="lineNum">    5793 </span>            :     .io_update_tagePreds_1                       (scTables_1_io_update_tagePreds_1_r),</a>
+<a name="5794"><span class="lineNum">    5794 </span>            :     .io_update_takens_0                          (scTables_1_io_update_takens_0_r),</a>
+<a name="5795"><span class="lineNum">    5795 </span>            :     .io_update_takens_1                          (scTables_1_io_update_takens_1_r)</a>
+<a name="5796"><span class="lineNum">    5796 </span>            :   );</a>
+<a name="5797"><span class="lineNum">    5797 </span>            :   SCTable_2 scTables_2 (</a>
+<a name="5798"><span class="lineNum">    5798 </span>            :     .clock                                       (clock),</a>
+<a name="5799"><span class="lineNum">    5799 </span>            :     .reset                                       (reset),</a>
+<a name="5800"><span class="lineNum">    5800 </span>            :     .io_req_valid                                (io_s0_fire_3),</a>
+<a name="5801"><span class="lineNum">    5801 </span>            :     .io_req_bits_pc                              (io_in_bits_s0_pc_3),</a>
+<a name="5802"><span class="lineNum">    5802 </span>            :     .io_req_bits_folded_hist_hist_11_folded_hist</a>
+<a name="5803"><span class="lineNum">    5803 </span>            :       (io_in_bits_folded_hist_3_hist_11_folded_hist),</a>
+<a name="5804"><span class="lineNum">    5804 </span>            :     .io_resp_ctrs_0_0                            (_scTables_2_io_resp_ctrs_0_0),</a>
+<a name="5805"><span class="lineNum">    5805 </span>            :     .io_resp_ctrs_0_1                            (_scTables_2_io_resp_ctrs_0_1),</a>
+<a name="5806"><span class="lineNum">    5806 </span>            :     .io_resp_ctrs_1_0                            (_scTables_2_io_resp_ctrs_1_0),</a>
+<a name="5807"><span class="lineNum">    5807 </span>            :     .io_resp_ctrs_1_1                            (_scTables_2_io_resp_ctrs_1_1),</a>
+<a name="5808"><span class="lineNum">    5808 </span>            :     .io_update_pc                                (scTables_2_io_update_pc_r_1),</a>
+<a name="5809"><span class="lineNum">    5809 </span>            :     .io_update_folded_hist_hist_11_folded_hist</a>
+<a name="5810"><span class="lineNum">    5810 </span>            :       (scTables_2_io_update_folded_hist_r_1_hist_11_folded_hist),</a>
+<a name="5811"><span class="lineNum">    5811 </span>            :     .io_update_mask_0                            (scTables_2_io_update_mask_0_REG),</a>
+<a name="5812"><span class="lineNum">    5812 </span>            :     .io_update_mask_1                            (scTables_2_io_update_mask_1_REG),</a>
+<a name="5813"><span class="lineNum">    5813 </span>            :     .io_update_oldCtrs_0                         (scTables_2_io_update_oldCtrs_0_r),</a>
+<a name="5814"><span class="lineNum">    5814 </span>            :     .io_update_oldCtrs_1                         (scTables_2_io_update_oldCtrs_1_r),</a>
+<a name="5815"><span class="lineNum">    5815 </span>            :     .io_update_tagePreds_0                       (scTables_2_io_update_tagePreds_0_r),</a>
+<a name="5816"><span class="lineNum">    5816 </span>            :     .io_update_tagePreds_1                       (scTables_2_io_update_tagePreds_1_r),</a>
+<a name="5817"><span class="lineNum">    5817 </span>            :     .io_update_takens_0                          (scTables_2_io_update_takens_0_r),</a>
+<a name="5818"><span class="lineNum">    5818 </span>            :     .io_update_takens_1                          (scTables_2_io_update_takens_1_r)</a>
+<a name="5819"><span class="lineNum">    5819 </span>            :   );</a>
+<a name="5820"><span class="lineNum">    5820 </span>            :   SCTable_3 scTables_3 (</a>
+<a name="5821"><span class="lineNum">    5821 </span>            :     .clock                                      (clock),</a>
+<a name="5822"><span class="lineNum">    5822 </span>            :     .reset                                      (reset),</a>
+<a name="5823"><span class="lineNum">    5823 </span>            :     .io_req_valid                               (io_s0_fire_3),</a>
+<a name="5824"><span class="lineNum">    5824 </span>            :     .io_req_bits_pc                             (io_in_bits_s0_pc_3),</a>
+<a name="5825"><span class="lineNum">    5825 </span>            :     .io_req_bits_folded_hist_hist_2_folded_hist</a>
+<a name="5826"><span class="lineNum">    5826 </span>            :       (io_in_bits_folded_hist_3_hist_2_folded_hist),</a>
+<a name="5827"><span class="lineNum">    5827 </span>            :     .io_resp_ctrs_0_0                           (_scTables_3_io_resp_ctrs_0_0),</a>
+<a name="5828"><span class="lineNum">    5828 </span>            :     .io_resp_ctrs_0_1                           (_scTables_3_io_resp_ctrs_0_1),</a>
+<a name="5829"><span class="lineNum">    5829 </span>            :     .io_resp_ctrs_1_0                           (_scTables_3_io_resp_ctrs_1_0),</a>
+<a name="5830"><span class="lineNum">    5830 </span>            :     .io_resp_ctrs_1_1                           (_scTables_3_io_resp_ctrs_1_1),</a>
+<a name="5831"><span class="lineNum">    5831 </span>            :     .io_update_pc                               (scTables_3_io_update_pc_r_1),</a>
+<a name="5832"><span class="lineNum">    5832 </span>            :     .io_update_folded_hist_hist_2_folded_hist</a>
+<a name="5833"><span class="lineNum">    5833 </span>            :       (scTables_3_io_update_folded_hist_r_1_hist_2_folded_hist),</a>
+<a name="5834"><span class="lineNum">    5834 </span>            :     .io_update_mask_0                           (scTables_3_io_update_mask_0_REG),</a>
+<a name="5835"><span class="lineNum">    5835 </span>            :     .io_update_mask_1                           (scTables_3_io_update_mask_1_REG),</a>
+<a name="5836"><span class="lineNum">    5836 </span>            :     .io_update_oldCtrs_0                        (scTables_3_io_update_oldCtrs_0_r),</a>
+<a name="5837"><span class="lineNum">    5837 </span>            :     .io_update_oldCtrs_1                        (scTables_3_io_update_oldCtrs_1_r),</a>
+<a name="5838"><span class="lineNum">    5838 </span>            :     .io_update_tagePreds_0                      (scTables_3_io_update_tagePreds_0_r),</a>
+<a name="5839"><span class="lineNum">    5839 </span>            :     .io_update_tagePreds_1                      (scTables_3_io_update_tagePreds_1_r),</a>
+<a name="5840"><span class="lineNum">    5840 </span>            :     .io_update_takens_0                         (scTables_3_io_update_takens_0_r),</a>
+<a name="5841"><span class="lineNum">    5841 </span>            :     .io_update_takens_1                         (scTables_3_io_update_takens_1_r)</a>
+<a name="5842"><span class="lineNum">    5842 </span>            :   );</a>
+<a name="5843"><span class="lineNum">    5843 </span>            :   assign io_out_s2_full_pred_0_br_taken_mask_0 =</a>
+<a name="5844"><span class="lineNum">    5844 </span>            :     tage_enable_dup_REG &amp; s2_tageTakens_dup_0_0;</a>
+<a name="5845"><span class="lineNum">    5845 </span>            :   assign io_out_s2_full_pred_0_br_taken_mask_1 =</a>
+<a name="5846"><span class="lineNum">    5846 </span>            :     tage_enable_dup_REG_1 &amp; s2_tageTakens_dup_0_1;</a>
+<a name="5847"><span class="lineNum">    5847 </span>            :   assign io_out_s2_full_pred_1_br_taken_mask_0 =</a>
+<a name="5848"><span class="lineNum">    5848 </span>            :     tage_enable_dup_REG &amp; s2_tageTakens_dup_1_0;</a>
+<a name="5849"><span class="lineNum">    5849 </span>            :   assign io_out_s2_full_pred_1_br_taken_mask_1 =</a>
+<a name="5850"><span class="lineNum">    5850 </span>            :     tage_enable_dup_REG_1 &amp; s2_tageTakens_dup_1_1;</a>
+<a name="5851"><span class="lineNum">    5851 </span>            :   assign io_out_s2_full_pred_2_br_taken_mask_0 =</a>
+<a name="5852"><span class="lineNum">    5852 </span>            :     tage_enable_dup_REG &amp; s2_tageTakens_dup_2_0;</a>
+<a name="5853"><span class="lineNum">    5853 </span>            :   assign io_out_s2_full_pred_2_br_taken_mask_1 =</a>
+<a name="5854"><span class="lineNum">    5854 </span>            :     tage_enable_dup_REG_1 &amp; s2_tageTakens_dup_2_1;</a>
+<a name="5855"><span class="lineNum">    5855 </span>            :   assign io_out_s2_full_pred_3_br_taken_mask_0 =</a>
+<a name="5856"><span class="lineNum">    5856 </span>            :     tage_enable_dup_REG &amp; s2_tageTakens_dup_3_0;</a>
+<a name="5857"><span class="lineNum">    5857 </span>            :   assign io_out_s2_full_pred_3_br_taken_mask_1 =</a>
+<a name="5858"><span class="lineNum">    5858 </span>            :     tage_enable_dup_REG_1 &amp; s2_tageTakens_dup_3_1;</a>
+<a name="5859"><span class="lineNum">    5859 </span>            :   assign io_out_s3_full_pred_0_br_taken_mask_0 = sc_enable_dup_REG &amp; s3_pred_dup_0;</a>
+<a name="5860"><span class="lineNum">    5860 </span>            :   assign io_out_s3_full_pred_0_br_taken_mask_1 = sc_enable_dup_REG_1 &amp; s3_pred_dup_0_1;</a>
+<a name="5861"><span class="lineNum">    5861 </span>            :   assign io_out_s3_full_pred_1_br_taken_mask_0 = sc_enable_dup_REG &amp; s3_pred_dup_1;</a>
+<a name="5862"><span class="lineNum">    5862 </span>            :   assign io_out_s3_full_pred_1_br_taken_mask_1 = sc_enable_dup_REG_1 &amp; s3_pred_dup_1_1;</a>
+<a name="5863"><span class="lineNum">    5863 </span>            :   assign io_out_s3_full_pred_2_br_taken_mask_0 = sc_enable_dup_REG &amp; s3_pred_dup_2;</a>
+<a name="5864"><span class="lineNum">    5864 </span>            :   assign io_out_s3_full_pred_2_br_taken_mask_1 = sc_enable_dup_REG_1 &amp; s3_pred_dup_2_1;</a>
+<a name="5865"><span class="lineNum">    5865 </span>            :   assign io_out_s3_full_pred_3_br_taken_mask_0 = sc_enable_dup_REG &amp; s3_pred_dup_3;</a>
+<a name="5866"><span class="lineNum">    5866 </span>            :   assign io_out_s3_full_pred_3_br_taken_mask_1 = sc_enable_dup_REG_1 &amp; s3_pred_dup_3_1;</a>
+<a name="5867"><span class="lineNum">    5867 </span>            :   assign io_out_last_stage_meta =</a>
+<a name="5868"><span class="lineNum">    5868 </span>            :     {135'h0,</a>
+<a name="5869"><span class="lineNum">    5869 </span>            :      resp_meta_providers_1_valid_r,</a>
+<a name="5870"><span class="lineNum">    5870 </span>            :      resp_meta_providers_1_bits_r,</a>
+<a name="5871"><span class="lineNum">    5871 </span>            :      resp_meta_providers_0_valid_r,</a>
+<a name="5872"><span class="lineNum">    5872 </span>            :      resp_meta_providers_0_bits_r,</a>
+<a name="5873"><span class="lineNum">    5873 </span>            :      resp_meta_providerResps_1_r_ctr,</a>
+<a name="5874"><span class="lineNum">    5874 </span>            :      resp_meta_providerResps_1_r_u,</a>
+<a name="5875"><span class="lineNum">    5875 </span>            :      resp_meta_providerResps_1_r_unconf,</a>
+<a name="5876"><span class="lineNum">    5876 </span>            :      resp_meta_providerResps_0_r_ctr,</a>
+<a name="5877"><span class="lineNum">    5877 </span>            :      resp_meta_providerResps_0_r_u,</a>
+<a name="5878"><span class="lineNum">    5878 </span>            :      resp_meta_providerResps_0_r_unconf,</a>
+<a name="5879"><span class="lineNum">    5879 </span>            :      resp_meta_altUsed_1_r,</a>
+<a name="5880"><span class="lineNum">    5880 </span>            :      resp_meta_altUsed_0_r,</a>
+<a name="5881"><span class="lineNum">    5881 </span>            :      resp_meta_altDiffers_1_r,</a>
+<a name="5882"><span class="lineNum">    5882 </span>            :      resp_meta_altDiffers_0_r,</a>
+<a name="5883"><span class="lineNum">    5883 </span>            :      resp_meta_basecnts_1_r,</a>
+<a name="5884"><span class="lineNum">    5884 </span>            :      resp_meta_basecnts_0_r,</a>
+<a name="5885"><span class="lineNum">    5885 </span>            :      resp_meta_allocates_1_r,</a>
+<a name="5886"><span class="lineNum">    5886 </span>            :      resp_meta_allocates_0_r,</a>
+<a name="5887"><span class="lineNum">    5887 </span>            :      resp_meta_takens_1_r,</a>
+<a name="5888"><span class="lineNum">    5888 </span>            :      resp_meta_takens_0_r,</a>
+<a name="5889"><span class="lineNum">    5889 </span>            :      resp_meta_scMeta_tageTakens_1_r,</a>
+<a name="5890"><span class="lineNum">    5890 </span>            :      resp_meta_scMeta_tageTakens_0_r,</a>
+<a name="5891"><span class="lineNum">    5891 </span>            :      resp_meta_scMeta_scUsed_1_r,</a>
+<a name="5892"><span class="lineNum">    5892 </span>            :      resp_meta_scMeta_scUsed_0_r,</a>
+<a name="5893"><span class="lineNum">    5893 </span>            :      resp_meta_scMeta_scPreds_1_r,</a>
+<a name="5894"><span class="lineNum">    5894 </span>            :      resp_meta_scMeta_scPreds_0_r,</a>
+<a name="5895"><span class="lineNum">    5895 </span>            :      r_3_3,</a>
+<a name="5896"><span class="lineNum">    5896 </span>            :      r_3_2,</a>
+<a name="5897"><span class="lineNum">    5897 </span>            :      r_3_1,</a>
+<a name="5898"><span class="lineNum">    5898 </span>            :      r_3_0,</a>
+<a name="5899"><span class="lineNum">    5899 </span>            :      r_2_3,</a>
+<a name="5900"><span class="lineNum">    5900 </span>            :      r_2_2,</a>
+<a name="5901"><span class="lineNum">    5901 </span>            :      r_2_1,</a>
+<a name="5902"><span class="lineNum">    5902 </span>            :      r_2_0};</a>
+<a name="5903"><span class="lineNum">    5903 </span>            :   assign io_s1_ready =</a>
+<a name="5904"><span class="lineNum">    5904 </span>            :     _tables_0_io_req_ready &amp; _tables_1_io_req_ready &amp; _tables_2_io_req_ready</a>
+<a name="5905"><span class="lineNum">    5905 </span>            :     &amp; _tables_3_io_req_ready &amp; _bt_io_req_ready;</a>
+<a name="5906"><span class="lineNum">    5906 </span>            :   assign io_perf_0_value = {4'h0, io_perf_0_value_REG_1};</a>
+<a name="5907"><span class="lineNum">    5907 </span>            :   assign io_perf_1_value = {4'h0, io_perf_1_value_REG_1};</a>
+<a name="5908"><span class="lineNum">    5908 </span>            :   assign io_perf_2_value = {4'h0, io_perf_2_value_REG_1};</a>
+<a name="5909"><span class="lineNum">    5909 </span>            : endmodule</a>
+<a name="5910"><span class="lineNum">    5910 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/WrBypass.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/WrBypass.sv.func-sort-c.html
new file mode 100644
index 0000000..29e2726
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/WrBypass.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/WrBypass.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - WrBypass.sv<span style="font-size: 80%;"> (<a href="WrBypass.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">114</td>
+            <td class="headerCovTableEntry">123</td>
+            <td class="headerCovTableEntryHi">92.7 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="WrBypass.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/WrBypass.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/WrBypass.sv.func.html
new file mode 100644
index 0000000..4b23522
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/WrBypass.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/WrBypass.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - WrBypass.sv<span style="font-size: 80%;"> (<a href="WrBypass.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">114</td>
+            <td class="headerCovTableEntry">123</td>
+            <td class="headerCovTableEntryHi">92.7 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="WrBypass.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/WrBypass.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/WrBypass.sv.gcov.html
new file mode 100644
index 0000000..011ba03
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/WrBypass.sv.gcov.html
@@ -0,0 +1,357 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/WrBypass.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - WrBypass.sv<span style="font-size: 80%;"> (source / <a href="WrBypass.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">114</td>
+            <td class="headerCovTableEntry">123</td>
+            <td class="headerCovTableEntryHi">92.7 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : module WrBypass(</a>
+<a name="59"><span class="lineNum">      59 </span><span class="lineCov">     127786 :   input        clock,</span></a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">         62 :   input        reset,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">        598 :   input        io_wen,</span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">        261 :   input  [8:0] io_write_idx,</span></a>
+<a name="63"><span class="lineNum">      63 </span><span class="lineCov">       1513 :   input  [2:0] io_write_data_0,</span></a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">        594 :   output       io_hit,</span></a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">        586 :   output       io_hit_data_0_valid,</span></a>
+<a name="66"><span class="lineNum">      66 </span><span class="lineCov">       1716 :   output [2:0] io_hit_data_0_bits</span></a>
+<a name="67"><span class="lineNum">      67 </span>            : );</a>
+<a name="68"><span class="lineNum">      68 </span>            : </a>
+<a name="69"><span class="lineNum">      69 </span>            :   wire       _idx_tag_cam_io_r_resp_0_0;</a>
+<a name="70"><span class="lineNum">      70 </span>            :   wire       _idx_tag_cam_io_r_resp_0_1;</a>
+<a name="71"><span class="lineNum">      71 </span>            :   wire       _idx_tag_cam_io_r_resp_0_2;</a>
+<a name="72"><span class="lineNum">      72 </span>            :   wire       _idx_tag_cam_io_r_resp_0_3;</a>
+<a name="73"><span class="lineNum">      73 </span>            :   wire       _idx_tag_cam_io_r_resp_0_4;</a>
+<a name="74"><span class="lineNum">      74 </span>            :   wire       _idx_tag_cam_io_r_resp_0_5;</a>
+<a name="75"><span class="lineNum">      75 </span>            :   wire       _idx_tag_cam_io_r_resp_0_6;</a>
+<a name="76"><span class="lineNum">      76 </span>            :   wire       _idx_tag_cam_io_r_resp_0_7;</a>
+<a name="77"><span class="lineNum">      77 </span><span class="lineCov">        718 :   reg        valids_0_0;</span></a>
+<a name="78"><span class="lineNum">      78 </span><span class="lineCov">        739 :   reg        valids_1_0;</span></a>
+<a name="79"><span class="lineNum">      79 </span><span class="lineCov">        705 :   reg        valids_2_0;</span></a>
+<a name="80"><span class="lineNum">      80 </span><span class="lineCov">        734 :   reg        valids_3_0;</span></a>
+<a name="81"><span class="lineNum">      81 </span><span class="lineCov">        751 :   reg        valids_4_0;</span></a>
+<a name="82"><span class="lineNum">      82 </span><span class="lineCov">        739 :   reg        valids_5_0;</span></a>
+<a name="83"><span class="lineNum">      83 </span><span class="lineCov">        722 :   reg        valids_6_0;</span></a>
+<a name="84"><span class="lineNum">      84 </span><span class="lineCov">        741 :   reg        valids_7_0;</span></a>
+<a name="85"><span class="lineNum">      85 </span><span class="lineCov">        732 :   reg        ever_written_0;</span></a>
+<a name="86"><span class="lineNum">      86 </span><span class="lineCov">        748 :   reg        ever_written_1;</span></a>
+<a name="87"><span class="lineNum">      87 </span><span class="lineCov">        724 :   reg        ever_written_2;</span></a>
+<a name="88"><span class="lineNum">      88 </span><span class="lineCov">        770 :   reg        ever_written_3;</span></a>
+<a name="89"><span class="lineNum">      89 </span><span class="lineCov">        751 :   reg        ever_written_4;</span></a>
+<a name="90"><span class="lineNum">      90 </span><span class="lineCov">        758 :   reg        ever_written_5;</span></a>
+<a name="91"><span class="lineNum">      91 </span><span class="lineCov">        766 :   reg        ever_written_6;</span></a>
+<a name="92"><span class="lineNum">      92 </span><span class="lineCov">        761 :   reg        ever_written_7;</span></a>
+<a name="93"><span class="lineNum">      93 </span><span class="lineCov">        463 :   wire       hits_oh_0 = _idx_tag_cam_io_r_resp_0_0 &amp; ever_written_0;</span></a>
+<a name="94"><span class="lineNum">      94 </span><span class="lineCov">        466 :   wire       hits_oh_1 = _idx_tag_cam_io_r_resp_0_1 &amp; ever_written_1;</span></a>
+<a name="95"><span class="lineNum">      95 </span><span class="lineCov">        485 :   wire       hits_oh_2 = _idx_tag_cam_io_r_resp_0_2 &amp; ever_written_2;</span></a>
+<a name="96"><span class="lineNum">      96 </span><span class="lineCov">        476 :   wire       hits_oh_3 = _idx_tag_cam_io_r_resp_0_3 &amp; ever_written_3;</span></a>
+<a name="97"><span class="lineNum">      97 </span><span class="lineCov">        507 :   wire       hits_oh_4 = _idx_tag_cam_io_r_resp_0_4 &amp; ever_written_4;</span></a>
+<a name="98"><span class="lineNum">      98 </span><span class="lineCov">        477 :   wire       hits_oh_5 = _idx_tag_cam_io_r_resp_0_5 &amp; ever_written_5;</span></a>
+<a name="99"><span class="lineNum">      99 </span><span class="lineCov">        447 :   wire       hits_oh_6 = _idx_tag_cam_io_r_resp_0_6 &amp; ever_written_6;</span></a>
+<a name="100"><span class="lineNum">     100 </span><span class="lineCov">        475 :   wire       hits_oh_7 = _idx_tag_cam_io_r_resp_0_7 &amp; ever_written_7;</span></a>
+<a name="101"><span class="lineNum">     101 </span>            :   wire [2:0] _hit_idx_T_2 =</a>
+<a name="102"><span class="lineNum">     102 </span>            :     {hits_oh_7, hits_oh_6, hits_oh_5} | {hits_oh_3, hits_oh_2, hits_oh_1};</a>
+<a name="103"><span class="lineNum">     103 </span><span class="lineCov">       1583 :   wire [2:0] hit_idx =</span></a>
+<a name="104"><span class="lineNum">     104 </span>            :     {|{hits_oh_7, hits_oh_6, hits_oh_5, hits_oh_4},</a>
+<a name="105"><span class="lineNum">     105 </span>            :      |(_hit_idx_T_2[2:1]),</a>
+<a name="106"><span class="lineNum">     106 </span>            :      _hit_idx_T_2[2] | _hit_idx_T_2[0]};</a>
+<a name="107"><span class="lineNum">     107 </span><span class="lineCov">        594 :   wire       hit =</span></a>
+<a name="108"><span class="lineNum">     108 </span>            :     hits_oh_0 | hits_oh_1 | hits_oh_2 | hits_oh_3 | hits_oh_4 | hits_oh_5 | hits_oh_6</a>
+<a name="109"><span class="lineNum">     109 </span>            :     | hits_oh_7;</a>
+<a name="110"><span class="lineNum">     110 </span><span class="lineCov">       5323 :   reg  [6:0] state_reg;</span></a>
+<a name="111"><span class="lineNum">     111 </span><span class="lineCov">       2358 :   wire [2:0] enq_idx =</span></a>
+<a name="112"><span class="lineNum">     112 </span>            :     {state_reg[6],</a>
+<a name="113"><span class="lineNum">     113 </span>            :      state_reg[6]</a>
+<a name="114"><span class="lineNum">     114 </span>            :        ? {state_reg[5], state_reg[5] ? state_reg[4] : state_reg[3]}</a>
+<a name="115"><span class="lineNum">     115 </span>            :        : {state_reg[2], state_reg[2] ? state_reg[1] : state_reg[0]}};</a>
+<a name="116"><span class="lineNum">     116 </span><span class="lineCov">       2233 :   wire [2:0] state_reg_touch_way_sized = hit ? hit_idx : enq_idx;</span></a>
+<a name="117"><span class="lineNum">     117 </span>            :   wire       _GEN = enq_idx == 3'h0;</a>
+<a name="118"><span class="lineNum">     118 </span>            :   wire       _GEN_0 = enq_idx == 3'h1;</a>
+<a name="119"><span class="lineNum">     119 </span>            :   wire       _GEN_1 = enq_idx == 3'h2;</a>
+<a name="120"><span class="lineNum">     120 </span>            :   wire       _GEN_2 = enq_idx == 3'h3;</a>
+<a name="121"><span class="lineNum">     121 </span>            :   wire       _GEN_3 = enq_idx == 3'h4;</a>
+<a name="122"><span class="lineNum">     122 </span>            :   wire       _GEN_4 = enq_idx == 3'h5;</a>
+<a name="123"><span class="lineNum">     123 </span>            :   wire       _GEN_5 = enq_idx == 3'h6;</a>
+<a name="124"><span class="lineNum">     124 </span><span class="lineCov">    4087360 :   always @(posedge clock or posedge reset) begin</span></a>
+<a name="125"><span class="lineNum">     125 </span><span class="lineCov">       8704 :     if (reset) begin</span></a>
+<a name="126"><span class="lineNum">     126 </span><span class="lineCov">       4352 :       valids_0_0 &lt;= 1'h0;</span></a>
+<a name="127"><span class="lineNum">     127 </span><span class="lineCov">       4352 :       valids_1_0 &lt;= 1'h0;</span></a>
+<a name="128"><span class="lineNum">     128 </span><span class="lineCov">       4352 :       valids_2_0 &lt;= 1'h0;</span></a>
+<a name="129"><span class="lineNum">     129 </span><span class="lineCov">       4352 :       valids_3_0 &lt;= 1'h0;</span></a>
+<a name="130"><span class="lineNum">     130 </span><span class="lineCov">       4352 :       valids_4_0 &lt;= 1'h0;</span></a>
+<a name="131"><span class="lineNum">     131 </span><span class="lineCov">       4352 :       valids_5_0 &lt;= 1'h0;</span></a>
+<a name="132"><span class="lineNum">     132 </span><span class="lineCov">       4352 :       valids_6_0 &lt;= 1'h0;</span></a>
+<a name="133"><span class="lineNum">     133 </span><span class="lineCov">       4352 :       valids_7_0 &lt;= 1'h0;</span></a>
+<a name="134"><span class="lineNum">     134 </span><span class="lineCov">       4352 :       ever_written_0 &lt;= 1'h0;</span></a>
+<a name="135"><span class="lineNum">     135 </span><span class="lineCov">       4352 :       ever_written_1 &lt;= 1'h0;</span></a>
+<a name="136"><span class="lineNum">     136 </span><span class="lineCov">       4352 :       ever_written_2 &lt;= 1'h0;</span></a>
+<a name="137"><span class="lineNum">     137 </span><span class="lineCov">       4352 :       ever_written_3 &lt;= 1'h0;</span></a>
+<a name="138"><span class="lineNum">     138 </span><span class="lineCov">       4352 :       ever_written_4 &lt;= 1'h0;</span></a>
+<a name="139"><span class="lineNum">     139 </span><span class="lineCov">       4352 :       ever_written_5 &lt;= 1'h0;</span></a>
+<a name="140"><span class="lineNum">     140 </span><span class="lineCov">       4352 :       ever_written_6 &lt;= 1'h0;</span></a>
+<a name="141"><span class="lineNum">     141 </span><span class="lineCov">       4352 :       ever_written_7 &lt;= 1'h0;</span></a>
+<a name="142"><span class="lineNum">     142 </span><span class="lineCov">       4352 :       state_reg &lt;= 7'h0;</span></a>
+<a name="143"><span class="lineNum">     143 </span>            :     end</a>
+<a name="144"><span class="lineNum">     144 </span><span class="lineCov">    2039328 :     else begin</span></a>
+<a name="145"><span class="lineNum">     145 </span><span class="lineCov">        142 :       if (io_wen) begin</span></a>
+<a name="146"><span class="lineNum">     146 </span><span class="lineNoCov">          0 :         if (hit) begin</span></a>
+<a name="147"><span class="lineNum">     147 </span><span class="lineNoCov">          0 :           valids_0_0 &lt;= hit_idx == 3'h0 | valids_0_0;</span></a>
+<a name="148"><span class="lineNum">     148 </span><span class="lineNoCov">          0 :           valids_1_0 &lt;= hit_idx == 3'h1 | valids_1_0;</span></a>
+<a name="149"><span class="lineNum">     149 </span><span class="lineNoCov">          0 :           valids_2_0 &lt;= hit_idx == 3'h2 | valids_2_0;</span></a>
+<a name="150"><span class="lineNum">     150 </span><span class="lineNoCov">          0 :           valids_3_0 &lt;= hit_idx == 3'h3 | valids_3_0;</span></a>
+<a name="151"><span class="lineNum">     151 </span><span class="lineNoCov">          0 :           valids_4_0 &lt;= hit_idx == 3'h4 | valids_4_0;</span></a>
+<a name="152"><span class="lineNum">     152 </span><span class="lineNoCov">          0 :           valids_5_0 &lt;= hit_idx == 3'h5 | valids_5_0;</span></a>
+<a name="153"><span class="lineNum">     153 </span><span class="lineNoCov">          0 :           valids_6_0 &lt;= hit_idx == 3'h6 | valids_6_0;</span></a>
+<a name="154"><span class="lineNum">     154 </span><span class="lineNoCov">          0 :           valids_7_0 &lt;= (&amp;hit_idx) | valids_7_0;</span></a>
+<a name="155"><span class="lineNum">     155 </span>            :         end</a>
+<a name="156"><span class="lineNum">     156 </span><span class="lineCov">         71 :         else begin</span></a>
+<a name="157"><span class="lineNum">     157 </span><span class="lineCov">         71 :           valids_0_0 &lt;= _GEN | ~_GEN &amp; valids_0_0;</span></a>
+<a name="158"><span class="lineNum">     158 </span><span class="lineCov">         71 :           valids_1_0 &lt;= _GEN_0 | ~_GEN_0 &amp; valids_1_0;</span></a>
+<a name="159"><span class="lineNum">     159 </span><span class="lineCov">         71 :           valids_2_0 &lt;= _GEN_1 | ~_GEN_1 &amp; valids_2_0;</span></a>
+<a name="160"><span class="lineNum">     160 </span><span class="lineCov">         71 :           valids_3_0 &lt;= _GEN_2 | ~_GEN_2 &amp; valids_3_0;</span></a>
+<a name="161"><span class="lineNum">     161 </span><span class="lineCov">         71 :           valids_4_0 &lt;= _GEN_3 | ~_GEN_3 &amp; valids_4_0;</span></a>
+<a name="162"><span class="lineNum">     162 </span><span class="lineCov">         71 :           valids_5_0 &lt;= _GEN_4 | ~_GEN_4 &amp; valids_5_0;</span></a>
+<a name="163"><span class="lineNum">     163 </span><span class="lineCov">         71 :           valids_6_0 &lt;= _GEN_5 | ~_GEN_5 &amp; valids_6_0;</span></a>
+<a name="164"><span class="lineNum">     164 </span><span class="lineCov">         71 :           valids_7_0 &lt;= (&amp;enq_idx) | ~(&amp;enq_idx) &amp; valids_7_0;</span></a>
+<a name="165"><span class="lineNum">     165 </span>            :         end</a>
+<a name="166"><span class="lineNum">     166 </span><span class="lineCov">         71 :         state_reg &lt;=</span></a>
+<a name="167"><span class="lineNum">     167 </span><span class="lineCov">         71 :           {~(state_reg_touch_way_sized[2]),</span></a>
+<a name="168"><span class="lineNum">     168 </span><span class="lineCov">         71 :            state_reg_touch_way_sized[2]</span></a>
+<a name="169"><span class="lineNum">     169 </span><span class="lineCov">         71 :              ? {~(state_reg_touch_way_sized[1]),</span></a>
+<a name="170"><span class="lineNum">     170 </span><span class="lineCov">         71 :                 state_reg_touch_way_sized[1]</span></a>
+<a name="171"><span class="lineNum">     171 </span><span class="lineCov">         71 :                   ? ~(state_reg_touch_way_sized[0])</span></a>
+<a name="172"><span class="lineNum">     172 </span><span class="lineCov">         71 :                   : state_reg[4],</span></a>
+<a name="173"><span class="lineNum">     173 </span><span class="lineCov">         71 :                 state_reg_touch_way_sized[1]</span></a>
+<a name="174"><span class="lineNum">     174 </span><span class="lineCov">         71 :                   ? state_reg[3]</span></a>
+<a name="175"><span class="lineNum">     175 </span><span class="lineCov">         71 :                   : ~(state_reg_touch_way_sized[0])}</span></a>
+<a name="176"><span class="lineNum">     176 </span><span class="lineCov">         71 :              : state_reg[5:3],</span></a>
+<a name="177"><span class="lineNum">     177 </span><span class="lineCov">         71 :            state_reg_touch_way_sized[2]</span></a>
+<a name="178"><span class="lineNum">     178 </span><span class="lineCov">         71 :              ? state_reg[2:0]</span></a>
+<a name="179"><span class="lineNum">     179 </span><span class="lineCov">         71 :              : {~(state_reg_touch_way_sized[1]),</span></a>
+<a name="180"><span class="lineNum">     180 </span><span class="lineCov">         71 :                 state_reg_touch_way_sized[1]</span></a>
+<a name="181"><span class="lineNum">     181 </span><span class="lineCov">         71 :                   ? ~(state_reg_touch_way_sized[0])</span></a>
+<a name="182"><span class="lineNum">     182 </span><span class="lineCov">         71 :                   : state_reg[1],</span></a>
+<a name="183"><span class="lineNum">     183 </span><span class="lineCov">         71 :                 state_reg_touch_way_sized[1]</span></a>
+<a name="184"><span class="lineNum">     184 </span><span class="lineCov">         71 :                   ? state_reg[0]</span></a>
+<a name="185"><span class="lineNum">     185 </span><span class="lineCov">         71 :                   : ~(state_reg_touch_way_sized[0])}};</span></a>
+<a name="186"><span class="lineNum">     186 </span>            :       end</a>
+<a name="187"><span class="lineNum">     187 </span><span class="lineCov">    2039328 :       ever_written_0 &lt;= io_wen &amp; ~hit &amp; _GEN | ever_written_0;</span></a>
+<a name="188"><span class="lineNum">     188 </span><span class="lineCov">    2039328 :       ever_written_1 &lt;= io_wen &amp; ~hit &amp; _GEN_0 | ever_written_1;</span></a>
+<a name="189"><span class="lineNum">     189 </span><span class="lineCov">    2039328 :       ever_written_2 &lt;= io_wen &amp; ~hit &amp; _GEN_1 | ever_written_2;</span></a>
+<a name="190"><span class="lineNum">     190 </span><span class="lineCov">    2039328 :       ever_written_3 &lt;= io_wen &amp; ~hit &amp; _GEN_2 | ever_written_3;</span></a>
+<a name="191"><span class="lineNum">     191 </span><span class="lineCov">    2039328 :       ever_written_4 &lt;= io_wen &amp; ~hit &amp; _GEN_3 | ever_written_4;</span></a>
+<a name="192"><span class="lineNum">     192 </span><span class="lineCov">    2039328 :       ever_written_5 &lt;= io_wen &amp; ~hit &amp; _GEN_4 | ever_written_5;</span></a>
+<a name="193"><span class="lineNum">     193 </span><span class="lineCov">    2039328 :       ever_written_6 &lt;= io_wen &amp; ~hit &amp; _GEN_5 | ever_written_6;</span></a>
+<a name="194"><span class="lineNum">     194 </span><span class="lineCov">    2039328 :       ever_written_7 &lt;= io_wen &amp; ~hit &amp; (&amp;enq_idx) | ever_written_7;</span></a>
+<a name="195"><span class="lineNum">     195 </span>            :     end</a>
+<a name="196"><span class="lineNum">     196 </span>            :   end // always @(posedge, posedge)</a>
+<a name="197"><span class="lineNum">     197 </span>            :   `ifdef ENABLE_INITIAL_REG_</a>
+<a name="198"><span class="lineNum">     198 </span>            :     `ifdef FIRRTL_BEFORE_INITIAL</a>
+<a name="199"><span class="lineNum">     199 </span>            :       `FIRRTL_BEFORE_INITIAL</a>
+<a name="200"><span class="lineNum">     200 </span>            :     `endif // FIRRTL_BEFORE_INITIAL</a>
+<a name="201"><span class="lineNum">     201 </span>            :     logic [31:0] _RANDOM[0:0];</a>
+<a name="202"><span class="lineNum">     202 </span><span class="lineCov">       1856 :     initial begin</span></a>
+<a name="203"><span class="lineNum">     203 </span>            :       `ifdef INIT_RANDOM_PROLOG_</a>
+<a name="204"><span class="lineNum">     204 </span>            :         `INIT_RANDOM_PROLOG_</a>
+<a name="205"><span class="lineNum">     205 </span>            :       `endif // INIT_RANDOM_PROLOG_</a>
+<a name="206"><span class="lineNum">     206 </span>            :       `ifdef RANDOMIZE_REG_INIT</a>
+<a name="207"><span class="lineNum">     207 </span>            :         _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;</a>
+<a name="208"><span class="lineNum">     208 </span>            :         valids_0_0 = _RANDOM[/*Zero width*/ 1'b0][0];</a>
+<a name="209"><span class="lineNum">     209 </span>            :         valids_1_0 = _RANDOM[/*Zero width*/ 1'b0][1];</a>
+<a name="210"><span class="lineNum">     210 </span>            :         valids_2_0 = _RANDOM[/*Zero width*/ 1'b0][2];</a>
+<a name="211"><span class="lineNum">     211 </span>            :         valids_3_0 = _RANDOM[/*Zero width*/ 1'b0][3];</a>
+<a name="212"><span class="lineNum">     212 </span>            :         valids_4_0 = _RANDOM[/*Zero width*/ 1'b0][4];</a>
+<a name="213"><span class="lineNum">     213 </span>            :         valids_5_0 = _RANDOM[/*Zero width*/ 1'b0][5];</a>
+<a name="214"><span class="lineNum">     214 </span>            :         valids_6_0 = _RANDOM[/*Zero width*/ 1'b0][6];</a>
+<a name="215"><span class="lineNum">     215 </span>            :         valids_7_0 = _RANDOM[/*Zero width*/ 1'b0][7];</a>
+<a name="216"><span class="lineNum">     216 </span>            :         ever_written_0 = _RANDOM[/*Zero width*/ 1'b0][8];</a>
+<a name="217"><span class="lineNum">     217 </span>            :         ever_written_1 = _RANDOM[/*Zero width*/ 1'b0][9];</a>
+<a name="218"><span class="lineNum">     218 </span>            :         ever_written_2 = _RANDOM[/*Zero width*/ 1'b0][10];</a>
+<a name="219"><span class="lineNum">     219 </span>            :         ever_written_3 = _RANDOM[/*Zero width*/ 1'b0][11];</a>
+<a name="220"><span class="lineNum">     220 </span>            :         ever_written_4 = _RANDOM[/*Zero width*/ 1'b0][12];</a>
+<a name="221"><span class="lineNum">     221 </span>            :         ever_written_5 = _RANDOM[/*Zero width*/ 1'b0][13];</a>
+<a name="222"><span class="lineNum">     222 </span>            :         ever_written_6 = _RANDOM[/*Zero width*/ 1'b0][14];</a>
+<a name="223"><span class="lineNum">     223 </span>            :         ever_written_7 = _RANDOM[/*Zero width*/ 1'b0][15];</a>
+<a name="224"><span class="lineNum">     224 </span>            :         state_reg = _RANDOM[/*Zero width*/ 1'b0][22:16];</a>
+<a name="225"><span class="lineNum">     225 </span>            :       `endif // RANDOMIZE_REG_INIT</a>
+<a name="226"><span class="lineNum">     226 </span><span class="lineCov">        544 :       if (reset) begin</span></a>
+<a name="227"><span class="lineNum">     227 </span><span class="lineCov">        384 :         valids_0_0 = 1'h0;</span></a>
+<a name="228"><span class="lineNum">     228 </span><span class="lineCov">        384 :         valids_1_0 = 1'h0;</span></a>
+<a name="229"><span class="lineNum">     229 </span><span class="lineCov">        384 :         valids_2_0 = 1'h0;</span></a>
+<a name="230"><span class="lineNum">     230 </span><span class="lineCov">        384 :         valids_3_0 = 1'h0;</span></a>
+<a name="231"><span class="lineNum">     231 </span><span class="lineCov">        384 :         valids_4_0 = 1'h0;</span></a>
+<a name="232"><span class="lineNum">     232 </span><span class="lineCov">        384 :         valids_5_0 = 1'h0;</span></a>
+<a name="233"><span class="lineNum">     233 </span><span class="lineCov">        384 :         valids_6_0 = 1'h0;</span></a>
+<a name="234"><span class="lineNum">     234 </span><span class="lineCov">        384 :         valids_7_0 = 1'h0;</span></a>
+<a name="235"><span class="lineNum">     235 </span><span class="lineCov">        384 :         ever_written_0 = 1'h0;</span></a>
+<a name="236"><span class="lineNum">     236 </span><span class="lineCov">        384 :         ever_written_1 = 1'h0;</span></a>
+<a name="237"><span class="lineNum">     237 </span><span class="lineCov">        384 :         ever_written_2 = 1'h0;</span></a>
+<a name="238"><span class="lineNum">     238 </span><span class="lineCov">        384 :         ever_written_3 = 1'h0;</span></a>
+<a name="239"><span class="lineNum">     239 </span><span class="lineCov">        384 :         ever_written_4 = 1'h0;</span></a>
+<a name="240"><span class="lineNum">     240 </span><span class="lineCov">        384 :         ever_written_5 = 1'h0;</span></a>
+<a name="241"><span class="lineNum">     241 </span><span class="lineCov">        384 :         ever_written_6 = 1'h0;</span></a>
+<a name="242"><span class="lineNum">     242 </span><span class="lineCov">        384 :         ever_written_7 = 1'h0;</span></a>
+<a name="243"><span class="lineNum">     243 </span><span class="lineCov">        384 :         state_reg = 7'h0;</span></a>
+<a name="244"><span class="lineNum">     244 </span>            :       end</a>
+<a name="245"><span class="lineNum">     245 </span>            :     end // initial</a>
+<a name="246"><span class="lineNum">     246 </span>            :     `ifdef FIRRTL_AFTER_INITIAL</a>
+<a name="247"><span class="lineNum">     247 </span>            :       `FIRRTL_AFTER_INITIAL</a>
+<a name="248"><span class="lineNum">     248 </span>            :     `endif // FIRRTL_AFTER_INITIAL</a>
+<a name="249"><span class="lineNum">     249 </span>            :   `endif // ENABLE_INITIAL_REG_</a>
+<a name="250"><span class="lineNum">     250 </span>            :   CAMTemplate idx_tag_cam (</a>
+<a name="251"><span class="lineNum">     251 </span>            :     .clock              (clock),</a>
+<a name="252"><span class="lineNum">     252 </span>            :     .io_r_req_0_idx     (io_write_idx),</a>
+<a name="253"><span class="lineNum">     253 </span>            :     .io_r_resp_0_0      (_idx_tag_cam_io_r_resp_0_0),</a>
+<a name="254"><span class="lineNum">     254 </span>            :     .io_r_resp_0_1      (_idx_tag_cam_io_r_resp_0_1),</a>
+<a name="255"><span class="lineNum">     255 </span>            :     .io_r_resp_0_2      (_idx_tag_cam_io_r_resp_0_2),</a>
+<a name="256"><span class="lineNum">     256 </span>            :     .io_r_resp_0_3      (_idx_tag_cam_io_r_resp_0_3),</a>
+<a name="257"><span class="lineNum">     257 </span>            :     .io_r_resp_0_4      (_idx_tag_cam_io_r_resp_0_4),</a>
+<a name="258"><span class="lineNum">     258 </span>            :     .io_r_resp_0_5      (_idx_tag_cam_io_r_resp_0_5),</a>
+<a name="259"><span class="lineNum">     259 </span>            :     .io_r_resp_0_6      (_idx_tag_cam_io_r_resp_0_6),</a>
+<a name="260"><span class="lineNum">     260 </span>            :     .io_r_resp_0_7      (_idx_tag_cam_io_r_resp_0_7),</a>
+<a name="261"><span class="lineNum">     261 </span>            :     .io_w_valid         (io_wen &amp; ~hit),</a>
+<a name="262"><span class="lineNum">     262 </span>            :     .io_w_bits_data_idx (io_write_idx),</a>
+<a name="263"><span class="lineNum">     263 </span>            :     .io_w_bits_index    (enq_idx)</a>
+<a name="264"><span class="lineNum">     264 </span>            :   );</a>
+<a name="265"><span class="lineNum">     265 </span>            :   data_mem_0_8x3 data_mem_0_ext (</a>
+<a name="266"><span class="lineNum">     266 </span>            :     .R0_addr (hit_idx),</a>
+<a name="267"><span class="lineNum">     267 </span>            :     .R0_en   (1'h1),</a>
+<a name="268"><span class="lineNum">     268 </span>            :     .R0_clk  (clock),</a>
+<a name="269"><span class="lineNum">     269 </span>            :     .R0_data (io_hit_data_0_bits),</a>
+<a name="270"><span class="lineNum">     270 </span>            :     .W0_addr (hit ? hit_idx : enq_idx),</a>
+<a name="271"><span class="lineNum">     271 </span>            :     .W0_en   (io_wen),</a>
+<a name="272"><span class="lineNum">     272 </span>            :     .W0_clk  (clock),</a>
+<a name="273"><span class="lineNum">     273 </span>            :     .W0_data (io_write_data_0)</a>
+<a name="274"><span class="lineNum">     274 </span>            :   );</a>
+<a name="275"><span class="lineNum">     275 </span>            :   assign io_hit = hit;</a>
+<a name="276"><span class="lineNum">     276 </span>            :   assign io_hit_data_0_valid =</a>
+<a name="277"><span class="lineNum">     277 </span>            :     hits_oh_0 &amp; valids_0_0 | hits_oh_1 &amp; valids_1_0 | hits_oh_2 &amp; valids_2_0 | hits_oh_3</a>
+<a name="278"><span class="lineNum">     278 </span>            :     &amp; valids_3_0 | hits_oh_4 &amp; valids_4_0 | hits_oh_5 &amp; valids_5_0 | hits_oh_6</a>
+<a name="279"><span class="lineNum">     279 </span>            :     &amp; valids_6_0 | hits_oh_7 &amp; valids_7_0;</a>
+<a name="280"><span class="lineNum">     280 </span>            : endmodule</a>
+<a name="281"><span class="lineNum">     281 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/WrBypass_32.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/WrBypass_32.sv.func-sort-c.html
new file mode 100644
index 0000000..4efcfc0
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/WrBypass_32.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/WrBypass_32.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - WrBypass_32.sv<span style="font-size: 80%;"> (<a href="WrBypass_32.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">152</td>
+            <td class="headerCovTableEntry">169</td>
+            <td class="headerCovTableEntryMed">89.9 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="WrBypass_32.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/WrBypass_32.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/WrBypass_32.sv.func.html
new file mode 100644
index 0000000..a4b0e5c
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/WrBypass_32.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/WrBypass_32.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - WrBypass_32.sv<span style="font-size: 80%;"> (<a href="WrBypass_32.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">152</td>
+            <td class="headerCovTableEntry">169</td>
+            <td class="headerCovTableEntryMed">89.9 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="WrBypass_32.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/WrBypass_32.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/WrBypass_32.sv.gcov.html
new file mode 100644
index 0000000..58d1d00
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/WrBypass_32.sv.gcov.html
@@ -0,0 +1,431 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/WrBypass_32.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - WrBypass_32.sv<span style="font-size: 80%;"> (source / <a href="WrBypass_32.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">152</td>
+            <td class="headerCovTableEntry">169</td>
+            <td class="headerCovTableEntryMed">89.9 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : module WrBypass_32(</a>
+<a name="59"><span class="lineNum">      59 </span><span class="lineCov">     127786 :   input         clock,</span></a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">         62 :   input         reset,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">         35 :   input         io_wen,</span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">        189 :   input  [10:0] io_write_idx,</span></a>
+<a name="63"><span class="lineNum">      63 </span><span class="lineCov">         39 :   input  [1:0]  io_write_data_0,</span></a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">         39 :   input  [1:0]  io_write_data_1,</span></a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">         28 :   input         io_write_way_mask_0,</span></a>
+<a name="66"><span class="lineNum">      66 </span><span class="lineCov">         26 :   input         io_write_way_mask_1,</span></a>
+<a name="67"><span class="lineNum">      67 </span><span class="lineCov">         32 :   output        io_hit,</span></a>
+<a name="68"><span class="lineNum">      68 </span><span class="lineCov">         23 :   output        io_hit_data_0_valid,</span></a>
+<a name="69"><span class="lineNum">      69 </span><span class="lineCov">         56 :   output [1:0]  io_hit_data_0_bits,</span></a>
+<a name="70"><span class="lineNum">      70 </span><span class="lineCov">         27 :   output        io_hit_data_1_valid,</span></a>
+<a name="71"><span class="lineNum">      71 </span><span class="lineCov">         57 :   output [1:0]  io_hit_data_1_bits</span></a>
+<a name="72"><span class="lineNum">      72 </span>            : );</a>
+<a name="73"><span class="lineNum">      73 </span>            : </a>
+<a name="74"><span class="lineNum">      74 </span>            :   wire [3:0] _data_mem_ext_R0_data;</a>
+<a name="75"><span class="lineNum">      75 </span>            :   wire [3:0] _data_mem_ext_R1_data;</a>
+<a name="76"><span class="lineNum">      76 </span>            :   wire       _idx_tag_cam_io_r_resp_0_0;</a>
+<a name="77"><span class="lineNum">      77 </span>            :   wire       _idx_tag_cam_io_r_resp_0_1;</a>
+<a name="78"><span class="lineNum">      78 </span>            :   wire       _idx_tag_cam_io_r_resp_0_2;</a>
+<a name="79"><span class="lineNum">      79 </span>            :   wire       _idx_tag_cam_io_r_resp_0_3;</a>
+<a name="80"><span class="lineNum">      80 </span>            :   wire       _idx_tag_cam_io_r_resp_0_4;</a>
+<a name="81"><span class="lineNum">      81 </span>            :   wire       _idx_tag_cam_io_r_resp_0_5;</a>
+<a name="82"><span class="lineNum">      82 </span>            :   wire       _idx_tag_cam_io_r_resp_0_6;</a>
+<a name="83"><span class="lineNum">      83 </span>            :   wire       _idx_tag_cam_io_r_resp_0_7;</a>
+<a name="84"><span class="lineNum">      84 </span><span class="lineCov">         20 :   reg        valids_0_0;</span></a>
+<a name="85"><span class="lineNum">      85 </span><span class="lineCov">         19 :   reg        valids_0_1;</span></a>
+<a name="86"><span class="lineNum">      86 </span><span class="lineCov">         22 :   reg        valids_1_0;</span></a>
+<a name="87"><span class="lineNum">      87 </span><span class="lineCov">         23 :   reg        valids_1_1;</span></a>
+<a name="88"><span class="lineNum">      88 </span><span class="lineCov">         22 :   reg        valids_2_0;</span></a>
+<a name="89"><span class="lineNum">      89 </span><span class="lineCov">         30 :   reg        valids_2_1;</span></a>
+<a name="90"><span class="lineNum">      90 </span><span class="lineCov">         28 :   reg        valids_3_0;</span></a>
+<a name="91"><span class="lineNum">      91 </span><span class="lineCov">         21 :   reg        valids_3_1;</span></a>
+<a name="92"><span class="lineNum">      92 </span><span class="lineCov">         23 :   reg        valids_4_0;</span></a>
+<a name="93"><span class="lineNum">      93 </span><span class="lineCov">         20 :   reg        valids_4_1;</span></a>
+<a name="94"><span class="lineNum">      94 </span><span class="lineCov">         19 :   reg        valids_5_0;</span></a>
+<a name="95"><span class="lineNum">      95 </span><span class="lineCov">         29 :   reg        valids_5_1;</span></a>
+<a name="96"><span class="lineNum">      96 </span><span class="lineCov">         23 :   reg        valids_6_0;</span></a>
+<a name="97"><span class="lineNum">      97 </span><span class="lineCov">         17 :   reg        valids_6_1;</span></a>
+<a name="98"><span class="lineNum">      98 </span><span class="lineCov">         22 :   reg        valids_7_0;</span></a>
+<a name="99"><span class="lineNum">      99 </span><span class="lineCov">         25 :   reg        valids_7_1;</span></a>
+<a name="100"><span class="lineNum">     100 </span><span class="lineCov">         25 :   reg        ever_written_0;</span></a>
+<a name="101"><span class="lineNum">     101 </span><span class="lineCov">         26 :   reg        ever_written_1;</span></a>
+<a name="102"><span class="lineNum">     102 </span><span class="lineCov">         30 :   reg        ever_written_2;</span></a>
+<a name="103"><span class="lineNum">     103 </span><span class="lineCov">         24 :   reg        ever_written_3;</span></a>
+<a name="104"><span class="lineNum">     104 </span><span class="lineCov">         25 :   reg        ever_written_4;</span></a>
+<a name="105"><span class="lineNum">     105 </span><span class="lineCov">         29 :   reg        ever_written_5;</span></a>
+<a name="106"><span class="lineNum">     106 </span><span class="lineCov">         21 :   reg        ever_written_6;</span></a>
+<a name="107"><span class="lineNum">     107 </span><span class="lineCov">         28 :   reg        ever_written_7;</span></a>
+<a name="108"><span class="lineNum">     108 </span><span class="lineCov">         19 :   wire       hits_oh_0 = _idx_tag_cam_io_r_resp_0_0 &amp; ever_written_0;</span></a>
+<a name="109"><span class="lineNum">     109 </span><span class="lineCov">         16 :   wire       hits_oh_1 = _idx_tag_cam_io_r_resp_0_1 &amp; ever_written_1;</span></a>
+<a name="110"><span class="lineNum">     110 </span><span class="lineCov">         24 :   wire       hits_oh_2 = _idx_tag_cam_io_r_resp_0_2 &amp; ever_written_2;</span></a>
+<a name="111"><span class="lineNum">     111 </span><span class="lineCov">         16 :   wire       hits_oh_3 = _idx_tag_cam_io_r_resp_0_3 &amp; ever_written_3;</span></a>
+<a name="112"><span class="lineNum">     112 </span><span class="lineCov">         10 :   wire       hits_oh_4 = _idx_tag_cam_io_r_resp_0_4 &amp; ever_written_4;</span></a>
+<a name="113"><span class="lineNum">     113 </span><span class="lineCov">         20 :   wire       hits_oh_5 = _idx_tag_cam_io_r_resp_0_5 &amp; ever_written_5;</span></a>
+<a name="114"><span class="lineNum">     114 </span><span class="lineCov">         12 :   wire       hits_oh_6 = _idx_tag_cam_io_r_resp_0_6 &amp; ever_written_6;</span></a>
+<a name="115"><span class="lineNum">     115 </span><span class="lineCov">         15 :   wire       hits_oh_7 = _idx_tag_cam_io_r_resp_0_7 &amp; ever_written_7;</span></a>
+<a name="116"><span class="lineNum">     116 </span>            :   wire [2:0] _hit_idx_T_2 =</a>
+<a name="117"><span class="lineNum">     117 </span>            :     {hits_oh_7, hits_oh_6, hits_oh_5} | {hits_oh_3, hits_oh_2, hits_oh_1};</a>
+<a name="118"><span class="lineNum">     118 </span><span class="lineCov">         68 :   wire [2:0] hit_idx =</span></a>
+<a name="119"><span class="lineNum">     119 </span>            :     {|{hits_oh_7, hits_oh_6, hits_oh_5, hits_oh_4},</a>
+<a name="120"><span class="lineNum">     120 </span>            :      |(_hit_idx_T_2[2:1]),</a>
+<a name="121"><span class="lineNum">     121 </span>            :      _hit_idx_T_2[2] | _hit_idx_T_2[0]};</a>
+<a name="122"><span class="lineNum">     122 </span><span class="lineCov">         32 :   wire       hit =</span></a>
+<a name="123"><span class="lineNum">     123 </span>            :     hits_oh_0 | hits_oh_1 | hits_oh_2 | hits_oh_3 | hits_oh_4 | hits_oh_5 | hits_oh_6</a>
+<a name="124"><span class="lineNum">     124 </span>            :     | hits_oh_7;</a>
+<a name="125"><span class="lineNum">     125 </span><span class="lineCov">        183 :   reg  [6:0] state_reg;</span></a>
+<a name="126"><span class="lineNum">     126 </span><span class="lineCov">         94 :   wire [2:0] enq_idx =</span></a>
+<a name="127"><span class="lineNum">     127 </span>            :     {state_reg[6],</a>
+<a name="128"><span class="lineNum">     128 </span>            :      state_reg[6]</a>
+<a name="129"><span class="lineNum">     129 </span>            :        ? {state_reg[5], state_reg[5] ? state_reg[4] : state_reg[3]}</a>
+<a name="130"><span class="lineNum">     130 </span>            :        : {state_reg[2], state_reg[2] ? state_reg[1] : state_reg[0]}};</a>
+<a name="131"><span class="lineNum">     131 </span>            :   wire       _GEN = hit_idx == 3'h0;</a>
+<a name="132"><span class="lineNum">     132 </span>            :   wire       _GEN_0 = hit_idx == 3'h1;</a>
+<a name="133"><span class="lineNum">     133 </span>            :   wire       _GEN_1 = hit_idx == 3'h2;</a>
+<a name="134"><span class="lineNum">     134 </span>            :   wire       _GEN_2 = hit_idx == 3'h3;</a>
+<a name="135"><span class="lineNum">     135 </span>            :   wire       _GEN_3 = hit_idx == 3'h4;</a>
+<a name="136"><span class="lineNum">     136 </span>            :   wire       _GEN_4 = hit_idx == 3'h5;</a>
+<a name="137"><span class="lineNum">     137 </span>            :   wire       _GEN_5 = hit_idx == 3'h6;</a>
+<a name="138"><span class="lineNum">     138 </span><span class="lineCov">         74 :   wire [2:0] state_reg_touch_way_sized = hit ? hit_idx : enq_idx;</span></a>
+<a name="139"><span class="lineNum">     139 </span>            :   wire       _GEN_6 = enq_idx == 3'h0;</a>
+<a name="140"><span class="lineNum">     140 </span>            :   wire       _GEN_7 = enq_idx == 3'h1;</a>
+<a name="141"><span class="lineNum">     141 </span>            :   wire       _GEN_8 = enq_idx == 3'h2;</a>
+<a name="142"><span class="lineNum">     142 </span>            :   wire       _GEN_9 = enq_idx == 3'h3;</a>
+<a name="143"><span class="lineNum">     143 </span>            :   wire       _GEN_10 = enq_idx == 3'h4;</a>
+<a name="144"><span class="lineNum">     144 </span>            :   wire       _GEN_11 = enq_idx == 3'h5;</a>
+<a name="145"><span class="lineNum">     145 </span>            :   wire       _GEN_12 = enq_idx == 3'h6;</a>
+<a name="146"><span class="lineNum">     146 </span><span class="lineCov">     127730 :   always @(posedge clock or posedge reset) begin</span></a>
+<a name="147"><span class="lineNum">     147 </span><span class="lineCov">        272 :     if (reset) begin</span></a>
+<a name="148"><span class="lineNum">     148 </span><span class="lineCov">        136 :       valids_0_0 &lt;= 1'h0;</span></a>
+<a name="149"><span class="lineNum">     149 </span><span class="lineCov">        136 :       valids_0_1 &lt;= 1'h0;</span></a>
+<a name="150"><span class="lineNum">     150 </span><span class="lineCov">        136 :       valids_1_0 &lt;= 1'h0;</span></a>
+<a name="151"><span class="lineNum">     151 </span><span class="lineCov">        136 :       valids_1_1 &lt;= 1'h0;</span></a>
+<a name="152"><span class="lineNum">     152 </span><span class="lineCov">        136 :       valids_2_0 &lt;= 1'h0;</span></a>
+<a name="153"><span class="lineNum">     153 </span><span class="lineCov">        136 :       valids_2_1 &lt;= 1'h0;</span></a>
+<a name="154"><span class="lineNum">     154 </span><span class="lineCov">        136 :       valids_3_0 &lt;= 1'h0;</span></a>
+<a name="155"><span class="lineNum">     155 </span><span class="lineCov">        136 :       valids_3_1 &lt;= 1'h0;</span></a>
+<a name="156"><span class="lineNum">     156 </span><span class="lineCov">        136 :       valids_4_0 &lt;= 1'h0;</span></a>
+<a name="157"><span class="lineNum">     157 </span><span class="lineCov">        136 :       valids_4_1 &lt;= 1'h0;</span></a>
+<a name="158"><span class="lineNum">     158 </span><span class="lineCov">        136 :       valids_5_0 &lt;= 1'h0;</span></a>
+<a name="159"><span class="lineNum">     159 </span><span class="lineCov">        136 :       valids_5_1 &lt;= 1'h0;</span></a>
+<a name="160"><span class="lineNum">     160 </span><span class="lineCov">        136 :       valids_6_0 &lt;= 1'h0;</span></a>
+<a name="161"><span class="lineNum">     161 </span><span class="lineCov">        136 :       valids_6_1 &lt;= 1'h0;</span></a>
+<a name="162"><span class="lineNum">     162 </span><span class="lineCov">        136 :       valids_7_0 &lt;= 1'h0;</span></a>
+<a name="163"><span class="lineNum">     163 </span><span class="lineCov">        136 :       valids_7_1 &lt;= 1'h0;</span></a>
+<a name="164"><span class="lineNum">     164 </span><span class="lineCov">        136 :       ever_written_0 &lt;= 1'h0;</span></a>
+<a name="165"><span class="lineNum">     165 </span><span class="lineCov">        136 :       ever_written_1 &lt;= 1'h0;</span></a>
+<a name="166"><span class="lineNum">     166 </span><span class="lineCov">        136 :       ever_written_2 &lt;= 1'h0;</span></a>
+<a name="167"><span class="lineNum">     167 </span><span class="lineCov">        136 :       ever_written_3 &lt;= 1'h0;</span></a>
+<a name="168"><span class="lineNum">     168 </span><span class="lineCov">        136 :       ever_written_4 &lt;= 1'h0;</span></a>
+<a name="169"><span class="lineNum">     169 </span><span class="lineCov">        136 :       ever_written_5 &lt;= 1'h0;</span></a>
+<a name="170"><span class="lineNum">     170 </span><span class="lineCov">        136 :       ever_written_6 &lt;= 1'h0;</span></a>
+<a name="171"><span class="lineNum">     171 </span><span class="lineCov">        136 :       ever_written_7 &lt;= 1'h0;</span></a>
+<a name="172"><span class="lineNum">     172 </span><span class="lineCov">        136 :       state_reg &lt;= 7'h0;</span></a>
+<a name="173"><span class="lineNum">     173 </span>            :     end</a>
+<a name="174"><span class="lineNum">     174 </span><span class="lineCov">      63729 :     else begin</span></a>
+<a name="175"><span class="lineNum">     175 </span><span class="lineCov">         24 :       if (io_wen) begin</span></a>
+<a name="176"><span class="lineNum">     176 </span><span class="lineNoCov">          0 :         if (hit) begin</span></a>
+<a name="177"><span class="lineNum">     177 </span><span class="lineNoCov">          0 :           valids_0_0 &lt;= io_write_way_mask_0 &amp; _GEN | valids_0_0;</span></a>
+<a name="178"><span class="lineNum">     178 </span><span class="lineNoCov">          0 :           valids_0_1 &lt;= io_write_way_mask_1 &amp; _GEN | valids_0_1;</span></a>
+<a name="179"><span class="lineNum">     179 </span><span class="lineNoCov">          0 :           valids_1_0 &lt;= io_write_way_mask_0 &amp; _GEN_0 | valids_1_0;</span></a>
+<a name="180"><span class="lineNum">     180 </span><span class="lineNoCov">          0 :           valids_1_1 &lt;= io_write_way_mask_1 &amp; _GEN_0 | valids_1_1;</span></a>
+<a name="181"><span class="lineNum">     181 </span><span class="lineNoCov">          0 :           valids_2_0 &lt;= io_write_way_mask_0 &amp; _GEN_1 | valids_2_0;</span></a>
+<a name="182"><span class="lineNum">     182 </span><span class="lineNoCov">          0 :           valids_2_1 &lt;= io_write_way_mask_1 &amp; _GEN_1 | valids_2_1;</span></a>
+<a name="183"><span class="lineNum">     183 </span><span class="lineNoCov">          0 :           valids_3_0 &lt;= io_write_way_mask_0 &amp; _GEN_2 | valids_3_0;</span></a>
+<a name="184"><span class="lineNum">     184 </span><span class="lineNoCov">          0 :           valids_3_1 &lt;= io_write_way_mask_1 &amp; _GEN_2 | valids_3_1;</span></a>
+<a name="185"><span class="lineNum">     185 </span><span class="lineNoCov">          0 :           valids_4_0 &lt;= io_write_way_mask_0 &amp; _GEN_3 | valids_4_0;</span></a>
+<a name="186"><span class="lineNum">     186 </span><span class="lineNoCov">          0 :           valids_4_1 &lt;= io_write_way_mask_1 &amp; _GEN_3 | valids_4_1;</span></a>
+<a name="187"><span class="lineNum">     187 </span><span class="lineNoCov">          0 :           valids_5_0 &lt;= io_write_way_mask_0 &amp; _GEN_4 | valids_5_0;</span></a>
+<a name="188"><span class="lineNum">     188 </span><span class="lineNoCov">          0 :           valids_5_1 &lt;= io_write_way_mask_1 &amp; _GEN_4 | valids_5_1;</span></a>
+<a name="189"><span class="lineNum">     189 </span><span class="lineNoCov">          0 :           valids_6_0 &lt;= io_write_way_mask_0 &amp; _GEN_5 | valids_6_0;</span></a>
+<a name="190"><span class="lineNum">     190 </span><span class="lineNoCov">          0 :           valids_6_1 &lt;= io_write_way_mask_1 &amp; _GEN_5 | valids_6_1;</span></a>
+<a name="191"><span class="lineNum">     191 </span><span class="lineNoCov">          0 :           valids_7_0 &lt;= io_write_way_mask_0 &amp; (&amp;hit_idx) | valids_7_0;</span></a>
+<a name="192"><span class="lineNum">     192 </span><span class="lineNoCov">          0 :           valids_7_1 &lt;= io_write_way_mask_1 &amp; (&amp;hit_idx) | valids_7_1;</span></a>
+<a name="193"><span class="lineNum">     193 </span>            :         end</a>
+<a name="194"><span class="lineNum">     194 </span><span class="lineCov">         12 :         else begin</span></a>
+<a name="195"><span class="lineNum">     195 </span><span class="lineCov">         12 :           valids_0_0 &lt;= io_write_way_mask_0 &amp; _GEN_6 | ~_GEN_6 &amp; valids_0_0;</span></a>
+<a name="196"><span class="lineNum">     196 </span><span class="lineCov">         12 :           valids_0_1 &lt;= io_write_way_mask_1 &amp; _GEN_6 | ~_GEN_6 &amp; valids_0_1;</span></a>
+<a name="197"><span class="lineNum">     197 </span><span class="lineCov">         12 :           valids_1_0 &lt;= io_write_way_mask_0 &amp; _GEN_7 | ~_GEN_7 &amp; valids_1_0;</span></a>
+<a name="198"><span class="lineNum">     198 </span><span class="lineCov">         12 :           valids_1_1 &lt;= io_write_way_mask_1 &amp; _GEN_7 | ~_GEN_7 &amp; valids_1_1;</span></a>
+<a name="199"><span class="lineNum">     199 </span><span class="lineCov">         12 :           valids_2_0 &lt;= io_write_way_mask_0 &amp; _GEN_8 | ~_GEN_8 &amp; valids_2_0;</span></a>
+<a name="200"><span class="lineNum">     200 </span><span class="lineCov">         12 :           valids_2_1 &lt;= io_write_way_mask_1 &amp; _GEN_8 | ~_GEN_8 &amp; valids_2_1;</span></a>
+<a name="201"><span class="lineNum">     201 </span><span class="lineCov">         12 :           valids_3_0 &lt;= io_write_way_mask_0 &amp; _GEN_9 | ~_GEN_9 &amp; valids_3_0;</span></a>
+<a name="202"><span class="lineNum">     202 </span><span class="lineCov">         12 :           valids_3_1 &lt;= io_write_way_mask_1 &amp; _GEN_9 | ~_GEN_9 &amp; valids_3_1;</span></a>
+<a name="203"><span class="lineNum">     203 </span><span class="lineCov">         12 :           valids_4_0 &lt;= io_write_way_mask_0 &amp; _GEN_10 | ~_GEN_10 &amp; valids_4_0;</span></a>
+<a name="204"><span class="lineNum">     204 </span><span class="lineCov">         12 :           valids_4_1 &lt;= io_write_way_mask_1 &amp; _GEN_10 | ~_GEN_10 &amp; valids_4_1;</span></a>
+<a name="205"><span class="lineNum">     205 </span><span class="lineCov">         12 :           valids_5_0 &lt;= io_write_way_mask_0 &amp; _GEN_11 | ~_GEN_11 &amp; valids_5_0;</span></a>
+<a name="206"><span class="lineNum">     206 </span><span class="lineCov">         12 :           valids_5_1 &lt;= io_write_way_mask_1 &amp; _GEN_11 | ~_GEN_11 &amp; valids_5_1;</span></a>
+<a name="207"><span class="lineNum">     207 </span><span class="lineCov">         12 :           valids_6_0 &lt;= io_write_way_mask_0 &amp; _GEN_12 | ~_GEN_12 &amp; valids_6_0;</span></a>
+<a name="208"><span class="lineNum">     208 </span><span class="lineCov">         12 :           valids_6_1 &lt;= io_write_way_mask_1 &amp; _GEN_12 | ~_GEN_12 &amp; valids_6_1;</span></a>
+<a name="209"><span class="lineNum">     209 </span><span class="lineCov">         12 :           valids_7_0 &lt;= io_write_way_mask_0 &amp; (&amp;enq_idx) | ~(&amp;enq_idx) &amp; valids_7_0;</span></a>
+<a name="210"><span class="lineNum">     210 </span><span class="lineCov">         12 :           valids_7_1 &lt;= io_write_way_mask_1 &amp; (&amp;enq_idx) | ~(&amp;enq_idx) &amp; valids_7_1;</span></a>
+<a name="211"><span class="lineNum">     211 </span>            :         end</a>
+<a name="212"><span class="lineNum">     212 </span><span class="lineCov">         12 :         state_reg &lt;=</span></a>
+<a name="213"><span class="lineNum">     213 </span><span class="lineCov">         12 :           {~(state_reg_touch_way_sized[2]),</span></a>
+<a name="214"><span class="lineNum">     214 </span><span class="lineCov">         12 :            state_reg_touch_way_sized[2]</span></a>
+<a name="215"><span class="lineNum">     215 </span><span class="lineCov">         12 :              ? {~(state_reg_touch_way_sized[1]),</span></a>
+<a name="216"><span class="lineNum">     216 </span><span class="lineCov">         12 :                 state_reg_touch_way_sized[1]</span></a>
+<a name="217"><span class="lineNum">     217 </span><span class="lineCov">         12 :                   ? ~(state_reg_touch_way_sized[0])</span></a>
+<a name="218"><span class="lineNum">     218 </span><span class="lineCov">         12 :                   : state_reg[4],</span></a>
+<a name="219"><span class="lineNum">     219 </span><span class="lineCov">         12 :                 state_reg_touch_way_sized[1]</span></a>
+<a name="220"><span class="lineNum">     220 </span><span class="lineCov">         12 :                   ? state_reg[3]</span></a>
+<a name="221"><span class="lineNum">     221 </span><span class="lineCov">         12 :                   : ~(state_reg_touch_way_sized[0])}</span></a>
+<a name="222"><span class="lineNum">     222 </span><span class="lineCov">         12 :              : state_reg[5:3],</span></a>
+<a name="223"><span class="lineNum">     223 </span><span class="lineCov">         12 :            state_reg_touch_way_sized[2]</span></a>
+<a name="224"><span class="lineNum">     224 </span><span class="lineCov">         12 :              ? state_reg[2:0]</span></a>
+<a name="225"><span class="lineNum">     225 </span><span class="lineCov">         12 :              : {~(state_reg_touch_way_sized[1]),</span></a>
+<a name="226"><span class="lineNum">     226 </span><span class="lineCov">         12 :                 state_reg_touch_way_sized[1]</span></a>
+<a name="227"><span class="lineNum">     227 </span><span class="lineCov">         12 :                   ? ~(state_reg_touch_way_sized[0])</span></a>
+<a name="228"><span class="lineNum">     228 </span><span class="lineCov">         12 :                   : state_reg[1],</span></a>
+<a name="229"><span class="lineNum">     229 </span><span class="lineCov">         12 :                 state_reg_touch_way_sized[1]</span></a>
+<a name="230"><span class="lineNum">     230 </span><span class="lineCov">         12 :                   ? state_reg[0]</span></a>
+<a name="231"><span class="lineNum">     231 </span><span class="lineCov">         12 :                   : ~(state_reg_touch_way_sized[0])}};</span></a>
+<a name="232"><span class="lineNum">     232 </span>            :       end</a>
+<a name="233"><span class="lineNum">     233 </span><span class="lineCov">      63729 :       ever_written_0 &lt;= io_wen &amp; ~hit &amp; (_GEN_6 | io_wen &amp; _GEN_6) | ever_written_0;</span></a>
+<a name="234"><span class="lineNum">     234 </span><span class="lineCov">      63729 :       ever_written_1 &lt;= io_wen &amp; ~hit &amp; (_GEN_7 | io_wen &amp; _GEN_7) | ever_written_1;</span></a>
+<a name="235"><span class="lineNum">     235 </span><span class="lineCov">      63729 :       ever_written_2 &lt;= io_wen &amp; ~hit &amp; (_GEN_8 | io_wen &amp; _GEN_8) | ever_written_2;</span></a>
+<a name="236"><span class="lineNum">     236 </span><span class="lineCov">      63729 :       ever_written_3 &lt;= io_wen &amp; ~hit &amp; (_GEN_9 | io_wen &amp; _GEN_9) | ever_written_3;</span></a>
+<a name="237"><span class="lineNum">     237 </span><span class="lineCov">      63729 :       ever_written_4 &lt;= io_wen &amp; ~hit &amp; (_GEN_10 | io_wen &amp; _GEN_10) | ever_written_4;</span></a>
+<a name="238"><span class="lineNum">     238 </span><span class="lineCov">      63729 :       ever_written_5 &lt;= io_wen &amp; ~hit &amp; (_GEN_11 | io_wen &amp; _GEN_11) | ever_written_5;</span></a>
+<a name="239"><span class="lineNum">     239 </span><span class="lineCov">      63729 :       ever_written_6 &lt;= io_wen &amp; ~hit &amp; (_GEN_12 | io_wen &amp; _GEN_12) | ever_written_6;</span></a>
+<a name="240"><span class="lineNum">     240 </span><span class="lineCov">      63729 :       ever_written_7 &lt;=</span></a>
+<a name="241"><span class="lineNum">     241 </span><span class="lineCov">      63729 :         io_wen &amp; ~hit &amp; ((&amp;enq_idx) | io_wen &amp; (&amp;enq_idx)) | ever_written_7;</span></a>
+<a name="242"><span class="lineNum">     242 </span>            :     end</a>
+<a name="243"><span class="lineNum">     243 </span>            :   end // always @(posedge, posedge)</a>
+<a name="244"><span class="lineNum">     244 </span>            :   `ifdef ENABLE_INITIAL_REG_</a>
+<a name="245"><span class="lineNum">     245 </span>            :     `ifdef FIRRTL_BEFORE_INITIAL</a>
+<a name="246"><span class="lineNum">     246 </span>            :       `FIRRTL_BEFORE_INITIAL</a>
+<a name="247"><span class="lineNum">     247 </span>            :     `endif // FIRRTL_BEFORE_INITIAL</a>
+<a name="248"><span class="lineNum">     248 </span>            :     logic [31:0] _RANDOM[0:0];</a>
+<a name="249"><span class="lineNum">     249 </span><span class="lineCov">         58 :     initial begin</span></a>
+<a name="250"><span class="lineNum">     250 </span>            :       `ifdef INIT_RANDOM_PROLOG_</a>
+<a name="251"><span class="lineNum">     251 </span>            :         `INIT_RANDOM_PROLOG_</a>
+<a name="252"><span class="lineNum">     252 </span>            :       `endif // INIT_RANDOM_PROLOG_</a>
+<a name="253"><span class="lineNum">     253 </span>            :       `ifdef RANDOMIZE_REG_INIT</a>
+<a name="254"><span class="lineNum">     254 </span>            :         _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;</a>
+<a name="255"><span class="lineNum">     255 </span>            :         valids_0_0 = _RANDOM[/*Zero width*/ 1'b0][0];</a>
+<a name="256"><span class="lineNum">     256 </span>            :         valids_0_1 = _RANDOM[/*Zero width*/ 1'b0][1];</a>
+<a name="257"><span class="lineNum">     257 </span>            :         valids_1_0 = _RANDOM[/*Zero width*/ 1'b0][2];</a>
+<a name="258"><span class="lineNum">     258 </span>            :         valids_1_1 = _RANDOM[/*Zero width*/ 1'b0][3];</a>
+<a name="259"><span class="lineNum">     259 </span>            :         valids_2_0 = _RANDOM[/*Zero width*/ 1'b0][4];</a>
+<a name="260"><span class="lineNum">     260 </span>            :         valids_2_1 = _RANDOM[/*Zero width*/ 1'b0][5];</a>
+<a name="261"><span class="lineNum">     261 </span>            :         valids_3_0 = _RANDOM[/*Zero width*/ 1'b0][6];</a>
+<a name="262"><span class="lineNum">     262 </span>            :         valids_3_1 = _RANDOM[/*Zero width*/ 1'b0][7];</a>
+<a name="263"><span class="lineNum">     263 </span>            :         valids_4_0 = _RANDOM[/*Zero width*/ 1'b0][8];</a>
+<a name="264"><span class="lineNum">     264 </span>            :         valids_4_1 = _RANDOM[/*Zero width*/ 1'b0][9];</a>
+<a name="265"><span class="lineNum">     265 </span>            :         valids_5_0 = _RANDOM[/*Zero width*/ 1'b0][10];</a>
+<a name="266"><span class="lineNum">     266 </span>            :         valids_5_1 = _RANDOM[/*Zero width*/ 1'b0][11];</a>
+<a name="267"><span class="lineNum">     267 </span>            :         valids_6_0 = _RANDOM[/*Zero width*/ 1'b0][12];</a>
+<a name="268"><span class="lineNum">     268 </span>            :         valids_6_1 = _RANDOM[/*Zero width*/ 1'b0][13];</a>
+<a name="269"><span class="lineNum">     269 </span>            :         valids_7_0 = _RANDOM[/*Zero width*/ 1'b0][14];</a>
+<a name="270"><span class="lineNum">     270 </span>            :         valids_7_1 = _RANDOM[/*Zero width*/ 1'b0][15];</a>
+<a name="271"><span class="lineNum">     271 </span>            :         ever_written_0 = _RANDOM[/*Zero width*/ 1'b0][16];</a>
+<a name="272"><span class="lineNum">     272 </span>            :         ever_written_1 = _RANDOM[/*Zero width*/ 1'b0][17];</a>
+<a name="273"><span class="lineNum">     273 </span>            :         ever_written_2 = _RANDOM[/*Zero width*/ 1'b0][18];</a>
+<a name="274"><span class="lineNum">     274 </span>            :         ever_written_3 = _RANDOM[/*Zero width*/ 1'b0][19];</a>
+<a name="275"><span class="lineNum">     275 </span>            :         ever_written_4 = _RANDOM[/*Zero width*/ 1'b0][20];</a>
+<a name="276"><span class="lineNum">     276 </span>            :         ever_written_5 = _RANDOM[/*Zero width*/ 1'b0][21];</a>
+<a name="277"><span class="lineNum">     277 </span>            :         ever_written_6 = _RANDOM[/*Zero width*/ 1'b0][22];</a>
+<a name="278"><span class="lineNum">     278 </span>            :         ever_written_7 = _RANDOM[/*Zero width*/ 1'b0][23];</a>
+<a name="279"><span class="lineNum">     279 </span>            :         state_reg = _RANDOM[/*Zero width*/ 1'b0][30:24];</a>
+<a name="280"><span class="lineNum">     280 </span>            :       `endif // RANDOMIZE_REG_INIT</a>
+<a name="281"><span class="lineNum">     281 </span><span class="lineCov">         17 :       if (reset) begin</span></a>
+<a name="282"><span class="lineNum">     282 </span><span class="lineCov">         12 :         valids_0_0 = 1'h0;</span></a>
+<a name="283"><span class="lineNum">     283 </span><span class="lineCov">         12 :         valids_0_1 = 1'h0;</span></a>
+<a name="284"><span class="lineNum">     284 </span><span class="lineCov">         12 :         valids_1_0 = 1'h0;</span></a>
+<a name="285"><span class="lineNum">     285 </span><span class="lineCov">         12 :         valids_1_1 = 1'h0;</span></a>
+<a name="286"><span class="lineNum">     286 </span><span class="lineCov">         12 :         valids_2_0 = 1'h0;</span></a>
+<a name="287"><span class="lineNum">     287 </span><span class="lineCov">         12 :         valids_2_1 = 1'h0;</span></a>
+<a name="288"><span class="lineNum">     288 </span><span class="lineCov">         12 :         valids_3_0 = 1'h0;</span></a>
+<a name="289"><span class="lineNum">     289 </span><span class="lineCov">         12 :         valids_3_1 = 1'h0;</span></a>
+<a name="290"><span class="lineNum">     290 </span><span class="lineCov">         12 :         valids_4_0 = 1'h0;</span></a>
+<a name="291"><span class="lineNum">     291 </span><span class="lineCov">         12 :         valids_4_1 = 1'h0;</span></a>
+<a name="292"><span class="lineNum">     292 </span><span class="lineCov">         12 :         valids_5_0 = 1'h0;</span></a>
+<a name="293"><span class="lineNum">     293 </span><span class="lineCov">         12 :         valids_5_1 = 1'h0;</span></a>
+<a name="294"><span class="lineNum">     294 </span><span class="lineCov">         12 :         valids_6_0 = 1'h0;</span></a>
+<a name="295"><span class="lineNum">     295 </span><span class="lineCov">         12 :         valids_6_1 = 1'h0;</span></a>
+<a name="296"><span class="lineNum">     296 </span><span class="lineCov">         12 :         valids_7_0 = 1'h0;</span></a>
+<a name="297"><span class="lineNum">     297 </span><span class="lineCov">         12 :         valids_7_1 = 1'h0;</span></a>
+<a name="298"><span class="lineNum">     298 </span><span class="lineCov">         12 :         ever_written_0 = 1'h0;</span></a>
+<a name="299"><span class="lineNum">     299 </span><span class="lineCov">         12 :         ever_written_1 = 1'h0;</span></a>
+<a name="300"><span class="lineNum">     300 </span><span class="lineCov">         12 :         ever_written_2 = 1'h0;</span></a>
+<a name="301"><span class="lineNum">     301 </span><span class="lineCov">         12 :         ever_written_3 = 1'h0;</span></a>
+<a name="302"><span class="lineNum">     302 </span><span class="lineCov">         12 :         ever_written_4 = 1'h0;</span></a>
+<a name="303"><span class="lineNum">     303 </span><span class="lineCov">         12 :         ever_written_5 = 1'h0;</span></a>
+<a name="304"><span class="lineNum">     304 </span><span class="lineCov">         12 :         ever_written_6 = 1'h0;</span></a>
+<a name="305"><span class="lineNum">     305 </span><span class="lineCov">         12 :         ever_written_7 = 1'h0;</span></a>
+<a name="306"><span class="lineNum">     306 </span><span class="lineCov">         12 :         state_reg = 7'h0;</span></a>
+<a name="307"><span class="lineNum">     307 </span>            :       end</a>
+<a name="308"><span class="lineNum">     308 </span>            :     end // initial</a>
+<a name="309"><span class="lineNum">     309 </span>            :     `ifdef FIRRTL_AFTER_INITIAL</a>
+<a name="310"><span class="lineNum">     310 </span>            :       `FIRRTL_AFTER_INITIAL</a>
+<a name="311"><span class="lineNum">     311 </span>            :     `endif // FIRRTL_AFTER_INITIAL</a>
+<a name="312"><span class="lineNum">     312 </span>            :   `endif // ENABLE_INITIAL_REG_</a>
+<a name="313"><span class="lineNum">     313 </span>            :   CAMTemplate_32 idx_tag_cam (</a>
+<a name="314"><span class="lineNum">     314 </span>            :     .clock              (clock),</a>
+<a name="315"><span class="lineNum">     315 </span>            :     .io_r_req_0_idx     (io_write_idx),</a>
+<a name="316"><span class="lineNum">     316 </span>            :     .io_r_resp_0_0      (_idx_tag_cam_io_r_resp_0_0),</a>
+<a name="317"><span class="lineNum">     317 </span>            :     .io_r_resp_0_1      (_idx_tag_cam_io_r_resp_0_1),</a>
+<a name="318"><span class="lineNum">     318 </span>            :     .io_r_resp_0_2      (_idx_tag_cam_io_r_resp_0_2),</a>
+<a name="319"><span class="lineNum">     319 </span>            :     .io_r_resp_0_3      (_idx_tag_cam_io_r_resp_0_3),</a>
+<a name="320"><span class="lineNum">     320 </span>            :     .io_r_resp_0_4      (_idx_tag_cam_io_r_resp_0_4),</a>
+<a name="321"><span class="lineNum">     321 </span>            :     .io_r_resp_0_5      (_idx_tag_cam_io_r_resp_0_5),</a>
+<a name="322"><span class="lineNum">     322 </span>            :     .io_r_resp_0_6      (_idx_tag_cam_io_r_resp_0_6),</a>
+<a name="323"><span class="lineNum">     323 </span>            :     .io_r_resp_0_7      (_idx_tag_cam_io_r_resp_0_7),</a>
+<a name="324"><span class="lineNum">     324 </span>            :     .io_w_valid         (io_wen &amp; ~hit),</a>
+<a name="325"><span class="lineNum">     325 </span>            :     .io_w_bits_data_idx (io_write_idx),</a>
+<a name="326"><span class="lineNum">     326 </span>            :     .io_w_bits_index    (enq_idx)</a>
+<a name="327"><span class="lineNum">     327 </span>            :   );</a>
+<a name="328"><span class="lineNum">     328 </span>            :   data_mem_8x4 data_mem_ext (</a>
+<a name="329"><span class="lineNum">     329 </span>            :     .R0_addr (hit_idx),</a>
+<a name="330"><span class="lineNum">     330 </span>            :     .R0_en   (1'h1),</a>
+<a name="331"><span class="lineNum">     331 </span>            :     .R0_clk  (clock),</a>
+<a name="332"><span class="lineNum">     332 </span>            :     .R0_data (_data_mem_ext_R0_data),</a>
+<a name="333"><span class="lineNum">     333 </span>            :     .R1_addr (hit_idx),</a>
+<a name="334"><span class="lineNum">     334 </span>            :     .R1_en   (1'h1),</a>
+<a name="335"><span class="lineNum">     335 </span>            :     .R1_clk  (clock),</a>
+<a name="336"><span class="lineNum">     336 </span>            :     .R1_data (_data_mem_ext_R1_data),</a>
+<a name="337"><span class="lineNum">     337 </span>            :     .W0_addr (hit ? hit_idx : enq_idx),</a>
+<a name="338"><span class="lineNum">     338 </span>            :     .W0_en   (io_wen),</a>
+<a name="339"><span class="lineNum">     339 </span>            :     .W0_clk  (clock),</a>
+<a name="340"><span class="lineNum">     340 </span>            :     .W0_data ({io_write_data_1, io_write_data_0}),</a>
+<a name="341"><span class="lineNum">     341 </span>            :     .W0_mask ({io_write_way_mask_1, io_write_way_mask_0})</a>
+<a name="342"><span class="lineNum">     342 </span>            :   );</a>
+<a name="343"><span class="lineNum">     343 </span>            :   assign io_hit = hit;</a>
+<a name="344"><span class="lineNum">     344 </span>            :   assign io_hit_data_0_valid =</a>
+<a name="345"><span class="lineNum">     345 </span>            :     hits_oh_0 &amp; valids_0_0 | hits_oh_1 &amp; valids_1_0 | hits_oh_2 &amp; valids_2_0 | hits_oh_3</a>
+<a name="346"><span class="lineNum">     346 </span>            :     &amp; valids_3_0 | hits_oh_4 &amp; valids_4_0 | hits_oh_5 &amp; valids_5_0 | hits_oh_6</a>
+<a name="347"><span class="lineNum">     347 </span>            :     &amp; valids_6_0 | hits_oh_7 &amp; valids_7_0;</a>
+<a name="348"><span class="lineNum">     348 </span>            :   assign io_hit_data_0_bits = _data_mem_ext_R1_data[1:0];</a>
+<a name="349"><span class="lineNum">     349 </span>            :   assign io_hit_data_1_valid =</a>
+<a name="350"><span class="lineNum">     350 </span>            :     hits_oh_0 &amp; valids_0_1 | hits_oh_1 &amp; valids_1_1 | hits_oh_2 &amp; valids_2_1 | hits_oh_3</a>
+<a name="351"><span class="lineNum">     351 </span>            :     &amp; valids_3_1 | hits_oh_4 &amp; valids_4_1 | hits_oh_5 &amp; valids_5_1 | hits_oh_6</a>
+<a name="352"><span class="lineNum">     352 </span>            :     &amp; valids_6_1 | hits_oh_7 &amp; valids_7_1;</a>
+<a name="353"><span class="lineNum">     353 </span>            :   assign io_hit_data_1_bits = _data_mem_ext_R0_data[3:2];</a>
+<a name="354"><span class="lineNum">     354 </span>            : endmodule</a>
+<a name="355"><span class="lineNum">     355 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/WrBypass_33.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/WrBypass_33.sv.func-sort-c.html
new file mode 100644
index 0000000..1270bd4
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/WrBypass_33.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/WrBypass_33.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - WrBypass_33.sv<span style="font-size: 80%;"> (<a href="WrBypass_33.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">313</td>
+            <td class="headerCovTableEntry">313</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="WrBypass_33.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/WrBypass_33.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/WrBypass_33.sv.func.html
new file mode 100644
index 0000000..4d359fe
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/WrBypass_33.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/WrBypass_33.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - WrBypass_33.sv<span style="font-size: 80%;"> (<a href="WrBypass_33.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">313</td>
+            <td class="headerCovTableEntry">313</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="WrBypass_33.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/WrBypass_33.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/WrBypass_33.sv.gcov.html
new file mode 100644
index 0000000..13895a8
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/WrBypass_33.sv.gcov.html
@@ -0,0 +1,656 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/WrBypass_33.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - WrBypass_33.sv<span style="font-size: 80%;"> (source / <a href="WrBypass_33.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">313</td>
+            <td class="headerCovTableEntry">313</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : module WrBypass_33(</a>
+<a name="59"><span class="lineNum">      59 </span><span class="lineCov">     127786 :   input        clock,</span></a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">         62 :   input        reset,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">         29 :   input        io_wen,</span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">        131 :   input  [7:0] io_write_idx,</span></a>
+<a name="63"><span class="lineNum">      63 </span><span class="lineCov">       1012 :   input  [5:0] io_write_data_0,</span></a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">        979 :   input  [5:0] io_write_data_1,</span></a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">        179 :   input        io_write_way_mask_0,</span></a>
+<a name="66"><span class="lineNum">      66 </span><span class="lineCov">        179 :   input        io_write_way_mask_1,</span></a>
+<a name="67"><span class="lineNum">      67 </span><span class="lineCov">        248 :   output       io_hit,</span></a>
+<a name="68"><span class="lineNum">      68 </span><span class="lineCov">        191 :   output       io_hit_data_0_valid,</span></a>
+<a name="69"><span class="lineNum">      69 </span><span class="lineCov">       1213 :   output [5:0] io_hit_data_0_bits,</span></a>
+<a name="70"><span class="lineNum">      70 </span><span class="lineCov">        176 :   output       io_hit_data_1_valid,</span></a>
+<a name="71"><span class="lineNum">      71 </span><span class="lineCov">       1147 :   output [5:0] io_hit_data_1_bits</span></a>
+<a name="72"><span class="lineNum">      72 </span>            : );</a>
+<a name="73"><span class="lineNum">      73 </span>            : </a>
+<a name="74"><span class="lineNum">      74 </span>            :   wire [11:0] _data_mem_ext_R0_data;</a>
+<a name="75"><span class="lineNum">      75 </span>            :   wire [11:0] _data_mem_ext_R1_data;</a>
+<a name="76"><span class="lineNum">      76 </span>            :   wire        _idx_tag_cam_io_r_resp_0_0;</a>
+<a name="77"><span class="lineNum">      77 </span>            :   wire        _idx_tag_cam_io_r_resp_0_1;</a>
+<a name="78"><span class="lineNum">      78 </span>            :   wire        _idx_tag_cam_io_r_resp_0_2;</a>
+<a name="79"><span class="lineNum">      79 </span>            :   wire        _idx_tag_cam_io_r_resp_0_3;</a>
+<a name="80"><span class="lineNum">      80 </span>            :   wire        _idx_tag_cam_io_r_resp_0_4;</a>
+<a name="81"><span class="lineNum">      81 </span>            :   wire        _idx_tag_cam_io_r_resp_0_5;</a>
+<a name="82"><span class="lineNum">      82 </span>            :   wire        _idx_tag_cam_io_r_resp_0_6;</a>
+<a name="83"><span class="lineNum">      83 </span>            :   wire        _idx_tag_cam_io_r_resp_0_7;</a>
+<a name="84"><span class="lineNum">      84 </span>            :   wire        _idx_tag_cam_io_r_resp_0_8;</a>
+<a name="85"><span class="lineNum">      85 </span>            :   wire        _idx_tag_cam_io_r_resp_0_9;</a>
+<a name="86"><span class="lineNum">      86 </span>            :   wire        _idx_tag_cam_io_r_resp_0_10;</a>
+<a name="87"><span class="lineNum">      87 </span>            :   wire        _idx_tag_cam_io_r_resp_0_11;</a>
+<a name="88"><span class="lineNum">      88 </span>            :   wire        _idx_tag_cam_io_r_resp_0_12;</a>
+<a name="89"><span class="lineNum">      89 </span>            :   wire        _idx_tag_cam_io_r_resp_0_13;</a>
+<a name="90"><span class="lineNum">      90 </span>            :   wire        _idx_tag_cam_io_r_resp_0_14;</a>
+<a name="91"><span class="lineNum">      91 </span>            :   wire        _idx_tag_cam_io_r_resp_0_15;</a>
+<a name="92"><span class="lineNum">      92 </span><span class="lineCov">        190 :   reg         valids_0_0;</span></a>
+<a name="93"><span class="lineNum">      93 </span><span class="lineCov">        181 :   reg         valids_0_1;</span></a>
+<a name="94"><span class="lineNum">      94 </span><span class="lineCov">        186 :   reg         valids_1_0;</span></a>
+<a name="95"><span class="lineNum">      95 </span><span class="lineCov">        204 :   reg         valids_1_1;</span></a>
+<a name="96"><span class="lineNum">      96 </span><span class="lineCov">        177 :   reg         valids_2_0;</span></a>
+<a name="97"><span class="lineNum">      97 </span><span class="lineCov">        170 :   reg         valids_2_1;</span></a>
+<a name="98"><span class="lineNum">      98 </span><span class="lineCov">        173 :   reg         valids_3_0;</span></a>
+<a name="99"><span class="lineNum">      99 </span><span class="lineCov">        188 :   reg         valids_3_1;</span></a>
+<a name="100"><span class="lineNum">     100 </span><span class="lineCov">        180 :   reg         valids_4_0;</span></a>
+<a name="101"><span class="lineNum">     101 </span><span class="lineCov">        172 :   reg         valids_4_1;</span></a>
+<a name="102"><span class="lineNum">     102 </span><span class="lineCov">        169 :   reg         valids_5_0;</span></a>
+<a name="103"><span class="lineNum">     103 </span><span class="lineCov">        182 :   reg         valids_5_1;</span></a>
+<a name="104"><span class="lineNum">     104 </span><span class="lineCov">        175 :   reg         valids_6_0;</span></a>
+<a name="105"><span class="lineNum">     105 </span><span class="lineCov">        199 :   reg         valids_6_1;</span></a>
+<a name="106"><span class="lineNum">     106 </span><span class="lineCov">        192 :   reg         valids_7_0;</span></a>
+<a name="107"><span class="lineNum">     107 </span><span class="lineCov">        190 :   reg         valids_7_1;</span></a>
+<a name="108"><span class="lineNum">     108 </span><span class="lineCov">        166 :   reg         valids_8_0;</span></a>
+<a name="109"><span class="lineNum">     109 </span><span class="lineCov">        177 :   reg         valids_8_1;</span></a>
+<a name="110"><span class="lineNum">     110 </span><span class="lineCov">        201 :   reg         valids_9_0;</span></a>
+<a name="111"><span class="lineNum">     111 </span><span class="lineCov">        191 :   reg         valids_9_1;</span></a>
+<a name="112"><span class="lineNum">     112 </span><span class="lineCov">        206 :   reg         valids_10_0;</span></a>
+<a name="113"><span class="lineNum">     113 </span><span class="lineCov">        187 :   reg         valids_10_1;</span></a>
+<a name="114"><span class="lineNum">     114 </span><span class="lineCov">        194 :   reg         valids_11_0;</span></a>
+<a name="115"><span class="lineNum">     115 </span><span class="lineCov">        200 :   reg         valids_11_1;</span></a>
+<a name="116"><span class="lineNum">     116 </span><span class="lineCov">        200 :   reg         valids_12_0;</span></a>
+<a name="117"><span class="lineNum">     117 </span><span class="lineCov">        184 :   reg         valids_12_1;</span></a>
+<a name="118"><span class="lineNum">     118 </span><span class="lineCov">        184 :   reg         valids_13_0;</span></a>
+<a name="119"><span class="lineNum">     119 </span><span class="lineCov">        200 :   reg         valids_13_1;</span></a>
+<a name="120"><span class="lineNum">     120 </span><span class="lineCov">        192 :   reg         valids_14_0;</span></a>
+<a name="121"><span class="lineNum">     121 </span><span class="lineCov">        172 :   reg         valids_14_1;</span></a>
+<a name="122"><span class="lineNum">     122 </span><span class="lineCov">        189 :   reg         valids_15_0;</span></a>
+<a name="123"><span class="lineNum">     123 </span><span class="lineCov">        203 :   reg         valids_15_1;</span></a>
+<a name="124"><span class="lineNum">     124 </span><span class="lineCov">        204 :   reg         ever_written_0;</span></a>
+<a name="125"><span class="lineNum">     125 </span><span class="lineCov">        192 :   reg         ever_written_1;</span></a>
+<a name="126"><span class="lineNum">     126 </span><span class="lineCov">        184 :   reg         ever_written_2;</span></a>
+<a name="127"><span class="lineNum">     127 </span><span class="lineCov">        188 :   reg         ever_written_3;</span></a>
+<a name="128"><span class="lineNum">     128 </span><span class="lineCov">        213 :   reg         ever_written_4;</span></a>
+<a name="129"><span class="lineNum">     129 </span><span class="lineCov">        192 :   reg         ever_written_5;</span></a>
+<a name="130"><span class="lineNum">     130 </span><span class="lineCov">        191 :   reg         ever_written_6;</span></a>
+<a name="131"><span class="lineNum">     131 </span><span class="lineCov">        194 :   reg         ever_written_7;</span></a>
+<a name="132"><span class="lineNum">     132 </span><span class="lineCov">        178 :   reg         ever_written_8;</span></a>
+<a name="133"><span class="lineNum">     133 </span><span class="lineCov">        203 :   reg         ever_written_9;</span></a>
+<a name="134"><span class="lineNum">     134 </span><span class="lineCov">        183 :   reg         ever_written_10;</span></a>
+<a name="135"><span class="lineNum">     135 </span><span class="lineCov">        184 :   reg         ever_written_11;</span></a>
+<a name="136"><span class="lineNum">     136 </span><span class="lineCov">        178 :   reg         ever_written_12;</span></a>
+<a name="137"><span class="lineNum">     137 </span><span class="lineCov">        192 :   reg         ever_written_13;</span></a>
+<a name="138"><span class="lineNum">     138 </span><span class="lineCov">        177 :   reg         ever_written_14;</span></a>
+<a name="139"><span class="lineNum">     139 </span><span class="lineCov">        193 :   reg         ever_written_15;</span></a>
+<a name="140"><span class="lineNum">     140 </span><span class="lineCov">        131 :   wire        hits_oh_0 = _idx_tag_cam_io_r_resp_0_0 &amp; ever_written_0;</span></a>
+<a name="141"><span class="lineNum">     141 </span><span class="lineCov">        131 :   wire        hits_oh_1 = _idx_tag_cam_io_r_resp_0_1 &amp; ever_written_1;</span></a>
+<a name="142"><span class="lineNum">     142 </span><span class="lineCov">        112 :   wire        hits_oh_2 = _idx_tag_cam_io_r_resp_0_2 &amp; ever_written_2;</span></a>
+<a name="143"><span class="lineNum">     143 </span><span class="lineCov">        118 :   wire        hits_oh_3 = _idx_tag_cam_io_r_resp_0_3 &amp; ever_written_3;</span></a>
+<a name="144"><span class="lineNum">     144 </span><span class="lineCov">        132 :   wire        hits_oh_4 = _idx_tag_cam_io_r_resp_0_4 &amp; ever_written_4;</span></a>
+<a name="145"><span class="lineNum">     145 </span><span class="lineCov">        129 :   wire        hits_oh_5 = _idx_tag_cam_io_r_resp_0_5 &amp; ever_written_5;</span></a>
+<a name="146"><span class="lineNum">     146 </span><span class="lineCov">        122 :   wire        hits_oh_6 = _idx_tag_cam_io_r_resp_0_6 &amp; ever_written_6;</span></a>
+<a name="147"><span class="lineNum">     147 </span><span class="lineCov">        108 :   wire        hits_oh_7 = _idx_tag_cam_io_r_resp_0_7 &amp; ever_written_7;</span></a>
+<a name="148"><span class="lineNum">     148 </span><span class="lineCov">        121 :   wire        hits_oh_8 = _idx_tag_cam_io_r_resp_0_8 &amp; ever_written_8;</span></a>
+<a name="149"><span class="lineNum">     149 </span><span class="lineCov">        127 :   wire        hits_oh_9 = _idx_tag_cam_io_r_resp_0_9 &amp; ever_written_9;</span></a>
+<a name="150"><span class="lineNum">     150 </span><span class="lineCov">        124 :   wire        hits_oh_10 = _idx_tag_cam_io_r_resp_0_10 &amp; ever_written_10;</span></a>
+<a name="151"><span class="lineNum">     151 </span><span class="lineCov">        117 :   wire        hits_oh_11 = _idx_tag_cam_io_r_resp_0_11 &amp; ever_written_11;</span></a>
+<a name="152"><span class="lineNum">     152 </span><span class="lineCov">        123 :   wire        hits_oh_12 = _idx_tag_cam_io_r_resp_0_12 &amp; ever_written_12;</span></a>
+<a name="153"><span class="lineNum">     153 </span><span class="lineCov">        102 :   wire        hits_oh_13 = _idx_tag_cam_io_r_resp_0_13 &amp; ever_written_13;</span></a>
+<a name="154"><span class="lineNum">     154 </span><span class="lineCov">        105 :   wire        hits_oh_14 = _idx_tag_cam_io_r_resp_0_14 &amp; ever_written_14;</span></a>
+<a name="155"><span class="lineNum">     155 </span><span class="lineCov">        116 :   wire        hits_oh_15 = _idx_tag_cam_io_r_resp_0_15 &amp; ever_written_15;</span></a>
+<a name="156"><span class="lineNum">     156 </span>            :   wire [6:0]  _hit_idx_T_2 =</a>
+<a name="157"><span class="lineNum">     157 </span>            :     {hits_oh_15, hits_oh_14, hits_oh_13, hits_oh_12, hits_oh_11, hits_oh_10, hits_oh_9}</a>
+<a name="158"><span class="lineNum">     158 </span>            :     | {hits_oh_7, hits_oh_6, hits_oh_5, hits_oh_4, hits_oh_3, hits_oh_2, hits_oh_1};</a>
+<a name="159"><span class="lineNum">     159 </span>            :   wire [2:0]  _hit_idx_T_4 = _hit_idx_T_2[6:4] | _hit_idx_T_2[2:0];</a>
+<a name="160"><span class="lineNum">     160 </span><span class="lineCov">        706 :   wire [3:0]  hit_idx =</span></a>
+<a name="161"><span class="lineNum">     161 </span>            :     {|{hits_oh_15,</a>
+<a name="162"><span class="lineNum">     162 </span>            :        hits_oh_14,</a>
+<a name="163"><span class="lineNum">     163 </span>            :        hits_oh_13,</a>
+<a name="164"><span class="lineNum">     164 </span>            :        hits_oh_12,</a>
+<a name="165"><span class="lineNum">     165 </span>            :        hits_oh_11,</a>
+<a name="166"><span class="lineNum">     166 </span>            :        hits_oh_10,</a>
+<a name="167"><span class="lineNum">     167 </span>            :        hits_oh_9,</a>
+<a name="168"><span class="lineNum">     168 </span>            :        hits_oh_8},</a>
+<a name="169"><span class="lineNum">     169 </span>            :      |(_hit_idx_T_2[6:3]),</a>
+<a name="170"><span class="lineNum">     170 </span>            :      |(_hit_idx_T_4[2:1]),</a>
+<a name="171"><span class="lineNum">     171 </span>            :      _hit_idx_T_4[2] | _hit_idx_T_4[0]};</a>
+<a name="172"><span class="lineNum">     172 </span><span class="lineCov">        248 :   wire        hit =</span></a>
+<a name="173"><span class="lineNum">     173 </span>            :     hits_oh_0 | hits_oh_1 | hits_oh_2 | hits_oh_3 | hits_oh_4 | hits_oh_5 | hits_oh_6</a>
+<a name="174"><span class="lineNum">     174 </span>            :     | hits_oh_7 | hits_oh_8 | hits_oh_9 | hits_oh_10 | hits_oh_11 | hits_oh_12</a>
+<a name="175"><span class="lineNum">     175 </span>            :     | hits_oh_13 | hits_oh_14 | hits_oh_15;</a>
+<a name="176"><span class="lineNum">     176 </span><span class="lineCov">       3028 :   reg  [14:0] state_reg;</span></a>
+<a name="177"><span class="lineNum">     177 </span><span class="lineCov">        926 :   wire [3:0]  enq_idx =</span></a>
+<a name="178"><span class="lineNum">     178 </span>            :     {state_reg[14],</a>
+<a name="179"><span class="lineNum">     179 </span>            :      state_reg[14]</a>
+<a name="180"><span class="lineNum">     180 </span>            :        ? {state_reg[13],</a>
+<a name="181"><span class="lineNum">     181 </span>            :           state_reg[13]</a>
+<a name="182"><span class="lineNum">     182 </span>            :             ? {state_reg[12], state_reg[12] ? state_reg[11] : state_reg[10]}</a>
+<a name="183"><span class="lineNum">     183 </span>            :             : {state_reg[9], state_reg[9] ? state_reg[8] : state_reg[7]}}</a>
+<a name="184"><span class="lineNum">     184 </span>            :        : {state_reg[6],</a>
+<a name="185"><span class="lineNum">     185 </span>            :           state_reg[6]</a>
+<a name="186"><span class="lineNum">     186 </span>            :             ? {state_reg[5], state_reg[5] ? state_reg[4] : state_reg[3]}</a>
+<a name="187"><span class="lineNum">     187 </span>            :             : {state_reg[2], state_reg[2] ? state_reg[1] : state_reg[0]}}};</a>
+<a name="188"><span class="lineNum">     188 </span>            :   wire        _GEN = hit_idx == 4'h0;</a>
+<a name="189"><span class="lineNum">     189 </span>            :   wire        _GEN_0 = hit_idx == 4'h1;</a>
+<a name="190"><span class="lineNum">     190 </span>            :   wire        _GEN_1 = hit_idx == 4'h2;</a>
+<a name="191"><span class="lineNum">     191 </span>            :   wire        _GEN_2 = hit_idx == 4'h3;</a>
+<a name="192"><span class="lineNum">     192 </span>            :   wire        _GEN_3 = hit_idx == 4'h4;</a>
+<a name="193"><span class="lineNum">     193 </span>            :   wire        _GEN_4 = hit_idx == 4'h5;</a>
+<a name="194"><span class="lineNum">     194 </span>            :   wire        _GEN_5 = hit_idx == 4'h6;</a>
+<a name="195"><span class="lineNum">     195 </span>            :   wire        _GEN_6 = hit_idx == 4'h7;</a>
+<a name="196"><span class="lineNum">     196 </span>            :   wire        _GEN_7 = hit_idx == 4'h8;</a>
+<a name="197"><span class="lineNum">     197 </span>            :   wire        _GEN_8 = hit_idx == 4'h9;</a>
+<a name="198"><span class="lineNum">     198 </span>            :   wire        _GEN_9 = hit_idx == 4'hA;</a>
+<a name="199"><span class="lineNum">     199 </span>            :   wire        _GEN_10 = hit_idx == 4'hB;</a>
+<a name="200"><span class="lineNum">     200 </span>            :   wire        _GEN_11 = hit_idx == 4'hC;</a>
+<a name="201"><span class="lineNum">     201 </span>            :   wire        _GEN_12 = hit_idx == 4'hD;</a>
+<a name="202"><span class="lineNum">     202 </span>            :   wire        _GEN_13 = hit_idx == 4'hE;</a>
+<a name="203"><span class="lineNum">     203 </span><span class="lineCov">        762 :   wire [3:0]  state_reg_touch_way_sized = hit ? hit_idx : enq_idx;</span></a>
+<a name="204"><span class="lineNum">     204 </span>            :   wire        _GEN_14 = enq_idx == 4'h0;</a>
+<a name="205"><span class="lineNum">     205 </span>            :   wire        _GEN_15 = enq_idx == 4'h1;</a>
+<a name="206"><span class="lineNum">     206 </span>            :   wire        _GEN_16 = enq_idx == 4'h2;</a>
+<a name="207"><span class="lineNum">     207 </span>            :   wire        _GEN_17 = enq_idx == 4'h3;</a>
+<a name="208"><span class="lineNum">     208 </span>            :   wire        _GEN_18 = enq_idx == 4'h4;</a>
+<a name="209"><span class="lineNum">     209 </span>            :   wire        _GEN_19 = enq_idx == 4'h5;</a>
+<a name="210"><span class="lineNum">     210 </span>            :   wire        _GEN_20 = enq_idx == 4'h6;</a>
+<a name="211"><span class="lineNum">     211 </span>            :   wire        _GEN_21 = enq_idx == 4'h7;</a>
+<a name="212"><span class="lineNum">     212 </span>            :   wire        _GEN_22 = enq_idx == 4'h8;</a>
+<a name="213"><span class="lineNum">     213 </span>            :   wire        _GEN_23 = enq_idx == 4'h9;</a>
+<a name="214"><span class="lineNum">     214 </span>            :   wire        _GEN_24 = enq_idx == 4'hA;</a>
+<a name="215"><span class="lineNum">     215 </span>            :   wire        _GEN_25 = enq_idx == 4'hB;</a>
+<a name="216"><span class="lineNum">     216 </span>            :   wire        _GEN_26 = enq_idx == 4'hC;</a>
+<a name="217"><span class="lineNum">     217 </span>            :   wire        _GEN_27 = enq_idx == 4'hD;</a>
+<a name="218"><span class="lineNum">     218 </span>            :   wire        _GEN_28 = enq_idx == 4'hE;</a>
+<a name="219"><span class="lineNum">     219 </span><span class="lineCov">    1021840 :   always @(posedge clock or posedge reset) begin</span></a>
+<a name="220"><span class="lineNum">     220 </span><span class="lineCov">       2176 :     if (reset) begin</span></a>
+<a name="221"><span class="lineNum">     221 </span><span class="lineCov">       1088 :       valids_0_0 &lt;= 1'h0;</span></a>
+<a name="222"><span class="lineNum">     222 </span><span class="lineCov">       1088 :       valids_0_1 &lt;= 1'h0;</span></a>
+<a name="223"><span class="lineNum">     223 </span><span class="lineCov">       1088 :       valids_1_0 &lt;= 1'h0;</span></a>
+<a name="224"><span class="lineNum">     224 </span><span class="lineCov">       1088 :       valids_1_1 &lt;= 1'h0;</span></a>
+<a name="225"><span class="lineNum">     225 </span><span class="lineCov">       1088 :       valids_2_0 &lt;= 1'h0;</span></a>
+<a name="226"><span class="lineNum">     226 </span><span class="lineCov">       1088 :       valids_2_1 &lt;= 1'h0;</span></a>
+<a name="227"><span class="lineNum">     227 </span><span class="lineCov">       1088 :       valids_3_0 &lt;= 1'h0;</span></a>
+<a name="228"><span class="lineNum">     228 </span><span class="lineCov">       1088 :       valids_3_1 &lt;= 1'h0;</span></a>
+<a name="229"><span class="lineNum">     229 </span><span class="lineCov">       1088 :       valids_4_0 &lt;= 1'h0;</span></a>
+<a name="230"><span class="lineNum">     230 </span><span class="lineCov">       1088 :       valids_4_1 &lt;= 1'h0;</span></a>
+<a name="231"><span class="lineNum">     231 </span><span class="lineCov">       1088 :       valids_5_0 &lt;= 1'h0;</span></a>
+<a name="232"><span class="lineNum">     232 </span><span class="lineCov">       1088 :       valids_5_1 &lt;= 1'h0;</span></a>
+<a name="233"><span class="lineNum">     233 </span><span class="lineCov">       1088 :       valids_6_0 &lt;= 1'h0;</span></a>
+<a name="234"><span class="lineNum">     234 </span><span class="lineCov">       1088 :       valids_6_1 &lt;= 1'h0;</span></a>
+<a name="235"><span class="lineNum">     235 </span><span class="lineCov">       1088 :       valids_7_0 &lt;= 1'h0;</span></a>
+<a name="236"><span class="lineNum">     236 </span><span class="lineCov">       1088 :       valids_7_1 &lt;= 1'h0;</span></a>
+<a name="237"><span class="lineNum">     237 </span><span class="lineCov">       1088 :       valids_8_0 &lt;= 1'h0;</span></a>
+<a name="238"><span class="lineNum">     238 </span><span class="lineCov">       1088 :       valids_8_1 &lt;= 1'h0;</span></a>
+<a name="239"><span class="lineNum">     239 </span><span class="lineCov">       1088 :       valids_9_0 &lt;= 1'h0;</span></a>
+<a name="240"><span class="lineNum">     240 </span><span class="lineCov">       1088 :       valids_9_1 &lt;= 1'h0;</span></a>
+<a name="241"><span class="lineNum">     241 </span><span class="lineCov">       1088 :       valids_10_0 &lt;= 1'h0;</span></a>
+<a name="242"><span class="lineNum">     242 </span><span class="lineCov">       1088 :       valids_10_1 &lt;= 1'h0;</span></a>
+<a name="243"><span class="lineNum">     243 </span><span class="lineCov">       1088 :       valids_11_0 &lt;= 1'h0;</span></a>
+<a name="244"><span class="lineNum">     244 </span><span class="lineCov">       1088 :       valids_11_1 &lt;= 1'h0;</span></a>
+<a name="245"><span class="lineNum">     245 </span><span class="lineCov">       1088 :       valids_12_0 &lt;= 1'h0;</span></a>
+<a name="246"><span class="lineNum">     246 </span><span class="lineCov">       1088 :       valids_12_1 &lt;= 1'h0;</span></a>
+<a name="247"><span class="lineNum">     247 </span><span class="lineCov">       1088 :       valids_13_0 &lt;= 1'h0;</span></a>
+<a name="248"><span class="lineNum">     248 </span><span class="lineCov">       1088 :       valids_13_1 &lt;= 1'h0;</span></a>
+<a name="249"><span class="lineNum">     249 </span><span class="lineCov">       1088 :       valids_14_0 &lt;= 1'h0;</span></a>
+<a name="250"><span class="lineNum">     250 </span><span class="lineCov">       1088 :       valids_14_1 &lt;= 1'h0;</span></a>
+<a name="251"><span class="lineNum">     251 </span><span class="lineCov">       1088 :       valids_15_0 &lt;= 1'h0;</span></a>
+<a name="252"><span class="lineNum">     252 </span><span class="lineCov">       1088 :       valids_15_1 &lt;= 1'h0;</span></a>
+<a name="253"><span class="lineNum">     253 </span><span class="lineCov">       1088 :       ever_written_0 &lt;= 1'h0;</span></a>
+<a name="254"><span class="lineNum">     254 </span><span class="lineCov">       1088 :       ever_written_1 &lt;= 1'h0;</span></a>
+<a name="255"><span class="lineNum">     255 </span><span class="lineCov">       1088 :       ever_written_2 &lt;= 1'h0;</span></a>
+<a name="256"><span class="lineNum">     256 </span><span class="lineCov">       1088 :       ever_written_3 &lt;= 1'h0;</span></a>
+<a name="257"><span class="lineNum">     257 </span><span class="lineCov">       1088 :       ever_written_4 &lt;= 1'h0;</span></a>
+<a name="258"><span class="lineNum">     258 </span><span class="lineCov">       1088 :       ever_written_5 &lt;= 1'h0;</span></a>
+<a name="259"><span class="lineNum">     259 </span><span class="lineCov">       1088 :       ever_written_6 &lt;= 1'h0;</span></a>
+<a name="260"><span class="lineNum">     260 </span><span class="lineCov">       1088 :       ever_written_7 &lt;= 1'h0;</span></a>
+<a name="261"><span class="lineNum">     261 </span><span class="lineCov">       1088 :       ever_written_8 &lt;= 1'h0;</span></a>
+<a name="262"><span class="lineNum">     262 </span><span class="lineCov">       1088 :       ever_written_9 &lt;= 1'h0;</span></a>
+<a name="263"><span class="lineNum">     263 </span><span class="lineCov">       1088 :       ever_written_10 &lt;= 1'h0;</span></a>
+<a name="264"><span class="lineNum">     264 </span><span class="lineCov">       1088 :       ever_written_11 &lt;= 1'h0;</span></a>
+<a name="265"><span class="lineNum">     265 </span><span class="lineCov">       1088 :       ever_written_12 &lt;= 1'h0;</span></a>
+<a name="266"><span class="lineNum">     266 </span><span class="lineCov">       1088 :       ever_written_13 &lt;= 1'h0;</span></a>
+<a name="267"><span class="lineNum">     267 </span><span class="lineCov">       1088 :       ever_written_14 &lt;= 1'h0;</span></a>
+<a name="268"><span class="lineNum">     268 </span><span class="lineCov">       1088 :       ever_written_15 &lt;= 1'h0;</span></a>
+<a name="269"><span class="lineNum">     269 </span><span class="lineCov">       1088 :       state_reg &lt;= 15'h0;</span></a>
+<a name="270"><span class="lineNum">     270 </span>            :     end</a>
+<a name="271"><span class="lineNum">     271 </span><span class="lineCov">     509832 :     else begin</span></a>
+<a name="272"><span class="lineNum">     272 </span><span class="lineCov">        146 :       if (io_wen) begin</span></a>
+<a name="273"><span class="lineNum">     273 </span><span class="lineCov">          6 :         if (hit) begin</span></a>
+<a name="274"><span class="lineNum">     274 </span><span class="lineCov">          3 :           valids_0_0 &lt;= io_write_way_mask_0 &amp; _GEN | valids_0_0;</span></a>
+<a name="275"><span class="lineNum">     275 </span><span class="lineCov">          3 :           valids_0_1 &lt;= io_write_way_mask_1 &amp; _GEN | valids_0_1;</span></a>
+<a name="276"><span class="lineNum">     276 </span><span class="lineCov">          3 :           valids_1_0 &lt;= io_write_way_mask_0 &amp; _GEN_0 | valids_1_0;</span></a>
+<a name="277"><span class="lineNum">     277 </span><span class="lineCov">          3 :           valids_1_1 &lt;= io_write_way_mask_1 &amp; _GEN_0 | valids_1_1;</span></a>
+<a name="278"><span class="lineNum">     278 </span><span class="lineCov">          3 :           valids_2_0 &lt;= io_write_way_mask_0 &amp; _GEN_1 | valids_2_0;</span></a>
+<a name="279"><span class="lineNum">     279 </span><span class="lineCov">          3 :           valids_2_1 &lt;= io_write_way_mask_1 &amp; _GEN_1 | valids_2_1;</span></a>
+<a name="280"><span class="lineNum">     280 </span><span class="lineCov">          3 :           valids_3_0 &lt;= io_write_way_mask_0 &amp; _GEN_2 | valids_3_0;</span></a>
+<a name="281"><span class="lineNum">     281 </span><span class="lineCov">          3 :           valids_3_1 &lt;= io_write_way_mask_1 &amp; _GEN_2 | valids_3_1;</span></a>
+<a name="282"><span class="lineNum">     282 </span><span class="lineCov">          3 :           valids_4_0 &lt;= io_write_way_mask_0 &amp; _GEN_3 | valids_4_0;</span></a>
+<a name="283"><span class="lineNum">     283 </span><span class="lineCov">          3 :           valids_4_1 &lt;= io_write_way_mask_1 &amp; _GEN_3 | valids_4_1;</span></a>
+<a name="284"><span class="lineNum">     284 </span><span class="lineCov">          3 :           valids_5_0 &lt;= io_write_way_mask_0 &amp; _GEN_4 | valids_5_0;</span></a>
+<a name="285"><span class="lineNum">     285 </span><span class="lineCov">          3 :           valids_5_1 &lt;= io_write_way_mask_1 &amp; _GEN_4 | valids_5_1;</span></a>
+<a name="286"><span class="lineNum">     286 </span><span class="lineCov">          3 :           valids_6_0 &lt;= io_write_way_mask_0 &amp; _GEN_5 | valids_6_0;</span></a>
+<a name="287"><span class="lineNum">     287 </span><span class="lineCov">          3 :           valids_6_1 &lt;= io_write_way_mask_1 &amp; _GEN_5 | valids_6_1;</span></a>
+<a name="288"><span class="lineNum">     288 </span><span class="lineCov">          3 :           valids_7_0 &lt;= io_write_way_mask_0 &amp; _GEN_6 | valids_7_0;</span></a>
+<a name="289"><span class="lineNum">     289 </span><span class="lineCov">          3 :           valids_7_1 &lt;= io_write_way_mask_1 &amp; _GEN_6 | valids_7_1;</span></a>
+<a name="290"><span class="lineNum">     290 </span><span class="lineCov">          3 :           valids_8_0 &lt;= io_write_way_mask_0 &amp; _GEN_7 | valids_8_0;</span></a>
+<a name="291"><span class="lineNum">     291 </span><span class="lineCov">          3 :           valids_8_1 &lt;= io_write_way_mask_1 &amp; _GEN_7 | valids_8_1;</span></a>
+<a name="292"><span class="lineNum">     292 </span><span class="lineCov">          3 :           valids_9_0 &lt;= io_write_way_mask_0 &amp; _GEN_8 | valids_9_0;</span></a>
+<a name="293"><span class="lineNum">     293 </span><span class="lineCov">          3 :           valids_9_1 &lt;= io_write_way_mask_1 &amp; _GEN_8 | valids_9_1;</span></a>
+<a name="294"><span class="lineNum">     294 </span><span class="lineCov">          3 :           valids_10_0 &lt;= io_write_way_mask_0 &amp; _GEN_9 | valids_10_0;</span></a>
+<a name="295"><span class="lineNum">     295 </span><span class="lineCov">          3 :           valids_10_1 &lt;= io_write_way_mask_1 &amp; _GEN_9 | valids_10_1;</span></a>
+<a name="296"><span class="lineNum">     296 </span><span class="lineCov">          3 :           valids_11_0 &lt;= io_write_way_mask_0 &amp; _GEN_10 | valids_11_0;</span></a>
+<a name="297"><span class="lineNum">     297 </span><span class="lineCov">          3 :           valids_11_1 &lt;= io_write_way_mask_1 &amp; _GEN_10 | valids_11_1;</span></a>
+<a name="298"><span class="lineNum">     298 </span><span class="lineCov">          3 :           valids_12_0 &lt;= io_write_way_mask_0 &amp; _GEN_11 | valids_12_0;</span></a>
+<a name="299"><span class="lineNum">     299 </span><span class="lineCov">          3 :           valids_12_1 &lt;= io_write_way_mask_1 &amp; _GEN_11 | valids_12_1;</span></a>
+<a name="300"><span class="lineNum">     300 </span><span class="lineCov">          3 :           valids_13_0 &lt;= io_write_way_mask_0 &amp; _GEN_12 | valids_13_0;</span></a>
+<a name="301"><span class="lineNum">     301 </span><span class="lineCov">          3 :           valids_13_1 &lt;= io_write_way_mask_1 &amp; _GEN_12 | valids_13_1;</span></a>
+<a name="302"><span class="lineNum">     302 </span><span class="lineCov">          3 :           valids_14_0 &lt;= io_write_way_mask_0 &amp; _GEN_13 | valids_14_0;</span></a>
+<a name="303"><span class="lineNum">     303 </span><span class="lineCov">          3 :           valids_14_1 &lt;= io_write_way_mask_1 &amp; _GEN_13 | valids_14_1;</span></a>
+<a name="304"><span class="lineNum">     304 </span><span class="lineCov">          3 :           valids_15_0 &lt;= io_write_way_mask_0 &amp; (&amp;hit_idx) | valids_15_0;</span></a>
+<a name="305"><span class="lineNum">     305 </span><span class="lineCov">          3 :           valids_15_1 &lt;= io_write_way_mask_1 &amp; (&amp;hit_idx) | valids_15_1;</span></a>
+<a name="306"><span class="lineNum">     306 </span>            :         end</a>
+<a name="307"><span class="lineNum">     307 </span><span class="lineCov">         70 :         else begin</span></a>
+<a name="308"><span class="lineNum">     308 </span><span class="lineCov">         70 :           valids_0_0 &lt;= io_write_way_mask_0 &amp; _GEN_14 | ~_GEN_14 &amp; valids_0_0;</span></a>
+<a name="309"><span class="lineNum">     309 </span><span class="lineCov">         70 :           valids_0_1 &lt;= io_write_way_mask_1 &amp; _GEN_14 | ~_GEN_14 &amp; valids_0_1;</span></a>
+<a name="310"><span class="lineNum">     310 </span><span class="lineCov">         70 :           valids_1_0 &lt;= io_write_way_mask_0 &amp; _GEN_15 | ~_GEN_15 &amp; valids_1_0;</span></a>
+<a name="311"><span class="lineNum">     311 </span><span class="lineCov">         70 :           valids_1_1 &lt;= io_write_way_mask_1 &amp; _GEN_15 | ~_GEN_15 &amp; valids_1_1;</span></a>
+<a name="312"><span class="lineNum">     312 </span><span class="lineCov">         70 :           valids_2_0 &lt;= io_write_way_mask_0 &amp; _GEN_16 | ~_GEN_16 &amp; valids_2_0;</span></a>
+<a name="313"><span class="lineNum">     313 </span><span class="lineCov">         70 :           valids_2_1 &lt;= io_write_way_mask_1 &amp; _GEN_16 | ~_GEN_16 &amp; valids_2_1;</span></a>
+<a name="314"><span class="lineNum">     314 </span><span class="lineCov">         70 :           valids_3_0 &lt;= io_write_way_mask_0 &amp; _GEN_17 | ~_GEN_17 &amp; valids_3_0;</span></a>
+<a name="315"><span class="lineNum">     315 </span><span class="lineCov">         70 :           valids_3_1 &lt;= io_write_way_mask_1 &amp; _GEN_17 | ~_GEN_17 &amp; valids_3_1;</span></a>
+<a name="316"><span class="lineNum">     316 </span><span class="lineCov">         70 :           valids_4_0 &lt;= io_write_way_mask_0 &amp; _GEN_18 | ~_GEN_18 &amp; valids_4_0;</span></a>
+<a name="317"><span class="lineNum">     317 </span><span class="lineCov">         70 :           valids_4_1 &lt;= io_write_way_mask_1 &amp; _GEN_18 | ~_GEN_18 &amp; valids_4_1;</span></a>
+<a name="318"><span class="lineNum">     318 </span><span class="lineCov">         70 :           valids_5_0 &lt;= io_write_way_mask_0 &amp; _GEN_19 | ~_GEN_19 &amp; valids_5_0;</span></a>
+<a name="319"><span class="lineNum">     319 </span><span class="lineCov">         70 :           valids_5_1 &lt;= io_write_way_mask_1 &amp; _GEN_19 | ~_GEN_19 &amp; valids_5_1;</span></a>
+<a name="320"><span class="lineNum">     320 </span><span class="lineCov">         70 :           valids_6_0 &lt;= io_write_way_mask_0 &amp; _GEN_20 | ~_GEN_20 &amp; valids_6_0;</span></a>
+<a name="321"><span class="lineNum">     321 </span><span class="lineCov">         70 :           valids_6_1 &lt;= io_write_way_mask_1 &amp; _GEN_20 | ~_GEN_20 &amp; valids_6_1;</span></a>
+<a name="322"><span class="lineNum">     322 </span><span class="lineCov">         70 :           valids_7_0 &lt;= io_write_way_mask_0 &amp; _GEN_21 | ~_GEN_21 &amp; valids_7_0;</span></a>
+<a name="323"><span class="lineNum">     323 </span><span class="lineCov">         70 :           valids_7_1 &lt;= io_write_way_mask_1 &amp; _GEN_21 | ~_GEN_21 &amp; valids_7_1;</span></a>
+<a name="324"><span class="lineNum">     324 </span><span class="lineCov">         70 :           valids_8_0 &lt;= io_write_way_mask_0 &amp; _GEN_22 | ~_GEN_22 &amp; valids_8_0;</span></a>
+<a name="325"><span class="lineNum">     325 </span><span class="lineCov">         70 :           valids_8_1 &lt;= io_write_way_mask_1 &amp; _GEN_22 | ~_GEN_22 &amp; valids_8_1;</span></a>
+<a name="326"><span class="lineNum">     326 </span><span class="lineCov">         70 :           valids_9_0 &lt;= io_write_way_mask_0 &amp; _GEN_23 | ~_GEN_23 &amp; valids_9_0;</span></a>
+<a name="327"><span class="lineNum">     327 </span><span class="lineCov">         70 :           valids_9_1 &lt;= io_write_way_mask_1 &amp; _GEN_23 | ~_GEN_23 &amp; valids_9_1;</span></a>
+<a name="328"><span class="lineNum">     328 </span><span class="lineCov">         70 :           valids_10_0 &lt;= io_write_way_mask_0 &amp; _GEN_24 | ~_GEN_24 &amp; valids_10_0;</span></a>
+<a name="329"><span class="lineNum">     329 </span><span class="lineCov">         70 :           valids_10_1 &lt;= io_write_way_mask_1 &amp; _GEN_24 | ~_GEN_24 &amp; valids_10_1;</span></a>
+<a name="330"><span class="lineNum">     330 </span><span class="lineCov">         70 :           valids_11_0 &lt;= io_write_way_mask_0 &amp; _GEN_25 | ~_GEN_25 &amp; valids_11_0;</span></a>
+<a name="331"><span class="lineNum">     331 </span><span class="lineCov">         70 :           valids_11_1 &lt;= io_write_way_mask_1 &amp; _GEN_25 | ~_GEN_25 &amp; valids_11_1;</span></a>
+<a name="332"><span class="lineNum">     332 </span><span class="lineCov">         70 :           valids_12_0 &lt;= io_write_way_mask_0 &amp; _GEN_26 | ~_GEN_26 &amp; valids_12_0;</span></a>
+<a name="333"><span class="lineNum">     333 </span><span class="lineCov">         70 :           valids_12_1 &lt;= io_write_way_mask_1 &amp; _GEN_26 | ~_GEN_26 &amp; valids_12_1;</span></a>
+<a name="334"><span class="lineNum">     334 </span><span class="lineCov">         70 :           valids_13_0 &lt;= io_write_way_mask_0 &amp; _GEN_27 | ~_GEN_27 &amp; valids_13_0;</span></a>
+<a name="335"><span class="lineNum">     335 </span><span class="lineCov">         70 :           valids_13_1 &lt;= io_write_way_mask_1 &amp; _GEN_27 | ~_GEN_27 &amp; valids_13_1;</span></a>
+<a name="336"><span class="lineNum">     336 </span><span class="lineCov">         70 :           valids_14_0 &lt;= io_write_way_mask_0 &amp; _GEN_28 | ~_GEN_28 &amp; valids_14_0;</span></a>
+<a name="337"><span class="lineNum">     337 </span><span class="lineCov">         70 :           valids_14_1 &lt;= io_write_way_mask_1 &amp; _GEN_28 | ~_GEN_28 &amp; valids_14_1;</span></a>
+<a name="338"><span class="lineNum">     338 </span><span class="lineCov">         70 :           valids_15_0 &lt;= io_write_way_mask_0 &amp; (&amp;enq_idx) | ~(&amp;enq_idx) &amp; valids_15_0;</span></a>
+<a name="339"><span class="lineNum">     339 </span><span class="lineCov">         70 :           valids_15_1 &lt;= io_write_way_mask_1 &amp; (&amp;enq_idx) | ~(&amp;enq_idx) &amp; valids_15_1;</span></a>
+<a name="340"><span class="lineNum">     340 </span>            :         end</a>
+<a name="341"><span class="lineNum">     341 </span><span class="lineCov">         73 :         state_reg &lt;=</span></a>
+<a name="342"><span class="lineNum">     342 </span><span class="lineCov">         73 :           {~(state_reg_touch_way_sized[3]),</span></a>
+<a name="343"><span class="lineNum">     343 </span><span class="lineCov">         73 :            state_reg_touch_way_sized[3]</span></a>
+<a name="344"><span class="lineNum">     344 </span><span class="lineCov">         73 :              ? {~(state_reg_touch_way_sized[2]),</span></a>
+<a name="345"><span class="lineNum">     345 </span><span class="lineCov">         73 :                 state_reg_touch_way_sized[2]</span></a>
+<a name="346"><span class="lineNum">     346 </span><span class="lineCov">         73 :                   ? {~(state_reg_touch_way_sized[1]),</span></a>
+<a name="347"><span class="lineNum">     347 </span><span class="lineCov">         73 :                      state_reg_touch_way_sized[1]</span></a>
+<a name="348"><span class="lineNum">     348 </span><span class="lineCov">         73 :                        ? ~(state_reg_touch_way_sized[0])</span></a>
+<a name="349"><span class="lineNum">     349 </span><span class="lineCov">         73 :                        : state_reg[11],</span></a>
+<a name="350"><span class="lineNum">     350 </span><span class="lineCov">         73 :                      state_reg_touch_way_sized[1]</span></a>
+<a name="351"><span class="lineNum">     351 </span><span class="lineCov">         73 :                        ? state_reg[10]</span></a>
+<a name="352"><span class="lineNum">     352 </span><span class="lineCov">         73 :                        : ~(state_reg_touch_way_sized[0])}</span></a>
+<a name="353"><span class="lineNum">     353 </span><span class="lineCov">         73 :                   : state_reg[12:10],</span></a>
+<a name="354"><span class="lineNum">     354 </span><span class="lineCov">         73 :                 state_reg_touch_way_sized[2]</span></a>
+<a name="355"><span class="lineNum">     355 </span><span class="lineCov">         73 :                   ? state_reg[9:7]</span></a>
+<a name="356"><span class="lineNum">     356 </span><span class="lineCov">         73 :                   : {~(state_reg_touch_way_sized[1]),</span></a>
+<a name="357"><span class="lineNum">     357 </span><span class="lineCov">         73 :                      state_reg_touch_way_sized[1]</span></a>
+<a name="358"><span class="lineNum">     358 </span><span class="lineCov">         73 :                        ? ~(state_reg_touch_way_sized[0])</span></a>
+<a name="359"><span class="lineNum">     359 </span><span class="lineCov">         73 :                        : state_reg[8],</span></a>
+<a name="360"><span class="lineNum">     360 </span><span class="lineCov">         73 :                      state_reg_touch_way_sized[1]</span></a>
+<a name="361"><span class="lineNum">     361 </span><span class="lineCov">         73 :                        ? state_reg[7]</span></a>
+<a name="362"><span class="lineNum">     362 </span><span class="lineCov">         73 :                        : ~(state_reg_touch_way_sized[0])}}</span></a>
+<a name="363"><span class="lineNum">     363 </span><span class="lineCov">         73 :              : state_reg[13:7],</span></a>
+<a name="364"><span class="lineNum">     364 </span><span class="lineCov">         73 :            state_reg_touch_way_sized[3]</span></a>
+<a name="365"><span class="lineNum">     365 </span><span class="lineCov">         73 :              ? state_reg[6:0]</span></a>
+<a name="366"><span class="lineNum">     366 </span><span class="lineCov">         73 :              : {~(state_reg_touch_way_sized[2]),</span></a>
+<a name="367"><span class="lineNum">     367 </span><span class="lineCov">         73 :                 state_reg_touch_way_sized[2]</span></a>
+<a name="368"><span class="lineNum">     368 </span><span class="lineCov">         73 :                   ? {~(state_reg_touch_way_sized[1]),</span></a>
+<a name="369"><span class="lineNum">     369 </span><span class="lineCov">         73 :                      state_reg_touch_way_sized[1]</span></a>
+<a name="370"><span class="lineNum">     370 </span><span class="lineCov">         73 :                        ? ~(state_reg_touch_way_sized[0])</span></a>
+<a name="371"><span class="lineNum">     371 </span><span class="lineCov">         73 :                        : state_reg[4],</span></a>
+<a name="372"><span class="lineNum">     372 </span><span class="lineCov">         73 :                      state_reg_touch_way_sized[1]</span></a>
+<a name="373"><span class="lineNum">     373 </span><span class="lineCov">         73 :                        ? state_reg[3]</span></a>
+<a name="374"><span class="lineNum">     374 </span><span class="lineCov">         73 :                        : ~(state_reg_touch_way_sized[0])}</span></a>
+<a name="375"><span class="lineNum">     375 </span><span class="lineCov">         73 :                   : state_reg[5:3],</span></a>
+<a name="376"><span class="lineNum">     376 </span><span class="lineCov">         73 :                 state_reg_touch_way_sized[2]</span></a>
+<a name="377"><span class="lineNum">     377 </span><span class="lineCov">         73 :                   ? state_reg[2:0]</span></a>
+<a name="378"><span class="lineNum">     378 </span><span class="lineCov">         73 :                   : {~(state_reg_touch_way_sized[1]),</span></a>
+<a name="379"><span class="lineNum">     379 </span><span class="lineCov">         73 :                      state_reg_touch_way_sized[1]</span></a>
+<a name="380"><span class="lineNum">     380 </span><span class="lineCov">         73 :                        ? ~(state_reg_touch_way_sized[0])</span></a>
+<a name="381"><span class="lineNum">     381 </span><span class="lineCov">         73 :                        : state_reg[1],</span></a>
+<a name="382"><span class="lineNum">     382 </span><span class="lineCov">         73 :                      state_reg_touch_way_sized[1]</span></a>
+<a name="383"><span class="lineNum">     383 </span><span class="lineCov">         73 :                        ? state_reg[0]</span></a>
+<a name="384"><span class="lineNum">     384 </span><span class="lineCov">         73 :                        : ~(state_reg_touch_way_sized[0])}}};</span></a>
+<a name="385"><span class="lineNum">     385 </span>            :       end</a>
+<a name="386"><span class="lineNum">     386 </span><span class="lineCov">     509832 :       ever_written_0 &lt;= io_wen &amp; ~hit &amp; (_GEN_14 | io_wen &amp; _GEN_14) | ever_written_0;</span></a>
+<a name="387"><span class="lineNum">     387 </span><span class="lineCov">     509832 :       ever_written_1 &lt;= io_wen &amp; ~hit &amp; (_GEN_15 | io_wen &amp; _GEN_15) | ever_written_1;</span></a>
+<a name="388"><span class="lineNum">     388 </span><span class="lineCov">     509832 :       ever_written_2 &lt;= io_wen &amp; ~hit &amp; (_GEN_16 | io_wen &amp; _GEN_16) | ever_written_2;</span></a>
+<a name="389"><span class="lineNum">     389 </span><span class="lineCov">     509832 :       ever_written_3 &lt;= io_wen &amp; ~hit &amp; (_GEN_17 | io_wen &amp; _GEN_17) | ever_written_3;</span></a>
+<a name="390"><span class="lineNum">     390 </span><span class="lineCov">     509832 :       ever_written_4 &lt;= io_wen &amp; ~hit &amp; (_GEN_18 | io_wen &amp; _GEN_18) | ever_written_4;</span></a>
+<a name="391"><span class="lineNum">     391 </span><span class="lineCov">     509832 :       ever_written_5 &lt;= io_wen &amp; ~hit &amp; (_GEN_19 | io_wen &amp; _GEN_19) | ever_written_5;</span></a>
+<a name="392"><span class="lineNum">     392 </span><span class="lineCov">     509832 :       ever_written_6 &lt;= io_wen &amp; ~hit &amp; (_GEN_20 | io_wen &amp; _GEN_20) | ever_written_6;</span></a>
+<a name="393"><span class="lineNum">     393 </span><span class="lineCov">     509832 :       ever_written_7 &lt;= io_wen &amp; ~hit &amp; (_GEN_21 | io_wen &amp; _GEN_21) | ever_written_7;</span></a>
+<a name="394"><span class="lineNum">     394 </span><span class="lineCov">     509832 :       ever_written_8 &lt;= io_wen &amp; ~hit &amp; (_GEN_22 | io_wen &amp; _GEN_22) | ever_written_8;</span></a>
+<a name="395"><span class="lineNum">     395 </span><span class="lineCov">     509832 :       ever_written_9 &lt;= io_wen &amp; ~hit &amp; (_GEN_23 | io_wen &amp; _GEN_23) | ever_written_9;</span></a>
+<a name="396"><span class="lineNum">     396 </span><span class="lineCov">     509832 :       ever_written_10 &lt;= io_wen &amp; ~hit &amp; (_GEN_24 | io_wen &amp; _GEN_24) | ever_written_10;</span></a>
+<a name="397"><span class="lineNum">     397 </span><span class="lineCov">     509832 :       ever_written_11 &lt;= io_wen &amp; ~hit &amp; (_GEN_25 | io_wen &amp; _GEN_25) | ever_written_11;</span></a>
+<a name="398"><span class="lineNum">     398 </span><span class="lineCov">     509832 :       ever_written_12 &lt;= io_wen &amp; ~hit &amp; (_GEN_26 | io_wen &amp; _GEN_26) | ever_written_12;</span></a>
+<a name="399"><span class="lineNum">     399 </span><span class="lineCov">     509832 :       ever_written_13 &lt;= io_wen &amp; ~hit &amp; (_GEN_27 | io_wen &amp; _GEN_27) | ever_written_13;</span></a>
+<a name="400"><span class="lineNum">     400 </span><span class="lineCov">     509832 :       ever_written_14 &lt;= io_wen &amp; ~hit &amp; (_GEN_28 | io_wen &amp; _GEN_28) | ever_written_14;</span></a>
+<a name="401"><span class="lineNum">     401 </span><span class="lineCov">     509832 :       ever_written_15 &lt;=</span></a>
+<a name="402"><span class="lineNum">     402 </span><span class="lineCov">     509832 :         io_wen &amp; ~hit &amp; ((&amp;enq_idx) | io_wen &amp; (&amp;enq_idx)) | ever_written_15;</span></a>
+<a name="403"><span class="lineNum">     403 </span>            :     end</a>
+<a name="404"><span class="lineNum">     404 </span>            :   end // always @(posedge, posedge)</a>
+<a name="405"><span class="lineNum">     405 </span>            :   `ifdef ENABLE_INITIAL_REG_</a>
+<a name="406"><span class="lineNum">     406 </span>            :     `ifdef FIRRTL_BEFORE_INITIAL</a>
+<a name="407"><span class="lineNum">     407 </span>            :       `FIRRTL_BEFORE_INITIAL</a>
+<a name="408"><span class="lineNum">     408 </span>            :     `endif // FIRRTL_BEFORE_INITIAL</a>
+<a name="409"><span class="lineNum">     409 </span>            :     logic [31:0] _RANDOM[0:1];</a>
+<a name="410"><span class="lineNum">     410 </span><span class="lineCov">        464 :     initial begin</span></a>
+<a name="411"><span class="lineNum">     411 </span>            :       `ifdef INIT_RANDOM_PROLOG_</a>
+<a name="412"><span class="lineNum">     412 </span>            :         `INIT_RANDOM_PROLOG_</a>
+<a name="413"><span class="lineNum">     413 </span>            :       `endif // INIT_RANDOM_PROLOG_</a>
+<a name="414"><span class="lineNum">     414 </span>            :       `ifdef RANDOMIZE_REG_INIT</a>
+<a name="415"><span class="lineNum">     415 </span>            :         for (logic [1:0] i = 2'h0; i &lt; 2'h2; i += 2'h1) begin</a>
+<a name="416"><span class="lineNum">     416 </span>            :           _RANDOM[i[0]] = `RANDOM;</a>
+<a name="417"><span class="lineNum">     417 </span>            :         end</a>
+<a name="418"><span class="lineNum">     418 </span>            :         valids_0_0 = _RANDOM[1'h0][0];</a>
+<a name="419"><span class="lineNum">     419 </span>            :         valids_0_1 = _RANDOM[1'h0][1];</a>
+<a name="420"><span class="lineNum">     420 </span>            :         valids_1_0 = _RANDOM[1'h0][2];</a>
+<a name="421"><span class="lineNum">     421 </span>            :         valids_1_1 = _RANDOM[1'h0][3];</a>
+<a name="422"><span class="lineNum">     422 </span>            :         valids_2_0 = _RANDOM[1'h0][4];</a>
+<a name="423"><span class="lineNum">     423 </span>            :         valids_2_1 = _RANDOM[1'h0][5];</a>
+<a name="424"><span class="lineNum">     424 </span>            :         valids_3_0 = _RANDOM[1'h0][6];</a>
+<a name="425"><span class="lineNum">     425 </span>            :         valids_3_1 = _RANDOM[1'h0][7];</a>
+<a name="426"><span class="lineNum">     426 </span>            :         valids_4_0 = _RANDOM[1'h0][8];</a>
+<a name="427"><span class="lineNum">     427 </span>            :         valids_4_1 = _RANDOM[1'h0][9];</a>
+<a name="428"><span class="lineNum">     428 </span>            :         valids_5_0 = _RANDOM[1'h0][10];</a>
+<a name="429"><span class="lineNum">     429 </span>            :         valids_5_1 = _RANDOM[1'h0][11];</a>
+<a name="430"><span class="lineNum">     430 </span>            :         valids_6_0 = _RANDOM[1'h0][12];</a>
+<a name="431"><span class="lineNum">     431 </span>            :         valids_6_1 = _RANDOM[1'h0][13];</a>
+<a name="432"><span class="lineNum">     432 </span>            :         valids_7_0 = _RANDOM[1'h0][14];</a>
+<a name="433"><span class="lineNum">     433 </span>            :         valids_7_1 = _RANDOM[1'h0][15];</a>
+<a name="434"><span class="lineNum">     434 </span>            :         valids_8_0 = _RANDOM[1'h0][16];</a>
+<a name="435"><span class="lineNum">     435 </span>            :         valids_8_1 = _RANDOM[1'h0][17];</a>
+<a name="436"><span class="lineNum">     436 </span>            :         valids_9_0 = _RANDOM[1'h0][18];</a>
+<a name="437"><span class="lineNum">     437 </span>            :         valids_9_1 = _RANDOM[1'h0][19];</a>
+<a name="438"><span class="lineNum">     438 </span>            :         valids_10_0 = _RANDOM[1'h0][20];</a>
+<a name="439"><span class="lineNum">     439 </span>            :         valids_10_1 = _RANDOM[1'h0][21];</a>
+<a name="440"><span class="lineNum">     440 </span>            :         valids_11_0 = _RANDOM[1'h0][22];</a>
+<a name="441"><span class="lineNum">     441 </span>            :         valids_11_1 = _RANDOM[1'h0][23];</a>
+<a name="442"><span class="lineNum">     442 </span>            :         valids_12_0 = _RANDOM[1'h0][24];</a>
+<a name="443"><span class="lineNum">     443 </span>            :         valids_12_1 = _RANDOM[1'h0][25];</a>
+<a name="444"><span class="lineNum">     444 </span>            :         valids_13_0 = _RANDOM[1'h0][26];</a>
+<a name="445"><span class="lineNum">     445 </span>            :         valids_13_1 = _RANDOM[1'h0][27];</a>
+<a name="446"><span class="lineNum">     446 </span>            :         valids_14_0 = _RANDOM[1'h0][28];</a>
+<a name="447"><span class="lineNum">     447 </span>            :         valids_14_1 = _RANDOM[1'h0][29];</a>
+<a name="448"><span class="lineNum">     448 </span>            :         valids_15_0 = _RANDOM[1'h0][30];</a>
+<a name="449"><span class="lineNum">     449 </span>            :         valids_15_1 = _RANDOM[1'h0][31];</a>
+<a name="450"><span class="lineNum">     450 </span>            :         ever_written_0 = _RANDOM[1'h1][0];</a>
+<a name="451"><span class="lineNum">     451 </span>            :         ever_written_1 = _RANDOM[1'h1][1];</a>
+<a name="452"><span class="lineNum">     452 </span>            :         ever_written_2 = _RANDOM[1'h1][2];</a>
+<a name="453"><span class="lineNum">     453 </span>            :         ever_written_3 = _RANDOM[1'h1][3];</a>
+<a name="454"><span class="lineNum">     454 </span>            :         ever_written_4 = _RANDOM[1'h1][4];</a>
+<a name="455"><span class="lineNum">     455 </span>            :         ever_written_5 = _RANDOM[1'h1][5];</a>
+<a name="456"><span class="lineNum">     456 </span>            :         ever_written_6 = _RANDOM[1'h1][6];</a>
+<a name="457"><span class="lineNum">     457 </span>            :         ever_written_7 = _RANDOM[1'h1][7];</a>
+<a name="458"><span class="lineNum">     458 </span>            :         ever_written_8 = _RANDOM[1'h1][8];</a>
+<a name="459"><span class="lineNum">     459 </span>            :         ever_written_9 = _RANDOM[1'h1][9];</a>
+<a name="460"><span class="lineNum">     460 </span>            :         ever_written_10 = _RANDOM[1'h1][10];</a>
+<a name="461"><span class="lineNum">     461 </span>            :         ever_written_11 = _RANDOM[1'h1][11];</a>
+<a name="462"><span class="lineNum">     462 </span>            :         ever_written_12 = _RANDOM[1'h1][12];</a>
+<a name="463"><span class="lineNum">     463 </span>            :         ever_written_13 = _RANDOM[1'h1][13];</a>
+<a name="464"><span class="lineNum">     464 </span>            :         ever_written_14 = _RANDOM[1'h1][14];</a>
+<a name="465"><span class="lineNum">     465 </span>            :         ever_written_15 = _RANDOM[1'h1][15];</a>
+<a name="466"><span class="lineNum">     466 </span>            :         state_reg = _RANDOM[1'h1][30:16];</a>
+<a name="467"><span class="lineNum">     467 </span>            :       `endif // RANDOMIZE_REG_INIT</a>
+<a name="468"><span class="lineNum">     468 </span><span class="lineCov">        136 :       if (reset) begin</span></a>
+<a name="469"><span class="lineNum">     469 </span><span class="lineCov">         96 :         valids_0_0 = 1'h0;</span></a>
+<a name="470"><span class="lineNum">     470 </span><span class="lineCov">         96 :         valids_0_1 = 1'h0;</span></a>
+<a name="471"><span class="lineNum">     471 </span><span class="lineCov">         96 :         valids_1_0 = 1'h0;</span></a>
+<a name="472"><span class="lineNum">     472 </span><span class="lineCov">         96 :         valids_1_1 = 1'h0;</span></a>
+<a name="473"><span class="lineNum">     473 </span><span class="lineCov">         96 :         valids_2_0 = 1'h0;</span></a>
+<a name="474"><span class="lineNum">     474 </span><span class="lineCov">         96 :         valids_2_1 = 1'h0;</span></a>
+<a name="475"><span class="lineNum">     475 </span><span class="lineCov">         96 :         valids_3_0 = 1'h0;</span></a>
+<a name="476"><span class="lineNum">     476 </span><span class="lineCov">         96 :         valids_3_1 = 1'h0;</span></a>
+<a name="477"><span class="lineNum">     477 </span><span class="lineCov">         96 :         valids_4_0 = 1'h0;</span></a>
+<a name="478"><span class="lineNum">     478 </span><span class="lineCov">         96 :         valids_4_1 = 1'h0;</span></a>
+<a name="479"><span class="lineNum">     479 </span><span class="lineCov">         96 :         valids_5_0 = 1'h0;</span></a>
+<a name="480"><span class="lineNum">     480 </span><span class="lineCov">         96 :         valids_5_1 = 1'h0;</span></a>
+<a name="481"><span class="lineNum">     481 </span><span class="lineCov">         96 :         valids_6_0 = 1'h0;</span></a>
+<a name="482"><span class="lineNum">     482 </span><span class="lineCov">         96 :         valids_6_1 = 1'h0;</span></a>
+<a name="483"><span class="lineNum">     483 </span><span class="lineCov">         96 :         valids_7_0 = 1'h0;</span></a>
+<a name="484"><span class="lineNum">     484 </span><span class="lineCov">         96 :         valids_7_1 = 1'h0;</span></a>
+<a name="485"><span class="lineNum">     485 </span><span class="lineCov">         96 :         valids_8_0 = 1'h0;</span></a>
+<a name="486"><span class="lineNum">     486 </span><span class="lineCov">         96 :         valids_8_1 = 1'h0;</span></a>
+<a name="487"><span class="lineNum">     487 </span><span class="lineCov">         96 :         valids_9_0 = 1'h0;</span></a>
+<a name="488"><span class="lineNum">     488 </span><span class="lineCov">         96 :         valids_9_1 = 1'h0;</span></a>
+<a name="489"><span class="lineNum">     489 </span><span class="lineCov">         96 :         valids_10_0 = 1'h0;</span></a>
+<a name="490"><span class="lineNum">     490 </span><span class="lineCov">         96 :         valids_10_1 = 1'h0;</span></a>
+<a name="491"><span class="lineNum">     491 </span><span class="lineCov">         96 :         valids_11_0 = 1'h0;</span></a>
+<a name="492"><span class="lineNum">     492 </span><span class="lineCov">         96 :         valids_11_1 = 1'h0;</span></a>
+<a name="493"><span class="lineNum">     493 </span><span class="lineCov">         96 :         valids_12_0 = 1'h0;</span></a>
+<a name="494"><span class="lineNum">     494 </span><span class="lineCov">         96 :         valids_12_1 = 1'h0;</span></a>
+<a name="495"><span class="lineNum">     495 </span><span class="lineCov">         96 :         valids_13_0 = 1'h0;</span></a>
+<a name="496"><span class="lineNum">     496 </span><span class="lineCov">         96 :         valids_13_1 = 1'h0;</span></a>
+<a name="497"><span class="lineNum">     497 </span><span class="lineCov">         96 :         valids_14_0 = 1'h0;</span></a>
+<a name="498"><span class="lineNum">     498 </span><span class="lineCov">         96 :         valids_14_1 = 1'h0;</span></a>
+<a name="499"><span class="lineNum">     499 </span><span class="lineCov">         96 :         valids_15_0 = 1'h0;</span></a>
+<a name="500"><span class="lineNum">     500 </span><span class="lineCov">         96 :         valids_15_1 = 1'h0;</span></a>
+<a name="501"><span class="lineNum">     501 </span><span class="lineCov">         96 :         ever_written_0 = 1'h0;</span></a>
+<a name="502"><span class="lineNum">     502 </span><span class="lineCov">         96 :         ever_written_1 = 1'h0;</span></a>
+<a name="503"><span class="lineNum">     503 </span><span class="lineCov">         96 :         ever_written_2 = 1'h0;</span></a>
+<a name="504"><span class="lineNum">     504 </span><span class="lineCov">         96 :         ever_written_3 = 1'h0;</span></a>
+<a name="505"><span class="lineNum">     505 </span><span class="lineCov">         96 :         ever_written_4 = 1'h0;</span></a>
+<a name="506"><span class="lineNum">     506 </span><span class="lineCov">         96 :         ever_written_5 = 1'h0;</span></a>
+<a name="507"><span class="lineNum">     507 </span><span class="lineCov">         96 :         ever_written_6 = 1'h0;</span></a>
+<a name="508"><span class="lineNum">     508 </span><span class="lineCov">         96 :         ever_written_7 = 1'h0;</span></a>
+<a name="509"><span class="lineNum">     509 </span><span class="lineCov">         96 :         ever_written_8 = 1'h0;</span></a>
+<a name="510"><span class="lineNum">     510 </span><span class="lineCov">         96 :         ever_written_9 = 1'h0;</span></a>
+<a name="511"><span class="lineNum">     511 </span><span class="lineCov">         96 :         ever_written_10 = 1'h0;</span></a>
+<a name="512"><span class="lineNum">     512 </span><span class="lineCov">         96 :         ever_written_11 = 1'h0;</span></a>
+<a name="513"><span class="lineNum">     513 </span><span class="lineCov">         96 :         ever_written_12 = 1'h0;</span></a>
+<a name="514"><span class="lineNum">     514 </span><span class="lineCov">         96 :         ever_written_13 = 1'h0;</span></a>
+<a name="515"><span class="lineNum">     515 </span><span class="lineCov">         96 :         ever_written_14 = 1'h0;</span></a>
+<a name="516"><span class="lineNum">     516 </span><span class="lineCov">         96 :         ever_written_15 = 1'h0;</span></a>
+<a name="517"><span class="lineNum">     517 </span><span class="lineCov">         96 :         state_reg = 15'h0;</span></a>
+<a name="518"><span class="lineNum">     518 </span>            :       end</a>
+<a name="519"><span class="lineNum">     519 </span>            :     end // initial</a>
+<a name="520"><span class="lineNum">     520 </span>            :     `ifdef FIRRTL_AFTER_INITIAL</a>
+<a name="521"><span class="lineNum">     521 </span>            :       `FIRRTL_AFTER_INITIAL</a>
+<a name="522"><span class="lineNum">     522 </span>            :     `endif // FIRRTL_AFTER_INITIAL</a>
+<a name="523"><span class="lineNum">     523 </span>            :   `endif // ENABLE_INITIAL_REG_</a>
+<a name="524"><span class="lineNum">     524 </span>            :   CAMTemplate_33 idx_tag_cam (</a>
+<a name="525"><span class="lineNum">     525 </span>            :     .clock              (clock),</a>
+<a name="526"><span class="lineNum">     526 </span>            :     .io_r_req_0_idx     (io_write_idx),</a>
+<a name="527"><span class="lineNum">     527 </span>            :     .io_r_resp_0_0      (_idx_tag_cam_io_r_resp_0_0),</a>
+<a name="528"><span class="lineNum">     528 </span>            :     .io_r_resp_0_1      (_idx_tag_cam_io_r_resp_0_1),</a>
+<a name="529"><span class="lineNum">     529 </span>            :     .io_r_resp_0_2      (_idx_tag_cam_io_r_resp_0_2),</a>
+<a name="530"><span class="lineNum">     530 </span>            :     .io_r_resp_0_3      (_idx_tag_cam_io_r_resp_0_3),</a>
+<a name="531"><span class="lineNum">     531 </span>            :     .io_r_resp_0_4      (_idx_tag_cam_io_r_resp_0_4),</a>
+<a name="532"><span class="lineNum">     532 </span>            :     .io_r_resp_0_5      (_idx_tag_cam_io_r_resp_0_5),</a>
+<a name="533"><span class="lineNum">     533 </span>            :     .io_r_resp_0_6      (_idx_tag_cam_io_r_resp_0_6),</a>
+<a name="534"><span class="lineNum">     534 </span>            :     .io_r_resp_0_7      (_idx_tag_cam_io_r_resp_0_7),</a>
+<a name="535"><span class="lineNum">     535 </span>            :     .io_r_resp_0_8      (_idx_tag_cam_io_r_resp_0_8),</a>
+<a name="536"><span class="lineNum">     536 </span>            :     .io_r_resp_0_9      (_idx_tag_cam_io_r_resp_0_9),</a>
+<a name="537"><span class="lineNum">     537 </span>            :     .io_r_resp_0_10     (_idx_tag_cam_io_r_resp_0_10),</a>
+<a name="538"><span class="lineNum">     538 </span>            :     .io_r_resp_0_11     (_idx_tag_cam_io_r_resp_0_11),</a>
+<a name="539"><span class="lineNum">     539 </span>            :     .io_r_resp_0_12     (_idx_tag_cam_io_r_resp_0_12),</a>
+<a name="540"><span class="lineNum">     540 </span>            :     .io_r_resp_0_13     (_idx_tag_cam_io_r_resp_0_13),</a>
+<a name="541"><span class="lineNum">     541 </span>            :     .io_r_resp_0_14     (_idx_tag_cam_io_r_resp_0_14),</a>
+<a name="542"><span class="lineNum">     542 </span>            :     .io_r_resp_0_15     (_idx_tag_cam_io_r_resp_0_15),</a>
+<a name="543"><span class="lineNum">     543 </span>            :     .io_w_valid         (io_wen &amp; ~hit),</a>
+<a name="544"><span class="lineNum">     544 </span>            :     .io_w_bits_data_idx (io_write_idx),</a>
+<a name="545"><span class="lineNum">     545 </span>            :     .io_w_bits_index    (enq_idx)</a>
+<a name="546"><span class="lineNum">     546 </span>            :   );</a>
+<a name="547"><span class="lineNum">     547 </span>            :   data_mem_16x12 data_mem_ext (</a>
+<a name="548"><span class="lineNum">     548 </span>            :     .R0_addr (hit_idx),</a>
+<a name="549"><span class="lineNum">     549 </span>            :     .R0_en   (1'h1),</a>
+<a name="550"><span class="lineNum">     550 </span>            :     .R0_clk  (clock),</a>
+<a name="551"><span class="lineNum">     551 </span>            :     .R0_data (_data_mem_ext_R0_data),</a>
+<a name="552"><span class="lineNum">     552 </span>            :     .R1_addr (hit_idx),</a>
+<a name="553"><span class="lineNum">     553 </span>            :     .R1_en   (1'h1),</a>
+<a name="554"><span class="lineNum">     554 </span>            :     .R1_clk  (clock),</a>
+<a name="555"><span class="lineNum">     555 </span>            :     .R1_data (_data_mem_ext_R1_data),</a>
+<a name="556"><span class="lineNum">     556 </span>            :     .W0_addr (hit ? hit_idx : enq_idx),</a>
+<a name="557"><span class="lineNum">     557 </span>            :     .W0_en   (io_wen),</a>
+<a name="558"><span class="lineNum">     558 </span>            :     .W0_clk  (clock),</a>
+<a name="559"><span class="lineNum">     559 </span>            :     .W0_data ({io_write_data_1, io_write_data_0}),</a>
+<a name="560"><span class="lineNum">     560 </span>            :     .W0_mask ({io_write_way_mask_1, io_write_way_mask_0})</a>
+<a name="561"><span class="lineNum">     561 </span>            :   );</a>
+<a name="562"><span class="lineNum">     562 </span>            :   assign io_hit = hit;</a>
+<a name="563"><span class="lineNum">     563 </span>            :   assign io_hit_data_0_valid =</a>
+<a name="564"><span class="lineNum">     564 </span>            :     hits_oh_0 &amp; valids_0_0 | hits_oh_1 &amp; valids_1_0 | hits_oh_2 &amp; valids_2_0 | hits_oh_3</a>
+<a name="565"><span class="lineNum">     565 </span>            :     &amp; valids_3_0 | hits_oh_4 &amp; valids_4_0 | hits_oh_5 &amp; valids_5_0 | hits_oh_6</a>
+<a name="566"><span class="lineNum">     566 </span>            :     &amp; valids_6_0 | hits_oh_7 &amp; valids_7_0 | hits_oh_8 &amp; valids_8_0 | hits_oh_9</a>
+<a name="567"><span class="lineNum">     567 </span>            :     &amp; valids_9_0 | hits_oh_10 &amp; valids_10_0 | hits_oh_11 &amp; valids_11_0 | hits_oh_12</a>
+<a name="568"><span class="lineNum">     568 </span>            :     &amp; valids_12_0 | hits_oh_13 &amp; valids_13_0 | hits_oh_14 &amp; valids_14_0 | hits_oh_15</a>
+<a name="569"><span class="lineNum">     569 </span>            :     &amp; valids_15_0;</a>
+<a name="570"><span class="lineNum">     570 </span>            :   assign io_hit_data_0_bits = _data_mem_ext_R1_data[5:0];</a>
+<a name="571"><span class="lineNum">     571 </span>            :   assign io_hit_data_1_valid =</a>
+<a name="572"><span class="lineNum">     572 </span>            :     hits_oh_0 &amp; valids_0_1 | hits_oh_1 &amp; valids_1_1 | hits_oh_2 &amp; valids_2_1 | hits_oh_3</a>
+<a name="573"><span class="lineNum">     573 </span>            :     &amp; valids_3_1 | hits_oh_4 &amp; valids_4_1 | hits_oh_5 &amp; valids_5_1 | hits_oh_6</a>
+<a name="574"><span class="lineNum">     574 </span>            :     &amp; valids_6_1 | hits_oh_7 &amp; valids_7_1 | hits_oh_8 &amp; valids_8_1 | hits_oh_9</a>
+<a name="575"><span class="lineNum">     575 </span>            :     &amp; valids_9_1 | hits_oh_10 &amp; valids_10_1 | hits_oh_11 &amp; valids_11_1 | hits_oh_12</a>
+<a name="576"><span class="lineNum">     576 </span>            :     &amp; valids_12_1 | hits_oh_13 &amp; valids_13_1 | hits_oh_14 &amp; valids_14_1 | hits_oh_15</a>
+<a name="577"><span class="lineNum">     577 </span>            :     &amp; valids_15_1;</a>
+<a name="578"><span class="lineNum">     578 </span>            :   assign io_hit_data_1_bits = _data_mem_ext_R0_data[11:6];</a>
+<a name="579"><span class="lineNum">     579 </span>            : endmodule</a>
+<a name="580"><span class="lineNum">     580 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/WrBypass_41.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/WrBypass_41.sv.func-sort-c.html
new file mode 100644
index 0000000..d25c99b
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/WrBypass_41.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/WrBypass_41.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - WrBypass_41.sv<span style="font-size: 80%;"> (<a href="WrBypass_41.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">43</td>
+            <td class="headerCovTableEntry">43</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="WrBypass_41.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/WrBypass_41.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/WrBypass_41.sv.func.html
new file mode 100644
index 0000000..807a52d
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/WrBypass_41.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/WrBypass_41.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - WrBypass_41.sv<span style="font-size: 80%;"> (<a href="WrBypass_41.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">43</td>
+            <td class="headerCovTableEntry">43</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="WrBypass_41.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/WrBypass_41.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/WrBypass_41.sv.gcov.html
new file mode 100644
index 0000000..f582f57
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/WrBypass_41.sv.gcov.html
@@ -0,0 +1,233 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/WrBypass_41.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - WrBypass_41.sv<span style="font-size: 80%;"> (source / <a href="WrBypass_41.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">43</td>
+            <td class="headerCovTableEntry">43</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : module WrBypass_41(</a>
+<a name="59"><span class="lineNum">      59 </span><span class="lineCov">     127786 :   input        clock,</span></a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">         62 :   input        reset,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">         27 :   input        io_wen,</span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">        105 :   input  [7:0] io_write_idx,</span></a>
+<a name="63"><span class="lineNum">      63 </span><span class="lineCov">         36 :   input  [1:0] io_write_data_0,</span></a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">         48 :   output       io_hit,</span></a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">         94 :   output [1:0] io_hit_data_0_bits</span></a>
+<a name="66"><span class="lineNum">      66 </span>            : );</a>
+<a name="67"><span class="lineNum">      67 </span>            : </a>
+<a name="68"><span class="lineNum">      68 </span>            :   wire       _idx_tag_cam_io_r_resp_0_0;</a>
+<a name="69"><span class="lineNum">      69 </span>            :   wire       _idx_tag_cam_io_r_resp_0_1;</a>
+<a name="70"><span class="lineNum">      70 </span>            :   wire       _idx_tag_cam_io_r_resp_0_2;</a>
+<a name="71"><span class="lineNum">      71 </span>            :   wire       _idx_tag_cam_io_r_resp_0_3;</a>
+<a name="72"><span class="lineNum">      72 </span><span class="lineCov">         54 :   reg        ever_written_0;</span></a>
+<a name="73"><span class="lineNum">      73 </span><span class="lineCov">         51 :   reg        ever_written_1;</span></a>
+<a name="74"><span class="lineNum">      74 </span><span class="lineCov">         50 :   reg        ever_written_2;</span></a>
+<a name="75"><span class="lineNum">      75 </span><span class="lineCov">         48 :   reg        ever_written_3;</span></a>
+<a name="76"><span class="lineNum">      76 </span><span class="lineCov">         32 :   wire       hits_oh_1 = _idx_tag_cam_io_r_resp_0_1 &amp; ever_written_1;</span></a>
+<a name="77"><span class="lineNum">      77 </span><span class="lineCov">         31 :   wire       hits_oh_2 = _idx_tag_cam_io_r_resp_0_2 &amp; ever_written_2;</span></a>
+<a name="78"><span class="lineNum">      78 </span><span class="lineCov">         37 :   wire       hits_oh_3 = _idx_tag_cam_io_r_resp_0_3 &amp; ever_written_3;</span></a>
+<a name="79"><span class="lineNum">      79 </span><span class="lineCov">         75 :   wire [1:0] hit_idx = {|{hits_oh_3, hits_oh_2}, hits_oh_3 | hits_oh_1};</span></a>
+<a name="80"><span class="lineNum">      80 </span><span class="lineCov">         48 :   wire       hit =</span></a>
+<a name="81"><span class="lineNum">      81 </span>            :     _idx_tag_cam_io_r_resp_0_0 &amp; ever_written_0 | hits_oh_1 | hits_oh_2 | hits_oh_3;</a>
+<a name="82"><span class="lineNum">      82 </span><span class="lineCov">        171 :   reg  [2:0] state_reg;</span></a>
+<a name="83"><span class="lineNum">      83 </span><span class="lineCov">        118 :   wire [1:0] enq_idx = {state_reg[2], state_reg[2] ? state_reg[1] : state_reg[0]};</span></a>
+<a name="84"><span class="lineNum">      84 </span><span class="lineCov">         90 :   wire [1:0] state_reg_touch_way_sized = hit ? hit_idx : enq_idx;</span></a>
+<a name="85"><span class="lineNum">      85 </span><span class="lineCov">     255460 :   always @(posedge clock or posedge reset) begin</span></a>
+<a name="86"><span class="lineNum">      86 </span><span class="lineCov">        544 :     if (reset) begin</span></a>
+<a name="87"><span class="lineNum">      87 </span><span class="lineCov">        272 :       ever_written_0 &lt;= 1'h0;</span></a>
+<a name="88"><span class="lineNum">      88 </span><span class="lineCov">        272 :       ever_written_1 &lt;= 1'h0;</span></a>
+<a name="89"><span class="lineNum">      89 </span><span class="lineCov">        272 :       ever_written_2 &lt;= 1'h0;</span></a>
+<a name="90"><span class="lineNum">      90 </span><span class="lineCov">        272 :       ever_written_3 &lt;= 1'h0;</span></a>
+<a name="91"><span class="lineNum">      91 </span><span class="lineCov">        272 :       state_reg &lt;= 3'h0;</span></a>
+<a name="92"><span class="lineNum">      92 </span>            :     end</a>
+<a name="93"><span class="lineNum">      93 </span><span class="lineCov">     127458 :     else begin</span></a>
+<a name="94"><span class="lineNum">      94 </span><span class="lineCov">     127458 :       ever_written_0 &lt;= io_wen &amp; ~hit &amp; enq_idx == 2'h0 | ever_written_0;</span></a>
+<a name="95"><span class="lineNum">      95 </span><span class="lineCov">     127458 :       ever_written_1 &lt;= io_wen &amp; ~hit &amp; enq_idx == 2'h1 | ever_written_1;</span></a>
+<a name="96"><span class="lineNum">      96 </span><span class="lineCov">     127458 :       ever_written_2 &lt;= io_wen &amp; ~hit &amp; enq_idx == 2'h2 | ever_written_2;</span></a>
+<a name="97"><span class="lineNum">      97 </span><span class="lineCov">     127458 :       ever_written_3 &lt;= io_wen &amp; ~hit &amp; (&amp;enq_idx) | ever_written_3;</span></a>
+<a name="98"><span class="lineNum">      98 </span><span class="lineCov">         26 :       if (io_wen)</span></a>
+<a name="99"><span class="lineNum">      99 </span><span class="lineCov">         13 :         state_reg &lt;=</span></a>
+<a name="100"><span class="lineNum">     100 </span><span class="lineCov">         13 :           {~(state_reg_touch_way_sized[1]),</span></a>
+<a name="101"><span class="lineNum">     101 </span><span class="lineCov">         13 :            state_reg_touch_way_sized[1] ? ~(state_reg_touch_way_sized[0]) : state_reg[1],</span></a>
+<a name="102"><span class="lineNum">     102 </span><span class="lineCov">         13 :            state_reg_touch_way_sized[1] ? state_reg[0] : ~(state_reg_touch_way_sized[0])};</span></a>
+<a name="103"><span class="lineNum">     103 </span>            :     end</a>
+<a name="104"><span class="lineNum">     104 </span>            :   end // always @(posedge, posedge)</a>
+<a name="105"><span class="lineNum">     105 </span>            :   `ifdef ENABLE_INITIAL_REG_</a>
+<a name="106"><span class="lineNum">     106 </span>            :     `ifdef FIRRTL_BEFORE_INITIAL</a>
+<a name="107"><span class="lineNum">     107 </span>            :       `FIRRTL_BEFORE_INITIAL</a>
+<a name="108"><span class="lineNum">     108 </span>            :     `endif // FIRRTL_BEFORE_INITIAL</a>
+<a name="109"><span class="lineNum">     109 </span>            :     logic [31:0] _RANDOM[0:0];</a>
+<a name="110"><span class="lineNum">     110 </span><span class="lineCov">        116 :     initial begin</span></a>
+<a name="111"><span class="lineNum">     111 </span>            :       `ifdef INIT_RANDOM_PROLOG_</a>
+<a name="112"><span class="lineNum">     112 </span>            :         `INIT_RANDOM_PROLOG_</a>
+<a name="113"><span class="lineNum">     113 </span>            :       `endif // INIT_RANDOM_PROLOG_</a>
+<a name="114"><span class="lineNum">     114 </span>            :       `ifdef RANDOMIZE_REG_INIT</a>
+<a name="115"><span class="lineNum">     115 </span>            :         _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;</a>
+<a name="116"><span class="lineNum">     116 </span>            :         ever_written_0 = _RANDOM[/*Zero width*/ 1'b0][4];</a>
+<a name="117"><span class="lineNum">     117 </span>            :         ever_written_1 = _RANDOM[/*Zero width*/ 1'b0][5];</a>
+<a name="118"><span class="lineNum">     118 </span>            :         ever_written_2 = _RANDOM[/*Zero width*/ 1'b0][6];</a>
+<a name="119"><span class="lineNum">     119 </span>            :         ever_written_3 = _RANDOM[/*Zero width*/ 1'b0][7];</a>
+<a name="120"><span class="lineNum">     120 </span>            :         state_reg = _RANDOM[/*Zero width*/ 1'b0][10:8];</a>
+<a name="121"><span class="lineNum">     121 </span>            :       `endif // RANDOMIZE_REG_INIT</a>
+<a name="122"><span class="lineNum">     122 </span><span class="lineCov">         34 :       if (reset) begin</span></a>
+<a name="123"><span class="lineNum">     123 </span><span class="lineCov">         24 :         ever_written_0 = 1'h0;</span></a>
+<a name="124"><span class="lineNum">     124 </span><span class="lineCov">         24 :         ever_written_1 = 1'h0;</span></a>
+<a name="125"><span class="lineNum">     125 </span><span class="lineCov">         24 :         ever_written_2 = 1'h0;</span></a>
+<a name="126"><span class="lineNum">     126 </span><span class="lineCov">         24 :         ever_written_3 = 1'h0;</span></a>
+<a name="127"><span class="lineNum">     127 </span><span class="lineCov">         24 :         state_reg = 3'h0;</span></a>
+<a name="128"><span class="lineNum">     128 </span>            :       end</a>
+<a name="129"><span class="lineNum">     129 </span>            :     end // initial</a>
+<a name="130"><span class="lineNum">     130 </span>            :     `ifdef FIRRTL_AFTER_INITIAL</a>
+<a name="131"><span class="lineNum">     131 </span>            :       `FIRRTL_AFTER_INITIAL</a>
+<a name="132"><span class="lineNum">     132 </span>            :     `endif // FIRRTL_AFTER_INITIAL</a>
+<a name="133"><span class="lineNum">     133 </span>            :   `endif // ENABLE_INITIAL_REG_</a>
+<a name="134"><span class="lineNum">     134 </span>            :   CAMTemplate_41 idx_tag_cam (</a>
+<a name="135"><span class="lineNum">     135 </span>            :     .clock              (clock),</a>
+<a name="136"><span class="lineNum">     136 </span>            :     .io_r_req_0_idx     (io_write_idx),</a>
+<a name="137"><span class="lineNum">     137 </span>            :     .io_r_resp_0_0      (_idx_tag_cam_io_r_resp_0_0),</a>
+<a name="138"><span class="lineNum">     138 </span>            :     .io_r_resp_0_1      (_idx_tag_cam_io_r_resp_0_1),</a>
+<a name="139"><span class="lineNum">     139 </span>            :     .io_r_resp_0_2      (_idx_tag_cam_io_r_resp_0_2),</a>
+<a name="140"><span class="lineNum">     140 </span>            :     .io_r_resp_0_3      (_idx_tag_cam_io_r_resp_0_3),</a>
+<a name="141"><span class="lineNum">     141 </span>            :     .io_w_valid         (io_wen &amp; ~hit),</a>
+<a name="142"><span class="lineNum">     142 </span>            :     .io_w_bits_data_idx (io_write_idx),</a>
+<a name="143"><span class="lineNum">     143 </span>            :     .io_w_bits_index    (enq_idx)</a>
+<a name="144"><span class="lineNum">     144 </span>            :   );</a>
+<a name="145"><span class="lineNum">     145 </span>            :   data_mem_0_4x2 data_mem_0_ext (</a>
+<a name="146"><span class="lineNum">     146 </span>            :     .R0_addr (hit_idx),</a>
+<a name="147"><span class="lineNum">     147 </span>            :     .R0_en   (1'h1),</a>
+<a name="148"><span class="lineNum">     148 </span>            :     .R0_clk  (clock),</a>
+<a name="149"><span class="lineNum">     149 </span>            :     .R0_data (io_hit_data_0_bits),</a>
+<a name="150"><span class="lineNum">     150 </span>            :     .W0_addr (hit ? hit_idx : enq_idx),</a>
+<a name="151"><span class="lineNum">     151 </span>            :     .W0_en   (io_wen),</a>
+<a name="152"><span class="lineNum">     152 </span>            :     .W0_clk  (clock),</a>
+<a name="153"><span class="lineNum">     153 </span>            :     .W0_data (io_write_data_0)</a>
+<a name="154"><span class="lineNum">     154 </span>            :   );</a>
+<a name="155"><span class="lineNum">     155 </span>            :   assign io_hit = hit;</a>
+<a name="156"><span class="lineNum">     156 </span>            : endmodule</a>
+<a name="157"><span class="lineNum">     157 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/WrBypass_43.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/WrBypass_43.sv.func-sort-c.html
new file mode 100644
index 0000000..3c5890a
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/WrBypass_43.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/WrBypass_43.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - WrBypass_43.sv<span style="font-size: 80%;"> (<a href="WrBypass_43.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">43</td>
+            <td class="headerCovTableEntry">43</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="WrBypass_43.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/WrBypass_43.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/WrBypass_43.sv.func.html
new file mode 100644
index 0000000..cc2749d
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/WrBypass_43.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/WrBypass_43.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - WrBypass_43.sv<span style="font-size: 80%;"> (<a href="WrBypass_43.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">43</td>
+            <td class="headerCovTableEntry">43</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="WrBypass_43.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/WrBypass_43.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/WrBypass_43.sv.gcov.html
new file mode 100644
index 0000000..05d1eb2
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/WrBypass_43.sv.gcov.html
@@ -0,0 +1,233 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/WrBypass_43.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - WrBypass_43.sv<span style="font-size: 80%;"> (source / <a href="WrBypass_43.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">43</td>
+            <td class="headerCovTableEntry">43</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : module WrBypass_43(</a>
+<a name="59"><span class="lineNum">      59 </span><span class="lineCov">     127786 :   input        clock,</span></a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">         62 :   input        reset,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">         24 :   input        io_wen,</span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">        125 :   input  [8:0] io_write_idx,</span></a>
+<a name="63"><span class="lineNum">      63 </span><span class="lineCov">         33 :   input  [1:0] io_write_data_0,</span></a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">         91 :   output       io_hit,</span></a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">        144 :   output [1:0] io_hit_data_0_bits</span></a>
+<a name="66"><span class="lineNum">      66 </span>            : );</a>
+<a name="67"><span class="lineNum">      67 </span>            : </a>
+<a name="68"><span class="lineNum">      68 </span>            :   wire       _idx_tag_cam_io_r_resp_0_0;</a>
+<a name="69"><span class="lineNum">      69 </span>            :   wire       _idx_tag_cam_io_r_resp_0_1;</a>
+<a name="70"><span class="lineNum">      70 </span>            :   wire       _idx_tag_cam_io_r_resp_0_2;</a>
+<a name="71"><span class="lineNum">      71 </span>            :   wire       _idx_tag_cam_io_r_resp_0_3;</a>
+<a name="72"><span class="lineNum">      72 </span><span class="lineCov">         81 :   reg        ever_written_0;</span></a>
+<a name="73"><span class="lineNum">      73 </span><span class="lineCov">         70 :   reg        ever_written_1;</span></a>
+<a name="74"><span class="lineNum">      74 </span><span class="lineCov">         76 :   reg        ever_written_2;</span></a>
+<a name="75"><span class="lineNum">      75 </span><span class="lineCov">         67 :   reg        ever_written_3;</span></a>
+<a name="76"><span class="lineNum">      76 </span><span class="lineCov">         48 :   wire       hits_oh_1 = _idx_tag_cam_io_r_resp_0_1 &amp; ever_written_1;</span></a>
+<a name="77"><span class="lineNum">      77 </span><span class="lineCov">         58 :   wire       hits_oh_2 = _idx_tag_cam_io_r_resp_0_2 &amp; ever_written_2;</span></a>
+<a name="78"><span class="lineNum">      78 </span><span class="lineCov">         50 :   wire       hits_oh_3 = _idx_tag_cam_io_r_resp_0_3 &amp; ever_written_3;</span></a>
+<a name="79"><span class="lineNum">      79 </span><span class="lineCov">        119 :   wire [1:0] hit_idx = {|{hits_oh_3, hits_oh_2}, hits_oh_3 | hits_oh_1};</span></a>
+<a name="80"><span class="lineNum">      80 </span><span class="lineCov">         91 :   wire       hit =</span></a>
+<a name="81"><span class="lineNum">      81 </span>            :     _idx_tag_cam_io_r_resp_0_0 &amp; ever_written_0 | hits_oh_1 | hits_oh_2 | hits_oh_3;</a>
+<a name="82"><span class="lineNum">      82 </span><span class="lineCov">        259 :   reg  [2:0] state_reg;</span></a>
+<a name="83"><span class="lineNum">      83 </span><span class="lineCov">        180 :   wire [1:0] enq_idx = {state_reg[2], state_reg[2] ? state_reg[1] : state_reg[0]};</span></a>
+<a name="84"><span class="lineNum">      84 </span><span class="lineCov">        143 :   wire [1:0] state_reg_touch_way_sized = hit ? hit_idx : enq_idx;</span></a>
+<a name="85"><span class="lineNum">      85 </span><span class="lineCov">     383190 :   always @(posedge clock or posedge reset) begin</span></a>
+<a name="86"><span class="lineNum">      86 </span><span class="lineCov">        816 :     if (reset) begin</span></a>
+<a name="87"><span class="lineNum">      87 </span><span class="lineCov">        408 :       ever_written_0 &lt;= 1'h0;</span></a>
+<a name="88"><span class="lineNum">      88 </span><span class="lineCov">        408 :       ever_written_1 &lt;= 1'h0;</span></a>
+<a name="89"><span class="lineNum">      89 </span><span class="lineCov">        408 :       ever_written_2 &lt;= 1'h0;</span></a>
+<a name="90"><span class="lineNum">      90 </span><span class="lineCov">        408 :       ever_written_3 &lt;= 1'h0;</span></a>
+<a name="91"><span class="lineNum">      91 </span><span class="lineCov">        408 :       state_reg &lt;= 3'h0;</span></a>
+<a name="92"><span class="lineNum">      92 </span>            :     end</a>
+<a name="93"><span class="lineNum">      93 </span><span class="lineCov">     191187 :     else begin</span></a>
+<a name="94"><span class="lineNum">      94 </span><span class="lineCov">     191187 :       ever_written_0 &lt;= io_wen &amp; ~hit &amp; enq_idx == 2'h0 | ever_written_0;</span></a>
+<a name="95"><span class="lineNum">      95 </span><span class="lineCov">     191187 :       ever_written_1 &lt;= io_wen &amp; ~hit &amp; enq_idx == 2'h1 | ever_written_1;</span></a>
+<a name="96"><span class="lineNum">      96 </span><span class="lineCov">     191187 :       ever_written_2 &lt;= io_wen &amp; ~hit &amp; enq_idx == 2'h2 | ever_written_2;</span></a>
+<a name="97"><span class="lineNum">      97 </span><span class="lineCov">     191187 :       ever_written_3 &lt;= io_wen &amp; ~hit &amp; (&amp;enq_idx) | ever_written_3;</span></a>
+<a name="98"><span class="lineNum">      98 </span><span class="lineCov">         42 :       if (io_wen)</span></a>
+<a name="99"><span class="lineNum">      99 </span><span class="lineCov">         21 :         state_reg &lt;=</span></a>
+<a name="100"><span class="lineNum">     100 </span><span class="lineCov">         21 :           {~(state_reg_touch_way_sized[1]),</span></a>
+<a name="101"><span class="lineNum">     101 </span><span class="lineCov">         21 :            state_reg_touch_way_sized[1] ? ~(state_reg_touch_way_sized[0]) : state_reg[1],</span></a>
+<a name="102"><span class="lineNum">     102 </span><span class="lineCov">         21 :            state_reg_touch_way_sized[1] ? state_reg[0] : ~(state_reg_touch_way_sized[0])};</span></a>
+<a name="103"><span class="lineNum">     103 </span>            :     end</a>
+<a name="104"><span class="lineNum">     104 </span>            :   end // always @(posedge, posedge)</a>
+<a name="105"><span class="lineNum">     105 </span>            :   `ifdef ENABLE_INITIAL_REG_</a>
+<a name="106"><span class="lineNum">     106 </span>            :     `ifdef FIRRTL_BEFORE_INITIAL</a>
+<a name="107"><span class="lineNum">     107 </span>            :       `FIRRTL_BEFORE_INITIAL</a>
+<a name="108"><span class="lineNum">     108 </span>            :     `endif // FIRRTL_BEFORE_INITIAL</a>
+<a name="109"><span class="lineNum">     109 </span>            :     logic [31:0] _RANDOM[0:0];</a>
+<a name="110"><span class="lineNum">     110 </span><span class="lineCov">        174 :     initial begin</span></a>
+<a name="111"><span class="lineNum">     111 </span>            :       `ifdef INIT_RANDOM_PROLOG_</a>
+<a name="112"><span class="lineNum">     112 </span>            :         `INIT_RANDOM_PROLOG_</a>
+<a name="113"><span class="lineNum">     113 </span>            :       `endif // INIT_RANDOM_PROLOG_</a>
+<a name="114"><span class="lineNum">     114 </span>            :       `ifdef RANDOMIZE_REG_INIT</a>
+<a name="115"><span class="lineNum">     115 </span>            :         _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;</a>
+<a name="116"><span class="lineNum">     116 </span>            :         ever_written_0 = _RANDOM[/*Zero width*/ 1'b0][4];</a>
+<a name="117"><span class="lineNum">     117 </span>            :         ever_written_1 = _RANDOM[/*Zero width*/ 1'b0][5];</a>
+<a name="118"><span class="lineNum">     118 </span>            :         ever_written_2 = _RANDOM[/*Zero width*/ 1'b0][6];</a>
+<a name="119"><span class="lineNum">     119 </span>            :         ever_written_3 = _RANDOM[/*Zero width*/ 1'b0][7];</a>
+<a name="120"><span class="lineNum">     120 </span>            :         state_reg = _RANDOM[/*Zero width*/ 1'b0][10:8];</a>
+<a name="121"><span class="lineNum">     121 </span>            :       `endif // RANDOMIZE_REG_INIT</a>
+<a name="122"><span class="lineNum">     122 </span><span class="lineCov">         51 :       if (reset) begin</span></a>
+<a name="123"><span class="lineNum">     123 </span><span class="lineCov">         36 :         ever_written_0 = 1'h0;</span></a>
+<a name="124"><span class="lineNum">     124 </span><span class="lineCov">         36 :         ever_written_1 = 1'h0;</span></a>
+<a name="125"><span class="lineNum">     125 </span><span class="lineCov">         36 :         ever_written_2 = 1'h0;</span></a>
+<a name="126"><span class="lineNum">     126 </span><span class="lineCov">         36 :         ever_written_3 = 1'h0;</span></a>
+<a name="127"><span class="lineNum">     127 </span><span class="lineCov">         36 :         state_reg = 3'h0;</span></a>
+<a name="128"><span class="lineNum">     128 </span>            :       end</a>
+<a name="129"><span class="lineNum">     129 </span>            :     end // initial</a>
+<a name="130"><span class="lineNum">     130 </span>            :     `ifdef FIRRTL_AFTER_INITIAL</a>
+<a name="131"><span class="lineNum">     131 </span>            :       `FIRRTL_AFTER_INITIAL</a>
+<a name="132"><span class="lineNum">     132 </span>            :     `endif // FIRRTL_AFTER_INITIAL</a>
+<a name="133"><span class="lineNum">     133 </span>            :   `endif // ENABLE_INITIAL_REG_</a>
+<a name="134"><span class="lineNum">     134 </span>            :   CAMTemplate_43 idx_tag_cam (</a>
+<a name="135"><span class="lineNum">     135 </span>            :     .clock              (clock),</a>
+<a name="136"><span class="lineNum">     136 </span>            :     .io_r_req_0_idx     (io_write_idx),</a>
+<a name="137"><span class="lineNum">     137 </span>            :     .io_r_resp_0_0      (_idx_tag_cam_io_r_resp_0_0),</a>
+<a name="138"><span class="lineNum">     138 </span>            :     .io_r_resp_0_1      (_idx_tag_cam_io_r_resp_0_1),</a>
+<a name="139"><span class="lineNum">     139 </span>            :     .io_r_resp_0_2      (_idx_tag_cam_io_r_resp_0_2),</a>
+<a name="140"><span class="lineNum">     140 </span>            :     .io_r_resp_0_3      (_idx_tag_cam_io_r_resp_0_3),</a>
+<a name="141"><span class="lineNum">     141 </span>            :     .io_w_valid         (io_wen &amp; ~hit),</a>
+<a name="142"><span class="lineNum">     142 </span>            :     .io_w_bits_data_idx (io_write_idx),</a>
+<a name="143"><span class="lineNum">     143 </span>            :     .io_w_bits_index    (enq_idx)</a>
+<a name="144"><span class="lineNum">     144 </span>            :   );</a>
+<a name="145"><span class="lineNum">     145 </span>            :   data_mem_0_4x2 data_mem_0_ext (</a>
+<a name="146"><span class="lineNum">     146 </span>            :     .R0_addr (hit_idx),</a>
+<a name="147"><span class="lineNum">     147 </span>            :     .R0_en   (1'h1),</a>
+<a name="148"><span class="lineNum">     148 </span>            :     .R0_clk  (clock),</a>
+<a name="149"><span class="lineNum">     149 </span>            :     .R0_data (io_hit_data_0_bits),</a>
+<a name="150"><span class="lineNum">     150 </span>            :     .W0_addr (hit ? hit_idx : enq_idx),</a>
+<a name="151"><span class="lineNum">     151 </span>            :     .W0_en   (io_wen),</a>
+<a name="152"><span class="lineNum">     152 </span>            :     .W0_clk  (clock),</a>
+<a name="153"><span class="lineNum">     153 </span>            :     .W0_data (io_write_data_0)</a>
+<a name="154"><span class="lineNum">     154 </span>            :   );</a>
+<a name="155"><span class="lineNum">     155 </span>            :   assign io_hit = hit;</a>
+<a name="156"><span class="lineNum">     156 </span>            : endmodule</a>
+<a name="157"><span class="lineNum">     157 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_0_0.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_0_0.sv.func-sort-c.html
new file mode 100644
index 0000000..4ac5752
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_0_0.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/array_0_0.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - array_0_0.sv<span style="font-size: 80%;"> (<a href="array_0_0.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">6</td>
+            <td class="headerCovTableEntry">6</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="array_0_0.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_0_0.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_0_0.sv.func.html
new file mode 100644
index 0000000..b41aa04
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_0_0.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/array_0_0.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - array_0_0.sv<span style="font-size: 80%;"> (<a href="array_0_0.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">6</td>
+            <td class="headerCovTableEntry">6</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="array_0_0.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_0_0.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_0_0.sv.gcov.html
new file mode 100644
index 0000000..086255e
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_0_0.sv.gcov.html
@@ -0,0 +1,152 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/array_0_0.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - array_0_0.sv<span style="font-size: 80%;"> (source / <a href="array_0_0.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">6</td>
+            <td class="headerCovTableEntry">6</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : module array_0_0(</a>
+<a name="59"><span class="lineNum">      59 </span><span class="lineCov">      62194 :   input  [6:0]  RW0_addr,</span></a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">        416 :   input         RW0_en,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">     127786 :   input         RW0_clk,</span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">        209 :   input         RW0_wmode,</span></a>
+<a name="63"><span class="lineNum">      63 </span><span class="lineCov">       7156 :   input  [52:0] RW0_wdata,</span></a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">       6175 :   output [52:0] RW0_rdata</span></a>
+<a name="65"><span class="lineNum">      65 </span>            : );</a>
+<a name="66"><span class="lineNum">      66 </span>            : </a>
+<a name="67"><span class="lineNum">      67 </span>            :   array_0_0_ext array_0_0_ext (</a>
+<a name="68"><span class="lineNum">      68 </span>            :     .RW0_addr  (RW0_addr),</a>
+<a name="69"><span class="lineNum">      69 </span>            :     .RW0_en    (RW0_en),</a>
+<a name="70"><span class="lineNum">      70 </span>            :     .RW0_clk   (RW0_clk),</a>
+<a name="71"><span class="lineNum">      71 </span>            :     .RW0_wmode (RW0_wmode),</a>
+<a name="72"><span class="lineNum">      72 </span>            :     .RW0_wdata (RW0_wdata),</a>
+<a name="73"><span class="lineNum">      73 </span>            :     .RW0_rdata (RW0_rdata)</a>
+<a name="74"><span class="lineNum">      74 </span>            :   );</a>
+<a name="75"><span class="lineNum">      75 </span>            : endmodule</a>
+<a name="76"><span class="lineNum">      76 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_0_0_ext.v.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_0_0_ext.v.func-sort-c.html
new file mode 100644
index 0000000..52f7a8c
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_0_0_ext.v.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/array_0_0_ext.v - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - array_0_0_ext.v<span style="font-size: 80%;"> (<a href="array_0_0_ext.v.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">16</td>
+            <td class="headerCovTableEntry">16</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="array_0_0_ext.v.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_0_0_ext.v.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_0_0_ext.v.func.html
new file mode 100644
index 0000000..a5901a8
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_0_0_ext.v.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/array_0_0_ext.v - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - array_0_0_ext.v<span style="font-size: 80%;"> (<a href="array_0_0_ext.v.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">16</td>
+            <td class="headerCovTableEntry">16</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="array_0_0_ext.v.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_0_0_ext.v.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_0_0_ext.v.gcov.html
new file mode 100644
index 0000000..903698f
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_0_0_ext.v.gcov.html
@@ -0,0 +1,125 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/array_0_0_ext.v</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - array_0_0_ext.v<span style="font-size: 80%;"> (source / <a href="array_0_0_ext.v.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">16</td>
+            <td class="headerCovTableEntry">16</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : </a>
+<a name="2"><span class="lineNum">       2 </span>            : module array_0_0_ext(</a>
+<a name="3"><span class="lineNum">       3 </span><span class="lineCov">     127786 :   input RW0_clk,</span></a>
+<a name="4"><span class="lineNum">       4 </span><span class="lineCov">      62194 :   input [6:0] RW0_addr,</span></a>
+<a name="5"><span class="lineNum">       5 </span><span class="lineCov">        416 :   input RW0_en,</span></a>
+<a name="6"><span class="lineNum">       6 </span><span class="lineCov">        209 :   input RW0_wmode,</span></a>
+<a name="7"><span class="lineNum">       7 </span><span class="lineCov">       7156 :   input [52:0] RW0_wdata,</span></a>
+<a name="8"><span class="lineNum">       8 </span><span class="lineCov">       6175 :   output [52:0] RW0_rdata</span></a>
+<a name="9"><span class="lineNum">       9 </span>            : );</a>
+<a name="10"><span class="lineNum">      10 </span>            : </a>
+<a name="11"><span class="lineNum">      11 </span><span class="lineCov">        302 :   reg reg_RW0_ren;</span></a>
+<a name="12"><span class="lineNum">      12 </span><span class="lineCov">      16174 :   reg [6:0] reg_RW0_addr;</span></a>
+<a name="13"><span class="lineNum">      13 </span>            :   reg [52:0] ram [127:0];</a>
+<a name="14"><span class="lineNum">      14 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="15"><span class="lineNum">      15 </span>            :     integer initvar;</a>
+<a name="16"><span class="lineNum">      16 </span>            :     initial begin</a>
+<a name="17"><span class="lineNum">      17 </span>            :       #`RANDOMIZE_DELAY begin end</a>
+<a name="18"><span class="lineNum">      18 </span>            :       for (initvar = 0; initvar &lt; 128; initvar = initvar+1)</a>
+<a name="19"><span class="lineNum">      19 </span>            :         ram[initvar] = {2 {$random}};</a>
+<a name="20"><span class="lineNum">      20 </span>            :       reg_RW0_addr = {1 {$random}};</a>
+<a name="21"><span class="lineNum">      21 </span>            :     end</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `endif</a>
+<a name="23"><span class="lineNum">      23 </span>            :   integer i;</a>
+<a name="24"><span class="lineNum">      24 </span><span class="lineCov">     510776 :   always @(posedge RW0_clk)</span></a>
+<a name="25"><span class="lineNum">      25 </span><span class="lineCov">     255388 :     reg_RW0_ren &lt;= RW0_en &amp;&amp; !RW0_wmode;</span></a>
+<a name="26"><span class="lineNum">      26 </span><span class="lineCov">     510776 :   always @(posedge RW0_clk)</span></a>
+<a name="27"><span class="lineNum">      27 </span><span class="lineCov">      16700 :     if (RW0_en &amp;&amp; !RW0_wmode) reg_RW0_addr &lt;= RW0_addr;</span></a>
+<a name="28"><span class="lineNum">      28 </span><span class="lineCov">     510776 :   always @(posedge RW0_clk)</span></a>
+<a name="29"><span class="lineNum">      29 </span><span class="lineCov">      31498 :     if (RW0_en &amp;&amp; RW0_wmode) begin</span></a>
+<a name="30"><span class="lineNum">      30 </span><span class="lineCov">      15749 :       for (i=0;i&lt;1;i=i+1) begin</span></a>
+<a name="31"><span class="lineNum">      31 </span><span class="lineCov">      15749 :         ram[RW0_addr][i*53 +: 53] &lt;= RW0_wdata[i*53 +: 53];</span></a>
+<a name="32"><span class="lineNum">      32 </span>            :       end</a>
+<a name="33"><span class="lineNum">      33 </span>            :     end</a>
+<a name="34"><span class="lineNum">      34 </span>            :   `ifdef RANDOMIZE_GARBAGE_ASSIGN</a>
+<a name="35"><span class="lineNum">      35 </span>            :   reg [63:0] RW0_random;</a>
+<a name="36"><span class="lineNum">      36 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="37"><span class="lineNum">      37 </span>            :     initial begin</a>
+<a name="38"><span class="lineNum">      38 </span>            :       #`RANDOMIZE_DELAY begin end</a>
+<a name="39"><span class="lineNum">      39 </span>            :       RW0_random = {$random, $random};</a>
+<a name="40"><span class="lineNum">      40 </span>            :       reg_RW0_ren = RW0_random[0];</a>
+<a name="41"><span class="lineNum">      41 </span>            :     end</a>
+<a name="42"><span class="lineNum">      42 </span>            :   `endif</a>
+<a name="43"><span class="lineNum">      43 </span>            :   always @(posedge RW0_clk) RW0_random &lt;= {$random, $random};</a>
+<a name="44"><span class="lineNum">      44 </span>            :   assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[52:0];</a>
+<a name="45"><span class="lineNum">      45 </span>            :   `else</a>
+<a name="46"><span class="lineNum">      46 </span>            :   assign RW0_rdata = ram[reg_RW0_addr];</a>
+<a name="47"><span class="lineNum">      47 </span>            :   `endif</a>
+<a name="48"><span class="lineNum">      48 </span>            : </a>
+<a name="49"><span class="lineNum">      49 </span>            : endmodule</a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_3.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_3.sv.func-sort-c.html
new file mode 100644
index 0000000..1e82008
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_3.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/array_3.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - array_3.sv<span style="font-size: 80%;"> (<a href="array_3.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">5</td>
+            <td class="headerCovTableEntry">5</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="array_3.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_3.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_3.sv.func.html
new file mode 100644
index 0000000..37feacf
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_3.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/array_3.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - array_3.sv<span style="font-size: 80%;"> (<a href="array_3.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">5</td>
+            <td class="headerCovTableEntry">5</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="array_3.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_3.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_3.sv.gcov.html
new file mode 100644
index 0000000..2d0a9c3
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_3.sv.gcov.html
@@ -0,0 +1,154 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/array_3.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - array_3.sv<span style="font-size: 80%;"> (source / <a href="array_3.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">5</td>
+            <td class="headerCovTableEntry">5</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : module array_3(</a>
+<a name="59"><span class="lineNum">      59 </span><span class="lineCov">      38293 :   input  [8:0]   RW0_addr,</span></a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">        112 :   input          RW0_en,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">     127786 :   input          RW0_clk,</span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">         89 :   input          RW0_wmode,</span></a>
+<a name="63"><span class="lineNum">      63 </span>            :   input  [319:0] RW0_wdata,</a>
+<a name="64"><span class="lineNum">      64 </span>            :   output [319:0] RW0_rdata,</a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">        278 :   input  [3:0]   RW0_wmask</span></a>
+<a name="66"><span class="lineNum">      66 </span>            : );</a>
+<a name="67"><span class="lineNum">      67 </span>            : </a>
+<a name="68"><span class="lineNum">      68 </span>            :   array_3_ext array_3_ext (</a>
+<a name="69"><span class="lineNum">      69 </span>            :     .RW0_addr  (RW0_addr),</a>
+<a name="70"><span class="lineNum">      70 </span>            :     .RW0_en    (RW0_en),</a>
+<a name="71"><span class="lineNum">      71 </span>            :     .RW0_clk   (RW0_clk),</a>
+<a name="72"><span class="lineNum">      72 </span>            :     .RW0_wmode (RW0_wmode),</a>
+<a name="73"><span class="lineNum">      73 </span>            :     .RW0_wdata (RW0_wdata),</a>
+<a name="74"><span class="lineNum">      74 </span>            :     .RW0_rdata (RW0_rdata),</a>
+<a name="75"><span class="lineNum">      75 </span>            :     .RW0_wmask (RW0_wmask)</a>
+<a name="76"><span class="lineNum">      76 </span>            :   );</a>
+<a name="77"><span class="lineNum">      77 </span>            : endmodule</a>
+<a name="78"><span class="lineNum">      78 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_3_ext.v.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_3_ext.v.func-sort-c.html
new file mode 100644
index 0000000..10faa54
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_3_ext.v.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/array_3_ext.v - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - array_3_ext.v<span style="font-size: 80%;"> (<a href="array_3_ext.v.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">16</td>
+            <td class="headerCovTableEntry">16</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="array_3_ext.v.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_3_ext.v.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_3_ext.v.func.html
new file mode 100644
index 0000000..a7c78e4
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_3_ext.v.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/array_3_ext.v - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - array_3_ext.v<span style="font-size: 80%;"> (<a href="array_3_ext.v.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">16</td>
+            <td class="headerCovTableEntry">16</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="array_3_ext.v.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_3_ext.v.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_3_ext.v.gcov.html
new file mode 100644
index 0000000..462f080
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_3_ext.v.gcov.html
@@ -0,0 +1,128 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/array_3_ext.v</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - array_3_ext.v<span style="font-size: 80%;"> (source / <a href="array_3_ext.v.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">16</td>
+            <td class="headerCovTableEntry">16</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : </a>
+<a name="2"><span class="lineNum">       2 </span>            : module array_3_ext(</a>
+<a name="3"><span class="lineNum">       3 </span><span class="lineCov">     127786 :   input RW0_clk,</span></a>
+<a name="4"><span class="lineNum">       4 </span><span class="lineCov">      38293 :   input [8:0] RW0_addr,</span></a>
+<a name="5"><span class="lineNum">       5 </span><span class="lineCov">        112 :   input RW0_en,</span></a>
+<a name="6"><span class="lineNum">       6 </span><span class="lineCov">         89 :   input RW0_wmode,</span></a>
+<a name="7"><span class="lineNum">       7 </span><span class="lineCov">        278 :   input [3:0] RW0_wmask,</span></a>
+<a name="8"><span class="lineNum">       8 </span>            :   input [319:0] RW0_wdata,</a>
+<a name="9"><span class="lineNum">       9 </span>            :   output [319:0] RW0_rdata</a>
+<a name="10"><span class="lineNum">      10 </span>            : );</a>
+<a name="11"><span class="lineNum">      11 </span>            : </a>
+<a name="12"><span class="lineNum">      12 </span><span class="lineCov">         87 :   reg reg_RW0_ren;</span></a>
+<a name="13"><span class="lineNum">      13 </span><span class="lineCov">       8335 :   reg [8:0] reg_RW0_addr;</span></a>
+<a name="14"><span class="lineNum">      14 </span>            :   reg [319:0] ram [511:0];</a>
+<a name="15"><span class="lineNum">      15 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="16"><span class="lineNum">      16 </span>            :     integer initvar;</a>
+<a name="17"><span class="lineNum">      17 </span>            :     initial begin</a>
+<a name="18"><span class="lineNum">      18 </span>            :       #`RANDOMIZE_DELAY begin end</a>
+<a name="19"><span class="lineNum">      19 </span>            :       for (initvar = 0; initvar &lt; 512; initvar = initvar+1)</a>
+<a name="20"><span class="lineNum">      20 </span>            :         ram[initvar] = {10 {$random}};</a>
+<a name="21"><span class="lineNum">      21 </span>            :       reg_RW0_addr = {1 {$random}};</a>
+<a name="22"><span class="lineNum">      22 </span>            :     end</a>
+<a name="23"><span class="lineNum">      23 </span>            :   `endif</a>
+<a name="24"><span class="lineNum">      24 </span>            :   integer i;</a>
+<a name="25"><span class="lineNum">      25 </span><span class="lineCov">     127694 :   always @(posedge RW0_clk)</span></a>
+<a name="26"><span class="lineNum">      26 </span><span class="lineCov">      63847 :     reg_RW0_ren &lt;= RW0_en &amp;&amp; !RW0_wmode;</span></a>
+<a name="27"><span class="lineNum">      27 </span><span class="lineCov">     127694 :   always @(posedge RW0_clk)</span></a>
+<a name="28"><span class="lineNum">      28 </span><span class="lineCov">       8384 :     if (RW0_en &amp;&amp; !RW0_wmode) reg_RW0_addr &lt;= RW0_addr;</span></a>
+<a name="29"><span class="lineNum">      29 </span><span class="lineCov">     127694 :   always @(posedge RW0_clk)</span></a>
+<a name="30"><span class="lineNum">      30 </span><span class="lineCov">      30186 :     if (RW0_en &amp;&amp; RW0_wmode) begin</span></a>
+<a name="31"><span class="lineNum">      31 </span><span class="lineCov">      15093 :       for (i=0;i&lt;4;i=i+1) begin</span></a>
+<a name="32"><span class="lineNum">      32 </span><span class="lineCov">         63 :         if (RW0_wmask[i]) begin</span></a>
+<a name="33"><span class="lineNum">      33 </span><span class="lineCov">      60309 :           ram[RW0_addr][i*80 +: 80] &lt;= RW0_wdata[i*80 +: 80];</span></a>
+<a name="34"><span class="lineNum">      34 </span>            :         end</a>
+<a name="35"><span class="lineNum">      35 </span>            :       end</a>
+<a name="36"><span class="lineNum">      36 </span>            :     end</a>
+<a name="37"><span class="lineNum">      37 </span>            :   `ifdef RANDOMIZE_GARBAGE_ASSIGN</a>
+<a name="38"><span class="lineNum">      38 </span>            :   reg [319:0] RW0_random;</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="40"><span class="lineNum">      40 </span>            :     initial begin</a>
+<a name="41"><span class="lineNum">      41 </span>            :       #`RANDOMIZE_DELAY begin end</a>
+<a name="42"><span class="lineNum">      42 </span>            :       RW0_random = {$random, $random, $random, $random, $random, $random, $random, $random, $random, $random};</a>
+<a name="43"><span class="lineNum">      43 </span>            :       reg_RW0_ren = RW0_random[0];</a>
+<a name="44"><span class="lineNum">      44 </span>            :     end</a>
+<a name="45"><span class="lineNum">      45 </span>            :   `endif</a>
+<a name="46"><span class="lineNum">      46 </span>            :   always @(posedge RW0_clk) RW0_random &lt;= {$random, $random, $random, $random, $random, $random, $random, $random, $random, $random};</a>
+<a name="47"><span class="lineNum">      47 </span>            :   assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[319:0];</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `else</a>
+<a name="49"><span class="lineNum">      49 </span>            :   assign RW0_rdata = ram[reg_RW0_addr];</a>
+<a name="50"><span class="lineNum">      50 </span>            :   `endif</a>
+<a name="51"><span class="lineNum">      51 </span>            : </a>
+<a name="52"><span class="lineNum">      52 </span>            : endmodule</a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_4.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_4.sv.func-sort-c.html
new file mode 100644
index 0000000..e73e315
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_4.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/array_4.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - array_4.sv<span style="font-size: 80%;"> (<a href="array_4.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">7</td>
+            <td class="headerCovTableEntry">7</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="array_4.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_4.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_4.sv.func.html
new file mode 100644
index 0000000..9e1299b
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_4.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/array_4.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - array_4.sv<span style="font-size: 80%;"> (<a href="array_4.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">7</td>
+            <td class="headerCovTableEntry">7</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="array_4.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_4.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_4.sv.gcov.html
new file mode 100644
index 0000000..ea7f3e4
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_4.sv.gcov.html
@@ -0,0 +1,154 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/array_4.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - array_4.sv<span style="font-size: 80%;"> (source / <a href="array_4.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">7</td>
+            <td class="headerCovTableEntry">7</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : module array_4(</a>
+<a name="59"><span class="lineNum">      59 </span><span class="lineCov">      93556 :   input  [7:0]  RW0_addr,</span></a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">        444 :   input         RW0_en,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">     127786 :   input         RW0_clk,</span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">        195 :   input         RW0_wmode,</span></a>
+<a name="63"><span class="lineNum">      63 </span><span class="lineCov">       2110 :   input  [15:0] RW0_wdata,</span></a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">       1829 :   output [15:0] RW0_rdata,</span></a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">       3103 :   input  [15:0] RW0_wmask</span></a>
+<a name="66"><span class="lineNum">      66 </span>            : );</a>
+<a name="67"><span class="lineNum">      67 </span>            : </a>
+<a name="68"><span class="lineNum">      68 </span>            :   array_4_ext array_4_ext (</a>
+<a name="69"><span class="lineNum">      69 </span>            :     .RW0_addr  (RW0_addr),</a>
+<a name="70"><span class="lineNum">      70 </span>            :     .RW0_en    (RW0_en),</a>
+<a name="71"><span class="lineNum">      71 </span>            :     .RW0_clk   (RW0_clk),</a>
+<a name="72"><span class="lineNum">      72 </span>            :     .RW0_wmode (RW0_wmode),</a>
+<a name="73"><span class="lineNum">      73 </span>            :     .RW0_wdata (RW0_wdata),</a>
+<a name="74"><span class="lineNum">      74 </span>            :     .RW0_rdata (RW0_rdata),</a>
+<a name="75"><span class="lineNum">      75 </span>            :     .RW0_wmask (RW0_wmask)</a>
+<a name="76"><span class="lineNum">      76 </span>            :   );</a>
+<a name="77"><span class="lineNum">      77 </span>            : endmodule</a>
+<a name="78"><span class="lineNum">      78 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_4_ext.v.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_4_ext.v.func-sort-c.html
new file mode 100644
index 0000000..579402a
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_4_ext.v.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/array_4_ext.v - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - array_4_ext.v<span style="font-size: 80%;"> (<a href="array_4_ext.v.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">16</td>
+            <td class="headerCovTableEntry">16</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="array_4_ext.v.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_4_ext.v.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_4_ext.v.func.html
new file mode 100644
index 0000000..f121c69
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_4_ext.v.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/array_4_ext.v - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - array_4_ext.v<span style="font-size: 80%;"> (<a href="array_4_ext.v.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">16</td>
+            <td class="headerCovTableEntry">16</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="array_4_ext.v.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_4_ext.v.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_4_ext.v.gcov.html
new file mode 100644
index 0000000..d7a3666
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_4_ext.v.gcov.html
@@ -0,0 +1,124 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/array_4_ext.v</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - array_4_ext.v<span style="font-size: 80%;"> (source / <a href="array_4_ext.v.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">16</td>
+            <td class="headerCovTableEntry">16</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : </a>
+<a name="2"><span class="lineNum">       2 </span>            : module array_4_ext(</a>
+<a name="3"><span class="lineNum">       3 </span><span class="lineCov">     127786 :   input RW0_clk,</span></a>
+<a name="4"><span class="lineNum">       4 </span><span class="lineCov">      93556 :   input [7:0] RW0_addr,</span></a>
+<a name="5"><span class="lineNum">       5 </span><span class="lineCov">        444 :   input RW0_en,</span></a>
+<a name="6"><span class="lineNum">       6 </span><span class="lineCov">        195 :   input RW0_wmode,</span></a>
+<a name="7"><span class="lineNum">       7 </span><span class="lineCov">       3103 :   input [15:0] RW0_wmask,</span></a>
+<a name="8"><span class="lineNum">       8 </span><span class="lineCov">       2110 :   input [15:0] RW0_wdata,</span></a>
+<a name="9"><span class="lineNum">       9 </span><span class="lineCov">       1829 :   output [15:0] RW0_rdata</span></a>
+<a name="10"><span class="lineNum">      10 </span>            : );</a>
+<a name="11"><span class="lineNum">      11 </span>            : </a>
+<a name="12"><span class="lineNum">      12 </span><span class="lineCov">        364 :   reg reg_RW0_ren;</span></a>
+<a name="13"><span class="lineNum">      13 </span><span class="lineCov">      33561 :   reg [7:0] reg_RW0_addr;</span></a>
+<a name="14"><span class="lineNum">      14 </span>            :   reg [15:0] ram [255:0];</a>
+<a name="15"><span class="lineNum">      15 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="16"><span class="lineNum">      16 </span>            :     integer initvar;</a>
+<a name="17"><span class="lineNum">      17 </span>            :     initial begin</a>
+<a name="18"><span class="lineNum">      18 </span>            :       #`RANDOMIZE_DELAY begin end</a>
+<a name="19"><span class="lineNum">      19 </span>            :       for (initvar = 0; initvar &lt; 256; initvar = initvar+1)</a>
+<a name="20"><span class="lineNum">      20 </span>            :         ram[initvar] = {1 {$random}};</a>
+<a name="21"><span class="lineNum">      21 </span>            :       reg_RW0_addr = {1 {$random}};</a>
+<a name="22"><span class="lineNum">      22 </span>            :     end</a>
+<a name="23"><span class="lineNum">      23 </span>            :   `endif</a>
+<a name="24"><span class="lineNum">      24 </span>            :   integer i;</a>
+<a name="25"><span class="lineNum">      25 </span><span class="lineCov">     510776 :   always @(posedge RW0_clk)</span></a>
+<a name="26"><span class="lineNum">      26 </span><span class="lineCov">     255388 :     reg_RW0_ren &lt;= RW0_en &amp;&amp; !RW0_wmode;</span></a>
+<a name="27"><span class="lineNum">      27 </span><span class="lineCov">     510776 :   always @(posedge RW0_clk)</span></a>
+<a name="28"><span class="lineNum">      28 </span><span class="lineCov">      33400 :     if (RW0_en &amp;&amp; !RW0_wmode) reg_RW0_addr &lt;= RW0_addr;</span></a>
+<a name="29"><span class="lineNum">      29 </span><span class="lineCov">     510776 :   always @(posedge RW0_clk)</span></a>
+<a name="30"><span class="lineNum">      30 </span><span class="lineCov">      61228 :     if (RW0_en &amp;&amp; RW0_wmode) begin</span></a>
+<a name="31"><span class="lineNum">      31 </span><span class="lineCov">      30614 :         ram[RW0_addr] &lt;= (RW0_wmask &amp; RW0_wdata) | (~RW0_wmask &amp; ram[RW0_addr]);</span></a>
+<a name="32"><span class="lineNum">      32 </span>            :     end</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE_GARBAGE_ASSIGN</a>
+<a name="34"><span class="lineNum">      34 </span>            :   reg [31:0] RW0_random;</a>
+<a name="35"><span class="lineNum">      35 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="36"><span class="lineNum">      36 </span>            :     initial begin</a>
+<a name="37"><span class="lineNum">      37 </span>            :       #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :       RW0_random = {$random};</a>
+<a name="39"><span class="lineNum">      39 </span>            :       reg_RW0_ren = RW0_random[0];</a>
+<a name="40"><span class="lineNum">      40 </span>            :     end</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif</a>
+<a name="42"><span class="lineNum">      42 </span>            :   always @(posedge RW0_clk) RW0_random &lt;= {$random};</a>
+<a name="43"><span class="lineNum">      43 </span>            :   assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[15:0];</a>
+<a name="44"><span class="lineNum">      44 </span>            :   `else</a>
+<a name="45"><span class="lineNum">      45 </span>            :   assign RW0_rdata = ram[reg_RW0_addr];</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `endif</a>
+<a name="47"><span class="lineNum">      47 </span>            : </a>
+<a name="48"><span class="lineNum">      48 </span>            : endmodule</a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_5.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_5.sv.func-sort-c.html
new file mode 100644
index 0000000..0f20196
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_5.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/array_5.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - array_5.sv<span style="font-size: 80%;"> (<a href="array_5.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">7</td>
+            <td class="headerCovTableEntry">7</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="array_5.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_5.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_5.sv.func.html
new file mode 100644
index 0000000..892b7a3
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_5.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/array_5.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - array_5.sv<span style="font-size: 80%;"> (<a href="array_5.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">7</td>
+            <td class="headerCovTableEntry">7</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="array_5.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_5.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_5.sv.gcov.html
new file mode 100644
index 0000000..917ff2c
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_5.sv.gcov.html
@@ -0,0 +1,154 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/array_5.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - array_5.sv<span style="font-size: 80%;"> (source / <a href="array_5.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">7</td>
+            <td class="headerCovTableEntry">7</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : module array_5(</a>
+<a name="59"><span class="lineNum">      59 </span><span class="lineCov">     612354 :   input  [8:0]  RW0_addr,</span></a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">       1280 :   input         RW0_en,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">     127786 :   input         RW0_clk,</span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">        872 :   input         RW0_wmode,</span></a>
+<a name="63"><span class="lineNum">      63 </span><span class="lineCov">      13928 :   input  [23:0] RW0_wdata,</span></a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">      11006 :   output [23:0] RW0_rdata,</span></a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">       1813 :   input  [1:0]  RW0_wmask</span></a>
+<a name="66"><span class="lineNum">      66 </span>            : );</a>
+<a name="67"><span class="lineNum">      67 </span>            : </a>
+<a name="68"><span class="lineNum">      68 </span>            :   array_5_ext array_5_ext (</a>
+<a name="69"><span class="lineNum">      69 </span>            :     .RW0_addr  (RW0_addr),</a>
+<a name="70"><span class="lineNum">      70 </span>            :     .RW0_en    (RW0_en),</a>
+<a name="71"><span class="lineNum">      71 </span>            :     .RW0_clk   (RW0_clk),</a>
+<a name="72"><span class="lineNum">      72 </span>            :     .RW0_wmode (RW0_wmode),</a>
+<a name="73"><span class="lineNum">      73 </span>            :     .RW0_wdata (RW0_wdata),</a>
+<a name="74"><span class="lineNum">      74 </span>            :     .RW0_rdata (RW0_rdata),</a>
+<a name="75"><span class="lineNum">      75 </span>            :     .RW0_wmask (RW0_wmask)</a>
+<a name="76"><span class="lineNum">      76 </span>            :   );</a>
+<a name="77"><span class="lineNum">      77 </span>            : endmodule</a>
+<a name="78"><span class="lineNum">      78 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_5_ext.v.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_5_ext.v.func-sort-c.html
new file mode 100644
index 0000000..167076a
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_5_ext.v.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/array_5_ext.v - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - array_5_ext.v<span style="font-size: 80%;"> (<a href="array_5_ext.v.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">18</td>
+            <td class="headerCovTableEntry">18</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="array_5_ext.v.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_5_ext.v.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_5_ext.v.func.html
new file mode 100644
index 0000000..0bfca60
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_5_ext.v.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/array_5_ext.v - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - array_5_ext.v<span style="font-size: 80%;"> (<a href="array_5_ext.v.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">18</td>
+            <td class="headerCovTableEntry">18</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="array_5_ext.v.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_5_ext.v.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_5_ext.v.gcov.html
new file mode 100644
index 0000000..24de4ef
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_5_ext.v.gcov.html
@@ -0,0 +1,128 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/array_5_ext.v</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - array_5_ext.v<span style="font-size: 80%;"> (source / <a href="array_5_ext.v.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">18</td>
+            <td class="headerCovTableEntry">18</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : </a>
+<a name="2"><span class="lineNum">       2 </span>            : module array_5_ext(</a>
+<a name="3"><span class="lineNum">       3 </span><span class="lineCov">     127786 :   input RW0_clk,</span></a>
+<a name="4"><span class="lineNum">       4 </span><span class="lineCov">     612354 :   input [8:0] RW0_addr,</span></a>
+<a name="5"><span class="lineNum">       5 </span><span class="lineCov">       1280 :   input RW0_en,</span></a>
+<a name="6"><span class="lineNum">       6 </span><span class="lineCov">        872 :   input RW0_wmode,</span></a>
+<a name="7"><span class="lineNum">       7 </span><span class="lineCov">       1813 :   input [1:0] RW0_wmask,</span></a>
+<a name="8"><span class="lineNum">       8 </span><span class="lineCov">      13928 :   input [23:0] RW0_wdata,</span></a>
+<a name="9"><span class="lineNum">       9 </span><span class="lineCov">      11006 :   output [23:0] RW0_rdata</span></a>
+<a name="10"><span class="lineNum">      10 </span>            : );</a>
+<a name="11"><span class="lineNum">      11 </span>            : </a>
+<a name="12"><span class="lineNum">      12 </span><span class="lineCov">        862 :   reg reg_RW0_ren;</span></a>
+<a name="13"><span class="lineNum">      13 </span><span class="lineCov">      35354 :   reg [8:0] reg_RW0_addr;</span></a>
+<a name="14"><span class="lineNum">      14 </span>            :   reg [23:0] ram [511:0];</a>
+<a name="15"><span class="lineNum">      15 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="16"><span class="lineNum">      16 </span>            :     integer initvar;</a>
+<a name="17"><span class="lineNum">      17 </span>            :     initial begin</a>
+<a name="18"><span class="lineNum">      18 </span>            :       #`RANDOMIZE_DELAY begin end</a>
+<a name="19"><span class="lineNum">      19 </span>            :       for (initvar = 0; initvar &lt; 512; initvar = initvar+1)</a>
+<a name="20"><span class="lineNum">      20 </span>            :         ram[initvar] = {1 {$random}};</a>
+<a name="21"><span class="lineNum">      21 </span>            :       reg_RW0_addr = {1 {$random}};</a>
+<a name="22"><span class="lineNum">      22 </span>            :     end</a>
+<a name="23"><span class="lineNum">      23 </span>            :   `endif</a>
+<a name="24"><span class="lineNum">      24 </span>            :   integer i;</a>
+<a name="25"><span class="lineNum">      25 </span><span class="lineCov">    2043104 :   always @(posedge RW0_clk)</span></a>
+<a name="26"><span class="lineNum">      26 </span><span class="lineCov">    1021552 :     reg_RW0_ren &lt;= RW0_en &amp;&amp; !RW0_wmode;</span></a>
+<a name="27"><span class="lineNum">      27 </span><span class="lineCov">    2043104 :   always @(posedge RW0_clk)</span></a>
+<a name="28"><span class="lineNum">      28 </span><span class="lineCov">      33400 :     if (RW0_en &amp;&amp; !RW0_wmode) reg_RW0_addr &lt;= RW0_addr;</span></a>
+<a name="29"><span class="lineNum">      29 </span><span class="lineCov">    2043104 :   always @(posedge RW0_clk)</span></a>
+<a name="30"><span class="lineNum">      30 </span><span class="lineCov">     482350 :     if (RW0_en &amp;&amp; RW0_wmode) begin</span></a>
+<a name="31"><span class="lineNum">      31 </span><span class="lineCov">     241175 :       for (i=0;i&lt;2;i=i+1) begin</span></a>
+<a name="32"><span class="lineNum">      32 </span><span class="lineCov">         20 :         if (RW0_wmask[i]) begin</span></a>
+<a name="33"><span class="lineNum">      33 </span><span class="lineCov">     482330 :           ram[RW0_addr][i*12 +: 12] &lt;= RW0_wdata[i*12 +: 12];</span></a>
+<a name="34"><span class="lineNum">      34 </span>            :         end</a>
+<a name="35"><span class="lineNum">      35 </span>            :       end</a>
+<a name="36"><span class="lineNum">      36 </span>            :     end</a>
+<a name="37"><span class="lineNum">      37 </span>            :   `ifdef RANDOMIZE_GARBAGE_ASSIGN</a>
+<a name="38"><span class="lineNum">      38 </span>            :   reg [31:0] RW0_random;</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="40"><span class="lineNum">      40 </span>            :     initial begin</a>
+<a name="41"><span class="lineNum">      41 </span>            :       #`RANDOMIZE_DELAY begin end</a>
+<a name="42"><span class="lineNum">      42 </span>            :       RW0_random = {$random};</a>
+<a name="43"><span class="lineNum">      43 </span>            :       reg_RW0_ren = RW0_random[0];</a>
+<a name="44"><span class="lineNum">      44 </span>            :     end</a>
+<a name="45"><span class="lineNum">      45 </span>            :   `endif</a>
+<a name="46"><span class="lineNum">      46 </span>            :   always @(posedge RW0_clk) RW0_random &lt;= {$random};</a>
+<a name="47"><span class="lineNum">      47 </span>            :   assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[23:0];</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `else</a>
+<a name="49"><span class="lineNum">      49 </span>            :   assign RW0_rdata = ram[reg_RW0_addr];</a>
+<a name="50"><span class="lineNum">      50 </span>            :   `endif</a>
+<a name="51"><span class="lineNum">      51 </span>            : </a>
+<a name="52"><span class="lineNum">      52 </span>            : endmodule</a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_6.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_6.sv.func-sort-c.html
new file mode 100644
index 0000000..32f0c77
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_6.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/array_6.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - array_6.sv<span style="font-size: 80%;"> (<a href="array_6.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">9</td>
+            <td class="headerCovTableEntry">9</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="array_6.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_6.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_6.sv.func.html
new file mode 100644
index 0000000..f5aac93
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_6.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/array_6.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - array_6.sv<span style="font-size: 80%;"> (<a href="array_6.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">9</td>
+            <td class="headerCovTableEntry">9</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="array_6.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_6.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_6.sv.gcov.html
new file mode 100644
index 0000000..d488081
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_6.sv.gcov.html
@@ -0,0 +1,158 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/array_6.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - array_6.sv<span style="font-size: 80%;"> (source / <a href="array_6.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">9</td>
+            <td class="headerCovTableEntry">9</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : module array_6(</a>
+<a name="59"><span class="lineNum">      59 </span><span class="lineCov">       8636 :   input  [8:0]  R0_addr,</span></a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">         76 :   input         R0_en,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">     127786 :   input         R0_clk,</span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">        460 :   output [15:0] R0_data,</span></a>
+<a name="63"><span class="lineNum">      63 </span><span class="lineCov">      29781 :   input  [8:0]  W0_addr,</span></a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">         59 :   input         W0_en,</span></a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">     127786 :   input         W0_clk,</span></a>
+<a name="66"><span class="lineNum">      66 </span><span class="lineCov">        575 :   input  [15:0] W0_data,</span></a>
+<a name="67"><span class="lineNum">      67 </span><span class="lineCov">     238101 :   input  [7:0]  W0_mask</span></a>
+<a name="68"><span class="lineNum">      68 </span>            : );</a>
+<a name="69"><span class="lineNum">      69 </span>            : </a>
+<a name="70"><span class="lineNum">      70 </span>            :   array_6_ext array_6_ext (</a>
+<a name="71"><span class="lineNum">      71 </span>            :     .R0_addr (R0_addr),</a>
+<a name="72"><span class="lineNum">      72 </span>            :     .R0_en   (R0_en),</a>
+<a name="73"><span class="lineNum">      73 </span>            :     .R0_clk  (R0_clk),</a>
+<a name="74"><span class="lineNum">      74 </span>            :     .R0_data (R0_data),</a>
+<a name="75"><span class="lineNum">      75 </span>            :     .W0_addr (W0_addr),</a>
+<a name="76"><span class="lineNum">      76 </span>            :     .W0_en   (W0_en),</a>
+<a name="77"><span class="lineNum">      77 </span>            :     .W0_clk  (W0_clk),</a>
+<a name="78"><span class="lineNum">      78 </span>            :     .W0_data (W0_data),</a>
+<a name="79"><span class="lineNum">      79 </span>            :     .W0_mask (W0_mask)</a>
+<a name="80"><span class="lineNum">      80 </span>            :   );</a>
+<a name="81"><span class="lineNum">      81 </span>            : endmodule</a>
+<a name="82"><span class="lineNum">      82 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_6_ext.v.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_6_ext.v.func-sort-c.html
new file mode 100644
index 0000000..e130875
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_6_ext.v.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/array_6_ext.v - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - array_6_ext.v<span style="font-size: 80%;"> (<a href="array_6_ext.v.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">25</td>
+            <td class="headerCovTableEntry">25</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="array_6_ext.v.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_6_ext.v.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_6_ext.v.func.html
new file mode 100644
index 0000000..af762f2
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_6_ext.v.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/array_6_ext.v - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - array_6_ext.v<span style="font-size: 80%;"> (<a href="array_6_ext.v.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">25</td>
+            <td class="headerCovTableEntry">25</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="array_6_ext.v.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_6_ext.v.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_6_ext.v.gcov.html
new file mode 100644
index 0000000..7bef556
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_6_ext.v.gcov.html
@@ -0,0 +1,133 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/array_6_ext.v</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - array_6_ext.v<span style="font-size: 80%;"> (source / <a href="array_6_ext.v.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">25</td>
+            <td class="headerCovTableEntry">25</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : </a>
+<a name="2"><span class="lineNum">       2 </span>            : module array_6_ext(</a>
+<a name="3"><span class="lineNum">       3 </span><span class="lineCov">     127786 :   input W0_clk,</span></a>
+<a name="4"><span class="lineNum">       4 </span><span class="lineCov">      29781 :   input [8:0] W0_addr,</span></a>
+<a name="5"><span class="lineNum">       5 </span><span class="lineCov">         59 :   input W0_en,</span></a>
+<a name="6"><span class="lineNum">       6 </span><span class="lineCov">        575 :   input [15:0] W0_data,</span></a>
+<a name="7"><span class="lineNum">       7 </span><span class="lineCov">     238101 :   input [7:0] W0_mask,</span></a>
+<a name="8"><span class="lineNum">       8 </span><span class="lineCov">     127786 :   input R0_clk,</span></a>
+<a name="9"><span class="lineNum">       9 </span><span class="lineCov">       8636 :   input [8:0] R0_addr,</span></a>
+<a name="10"><span class="lineNum">      10 </span><span class="lineCov">         76 :   input R0_en,</span></a>
+<a name="11"><span class="lineNum">      11 </span><span class="lineCov">        460 :   output [15:0] R0_data</span></a>
+<a name="12"><span class="lineNum">      12 </span>            : );</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span><span class="lineCov">         95 :   reg reg_R0_ren;</span></a>
+<a name="15"><span class="lineNum">      15 </span><span class="lineCov">       8411 :   reg [8:0] reg_R0_addr;</span></a>
+<a name="16"><span class="lineNum">      16 </span>            :   reg [15:0] ram [511:0];</a>
+<a name="17"><span class="lineNum">      17 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="18"><span class="lineNum">      18 </span>            :     integer initvar;</a>
+<a name="19"><span class="lineNum">      19 </span>            :     initial begin</a>
+<a name="20"><span class="lineNum">      20 </span>            :       #`RANDOMIZE_DELAY begin end</a>
+<a name="21"><span class="lineNum">      21 </span>            :       for (initvar = 0; initvar &lt; 512; initvar = initvar+1)</a>
+<a name="22"><span class="lineNum">      22 </span>            :         ram[initvar] = {1 {$random}};</a>
+<a name="23"><span class="lineNum">      23 </span>            :       reg_R0_addr = {1 {$random}};</a>
+<a name="24"><span class="lineNum">      24 </span>            :     end</a>
+<a name="25"><span class="lineNum">      25 </span>            :   `endif</a>
+<a name="26"><span class="lineNum">      26 </span>            :   integer i;</a>
+<a name="27"><span class="lineNum">      27 </span><span class="lineCov">     127694 :   always @(posedge R0_clk)</span></a>
+<a name="28"><span class="lineNum">      28 </span><span class="lineCov">      63847 :     reg_R0_ren &lt;= R0_en;</span></a>
+<a name="29"><span class="lineNum">      29 </span><span class="lineCov">     127694 :   always @(posedge R0_clk)</span></a>
+<a name="30"><span class="lineNum">      30 </span><span class="lineCov">       8350 :     if (R0_en) reg_R0_addr &lt;= R0_addr;</span></a>
+<a name="31"><span class="lineNum">      31 </span><span class="lineCov">     127694 :   always @(posedge W0_clk)</span></a>
+<a name="32"><span class="lineNum">      32 </span><span class="lineCov">       4225 :     if (W0_en) begin</span></a>
+<a name="33"><span class="lineNum">      33 </span><span class="lineCov">      29988 :       if (W0_mask[0]) ram[W0_addr][1:0] &lt;= W0_data[1:0];</span></a>
+<a name="34"><span class="lineNum">      34 </span><span class="lineCov">      29988 :       if (W0_mask[1]) ram[W0_addr][3:2] &lt;= W0_data[3:2];</span></a>
+<a name="35"><span class="lineNum">      35 </span><span class="lineCov">      29750 :       if (W0_mask[2]) ram[W0_addr][5:4] &lt;= W0_data[5:4];</span></a>
+<a name="36"><span class="lineNum">      36 </span><span class="lineCov">      29746 :       if (W0_mask[3]) ram[W0_addr][7:6] &lt;= W0_data[7:6];</span></a>
+<a name="37"><span class="lineNum">      37 </span><span class="lineCov">      29748 :       if (W0_mask[4]) ram[W0_addr][9:8] &lt;= W0_data[9:8];</span></a>
+<a name="38"><span class="lineNum">      38 </span><span class="lineCov">      29748 :       if (W0_mask[5]) ram[W0_addr][11:10] &lt;= W0_data[11:10];</span></a>
+<a name="39"><span class="lineNum">      39 </span><span class="lineCov">      29756 :       if (W0_mask[6]) ram[W0_addr][13:12] &lt;= W0_data[13:12];</span></a>
+<a name="40"><span class="lineNum">      40 </span><span class="lineCov">      29754 :       if (W0_mask[7]) ram[W0_addr][15:14] &lt;= W0_data[15:14];</span></a>
+<a name="41"><span class="lineNum">      41 </span>            :     end</a>
+<a name="42"><span class="lineNum">      42 </span>            :   `ifdef RANDOMIZE_GARBAGE_ASSIGN</a>
+<a name="43"><span class="lineNum">      43 </span>            :   reg [31:0] R0_random;</a>
+<a name="44"><span class="lineNum">      44 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="45"><span class="lineNum">      45 </span>            :     initial begin</a>
+<a name="46"><span class="lineNum">      46 </span>            :       #`RANDOMIZE_DELAY begin end</a>
+<a name="47"><span class="lineNum">      47 </span>            :       R0_random = {$random};</a>
+<a name="48"><span class="lineNum">      48 </span>            :       reg_R0_ren = R0_random[0];</a>
+<a name="49"><span class="lineNum">      49 </span>            :     end</a>
+<a name="50"><span class="lineNum">      50 </span>            :   `endif</a>
+<a name="51"><span class="lineNum">      51 </span>            :   always @(posedge R0_clk) R0_random &lt;= {$random};</a>
+<a name="52"><span class="lineNum">      52 </span>            :   assign R0_data = reg_R0_ren ? ram[reg_R0_addr] : R0_random[15:0];</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `else</a>
+<a name="54"><span class="lineNum">      54 </span>            :   assign R0_data = ram[reg_R0_addr];</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif</a>
+<a name="56"><span class="lineNum">      56 </span>            : </a>
+<a name="57"><span class="lineNum">      57 </span>            : endmodule</a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_7.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_7.sv.func-sort-c.html
new file mode 100644
index 0000000..8c65cd7
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_7.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/array_7.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - array_7.sv<span style="font-size: 80%;"> (<a href="array_7.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">9</td>
+            <td class="headerCovTableEntry">9</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="array_7.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_7.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_7.sv.func.html
new file mode 100644
index 0000000..d514db3
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_7.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/array_7.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - array_7.sv<span style="font-size: 80%;"> (<a href="array_7.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">9</td>
+            <td class="headerCovTableEntry">9</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="array_7.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_7.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_7.sv.gcov.html
new file mode 100644
index 0000000..86dc45f
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_7.sv.gcov.html
@@ -0,0 +1,158 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/array_7.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - array_7.sv<span style="font-size: 80%;"> (source / <a href="array_7.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">9</td>
+            <td class="headerCovTableEntry">9</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : module array_7(</a>
+<a name="59"><span class="lineNum">      59 </span><span class="lineCov">      32986 :   input  [7:0]  R0_addr,</span></a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">         73 :   input         R0_en,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">     127786 :   input         R0_clk,</span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">       2778 :   output [23:0] R0_data,</span></a>
+<a name="63"><span class="lineNum">      63 </span><span class="lineCov">      60329 :   input  [7:0]  W0_addr,</span></a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">        220 :   input         W0_en,</span></a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">     127786 :   input         W0_clk,</span></a>
+<a name="66"><span class="lineNum">      66 </span><span class="lineCov">       3331 :   input  [23:0] W0_data,</span></a>
+<a name="67"><span class="lineNum">      67 </span><span class="lineCov">        870 :   input  [3:0]  W0_mask</span></a>
+<a name="68"><span class="lineNum">      68 </span>            : );</a>
+<a name="69"><span class="lineNum">      69 </span>            : </a>
+<a name="70"><span class="lineNum">      70 </span>            :   array_7_ext array_7_ext (</a>
+<a name="71"><span class="lineNum">      71 </span>            :     .R0_addr (R0_addr),</a>
+<a name="72"><span class="lineNum">      72 </span>            :     .R0_en   (R0_en),</a>
+<a name="73"><span class="lineNum">      73 </span>            :     .R0_clk  (R0_clk),</a>
+<a name="74"><span class="lineNum">      74 </span>            :     .R0_data (R0_data),</a>
+<a name="75"><span class="lineNum">      75 </span>            :     .W0_addr (W0_addr),</a>
+<a name="76"><span class="lineNum">      76 </span>            :     .W0_en   (W0_en),</a>
+<a name="77"><span class="lineNum">      77 </span>            :     .W0_clk  (W0_clk),</a>
+<a name="78"><span class="lineNum">      78 </span>            :     .W0_data (W0_data),</a>
+<a name="79"><span class="lineNum">      79 </span>            :     .W0_mask (W0_mask)</a>
+<a name="80"><span class="lineNum">      80 </span>            :   );</a>
+<a name="81"><span class="lineNum">      81 </span>            : endmodule</a>
+<a name="82"><span class="lineNum">      82 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_7_ext.v.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_7_ext.v.func-sort-c.html
new file mode 100644
index 0000000..135d292
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_7_ext.v.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/array_7_ext.v - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - array_7_ext.v<span style="font-size: 80%;"> (<a href="array_7_ext.v.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">21</td>
+            <td class="headerCovTableEntry">21</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="array_7_ext.v.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_7_ext.v.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_7_ext.v.func.html
new file mode 100644
index 0000000..9864d95
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_7_ext.v.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/array_7_ext.v - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - array_7_ext.v<span style="font-size: 80%;"> (<a href="array_7_ext.v.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">21</td>
+            <td class="headerCovTableEntry">21</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="array_7_ext.v.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_7_ext.v.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_7_ext.v.gcov.html
new file mode 100644
index 0000000..0101245
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_7_ext.v.gcov.html
@@ -0,0 +1,129 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/array_7_ext.v</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - array_7_ext.v<span style="font-size: 80%;"> (source / <a href="array_7_ext.v.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">21</td>
+            <td class="headerCovTableEntry">21</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : </a>
+<a name="2"><span class="lineNum">       2 </span>            : module array_7_ext(</a>
+<a name="3"><span class="lineNum">       3 </span><span class="lineCov">     127786 :   input W0_clk,</span></a>
+<a name="4"><span class="lineNum">       4 </span><span class="lineCov">      60329 :   input [7:0] W0_addr,</span></a>
+<a name="5"><span class="lineNum">       5 </span><span class="lineCov">        220 :   input W0_en,</span></a>
+<a name="6"><span class="lineNum">       6 </span><span class="lineCov">       3331 :   input [23:0] W0_data,</span></a>
+<a name="7"><span class="lineNum">       7 </span><span class="lineCov">        870 :   input [3:0] W0_mask,</span></a>
+<a name="8"><span class="lineNum">       8 </span><span class="lineCov">     127786 :   input R0_clk,</span></a>
+<a name="9"><span class="lineNum">       9 </span><span class="lineCov">      32986 :   input [7:0] R0_addr,</span></a>
+<a name="10"><span class="lineNum">      10 </span><span class="lineCov">         73 :   input R0_en,</span></a>
+<a name="11"><span class="lineNum">      11 </span><span class="lineCov">       2778 :   output [23:0] R0_data</span></a>
+<a name="12"><span class="lineNum">      12 </span>            : );</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span><span class="lineCov">        364 :   reg reg_R0_ren;</span></a>
+<a name="15"><span class="lineNum">      15 </span><span class="lineCov">      31999 :   reg [7:0] reg_R0_addr;</span></a>
+<a name="16"><span class="lineNum">      16 </span>            :   reg [23:0] ram [255:0];</a>
+<a name="17"><span class="lineNum">      17 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="18"><span class="lineNum">      18 </span>            :     integer initvar;</a>
+<a name="19"><span class="lineNum">      19 </span>            :     initial begin</a>
+<a name="20"><span class="lineNum">      20 </span>            :       #`RANDOMIZE_DELAY begin end</a>
+<a name="21"><span class="lineNum">      21 </span>            :       for (initvar = 0; initvar &lt; 256; initvar = initvar+1)</a>
+<a name="22"><span class="lineNum">      22 </span>            :         ram[initvar] = {1 {$random}};</a>
+<a name="23"><span class="lineNum">      23 </span>            :       reg_R0_addr = {1 {$random}};</a>
+<a name="24"><span class="lineNum">      24 </span>            :     end</a>
+<a name="25"><span class="lineNum">      25 </span>            :   `endif</a>
+<a name="26"><span class="lineNum">      26 </span>            :   integer i;</a>
+<a name="27"><span class="lineNum">      27 </span><span class="lineCov">     510776 :   always @(posedge R0_clk)</span></a>
+<a name="28"><span class="lineNum">      28 </span><span class="lineCov">     255388 :     reg_R0_ren &lt;= R0_en;</span></a>
+<a name="29"><span class="lineNum">      29 </span><span class="lineCov">     510776 :   always @(posedge R0_clk)</span></a>
+<a name="30"><span class="lineNum">      30 </span><span class="lineCov">      33400 :     if (R0_en) reg_R0_addr &lt;= R0_addr;</span></a>
+<a name="31"><span class="lineNum">      31 </span><span class="lineCov">     510776 :   always @(posedge W0_clk)</span></a>
+<a name="32"><span class="lineNum">      32 </span><span class="lineCov">      61240 :     if (W0_en) begin</span></a>
+<a name="33"><span class="lineNum">      33 </span><span class="lineCov">         15 :       if (W0_mask[0]) ram[W0_addr][5:0] &lt;= W0_data[5:0];</span></a>
+<a name="34"><span class="lineNum">      34 </span><span class="lineCov">         18 :       if (W0_mask[1]) ram[W0_addr][11:6] &lt;= W0_data[11:6];</span></a>
+<a name="35"><span class="lineNum">      35 </span><span class="lineCov">         18 :       if (W0_mask[2]) ram[W0_addr][17:12] &lt;= W0_data[17:12];</span></a>
+<a name="36"><span class="lineNum">      36 </span><span class="lineCov">         15 :       if (W0_mask[3]) ram[W0_addr][23:18] &lt;= W0_data[23:18];</span></a>
+<a name="37"><span class="lineNum">      37 </span>            :     end</a>
+<a name="38"><span class="lineNum">      38 </span>            :   `ifdef RANDOMIZE_GARBAGE_ASSIGN</a>
+<a name="39"><span class="lineNum">      39 </span>            :   reg [31:0] R0_random;</a>
+<a name="40"><span class="lineNum">      40 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="41"><span class="lineNum">      41 </span>            :     initial begin</a>
+<a name="42"><span class="lineNum">      42 </span>            :       #`RANDOMIZE_DELAY begin end</a>
+<a name="43"><span class="lineNum">      43 </span>            :       R0_random = {$random};</a>
+<a name="44"><span class="lineNum">      44 </span>            :       reg_R0_ren = R0_random[0];</a>
+<a name="45"><span class="lineNum">      45 </span>            :     end</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `endif</a>
+<a name="47"><span class="lineNum">      47 </span>            :   always @(posedge R0_clk) R0_random &lt;= {$random};</a>
+<a name="48"><span class="lineNum">      48 </span>            :   assign R0_data = reg_R0_ren ? ram[reg_R0_addr] : R0_random[23:0];</a>
+<a name="49"><span class="lineNum">      49 </span>            :   `else</a>
+<a name="50"><span class="lineNum">      50 </span>            :   assign R0_data = ram[reg_R0_addr];</a>
+<a name="51"><span class="lineNum">      51 </span>            :   `endif</a>
+<a name="52"><span class="lineNum">      52 </span>            : </a>
+<a name="53"><span class="lineNum">      53 </span>            : endmodule</a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_8.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_8.sv.func-sort-c.html
new file mode 100644
index 0000000..d70befd
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_8.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/array_8.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - array_8.sv<span style="font-size: 80%;"> (<a href="array_8.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">7</td>
+            <td class="headerCovTableEntry">7</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="array_8.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_8.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_8.sv.func.html
new file mode 100644
index 0000000..5e8b619
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_8.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/array_8.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - array_8.sv<span style="font-size: 80%;"> (<a href="array_8.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">7</td>
+            <td class="headerCovTableEntry">7</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="array_8.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_8.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_8.sv.gcov.html
new file mode 100644
index 0000000..adb8d82
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_8.sv.gcov.html
@@ -0,0 +1,154 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/array_8.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - array_8.sv<span style="font-size: 80%;"> (source / <a href="array_8.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">7</td>
+            <td class="headerCovTableEntry">7</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : module array_8(</a>
+<a name="59"><span class="lineNum">      59 </span><span class="lineCov">      94757 :   input  [6:0]   RW0_addr,</span></a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">        639 :   input          RW0_en,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">     127786 :   input          RW0_clk,</span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">        327 :   input          RW0_wmode,</span></a>
+<a name="63"><span class="lineNum">      63 </span><span class="lineCov">      22033 :   input  [105:0] RW0_wdata,</span></a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">      18523 :   output [105:0] RW0_rdata,</span></a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">        399 :   input  [1:0]   RW0_wmask</span></a>
+<a name="66"><span class="lineNum">      66 </span>            : );</a>
+<a name="67"><span class="lineNum">      67 </span>            : </a>
+<a name="68"><span class="lineNum">      68 </span>            :   array_8_ext array_8_ext (</a>
+<a name="69"><span class="lineNum">      69 </span>            :     .RW0_addr  (RW0_addr),</a>
+<a name="70"><span class="lineNum">      70 </span>            :     .RW0_en    (RW0_en),</a>
+<a name="71"><span class="lineNum">      71 </span>            :     .RW0_clk   (RW0_clk),</a>
+<a name="72"><span class="lineNum">      72 </span>            :     .RW0_wmode (RW0_wmode),</a>
+<a name="73"><span class="lineNum">      73 </span>            :     .RW0_wdata (RW0_wdata),</a>
+<a name="74"><span class="lineNum">      74 </span>            :     .RW0_rdata (RW0_rdata),</a>
+<a name="75"><span class="lineNum">      75 </span>            :     .RW0_wmask (RW0_wmask)</a>
+<a name="76"><span class="lineNum">      76 </span>            :   );</a>
+<a name="77"><span class="lineNum">      77 </span>            : endmodule</a>
+<a name="78"><span class="lineNum">      78 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_8_ext.v.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_8_ext.v.func-sort-c.html
new file mode 100644
index 0000000..7ef7e55
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_8_ext.v.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/array_8_ext.v - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - array_8_ext.v<span style="font-size: 80%;"> (<a href="array_8_ext.v.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">18</td>
+            <td class="headerCovTableEntry">18</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="array_8_ext.v.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_8_ext.v.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_8_ext.v.func.html
new file mode 100644
index 0000000..252524a
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_8_ext.v.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/array_8_ext.v - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - array_8_ext.v<span style="font-size: 80%;"> (<a href="array_8_ext.v.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">18</td>
+            <td class="headerCovTableEntry">18</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="array_8_ext.v.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_8_ext.v.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_8_ext.v.gcov.html
new file mode 100644
index 0000000..f85b41f
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/array_8_ext.v.gcov.html
@@ -0,0 +1,128 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/array_8_ext.v</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - array_8_ext.v<span style="font-size: 80%;"> (source / <a href="array_8_ext.v.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">18</td>
+            <td class="headerCovTableEntry">18</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : </a>
+<a name="2"><span class="lineNum">       2 </span>            : module array_8_ext(</a>
+<a name="3"><span class="lineNum">       3 </span><span class="lineCov">     127786 :   input RW0_clk,</span></a>
+<a name="4"><span class="lineNum">       4 </span><span class="lineCov">      94757 :   input [6:0] RW0_addr,</span></a>
+<a name="5"><span class="lineNum">       5 </span><span class="lineCov">        639 :   input RW0_en,</span></a>
+<a name="6"><span class="lineNum">       6 </span><span class="lineCov">        327 :   input RW0_wmode,</span></a>
+<a name="7"><span class="lineNum">       7 </span><span class="lineCov">        399 :   input [1:0] RW0_wmask,</span></a>
+<a name="8"><span class="lineNum">       8 </span><span class="lineCov">      22033 :   input [105:0] RW0_wdata,</span></a>
+<a name="9"><span class="lineNum">       9 </span><span class="lineCov">      18523 :   output [105:0] RW0_rdata</span></a>
+<a name="10"><span class="lineNum">      10 </span>            : );</a>
+<a name="11"><span class="lineNum">      11 </span>            : </a>
+<a name="12"><span class="lineNum">      12 </span><span class="lineCov">        458 :   reg reg_RW0_ren;</span></a>
+<a name="13"><span class="lineNum">      13 </span><span class="lineCov">      24955 :   reg [6:0] reg_RW0_addr;</span></a>
+<a name="14"><span class="lineNum">      14 </span>            :   reg [105:0] ram [127:0];</a>
+<a name="15"><span class="lineNum">      15 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="16"><span class="lineNum">      16 </span>            :     integer initvar;</a>
+<a name="17"><span class="lineNum">      17 </span>            :     initial begin</a>
+<a name="18"><span class="lineNum">      18 </span>            :       #`RANDOMIZE_DELAY begin end</a>
+<a name="19"><span class="lineNum">      19 </span>            :       for (initvar = 0; initvar &lt; 128; initvar = initvar+1)</a>
+<a name="20"><span class="lineNum">      20 </span>            :         ram[initvar] = {4 {$random}};</a>
+<a name="21"><span class="lineNum">      21 </span>            :       reg_RW0_addr = {1 {$random}};</a>
+<a name="22"><span class="lineNum">      22 </span>            :     end</a>
+<a name="23"><span class="lineNum">      23 </span>            :   `endif</a>
+<a name="24"><span class="lineNum">      24 </span>            :   integer i;</a>
+<a name="25"><span class="lineNum">      25 </span><span class="lineCov">     766164 :   always @(posedge RW0_clk)</span></a>
+<a name="26"><span class="lineNum">      26 </span><span class="lineCov">     383082 :     reg_RW0_ren &lt;= RW0_en &amp;&amp; !RW0_wmode;</span></a>
+<a name="27"><span class="lineNum">      27 </span><span class="lineCov">     766164 :   always @(posedge RW0_clk)</span></a>
+<a name="28"><span class="lineNum">      28 </span><span class="lineCov">      25050 :     if (RW0_en &amp;&amp; !RW0_wmode) reg_RW0_addr &lt;= RW0_addr;</span></a>
+<a name="29"><span class="lineNum">      29 </span><span class="lineCov">     766164 :   always @(posedge RW0_clk)</span></a>
+<a name="30"><span class="lineNum">      30 </span><span class="lineCov">      47242 :     if (RW0_en &amp;&amp; RW0_wmode) begin</span></a>
+<a name="31"><span class="lineNum">      31 </span><span class="lineCov">      23621 :       for (i=0;i&lt;2;i=i+1) begin</span></a>
+<a name="32"><span class="lineNum">      32 </span><span class="lineCov">          9 :         if (RW0_wmask[i]) begin</span></a>
+<a name="33"><span class="lineNum">      33 </span><span class="lineCov">      47233 :           ram[RW0_addr][i*53 +: 53] &lt;= RW0_wdata[i*53 +: 53];</span></a>
+<a name="34"><span class="lineNum">      34 </span>            :         end</a>
+<a name="35"><span class="lineNum">      35 </span>            :       end</a>
+<a name="36"><span class="lineNum">      36 </span>            :     end</a>
+<a name="37"><span class="lineNum">      37 </span>            :   `ifdef RANDOMIZE_GARBAGE_ASSIGN</a>
+<a name="38"><span class="lineNum">      38 </span>            :   reg [127:0] RW0_random;</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="40"><span class="lineNum">      40 </span>            :     initial begin</a>
+<a name="41"><span class="lineNum">      41 </span>            :       #`RANDOMIZE_DELAY begin end</a>
+<a name="42"><span class="lineNum">      42 </span>            :       RW0_random = {$random, $random, $random, $random};</a>
+<a name="43"><span class="lineNum">      43 </span>            :       reg_RW0_ren = RW0_random[0];</a>
+<a name="44"><span class="lineNum">      44 </span>            :     end</a>
+<a name="45"><span class="lineNum">      45 </span>            :   `endif</a>
+<a name="46"><span class="lineNum">      46 </span>            :   always @(posedge RW0_clk) RW0_random &lt;= {$random, $random, $random, $random};</a>
+<a name="47"><span class="lineNum">      47 </span>            :   assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[105:0];</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `else</a>
+<a name="49"><span class="lineNum">      49 </span>            :   assign RW0_rdata = ram[reg_RW0_addr];</a>
+<a name="50"><span class="lineNum">      50 </span>            :   `endif</a>
+<a name="51"><span class="lineNum">      51 </span>            : </a>
+<a name="52"><span class="lineNum">      52 </span>            : endmodule</a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/data_16x16.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/data_16x16.sv.func-sort-c.html
new file mode 100644
index 0000000..8d58826
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/data_16x16.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/data_16x16.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - data_16x16.sv<span style="font-size: 80%;"> (<a href="data_16x16.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">19</td>
+            <td class="headerCovTableEntry">19</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="data_16x16.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/data_16x16.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/data_16x16.sv.func.html
new file mode 100644
index 0000000..17a05bc
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/data_16x16.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/data_16x16.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - data_16x16.sv<span style="font-size: 80%;"> (<a href="data_16x16.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">19</td>
+            <td class="headerCovTableEntry">19</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="data_16x16.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/data_16x16.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/data_16x16.sv.gcov.html
new file mode 100644
index 0000000..5f63240
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/data_16x16.sv.gcov.html
@@ -0,0 +1,171 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/data_16x16.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - data_16x16.sv<span style="font-size: 80%;"> (source / <a href="data_16x16.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">19</td>
+            <td class="headerCovTableEntry">19</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : // VCS coverage exclude_file</a>
+<a name="59"><span class="lineNum">      59 </span>            : module data_16x16(</a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">      15694 :   input  [3:0]  R0_addr,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">         19 :   input         R0_en,</span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">     127786 :   input         R0_clk,</span></a>
+<a name="63"><span class="lineNum">      63 </span><span class="lineCov">       5022 :   output [15:0] R0_data,</span></a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">         51 :   input  [3:0]  W0_addr,</span></a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">         69 :   input         W0_en,</span></a>
+<a name="66"><span class="lineNum">      66 </span><span class="lineCov">     127786 :   input         W0_clk,</span></a>
+<a name="67"><span class="lineNum">      67 </span><span class="lineCov">        224 :   input  [15:0] W0_data,</span></a>
+<a name="68"><span class="lineNum">      68 </span><span class="lineCov">       2019 :   input  [3:0]  W1_addr,</span></a>
+<a name="69"><span class="lineNum">      69 </span><span class="lineCov">        113 :   input         W1_en,</span></a>
+<a name="70"><span class="lineNum">      70 </span><span class="lineCov">     127786 :   input         W1_clk,</span></a>
+<a name="71"><span class="lineNum">      71 </span><span class="lineCov">    2044576 :   input  [15:0] W1_data</span></a>
+<a name="72"><span class="lineNum">      72 </span>            : );</a>
+<a name="73"><span class="lineNum">      73 </span>            : </a>
+<a name="74"><span class="lineNum">      74 </span><span class="lineCov">      15235 :   reg [15:0] Memory[0:15];</span></a>
+<a name="75"><span class="lineNum">      75 </span><span class="lineCov">     255388 :   always @(posedge W0_clk) begin</span></a>
+<a name="76"><span class="lineNum">      76 </span><span class="lineCov">      64436 :     if (W0_en &amp; 1'h1)</span></a>
+<a name="77"><span class="lineNum">      77 </span><span class="lineCov">      63258 :       Memory[W0_addr] &lt;= W0_data;</span></a>
+<a name="78"><span class="lineNum">      78 </span><span class="lineCov">       2428 :     if (W1_en &amp; 1'h1)</span></a>
+<a name="79"><span class="lineNum">      79 </span><span class="lineCov">       1214 :       Memory[W1_addr] &lt;= W1_data;</span></a>
+<a name="80"><span class="lineNum">      80 </span>            :   end // always @(posedge)</a>
+<a name="81"><span class="lineNum">      81 </span>            :   `ifdef ENABLE_INITIAL_MEM_</a>
+<a name="82"><span class="lineNum">      82 </span>            :     reg [31:0] _RANDOM_MEM;</a>
+<a name="83"><span class="lineNum">      83 </span><span class="lineCov">        116 :     initial begin</span></a>
+<a name="84"><span class="lineNum">      84 </span>            :       `INIT_RANDOM_PROLOG_</a>
+<a name="85"><span class="lineNum">      85 </span>            :       `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="86"><span class="lineNum">      86 </span>            :         for (logic [4:0] i = 5'h0; i &lt; 5'h10; i += 5'h1) begin</a>
+<a name="87"><span class="lineNum">      87 </span>            :           _RANDOM_MEM = `RANDOM;</a>
+<a name="88"><span class="lineNum">      88 </span>            :           Memory[i[3:0]] = _RANDOM_MEM[15:0];</a>
+<a name="89"><span class="lineNum">      89 </span>            :         end</a>
+<a name="90"><span class="lineNum">      90 </span>            :       `endif // RANDOMIZE_MEM_INIT</a>
+<a name="91"><span class="lineNum">      91 </span>            :     end // initial</a>
+<a name="92"><span class="lineNum">      92 </span>            :   `endif // ENABLE_INITIAL_MEM_</a>
+<a name="93"><span class="lineNum">      93 </span>            :   assign R0_data = R0_en ? Memory[R0_addr] : 16'bx;</a>
+<a name="94"><span class="lineNum">      94 </span>            : endmodule</a>
+<a name="95"><span class="lineNum">      95 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/data_32x16.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/data_32x16.sv.func-sort-c.html
new file mode 100644
index 0000000..e4c3133
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/data_32x16.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/data_32x16.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - data_32x16.sv<span style="font-size: 80%;"> (<a href="data_32x16.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">18</td>
+            <td class="headerCovTableEntry">18</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="data_32x16.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/data_32x16.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/data_32x16.sv.func.html
new file mode 100644
index 0000000..acf4b0d
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/data_32x16.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/data_32x16.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - data_32x16.sv<span style="font-size: 80%;"> (<a href="data_32x16.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">18</td>
+            <td class="headerCovTableEntry">18</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="data_32x16.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/data_32x16.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/data_32x16.sv.gcov.html
new file mode 100644
index 0000000..036c062
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/data_32x16.sv.gcov.html
@@ -0,0 +1,171 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/data_32x16.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - data_32x16.sv<span style="font-size: 80%;"> (source / <a href="data_32x16.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">18</td>
+            <td class="headerCovTableEntry">18</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : // VCS coverage exclude_file</a>
+<a name="59"><span class="lineNum">      59 </span>            : module data_32x16(</a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">      24363 :   input  [4:0]  R0_addr,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">         19 :   input         R0_en,</span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">     127786 :   input         R0_clk,</span></a>
+<a name="63"><span class="lineNum">      63 </span><span class="lineCov">       4003 :   output [15:0] R0_data,</span></a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">         74 :   input  [4:0]  W0_addr,</span></a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">        111 :   input         W0_en,</span></a>
+<a name="66"><span class="lineNum">      66 </span><span class="lineCov">     127786 :   input         W0_clk,</span></a>
+<a name="67"><span class="lineNum">      67 </span><span class="lineCov">        320 :   input  [15:0] W0_data,</span></a>
+<a name="68"><span class="lineNum">      68 </span><span class="lineCov">       5949 :   input  [4:0]  W1_addr,</span></a>
+<a name="69"><span class="lineNum">      69 </span><span class="lineCov">        176 :   input         W1_en,</span></a>
+<a name="70"><span class="lineNum">      70 </span><span class="lineCov">     127786 :   input         W1_clk,</span></a>
+<a name="71"><span class="lineNum">      71 </span><span class="lineCov">    2044576 :   input  [15:0] W1_data</span></a>
+<a name="72"><span class="lineNum">      72 </span>            : );</a>
+<a name="73"><span class="lineNum">      73 </span>            : </a>
+<a name="74"><span class="lineNum">      74 </span>            :   reg [15:0] Memory[0:31];</a>
+<a name="75"><span class="lineNum">      75 </span><span class="lineCov">     383082 :   always @(posedge W0_clk) begin</span></a>
+<a name="76"><span class="lineNum">      76 </span><span class="lineCov">     102839 :     if (W0_en &amp; 1'h1)</span></a>
+<a name="77"><span class="lineNum">      77 </span><span class="lineCov">      88702 :       Memory[W0_addr] &lt;= W0_data;</span></a>
+<a name="78"><span class="lineNum">      78 </span><span class="lineCov">       6508 :     if (W1_en &amp; 1'h1)</span></a>
+<a name="79"><span class="lineNum">      79 </span><span class="lineCov">       3254 :       Memory[W1_addr] &lt;= W1_data;</span></a>
+<a name="80"><span class="lineNum">      80 </span>            :   end // always @(posedge)</a>
+<a name="81"><span class="lineNum">      81 </span>            :   `ifdef ENABLE_INITIAL_MEM_</a>
+<a name="82"><span class="lineNum">      82 </span>            :     reg [31:0] _RANDOM_MEM;</a>
+<a name="83"><span class="lineNum">      83 </span><span class="lineCov">        174 :     initial begin</span></a>
+<a name="84"><span class="lineNum">      84 </span>            :       `INIT_RANDOM_PROLOG_</a>
+<a name="85"><span class="lineNum">      85 </span>            :       `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="86"><span class="lineNum">      86 </span>            :         for (logic [5:0] i = 6'h0; i &lt; 6'h20; i += 6'h1) begin</a>
+<a name="87"><span class="lineNum">      87 </span>            :           _RANDOM_MEM = `RANDOM;</a>
+<a name="88"><span class="lineNum">      88 </span>            :           Memory[i[4:0]] = _RANDOM_MEM[15:0];</a>
+<a name="89"><span class="lineNum">      89 </span>            :         end</a>
+<a name="90"><span class="lineNum">      90 </span>            :       `endif // RANDOMIZE_MEM_INIT</a>
+<a name="91"><span class="lineNum">      91 </span>            :     end // initial</a>
+<a name="92"><span class="lineNum">      92 </span>            :   `endif // ENABLE_INITIAL_MEM_</a>
+<a name="93"><span class="lineNum">      93 </span>            :   assign R0_data = R0_en ? Memory[R0_addr] : 16'bx;</a>
+<a name="94"><span class="lineNum">      94 </span>            : endmodule</a>
+<a name="95"><span class="lineNum">      95 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/data_mem_0_4x2.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/data_mem_0_4x2.sv.func-sort-c.html
new file mode 100644
index 0000000..5ea4576
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/data_mem_0_4x2.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/data_mem_0_4x2.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - data_mem_0_4x2.sv<span style="font-size: 80%;"> (<a href="data_mem_0_4x2.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">13</td>
+            <td class="headerCovTableEntry">13</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="data_mem_0_4x2.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/data_mem_0_4x2.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/data_mem_0_4x2.sv.func.html
new file mode 100644
index 0000000..005f19c
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/data_mem_0_4x2.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/data_mem_0_4x2.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - data_mem_0_4x2.sv<span style="font-size: 80%;"> (<a href="data_mem_0_4x2.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">13</td>
+            <td class="headerCovTableEntry">13</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="data_mem_0_4x2.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/data_mem_0_4x2.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/data_mem_0_4x2.sv.gcov.html
new file mode 100644
index 0000000..82388b9
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/data_mem_0_4x2.sv.gcov.html
@@ -0,0 +1,165 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/data_mem_0_4x2.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - data_mem_0_4x2.sv<span style="font-size: 80%;"> (source / <a href="data_mem_0_4x2.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">13</td>
+            <td class="headerCovTableEntry">13</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : // VCS coverage exclude_file</a>
+<a name="59"><span class="lineNum">      59 </span>            : module data_mem_0_4x2(</a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">        194 :   input  [1:0] R0_addr,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">         38 :   input        R0_en,</span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">     255572 :   input        R0_clk,</span></a>
+<a name="63"><span class="lineNum">      63 </span><span class="lineCov">        238 :   output [1:0] R0_data,</span></a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">        215 :   input  [1:0] W0_addr,</span></a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">         51 :   input        W0_en,</span></a>
+<a name="66"><span class="lineNum">      66 </span><span class="lineCov">     255572 :   input        W0_clk,</span></a>
+<a name="67"><span class="lineNum">      67 </span><span class="lineCov">         69 :   input  [1:0] W0_data</span></a>
+<a name="68"><span class="lineNum">      68 </span>            : );</a>
+<a name="69"><span class="lineNum">      69 </span>            : </a>
+<a name="70"><span class="lineNum">      70 </span><span class="lineCov">        660 :   reg [1:0] Memory[0:3];</span></a>
+<a name="71"><span class="lineNum">      71 </span><span class="lineCov">     638470 :   always @(posedge W0_clk) begin</span></a>
+<a name="72"><span class="lineNum">      72 </span><span class="lineCov">        126 :     if (W0_en &amp; 1'h1)</span></a>
+<a name="73"><span class="lineNum">      73 </span><span class="lineCov">         63 :       Memory[W0_addr] &lt;= W0_data;</span></a>
+<a name="74"><span class="lineNum">      74 </span>            :   end // always @(posedge)</a>
+<a name="75"><span class="lineNum">      75 </span>            :   `ifdef ENABLE_INITIAL_MEM_</a>
+<a name="76"><span class="lineNum">      76 </span>            :     reg [31:0] _RANDOM_MEM;</a>
+<a name="77"><span class="lineNum">      77 </span><span class="lineCov">        290 :     initial begin</span></a>
+<a name="78"><span class="lineNum">      78 </span>            :       `INIT_RANDOM_PROLOG_</a>
+<a name="79"><span class="lineNum">      79 </span>            :       `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="80"><span class="lineNum">      80 </span>            :         for (logic [2:0] i = 3'h0; i &lt; 3'h4; i += 3'h1) begin</a>
+<a name="81"><span class="lineNum">      81 </span>            :           _RANDOM_MEM = `RANDOM;</a>
+<a name="82"><span class="lineNum">      82 </span>            :           Memory[i[1:0]] = _RANDOM_MEM[1:0];</a>
+<a name="83"><span class="lineNum">      83 </span>            :         end</a>
+<a name="84"><span class="lineNum">      84 </span>            :       `endif // RANDOMIZE_MEM_INIT</a>
+<a name="85"><span class="lineNum">      85 </span>            :     end // initial</a>
+<a name="86"><span class="lineNum">      86 </span>            :   `endif // ENABLE_INITIAL_MEM_</a>
+<a name="87"><span class="lineNum">      87 </span>            :   assign R0_data = R0_en ? Memory[R0_addr] : 2'bx;</a>
+<a name="88"><span class="lineNum">      88 </span>            : endmodule</a>
+<a name="89"><span class="lineNum">      89 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/data_mem_0_8x3.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/data_mem_0_8x3.sv.func-sort-c.html
new file mode 100644
index 0000000..c0a14b4
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/data_mem_0_8x3.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/data_mem_0_8x3.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - data_mem_0_8x3.sv<span style="font-size: 80%;"> (<a href="data_mem_0_8x3.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">13</td>
+            <td class="headerCovTableEntry">13</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="data_mem_0_8x3.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/data_mem_0_8x3.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/data_mem_0_8x3.sv.func.html
new file mode 100644
index 0000000..1aead66
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/data_mem_0_8x3.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/data_mem_0_8x3.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - data_mem_0_8x3.sv<span style="font-size: 80%;"> (<a href="data_mem_0_8x3.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">13</td>
+            <td class="headerCovTableEntry">13</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="data_mem_0_8x3.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/data_mem_0_8x3.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/data_mem_0_8x3.sv.gcov.html
new file mode 100644
index 0000000..6490866
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/data_mem_0_8x3.sv.gcov.html
@@ -0,0 +1,165 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/data_mem_0_8x3.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - data_mem_0_8x3.sv<span style="font-size: 80%;"> (source / <a href="data_mem_0_8x3.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">13</td>
+            <td class="headerCovTableEntry">13</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : // VCS coverage exclude_file</a>
+<a name="59"><span class="lineNum">      59 </span>            : module data_mem_0_8x3(</a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">       1583 :   input  [2:0] R0_addr,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">         19 :   input        R0_en,</span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">     127786 :   input        R0_clk,</span></a>
+<a name="63"><span class="lineNum">      63 </span><span class="lineCov">       1716 :   output [2:0] R0_data,</span></a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">       2213 :   input  [2:0] W0_addr,</span></a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">        598 :   input        W0_en,</span></a>
+<a name="66"><span class="lineNum">      66 </span><span class="lineCov">     127786 :   input        W0_clk,</span></a>
+<a name="67"><span class="lineNum">      67 </span><span class="lineCov">       1513 :   input  [2:0] W0_data</span></a>
+<a name="68"><span class="lineNum">      68 </span>            : );</a>
+<a name="69"><span class="lineNum">      69 </span>            : </a>
+<a name="70"><span class="lineNum">      70 </span><span class="lineCov">      11282 :   reg [2:0] Memory[0:7];</span></a>
+<a name="71"><span class="lineNum">      71 </span><span class="lineCov">    4086208 :   always @(posedge W0_clk) begin</span></a>
+<a name="72"><span class="lineNum">      72 </span><span class="lineCov">        276 :     if (W0_en &amp; 1'h1)</span></a>
+<a name="73"><span class="lineNum">      73 </span><span class="lineCov">        138 :       Memory[W0_addr] &lt;= W0_data;</span></a>
+<a name="74"><span class="lineNum">      74 </span>            :   end // always @(posedge)</a>
+<a name="75"><span class="lineNum">      75 </span>            :   `ifdef ENABLE_INITIAL_MEM_</a>
+<a name="76"><span class="lineNum">      76 </span>            :     reg [31:0] _RANDOM_MEM;</a>
+<a name="77"><span class="lineNum">      77 </span><span class="lineCov">       1856 :     initial begin</span></a>
+<a name="78"><span class="lineNum">      78 </span>            :       `INIT_RANDOM_PROLOG_</a>
+<a name="79"><span class="lineNum">      79 </span>            :       `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="80"><span class="lineNum">      80 </span>            :         for (logic [3:0] i = 4'h0; i &lt; 4'h8; i += 4'h1) begin</a>
+<a name="81"><span class="lineNum">      81 </span>            :           _RANDOM_MEM = `RANDOM;</a>
+<a name="82"><span class="lineNum">      82 </span>            :           Memory[i[2:0]] = _RANDOM_MEM[2:0];</a>
+<a name="83"><span class="lineNum">      83 </span>            :         end</a>
+<a name="84"><span class="lineNum">      84 </span>            :       `endif // RANDOMIZE_MEM_INIT</a>
+<a name="85"><span class="lineNum">      85 </span>            :     end // initial</a>
+<a name="86"><span class="lineNum">      86 </span>            :   `endif // ENABLE_INITIAL_MEM_</a>
+<a name="87"><span class="lineNum">      87 </span>            :   assign R0_data = R0_en ? Memory[R0_addr] : 3'bx;</a>
+<a name="88"><span class="lineNum">      88 </span>            : endmodule</a>
+<a name="89"><span class="lineNum">      89 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/data_mem_16x12.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/data_mem_16x12.sv.func-sort-c.html
new file mode 100644
index 0000000..adff9c8
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/data_mem_16x12.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/data_mem_16x12.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - data_mem_16x12.sv<span style="font-size: 80%;"> (<a href="data_mem_16x12.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">20</td>
+            <td class="headerCovTableEntry">20</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="data_mem_16x12.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/data_mem_16x12.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/data_mem_16x12.sv.func.html
new file mode 100644
index 0000000..135b7ef
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/data_mem_16x12.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/data_mem_16x12.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - data_mem_16x12.sv<span style="font-size: 80%;"> (<a href="data_mem_16x12.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">20</td>
+            <td class="headerCovTableEntry">20</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="data_mem_16x12.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/data_mem_16x12.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/data_mem_16x12.sv.gcov.html
new file mode 100644
index 0000000..0588563
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/data_mem_16x12.sv.gcov.html
@@ -0,0 +1,173 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/data_mem_16x12.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - data_mem_16x12.sv<span style="font-size: 80%;"> (source / <a href="data_mem_16x12.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">20</td>
+            <td class="headerCovTableEntry">20</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : // VCS coverage exclude_file</a>
+<a name="59"><span class="lineNum">      59 </span>            : module data_mem_16x12(</a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">        706 :   input  [3:0]  R0_addr,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">         19 :   input         R0_en,</span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">     127786 :   input         R0_clk,</span></a>
+<a name="63"><span class="lineNum">      63 </span><span class="lineCov">       2319 :   output [11:0] R0_data,</span></a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">        706 :   input  [3:0]  R1_addr,</span></a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">         19 :   input         R1_en,</span></a>
+<a name="66"><span class="lineNum">      66 </span><span class="lineCov">     127786 :   input         R1_clk,</span></a>
+<a name="67"><span class="lineNum">      67 </span><span class="lineCov">       2340 :   output [11:0] R1_data,</span></a>
+<a name="68"><span class="lineNum">      68 </span><span class="lineCov">        740 :   input  [3:0]  W0_addr,</span></a>
+<a name="69"><span class="lineNum">      69 </span><span class="lineCov">         29 :   input         W0_en,</span></a>
+<a name="70"><span class="lineNum">      70 </span><span class="lineCov">     127786 :   input         W0_clk,</span></a>
+<a name="71"><span class="lineNum">      71 </span><span class="lineCov">       2016 :   input  [11:0] W0_data,</span></a>
+<a name="72"><span class="lineNum">      72 </span><span class="lineCov">        382 :   input  [1:0]  W0_mask</span></a>
+<a name="73"><span class="lineNum">      73 </span>            : );</a>
+<a name="74"><span class="lineNum">      74 </span>            : </a>
+<a name="75"><span class="lineNum">      75 </span><span class="lineCov">      22524 :   reg [11:0] Memory[0:15];</span></a>
+<a name="76"><span class="lineNum">      76 </span><span class="lineCov">    1021552 :   always @(posedge W0_clk) begin</span></a>
+<a name="77"><span class="lineNum">      77 </span><span class="lineCov">        138 :     if (W0_en &amp; W0_mask[0])</span></a>
+<a name="78"><span class="lineNum">      78 </span><span class="lineCov">         69 :       Memory[W0_addr][32'h0 +: 6] &lt;= W0_data[5:0];</span></a>
+<a name="79"><span class="lineNum">      79 </span><span class="lineCov">        122 :     if (W0_en &amp; W0_mask[1])</span></a>
+<a name="80"><span class="lineNum">      80 </span><span class="lineCov">         61 :       Memory[W0_addr][32'h6 +: 6] &lt;= W0_data[11:6];</span></a>
+<a name="81"><span class="lineNum">      81 </span>            :   end // always @(posedge)</a>
+<a name="82"><span class="lineNum">      82 </span>            :   `ifdef ENABLE_INITIAL_MEM_</a>
+<a name="83"><span class="lineNum">      83 </span>            :     reg [31:0] _RANDOM_MEM;</a>
+<a name="84"><span class="lineNum">      84 </span><span class="lineCov">        464 :     initial begin</span></a>
+<a name="85"><span class="lineNum">      85 </span>            :       `INIT_RANDOM_PROLOG_</a>
+<a name="86"><span class="lineNum">      86 </span>            :       `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="87"><span class="lineNum">      87 </span>            :         for (logic [4:0] i = 5'h0; i &lt; 5'h10; i += 5'h1) begin</a>
+<a name="88"><span class="lineNum">      88 </span>            :           _RANDOM_MEM = `RANDOM;</a>
+<a name="89"><span class="lineNum">      89 </span>            :           Memory[i[3:0]] = _RANDOM_MEM[11:0];</a>
+<a name="90"><span class="lineNum">      90 </span>            :         end</a>
+<a name="91"><span class="lineNum">      91 </span>            :       `endif // RANDOMIZE_MEM_INIT</a>
+<a name="92"><span class="lineNum">      92 </span>            :     end // initial</a>
+<a name="93"><span class="lineNum">      93 </span>            :   `endif // ENABLE_INITIAL_MEM_</a>
+<a name="94"><span class="lineNum">      94 </span>            :   assign R0_data = R0_en ? Memory[R0_addr] : 12'bx;</a>
+<a name="95"><span class="lineNum">      95 </span>            :   assign R1_data = R1_en ? Memory[R1_addr] : 12'bx;</a>
+<a name="96"><span class="lineNum">      96 </span>            : endmodule</a>
+<a name="97"><span class="lineNum">      97 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/data_mem_8x4.sv.func-sort-c.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/data_mem_8x4.sv.func-sort-c.html
new file mode 100644
index 0000000..2cb133c
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/data_mem_8x4.sv.func-sort-c.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/data_mem_8x4.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - data_mem_8x4.sv<span style="font-size: 80%;"> (<a href="data_mem_8x4.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">20</td>
+            <td class="headerCovTableEntry">20</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><a href="data_mem_8x4.sv.func.html"><img src="../updown.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></a></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/data_mem_8x4.sv.func.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/data_mem_8x4.sv.func.html
new file mode 100644
index 0000000..7349626
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/data_mem_8x4.sv.func.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/data_mem_8x4.sv - functions</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - data_mem_8x4.sv<span style="font-size: 80%;"> (<a href="data_mem_8x4.sv.gcov.html">source</a> / functions)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">20</td>
+            <td class="headerCovTableEntry">20</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="60%" cellpadding=1 cellspacing=1 border=0>
+    <tr><td><br></td></tr>
+    <tr>
+      <td width="80%" class="tableHead">Function Name <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function name" title="Sort by function name" border=0></span></td>
+      <td width="20%" class="tableHead">Hit count <span class="tableHeadSort"><a href="data_mem_8x4.sv.func-sort-c.html"><img src="../updown.png" width=10 height=14 alt="Sort by hit count" title="Sort by hit count" border=0></a></span></td>
+    </tr>
+  </table>
+  <br>
+  </center>
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/data_mem_8x4.sv.gcov.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/data_mem_8x4.sv.gcov.html
new file mode 100644
index 0000000..b995e1a
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/data_mem_8x4.sv.gcov.html
@@ -0,0 +1,173 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop/data_mem_8x4.sv</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - <a href="index.html">BPUTop</a> - data_mem_8x4.sv<span style="font-size: 80%;"> (source / <a href="data_mem_8x4.sv.func-sort-c.html">functions</a>)</span></td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">20</td>
+            <td class="headerCovTableEntry">20</td>
+            <td class="headerCovTableEntryHi">100.0 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <table cellpadding=0 cellspacing=0 border=0>
+    <tr>
+      <td><br></td>
+    </tr>
+    <tr>
+      <td>
+<pre class="sourceHeading">          Line data    Source code</pre>
+<pre class="source">
+<a name="1"><span class="lineNum">       1 </span>            : // Generated by CIRCT firtool-1.62.0</a>
+<a name="2"><span class="lineNum">       2 </span>            : // Standard header to adapt well known macros for register randomization.</a>
+<a name="3"><span class="lineNum">       3 </span>            : `ifndef RANDOMIZE</a>
+<a name="4"><span class="lineNum">       4 </span>            :   `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="5"><span class="lineNum">       5 </span>            :     `define RANDOMIZE</a>
+<a name="6"><span class="lineNum">       6 </span>            :   `endif // RANDOMIZE_MEM_INIT</a>
+<a name="7"><span class="lineNum">       7 </span>            : `endif // not def RANDOMIZE</a>
+<a name="8"><span class="lineNum">       8 </span>            : `ifndef RANDOMIZE</a>
+<a name="9"><span class="lineNum">       9 </span>            :   `ifdef RANDOMIZE_REG_INIT</a>
+<a name="10"><span class="lineNum">      10 </span>            :     `define RANDOMIZE</a>
+<a name="11"><span class="lineNum">      11 </span>            :   `endif // RANDOMIZE_REG_INIT</a>
+<a name="12"><span class="lineNum">      12 </span>            : `endif // not def RANDOMIZE</a>
+<a name="13"><span class="lineNum">      13 </span>            : </a>
+<a name="14"><span class="lineNum">      14 </span>            : // RANDOM may be set to an expression that produces a 32-bit random unsigned value.</a>
+<a name="15"><span class="lineNum">      15 </span>            : `ifndef RANDOM</a>
+<a name="16"><span class="lineNum">      16 </span>            :   `define RANDOM $random</a>
+<a name="17"><span class="lineNum">      17 </span>            : `endif // not def RANDOM</a>
+<a name="18"><span class="lineNum">      18 </span>            : </a>
+<a name="19"><span class="lineNum">      19 </span>            : // Users can define INIT_RANDOM as general code that gets injected into the</a>
+<a name="20"><span class="lineNum">      20 </span>            : // initializer block for modules with registers.</a>
+<a name="21"><span class="lineNum">      21 </span>            : `ifndef INIT_RANDOM</a>
+<a name="22"><span class="lineNum">      22 </span>            :   `define INIT_RANDOM</a>
+<a name="23"><span class="lineNum">      23 </span>            : `endif // not def INIT_RANDOM</a>
+<a name="24"><span class="lineNum">      24 </span>            : </a>
+<a name="25"><span class="lineNum">      25 </span>            : // If using random initialization, you can also define RANDOMIZE_DELAY to</a>
+<a name="26"><span class="lineNum">      26 </span>            : // customize the delay used, otherwise 0.002 is used.</a>
+<a name="27"><span class="lineNum">      27 </span>            : `ifndef RANDOMIZE_DELAY</a>
+<a name="28"><span class="lineNum">      28 </span>            :   `define RANDOMIZE_DELAY 0.002</a>
+<a name="29"><span class="lineNum">      29 </span>            : `endif // not def RANDOMIZE_DELAY</a>
+<a name="30"><span class="lineNum">      30 </span>            : </a>
+<a name="31"><span class="lineNum">      31 </span>            : // Define INIT_RANDOM_PROLOG_ for use in our modules below.</a>
+<a name="32"><span class="lineNum">      32 </span>            : `ifndef INIT_RANDOM_PROLOG_</a>
+<a name="33"><span class="lineNum">      33 </span>            :   `ifdef RANDOMIZE</a>
+<a name="34"><span class="lineNum">      34 </span>            :     `ifdef VERILATOR</a>
+<a name="35"><span class="lineNum">      35 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM</a>
+<a name="36"><span class="lineNum">      36 </span>            :     `else  // VERILATOR</a>
+<a name="37"><span class="lineNum">      37 </span>            :       `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end</a>
+<a name="38"><span class="lineNum">      38 </span>            :     `endif // VERILATOR</a>
+<a name="39"><span class="lineNum">      39 </span>            :   `else  // RANDOMIZE</a>
+<a name="40"><span class="lineNum">      40 </span>            :     `define INIT_RANDOM_PROLOG_</a>
+<a name="41"><span class="lineNum">      41 </span>            :   `endif // RANDOMIZE</a>
+<a name="42"><span class="lineNum">      42 </span>            : `endif // not def INIT_RANDOM_PROLOG_</a>
+<a name="43"><span class="lineNum">      43 </span>            : </a>
+<a name="44"><span class="lineNum">      44 </span>            : // Include register initializers in init blocks unless synthesis is set</a>
+<a name="45"><span class="lineNum">      45 </span>            : `ifndef SYNTHESIS</a>
+<a name="46"><span class="lineNum">      46 </span>            :   `ifndef ENABLE_INITIAL_REG_</a>
+<a name="47"><span class="lineNum">      47 </span>            :     `define ENABLE_INITIAL_REG_</a>
+<a name="48"><span class="lineNum">      48 </span>            :   `endif // not def ENABLE_INITIAL_REG_</a>
+<a name="49"><span class="lineNum">      49 </span>            : `endif // not def SYNTHESIS</a>
+<a name="50"><span class="lineNum">      50 </span>            : </a>
+<a name="51"><span class="lineNum">      51 </span>            : // Include rmemory initializers in init blocks unless synthesis is set</a>
+<a name="52"><span class="lineNum">      52 </span>            : `ifndef SYNTHESIS</a>
+<a name="53"><span class="lineNum">      53 </span>            :   `ifndef ENABLE_INITIAL_MEM_</a>
+<a name="54"><span class="lineNum">      54 </span>            :     `define ENABLE_INITIAL_MEM_</a>
+<a name="55"><span class="lineNum">      55 </span>            :   `endif // not def ENABLE_INITIAL_MEM_</a>
+<a name="56"><span class="lineNum">      56 </span>            : `endif // not def SYNTHESIS</a>
+<a name="57"><span class="lineNum">      57 </span>            : </a>
+<a name="58"><span class="lineNum">      58 </span>            : // VCS coverage exclude_file</a>
+<a name="59"><span class="lineNum">      59 </span>            : module data_mem_8x4(</a>
+<a name="60"><span class="lineNum">      60 </span><span class="lineCov">         68 :   input  [2:0] R0_addr,</span></a>
+<a name="61"><span class="lineNum">      61 </span><span class="lineCov">         19 :   input        R0_en,</span></a>
+<a name="62"><span class="lineNum">      62 </span><span class="lineCov">     127786 :   input        R0_clk,</span></a>
+<a name="63"><span class="lineNum">      63 </span><span class="lineCov">        111 :   output [3:0] R0_data,</span></a>
+<a name="64"><span class="lineNum">      64 </span><span class="lineCov">         68 :   input  [2:0] R1_addr,</span></a>
+<a name="65"><span class="lineNum">      65 </span><span class="lineCov">         19 :   input        R1_en,</span></a>
+<a name="66"><span class="lineNum">      66 </span><span class="lineCov">     127786 :   input        R1_clk,</span></a>
+<a name="67"><span class="lineNum">      67 </span><span class="lineCov">        112 :   output [3:0] R1_data,</span></a>
+<a name="68"><span class="lineNum">      68 </span><span class="lineCov">         73 :   input  [2:0] W0_addr,</span></a>
+<a name="69"><span class="lineNum">      69 </span><span class="lineCov">         35 :   input        W0_en,</span></a>
+<a name="70"><span class="lineNum">      70 </span><span class="lineCov">     127786 :   input        W0_clk,</span></a>
+<a name="71"><span class="lineNum">      71 </span><span class="lineCov">         76 :   input  [3:0] W0_data,</span></a>
+<a name="72"><span class="lineNum">      72 </span><span class="lineCov">         65 :   input  [1:0] W0_mask</span></a>
+<a name="73"><span class="lineNum">      73 </span>            : );</a>
+<a name="74"><span class="lineNum">      74 </span>            : </a>
+<a name="75"><span class="lineNum">      75 </span><span class="lineCov">        509 :   reg [3:0] Memory[0:7];</span></a>
+<a name="76"><span class="lineNum">      76 </span><span class="lineCov">     127694 :   always @(posedge W0_clk) begin</span></a>
+<a name="77"><span class="lineNum">      77 </span><span class="lineCov">         32 :     if (W0_en &amp; W0_mask[0])</span></a>
+<a name="78"><span class="lineNum">      78 </span><span class="lineCov">         16 :       Memory[W0_addr][32'h0 +: 2] &lt;= W0_data[1:0];</span></a>
+<a name="79"><span class="lineNum">      79 </span><span class="lineCov">         30 :     if (W0_en &amp; W0_mask[1])</span></a>
+<a name="80"><span class="lineNum">      80 </span><span class="lineCov">         15 :       Memory[W0_addr][32'h2 +: 2] &lt;= W0_data[3:2];</span></a>
+<a name="81"><span class="lineNum">      81 </span>            :   end // always @(posedge)</a>
+<a name="82"><span class="lineNum">      82 </span>            :   `ifdef ENABLE_INITIAL_MEM_</a>
+<a name="83"><span class="lineNum">      83 </span>            :     reg [31:0] _RANDOM_MEM;</a>
+<a name="84"><span class="lineNum">      84 </span><span class="lineCov">         58 :     initial begin</span></a>
+<a name="85"><span class="lineNum">      85 </span>            :       `INIT_RANDOM_PROLOG_</a>
+<a name="86"><span class="lineNum">      86 </span>            :       `ifdef RANDOMIZE_MEM_INIT</a>
+<a name="87"><span class="lineNum">      87 </span>            :         for (logic [3:0] i = 4'h0; i &lt; 4'h8; i += 4'h1) begin</a>
+<a name="88"><span class="lineNum">      88 </span>            :           _RANDOM_MEM = `RANDOM;</a>
+<a name="89"><span class="lineNum">      89 </span>            :           Memory[i[2:0]] = _RANDOM_MEM[3:0];</a>
+<a name="90"><span class="lineNum">      90 </span>            :         end</a>
+<a name="91"><span class="lineNum">      91 </span>            :       `endif // RANDOMIZE_MEM_INIT</a>
+<a name="92"><span class="lineNum">      92 </span>            :     end // initial</a>
+<a name="93"><span class="lineNum">      93 </span>            :   `endif // ENABLE_INITIAL_MEM_</a>
+<a name="94"><span class="lineNum">      94 </span>            :   assign R0_data = R0_en ? Memory[R0_addr] : 4'bx;</a>
+<a name="95"><span class="lineNum">      95 </span>            :   assign R1_data = R1_en ? Memory[R1_addr] : 4'bx;</a>
+<a name="96"><span class="lineNum">      96 </span>            : endmodule</a>
+<a name="97"><span class="lineNum">      97 </span>            : </a>
+</pre>
+      </td>
+    </tr>
+  </table>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php" target="_parent">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/index-sort-f.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/index-sort-f.html
new file mode 100644
index 0000000..28405d7
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/index-sort-f.html
@@ -0,0 +1,863 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - BPUTop</td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">10047</td>
+            <td class="headerCovTableEntry">15626</td>
+            <td class="headerCovTableEntryLo">64.3 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="80%" cellpadding=1 cellspacing=1 border=0>
+
+    <tr>
+      <td width="50%"><br></td>
+      <td width="10%"></td>
+      <td width="10%"></td>
+      <td width="10%"></td>
+      <td width="10%"></td>
+      <td width="10%"></td>
+    </tr>
+
+    <tr>
+      <td class="tableHead">Filename <span class="tableHeadSort"><a href="index.html"><img src="../updown.png" width=10 height=14 alt="Sort by name" title="Sort by name" border=0></a></span></td>
+      <td class="tableHead" colspan=3>Line Coverage <span class="tableHeadSort"><a href="index-sort-l.html"><img src="../updown.png" width=10 height=14 alt="Sort by line coverage" title="Sort by line coverage" border=0></a></span></td>
+      <td class="tableHead" colspan=2>Functions <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by function coverage" title="Sort by function coverage" border=0></span></td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="SRAMTemplate_13.sv.gcov.html">SRAMTemplate_13.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">183 / 183</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="DelayN_2.sv.gcov.html">DelayN_2.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">15 / 15</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="PriorityMuxModule_4.sv.gcov.html">PriorityMuxModule_4.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">112 / 112</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="SRAMTemplate_14.sv.gcov.html">SRAMTemplate_14.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">95 / 95</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="PriorityMuxModule_8.sv.gcov.html">PriorityMuxModule_8.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">16 / 16</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="SRAMTemplate_34.sv.gcov.html">SRAMTemplate_34.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../amber.png" width=86 height=10 alt="85.6%"><img src="../snow.png" width=14 height=10 alt="85.6%"></td></tr></table>
+      </td>
+      <td class="coverPerMed">85.6&nbsp;%</td>
+      <td class="coverNumMed">77 / 90</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="SCTable_2.sv.gcov.html">SCTable_2.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">37 / 37</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="FauFTBWay.sv.gcov.html">FauFTBWay.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">72 / 72</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="ITTageTable_2.sv.gcov.html">ITTageTable_2.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">44 / 44</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="PriorityMuxModule_16.sv.gcov.html">PriorityMuxModule_16.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">10 / 10</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="ITTage.sv.gcov.html">ITTage.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../amber.png" width=86 height=10 alt="85.6%"><img src="../snow.png" width=14 height=10 alt="85.6%"></td></tr></table>
+      </td>
+      <td class="coverPerMed">85.6&nbsp;%</td>
+      <td class="coverNumMed">495 / 578</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="WrBypass.sv.gcov.html">WrBypass.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=93 height=10 alt="92.7%"><img src="../snow.png" width=7 height=10 alt="92.7%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">92.7&nbsp;%</td>
+      <td class="coverNumHi">114 / 123</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="CAMTemplate.sv.gcov.html">CAMTemplate.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">39 / 39</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="ITTageTable.sv.gcov.html">ITTageTable.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">44 / 44</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="array_0_0.sv.gcov.html">array_0_0.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
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+    </tr>
+    <tr>
+      <td class="coverFile"><a href="ITTageTable_3.sv.gcov.html">ITTageTable_3.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
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+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">44 / 44</td>
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+    <tr>
+      <td class="coverFile"><a href="CAMTemplate_41.sv.gcov.html">CAMTemplate_41.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
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+    <tr>
+      <td class="coverFile"><a href="DelayN_1.sv.gcov.html">DelayN_1.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
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+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">23 / 23</td>
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+    </tr>
+    <tr>
+      <td class="coverFile"><a href="data_16x16.sv.gcov.html">data_16x16.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
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+      <td class="coverNumHi">19 / 19</td>
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+    <tr>
+      <td class="coverFile"><a href="ITTageTable_1.sv.gcov.html">ITTageTable_1.sv</a></td>
+      <td class="coverBar" align="center">
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+    <tr>
+      <td class="coverFile"><a href="array_4.sv.gcov.html">array_4.sv</a></td>
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+    <tr>
+      <td class="coverFile"><a href="ITTageTable_4.sv.gcov.html">ITTageTable_4.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
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+      <td class="coverNumHi">44 / 44</td>
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+    <tr>
+      <td class="coverFile"><a href="CAMTemplate_33.sv.gcov.html">CAMTemplate_33.sv</a></td>
+      <td class="coverBar" align="center">
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+      <td class="coverNumHi">71 / 71</td>
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+    <tr>
+      <td class="coverFile"><a href="RASStack.sv.gcov.html">RASStack.sv</a></td>
+      <td class="coverBar" align="center">
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+    </tr>
+    <tr>
+      <td class="coverFile"><a href="CAMTemplate_43.sv.gcov.html">CAMTemplate_43.sv</a></td>
+      <td class="coverBar" align="center">
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+    <tr>
+      <td class="coverFile"><a href="array_7.sv.gcov.html">array_7.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
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+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">9 / 9</td>
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+    <tr>
+      <td class="coverFile"><a href="PriorityMuxModule.sv.gcov.html">PriorityMuxModule.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
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+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">10 / 10</td>
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+    <tr>
+      <td class="coverFile"><a href="array_3_ext.v.gcov.html">array_3_ext.v</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
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+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">16 / 16</td>
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+      <td class="coverFile"><a href="data_mem_0_4x2.sv.gcov.html">data_mem_0_4x2.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
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+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">13 / 13</td>
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+    </tr>
+    <tr>
+      <td class="coverFile"><a href="PriorityMuxModule_20.sv.gcov.html">PriorityMuxModule_20.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
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+    </tr>
+    <tr>
+      <td class="coverFile"><a href="array_3.sv.gcov.html">array_3.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
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+    <tr>
+      <td class="coverFile"><a href="FoldedSRAMTemplate_20.sv.gcov.html">FoldedSRAMTemplate_20.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
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+      <td class="coverPerHi">100.0&nbsp;%</td>
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+    </tr>
+    <tr>
+      <td class="coverFile"><a href="FoldedSRAMTemplate_25.sv.gcov.html">FoldedSRAMTemplate_25.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
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+    </tr>
+    <tr>
+      <td class="coverFile"><a href="array_7_ext.v.gcov.html">array_7_ext.v</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
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+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">21 / 21</td>
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+    </tr>
+    <tr>
+      <td class="coverFile"><a href="data_32x16.sv.gcov.html">data_32x16.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
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+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">18 / 18</td>
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+    </tr>
+    <tr>
+      <td class="coverFile"><a href="array_4_ext.v.gcov.html">array_4_ext.v</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
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+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">16 / 16</td>
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+    </tr>
+    <tr>
+      <td class="coverFile"><a href="SRAMTemplate_43.sv.gcov.html">SRAMTemplate_43.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">47 / 47</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="TageBTable.sv.gcov.html">TageBTable.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
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+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">35 / 35</td>
+      <td class="coverPerHi">-</td>
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+    </tr>
+    <tr>
+      <td class="coverFile"><a href="DelayN_4.sv.gcov.html">DelayN_4.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
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+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">9 / 9</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="TageTable.sv.gcov.html">TageTable.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
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+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">102 / 102</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="SCTable_3.sv.gcov.html">SCTable_3.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
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+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">37 / 37</td>
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+    </tr>
+    <tr>
+      <td class="coverFile"><a href="SRAMTemplate_39.sv.gcov.html">SRAMTemplate_39.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
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+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">37 / 37</td>
+      <td class="coverPerHi">-</td>
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+    </tr>
+    <tr>
+      <td class="coverFile"><a href="WrBypass_32.sv.gcov.html">WrBypass_32.sv</a></td>
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+      <td class="coverPerMed">89.9&nbsp;%</td>
+      <td class="coverNumMed">152 / 169</td>
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+    <tr>
+      <td class="coverFile"><a href="CAMTemplate_32.sv.gcov.html">CAMTemplate_32.sv</a></td>
+      <td class="coverBar" align="center">
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+      <td class="coverNumMed">33 / 39</td>
+      <td class="coverPerHi">-</td>
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+    </tr>
+    <tr>
+      <td class="coverFile"><a href="SCTable_1.sv.gcov.html">SCTable_1.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
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+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">37 / 37</td>
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+    </tr>
+    <tr>
+      <td class="coverFile"><a href="RAS.sv.gcov.html">RAS.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
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+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">401 / 401</td>
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+    <tr>
+      <td class="coverFile"><a href="DelayNWithValid.sv.gcov.html">DelayNWithValid.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
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+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="WrBypass_33.sv.gcov.html">WrBypass_33.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
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+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">313 / 313</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="array_0_0_ext.v.gcov.html">array_0_0_ext.v</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
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+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">16 / 16</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="Folded1WDataModuleTemplate.sv.gcov.html">Folded1WDataModuleTemplate.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">27 / 27</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="SCTable.sv.gcov.html">SCTable.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">34 / 34</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="FTBBank.sv.gcov.html">FTBBank.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../ruby.png" width=44 height=10 alt="43.8%"><img src="../snow.png" width=56 height=10 alt="43.8%"></td></tr></table>
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+      <td class="coverPerLo">43.8&nbsp;%</td>
+      <td class="coverNumLo">1935 / 4420</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="Composer.sv.gcov.html">Composer.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">320 / 320</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="array_5_ext.v.gcov.html">array_5_ext.v</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">18 / 18</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="FauFTB.sv.gcov.html">FauFTB.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../ruby.png" width=61 height=10 alt="61.2%"><img src="../snow.png" width=39 height=10 alt="61.2%"></td></tr></table>
+      </td>
+      <td class="coverPerLo">61.2&nbsp;%</td>
+      <td class="coverNumLo">648 / 1058</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="data_mem_16x12.sv.gcov.html">data_mem_16x12.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">20 / 20</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="array_6.sv.gcov.html">array_6.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">9 / 9</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="PriorityMuxModule_12.sv.gcov.html">PriorityMuxModule_12.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">148 / 148</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="SRAMTemplate_35.sv.gcov.html">SRAMTemplate_35.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../amber.png" width=87 height=10 alt="87.0%"><img src="../snow.png" width=13 height=10 alt="87.0%"></td></tr></table>
+      </td>
+      <td class="coverPerMed">87.0&nbsp;%</td>
+      <td class="coverNumMed">60 / 69</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="SRAMTemplate_15.sv.gcov.html">SRAMTemplate_15.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">44 / 44</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="FoldedSRAMTemplate_1.sv.gcov.html">FoldedSRAMTemplate_1.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">18 / 18</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="WrBypass_41.sv.gcov.html">WrBypass_41.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">43 / 43</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="WrBypass_43.sv.gcov.html">WrBypass_43.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">43 / 43</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="TageTable_3.sv.gcov.html">TageTable_3.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">107 / 107</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="TageTable_1.sv.gcov.html">TageTable_1.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">107 / 107</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="data_mem_0_8x3.sv.gcov.html">data_mem_0_8x3.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">13 / 13</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="array_8_ext.v.gcov.html">array_8_ext.v</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">18 / 18</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="TageTable_2.sv.gcov.html">TageTable_2.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">107 / 107</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="FTB.sv.gcov.html">FTB.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">703 / 703</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="Folded1WDataModuleTemplate_2.sv.gcov.html">Folded1WDataModuleTemplate_2.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">27 / 27</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="array_8.sv.gcov.html">array_8.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">7 / 7</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="FoldedSRAMTemplate_21.sv.gcov.html">FoldedSRAMTemplate_21.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">13 / 13</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="Tage_SC.sv.gcov.html">Tage_SC.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../ruby.png" width=41 height=10 alt="41.2%"><img src="../snow.png" width=59 height=10 alt="41.2%"></td></tr></table>
+      </td>
+      <td class="coverPerLo">41.2&nbsp;%</td>
+      <td class="coverNumLo">1491 / 3621</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="array_5.sv.gcov.html">array_5.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">7 / 7</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="FoldedSRAMTemplate.sv.gcov.html">FoldedSRAMTemplate.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">40 / 40</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="DelayNWithValid_1.sv.gcov.html">DelayNWithValid_1.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">128 / 128</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="array_6_ext.v.gcov.html">array_6_ext.v</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">25 / 25</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+  </table>
+  </center>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/index-sort-l.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/index-sort-l.html
new file mode 100644
index 0000000..21b78e5
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/index-sort-l.html
@@ -0,0 +1,863 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - BPUTop</td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">10047</td>
+            <td class="headerCovTableEntry">15626</td>
+            <td class="headerCovTableEntryLo">64.3 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="80%" cellpadding=1 cellspacing=1 border=0>
+
+    <tr>
+      <td width="50%"><br></td>
+      <td width="10%"></td>
+      <td width="10%"></td>
+      <td width="10%"></td>
+      <td width="10%"></td>
+      <td width="10%"></td>
+    </tr>
+
+    <tr>
+      <td class="tableHead">Filename <span class="tableHeadSort"><a href="index.html"><img src="../updown.png" width=10 height=14 alt="Sort by name" title="Sort by name" border=0></a></span></td>
+      <td class="tableHead" colspan=3>Line Coverage <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by line coverage" title="Sort by line coverage" border=0></span></td>
+      <td class="tableHead" colspan=2>Functions <span class="tableHeadSort"><a href="index-sort-f.html"><img src="../updown.png" width=10 height=14 alt="Sort by function coverage" title="Sort by function coverage" border=0></a></span></td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="Tage_SC.sv.gcov.html">Tage_SC.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../ruby.png" width=41 height=10 alt="41.2%"><img src="../snow.png" width=59 height=10 alt="41.2%"></td></tr></table>
+      </td>
+      <td class="coverPerLo">41.2&nbsp;%</td>
+      <td class="coverNumLo">1491 / 3621</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="FTBBank.sv.gcov.html">FTBBank.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../ruby.png" width=44 height=10 alt="43.8%"><img src="../snow.png" width=56 height=10 alt="43.8%"></td></tr></table>
+      </td>
+      <td class="coverPerLo">43.8&nbsp;%</td>
+      <td class="coverNumLo">1935 / 4420</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="FauFTB.sv.gcov.html">FauFTB.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../ruby.png" width=61 height=10 alt="61.2%"><img src="../snow.png" width=39 height=10 alt="61.2%"></td></tr></table>
+      </td>
+      <td class="coverPerLo">61.2&nbsp;%</td>
+      <td class="coverNumLo">648 / 1058</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="RASStack.sv.gcov.html">RASStack.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../ruby.png" width=66 height=10 alt="65.6%"><img src="../snow.png" width=34 height=10 alt="65.6%"></td></tr></table>
+      </td>
+      <td class="coverPerLo">65.6&nbsp;%</td>
+      <td class="coverNumLo">790 / 1205</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="CAMTemplate_32.sv.gcov.html">CAMTemplate_32.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../amber.png" width=85 height=10 alt="84.6%"><img src="../snow.png" width=15 height=10 alt="84.6%"></td></tr></table>
+      </td>
+      <td class="coverPerMed">84.6&nbsp;%</td>
+      <td class="coverNumMed">33 / 39</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="SRAMTemplate_34.sv.gcov.html">SRAMTemplate_34.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../amber.png" width=86 height=10 alt="85.6%"><img src="../snow.png" width=14 height=10 alt="85.6%"></td></tr></table>
+      </td>
+      <td class="coverPerMed">85.6&nbsp;%</td>
+      <td class="coverNumMed">77 / 90</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="ITTage.sv.gcov.html">ITTage.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../amber.png" width=86 height=10 alt="85.6%"><img src="../snow.png" width=14 height=10 alt="85.6%"></td></tr></table>
+      </td>
+      <td class="coverPerMed">85.6&nbsp;%</td>
+      <td class="coverNumMed">495 / 578</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="SRAMTemplate_35.sv.gcov.html">SRAMTemplate_35.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../amber.png" width=87 height=10 alt="87.0%"><img src="../snow.png" width=13 height=10 alt="87.0%"></td></tr></table>
+      </td>
+      <td class="coverPerMed">87.0&nbsp;%</td>
+      <td class="coverNumMed">60 / 69</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="WrBypass_32.sv.gcov.html">WrBypass_32.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../amber.png" width=90 height=10 alt="89.9%"><img src="../snow.png" width=10 height=10 alt="89.9%"></td></tr></table>
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+      <td class="coverPerMed">89.9&nbsp;%</td>
+      <td class="coverNumMed">152 / 169</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="CAMTemplate_43.sv.gcov.html">CAMTemplate_43.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=91 height=10 alt="91.3%"><img src="../snow.png" width=9 height=10 alt="91.3%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">91.3&nbsp;%</td>
+      <td class="coverNumHi">21 / 23</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="WrBypass.sv.gcov.html">WrBypass.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=93 height=10 alt="92.7%"><img src="../snow.png" width=7 height=10 alt="92.7%"></td></tr></table>
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+      <td class="coverPerHi">92.7&nbsp;%</td>
+      <td class="coverNumHi">114 / 123</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="array_3.sv.gcov.html">array_3.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">5 / 5</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="array_0_0.sv.gcov.html">array_0_0.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">6 / 6</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="array_4.sv.gcov.html">array_4.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">7 / 7</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="array_8.sv.gcov.html">array_8.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">7 / 7</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="array_5.sv.gcov.html">array_5.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">7 / 7</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="PriorityMuxModule_20.sv.gcov.html">PriorityMuxModule_20.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">8 / 8</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="array_7.sv.gcov.html">array_7.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">9 / 9</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="DelayN_4.sv.gcov.html">DelayN_4.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">9 / 9</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="array_6.sv.gcov.html">array_6.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">9 / 9</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="PriorityMuxModule_16.sv.gcov.html">PriorityMuxModule_16.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
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+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">10 / 10</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="PriorityMuxModule.sv.gcov.html">PriorityMuxModule.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">10 / 10</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="data_mem_0_4x2.sv.gcov.html">data_mem_0_4x2.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">13 / 13</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="data_mem_0_8x3.sv.gcov.html">data_mem_0_8x3.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
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+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">13 / 13</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="FoldedSRAMTemplate_21.sv.gcov.html">FoldedSRAMTemplate_21.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">13 / 13</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="DelayN_2.sv.gcov.html">DelayN_2.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">15 / 15</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="PriorityMuxModule_8.sv.gcov.html">PriorityMuxModule_8.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">16 / 16</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="array_3_ext.v.gcov.html">array_3_ext.v</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">16 / 16</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="array_4_ext.v.gcov.html">array_4_ext.v</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">16 / 16</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="array_0_0_ext.v.gcov.html">array_0_0_ext.v</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">16 / 16</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="data_32x16.sv.gcov.html">data_32x16.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">18 / 18</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="array_5_ext.v.gcov.html">array_5_ext.v</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">18 / 18</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="FoldedSRAMTemplate_1.sv.gcov.html">FoldedSRAMTemplate_1.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">18 / 18</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="array_8_ext.v.gcov.html">array_8_ext.v</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">18 / 18</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="data_16x16.sv.gcov.html">data_16x16.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">19 / 19</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="data_mem_8x4.sv.gcov.html">data_mem_8x4.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">20 / 20</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="DelayNWithValid.sv.gcov.html">DelayNWithValid.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">20 / 20</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="data_mem_16x12.sv.gcov.html">data_mem_16x12.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">20 / 20</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="array_7_ext.v.gcov.html">array_7_ext.v</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">21 / 21</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="CAMTemplate_41.sv.gcov.html">CAMTemplate_41.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">23 / 23</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="DelayN_1.sv.gcov.html">DelayN_1.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">23 / 23</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="array_6_ext.v.gcov.html">array_6_ext.v</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">25 / 25</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="Folded1WDataModuleTemplate.sv.gcov.html">Folded1WDataModuleTemplate.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">27 / 27</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="Folded1WDataModuleTemplate_2.sv.gcov.html">Folded1WDataModuleTemplate_2.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">27 / 27</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="FoldedSRAMTemplate_25.sv.gcov.html">FoldedSRAMTemplate_25.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">30 / 30</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="SCTable.sv.gcov.html">SCTable.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">34 / 34</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="TageBTable.sv.gcov.html">TageBTable.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">35 / 35</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="SCTable_2.sv.gcov.html">SCTable_2.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">37 / 37</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="SCTable_3.sv.gcov.html">SCTable_3.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">37 / 37</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="SRAMTemplate_39.sv.gcov.html">SRAMTemplate_39.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">37 / 37</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="SCTable_1.sv.gcov.html">SCTable_1.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">37 / 37</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="FoldedSRAMTemplate_20.sv.gcov.html">FoldedSRAMTemplate_20.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">38 / 38</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="CAMTemplate.sv.gcov.html">CAMTemplate.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">39 / 39</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="FoldedSRAMTemplate.sv.gcov.html">FoldedSRAMTemplate.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">40 / 40</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="ITTageTable_1.sv.gcov.html">ITTageTable_1.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">43 / 43</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="WrBypass_41.sv.gcov.html">WrBypass_41.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">43 / 43</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="WrBypass_43.sv.gcov.html">WrBypass_43.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">43 / 43</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="ITTageTable_2.sv.gcov.html">ITTageTable_2.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">44 / 44</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="ITTageTable.sv.gcov.html">ITTageTable.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">44 / 44</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="ITTageTable_3.sv.gcov.html">ITTageTable_3.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">44 / 44</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="ITTageTable_4.sv.gcov.html">ITTageTable_4.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">44 / 44</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="SRAMTemplate_15.sv.gcov.html">SRAMTemplate_15.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">44 / 44</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="SRAMTemplate_43.sv.gcov.html">SRAMTemplate_43.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">47 / 47</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="CAMTemplate_33.sv.gcov.html">CAMTemplate_33.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">71 / 71</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="FauFTBWay.sv.gcov.html">FauFTBWay.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">72 / 72</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="SRAMTemplate_14.sv.gcov.html">SRAMTemplate_14.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">95 / 95</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="TageTable.sv.gcov.html">TageTable.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">102 / 102</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="TageTable_3.sv.gcov.html">TageTable_3.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">107 / 107</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="TageTable_1.sv.gcov.html">TageTable_1.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">107 / 107</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="TageTable_2.sv.gcov.html">TageTable_2.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">107 / 107</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="PriorityMuxModule_4.sv.gcov.html">PriorityMuxModule_4.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">112 / 112</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="DelayNWithValid_1.sv.gcov.html">DelayNWithValid_1.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">128 / 128</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="PriorityMuxModule_12.sv.gcov.html">PriorityMuxModule_12.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">148 / 148</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="SRAMTemplate_13.sv.gcov.html">SRAMTemplate_13.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">183 / 183</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="WrBypass_33.sv.gcov.html">WrBypass_33.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">313 / 313</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="Composer.sv.gcov.html">Composer.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">320 / 320</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="RAS.sv.gcov.html">RAS.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">401 / 401</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="FTB.sv.gcov.html">FTB.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">703 / 703</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+  </table>
+  </center>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/index.html b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/index.html
new file mode 100644
index 0000000..b1262d6
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/BPUTop/index.html
@@ -0,0 +1,863 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info - BPUTop</title>
+  <link rel="stylesheet" type="text/css" href="../gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue"><a href="../index.html">top level</a> - BPUTop</td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">10047</td>
+            <td class="headerCovTableEntry">15626</td>
+            <td class="headerCovTableEntryLo">64.3 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="80%" cellpadding=1 cellspacing=1 border=0>
+
+    <tr>
+      <td width="50%"><br></td>
+      <td width="10%"></td>
+      <td width="10%"></td>
+      <td width="10%"></td>
+      <td width="10%"></td>
+      <td width="10%"></td>
+    </tr>
+
+    <tr>
+      <td class="tableHead">Filename <span class="tableHeadSort"><img src="../glass.png" width=10 height=14 alt="Sort by name" title="Sort by name" border=0></span></td>
+      <td class="tableHead" colspan=3>Line Coverage <span class="tableHeadSort"><a href="index-sort-l.html"><img src="../updown.png" width=10 height=14 alt="Sort by line coverage" title="Sort by line coverage" border=0></a></span></td>
+      <td class="tableHead" colspan=2>Functions <span class="tableHeadSort"><a href="index-sort-f.html"><img src="../updown.png" width=10 height=14 alt="Sort by function coverage" title="Sort by function coverage" border=0></a></span></td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="CAMTemplate.sv.gcov.html">CAMTemplate.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">39 / 39</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="CAMTemplate_32.sv.gcov.html">CAMTemplate_32.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../amber.png" width=85 height=10 alt="84.6%"><img src="../snow.png" width=15 height=10 alt="84.6%"></td></tr></table>
+      </td>
+      <td class="coverPerMed">84.6&nbsp;%</td>
+      <td class="coverNumMed">33 / 39</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="CAMTemplate_33.sv.gcov.html">CAMTemplate_33.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">71 / 71</td>
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+      <td class="coverPerHi">100.0&nbsp;%</td>
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+    <tr>
+      <td class="coverFile"><a href="CAMTemplate_43.sv.gcov.html">CAMTemplate_43.sv</a></td>
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+    </tr>
+    <tr>
+      <td class="coverFile"><a href="Composer.sv.gcov.html">Composer.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
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+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">320 / 320</td>
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+    <tr>
+      <td class="coverFile"><a href="DelayNWithValid.sv.gcov.html">DelayNWithValid.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
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+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">20 / 20</td>
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+      <td class="coverNumHi">0 / 0</td>
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+    <tr>
+      <td class="coverFile"><a href="DelayNWithValid_1.sv.gcov.html">DelayNWithValid_1.sv</a></td>
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+      <td class="coverNumHi">128 / 128</td>
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+    <tr>
+      <td class="coverFile"><a href="DelayN_1.sv.gcov.html">DelayN_1.sv</a></td>
+      <td class="coverBar" align="center">
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+    <tr>
+      <td class="coverFile"><a href="DelayN_2.sv.gcov.html">DelayN_2.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
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+      <td class="coverFile"><a href="DelayN_4.sv.gcov.html">DelayN_4.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
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+    <tr>
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+      <td class="coverNumHi">703 / 703</td>
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+      <td class="coverFile"><a href="FauFTB.sv.gcov.html">FauFTB.sv</a></td>
+      <td class="coverBar" align="center">
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+    <tr>
+      <td class="coverFile"><a href="FauFTBWay.sv.gcov.html">FauFTBWay.sv</a></td>
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+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">72 / 72</td>
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+    </tr>
+    <tr>
+      <td class="coverFile"><a href="Folded1WDataModuleTemplate.sv.gcov.html">Folded1WDataModuleTemplate.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
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+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">27 / 27</td>
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+    </tr>
+    <tr>
+      <td class="coverFile"><a href="Folded1WDataModuleTemplate_2.sv.gcov.html">Folded1WDataModuleTemplate_2.sv</a></td>
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+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
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+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">27 / 27</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="FoldedSRAMTemplate.sv.gcov.html">FoldedSRAMTemplate.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">40 / 40</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="FoldedSRAMTemplate_1.sv.gcov.html">FoldedSRAMTemplate_1.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">18 / 18</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="FoldedSRAMTemplate_20.sv.gcov.html">FoldedSRAMTemplate_20.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">38 / 38</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="FoldedSRAMTemplate_21.sv.gcov.html">FoldedSRAMTemplate_21.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
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+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">13 / 13</td>
+      <td class="coverPerHi">-</td>
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+    </tr>
+    <tr>
+      <td class="coverFile"><a href="FoldedSRAMTemplate_25.sv.gcov.html">FoldedSRAMTemplate_25.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
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+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">30 / 30</td>
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+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="ITTage.sv.gcov.html">ITTage.sv</a></td>
+      <td class="coverBar" align="center">
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+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="ITTageTable.sv.gcov.html">ITTageTable.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
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+      <td class="coverNumHi">44 / 44</td>
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+    <tr>
+      <td class="coverFile"><a href="ITTageTable_1.sv.gcov.html">ITTageTable_1.sv</a></td>
+      <td class="coverBar" align="center">
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+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">43 / 43</td>
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+    </tr>
+    <tr>
+      <td class="coverFile"><a href="ITTageTable_2.sv.gcov.html">ITTageTable_2.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
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+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">44 / 44</td>
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+    </tr>
+    <tr>
+      <td class="coverFile"><a href="ITTageTable_3.sv.gcov.html">ITTageTable_3.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
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+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">44 / 44</td>
+      <td class="coverPerHi">-</td>
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+    </tr>
+    <tr>
+      <td class="coverFile"><a href="ITTageTable_4.sv.gcov.html">ITTageTable_4.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
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+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">44 / 44</td>
+      <td class="coverPerHi">-</td>
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+    </tr>
+    <tr>
+      <td class="coverFile"><a href="PriorityMuxModule.sv.gcov.html">PriorityMuxModule.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
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+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">10 / 10</td>
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+    <tr>
+      <td class="coverFile"><a href="PriorityMuxModule_12.sv.gcov.html">PriorityMuxModule_12.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
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+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">148 / 148</td>
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+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="PriorityMuxModule_16.sv.gcov.html">PriorityMuxModule_16.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
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+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">10 / 10</td>
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+      <td class="coverNumHi">0 / 0</td>
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+    <tr>
+      <td class="coverFile"><a href="PriorityMuxModule_20.sv.gcov.html">PriorityMuxModule_20.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
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+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">8 / 8</td>
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+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="PriorityMuxModule_4.sv.gcov.html">PriorityMuxModule_4.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
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+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">112 / 112</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="PriorityMuxModule_8.sv.gcov.html">PriorityMuxModule_8.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
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+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">16 / 16</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="RAS.sv.gcov.html">RAS.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
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+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">401 / 401</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
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+    <tr>
+      <td class="coverFile"><a href="RASStack.sv.gcov.html">RASStack.sv</a></td>
+      <td class="coverBar" align="center">
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+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="SCTable.sv.gcov.html">SCTable.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
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+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">34 / 34</td>
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+    <tr>
+      <td class="coverFile"><a href="SCTable_1.sv.gcov.html">SCTable_1.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">37 / 37</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="SCTable_2.sv.gcov.html">SCTable_2.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
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+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">37 / 37</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="SCTable_3.sv.gcov.html">SCTable_3.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">37 / 37</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="SRAMTemplate_13.sv.gcov.html">SRAMTemplate_13.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
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+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">183 / 183</td>
+      <td class="coverPerHi">-</td>
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+    </tr>
+    <tr>
+      <td class="coverFile"><a href="SRAMTemplate_14.sv.gcov.html">SRAMTemplate_14.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
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+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">95 / 95</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="SRAMTemplate_15.sv.gcov.html">SRAMTemplate_15.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">44 / 44</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="SRAMTemplate_34.sv.gcov.html">SRAMTemplate_34.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../amber.png" width=86 height=10 alt="85.6%"><img src="../snow.png" width=14 height=10 alt="85.6%"></td></tr></table>
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+      <td class="coverPerMed">85.6&nbsp;%</td>
+      <td class="coverNumMed">77 / 90</td>
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+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="SRAMTemplate_35.sv.gcov.html">SRAMTemplate_35.sv</a></td>
+      <td class="coverBar" align="center">
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+      <td class="coverPerMed">87.0&nbsp;%</td>
+      <td class="coverNumMed">60 / 69</td>
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+      <td class="coverNumHi">0 / 0</td>
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+    <tr>
+      <td class="coverFile"><a href="SRAMTemplate_39.sv.gcov.html">SRAMTemplate_39.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
+      </td>
+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">37 / 37</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="SRAMTemplate_43.sv.gcov.html">SRAMTemplate_43.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
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+      <td class="coverPerHi">100.0&nbsp;%</td>
+      <td class="coverNumHi">47 / 47</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="TageBTable.sv.gcov.html">TageBTable.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
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+      <td class="coverPerHi">100.0&nbsp;%</td>
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+    <tr>
+      <td class="coverFile"><a href="TageTable.sv.gcov.html">TageTable.sv</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
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+      <td class="coverFile"><a href="TageTable_1.sv.gcov.html">TageTable_1.sv</a></td>
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+    <tr>
+      <td class="coverFile"><a href="TageTable_2.sv.gcov.html">TageTable_2.sv</a></td>
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+      <td class="coverFile"><a href="WrBypass_33.sv.gcov.html">WrBypass_33.sv</a></td>
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+      <td class="coverFile"><a href="WrBypass_43.sv.gcov.html">WrBypass_43.sv</a></td>
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+      <td class="coverFile"><a href="array_8.sv.gcov.html">array_8.sv</a></td>
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+      <td class="coverFile"><a href="array_8_ext.v.gcov.html">array_8_ext.v</a></td>
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+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
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+      <td class="coverFile"><a href="data_32x16.sv.gcov.html">data_32x16.sv</a></td>
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+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
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+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="../emerald.png" width=100 height=10 alt="100.0%"></td></tr></table>
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+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="../glass.png" width=3 height=3 alt=""></td></tr>
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+  <br>
+
+</body>
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diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/amber.png b/tests/bpu_top/reports/report-20241027201927/line_dat/amber.png
new file mode 100644
index 0000000000000000000000000000000000000000..2cab170d8359081983a4e343848dfe06bc490f12
GIT binary patch
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new file mode 100644
index 0000000000000000000000000000000000000000..38ad4f4068b935643d2486f323005fb294a9bd7e
GIT binary patch
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diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/gcov.css b/tests/bpu_top/reports/report-20241027201927/line_dat/gcov.css
new file mode 100644
index 0000000..bfd0a83
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/gcov.css
@@ -0,0 +1,519 @@
+/* All views: initial background and text color */
+body
+{
+  color: #000000;
+  background-color: #FFFFFF;
+}
+
+/* All views: standard link format*/
+a:link
+{
+  color: #284FA8;
+  text-decoration: underline;
+}
+
+/* All views: standard link - visited format */
+a:visited
+{
+  color: #00CB40;
+  text-decoration: underline;
+}
+
+/* All views: standard link - activated format */
+a:active
+{
+  color: #FF0040;
+  text-decoration: underline;
+}
+
+/* All views: main title format */
+td.title
+{
+  text-align: center;
+  padding-bottom: 10px;
+  font-family: sans-serif;
+  font-size: 20pt;
+  font-style: italic;
+  font-weight: bold;
+}
+
+/* All views: header item format */
+td.headerItem
+{
+  text-align: right;
+  padding-right: 6px;
+  font-family: sans-serif;
+  font-weight: bold;
+  vertical-align: top;
+  white-space: nowrap;
+}
+
+/* All views: header item value format */
+td.headerValue
+{
+  text-align: left;
+  color: #284FA8;
+  font-family: sans-serif;
+  font-weight: bold;
+  white-space: nowrap;
+}
+
+/* All views: header item coverage table heading */
+td.headerCovTableHead
+{
+  text-align: center;
+  padding-right: 6px;
+  padding-left: 6px;
+  padding-bottom: 0px;
+  font-family: sans-serif;
+  font-size: 80%;
+  white-space: nowrap;
+}
+
+/* All views: header item coverage table entry */
+td.headerCovTableEntry
+{
+  text-align: right;
+  color: #284FA8;
+  font-family: sans-serif;
+  font-weight: bold;
+  white-space: nowrap;
+  padding-left: 12px;
+  padding-right: 4px;
+  background-color: #DAE7FE;
+}
+
+/* All views: header item coverage table entry for high coverage rate */
+td.headerCovTableEntryHi
+{
+  text-align: right;
+  color: #000000;
+  font-family: sans-serif;
+  font-weight: bold;
+  white-space: nowrap;
+  padding-left: 12px;
+  padding-right: 4px;
+  background-color: #A7FC9D;
+}
+
+/* All views: header item coverage table entry for medium coverage rate */
+td.headerCovTableEntryMed
+{
+  text-align: right;
+  color: #000000;
+  font-family: sans-serif;
+  font-weight: bold;
+  white-space: nowrap;
+  padding-left: 12px;
+  padding-right: 4px;
+  background-color: #FFEA20;
+}
+
+/* All views: header item coverage table entry for ow coverage rate */
+td.headerCovTableEntryLo
+{
+  text-align: right;
+  color: #000000;
+  font-family: sans-serif;
+  font-weight: bold;
+  white-space: nowrap;
+  padding-left: 12px;
+  padding-right: 4px;
+  background-color: #FF0000;
+}
+
+/* All views: header legend value for legend entry */
+td.headerValueLeg
+{
+  text-align: left;
+  color: #000000;
+  font-family: sans-serif;
+  font-size: 80%;
+  white-space: nowrap;
+  padding-top: 4px;
+}
+
+/* All views: color of horizontal ruler */
+td.ruler
+{
+  background-color: #6688D4;
+}
+
+/* All views: version string format */
+td.versionInfo
+{
+  text-align: center;
+  padding-top: 2px;
+  font-family: sans-serif;
+  font-style: italic;
+}
+
+/* Directory view/File view (all)/Test case descriptions:
+   table headline format */
+td.tableHead
+{
+  text-align: center;
+  color: #FFFFFF;
+  background-color: #6688D4;
+  font-family: sans-serif;
+  font-size: 120%;
+  font-weight: bold;
+  white-space: nowrap;
+  padding-left: 4px;
+  padding-right: 4px;
+}
+
+span.tableHeadSort
+{
+  padding-right: 4px;
+}
+
+/* Directory view/File view (all): filename entry format */
+td.coverFile
+{
+  text-align: left;
+  padding-left: 10px;
+  padding-right: 20px; 
+  color: #284FA8;
+  background-color: #DAE7FE;
+  font-family: monospace;
+}
+
+/* Directory view/File view (all): bar-graph entry format*/
+td.coverBar
+{
+  padding-left: 10px;
+  padding-right: 10px;
+  background-color: #DAE7FE;
+}
+
+/* Directory view/File view (all): bar-graph outline color */
+td.coverBarOutline
+{
+  background-color: #000000;
+}
+
+/* Directory view/File view (all): percentage entry for files with
+   high coverage rate */
+td.coverPerHi
+{
+  text-align: right;
+  padding-left: 10px;
+  padding-right: 10px;
+  background-color: #A7FC9D;
+  font-weight: bold;
+  font-family: sans-serif;
+}
+
+/* Directory view/File view (all): line count entry for files with
+   high coverage rate */
+td.coverNumHi
+{
+  text-align: right;
+  padding-left: 10px;
+  padding-right: 10px;
+  background-color: #A7FC9D;
+  white-space: nowrap;
+  font-family: sans-serif;
+}
+
+/* Directory view/File view (all): percentage entry for files with
+   medium coverage rate */
+td.coverPerMed
+{
+  text-align: right;
+  padding-left: 10px;
+  padding-right: 10px;
+  background-color: #FFEA20;
+  font-weight: bold;
+  font-family: sans-serif;
+}
+
+/* Directory view/File view (all): line count entry for files with
+   medium coverage rate */
+td.coverNumMed
+{
+  text-align: right;
+  padding-left: 10px;
+  padding-right: 10px;
+  background-color: #FFEA20;
+  white-space: nowrap;
+  font-family: sans-serif;
+}
+
+/* Directory view/File view (all): percentage entry for files with
+   low coverage rate */
+td.coverPerLo
+{
+  text-align: right;
+  padding-left: 10px;
+  padding-right: 10px;
+  background-color: #FF0000;
+  font-weight: bold;
+  font-family: sans-serif;
+}
+
+/* Directory view/File view (all): line count entry for files with
+   low coverage rate */
+td.coverNumLo
+{
+  text-align: right;
+  padding-left: 10px;
+  padding-right: 10px;
+  background-color: #FF0000;
+  white-space: nowrap;
+  font-family: sans-serif;
+}
+
+/* File view (all): "show/hide details" link format */
+a.detail:link
+{
+  color: #B8D0FF;
+  font-size:80%;
+}
+
+/* File view (all): "show/hide details" link - visited format */
+a.detail:visited
+{
+  color: #B8D0FF;
+  font-size:80%;
+}
+
+/* File view (all): "show/hide details" link - activated format */
+a.detail:active
+{
+  color: #FFFFFF;
+  font-size:80%;
+}
+
+/* File view (detail): test name entry */
+td.testName
+{
+  text-align: right;
+  padding-right: 10px;
+  background-color: #DAE7FE;
+  font-family: sans-serif;
+}
+
+/* File view (detail): test percentage entry */
+td.testPer
+{
+  text-align: right;
+  padding-left: 10px;
+  padding-right: 10px; 
+  background-color: #DAE7FE;
+  font-family: sans-serif;
+}
+
+/* File view (detail): test lines count entry */
+td.testNum
+{
+  text-align: right;
+  padding-left: 10px;
+  padding-right: 10px; 
+  background-color: #DAE7FE;
+  font-family: sans-serif;
+}
+
+/* Test case descriptions: test name format*/
+dt
+{
+  font-family: sans-serif;
+  font-weight: bold;
+}
+
+/* Test case descriptions: description table body */
+td.testDescription
+{
+  padding-top: 10px;
+  padding-left: 30px;
+  padding-bottom: 10px;
+  padding-right: 30px;
+  background-color: #DAE7FE;
+}
+
+/* Source code view: function entry */
+td.coverFn
+{
+  text-align: left;
+  padding-left: 10px;
+  padding-right: 20px; 
+  color: #284FA8;
+  background-color: #DAE7FE;
+  font-family: monospace;
+}
+
+/* Source code view: function entry zero count*/
+td.coverFnLo
+{
+  text-align: right;
+  padding-left: 10px;
+  padding-right: 10px;
+  background-color: #FF0000;
+  font-weight: bold;
+  font-family: sans-serif;
+}
+
+/* Source code view: function entry nonzero count*/
+td.coverFnHi
+{
+  text-align: right;
+  padding-left: 10px;
+  padding-right: 10px;
+  background-color: #DAE7FE;
+  font-weight: bold;
+  font-family: sans-serif;
+}
+
+/* Source code view: source code format */
+pre.source
+{
+  font-family: monospace;
+  white-space: pre;
+  margin-top: 2px;
+}
+
+/* Source code view: line number format */
+span.lineNum
+{
+  background-color: #EFE383;
+}
+
+/* Source code view: format for lines which were executed */
+td.lineCov,
+span.lineCov
+{
+  background-color: #CAD7FE;
+}
+
+/* Source code view: format for Cov legend */
+span.coverLegendCov
+{
+  padding-left: 10px;
+  padding-right: 10px;
+  padding-bottom: 2px;
+  background-color: #CAD7FE;
+}
+
+/* Source code view: format for lines which were not executed */
+td.lineNoCov,
+span.lineNoCov
+{
+  background-color: #FF6230;
+}
+
+/* Source code view: format for NoCov legend */
+span.coverLegendNoCov
+{
+  padding-left: 10px;
+  padding-right: 10px;
+  padding-bottom: 2px;
+  background-color: #FF6230;
+}
+
+/* Source code view (function table): standard link - visited format */
+td.lineNoCov > a:visited,
+td.lineCov > a:visited
+{  
+  color: black;
+  text-decoration: underline;
+}  
+
+/* Source code view: format for lines which were executed only in a
+   previous version */
+span.lineDiffCov
+{
+  background-color: #B5F7AF;
+}
+
+/* Source code view: format for branches which were executed
+ * and taken */
+span.branchCov
+{
+  background-color: #CAD7FE;
+}
+
+/* Source code view: format for branches which were executed
+ * but not taken */
+span.branchNoCov
+{
+  background-color: #FF6230;
+}
+
+/* Source code view: format for branches which were not executed */
+span.branchNoExec
+{
+  background-color: #FF6230;
+}
+
+/* Source code view: format for the source code heading line */
+pre.sourceHeading
+{
+  white-space: pre;
+  font-family: monospace;
+  font-weight: bold;
+  margin: 0px;
+}
+
+/* All views: header legend value for low rate */
+td.headerValueLegL
+{
+  font-family: sans-serif;
+  text-align: center;
+  white-space: nowrap;
+  padding-left: 4px;
+  padding-right: 2px;
+  background-color: #FF0000;
+  font-size: 80%;
+}
+
+/* All views: header legend value for med rate */
+td.headerValueLegM
+{
+  font-family: sans-serif;
+  text-align: center;
+  white-space: nowrap;
+  padding-left: 2px;
+  padding-right: 2px;
+  background-color: #FFEA20;
+  font-size: 80%;
+}
+
+/* All views: header legend value for hi rate */
+td.headerValueLegH
+{
+  font-family: sans-serif;
+  text-align: center;
+  white-space: nowrap;
+  padding-left: 2px;
+  padding-right: 4px;
+  background-color: #A7FC9D;
+  font-size: 80%;
+}
+
+/* All views except source code view: legend format for low coverage */
+span.coverLegendCovLo
+{
+  padding-left: 10px;
+  padding-right: 10px;
+  padding-top: 2px;
+  background-color: #FF0000;
+}
+
+/* All views except source code view: legend format for med coverage */
+span.coverLegendCovMed
+{
+  padding-left: 10px;
+  padding-right: 10px;
+  padding-top: 2px;
+  background-color: #FFEA20;
+}
+
+/* All views except source code view: legend format for hi coverage */
+span.coverLegendCovHi
+{
+  padding-left: 10px;
+  padding-right: 10px;
+  padding-top: 2px;
+  background-color: #A7FC9D;
+}
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/glass.png b/tests/bpu_top/reports/report-20241027201927/line_dat/glass.png
new file mode 100644
index 0000000000000000000000000000000000000000..e1abc00680a3093c49fdb775ae6bdb6764c95af2
GIT binary patch
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HcmV?d00001

diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/index-sort-f.html b/tests/bpu_top/reports/report-20241027201927/line_dat/index-sort-f.html
new file mode 100644
index 0000000..cc2b125
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/index-sort-f.html
@@ -0,0 +1,103 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info</title>
+  <link rel="stylesheet" type="text/css" href="gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue">top level</td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">15643</td>
+            <td class="headerCovTableEntry">21948</td>
+            <td class="headerCovTableEntryLo">71.3 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="80%" cellpadding=1 cellspacing=1 border=0>
+
+    <tr>
+      <td width="50%"><br></td>
+      <td width="10%"></td>
+      <td width="10%"></td>
+      <td width="10%"></td>
+      <td width="10%"></td>
+      <td width="10%"></td>
+    </tr>
+
+    <tr>
+      <td class="tableHead">Directory <span class="tableHeadSort"><a href="index.html"><img src="updown.png" width=10 height=14 alt="Sort by name" title="Sort by name" border=0></a></span></td>
+      <td class="tableHead" colspan=3>Line Coverage <span class="tableHeadSort"><a href="index-sort-l.html"><img src="updown.png" width=10 height=14 alt="Sort by line coverage" title="Sort by line coverage" border=0></a></span></td>
+      <td class="tableHead" colspan=2>Functions <span class="tableHeadSort"><img src="glass.png" width=10 height=14 alt="Sort by function coverage" title="Sort by function coverage" border=0></span></td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="BPUTop/index.html">BPUTop</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="ruby.png" width=64 height=10 alt="64.3%"><img src="snow.png" width=36 height=10 alt="64.3%"></td></tr></table>
+      </td>
+      <td class="coverPerLo">64.3&nbsp;%</td>
+      <td class="coverNumLo">10047 / 15626</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="home/xianshan/glcc/xianshan/env-xs-ov-00-bpu/out/picker_out_BPUTop/index.html">/home/xianshan/glcc/xianshan/env-xs-ov-00-bpu/out/picker_out_BPUTop</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="amber.png" width=89 height=10 alt="88.5%"><img src="snow.png" width=11 height=10 alt="88.5%"></td></tr></table>
+      </td>
+      <td class="coverPerMed">88.5&nbsp;%</td>
+      <td class="coverNumMed">5596 / 6322</td>
+      <td class="coverPerHi">-</td>
+      <td class="coverNumHi">0 / 0</td>
+    </tr>
+  </table>
+  </center>
+  <br>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="ruler"><img src="glass.png" width=3 height=3 alt=""></td></tr>
+    <tr><td class="versionInfo">Generated by: <a href="http://ltp.sourceforge.net/coverage/lcov.php">LCOV version 1.14</a></td></tr>
+  </table>
+  <br>
+
+</body>
+</html>
diff --git a/tests/bpu_top/reports/report-20241027201927/line_dat/index-sort-l.html b/tests/bpu_top/reports/report-20241027201927/line_dat/index-sort-l.html
new file mode 100644
index 0000000..8468510
--- /dev/null
+++ b/tests/bpu_top/reports/report-20241027201927/line_dat/index-sort-l.html
@@ -0,0 +1,103 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+
+<html lang="en">
+
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
+  <title>LCOV - merged.info</title>
+  <link rel="stylesheet" type="text/css" href="gcov.css">
+</head>
+
+<body>
+
+  <table width="100%" border=0 cellspacing=0 cellpadding=0>
+    <tr><td class="title">LCOV - code coverage report</td></tr>
+    <tr><td class="ruler"><img src="glass.png" width=3 height=3 alt=""></td></tr>
+
+    <tr>
+      <td width="100%">
+        <table cellpadding=1 border=0 width="100%">
+          <tr>
+            <td width="10%" class="headerItem">Current view:</td>
+            <td width="35%" class="headerValue">top level</td>
+            <td width="5%"></td>
+            <td width="15%"></td>
+            <td width="10%" class="headerCovTableHead">Hit</td>
+            <td width="10%" class="headerCovTableHead">Total</td>
+            <td width="15%" class="headerCovTableHead">Coverage</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Test:</td>
+            <td class="headerValue">merged.info</td>
+            <td></td>
+            <td class="headerItem">Lines:</td>
+            <td class="headerCovTableEntry">15643</td>
+            <td class="headerCovTableEntry">21948</td>
+            <td class="headerCovTableEntryLo">71.3 %</td>
+          </tr>
+          <tr>
+            <td class="headerItem">Date:</td>
+            <td class="headerValue">2024-10-27 20:24:07</td>
+            <td></td>
+            <td class="headerItem">Functions:</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntry">0</td>
+            <td class="headerCovTableEntryHi">-</td>
+          </tr>
+          <tr><td><img src="glass.png" width=3 height=3 alt=""></td></tr>
+        </table>
+      </td>
+    </tr>
+
+    <tr><td class="ruler"><img src="glass.png" width=3 height=3 alt=""></td></tr>
+  </table>
+
+  <center>
+  <table width="80%" cellpadding=1 cellspacing=1 border=0>
+
+    <tr>
+      <td width="50%"><br></td>
+      <td width="10%"></td>
+      <td width="10%"></td>
+      <td width="10%"></td>
+      <td width="10%"></td>
+      <td width="10%"></td>
+    </tr>
+
+    <tr>
+      <td class="tableHead">Directory <span class="tableHeadSort"><a href="index.html"><img src="updown.png" width=10 height=14 alt="Sort by name" title="Sort by name" border=0></a></span></td>
+      <td class="tableHead" colspan=3>Line Coverage <span class="tableHeadSort"><img src="glass.png" width=10 height=14 alt="Sort by line coverage" title="Sort by line coverage" border=0></span></td>
+      <td class="tableHead" colspan=2>Functions <span class="tableHeadSort"><a href="index-sort-f.html"><img src="updown.png" width=10 height=14 alt="Sort by function coverage" title="Sort by function coverage" border=0></a></span></td>
+    </tr>
+    <tr>
+      <td class="coverFile"><a href="BPUTop/index.html">BPUTop</a></td>
+      <td class="coverBar" align="center">
+        <table border=0 cellspacing=0 cellpadding=1><tr><td class="coverBarOutline"><img src="ruby.png" width=64 height=10 alt="64.3%"><img src="snow.png" width=36 height=10 alt="64.3%"></td></tr></table>
+      </td>
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+            <td width="15%"></td>
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+  </style><script>
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+
+  </script></head> <body> <header> <div class=container> <span class=report-title>XiangShan-BPU UT-Test Report</span> </div> </header> <main> <section id=summary> <div class=container> <h1>Summary</h1> <div class=metadata> <table> <tr> <th>Started</th> <td>2024-10-27 20:19:27</td> </tr> <tr> <th>Ended</th> <td> 2024-10-27 20:24:05 </td> </tr> <tr> <th>Duration</th> <td>0:04:38.217004</td> </tr> <tr> <th>Total run time</th> <td>0:04:38.082693</td> </tr> <tr> <th>Python</th> <td> 3.10.12 </td> </tr> <tr> <th>Platform</th> <td> Linux-6.8.0-40-generic-x86_64-with-glibc2.35 </td> </tr> </table> </div> <div class=graph> <svg width=200 height=200 viewbox="0 0 42 42"> <circle class="donut-segment passed" stroke-dasharray="100.13096491487337 0.4000000000000057" stroke-dashoffset=125.46370614359172 cx=21 cy=21 r=16 fill=transparent stroke=#43A047 stroke-width=4> </circle> <text x=21 y=24 text-anchor=middle>29</text> </svg> <div class=legend> <span class="status badge passed "> 29 </span> <span>passed</span> </div> </div> </div> </section> <div id=functional-detail-modal-overlay class=modal-overlay></div> <div id=functional-detail-modal class=modal> <div class=container> <h2>Functional Coverage <button onclick=closeFunctionalDetailModal() style="float: right; top: 5px;">close</button></h2> </div> <hr> <div class="cantainer coverage-list"> <div style="text-align: center;"> Groups: 0/0 (<span style="font-weight: bold; color: red ;">0%</span>) &nbsp;&nbsp;&nbsp;&nbsp; Points: 0/0 (<span style="font-weight: bold; color: red ;">0%</span>) &nbsp;&nbsp;&nbsp;&nbsp; Bins: 0/0 (<span style="font-weight: bold; color: red ;">0%</span>) </div> <ul style="height: 66.67vh; overflow: auto; border-top: 1px solid #ccc; border-bottom: 1px solid #ccc; padding-right:10px"> </ul> </div> </div> <section id=coverage> <hr> <div class=container> <table style="width: 100%;"> <td> <h3>Line Coverage</h3> <table class=min-width-td> <tr> <th>Coverage Rate</th> <th>Hint Lines</th> <th>Total Lines</th> <th>Detail</th> </tr> <tr> <td> <span style="font-weight: bold; color:  red ;">71.27%</span> </td> <td>15643</td> <td>21948</td> <td><a href=line_dat/index.html target=_blank>View Details</a></td> </tr> </table> </td> <td> <h3>Functional Coverage</h3> <table class=min-width-td> <tr> <th>Coverage Rate</th> <th>Hint Points</th> <th>Total Points</th> <th>Detail</th> </tr> <tr> <tr> <td> <span style="font-weight: bold; color:  red ;">0%</span> </td> <td>0</td> <td>0</td> <td><a href=javascript:openFunctionalDetailModal()>View Details</a></td> </tr> </tr> </table> </td> </table> </div> <hr> </section> <section id=test-files> <div class=container> <h1>Tests</h1> <details class=file> <summary> <h2 class="title file-title"> <span class=fspath> test_bpu_top_all.py </span> <span class=counts> <span title="29 passed" class="count status badge passed ">29</span> </span> <span class=duration> 0:04:38.082693 </span> </h2> </summary> <div class="content box"> <details class="test passed"> <summary> <h3 class="title test-title"> <span class="status badge passed ">PASSED</span> <span class=test-name> <span class=funcname>test_redirect_signals_sanity</span> </span> <span class=duration>0:00:09.533072</span> </h3> </summary> <div class=content> <table class=metadata> <tr> <th>Started</th> <td>2024-10-27 20:19:27</td> </tr> <tr> <th>Ended</th> <td>2024-10-27 20:19:36</td> </tr> <tr> <th>Duration</th> <td>0:00:09.533072</td> </tr> <tr> <th>Markers</th> <td> <div class=marker> <span class="marker-name badge">mlvp_async</span> <span class=marker-args> </span> </div> </td> </tr> <tr> <th>Fixtures</th> <td> <span class="badge fixturename"> mlvp_request </span> <span class="badge fixturename"> mlvp_pre_request </span> <span class="badge fixturename"> request </span> </td> </tr> </table> <div class=test-phases> <details class="phase setup passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Setup</span> </h4> </summary> <div class=content> <div class=section> <h5 class=section-title>Captured stderr setup</h5> <pre><samp><span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_btb_enable&#34; is connected to &#34;io_ctrl_btb_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_ras_enable&#34; is connected to &#34;io_ctrl_ras_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_sc_enable&#34; is connected to &#34;io_ctrl_sc_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_tage_enable&#34; is connected to &#34;io_ctrl_tage_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_ubtb_enable&#34; is connected to &#34;io_ctrl_ubtb_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34;</span>
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+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_level&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_level&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured log setup</h5> <pre><samp><span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_btb_enable&#34; is connected to &#34;io_ctrl_btb_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_ras_enable&#34; is connected to &#34;io_ctrl_ras_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_sc_enable&#34; is connected to &#34;io_ctrl_sc_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_tage_enable&#34; is connected to &#34;io_ctrl_tage_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_ubtb_enable&#34; is connected to &#34;io_ctrl_ubtb_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_full_target&#34; is connected to &#34;io_ftq_to_bpu_update_bits_full_target&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34; is connected to &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_meta&#34; is connected to &#34;io_ftq_to_bpu_update_bits_meta&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_old_entry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_old_entry&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_level&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_level&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</samp></pre> </div> </div> </details> <details class="phase call passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Call</span> </h4> </summary> <div class=content> <div class=section> <h5 class=section-title>Captured stdout call</h5> <pre><samp>&lt;function mlvp_request.&lt;locals&gt;.start_code at 0x759cc153d480&gt;
+begin exec test_redirect_signals_sanity test
+test_update_signals_sanity IS OVER
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured stderr call</h5> <pre><samp><span class=ansi37>MLVP_INFO @logger.py:147:	Log Summary
+============
+* Report counts by severity
+INFO:	143
+</span>
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured log call</h5> <pre><samp><span class=ansi32>INFO    </span> MLVP:logger.py:147 Log Summary
+============
+* Report counts by severity
+INFO:	143</samp></pre> </div> </div> </details> <details class="phase teardown passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Teardown</span> </h4> </summary> <div class=content> </div> </details> </div> </div> </details> <details class="test passed"> <summary> <h3 class="title test-title"> <span class="status badge passed ">PASSED</span> <span class=test-name> <span class=funcname>test_normal_sanity</span> </span> <span class=duration>0:00:09.140642</span> </h3> </summary> <div class=content> <table class=metadata> <tr> <th>Started</th> <td>2024-10-27 20:19:36</td> </tr> <tr> <th>Ended</th> <td>2024-10-27 20:19:46</td> </tr> <tr> <th>Duration</th> <td>0:00:09.140642</td> </tr> <tr> <th>Markers</th> <td> <div class=marker> <span class="marker-name badge">mlvp_async</span> <span class=marker-args> </span> </div> </td> </tr> <tr> <th>Fixtures</th> <td> <span class="badge fixturename"> mlvp_request </span> <span class="badge fixturename"> mlvp_pre_request </span> <span class="badge fixturename"> request </span> </td> </tr> </table> <div class=test-phases> <details class="phase setup passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Setup</span> </h4> </summary> <div class=content> <div class=section> <h5 class=section-title>Captured stderr setup</h5> <pre><samp><span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_btb_enable&#34; is connected to &#34;io_ctrl_btb_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_ras_enable&#34; is connected to &#34;io_ctrl_ras_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_sc_enable&#34; is connected to &#34;io_ctrl_sc_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_tage_enable&#34; is connected to &#34;io_ctrl_tage_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_ubtb_enable&#34; is connected to &#34;io_ctrl_ubtb_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_full_target&#34; is connected to &#34;io_ftq_to_bpu_update_bits_full_target&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34; is connected to &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_meta&#34; is connected to &#34;io_ftq_to_bpu_update_bits_meta&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_old_entry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_old_entry&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_level&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_level&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured log setup</h5> <pre><samp><span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_btb_enable&#34; is connected to &#34;io_ctrl_btb_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_ras_enable&#34; is connected to &#34;io_ctrl_ras_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_sc_enable&#34; is connected to &#34;io_ctrl_sc_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_tage_enable&#34; is connected to &#34;io_ctrl_tage_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_ubtb_enable&#34; is connected to &#34;io_ctrl_ubtb_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_full_target&#34; is connected to &#34;io_ftq_to_bpu_update_bits_full_target&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34; is connected to &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_meta&#34; is connected to &#34;io_ftq_to_bpu_update_bits_meta&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_old_entry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_old_entry&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_level&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_level&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</samp></pre> </div> </div> </details> <details class="phase call passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Call</span> </h4> </summary> <div class=content> <div class=section> <h5 class=section-title>Captured stdout call</h5> <pre><samp>&lt;function mlvp_request.&lt;locals&gt;.start_code at 0x759cc153df30&gt;
+set_sub_predic_ctrl_en Begin exec
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+begin exec test_redirect_signals_sanity test
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+test_normal_sanity IS OVER
+1
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured stderr call</h5> <pre><samp><span class=ansi37>MLVP_INFO @logger.py:147:	Log Summary
+============
+* Report counts by severity
+INFO:	287
+</span>
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured log call</h5> <pre><samp><span class=ansi32>INFO    </span> MLVP:logger.py:147 Log Summary
+============
+* Report counts by severity
+INFO:	287</samp></pre> </div> </div> </details> <details class="phase teardown passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Teardown</span> </h4> </summary> <div class=content> </div> </details> </div> </div> </details> <details class="test passed"> <summary> <h3 class="title test-title"> <span class="status badge passed ">PASSED</span> <span class=test-name> <span class=funcname>test_normal_update_cfi_sanity</span> </span> <span class=duration>0:00:09.083435</span> </h3> </summary> <div class=content> <table class=metadata> <tr> <th>Started</th> <td>2024-10-27 20:19:46</td> </tr> <tr> <th>Ended</th> <td>2024-10-27 20:19:55</td> </tr> <tr> <th>Duration</th> <td>0:00:09.083435</td> </tr> <tr> <th>Markers</th> <td> <div class=marker> <span class="marker-name badge">mlvp_async</span> <span class=marker-args> </span> </div> </td> </tr> <tr> <th>Fixtures</th> <td> <span class="badge fixturename"> mlvp_request </span> <span class="badge fixturename"> mlvp_pre_request </span> <span class="badge fixturename"> request </span> </td> </tr> </table> <div class=test-phases> <details class="phase setup passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Setup</span> </h4> </summary> <div class=content> <div class=section> <h5 class=section-title>Captured stderr setup</h5> <pre><samp><span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_btb_enable&#34; is connected to &#34;io_ctrl_btb_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_ras_enable&#34; is connected to &#34;io_ctrl_ras_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_sc_enable&#34; is connected to &#34;io_ctrl_sc_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_tage_enable&#34; is connected to &#34;io_ctrl_tage_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_ubtb_enable&#34; is connected to &#34;io_ctrl_ubtb_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34;</span>
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+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_level&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_level&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured log setup</h5> <pre><samp><span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_btb_enable&#34; is connected to &#34;io_ctrl_btb_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_ras_enable&#34; is connected to &#34;io_ctrl_ras_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_sc_enable&#34; is connected to &#34;io_ctrl_sc_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_tage_enable&#34; is connected to &#34;io_ctrl_tage_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_ubtb_enable&#34; is connected to &#34;io_ctrl_ubtb_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_full_target&#34; is connected to &#34;io_ftq_to_bpu_update_bits_full_target&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34; is connected to &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_meta&#34; is connected to &#34;io_ftq_to_bpu_update_bits_meta&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_old_entry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_old_entry&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_level&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_level&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</samp></pre> </div> </div> </details> <details class="phase call passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Call</span> </h4> </summary> <div class=content> <div class=section> <h5 class=section-title>Captured stdout call</h5> <pre><samp>&lt;function mlvp_request.&lt;locals&gt;.start_code at 0x759cc153e9e0&gt;
+set_sub_predic_ctrl_en Begin exec
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+begin exec test_redirect_signals_sanity test
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+test_normal_sanity IS OVER
+1
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured stderr call</h5> <pre><samp><span class=ansi37>MLVP_INFO @logger.py:147:	Log Summary
+============
+* Report counts by severity
+INFO:	431
+</span>
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured log call</h5> <pre><samp><span class=ansi32>INFO    </span> MLVP:logger.py:147 Log Summary
+============
+* Report counts by severity
+INFO:	431</samp></pre> </div> </div> </details> <details class="phase teardown passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Teardown</span> </h4> </summary> <div class=content> </div> </details> </div> </div> </details> <details class="test passed"> <summary> <h3 class="title test-title"> <span class="status badge passed ">PASSED</span> <span class=test-name> <span class=funcname>test_normal_redirect_cfi_sanity</span> </span> <span class=duration>0:00:09.358788</span> </h3> </summary> <div class=content> <table class=metadata> <tr> <th>Started</th> <td>2024-10-27 20:19:55</td> </tr> <tr> <th>Ended</th> <td>2024-10-27 20:20:04</td> </tr> <tr> <th>Duration</th> <td>0:00:09.358788</td> </tr> <tr> <th>Markers</th> <td> <div class=marker> <span class="marker-name badge">mlvp_async</span> <span class=marker-args> </span> </div> </td> </tr> <tr> <th>Fixtures</th> <td> <span class="badge fixturename"> mlvp_request </span> <span class="badge fixturename"> mlvp_pre_request </span> <span class="badge fixturename"> request </span> </td> </tr> </table> <div class=test-phases> <details class="phase setup passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Setup</span> </h4> </summary> <div class=content> <div class=section> <h5 class=section-title>Captured stderr setup</h5> <pre><samp><span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_btb_enable&#34; is connected to &#34;io_ctrl_btb_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_ras_enable&#34; is connected to &#34;io_ctrl_ras_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_sc_enable&#34; is connected to &#34;io_ctrl_sc_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_tage_enable&#34; is connected to &#34;io_ctrl_tage_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_ubtb_enable&#34; is connected to &#34;io_ctrl_ubtb_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_full_target&#34; is connected to &#34;io_ftq_to_bpu_update_bits_full_target&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34; is connected to &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_meta&#34; is connected to &#34;io_ftq_to_bpu_update_bits_meta&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_old_entry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_old_entry&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_level&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_level&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured log setup</h5> <pre><samp><span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_btb_enable&#34; is connected to &#34;io_ctrl_btb_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_ras_enable&#34; is connected to &#34;io_ctrl_ras_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_sc_enable&#34; is connected to &#34;io_ctrl_sc_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_tage_enable&#34; is connected to &#34;io_ctrl_tage_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_ubtb_enable&#34; is connected to &#34;io_ctrl_ubtb_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_full_target&#34; is connected to &#34;io_ftq_to_bpu_update_bits_full_target&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34; is connected to &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_meta&#34; is connected to &#34;io_ftq_to_bpu_update_bits_meta&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_old_entry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_old_entry&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_level&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_level&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</samp></pre> </div> </div> </details> <details class="phase call passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Call</span> </h4> </summary> <div class=content> <div class=section> <h5 class=section-title>Captured stdout call</h5> <pre><samp>&lt;function mlvp_request.&lt;locals&gt;.start_code at 0x759cc153f490&gt;
+set_sub_predic_ctrl_en Begin exec
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+begin exec test_redirect_cfi_sanity test
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+test_normal_sanity IS OVER
+1
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured stderr call</h5> <pre><samp><span class=ansi37>MLVP_INFO @logger.py:147:	Log Summary
+============
+* Report counts by severity
+INFO:	575
+</span>
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured log call</h5> <pre><samp><span class=ansi32>INFO    </span> MLVP:logger.py:147 Log Summary
+============
+* Report counts by severity
+INFO:	575</samp></pre> </div> </div> </details> <details class="phase teardown passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Teardown</span> </h4> </summary> <div class=content> </div> </details> </div> </div> </details> <details class="test passed"> <summary> <h3 class="title test-title"> <span class="status badge passed ">PASSED</span> <span class=test-name> <span class=funcname>test_update_signals_sanity</span> </span> <span class=duration>0:00:08.759901</span> </h3> </summary> <div class=content> <table class=metadata> <tr> <th>Started</th> <td>2024-10-27 20:20:04</td> </tr> <tr> <th>Ended</th> <td>2024-10-27 20:20:13</td> </tr> <tr> <th>Duration</th> <td>0:00:08.759901</td> </tr> <tr> <th>Markers</th> <td> <div class=marker> <span class="marker-name badge">mlvp_async</span> <span class=marker-args> </span> </div> </td> </tr> <tr> <th>Fixtures</th> <td> <span class="badge fixturename"> mlvp_request </span> <span class="badge fixturename"> mlvp_pre_request </span> <span class="badge fixturename"> request </span> </td> </tr> </table> <div class=test-phases> <details class="phase setup passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Setup</span> </h4> </summary> <div class=content> <div class=section> <h5 class=section-title>Captured stderr setup</h5> <pre><samp><span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_btb_enable&#34; is connected to &#34;io_ctrl_btb_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_ras_enable&#34; is connected to &#34;io_ctrl_ras_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_sc_enable&#34; is connected to &#34;io_ctrl_sc_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_tage_enable&#34; is connected to &#34;io_ctrl_tage_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_ubtb_enable&#34; is connected to &#34;io_ctrl_ubtb_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_full_target&#34; is connected to &#34;io_ftq_to_bpu_update_bits_full_target&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34; is connected to &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_meta&#34; is connected to &#34;io_ftq_to_bpu_update_bits_meta&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_old_entry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_old_entry&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;</span>
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+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34;</span>
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+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
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+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34;</span>
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+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34;</span>
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+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34;</span>
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+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_level&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_level&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
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+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured log setup</h5> <pre><samp><span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_btb_enable&#34; is connected to &#34;io_ctrl_btb_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_ras_enable&#34; is connected to &#34;io_ctrl_ras_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_sc_enable&#34; is connected to &#34;io_ctrl_sc_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_tage_enable&#34; is connected to &#34;io_ctrl_tage_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_ubtb_enable&#34; is connected to &#34;io_ctrl_ubtb_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_full_target&#34; is connected to &#34;io_ftq_to_bpu_update_bits_full_target&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34; is connected to &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_meta&#34; is connected to &#34;io_ftq_to_bpu_update_bits_meta&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_old_entry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_old_entry&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_level&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_level&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</samp></pre> </div> </div> </details> <details class="phase call passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Call</span> </h4> </summary> <div class=content> <div class=section> <h5 class=section-title>Captured stdout call</h5> <pre><samp>&lt;function mlvp_request.&lt;locals&gt;.start_code at 0x759cc153ff40&gt;
+begin exec test_update_signals_sanity test
+test_update_signals_sanity IS OVER
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured stderr call</h5> <pre><samp><span class=ansi37>MLVP_INFO @logger.py:147:	Log Summary
+============
+* Report counts by severity
+INFO:	719
+</span>
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured log call</h5> <pre><samp><span class=ansi32>INFO    </span> MLVP:logger.py:147 Log Summary
+============
+* Report counts by severity
+INFO:	719</samp></pre> </div> </div> </details> <details class="phase teardown passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Teardown</span> </h4> </summary> <div class=content> </div> </details> </div> </div> </details> <details class="test passed"> <summary> <h3 class="title test-title"> <span class="status badge passed ">PASSED</span> <span class=test-name> <span class=funcname>test_update_fold_hist_sanity</span> </span> <span class=duration>0:00:09.724301</span> </h3> </summary> <div class=content> <table class=metadata> <tr> <th>Started</th> <td>2024-10-27 20:20:13</td> </tr> <tr> <th>Ended</th> <td>2024-10-27 20:20:22</td> </tr> <tr> <th>Duration</th> <td>0:00:09.724301</td> </tr> <tr> <th>Markers</th> <td> <div class=marker> <span class="marker-name badge">mlvp_async</span> <span class=marker-args> </span> </div> </td> </tr> <tr> <th>Fixtures</th> <td> <span class="badge fixturename"> mlvp_request </span> <span class="badge fixturename"> mlvp_pre_request </span> <span class="badge fixturename"> request </span> </td> </tr> </table> <div class=test-phases> <details class="phase setup passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Setup</span> </h4> </summary> <div class=content> <div class=section> <h5 class=section-title>Captured stderr setup</h5> <pre><samp><span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_btb_enable&#34; is connected to &#34;io_ctrl_btb_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_ras_enable&#34; is connected to &#34;io_ctrl_ras_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_sc_enable&#34; is connected to &#34;io_ctrl_sc_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_tage_enable&#34; is connected to &#34;io_ctrl_tage_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_ubtb_enable&#34; is connected to &#34;io_ctrl_ubtb_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34;</span>
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+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
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+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_level&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_level&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured log setup</h5> <pre><samp><span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_btb_enable&#34; is connected to &#34;io_ctrl_btb_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_ras_enable&#34; is connected to &#34;io_ctrl_ras_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_sc_enable&#34; is connected to &#34;io_ctrl_sc_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_tage_enable&#34; is connected to &#34;io_ctrl_tage_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_ubtb_enable&#34; is connected to &#34;io_ctrl_ubtb_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_full_target&#34; is connected to &#34;io_ftq_to_bpu_update_bits_full_target&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34; is connected to &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_meta&#34; is connected to &#34;io_ftq_to_bpu_update_bits_meta&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_old_entry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_old_entry&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_level&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_level&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</samp></pre> </div> </div> </details> <details class="phase call passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Call</span> </h4> </summary> <div class=content> <div class=section> <h5 class=section-title>Captured stdout call</h5> <pre><samp>&lt;function mlvp_request.&lt;locals&gt;.start_code at 0x759cc0634a60&gt;
+begin exec test_update_fold_hist_sanity test
+test_update_signals_sanity IS OVER
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured stderr call</h5> <pre><samp><span class=ansi37>MLVP_INFO @logger.py:147:	Log Summary
+============
+* Report counts by severity
+INFO:	863
+</span>
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured log call</h5> <pre><samp><span class=ansi32>INFO    </span> MLVP:logger.py:147 Log Summary
+============
+* Report counts by severity
+INFO:	863</samp></pre> </div> </div> </details> <details class="phase teardown passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Teardown</span> </h4> </summary> <div class=content> </div> </details> </div> </div> </details> <details class="test passed"> <summary> <h3 class="title test-title"> <span class="status badge passed ">PASSED</span> <span class=test-name> <span class=funcname>test_update_FtbEntry_foldHist_once_signals</span> </span> <span class=duration>0:00:08.642993</span> </h3> </summary> <div class=content> <table class=metadata> <tr> <th>Started</th> <td>2024-10-27 20:20:22</td> </tr> <tr> <th>Ended</th> <td>2024-10-27 20:20:31</td> </tr> <tr> <th>Duration</th> <td>0:00:08.642993</td> </tr> <tr> <th>Markers</th> <td> <div class=marker> <span class="marker-name badge">mlvp_async</span> <span class=marker-args> </span> </div> </td> </tr> <tr> <th>Fixtures</th> <td> <span class="badge fixturename"> mlvp_request </span> <span class="badge fixturename"> mlvp_pre_request </span> <span class="badge fixturename"> request </span> </td> </tr> </table> <div class=test-phases> <details class="phase setup passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Setup</span> </h4> </summary> <div class=content> <div class=section> <h5 class=section-title>Captured stderr setup</h5> <pre><samp><span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_btb_enable&#34; is connected to &#34;io_ctrl_btb_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_ras_enable&#34; is connected to &#34;io_ctrl_ras_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_sc_enable&#34; is connected to &#34;io_ctrl_sc_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_tage_enable&#34; is connected to &#34;io_ctrl_tage_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_ubtb_enable&#34; is connected to &#34;io_ctrl_ubtb_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_full_target&#34; is connected to &#34;io_ftq_to_bpu_update_bits_full_target&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34; is connected to &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_meta&#34; is connected to &#34;io_ftq_to_bpu_update_bits_meta&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_old_entry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_old_entry&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_level&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_level&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured log setup</h5> <pre><samp><span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_btb_enable&#34; is connected to &#34;io_ctrl_btb_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_ras_enable&#34; is connected to &#34;io_ctrl_ras_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_sc_enable&#34; is connected to &#34;io_ctrl_sc_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_tage_enable&#34; is connected to &#34;io_ctrl_tage_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_ubtb_enable&#34; is connected to &#34;io_ctrl_ubtb_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_full_target&#34; is connected to &#34;io_ftq_to_bpu_update_bits_full_target&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34; is connected to &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_meta&#34; is connected to &#34;io_ftq_to_bpu_update_bits_meta&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_old_entry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_old_entry&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_level&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_level&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</samp></pre> </div> </div> </details> <details class="phase call passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Call</span> </h4> </summary> <div class=content> <div class=section> <h5 class=section-title>Captured stdout call</h5> <pre><samp>&lt;function mlvp_request.&lt;locals&gt;.start_code at 0x759cc0635630&gt;
+begin exec test_update_fold_hist_sanity test
+test_update_signals_sanity IS OVER
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured stderr call</h5> <pre><samp><span class=ansi37>MLVP_INFO @logger.py:147:	Log Summary
+============
+* Report counts by severity
+INFO:	1007
+</span>
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured log call</h5> <pre><samp><span class=ansi32>INFO    </span> MLVP:logger.py:147 Log Summary
+============
+* Report counts by severity
+INFO:	1007</samp></pre> </div> </div> </details> <details class="phase teardown passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Teardown</span> </h4> </summary> <div class=content> </div> </details> </div> </div> </details> <details class="test passed"> <summary> <h3 class="title test-title"> <span class="status badge passed ">PASSED</span> <span class=test-name> <span class=funcname>test_update_FtbEntry_foldHist_twice_signals</span> </span> <span class=duration>0:00:08.948329</span> </h3> </summary> <div class=content> <table class=metadata> <tr> <th>Started</th> <td>2024-10-27 20:20:31</td> </tr> <tr> <th>Ended</th> <td>2024-10-27 20:20:40</td> </tr> <tr> <th>Duration</th> <td>0:00:08.948329</td> </tr> <tr> <th>Markers</th> <td> <div class=marker> <span class="marker-name badge">mlvp_async</span> <span class=marker-args> </span> </div> </td> </tr> <tr> <th>Fixtures</th> <td> <span class="badge fixturename"> mlvp_request </span> <span class="badge fixturename"> mlvp_pre_request </span> <span class="badge fixturename"> request </span> </td> </tr> </table> <div class=test-phases> <details class="phase setup passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Setup</span> </h4> </summary> <div class=content> <div class=section> <h5 class=section-title>Captured stderr setup</h5> <pre><samp><span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_btb_enable&#34; is connected to &#34;io_ctrl_btb_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_ras_enable&#34; is connected to &#34;io_ctrl_ras_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_sc_enable&#34; is connected to &#34;io_ctrl_sc_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_tage_enable&#34; is connected to &#34;io_ctrl_tage_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_ubtb_enable&#34; is connected to &#34;io_ctrl_ubtb_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_full_target&#34; is connected to &#34;io_ftq_to_bpu_update_bits_full_target&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34; is connected to &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_meta&#34; is connected to &#34;io_ftq_to_bpu_update_bits_meta&#34;</span>
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+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_level&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_level&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured log setup</h5> <pre><samp><span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_btb_enable&#34; is connected to &#34;io_ctrl_btb_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_ras_enable&#34; is connected to &#34;io_ctrl_ras_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_sc_enable&#34; is connected to &#34;io_ctrl_sc_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_tage_enable&#34; is connected to &#34;io_ctrl_tage_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_ubtb_enable&#34; is connected to &#34;io_ctrl_ubtb_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_full_target&#34; is connected to &#34;io_ftq_to_bpu_update_bits_full_target&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34; is connected to &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_meta&#34; is connected to &#34;io_ftq_to_bpu_update_bits_meta&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_old_entry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_old_entry&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_level&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_level&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</samp></pre> </div> </div> </details> <details class="phase call passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Call</span> </h4> </summary> <div class=content> <div class=section> <h5 class=section-title>Captured stdout call</h5> <pre><samp>&lt;function mlvp_request.&lt;locals&gt;.start_code at 0x759cc0636170&gt;
+begin exec test_update_fold_hist_sanity test
+test_update_signals_sanity IS OVER
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured stderr call</h5> <pre><samp><span class=ansi37>MLVP_INFO @logger.py:147:	Log Summary
+============
+* Report counts by severity
+INFO:	1151
+</span>
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured log call</h5> <pre><samp><span class=ansi32>INFO    </span> MLVP:logger.py:147 Log Summary
+============
+* Report counts by severity
+INFO:	1151</samp></pre> </div> </div> </details> <details class="phase teardown passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Teardown</span> </h4> </summary> <div class=content> </div> </details> </div> </div> </details> <details class="test passed"> <summary> <h3 class="title test-title"> <span class="status badge passed ">PASSED</span> <span class=test-name> <span class=funcname>test_sub_predi_all_enable_reset</span> </span> <span class=duration>0:00:09.939243</span> </h3> </summary> <div class=content> <table class=metadata> <tr> <th>Started</th> <td>2024-10-27 20:20:40</td> </tr> <tr> <th>Ended</th> <td>2024-10-27 20:20:50</td> </tr> <tr> <th>Duration</th> <td>0:00:09.939243</td> </tr> <tr> <th>Markers</th> <td> <div class=marker> <span class="marker-name badge">mlvp_async</span> <span class=marker-args> </span> </div> </td> </tr> <tr> <th>Fixtures</th> <td> <span class="badge fixturename"> mlvp_request </span> <span class="badge fixturename"> mlvp_pre_request </span> <span class="badge fixturename"> request </span> </td> </tr> </table> <div class=test-phases> <details class="phase setup passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Setup</span> </h4> </summary> <div class=content> <div class=section> <h5 class=section-title>Captured stderr setup</h5> <pre><samp><span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_btb_enable&#34; is connected to &#34;io_ctrl_btb_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_ras_enable&#34; is connected to &#34;io_ctrl_ras_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_sc_enable&#34; is connected to &#34;io_ctrl_sc_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_tage_enable&#34; is connected to &#34;io_ctrl_tage_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_ubtb_enable&#34; is connected to &#34;io_ctrl_ubtb_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
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+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
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+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34;</span>
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+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34;</span>
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+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34;</span>
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+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34;</span>
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+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_level&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_level&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured log setup</h5> <pre><samp><span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_btb_enable&#34; is connected to &#34;io_ctrl_btb_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_ras_enable&#34; is connected to &#34;io_ctrl_ras_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_sc_enable&#34; is connected to &#34;io_ctrl_sc_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_tage_enable&#34; is connected to &#34;io_ctrl_tage_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_ubtb_enable&#34; is connected to &#34;io_ctrl_ubtb_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_full_target&#34; is connected to &#34;io_ftq_to_bpu_update_bits_full_target&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34; is connected to &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_meta&#34; is connected to &#34;io_ftq_to_bpu_update_bits_meta&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_old_entry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_old_entry&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_level&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_level&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</samp></pre> </div> </div> </details> <details class="phase call passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Call</span> </h4> </summary> <div class=content> <div class=section> <h5 class=section-title>Captured stdout call</h5> <pre><samp>&lt;function mlvp_request.&lt;locals&gt;.start_code at 0x759cc0636b90&gt;
+begin exec env test
+set_sub_predic_ctrl_en Begin exec
+1
+test_sub_predi_all_enable Is Over!!!!!!!!!!!!!!!!!!!!!!!
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+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured stderr call</h5> <pre><samp><span class=ansi37>MLVP_INFO @logger.py:147:	Log Summary
+============
+* Report counts by severity
+INFO:	1295
+</span>
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured log call</h5> <pre><samp><span class=ansi32>INFO    </span> MLVP:logger.py:147 Log Summary
+============
+* Report counts by severity
+INFO:	1295</samp></pre> </div> </div> </details> <details class="phase teardown passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Teardown</span> </h4> </summary> <div class=content> </div> </details> </div> </div> </details> <details class="test passed"> <summary> <h3 class="title test-title"> <span class="status badge passed ">PASSED</span> <span class=test-name> <span class=funcname>test_sub_predi_UFTB_disable</span> </span> <span class=duration>0:00:09.261189</span> </h3> </summary> <div class=content> <table class=metadata> <tr> <th>Started</th> <td>2024-10-27 20:20:50</td> </tr> <tr> <th>Ended</th> <td>2024-10-27 20:20:59</td> </tr> <tr> <th>Duration</th> <td>0:00:09.261189</td> </tr> <tr> <th>Markers</th> <td> <div class=marker> <span class="marker-name badge">mlvp_async</span> <span class=marker-args> </span> </div> </td> </tr> <tr> <th>Fixtures</th> <td> <span class="badge fixturename"> mlvp_request </span> <span class="badge fixturename"> mlvp_pre_request </span> <span class="badge fixturename"> request </span> </td> </tr> </table> <div class=test-phases> <details class="phase setup passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Setup</span> </h4> </summary> <div class=content> <div class=section> <h5 class=section-title>Captured stderr setup</h5> <pre><samp><span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_btb_enable&#34; is connected to &#34;io_ctrl_btb_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_ras_enable&#34; is connected to &#34;io_ctrl_ras_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_sc_enable&#34; is connected to &#34;io_ctrl_sc_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_tage_enable&#34; is connected to &#34;io_ctrl_tage_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_ubtb_enable&#34; is connected to &#34;io_ctrl_ubtb_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_full_target&#34; is connected to &#34;io_ftq_to_bpu_update_bits_full_target&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34; is connected to &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_meta&#34; is connected to &#34;io_ftq_to_bpu_update_bits_meta&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_old_entry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_old_entry&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_level&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_level&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured log setup</h5> <pre><samp><span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_btb_enable&#34; is connected to &#34;io_ctrl_btb_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_ras_enable&#34; is connected to &#34;io_ctrl_ras_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_sc_enable&#34; is connected to &#34;io_ctrl_sc_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_tage_enable&#34; is connected to &#34;io_ctrl_tage_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_ubtb_enable&#34; is connected to &#34;io_ctrl_ubtb_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_full_target&#34; is connected to &#34;io_ftq_to_bpu_update_bits_full_target&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34; is connected to &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_meta&#34; is connected to &#34;io_ftq_to_bpu_update_bits_meta&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_old_entry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_old_entry&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_level&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_level&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</samp></pre> </div> </div> </details> <details class="phase call passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Call</span> </h4> </summary> <div class=content> <div class=section> <h5 class=section-title>Captured stdout call</h5> <pre><samp>&lt;function mlvp_request.&lt;locals&gt;.start_code at 0x759cc0637640&gt;
+begin exec test
+set_sub_predic_ctrl_en Begin exec
+test_sub_predi_uftb_enable Is Over!!!!!!!!!!!!!!!!!!!!!!!
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured stderr call</h5> <pre><samp><span class=ansi37>MLVP_INFO @logger.py:147:	Log Summary
+============
+* Report counts by severity
+INFO:	1439
+</span>
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured log call</h5> <pre><samp><span class=ansi32>INFO    </span> MLVP:logger.py:147 Log Summary
+============
+* Report counts by severity
+INFO:	1439</samp></pre> </div> </div> </details> <details class="phase teardown passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Teardown</span> </h4> </summary> <div class=content> </div> </details> </div> </div> </details> <details class="test passed"> <summary> <h3 class="title test-title"> <span class="status badge passed ">PASSED</span> <span class=test-name> <span class=funcname>test_sub_predi_FTB_disable</span> </span> <span class=duration>0:00:09.499094</span> </h3> </summary> <div class=content> <table class=metadata> <tr> <th>Started</th> <td>2024-10-27 20:20:59</td> </tr> <tr> <th>Ended</th> <td>2024-10-27 20:21:09</td> </tr> <tr> <th>Duration</th> <td>0:00:09.499094</td> </tr> <tr> <th>Markers</th> <td> <div class=marker> <span class="marker-name badge">mlvp_async</span> <span class=marker-args> </span> </div> </td> </tr> <tr> <th>Fixtures</th> <td> <span class="badge fixturename"> mlvp_request </span> <span class="badge fixturename"> mlvp_pre_request </span> <span class="badge fixturename"> request </span> </td> </tr> </table> <div class=test-phases> <details class="phase setup passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Setup</span> </h4> </summary> <div class=content> <div class=section> <h5 class=section-title>Captured stderr setup</h5> <pre><samp><span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_btb_enable&#34; is connected to &#34;io_ctrl_btb_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_ras_enable&#34; is connected to &#34;io_ctrl_ras_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_sc_enable&#34; is connected to &#34;io_ctrl_sc_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_tage_enable&#34; is connected to &#34;io_ctrl_tage_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_ubtb_enable&#34; is connected to &#34;io_ctrl_ubtb_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;</span>
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+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_level&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_level&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured log setup</h5> <pre><samp><span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_btb_enable&#34; is connected to &#34;io_ctrl_btb_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_ras_enable&#34; is connected to &#34;io_ctrl_ras_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_sc_enable&#34; is connected to &#34;io_ctrl_sc_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_tage_enable&#34; is connected to &#34;io_ctrl_tage_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_ubtb_enable&#34; is connected to &#34;io_ctrl_ubtb_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_full_target&#34; is connected to &#34;io_ftq_to_bpu_update_bits_full_target&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34; is connected to &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_meta&#34; is connected to &#34;io_ftq_to_bpu_update_bits_meta&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_old_entry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_old_entry&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_level&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_level&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</samp></pre> </div> </div> </details> <details class="phase call passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Call</span> </h4> </summary> <div class=content> <div class=section> <h5 class=section-title>Captured stdout call</h5> <pre><samp>&lt;function mlvp_request.&lt;locals&gt;.start_code at 0x759cc05cc160&gt;
+set_sub_predic_ctrl_en Begin exec
+1
+test_sub_predi_uftb_enable Is Over!!!!!!!!!!!!!!!!!!!!!!!
+1
+1
+1
+1
+1
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+1
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+1
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+1
+1
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+1
+1
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+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured stderr call</h5> <pre><samp><span class=ansi37>MLVP_INFO @logger.py:147:	Log Summary
+============
+* Report counts by severity
+INFO:	1583
+</span>
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured log call</h5> <pre><samp><span class=ansi32>INFO    </span> MLVP:logger.py:147 Log Summary
+============
+* Report counts by severity
+INFO:	1583</samp></pre> </div> </div> </details> <details class="phase teardown passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Teardown</span> </h4> </summary> <div class=content> </div> </details> </div> </div> </details> <details class="test passed"> <summary> <h3 class="title test-title"> <span class="status badge passed ">PASSED</span> <span class=test-name> <span class=funcname>test_sub_predi_TAGE_disable</span> </span> <span class=duration>0:00:09.249898</span> </h3> </summary> <div class=content> <table class=metadata> <tr> <th>Started</th> <td>2024-10-27 20:21:09</td> </tr> <tr> <th>Ended</th> <td>2024-10-27 20:21:18</td> </tr> <tr> <th>Duration</th> <td>0:00:09.249898</td> </tr> <tr> <th>Markers</th> <td> <div class=marker> <span class="marker-name badge">mlvp_async</span> <span class=marker-args> </span> </div> </td> </tr> <tr> <th>Fixtures</th> <td> <span class="badge fixturename"> mlvp_request </span> <span class="badge fixturename"> mlvp_pre_request </span> <span class="badge fixturename"> request </span> </td> </tr> </table> <div class=test-phases> <details class="phase setup passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Setup</span> </h4> </summary> <div class=content> <div class=section> <h5 class=section-title>Captured stderr setup</h5> <pre><samp><span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_btb_enable&#34; is connected to &#34;io_ctrl_btb_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_ras_enable&#34; is connected to &#34;io_ctrl_ras_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_sc_enable&#34; is connected to &#34;io_ctrl_sc_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_tage_enable&#34; is connected to &#34;io_ctrl_tage_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_ubtb_enable&#34; is connected to &#34;io_ctrl_ubtb_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_full_target&#34; is connected to &#34;io_ftq_to_bpu_update_bits_full_target&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34; is connected to &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_meta&#34; is connected to &#34;io_ftq_to_bpu_update_bits_meta&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_old_entry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_old_entry&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_level&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_level&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured log setup</h5> <pre><samp><span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_btb_enable&#34; is connected to &#34;io_ctrl_btb_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_ras_enable&#34; is connected to &#34;io_ctrl_ras_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_sc_enable&#34; is connected to &#34;io_ctrl_sc_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_tage_enable&#34; is connected to &#34;io_ctrl_tage_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_ubtb_enable&#34; is connected to &#34;io_ctrl_ubtb_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_full_target&#34; is connected to &#34;io_ftq_to_bpu_update_bits_full_target&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34; is connected to &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_meta&#34; is connected to &#34;io_ftq_to_bpu_update_bits_meta&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_old_entry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_old_entry&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_level&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_level&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</samp></pre> </div> </div> </details> <details class="phase call passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Call</span> </h4> </summary> <div class=content> <div class=section> <h5 class=section-title>Captured stdout call</h5> <pre><samp>&lt;function mlvp_request.&lt;locals&gt;.start_code at 0x759cc05ccc10&gt;
+set_sub_predic_ctrl_en Begin exec
+1
+test_sub_predi_uftb_enable Is Over!!!!!!!!!!!!!!!!!!!!!!!
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+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured stderr call</h5> <pre><samp><span class=ansi37>MLVP_INFO @logger.py:147:	Log Summary
+============
+* Report counts by severity
+INFO:	1727
+</span>
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured log call</h5> <pre><samp><span class=ansi32>INFO    </span> MLVP:logger.py:147 Log Summary
+============
+* Report counts by severity
+INFO:	1727</samp></pre> </div> </div> </details> <details class="phase teardown passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Teardown</span> </h4> </summary> <div class=content> </div> </details> </div> </div> </details> <details class="test passed"> <summary> <h3 class="title test-title"> <span class="status badge passed ">PASSED</span> <span class=test-name> <span class=funcname>test_sub_predi_SC_disable</span> </span> <span class=duration>0:00:10.285772</span> </h3> </summary> <div class=content> <table class=metadata> <tr> <th>Started</th> <td>2024-10-27 20:21:18</td> </tr> <tr> <th>Ended</th> <td>2024-10-27 20:21:28</td> </tr> <tr> <th>Duration</th> <td>0:00:10.285772</td> </tr> <tr> <th>Markers</th> <td> <div class=marker> <span class="marker-name badge">mlvp_async</span> <span class=marker-args> </span> </div> </td> </tr> <tr> <th>Fixtures</th> <td> <span class="badge fixturename"> mlvp_request </span> <span class="badge fixturename"> mlvp_pre_request </span> <span class="badge fixturename"> request </span> </td> </tr> </table> <div class=test-phases> <details class="phase setup passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Setup</span> </h4> </summary> <div class=content> <div class=section> <h5 class=section-title>Captured stderr setup</h5> <pre><samp><span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_btb_enable&#34; is connected to &#34;io_ctrl_btb_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_ras_enable&#34; is connected to &#34;io_ctrl_ras_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_sc_enable&#34; is connected to &#34;io_ctrl_sc_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_tage_enable&#34; is connected to &#34;io_ctrl_tage_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_ubtb_enable&#34; is connected to &#34;io_ctrl_ubtb_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_full_target&#34; is connected to &#34;io_ftq_to_bpu_update_bits_full_target&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34; is connected to &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_meta&#34; is connected to &#34;io_ftq_to_bpu_update_bits_meta&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_old_entry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_old_entry&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
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+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
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+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_level&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_level&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured log setup</h5> <pre><samp><span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_btb_enable&#34; is connected to &#34;io_ctrl_btb_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_ras_enable&#34; is connected to &#34;io_ctrl_ras_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_sc_enable&#34; is connected to &#34;io_ctrl_sc_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_tage_enable&#34; is connected to &#34;io_ctrl_tage_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_ubtb_enable&#34; is connected to &#34;io_ctrl_ubtb_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_full_target&#34; is connected to &#34;io_ftq_to_bpu_update_bits_full_target&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34; is connected to &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_meta&#34; is connected to &#34;io_ftq_to_bpu_update_bits_meta&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_old_entry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_old_entry&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_level&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_level&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</samp></pre> </div> </div> </details> <details class="phase call passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Call</span> </h4> </summary> <div class=content> <div class=section> <h5 class=section-title>Captured stdout call</h5> <pre><samp>&lt;function mlvp_request.&lt;locals&gt;.start_code at 0x759cc05cd6c0&gt;
+set_sub_predic_ctrl_en Begin exec
+1
+test_sub_predi_uftb_enable Is Over!!!!!!!!!!!!!!!!!!!!!!!
+1
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+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured stderr call</h5> <pre><samp><span class=ansi37>MLVP_INFO @logger.py:147:	Log Summary
+============
+* Report counts by severity
+INFO:	1871
+</span>
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured log call</h5> <pre><samp><span class=ansi32>INFO    </span> MLVP:logger.py:147 Log Summary
+============
+* Report counts by severity
+INFO:	1871</samp></pre> </div> </div> </details> <details class="phase teardown passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Teardown</span> </h4> </summary> <div class=content> </div> </details> </div> </div> </details> <details class="test passed"> <summary> <h3 class="title test-title"> <span class="status badge passed ">PASSED</span> <span class=test-name> <span class=funcname>test_sub_predi_RAS_disable</span> </span> <span class=duration>0:00:09.578681</span> </h3> </summary> <div class=content> <table class=metadata> <tr> <th>Started</th> <td>2024-10-27 20:21:28</td> </tr> <tr> <th>Ended</th> <td>2024-10-27 20:21:38</td> </tr> <tr> <th>Duration</th> <td>0:00:09.578681</td> </tr> <tr> <th>Markers</th> <td> <div class=marker> <span class="marker-name badge">mlvp_async</span> <span class=marker-args> </span> </div> </td> </tr> <tr> <th>Fixtures</th> <td> <span class="badge fixturename"> mlvp_request </span> <span class="badge fixturename"> mlvp_pre_request </span> <span class="badge fixturename"> request </span> </td> </tr> </table> <div class=test-phases> <details class="phase setup passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Setup</span> </h4> </summary> <div class=content> <div class=section> <h5 class=section-title>Captured stderr setup</h5> <pre><samp><span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_btb_enable&#34; is connected to &#34;io_ctrl_btb_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_ras_enable&#34; is connected to &#34;io_ctrl_ras_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_sc_enable&#34; is connected to &#34;io_ctrl_sc_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_tage_enable&#34; is connected to &#34;io_ctrl_tage_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_ubtb_enable&#34; is connected to &#34;io_ctrl_ubtb_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
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+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34;</span>
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+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34;</span>
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+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34;</span>
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+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
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+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34;</span>
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+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34;</span>
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+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34;</span>
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+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_level&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_level&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured log setup</h5> <pre><samp><span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_btb_enable&#34; is connected to &#34;io_ctrl_btb_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_ras_enable&#34; is connected to &#34;io_ctrl_ras_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_sc_enable&#34; is connected to &#34;io_ctrl_sc_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_tage_enable&#34; is connected to &#34;io_ctrl_tage_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_ubtb_enable&#34; is connected to &#34;io_ctrl_ubtb_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_full_target&#34; is connected to &#34;io_ftq_to_bpu_update_bits_full_target&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34; is connected to &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_meta&#34; is connected to &#34;io_ftq_to_bpu_update_bits_meta&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_old_entry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_old_entry&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_level&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_level&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</samp></pre> </div> </div> </details> <details class="phase call passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Call</span> </h4> </summary> <div class=content> <div class=section> <h5 class=section-title>Captured stdout call</h5> <pre><samp>&lt;function mlvp_request.&lt;locals&gt;.start_code at 0x759cc05ce170&gt;
+set_sub_predic_ctrl_en Begin exec
+1
+test_sub_predi_uftb_enable Is Over!!!!!!!!!!!!!!!!!!!!!!!
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+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured stderr call</h5> <pre><samp><span class=ansi37>MLVP_INFO @logger.py:147:	Log Summary
+============
+* Report counts by severity
+INFO:	2015
+</span>
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured log call</h5> <pre><samp><span class=ansi32>INFO    </span> MLVP:logger.py:147 Log Summary
+============
+* Report counts by severity
+INFO:	2015</samp></pre> </div> </div> </details> <details class="phase teardown passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Teardown</span> </h4> </summary> <div class=content> </div> </details> </div> </div> </details> <details class="test passed"> <summary> <h3 class="title test-title"> <span class="status badge passed ">PASSED</span> <span class=test-name> <span class=funcname>test_normal_redirect_cfi_twice</span> </span> <span class=duration>0:00:08.796561</span> </h3> </summary> <div class=content> <table class=metadata> <tr> <th>Started</th> <td>2024-10-27 20:21:38</td> </tr> <tr> <th>Ended</th> <td>2024-10-27 20:21:47</td> </tr> <tr> <th>Duration</th> <td>0:00:08.796561</td> </tr> <tr> <th>Markers</th> <td> <div class=marker> <span class="marker-name badge">mlvp_async</span> <span class=marker-args> </span> </div> </td> </tr> <tr> <th>Fixtures</th> <td> <span class="badge fixturename"> mlvp_request </span> <span class="badge fixturename"> mlvp_pre_request </span> <span class="badge fixturename"> request </span> </td> </tr> </table> <div class=test-phases> <details class="phase setup passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Setup</span> </h4> </summary> <div class=content> <div class=section> <h5 class=section-title>Captured stderr setup</h5> <pre><samp><span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_btb_enable&#34; is connected to &#34;io_ctrl_btb_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_ras_enable&#34; is connected to &#34;io_ctrl_ras_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_sc_enable&#34; is connected to &#34;io_ctrl_sc_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_tage_enable&#34; is connected to &#34;io_ctrl_tage_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_ubtb_enable&#34; is connected to &#34;io_ctrl_ubtb_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_full_target&#34; is connected to &#34;io_ftq_to_bpu_update_bits_full_target&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34; is connected to &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_meta&#34; is connected to &#34;io_ftq_to_bpu_update_bits_meta&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_old_entry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_old_entry&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34;</span>
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+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
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+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34;</span>
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+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34;</span>
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+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34;</span>
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+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_level&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_level&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
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+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured log setup</h5> <pre><samp><span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_btb_enable&#34; is connected to &#34;io_ctrl_btb_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_ras_enable&#34; is connected to &#34;io_ctrl_ras_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_sc_enable&#34; is connected to &#34;io_ctrl_sc_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_tage_enable&#34; is connected to &#34;io_ctrl_tage_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_ubtb_enable&#34; is connected to &#34;io_ctrl_ubtb_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_full_target&#34; is connected to &#34;io_ftq_to_bpu_update_bits_full_target&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34; is connected to &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_meta&#34; is connected to &#34;io_ftq_to_bpu_update_bits_meta&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_old_entry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_old_entry&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_level&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_level&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</samp></pre> </div> </div> </details> <details class="phase call passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Call</span> </h4> </summary> <div class=content> <div class=section> <h5 class=section-title>Captured stdout call</h5> <pre><samp>&lt;function mlvp_request.&lt;locals&gt;.start_code at 0x759cc05cec20&gt;
+begin exec test_redirect_cfi_sanity test
+test_normal_sanity IS OVER
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured stderr call</h5> <pre><samp><span class=ansi37>MLVP_INFO @logger.py:147:	Log Summary
+============
+* Report counts by severity
+INFO:	2159
+</span>
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured log call</h5> <pre><samp><span class=ansi32>INFO    </span> MLVP:logger.py:147 Log Summary
+============
+* Report counts by severity
+INFO:	2159</samp></pre> </div> </div> </details> <details class="phase teardown passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Teardown</span> </h4> </summary> <div class=content> </div> </details> </div> </div> </details> <details class="test passed"> <summary> <h3 class="title test-title"> <span class="status badge passed ">PASSED</span> <span class=test-name> <span class=funcname>test_normal_redirect_cfi_twice_1</span> </span> <span class=duration>0:00:09.505974</span> </h3> </summary> <div class=content> <table class=metadata> <tr> <th>Started</th> <td>2024-10-27 20:21:47</td> </tr> <tr> <th>Ended</th> <td>2024-10-27 20:21:56</td> </tr> <tr> <th>Duration</th> <td>0:00:09.505974</td> </tr> <tr> <th>Markers</th> <td> <div class=marker> <span class="marker-name badge">mlvp_async</span> <span class=marker-args> </span> </div> </td> </tr> <tr> <th>Fixtures</th> <td> <span class="badge fixturename"> mlvp_request </span> <span class="badge fixturename"> mlvp_pre_request </span> <span class="badge fixturename"> request </span> </td> </tr> </table> <div class=test-phases> <details class="phase setup passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Setup</span> </h4> </summary> <div class=content> <div class=section> <h5 class=section-title>Captured stderr setup</h5> <pre><samp><span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_btb_enable&#34; is connected to &#34;io_ctrl_btb_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_ras_enable&#34; is connected to &#34;io_ctrl_ras_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_sc_enable&#34; is connected to &#34;io_ctrl_sc_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_tage_enable&#34; is connected to &#34;io_ctrl_tage_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_ubtb_enable&#34; is connected to &#34;io_ctrl_ubtb_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34;</span>
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+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_level&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_level&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured log setup</h5> <pre><samp><span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_btb_enable&#34; is connected to &#34;io_ctrl_btb_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_ras_enable&#34; is connected to &#34;io_ctrl_ras_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_sc_enable&#34; is connected to &#34;io_ctrl_sc_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_tage_enable&#34; is connected to &#34;io_ctrl_tage_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_ubtb_enable&#34; is connected to &#34;io_ctrl_ubtb_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_full_target&#34; is connected to &#34;io_ftq_to_bpu_update_bits_full_target&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34; is connected to &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_meta&#34; is connected to &#34;io_ftq_to_bpu_update_bits_meta&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_old_entry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_old_entry&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_level&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_level&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</samp></pre> </div> </div> </details> <details class="phase call passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Call</span> </h4> </summary> <div class=content> <div class=section> <h5 class=section-title>Captured stdout call</h5> <pre><samp>&lt;function mlvp_request.&lt;locals&gt;.start_code at 0x759cc05cf6d0&gt;
+set_sub_predic_ctrl_en Begin exec
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+begin exec test_redirect_cfi_sanity test
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+test_normal_sanity IS OVER
+1
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured stderr call</h5> <pre><samp><span class=ansi37>MLVP_INFO @logger.py:147:	Log Summary
+============
+* Report counts by severity
+INFO:	2303
+</span>
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured log call</h5> <pre><samp><span class=ansi32>INFO    </span> MLVP:logger.py:147 Log Summary
+============
+* Report counts by severity
+INFO:	2303</samp></pre> </div> </div> </details> <details class="phase teardown passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Teardown</span> </h4> </summary> <div class=content> </div> </details> </div> </div> </details> <details class="test passed"> <summary> <h3 class="title test-title"> <span class="status badge passed ">PASSED</span> <span class=test-name> <span class=funcname>test_normal_redirect_cfi_twice_2</span> </span> <span class=duration>0:00:10.462607</span> </h3> </summary> <div class=content> <table class=metadata> <tr> <th>Started</th> <td>2024-10-27 20:21:56</td> </tr> <tr> <th>Ended</th> <td>2024-10-27 20:22:07</td> </tr> <tr> <th>Duration</th> <td>0:00:10.462607</td> </tr> <tr> <th>Markers</th> <td> <div class=marker> <span class="marker-name badge">mlvp_async</span> <span class=marker-args> </span> </div> </td> </tr> <tr> <th>Fixtures</th> <td> <span class="badge fixturename"> mlvp_request </span> <span class="badge fixturename"> mlvp_pre_request </span> <span class="badge fixturename"> request </span> </td> </tr> </table> <div class=test-phases> <details class="phase setup passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Setup</span> </h4> </summary> <div class=content> <div class=section> <h5 class=section-title>Captured stderr setup</h5> <pre><samp><span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_btb_enable&#34; is connected to &#34;io_ctrl_btb_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_ras_enable&#34; is connected to &#34;io_ctrl_ras_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_sc_enable&#34; is connected to &#34;io_ctrl_sc_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_tage_enable&#34; is connected to &#34;io_ctrl_tage_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_ubtb_enable&#34; is connected to &#34;io_ctrl_ubtb_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_full_target&#34; is connected to &#34;io_ftq_to_bpu_update_bits_full_target&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34; is connected to &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_meta&#34; is connected to &#34;io_ftq_to_bpu_update_bits_meta&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_old_entry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_old_entry&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_level&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_level&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured log setup</h5> <pre><samp><span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_btb_enable&#34; is connected to &#34;io_ctrl_btb_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_ras_enable&#34; is connected to &#34;io_ctrl_ras_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_sc_enable&#34; is connected to &#34;io_ctrl_sc_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_tage_enable&#34; is connected to &#34;io_ctrl_tage_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_ubtb_enable&#34; is connected to &#34;io_ctrl_ubtb_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_full_target&#34; is connected to &#34;io_ftq_to_bpu_update_bits_full_target&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34; is connected to &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_meta&#34; is connected to &#34;io_ftq_to_bpu_update_bits_meta&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_old_entry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_old_entry&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_level&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_level&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</samp></pre> </div> </div> </details> <details class="phase call passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Call</span> </h4> </summary> <div class=content> <div class=section> <h5 class=section-title>Captured stdout call</h5> <pre><samp>&lt;function mlvp_request.&lt;locals&gt;.start_code at 0x759cc00101f0&gt;
+set_sub_predic_ctrl_en Begin exec
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+begin exec test_redirect_cfi_sanity test
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+test_normal_sanity IS OVER
+1
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured stderr call</h5> <pre><samp><span class=ansi37>MLVP_INFO @logger.py:147:	Log Summary
+============
+* Report counts by severity
+INFO:	2447
+</span>
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured log call</h5> <pre><samp><span class=ansi32>INFO    </span> MLVP:logger.py:147 Log Summary
+============
+* Report counts by severity
+INFO:	2447</samp></pre> </div> </div> </details> <details class="phase teardown passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Teardown</span> </h4> </summary> <div class=content> </div> </details> </div> </div> </details> <details class="test passed"> <summary> <h3 class="title test-title"> <span class="status badge passed ">PASSED</span> <span class=test-name> <span class=funcname>test_normal_redirect_cfi_twice_3</span> </span> <span class=duration>0:00:09.440641</span> </h3> </summary> <div class=content> <table class=metadata> <tr> <th>Started</th> <td>2024-10-27 20:22:07</td> </tr> <tr> <th>Ended</th> <td>2024-10-27 20:22:16</td> </tr> <tr> <th>Duration</th> <td>0:00:09.440641</td> </tr> <tr> <th>Markers</th> <td> <div class=marker> <span class="marker-name badge">mlvp_async</span> <span class=marker-args> </span> </div> </td> </tr> <tr> <th>Fixtures</th> <td> <span class="badge fixturename"> mlvp_request </span> <span class="badge fixturename"> mlvp_pre_request </span> <span class="badge fixturename"> request </span> </td> </tr> </table> <div class=test-phases> <details class="phase setup passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Setup</span> </h4> </summary> <div class=content> <div class=section> <h5 class=section-title>Captured stderr setup</h5> <pre><samp><span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_btb_enable&#34; is connected to &#34;io_ctrl_btb_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_ras_enable&#34; is connected to &#34;io_ctrl_ras_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_sc_enable&#34; is connected to &#34;io_ctrl_sc_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_tage_enable&#34; is connected to &#34;io_ctrl_tage_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_ubtb_enable&#34; is connected to &#34;io_ctrl_ubtb_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34;</span>
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+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_level&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_level&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured log setup</h5> <pre><samp><span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_btb_enable&#34; is connected to &#34;io_ctrl_btb_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_ras_enable&#34; is connected to &#34;io_ctrl_ras_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_sc_enable&#34; is connected to &#34;io_ctrl_sc_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_tage_enable&#34; is connected to &#34;io_ctrl_tage_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_ubtb_enable&#34; is connected to &#34;io_ctrl_ubtb_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_full_target&#34; is connected to &#34;io_ftq_to_bpu_update_bits_full_target&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34; is connected to &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_meta&#34; is connected to &#34;io_ftq_to_bpu_update_bits_meta&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_old_entry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_old_entry&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_level&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_level&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</samp></pre> </div> </div> </details> <details class="phase call passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Call</span> </h4> </summary> <div class=content> <div class=section> <h5 class=section-title>Captured stdout call</h5> <pre><samp>&lt;function mlvp_request.&lt;locals&gt;.start_code at 0x759cc0010ca0&gt;
+set_sub_predic_ctrl_en Begin exec
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+begin exec test_redirect_cfi_sanity test
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+1
+1
+1
+1
+1
+1
+1
+1
+1
+1
+test_normal_sanity IS OVER
+1
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured stderr call</h5> <pre><samp><span class=ansi37>MLVP_INFO @logger.py:147:	Log Summary
+============
+* Report counts by severity
+INFO:	2591
+</span>
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured log call</h5> <pre><samp><span class=ansi32>INFO    </span> MLVP:logger.py:147 Log Summary
+============
+* Report counts by severity
+INFO:	2591</samp></pre> </div> </div> </details> <details class="phase teardown passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Teardown</span> </h4> </summary> <div class=content> </div> </details> </div> </div> </details> <details class="test passed"> <summary> <h3 class="title test-title"> <span class="status badge passed ">PASSED</span> <span class=test-name> <span class=funcname>test_normal_redirect_cfi_twice_4</span> </span> <span class=duration>0:00:10.002389</span> </h3> </summary> <div class=content> <table class=metadata> <tr> <th>Started</th> <td>2024-10-27 20:22:16</td> </tr> <tr> <th>Ended</th> <td>2024-10-27 20:22:26</td> </tr> <tr> <th>Duration</th> <td>0:00:10.002389</td> </tr> <tr> <th>Markers</th> <td> <div class=marker> <span class="marker-name badge">mlvp_async</span> <span class=marker-args> </span> </div> </td> </tr> <tr> <th>Fixtures</th> <td> <span class="badge fixturename"> mlvp_request </span> <span class="badge fixturename"> mlvp_pre_request </span> <span class="badge fixturename"> request </span> </td> </tr> </table> <div class=test-phases> <details class="phase setup passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Setup</span> </h4> </summary> <div class=content> <div class=section> <h5 class=section-title>Captured stderr setup</h5> <pre><samp><span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_btb_enable&#34; is connected to &#34;io_ctrl_btb_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_ras_enable&#34; is connected to &#34;io_ctrl_ras_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_sc_enable&#34; is connected to &#34;io_ctrl_sc_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_tage_enable&#34; is connected to &#34;io_ctrl_tage_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_ubtb_enable&#34; is connected to &#34;io_ctrl_ubtb_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_full_target&#34; is connected to &#34;io_ftq_to_bpu_update_bits_full_target&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34; is connected to &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_meta&#34; is connected to &#34;io_ftq_to_bpu_update_bits_meta&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_old_entry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_old_entry&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_level&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_level&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured log setup</h5> <pre><samp><span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_btb_enable&#34; is connected to &#34;io_ctrl_btb_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_ras_enable&#34; is connected to &#34;io_ctrl_ras_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_sc_enable&#34; is connected to &#34;io_ctrl_sc_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_tage_enable&#34; is connected to &#34;io_ctrl_tage_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_ubtb_enable&#34; is connected to &#34;io_ctrl_ubtb_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_full_target&#34; is connected to &#34;io_ftq_to_bpu_update_bits_full_target&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34; is connected to &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_meta&#34; is connected to &#34;io_ftq_to_bpu_update_bits_meta&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_old_entry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_old_entry&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_level&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_level&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</samp></pre> </div> </div> </details> <details class="phase call passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Call</span> </h4> </summary> <div class=content> <div class=section> <h5 class=section-title>Captured stdout call</h5> <pre><samp>&lt;function mlvp_request.&lt;locals&gt;.start_code at 0x759cc1529990&gt;
+set_sub_predic_ctrl_en Begin exec
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+begin exec test_redirect_cfi_sanity test
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+test_normal_sanity IS OVER
+1
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured stderr call</h5> <pre><samp><span class=ansi37>MLVP_INFO @logger.py:147:	Log Summary
+============
+* Report counts by severity
+INFO:	2735
+</span>
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured log call</h5> <pre><samp><span class=ansi32>INFO    </span> MLVP:logger.py:147 Log Summary
+============
+* Report counts by severity
+INFO:	2735</samp></pre> </div> </div> </details> <details class="phase teardown passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Teardown</span> </h4> </summary> <div class=content> </div> </details> </div> </div> </details> <details class="test passed"> <summary> <h3 class="title test-title"> <span class="status badge passed ">PASSED</span> <span class=test-name> <span class=funcname>test_update_FtbEntry_foldHist_signals_1</span> </span> <span class=duration>0:00:09.761200</span> </h3> </summary> <div class=content> <table class=metadata> <tr> <th>Started</th> <td>2024-10-27 20:22:26</td> </tr> <tr> <th>Ended</th> <td>2024-10-27 20:22:36</td> </tr> <tr> <th>Duration</th> <td>0:00:09.761200</td> </tr> <tr> <th>Markers</th> <td> <div class=marker> <span class="marker-name badge">mlvp_async</span> <span class=marker-args> </span> </div> </td> </tr> <tr> <th>Fixtures</th> <td> <span class="badge fixturename"> mlvp_request </span> <span class="badge fixturename"> mlvp_pre_request </span> <span class="badge fixturename"> request </span> </td> </tr> </table> <div class=test-phases> <details class="phase setup passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Setup</span> </h4> </summary> <div class=content> <div class=section> <h5 class=section-title>Captured stderr setup</h5> <pre><samp><span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_btb_enable&#34; is connected to &#34;io_ctrl_btb_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_ras_enable&#34; is connected to &#34;io_ctrl_ras_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_sc_enable&#34; is connected to &#34;io_ctrl_sc_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_tage_enable&#34; is connected to &#34;io_ctrl_tage_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_ubtb_enable&#34; is connected to &#34;io_ctrl_ubtb_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_full_target&#34; is connected to &#34;io_ftq_to_bpu_update_bits_full_target&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34; is connected to &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_meta&#34; is connected to &#34;io_ftq_to_bpu_update_bits_meta&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_old_entry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_old_entry&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
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+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
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+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_level&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_level&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured log setup</h5> <pre><samp><span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_btb_enable&#34; is connected to &#34;io_ctrl_btb_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_ras_enable&#34; is connected to &#34;io_ctrl_ras_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_sc_enable&#34; is connected to &#34;io_ctrl_sc_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_tage_enable&#34; is connected to &#34;io_ctrl_tage_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_ubtb_enable&#34; is connected to &#34;io_ctrl_ubtb_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_full_target&#34; is connected to &#34;io_ftq_to_bpu_update_bits_full_target&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34; is connected to &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_meta&#34; is connected to &#34;io_ftq_to_bpu_update_bits_meta&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_old_entry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_old_entry&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_level&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_level&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</samp></pre> </div> </div> </details> <details class="phase call passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Call</span> </h4> </summary> <div class=content> <div class=section> <h5 class=section-title>Captured stdout call</h5> <pre><samp>&lt;function mlvp_request.&lt;locals&gt;.start_code at 0x759cc0011ea0&gt;
+begin exec test_update_fold_hist_sanity test
+test_update_signals_sanity IS OVER
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured stderr call</h5> <pre><samp><span class=ansi37>MLVP_INFO @logger.py:147:	Log Summary
+============
+* Report counts by severity
+INFO:	2879
+</span>
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured log call</h5> <pre><samp><span class=ansi32>INFO    </span> MLVP:logger.py:147 Log Summary
+============
+* Report counts by severity
+INFO:	2879</samp></pre> </div> </div> </details> <details class="phase teardown passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Teardown</span> </h4> </summary> <div class=content> </div> </details> </div> </div> </details> <details class="test passed"> <summary> <h3 class="title test-title"> <span class="status badge passed ">PASSED</span> <span class=test-name> <span class=funcname>test_update_FtbEntry_foldHist_signals_2</span> </span> <span class=duration>0:00:09.625023</span> </h3> </summary> <div class=content> <table class=metadata> <tr> <th>Started</th> <td>2024-10-27 20:22:36</td> </tr> <tr> <th>Ended</th> <td>2024-10-27 20:22:45</td> </tr> <tr> <th>Duration</th> <td>0:00:09.625023</td> </tr> <tr> <th>Markers</th> <td> <div class=marker> <span class="marker-name badge">mlvp_async</span> <span class=marker-args> </span> </div> </td> </tr> <tr> <th>Fixtures</th> <td> <span class="badge fixturename"> mlvp_request </span> <span class="badge fixturename"> mlvp_pre_request </span> <span class="badge fixturename"> request </span> </td> </tr> </table> <div class=test-phases> <details class="phase setup passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Setup</span> </h4> </summary> <div class=content> <div class=section> <h5 class=section-title>Captured stderr setup</h5> <pre><samp><span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_btb_enable&#34; is connected to &#34;io_ctrl_btb_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_ras_enable&#34; is connected to &#34;io_ctrl_ras_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_sc_enable&#34; is connected to &#34;io_ctrl_sc_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_tage_enable&#34; is connected to &#34;io_ctrl_tage_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_ubtb_enable&#34; is connected to &#34;io_ctrl_ubtb_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34;</span>
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+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
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+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_level&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_level&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured log setup</h5> <pre><samp><span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_btb_enable&#34; is connected to &#34;io_ctrl_btb_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_ras_enable&#34; is connected to &#34;io_ctrl_ras_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_sc_enable&#34; is connected to &#34;io_ctrl_sc_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_tage_enable&#34; is connected to &#34;io_ctrl_tage_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_ubtb_enable&#34; is connected to &#34;io_ctrl_ubtb_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_full_target&#34; is connected to &#34;io_ftq_to_bpu_update_bits_full_target&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34; is connected to &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_meta&#34; is connected to &#34;io_ftq_to_bpu_update_bits_meta&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_old_entry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_old_entry&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_level&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_level&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</samp></pre> </div> </div> </details> <details class="phase call passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Call</span> </h4> </summary> <div class=content> <div class=section> <h5 class=section-title>Captured stdout call</h5> <pre><samp>&lt;function mlvp_request.&lt;locals&gt;.start_code at 0x759cc00129e0&gt;
+set_sub_predic_ctrl_en Begin exec
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+begin exec test_update_fold_hist_sanity test
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+test_update_signals_sanity IS OVER
+1
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured stderr call</h5> <pre><samp><span class=ansi37>MLVP_INFO @logger.py:147:	Log Summary
+============
+* Report counts by severity
+INFO:	3023
+</span>
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured log call</h5> <pre><samp><span class=ansi32>INFO    </span> MLVP:logger.py:147 Log Summary
+============
+* Report counts by severity
+INFO:	3023</samp></pre> </div> </div> </details> <details class="phase teardown passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Teardown</span> </h4> </summary> <div class=content> </div> </details> </div> </div> </details> <details class="test passed"> <summary> <h3 class="title test-title"> <span class="status badge passed ">PASSED</span> <span class=test-name> <span class=funcname>test_update_FtbEntry_foldHist_signals_3</span> </span> <span class=duration>0:00:09.548938</span> </h3> </summary> <div class=content> <table class=metadata> <tr> <th>Started</th> <td>2024-10-27 20:22:45</td> </tr> <tr> <th>Ended</th> <td>2024-10-27 20:22:55</td> </tr> <tr> <th>Duration</th> <td>0:00:09.548938</td> </tr> <tr> <th>Markers</th> <td> <div class=marker> <span class="marker-name badge">mlvp_async</span> <span class=marker-args> </span> </div> </td> </tr> <tr> <th>Fixtures</th> <td> <span class="badge fixturename"> mlvp_request </span> <span class="badge fixturename"> mlvp_pre_request </span> <span class="badge fixturename"> request </span> </td> </tr> </table> <div class=test-phases> <details class="phase setup passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Setup</span> </h4> </summary> <div class=content> <div class=section> <h5 class=section-title>Captured stderr setup</h5> <pre><samp><span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_btb_enable&#34; is connected to &#34;io_ctrl_btb_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_ras_enable&#34; is connected to &#34;io_ctrl_ras_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_sc_enable&#34; is connected to &#34;io_ctrl_sc_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_tage_enable&#34; is connected to &#34;io_ctrl_tage_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_ubtb_enable&#34; is connected to &#34;io_ctrl_ubtb_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_full_target&#34; is connected to &#34;io_ftq_to_bpu_update_bits_full_target&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34; is connected to &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_meta&#34; is connected to &#34;io_ftq_to_bpu_update_bits_meta&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_old_entry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_old_entry&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_level&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_level&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured log setup</h5> <pre><samp><span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_btb_enable&#34; is connected to &#34;io_ctrl_btb_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_ras_enable&#34; is connected to &#34;io_ctrl_ras_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_sc_enable&#34; is connected to &#34;io_ctrl_sc_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_tage_enable&#34; is connected to &#34;io_ctrl_tage_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_ubtb_enable&#34; is connected to &#34;io_ctrl_ubtb_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_full_target&#34; is connected to &#34;io_ftq_to_bpu_update_bits_full_target&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34; is connected to &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_meta&#34; is connected to &#34;io_ftq_to_bpu_update_bits_meta&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_old_entry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_old_entry&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_level&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_level&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</samp></pre> </div> </div> </details> <details class="phase call passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Call</span> </h4> </summary> <div class=content> <div class=section> <h5 class=section-title>Captured stdout call</h5> <pre><samp>&lt;function mlvp_request.&lt;locals&gt;.start_code at 0x759cc0013520&gt;
+set_sub_predic_ctrl_en Begin exec
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+begin exec test_update_fold_hist_sanity test
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+test_update_signals_sanity IS OVER
+1
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured stderr call</h5> <pre><samp><span class=ansi37>MLVP_INFO @logger.py:147:	Log Summary
+============
+* Report counts by severity
+INFO:	3167
+</span>
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured log call</h5> <pre><samp><span class=ansi32>INFO    </span> MLVP:logger.py:147 Log Summary
+============
+* Report counts by severity
+INFO:	3167</samp></pre> </div> </div> </details> <details class="phase teardown passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Teardown</span> </h4> </summary> <div class=content> </div> </details> </div> </div> </details> <details class="test passed"> <summary> <h3 class="title test-title"> <span class="status badge passed ">PASSED</span> <span class=test-name> <span class=funcname>test_update_FtbEntry_foldHist_signals_4</span> </span> <span class=duration>0:00:09.491244</span> </h3> </summary> <div class=content> <table class=metadata> <tr> <th>Started</th> <td>2024-10-27 20:22:55</td> </tr> <tr> <th>Ended</th> <td>2024-10-27 20:23:05</td> </tr> <tr> <th>Duration</th> <td>0:00:09.491244</td> </tr> <tr> <th>Markers</th> <td> <div class=marker> <span class="marker-name badge">mlvp_async</span> <span class=marker-args> </span> </div> </td> </tr> <tr> <th>Fixtures</th> <td> <span class="badge fixturename"> mlvp_request </span> <span class="badge fixturename"> mlvp_pre_request </span> <span class="badge fixturename"> request </span> </td> </tr> </table> <div class=test-phases> <details class="phase setup passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Setup</span> </h4> </summary> <div class=content> <div class=section> <h5 class=section-title>Captured stdout setup</h5> <pre><samp>INFO: Shared DPI Library Path: /home/xianshan/glcc/xianshan/env-xs-ov-00-bpu/tests/bpu_top/env/../../../out/picker_out_BPUTop/UT_Predictor/libUTPredictor.so
+INFO: Using main namespace
+INFO: Shared DPI Library Path: /home/xianshan/glcc/xianshan/env-xs-ov-00-bpu/tests/bpu_top/env/../../../out/picker_out_BPUTop/UT_Predictor/libUTPredictor.so
+INFO: Using main namespace
+INFO: Shared DPI Library Path: /home/xianshan/glcc/xianshan/env-xs-ov-00-bpu/tests/bpu_top/env/../../../out/picker_out_BPUTop/UT_Predictor/libUTPredictor.so
+INFO: Using main namespace
+INFO: Shared DPI Library Path: /home/xianshan/glcc/xianshan/env-xs-ov-00-bpu/tests/bpu_top/env/../../../out/picker_out_BPUTop/UT_Predictor/libUTPredictor.so
+INFO: Using main namespace
+INFO: Shared DPI Library Path: /home/xianshan/glcc/xianshan/env-xs-ov-00-bpu/tests/bpu_top/env/../../../out/picker_out_BPUTop/UT_Predictor/libUTPredictor.so
+INFO: Using main namespace
+INFO: Shared DPI Library Path: /home/xianshan/glcc/xianshan/env-xs-ov-00-bpu/tests/bpu_top/env/../../../out/picker_out_BPUTop/UT_Predictor/libUTPredictor.so
+INFO: Using main namespace
+INFO: Shared DPI Library Path: /home/xianshan/glcc/xianshan/env-xs-ov-00-bpu/tests/bpu_top/env/../../../out/picker_out_BPUTop/UT_Predictor/libUTPredictor.so
+INFO: Using main namespace
+INFO: Shared DPI Library Path: /home/xianshan/glcc/xianshan/env-xs-ov-00-bpu/tests/bpu_top/env/../../../out/picker_out_BPUTop/UT_Predictor/libUTPredictor.so
+INFO: Using main namespace
+INFO: Shared DPI Library Path: /home/xianshan/glcc/xianshan/env-xs-ov-00-bpu/tests/bpu_top/env/../../../out/picker_out_BPUTop/UT_Predictor/libUTPredictor.so
+INFO: Using main namespace
+INFO: Shared DPI Library Path: /home/xianshan/glcc/xianshan/env-xs-ov-00-bpu/tests/bpu_top/env/../../../out/picker_out_BPUTop/UT_Predictor/libUTPredictor.so
+INFO: Using main namespace
+INFO: Shared DPI Library Path: /home/xianshan/glcc/xianshan/env-xs-ov-00-bpu/tests/bpu_top/env/../../../out/picker_out_BPUTop/UT_Predictor/libUTPredictor.so
+INFO: Using main namespace
+INFO: Shared DPI Library Path: /home/xianshan/glcc/xianshan/env-xs-ov-00-bpu/tests/bpu_top/env/../../../out/picker_out_BPUTop/UT_Predictor/libUTPredictor.so
+INFO: Using main namespace
+INFO: Shared DPI Library Path: /home/xianshan/glcc/xianshan/env-xs-ov-00-bpu/tests/bpu_top/env/../../../out/picker_out_BPUTop/UT_Predictor/libUTPredictor.so
+INFO: Using main namespace
+INFO: Shared DPI Library Path: /home/xianshan/glcc/xianshan/env-xs-ov-00-bpu/tests/bpu_top/env/../../../out/picker_out_BPUTop/UT_Predictor/libUTPredictor.so
+INFO: Using main namespace
+INFO: Shared DPI Library Path: /home/xianshan/glcc/xianshan/env-xs-ov-00-bpu/tests/bpu_top/env/../../../out/picker_out_BPUTop/UT_Predictor/libUTPredictor.so
+INFO: Using main namespace
+INFO: Shared DPI Library Path: /home/xianshan/glcc/xianshan/env-xs-ov-00-bpu/tests/bpu_top/env/../../../out/picker_out_BPUTop/UT_Predictor/libUTPredictor.so
+INFO: Using main namespace
+INFO: Shared DPI Library Path: /home/xianshan/glcc/xianshan/env-xs-ov-00-bpu/tests/bpu_top/env/../../../out/picker_out_BPUTop/UT_Predictor/libUTPredictor.so
+INFO: Using main namespace
+INFO: Shared DPI Library Path: /home/xianshan/glcc/xianshan/env-xs-ov-00-bpu/tests/bpu_top/env/../../../out/picker_out_BPUTop/UT_Predictor/libUTPredictor.so
+INFO: Using main namespace
+INFO: Shared DPI Library Path: /home/xianshan/glcc/xianshan/env-xs-ov-00-bpu/tests/bpu_top/env/../../../out/picker_out_BPUTop/UT_Predictor/libUTPredictor.so
+INFO: Using main namespace
+INFO: Shared DPI Library Path: /home/xianshan/glcc/xianshan/env-xs-ov-00-bpu/tests/bpu_top/env/../../../out/picker_out_BPUTop/UT_Predictor/libUTPredictor.so
+INFO: Using main namespace
+INFO: Shared DPI Library Path: /home/xianshan/glcc/xianshan/env-xs-ov-00-bpu/tests/bpu_top/env/../../../out/picker_out_BPUTop/UT_Predictor/libUTPredictor.so
+INFO: Using main namespace
+INFO: Shared DPI Library Path: /home/xianshan/glcc/xianshan/env-xs-ov-00-bpu/tests/bpu_top/env/../../../out/picker_out_BPUTop/UT_Predictor/libUTPredictor.so
+INFO: Using main namespace
+INFO: Shared DPI Library Path: /home/xianshan/gl</samp></pre> </div> <div class=section> <h5 class=section-title>Captured stderr setup</h5> <pre><samp><span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_btb_enable&#34; is connected to &#34;io_ctrl_btb_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_ras_enable&#34; is connected to &#34;io_ctrl_ras_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_sc_enable&#34; is connected to &#34;io_ctrl_sc_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_tage_enable&#34; is connected to &#34;io_ctrl_tage_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_ubtb_enable&#34; is connected to &#34;io_ctrl_ubtb_enable&#34;</span>
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+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34;</span>
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+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34;</span>
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+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34;</span>
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+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34;</span>
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+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34;</span>
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+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34;</span>
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+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured log setup</h5> <pre><samp><span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_btb_enable&#34; is connected to &#34;io_ctrl_btb_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_ras_enable&#34; is connected to &#34;io_ctrl_ras_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_sc_enable&#34; is connected to &#34;io_ctrl_sc_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_tage_enable&#34; is connected to &#34;io_ctrl_tage_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_ubtb_enable&#34; is connected to &#34;io_ctrl_ubtb_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_full_target&#34; is connected to &#34;io_ftq_to_bpu_update_bits_full_target&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34; is connected to &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_meta&#34; is connected to &#34;io_ftq_to_bpu_update_bits_meta&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_old_entry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_old_entry&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_level&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_level&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</samp></pre> </div> </div> </details> <details class="phase call passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Call</span> </h4> </summary> <div class=content> <div class=section> <h5 class=section-title>Captured stdout call</h5> <pre><samp>&lt;function mlvp_request.&lt;locals&gt;.start_code at 0x759cc037c0d0&gt;
+set_sub_predic_ctrl_en Begin exec
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+begin exec test_update_fold_hist_sanity test
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+test_update_signals_sanity IS OVER
+1
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured stderr call</h5> <pre><samp><span class=ansi37>MLVP_INFO @logger.py:147:	Log Summary
+============
+* Report counts by severity
+INFO:	3311
+</span>
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured log call</h5> <pre><samp><span class=ansi32>INFO    </span> MLVP:logger.py:147 Log Summary
+============
+* Report counts by severity
+INFO:	3311</samp></pre> </div> </div> </details> <details class="phase teardown passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Teardown</span> </h4> </summary> <div class=content> </div> </details> </div> </div> </details> <details class="test passed"> <summary> <h3 class="title test-title"> <span class="status badge passed ">PASSED</span> <span class=test-name> <span class=funcname>test_update_FtbEntry_foldHist_signals_5</span> </span> <span class=duration>0:00:10.470490</span> </h3> </summary> <div class=content> <table class=metadata> <tr> <th>Started</th> <td>2024-10-27 20:23:05</td> </tr> <tr> <th>Ended</th> <td>2024-10-27 20:23:15</td> </tr> <tr> <th>Duration</th> <td>0:00:10.470490</td> </tr> <tr> <th>Markers</th> <td> <div class=marker> <span class="marker-name badge">mlvp_async</span> <span class=marker-args> </span> </div> </td> </tr> <tr> <th>Fixtures</th> <td> <span class="badge fixturename"> mlvp_request </span> <span class="badge fixturename"> mlvp_pre_request </span> <span class="badge fixturename"> request </span> </td> </tr> </table> <div class=test-phases> <details class="phase setup passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Setup</span> </h4> </summary> <div class=content> <div class=section> <h5 class=section-title>Captured stderr setup</h5> <pre><samp><span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_btb_enable&#34; is connected to &#34;io_ctrl_btb_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_ras_enable&#34; is connected to &#34;io_ctrl_ras_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_sc_enable&#34; is connected to &#34;io_ctrl_sc_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_tage_enable&#34; is connected to &#34;io_ctrl_tage_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_ubtb_enable&#34; is connected to &#34;io_ctrl_ubtb_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_full_target&#34; is connected to &#34;io_ftq_to_bpu_update_bits_full_target&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34; is connected to &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_meta&#34; is connected to &#34;io_ftq_to_bpu_update_bits_meta&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_old_entry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_old_entry&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34;</span>
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+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
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+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34;</span>
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+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34;</span>
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+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34;</span>
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+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_level&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_level&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
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+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured log setup</h5> <pre><samp><span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_btb_enable&#34; is connected to &#34;io_ctrl_btb_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_ras_enable&#34; is connected to &#34;io_ctrl_ras_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_sc_enable&#34; is connected to &#34;io_ctrl_sc_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_tage_enable&#34; is connected to &#34;io_ctrl_tage_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_ubtb_enable&#34; is connected to &#34;io_ctrl_ubtb_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_full_target&#34; is connected to &#34;io_ftq_to_bpu_update_bits_full_target&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34; is connected to &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_meta&#34; is connected to &#34;io_ftq_to_bpu_update_bits_meta&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_old_entry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_old_entry&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_level&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_level&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</samp></pre> </div> </div> </details> <details class="phase call passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Call</span> </h4> </summary> <div class=content> <div class=section> <h5 class=section-title>Captured stdout call</h5> <pre><samp>&lt;function mlvp_request.&lt;locals&gt;.start_code at 0x759cc037cc10&gt;
+set_sub_predic_ctrl_en Begin exec
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+begin exec test_update_fold_hist_sanity test
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+set_sub_predic_ctrl_en Begin exec
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+test_update_signals_sanity IS OVER
+1
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured stderr call</h5> <pre><samp><span class=ansi37>MLVP_INFO @logger.py:147:	Log Summary
+============
+* Report counts by severity
+INFO:	3455
+</span>
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured log call</h5> <pre><samp><span class=ansi32>INFO    </span> MLVP:logger.py:147 Log Summary
+============
+* Report counts by severity
+INFO:	3455</samp></pre> </div> </div> </details> <details class="phase teardown passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Teardown</span> </h4> </summary> <div class=content> </div> </details> </div> </div> </details> <details class="test passed"> <summary> <h3 class="title test-title"> <span class="status badge passed ">PASSED</span> <span class=test-name> <span class=funcname>test_update_FtbEntry_foldHist_signals_6</span> </span> <span class=duration>0:00:09.641382</span> </h3> </summary> <div class=content> <table class=metadata> <tr> <th>Started</th> <td>2024-10-27 20:23:15</td> </tr> <tr> <th>Ended</th> <td>2024-10-27 20:23:25</td> </tr> <tr> <th>Duration</th> <td>0:00:09.641382</td> </tr> <tr> <th>Markers</th> <td> <div class=marker> <span class="marker-name badge">mlvp_async</span> <span class=marker-args> </span> </div> </td> </tr> <tr> <th>Fixtures</th> <td> <span class="badge fixturename"> mlvp_request </span> <span class="badge fixturename"> mlvp_pre_request </span> <span class="badge fixturename"> request </span> </td> </tr> </table> <div class=test-phases> <details class="phase setup passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Setup</span> </h4> </summary> <div class=content> <div class=section> <h5 class=section-title>Captured stderr setup</h5> <pre><samp><span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_btb_enable&#34; is connected to &#34;io_ctrl_btb_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_ras_enable&#34; is connected to &#34;io_ctrl_ras_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_sc_enable&#34; is connected to &#34;io_ctrl_sc_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_tage_enable&#34; is connected to &#34;io_ctrl_tage_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_ubtb_enable&#34; is connected to &#34;io_ctrl_ubtb_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34;</span>
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+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
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+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_level&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_level&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured log setup</h5> <pre><samp><span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_btb_enable&#34; is connected to &#34;io_ctrl_btb_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_ras_enable&#34; is connected to &#34;io_ctrl_ras_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_sc_enable&#34; is connected to &#34;io_ctrl_sc_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_tage_enable&#34; is connected to &#34;io_ctrl_tage_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_ubtb_enable&#34; is connected to &#34;io_ctrl_ubtb_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_full_target&#34; is connected to &#34;io_ftq_to_bpu_update_bits_full_target&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34; is connected to &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_meta&#34; is connected to &#34;io_ftq_to_bpu_update_bits_meta&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_old_entry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_old_entry&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_level&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_level&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</samp></pre> </div> </div> </details> <details class="phase call passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Call</span> </h4> </summary> <div class=content> <div class=section> <h5 class=section-title>Captured stdout call</h5> <pre><samp>&lt;function mlvp_request.&lt;locals&gt;.start_code at 0x759cc037d750&gt;
+set_sub_predic_ctrl_en Begin exec
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+begin exec test_update_fold_hist_sanity test
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+set_sub_predic_ctrl_en Begin exec
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+test_update_signals_sanity IS OVER
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+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured stderr call</h5> <pre><samp><span class=ansi37>MLVP_INFO @logger.py:147:	Log Summary
+============
+* Report counts by severity
+INFO:	3599
+</span>
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured log call</h5> <pre><samp><span class=ansi32>INFO    </span> MLVP:logger.py:147 Log Summary
+============
+* Report counts by severity
+INFO:	3599</samp></pre> </div> </div> </details> <details class="phase teardown passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Teardown</span> </h4> </summary> <div class=content> </div> </details> </div> </div> </details> <details class="test passed"> <summary> <h3 class="title test-title"> <span class="status badge passed ">PASSED</span> <span class=test-name> <span class=funcname>test_normal_redirect_cfi_twice_5</span> </span> <span class=duration>0:00:09.641413</span> </h3> </summary> <div class=content> <table class=metadata> <tr> <th>Started</th> <td>2024-10-27 20:23:25</td> </tr> <tr> <th>Ended</th> <td>2024-10-27 20:23:34</td> </tr> <tr> <th>Duration</th> <td>0:00:09.641413</td> </tr> <tr> <th>Markers</th> <td> <div class=marker> <span class="marker-name badge">mlvp_async</span> <span class=marker-args> </span> </div> </td> </tr> <tr> <th>Fixtures</th> <td> <span class="badge fixturename"> mlvp_request </span> <span class="badge fixturename"> mlvp_pre_request </span> <span class="badge fixturename"> request </span> </td> </tr> </table> <div class=test-phases> <details class="phase setup passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Setup</span> </h4> </summary> <div class=content> <div class=section> <h5 class=section-title>Captured stderr setup</h5> <pre><samp><span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_btb_enable&#34; is connected to &#34;io_ctrl_btb_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_ras_enable&#34; is connected to &#34;io_ctrl_ras_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_sc_enable&#34; is connected to &#34;io_ctrl_sc_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_tage_enable&#34; is connected to &#34;io_ctrl_tage_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_ubtb_enable&#34; is connected to &#34;io_ctrl_ubtb_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_full_target&#34; is connected to &#34;io_ftq_to_bpu_update_bits_full_target&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34; is connected to &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_meta&#34; is connected to &#34;io_ftq_to_bpu_update_bits_meta&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_old_entry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_old_entry&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_level&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_level&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured log setup</h5> <pre><samp><span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_btb_enable&#34; is connected to &#34;io_ctrl_btb_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_ras_enable&#34; is connected to &#34;io_ctrl_ras_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_sc_enable&#34; is connected to &#34;io_ctrl_sc_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_tage_enable&#34; is connected to &#34;io_ctrl_tage_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_ubtb_enable&#34; is connected to &#34;io_ctrl_ubtb_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_full_target&#34; is connected to &#34;io_ftq_to_bpu_update_bits_full_target&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34; is connected to &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_meta&#34; is connected to &#34;io_ftq_to_bpu_update_bits_meta&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_old_entry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_old_entry&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_level&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_level&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</samp></pre> </div> </div> </details> <details class="phase call passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Call</span> </h4> </summary> <div class=content> <div class=section> <h5 class=section-title>Captured stdout call</h5> <pre><samp>&lt;function mlvp_request.&lt;locals&gt;.start_code at 0x759cc037e170&gt;
+set_sub_predic_ctrl_en Begin exec
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+begin exec test_redirect_cfi_sanity test
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+set_sub_predic_ctrl_en Begin exec
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+test_normal_sanity IS OVER
+1
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured stderr call</h5> <pre><samp><span class=ansi37>MLVP_INFO @logger.py:147:	Log Summary
+============
+* Report counts by severity
+INFO:	3743
+</span>
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured log call</h5> <pre><samp><span class=ansi32>INFO    </span> MLVP:logger.py:147 Log Summary
+============
+* Report counts by severity
+INFO:	3743</samp></pre> </div> </div> </details> <details class="phase teardown passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Teardown</span> </h4> </summary> <div class=content> </div> </details> </div> </div> </details> <details class="test passed"> <summary> <h3 class="title test-title"> <span class="status badge passed ">PASSED</span> <span class=test-name> <span class=funcname>test_normal_redirect_cfi_twice_6</span> </span> <span class=duration>0:00:10.898214</span> </h3> </summary> <div class=content> <table class=metadata> <tr> <th>Started</th> <td>2024-10-27 20:23:34</td> </tr> <tr> <th>Ended</th> <td>2024-10-27 20:23:45</td> </tr> <tr> <th>Duration</th> <td>0:00:10.898214</td> </tr> <tr> <th>Markers</th> <td> <div class=marker> <span class="marker-name badge">mlvp_async</span> <span class=marker-args> </span> </div> </td> </tr> <tr> <th>Fixtures</th> <td> <span class="badge fixturename"> mlvp_request </span> <span class="badge fixturename"> mlvp_pre_request </span> <span class="badge fixturename"> request </span> </td> </tr> </table> <div class=test-phases> <details class="phase setup passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Setup</span> </h4> </summary> <div class=content> <div class=section> <h5 class=section-title>Captured stderr setup</h5> <pre><samp><span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_btb_enable&#34; is connected to &#34;io_ctrl_btb_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_ras_enable&#34; is connected to &#34;io_ctrl_ras_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_sc_enable&#34; is connected to &#34;io_ctrl_sc_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_tage_enable&#34; is connected to &#34;io_ctrl_tage_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_ubtb_enable&#34; is connected to &#34;io_ctrl_ubtb_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34;</span>
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+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_level&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_level&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured log setup</h5> <pre><samp><span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_btb_enable&#34; is connected to &#34;io_ctrl_btb_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_ras_enable&#34; is connected to &#34;io_ctrl_ras_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_sc_enable&#34; is connected to &#34;io_ctrl_sc_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_tage_enable&#34; is connected to &#34;io_ctrl_tage_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_ubtb_enable&#34; is connected to &#34;io_ctrl_ubtb_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_full_target&#34; is connected to &#34;io_ftq_to_bpu_update_bits_full_target&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34; is connected to &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_meta&#34; is connected to &#34;io_ftq_to_bpu_update_bits_meta&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_old_entry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_old_entry&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_level&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_level&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</samp></pre> </div> </div> </details> <details class="phase call passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Call</span> </h4> </summary> <div class=content> <div class=section> <h5 class=section-title>Captured stdout call</h5> <pre><samp>&lt;function mlvp_request.&lt;locals&gt;.start_code at 0x759cc037ec20&gt;
+set_sub_predic_ctrl_en Begin exec
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+begin exec test_redirect_cfi_sanity test
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+set_sub_predic_ctrl_en Begin exec
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+test_normal_sanity IS OVER
+1
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured stderr call</h5> <pre><samp><span class=ansi37>MLVP_INFO @logger.py:147:	Log Summary
+============
+* Report counts by severity
+INFO:	3887
+</span>
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured log call</h5> <pre><samp><span class=ansi32>INFO    </span> MLVP:logger.py:147 Log Summary
+============
+* Report counts by severity
+INFO:	3887</samp></pre> </div> </div> </details> <details class="phase teardown passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Teardown</span> </h4> </summary> <div class=content> </div> </details> </div> </div> </details> <details class="test passed"> <summary> <h3 class="title test-title"> <span class="status badge passed ">PASSED</span> <span class=test-name> <span class=funcname>test_normal_redirect_cfi_twice_7</span> </span> <span class=duration>0:00:09.819208</span> </h3> </summary> <div class=content> <table class=metadata> <tr> <th>Started</th> <td>2024-10-27 20:23:45</td> </tr> <tr> <th>Ended</th> <td>2024-10-27 20:23:55</td> </tr> <tr> <th>Duration</th> <td>0:00:09.819208</td> </tr> <tr> <th>Markers</th> <td> <div class=marker> <span class="marker-name badge">mlvp_async</span> <span class=marker-args> </span> </div> </td> </tr> <tr> <th>Fixtures</th> <td> <span class="badge fixturename"> mlvp_request </span> <span class="badge fixturename"> mlvp_pre_request </span> <span class="badge fixturename"> request </span> </td> </tr> </table> <div class=test-phases> <details class="phase setup passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Setup</span> </h4> </summary> <div class=content> <div class=section> <h5 class=section-title>Captured stderr setup</h5> <pre><samp><span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_btb_enable&#34; is connected to &#34;io_ctrl_btb_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_ras_enable&#34; is connected to &#34;io_ctrl_ras_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_sc_enable&#34; is connected to &#34;io_ctrl_sc_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_tage_enable&#34; is connected to &#34;io_ctrl_tage_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_ubtb_enable&#34; is connected to &#34;io_ctrl_ubtb_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_full_target&#34; is connected to &#34;io_ftq_to_bpu_update_bits_full_target&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34; is connected to &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_meta&#34; is connected to &#34;io_ftq_to_bpu_update_bits_meta&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_old_entry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_old_entry&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_level&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_level&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured log setup</h5> <pre><samp><span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_btb_enable&#34; is connected to &#34;io_ctrl_btb_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_ras_enable&#34; is connected to &#34;io_ctrl_ras_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_sc_enable&#34; is connected to &#34;io_ctrl_sc_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_tage_enable&#34; is connected to &#34;io_ctrl_tage_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_ubtb_enable&#34; is connected to &#34;io_ctrl_ubtb_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_full_target&#34; is connected to &#34;io_ftq_to_bpu_update_bits_full_target&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34; is connected to &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_meta&#34; is connected to &#34;io_ftq_to_bpu_update_bits_meta&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_old_entry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_old_entry&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_level&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_level&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</samp></pre> </div> </div> </details> <details class="phase call passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Call</span> </h4> </summary> <div class=content> <div class=section> <h5 class=section-title>Captured stdout call</h5> <pre><samp>&lt;function mlvp_request.&lt;locals&gt;.start_code at 0x759cc037f6d0&gt;
+set_sub_predic_ctrl_en Begin exec
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+begin exec test_redirect_cfi_sanity test
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+set_sub_predic_ctrl_en Begin exec
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+test_normal_sanity IS OVER
+1
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured stderr call</h5> <pre><samp><span class=ansi37>MLVP_INFO @logger.py:147:	Log Summary
+============
+* Report counts by severity
+INFO:	4031
+</span>
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured log call</h5> <pre><samp><span class=ansi32>INFO    </span> MLVP:logger.py:147 Log Summary
+============
+* Report counts by severity
+INFO:	4031</samp></pre> </div> </div> </details> <details class="phase teardown passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Teardown</span> </h4> </summary> <div class=content> </div> </details> </div> </div> </details> <details class="test passed"> <summary> <h3 class="title test-title"> <span class="status badge passed ">PASSED</span> <span class=test-name> <span class=funcname>test_normal_redirect_cfi_twice_8</span> </span> <span class=duration>0:00:09.972072</span> </h3> </summary> <div class=content> <table class=metadata> <tr> <th>Started</th> <td>2024-10-27 20:23:55</td> </tr> <tr> <th>Ended</th> <td>2024-10-27 20:24:05</td> </tr> <tr> <th>Duration</th> <td>0:00:09.972072</td> </tr> <tr> <th>Markers</th> <td> <div class=marker> <span class="marker-name badge">mlvp_async</span> <span class=marker-args> </span> </div> </td> </tr> <tr> <th>Fixtures</th> <td> <span class="badge fixturename"> mlvp_request </span> <span class="badge fixturename"> mlvp_pre_request </span> <span class="badge fixturename"> request </span> </td> </tr> </table> <div class=test-phases> <details class="phase setup passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Setup</span> </h4> </summary> <div class=content> <div class=section> <h5 class=section-title>Captured stderr setup</h5> <pre><samp><span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_btb_enable&#34; is connected to &#34;io_ctrl_btb_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_ras_enable&#34; is connected to &#34;io_ctrl_ras_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_sc_enable&#34; is connected to &#34;io_ctrl_sc_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_tage_enable&#34; is connected to &#34;io_ctrl_tage_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ctrl_ubtb_enable&#34; is connected to &#34;io_ctrl_ubtb_enable&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34;</span>
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+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_level&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_level&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;</span>
+<span class=ansi37>MLVP_INFO @bundle.py:810:	dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</span>
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured log setup</h5> <pre><samp><span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_btb_enable&#34; is connected to &#34;io_ctrl_btb_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_ras_enable&#34; is connected to &#34;io_ctrl_ras_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_sc_enable&#34; is connected to &#34;io_ctrl_sc_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_tage_enable&#34; is connected to &#34;io_ctrl_tage_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ctrl_ubtb_enable&#34; is connected to &#34;io_ctrl_ubtb_enable&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_carry&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isCall&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isJalr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_isRet&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_pftAddr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_ftb_entry_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_br_taken_mask_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_bits&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34; is connected to &#34;io_ftq_to_bpu_update_bits_cfi_idx_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_full_target&#34; is connected to &#34;io_ftq_to_bpu_update_bits_full_target&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34; is connected to &#34;io_ftq_to_bpu_update_bits_jmp_taken&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_meta&#34; is connected to &#34;io_ftq_to_bpu_update_bits_meta&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34; is connected to &#34;io_ftq_to_bpu_update_bits_mispred_mask_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_old_entry&#34; is connected to &#34;io_ftq_to_bpu_update_bits_old_entry&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_pc&#34; is connected to &#34;io_ftq_to_bpu_update_bits_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_update_valid&#34; is connected to &#34;io_ftq_to_bpu_update_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pc&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_shift&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_taken&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_target&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_level&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_level&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_bpu_to_ftq_resp_ready&#34; is connected to &#34;io_bpu_to_ftq_resp_ready&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34; is connected to &#34;io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_ftq_to_bpu_redirect_valid&#34; is connected to &#34;io_ftq_to_bpu_redirect_valid&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;io_reset_vector&#34; is connected to &#34;io_reset_vector&#34;
+<span class=ansi32>INFO    </span> MLVP:bundle.py:810 dut&#39;s signal &#34;reset&#34; is connected to &#34;reset&#34;</samp></pre> </div> </div> </details> <details class="phase call passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Call</span> </h4> </summary> <div class=content> <div class=section> <h5 class=section-title>Captured stdout call</h5> <pre><samp>&lt;function mlvp_request.&lt;locals&gt;.start_code at 0x759cb1f981f0&gt;
+set_sub_predic_ctrl_en Begin exec
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+begin exec test_redirect_cfi_sanity test
+1
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+set_sub_predic_ctrl_en Begin exec
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+test_normal_sanity IS OVER
+1
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured stderr call</h5> <pre><samp><span class=ansi37>MLVP_INFO @logger.py:147:	Log Summary
+============
+* Report counts by severity
+INFO:	4175
+</span>
+</samp></pre> </div> <div class=section> <h5 class=section-title>Captured log call</h5> <pre><samp><span class=ansi32>INFO    </span> MLVP:logger.py:147 Log Summary
+============
+* Report counts by severity
+INFO:	4175</samp></pre> </div> </div> </details> <details class="phase teardown passed" open> <summary> <h4 class=title> <span class="status  passed"></span> <span class=phase-name>Teardown</span> </h4> </summary> <div class=content> </div> </details> </div> </div> </details> </div> </details> </div> </section> </main> <footer> <div class=container> MLVP Report, Do Not Edit. </div> </footer> </body> </html>
\ No newline at end of file
diff --git a/tests/bpu_top/test_bpu_sanity.py b/tests/bpu_top/test_bpu_sanity.py
deleted file mode 100644
index 20db893..0000000
--- a/tests/bpu_top/test_bpu_sanity.py
+++ /dev/null
@@ -1,100 +0,0 @@
-from config import *
-
-import os
-os.sys.path.append(TESTS_PATH)
-os.sys.path.append(DUT_PATH)
-
-from UT_Predictor import *
-import random
-
-import mlvp
-import logging
-
-import mlvp.funcov as fc
-from mlvp.reporter import *
-
-import asyncio
-
-import test_bpu_sanity as bpu
-
-"""
-#######Usr function #######
-"""
-
-async def cfg_default(dut: DUTPredictor):
-	set_bpu_ctrl(dut,1)
-	reset_bpu(dut,1)
-	dut.io_reset_vector.value = 0x1000
-	dut.io_bpu_to_ftq_resp_ready.value = 1
-	await dut.AStep(2)
-	reset_bpu(dut,0)
-	await dut.AStep(2050)
-
-def reset_bpu(dut: DUTPredictor,data: int):
-	dut.reset.value = data
-
-def set_bpu_ctrl(dut: DUTPredictor,data: int) -> None:
-	dut.io_ctrl_btb_enable.value = data
-	dut.io_ctrl_ubtb_enable.value= data
-	dut.io_ctrl_ras_enable.value = data
-	dut.io_ctrl_tage_enable.value= data
-	dut.io_ctrl_sc_enable.value	 = data
-
-async def set_bpu_ftq(dut: DUTPredictor) -> None:
-	dut.io_bpu_to_ftq_resp_ready.value = 0
-	await dut.AStep(2)
-	dut.io_bpu_to_ftq_resp_ready.value = 1
-
-def set_pin_bits(pin: int, high: int, low: int, value:int) -> int:
-	"""
-	Function: set pin's bits from low to high as value
-
-	Args:
-		-pin:dut.pin.value
-		-high:
-		-low:can from zero start
-		-value:the set value
-	
-	Returns: the calculated value 
-	"""
-	low_high_mask = ((1 << (high - low + 1)) -1) << low
-	cleard_pin = pin & ~low_high_mask
-	shifted_value = value << low
-	pin = cleard_pin | shifted_value
-	return pin
-	
-
-#def set_bits(pin,high: int,low: int ,value: int):
-
-async def bpu_sanity_test():
-	dut: DUTPredictor = DUTPredictor(
-		waveform_filename="report/BPUTop.fst", coverage_filename="report/BPUTop_coverage.dat")
-#	print(TEST_PATH)
-	print("Init DUT is OK!!!")
-	dut.InitClock("clock")
-
-	task = asyncio.create_task(dut.RunStep(20))	#create a async task
-	dut.reset.value = 0
-	await dut.AStep(2)
-	dut.reset.value = 1
-
-	await dut.AStep(1)
-	set_bpu_ctrl(dut,1)
-	await dut.AStep(2)
-	set_bpu_ctrl(dut,0)
-	
-#	dut.io_reset_vector.value = set_pin_bits(dut.io_reset_vector.value, 2, 1, 3)
-
-	#Finish
-	await task
-	dut.Finish()
-	print("test_bpu_sanity() exec over!!!")
-
-
-def tet_bpu_sanity(request):
-	asyncio.run(bpu_sanity_test())
-	set_line_coverage(request, "report/BPUTop_coverage.dat")
-
-if __name__ == "__main__":
-	asyncio.run(bpu_sanity_test())
-	
diff --git a/tests/bpu_top/test_bpu_sub_uftb_enable.py b/tests/bpu_top/test_bpu_sub_uftb_enable.py
deleted file mode 100644
index 0cebaf6..0000000
--- a/tests/bpu_top/test_bpu_sub_uftb_enable.py
+++ /dev/null
@@ -1,113 +0,0 @@
-from config import *
-
-import os
-os.sys.path.append(TESTS_PATH)
-os.sys.path.append(DUT_PATH)
-
-from UT_Predictor import *
-import random
-
-import mlvp
-import logging
-
-import mlvp.funcov as fc
-from mlvp.reporter import *
-
-import asyncio
-
-import test_bpu_sanity as bpu
-
-"""
-#######Usr function #######
-"""
-
-def cfg_ftq_entry_value_for_uftb(dut: DUTPredictor):
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid.value = 0b1
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset.value= 0xA
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower.value	= 0xABC
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat.value = 0x3
-#	dut.io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing = 0
-
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid.value	= 0x1
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset.value 	= 0xB
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower.value 	= 0xCCCCC
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat.value	= 0x2
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing.value	= 0x0
-
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_pftAddr.value 	= 0xC
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_carry.value 	= 0x0
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0.value 	= 0x1
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1.value 	= 0x1
-	dut.io_ftq_to_bpu_update_bits_br_taken_mask_0.value = 0x1
-	dut.io_ftq_to_bpu_update_bits_br_taken_mask_1.value = 0x1
-#	dut.io_ftq_to_bpu_update_bits_ftb_entry_isCall= 0x1
-#	dut.io_ftq_to_bpu_update_bits_ftb_entry_isRet = 0x1
-#	dut.io_ftq_to_bpu_update_bits_ftb_entry_isJalr= 0x1
-#	dut.io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call = 0x1
-
-async def bpu_sub_uftb_enable_test(dut: DUTPredictor):
-	await dut.AStep(2050)
-	dut.reset.value = 1
-	await dut.AStep(2)
-	dut.reset.value = 0
-	for i in range(32):
-		dut.io_ftq_to_bpu_update_valid.value = 1
-		dut.io_ftq_to_bpu_update_bits_pc.value = 0x1000 + 0x20 * i
-		cfg_ftq_entry_value_for_uftb(dut)
-		await dut.AStep(1)
-
-	dut.io_ftq_to_bpu_update_valid.value = 0
-	await dut.AStep(1)
-	await dut.AStep(2050)
-#	await dut.AStep(2100)
-	dut.io_ftq_to_bpu_update_valid.value = 1
-	dut.io_ftq_to_bpu_update_bits_pc.value = 0x1200
-	await dut.AStep(1)
-	dut.io_ftq_to_bpu_update_valid.value = 0
-	dut.io_ftq_to_bpu_update_bits_pc.value = 0x0000
-	await dut.AStep(1)
-	#The second the update PC
-	dut.io_ftq_to_bpu_update_valid.value = 1
-	dut.io_ftq_to_bpu_update_bits_pc.value = 0x1080
-	await dut.AStep(1)
-	dut.io_ftq_to_bpu_update_valid.value = 0
-	dut.io_ftq_to_bpu_update_bits_pc.value = 0x0000
-	await dut.AStep(1)
-	#The third the update PC
-	dut.io_ftq_to_bpu_update_valid.value = 1
-	dut.io_ftq_to_bpu_update_bits_pc.value = 0x1180
-	await dut.AStep(1)
-	dut.io_ftq_to_bpu_update_valid.value = 0
-	dut.io_ftq_to_bpu_update_bits_pc.value = 0x0000
-	await dut.AStep(1)
-
-#	dut.io_ctrl_ubtb_enable.value = 0
-
-async def main():
-	dut: DUTPredictor = DUTPredictor(
-		waveform_filename="report/BPUTop.fst", coverage_filename="report/BPUTop_coverage.dat")
-#	print(TEST_PATH)
-	print("Init DUT is OK!!!")
-	dut.InitClock("clock")
-#	task = asyncio.create_task(dut.RunStep(2100))	#create a async task
-	task = asyncio.create_task(dut.RunStep(5000))	#create a async task
-	task_cfg_default = asyncio.create_task(bpu.cfg_default(dut))
-	task_test_bpu_sub_uftb_enable = asyncio.create_task(bpu_sub_uftb_enable_test(dut))
-
-
-	#TEST Here
-	await task_test_bpu_sub_uftb_enable
-
-	#Finish
-	await task_cfg_default
-	await task
-	dut.Finish()
-	print("test_bpu_sanity() exec over!!!")
-
-
-def test_bpu_sub_uftb_enable():
-	asyncio.run(main())
-
-if __name__ == "__main__":
-	asyncio.run(main())
-	
diff --git a/tests/bpu_top/test_bpu_sub_uftb_enable_disable.py b/tests/bpu_top/test_bpu_sub_uftb_enable_disable.py
deleted file mode 100644
index bbe4a99..0000000
--- a/tests/bpu_top/test_bpu_sub_uftb_enable_disable.py
+++ /dev/null
@@ -1,121 +0,0 @@
-from config import *
-
-import os
-os.sys.path.append(TESTS_PATH)
-os.sys.path.append(DUT_PATH)
-
-from UT_Predictor import *
-import random
-
-import mlvp
-import logging
-
-import mlvp.funcov as fc
-from mlvp.reporter import *
-
-import asyncio
-
-import test_bpu_sanity as bpu
-
-
-"""
-#######Usr function #######
-"""
-
-def cfg_ftq_entry_value_for_uftb(dut: DUTPredictor):
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid.value = 0b1
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset.value= 0xA
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower.value	= 0xABC
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat.value = 0x3
-#	dut.io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing = 0
-
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid.value	= 0x1
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset.value 	= 0xB
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower.value 	= 0xCCCCC
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat.value	= 0x2
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing.value	= 0x0
-
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_pftAddr.value 	= 0xC
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_carry.value 	= 0x0
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0.value 	= 0x1
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1.value 	= 0x1
-	dut.io_ftq_to_bpu_update_bits_br_taken_mask_0.value = 0x1
-	dut.io_ftq_to_bpu_update_bits_br_taken_mask_1.value = 0x1
-#	dut.io_ftq_to_bpu_update_bits_ftb_entry_isCall= 0x1
-#	dut.io_ftq_to_bpu_update_bits_ftb_entry_isRet = 0x1
-#	dut.io_ftq_to_bpu_update_bits_ftb_entry_isJalr= 0x1
-#	dut.io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call = 0x1
-
-async def bpu_sub_uftb_enable_disable_test(dut: DUTPredictor):
-	await dut.AStep(2050)
-	dut.reset.value = 1
-	await dut.AStep(2)
-	dut.reset.value = 0
-	for i in range(32):
-		dut.io_ftq_to_bpu_update_valid.value = 1
-		dut.io_ftq_to_bpu_update_bits_pc.value = 0x1000 + 0x20 * i
-		cfg_ftq_entry_value_for_uftb(dut)
-		await dut.AStep(1)
-
-	dut.io_ftq_to_bpu_update_valid.value = 0
-	await dut.AStep(1)
-	await dut.AStep(2050)
-	dut.io_ftq_to_bpu_update_valid.value = 1
-	dut.io_ftq_to_bpu_update_bits_pc.value = 0x1200
-	await dut.AStep(1)
-	dut.io_ftq_to_bpu_update_valid.value = 0
-	dut.io_ftq_to_bpu_update_bits_pc.value = 0x0000
-	await dut.AStep(1)
-	#The second the update PC
-	dut.io_ftq_to_bpu_update_valid.value = 1
-	dut.io_ftq_to_bpu_update_bits_pc.value = 0x1080
-	await dut.AStep(1)
-	dut.io_ftq_to_bpu_update_valid.value = 0
-	dut.io_ftq_to_bpu_update_bits_pc.value = 0x0000
-	await dut.AStep(1)
-
-	##uftb_enable reset
-	dut.io_ctrl_ubtb_enable.value = 0
-	await dut.AStep(1)
-	dut.io_ftq_to_bpu_update_valid.value = 1
-	dut.io_ftq_to_bpu_update_bits_pc.value = 0x1200
-	await dut.AStep(1)
-	dut.io_ftq_to_bpu_update_valid.value = 0
-	dut.io_ftq_to_bpu_update_bits_pc.value = 0x0000
-	await dut.AStep(1)
-	#The second the update PC
-	dut.io_ftq_to_bpu_update_valid.value = 1
-	dut.io_ftq_to_bpu_update_bits_pc.value = 0x1080
-	await dut.AStep(1)
-	dut.io_ftq_to_bpu_update_valid.value = 0
-	dut.io_ftq_to_bpu_update_bits_pc.value = 0x0000
-	await dut.AStep(1)
-#	dut.io_ctrl_ubtb_enable.value = 0
-
-async def main():
-	dut: DUTPredictor = DUTPredictor(
-		waveform_filename="report/BPUTop.fst", coverage_filename="report/BPUTop_coverage.dat")
-#	print(TEST_PATH)
-	print("Init DUT is OK!!!")
-	dut.InitClock("clock")
-#	task = asyncio.create_task(dut.RunStep(2100))	#create a async task
-	task = asyncio.create_task(dut.RunStep(5000))	#create a async task
-	task_cfg_default = asyncio.create_task(bpu.cfg_default(dut))
-	task_test_bpu_sub_uftb_enable_disable = asyncio.create_task(bpu_sub_uftb_enable_disable_test(dut))
-
-
-	#TEST Here
-	await task_test_bpu_sub_uftb_enable_disable
-
-	#Finish
-	await task_cfg_default
-	await task
-	dut.Finish()
-	print("test_bpu_sanity() exec over!!!")
-
-def	test_bpu_sub_uftb_enable_disable():
-	asyncio.run(main())
-
-if __name__ == "__main__":
-	asyncio.run(main())
-	
diff --git a/tests/bpu_top/test_bpu_sub_uftb_entry_way_resp_hit.py b/tests/bpu_top/test_bpu_sub_uftb_entry_way_resp_hit.py
deleted file mode 100644
index de46d33..0000000
--- a/tests/bpu_top/test_bpu_sub_uftb_entry_way_resp_hit.py
+++ /dev/null
@@ -1,99 +0,0 @@
-from config import *
-
-import os
-os.sys.path.append(TESTS_PATH)
-os.sys.path.append(DUT_PATH)
-
-from UT_Predictor import *
-import random
-
-import mlvp
-import logging
-
-import mlvp.funcov as fc
-from mlvp.reporter import *
-
-import asyncio
-
-import test_bpu_sanity as bpu
-
-
-"""
-#######Usr function #######
-"""
-
-def cfg_ftq_entry_value_for_uftb(dut: DUTPredictor):
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid.value = 0b1
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset.value= 0xA
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower.value	= 0xABC
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat.value = 0x3
-#	dut.io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing = 0
-
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid.value	= 0x1
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset.value 	= 0xB
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower.value 	= 0xCCCCC
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat.value	= 0x2
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing.value	= 0x0
-
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_pftAddr.value 	= 0xC
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_carry.value 	= 0x0
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0.value 	= 0x1
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1.value 	= 0x1
-	dut.io_ftq_to_bpu_update_bits_br_taken_mask_0.value = 0x1
-	dut.io_ftq_to_bpu_update_bits_br_taken_mask_1.value = 0x1
-#	dut.io_ftq_to_bpu_update_bits_ftb_entry_isCall= 0x1
-#	dut.io_ftq_to_bpu_update_bits_ftb_entry_isRet = 0x1
-#	dut.io_ftq_to_bpu_update_bits_ftb_entry_isJalr= 0x1
-#	dut.io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call = 0x1
-
-async def bpu_sub_uftb_entry_way_resp_hit_test(dut: DUTPredictor):
-	await dut.AStep(2050)
-	dut.reset.value = 1
-	await dut.AStep(2)
-	dut.reset.value = 0
-	for i in range(32):
-		dut.io_ftq_to_bpu_update_valid.value = 1
-		dut.io_ftq_to_bpu_update_bits_pc.value = 0x1000 + 0x20 * i
-		cfg_ftq_entry_value_for_uftb(dut)
-		await dut.AStep(1)
-
-	dut.io_ftq_to_bpu_update_valid.value = 0
-	await dut.AStep(1)
-	await dut.AStep(2050)
-#	await dut.AStep(2100)
-	dut.io_ftq_to_bpu_update_valid.value = 1
-	dut.io_ftq_to_bpu_update_bits_pc.value = 0x1200
-	await dut.AStep(1)
-	dut.io_ftq_to_bpu_update_valid.value = 0
-	dut.io_ftq_to_bpu_update_bits_pc.value = 0x0000
-	await dut.AStep(1)
-
-#	dut.io_ctrl_ubtb_enable.value = 0
-
-async def main():
-	dut: DUTPredictor = DUTPredictor(
-		waveform_filename="report/BPUTop.fst", coverage_filename="report/BPUTop_coverage.dat")
-#	print(TEST_PATH)
-	print("Init DUT is OK!!!")
-	dut.InitClock("clock")
-#	task = asyncio.create_task(dut.RunStep(2100))	#create a async task
-	task = asyncio.create_task(dut.RunStep(5000))	#create a async task
-	task_cfg_default = asyncio.create_task(bpu.cfg_default(dut))
-	task_test_bpu_sub_uftb_entry_way_resp_hit = asyncio.create_task(bpu_sub_uftb_entry_way_resp_hit_test(dut))
-
-
-	#TEST Here
-	await task_test_bpu_sub_uftb_entry_way_resp_hit
-
-	#Finish
-	await task_cfg_default
-	await task
-	dut.Finish()
-	print("test_bpu_sanity() exec over!!!")
-
-def test_bpu_sub_uftb_entry_way_resp_hit():
-	asyncio.run(main())
-
-if __name__ == "__main__":
-	asyncio.run(main())
-	
diff --git a/tests/bpu_top/test_bpu_sub_uftb_entry_way_update_hit.py b/tests/bpu_top/test_bpu_sub_uftb_entry_way_update_hit.py
deleted file mode 100644
index 66bd02c..0000000
--- a/tests/bpu_top/test_bpu_sub_uftb_entry_way_update_hit.py
+++ /dev/null
@@ -1,93 +0,0 @@
-from config import *
-
-import os
-os.sys.path.append(TESTS_PATH)
-os.sys.path.append(DUT_PATH)
-
-from UT_Predictor import *
-import random
-
-import mlvp
-import logging
-
-import mlvp.funcov as fc
-from mlvp.reporter import *
-
-import asyncio
-
-import test_bpu_sanity as bpu
-
-"""
-#######Usr function #######
-"""
-
-def cfg_ftq_entry_value_for_uftb(dut: DUTPredictor):
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid.value = 0b1
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset.value= 0xA
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower.value	= 0xABC
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat.value = 0x3
-#	dut.io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing = 0
-
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid.value	= 0x1
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset.value 	= 0xB
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower.value 	= 0xCCCCC
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat.value	= 0x2
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing.value	= 0x0
-
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_pftAddr.value 	= 0xC
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_carry.value 	= 0x0
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0.value 	= 0x1
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1.value 	= 0x1
-	dut.io_ftq_to_bpu_update_bits_br_taken_mask_0.value = 0x1
-	dut.io_ftq_to_bpu_update_bits_br_taken_mask_1.value = 0x1
-#	dut.io_ftq_to_bpu_update_bits_ftb_entry_isCall= 0x1
-#	dut.io_ftq_to_bpu_update_bits_ftb_entry_isRet = 0x1
-#	dut.io_ftq_to_bpu_update_bits_ftb_entry_isJalr= 0x1
-#	dut.io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call = 0x1
-
-async def bpu_sub_uftb_entry_way_update_hit_test(dut: DUTPredictor):
-	await dut.AStep(2050)
-	for i in range(32):
-		dut.io_ftq_to_bpu_update_valid.value = 1
-		dut.io_ftq_to_bpu_update_bits_pc.value = 0x1000 + 0x20 * i
-		cfg_ftq_entry_value_for_uftb(dut)
-		await dut.AStep(1)
-
-	dut.io_ftq_to_bpu_update_valid.value = 0
-	await dut.AStep(100)
-	for i in range(32):
-		dut.io_ftq_to_bpu_update_valid.value = 1
-		dut.io_ftq_to_bpu_update_bits_pc.value = 0x1000 + 0x20 * i
-		cfg_ftq_entry_value_for_uftb(dut)
-		await dut.AStep(1)
-
-#	dut.io_ctrl_ubtb_enable.value = 0
-
-async def main():
-	dut: DUTPredictor = DUTPredictor(
-		waveform_filename="report/BPUTop.fst", coverage_filename="report/BPUTop_coverage.dat")
-#	print(TEST_PATH)
-	print("Init DUT is OK!!!")
-	dut.InitClock("clock")
-#	task = asyncio.create_task(dut.RunStep(2100))	#create a async task
-	task = asyncio.create_task(dut.RunStep(5000))	#create a async task
-	task_cfg_default = asyncio.create_task(bpu.cfg_default(dut))
-	task_test_bpu_sub_uftb_entry_way_update_hit = asyncio.create_task(bpu_sub_uftb_entry_way_update_hit_test(dut))
-
-
-	#TEST Here
-	await task_test_bpu_sub_uftb_entry_way_update_hit
-
-	#Finish
-	await task_cfg_default
-	await task
-	dut.Finish()
-
-	print("test_bpu_sanity() exec over!!!")
-
-def test_bpu_sub_uftb_entry_way_update_hit():
-	asyncio.run(main())
-
-if __name__ == "__main__":
-	asyncio.run(main())
-	
diff --git a/tests/bpu_top/test_bpu_sub_uftb_ready.py b/tests/bpu_top/test_bpu_sub_uftb_ready.py
deleted file mode 100644
index ebfc989..0000000
--- a/tests/bpu_top/test_bpu_sub_uftb_ready.py
+++ /dev/null
@@ -1,87 +0,0 @@
-from config import *
-
-import os
-os.sys.path.append(TESTS_PATH)
-os.sys.path.append(DUT_PATH)
-
-from UT_Predictor import *
-import random
-
-import mlvp
-import logging
-
-import mlvp.funcov as fc
-from mlvp.reporter import *
-
-import asyncio
-
-import test_bpu_sanity as bpu
-
-"""
-#######Usr function #######
-"""
-
-def cfg_ftq_entry_value_for_uftb(dut: DUTPredictor):
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid.value = 0b1
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset.value= 0xA
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower.value	= 0xABC
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat.value = 0x3
-#	dut.io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing = 0
-
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid.value	= 0x1
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset.value 	= 0xB
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower.value 	= 0xCCCCC
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat.value	= 0x2
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing.value	= 0x0
-
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_pftAddr.value 	= 0xC
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_carry.value 	= 0x0
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0.value 	= 0x1
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1.value 	= 0x1
-	dut.io_ftq_to_bpu_update_bits_br_taken_mask_0.value = 0x1
-	dut.io_ftq_to_bpu_update_bits_br_taken_mask_1.value = 0x1
-#	dut.io_ftq_to_bpu_update_bits_ftb_entry_isCall= 0x1
-#	dut.io_ftq_to_bpu_update_bits_ftb_entry_isRet = 0x1
-#	dut.io_ftq_to_bpu_update_bits_ftb_entry_isJalr= 0x1
-#	dut.io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call = 0x1
-
-async def bpu_sub_uftb_ready_test(dut: DUTPredictor):
-	await dut.AStep(2050)
-
-	dut.io_bpu_to_ftq_resp_ready.value = 0
-	await dut.AStep(100)
-	dut.io_bpu_to_ftq_resp_ready.value = 1
-	await dut.AStep(100)
-	dut.io_bpu_to_ftq_resp_ready.value = 0
-	await dut.AStep(100)
-	
-
-#	dut.io_ctrl_ubtb_enable.value = 0
-
-async def main():
-	dut: DUTPredictor = DUTPredictor(
-		waveform_filename="report/BPUTop.fst", coverage_filename="report/BPUTop_coverage.dat")
-#	print(TEST_PATH)
-	print("Init DUT is OK!!!")
-	dut.InitClock("clock")
-#	task = asyncio.create_task(dut.RunStep(2100))	#create a async task
-	task = asyncio.create_task(dut.RunStep(5000))	#create a async task
-	task_cfg_default = asyncio.create_task(bpu.cfg_default(dut))
-	task_test_bpu_sub_uftb_ready = asyncio.create_task(bpu_sub_uftb_ready_test(dut))
-
-
-	#TEST Here
-	await task_test_bpu_sub_uftb_ready
-
-	#Finish
-	await task_cfg_default
-	await task
-	dut.Finish()
-	print("mian() exec over!!!")
-
-def test_bpu_sub_uftb_ready():
-	asyncio.run(main())
-
-if __name__ == "__main__":
-	asyncio.run(main())
-	
diff --git a/tests/bpu_top/test_bpu_sub_uftb_reset.py b/tests/bpu_top/test_bpu_sub_uftb_reset.py
deleted file mode 100644
index db77023..0000000
--- a/tests/bpu_top/test_bpu_sub_uftb_reset.py
+++ /dev/null
@@ -1,99 +0,0 @@
-from config import *
-
-import os
-os.sys.path.append(TESTS_PATH)
-os.sys.path.append(DUT_PATH)
-
-from UT_Predictor import *
-import random
-
-import mlvp
-import logging
-
-import mlvp.funcov as fc
-from mlvp.reporter import *
-
-import asyncio
-
-import test_bpu_sanity as bpu
-
-"""
-#######Usr function #######
-"""
-
-def cfg_ftq_entry_value_for_uftb(dut: DUTPredictor):
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid.value = 0b1
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset.value= 0xA
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower.value	= 0xABC
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat.value = 0x3
-#	dut.io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing = 0
-
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid.value	= 0x1
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset.value 	= 0xB
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower.value 	= 0xCCCCC
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat.value	= 0x2
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing.value	= 0x0
-
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_pftAddr.value 	= 0xC
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_carry.value 	= 0x0
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0.value 	= 0x1
-	dut.io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1.value 	= 0x1
-	dut.io_ftq_to_bpu_update_bits_br_taken_mask_0.value = 0x1
-	dut.io_ftq_to_bpu_update_bits_br_taken_mask_1.value = 0x1
-#	dut.io_ftq_to_bpu_update_bits_ftb_entry_isCall= 0x1
-#	dut.io_ftq_to_bpu_update_bits_ftb_entry_isRet = 0x1
-#	dut.io_ftq_to_bpu_update_bits_ftb_entry_isJalr= 0x1
-#	dut.io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call = 0x1
-
-async def bpu_sub_uftb_reset_test(dut: DUTPredictor):
-	await dut.AStep(2050)
-	dut.reset.value = 1
-	await dut.AStep(4)
-	dut.reset.value = 0
-	for i in range(32):
-		dut.io_ftq_to_bpu_update_valid.value = 1
-		dut.io_ftq_to_bpu_update_bits_pc.value = 0x1000 + 0x20 * i
-		cfg_ftq_entry_value_for_uftb(dut)
-		await dut.AStep(1)
-
-	dut.io_ftq_to_bpu_update_valid.value = 0
-	await dut.AStep(1)
-	await dut.AStep(2050)
-	dut.reset.value = 1
-#	await dut.AStep(2100)
-	dut.io_ftq_to_bpu_update_valid.value = 1
-	dut.io_ftq_to_bpu_update_bits_pc.value = 0x1200
-	await dut.AStep(1)
-	dut.io_ftq_to_bpu_update_valid.value = 0
-	dut.io_ftq_to_bpu_update_bits_pc.value = 0x0000
-	await dut.AStep(1)
-
-#	dut.io_ctrl_ubtb_enable.value = 0
-
-async def main():
-	dut: DUTPredictor = DUTPredictor(
-		waveform_filename="report/BPUTop.fst", coverage_filename="report/BPUTop_coverage.dat")
-#	print(TEST_PATH)
-	print("Init DUT is OK!!!")
-	dut.InitClock("clock")
-#	task = asyncio.create_task(dut.RunStep(2100))	#create a async task
-	task = asyncio.create_task(dut.RunStep(5000))	#create a async task
-	task_cfg_default = asyncio.create_task(bpu.cfg_default(dut))
-	task_bpu_sub_uftb_reset_test = asyncio.create_task(bpu_sub_uftb_reset_test(dut))
-
-
-	#TEST Here
-	await task_bpu_sub_uftb_reset_test
-
-	#Finish
-	await task_cfg_default
-	await task
-	dut.Finish()
-	print("mian() exec over!!!")
-
-def test_bpu_sub_uftb_reset():
-	asyncio.run(main())
-
-if __name__ == "__main__":
-	asyncio.run(main())
-	
diff --git a/tests/bpu_top/test_bpu_reset_true.py b/tests/bpu_top/tests/test_bpu_reset_true.py
similarity index 100%
rename from tests/bpu_top/test_bpu_reset_true.py
rename to tests/bpu_top/tests/test_bpu_reset_true.py
diff --git a/tests/bpu_top/test_bpu_reset_vector.py b/tests/bpu_top/tests/test_bpu_reset_vector.py
similarity index 100%
rename from tests/bpu_top/test_bpu_reset_vector.py
rename to tests/bpu_top/tests/test_bpu_reset_vector.py
diff --git a/tests/bpu_top/tests/test_bpu_sub_ftb_sanity.py b/tests/bpu_top/tests/test_bpu_sub_ftb_sanity.py
new file mode 100644
index 0000000..da6ac63
--- /dev/null
+++ b/tests/bpu_top/tests/test_bpu_sub_ftb_sanity.py
@@ -0,0 +1,22 @@
+import os
+CFG_PATH = os.path.dirname(os.path.abspath(__file__))+"/../"
+os.sys.path.append(CFG_PATH)
+from config import *
+os.sys.path.append(FTB_PATH)
+print(FTB_PATH + " !")
+from bpu_dut import *
+
+
+async def ftb_sanity_test():
+	dut: bpu_dut = bpu_dut()
+						# waveform_filename="report/BPUTop.fst", 
+						# coverage_filename="report/BPUTop_coverage.dat")
+
+	print("ftb_sanity_test() exec over!!!")
+	dut.Finish()
+
+def test_ftb_sanity(request):
+	asyncio.run(ftb_sanity_test())
+
+if __name__ == "__main__":
+	asyncio.run(ftb_sanity_test())
diff --git a/tests/bpu_top/tests/test_bpu_top_all.py b/tests/bpu_top/tests/test_bpu_top_all.py
new file mode 100644
index 0000000..99ca134
--- /dev/null
+++ b/tests/bpu_top/tests/test_bpu_top_all.py
@@ -0,0 +1,4996 @@
+"""
+Initialize before the test
+"""
+import os
+ENV_PATH = os.path.dirname(os.path.abspath(__file__))+"/../"
+os.sys.path.append(ENV_PATH)
+from env.config import *
+
+os.sys.path.append(TESTS_PATH)
+os.sys.path.append(DUT_PATH)
+
+import mlvp
+from mlvp import PreRequest
+from UT_Predictor import *
+import random
+
+"""
+Testcase
+"""
+
+from env import *
+from env.bpu_bundle import *
+from env.bpu_agent import *
+from env.bpu_env import *
+
+import pytest
+
+#########################################py test###################
+@pytest.fixture()
+def mlvp_request(mlvp_pre_request: PreRequest):
+	mlvp.setup_logging(mlvp.INFO)
+	dut = mlvp_pre_request.create_dut(DUTPredictor,"clock")
+
+	sub_predi_ctrl_bundle 	= SubPrediCtrlBundle()
+	sub_predi_ctrl_bundle.bind(dut)
+	update_ftb_entry_bundle = Ftq2BpuUpdateFtbEntryBundle()
+	update_ftb_entry_bundle.bind(dut)
+	update_other_bundle	= Ftq2BpuUpdateOtherBundle()
+	update_other_bundle.bind(dut)
+	update_fold_hist_bundle 	= Ftq2BpuUpdateFoldHistBundle()
+	update_fold_hist_bundle.bind(dut)	
+	redirect_other_bundle = Ftq2BpuRedirectOtherBundle()
+	redirect_other_bundle.bind(dut)
+	redirect_hist_fold_bundle = Ftq2BpuRedirectFoldHistBundle()
+	redirect_hist_fold_bundle.bind(dut)
+	redirect_afhob_bundle = Ftq2BpuRedirectAfhobBundle()
+	redirect_afhob_bundle.bind(dut)	
+
+	def start_code():
+		mlvp.start_clock(dut)
+		return BpuEnv(sub_predi_ctrl_bundle, update_ftb_entry_bundle, update_other_bundle, 
+					update_fold_hist_bundle, redirect_other_bundle,redirect_hist_fold_bundle, 
+					redirect_afhob_bundle)	
+
+	return start_code
+
+
+"""
+Way: pytest
+"""
+
+#	below is the pytest
+@pytest.mark.mlvp_async
+async def test_redirect_signals_sanity(mlvp_request):
+	print(mlvp_request)
+	env: BpuEnv = mlvp_request()
+
+	# reset
+	task_clock = mlvp.create_task(env.update_ftb_entry_agent.bundle.step(2200))
+	await env.redirect_other_agent.reset(4)
+	await env.redirect_other_agent.bundle.step(2100)	#for the Initial ram
+	# set value
+	print("begin exec test_redirect_signals_sanity test")
+
+	redirect_other_dict = {
+		'level'					: 1,
+		'cfiUpdate_pc'			: 0x1000,
+		'cfiUpdate_pd_isRVC'	: 1,
+		'cfiUpdate_pd_isCall'	: 1,
+		'cfiUpdate_pd_isRet'	: 1,
+		'cfiUpdate_ssp'			: 1,
+		'cfiUpdate_sctr'		: 1,
+		'cfiUpdate_TOSW_flag'	: 1,
+		'cfiUpdate_TOSW_value'	: 1,
+		'cfiUpdate_TOSR_flag'	: 1,
+		'cfiUpdate_TOSR_value'	: 1,
+		'cfiUpdate_NOS_flag'	: 1,
+		'cfiUpdate_NOS_value'	: 1,
+
+		'cfiUpdate_lastBrNumOH'	: 1, 
+		'cfiUpdate_histPtr_flag': 1, 
+		'cfiUpdate_histPtr_value':1, 
+		'cfiUpdate_target'		: 1,
+		'cfiUpdate_taken'		: 1,
+		'cfiUpdate_shift'		: 1,
+		'cfiUpdate_addIntoHist'	: 1
+	}
+
+	await env.redirect_other_agent.set_redirect_other_value(redirect_other_dict)
+	await task_clock
+
+	print("test_update_signals_sanity IS OVER")
+
+@pytest.mark.mlvp_async
+async def test_normal_sanity(mlvp_request):
+	print(mlvp_request)
+	env: BpuEnv = mlvp_request()
+
+	# reset
+	task_clock = mlvp.create_task(env.update_ftb_entry_agent.bundle.step(2200))
+	await env.redirect_other_agent.reset(4)
+	await env.sub_predi_ctrl_agent.set_sub_predic_ctrl_en()
+	await env.redirect_other_agent.bundle.step(2100)	#for the Initial ram
+	# set value
+	print("begin exec test_redirect_signals_sanity test")
+
+	await task_clock
+	print("test_normal_sanity IS OVER")
+
+
+
+##############################################update#############
+@pytest.mark.mlvp_async
+async def test_normal_update_cfi_sanity(mlvp_request):
+	print(mlvp_request)
+	env: BpuEnv = mlvp_request()
+
+	# reset
+	task_clock = mlvp.create_task(env.update_ftb_entry_agent.bundle.step(2200))
+	await env.redirect_other_agent.reset(4)
+	await env.sub_predi_ctrl_agent.set_sub_predic_ctrl_en()
+	await env.redirect_other_agent.bundle.step(2100)	#for the Initial ram
+	# set value
+	print("begin exec test_redirect_signals_sanity test")
+
+	update_pc = 0x1280
+	task_update_ftb_entry = mlvp.create_task(env.update_ftb_entry_agent.set_update_ftb_entry_value(update_pc))
+	task_update_other = mlvp.create_task(env.update_other_agent.set_update_other_value(update_pc))
+	task_update_fold_hist = mlvp.create_task(env.update_fold_hist_agent.set_update_fold_hist_value(update_pc))
+
+	await task_update_ftb_entry 
+	await task_update_other
+	await task_update_fold_hist
+
+	await task_clock
+	print("test_normal_sanity IS OVER")
+
+@pytest.mark.mlvp_async
+async def test_normal_redirect_cfi_sanity(mlvp_request):
+	print(mlvp_request)
+	env: BpuEnv = mlvp_request()
+	update_pc = 0x1280
+
+	# reset
+	task_clock = mlvp.create_task(env.update_ftb_entry_agent.bundle.step(2200))
+	await env.redirect_other_agent.reset(4)
+	await env.sub_predi_ctrl_agent.set_sub_predic_ctrl_en()
+	await env.redirect_other_agent.bundle.step(2100)	#for the Initial ram
+	# set value
+	print("begin exec test_redirect_cfi_sanity test")
+
+#	await env.redirect_other_agent.set_redirect_other_value()
+	task_redirect_other 	= mlvp.create_task(env.redirect_other_agent.set_redirect_other_value())
+	task_redirect_fold_hist = mlvp.create_task(env.redirect_fold_hist_agent.set_redirect_fold_hist_value())
+	task_redirect_afhob 	= mlvp.create_task(env.redirect_afhob_agent.set_redirect_afhob_value())
+
+	await task_redirect_other 
+	await task_redirect_fold_hist
+	await task_redirect_afhob
+
+	await env.redirect_other_agent.bundle.step(1)
+
+	task_redirect_other 	= mlvp.create_task(env.redirect_other_agent.set_redirect_other_value())
+	task_redirect_fold_hist = mlvp.create_task(env.redirect_fold_hist_agent.set_redirect_fold_hist_value())
+	task_redirect_afhob 	= mlvp.create_task(env.redirect_afhob_agent.set_redirect_afhob_value())
+
+	await task_redirect_other 
+	await task_redirect_fold_hist
+	await task_redirect_afhob
+
+#	await env.redirect_afhob_agent.set_redirect_afhob_value()
+
+	await task_clock
+	print("test_normal_sanity IS OVER")
+
+
+######################################################################################
+"""
+Way-2: pytest
+"""
+@pytest.mark.mlvp_async
+async def test_update_signals_sanity(mlvp_request):
+	print(mlvp_request)
+	env: BpuEnv = mlvp_request()
+	update_pc = 0x1248
+
+	# rese
+	task_clock = mlvp.create_task(env.update_ftb_entry_agent.bundle.step(2200))
+	await env.update_ftb_entry_agent.reset(4)
+	await env.update_ftb_entry_agent.bundle.step(2100)
+	# set value
+	print("begin exec test_update_signals_sanity test")
+
+	update_ftb_entry_dict = {
+		'ftb_entry_valid'	: 1,
+		'tailSlot_valid'	: 1,
+		'tailSlot_tarStat'	: 0b10,
+		'tailSlot_sharing'	: 1,
+		'tailSlot_offset'	: 0b0100,
+		'tailSlot_lower'	: 0x20,
+		'pftAddr'			: 0b1000,
+		'may_be_rvi_call'	: 1,
+		'isRet'				: 1,
+		'isJalr'			: 1,
+		'isCall'			: 1,
+		'carry'				: 1,
+		'always_taken_0'	: 1,
+		'always_taken_1'	: 1,
+		'brSlots_0_valid'	: 1,
+		'brSlots_0_tarStat' : 0b10,
+		'brSlots_0_sharing'	: 1,
+		'brSlots_0_offset'	: 0b0100,
+		'brSlots_0_lower'	: 0x200
+	}
+	## update_other_signals
+	update_other_dict = {
+		'cfi_idx_valid'		: 1,
+		'cfi_idx_bits'		: 0b1000,
+		'br_taken_mask_0'	: 1,
+		'br_taken_mask_1'	: 1,
+		'jmp_taken'			: 1,
+		'mispred_mask_0'	: 1,
+		'mispred_mask_1'	: 1,
+		'mispred_mask_2'	: 1,
+		'old_entry'			: 1,
+		'meta'				: 1,
+		'full_target'		: 1
+	}
+	## This is Serial exec
+#	await env.update_ftb_entry_agent.set_update_ftb_entry_value(update_ftb_entry_dict)
+#	await env.update_other_agent.set_update_other_value(update_other_dict)
+
+	## This is Parrel exec
+	task_update_ftb_entry 	= mlvp.create_task(env.update_ftb_entry_agent.set_update_ftb_entry_value(update_pc,update_ftb_entry_dict)) 
+	task_update_other 		= mlvp.create_task(env.update_other_agent.set_update_other_value(update_pc,update_other_dict))
+
+	await task_update_ftb_entry
+	await task_update_other
+
+	await task_clock
+	print("test_update_signals_sanity IS OVER")
+
+
+@pytest.mark.mlvp_async
+async def test_update_fold_hist_sanity(mlvp_request):
+	print(mlvp_request)
+	env: BpuEnv = mlvp_request()
+	update_pc = 0x1248
+
+	# rese
+	task_clock = mlvp.create_task(env.update_ftb_entry_agent.bundle.step(2200))
+	await env.update_ftb_entry_agent.reset(4)
+	await env.update_ftb_entry_agent.bundle.step(2100)
+	print("begin exec test_update_fold_hist_sanity test")
+
+	update_fold_hist_dict = {
+		'folded_hist_1' 	: 0b1000,
+		'folded_hist_2' 	: 0b1001,
+		'folded_hist_3' 	: 0b1010,
+		'folded_hist_4' 	: 0b1100,
+		'folded_hist_5' 	: 0b0001,
+		'folded_hist_6' 	: 0b0000,
+		'folded_hist_7' 	: 0b0001,
+		'folded_hist_8' 	: 0b0010,
+		'folded_hist_9' 	: 0b0100,
+		'folded_hist_10' 	: 0b1000,
+		'folded_hist_11' 	: 0b1100,
+		'folded_hist_12' 	: 0b1110,
+		'folded_hist_13' 	: 0b1111,
+		'folded_hist_14' 	: 0b0000,
+		'folded_hist_15' 	: 0b1111,
+		'folded_hist_16' 	: 0b1001,
+		'folded_hist_17' 	: 0b1001
+	}
+	await env.update_fold_hist_agent.set_update_fold_hist_value(update_pc,update_fold_hist_dict)
+
+	await task_clock
+	print("test_update_signals_sanity IS OVER")
+
+
+@pytest.mark.mlvp_async
+async def test_update_FtbEntry_foldHist_once_signals(mlvp_request):
+	print(mlvp_request)
+	env: BpuEnv = mlvp_request()
+	update_pc = 0x1248
+
+	# rese
+	task_clock = mlvp.create_task(env.update_ftb_entry_agent.bundle.step(2200))
+	await env.update_ftb_entry_agent.reset(4)
+	await env.update_ftb_entry_agent.bundle.step(2100)
+	print("begin exec test_update_fold_hist_sanity test")
+
+	update_ftb_entry_dict = {
+		'ftb_entry_valid'	: 1,
+		'tailSlot_valid'	: 1,
+		'tailSlot_tarStat'	: 0b10,
+		'tailSlot_sharing'	: 1,
+		'tailSlot_offset'	: 0b0100,
+		'tailSlot_lower'	: 0x20,
+		'pftAddr'			: 0b1000,
+		'may_be_rvi_call'	: 1,
+		'isRet'				: 1,
+		'isJalr'			: 1,
+		'isCall'			: 1,
+		'carry'				: 1,
+		'always_taken_0'	: 1,
+		'always_taken_1'	: 1,
+		'brSlots_0_valid'	: 1,
+		'brSlots_0_tarStat' : 0b10,
+		'brSlots_0_sharing'	: 1,
+		'brSlots_0_offset'	: 0b0100,
+		'brSlots_0_lower'	: 0x200
+	}
+	## update_other_signals
+	update_other_dict = {
+		'cfi_idx_valid'		: 1,
+		'cfi_idx_bits'		: 0b1000,
+		'br_taken_mask_0'	: 1,
+		'br_taken_mask_1'	: 1,
+		'jmp_taken'			: 1,
+		'mispred_mask_0'	: 1,
+		'mispred_mask_1'	: 1,
+		'mispred_mask_2'	: 1,
+		'old_entry'			: 1,
+		'meta'				: 1,
+		'full_target'		: 1
+	}
+
+	update_fold_hist_dict = {
+		'folded_hist_1' 	: 0b1000,
+		'folded_hist_2' 	: 0b1001,
+		'folded_hist_3' 	: 0b1010,
+		'folded_hist_4' 	: 0b1100,
+		'folded_hist_5' 	: 0b0001,
+		'folded_hist_6' 	: 0b0000,
+		'folded_hist_7' 	: 0b0001,
+		'folded_hist_8' 	: 0b0010,
+		'folded_hist_9' 	: 0b0100,
+		'folded_hist_10' 	: 0b1000,
+		'folded_hist_11' 	: 0b1100,
+		'folded_hist_12' 	: 0b1110,
+		'folded_hist_13' 	: 0b1111,
+		'folded_hist_14' 	: 0b0000,
+		'folded_hist_15' 	: 0b1111,
+		'folded_hist_16' 	: 0b1001,
+		'folded_hist_17' 	: 0b1001
+	}
+
+	task_update_ftb_entry 	= mlvp.create_task(env.update_ftb_entry_agent.set_update_ftb_entry_value(update_pc,update_ftb_entry_dict)) 
+	task_update_other 		= mlvp.create_task(env.update_other_agent.set_update_other_value(update_pc,update_other_dict))
+	task_update_foldedHist 	= mlvp.create_task(env.update_fold_hist_agent.set_update_fold_hist_value(update_pc,update_fold_hist_dict))
+
+	await task_update_ftb_entry
+	await task_update_other
+	await task_update_foldedHist
+
+	await task_clock
+	print("test_update_signals_sanity IS OVER")
+
+
+@pytest.mark.mlvp_async
+async def test_update_FtbEntry_foldHist_twice_signals(mlvp_request):
+	print(mlvp_request)
+	env: BpuEnv = mlvp_request()
+	update_pc = 0x1248
+
+	# rese
+	task_clock = mlvp.create_task(env.update_ftb_entry_agent.bundle.step(2200))
+	await env.update_ftb_entry_agent.reset(4)
+	await env.update_ftb_entry_agent.bundle.step(2100)
+	print("begin exec test_update_fold_hist_sanity test")
+
+	update_ftb_entry_dict = {
+		'ftb_entry_valid'	: 1,
+		'tailSlot_valid'	: 1,
+		'tailSlot_tarStat'	: 0b10,
+		'tailSlot_sharing'	: 1,
+		'tailSlot_offset'	: 0b0100,
+		'tailSlot_lower'	: 0x20,
+		'pftAddr'			: 0b1000,
+		'may_be_rvi_call'	: 1,
+		'isRet'				: 1,
+		'isJalr'			: 1,
+		'isCall'			: 1,
+		'carry'				: 1,
+		'always_taken_0'	: 1,
+		'always_taken_1'	: 1,
+		'brSlots_0_valid'	: 1,
+		'brSlots_0_tarStat' : 0b10,
+		'brSlots_0_sharing'	: 1,
+		'brSlots_0_offset'	: 0b0100,
+		'brSlots_0_lower'	: 0x200
+	}
+	## update_other_signals
+	update_other_dict = {
+		'cfi_idx_valid'		: 1,
+		'cfi_idx_bits'		: 0b1000,
+		'br_taken_mask_0'	: 1,
+		'br_taken_mask_1'	: 1,
+		'jmp_taken'			: 0,
+		'mispred_mask_0'	: 1,
+		'mispred_mask_1'	: 1,
+		'mispred_mask_2'	: 1,
+		'old_entry'			: 1,
+		'meta'				: 1,
+		'full_target'		: 1
+	}
+
+	update_fold_hist_dict = {
+		'folded_hist_1' 	: 0b1000,
+		'folded_hist_2' 	: 0b1001,
+		'folded_hist_3' 	: 0b1010,
+		'folded_hist_4' 	: 0b1100,
+		'folded_hist_5' 	: 0b0001,
+		'folded_hist_6' 	: 0b0000,
+		'folded_hist_7' 	: 0b0001,
+		'folded_hist_8' 	: 0b0010,
+		'folded_hist_9' 	: 0b0100,
+		'folded_hist_10' 	: 0b1000,
+		'folded_hist_11' 	: 0b1100,
+		'folded_hist_12' 	: 0b1110,
+		'folded_hist_13' 	: 0b1111,
+		'folded_hist_14' 	: 0b0000,
+		'folded_hist_15' 	: 0b1111,
+		'folded_hist_16' 	: 0b1001,
+		'folded_hist_17' 	: 0b1001
+	}
+
+	task_update_ftb_entry 	= mlvp.create_task(env.update_ftb_entry_agent.set_update_ftb_entry_value(update_pc,update_ftb_entry_dict)) 
+	task_update_other 		= mlvp.create_task(env.update_other_agent.set_update_other_value(update_pc,update_other_dict))
+	task_update_foldedHist 	= mlvp.create_task(env.update_fold_hist_agent.set_update_fold_hist_value(update_pc,update_fold_hist_dict))
+
+	await task_update_ftb_entry
+	await task_update_other
+	await task_update_foldedHist
+
+	await env.update_ftb_entry_agent.bundle.step(1)
+
+	update_ftb_entry_dict = {
+		'ftb_entry_valid'	: 1,
+		'tailSlot_valid'	: 1,
+		'tailSlot_tarStat'	: 0b11,
+		'tailSlot_sharing'	: 1,
+		'tailSlot_offset'	: 0b1111,
+		'tailSlot_lower'	: 0x22,
+		'pftAddr'			: 0b1111,
+		'may_be_rvi_call'	: 1,
+		'isRet'				: 1,
+		'isJalr'			: 1,
+		'isCall'			: 1,
+		'carry'				: 1,
+		'always_taken_0'	: 1,
+		'always_taken_1'	: 1,
+		'brSlots_0_valid'	: 1,
+		'brSlots_0_tarStat' : 0b10,
+		'brSlots_0_sharing'	: 1,
+		'brSlots_0_offset'	: 0b0100,
+		'brSlots_0_lower'	: 0x200
+	}
+
+	## update_other_signals
+	update_other_dict = {
+		'cfi_idx_valid'		: 1,
+		'cfi_idx_bits'		: 0b0111,
+		'br_taken_mask_0'	: 1,
+		'br_taken_mask_1'	: 0,
+		'jmp_taken'			: 1,
+		'mispred_mask_0'	: 1,
+		'mispred_mask_1'	: 1,
+		'mispred_mask_2'	: 1,
+		'old_entry'			: 1,
+		'meta'				: 1,
+		'full_target'		: 1
+	}
+
+	update_fold_hist_dict = {
+		'folded_hist_1' 	: 0b1000,
+		'folded_hist_2' 	: 0b1001,
+		'folded_hist_3' 	: 0b1010,
+		'folded_hist_4' 	: 0b1100,
+		'folded_hist_5' 	: 0b0001,
+		'folded_hist_6' 	: 0b0000,
+		'folded_hist_7' 	: 0b0001,
+		'folded_hist_8' 	: 0b0010,
+		'folded_hist_9' 	: 0b0100,
+		'folded_hist_10' 	: 0b1000,
+		'folded_hist_11' 	: 0b1100,
+		'folded_hist_12' 	: 0b1110,
+		'folded_hist_13' 	: 0b1111,
+		'folded_hist_14' 	: 0b0000,
+		'folded_hist_15' 	: 0b1111,
+		'folded_hist_16' 	: 0b1001,
+		'folded_hist_17' 	: 0b1001
+	}
+
+	task_update_ftb_entry_1		= mlvp.create_task(env.update_ftb_entry_agent.set_update_ftb_entry_value(update_pc,update_ftb_entry_dict)) 
+	task_update_other_1 		= mlvp.create_task(env.update_other_agent.set_update_other_value(update_pc,update_other_dict))
+	task_update_foldedHist_1 	= mlvp.create_task(env.update_fold_hist_agent.set_update_fold_hist_value(update_pc,update_fold_hist_dict))
+
+	await task_update_ftb_entry_1
+	await task_update_other_1
+	await task_update_foldedHist_1
+
+	await task_clock
+	print("test_update_signals_sanity IS OVER")
+
+
+###############################sub pridic##########
+"""
+pytest --mlvp-report
+"""
+@pytest.mark.mlvp_async
+async def test_sub_predi_all_enable_reset(mlvp_request):
+	print(mlvp_request)
+	env: BpuEnv = mlvp_request()
+
+	task_clock = mlvp.create_task(env.sub_predi_ctrl_agent.bundle.step(2200))
+	# reset for reset
+	await env.sub_predi_ctrl_agent.reset(2)
+	# set value
+	enable_dict = {
+		'ubtb_en' 	: 1,	
+		'btb_en'	: 1,
+		'tage_en'	: 1,
+		'sc_en'		: 1,
+		'ras_en'	: 1
+	}
+	print("begin exec env test")
+	await env.sub_predi_ctrl_agent.set_sub_predic_ctrl_en(enable_dict)
+	print("test_sub_predi_all_enable Is Over!!!!!!!!!!!!!!!!!!!!!!!")
+
+	await env.sub_predi_ctrl_agent.bundle.step(2100)
+	await env.sub_predi_ctrl_agent.reset(2)
+	await task_clock
+
+
+@pytest.mark.mlvp_async
+async def test_sub_predi_UFTB_disable(mlvp_request):
+	print(mlvp_request)
+	env: BpuEnv = mlvp_request()
+
+	task_clock = mlvp.create_task(env.sub_predi_ctrl_agent.bundle.step(2200))
+	# reset for reset
+	await env.sub_predi_ctrl_agent.reset(2)
+	# set value ==similar to ref 
+	enable_dict = {
+		'ubtb_en' 	: 0,	
+		'btb_en'	: 1,
+		'tage_en'	: 1,
+		'sc_en'		: 1,
+		'ras_en'	: 1
+	}
+	print("begin exec test")
+	await env.sub_predi_ctrl_agent.set_sub_predic_ctrl_en(enable_dict)
+
+	print("test_sub_predi_uftb_enable Is Over!!!!!!!!!!!!!!!!!!!!!!!")
+	await task_clock
+
+@pytest.mark.mlvp_async
+async def test_sub_predi_FTB_disable(mlvp_request):
+	print(mlvp_request)
+	env: BpuEnv = mlvp_request()
+
+	task_clock = mlvp.create_task(env.sub_predi_ctrl_agent.bundle.step(2200))
+	# reset for reset
+	await env.sub_predi_ctrl_agent.reset(2)
+	# set value ==similar to ref 
+
+	enable_dict = {
+		'ubtb_en' 	: 1,	
+		'btb_en'	: 0,
+		'tage_en'	: 1,
+		'sc_en'		: 1,
+		'ras_en'	: 1
+	}
+	await env.sub_predi_ctrl_agent.set_sub_predic_ctrl_en(enable_dict)
+
+	print("test_sub_predi_uftb_enable Is Over!!!!!!!!!!!!!!!!!!!!!!!")
+	await task_clock
+
+
+@pytest.mark.mlvp_async
+async def test_sub_predi_TAGE_disable(mlvp_request):
+	print(mlvp_request)
+	env: BpuEnv = mlvp_request()
+
+	task_clock = mlvp.create_task(env.sub_predi_ctrl_agent.bundle.step(2200))
+	# reset for reset
+	await env.sub_predi_ctrl_agent.reset(2)
+	# set value ==similar to ref 
+
+	enable_dict = {
+		'ubtb_en' 	: 1,	
+		'btb_en'	: 1,
+		'tage_en'	: 0,
+		'sc_en'		: 1,
+		'ras_en'	: 1
+	}
+	await env.sub_predi_ctrl_agent.set_sub_predic_ctrl_en(enable_dict)
+
+	print("test_sub_predi_uftb_enable Is Over!!!!!!!!!!!!!!!!!!!!!!!")
+	await task_clock
+
+@pytest.mark.mlvp_async
+async def test_sub_predi_SC_disable(mlvp_request):
+	print(mlvp_request)
+	env: BpuEnv = mlvp_request()
+
+	task_clock = mlvp.create_task(env.sub_predi_ctrl_agent.bundle.step(2200))
+	# reset for reset
+	await env.sub_predi_ctrl_agent.reset(2)
+	# set value ==similar to ref 
+
+	enable_dict = {
+		'ubtb_en' 	: 1,	
+		'btb_en'	: 1,
+		'tage_en'	: 1,
+		'sc_en'		: 0,
+		'ras_en'	: 1
+	}
+	await env.sub_predi_ctrl_agent.set_sub_predic_ctrl_en(enable_dict)
+
+	print("test_sub_predi_uftb_enable Is Over!!!!!!!!!!!!!!!!!!!!!!!")
+	await task_clock
+
+@pytest.mark.mlvp_async
+async def test_sub_predi_RAS_disable(mlvp_request):
+	print(mlvp_request)
+	env: BpuEnv = mlvp_request()
+
+	task_clock = mlvp.create_task(env.sub_predi_ctrl_agent.bundle.step(2200))
+	# reset for reset
+	await env.sub_predi_ctrl_agent.reset(2)
+	# set value ==similar to ref 
+
+	enable_dict = {
+		'ubtb_en' 	: 1,	
+		'btb_en'	: 1,
+		'tage_en'	: 1,
+		'sc_en'		: 1,
+		'ras_en'	: 0
+	}
+	await env.sub_predi_ctrl_agent.set_sub_predic_ctrl_en(enable_dict)
+	print("test_sub_predi_uftb_enable Is Over!!!!!!!!!!!!!!!!!!!!!!!")
+	await task_clock
+
+
+###############################################ADD ########################
+
+@pytest.mark.mlvp_async
+async def test_normal_redirect_cfi_twice(mlvp_request):
+	print(mlvp_request)
+	env: BpuEnv = mlvp_request()
+	update_pc = 0x1280
+
+	rediretc_ohter_dict = {
+		'level'					: 1,
+		'cfiUpdate_pc'			: 0x1280,
+		'cfiUpdate_pd_isRVC'	: 1,
+		'cfiUpdate_pd_isCall'	: 1,
+		'cfiUpdate_pd_isRet'	: 1,
+		'cfiUpdate_ssp'			: 1,
+		'cfiUpdate_sctr'		: 1,
+		'cfiUpdate_TOSW_flag'	: 1,
+		'cfiUpdate_TOSW_value'	: 1,
+		'cfiUpdate_TOSR_flag'	: 1,
+		'cfiUpdate_TOSR_value'	: 1,
+		'cfiUpdate_NOS_flag'	: 1,
+		'cfiUpdate_NOS_value'	: 1,
+
+		'cfiUpdate_lastBrNumOH'	: 1, 
+		'cfiUpdate_histPtr_flag': 1, 
+		'cfiUpdate_histPtr_value':1, 
+		'cfiUpdate_target'		: 1,
+		'cfiUpdate_taken'		: 1,
+		'cfiUpdate_shift'		: 1,
+		'cfiUpdate_addIntoHist'	: 1
+	}
+
+	redirect_fold_hist_dict = {
+		'cfiUpdate_folded_hist_0'	: 0b100,
+		'cfiUpdate_folded_hist_1'	: 0b100,
+		'cfiUpdate_folded_hist_2'	: 0b100,
+		'cfiUpdate_folded_hist_3'	: 0b100,
+		'cfiUpdate_folded_hist_4'	: 0b100,
+		'cfiUpdate_folded_hist_5'	: 0b100,
+		'cfiUpdate_folded_hist_6'	: 0b100,
+		'cfiUpdate_folded_hist_7'	: 0b100,
+		'cfiUpdate_folded_hist_8'	: 0b100,
+		'cfiUpdate_folded_hist_9'	: 0b100,
+
+		'cfiUpdate_folded_hist_10': 0b100,
+		'cfiUpdate_folded_hist_11': 0b100,
+		'cfiUpdate_folded_hist_12': 0b100,
+		'cfiUpdate_folded_hist_13': 0b100,
+		'cfiUpdate_folded_hist_14': 0b100,
+		'cfiUpdate_folded_hist_15': 0b100,
+		'cfiUpdate_folded_hist_16': 0b100,
+		'cfiUpdate_folded_hist_17': 0b100
+	}
+
+	redirect_afhob_dict = {
+		'afhob_0_bits_0'	: 0b1,
+		'afhob_0_bits_1'	: 0b1,
+		'afhob_0_bits_2'	: 0b1,
+		'afhob_0_bits_3'	: 0b1,
+		'afhob_1_bits_0'	: 0b1,
+		'afhob_1_bits_1'	: 0b1,
+		'afhob_1_bits_2'	: 0b1,
+		'afhob_1_bits_3'	: 0b1,
+		'afhob_2_bits_0'	: 0b1,
+		'afhob_2_bits_1'	: 0b1,
+		'afhob_2_bits_2'	: 0b1,
+		'afhob_2_bits_3'	: 0b1,
+		'afhob_3_bits_0'	: 0b1,
+		'afhob_3_bits_1'	: 0b1,
+		'afhob_3_bits_2'	: 0b1,
+		'afhob_3_bits_3'	: 0b1,
+		'afhob_4_bits_0'	: 0b1,
+		'afhob_4_bits_1'	: 0b1,
+		'afhob_4_bits_2'	: 0b1,
+		'afhob_5_bits_0'	: 0b1,
+		'afhob_5_bits_1'	: 0b1,
+		'afhob_5_bits_2'	: 0b1,
+		'afhob_5_bits_3'	: 0b1
+	}
+
+	# reset
+	task_clock = mlvp.create_task(env.update_ftb_entry_agent.bundle.step(2200))
+	await env.redirect_other_agent.reset(4)
+	await env.redirect_other_agent.bundle.step(2100)	#for the Initial ram
+	# set value
+	print("begin exec test_redirect_cfi_sanity test")
+
+#	await env.redirect_other_agent.set_redirect_other_value()
+	task_redirect_other 	= mlvp.create_task(env.redirect_other_agent.set_redirect_other_value(rediretc_ohter_dict))
+	task_redirect_fold_hist = mlvp.create_task(env.redirect_fold_hist_agent.set_redirect_fold_hist_value(redirect_fold_hist_dict))
+	task_redirect_afhob 	= mlvp.create_task(env.redirect_afhob_agent.set_redirect_afhob_value(redirect_afhob_dict))
+
+	await task_redirect_other 
+	await task_redirect_fold_hist
+	await task_redirect_afhob
+
+	await env.redirect_other_agent.bundle.step(1)
+
+	rediretc_ohter_dict = {
+		'level'					: 1,
+		'cfiUpdate_pc'			: 0x1280,
+		'cfiUpdate_pd_isRVC'	: 1,
+		'cfiUpdate_pd_isCall'	: 1,
+		'cfiUpdate_pd_isRet'	: 0,
+		'cfiUpdate_ssp'			: 1,
+		'cfiUpdate_sctr'		: 0,
+		'cfiUpdate_TOSW_flag'	: 1,
+		'cfiUpdate_TOSW_value'	: 1,
+		'cfiUpdate_TOSR_flag'	: 0,
+		'cfiUpdate_TOSR_value'	: 1,
+		'cfiUpdate_NOS_flag'	: 1,
+		'cfiUpdate_NOS_value'	: 1,
+
+		'cfiUpdate_lastBrNumOH'	: 1, 
+		'cfiUpdate_histPtr_flag': 1, 
+		'cfiUpdate_histPtr_value':0, 
+		'cfiUpdate_target'		: 1,
+		'cfiUpdate_taken'		: 0,
+		'cfiUpdate_shift'		: 1,
+		'cfiUpdate_addIntoHist'	: 1
+	}
+
+	redirect_fold_hist_dict = {
+		'cfiUpdate_folded_hist_0'	: 0b111,
+		'cfiUpdate_folded_hist_1'	: 0b111,
+		'cfiUpdate_folded_hist_2'	: 0b111,
+		'cfiUpdate_folded_hist_3'	: 0b111,
+		'cfiUpdate_folded_hist_4'	: 0b111,
+		'cfiUpdate_folded_hist_5'	: 0b111,
+		'cfiUpdate_folded_hist_6'	: 0b111,
+		'cfiUpdate_folded_hist_7'	: 0b111,
+		'cfiUpdate_folded_hist_8'	: 0b111,
+		'cfiUpdate_folded_hist_9'	: 0b111,
+
+		'cfiUpdate_folded_hist_10': 0b111,
+		'cfiUpdate_folded_hist_11': 0b111,
+		'cfiUpdate_folded_hist_12': 0b111,
+		'cfiUpdate_folded_hist_13': 0b111,
+		'cfiUpdate_folded_hist_14': 0b111,
+		'cfiUpdate_folded_hist_15': 0b111,
+		'cfiUpdate_folded_hist_16': 0b111,
+		'cfiUpdate_folded_hist_17': 0b111
+	}
+
+	redirect_afhob_dict = {
+		'afhob_0_bits_0'	: 0b0,
+		'afhob_0_bits_1'	: 0b0,
+		'afhob_0_bits_2'	: 0b0,
+		'afhob_0_bits_3'	: 0b0,
+		'afhob_1_bits_0'	: 0b0,
+		'afhob_1_bits_1'	: 0b0,
+		'afhob_1_bits_2'	: 0b0,
+		'afhob_1_bits_3'	: 0b0,
+		'afhob_2_bits_0'	: 0b0,
+		'afhob_2_bits_1'	: 0b0,
+		'afhob_2_bits_2'	: 0b0,
+		'afhob_2_bits_3'	: 0b0,
+		'afhob_3_bits_0'	: 0b0,
+		'afhob_3_bits_1'	: 0b0,
+		'afhob_3_bits_2'	: 0b0,
+		'afhob_3_bits_3'	: 0b0,
+		'afhob_4_bits_0'	: 0b0,
+		'afhob_4_bits_1'	: 0b0,
+		'afhob_4_bits_2'	: 0b0,
+		'afhob_5_bits_0'	: 0b0,
+		'afhob_5_bits_1'	: 0b0,
+		'afhob_5_bits_2'	: 0b0,
+		'afhob_5_bits_3'	: 0b0
+	}
+
+	task_redirect_other_1 	= mlvp.create_task(env.redirect_other_agent.set_redirect_other_value(rediretc_ohter_dict))
+	task_redirect_fold_hist_1 = mlvp.create_task(env.redirect_fold_hist_agent.set_redirect_fold_hist_value(redirect_fold_hist_dict))
+	task_redirect_afhob_1 	= mlvp.create_task(env.redirect_afhob_agent.set_redirect_afhob_value(redirect_afhob_dict))
+
+	await task_redirect_other_1 
+	await task_redirect_fold_hist_1
+	await task_redirect_afhob_1
+
+#	await env.redirect_afhob_agent.set_redirect_afhob_value()
+
+	await task_clock
+	print("test_normal_sanity IS OVER")
+
+
+@pytest.mark.mlvp_async
+async def test_normal_redirect_cfi_twice_1(mlvp_request):
+	print(mlvp_request)
+	env: BpuEnv = mlvp_request()
+	update_pc = 0x1280
+
+	# set value
+	enable_dict = {
+		'ubtb_en' 	: 1,	
+		'btb_en'	: 1,
+		'tage_en'	: 1,
+		'sc_en'		: 1,
+		'ras_en'	: 1
+	}
+
+	rediretc_ohter_dict = {
+		'level'					: 1,
+		'cfiUpdate_pc'			: 0x1280,
+		'cfiUpdate_pd_isRVC'	: 1,
+		'cfiUpdate_pd_isCall'	: 1,
+		'cfiUpdate_pd_isRet'	: 1,
+		'cfiUpdate_ssp'			: 1,
+		'cfiUpdate_sctr'		: 1,
+		'cfiUpdate_TOSW_flag'	: 1,
+		'cfiUpdate_TOSW_value'	: 1,
+		'cfiUpdate_TOSR_flag'	: 1,
+		'cfiUpdate_TOSR_value'	: 1,
+		'cfiUpdate_NOS_flag'	: 1,
+		'cfiUpdate_NOS_value'	: 1,
+
+		'cfiUpdate_lastBrNumOH'	: 1, 
+		'cfiUpdate_histPtr_flag': 1, 
+		'cfiUpdate_histPtr_value':1, 
+		'cfiUpdate_target'		: 1,
+		'cfiUpdate_taken'		: 1,
+		'cfiUpdate_shift'		: 1,
+		'cfiUpdate_addIntoHist'	: 1
+	}
+
+	redirect_fold_hist_dict = {
+		'cfiUpdate_folded_hist_0'	: 0b100,
+		'cfiUpdate_folded_hist_1'	: 0b100,
+		'cfiUpdate_folded_hist_2'	: 0b100,
+		'cfiUpdate_folded_hist_3'	: 0b100,
+		'cfiUpdate_folded_hist_4'	: 0b100,
+		'cfiUpdate_folded_hist_5'	: 0b100,
+		'cfiUpdate_folded_hist_6'	: 0b100,
+		'cfiUpdate_folded_hist_7'	: 0b100,
+		'cfiUpdate_folded_hist_8'	: 0b100,
+		'cfiUpdate_folded_hist_9'	: 0b100,
+
+		'cfiUpdate_folded_hist_10': 0b100,
+		'cfiUpdate_folded_hist_11': 0b100,
+		'cfiUpdate_folded_hist_12': 0b100,
+		'cfiUpdate_folded_hist_13': 0b100,
+		'cfiUpdate_folded_hist_14': 0b100,
+		'cfiUpdate_folded_hist_15': 0b100,
+		'cfiUpdate_folded_hist_16': 0b100,
+		'cfiUpdate_folded_hist_17': 0b100
+	}
+
+	redirect_afhob_dict = {
+		'afhob_0_bits_0'	: 0b1,
+		'afhob_0_bits_1'	: 0b1,
+		'afhob_0_bits_2'	: 0b1,
+		'afhob_0_bits_3'	: 0b1,
+		'afhob_1_bits_0'	: 0b1,
+		'afhob_1_bits_1'	: 0b1,
+		'afhob_1_bits_2'	: 0b1,
+		'afhob_1_bits_3'	: 0b1,
+		'afhob_2_bits_0'	: 0b1,
+		'afhob_2_bits_1'	: 0b1,
+		'afhob_2_bits_2'	: 0b1,
+		'afhob_2_bits_3'	: 0b1,
+		'afhob_3_bits_0'	: 0b1,
+		'afhob_3_bits_1'	: 0b1,
+		'afhob_3_bits_2'	: 0b1,
+		'afhob_3_bits_3'	: 0b1,
+		'afhob_4_bits_0'	: 0b1,
+		'afhob_4_bits_1'	: 0b1,
+		'afhob_4_bits_2'	: 0b1,
+		'afhob_5_bits_0'	: 0b1,
+		'afhob_5_bits_1'	: 0b1,
+		'afhob_5_bits_2'	: 0b1,
+		'afhob_5_bits_3'	: 0b1
+	}
+
+	# reset
+	task_clock = mlvp.create_task(env.update_ftb_entry_agent.bundle.step(2200))
+	await env.redirect_other_agent.reset(4)
+	await env.sub_predi_ctrl_agent.set_sub_predic_ctrl_en(enable_dict)
+	await env.redirect_other_agent.bundle.step(2100)	#for the Initial ram
+	# set value
+	print("begin exec test_redirect_cfi_sanity test")
+
+#	await env.redirect_other_agent.set_redirect_other_value()
+	task_redirect_other 	= mlvp.create_task(env.redirect_other_agent.set_redirect_other_value(rediretc_ohter_dict))
+	task_redirect_fold_hist = mlvp.create_task(env.redirect_fold_hist_agent.set_redirect_fold_hist_value(redirect_fold_hist_dict))
+	task_redirect_afhob 	= mlvp.create_task(env.redirect_afhob_agent.set_redirect_afhob_value(redirect_afhob_dict))
+
+	await task_redirect_other 
+	await task_redirect_fold_hist
+	await task_redirect_afhob
+
+	await env.redirect_other_agent.bundle.step(1)
+
+	rediretc_ohter_dict = {
+		'level'					: 1,
+		'cfiUpdate_pc'			: 0x1280,
+		'cfiUpdate_pd_isRVC'	: 1,
+		'cfiUpdate_pd_isCall'	: 1,
+		'cfiUpdate_pd_isRet'	: 0,
+		'cfiUpdate_ssp'			: 1,
+		'cfiUpdate_sctr'		: 0,
+		'cfiUpdate_TOSW_flag'	: 1,
+		'cfiUpdate_TOSW_value'	: 1,
+		'cfiUpdate_TOSR_flag'	: 0,
+		'cfiUpdate_TOSR_value'	: 1,
+		'cfiUpdate_NOS_flag'	: 1,
+		'cfiUpdate_NOS_value'	: 1,
+
+		'cfiUpdate_lastBrNumOH'	: 1, 
+		'cfiUpdate_histPtr_flag': 1, 
+		'cfiUpdate_histPtr_value':0, 
+		'cfiUpdate_target'		: 1,
+		'cfiUpdate_taken'		: 0,
+		'cfiUpdate_shift'		: 1,
+		'cfiUpdate_addIntoHist'	: 1
+	}
+
+	redirect_fold_hist_dict = {
+		'cfiUpdate_folded_hist_0'	: 0b111,
+		'cfiUpdate_folded_hist_1'	: 0b111,
+		'cfiUpdate_folded_hist_2'	: 0b111,
+		'cfiUpdate_folded_hist_3'	: 0b111,
+		'cfiUpdate_folded_hist_4'	: 0b111,
+		'cfiUpdate_folded_hist_5'	: 0b111,
+		'cfiUpdate_folded_hist_6'	: 0b111,
+		'cfiUpdate_folded_hist_7'	: 0b111,
+		'cfiUpdate_folded_hist_8'	: 0b111,
+		'cfiUpdate_folded_hist_9'	: 0b111,
+
+		'cfiUpdate_folded_hist_10': 0b111,
+		'cfiUpdate_folded_hist_11': 0b111,
+		'cfiUpdate_folded_hist_12': 0b111,
+		'cfiUpdate_folded_hist_13': 0b111,
+		'cfiUpdate_folded_hist_14': 0b111,
+		'cfiUpdate_folded_hist_15': 0b111,
+		'cfiUpdate_folded_hist_16': 0b111,
+		'cfiUpdate_folded_hist_17': 0b111
+	}
+
+	redirect_afhob_dict = {
+		'afhob_0_bits_0'	: 0b0,
+		'afhob_0_bits_1'	: 0b0,
+		'afhob_0_bits_2'	: 0b0,
+		'afhob_0_bits_3'	: 0b0,
+		'afhob_1_bits_0'	: 0b0,
+		'afhob_1_bits_1'	: 0b0,
+		'afhob_1_bits_2'	: 0b0,
+		'afhob_1_bits_3'	: 0b0,
+		'afhob_2_bits_0'	: 0b0,
+		'afhob_2_bits_1'	: 0b0,
+		'afhob_2_bits_2'	: 0b0,
+		'afhob_2_bits_3'	: 0b0,
+		'afhob_3_bits_0'	: 0b0,
+		'afhob_3_bits_1'	: 0b0,
+		'afhob_3_bits_2'	: 0b0,
+		'afhob_3_bits_3'	: 0b0,
+		'afhob_4_bits_0'	: 0b0,
+		'afhob_4_bits_1'	: 0b0,
+		'afhob_4_bits_2'	: 0b0,
+		'afhob_5_bits_0'	: 0b0,
+		'afhob_5_bits_1'	: 0b0,
+		'afhob_5_bits_2'	: 0b0,
+		'afhob_5_bits_3'	: 0b0
+	}
+
+	task_redirect_other_1 	= mlvp.create_task(env.redirect_other_agent.set_redirect_other_value(rediretc_ohter_dict))
+	task_redirect_fold_hist_1 = mlvp.create_task(env.redirect_fold_hist_agent.set_redirect_fold_hist_value(redirect_fold_hist_dict))
+	task_redirect_afhob_1 	= mlvp.create_task(env.redirect_afhob_agent.set_redirect_afhob_value(redirect_afhob_dict))
+
+	await task_redirect_other_1 
+	await task_redirect_fold_hist_1
+	await task_redirect_afhob_1
+
+#	await env.redirect_afhob_agent.set_redirect_afhob_value()
+
+	await task_clock
+	print("test_normal_sanity IS OVER")
+
+
+@pytest.mark.mlvp_async
+async def test_normal_redirect_cfi_twice_2(mlvp_request):
+	print(mlvp_request)
+	env: BpuEnv = mlvp_request()
+	update_pc = 0x1280
+
+	# set value
+	enable_dict = {
+		'ubtb_en' 	: 1,	
+		'btb_en'	: 0,
+		'tage_en'	: 1,
+		'sc_en'		: 1,
+		'ras_en'	: 1
+	}
+
+	rediretc_ohter_dict = {
+		'level'					: 1,
+		'cfiUpdate_pc'			: 0x1280,
+		'cfiUpdate_pd_isRVC'	: 1,
+		'cfiUpdate_pd_isCall'	: 1,
+		'cfiUpdate_pd_isRet'	: 1,
+		'cfiUpdate_ssp'			: 1,
+		'cfiUpdate_sctr'		: 1,
+		'cfiUpdate_TOSW_flag'	: 1,
+		'cfiUpdate_TOSW_value'	: 1,
+		'cfiUpdate_TOSR_flag'	: 1,
+		'cfiUpdate_TOSR_value'	: 1,
+		'cfiUpdate_NOS_flag'	: 1,
+		'cfiUpdate_NOS_value'	: 1,
+
+		'cfiUpdate_lastBrNumOH'	: 1, 
+		'cfiUpdate_histPtr_flag': 1, 
+		'cfiUpdate_histPtr_value':1, 
+		'cfiUpdate_target'		: 1,
+		'cfiUpdate_taken'		: 1,
+		'cfiUpdate_shift'		: 1,
+		'cfiUpdate_addIntoHist'	: 1
+	}
+
+	redirect_fold_hist_dict = {
+		'cfiUpdate_folded_hist_0'	: 0b100,
+		'cfiUpdate_folded_hist_1'	: 0b100,
+		'cfiUpdate_folded_hist_2'	: 0b100,
+		'cfiUpdate_folded_hist_3'	: 0b100,
+		'cfiUpdate_folded_hist_4'	: 0b100,
+		'cfiUpdate_folded_hist_5'	: 0b100,
+		'cfiUpdate_folded_hist_6'	: 0b100,
+		'cfiUpdate_folded_hist_7'	: 0b100,
+		'cfiUpdate_folded_hist_8'	: 0b100,
+		'cfiUpdate_folded_hist_9'	: 0b100,
+
+		'cfiUpdate_folded_hist_10': 0b100,
+		'cfiUpdate_folded_hist_11': 0b100,
+		'cfiUpdate_folded_hist_12': 0b100,
+		'cfiUpdate_folded_hist_13': 0b100,
+		'cfiUpdate_folded_hist_14': 0b100,
+		'cfiUpdate_folded_hist_15': 0b100,
+		'cfiUpdate_folded_hist_16': 0b100,
+		'cfiUpdate_folded_hist_17': 0b100
+	}
+
+	redirect_afhob_dict = {
+		'afhob_0_bits_0'	: 0b1,
+		'afhob_0_bits_1'	: 0b1,
+		'afhob_0_bits_2'	: 0b1,
+		'afhob_0_bits_3'	: 0b1,
+		'afhob_1_bits_0'	: 0b1,
+		'afhob_1_bits_1'	: 0b1,
+		'afhob_1_bits_2'	: 0b1,
+		'afhob_1_bits_3'	: 0b1,
+		'afhob_2_bits_0'	: 0b1,
+		'afhob_2_bits_1'	: 0b1,
+		'afhob_2_bits_2'	: 0b1,
+		'afhob_2_bits_3'	: 0b1,
+		'afhob_3_bits_0'	: 0b1,
+		'afhob_3_bits_1'	: 0b1,
+		'afhob_3_bits_2'	: 0b1,
+		'afhob_3_bits_3'	: 0b1,
+		'afhob_4_bits_0'	: 0b1,
+		'afhob_4_bits_1'	: 0b1,
+		'afhob_4_bits_2'	: 0b1,
+		'afhob_5_bits_0'	: 0b1,
+		'afhob_5_bits_1'	: 0b1,
+		'afhob_5_bits_2'	: 0b1,
+		'afhob_5_bits_3'	: 0b1
+	}
+
+	# reset
+	task_clock = mlvp.create_task(env.update_ftb_entry_agent.bundle.step(2200))
+	await env.redirect_other_agent.reset(4)
+	await env.sub_predi_ctrl_agent.set_sub_predic_ctrl_en(enable_dict)
+	await env.redirect_other_agent.bundle.step(2100)	#for the Initial ram
+	# set value
+	print("begin exec test_redirect_cfi_sanity test")
+
+#	await env.redirect_other_agent.set_redirect_other_value()
+	task_redirect_other 	= mlvp.create_task(env.redirect_other_agent.set_redirect_other_value(rediretc_ohter_dict))
+	task_redirect_fold_hist = mlvp.create_task(env.redirect_fold_hist_agent.set_redirect_fold_hist_value(redirect_fold_hist_dict))
+	task_redirect_afhob 	= mlvp.create_task(env.redirect_afhob_agent.set_redirect_afhob_value(redirect_afhob_dict))
+
+	await task_redirect_other 
+	await task_redirect_fold_hist
+	await task_redirect_afhob
+
+	await env.redirect_other_agent.bundle.step(10)
+
+	rediretc_ohter_dict = {
+		'level'					: 1,
+		'cfiUpdate_pc'			: 0x1280,
+		'cfiUpdate_pd_isRVC'	: 1,
+		'cfiUpdate_pd_isCall'	: 1,
+		'cfiUpdate_pd_isRet'	: 0,
+		'cfiUpdate_ssp'			: 1,
+		'cfiUpdate_sctr'		: 0,
+		'cfiUpdate_TOSW_flag'	: 1,
+		'cfiUpdate_TOSW_value'	: 1,
+		'cfiUpdate_TOSR_flag'	: 0,
+		'cfiUpdate_TOSR_value'	: 1,
+		'cfiUpdate_NOS_flag'	: 1,
+		'cfiUpdate_NOS_value'	: 1,
+
+		'cfiUpdate_lastBrNumOH'	: 1, 
+		'cfiUpdate_histPtr_flag': 1, 
+		'cfiUpdate_histPtr_value':0, 
+		'cfiUpdate_target'		: 1,
+		'cfiUpdate_taken'		: 0,
+		'cfiUpdate_shift'		: 1,
+		'cfiUpdate_addIntoHist'	: 1
+	}
+
+	redirect_fold_hist_dict = {
+		'cfiUpdate_folded_hist_0'	: 0b111,
+		'cfiUpdate_folded_hist_1'	: 0b111,
+		'cfiUpdate_folded_hist_2'	: 0b111,
+		'cfiUpdate_folded_hist_3'	: 0b111,
+		'cfiUpdate_folded_hist_4'	: 0b111,
+		'cfiUpdate_folded_hist_5'	: 0b111,
+		'cfiUpdate_folded_hist_6'	: 0b111,
+		'cfiUpdate_folded_hist_7'	: 0b111,
+		'cfiUpdate_folded_hist_8'	: 0b111,
+		'cfiUpdate_folded_hist_9'	: 0b111,
+
+		'cfiUpdate_folded_hist_10': 0b111,
+		'cfiUpdate_folded_hist_11': 0b111,
+		'cfiUpdate_folded_hist_12': 0b111,
+		'cfiUpdate_folded_hist_13': 0b111,
+		'cfiUpdate_folded_hist_14': 0b111,
+		'cfiUpdate_folded_hist_15': 0b111,
+		'cfiUpdate_folded_hist_16': 0b111,
+		'cfiUpdate_folded_hist_17': 0b111
+	}
+
+	redirect_afhob_dict = {
+		'afhob_0_bits_0'	: 0b0,
+		'afhob_0_bits_1'	: 0b0,
+		'afhob_0_bits_2'	: 0b0,
+		'afhob_0_bits_3'	: 0b0,
+		'afhob_1_bits_0'	: 0b0,
+		'afhob_1_bits_1'	: 0b0,
+		'afhob_1_bits_2'	: 0b0,
+		'afhob_1_bits_3'	: 0b0,
+		'afhob_2_bits_0'	: 0b0,
+		'afhob_2_bits_1'	: 0b0,
+		'afhob_2_bits_2'	: 0b0,
+		'afhob_2_bits_3'	: 0b0,
+		'afhob_3_bits_0'	: 0b0,
+		'afhob_3_bits_1'	: 0b0,
+		'afhob_3_bits_2'	: 0b0,
+		'afhob_3_bits_3'	: 0b0,
+		'afhob_4_bits_0'	: 0b0,
+		'afhob_4_bits_1'	: 0b0,
+		'afhob_4_bits_2'	: 0b0,
+		'afhob_5_bits_0'	: 0b0,
+		'afhob_5_bits_1'	: 0b0,
+		'afhob_5_bits_2'	: 0b0,
+		'afhob_5_bits_3'	: 0b0
+	}
+
+	task_redirect_other_1 	= mlvp.create_task(env.redirect_other_agent.set_redirect_other_value(rediretc_ohter_dict))
+	task_redirect_fold_hist_1 = mlvp.create_task(env.redirect_fold_hist_agent.set_redirect_fold_hist_value(redirect_fold_hist_dict))
+	task_redirect_afhob_1 	= mlvp.create_task(env.redirect_afhob_agent.set_redirect_afhob_value(redirect_afhob_dict))
+
+	await task_redirect_other_1 
+	await task_redirect_fold_hist_1
+	await task_redirect_afhob_1
+
+#	await env.redirect_afhob_agent.set_redirect_afhob_value()
+
+	await task_clock
+	print("test_normal_sanity IS OVER")
+
+
+@pytest.mark.mlvp_async
+async def test_normal_redirect_cfi_twice_3(mlvp_request):
+	print(mlvp_request)
+	env: BpuEnv = mlvp_request()
+	update_pc = 0x1280
+
+	# set value
+	enable_dict = {
+		'ubtb_en' 	: 1,	
+		'btb_en'	: 0,
+		'tage_en'	: 1,
+		'sc_en'		: 1,
+		'ras_en'	: 1
+	}
+
+	rediretc_ohter_dict = {
+		'level'					: 1,
+		'cfiUpdate_pc'			: 0x1280,
+		'cfiUpdate_pd_isRVC'	: 1,
+		'cfiUpdate_pd_isCall'	: 1,
+		'cfiUpdate_pd_isRet'	: 1,
+		'cfiUpdate_ssp'			: 1,
+		'cfiUpdate_sctr'		: 1,
+		'cfiUpdate_TOSW_flag'	: 1,
+		'cfiUpdate_TOSW_value'	: 1,
+		'cfiUpdate_TOSR_flag'	: 1,
+		'cfiUpdate_TOSR_value'	: 1,
+		'cfiUpdate_NOS_flag'	: 1,
+		'cfiUpdate_NOS_value'	: 1,
+
+		'cfiUpdate_lastBrNumOH'	: 1, 
+		'cfiUpdate_histPtr_flag': 1, 
+		'cfiUpdate_histPtr_value':1, 
+		'cfiUpdate_target'		: 1,
+		'cfiUpdate_taken'		: 1,
+		'cfiUpdate_shift'		: 1,
+		'cfiUpdate_addIntoHist'	: 1
+	}
+
+	redirect_fold_hist_dict = {
+		'cfiUpdate_folded_hist_0'	: 0b100,
+		'cfiUpdate_folded_hist_1'	: 0b100,
+		'cfiUpdate_folded_hist_2'	: 0b100,
+		'cfiUpdate_folded_hist_3'	: 0b100,
+		'cfiUpdate_folded_hist_4'	: 0b100,
+		'cfiUpdate_folded_hist_5'	: 0b100,
+		'cfiUpdate_folded_hist_6'	: 0b100,
+		'cfiUpdate_folded_hist_7'	: 0b100,
+		'cfiUpdate_folded_hist_8'	: 0b100,
+		'cfiUpdate_folded_hist_9'	: 0b100,
+
+		'cfiUpdate_folded_hist_10': 0b100,
+		'cfiUpdate_folded_hist_11': 0b100,
+		'cfiUpdate_folded_hist_12': 0b100,
+		'cfiUpdate_folded_hist_13': 0b100,
+		'cfiUpdate_folded_hist_14': 0b100,
+		'cfiUpdate_folded_hist_15': 0b100,
+		'cfiUpdate_folded_hist_16': 0b100,
+		'cfiUpdate_folded_hist_17': 0b100
+	}
+
+	redirect_afhob_dict = {
+		'afhob_0_bits_0'	: 0b1,
+		'afhob_0_bits_1'	: 0b1,
+		'afhob_0_bits_2'	: 0b1,
+		'afhob_0_bits_3'	: 0b1,
+		'afhob_1_bits_0'	: 0b1,
+		'afhob_1_bits_1'	: 0b1,
+		'afhob_1_bits_2'	: 0b1,
+		'afhob_1_bits_3'	: 0b1,
+		'afhob_2_bits_0'	: 0b1,
+		'afhob_2_bits_1'	: 0b1,
+		'afhob_2_bits_2'	: 0b1,
+		'afhob_2_bits_3'	: 0b1,
+		'afhob_3_bits_0'	: 0b1,
+		'afhob_3_bits_1'	: 0b1,
+		'afhob_3_bits_2'	: 0b1,
+		'afhob_3_bits_3'	: 0b1,
+		'afhob_4_bits_0'	: 0b1,
+		'afhob_4_bits_1'	: 0b1,
+		'afhob_4_bits_2'	: 0b1,
+		'afhob_5_bits_0'	: 0b1,
+		'afhob_5_bits_1'	: 0b1,
+		'afhob_5_bits_2'	: 0b1,
+		'afhob_5_bits_3'	: 0b1
+	}
+
+	update_ftb_entry_dict = {
+		'ftb_entry_valid'	: 1,
+		'tailSlot_valid'	: 1,
+		'tailSlot_tarStat'	: 0b10,
+		'tailSlot_sharing'	: 1,
+		'tailSlot_offset'	: 0b0100,
+		'tailSlot_lower'	: 0x20,
+		'pftAddr'			: 0b1000,
+		'may_be_rvi_call'	: 1,
+		'isRet'				: 1,
+		'isJalr'			: 1,
+		'isCall'			: 1,
+		'carry'				: 1,
+		'always_taken_0'	: 1,
+		'always_taken_1'	: 1,
+		'brSlots_0_valid'	: 1,
+		'brSlots_0_tarStat' : 0b10,
+		'brSlots_0_sharing'	: 1,
+		'brSlots_0_offset'	: 0b0100,
+		'brSlots_0_lower'	: 0x200
+	}
+	## update_other_signals
+	update_other_dict = {
+		'cfi_idx_valid'		: 1,
+		'cfi_idx_bits'		: 0b1000,
+		'br_taken_mask_0'	: 1,
+		'br_taken_mask_1'	: 1,
+		'jmp_taken'			: 0,
+		'mispred_mask_0'	: 1,
+		'mispred_mask_1'	: 1,
+		'mispred_mask_2'	: 1,
+		'old_entry'			: 1,
+		'meta'				: 1,
+		'full_target'		: 1
+	}
+
+	update_fold_hist_dict = {
+		'folded_hist_1' 	: 0b1000,
+		'folded_hist_2' 	: 0b1001,
+		'folded_hist_3' 	: 0b1010,
+		'folded_hist_4' 	: 0b1100,
+		'folded_hist_5' 	: 0b0001,
+		'folded_hist_6' 	: 0b0000,
+		'folded_hist_7' 	: 0b0001,
+		'folded_hist_8' 	: 0b0010,
+		'folded_hist_9' 	: 0b0100,
+		'folded_hist_10' 	: 0b1000,
+		'folded_hist_11' 	: 0b1100,
+		'folded_hist_12' 	: 0b1110,
+		'folded_hist_13' 	: 0b1111,
+		'folded_hist_14' 	: 0b0000,
+		'folded_hist_15' 	: 0b1111,
+		'folded_hist_16' 	: 0b1001,
+		'folded_hist_17' 	: 0b1001
+	}
+
+
+	# reset
+	task_clock = mlvp.create_task(env.update_ftb_entry_agent.bundle.step(2200))
+	await env.redirect_other_agent.reset(4)
+	await env.sub_predi_ctrl_agent.set_sub_predic_ctrl_en(enable_dict)
+	await env.redirect_other_agent.bundle.step(2100)	#for the Initial ram
+	# set value
+	print("begin exec test_redirect_cfi_sanity test")
+
+#	await env.redirect_other_agent.set_redirect_other_value()
+	task_redirect_other 	= mlvp.create_task(env.redirect_other_agent.set_redirect_other_value(rediretc_ohter_dict))
+	task_redirect_fold_hist = mlvp.create_task(env.redirect_fold_hist_agent.set_redirect_fold_hist_value(redirect_fold_hist_dict))
+	task_redirect_afhob 	= mlvp.create_task(env.redirect_afhob_agent.set_redirect_afhob_value(redirect_afhob_dict))
+
+	await task_redirect_other 
+	await task_redirect_fold_hist
+	await task_redirect_afhob
+
+	await env.redirect_other_agent.bundle.step(10)
+
+
+	task_update_ftb_entry 	= mlvp.create_task(env.update_ftb_entry_agent.set_update_ftb_entry_value(update_pc,update_ftb_entry_dict)) 
+	task_update_other 		= mlvp.create_task(env.update_other_agent.set_update_other_value(update_pc,update_other_dict))
+	task_update_foldedHist 	= mlvp.create_task(env.update_fold_hist_agent.set_update_fold_hist_value(update_pc,update_fold_hist_dict))
+
+	await task_update_ftb_entry
+	await task_update_other
+	await task_update_foldedHist
+
+	####Second value
+	rediretc_ohter_dict = {
+		'level'					: 1,
+		'cfiUpdate_pc'			: 0x1280,
+		'cfiUpdate_pd_isRVC'	: 1,
+		'cfiUpdate_pd_isCall'	: 1,
+		'cfiUpdate_pd_isRet'	: 0,
+		'cfiUpdate_ssp'			: 1,
+		'cfiUpdate_sctr'		: 0,
+		'cfiUpdate_TOSW_flag'	: 1,
+		'cfiUpdate_TOSW_value'	: 1,
+		'cfiUpdate_TOSR_flag'	: 0,
+		'cfiUpdate_TOSR_value'	: 1,
+		'cfiUpdate_NOS_flag'	: 1,
+		'cfiUpdate_NOS_value'	: 1,
+
+		'cfiUpdate_lastBrNumOH'	: 1, 
+		'cfiUpdate_histPtr_flag': 1, 
+		'cfiUpdate_histPtr_value':0, 
+		'cfiUpdate_target'		: 1,
+		'cfiUpdate_taken'		: 0,
+		'cfiUpdate_shift'		: 1,
+		'cfiUpdate_addIntoHist'	: 1
+	}
+
+	redirect_fold_hist_dict = {
+		'cfiUpdate_folded_hist_0'	: 0b111,
+		'cfiUpdate_folded_hist_1'	: 0b111,
+		'cfiUpdate_folded_hist_2'	: 0b111,
+		'cfiUpdate_folded_hist_3'	: 0b111,
+		'cfiUpdate_folded_hist_4'	: 0b111,
+		'cfiUpdate_folded_hist_5'	: 0b111,
+		'cfiUpdate_folded_hist_6'	: 0b111,
+		'cfiUpdate_folded_hist_7'	: 0b111,
+		'cfiUpdate_folded_hist_8'	: 0b111,
+		'cfiUpdate_folded_hist_9'	: 0b111,
+
+		'cfiUpdate_folded_hist_10': 0b111,
+		'cfiUpdate_folded_hist_11': 0b111,
+		'cfiUpdate_folded_hist_12': 0b111,
+		'cfiUpdate_folded_hist_13': 0b111,
+		'cfiUpdate_folded_hist_14': 0b111,
+		'cfiUpdate_folded_hist_15': 0b111,
+		'cfiUpdate_folded_hist_16': 0b111,
+		'cfiUpdate_folded_hist_17': 0b111
+	}
+
+	redirect_afhob_dict = {
+		'afhob_0_bits_0'	: 0b0,
+		'afhob_0_bits_1'	: 0b0,
+		'afhob_0_bits_2'	: 0b0,
+		'afhob_0_bits_3'	: 0b0,
+		'afhob_1_bits_0'	: 0b0,
+		'afhob_1_bits_1'	: 0b0,
+		'afhob_1_bits_2'	: 0b0,
+		'afhob_1_bits_3'	: 0b0,
+		'afhob_2_bits_0'	: 0b0,
+		'afhob_2_bits_1'	: 0b0,
+		'afhob_2_bits_2'	: 0b0,
+		'afhob_2_bits_3'	: 0b0,
+		'afhob_3_bits_0'	: 0b0,
+		'afhob_3_bits_1'	: 0b0,
+		'afhob_3_bits_2'	: 0b0,
+		'afhob_3_bits_3'	: 0b0,
+		'afhob_4_bits_0'	: 0b0,
+		'afhob_4_bits_1'	: 0b0,
+		'afhob_4_bits_2'	: 0b0,
+		'afhob_5_bits_0'	: 0b0,
+		'afhob_5_bits_1'	: 0b0,
+		'afhob_5_bits_2'	: 0b0,
+		'afhob_5_bits_3'	: 0b0
+	}
+
+	task_redirect_other_1 	= mlvp.create_task(env.redirect_other_agent.set_redirect_other_value(rediretc_ohter_dict))
+	task_redirect_fold_hist_1 = mlvp.create_task(env.redirect_fold_hist_agent.set_redirect_fold_hist_value(redirect_fold_hist_dict))
+	task_redirect_afhob_1 	= mlvp.create_task(env.redirect_afhob_agent.set_redirect_afhob_value(redirect_afhob_dict))
+
+	await task_redirect_other_1 
+	await task_redirect_fold_hist_1
+	await task_redirect_afhob_1
+
+#	await env.redirect_afhob_agent.set_redirect_afhob_value()
+
+	await task_clock
+	print("test_normal_sanity IS OVER")
+
+
+@pytest.mark.mlvp_async
+async def test_normal_redirect_cfi_twice_4(mlvp_request):
+	print(mlvp_request)
+	env: BpuEnv = mlvp_request()
+	update_pc = 0x1280
+
+	# set value
+	enable_dict = {
+		'ubtb_en' 	: 1,	
+		'btb_en'	: 1,
+		'tage_en'	: 1,
+		'sc_en'		: 1,
+		'ras_en'	: 1
+	}
+
+	rediretc_ohter_dict = {
+		'level'					: 1,
+		'cfiUpdate_pc'			: 0x2280,
+		'cfiUpdate_pd_isRVC'	: 1,
+		'cfiUpdate_pd_isCall'	: 1,
+		'cfiUpdate_pd_isRet'	: 1,
+		'cfiUpdate_ssp'			: 1,
+		'cfiUpdate_sctr'		: 1,
+		'cfiUpdate_TOSW_flag'	: 1,
+		'cfiUpdate_TOSW_value'	: 1,
+		'cfiUpdate_TOSR_flag'	: 1,
+		'cfiUpdate_TOSR_value'	: 1,
+		'cfiUpdate_NOS_flag'	: 1,
+		'cfiUpdate_NOS_value'	: 1,
+
+		'cfiUpdate_lastBrNumOH'	: 1, 
+		'cfiUpdate_histPtr_flag': 1, 
+		'cfiUpdate_histPtr_value':1, 
+		'cfiUpdate_target'		: 1,
+		'cfiUpdate_taken'		: 1,
+		'cfiUpdate_shift'		: 1,
+		'cfiUpdate_addIntoHist'	: 1
+	}
+
+	redirect_fold_hist_dict = {
+		'cfiUpdate_folded_hist_0'	: 0b100,
+		'cfiUpdate_folded_hist_1'	: 0b100,
+		'cfiUpdate_folded_hist_2'	: 0b100,
+		'cfiUpdate_folded_hist_3'	: 0b100,
+		'cfiUpdate_folded_hist_4'	: 0b100,
+		'cfiUpdate_folded_hist_5'	: 0b100,
+		'cfiUpdate_folded_hist_6'	: 0b100,
+		'cfiUpdate_folded_hist_7'	: 0b100,
+		'cfiUpdate_folded_hist_8'	: 0b100,
+		'cfiUpdate_folded_hist_9'	: 0b100,
+
+		'cfiUpdate_folded_hist_10': 0b100,
+		'cfiUpdate_folded_hist_11': 0b100,
+		'cfiUpdate_folded_hist_12': 0b100,
+		'cfiUpdate_folded_hist_13': 0b100,
+		'cfiUpdate_folded_hist_14': 0b100,
+		'cfiUpdate_folded_hist_15': 0b100,
+		'cfiUpdate_folded_hist_16': 0b100,
+		'cfiUpdate_folded_hist_17': 0b100
+	}
+
+	redirect_afhob_dict = {
+		'afhob_0_bits_0'	: 0b1,
+		'afhob_0_bits_1'	: 0b1,
+		'afhob_0_bits_2'	: 0b1,
+		'afhob_0_bits_3'	: 0b1,
+		'afhob_1_bits_0'	: 0b1,
+		'afhob_1_bits_1'	: 0b1,
+		'afhob_1_bits_2'	: 0b1,
+		'afhob_1_bits_3'	: 0b1,
+		'afhob_2_bits_0'	: 0b1,
+		'afhob_2_bits_1'	: 0b1,
+		'afhob_2_bits_2'	: 0b1,
+		'afhob_2_bits_3'	: 0b1,
+		'afhob_3_bits_0'	: 0b1,
+		'afhob_3_bits_1'	: 0b1,
+		'afhob_3_bits_2'	: 0b1,
+		'afhob_3_bits_3'	: 0b1,
+		'afhob_4_bits_0'	: 0b1,
+		'afhob_4_bits_1'	: 0b1,
+		'afhob_4_bits_2'	: 0b1,
+		'afhob_5_bits_0'	: 0b1,
+		'afhob_5_bits_1'	: 0b1,
+		'afhob_5_bits_2'	: 0b1,
+		'afhob_5_bits_3'	: 0b1
+	}
+
+	update_ftb_entry_dict = {
+		'ftb_entry_valid'	: 1,
+		'tailSlot_valid'	: 1,
+		'tailSlot_tarStat'	: 0b10,
+		'tailSlot_sharing'	: 1,
+		'tailSlot_offset'	: 0b0100,
+		'tailSlot_lower'	: 0x20,
+		'pftAddr'			: 0b1000,
+		'may_be_rvi_call'	: 1,
+		'isRet'				: 1,
+		'isJalr'			: 1,
+		'isCall'			: 1,
+		'carry'				: 1,
+		'always_taken_0'	: 1,
+		'always_taken_1'	: 1,
+		'brSlots_0_valid'	: 1,
+		'brSlots_0_tarStat' : 0b10,
+		'brSlots_0_sharing'	: 1,
+		'brSlots_0_offset'	: 0b0100,
+		'brSlots_0_lower'	: 0x200
+	}
+	## update_other_signals
+	update_other_dict = {
+		'cfi_idx_valid'		: 1,
+		'cfi_idx_bits'		: 0b1000,
+		'br_taken_mask_0'	: 1,
+		'br_taken_mask_1'	: 1,
+		'jmp_taken'			: 0,
+		'mispred_mask_0'	: 1,
+		'mispred_mask_1'	: 1,
+		'mispred_mask_2'	: 1,
+		'old_entry'			: 1,
+		'meta'				: 1,
+		'full_target'		: 1
+	}
+
+	update_fold_hist_dict = {
+		'folded_hist_1' 	: 0b1000,
+		'folded_hist_2' 	: 0b1001,
+		'folded_hist_3' 	: 0b1010,
+		'folded_hist_4' 	: 0b1100,
+		'folded_hist_5' 	: 0b0001,
+		'folded_hist_6' 	: 0b0000,
+		'folded_hist_7' 	: 0b0001,
+		'folded_hist_8' 	: 0b0010,
+		'folded_hist_9' 	: 0b0100,
+		'folded_hist_10' 	: 0b1000,
+		'folded_hist_11' 	: 0b1100,
+		'folded_hist_12' 	: 0b1110,
+		'folded_hist_13' 	: 0b1111,
+		'folded_hist_14' 	: 0b0000,
+		'folded_hist_15' 	: 0b1111,
+		'folded_hist_16' 	: 0b1001,
+		'folded_hist_17' 	: 0b1001
+	}
+
+
+	# reset
+	task_clock = mlvp.create_task(env.update_ftb_entry_agent.bundle.step(2200))
+	await env.redirect_other_agent.reset(4)
+	await env.sub_predi_ctrl_agent.set_sub_predic_ctrl_en(enable_dict)
+	await env.redirect_other_agent.bundle.step(2100)	#for the Initial ram
+	# set value
+	print("begin exec test_redirect_cfi_sanity test")
+
+#	await env.redirect_other_agent.set_redirect_other_value()
+	task_redirect_other 	= mlvp.create_task(env.redirect_other_agent.set_redirect_other_value(rediretc_ohter_dict))
+	task_redirect_fold_hist = mlvp.create_task(env.redirect_fold_hist_agent.set_redirect_fold_hist_value(redirect_fold_hist_dict))
+	task_redirect_afhob 	= mlvp.create_task(env.redirect_afhob_agent.set_redirect_afhob_value(redirect_afhob_dict))
+
+	await task_redirect_other 
+	await task_redirect_fold_hist
+	await task_redirect_afhob
+
+	await env.redirect_other_agent.bundle.step(10)
+
+
+	task_update_ftb_entry 	= mlvp.create_task(env.update_ftb_entry_agent.set_update_ftb_entry_value(update_pc,update_ftb_entry_dict)) 
+	task_update_other 		= mlvp.create_task(env.update_other_agent.set_update_other_value(update_pc,update_other_dict))
+	task_update_foldedHist 	= mlvp.create_task(env.update_fold_hist_agent.set_update_fold_hist_value(update_pc,update_fold_hist_dict))
+
+	await task_update_ftb_entry
+	await task_update_other
+	await task_update_foldedHist
+
+	####Second value
+	rediretc_ohter_dict = {
+		'level'					: 1,
+		'cfiUpdate_pc'			: 0x1480,
+		'cfiUpdate_pd_isRVC'	: 0,
+		'cfiUpdate_pd_isCall'	: 0,
+		'cfiUpdate_pd_isRet'	: 0,
+		'cfiUpdate_ssp'			: 0,
+		'cfiUpdate_sctr'		: 0,
+		'cfiUpdate_TOSW_flag'	: 0,
+		'cfiUpdate_TOSW_value'	: 0,
+		'cfiUpdate_TOSR_flag'	: 0,
+		'cfiUpdate_TOSR_value'	: 0,
+		'cfiUpdate_NOS_flag'	: 0,
+		'cfiUpdate_NOS_value'	: 0,
+
+		'cfiUpdate_lastBrNumOH'	: 1, 
+		'cfiUpdate_histPtr_flag': 1, 
+		'cfiUpdate_histPtr_value':0, 
+		'cfiUpdate_target'		: 0,
+		'cfiUpdate_taken'		: 0,
+		'cfiUpdate_shift'		: 1,
+		'cfiUpdate_addIntoHist'	: 1
+	}
+
+	redirect_fold_hist_dict = {
+		'cfiUpdate_folded_hist_0'	: 0b011,
+		'cfiUpdate_folded_hist_1'	: 0b011,
+		'cfiUpdate_folded_hist_2'	: 0b011,
+		'cfiUpdate_folded_hist_3'	: 0b011,
+		'cfiUpdate_folded_hist_4'	: 0b011,
+		'cfiUpdate_folded_hist_5'	: 0b011,
+		'cfiUpdate_folded_hist_6'	: 0b011,
+		'cfiUpdate_folded_hist_7'	: 0b011,
+		'cfiUpdate_folded_hist_8'	: 0b011,
+		'cfiUpdate_folded_hist_9'	: 0b011,
+
+		'cfiUpdate_folded_hist_10': 0b111,
+		'cfiUpdate_folded_hist_11': 0b111,
+		'cfiUpdate_folded_hist_12': 0b111,
+		'cfiUpdate_folded_hist_13': 0b111,
+		'cfiUpdate_folded_hist_14': 0b111,
+		'cfiUpdate_folded_hist_15': 0b111,
+		'cfiUpdate_folded_hist_16': 0b111,
+		'cfiUpdate_folded_hist_17': 0b111
+	}
+
+	redirect_afhob_dict = {
+		'afhob_0_bits_0'	: 0b0,
+		'afhob_0_bits_1'	: 0b0,
+		'afhob_0_bits_2'	: 0b0,
+		'afhob_0_bits_3'	: 0b0,
+		'afhob_1_bits_0'	: 0b0,
+		'afhob_1_bits_1'	: 0b0,
+		'afhob_1_bits_2'	: 0b0,
+		'afhob_1_bits_3'	: 0b0,
+		'afhob_2_bits_0'	: 0b0,
+		'afhob_2_bits_1'	: 0b0,
+		'afhob_2_bits_2'	: 0b0,
+		'afhob_2_bits_3'	: 0b0,
+		'afhob_3_bits_0'	: 0b0,
+		'afhob_3_bits_1'	: 0b0,
+		'afhob_3_bits_2'	: 0b0,
+		'afhob_3_bits_3'	: 0b0,
+		'afhob_4_bits_0'	: 0b0,
+		'afhob_4_bits_1'	: 0b0,
+		'afhob_4_bits_2'	: 0b0,
+		'afhob_5_bits_0'	: 0b0,
+		'afhob_5_bits_1'	: 0b0,
+		'afhob_5_bits_2'	: 0b0,
+		'afhob_5_bits_3'	: 0b0
+	}
+	update_ftb_entry_dict = {
+		'ftb_entry_valid'	: 1,
+		'tailSlot_valid'	: 1,
+		'tailSlot_tarStat'	: 0b11,
+		'tailSlot_sharing'	: 1,
+		'tailSlot_offset'	: 0b1111,
+		'tailSlot_lower'	: 0x22,
+		'pftAddr'			: 0b1111,
+		'may_be_rvi_call'	: 1,
+		'isRet'				: 1,
+		'isJalr'			: 1,
+		'isCall'			: 1,
+		'carry'				: 1,
+		'always_taken_0'	: 1,
+		'always_taken_1'	: 1,
+		'brSlots_0_valid'	: 1,
+		'brSlots_0_tarStat' : 0b10,
+		'brSlots_0_sharing'	: 1,
+		'brSlots_0_offset'	: 0b0100,
+		'brSlots_0_lower'	: 0x200
+	}
+
+	## update_other_signals
+	update_other_dict = {
+		'cfi_idx_valid'		: 1,
+		'cfi_idx_bits'		: 0b0111,
+		'br_taken_mask_0'	: 1,
+		'br_taken_mask_1'	: 0,
+		'jmp_taken'			: 0,
+		'mispred_mask_0'	: 0,
+		'mispred_mask_1'	: 0,
+		'mispred_mask_2'	: 0,
+		'old_entry'			: 0,
+		'meta'				: 0,
+		'full_target'		: 0
+	}
+
+	update_fold_hist_dict = {
+		'folded_hist_1' 	: 0b1000,
+		'folded_hist_2' 	: 0b1001,
+		'folded_hist_3' 	: 0b1010,
+		'folded_hist_4' 	: 0b1100,
+		'folded_hist_5' 	: 0b0001,
+		'folded_hist_6' 	: 0b0000,
+		'folded_hist_7' 	: 0b0001,
+		'folded_hist_8' 	: 0b0010,
+		'folded_hist_9' 	: 0b0100,
+		'folded_hist_10' 	: 0b1000,
+		'folded_hist_11' 	: 0b1100,
+		'folded_hist_12' 	: 0b1110,
+		'folded_hist_13' 	: 0b1111,
+		'folded_hist_14' 	: 0b0000,
+		'folded_hist_15' 	: 0b1111,
+		'folded_hist_16' 	: 0b1001,
+		'folded_hist_17' 	: 0b1001
+	}
+
+	task_redirect_other_1 	= mlvp.create_task(env.redirect_other_agent.set_redirect_other_value(rediretc_ohter_dict))
+	task_redirect_fold_hist_1 = mlvp.create_task(env.redirect_fold_hist_agent.set_redirect_fold_hist_value(redirect_fold_hist_dict))
+	task_redirect_afhob_1 	= mlvp.create_task(env.redirect_afhob_agent.set_redirect_afhob_value(redirect_afhob_dict))
+
+	await task_redirect_other_1 
+	await task_redirect_fold_hist_1
+	await task_redirect_afhob_1
+
+	await env.redirect_other_agent.bundle.step(10)
+
+	task_update_ftb_entry_1 	= mlvp.create_task(env.update_ftb_entry_agent.set_update_ftb_entry_value(update_pc,update_ftb_entry_dict)) 
+	task_update_other_1 		= mlvp.create_task(env.update_other_agent.set_update_other_value(update_pc,update_other_dict))
+	task_update_foldedHist_1 	= mlvp.create_task(env.update_fold_hist_agent.set_update_fold_hist_value(update_pc,update_fold_hist_dict))
+
+	await task_update_ftb_entry_1
+	await task_update_other_1
+	await task_update_foldedHist_1
+
+#	await env.redirect_afhob_agent.set_redirect_afhob_value()
+
+	await task_clock
+	print("test_normal_sanity IS OVER")
+
+
+@pytest.mark.mlvp_async
+async def test_update_FtbEntry_foldHist_signals_1(mlvp_request):
+	print(mlvp_request)
+	env: BpuEnv = mlvp_request()
+	update_pc = 0x1248
+
+	# rese
+	task_clock = mlvp.create_task(env.update_ftb_entry_agent.bundle.step(2200))
+	await env.update_ftb_entry_agent.reset(4)
+	await env.update_ftb_entry_agent.bundle.step(2100)
+	print("begin exec test_update_fold_hist_sanity test")
+
+	update_ftb_entry_dict = {
+		'ftb_entry_valid'	: 1,
+		'tailSlot_valid'	: 1,
+		'tailSlot_tarStat'	: 0b11,
+		'tailSlot_sharing'	: 1,
+		'tailSlot_offset'	: 0b1111,
+		'tailSlot_lower'	: 0x21,
+		'pftAddr'			: 0b1110,
+		'may_be_rvi_call'	: 0,
+		'isRet'				: 0,
+		'isJalr'			: 0,
+		'isCall'			: 0,
+		'carry'				: 0,
+		'always_taken_0'	: 0,
+		'always_taken_1'	: 0,
+		'brSlots_0_valid'	: 0,
+		'brSlots_0_tarStat' : 0b00,
+		'brSlots_0_sharing'	: 0,
+		'brSlots_0_offset'	: 0b0000,
+		'brSlots_0_lower'	: 0x000
+	}
+	## update_other_signals
+	update_other_dict = {
+		'cfi_idx_valid'		: 1,
+		'cfi_idx_bits'		: 0b1000,
+		'br_taken_mask_0'	: 1,
+		'br_taken_mask_1'	: 1,
+		'jmp_taken'			: 0,
+		'mispred_mask_0'	: 0,
+		'mispred_mask_1'	: 0,
+		'mispred_mask_2'	: 0,
+		'old_entry'			: 0,
+		'meta'				: 0,
+		'full_target'		: 0
+	}
+
+	update_fold_hist_dict = {
+		'folded_hist_1' 	: 0b1000,
+		'folded_hist_2' 	: 0b1001,
+		'folded_hist_3' 	: 0b1010,
+		'folded_hist_4' 	: 0b1100,
+		'folded_hist_5' 	: 0b0001,
+		'folded_hist_6' 	: 0b0000,
+		'folded_hist_7' 	: 0b0001,
+		'folded_hist_8' 	: 0b0010,
+		'folded_hist_9' 	: 0b0100,
+		'folded_hist_10' 	: 0b1000,
+		'folded_hist_11' 	: 0b1100,
+		'folded_hist_12' 	: 0b1110,
+		'folded_hist_13' 	: 0b1111,
+		'folded_hist_14' 	: 0b0000,
+		'folded_hist_15' 	: 0b1111,
+		'folded_hist_16' 	: 0b1001,
+		'folded_hist_17' 	: 0b1001
+	}
+
+	task_update_ftb_entry 	= mlvp.create_task(env.update_ftb_entry_agent.set_update_ftb_entry_value(update_pc,update_ftb_entry_dict)) 
+	task_update_other 		= mlvp.create_task(env.update_other_agent.set_update_other_value(update_pc,update_other_dict))
+	task_update_foldedHist 	= mlvp.create_task(env.update_fold_hist_agent.set_update_fold_hist_value(update_pc,update_fold_hist_dict))
+
+	await task_update_ftb_entry
+	await task_update_other
+	await task_update_foldedHist
+
+	await env.update_ftb_entry_agent.bundle.step(1)
+
+	update_ftb_entry_dict = {
+		'ftb_entry_valid'	: 1,
+		'tailSlot_valid'	: 1,
+		'tailSlot_tarStat'	: 0b11,
+		'tailSlot_sharing'	: 1,
+		'tailSlot_offset'	: 0b1111,
+		'tailSlot_lower'	: 0x22,
+		'pftAddr'			: 0b1111,
+		'may_be_rvi_call'	: 1,
+		'isRet'				: 1,
+		'isJalr'			: 1,
+		'isCall'			: 1,
+		'carry'				: 1,
+		'always_taken_0'	: 1,
+		'always_taken_1'	: 1,
+		'brSlots_0_valid'	: 1,
+		'brSlots_0_tarStat' : 0b10,
+		'brSlots_0_sharing'	: 1,
+		'brSlots_0_offset'	: 0b0100,
+		'brSlots_0_lower'	: 0x200
+	}
+
+	## update_other_signals
+	update_other_dict = {
+		'cfi_idx_valid'		: 1,
+		'cfi_idx_bits'		: 0b0111,
+		'br_taken_mask_0'	: 1,
+		'br_taken_mask_1'	: 0,
+		'jmp_taken'			: 1,
+		'mispred_mask_0'	: 1,
+		'mispred_mask_1'	: 1,
+		'mispred_mask_2'	: 1,
+		'old_entry'			: 1,
+		'meta'				: 1,
+		'full_target'		: 1
+	}
+
+	update_fold_hist_dict = {
+		'folded_hist_1' 	: 0b1000,
+		'folded_hist_2' 	: 0b1001,
+		'folded_hist_3' 	: 0b1010,
+		'folded_hist_4' 	: 0b1100,
+		'folded_hist_5' 	: 0b0001,
+		'folded_hist_6' 	: 0b0000,
+		'folded_hist_7' 	: 0b0001,
+		'folded_hist_8' 	: 0b0010,
+		'folded_hist_9' 	: 0b0100,
+		'folded_hist_10' 	: 0b1000,
+		'folded_hist_11' 	: 0b1100,
+		'folded_hist_12' 	: 0b1110,
+		'folded_hist_13' 	: 0b1111,
+		'folded_hist_14' 	: 0b0000,
+		'folded_hist_15' 	: 0b1111,
+		'folded_hist_16' 	: 0b1001,
+		'folded_hist_17' 	: 0b1001
+	}
+
+	task_update_ftb_entry_1		= mlvp.create_task(env.update_ftb_entry_agent.set_update_ftb_entry_value(update_pc,update_ftb_entry_dict)) 
+	task_update_other_1 		= mlvp.create_task(env.update_other_agent.set_update_other_value(update_pc,update_other_dict))
+	task_update_foldedHist_1 	= mlvp.create_task(env.update_fold_hist_agent.set_update_fold_hist_value(update_pc,update_fold_hist_dict))
+
+	await task_update_ftb_entry_1
+	await task_update_other_1
+	await task_update_foldedHist_1
+
+	await task_clock
+	print("test_update_signals_sanity IS OVER")
+
+
+@pytest.mark.mlvp_async
+async def test_update_FtbEntry_foldHist_signals_2(mlvp_request):
+	print(mlvp_request)
+	env: BpuEnv = mlvp_request()
+	update_pc = 0x1248
+
+	enable_dict = {
+		'ubtb_en' 	: 1,	
+		'btb_en'	: 1,
+		'tage_en'	: 1,
+		'sc_en'		: 1,
+		'ras_en'	: 1
+	}
+
+	# rese
+	task_clock = mlvp.create_task(env.update_ftb_entry_agent.bundle.step(2200))
+	await env.update_ftb_entry_agent.reset(4)
+	await env.sub_predi_ctrl_agent.set_sub_predic_ctrl_en(enable_dict)
+	await env.update_ftb_entry_agent.bundle.step(2100)
+	print("begin exec test_update_fold_hist_sanity test")
+
+	update_ftb_entry_dict = {
+		'ftb_entry_valid'	: 1,
+		'tailSlot_valid'	: 1,
+		'tailSlot_tarStat'	: 0b11,
+		'tailSlot_sharing'	: 1,
+		'tailSlot_offset'	: 0b1111,
+		'tailSlot_lower'	: 0x21,
+		'pftAddr'			: 0b1110,
+		'may_be_rvi_call'	: 0,
+		'isRet'				: 0,
+		'isJalr'			: 0,
+		'isCall'			: 0,
+		'carry'				: 0,
+		'always_taken_0'	: 0,
+		'always_taken_1'	: 0,
+		'brSlots_0_valid'	: 0,
+		'brSlots_0_tarStat' : 0b00,
+		'brSlots_0_sharing'	: 0,
+		'brSlots_0_offset'	: 0b0000,
+		'brSlots_0_lower'	: 0x000
+	}
+	## update_other_signals
+	update_other_dict = {
+		'cfi_idx_valid'		: 1,
+		'cfi_idx_bits'		: 0b1000,
+		'br_taken_mask_0'	: 1,
+		'br_taken_mask_1'	: 1,
+		'jmp_taken'			: 0,
+		'mispred_mask_0'	: 0,
+		'mispred_mask_1'	: 0,
+		'mispred_mask_2'	: 0,
+		'old_entry'			: 0,
+		'meta'				: 0,
+		'full_target'		: 0
+	}
+
+	update_fold_hist_dict = {
+		'folded_hist_1' 	: 0b1000,
+		'folded_hist_2' 	: 0b1001,
+		'folded_hist_3' 	: 0b1010,
+		'folded_hist_4' 	: 0b1100,
+		'folded_hist_5' 	: 0b0001,
+		'folded_hist_6' 	: 0b0000,
+		'folded_hist_7' 	: 0b0001,
+		'folded_hist_8' 	: 0b0010,
+		'folded_hist_9' 	: 0b0100,
+		'folded_hist_10' 	: 0b1000,
+		'folded_hist_11' 	: 0b1100,
+		'folded_hist_12' 	: 0b1110,
+		'folded_hist_13' 	: 0b1111,
+		'folded_hist_14' 	: 0b0000,
+		'folded_hist_15' 	: 0b1111,
+		'folded_hist_16' 	: 0b1001,
+		'folded_hist_17' 	: 0b1001
+	}
+
+	task_update_ftb_entry 	= mlvp.create_task(env.update_ftb_entry_agent.set_update_ftb_entry_value(update_pc,update_ftb_entry_dict)) 
+	task_update_other 		= mlvp.create_task(env.update_other_agent.set_update_other_value(update_pc,update_other_dict))
+	task_update_foldedHist 	= mlvp.create_task(env.update_fold_hist_agent.set_update_fold_hist_value(update_pc,update_fold_hist_dict))
+
+	await task_update_ftb_entry
+	await task_update_other
+	await task_update_foldedHist
+
+	await env.update_ftb_entry_agent.bundle.step(1)
+
+	update_ftb_entry_dict = {
+		'ftb_entry_valid'	: 1,
+		'tailSlot_valid'	: 1,
+		'tailSlot_tarStat'	: 0b11,
+		'tailSlot_sharing'	: 1,
+		'tailSlot_offset'	: 0b1111,
+		'tailSlot_lower'	: 0x22,
+		'pftAddr'			: 0b1111,
+		'may_be_rvi_call'	: 1,
+		'isRet'				: 1,
+		'isJalr'			: 1,
+		'isCall'			: 1,
+		'carry'				: 1,
+		'always_taken_0'	: 1,
+		'always_taken_1'	: 1,
+		'brSlots_0_valid'	: 1,
+		'brSlots_0_tarStat' : 0b10,
+		'brSlots_0_sharing'	: 1,
+		'brSlots_0_offset'	: 0b0100,
+		'brSlots_0_lower'	: 0x200
+	}
+
+	## update_other_signals
+	update_other_dict = {
+		'cfi_idx_valid'		: 1,
+		'cfi_idx_bits'		: 0b0111,
+		'br_taken_mask_0'	: 1,
+		'br_taken_mask_1'	: 0,
+		'jmp_taken'			: 1,
+		'mispred_mask_0'	: 1,
+		'mispred_mask_1'	: 1,
+		'mispred_mask_2'	: 1,
+		'old_entry'			: 1,
+		'meta'				: 1,
+		'full_target'		: 1
+	}
+
+	update_fold_hist_dict = {
+		'folded_hist_1' 	: 0b1000,
+		'folded_hist_2' 	: 0b1001,
+		'folded_hist_3' 	: 0b1010,
+		'folded_hist_4' 	: 0b1100,
+		'folded_hist_5' 	: 0b0001,
+		'folded_hist_6' 	: 0b0000,
+		'folded_hist_7' 	: 0b0001,
+		'folded_hist_8' 	: 0b0010,
+		'folded_hist_9' 	: 0b0100,
+		'folded_hist_10' 	: 0b1000,
+		'folded_hist_11' 	: 0b1100,
+		'folded_hist_12' 	: 0b1110,
+		'folded_hist_13' 	: 0b1111,
+		'folded_hist_14' 	: 0b0000,
+		'folded_hist_15' 	: 0b1111,
+		'folded_hist_16' 	: 0b1001,
+		'folded_hist_17' 	: 0b1001
+	}
+
+	task_update_ftb_entry_1		= mlvp.create_task(env.update_ftb_entry_agent.set_update_ftb_entry_value(update_pc,update_ftb_entry_dict)) 
+	task_update_other_1 		= mlvp.create_task(env.update_other_agent.set_update_other_value(update_pc,update_other_dict))
+	task_update_foldedHist_1 	= mlvp.create_task(env.update_fold_hist_agent.set_update_fold_hist_value(update_pc,update_fold_hist_dict))
+
+	await task_update_ftb_entry_1
+	await task_update_other_1
+	await task_update_foldedHist_1
+
+	await task_clock
+	print("test_update_signals_sanity IS OVER")
+
+
+@pytest.mark.mlvp_async
+async def test_update_FtbEntry_foldHist_signals_3(mlvp_request):
+	print(mlvp_request)
+	env: BpuEnv = mlvp_request()
+	update_pc = 0x1248
+
+	enable_dict = {
+		'ubtb_en' 	: 1,	
+		'btb_en'	: 0,
+		'tage_en'	: 0,
+		'sc_en'		: 0,
+		'ras_en'	: 0
+	}
+
+	# rese
+	task_clock = mlvp.create_task(env.update_ftb_entry_agent.bundle.step(2200))
+	await env.update_ftb_entry_agent.reset(4)
+	await env.sub_predi_ctrl_agent.set_sub_predic_ctrl_en(enable_dict)
+	await env.update_ftb_entry_agent.bundle.step(2100)
+	print("begin exec test_update_fold_hist_sanity test")
+
+	update_ftb_entry_dict = {
+		'ftb_entry_valid'	: 1,
+		'tailSlot_valid'	: 1,
+		'tailSlot_tarStat'	: 0b11,
+		'tailSlot_sharing'	: 1,
+		'tailSlot_offset'	: 0b1111,
+		'tailSlot_lower'	: 0x21,
+		'pftAddr'			: 0b1110,
+		'may_be_rvi_call'	: 0,
+		'isRet'				: 0,
+		'isJalr'			: 0,
+		'isCall'			: 0,
+		'carry'				: 0,
+		'always_taken_0'	: 0,
+		'always_taken_1'	: 0,
+		'brSlots_0_valid'	: 0,
+		'brSlots_0_tarStat' : 0b00,
+		'brSlots_0_sharing'	: 0,
+		'brSlots_0_offset'	: 0b0000,
+		'brSlots_0_lower'	: 0x000
+	}
+	## update_other_signals
+	update_other_dict = {
+		'cfi_idx_valid'		: 1,
+		'cfi_idx_bits'		: 0b1000,
+		'br_taken_mask_0'	: 1,
+		'br_taken_mask_1'	: 1,
+		'jmp_taken'			: 0,
+		'mispred_mask_0'	: 0,
+		'mispred_mask_1'	: 0,
+		'mispred_mask_2'	: 0,
+		'old_entry'			: 0,
+		'meta'				: 0,
+		'full_target'		: 0
+	}
+
+	update_fold_hist_dict = {
+		'folded_hist_1' 	: 0b1000,
+		'folded_hist_2' 	: 0b1001,
+		'folded_hist_3' 	: 0b1010,
+		'folded_hist_4' 	: 0b1100,
+		'folded_hist_5' 	: 0b0001,
+		'folded_hist_6' 	: 0b0000,
+		'folded_hist_7' 	: 0b0001,
+		'folded_hist_8' 	: 0b0010,
+		'folded_hist_9' 	: 0b0100,
+		'folded_hist_10' 	: 0b1000,
+		'folded_hist_11' 	: 0b1100,
+		'folded_hist_12' 	: 0b1110,
+		'folded_hist_13' 	: 0b1111,
+		'folded_hist_14' 	: 0b0000,
+		'folded_hist_15' 	: 0b1111,
+		'folded_hist_16' 	: 0b1001,
+		'folded_hist_17' 	: 0b1001
+	}
+
+	task_update_ftb_entry 	= mlvp.create_task(env.update_ftb_entry_agent.set_update_ftb_entry_value(update_pc,update_ftb_entry_dict)) 
+	task_update_other 		= mlvp.create_task(env.update_other_agent.set_update_other_value(update_pc,update_other_dict))
+	task_update_foldedHist 	= mlvp.create_task(env.update_fold_hist_agent.set_update_fold_hist_value(update_pc,update_fold_hist_dict))
+
+	await task_update_ftb_entry
+	await task_update_other
+	await task_update_foldedHist
+
+	await env.update_ftb_entry_agent.bundle.step(1)
+
+	update_ftb_entry_dict = {
+		'ftb_entry_valid'	: 1,
+		'tailSlot_valid'	: 1,
+		'tailSlot_tarStat'	: 0b11,
+		'tailSlot_sharing'	: 1,
+		'tailSlot_offset'	: 0b1111,
+		'tailSlot_lower'	: 0x22,
+		'pftAddr'			: 0b1111,
+		'may_be_rvi_call'	: 1,
+		'isRet'				: 1,
+		'isJalr'			: 1,
+		'isCall'			: 1,
+		'carry'				: 1,
+		'always_taken_0'	: 1,
+		'always_taken_1'	: 1,
+		'brSlots_0_valid'	: 1,
+		'brSlots_0_tarStat' : 0b10,
+		'brSlots_0_sharing'	: 1,
+		'brSlots_0_offset'	: 0b0100,
+		'brSlots_0_lower'	: 0x200
+	}
+
+	## update_other_signals
+	update_other_dict = {
+		'cfi_idx_valid'		: 1,
+		'cfi_idx_bits'		: 0b0111,
+		'br_taken_mask_0'	: 1,
+		'br_taken_mask_1'	: 0,
+		'jmp_taken'			: 1,
+		'mispred_mask_0'	: 1,
+		'mispred_mask_1'	: 1,
+		'mispred_mask_2'	: 1,
+		'old_entry'			: 1,
+		'meta'				: 1,
+		'full_target'		: 1
+	}
+
+	update_fold_hist_dict = {
+		'folded_hist_1' 	: 0b1000,
+		'folded_hist_2' 	: 0b1001,
+		'folded_hist_3' 	: 0b1010,
+		'folded_hist_4' 	: 0b1100,
+		'folded_hist_5' 	: 0b0001,
+		'folded_hist_6' 	: 0b0000,
+		'folded_hist_7' 	: 0b0001,
+		'folded_hist_8' 	: 0b0010,
+		'folded_hist_9' 	: 0b0100,
+		'folded_hist_10' 	: 0b1000,
+		'folded_hist_11' 	: 0b1100,
+		'folded_hist_12' 	: 0b1110,
+		'folded_hist_13' 	: 0b1111,
+		'folded_hist_14' 	: 0b0000,
+		'folded_hist_15' 	: 0b1111,
+		'folded_hist_16' 	: 0b1001,
+		'folded_hist_17' 	: 0b1001
+	}
+
+	task_update_ftb_entry_1		= mlvp.create_task(env.update_ftb_entry_agent.set_update_ftb_entry_value(update_pc,update_ftb_entry_dict)) 
+	task_update_other_1 		= mlvp.create_task(env.update_other_agent.set_update_other_value(update_pc,update_other_dict))
+	task_update_foldedHist_1 	= mlvp.create_task(env.update_fold_hist_agent.set_update_fold_hist_value(update_pc,update_fold_hist_dict))
+
+	await task_update_ftb_entry_1
+	await task_update_other_1
+	await task_update_foldedHist_1
+
+	await task_clock
+	print("test_update_signals_sanity IS OVER")
+
+
+@pytest.mark.mlvp_async
+async def test_update_FtbEntry_foldHist_signals_4(mlvp_request):
+	print(mlvp_request)
+	env: BpuEnv = mlvp_request()
+	update_pc = 0x1248
+
+	enable_dict = {
+		'ubtb_en' 	: 1,	
+		'btb_en'	: 1,
+		'tage_en'	: 1,
+		'sc_en'		: 1,
+		'ras_en'	: 1
+	}
+
+	# reset
+	task_clock = mlvp.create_task(env.update_ftb_entry_agent.bundle.step(2200))
+	await env.update_ftb_entry_agent.reset(4)
+	await env.sub_predi_ctrl_agent.set_sub_predic_ctrl_en(enable_dict)
+	await env.update_ftb_entry_agent.bundle.step(2100)
+	print("begin exec test_update_fold_hist_sanity test")
+
+	update_ftb_entry_dict = {
+		'ftb_entry_valid'	: 1,
+		'tailSlot_valid'	: 1,
+		'tailSlot_tarStat'	: 0b11,
+		'tailSlot_sharing'	: 1,
+		'tailSlot_offset'	: 0b1111,
+		'tailSlot_lower'	: 0x21,
+		'pftAddr'			: 0b1111,
+		'may_be_rvi_call'	: 0,
+		'isRet'				: 0,
+		'isJalr'			: 0,
+		'isCall'			: 0,
+		'carry'				: 0,
+		'always_taken_0'	: 0,
+		'always_taken_1'	: 0,
+		'brSlots_0_valid'	: 0,
+		'brSlots_0_tarStat' : 0b00,
+		'brSlots_0_sharing'	: 0,
+		'brSlots_0_offset'	: 0b0000,
+		'brSlots_0_lower'	: 0x000
+	}
+	## update_other_signals
+	update_other_dict = {
+		'cfi_idx_valid'		: 1,
+		'cfi_idx_bits'		: 0b1000,
+		'br_taken_mask_0'	: 1,
+		'br_taken_mask_1'	: 1,
+		'jmp_taken'			: 0,
+		'mispred_mask_0'	: 0,
+		'mispred_mask_1'	: 0,
+		'mispred_mask_2'	: 0,
+		'old_entry'			: 0,
+		'meta'				: 0,
+		'full_target'		: 0
+	}
+
+	update_fold_hist_dict = {
+		'folded_hist_1' 	: 0b1000,
+		'folded_hist_2' 	: 0b1001,
+		'folded_hist_3' 	: 0b1010,
+		'folded_hist_4' 	: 0b1100,
+		'folded_hist_5' 	: 0b0001,
+		'folded_hist_6' 	: 0b0000,
+		'folded_hist_7' 	: 0b0001,
+		'folded_hist_8' 	: 0b0010,
+		'folded_hist_9' 	: 0b0100,
+		'folded_hist_10' 	: 0b1000,
+		'folded_hist_11' 	: 0b1100,
+		'folded_hist_12' 	: 0b1110,
+		'folded_hist_13' 	: 0b1111,
+		'folded_hist_14' 	: 0b0000,
+		'folded_hist_15' 	: 0b1111,
+		'folded_hist_16' 	: 0b1001,
+		'folded_hist_17' 	: 0b1001
+	}
+
+	task_update_ftb_entry 	= mlvp.create_task(env.update_ftb_entry_agent.set_update_ftb_entry_value(update_pc,update_ftb_entry_dict)) 
+	task_update_other 		= mlvp.create_task(env.update_other_agent.set_update_other_value(update_pc,update_other_dict))
+	task_update_foldedHist 	= mlvp.create_task(env.update_fold_hist_agent.set_update_fold_hist_value(update_pc,update_fold_hist_dict))
+
+	await task_update_ftb_entry
+	await task_update_other
+	await task_update_foldedHist
+
+	await env.update_ftb_entry_agent.bundle.step(1)
+
+	update_ftb_entry_dict = {
+		'ftb_entry_valid'	: 1,
+		'tailSlot_valid'	: 1,
+		'tailSlot_tarStat'	: 0b11,
+		'tailSlot_sharing'	: 1,
+		'tailSlot_offset'	: 0b1111,
+		'tailSlot_lower'	: 0x22,
+		'pftAddr'			: 0b1111,
+		'may_be_rvi_call'	: 1,
+		'isRet'				: 1,
+		'isJalr'			: 1,
+		'isCall'			: 1,
+		'carry'				: 1,
+		'always_taken_0'	: 1,
+		'always_taken_1'	: 1,
+		'brSlots_0_valid'	: 1,
+		'brSlots_0_tarStat' : 0b10,
+		'brSlots_0_sharing'	: 1,
+		'brSlots_0_offset'	: 0b1111,
+		'brSlots_0_lower'	: 0x222
+	}
+
+	## update_other_signals
+	update_other_dict = {
+		'cfi_idx_valid'		: 1,
+		'cfi_idx_bits'		: 0b1111,
+		'br_taken_mask_0'	: 1,
+		'br_taken_mask_1'	: 1,
+		'jmp_taken'			: 1,
+		'mispred_mask_0'	: 1,
+		'mispred_mask_1'	: 1,
+		'mispred_mask_2'	: 1,
+		'old_entry'			: 1,
+		'meta'				: 1,
+		'full_target'		: 1
+	}
+
+	update_fold_hist_dict = {
+		'folded_hist_1' 	: 0b1111,
+		'folded_hist_2' 	: 0b1111,
+		'folded_hist_3' 	: 0b1111,
+		'folded_hist_4' 	: 0b1111,
+		'folded_hist_5' 	: 0b1111,
+		'folded_hist_6' 	: 0b1111,
+		'folded_hist_7' 	: 0b1111,
+		'folded_hist_8' 	: 0b1111,
+		'folded_hist_9' 	: 0b1111,
+		'folded_hist_10' 	: 0b1111,
+		'folded_hist_11' 	: 0b1111,
+		'folded_hist_12' 	: 0b1111,
+		'folded_hist_13' 	: 0b1111,
+		'folded_hist_14' 	: 0b1111,
+		'folded_hist_15' 	: 0b1111,
+		'folded_hist_16' 	: 0b1111,
+		'folded_hist_17' 	: 0b1111
+	}
+
+	task_update_ftb_entry_1		= mlvp.create_task(env.update_ftb_entry_agent.set_update_ftb_entry_value(update_pc,update_ftb_entry_dict)) 
+	task_update_other_1 		= mlvp.create_task(env.update_other_agent.set_update_other_value(update_pc,update_other_dict))
+	task_update_foldedHist_1 	= mlvp.create_task(env.update_fold_hist_agent.set_update_fold_hist_value(update_pc,update_fold_hist_dict))
+
+	await task_update_ftb_entry_1
+	await task_update_other_1
+	await task_update_foldedHist_1
+
+	await task_clock
+	print("test_update_signals_sanity IS OVER")
+
+
+@pytest.mark.mlvp_async
+async def test_update_FtbEntry_foldHist_signals_5(mlvp_request):
+	print(mlvp_request)
+	env: BpuEnv = mlvp_request()
+	update_pc = 0x2428
+
+	enable_dict = {
+		'ubtb_en' 	: 1,	
+		'btb_en'	: 1,
+		'tage_en'	: 1,
+		'sc_en'		: 1,
+		'ras_en'	: 1
+	}
+
+	# reset
+	task_clock = mlvp.create_task(env.update_ftb_entry_agent.bundle.step(2200))
+	await env.update_ftb_entry_agent.reset(4)
+	await env.sub_predi_ctrl_agent.set_sub_predic_ctrl_en(enable_dict)
+	await env.update_ftb_entry_agent.bundle.step(2100)
+	print("begin exec test_update_fold_hist_sanity test")
+
+	update_ftb_entry_dict = {
+		'ftb_entry_valid'	: 1,
+		'tailSlot_valid'	: 1,
+		'tailSlot_tarStat'	: 0b11,
+		'tailSlot_sharing'	: 1,
+		'tailSlot_offset'	: 0b1111,
+		'tailSlot_lower'	: 0x21,
+		'pftAddr'			: 0b1111,
+		'may_be_rvi_call'	: 0,
+		'isRet'				: 0,
+		'isJalr'			: 0,
+		'isCall'			: 0,
+		'carry'				: 0,
+		'always_taken_0'	: 0,
+		'always_taken_1'	: 0,
+		'brSlots_0_valid'	: 0,
+		'brSlots_0_tarStat' : 0b00,
+		'brSlots_0_sharing'	: 0,
+		'brSlots_0_offset'	: 0b0000,
+		'brSlots_0_lower'	: 0x000
+	}
+	## update_other_signals
+	update_other_dict = {
+		'cfi_idx_valid'		: 1,
+		'cfi_idx_bits'		: 0b1000,
+		'br_taken_mask_0'	: 1,
+		'br_taken_mask_1'	: 1,
+		'jmp_taken'			: 0,
+		'mispred_mask_0'	: 0,
+		'mispred_mask_1'	: 0,
+		'mispred_mask_2'	: 0,
+		'old_entry'			: 0,
+		'meta'				: 0,
+		'full_target'		: 0
+	}
+
+	update_fold_hist_dict = {
+		'folded_hist_1' 	: 0b1000,
+		'folded_hist_2' 	: 0b1001,
+		'folded_hist_3' 	: 0b1010,
+		'folded_hist_4' 	: 0b1100,
+		'folded_hist_5' 	: 0b0001,
+		'folded_hist_6' 	: 0b0000,
+		'folded_hist_7' 	: 0b0001,
+		'folded_hist_8' 	: 0b0010,
+		'folded_hist_9' 	: 0b0100,
+		'folded_hist_10' 	: 0b1000,
+		'folded_hist_11' 	: 0b1100,
+		'folded_hist_12' 	: 0b1110,
+		'folded_hist_13' 	: 0b1111,
+		'folded_hist_14' 	: 0b0000,
+		'folded_hist_15' 	: 0b1111,
+		'folded_hist_16' 	: 0b1001,
+		'folded_hist_17' 	: 0b1001
+	}
+
+	task_update_ftb_entry 	= mlvp.create_task(env.update_ftb_entry_agent.set_update_ftb_entry_value(update_pc,update_ftb_entry_dict)) 
+	task_update_other 		= mlvp.create_task(env.update_other_agent.set_update_other_value(update_pc,update_other_dict))
+	task_update_foldedHist 	= mlvp.create_task(env.update_fold_hist_agent.set_update_fold_hist_value(update_pc,update_fold_hist_dict))
+
+	await task_update_ftb_entry
+	await task_update_other
+	await task_update_foldedHist
+
+	await env.update_ftb_entry_agent.bundle.step(20)
+
+	update_ftb_entry_dict = {
+		'ftb_entry_valid'	: 1,
+		'tailSlot_valid'	: 1,
+		'tailSlot_tarStat'	: 0b11,
+		'tailSlot_sharing'	: 1,
+		'tailSlot_offset'	: 0b1111,
+		'tailSlot_lower'	: 0x22,
+		'pftAddr'			: 0b1111,
+		'may_be_rvi_call'	: 1,
+		'isRet'				: 1,
+		'isJalr'			: 1,
+		'isCall'			: 1,
+		'carry'				: 1,
+		'always_taken_0'	: 1,
+		'always_taken_1'	: 1,
+		'brSlots_0_valid'	: 1,
+		'brSlots_0_tarStat' : 0b10,
+		'brSlots_0_sharing'	: 1,
+		'brSlots_0_offset'	: 0b1111,
+		'brSlots_0_lower'	: 0x222
+	}
+
+	## update_other_signals
+	update_other_dict = {
+		'cfi_idx_valid'		: 1,
+		'cfi_idx_bits'		: 0b1111,
+		'br_taken_mask_0'	: 1,
+		'br_taken_mask_1'	: 1,
+		'jmp_taken'			: 1,
+		'mispred_mask_0'	: 1,
+		'mispred_mask_1'	: 1,
+		'mispred_mask_2'	: 1,
+		'old_entry'			: 1,
+		'meta'				: 1,
+		'full_target'		: 1
+	}
+
+	update_fold_hist_dict = {
+		'folded_hist_1' 	: 0b1111,
+		'folded_hist_2' 	: 0b1111,
+		'folded_hist_3' 	: 0b1111,
+		'folded_hist_4' 	: 0b1111,
+		'folded_hist_5' 	: 0b1111,
+		'folded_hist_6' 	: 0b1111,
+		'folded_hist_7' 	: 0b1111,
+		'folded_hist_8' 	: 0b1111,
+		'folded_hist_9' 	: 0b1111,
+		'folded_hist_10' 	: 0b1111,
+		'folded_hist_11' 	: 0b1111,
+		'folded_hist_12' 	: 0b1111,
+		'folded_hist_13' 	: 0b1111,
+		'folded_hist_14' 	: 0b1111,
+		'folded_hist_15' 	: 0b1111,
+		'folded_hist_16' 	: 0b1111,
+		'folded_hist_17' 	: 0b1111
+	}
+
+	task_update_ftb_entry_1		= mlvp.create_task(env.update_ftb_entry_agent.set_update_ftb_entry_value(update_pc,update_ftb_entry_dict)) 
+	task_update_other_1 		= mlvp.create_task(env.update_other_agent.set_update_other_value(update_pc,update_other_dict))
+	task_update_foldedHist_1 	= mlvp.create_task(env.update_fold_hist_agent.set_update_fold_hist_value(update_pc,update_fold_hist_dict))
+
+	await task_update_ftb_entry_1
+	await task_update_other_1
+	await task_update_foldedHist_1
+
+
+####################################
+	await env.update_ftb_entry_agent.bundle.step(20)
+
+	enable_dict = {
+		'ubtb_en' 	: 1,	
+		'btb_en'	: 1,
+		'tage_en'	: 0,
+		'sc_en'		: 0,
+		'ras_en'	: 0
+	}
+
+
+	await env.sub_predi_ctrl_agent.set_sub_predic_ctrl_en(enable_dict)
+	await env.update_ftb_entry_agent.bundle.step(2)
+
+	update_ftb_entry_dict = {
+		'ftb_entry_valid'	: 1,
+		'tailSlot_valid'	: 1,
+		'tailSlot_tarStat'	: 0b11,
+		'tailSlot_sharing'	: 1,
+		'tailSlot_offset'	: 0b1111,
+		'tailSlot_lower'	: 0x22,
+		'pftAddr'			: 0b1111,
+		'may_be_rvi_call'	: 1,
+		'isRet'				: 1,
+		'isJalr'			: 1,
+		'isCall'			: 1,
+		'carry'				: 1,
+		'always_taken_0'	: 1,
+		'always_taken_1'	: 1,
+		'brSlots_0_valid'	: 1,
+		'brSlots_0_tarStat' : 0b10,
+		'brSlots_0_sharing'	: 1,
+		'brSlots_0_offset'	: 0b1111,
+		'brSlots_0_lower'	: 0x222
+	}
+
+	## update_other_signals
+	update_other_dict = {
+		'cfi_idx_valid'		: 1,
+		'cfi_idx_bits'		: 0b1111,
+		'br_taken_mask_0'	: 1,
+		'br_taken_mask_1'	: 1,
+		'jmp_taken'			: 1,
+		'mispred_mask_0'	: 1,
+		'mispred_mask_1'	: 1,
+		'mispred_mask_2'	: 1,
+		'old_entry'			: 1,
+		'meta'				: 1,
+		'full_target'		: 1
+	}
+
+	update_fold_hist_dict = {
+		'folded_hist_1' 	: 0b1111,
+		'folded_hist_2' 	: 0b1111,
+		'folded_hist_3' 	: 0b1111,
+		'folded_hist_4' 	: 0b1111,
+		'folded_hist_5' 	: 0b1111,
+		'folded_hist_6' 	: 0b1111,
+		'folded_hist_7' 	: 0b1111,
+		'folded_hist_8' 	: 0b1111,
+		'folded_hist_9' 	: 0b1111,
+		'folded_hist_10' 	: 0b1111,
+		'folded_hist_11' 	: 0b1111,
+		'folded_hist_12' 	: 0b1111,
+		'folded_hist_13' 	: 0b1111,
+		'folded_hist_14' 	: 0b1111,
+		'folded_hist_15' 	: 0b1111,
+		'folded_hist_16' 	: 0b1111,
+		'folded_hist_17' 	: 0b1111
+	}
+
+	task_update_ftb_entry_1		= mlvp.create_task(env.update_ftb_entry_agent.set_update_ftb_entry_value(update_pc,update_ftb_entry_dict)) 
+	task_update_other_1 		= mlvp.create_task(env.update_other_agent.set_update_other_value(update_pc,update_other_dict))
+	task_update_foldedHist_1 	= mlvp.create_task(env.update_fold_hist_agent.set_update_fold_hist_value(update_pc,update_fold_hist_dict))
+
+	await task_update_ftb_entry_1
+	await task_update_other_1
+	await task_update_foldedHist_1
+
+
+	await task_clock
+	print("test_update_signals_sanity IS OVER")
+
+
+@pytest.mark.mlvp_async
+async def test_update_FtbEntry_foldHist_signals_6(mlvp_request):
+	print(mlvp_request)
+	env: BpuEnv = mlvp_request()
+	update_pc = 0x2428
+
+	enable_dict = {
+		'ubtb_en' 	: 1,	
+		'btb_en'	: 1,
+		'tage_en'	: 1,
+		'sc_en'		: 1,
+		'ras_en'	: 1
+	}
+
+	# reset
+	task_clock = mlvp.create_task(env.update_ftb_entry_agent.bundle.step(2200))
+	await env.update_ftb_entry_agent.reset(4)
+	await env.sub_predi_ctrl_agent.set_sub_predic_ctrl_en(enable_dict)
+	await env.update_ftb_entry_agent.bundle.step(2100)
+	print("begin exec test_update_fold_hist_sanity test")
+
+	update_ftb_entry_dict = {
+		'ftb_entry_valid'	: 1,
+		'tailSlot_valid'	: 1,
+		'tailSlot_tarStat'	: 0b11,
+		'tailSlot_sharing'	: 1,
+		'tailSlot_offset'	: 0b1111,
+		'tailSlot_lower'	: 0x21,
+		'pftAddr'			: 0b1111,
+		'may_be_rvi_call'	: 0,
+		'isRet'				: 0,
+		'isJalr'			: 0,
+		'isCall'			: 0,
+		'carry'				: 0,
+		'always_taken_0'	: 0,
+		'always_taken_1'	: 0,
+		'brSlots_0_valid'	: 0,
+		'brSlots_0_tarStat' : 0b00,
+		'brSlots_0_sharing'	: 0,
+		'brSlots_0_offset'	: 0b0000,
+		'brSlots_0_lower'	: 0x000
+	}
+	## update_other_signals
+	update_other_dict = {
+		'cfi_idx_valid'		: 1,
+		'cfi_idx_bits'		: 0b1000,
+		'br_taken_mask_0'	: 1,
+		'br_taken_mask_1'	: 1,
+		'jmp_taken'			: 0,
+		'mispred_mask_0'	: 0,
+		'mispred_mask_1'	: 0,
+		'mispred_mask_2'	: 0,
+		'old_entry'			: 0,
+		'meta'				: 0,
+		'full_target'		: 0
+	}
+
+	update_fold_hist_dict = {
+		'folded_hist_1' 	: 0b1000,
+		'folded_hist_2' 	: 0b1001,
+		'folded_hist_3' 	: 0b1010,
+		'folded_hist_4' 	: 0b1100,
+		'folded_hist_5' 	: 0b0001,
+		'folded_hist_6' 	: 0b0000,
+		'folded_hist_7' 	: 0b0001,
+		'folded_hist_8' 	: 0b0010,
+		'folded_hist_9' 	: 0b0100,
+		'folded_hist_10' 	: 0b1000,
+		'folded_hist_11' 	: 0b1100,
+		'folded_hist_12' 	: 0b1110,
+		'folded_hist_13' 	: 0b1111,
+		'folded_hist_14' 	: 0b0000,
+		'folded_hist_15' 	: 0b1111,
+		'folded_hist_16' 	: 0b1001,
+		'folded_hist_17' 	: 0b1001
+	}
+
+	task_update_ftb_entry 	= mlvp.create_task(env.update_ftb_entry_agent.set_update_ftb_entry_value(update_pc,update_ftb_entry_dict)) 
+	task_update_other 		= mlvp.create_task(env.update_other_agent.set_update_other_value(update_pc,update_other_dict))
+	task_update_foldedHist 	= mlvp.create_task(env.update_fold_hist_agent.set_update_fold_hist_value(update_pc,update_fold_hist_dict))
+
+	await task_update_ftb_entry
+	await task_update_other
+	await task_update_foldedHist
+
+	await env.update_ftb_entry_agent.bundle.step(20)
+
+	update_ftb_entry_dict = {
+		'ftb_entry_valid'	: 1,
+		'tailSlot_valid'	: 1,
+		'tailSlot_tarStat'	: 0b11,
+		'tailSlot_sharing'	: 1,
+		'tailSlot_offset'	: 0b1111,
+		'tailSlot_lower'	: 0x22,
+		'pftAddr'			: 0b1111,
+		'may_be_rvi_call'	: 1,
+		'isRet'				: 1,
+		'isJalr'			: 1,
+		'isCall'			: 1,
+		'carry'				: 1,
+		'always_taken_0'	: 1,
+		'always_taken_1'	: 1,
+		'brSlots_0_valid'	: 1,
+		'brSlots_0_tarStat' : 0b10,
+		'brSlots_0_sharing'	: 1,
+		'brSlots_0_offset'	: 0b1111,
+		'brSlots_0_lower'	: 0x222
+	}
+
+	## update_other_signals
+	update_other_dict = {
+		'cfi_idx_valid'		: 1,
+		'cfi_idx_bits'		: 0b1111,
+		'br_taken_mask_0'	: 1,
+		'br_taken_mask_1'	: 1,
+		'jmp_taken'			: 1,
+		'mispred_mask_0'	: 1,
+		'mispred_mask_1'	: 1,
+		'mispred_mask_2'	: 1,
+		'old_entry'			: 1,
+		'meta'				: 1,
+		'full_target'		: 1
+	}
+
+	update_fold_hist_dict = {
+		'folded_hist_1' 	: 0b1111,
+		'folded_hist_2' 	: 0b1111,
+		'folded_hist_3' 	: 0b1111,
+		'folded_hist_4' 	: 0b1111,
+		'folded_hist_5' 	: 0b1111,
+		'folded_hist_6' 	: 0b1111,
+		'folded_hist_7' 	: 0b1111,
+		'folded_hist_8' 	: 0b1111,
+		'folded_hist_9' 	: 0b1111,
+		'folded_hist_10' 	: 0b1111,
+		'folded_hist_11' 	: 0b1111,
+		'folded_hist_12' 	: 0b1111,
+		'folded_hist_13' 	: 0b1111,
+		'folded_hist_14' 	: 0b1111,
+		'folded_hist_15' 	: 0b1111,
+		'folded_hist_16' 	: 0b1111,
+		'folded_hist_17' 	: 0b1111
+	}
+
+	task_update_ftb_entry_1		= mlvp.create_task(env.update_ftb_entry_agent.set_update_ftb_entry_value(update_pc,update_ftb_entry_dict)) 
+	task_update_other_1 		= mlvp.create_task(env.update_other_agent.set_update_other_value(update_pc,update_other_dict))
+	task_update_foldedHist_1 	= mlvp.create_task(env.update_fold_hist_agent.set_update_fold_hist_value(update_pc,update_fold_hist_dict))
+
+	await task_update_ftb_entry_1
+	await task_update_other_1
+	await task_update_foldedHist_1
+
+
+####################################
+	await env.update_ftb_entry_agent.bundle.step(20)
+
+	enable_dict = {
+		'ubtb_en' 	: 1,	
+		'btb_en'	: 1,
+		'tage_en'	: 1,
+		'sc_en'		: 0,
+		'ras_en'	: 0
+	}
+
+
+	await env.sub_predi_ctrl_agent.set_sub_predic_ctrl_en(enable_dict)
+	await env.update_ftb_entry_agent.bundle.step(2)
+
+	update_ftb_entry_dict = {
+		'ftb_entry_valid'	: 1,
+		'tailSlot_valid'	: 1,
+		'tailSlot_tarStat'	: 0b11,
+		'tailSlot_sharing'	: 1,
+		'tailSlot_offset'	: 0b1111,
+		'tailSlot_lower'	: 0x22,
+		'pftAddr'			: 0b1111,
+		'may_be_rvi_call'	: 1,
+		'isRet'				: 1,
+		'isJalr'			: 1,
+		'isCall'			: 1,
+		'carry'				: 1,
+		'always_taken_0'	: 1,
+		'always_taken_1'	: 1,
+		'brSlots_0_valid'	: 1,
+		'brSlots_0_tarStat' : 0b10,
+		'brSlots_0_sharing'	: 1,
+		'brSlots_0_offset'	: 0b1111,
+		'brSlots_0_lower'	: 0x222
+	}
+
+	## update_other_signals
+	update_other_dict = {
+		'cfi_idx_valid'		: 1,
+		'cfi_idx_bits'		: 0b1111,
+		'br_taken_mask_0'	: 1,
+		'br_taken_mask_1'	: 1,
+		'jmp_taken'			: 1,
+		'mispred_mask_0'	: 1,
+		'mispred_mask_1'	: 1,
+		'mispred_mask_2'	: 1,
+		'old_entry'			: 1,
+		'meta'				: 1,
+		'full_target'		: 1
+	}
+
+	update_fold_hist_dict = {
+		'folded_hist_1' 	: 0b1111,
+		'folded_hist_2' 	: 0b1111,
+		'folded_hist_3' 	: 0b1111,
+		'folded_hist_4' 	: 0b1111,
+		'folded_hist_5' 	: 0b1111,
+		'folded_hist_6' 	: 0b1111,
+		'folded_hist_7' 	: 0b1111,
+		'folded_hist_8' 	: 0b1111,
+		'folded_hist_9' 	: 0b1111,
+		'folded_hist_10' 	: 0b1111,
+		'folded_hist_11' 	: 0b1111,
+		'folded_hist_12' 	: 0b1111,
+		'folded_hist_13' 	: 0b1111,
+		'folded_hist_14' 	: 0b1111,
+		'folded_hist_15' 	: 0b1111,
+		'folded_hist_16' 	: 0b1111,
+		'folded_hist_17' 	: 0b1111
+	}
+
+	task_update_ftb_entry_1		= mlvp.create_task(env.update_ftb_entry_agent.set_update_ftb_entry_value(update_pc,update_ftb_entry_dict)) 
+	task_update_other_1 		= mlvp.create_task(env.update_other_agent.set_update_other_value(update_pc,update_other_dict))
+	task_update_foldedHist_1 	= mlvp.create_task(env.update_fold_hist_agent.set_update_fold_hist_value(update_pc,update_fold_hist_dict))
+
+	await task_update_ftb_entry_1
+	await task_update_other_1
+	await task_update_foldedHist_1
+
+
+	await env.update_ftb_entry_agent.bundle.step(20)
+
+	enable_dict = {
+		'ubtb_en' 	: 1,	
+		'btb_en'	: 1,
+		'tage_en'	: 1,
+		'sc_en'		: 1,
+		'ras_en'	: 0
+	}
+
+
+	await env.sub_predi_ctrl_agent.set_sub_predic_ctrl_en(enable_dict)
+	await env.update_ftb_entry_agent.bundle.step(2)
+
+	update_ftb_entry_dict = {
+		'ftb_entry_valid'	: 1,
+		'tailSlot_valid'	: 1,
+		'tailSlot_tarStat'	: 0b11,
+		'tailSlot_sharing'	: 1,
+		'tailSlot_offset'	: 0b1111,
+		'tailSlot_lower'	: 0x22,
+		'pftAddr'			: 0b1111,
+		'may_be_rvi_call'	: 1,
+		'isRet'				: 1,
+		'isJalr'			: 1,
+		'isCall'			: 1,
+		'carry'				: 1,
+		'always_taken_0'	: 1,
+		'always_taken_1'	: 1,
+		'brSlots_0_valid'	: 1,
+		'brSlots_0_tarStat' : 0b10,
+		'brSlots_0_sharing'	: 1,
+		'brSlots_0_offset'	: 0b1111,
+		'brSlots_0_lower'	: 0x222
+	}
+
+	## update_other_signals
+	update_other_dict = {
+		'cfi_idx_valid'		: 1,
+		'cfi_idx_bits'		: 0b1111,
+		'br_taken_mask_0'	: 1,
+		'br_taken_mask_1'	: 1,
+		'jmp_taken'			: 1,
+		'mispred_mask_0'	: 1,
+		'mispred_mask_1'	: 1,
+		'mispred_mask_2'	: 1,
+		'old_entry'			: 1,
+		'meta'				: 1,
+		'full_target'		: 1
+	}
+
+	update_fold_hist_dict = {
+		'folded_hist_1' 	: 0b1111,
+		'folded_hist_2' 	: 0b1111,
+		'folded_hist_3' 	: 0b1111,
+		'folded_hist_4' 	: 0b1111,
+		'folded_hist_5' 	: 0b1111,
+		'folded_hist_6' 	: 0b1111,
+		'folded_hist_7' 	: 0b1111,
+		'folded_hist_8' 	: 0b1111,
+		'folded_hist_9' 	: 0b1111,
+		'folded_hist_10' 	: 0b1111,
+		'folded_hist_11' 	: 0b1111,
+		'folded_hist_12' 	: 0b1111,
+		'folded_hist_13' 	: 0b1111,
+		'folded_hist_14' 	: 0b1111,
+		'folded_hist_15' 	: 0b1111,
+		'folded_hist_16' 	: 0b1111,
+		'folded_hist_17' 	: 0b1111
+	}
+
+	task_update_ftb_entry_1		= mlvp.create_task(env.update_ftb_entry_agent.set_update_ftb_entry_value(update_pc,update_ftb_entry_dict)) 
+	task_update_other_1 		= mlvp.create_task(env.update_other_agent.set_update_other_value(update_pc,update_other_dict))
+	task_update_foldedHist_1 	= mlvp.create_task(env.update_fold_hist_agent.set_update_fold_hist_value(update_pc,update_fold_hist_dict))
+
+	await task_update_ftb_entry_1
+	await task_update_other_1
+	await task_update_foldedHist_1
+
+
+	await env.update_ftb_entry_agent.bundle.step(20)
+
+	enable_dict = {
+		'ubtb_en' 	: 1,	
+		'btb_en'	: 0,
+		'tage_en'	: 1,
+		'sc_en'		: 1,
+		'ras_en'	: 0
+	}
+
+
+	await env.sub_predi_ctrl_agent.set_sub_predic_ctrl_en(enable_dict)
+	await env.update_ftb_entry_agent.bundle.step(2)
+
+	update_ftb_entry_dict = {
+		'ftb_entry_valid'	: 1,
+		'tailSlot_valid'	: 1,
+		'tailSlot_tarStat'	: 0b11,
+		'tailSlot_sharing'	: 1,
+		'tailSlot_offset'	: 0b1111,
+		'tailSlot_lower'	: 0x22,
+		'pftAddr'			: 0b1111,
+		'may_be_rvi_call'	: 1,
+		'isRet'				: 1,
+		'isJalr'			: 1,
+		'isCall'			: 1,
+		'carry'				: 1,
+		'always_taken_0'	: 1,
+		'always_taken_1'	: 1,
+		'brSlots_0_valid'	: 1,
+		'brSlots_0_tarStat' : 0b10,
+		'brSlots_0_sharing'	: 1,
+		'brSlots_0_offset'	: 0b1111,
+		'brSlots_0_lower'	: 0x222
+	}
+
+	## update_other_signals
+	update_other_dict = {
+		'cfi_idx_valid'		: 1,
+		'cfi_idx_bits'		: 0b1111,
+		'br_taken_mask_0'	: 1,
+		'br_taken_mask_1'	: 1,
+		'jmp_taken'			: 1,
+		'mispred_mask_0'	: 1,
+		'mispred_mask_1'	: 1,
+		'mispred_mask_2'	: 1,
+		'old_entry'			: 1,
+		'meta'				: 1,
+		'full_target'		: 1
+	}
+
+	update_fold_hist_dict = {
+		'folded_hist_1' 	: 0b1111,
+		'folded_hist_2' 	: 0b1111,
+		'folded_hist_3' 	: 0b1111,
+		'folded_hist_4' 	: 0b1111,
+		'folded_hist_5' 	: 0b1111,
+		'folded_hist_6' 	: 0b1111,
+		'folded_hist_7' 	: 0b1111,
+		'folded_hist_8' 	: 0b1111,
+		'folded_hist_9' 	: 0b1111,
+		'folded_hist_10' 	: 0b1111,
+		'folded_hist_11' 	: 0b1111,
+		'folded_hist_12' 	: 0b1111,
+		'folded_hist_13' 	: 0b1111,
+		'folded_hist_14' 	: 0b1111,
+		'folded_hist_15' 	: 0b1111,
+		'folded_hist_16' 	: 0b1111,
+		'folded_hist_17' 	: 0b1111
+	}
+
+	task_update_ftb_entry_1		= mlvp.create_task(env.update_ftb_entry_agent.set_update_ftb_entry_value(update_pc,update_ftb_entry_dict)) 
+	task_update_other_1 		= mlvp.create_task(env.update_other_agent.set_update_other_value(update_pc,update_other_dict))
+	task_update_foldedHist_1 	= mlvp.create_task(env.update_fold_hist_agent.set_update_fold_hist_value(update_pc,update_fold_hist_dict))
+
+	await task_update_ftb_entry_1
+	await task_update_other_1
+	await task_update_foldedHist_1
+
+
+	await task_clock
+	print("test_update_signals_sanity IS OVER")
+
+
+@pytest.mark.mlvp_async
+async def test_normal_redirect_cfi_twice_5(mlvp_request):
+	print(mlvp_request)
+	env: BpuEnv = mlvp_request()
+	update_pc = 0x2480
+
+	# set value
+	enable_dict = {
+		'ubtb_en' 	: 1,	
+		'btb_en'	: 1,
+		'tage_en'	: 1,
+		'sc_en'		: 1,
+		'ras_en'	: 1
+	}
+
+	rediretc_ohter_dict = {
+		'level'					: 1,
+		'cfiUpdate_pc'			: 0x2280,
+		'cfiUpdate_pd_isRVC'	: 1,
+		'cfiUpdate_pd_isCall'	: 1,
+		'cfiUpdate_pd_isRet'	: 1,
+		'cfiUpdate_ssp'			: 1,
+		'cfiUpdate_sctr'		: 1,
+		'cfiUpdate_TOSW_flag'	: 1,
+		'cfiUpdate_TOSW_value'	: 1,
+		'cfiUpdate_TOSR_flag'	: 1,
+		'cfiUpdate_TOSR_value'	: 1,
+		'cfiUpdate_NOS_flag'	: 1,
+		'cfiUpdate_NOS_value'	: 1,
+
+		'cfiUpdate_lastBrNumOH'	: 1, 
+		'cfiUpdate_histPtr_flag': 1, 
+		'cfiUpdate_histPtr_value':1, 
+		'cfiUpdate_target'		: 1,
+		'cfiUpdate_taken'		: 1,
+		'cfiUpdate_shift'		: 1,
+		'cfiUpdate_addIntoHist'	: 1
+	}
+
+	redirect_fold_hist_dict = {
+		'cfiUpdate_folded_hist_0'	: 0b100,
+		'cfiUpdate_folded_hist_1'	: 0b100,
+		'cfiUpdate_folded_hist_2'	: 0b100,
+		'cfiUpdate_folded_hist_3'	: 0b100,
+		'cfiUpdate_folded_hist_4'	: 0b100,
+		'cfiUpdate_folded_hist_5'	: 0b100,
+		'cfiUpdate_folded_hist_6'	: 0b100,
+		'cfiUpdate_folded_hist_7'	: 0b100,
+		'cfiUpdate_folded_hist_8'	: 0b100,
+		'cfiUpdate_folded_hist_9'	: 0b100,
+
+		'cfiUpdate_folded_hist_10': 0b100,
+		'cfiUpdate_folded_hist_11': 0b100,
+		'cfiUpdate_folded_hist_12': 0b100,
+		'cfiUpdate_folded_hist_13': 0b100,
+		'cfiUpdate_folded_hist_14': 0b100,
+		'cfiUpdate_folded_hist_15': 0b100,
+		'cfiUpdate_folded_hist_16': 0b100,
+		'cfiUpdate_folded_hist_17': 0b100
+	}
+
+	redirect_afhob_dict = {
+		'afhob_0_bits_0'	: 0b1,
+		'afhob_0_bits_1'	: 0b1,
+		'afhob_0_bits_2'	: 0b1,
+		'afhob_0_bits_3'	: 0b1,
+		'afhob_1_bits_0'	: 0b1,
+		'afhob_1_bits_1'	: 0b1,
+		'afhob_1_bits_2'	: 0b1,
+		'afhob_1_bits_3'	: 0b1,
+		'afhob_2_bits_0'	: 0b1,
+		'afhob_2_bits_1'	: 0b1,
+		'afhob_2_bits_2'	: 0b1,
+		'afhob_2_bits_3'	: 0b1,
+		'afhob_3_bits_0'	: 0b1,
+		'afhob_3_bits_1'	: 0b1,
+		'afhob_3_bits_2'	: 0b1,
+		'afhob_3_bits_3'	: 0b1,
+		'afhob_4_bits_0'	: 0b1,
+		'afhob_4_bits_1'	: 0b1,
+		'afhob_4_bits_2'	: 0b1,
+		'afhob_5_bits_0'	: 0b1,
+		'afhob_5_bits_1'	: 0b1,
+		'afhob_5_bits_2'	: 0b1,
+		'afhob_5_bits_3'	: 0b1
+	}
+
+	update_ftb_entry_dict = {
+		'ftb_entry_valid'	: 1,
+		'tailSlot_valid'	: 1,
+		'tailSlot_tarStat'	: 0b10,
+		'tailSlot_sharing'	: 1,
+		'tailSlot_offset'	: 0b0100,
+		'tailSlot_lower'	: 0x20,
+		'pftAddr'			: 0b1000,
+		'may_be_rvi_call'	: 1,
+		'isRet'				: 1,
+		'isJalr'			: 1,
+		'isCall'			: 1,
+		'carry'				: 1,
+		'always_taken_0'	: 1,
+		'always_taken_1'	: 1,
+		'brSlots_0_valid'	: 1,
+		'brSlots_0_tarStat' : 0b10,
+		'brSlots_0_sharing'	: 1,
+		'brSlots_0_offset'	: 0b0100,
+		'brSlots_0_lower'	: 0x200
+	}
+	## update_other_signals
+	update_other_dict = {
+		'cfi_idx_valid'		: 1,
+		'cfi_idx_bits'		: 0b1000,
+		'br_taken_mask_0'	: 1,
+		'br_taken_mask_1'	: 1,
+		'jmp_taken'			: 0,
+		'mispred_mask_0'	: 1,
+		'mispred_mask_1'	: 1,
+		'mispred_mask_2'	: 1,
+		'old_entry'			: 1,
+		'meta'				: 1,
+		'full_target'		: 1
+	}
+
+	update_fold_hist_dict = {
+		'folded_hist_1' 	: 0b1000,
+		'folded_hist_2' 	: 0b1001,
+		'folded_hist_3' 	: 0b1010,
+		'folded_hist_4' 	: 0b1100,
+		'folded_hist_5' 	: 0b0001,
+		'folded_hist_6' 	: 0b0000,
+		'folded_hist_7' 	: 0b0001,
+		'folded_hist_8' 	: 0b0010,
+		'folded_hist_9' 	: 0b0100,
+		'folded_hist_10' 	: 0b1000,
+		'folded_hist_11' 	: 0b1100,
+		'folded_hist_12' 	: 0b1110,
+		'folded_hist_13' 	: 0b1111,
+		'folded_hist_14' 	: 0b0000,
+		'folded_hist_15' 	: 0b1111,
+		'folded_hist_16' 	: 0b1001,
+		'folded_hist_17' 	: 0b1001
+	}
+
+
+	# reset
+	task_clock = mlvp.create_task(env.update_ftb_entry_agent.bundle.step(2200))
+	await env.redirect_other_agent.reset(4)
+	await env.sub_predi_ctrl_agent.set_sub_predic_ctrl_en(enable_dict)
+	await env.redirect_other_agent.bundle.step(2100)	#for the Initial ram
+	# set value
+	print("begin exec test_redirect_cfi_sanity test")
+
+#	await env.redirect_other_agent.set_redirect_other_value()
+	task_redirect_other 	= mlvp.create_task(env.redirect_other_agent.set_redirect_other_value(rediretc_ohter_dict))
+	task_redirect_fold_hist = mlvp.create_task(env.redirect_fold_hist_agent.set_redirect_fold_hist_value(redirect_fold_hist_dict))
+	task_redirect_afhob 	= mlvp.create_task(env.redirect_afhob_agent.set_redirect_afhob_value(redirect_afhob_dict))
+
+	await task_redirect_other 
+	await task_redirect_fold_hist
+	await task_redirect_afhob
+
+	await env.redirect_other_agent.bundle.step(10)
+
+
+	task_update_ftb_entry 	= mlvp.create_task(env.update_ftb_entry_agent.set_update_ftb_entry_value(update_pc,update_ftb_entry_dict)) 
+	task_update_other 		= mlvp.create_task(env.update_other_agent.set_update_other_value(update_pc,update_other_dict))
+	task_update_foldedHist 	= mlvp.create_task(env.update_fold_hist_agent.set_update_fold_hist_value(update_pc,update_fold_hist_dict))
+
+	await task_update_ftb_entry
+	await task_update_other
+	await task_update_foldedHist
+
+	####Second value
+	rediretc_ohter_dict = {
+		'level'					: 1,
+		'cfiUpdate_pc'			: 0x1480,
+		'cfiUpdate_pd_isRVC'	: 0,
+		'cfiUpdate_pd_isCall'	: 0,
+		'cfiUpdate_pd_isRet'	: 0,
+		'cfiUpdate_ssp'			: 0,
+		'cfiUpdate_sctr'		: 0,
+		'cfiUpdate_TOSW_flag'	: 0,
+		'cfiUpdate_TOSW_value'	: 0,
+		'cfiUpdate_TOSR_flag'	: 0,
+		'cfiUpdate_TOSR_value'	: 0,
+		'cfiUpdate_NOS_flag'	: 0,
+		'cfiUpdate_NOS_value'	: 0,
+
+		'cfiUpdate_lastBrNumOH'	: 1, 
+		'cfiUpdate_histPtr_flag': 1, 
+		'cfiUpdate_histPtr_value':0, 
+		'cfiUpdate_target'		: 0,
+		'cfiUpdate_taken'		: 0,
+		'cfiUpdate_shift'		: 1,
+		'cfiUpdate_addIntoHist'	: 1
+	}
+
+	redirect_fold_hist_dict = {
+		'cfiUpdate_folded_hist_0'	: 0b011,
+		'cfiUpdate_folded_hist_1'	: 0b011,
+		'cfiUpdate_folded_hist_2'	: 0b011,
+		'cfiUpdate_folded_hist_3'	: 0b011,
+		'cfiUpdate_folded_hist_4'	: 0b011,
+		'cfiUpdate_folded_hist_5'	: 0b011,
+		'cfiUpdate_folded_hist_6'	: 0b011,
+		'cfiUpdate_folded_hist_7'	: 0b011,
+		'cfiUpdate_folded_hist_8'	: 0b011,
+		'cfiUpdate_folded_hist_9'	: 0b011,
+
+		'cfiUpdate_folded_hist_10': 0b111,
+		'cfiUpdate_folded_hist_11': 0b111,
+		'cfiUpdate_folded_hist_12': 0b111,
+		'cfiUpdate_folded_hist_13': 0b111,
+		'cfiUpdate_folded_hist_14': 0b111,
+		'cfiUpdate_folded_hist_15': 0b111,
+		'cfiUpdate_folded_hist_16': 0b111,
+		'cfiUpdate_folded_hist_17': 0b111
+	}
+
+	redirect_afhob_dict = {
+		'afhob_0_bits_0'	: 0b0,
+		'afhob_0_bits_1'	: 0b0,
+		'afhob_0_bits_2'	: 0b0,
+		'afhob_0_bits_3'	: 0b0,
+		'afhob_1_bits_0'	: 0b0,
+		'afhob_1_bits_1'	: 0b0,
+		'afhob_1_bits_2'	: 0b0,
+		'afhob_1_bits_3'	: 0b0,
+		'afhob_2_bits_0'	: 0b0,
+		'afhob_2_bits_1'	: 0b0,
+		'afhob_2_bits_2'	: 0b0,
+		'afhob_2_bits_3'	: 0b0,
+		'afhob_3_bits_0'	: 0b0,
+		'afhob_3_bits_1'	: 0b0,
+		'afhob_3_bits_2'	: 0b0,
+		'afhob_3_bits_3'	: 0b0,
+		'afhob_4_bits_0'	: 0b0,
+		'afhob_4_bits_1'	: 0b0,
+		'afhob_4_bits_2'	: 0b0,
+		'afhob_5_bits_0'	: 0b0,
+		'afhob_5_bits_1'	: 0b0,
+		'afhob_5_bits_2'	: 0b0,
+		'afhob_5_bits_3'	: 0b0
+	}
+	update_ftb_entry_dict = {
+		'ftb_entry_valid'	: 1,
+		'tailSlot_valid'	: 1,
+		'tailSlot_tarStat'	: 0b11,
+		'tailSlot_sharing'	: 1,
+		'tailSlot_offset'	: 0b1111,
+		'tailSlot_lower'	: 0x22,
+		'pftAddr'			: 0b1111,
+		'may_be_rvi_call'	: 1,
+		'isRet'				: 1,
+		'isJalr'			: 1,
+		'isCall'			: 1,
+		'carry'				: 1,
+		'always_taken_0'	: 1,
+		'always_taken_1'	: 1,
+		'brSlots_0_valid'	: 1,
+		'brSlots_0_tarStat' : 0b10,
+		'brSlots_0_sharing'	: 1,
+		'brSlots_0_offset'	: 0b0100,
+		'brSlots_0_lower'	: 0x200
+	}
+
+	## update_other_signals
+	update_other_dict = {
+		'cfi_idx_valid'		: 1,
+		'cfi_idx_bits'		: 0b0111,
+		'br_taken_mask_0'	: 1,
+		'br_taken_mask_1'	: 0,
+		'jmp_taken'			: 0,
+		'mispred_mask_0'	: 0,
+		'mispred_mask_1'	: 0,
+		'mispred_mask_2'	: 0,
+		'old_entry'			: 0,
+		'meta'				: 0,
+		'full_target'		: 0
+	}
+
+	update_fold_hist_dict = {
+		'folded_hist_1' 	: 0b1000,
+		'folded_hist_2' 	: 0b1001,
+		'folded_hist_3' 	: 0b1010,
+		'folded_hist_4' 	: 0b1100,
+		'folded_hist_5' 	: 0b0001,
+		'folded_hist_6' 	: 0b0000,
+		'folded_hist_7' 	: 0b0001,
+		'folded_hist_8' 	: 0b0010,
+		'folded_hist_9' 	: 0b0100,
+		'folded_hist_10' 	: 0b1000,
+		'folded_hist_11' 	: 0b1100,
+		'folded_hist_12' 	: 0b1110,
+		'folded_hist_13' 	: 0b1111,
+		'folded_hist_14' 	: 0b0000,
+		'folded_hist_15' 	: 0b1111,
+		'folded_hist_16' 	: 0b1001,
+		'folded_hist_17' 	: 0b1001
+	}
+
+	task_redirect_other_1 	= mlvp.create_task(env.redirect_other_agent.set_redirect_other_value(rediretc_ohter_dict))
+	task_redirect_fold_hist_1 = mlvp.create_task(env.redirect_fold_hist_agent.set_redirect_fold_hist_value(redirect_fold_hist_dict))
+	task_redirect_afhob_1 	= mlvp.create_task(env.redirect_afhob_agent.set_redirect_afhob_value(redirect_afhob_dict))
+
+	await task_redirect_other_1 
+	await task_redirect_fold_hist_1
+	await task_redirect_afhob_1
+
+	await env.redirect_other_agent.bundle.step(10)
+
+	task_update_ftb_entry_1 	= mlvp.create_task(env.update_ftb_entry_agent.set_update_ftb_entry_value(update_pc,update_ftb_entry_dict)) 
+	task_update_other_1 		= mlvp.create_task(env.update_other_agent.set_update_other_value(update_pc,update_other_dict))
+	task_update_foldedHist_1 	= mlvp.create_task(env.update_fold_hist_agent.set_update_fold_hist_value(update_pc,update_fold_hist_dict))
+
+	await task_update_ftb_entry_1
+	await task_update_other_1
+	await task_update_foldedHist_1
+
+#	await env.redirect_afhob_agent.set_redirect_afhob_value()
+
+
+
+	enable_dict = {
+		'ubtb_en' 	: 1,	
+		'btb_en'	: 0,
+		'tage_en'	: 0,
+		'sc_en'		: 1,
+		'ras_en'	: 1
+	}
+
+	await env.sub_predi_ctrl_agent.set_sub_predic_ctrl_en(enable_dict)
+	await env.redirect_other_agent.bundle.step(20)	#for the Initial ram
+
+	####Third value
+	rediretc_ohter_dict = {
+		'level'					: 1,
+		'cfiUpdate_pc'			: 0x1480,
+		'cfiUpdate_pd_isRVC'	: 1,
+		'cfiUpdate_pd_isCall'	: 0,
+		'cfiUpdate_pd_isRet'	: 0,
+		'cfiUpdate_ssp'			: 0,
+		'cfiUpdate_sctr'		: 1,
+		'cfiUpdate_TOSW_flag'	: 0,
+		'cfiUpdate_TOSW_value'	: 1,
+		'cfiUpdate_TOSR_flag'	: 0,
+		'cfiUpdate_TOSR_value'	: 0,
+		'cfiUpdate_NOS_flag'	: 1,
+		'cfiUpdate_NOS_value'	: 0,
+
+		'cfiUpdate_lastBrNumOH'	: 1, 
+		'cfiUpdate_histPtr_flag': 1, 
+		'cfiUpdate_histPtr_value':0, 
+		'cfiUpdate_target'		: 1,
+		'cfiUpdate_taken'		: 0,
+		'cfiUpdate_shift'		: 1,
+		'cfiUpdate_addIntoHist'	: 1
+	}
+
+	redirect_fold_hist_dict = {
+		'cfiUpdate_folded_hist_0'	: 0b011,
+		'cfiUpdate_folded_hist_1'	: 0b011,
+		'cfiUpdate_folded_hist_2'	: 0b011,
+		'cfiUpdate_folded_hist_3'	: 0b011,
+		'cfiUpdate_folded_hist_4'	: 0b011,
+		'cfiUpdate_folded_hist_5'	: 0b011,
+		'cfiUpdate_folded_hist_6'	: 0b011,
+		'cfiUpdate_folded_hist_7'	: 0b011,
+		'cfiUpdate_folded_hist_8'	: 0b011,
+		'cfiUpdate_folded_hist_9'	: 0b011,
+
+		'cfiUpdate_folded_hist_10': 0b111,
+		'cfiUpdate_folded_hist_11': 0b111,
+		'cfiUpdate_folded_hist_12': 0b111,
+		'cfiUpdate_folded_hist_13': 0b111,
+		'cfiUpdate_folded_hist_14': 0b111,
+		'cfiUpdate_folded_hist_15': 0b111,
+		'cfiUpdate_folded_hist_16': 0b111,
+		'cfiUpdate_folded_hist_17': 0b111
+	}
+
+	redirect_afhob_dict = {
+		'afhob_0_bits_0'	: 0b1,
+		'afhob_0_bits_1'	: 0b1,
+		'afhob_0_bits_2'	: 0b1,
+		'afhob_0_bits_3'	: 0b1,
+		'afhob_1_bits_0'	: 0b1,
+		'afhob_1_bits_1'	: 0b1,
+		'afhob_1_bits_2'	: 0b1,
+		'afhob_1_bits_3'	: 0b1,
+		'afhob_2_bits_0'	: 0b1,
+		'afhob_2_bits_1'	: 0b1,
+		'afhob_2_bits_2'	: 0b1,
+		'afhob_2_bits_3'	: 0b1,
+		'afhob_3_bits_0'	: 0b1,
+		'afhob_3_bits_1'	: 0b1,
+		'afhob_3_bits_2'	: 0b1,
+		'afhob_3_bits_3'	: 0b1,
+		'afhob_4_bits_0'	: 0b1,
+		'afhob_4_bits_1'	: 0b1,
+		'afhob_4_bits_2'	: 0b1,
+		'afhob_5_bits_0'	: 0b1,
+		'afhob_5_bits_1'	: 0b1,
+		'afhob_5_bits_2'	: 0b1,
+		'afhob_5_bits_3'	: 0b1
+	}
+	update_ftb_entry_dict = {
+		'ftb_entry_valid'	: 1,
+		'tailSlot_valid'	: 1,
+		'tailSlot_tarStat'	: 0b11,
+		'tailSlot_sharing'	: 1,
+		'tailSlot_offset'	: 0b1111,
+		'tailSlot_lower'	: 0x22,
+		'pftAddr'			: 0b1111,
+		'may_be_rvi_call'	: 1,
+		'isRet'				: 1,
+		'isJalr'			: 1,
+		'isCall'			: 1,
+		'carry'				: 1,
+		'always_taken_0'	: 1,
+		'always_taken_1'	: 1,
+		'brSlots_0_valid'	: 1,
+		'brSlots_0_tarStat' : 0b10,
+		'brSlots_0_sharing'	: 1,
+		'brSlots_0_offset'	: 0b0100,
+		'brSlots_0_lower'	: 0x200
+	}
+
+	## update_other_signals
+	update_other_dict = {
+		'cfi_idx_valid'		: 1,
+		'cfi_idx_bits'		: 0b0111,
+		'br_taken_mask_0'	: 1,
+		'br_taken_mask_1'	: 0,
+		'jmp_taken'			: 0,
+		'mispred_mask_0'	: 0,
+		'mispred_mask_1'	: 0,
+		'mispred_mask_2'	: 0,
+		'old_entry'			: 0,
+		'meta'				: 0,
+		'full_target'		: 0
+	}
+
+	update_fold_hist_dict = {
+		'folded_hist_1' 	: 0b1000,
+		'folded_hist_2' 	: 0b1001,
+		'folded_hist_3' 	: 0b1010,
+		'folded_hist_4' 	: 0b1100,
+		'folded_hist_5' 	: 0b0001,
+		'folded_hist_6' 	: 0b0000,
+		'folded_hist_7' 	: 0b0001,
+		'folded_hist_8' 	: 0b0010,
+		'folded_hist_9' 	: 0b0100,
+		'folded_hist_10' 	: 0b1000,
+		'folded_hist_11' 	: 0b1100,
+		'folded_hist_12' 	: 0b1110,
+		'folded_hist_13' 	: 0b1111,
+		'folded_hist_14' 	: 0b0000,
+		'folded_hist_15' 	: 0b1111,
+		'folded_hist_16' 	: 0b1001,
+		'folded_hist_17' 	: 0b1001
+	}
+
+	task_redirect_other_1 	= mlvp.create_task(env.redirect_other_agent.set_redirect_other_value(rediretc_ohter_dict))
+	task_redirect_fold_hist_1 = mlvp.create_task(env.redirect_fold_hist_agent.set_redirect_fold_hist_value(redirect_fold_hist_dict))
+	task_redirect_afhob_1 	= mlvp.create_task(env.redirect_afhob_agent.set_redirect_afhob_value(redirect_afhob_dict))
+
+	await task_redirect_other_1 
+	await task_redirect_fold_hist_1
+	await task_redirect_afhob_1
+
+	await env.redirect_other_agent.bundle.step(10)
+
+	task_update_ftb_entry_1 	= mlvp.create_task(env.update_ftb_entry_agent.set_update_ftb_entry_value(update_pc,update_ftb_entry_dict)) 
+	task_update_other_1 		= mlvp.create_task(env.update_other_agent.set_update_other_value(update_pc,update_other_dict))
+	task_update_foldedHist_1 	= mlvp.create_task(env.update_fold_hist_agent.set_update_fold_hist_value(update_pc,update_fold_hist_dict))
+
+	await task_update_ftb_entry_1
+	await task_update_other_1
+	await task_update_foldedHist_1
+
+
+	await task_clock
+	print("test_normal_sanity IS OVER")
+
+
+@pytest.mark.mlvp_async
+async def test_normal_redirect_cfi_twice_6(mlvp_request):
+	print(mlvp_request)
+	env: BpuEnv = mlvp_request()
+	update_pc = 0x2480
+
+	# set value
+	enable_dict = {
+		'ubtb_en' 	: 1,	
+		'btb_en'	: 1,
+		'tage_en'	: 1,
+		'sc_en'		: 1,
+		'ras_en'	: 1
+	}
+
+	rediretc_ohter_dict = {
+		'level'					: 1,
+		'cfiUpdate_pc'			: 0x2280,
+		'cfiUpdate_pd_isRVC'	: 1,
+		'cfiUpdate_pd_isCall'	: 1,
+		'cfiUpdate_pd_isRet'	: 1,
+		'cfiUpdate_ssp'			: 1,
+		'cfiUpdate_sctr'		: 1,
+		'cfiUpdate_TOSW_flag'	: 1,
+		'cfiUpdate_TOSW_value'	: 1,
+		'cfiUpdate_TOSR_flag'	: 1,
+		'cfiUpdate_TOSR_value'	: 1,
+		'cfiUpdate_NOS_flag'	: 1,
+		'cfiUpdate_NOS_value'	: 1,
+
+		'cfiUpdate_lastBrNumOH'	: 1, 
+		'cfiUpdate_histPtr_flag': 1, 
+		'cfiUpdate_histPtr_value':1, 
+		'cfiUpdate_target'		: 1,
+		'cfiUpdate_taken'		: 1,
+		'cfiUpdate_shift'		: 1,
+		'cfiUpdate_addIntoHist'	: 1
+	}
+
+	redirect_fold_hist_dict = {
+		'cfiUpdate_folded_hist_0'	: 0b100,
+		'cfiUpdate_folded_hist_1'	: 0b100,
+		'cfiUpdate_folded_hist_2'	: 0b100,
+		'cfiUpdate_folded_hist_3'	: 0b100,
+		'cfiUpdate_folded_hist_4'	: 0b100,
+		'cfiUpdate_folded_hist_5'	: 0b100,
+		'cfiUpdate_folded_hist_6'	: 0b100,
+		'cfiUpdate_folded_hist_7'	: 0b100,
+		'cfiUpdate_folded_hist_8'	: 0b100,
+		'cfiUpdate_folded_hist_9'	: 0b100,
+
+		'cfiUpdate_folded_hist_10': 0b100,
+		'cfiUpdate_folded_hist_11': 0b100,
+		'cfiUpdate_folded_hist_12': 0b100,
+		'cfiUpdate_folded_hist_13': 0b100,
+		'cfiUpdate_folded_hist_14': 0b100,
+		'cfiUpdate_folded_hist_15': 0b100,
+		'cfiUpdate_folded_hist_16': 0b100,
+		'cfiUpdate_folded_hist_17': 0b100
+	}
+
+	redirect_afhob_dict = {
+		'afhob_0_bits_0'	: 0b1,
+		'afhob_0_bits_1'	: 0b1,
+		'afhob_0_bits_2'	: 0b1,
+		'afhob_0_bits_3'	: 0b1,
+		'afhob_1_bits_0'	: 0b1,
+		'afhob_1_bits_1'	: 0b1,
+		'afhob_1_bits_2'	: 0b1,
+		'afhob_1_bits_3'	: 0b1,
+		'afhob_2_bits_0'	: 0b1,
+		'afhob_2_bits_1'	: 0b1,
+		'afhob_2_bits_2'	: 0b1,
+		'afhob_2_bits_3'	: 0b1,
+		'afhob_3_bits_0'	: 0b1,
+		'afhob_3_bits_1'	: 0b1,
+		'afhob_3_bits_2'	: 0b1,
+		'afhob_3_bits_3'	: 0b1,
+		'afhob_4_bits_0'	: 0b1,
+		'afhob_4_bits_1'	: 0b1,
+		'afhob_4_bits_2'	: 0b1,
+		'afhob_5_bits_0'	: 0b1,
+		'afhob_5_bits_1'	: 0b1,
+		'afhob_5_bits_2'	: 0b1,
+		'afhob_5_bits_3'	: 0b1
+	}
+
+	update_ftb_entry_dict = {
+		'ftb_entry_valid'	: 1,
+		'tailSlot_valid'	: 1,
+		'tailSlot_tarStat'	: 0b10,
+		'tailSlot_sharing'	: 1,
+		'tailSlot_offset'	: 0b0100,
+		'tailSlot_lower'	: 0x20,
+		'pftAddr'			: 0b1000,
+		'may_be_rvi_call'	: 1,
+		'isRet'				: 1,
+		'isJalr'			: 1,
+		'isCall'			: 1,
+		'carry'				: 1,
+		'always_taken_0'	: 1,
+		'always_taken_1'	: 1,
+		'brSlots_0_valid'	: 1,
+		'brSlots_0_tarStat' : 0b10,
+		'brSlots_0_sharing'	: 1,
+		'brSlots_0_offset'	: 0b0100,
+		'brSlots_0_lower'	: 0x200
+	}
+	## update_other_signals
+	update_other_dict = {
+		'cfi_idx_valid'		: 1,
+		'cfi_idx_bits'		: 0b1000,
+		'br_taken_mask_0'	: 1,
+		'br_taken_mask_1'	: 1,
+		'jmp_taken'			: 0,
+		'mispred_mask_0'	: 1,
+		'mispred_mask_1'	: 1,
+		'mispred_mask_2'	: 1,
+		'old_entry'			: 1,
+		'meta'				: 1,
+		'full_target'		: 1
+	}
+
+	update_fold_hist_dict = {
+		'folded_hist_1' 	: 0b1000,
+		'folded_hist_2' 	: 0b1001,
+		'folded_hist_3' 	: 0b1010,
+		'folded_hist_4' 	: 0b1100,
+		'folded_hist_5' 	: 0b0001,
+		'folded_hist_6' 	: 0b0000,
+		'folded_hist_7' 	: 0b0001,
+		'folded_hist_8' 	: 0b0010,
+		'folded_hist_9' 	: 0b0100,
+		'folded_hist_10' 	: 0b1000,
+		'folded_hist_11' 	: 0b1100,
+		'folded_hist_12' 	: 0b1110,
+		'folded_hist_13' 	: 0b1111,
+		'folded_hist_14' 	: 0b0000,
+		'folded_hist_15' 	: 0b1111,
+		'folded_hist_16' 	: 0b1001,
+		'folded_hist_17' 	: 0b1001
+	}
+
+
+	# reset
+	task_clock = mlvp.create_task(env.update_ftb_entry_agent.bundle.step(2200))
+	await env.redirect_other_agent.reset(4)
+	await env.sub_predi_ctrl_agent.set_sub_predic_ctrl_en(enable_dict)
+	await env.redirect_other_agent.bundle.step(2100)	#for the Initial ram
+	# set value
+	print("begin exec test_redirect_cfi_sanity test")
+
+#	await env.redirect_other_agent.set_redirect_other_value()
+	task_redirect_other 	= mlvp.create_task(env.redirect_other_agent.set_redirect_other_value(rediretc_ohter_dict))
+	task_redirect_fold_hist = mlvp.create_task(env.redirect_fold_hist_agent.set_redirect_fold_hist_value(redirect_fold_hist_dict))
+	task_redirect_afhob 	= mlvp.create_task(env.redirect_afhob_agent.set_redirect_afhob_value(redirect_afhob_dict))
+
+	await task_redirect_other 
+	await task_redirect_fold_hist
+	await task_redirect_afhob
+
+	await env.redirect_other_agent.bundle.step(10)
+
+
+	task_update_ftb_entry 	= mlvp.create_task(env.update_ftb_entry_agent.set_update_ftb_entry_value(update_pc,update_ftb_entry_dict)) 
+	task_update_other 		= mlvp.create_task(env.update_other_agent.set_update_other_value(update_pc,update_other_dict))
+	task_update_foldedHist 	= mlvp.create_task(env.update_fold_hist_agent.set_update_fold_hist_value(update_pc,update_fold_hist_dict))
+
+	await task_update_ftb_entry
+	await task_update_other
+	await task_update_foldedHist
+
+	####Second value
+	rediretc_ohter_dict = {
+		'level'					: 1,
+		'cfiUpdate_pc'			: 0x1480,
+		'cfiUpdate_pd_isRVC'	: 0,
+		'cfiUpdate_pd_isCall'	: 0,
+		'cfiUpdate_pd_isRet'	: 0,
+		'cfiUpdate_ssp'			: 0,
+		'cfiUpdate_sctr'		: 0,
+		'cfiUpdate_TOSW_flag'	: 0,
+		'cfiUpdate_TOSW_value'	: 0,
+		'cfiUpdate_TOSR_flag'	: 0,
+		'cfiUpdate_TOSR_value'	: 0,
+		'cfiUpdate_NOS_flag'	: 0,
+		'cfiUpdate_NOS_value'	: 0,
+
+		'cfiUpdate_lastBrNumOH'	: 1, 
+		'cfiUpdate_histPtr_flag': 1, 
+		'cfiUpdate_histPtr_value':0, 
+		'cfiUpdate_target'		: 0,
+		'cfiUpdate_taken'		: 0,
+		'cfiUpdate_shift'		: 1,
+		'cfiUpdate_addIntoHist'	: 1
+	}
+
+	redirect_fold_hist_dict = {
+		'cfiUpdate_folded_hist_0'	: 0b011,
+		'cfiUpdate_folded_hist_1'	: 0b011,
+		'cfiUpdate_folded_hist_2'	: 0b011,
+		'cfiUpdate_folded_hist_3'	: 0b011,
+		'cfiUpdate_folded_hist_4'	: 0b011,
+		'cfiUpdate_folded_hist_5'	: 0b011,
+		'cfiUpdate_folded_hist_6'	: 0b011,
+		'cfiUpdate_folded_hist_7'	: 0b011,
+		'cfiUpdate_folded_hist_8'	: 0b011,
+		'cfiUpdate_folded_hist_9'	: 0b011,
+
+		'cfiUpdate_folded_hist_10': 0b111,
+		'cfiUpdate_folded_hist_11': 0b111,
+		'cfiUpdate_folded_hist_12': 0b111,
+		'cfiUpdate_folded_hist_13': 0b111,
+		'cfiUpdate_folded_hist_14': 0b111,
+		'cfiUpdate_folded_hist_15': 0b111,
+		'cfiUpdate_folded_hist_16': 0b111,
+		'cfiUpdate_folded_hist_17': 0b111
+	}
+
+	redirect_afhob_dict = {
+		'afhob_0_bits_0'	: 0b0,
+		'afhob_0_bits_1'	: 0b0,
+		'afhob_0_bits_2'	: 0b0,
+		'afhob_0_bits_3'	: 0b0,
+		'afhob_1_bits_0'	: 0b0,
+		'afhob_1_bits_1'	: 0b0,
+		'afhob_1_bits_2'	: 0b0,
+		'afhob_1_bits_3'	: 0b0,
+		'afhob_2_bits_0'	: 0b0,
+		'afhob_2_bits_1'	: 0b0,
+		'afhob_2_bits_2'	: 0b0,
+		'afhob_2_bits_3'	: 0b0,
+		'afhob_3_bits_0'	: 0b0,
+		'afhob_3_bits_1'	: 0b0,
+		'afhob_3_bits_2'	: 0b0,
+		'afhob_3_bits_3'	: 0b0,
+		'afhob_4_bits_0'	: 0b0,
+		'afhob_4_bits_1'	: 0b0,
+		'afhob_4_bits_2'	: 0b0,
+		'afhob_5_bits_0'	: 0b0,
+		'afhob_5_bits_1'	: 0b0,
+		'afhob_5_bits_2'	: 0b0,
+		'afhob_5_bits_3'	: 0b0
+	}
+	update_ftb_entry_dict = {
+		'ftb_entry_valid'	: 1,
+		'tailSlot_valid'	: 1,
+		'tailSlot_tarStat'	: 0b11,
+		'tailSlot_sharing'	: 1,
+		'tailSlot_offset'	: 0b1111,
+		'tailSlot_lower'	: 0x22,
+		'pftAddr'			: 0b1111,
+		'may_be_rvi_call'	: 1,
+		'isRet'				: 1,
+		'isJalr'			: 1,
+		'isCall'			: 1,
+		'carry'				: 1,
+		'always_taken_0'	: 1,
+		'always_taken_1'	: 1,
+		'brSlots_0_valid'	: 1,
+		'brSlots_0_tarStat' : 0b10,
+		'brSlots_0_sharing'	: 1,
+		'brSlots_0_offset'	: 0b0100,
+		'brSlots_0_lower'	: 0x200
+	}
+
+	## update_other_signals
+	update_other_dict = {
+		'cfi_idx_valid'		: 1,
+		'cfi_idx_bits'		: 0b0111,
+		'br_taken_mask_0'	: 1,
+		'br_taken_mask_1'	: 0,
+		'jmp_taken'			: 0,
+		'mispred_mask_0'	: 0,
+		'mispred_mask_1'	: 0,
+		'mispred_mask_2'	: 0,
+		'old_entry'			: 0,
+		'meta'				: 0,
+		'full_target'		: 0
+	}
+
+	update_fold_hist_dict = {
+		'folded_hist_1' 	: 0b1000,
+		'folded_hist_2' 	: 0b1001,
+		'folded_hist_3' 	: 0b1010,
+		'folded_hist_4' 	: 0b1100,
+		'folded_hist_5' 	: 0b0001,
+		'folded_hist_6' 	: 0b0000,
+		'folded_hist_7' 	: 0b0001,
+		'folded_hist_8' 	: 0b0010,
+		'folded_hist_9' 	: 0b0100,
+		'folded_hist_10' 	: 0b1000,
+		'folded_hist_11' 	: 0b1100,
+		'folded_hist_12' 	: 0b1110,
+		'folded_hist_13' 	: 0b1111,
+		'folded_hist_14' 	: 0b0000,
+		'folded_hist_15' 	: 0b1111,
+		'folded_hist_16' 	: 0b1001,
+		'folded_hist_17' 	: 0b1001
+	}
+
+	task_redirect_other_1 	= mlvp.create_task(env.redirect_other_agent.set_redirect_other_value(rediretc_ohter_dict))
+	task_redirect_fold_hist_1 = mlvp.create_task(env.redirect_fold_hist_agent.set_redirect_fold_hist_value(redirect_fold_hist_dict))
+	task_redirect_afhob_1 	= mlvp.create_task(env.redirect_afhob_agent.set_redirect_afhob_value(redirect_afhob_dict))
+
+	await task_redirect_other_1 
+	await task_redirect_fold_hist_1
+	await task_redirect_afhob_1
+
+	await env.redirect_other_agent.bundle.step(10)
+
+	task_update_ftb_entry_1 	= mlvp.create_task(env.update_ftb_entry_agent.set_update_ftb_entry_value(update_pc,update_ftb_entry_dict)) 
+	task_update_other_1 		= mlvp.create_task(env.update_other_agent.set_update_other_value(update_pc,update_other_dict))
+	task_update_foldedHist_1 	= mlvp.create_task(env.update_fold_hist_agent.set_update_fold_hist_value(update_pc,update_fold_hist_dict))
+
+	await task_update_ftb_entry_1
+	await task_update_other_1
+	await task_update_foldedHist_1
+
+#	await env.redirect_afhob_agent.set_redirect_afhob_value()
+
+	enable_dict = {
+		'ubtb_en' 	: 1,	
+		'btb_en'	: 1,
+		'tage_en'	: 0,
+		'sc_en'		: 0,
+		'ras_en'	: 1
+	}
+
+	await env.sub_predi_ctrl_agent.set_sub_predic_ctrl_en(enable_dict)
+	await env.redirect_other_agent.bundle.step(20)	#for the Initial ram
+
+	####Third value
+	rediretc_ohter_dict = {
+		'level'					: 1,
+		'cfiUpdate_pc'			: 0x1480,
+		'cfiUpdate_pd_isRVC'	: 1,
+		'cfiUpdate_pd_isCall'	: 0,
+		'cfiUpdate_pd_isRet'	: 0,
+		'cfiUpdate_ssp'			: 0,
+		'cfiUpdate_sctr'		: 1,
+		'cfiUpdate_TOSW_flag'	: 0,
+		'cfiUpdate_TOSW_value'	: 1,
+		'cfiUpdate_TOSR_flag'	: 0,
+		'cfiUpdate_TOSR_value'	: 0,
+		'cfiUpdate_NOS_flag'	: 1,
+		'cfiUpdate_NOS_value'	: 0,
+
+		'cfiUpdate_lastBrNumOH'	: 1, 
+		'cfiUpdate_histPtr_flag': 1, 
+		'cfiUpdate_histPtr_value':0, 
+		'cfiUpdate_target'		: 1,
+		'cfiUpdate_taken'		: 0,
+		'cfiUpdate_shift'		: 1,
+		'cfiUpdate_addIntoHist'	: 1
+	}
+
+	redirect_fold_hist_dict = {
+		'cfiUpdate_folded_hist_0'	: 0b011,
+		'cfiUpdate_folded_hist_1'	: 0b011,
+		'cfiUpdate_folded_hist_2'	: 0b011,
+		'cfiUpdate_folded_hist_3'	: 0b011,
+		'cfiUpdate_folded_hist_4'	: 0b011,
+		'cfiUpdate_folded_hist_5'	: 0b011,
+		'cfiUpdate_folded_hist_6'	: 0b011,
+		'cfiUpdate_folded_hist_7'	: 0b011,
+		'cfiUpdate_folded_hist_8'	: 0b011,
+		'cfiUpdate_folded_hist_9'	: 0b011,
+
+		'cfiUpdate_folded_hist_10': 0b111,
+		'cfiUpdate_folded_hist_11': 0b111,
+		'cfiUpdate_folded_hist_12': 0b111,
+		'cfiUpdate_folded_hist_13': 0b111,
+		'cfiUpdate_folded_hist_14': 0b111,
+		'cfiUpdate_folded_hist_15': 0b111,
+		'cfiUpdate_folded_hist_16': 0b111,
+		'cfiUpdate_folded_hist_17': 0b111
+	}
+
+	redirect_afhob_dict = {
+		'afhob_0_bits_0'	: 0b1,
+		'afhob_0_bits_1'	: 0b1,
+		'afhob_0_bits_2'	: 0b1,
+		'afhob_0_bits_3'	: 0b1,
+		'afhob_1_bits_0'	: 0b1,
+		'afhob_1_bits_1'	: 0b1,
+		'afhob_1_bits_2'	: 0b1,
+		'afhob_1_bits_3'	: 0b1,
+		'afhob_2_bits_0'	: 0b1,
+		'afhob_2_bits_1'	: 0b1,
+		'afhob_2_bits_2'	: 0b1,
+		'afhob_2_bits_3'	: 0b1,
+		'afhob_3_bits_0'	: 0b1,
+		'afhob_3_bits_1'	: 0b1,
+		'afhob_3_bits_2'	: 0b1,
+		'afhob_3_bits_3'	: 0b1,
+		'afhob_4_bits_0'	: 0b1,
+		'afhob_4_bits_1'	: 0b1,
+		'afhob_4_bits_2'	: 0b1,
+		'afhob_5_bits_0'	: 0b1,
+		'afhob_5_bits_1'	: 0b1,
+		'afhob_5_bits_2'	: 0b1,
+		'afhob_5_bits_3'	: 0b1
+	}
+	update_ftb_entry_dict = {
+		'ftb_entry_valid'	: 1,
+		'tailSlot_valid'	: 1,
+		'tailSlot_tarStat'	: 0b11,
+		'tailSlot_sharing'	: 1,
+		'tailSlot_offset'	: 0b1111,
+		'tailSlot_lower'	: 0x22,
+		'pftAddr'			: 0b1111,
+		'may_be_rvi_call'	: 1,
+		'isRet'				: 1,
+		'isJalr'			: 1,
+		'isCall'			: 1,
+		'carry'				: 1,
+		'always_taken_0'	: 1,
+		'always_taken_1'	: 1,
+		'brSlots_0_valid'	: 1,
+		'brSlots_0_tarStat' : 0b10,
+		'brSlots_0_sharing'	: 1,
+		'brSlots_0_offset'	: 0b0100,
+		'brSlots_0_lower'	: 0x200
+	}
+
+	## update_other_signals
+	update_other_dict = {
+		'cfi_idx_valid'		: 1,
+		'cfi_idx_bits'		: 0b0111,
+		'br_taken_mask_0'	: 1,
+		'br_taken_mask_1'	: 0,
+		'jmp_taken'			: 0,
+		'mispred_mask_0'	: 0,
+		'mispred_mask_1'	: 0,
+		'mispred_mask_2'	: 0,
+		'old_entry'			: 0,
+		'meta'				: 0,
+		'full_target'		: 0
+	}
+
+	update_fold_hist_dict = {
+		'folded_hist_1' 	: 0b1000,
+		'folded_hist_2' 	: 0b1001,
+		'folded_hist_3' 	: 0b1010,
+		'folded_hist_4' 	: 0b1100,
+		'folded_hist_5' 	: 0b0001,
+		'folded_hist_6' 	: 0b0000,
+		'folded_hist_7' 	: 0b0001,
+		'folded_hist_8' 	: 0b0010,
+		'folded_hist_9' 	: 0b0100,
+		'folded_hist_10' 	: 0b1000,
+		'folded_hist_11' 	: 0b1100,
+		'folded_hist_12' 	: 0b1110,
+		'folded_hist_13' 	: 0b1111,
+		'folded_hist_14' 	: 0b0000,
+		'folded_hist_15' 	: 0b1111,
+		'folded_hist_16' 	: 0b1001,
+		'folded_hist_17' 	: 0b1001
+	}
+
+	task_redirect_other_1 	= mlvp.create_task(env.redirect_other_agent.set_redirect_other_value(rediretc_ohter_dict))
+	task_redirect_fold_hist_1 = mlvp.create_task(env.redirect_fold_hist_agent.set_redirect_fold_hist_value(redirect_fold_hist_dict))
+	task_redirect_afhob_1 	= mlvp.create_task(env.redirect_afhob_agent.set_redirect_afhob_value(redirect_afhob_dict))
+
+	await task_redirect_other_1 
+	await task_redirect_fold_hist_1
+	await task_redirect_afhob_1
+
+	await env.redirect_other_agent.bundle.step(10)
+
+	task_update_ftb_entry_1 	= mlvp.create_task(env.update_ftb_entry_agent.set_update_ftb_entry_value(update_pc,update_ftb_entry_dict)) 
+	task_update_other_1 		= mlvp.create_task(env.update_other_agent.set_update_other_value(update_pc,update_other_dict))
+	task_update_foldedHist_1 	= mlvp.create_task(env.update_fold_hist_agent.set_update_fold_hist_value(update_pc,update_fold_hist_dict))
+
+	await task_update_ftb_entry_1
+	await task_update_other_1
+	await task_update_foldedHist_1
+
+
+	await task_clock
+	print("test_normal_sanity IS OVER")
+
+
+@pytest.mark.mlvp_async
+async def test_normal_redirect_cfi_twice_7(mlvp_request):
+	print(mlvp_request)
+	env: BpuEnv = mlvp_request()
+	update_pc = 0x2480
+
+	# set value
+	enable_dict = {
+		'ubtb_en' 	: 1,	
+		'btb_en'	: 1,
+		'tage_en'	: 1,
+		'sc_en'		: 1,
+		'ras_en'	: 1
+	}
+
+	rediretc_ohter_dict = {
+		'level'					: 1,
+		'cfiUpdate_pc'			: 0x2280,
+		'cfiUpdate_pd_isRVC'	: 1,
+		'cfiUpdate_pd_isCall'	: 1,
+		'cfiUpdate_pd_isRet'	: 1,
+		'cfiUpdate_ssp'			: 1,
+		'cfiUpdate_sctr'		: 1,
+		'cfiUpdate_TOSW_flag'	: 1,
+		'cfiUpdate_TOSW_value'	: 1,
+		'cfiUpdate_TOSR_flag'	: 1,
+		'cfiUpdate_TOSR_value'	: 1,
+		'cfiUpdate_NOS_flag'	: 1,
+		'cfiUpdate_NOS_value'	: 1,
+
+		'cfiUpdate_lastBrNumOH'	: 1, 
+		'cfiUpdate_histPtr_flag': 1, 
+		'cfiUpdate_histPtr_value':1, 
+		'cfiUpdate_target'		: 1,
+		'cfiUpdate_taken'		: 1,
+		'cfiUpdate_shift'		: 1,
+		'cfiUpdate_addIntoHist'	: 1
+	}
+
+	redirect_fold_hist_dict = {
+		'cfiUpdate_folded_hist_0'	: 0b100,
+		'cfiUpdate_folded_hist_1'	: 0b100,
+		'cfiUpdate_folded_hist_2'	: 0b100,
+		'cfiUpdate_folded_hist_3'	: 0b100,
+		'cfiUpdate_folded_hist_4'	: 0b100,
+		'cfiUpdate_folded_hist_5'	: 0b100,
+		'cfiUpdate_folded_hist_6'	: 0b100,
+		'cfiUpdate_folded_hist_7'	: 0b100,
+		'cfiUpdate_folded_hist_8'	: 0b100,
+		'cfiUpdate_folded_hist_9'	: 0b100,
+
+		'cfiUpdate_folded_hist_10': 0b100,
+		'cfiUpdate_folded_hist_11': 0b100,
+		'cfiUpdate_folded_hist_12': 0b100,
+		'cfiUpdate_folded_hist_13': 0b100,
+		'cfiUpdate_folded_hist_14': 0b100,
+		'cfiUpdate_folded_hist_15': 0b100,
+		'cfiUpdate_folded_hist_16': 0b100,
+		'cfiUpdate_folded_hist_17': 0b100
+	}
+
+	redirect_afhob_dict = {
+		'afhob_0_bits_0'	: 0b1,
+		'afhob_0_bits_1'	: 0b1,
+		'afhob_0_bits_2'	: 0b1,
+		'afhob_0_bits_3'	: 0b1,
+		'afhob_1_bits_0'	: 0b1,
+		'afhob_1_bits_1'	: 0b1,
+		'afhob_1_bits_2'	: 0b1,
+		'afhob_1_bits_3'	: 0b1,
+		'afhob_2_bits_0'	: 0b1,
+		'afhob_2_bits_1'	: 0b1,
+		'afhob_2_bits_2'	: 0b1,
+		'afhob_2_bits_3'	: 0b1,
+		'afhob_3_bits_0'	: 0b1,
+		'afhob_3_bits_1'	: 0b1,
+		'afhob_3_bits_2'	: 0b1,
+		'afhob_3_bits_3'	: 0b1,
+		'afhob_4_bits_0'	: 0b1,
+		'afhob_4_bits_1'	: 0b1,
+		'afhob_4_bits_2'	: 0b1,
+		'afhob_5_bits_0'	: 0b1,
+		'afhob_5_bits_1'	: 0b1,
+		'afhob_5_bits_2'	: 0b1,
+		'afhob_5_bits_3'	: 0b1
+	}
+
+	update_ftb_entry_dict = {
+		'ftb_entry_valid'	: 1,
+		'tailSlot_valid'	: 1,
+		'tailSlot_tarStat'	: 0b10,
+		'tailSlot_sharing'	: 1,
+		'tailSlot_offset'	: 0b0100,
+		'tailSlot_lower'	: 0x20,
+		'pftAddr'			: 0b1000,
+		'may_be_rvi_call'	: 1,
+		'isRet'				: 1,
+		'isJalr'			: 1,
+		'isCall'			: 1,
+		'carry'				: 1,
+		'always_taken_0'	: 1,
+		'always_taken_1'	: 1,
+		'brSlots_0_valid'	: 1,
+		'brSlots_0_tarStat' : 0b10,
+		'brSlots_0_sharing'	: 1,
+		'brSlots_0_offset'	: 0b0100,
+		'brSlots_0_lower'	: 0x200
+	}
+	## update_other_signals
+	update_other_dict = {
+		'cfi_idx_valid'		: 1,
+		'cfi_idx_bits'		: 0b1000,
+		'br_taken_mask_0'	: 1,
+		'br_taken_mask_1'	: 1,
+		'jmp_taken'			: 0,
+		'mispred_mask_0'	: 1,
+		'mispred_mask_1'	: 1,
+		'mispred_mask_2'	: 1,
+		'old_entry'			: 1,
+		'meta'				: 1,
+		'full_target'		: 1
+	}
+
+	update_fold_hist_dict = {
+		'folded_hist_1' 	: 0b1000,
+		'folded_hist_2' 	: 0b1001,
+		'folded_hist_3' 	: 0b1010,
+		'folded_hist_4' 	: 0b1100,
+		'folded_hist_5' 	: 0b0001,
+		'folded_hist_6' 	: 0b0000,
+		'folded_hist_7' 	: 0b0001,
+		'folded_hist_8' 	: 0b0010,
+		'folded_hist_9' 	: 0b0100,
+		'folded_hist_10' 	: 0b1000,
+		'folded_hist_11' 	: 0b1100,
+		'folded_hist_12' 	: 0b1110,
+		'folded_hist_13' 	: 0b1111,
+		'folded_hist_14' 	: 0b0000,
+		'folded_hist_15' 	: 0b1111,
+		'folded_hist_16' 	: 0b1001,
+		'folded_hist_17' 	: 0b1001
+	}
+
+
+	# reset
+	task_clock = mlvp.create_task(env.update_ftb_entry_agent.bundle.step(2200))
+	await env.redirect_other_agent.reset(4)
+	await env.sub_predi_ctrl_agent.set_sub_predic_ctrl_en(enable_dict)
+	await env.redirect_other_agent.bundle.step(2100)	#for the Initial ram
+	# set value
+	print("begin exec test_redirect_cfi_sanity test")
+
+#	await env.redirect_other_agent.set_redirect_other_value()
+	task_redirect_other 	= mlvp.create_task(env.redirect_other_agent.set_redirect_other_value(rediretc_ohter_dict))
+	task_redirect_fold_hist = mlvp.create_task(env.redirect_fold_hist_agent.set_redirect_fold_hist_value(redirect_fold_hist_dict))
+	task_redirect_afhob 	= mlvp.create_task(env.redirect_afhob_agent.set_redirect_afhob_value(redirect_afhob_dict))
+
+	await task_redirect_other 
+	await task_redirect_fold_hist
+	await task_redirect_afhob
+
+	await env.redirect_other_agent.bundle.step(10)
+
+
+	task_update_ftb_entry 	= mlvp.create_task(env.update_ftb_entry_agent.set_update_ftb_entry_value(update_pc,update_ftb_entry_dict)) 
+	task_update_other 		= mlvp.create_task(env.update_other_agent.set_update_other_value(update_pc,update_other_dict))
+	task_update_foldedHist 	= mlvp.create_task(env.update_fold_hist_agent.set_update_fold_hist_value(update_pc,update_fold_hist_dict))
+
+	await task_update_ftb_entry
+	await task_update_other
+	await task_update_foldedHist
+
+	####Second value
+	rediretc_ohter_dict = {
+		'level'					: 1,
+		'cfiUpdate_pc'			: 0x1480,
+		'cfiUpdate_pd_isRVC'	: 0,
+		'cfiUpdate_pd_isCall'	: 0,
+		'cfiUpdate_pd_isRet'	: 0,
+		'cfiUpdate_ssp'			: 0,
+		'cfiUpdate_sctr'		: 0,
+		'cfiUpdate_TOSW_flag'	: 0,
+		'cfiUpdate_TOSW_value'	: 0,
+		'cfiUpdate_TOSR_flag'	: 0,
+		'cfiUpdate_TOSR_value'	: 0,
+		'cfiUpdate_NOS_flag'	: 0,
+		'cfiUpdate_NOS_value'	: 0,
+
+		'cfiUpdate_lastBrNumOH'	: 1, 
+		'cfiUpdate_histPtr_flag': 1, 
+		'cfiUpdate_histPtr_value':0, 
+		'cfiUpdate_target'		: 0,
+		'cfiUpdate_taken'		: 0,
+		'cfiUpdate_shift'		: 1,
+		'cfiUpdate_addIntoHist'	: 1
+	}
+
+	redirect_fold_hist_dict = {
+		'cfiUpdate_folded_hist_0'	: 0b011,
+		'cfiUpdate_folded_hist_1'	: 0b011,
+		'cfiUpdate_folded_hist_2'	: 0b011,
+		'cfiUpdate_folded_hist_3'	: 0b011,
+		'cfiUpdate_folded_hist_4'	: 0b011,
+		'cfiUpdate_folded_hist_5'	: 0b011,
+		'cfiUpdate_folded_hist_6'	: 0b011,
+		'cfiUpdate_folded_hist_7'	: 0b011,
+		'cfiUpdate_folded_hist_8'	: 0b011,
+		'cfiUpdate_folded_hist_9'	: 0b011,
+
+		'cfiUpdate_folded_hist_10': 0b111,
+		'cfiUpdate_folded_hist_11': 0b111,
+		'cfiUpdate_folded_hist_12': 0b111,
+		'cfiUpdate_folded_hist_13': 0b111,
+		'cfiUpdate_folded_hist_14': 0b111,
+		'cfiUpdate_folded_hist_15': 0b111,
+		'cfiUpdate_folded_hist_16': 0b111,
+		'cfiUpdate_folded_hist_17': 0b111
+	}
+
+	redirect_afhob_dict = {
+		'afhob_0_bits_0'	: 0b0,
+		'afhob_0_bits_1'	: 0b0,
+		'afhob_0_bits_2'	: 0b0,
+		'afhob_0_bits_3'	: 0b0,
+		'afhob_1_bits_0'	: 0b0,
+		'afhob_1_bits_1'	: 0b0,
+		'afhob_1_bits_2'	: 0b0,
+		'afhob_1_bits_3'	: 0b0,
+		'afhob_2_bits_0'	: 0b0,
+		'afhob_2_bits_1'	: 0b0,
+		'afhob_2_bits_2'	: 0b0,
+		'afhob_2_bits_3'	: 0b0,
+		'afhob_3_bits_0'	: 0b0,
+		'afhob_3_bits_1'	: 0b0,
+		'afhob_3_bits_2'	: 0b0,
+		'afhob_3_bits_3'	: 0b0,
+		'afhob_4_bits_0'	: 0b0,
+		'afhob_4_bits_1'	: 0b0,
+		'afhob_4_bits_2'	: 0b0,
+		'afhob_5_bits_0'	: 0b0,
+		'afhob_5_bits_1'	: 0b0,
+		'afhob_5_bits_2'	: 0b0,
+		'afhob_5_bits_3'	: 0b0
+	}
+	update_ftb_entry_dict = {
+		'ftb_entry_valid'	: 1,
+		'tailSlot_valid'	: 1,
+		'tailSlot_tarStat'	: 0b11,
+		'tailSlot_sharing'	: 1,
+		'tailSlot_offset'	: 0b1111,
+		'tailSlot_lower'	: 0x22,
+		'pftAddr'			: 0b1111,
+		'may_be_rvi_call'	: 1,
+		'isRet'				: 1,
+		'isJalr'			: 1,
+		'isCall'			: 1,
+		'carry'				: 1,
+		'always_taken_0'	: 1,
+		'always_taken_1'	: 1,
+		'brSlots_0_valid'	: 1,
+		'brSlots_0_tarStat' : 0b10,
+		'brSlots_0_sharing'	: 1,
+		'brSlots_0_offset'	: 0b0100,
+		'brSlots_0_lower'	: 0x200
+	}
+
+	## update_other_signals
+	update_other_dict = {
+		'cfi_idx_valid'		: 1,
+		'cfi_idx_bits'		: 0b0111,
+		'br_taken_mask_0'	: 1,
+		'br_taken_mask_1'	: 0,
+		'jmp_taken'			: 0,
+		'mispred_mask_0'	: 0,
+		'mispred_mask_1'	: 0,
+		'mispred_mask_2'	: 0,
+		'old_entry'			: 0,
+		'meta'				: 0,
+		'full_target'		: 0
+	}
+
+	update_fold_hist_dict = {
+		'folded_hist_1' 	: 0b1000,
+		'folded_hist_2' 	: 0b1001,
+		'folded_hist_3' 	: 0b1010,
+		'folded_hist_4' 	: 0b1100,
+		'folded_hist_5' 	: 0b0001,
+		'folded_hist_6' 	: 0b0000,
+		'folded_hist_7' 	: 0b0001,
+		'folded_hist_8' 	: 0b0010,
+		'folded_hist_9' 	: 0b0100,
+		'folded_hist_10' 	: 0b1000,
+		'folded_hist_11' 	: 0b1100,
+		'folded_hist_12' 	: 0b1110,
+		'folded_hist_13' 	: 0b1111,
+		'folded_hist_14' 	: 0b0000,
+		'folded_hist_15' 	: 0b1111,
+		'folded_hist_16' 	: 0b1001,
+		'folded_hist_17' 	: 0b1001
+	}
+
+	task_redirect_other_1 	= mlvp.create_task(env.redirect_other_agent.set_redirect_other_value(rediretc_ohter_dict))
+	task_redirect_fold_hist_1 = mlvp.create_task(env.redirect_fold_hist_agent.set_redirect_fold_hist_value(redirect_fold_hist_dict))
+	task_redirect_afhob_1 	= mlvp.create_task(env.redirect_afhob_agent.set_redirect_afhob_value(redirect_afhob_dict))
+
+	await task_redirect_other_1 
+	await task_redirect_fold_hist_1
+	await task_redirect_afhob_1
+
+	await env.redirect_other_agent.bundle.step(10)
+
+	task_update_ftb_entry_1 	= mlvp.create_task(env.update_ftb_entry_agent.set_update_ftb_entry_value(update_pc,update_ftb_entry_dict)) 
+	task_update_other_1 		= mlvp.create_task(env.update_other_agent.set_update_other_value(update_pc,update_other_dict))
+	task_update_foldedHist_1 	= mlvp.create_task(env.update_fold_hist_agent.set_update_fold_hist_value(update_pc,update_fold_hist_dict))
+
+	await task_update_ftb_entry_1
+	await task_update_other_1
+	await task_update_foldedHist_1
+
+#	await env.redirect_afhob_agent.set_redirect_afhob_value()
+
+	enable_dict = {
+		'ubtb_en' 	: 1,	
+		'btb_en'	: 0,
+		'tage_en'	: 0,
+		'sc_en'		: 0,
+		'ras_en'	: 0
+	}
+
+	await env.sub_predi_ctrl_agent.set_sub_predic_ctrl_en(enable_dict)
+	await env.redirect_other_agent.bundle.step(20)	#for the Initial ram
+
+	####Third value
+	rediretc_ohter_dict = {
+		'level'					: 1,
+		'cfiUpdate_pc'			: 0x1480,
+		'cfiUpdate_pd_isRVC'	: 1,
+		'cfiUpdate_pd_isCall'	: 0,
+		'cfiUpdate_pd_isRet'	: 0,
+		'cfiUpdate_ssp'			: 0,
+		'cfiUpdate_sctr'		: 1,
+		'cfiUpdate_TOSW_flag'	: 0,
+		'cfiUpdate_TOSW_value'	: 1,
+		'cfiUpdate_TOSR_flag'	: 0,
+		'cfiUpdate_TOSR_value'	: 0,
+		'cfiUpdate_NOS_flag'	: 1,
+		'cfiUpdate_NOS_value'	: 0,
+
+		'cfiUpdate_lastBrNumOH'	: 1, 
+		'cfiUpdate_histPtr_flag': 1, 
+		'cfiUpdate_histPtr_value':0, 
+		'cfiUpdate_target'		: 1,
+		'cfiUpdate_taken'		: 0,
+		'cfiUpdate_shift'		: 1,
+		'cfiUpdate_addIntoHist'	: 1
+	}
+
+	redirect_fold_hist_dict = {
+		'cfiUpdate_folded_hist_0'	: 0b011,
+		'cfiUpdate_folded_hist_1'	: 0b011,
+		'cfiUpdate_folded_hist_2'	: 0b011,
+		'cfiUpdate_folded_hist_3'	: 0b011,
+		'cfiUpdate_folded_hist_4'	: 0b011,
+		'cfiUpdate_folded_hist_5'	: 0b011,
+		'cfiUpdate_folded_hist_6'	: 0b011,
+		'cfiUpdate_folded_hist_7'	: 0b011,
+		'cfiUpdate_folded_hist_8'	: 0b011,
+		'cfiUpdate_folded_hist_9'	: 0b011,
+
+		'cfiUpdate_folded_hist_10': 0b111,
+		'cfiUpdate_folded_hist_11': 0b111,
+		'cfiUpdate_folded_hist_12': 0b111,
+		'cfiUpdate_folded_hist_13': 0b111,
+		'cfiUpdate_folded_hist_14': 0b111,
+		'cfiUpdate_folded_hist_15': 0b111,
+		'cfiUpdate_folded_hist_16': 0b111,
+		'cfiUpdate_folded_hist_17': 0b111
+	}
+
+	redirect_afhob_dict = {
+		'afhob_0_bits_0'	: 0b1,
+		'afhob_0_bits_1'	: 0b1,
+		'afhob_0_bits_2'	: 0b1,
+		'afhob_0_bits_3'	: 0b1,
+		'afhob_1_bits_0'	: 0b1,
+		'afhob_1_bits_1'	: 0b1,
+		'afhob_1_bits_2'	: 0b1,
+		'afhob_1_bits_3'	: 0b1,
+		'afhob_2_bits_0'	: 0b1,
+		'afhob_2_bits_1'	: 0b1,
+		'afhob_2_bits_2'	: 0b1,
+		'afhob_2_bits_3'	: 0b1,
+		'afhob_3_bits_0'	: 0b1,
+		'afhob_3_bits_1'	: 0b1,
+		'afhob_3_bits_2'	: 0b1,
+		'afhob_3_bits_3'	: 0b1,
+		'afhob_4_bits_0'	: 0b1,
+		'afhob_4_bits_1'	: 0b1,
+		'afhob_4_bits_2'	: 0b1,
+		'afhob_5_bits_0'	: 0b1,
+		'afhob_5_bits_1'	: 0b1,
+		'afhob_5_bits_2'	: 0b1,
+		'afhob_5_bits_3'	: 0b1
+	}
+	update_ftb_entry_dict = {
+		'ftb_entry_valid'	: 1,
+		'tailSlot_valid'	: 1,
+		'tailSlot_tarStat'	: 0b11,
+		'tailSlot_sharing'	: 1,
+		'tailSlot_offset'	: 0b1111,
+		'tailSlot_lower'	: 0x22,
+		'pftAddr'			: 0b1111,
+		'may_be_rvi_call'	: 1,
+		'isRet'				: 1,
+		'isJalr'			: 1,
+		'isCall'			: 1,
+		'carry'				: 1,
+		'always_taken_0'	: 1,
+		'always_taken_1'	: 1,
+		'brSlots_0_valid'	: 1,
+		'brSlots_0_tarStat' : 0b10,
+		'brSlots_0_sharing'	: 1,
+		'brSlots_0_offset'	: 0b0100,
+		'brSlots_0_lower'	: 0x200
+	}
+
+	## update_other_signals
+	update_other_dict = {
+		'cfi_idx_valid'		: 1,
+		'cfi_idx_bits'		: 0b0111,
+		'br_taken_mask_0'	: 1,
+		'br_taken_mask_1'	: 0,
+		'jmp_taken'			: 0,
+		'mispred_mask_0'	: 0,
+		'mispred_mask_1'	: 0,
+		'mispred_mask_2'	: 0,
+		'old_entry'			: 0,
+		'meta'				: 0,
+		'full_target'		: 0
+	}
+
+	update_fold_hist_dict = {
+		'folded_hist_1' 	: 0b1000,
+		'folded_hist_2' 	: 0b1001,
+		'folded_hist_3' 	: 0b1010,
+		'folded_hist_4' 	: 0b1100,
+		'folded_hist_5' 	: 0b0001,
+		'folded_hist_6' 	: 0b0000,
+		'folded_hist_7' 	: 0b0001,
+		'folded_hist_8' 	: 0b0010,
+		'folded_hist_9' 	: 0b0100,
+		'folded_hist_10' 	: 0b1000,
+		'folded_hist_11' 	: 0b1100,
+		'folded_hist_12' 	: 0b1110,
+		'folded_hist_13' 	: 0b1111,
+		'folded_hist_14' 	: 0b0000,
+		'folded_hist_15' 	: 0b1111,
+		'folded_hist_16' 	: 0b1001,
+		'folded_hist_17' 	: 0b1001
+	}
+
+	task_redirect_other_1 	= mlvp.create_task(env.redirect_other_agent.set_redirect_other_value(rediretc_ohter_dict))
+	task_redirect_fold_hist_1 = mlvp.create_task(env.redirect_fold_hist_agent.set_redirect_fold_hist_value(redirect_fold_hist_dict))
+	task_redirect_afhob_1 	= mlvp.create_task(env.redirect_afhob_agent.set_redirect_afhob_value(redirect_afhob_dict))
+
+	await task_redirect_other_1 
+	await task_redirect_fold_hist_1
+	await task_redirect_afhob_1
+
+	await env.redirect_other_agent.bundle.step(10)
+
+	task_update_ftb_entry_1 	= mlvp.create_task(env.update_ftb_entry_agent.set_update_ftb_entry_value(update_pc,update_ftb_entry_dict)) 
+	task_update_other_1 		= mlvp.create_task(env.update_other_agent.set_update_other_value(update_pc,update_other_dict))
+	task_update_foldedHist_1 	= mlvp.create_task(env.update_fold_hist_agent.set_update_fold_hist_value(update_pc,update_fold_hist_dict))
+
+	await task_update_ftb_entry_1
+	await task_update_other_1
+	await task_update_foldedHist_1
+
+
+	await task_clock
+	print("test_normal_sanity IS OVER")
+
+
+@pytest.mark.mlvp_async
+async def test_normal_redirect_cfi_twice_8(mlvp_request):
+	print(mlvp_request)
+	env: BpuEnv = mlvp_request()
+	update_pc = 0x2480
+
+	# set value
+	enable_dict = {
+		'ubtb_en' 	: 1,	
+		'btb_en'	: 1,
+		'tage_en'	: 1,
+		'sc_en'		: 1,
+		'ras_en'	: 1
+	}
+
+	rediretc_ohter_dict = {
+		'level'					: 1,
+		'cfiUpdate_pc'			: 0x2280,
+		'cfiUpdate_pd_isRVC'	: 1,
+		'cfiUpdate_pd_isCall'	: 1,
+		'cfiUpdate_pd_isRet'	: 1,
+		'cfiUpdate_ssp'			: 1,
+		'cfiUpdate_sctr'		: 1,
+		'cfiUpdate_TOSW_flag'	: 1,
+		'cfiUpdate_TOSW_value'	: 1,
+		'cfiUpdate_TOSR_flag'	: 1,
+		'cfiUpdate_TOSR_value'	: 1,
+		'cfiUpdate_NOS_flag'	: 1,
+		'cfiUpdate_NOS_value'	: 1,
+
+		'cfiUpdate_lastBrNumOH'	: 1, 
+		'cfiUpdate_histPtr_flag': 1, 
+		'cfiUpdate_histPtr_value':1, 
+		'cfiUpdate_target'		: 1,
+		'cfiUpdate_taken'		: 1,
+		'cfiUpdate_shift'		: 1,
+		'cfiUpdate_addIntoHist'	: 1
+	}
+
+	redirect_fold_hist_dict = {
+		'cfiUpdate_folded_hist_0'	: 0b100,
+		'cfiUpdate_folded_hist_1'	: 0b100,
+		'cfiUpdate_folded_hist_2'	: 0b100,
+		'cfiUpdate_folded_hist_3'	: 0b100,
+		'cfiUpdate_folded_hist_4'	: 0b100,
+		'cfiUpdate_folded_hist_5'	: 0b100,
+		'cfiUpdate_folded_hist_6'	: 0b100,
+		'cfiUpdate_folded_hist_7'	: 0b100,
+		'cfiUpdate_folded_hist_8'	: 0b100,
+		'cfiUpdate_folded_hist_9'	: 0b100,
+
+		'cfiUpdate_folded_hist_10': 0b100,
+		'cfiUpdate_folded_hist_11': 0b100,
+		'cfiUpdate_folded_hist_12': 0b100,
+		'cfiUpdate_folded_hist_13': 0b100,
+		'cfiUpdate_folded_hist_14': 0b100,
+		'cfiUpdate_folded_hist_15': 0b100,
+		'cfiUpdate_folded_hist_16': 0b100,
+		'cfiUpdate_folded_hist_17': 0b100
+	}
+
+	redirect_afhob_dict = {
+		'afhob_0_bits_0'	: 0b1,
+		'afhob_0_bits_1'	: 0b1,
+		'afhob_0_bits_2'	: 0b1,
+		'afhob_0_bits_3'	: 0b1,
+		'afhob_1_bits_0'	: 0b1,
+		'afhob_1_bits_1'	: 0b1,
+		'afhob_1_bits_2'	: 0b1,
+		'afhob_1_bits_3'	: 0b1,
+		'afhob_2_bits_0'	: 0b1,
+		'afhob_2_bits_1'	: 0b1,
+		'afhob_2_bits_2'	: 0b1,
+		'afhob_2_bits_3'	: 0b1,
+		'afhob_3_bits_0'	: 0b1,
+		'afhob_3_bits_1'	: 0b1,
+		'afhob_3_bits_2'	: 0b1,
+		'afhob_3_bits_3'	: 0b1,
+		'afhob_4_bits_0'	: 0b1,
+		'afhob_4_bits_1'	: 0b1,
+		'afhob_4_bits_2'	: 0b1,
+		'afhob_5_bits_0'	: 0b1,
+		'afhob_5_bits_1'	: 0b1,
+		'afhob_5_bits_2'	: 0b1,
+		'afhob_5_bits_3'	: 0b1
+	}
+
+	update_ftb_entry_dict = {
+		'ftb_entry_valid'	: 1,
+		'tailSlot_valid'	: 1,
+		'tailSlot_tarStat'	: 0b10,
+		'tailSlot_sharing'	: 1,
+		'tailSlot_offset'	: 0b0100,
+		'tailSlot_lower'	: 0x20,
+		'pftAddr'			: 0b1000,
+		'may_be_rvi_call'	: 1,
+		'isRet'				: 1,
+		'isJalr'			: 1,
+		'isCall'			: 1,
+		'carry'				: 1,
+		'always_taken_0'	: 1,
+		'always_taken_1'	: 1,
+		'brSlots_0_valid'	: 1,
+		'brSlots_0_tarStat' : 0b10,
+		'brSlots_0_sharing'	: 1,
+		'brSlots_0_offset'	: 0b0100,
+		'brSlots_0_lower'	: 0x200
+	}
+	## update_other_signals
+	update_other_dict = {
+		'cfi_idx_valid'		: 1,
+		'cfi_idx_bits'		: 0b1000,
+		'br_taken_mask_0'	: 1,
+		'br_taken_mask_1'	: 1,
+		'jmp_taken'			: 0,
+		'mispred_mask_0'	: 1,
+		'mispred_mask_1'	: 1,
+		'mispred_mask_2'	: 1,
+		'old_entry'			: 1,
+		'meta'				: 1,
+		'full_target'		: 1
+	}
+
+	update_fold_hist_dict = {
+		'folded_hist_1' 	: 0b1000,
+		'folded_hist_2' 	: 0b1001,
+		'folded_hist_3' 	: 0b1010,
+		'folded_hist_4' 	: 0b1100,
+		'folded_hist_5' 	: 0b0001,
+		'folded_hist_6' 	: 0b0000,
+		'folded_hist_7' 	: 0b0001,
+		'folded_hist_8' 	: 0b0010,
+		'folded_hist_9' 	: 0b0100,
+		'folded_hist_10' 	: 0b1000,
+		'folded_hist_11' 	: 0b1100,
+		'folded_hist_12' 	: 0b1110,
+		'folded_hist_13' 	: 0b1111,
+		'folded_hist_14' 	: 0b0000,
+		'folded_hist_15' 	: 0b1111,
+		'folded_hist_16' 	: 0b1001,
+		'folded_hist_17' 	: 0b1001
+	}
+
+
+	# reset
+	task_clock = mlvp.create_task(env.update_ftb_entry_agent.bundle.step(2200))
+	await env.redirect_other_agent.reset(4)
+	await env.sub_predi_ctrl_agent.set_sub_predic_ctrl_en(enable_dict)
+	await env.redirect_other_agent.bundle.step(2100)	#for the Initial ram
+	# set value
+	print("begin exec test_redirect_cfi_sanity test")
+
+#	await env.redirect_other_agent.set_redirect_other_value()
+	task_redirect_other 	= mlvp.create_task(env.redirect_other_agent.set_redirect_other_value(rediretc_ohter_dict))
+	task_redirect_fold_hist = mlvp.create_task(env.redirect_fold_hist_agent.set_redirect_fold_hist_value(redirect_fold_hist_dict))
+	task_redirect_afhob 	= mlvp.create_task(env.redirect_afhob_agent.set_redirect_afhob_value(redirect_afhob_dict))
+
+	await task_redirect_other 
+	await task_redirect_fold_hist
+	await task_redirect_afhob
+
+	await env.redirect_other_agent.bundle.step(10)
+
+
+	task_update_ftb_entry 	= mlvp.create_task(env.update_ftb_entry_agent.set_update_ftb_entry_value(update_pc,update_ftb_entry_dict)) 
+	task_update_other 		= mlvp.create_task(env.update_other_agent.set_update_other_value(update_pc,update_other_dict))
+	task_update_foldedHist 	= mlvp.create_task(env.update_fold_hist_agent.set_update_fold_hist_value(update_pc,update_fold_hist_dict))
+
+	await task_update_ftb_entry
+	await task_update_other
+	await task_update_foldedHist
+
+	####Second value
+	rediretc_ohter_dict = {
+		'level'					: 1,
+		'cfiUpdate_pc'			: 0x1480,
+		'cfiUpdate_pd_isRVC'	: 0,
+		'cfiUpdate_pd_isCall'	: 0,
+		'cfiUpdate_pd_isRet'	: 0,
+		'cfiUpdate_ssp'			: 0,
+		'cfiUpdate_sctr'		: 0,
+		'cfiUpdate_TOSW_flag'	: 0,
+		'cfiUpdate_TOSW_value'	: 0,
+		'cfiUpdate_TOSR_flag'	: 0,
+		'cfiUpdate_TOSR_value'	: 0,
+		'cfiUpdate_NOS_flag'	: 0,
+		'cfiUpdate_NOS_value'	: 0,
+
+		'cfiUpdate_lastBrNumOH'	: 1, 
+		'cfiUpdate_histPtr_flag': 1, 
+		'cfiUpdate_histPtr_value':0, 
+		'cfiUpdate_target'		: 0,
+		'cfiUpdate_taken'		: 0,
+		'cfiUpdate_shift'		: 1,
+		'cfiUpdate_addIntoHist'	: 1
+	}
+
+	redirect_fold_hist_dict = {
+		'cfiUpdate_folded_hist_0'	: 0b011,
+		'cfiUpdate_folded_hist_1'	: 0b011,
+		'cfiUpdate_folded_hist_2'	: 0b011,
+		'cfiUpdate_folded_hist_3'	: 0b011,
+		'cfiUpdate_folded_hist_4'	: 0b011,
+		'cfiUpdate_folded_hist_5'	: 0b011,
+		'cfiUpdate_folded_hist_6'	: 0b011,
+		'cfiUpdate_folded_hist_7'	: 0b011,
+		'cfiUpdate_folded_hist_8'	: 0b011,
+		'cfiUpdate_folded_hist_9'	: 0b011,
+
+		'cfiUpdate_folded_hist_10': 0b111,
+		'cfiUpdate_folded_hist_11': 0b111,
+		'cfiUpdate_folded_hist_12': 0b111,
+		'cfiUpdate_folded_hist_13': 0b111,
+		'cfiUpdate_folded_hist_14': 0b111,
+		'cfiUpdate_folded_hist_15': 0b111,
+		'cfiUpdate_folded_hist_16': 0b111,
+		'cfiUpdate_folded_hist_17': 0b111
+	}
+
+	redirect_afhob_dict = {
+		'afhob_0_bits_0'	: 0b0,
+		'afhob_0_bits_1'	: 0b0,
+		'afhob_0_bits_2'	: 0b0,
+		'afhob_0_bits_3'	: 0b0,
+		'afhob_1_bits_0'	: 0b0,
+		'afhob_1_bits_1'	: 0b0,
+		'afhob_1_bits_2'	: 0b0,
+		'afhob_1_bits_3'	: 0b0,
+		'afhob_2_bits_0'	: 0b0,
+		'afhob_2_bits_1'	: 0b0,
+		'afhob_2_bits_2'	: 0b0,
+		'afhob_2_bits_3'	: 0b0,
+		'afhob_3_bits_0'	: 0b0,
+		'afhob_3_bits_1'	: 0b0,
+		'afhob_3_bits_2'	: 0b0,
+		'afhob_3_bits_3'	: 0b0,
+		'afhob_4_bits_0'	: 0b0,
+		'afhob_4_bits_1'	: 0b0,
+		'afhob_4_bits_2'	: 0b0,
+		'afhob_5_bits_0'	: 0b0,
+		'afhob_5_bits_1'	: 0b0,
+		'afhob_5_bits_2'	: 0b0,
+		'afhob_5_bits_3'	: 0b0
+	}
+	update_ftb_entry_dict = {
+		'ftb_entry_valid'	: 1,
+		'tailSlot_valid'	: 1,
+		'tailSlot_tarStat'	: 0b11,
+		'tailSlot_sharing'	: 1,
+		'tailSlot_offset'	: 0b1111,
+		'tailSlot_lower'	: 0x22,
+		'pftAddr'			: 0b1111,
+		'may_be_rvi_call'	: 1,
+		'isRet'				: 1,
+		'isJalr'			: 1,
+		'isCall'			: 1,
+		'carry'				: 1,
+		'always_taken_0'	: 1,
+		'always_taken_1'	: 1,
+		'brSlots_0_valid'	: 1,
+		'brSlots_0_tarStat' : 0b10,
+		'brSlots_0_sharing'	: 1,
+		'brSlots_0_offset'	: 0b0100,
+		'brSlots_0_lower'	: 0x200
+	}
+
+	## update_other_signals
+	update_other_dict = {
+		'cfi_idx_valid'		: 1,
+		'cfi_idx_bits'		: 0b0111,
+		'br_taken_mask_0'	: 1,
+		'br_taken_mask_1'	: 0,
+		'jmp_taken'			: 0,
+		'mispred_mask_0'	: 0,
+		'mispred_mask_1'	: 0,
+		'mispred_mask_2'	: 0,
+		'old_entry'			: 0,
+		'meta'				: 0,
+		'full_target'		: 0
+	}
+
+	update_fold_hist_dict = {
+		'folded_hist_1' 	: 0b1000,
+		'folded_hist_2' 	: 0b1001,
+		'folded_hist_3' 	: 0b1010,
+		'folded_hist_4' 	: 0b1100,
+		'folded_hist_5' 	: 0b0001,
+		'folded_hist_6' 	: 0b0000,
+		'folded_hist_7' 	: 0b0001,
+		'folded_hist_8' 	: 0b0010,
+		'folded_hist_9' 	: 0b0100,
+		'folded_hist_10' 	: 0b1000,
+		'folded_hist_11' 	: 0b1100,
+		'folded_hist_12' 	: 0b1110,
+		'folded_hist_13' 	: 0b1111,
+		'folded_hist_14' 	: 0b0000,
+		'folded_hist_15' 	: 0b1111,
+		'folded_hist_16' 	: 0b1001,
+		'folded_hist_17' 	: 0b1001
+	}
+
+	task_redirect_other_1 	= mlvp.create_task(env.redirect_other_agent.set_redirect_other_value(rediretc_ohter_dict))
+	task_redirect_fold_hist_1 = mlvp.create_task(env.redirect_fold_hist_agent.set_redirect_fold_hist_value(redirect_fold_hist_dict))
+	task_redirect_afhob_1 	= mlvp.create_task(env.redirect_afhob_agent.set_redirect_afhob_value(redirect_afhob_dict))
+
+	await task_redirect_other_1 
+	await task_redirect_fold_hist_1
+	await task_redirect_afhob_1
+
+	await env.redirect_other_agent.bundle.step(10)
+
+	task_update_ftb_entry_1 	= mlvp.create_task(env.update_ftb_entry_agent.set_update_ftb_entry_value(update_pc,update_ftb_entry_dict)) 
+	task_update_other_1 		= mlvp.create_task(env.update_other_agent.set_update_other_value(update_pc,update_other_dict))
+	task_update_foldedHist_1 	= mlvp.create_task(env.update_fold_hist_agent.set_update_fold_hist_value(update_pc,update_fold_hist_dict))
+
+	await task_update_ftb_entry_1
+	await task_update_other_1
+	await task_update_foldedHist_1
+
+#	await env.redirect_afhob_agent.set_redirect_afhob_value()
+
+	enable_dict = {
+		'ubtb_en' 	: 1,	
+		'btb_en'	: 0,
+		'tage_en'	: 0,
+		'sc_en'		: 0,
+		'ras_en'	: 0
+	}
+
+	await env.sub_predi_ctrl_agent.set_sub_predic_ctrl_en(enable_dict)
+	await env.redirect_other_agent.bundle.step(20)	#for the Initial ram
+
+	####Third value
+	rediretc_ohter_dict = {
+		'level'					: 1,
+		'cfiUpdate_pc'			: 0x1480,
+		'cfiUpdate_pd_isRVC'	: 1,
+		'cfiUpdate_pd_isCall'	: 0,
+		'cfiUpdate_pd_isRet'	: 0,
+		'cfiUpdate_ssp'			: 0,
+		'cfiUpdate_sctr'		: 1,
+		'cfiUpdate_TOSW_flag'	: 0,
+		'cfiUpdate_TOSW_value'	: 1,
+		'cfiUpdate_TOSR_flag'	: 0,
+		'cfiUpdate_TOSR_value'	: 0,
+		'cfiUpdate_NOS_flag'	: 1,
+		'cfiUpdate_NOS_value'	: 0,
+
+		'cfiUpdate_lastBrNumOH'	: 1, 
+		'cfiUpdate_histPtr_flag': 1, 
+		'cfiUpdate_histPtr_value':0, 
+		'cfiUpdate_target'		: 1,
+		'cfiUpdate_taken'		: 0,
+		'cfiUpdate_shift'		: 1,
+		'cfiUpdate_addIntoHist'	: 1
+	}
+
+	redirect_fold_hist_dict = {
+		'cfiUpdate_folded_hist_0'	: 0b011,
+		'cfiUpdate_folded_hist_1'	: 0b011,
+		'cfiUpdate_folded_hist_2'	: 0b011,
+		'cfiUpdate_folded_hist_3'	: 0b011,
+		'cfiUpdate_folded_hist_4'	: 0b011,
+		'cfiUpdate_folded_hist_5'	: 0b011,
+		'cfiUpdate_folded_hist_6'	: 0b011,
+		'cfiUpdate_folded_hist_7'	: 0b011,
+		'cfiUpdate_folded_hist_8'	: 0b011,
+		'cfiUpdate_folded_hist_9'	: 0b011,
+
+		'cfiUpdate_folded_hist_10': 0b111,
+		'cfiUpdate_folded_hist_11': 0b111,
+		'cfiUpdate_folded_hist_12': 0b111,
+		'cfiUpdate_folded_hist_13': 0b111,
+		'cfiUpdate_folded_hist_14': 0b111,
+		'cfiUpdate_folded_hist_15': 0b111,
+		'cfiUpdate_folded_hist_16': 0b111,
+		'cfiUpdate_folded_hist_17': 0b111
+	}
+
+	redirect_afhob_dict = {
+		'afhob_0_bits_0'	: 0b1,
+		'afhob_0_bits_1'	: 0b1,
+		'afhob_0_bits_2'	: 0b1,
+		'afhob_0_bits_3'	: 0b1,
+		'afhob_1_bits_0'	: 0b1,
+		'afhob_1_bits_1'	: 0b1,
+		'afhob_1_bits_2'	: 0b1,
+		'afhob_1_bits_3'	: 0b1,
+		'afhob_2_bits_0'	: 0b1,
+		'afhob_2_bits_1'	: 0b1,
+		'afhob_2_bits_2'	: 0b1,
+		'afhob_2_bits_3'	: 0b1,
+		'afhob_3_bits_0'	: 0b1,
+		'afhob_3_bits_1'	: 0b1,
+		'afhob_3_bits_2'	: 0b1,
+		'afhob_3_bits_3'	: 0b1,
+		'afhob_4_bits_0'	: 0b1,
+		'afhob_4_bits_1'	: 0b1,
+		'afhob_4_bits_2'	: 0b1,
+		'afhob_5_bits_0'	: 0b1,
+		'afhob_5_bits_1'	: 0b1,
+		'afhob_5_bits_2'	: 0b1,
+		'afhob_5_bits_3'	: 0b1
+	}
+	update_ftb_entry_dict = {
+		'ftb_entry_valid'	: 1,
+		'tailSlot_valid'	: 1,
+		'tailSlot_tarStat'	: 0b11,
+		'tailSlot_sharing'	: 1,
+		'tailSlot_offset'	: 0b1111,
+		'tailSlot_lower'	: 0x22,
+		'pftAddr'			: 0b1111,
+		'may_be_rvi_call'	: 1,
+		'isRet'				: 1,
+		'isJalr'			: 1,
+		'isCall'			: 1,
+		'carry'				: 1,
+		'always_taken_0'	: 1,
+		'always_taken_1'	: 1,
+		'brSlots_0_valid'	: 1,
+		'brSlots_0_tarStat' : 0b10,
+		'brSlots_0_sharing'	: 1,
+		'brSlots_0_offset'	: 0b0100,
+		'brSlots_0_lower'	: 0x200
+	}
+
+	## update_other_signals
+	update_other_dict = {
+		'cfi_idx_valid'		: 1,
+		'cfi_idx_bits'		: 0b0111,
+		'br_taken_mask_0'	: 1,
+		'br_taken_mask_1'	: 0,
+		'jmp_taken'			: 0,
+		'mispred_mask_0'	: 0,
+		'mispred_mask_1'	: 0,
+		'mispred_mask_2'	: 0,
+		'old_entry'			: 0,
+		'meta'				: 0,
+		'full_target'		: 0
+	}
+
+	update_fold_hist_dict = {
+		'folded_hist_1' 	: 0b1111,
+		'folded_hist_2' 	: 0b1111,
+		'folded_hist_3' 	: 0b1111,
+		'folded_hist_4' 	: 0b1111,
+		'folded_hist_5' 	: 0b1111,
+		'folded_hist_6' 	: 0b1111,
+		'folded_hist_7' 	: 0b1111,
+		'folded_hist_8' 	: 0b1111,
+		'folded_hist_9' 	: 0b1111,
+		'folded_hist_10' 	: 0b1111,
+		'folded_hist_11' 	: 0b1111,
+		'folded_hist_12' 	: 0b1111,
+		'folded_hist_13' 	: 0b1111,
+		'folded_hist_14' 	: 0b1111,
+		'folded_hist_15' 	: 0b1111,
+		'folded_hist_16' 	: 0b1111,
+		'folded_hist_17' 	: 0b1111
+	}
+
+	task_redirect_other_1 	= mlvp.create_task(env.redirect_other_agent.set_redirect_other_value(rediretc_ohter_dict))
+	task_redirect_fold_hist_1 = mlvp.create_task(env.redirect_fold_hist_agent.set_redirect_fold_hist_value(redirect_fold_hist_dict))
+	task_redirect_afhob_1 	= mlvp.create_task(env.redirect_afhob_agent.set_redirect_afhob_value(redirect_afhob_dict))
+
+	await task_redirect_other_1 
+	await task_redirect_fold_hist_1
+	await task_redirect_afhob_1
+
+	await env.redirect_other_agent.bundle.step(10)
+
+	task_update_ftb_entry_1 	= mlvp.create_task(env.update_ftb_entry_agent.set_update_ftb_entry_value(update_pc,update_ftb_entry_dict)) 
+	task_update_other_1 		= mlvp.create_task(env.update_other_agent.set_update_other_value(update_pc,update_other_dict))
+	task_update_foldedHist_1 	= mlvp.create_task(env.update_fold_hist_agent.set_update_fold_hist_value(update_pc,update_fold_hist_dict))
+
+	await task_update_ftb_entry_1
+	await task_update_other_1
+	await task_update_foldedHist_1
+
+
+	await task_clock
+	print("test_normal_sanity IS OVER")
diff --git a/tests/bpu_top/tests/test_mlvp.py b/tests/bpu_top/tests/test_mlvp.py
new file mode 100644
index 0000000..667bdce
--- /dev/null
+++ b/tests/bpu_top/tests/test_mlvp.py
@@ -0,0 +1,148 @@
+"""
+Initialize before the test
+"""
+import os
+ENV_PATH = os.path.dirname(os.path.abspath(__file__))+"/../"
+os.sys.path.append(ENV_PATH)
+from env.config import *
+
+os.sys.path.append(TESTS_PATH)
+os.sys.path.append(DUT_PATH)
+
+import mlvp
+from mlvp import PreRequest
+from UT_Predictor import *
+import random
+
+
+"""
+Testcase
+"""
+
+from env import *
+from env.bpu_bundle import *
+from env.bpu_agent import *
+from env.bpu_env import *
+
+import pytest
+
+#########################################Concrete pytest###################
+
+#	async def test_mlvp_demo(dut: DUTPredictor):
+#		mlvp.start_clock(dut)
+#	
+#		sub_predi_ctrl_bundle = SubPrediCtrlBundle()
+#		sub_predi_ctrl_bundle.bind(dut)
+#		io_spec_info_bundle = Ftq2BpuUpdateSpecInfoBundle()
+#		io_spec_info_bundle.bind(dut)	
+#	
+#		env = BpuEnv(sub_predi_ctrl_bundle,io_spec_info_bundle)
+#	
+#		# reset
+#		await env.sub_predi_ctrl_agent.reset(dut, 2)
+#		# set value
+#		enable_dict = {
+#			'ubtb_en' 	: 1,	
+#			'btb_en'	: 1,
+#			'tage_en'	: 0,
+#			'sc_en'		: 1,
+#			'ras_en'	: 1
+#		}
+#		print("begin exec env test")
+#		await env.sub_predi_ctrl_agent.set_sub_predic_ctrl_en(dut, enable_dict)
+#		print("await 2 clock")
+#		await env.sub_predi_ctrl_agent.bundle.step(2)
+#		enable_dict = {
+#			'ubtb_en' 	: 1,	
+#			'btb_en'	: 1,
+#			'tage_en'	: 1,
+#			'sc_en'		: 1,
+#			'ras_en'	: 0
+#		}
+#		await env.sub_predi_ctrl_agent.set_sub_predic_ctrl_en(dut, enable_dict)
+#	
+#		# the another agent
+#		await env.spec_info_agent.reset(dut, 2)
+
+#	async def test_mlvp_demo(dut: DUTPredictor):
+#		mlvp.start_clock(dut)
+#	
+#		sub_predi_ctrl_bundle = SubPrediCtrlBundle()
+#		sub_predi_ctrl_bundle.bind(dut)
+#		io_spec_info_bundle = Ftq2BpuUpdateSpecInfoBundle()
+#		io_spec_info_bundle.bind(dut)	
+#	
+#		env = BpuEnv(sub_predi_ctrl_bundle,io_spec_info_bundle)
+#	
+#		# reset
+#		await env.sub_predi_ctrl_agent.reset(2)
+#		# set value
+#		enable_dict = {
+#			'ubtb_en' 	: 1,	
+#			'btb_en'	: 1,
+#			'tage_en'	: 0,
+#			'sc_en'		: 1,
+#			'ras_en'	: 1
+#		}
+#		print("begin exec env test")
+#		await env.sub_predi_ctrl_agent.set_sub_predic_ctrl_en(enable_dict)
+
+#	if __name__ == "__main__":
+#		dut = DUTPredictor()
+#		dut.InitClock("clock")
+#	
+#		mlvp.setup_logging(mlvp.INFO)
+#	#	mlvp.run(test_sub_predi_enable_ctrl(mlvp_request))
+#		mlvp.run(test_mlvp_demo(dut))
+#	
+#		dut.Finish()
+
+
+#########################################py test###################
+def bpu_cover_point(dut:DUTPredictor ):
+	g = CovGroup("BPU Addition Function")
+	
+	return g
+
+
+@pytest.fixture()
+def mlvp_request(mlvp_pre_request: PreRequest):
+	mlvp.setup_logging(mlvp.INFO)
+	dut = mlvp_pre_request.create_dut(DUTPredictor,"clock")
+
+	sub_predi_ctrl_bundle = SubPrediCtrlBundle()
+	sub_predi_ctrl_bundle.bind(dut)
+	io_spec_info_bundle = Ftq2BpuUpdateSpecInfoBundle()
+	io_spec_info_bundle.bind(dut)	
+
+	def start_code():
+		mlvp.start_clock(dut)
+		return BpuEnv(sub_predi_ctrl_bundle,io_spec_info_bundle)	
+
+	return start_code
+
+"""
+Way-2: pytest
+"""
+@pytest.mark.mlvp_async
+async def test_request_demo(mlvp_request):
+	print(mlvp_request)
+	env: BpuEnv = mlvp_request()
+
+	# reset
+	await env.sub_predi_ctrl_agent.reset(2)
+	# set value
+	enable_dict = {
+		'ubtb_en' 	: 1,	
+		'btb_en'	: 1,
+		'tage_en'	: 0,
+		'sc_en'		: 1,
+		'ras_en'	: 1
+	}
+	print("begin exec env test")
+	await env.sub_predi_ctrl_agent.set_sub_predic_ctrl_en(enable_dict)
+
+
+if __name__ == "__main__":
+	print("test_request_demo")
+	mlvp.run(test_request_demo(mlvp_request))
diff --git a/tests/bpu_top/tests/test_redirect_signals.py b/tests/bpu_top/tests/test_redirect_signals.py
new file mode 100644
index 0000000..30876f4
--- /dev/null
+++ b/tests/bpu_top/tests/test_redirect_signals.py
@@ -0,0 +1,3119 @@
+"""
+Initialize before the test
+"""
+import os
+ENV_PATH = os.path.dirname(os.path.abspath(__file__))+"/../"
+os.sys.path.append(ENV_PATH)
+from env.config import *
+
+os.sys.path.append(TESTS_PATH)
+os.sys.path.append(DUT_PATH)
+
+import mlvp
+from mlvp import PreRequest
+from UT_Predictor import *
+import random
+
+"""
+Testcase
+"""
+
+from env import *
+from env.bpu_bundle import *
+from env.bpu_agent import *
+from env.bpu_env import *
+
+import pytest
+
+#########################################py test###################
+def bpu_cover_point(dut:DUTPredictor ):
+	g = CovGroup("BPU Addition Function")
+	
+	return g
+
+
+@pytest.fixture()
+def mlvp_request(mlvp_pre_request: PreRequest):
+	mlvp.setup_logging(mlvp.INFO)
+	dut = mlvp_pre_request.create_dut(DUTPredictor,"clock")
+
+	sub_predi_ctrl_bundle 	= SubPrediCtrlBundle()
+	sub_predi_ctrl_bundle.bind(dut)
+	update_ftb_entry_bundle = Ftq2BpuUpdateFtbEntryBundle()
+	update_ftb_entry_bundle.bind(dut)
+	update_other_bundle	= Ftq2BpuUpdateOtherBundle()
+	update_other_bundle.bind(dut)
+	update_fold_hist_bundle 	= Ftq2BpuUpdateFoldHistBundle()
+	update_fold_hist_bundle.bind(dut)	
+	redirect_other_bundle = Ftq2BpuRedirectOtherBundle()
+	redirect_other_bundle.bind(dut)
+	redirect_hist_fold_bundle = Ftq2BpuRedirectFoldHistBundle()
+	redirect_hist_fold_bundle.bind(dut)
+	redirect_afhob_bundle = Ftq2BpuRedirectAfhobBundle()
+	redirect_afhob_bundle.bind(dut)	
+
+	def start_code():
+		mlvp.start_clock(dut)
+		return BpuEnv(sub_predi_ctrl_bundle, update_ftb_entry_bundle, update_other_bundle, 
+					update_fold_hist_bundle, redirect_other_bundle,redirect_hist_fold_bundle, 
+					redirect_afhob_bundle)	
+
+	return start_code
+
+
+"""
+Way: pytest
+"""
+
+"""
+#	below is the pytest
+@pytest.mark.mlvp_async
+async def test_redirect_signals_sanity(mlvp_request):
+	print(mlvp_request)
+	env: BpuEnv = mlvp_request()
+
+	# reset
+	task_clock = mlvp.create_task(env.update_ftb_entry_agent.bundle.step(2200))
+	await env.redirect_other_agent.reset(4)
+	await env.redirect_other_agent.bundle.step(2100)	#for the Initial ram
+	# set value
+	print("begin exec test_redirect_signals_sanity test")
+
+	redirect_other_dict = {
+		'level'					: 1,
+		'cfiUpdate_pc'			: 0x1000,
+		'cfiUpdate_pd_isRVC'	: 1,
+		'cfiUpdate_pd_isCall'	: 1,
+		'cfiUpdate_pd_isRet'	: 1,
+		'cfiUpdate_ssp'			: 1,
+		'cfiUpdate_sctr'		: 1,
+		'cfiUpdate_TOSW_flag'	: 1,
+		'cfiUpdate_TOSW_value'	: 1,
+		'cfiUpdate_TOSR_flag'	: 1,
+		'cfiUpdate_TOSR_value'	: 1,
+		'cfiUpdate_NOS_flag'	: 1,
+		'cfiUpdate_NOS_value'	: 1,
+
+		'cfiUpdate_lastBrNumOH'	: 1, 
+		'cfiUpdate_histPtr_flag': 1, 
+		'cfiUpdate_histPtr_value':1, 
+		'cfiUpdate_target'		: 1,
+		'cfiUpdate_taken'		: 1,
+		'cfiUpdate_shift'		: 1,
+		'cfiUpdate_addIntoHist'	: 1
+	}
+
+	await env.redirect_other_agent.set_redirect_other_value(redirect_other_dict)
+	await task_clock
+
+	print("test_update_signals_sanity IS OVER")
+
+@pytest.mark.mlvp_async
+async def test_normal_sanity(mlvp_request):
+	print(mlvp_request)
+	env: BpuEnv = mlvp_request()
+
+	# reset
+	task_clock = mlvp.create_task(env.update_ftb_entry_agent.bundle.step(2200))
+	await env.redirect_other_agent.reset(4)
+	await env.sub_predi_ctrl_agent.set_sub_predic_ctrl_en()
+	await env.redirect_other_agent.bundle.step(2100)	#for the Initial ram
+	# set value
+	print("begin exec test_redirect_signals_sanity test")
+
+	await task_clock
+	print("test_normal_sanity IS OVER")
+"""
+
+
+@pytest.mark.mlvp_async
+async def test_normal_update_cfi_sanity(mlvp_request):
+	print(mlvp_request)
+	env: BpuEnv = mlvp_request()
+
+	# reset
+	task_clock = mlvp.create_task(env.update_ftb_entry_agent.bundle.step(2200))
+	await env.redirect_other_agent.reset(4)
+	await env.sub_predi_ctrl_agent.set_sub_predic_ctrl_en()
+	await env.redirect_other_agent.bundle.step(2100)	#for the Initial ram
+	# set value
+	print("begin exec test_redirect_signals_sanity test")
+
+	update_pc = 0x1280
+	task_update_ftb_entry = mlvp.create_task(env.update_ftb_entry_agent.set_update_ftb_entry_value(update_pc))
+	task_update_other = mlvp.create_task(env.update_other_agent.set_update_other_value(update_pc))
+	task_update_fold_hist = mlvp.create_task(env.update_fold_hist_agent.set_update_fold_hist_value(update_pc))
+
+	await task_update_ftb_entry 
+	await task_update_other
+	await task_update_fold_hist
+
+	await task_clock
+	print("test_normal_sanity IS OVER")
+
+@pytest.mark.mlvp_async
+async def test_normal_redirect_cfi_sanity(mlvp_request):
+	print(mlvp_request)
+	env: BpuEnv = mlvp_request()
+
+	# reset
+	task_clock = mlvp.create_task(env.update_ftb_entry_agent.bundle.step(2200))
+	await env.redirect_other_agent.reset(4)
+	await env.sub_predi_ctrl_agent.set_sub_predic_ctrl_en()
+	await env.redirect_other_agent.bundle.step(2100)	#for the Initial ram
+	# set value
+	print("begin exec test_redirect_cfi_sanity test")
+
+#	await env.redirect_other_agent.set_redirect_other_value()
+	task_redirect_other 	= mlvp.create_task(env.redirect_other_agent.set_redirect_other_value())
+	task_redirect_fold_hist = mlvp.create_task(env.redirect_fold_hist_agent.set_redirect_fold_hist_value())
+	task_redirect_afhob 	= mlvp.create_task(env.redirect_afhob_agent.set_redirect_afhob_value())
+
+	await task_redirect_other 
+	await task_redirect_fold_hist
+	await task_redirect_afhob
+
+	await env.redirect_other_agent.bundle.step(1)
+
+	task_redirect_other 	= mlvp.create_task(env.redirect_other_agent.set_redirect_other_value())
+	task_redirect_fold_hist = mlvp.create_task(env.redirect_fold_hist_agent.set_redirect_fold_hist_value())
+	task_redirect_afhob 	= mlvp.create_task(env.redirect_afhob_agent.set_redirect_afhob_value())
+
+	await task_redirect_other 
+	await task_redirect_fold_hist
+	await task_redirect_afhob
+
+#	await env.redirect_afhob_agent.set_redirect_afhob_value()
+
+	await task_clock
+	print("test_normal_sanity IS OVER")
+
+
+
+@pytest.mark.mlvp_async
+async def test_normal_redirect_cfi_twice(mlvp_request):
+	print(mlvp_request)
+	env: BpuEnv = mlvp_request()
+	update_pc = 0x1280
+
+	rediretc_ohter_dict = {
+		'level'					: 1,
+		'cfiUpdate_pc'			: 0x1280,
+		'cfiUpdate_pd_isRVC'	: 1,
+		'cfiUpdate_pd_isCall'	: 1,
+		'cfiUpdate_pd_isRet'	: 1,
+		'cfiUpdate_ssp'			: 1,
+		'cfiUpdate_sctr'		: 1,
+		'cfiUpdate_TOSW_flag'	: 1,
+		'cfiUpdate_TOSW_value'	: 1,
+		'cfiUpdate_TOSR_flag'	: 1,
+		'cfiUpdate_TOSR_value'	: 1,
+		'cfiUpdate_NOS_flag'	: 1,
+		'cfiUpdate_NOS_value'	: 1,
+
+		'cfiUpdate_lastBrNumOH'	: 1, 
+		'cfiUpdate_histPtr_flag': 1, 
+		'cfiUpdate_histPtr_value':1, 
+		'cfiUpdate_target'		: 1,
+		'cfiUpdate_taken'		: 1,
+		'cfiUpdate_shift'		: 1,
+		'cfiUpdate_addIntoHist'	: 1
+	}
+
+	redirect_fold_hist_dict = {
+		'cfiUpdate_folded_hist_0'	: 0b100,
+		'cfiUpdate_folded_hist_1'	: 0b100,
+		'cfiUpdate_folded_hist_2'	: 0b100,
+		'cfiUpdate_folded_hist_3'	: 0b100,
+		'cfiUpdate_folded_hist_4'	: 0b100,
+		'cfiUpdate_folded_hist_5'	: 0b100,
+		'cfiUpdate_folded_hist_6'	: 0b100,
+		'cfiUpdate_folded_hist_7'	: 0b100,
+		'cfiUpdate_folded_hist_8'	: 0b100,
+		'cfiUpdate_folded_hist_9'	: 0b100,
+
+		'cfiUpdate_folded_hist_10': 0b100,
+		'cfiUpdate_folded_hist_11': 0b100,
+		'cfiUpdate_folded_hist_12': 0b100,
+		'cfiUpdate_folded_hist_13': 0b100,
+		'cfiUpdate_folded_hist_14': 0b100,
+		'cfiUpdate_folded_hist_15': 0b100,
+		'cfiUpdate_folded_hist_16': 0b100,
+		'cfiUpdate_folded_hist_17': 0b100
+	}
+
+	redirect_afhob_dict = {
+		'afhob_0_bits_0'	: 0b1,
+		'afhob_0_bits_1'	: 0b1,
+		'afhob_0_bits_2'	: 0b1,
+		'afhob_0_bits_3'	: 0b1,
+		'afhob_1_bits_0'	: 0b1,
+		'afhob_1_bits_1'	: 0b1,
+		'afhob_1_bits_2'	: 0b1,
+		'afhob_1_bits_3'	: 0b1,
+		'afhob_2_bits_0'	: 0b1,
+		'afhob_2_bits_1'	: 0b1,
+		'afhob_2_bits_2'	: 0b1,
+		'afhob_2_bits_3'	: 0b1,
+		'afhob_3_bits_0'	: 0b1,
+		'afhob_3_bits_1'	: 0b1,
+		'afhob_3_bits_2'	: 0b1,
+		'afhob_3_bits_3'	: 0b1,
+		'afhob_4_bits_0'	: 0b1,
+		'afhob_4_bits_1'	: 0b1,
+		'afhob_4_bits_2'	: 0b1,
+		'afhob_5_bits_0'	: 0b1,
+		'afhob_5_bits_1'	: 0b1,
+		'afhob_5_bits_2'	: 0b1,
+		'afhob_5_bits_3'	: 0b1
+	}
+
+	# reset
+	task_clock = mlvp.create_task(env.update_ftb_entry_agent.bundle.step(2200))
+	await env.redirect_other_agent.reset(4)
+	await env.redirect_other_agent.bundle.step(2100)	#for the Initial ram
+	# set value
+	print("begin exec test_redirect_cfi_sanity test")
+
+#	await env.redirect_other_agent.set_redirect_other_value()
+	task_redirect_other 	= mlvp.create_task(env.redirect_other_agent.set_redirect_other_value(rediretc_ohter_dict))
+	task_redirect_fold_hist = mlvp.create_task(env.redirect_fold_hist_agent.set_redirect_fold_hist_value(redirect_fold_hist_dict))
+	task_redirect_afhob 	= mlvp.create_task(env.redirect_afhob_agent.set_redirect_afhob_value(redirect_afhob_dict))
+
+	await task_redirect_other 
+	await task_redirect_fold_hist
+	await task_redirect_afhob
+
+	await env.redirect_other_agent.bundle.step(1)
+
+	rediretc_ohter_dict = {
+		'level'					: 1,
+		'cfiUpdate_pc'			: 0x1280,
+		'cfiUpdate_pd_isRVC'	: 1,
+		'cfiUpdate_pd_isCall'	: 1,
+		'cfiUpdate_pd_isRet'	: 0,
+		'cfiUpdate_ssp'			: 1,
+		'cfiUpdate_sctr'		: 0,
+		'cfiUpdate_TOSW_flag'	: 1,
+		'cfiUpdate_TOSW_value'	: 1,
+		'cfiUpdate_TOSR_flag'	: 0,
+		'cfiUpdate_TOSR_value'	: 1,
+		'cfiUpdate_NOS_flag'	: 1,
+		'cfiUpdate_NOS_value'	: 1,
+
+		'cfiUpdate_lastBrNumOH'	: 1, 
+		'cfiUpdate_histPtr_flag': 1, 
+		'cfiUpdate_histPtr_value':0, 
+		'cfiUpdate_target'		: 1,
+		'cfiUpdate_taken'		: 0,
+		'cfiUpdate_shift'		: 1,
+		'cfiUpdate_addIntoHist'	: 1
+	}
+
+	redirect_fold_hist_dict = {
+		'cfiUpdate_folded_hist_0'	: 0b111,
+		'cfiUpdate_folded_hist_1'	: 0b111,
+		'cfiUpdate_folded_hist_2'	: 0b111,
+		'cfiUpdate_folded_hist_3'	: 0b111,
+		'cfiUpdate_folded_hist_4'	: 0b111,
+		'cfiUpdate_folded_hist_5'	: 0b111,
+		'cfiUpdate_folded_hist_6'	: 0b111,
+		'cfiUpdate_folded_hist_7'	: 0b111,
+		'cfiUpdate_folded_hist_8'	: 0b111,
+		'cfiUpdate_folded_hist_9'	: 0b111,
+
+		'cfiUpdate_folded_hist_10': 0b111,
+		'cfiUpdate_folded_hist_11': 0b111,
+		'cfiUpdate_folded_hist_12': 0b111,
+		'cfiUpdate_folded_hist_13': 0b111,
+		'cfiUpdate_folded_hist_14': 0b111,
+		'cfiUpdate_folded_hist_15': 0b111,
+		'cfiUpdate_folded_hist_16': 0b111,
+		'cfiUpdate_folded_hist_17': 0b111
+	}
+
+	redirect_afhob_dict = {
+		'afhob_0_bits_0'	: 0b0,
+		'afhob_0_bits_1'	: 0b0,
+		'afhob_0_bits_2'	: 0b0,
+		'afhob_0_bits_3'	: 0b0,
+		'afhob_1_bits_0'	: 0b0,
+		'afhob_1_bits_1'	: 0b0,
+		'afhob_1_bits_2'	: 0b0,
+		'afhob_1_bits_3'	: 0b0,
+		'afhob_2_bits_0'	: 0b0,
+		'afhob_2_bits_1'	: 0b0,
+		'afhob_2_bits_2'	: 0b0,
+		'afhob_2_bits_3'	: 0b0,
+		'afhob_3_bits_0'	: 0b0,
+		'afhob_3_bits_1'	: 0b0,
+		'afhob_3_bits_2'	: 0b0,
+		'afhob_3_bits_3'	: 0b0,
+		'afhob_4_bits_0'	: 0b0,
+		'afhob_4_bits_1'	: 0b0,
+		'afhob_4_bits_2'	: 0b0,
+		'afhob_5_bits_0'	: 0b0,
+		'afhob_5_bits_1'	: 0b0,
+		'afhob_5_bits_2'	: 0b0,
+		'afhob_5_bits_3'	: 0b0
+	}
+
+	task_redirect_other_1 	= mlvp.create_task(env.redirect_other_agent.set_redirect_other_value(rediretc_ohter_dict))
+	task_redirect_fold_hist_1 = mlvp.create_task(env.redirect_fold_hist_agent.set_redirect_fold_hist_value(redirect_fold_hist_dict))
+	task_redirect_afhob_1 	= mlvp.create_task(env.redirect_afhob_agent.set_redirect_afhob_value(redirect_afhob_dict))
+
+	await task_redirect_other_1 
+	await task_redirect_fold_hist_1
+	await task_redirect_afhob_1
+
+#	await env.redirect_afhob_agent.set_redirect_afhob_value()
+
+	await task_clock
+	print("test_normal_sanity IS OVER")
+
+
+@pytest.mark.mlvp_async
+async def test_normal_redirect_cfi_twice_1(mlvp_request):
+	print(mlvp_request)
+	env: BpuEnv = mlvp_request()
+	update_pc = 0x1280
+
+	# set value
+	enable_dict = {
+		'ubtb_en' 	: 1,	
+		'btb_en'	: 1,
+		'tage_en'	: 1,
+		'sc_en'		: 1,
+		'ras_en'	: 1
+	}
+
+	rediretc_ohter_dict = {
+		'level'					: 1,
+		'cfiUpdate_pc'			: 0x1280,
+		'cfiUpdate_pd_isRVC'	: 1,
+		'cfiUpdate_pd_isCall'	: 1,
+		'cfiUpdate_pd_isRet'	: 1,
+		'cfiUpdate_ssp'			: 1,
+		'cfiUpdate_sctr'		: 1,
+		'cfiUpdate_TOSW_flag'	: 1,
+		'cfiUpdate_TOSW_value'	: 1,
+		'cfiUpdate_TOSR_flag'	: 1,
+		'cfiUpdate_TOSR_value'	: 1,
+		'cfiUpdate_NOS_flag'	: 1,
+		'cfiUpdate_NOS_value'	: 1,
+
+		'cfiUpdate_lastBrNumOH'	: 1, 
+		'cfiUpdate_histPtr_flag': 1, 
+		'cfiUpdate_histPtr_value':1, 
+		'cfiUpdate_target'		: 1,
+		'cfiUpdate_taken'		: 1,
+		'cfiUpdate_shift'		: 1,
+		'cfiUpdate_addIntoHist'	: 1
+	}
+
+	redirect_fold_hist_dict = {
+		'cfiUpdate_folded_hist_0'	: 0b100,
+		'cfiUpdate_folded_hist_1'	: 0b100,
+		'cfiUpdate_folded_hist_2'	: 0b100,
+		'cfiUpdate_folded_hist_3'	: 0b100,
+		'cfiUpdate_folded_hist_4'	: 0b100,
+		'cfiUpdate_folded_hist_5'	: 0b100,
+		'cfiUpdate_folded_hist_6'	: 0b100,
+		'cfiUpdate_folded_hist_7'	: 0b100,
+		'cfiUpdate_folded_hist_8'	: 0b100,
+		'cfiUpdate_folded_hist_9'	: 0b100,
+
+		'cfiUpdate_folded_hist_10': 0b100,
+		'cfiUpdate_folded_hist_11': 0b100,
+		'cfiUpdate_folded_hist_12': 0b100,
+		'cfiUpdate_folded_hist_13': 0b100,
+		'cfiUpdate_folded_hist_14': 0b100,
+		'cfiUpdate_folded_hist_15': 0b100,
+		'cfiUpdate_folded_hist_16': 0b100,
+		'cfiUpdate_folded_hist_17': 0b100
+	}
+
+	redirect_afhob_dict = {
+		'afhob_0_bits_0'	: 0b1,
+		'afhob_0_bits_1'	: 0b1,
+		'afhob_0_bits_2'	: 0b1,
+		'afhob_0_bits_3'	: 0b1,
+		'afhob_1_bits_0'	: 0b1,
+		'afhob_1_bits_1'	: 0b1,
+		'afhob_1_bits_2'	: 0b1,
+		'afhob_1_bits_3'	: 0b1,
+		'afhob_2_bits_0'	: 0b1,
+		'afhob_2_bits_1'	: 0b1,
+		'afhob_2_bits_2'	: 0b1,
+		'afhob_2_bits_3'	: 0b1,
+		'afhob_3_bits_0'	: 0b1,
+		'afhob_3_bits_1'	: 0b1,
+		'afhob_3_bits_2'	: 0b1,
+		'afhob_3_bits_3'	: 0b1,
+		'afhob_4_bits_0'	: 0b1,
+		'afhob_4_bits_1'	: 0b1,
+		'afhob_4_bits_2'	: 0b1,
+		'afhob_5_bits_0'	: 0b1,
+		'afhob_5_bits_1'	: 0b1,
+		'afhob_5_bits_2'	: 0b1,
+		'afhob_5_bits_3'	: 0b1
+	}
+
+	# reset
+	task_clock = mlvp.create_task(env.update_ftb_entry_agent.bundle.step(2200))
+	await env.redirect_other_agent.reset(4)
+	await env.sub_predi_ctrl_agent.set_sub_predic_ctrl_en(enable_dict)
+	await env.redirect_other_agent.bundle.step(2100)	#for the Initial ram
+	# set value
+	print("begin exec test_redirect_cfi_sanity test")
+
+#	await env.redirect_other_agent.set_redirect_other_value()
+	task_redirect_other 	= mlvp.create_task(env.redirect_other_agent.set_redirect_other_value(rediretc_ohter_dict))
+	task_redirect_fold_hist = mlvp.create_task(env.redirect_fold_hist_agent.set_redirect_fold_hist_value(redirect_fold_hist_dict))
+	task_redirect_afhob 	= mlvp.create_task(env.redirect_afhob_agent.set_redirect_afhob_value(redirect_afhob_dict))
+
+	await task_redirect_other 
+	await task_redirect_fold_hist
+	await task_redirect_afhob
+
+	await env.redirect_other_agent.bundle.step(1)
+
+	rediretc_ohter_dict = {
+		'level'					: 1,
+		'cfiUpdate_pc'			: 0x1280,
+		'cfiUpdate_pd_isRVC'	: 1,
+		'cfiUpdate_pd_isCall'	: 1,
+		'cfiUpdate_pd_isRet'	: 0,
+		'cfiUpdate_ssp'			: 1,
+		'cfiUpdate_sctr'		: 0,
+		'cfiUpdate_TOSW_flag'	: 1,
+		'cfiUpdate_TOSW_value'	: 1,
+		'cfiUpdate_TOSR_flag'	: 0,
+		'cfiUpdate_TOSR_value'	: 1,
+		'cfiUpdate_NOS_flag'	: 1,
+		'cfiUpdate_NOS_value'	: 1,
+
+		'cfiUpdate_lastBrNumOH'	: 1, 
+		'cfiUpdate_histPtr_flag': 1, 
+		'cfiUpdate_histPtr_value':0, 
+		'cfiUpdate_target'		: 1,
+		'cfiUpdate_taken'		: 0,
+		'cfiUpdate_shift'		: 1,
+		'cfiUpdate_addIntoHist'	: 1
+	}
+
+	redirect_fold_hist_dict = {
+		'cfiUpdate_folded_hist_0'	: 0b111,
+		'cfiUpdate_folded_hist_1'	: 0b111,
+		'cfiUpdate_folded_hist_2'	: 0b111,
+		'cfiUpdate_folded_hist_3'	: 0b111,
+		'cfiUpdate_folded_hist_4'	: 0b111,
+		'cfiUpdate_folded_hist_5'	: 0b111,
+		'cfiUpdate_folded_hist_6'	: 0b111,
+		'cfiUpdate_folded_hist_7'	: 0b111,
+		'cfiUpdate_folded_hist_8'	: 0b111,
+		'cfiUpdate_folded_hist_9'	: 0b111,
+
+		'cfiUpdate_folded_hist_10': 0b111,
+		'cfiUpdate_folded_hist_11': 0b111,
+		'cfiUpdate_folded_hist_12': 0b111,
+		'cfiUpdate_folded_hist_13': 0b111,
+		'cfiUpdate_folded_hist_14': 0b111,
+		'cfiUpdate_folded_hist_15': 0b111,
+		'cfiUpdate_folded_hist_16': 0b111,
+		'cfiUpdate_folded_hist_17': 0b111
+	}
+
+	redirect_afhob_dict = {
+		'afhob_0_bits_0'	: 0b0,
+		'afhob_0_bits_1'	: 0b0,
+		'afhob_0_bits_2'	: 0b0,
+		'afhob_0_bits_3'	: 0b0,
+		'afhob_1_bits_0'	: 0b0,
+		'afhob_1_bits_1'	: 0b0,
+		'afhob_1_bits_2'	: 0b0,
+		'afhob_1_bits_3'	: 0b0,
+		'afhob_2_bits_0'	: 0b0,
+		'afhob_2_bits_1'	: 0b0,
+		'afhob_2_bits_2'	: 0b0,
+		'afhob_2_bits_3'	: 0b0,
+		'afhob_3_bits_0'	: 0b0,
+		'afhob_3_bits_1'	: 0b0,
+		'afhob_3_bits_2'	: 0b0,
+		'afhob_3_bits_3'	: 0b0,
+		'afhob_4_bits_0'	: 0b0,
+		'afhob_4_bits_1'	: 0b0,
+		'afhob_4_bits_2'	: 0b0,
+		'afhob_5_bits_0'	: 0b0,
+		'afhob_5_bits_1'	: 0b0,
+		'afhob_5_bits_2'	: 0b0,
+		'afhob_5_bits_3'	: 0b0
+	}
+
+	task_redirect_other_1 	= mlvp.create_task(env.redirect_other_agent.set_redirect_other_value(rediretc_ohter_dict))
+	task_redirect_fold_hist_1 = mlvp.create_task(env.redirect_fold_hist_agent.set_redirect_fold_hist_value(redirect_fold_hist_dict))
+	task_redirect_afhob_1 	= mlvp.create_task(env.redirect_afhob_agent.set_redirect_afhob_value(redirect_afhob_dict))
+
+	await task_redirect_other_1 
+	await task_redirect_fold_hist_1
+	await task_redirect_afhob_1
+
+#	await env.redirect_afhob_agent.set_redirect_afhob_value()
+
+	await task_clock
+	print("test_normal_sanity IS OVER")
+
+
+@pytest.mark.mlvp_async
+async def test_normal_redirect_cfi_twice_2(mlvp_request):
+	print(mlvp_request)
+	env: BpuEnv = mlvp_request()
+	update_pc = 0x1280
+
+	# set value
+	enable_dict = {
+		'ubtb_en' 	: 1,	
+		'btb_en'	: 0,
+		'tage_en'	: 1,
+		'sc_en'		: 1,
+		'ras_en'	: 1
+	}
+
+	rediretc_ohter_dict = {
+		'level'					: 1,
+		'cfiUpdate_pc'			: 0x1280,
+		'cfiUpdate_pd_isRVC'	: 1,
+		'cfiUpdate_pd_isCall'	: 1,
+		'cfiUpdate_pd_isRet'	: 1,
+		'cfiUpdate_ssp'			: 1,
+		'cfiUpdate_sctr'		: 1,
+		'cfiUpdate_TOSW_flag'	: 1,
+		'cfiUpdate_TOSW_value'	: 1,
+		'cfiUpdate_TOSR_flag'	: 1,
+		'cfiUpdate_TOSR_value'	: 1,
+		'cfiUpdate_NOS_flag'	: 1,
+		'cfiUpdate_NOS_value'	: 1,
+
+		'cfiUpdate_lastBrNumOH'	: 1, 
+		'cfiUpdate_histPtr_flag': 1, 
+		'cfiUpdate_histPtr_value':1, 
+		'cfiUpdate_target'		: 1,
+		'cfiUpdate_taken'		: 1,
+		'cfiUpdate_shift'		: 1,
+		'cfiUpdate_addIntoHist'	: 1
+	}
+
+	redirect_fold_hist_dict = {
+		'cfiUpdate_folded_hist_0'	: 0b100,
+		'cfiUpdate_folded_hist_1'	: 0b100,
+		'cfiUpdate_folded_hist_2'	: 0b100,
+		'cfiUpdate_folded_hist_3'	: 0b100,
+		'cfiUpdate_folded_hist_4'	: 0b100,
+		'cfiUpdate_folded_hist_5'	: 0b100,
+		'cfiUpdate_folded_hist_6'	: 0b100,
+		'cfiUpdate_folded_hist_7'	: 0b100,
+		'cfiUpdate_folded_hist_8'	: 0b100,
+		'cfiUpdate_folded_hist_9'	: 0b100,
+
+		'cfiUpdate_folded_hist_10': 0b100,
+		'cfiUpdate_folded_hist_11': 0b100,
+		'cfiUpdate_folded_hist_12': 0b100,
+		'cfiUpdate_folded_hist_13': 0b100,
+		'cfiUpdate_folded_hist_14': 0b100,
+		'cfiUpdate_folded_hist_15': 0b100,
+		'cfiUpdate_folded_hist_16': 0b100,
+		'cfiUpdate_folded_hist_17': 0b100
+	}
+
+	redirect_afhob_dict = {
+		'afhob_0_bits_0'	: 0b1,
+		'afhob_0_bits_1'	: 0b1,
+		'afhob_0_bits_2'	: 0b1,
+		'afhob_0_bits_3'	: 0b1,
+		'afhob_1_bits_0'	: 0b1,
+		'afhob_1_bits_1'	: 0b1,
+		'afhob_1_bits_2'	: 0b1,
+		'afhob_1_bits_3'	: 0b1,
+		'afhob_2_bits_0'	: 0b1,
+		'afhob_2_bits_1'	: 0b1,
+		'afhob_2_bits_2'	: 0b1,
+		'afhob_2_bits_3'	: 0b1,
+		'afhob_3_bits_0'	: 0b1,
+		'afhob_3_bits_1'	: 0b1,
+		'afhob_3_bits_2'	: 0b1,
+		'afhob_3_bits_3'	: 0b1,
+		'afhob_4_bits_0'	: 0b1,
+		'afhob_4_bits_1'	: 0b1,
+		'afhob_4_bits_2'	: 0b1,
+		'afhob_5_bits_0'	: 0b1,
+		'afhob_5_bits_1'	: 0b1,
+		'afhob_5_bits_2'	: 0b1,
+		'afhob_5_bits_3'	: 0b1
+	}
+
+	# reset
+	task_clock = mlvp.create_task(env.update_ftb_entry_agent.bundle.step(2200))
+	await env.redirect_other_agent.reset(4)
+	await env.sub_predi_ctrl_agent.set_sub_predic_ctrl_en(enable_dict)
+	await env.redirect_other_agent.bundle.step(2100)	#for the Initial ram
+	# set value
+	print("begin exec test_redirect_cfi_sanity test")
+
+#	await env.redirect_other_agent.set_redirect_other_value()
+	task_redirect_other 	= mlvp.create_task(env.redirect_other_agent.set_redirect_other_value(rediretc_ohter_dict))
+	task_redirect_fold_hist = mlvp.create_task(env.redirect_fold_hist_agent.set_redirect_fold_hist_value(redirect_fold_hist_dict))
+	task_redirect_afhob 	= mlvp.create_task(env.redirect_afhob_agent.set_redirect_afhob_value(redirect_afhob_dict))
+
+	await task_redirect_other 
+	await task_redirect_fold_hist
+	await task_redirect_afhob
+
+	await env.redirect_other_agent.bundle.step(10)
+
+	rediretc_ohter_dict = {
+		'level'					: 1,
+		'cfiUpdate_pc'			: 0x1280,
+		'cfiUpdate_pd_isRVC'	: 1,
+		'cfiUpdate_pd_isCall'	: 1,
+		'cfiUpdate_pd_isRet'	: 0,
+		'cfiUpdate_ssp'			: 1,
+		'cfiUpdate_sctr'		: 0,
+		'cfiUpdate_TOSW_flag'	: 1,
+		'cfiUpdate_TOSW_value'	: 1,
+		'cfiUpdate_TOSR_flag'	: 0,
+		'cfiUpdate_TOSR_value'	: 1,
+		'cfiUpdate_NOS_flag'	: 1,
+		'cfiUpdate_NOS_value'	: 1,
+
+		'cfiUpdate_lastBrNumOH'	: 1, 
+		'cfiUpdate_histPtr_flag': 1, 
+		'cfiUpdate_histPtr_value':0, 
+		'cfiUpdate_target'		: 1,
+		'cfiUpdate_taken'		: 0,
+		'cfiUpdate_shift'		: 1,
+		'cfiUpdate_addIntoHist'	: 1
+	}
+
+	redirect_fold_hist_dict = {
+		'cfiUpdate_folded_hist_0'	: 0b111,
+		'cfiUpdate_folded_hist_1'	: 0b111,
+		'cfiUpdate_folded_hist_2'	: 0b111,
+		'cfiUpdate_folded_hist_3'	: 0b111,
+		'cfiUpdate_folded_hist_4'	: 0b111,
+		'cfiUpdate_folded_hist_5'	: 0b111,
+		'cfiUpdate_folded_hist_6'	: 0b111,
+		'cfiUpdate_folded_hist_7'	: 0b111,
+		'cfiUpdate_folded_hist_8'	: 0b111,
+		'cfiUpdate_folded_hist_9'	: 0b111,
+
+		'cfiUpdate_folded_hist_10': 0b111,
+		'cfiUpdate_folded_hist_11': 0b111,
+		'cfiUpdate_folded_hist_12': 0b111,
+		'cfiUpdate_folded_hist_13': 0b111,
+		'cfiUpdate_folded_hist_14': 0b111,
+		'cfiUpdate_folded_hist_15': 0b111,
+		'cfiUpdate_folded_hist_16': 0b111,
+		'cfiUpdate_folded_hist_17': 0b111
+	}
+
+	redirect_afhob_dict = {
+		'afhob_0_bits_0'	: 0b0,
+		'afhob_0_bits_1'	: 0b0,
+		'afhob_0_bits_2'	: 0b0,
+		'afhob_0_bits_3'	: 0b0,
+		'afhob_1_bits_0'	: 0b0,
+		'afhob_1_bits_1'	: 0b0,
+		'afhob_1_bits_2'	: 0b0,
+		'afhob_1_bits_3'	: 0b0,
+		'afhob_2_bits_0'	: 0b0,
+		'afhob_2_bits_1'	: 0b0,
+		'afhob_2_bits_2'	: 0b0,
+		'afhob_2_bits_3'	: 0b0,
+		'afhob_3_bits_0'	: 0b0,
+		'afhob_3_bits_1'	: 0b0,
+		'afhob_3_bits_2'	: 0b0,
+		'afhob_3_bits_3'	: 0b0,
+		'afhob_4_bits_0'	: 0b0,
+		'afhob_4_bits_1'	: 0b0,
+		'afhob_4_bits_2'	: 0b0,
+		'afhob_5_bits_0'	: 0b0,
+		'afhob_5_bits_1'	: 0b0,
+		'afhob_5_bits_2'	: 0b0,
+		'afhob_5_bits_3'	: 0b0
+	}
+
+	task_redirect_other_1 	= mlvp.create_task(env.redirect_other_agent.set_redirect_other_value(rediretc_ohter_dict))
+	task_redirect_fold_hist_1 = mlvp.create_task(env.redirect_fold_hist_agent.set_redirect_fold_hist_value(redirect_fold_hist_dict))
+	task_redirect_afhob_1 	= mlvp.create_task(env.redirect_afhob_agent.set_redirect_afhob_value(redirect_afhob_dict))
+
+	await task_redirect_other_1 
+	await task_redirect_fold_hist_1
+	await task_redirect_afhob_1
+
+#	await env.redirect_afhob_agent.set_redirect_afhob_value()
+
+	await task_clock
+	print("test_normal_sanity IS OVER")
+
+
+@pytest.mark.mlvp_async
+async def test_normal_redirect_cfi_twice_3(mlvp_request):
+	print(mlvp_request)
+	env: BpuEnv = mlvp_request()
+	update_pc = 0x1280
+
+	# set value
+	enable_dict = {
+		'ubtb_en' 	: 1,	
+		'btb_en'	: 0,
+		'tage_en'	: 1,
+		'sc_en'		: 1,
+		'ras_en'	: 1
+	}
+
+	rediretc_ohter_dict = {
+		'level'					: 1,
+		'cfiUpdate_pc'			: 0x1280,
+		'cfiUpdate_pd_isRVC'	: 1,
+		'cfiUpdate_pd_isCall'	: 1,
+		'cfiUpdate_pd_isRet'	: 1,
+		'cfiUpdate_ssp'			: 1,
+		'cfiUpdate_sctr'		: 1,
+		'cfiUpdate_TOSW_flag'	: 1,
+		'cfiUpdate_TOSW_value'	: 1,
+		'cfiUpdate_TOSR_flag'	: 1,
+		'cfiUpdate_TOSR_value'	: 1,
+		'cfiUpdate_NOS_flag'	: 1,
+		'cfiUpdate_NOS_value'	: 1,
+
+		'cfiUpdate_lastBrNumOH'	: 1, 
+		'cfiUpdate_histPtr_flag': 1, 
+		'cfiUpdate_histPtr_value':1, 
+		'cfiUpdate_target'		: 1,
+		'cfiUpdate_taken'		: 1,
+		'cfiUpdate_shift'		: 1,
+		'cfiUpdate_addIntoHist'	: 1
+	}
+
+	redirect_fold_hist_dict = {
+		'cfiUpdate_folded_hist_0'	: 0b100,
+		'cfiUpdate_folded_hist_1'	: 0b100,
+		'cfiUpdate_folded_hist_2'	: 0b100,
+		'cfiUpdate_folded_hist_3'	: 0b100,
+		'cfiUpdate_folded_hist_4'	: 0b100,
+		'cfiUpdate_folded_hist_5'	: 0b100,
+		'cfiUpdate_folded_hist_6'	: 0b100,
+		'cfiUpdate_folded_hist_7'	: 0b100,
+		'cfiUpdate_folded_hist_8'	: 0b100,
+		'cfiUpdate_folded_hist_9'	: 0b100,
+
+		'cfiUpdate_folded_hist_10': 0b100,
+		'cfiUpdate_folded_hist_11': 0b100,
+		'cfiUpdate_folded_hist_12': 0b100,
+		'cfiUpdate_folded_hist_13': 0b100,
+		'cfiUpdate_folded_hist_14': 0b100,
+		'cfiUpdate_folded_hist_15': 0b100,
+		'cfiUpdate_folded_hist_16': 0b100,
+		'cfiUpdate_folded_hist_17': 0b100
+	}
+
+	redirect_afhob_dict = {
+		'afhob_0_bits_0'	: 0b1,
+		'afhob_0_bits_1'	: 0b1,
+		'afhob_0_bits_2'	: 0b1,
+		'afhob_0_bits_3'	: 0b1,
+		'afhob_1_bits_0'	: 0b1,
+		'afhob_1_bits_1'	: 0b1,
+		'afhob_1_bits_2'	: 0b1,
+		'afhob_1_bits_3'	: 0b1,
+		'afhob_2_bits_0'	: 0b1,
+		'afhob_2_bits_1'	: 0b1,
+		'afhob_2_bits_2'	: 0b1,
+		'afhob_2_bits_3'	: 0b1,
+		'afhob_3_bits_0'	: 0b1,
+		'afhob_3_bits_1'	: 0b1,
+		'afhob_3_bits_2'	: 0b1,
+		'afhob_3_bits_3'	: 0b1,
+		'afhob_4_bits_0'	: 0b1,
+		'afhob_4_bits_1'	: 0b1,
+		'afhob_4_bits_2'	: 0b1,
+		'afhob_5_bits_0'	: 0b1,
+		'afhob_5_bits_1'	: 0b1,
+		'afhob_5_bits_2'	: 0b1,
+		'afhob_5_bits_3'	: 0b1
+	}
+
+	update_ftb_entry_dict = {
+		'ftb_entry_valid'	: 1,
+		'tailSlot_valid'	: 1,
+		'tailSlot_tarStat'	: 0b10,
+		'tailSlot_sharing'	: 1,
+		'tailSlot_offset'	: 0b0100,
+		'tailSlot_lower'	: 0x20,
+		'pftAddr'			: 0b1000,
+		'may_be_rvi_call'	: 1,
+		'isRet'				: 1,
+		'isJalr'			: 1,
+		'isCall'			: 1,
+		'carry'				: 1,
+		'always_taken_0'	: 1,
+		'always_taken_1'	: 1,
+		'brSlots_0_valid'	: 1,
+		'brSlots_0_tarStat' : 0b10,
+		'brSlots_0_sharing'	: 1,
+		'brSlots_0_offset'	: 0b0100,
+		'brSlots_0_lower'	: 0x200
+	}
+	## update_other_signals
+	update_other_dict = {
+		'cfi_idx_valid'		: 1,
+		'cfi_idx_bits'		: 0b1000,
+		'br_taken_mask_0'	: 1,
+		'br_taken_mask_1'	: 1,
+		'jmp_taken'			: 0,
+		'mispred_mask_0'	: 1,
+		'mispred_mask_1'	: 1,
+		'mispred_mask_2'	: 1,
+		'old_entry'			: 1,
+		'meta'				: 1,
+		'full_target'		: 1
+	}
+
+	update_fold_hist_dict = {
+		'folded_hist_1' 	: 0b1000,
+		'folded_hist_2' 	: 0b1001,
+		'folded_hist_3' 	: 0b1010,
+		'folded_hist_4' 	: 0b1100,
+		'folded_hist_5' 	: 0b0001,
+		'folded_hist_6' 	: 0b0000,
+		'folded_hist_7' 	: 0b0001,
+		'folded_hist_8' 	: 0b0010,
+		'folded_hist_9' 	: 0b0100,
+		'folded_hist_10' 	: 0b1000,
+		'folded_hist_11' 	: 0b1100,
+		'folded_hist_12' 	: 0b1110,
+		'folded_hist_13' 	: 0b1111,
+		'folded_hist_14' 	: 0b0000,
+		'folded_hist_15' 	: 0b1111,
+		'folded_hist_16' 	: 0b1001,
+		'folded_hist_17' 	: 0b1001
+	}
+
+
+	# reset
+	task_clock = mlvp.create_task(env.update_ftb_entry_agent.bundle.step(2200))
+	await env.redirect_other_agent.reset(4)
+	await env.sub_predi_ctrl_agent.set_sub_predic_ctrl_en(enable_dict)
+	await env.redirect_other_agent.bundle.step(2100)	#for the Initial ram
+	# set value
+	print("begin exec test_redirect_cfi_sanity test")
+
+#	await env.redirect_other_agent.set_redirect_other_value()
+	task_redirect_other 	= mlvp.create_task(env.redirect_other_agent.set_redirect_other_value(rediretc_ohter_dict))
+	task_redirect_fold_hist = mlvp.create_task(env.redirect_fold_hist_agent.set_redirect_fold_hist_value(redirect_fold_hist_dict))
+	task_redirect_afhob 	= mlvp.create_task(env.redirect_afhob_agent.set_redirect_afhob_value(redirect_afhob_dict))
+
+	await task_redirect_other 
+	await task_redirect_fold_hist
+	await task_redirect_afhob
+
+	await env.redirect_other_agent.bundle.step(10)
+
+
+	task_update_ftb_entry 	= mlvp.create_task(env.update_ftb_entry_agent.set_update_ftb_entry_value(update_pc,update_ftb_entry_dict)) 
+	task_update_other 		= mlvp.create_task(env.update_other_agent.set_update_other_value(update_pc,update_other_dict))
+	task_update_foldedHist 	= mlvp.create_task(env.update_fold_hist_agent.set_update_fold_hist_value(update_pc,update_fold_hist_dict))
+
+	await task_update_ftb_entry
+	await task_update_other
+	await task_update_foldedHist
+
+	####Second value
+	rediretc_ohter_dict = {
+		'level'					: 1,
+		'cfiUpdate_pc'			: 0x1280,
+		'cfiUpdate_pd_isRVC'	: 1,
+		'cfiUpdate_pd_isCall'	: 1,
+		'cfiUpdate_pd_isRet'	: 0,
+		'cfiUpdate_ssp'			: 1,
+		'cfiUpdate_sctr'		: 0,
+		'cfiUpdate_TOSW_flag'	: 1,
+		'cfiUpdate_TOSW_value'	: 1,
+		'cfiUpdate_TOSR_flag'	: 0,
+		'cfiUpdate_TOSR_value'	: 1,
+		'cfiUpdate_NOS_flag'	: 1,
+		'cfiUpdate_NOS_value'	: 1,
+
+		'cfiUpdate_lastBrNumOH'	: 1, 
+		'cfiUpdate_histPtr_flag': 1, 
+		'cfiUpdate_histPtr_value':0, 
+		'cfiUpdate_target'		: 1,
+		'cfiUpdate_taken'		: 0,
+		'cfiUpdate_shift'		: 1,
+		'cfiUpdate_addIntoHist'	: 1
+	}
+
+	redirect_fold_hist_dict = {
+		'cfiUpdate_folded_hist_0'	: 0b111,
+		'cfiUpdate_folded_hist_1'	: 0b111,
+		'cfiUpdate_folded_hist_2'	: 0b111,
+		'cfiUpdate_folded_hist_3'	: 0b111,
+		'cfiUpdate_folded_hist_4'	: 0b111,
+		'cfiUpdate_folded_hist_5'	: 0b111,
+		'cfiUpdate_folded_hist_6'	: 0b111,
+		'cfiUpdate_folded_hist_7'	: 0b111,
+		'cfiUpdate_folded_hist_8'	: 0b111,
+		'cfiUpdate_folded_hist_9'	: 0b111,
+
+		'cfiUpdate_folded_hist_10': 0b111,
+		'cfiUpdate_folded_hist_11': 0b111,
+		'cfiUpdate_folded_hist_12': 0b111,
+		'cfiUpdate_folded_hist_13': 0b111,
+		'cfiUpdate_folded_hist_14': 0b111,
+		'cfiUpdate_folded_hist_15': 0b111,
+		'cfiUpdate_folded_hist_16': 0b111,
+		'cfiUpdate_folded_hist_17': 0b111
+	}
+
+	redirect_afhob_dict = {
+		'afhob_0_bits_0'	: 0b0,
+		'afhob_0_bits_1'	: 0b0,
+		'afhob_0_bits_2'	: 0b0,
+		'afhob_0_bits_3'	: 0b0,
+		'afhob_1_bits_0'	: 0b0,
+		'afhob_1_bits_1'	: 0b0,
+		'afhob_1_bits_2'	: 0b0,
+		'afhob_1_bits_3'	: 0b0,
+		'afhob_2_bits_0'	: 0b0,
+		'afhob_2_bits_1'	: 0b0,
+		'afhob_2_bits_2'	: 0b0,
+		'afhob_2_bits_3'	: 0b0,
+		'afhob_3_bits_0'	: 0b0,
+		'afhob_3_bits_1'	: 0b0,
+		'afhob_3_bits_2'	: 0b0,
+		'afhob_3_bits_3'	: 0b0,
+		'afhob_4_bits_0'	: 0b0,
+		'afhob_4_bits_1'	: 0b0,
+		'afhob_4_bits_2'	: 0b0,
+		'afhob_5_bits_0'	: 0b0,
+		'afhob_5_bits_1'	: 0b0,
+		'afhob_5_bits_2'	: 0b0,
+		'afhob_5_bits_3'	: 0b0
+	}
+
+	task_redirect_other_1 	= mlvp.create_task(env.redirect_other_agent.set_redirect_other_value(rediretc_ohter_dict))
+	task_redirect_fold_hist_1 = mlvp.create_task(env.redirect_fold_hist_agent.set_redirect_fold_hist_value(redirect_fold_hist_dict))
+	task_redirect_afhob_1 	= mlvp.create_task(env.redirect_afhob_agent.set_redirect_afhob_value(redirect_afhob_dict))
+
+	await task_redirect_other_1 
+	await task_redirect_fold_hist_1
+	await task_redirect_afhob_1
+
+#	await env.redirect_afhob_agent.set_redirect_afhob_value()
+
+	await task_clock
+	print("test_normal_sanity IS OVER")
+
+
+@pytest.mark.mlvp_async
+async def test_normal_redirect_cfi_twice_3(mlvp_request):
+	print(mlvp_request)
+	env: BpuEnv = mlvp_request()
+	update_pc = 0x1280
+
+	# set value
+	enable_dict = {
+		'ubtb_en' 	: 1,	
+		'btb_en'	: 1,
+		'tage_en'	: 1,
+		'sc_en'		: 1,
+		'ras_en'	: 1
+	}
+
+	rediretc_ohter_dict = {
+		'level'					: 1,
+		'cfiUpdate_pc'			: 0x1280,
+		'cfiUpdate_pd_isRVC'	: 1,
+		'cfiUpdate_pd_isCall'	: 1,
+		'cfiUpdate_pd_isRet'	: 1,
+		'cfiUpdate_ssp'			: 1,
+		'cfiUpdate_sctr'		: 1,
+		'cfiUpdate_TOSW_flag'	: 1,
+		'cfiUpdate_TOSW_value'	: 1,
+		'cfiUpdate_TOSR_flag'	: 1,
+		'cfiUpdate_TOSR_value'	: 1,
+		'cfiUpdate_NOS_flag'	: 1,
+		'cfiUpdate_NOS_value'	: 1,
+
+		'cfiUpdate_lastBrNumOH'	: 1, 
+		'cfiUpdate_histPtr_flag': 1, 
+		'cfiUpdate_histPtr_value':1, 
+		'cfiUpdate_target'		: 1,
+		'cfiUpdate_taken'		: 1,
+		'cfiUpdate_shift'		: 1,
+		'cfiUpdate_addIntoHist'	: 1
+	}
+
+	redirect_fold_hist_dict = {
+		'cfiUpdate_folded_hist_0'	: 0b100,
+		'cfiUpdate_folded_hist_1'	: 0b100,
+		'cfiUpdate_folded_hist_2'	: 0b100,
+		'cfiUpdate_folded_hist_3'	: 0b100,
+		'cfiUpdate_folded_hist_4'	: 0b100,
+		'cfiUpdate_folded_hist_5'	: 0b100,
+		'cfiUpdate_folded_hist_6'	: 0b100,
+		'cfiUpdate_folded_hist_7'	: 0b100,
+		'cfiUpdate_folded_hist_8'	: 0b100,
+		'cfiUpdate_folded_hist_9'	: 0b100,
+
+		'cfiUpdate_folded_hist_10': 0b100,
+		'cfiUpdate_folded_hist_11': 0b100,
+		'cfiUpdate_folded_hist_12': 0b100,
+		'cfiUpdate_folded_hist_13': 0b100,
+		'cfiUpdate_folded_hist_14': 0b100,
+		'cfiUpdate_folded_hist_15': 0b100,
+		'cfiUpdate_folded_hist_16': 0b100,
+		'cfiUpdate_folded_hist_17': 0b100
+	}
+
+	redirect_afhob_dict = {
+		'afhob_0_bits_0'	: 0b1,
+		'afhob_0_bits_1'	: 0b1,
+		'afhob_0_bits_2'	: 0b1,
+		'afhob_0_bits_3'	: 0b1,
+		'afhob_1_bits_0'	: 0b1,
+		'afhob_1_bits_1'	: 0b1,
+		'afhob_1_bits_2'	: 0b1,
+		'afhob_1_bits_3'	: 0b1,
+		'afhob_2_bits_0'	: 0b1,
+		'afhob_2_bits_1'	: 0b1,
+		'afhob_2_bits_2'	: 0b1,
+		'afhob_2_bits_3'	: 0b1,
+		'afhob_3_bits_0'	: 0b1,
+		'afhob_3_bits_1'	: 0b1,
+		'afhob_3_bits_2'	: 0b1,
+		'afhob_3_bits_3'	: 0b1,
+		'afhob_4_bits_0'	: 0b1,
+		'afhob_4_bits_1'	: 0b1,
+		'afhob_4_bits_2'	: 0b1,
+		'afhob_5_bits_0'	: 0b1,
+		'afhob_5_bits_1'	: 0b1,
+		'afhob_5_bits_2'	: 0b1,
+		'afhob_5_bits_3'	: 0b1
+	}
+
+	update_ftb_entry_dict = {
+		'ftb_entry_valid'	: 1,
+		'tailSlot_valid'	: 1,
+		'tailSlot_tarStat'	: 0b10,
+		'tailSlot_sharing'	: 1,
+		'tailSlot_offset'	: 0b0100,
+		'tailSlot_lower'	: 0x20,
+		'pftAddr'			: 0b1000,
+		'may_be_rvi_call'	: 1,
+		'isRet'				: 1,
+		'isJalr'			: 1,
+		'isCall'			: 1,
+		'carry'				: 1,
+		'always_taken_0'	: 1,
+		'always_taken_1'	: 1,
+		'brSlots_0_valid'	: 1,
+		'brSlots_0_tarStat' : 0b10,
+		'brSlots_0_sharing'	: 1,
+		'brSlots_0_offset'	: 0b0100,
+		'brSlots_0_lower'	: 0x200
+	}
+	## update_other_signals
+	update_other_dict = {
+		'cfi_idx_valid'		: 1,
+		'cfi_idx_bits'		: 0b1000,
+		'br_taken_mask_0'	: 1,
+		'br_taken_mask_1'	: 1,
+		'jmp_taken'			: 0,
+		'mispred_mask_0'	: 1,
+		'mispred_mask_1'	: 1,
+		'mispred_mask_2'	: 1,
+		'old_entry'			: 1,
+		'meta'				: 1,
+		'full_target'		: 1
+	}
+
+	update_fold_hist_dict = {
+		'folded_hist_1' 	: 0b1000,
+		'folded_hist_2' 	: 0b1001,
+		'folded_hist_3' 	: 0b1010,
+		'folded_hist_4' 	: 0b1100,
+		'folded_hist_5' 	: 0b0001,
+		'folded_hist_6' 	: 0b0000,
+		'folded_hist_7' 	: 0b0001,
+		'folded_hist_8' 	: 0b0010,
+		'folded_hist_9' 	: 0b0100,
+		'folded_hist_10' 	: 0b1000,
+		'folded_hist_11' 	: 0b1100,
+		'folded_hist_12' 	: 0b1110,
+		'folded_hist_13' 	: 0b1111,
+		'folded_hist_14' 	: 0b0000,
+		'folded_hist_15' 	: 0b1111,
+		'folded_hist_16' 	: 0b1001,
+		'folded_hist_17' 	: 0b1001
+	}
+
+
+	# reset
+	task_clock = mlvp.create_task(env.update_ftb_entry_agent.bundle.step(2200))
+	await env.redirect_other_agent.reset(4)
+	await env.sub_predi_ctrl_agent.set_sub_predic_ctrl_en(enable_dict)
+	await env.redirect_other_agent.bundle.step(2100)	#for the Initial ram
+	# set value
+	print("begin exec test_redirect_cfi_sanity test")
+
+#	await env.redirect_other_agent.set_redirect_other_value()
+	task_redirect_other 	= mlvp.create_task(env.redirect_other_agent.set_redirect_other_value(rediretc_ohter_dict))
+	task_redirect_fold_hist = mlvp.create_task(env.redirect_fold_hist_agent.set_redirect_fold_hist_value(redirect_fold_hist_dict))
+	task_redirect_afhob 	= mlvp.create_task(env.redirect_afhob_agent.set_redirect_afhob_value(redirect_afhob_dict))
+
+	await task_redirect_other 
+	await task_redirect_fold_hist
+	await task_redirect_afhob
+
+	await env.redirect_other_agent.bundle.step(10)
+
+
+	task_update_ftb_entry 	= mlvp.create_task(env.update_ftb_entry_agent.set_update_ftb_entry_value(update_pc,update_ftb_entry_dict)) 
+	task_update_other 		= mlvp.create_task(env.update_other_agent.set_update_other_value(update_pc,update_other_dict))
+	task_update_foldedHist 	= mlvp.create_task(env.update_fold_hist_agent.set_update_fold_hist_value(update_pc,update_fold_hist_dict))
+
+	await task_update_ftb_entry
+	await task_update_other
+	await task_update_foldedHist
+
+	####Second value
+	rediretc_ohter_dict = {
+		'level'					: 1,
+		'cfiUpdate_pc'			: 0x1280,
+		'cfiUpdate_pd_isRVC'	: 1,
+		'cfiUpdate_pd_isCall'	: 1,
+		'cfiUpdate_pd_isRet'	: 0,
+		'cfiUpdate_ssp'			: 1,
+		'cfiUpdate_sctr'		: 0,
+		'cfiUpdate_TOSW_flag'	: 1,
+		'cfiUpdate_TOSW_value'	: 1,
+		'cfiUpdate_TOSR_flag'	: 0,
+		'cfiUpdate_TOSR_value'	: 1,
+		'cfiUpdate_NOS_flag'	: 1,
+		'cfiUpdate_NOS_value'	: 1,
+
+		'cfiUpdate_lastBrNumOH'	: 1, 
+		'cfiUpdate_histPtr_flag': 1, 
+		'cfiUpdate_histPtr_value':0, 
+		'cfiUpdate_target'		: 1,
+		'cfiUpdate_taken'		: 0,
+		'cfiUpdate_shift'		: 1,
+		'cfiUpdate_addIntoHist'	: 1
+	}
+
+	redirect_fold_hist_dict = {
+		'cfiUpdate_folded_hist_0'	: 0b111,
+		'cfiUpdate_folded_hist_1'	: 0b111,
+		'cfiUpdate_folded_hist_2'	: 0b111,
+		'cfiUpdate_folded_hist_3'	: 0b111,
+		'cfiUpdate_folded_hist_4'	: 0b111,
+		'cfiUpdate_folded_hist_5'	: 0b111,
+		'cfiUpdate_folded_hist_6'	: 0b111,
+		'cfiUpdate_folded_hist_7'	: 0b111,
+		'cfiUpdate_folded_hist_8'	: 0b111,
+		'cfiUpdate_folded_hist_9'	: 0b111,
+
+		'cfiUpdate_folded_hist_10': 0b111,
+		'cfiUpdate_folded_hist_11': 0b111,
+		'cfiUpdate_folded_hist_12': 0b111,
+		'cfiUpdate_folded_hist_13': 0b111,
+		'cfiUpdate_folded_hist_14': 0b111,
+		'cfiUpdate_folded_hist_15': 0b111,
+		'cfiUpdate_folded_hist_16': 0b111,
+		'cfiUpdate_folded_hist_17': 0b111
+	}
+
+	redirect_afhob_dict = {
+		'afhob_0_bits_0'	: 0b0,
+		'afhob_0_bits_1'	: 0b0,
+		'afhob_0_bits_2'	: 0b0,
+		'afhob_0_bits_3'	: 0b0,
+		'afhob_1_bits_0'	: 0b0,
+		'afhob_1_bits_1'	: 0b0,
+		'afhob_1_bits_2'	: 0b0,
+		'afhob_1_bits_3'	: 0b0,
+		'afhob_2_bits_0'	: 0b0,
+		'afhob_2_bits_1'	: 0b0,
+		'afhob_2_bits_2'	: 0b0,
+		'afhob_2_bits_3'	: 0b0,
+		'afhob_3_bits_0'	: 0b0,
+		'afhob_3_bits_1'	: 0b0,
+		'afhob_3_bits_2'	: 0b0,
+		'afhob_3_bits_3'	: 0b0,
+		'afhob_4_bits_0'	: 0b0,
+		'afhob_4_bits_1'	: 0b0,
+		'afhob_4_bits_2'	: 0b0,
+		'afhob_5_bits_0'	: 0b0,
+		'afhob_5_bits_1'	: 0b0,
+		'afhob_5_bits_2'	: 0b0,
+		'afhob_5_bits_3'	: 0b0
+	}
+	update_ftb_entry_dict = {
+		'ftb_entry_valid'	: 1,
+		'tailSlot_valid'	: 1,
+		'tailSlot_tarStat'	: 0b11,
+		'tailSlot_sharing'	: 1,
+		'tailSlot_offset'	: 0b1111,
+		'tailSlot_lower'	: 0x22,
+		'pftAddr'			: 0b1111,
+		'may_be_rvi_call'	: 1,
+		'isRet'				: 1,
+		'isJalr'			: 1,
+		'isCall'			: 1,
+		'carry'				: 1,
+		'always_taken_0'	: 1,
+		'always_taken_1'	: 1,
+		'brSlots_0_valid'	: 1,
+		'brSlots_0_tarStat' : 0b10,
+		'brSlots_0_sharing'	: 1,
+		'brSlots_0_offset'	: 0b0100,
+		'brSlots_0_lower'	: 0x200
+	}
+
+	## update_other_signals
+	update_other_dict = {
+		'cfi_idx_valid'		: 1,
+		'cfi_idx_bits'		: 0b0111,
+		'br_taken_mask_0'	: 1,
+		'br_taken_mask_1'	: 0,
+		'jmp_taken'			: 1,
+		'mispred_mask_0'	: 1,
+		'mispred_mask_1'	: 1,
+		'mispred_mask_2'	: 1,
+		'old_entry'			: 1,
+		'meta'				: 1,
+		'full_target'		: 1
+	}
+
+	update_fold_hist_dict = {
+		'folded_hist_1' 	: 0b1000,
+		'folded_hist_2' 	: 0b1001,
+		'folded_hist_3' 	: 0b1010,
+		'folded_hist_4' 	: 0b1100,
+		'folded_hist_5' 	: 0b0001,
+		'folded_hist_6' 	: 0b0000,
+		'folded_hist_7' 	: 0b0001,
+		'folded_hist_8' 	: 0b0010,
+		'folded_hist_9' 	: 0b0100,
+		'folded_hist_10' 	: 0b1000,
+		'folded_hist_11' 	: 0b1100,
+		'folded_hist_12' 	: 0b1110,
+		'folded_hist_13' 	: 0b1111,
+		'folded_hist_14' 	: 0b0000,
+		'folded_hist_15' 	: 0b1111,
+		'folded_hist_16' 	: 0b1001,
+		'folded_hist_17' 	: 0b1001
+	}
+
+
+	task_redirect_other_1 	= mlvp.create_task(env.redirect_other_agent.set_redirect_other_value(rediretc_ohter_dict))
+	task_redirect_fold_hist_1 = mlvp.create_task(env.redirect_fold_hist_agent.set_redirect_fold_hist_value(redirect_fold_hist_dict))
+	task_redirect_afhob_1 	= mlvp.create_task(env.redirect_afhob_agent.set_redirect_afhob_value(redirect_afhob_dict))
+
+	await task_redirect_other_1 
+	await task_redirect_fold_hist_1
+	await task_redirect_afhob_1
+
+	await env.redirect_other_agent.bundle.step(10)
+
+	task_update_ftb_entry_1 	= mlvp.create_task(env.update_ftb_entry_agent.set_update_ftb_entry_value(update_pc,update_ftb_entry_dict)) 
+	task_update_other_1 		= mlvp.create_task(env.update_other_agent.set_update_other_value(update_pc,update_other_dict))
+	task_update_foldedHist_1 	= mlvp.create_task(env.update_fold_hist_agent.set_update_fold_hist_value(update_pc,update_fold_hist_dict))
+
+	await task_update_ftb_entry_1
+	await task_update_other_1
+	await task_update_foldedHist_1
+
+#	await env.redirect_afhob_agent.set_redirect_afhob_value()
+
+	await task_clock
+	print("test_normal_sanity IS OVER")
+
+@pytest.mark.mlvp_async
+async def test_normal_redirect_cfi_twice_4(mlvp_request):
+	print(mlvp_request)
+	env: BpuEnv = mlvp_request()
+	update_pc = 0x1280
+
+	# set value
+	enable_dict = {
+		'ubtb_en' 	: 1,	
+		'btb_en'	: 1,
+		'tage_en'	: 1,
+		'sc_en'		: 1,
+		'ras_en'	: 1
+	}
+
+	rediretc_ohter_dict = {
+		'level'					: 1,
+		'cfiUpdate_pc'			: 0x2280,
+		'cfiUpdate_pd_isRVC'	: 1,
+		'cfiUpdate_pd_isCall'	: 1,
+		'cfiUpdate_pd_isRet'	: 1,
+		'cfiUpdate_ssp'			: 1,
+		'cfiUpdate_sctr'		: 1,
+		'cfiUpdate_TOSW_flag'	: 1,
+		'cfiUpdate_TOSW_value'	: 1,
+		'cfiUpdate_TOSR_flag'	: 1,
+		'cfiUpdate_TOSR_value'	: 1,
+		'cfiUpdate_NOS_flag'	: 1,
+		'cfiUpdate_NOS_value'	: 1,
+
+		'cfiUpdate_lastBrNumOH'	: 1, 
+		'cfiUpdate_histPtr_flag': 1, 
+		'cfiUpdate_histPtr_value':1, 
+		'cfiUpdate_target'		: 1,
+		'cfiUpdate_taken'		: 1,
+		'cfiUpdate_shift'		: 1,
+		'cfiUpdate_addIntoHist'	: 1
+	}
+
+	redirect_fold_hist_dict = {
+		'cfiUpdate_folded_hist_0'	: 0b100,
+		'cfiUpdate_folded_hist_1'	: 0b100,
+		'cfiUpdate_folded_hist_2'	: 0b100,
+		'cfiUpdate_folded_hist_3'	: 0b100,
+		'cfiUpdate_folded_hist_4'	: 0b100,
+		'cfiUpdate_folded_hist_5'	: 0b100,
+		'cfiUpdate_folded_hist_6'	: 0b100,
+		'cfiUpdate_folded_hist_7'	: 0b100,
+		'cfiUpdate_folded_hist_8'	: 0b100,
+		'cfiUpdate_folded_hist_9'	: 0b100,
+
+		'cfiUpdate_folded_hist_10': 0b100,
+		'cfiUpdate_folded_hist_11': 0b100,
+		'cfiUpdate_folded_hist_12': 0b100,
+		'cfiUpdate_folded_hist_13': 0b100,
+		'cfiUpdate_folded_hist_14': 0b100,
+		'cfiUpdate_folded_hist_15': 0b100,
+		'cfiUpdate_folded_hist_16': 0b100,
+		'cfiUpdate_folded_hist_17': 0b100
+	}
+
+	redirect_afhob_dict = {
+		'afhob_0_bits_0'	: 0b1,
+		'afhob_0_bits_1'	: 0b1,
+		'afhob_0_bits_2'	: 0b1,
+		'afhob_0_bits_3'	: 0b1,
+		'afhob_1_bits_0'	: 0b1,
+		'afhob_1_bits_1'	: 0b1,
+		'afhob_1_bits_2'	: 0b1,
+		'afhob_1_bits_3'	: 0b1,
+		'afhob_2_bits_0'	: 0b1,
+		'afhob_2_bits_1'	: 0b1,
+		'afhob_2_bits_2'	: 0b1,
+		'afhob_2_bits_3'	: 0b1,
+		'afhob_3_bits_0'	: 0b1,
+		'afhob_3_bits_1'	: 0b1,
+		'afhob_3_bits_2'	: 0b1,
+		'afhob_3_bits_3'	: 0b1,
+		'afhob_4_bits_0'	: 0b1,
+		'afhob_4_bits_1'	: 0b1,
+		'afhob_4_bits_2'	: 0b1,
+		'afhob_5_bits_0'	: 0b1,
+		'afhob_5_bits_1'	: 0b1,
+		'afhob_5_bits_2'	: 0b1,
+		'afhob_5_bits_3'	: 0b1
+	}
+
+	update_ftb_entry_dict = {
+		'ftb_entry_valid'	: 1,
+		'tailSlot_valid'	: 1,
+		'tailSlot_tarStat'	: 0b10,
+		'tailSlot_sharing'	: 1,
+		'tailSlot_offset'	: 0b0100,
+		'tailSlot_lower'	: 0x20,
+		'pftAddr'			: 0b1000,
+		'may_be_rvi_call'	: 1,
+		'isRet'				: 1,
+		'isJalr'			: 1,
+		'isCall'			: 1,
+		'carry'				: 1,
+		'always_taken_0'	: 1,
+		'always_taken_1'	: 1,
+		'brSlots_0_valid'	: 1,
+		'brSlots_0_tarStat' : 0b10,
+		'brSlots_0_sharing'	: 1,
+		'brSlots_0_offset'	: 0b0100,
+		'brSlots_0_lower'	: 0x200
+	}
+	## update_other_signals
+	update_other_dict = {
+		'cfi_idx_valid'		: 1,
+		'cfi_idx_bits'		: 0b1000,
+		'br_taken_mask_0'	: 1,
+		'br_taken_mask_1'	: 1,
+		'jmp_taken'			: 0,
+		'mispred_mask_0'	: 1,
+		'mispred_mask_1'	: 1,
+		'mispred_mask_2'	: 1,
+		'old_entry'			: 1,
+		'meta'				: 1,
+		'full_target'		: 1
+	}
+
+	update_fold_hist_dict = {
+		'folded_hist_1' 	: 0b1000,
+		'folded_hist_2' 	: 0b1001,
+		'folded_hist_3' 	: 0b1010,
+		'folded_hist_4' 	: 0b1100,
+		'folded_hist_5' 	: 0b0001,
+		'folded_hist_6' 	: 0b0000,
+		'folded_hist_7' 	: 0b0001,
+		'folded_hist_8' 	: 0b0010,
+		'folded_hist_9' 	: 0b0100,
+		'folded_hist_10' 	: 0b1000,
+		'folded_hist_11' 	: 0b1100,
+		'folded_hist_12' 	: 0b1110,
+		'folded_hist_13' 	: 0b1111,
+		'folded_hist_14' 	: 0b0000,
+		'folded_hist_15' 	: 0b1111,
+		'folded_hist_16' 	: 0b1001,
+		'folded_hist_17' 	: 0b1001
+	}
+
+
+	# reset
+	task_clock = mlvp.create_task(env.update_ftb_entry_agent.bundle.step(2200))
+	await env.redirect_other_agent.reset(4)
+	await env.sub_predi_ctrl_agent.set_sub_predic_ctrl_en(enable_dict)
+	await env.redirect_other_agent.bundle.step(2100)	#for the Initial ram
+	# set value
+	print("begin exec test_redirect_cfi_sanity test")
+
+#	await env.redirect_other_agent.set_redirect_other_value()
+	task_redirect_other 	= mlvp.create_task(env.redirect_other_agent.set_redirect_other_value(rediretc_ohter_dict))
+	task_redirect_fold_hist = mlvp.create_task(env.redirect_fold_hist_agent.set_redirect_fold_hist_value(redirect_fold_hist_dict))
+	task_redirect_afhob 	= mlvp.create_task(env.redirect_afhob_agent.set_redirect_afhob_value(redirect_afhob_dict))
+
+	await task_redirect_other 
+	await task_redirect_fold_hist
+	await task_redirect_afhob
+
+	await env.redirect_other_agent.bundle.step(10)
+
+
+	task_update_ftb_entry 	= mlvp.create_task(env.update_ftb_entry_agent.set_update_ftb_entry_value(update_pc,update_ftb_entry_dict)) 
+	task_update_other 		= mlvp.create_task(env.update_other_agent.set_update_other_value(update_pc,update_other_dict))
+	task_update_foldedHist 	= mlvp.create_task(env.update_fold_hist_agent.set_update_fold_hist_value(update_pc,update_fold_hist_dict))
+
+	await task_update_ftb_entry
+	await task_update_other
+	await task_update_foldedHist
+
+	####Second value
+	rediretc_ohter_dict = {
+		'level'					: 1,
+		'cfiUpdate_pc'			: 0x1480,
+		'cfiUpdate_pd_isRVC'	: 0,
+		'cfiUpdate_pd_isCall'	: 0,
+		'cfiUpdate_pd_isRet'	: 0,
+		'cfiUpdate_ssp'			: 0,
+		'cfiUpdate_sctr'		: 0,
+		'cfiUpdate_TOSW_flag'	: 0,
+		'cfiUpdate_TOSW_value'	: 0,
+		'cfiUpdate_TOSR_flag'	: 0,
+		'cfiUpdate_TOSR_value'	: 0,
+		'cfiUpdate_NOS_flag'	: 0,
+		'cfiUpdate_NOS_value'	: 0,
+
+		'cfiUpdate_lastBrNumOH'	: 1, 
+		'cfiUpdate_histPtr_flag': 1, 
+		'cfiUpdate_histPtr_value':0, 
+		'cfiUpdate_target'		: 0,
+		'cfiUpdate_taken'		: 0,
+		'cfiUpdate_shift'		: 1,
+		'cfiUpdate_addIntoHist'	: 1
+	}
+
+	redirect_fold_hist_dict = {
+		'cfiUpdate_folded_hist_0'	: 0b011,
+		'cfiUpdate_folded_hist_1'	: 0b011,
+		'cfiUpdate_folded_hist_2'	: 0b011,
+		'cfiUpdate_folded_hist_3'	: 0b011,
+		'cfiUpdate_folded_hist_4'	: 0b011,
+		'cfiUpdate_folded_hist_5'	: 0b011,
+		'cfiUpdate_folded_hist_6'	: 0b011,
+		'cfiUpdate_folded_hist_7'	: 0b011,
+		'cfiUpdate_folded_hist_8'	: 0b011,
+		'cfiUpdate_folded_hist_9'	: 0b011,
+
+		'cfiUpdate_folded_hist_10': 0b111,
+		'cfiUpdate_folded_hist_11': 0b111,
+		'cfiUpdate_folded_hist_12': 0b111,
+		'cfiUpdate_folded_hist_13': 0b111,
+		'cfiUpdate_folded_hist_14': 0b111,
+		'cfiUpdate_folded_hist_15': 0b111,
+		'cfiUpdate_folded_hist_16': 0b111,
+		'cfiUpdate_folded_hist_17': 0b111
+	}
+
+	redirect_afhob_dict = {
+		'afhob_0_bits_0'	: 0b0,
+		'afhob_0_bits_1'	: 0b0,
+		'afhob_0_bits_2'	: 0b0,
+		'afhob_0_bits_3'	: 0b0,
+		'afhob_1_bits_0'	: 0b0,
+		'afhob_1_bits_1'	: 0b0,
+		'afhob_1_bits_2'	: 0b0,
+		'afhob_1_bits_3'	: 0b0,
+		'afhob_2_bits_0'	: 0b0,
+		'afhob_2_bits_1'	: 0b0,
+		'afhob_2_bits_2'	: 0b0,
+		'afhob_2_bits_3'	: 0b0,
+		'afhob_3_bits_0'	: 0b0,
+		'afhob_3_bits_1'	: 0b0,
+		'afhob_3_bits_2'	: 0b0,
+		'afhob_3_bits_3'	: 0b0,
+		'afhob_4_bits_0'	: 0b0,
+		'afhob_4_bits_1'	: 0b0,
+		'afhob_4_bits_2'	: 0b0,
+		'afhob_5_bits_0'	: 0b0,
+		'afhob_5_bits_1'	: 0b0,
+		'afhob_5_bits_2'	: 0b0,
+		'afhob_5_bits_3'	: 0b0
+	}
+	update_ftb_entry_dict = {
+		'ftb_entry_valid'	: 1,
+		'tailSlot_valid'	: 1,
+		'tailSlot_tarStat'	: 0b11,
+		'tailSlot_sharing'	: 1,
+		'tailSlot_offset'	: 0b1111,
+		'tailSlot_lower'	: 0x22,
+		'pftAddr'			: 0b1111,
+		'may_be_rvi_call'	: 1,
+		'isRet'				: 1,
+		'isJalr'			: 1,
+		'isCall'			: 1,
+		'carry'				: 1,
+		'always_taken_0'	: 1,
+		'always_taken_1'	: 1,
+		'brSlots_0_valid'	: 1,
+		'brSlots_0_tarStat' : 0b10,
+		'brSlots_0_sharing'	: 1,
+		'brSlots_0_offset'	: 0b0100,
+		'brSlots_0_lower'	: 0x200
+	}
+
+	## update_other_signals
+	update_other_dict = {
+		'cfi_idx_valid'		: 1,
+		'cfi_idx_bits'		: 0b0111,
+		'br_taken_mask_0'	: 1,
+		'br_taken_mask_1'	: 0,
+		'jmp_taken'			: 0,
+		'mispred_mask_0'	: 0,
+		'mispred_mask_1'	: 0,
+		'mispred_mask_2'	: 0,
+		'old_entry'			: 0,
+		'meta'				: 0,
+		'full_target'		: 0
+	}
+
+	update_fold_hist_dict = {
+		'folded_hist_1' 	: 0b1000,
+		'folded_hist_2' 	: 0b1001,
+		'folded_hist_3' 	: 0b1010,
+		'folded_hist_4' 	: 0b1100,
+		'folded_hist_5' 	: 0b0001,
+		'folded_hist_6' 	: 0b0000,
+		'folded_hist_7' 	: 0b0001,
+		'folded_hist_8' 	: 0b0010,
+		'folded_hist_9' 	: 0b0100,
+		'folded_hist_10' 	: 0b1000,
+		'folded_hist_11' 	: 0b1100,
+		'folded_hist_12' 	: 0b1110,
+		'folded_hist_13' 	: 0b1111,
+		'folded_hist_14' 	: 0b0000,
+		'folded_hist_15' 	: 0b1111,
+		'folded_hist_16' 	: 0b1001,
+		'folded_hist_17' 	: 0b1001
+	}
+
+	task_redirect_other_1 	= mlvp.create_task(env.redirect_other_agent.set_redirect_other_value(rediretc_ohter_dict))
+	task_redirect_fold_hist_1 = mlvp.create_task(env.redirect_fold_hist_agent.set_redirect_fold_hist_value(redirect_fold_hist_dict))
+	task_redirect_afhob_1 	= mlvp.create_task(env.redirect_afhob_agent.set_redirect_afhob_value(redirect_afhob_dict))
+
+	await task_redirect_other_1 
+	await task_redirect_fold_hist_1
+	await task_redirect_afhob_1
+
+	await env.redirect_other_agent.bundle.step(10)
+
+	task_update_ftb_entry_1 	= mlvp.create_task(env.update_ftb_entry_agent.set_update_ftb_entry_value(update_pc,update_ftb_entry_dict)) 
+	task_update_other_1 		= mlvp.create_task(env.update_other_agent.set_update_other_value(update_pc,update_other_dict))
+	task_update_foldedHist_1 	= mlvp.create_task(env.update_fold_hist_agent.set_update_fold_hist_value(update_pc,update_fold_hist_dict))
+
+	await task_update_ftb_entry_1
+	await task_update_other_1
+	await task_update_foldedHist_1
+
+#	await env.redirect_afhob_agent.set_redirect_afhob_value()
+
+	await task_clock
+	print("test_normal_sanity IS OVER")
+
+
+@pytest.mark.mlvp_async
+async def test_normal_redirect_cfi_twice_5(mlvp_request):
+	print(mlvp_request)
+	env: BpuEnv = mlvp_request()
+	update_pc = 0x2480
+
+	# set value
+	enable_dict = {
+		'ubtb_en' 	: 1,	
+		'btb_en'	: 1,
+		'tage_en'	: 1,
+		'sc_en'		: 1,
+		'ras_en'	: 1
+	}
+
+	rediretc_ohter_dict = {
+		'level'					: 1,
+		'cfiUpdate_pc'			: 0x2280,
+		'cfiUpdate_pd_isRVC'	: 1,
+		'cfiUpdate_pd_isCall'	: 1,
+		'cfiUpdate_pd_isRet'	: 1,
+		'cfiUpdate_ssp'			: 1,
+		'cfiUpdate_sctr'		: 1,
+		'cfiUpdate_TOSW_flag'	: 1,
+		'cfiUpdate_TOSW_value'	: 1,
+		'cfiUpdate_TOSR_flag'	: 1,
+		'cfiUpdate_TOSR_value'	: 1,
+		'cfiUpdate_NOS_flag'	: 1,
+		'cfiUpdate_NOS_value'	: 1,
+
+		'cfiUpdate_lastBrNumOH'	: 1, 
+		'cfiUpdate_histPtr_flag': 1, 
+		'cfiUpdate_histPtr_value':1, 
+		'cfiUpdate_target'		: 1,
+		'cfiUpdate_taken'		: 1,
+		'cfiUpdate_shift'		: 1,
+		'cfiUpdate_addIntoHist'	: 1
+	}
+
+	redirect_fold_hist_dict = {
+		'cfiUpdate_folded_hist_0'	: 0b100,
+		'cfiUpdate_folded_hist_1'	: 0b100,
+		'cfiUpdate_folded_hist_2'	: 0b100,
+		'cfiUpdate_folded_hist_3'	: 0b100,
+		'cfiUpdate_folded_hist_4'	: 0b100,
+		'cfiUpdate_folded_hist_5'	: 0b100,
+		'cfiUpdate_folded_hist_6'	: 0b100,
+		'cfiUpdate_folded_hist_7'	: 0b100,
+		'cfiUpdate_folded_hist_8'	: 0b100,
+		'cfiUpdate_folded_hist_9'	: 0b100,
+
+		'cfiUpdate_folded_hist_10': 0b100,
+		'cfiUpdate_folded_hist_11': 0b100,
+		'cfiUpdate_folded_hist_12': 0b100,
+		'cfiUpdate_folded_hist_13': 0b100,
+		'cfiUpdate_folded_hist_14': 0b100,
+		'cfiUpdate_folded_hist_15': 0b100,
+		'cfiUpdate_folded_hist_16': 0b100,
+		'cfiUpdate_folded_hist_17': 0b100
+	}
+
+	redirect_afhob_dict = {
+		'afhob_0_bits_0'	: 0b1,
+		'afhob_0_bits_1'	: 0b1,
+		'afhob_0_bits_2'	: 0b1,
+		'afhob_0_bits_3'	: 0b1,
+		'afhob_1_bits_0'	: 0b1,
+		'afhob_1_bits_1'	: 0b1,
+		'afhob_1_bits_2'	: 0b1,
+		'afhob_1_bits_3'	: 0b1,
+		'afhob_2_bits_0'	: 0b1,
+		'afhob_2_bits_1'	: 0b1,
+		'afhob_2_bits_2'	: 0b1,
+		'afhob_2_bits_3'	: 0b1,
+		'afhob_3_bits_0'	: 0b1,
+		'afhob_3_bits_1'	: 0b1,
+		'afhob_3_bits_2'	: 0b1,
+		'afhob_3_bits_3'	: 0b1,
+		'afhob_4_bits_0'	: 0b1,
+		'afhob_4_bits_1'	: 0b1,
+		'afhob_4_bits_2'	: 0b1,
+		'afhob_5_bits_0'	: 0b1,
+		'afhob_5_bits_1'	: 0b1,
+		'afhob_5_bits_2'	: 0b1,
+		'afhob_5_bits_3'	: 0b1
+	}
+
+	update_ftb_entry_dict = {
+		'ftb_entry_valid'	: 1,
+		'tailSlot_valid'	: 1,
+		'tailSlot_tarStat'	: 0b10,
+		'tailSlot_sharing'	: 1,
+		'tailSlot_offset'	: 0b0100,
+		'tailSlot_lower'	: 0x20,
+		'pftAddr'			: 0b1000,
+		'may_be_rvi_call'	: 1,
+		'isRet'				: 1,
+		'isJalr'			: 1,
+		'isCall'			: 1,
+		'carry'				: 1,
+		'always_taken_0'	: 1,
+		'always_taken_1'	: 1,
+		'brSlots_0_valid'	: 1,
+		'brSlots_0_tarStat' : 0b10,
+		'brSlots_0_sharing'	: 1,
+		'brSlots_0_offset'	: 0b0100,
+		'brSlots_0_lower'	: 0x200
+	}
+	## update_other_signals
+	update_other_dict = {
+		'cfi_idx_valid'		: 1,
+		'cfi_idx_bits'		: 0b1000,
+		'br_taken_mask_0'	: 1,
+		'br_taken_mask_1'	: 1,
+		'jmp_taken'			: 0,
+		'mispred_mask_0'	: 1,
+		'mispred_mask_1'	: 1,
+		'mispred_mask_2'	: 1,
+		'old_entry'			: 1,
+		'meta'				: 1,
+		'full_target'		: 1
+	}
+
+	update_fold_hist_dict = {
+		'folded_hist_1' 	: 0b1000,
+		'folded_hist_2' 	: 0b1001,
+		'folded_hist_3' 	: 0b1010,
+		'folded_hist_4' 	: 0b1100,
+		'folded_hist_5' 	: 0b0001,
+		'folded_hist_6' 	: 0b0000,
+		'folded_hist_7' 	: 0b0001,
+		'folded_hist_8' 	: 0b0010,
+		'folded_hist_9' 	: 0b0100,
+		'folded_hist_10' 	: 0b1000,
+		'folded_hist_11' 	: 0b1100,
+		'folded_hist_12' 	: 0b1110,
+		'folded_hist_13' 	: 0b1111,
+		'folded_hist_14' 	: 0b0000,
+		'folded_hist_15' 	: 0b1111,
+		'folded_hist_16' 	: 0b1001,
+		'folded_hist_17' 	: 0b1001
+	}
+
+
+	# reset
+	task_clock = mlvp.create_task(env.update_ftb_entry_agent.bundle.step(2200))
+	await env.redirect_other_agent.reset(4)
+	await env.sub_predi_ctrl_agent.set_sub_predic_ctrl_en(enable_dict)
+	await env.redirect_other_agent.bundle.step(2100)	#for the Initial ram
+	# set value
+	print("begin exec test_redirect_cfi_sanity test")
+
+#	await env.redirect_other_agent.set_redirect_other_value()
+	task_redirect_other 	= mlvp.create_task(env.redirect_other_agent.set_redirect_other_value(rediretc_ohter_dict))
+	task_redirect_fold_hist = mlvp.create_task(env.redirect_fold_hist_agent.set_redirect_fold_hist_value(redirect_fold_hist_dict))
+	task_redirect_afhob 	= mlvp.create_task(env.redirect_afhob_agent.set_redirect_afhob_value(redirect_afhob_dict))
+
+	await task_redirect_other 
+	await task_redirect_fold_hist
+	await task_redirect_afhob
+
+	await env.redirect_other_agent.bundle.step(10)
+
+
+	task_update_ftb_entry 	= mlvp.create_task(env.update_ftb_entry_agent.set_update_ftb_entry_value(update_pc,update_ftb_entry_dict)) 
+	task_update_other 		= mlvp.create_task(env.update_other_agent.set_update_other_value(update_pc,update_other_dict))
+	task_update_foldedHist 	= mlvp.create_task(env.update_fold_hist_agent.set_update_fold_hist_value(update_pc,update_fold_hist_dict))
+
+	await task_update_ftb_entry
+	await task_update_other
+	await task_update_foldedHist
+
+	####Second value
+	rediretc_ohter_dict = {
+		'level'					: 1,
+		'cfiUpdate_pc'			: 0x1480,
+		'cfiUpdate_pd_isRVC'	: 0,
+		'cfiUpdate_pd_isCall'	: 0,
+		'cfiUpdate_pd_isRet'	: 0,
+		'cfiUpdate_ssp'			: 0,
+		'cfiUpdate_sctr'		: 0,
+		'cfiUpdate_TOSW_flag'	: 0,
+		'cfiUpdate_TOSW_value'	: 0,
+		'cfiUpdate_TOSR_flag'	: 0,
+		'cfiUpdate_TOSR_value'	: 0,
+		'cfiUpdate_NOS_flag'	: 0,
+		'cfiUpdate_NOS_value'	: 0,
+
+		'cfiUpdate_lastBrNumOH'	: 1, 
+		'cfiUpdate_histPtr_flag': 1, 
+		'cfiUpdate_histPtr_value':0, 
+		'cfiUpdate_target'		: 0,
+		'cfiUpdate_taken'		: 0,
+		'cfiUpdate_shift'		: 1,
+		'cfiUpdate_addIntoHist'	: 1
+	}
+
+	redirect_fold_hist_dict = {
+		'cfiUpdate_folded_hist_0'	: 0b011,
+		'cfiUpdate_folded_hist_1'	: 0b011,
+		'cfiUpdate_folded_hist_2'	: 0b011,
+		'cfiUpdate_folded_hist_3'	: 0b011,
+		'cfiUpdate_folded_hist_4'	: 0b011,
+		'cfiUpdate_folded_hist_5'	: 0b011,
+		'cfiUpdate_folded_hist_6'	: 0b011,
+		'cfiUpdate_folded_hist_7'	: 0b011,
+		'cfiUpdate_folded_hist_8'	: 0b011,
+		'cfiUpdate_folded_hist_9'	: 0b011,
+
+		'cfiUpdate_folded_hist_10': 0b111,
+		'cfiUpdate_folded_hist_11': 0b111,
+		'cfiUpdate_folded_hist_12': 0b111,
+		'cfiUpdate_folded_hist_13': 0b111,
+		'cfiUpdate_folded_hist_14': 0b111,
+		'cfiUpdate_folded_hist_15': 0b111,
+		'cfiUpdate_folded_hist_16': 0b111,
+		'cfiUpdate_folded_hist_17': 0b111
+	}
+
+	redirect_afhob_dict = {
+		'afhob_0_bits_0'	: 0b0,
+		'afhob_0_bits_1'	: 0b0,
+		'afhob_0_bits_2'	: 0b0,
+		'afhob_0_bits_3'	: 0b0,
+		'afhob_1_bits_0'	: 0b0,
+		'afhob_1_bits_1'	: 0b0,
+		'afhob_1_bits_2'	: 0b0,
+		'afhob_1_bits_3'	: 0b0,
+		'afhob_2_bits_0'	: 0b0,
+		'afhob_2_bits_1'	: 0b0,
+		'afhob_2_bits_2'	: 0b0,
+		'afhob_2_bits_3'	: 0b0,
+		'afhob_3_bits_0'	: 0b0,
+		'afhob_3_bits_1'	: 0b0,
+		'afhob_3_bits_2'	: 0b0,
+		'afhob_3_bits_3'	: 0b0,
+		'afhob_4_bits_0'	: 0b0,
+		'afhob_4_bits_1'	: 0b0,
+		'afhob_4_bits_2'	: 0b0,
+		'afhob_5_bits_0'	: 0b0,
+		'afhob_5_bits_1'	: 0b0,
+		'afhob_5_bits_2'	: 0b0,
+		'afhob_5_bits_3'	: 0b0
+	}
+	update_ftb_entry_dict = {
+		'ftb_entry_valid'	: 1,
+		'tailSlot_valid'	: 1,
+		'tailSlot_tarStat'	: 0b11,
+		'tailSlot_sharing'	: 1,
+		'tailSlot_offset'	: 0b1111,
+		'tailSlot_lower'	: 0x22,
+		'pftAddr'			: 0b1111,
+		'may_be_rvi_call'	: 1,
+		'isRet'				: 1,
+		'isJalr'			: 1,
+		'isCall'			: 1,
+		'carry'				: 1,
+		'always_taken_0'	: 1,
+		'always_taken_1'	: 1,
+		'brSlots_0_valid'	: 1,
+		'brSlots_0_tarStat' : 0b10,
+		'brSlots_0_sharing'	: 1,
+		'brSlots_0_offset'	: 0b0100,
+		'brSlots_0_lower'	: 0x200
+	}
+
+	## update_other_signals
+	update_other_dict = {
+		'cfi_idx_valid'		: 1,
+		'cfi_idx_bits'		: 0b0111,
+		'br_taken_mask_0'	: 1,
+		'br_taken_mask_1'	: 0,
+		'jmp_taken'			: 0,
+		'mispred_mask_0'	: 0,
+		'mispred_mask_1'	: 0,
+		'mispred_mask_2'	: 0,
+		'old_entry'			: 0,
+		'meta'				: 0,
+		'full_target'		: 0
+	}
+
+	update_fold_hist_dict = {
+		'folded_hist_1' 	: 0b1000,
+		'folded_hist_2' 	: 0b1001,
+		'folded_hist_3' 	: 0b1010,
+		'folded_hist_4' 	: 0b1100,
+		'folded_hist_5' 	: 0b0001,
+		'folded_hist_6' 	: 0b0000,
+		'folded_hist_7' 	: 0b0001,
+		'folded_hist_8' 	: 0b0010,
+		'folded_hist_9' 	: 0b0100,
+		'folded_hist_10' 	: 0b1000,
+		'folded_hist_11' 	: 0b1100,
+		'folded_hist_12' 	: 0b1110,
+		'folded_hist_13' 	: 0b1111,
+		'folded_hist_14' 	: 0b0000,
+		'folded_hist_15' 	: 0b1111,
+		'folded_hist_16' 	: 0b1001,
+		'folded_hist_17' 	: 0b1001
+	}
+
+	task_redirect_other_1 	= mlvp.create_task(env.redirect_other_agent.set_redirect_other_value(rediretc_ohter_dict))
+	task_redirect_fold_hist_1 = mlvp.create_task(env.redirect_fold_hist_agent.set_redirect_fold_hist_value(redirect_fold_hist_dict))
+	task_redirect_afhob_1 	= mlvp.create_task(env.redirect_afhob_agent.set_redirect_afhob_value(redirect_afhob_dict))
+
+	await task_redirect_other_1 
+	await task_redirect_fold_hist_1
+	await task_redirect_afhob_1
+
+	await env.redirect_other_agent.bundle.step(10)
+
+	task_update_ftb_entry_1 	= mlvp.create_task(env.update_ftb_entry_agent.set_update_ftb_entry_value(update_pc,update_ftb_entry_dict)) 
+	task_update_other_1 		= mlvp.create_task(env.update_other_agent.set_update_other_value(update_pc,update_other_dict))
+	task_update_foldedHist_1 	= mlvp.create_task(env.update_fold_hist_agent.set_update_fold_hist_value(update_pc,update_fold_hist_dict))
+
+	await task_update_ftb_entry_1
+	await task_update_other_1
+	await task_update_foldedHist_1
+
+#	await env.redirect_afhob_agent.set_redirect_afhob_value()
+
+
+
+	enable_dict = {
+		'ubtb_en' 	: 1,	
+		'btb_en'	: 0,
+		'tage_en'	: 0,
+		'sc_en'		: 1,
+		'ras_en'	: 1
+	}
+
+	await env.sub_predi_ctrl_agent.set_sub_predic_ctrl_en(enable_dict)
+	await env.redirect_other_agent.bundle.step(20)	#for the Initial ram
+
+	####Third value
+	rediretc_ohter_dict = {
+		'level'					: 1,
+		'cfiUpdate_pc'			: 0x1480,
+		'cfiUpdate_pd_isRVC'	: 1,
+		'cfiUpdate_pd_isCall'	: 0,
+		'cfiUpdate_pd_isRet'	: 0,
+		'cfiUpdate_ssp'			: 0,
+		'cfiUpdate_sctr'		: 1,
+		'cfiUpdate_TOSW_flag'	: 0,
+		'cfiUpdate_TOSW_value'	: 1,
+		'cfiUpdate_TOSR_flag'	: 0,
+		'cfiUpdate_TOSR_value'	: 0,
+		'cfiUpdate_NOS_flag'	: 1,
+		'cfiUpdate_NOS_value'	: 0,
+
+		'cfiUpdate_lastBrNumOH'	: 1, 
+		'cfiUpdate_histPtr_flag': 1, 
+		'cfiUpdate_histPtr_value':0, 
+		'cfiUpdate_target'		: 1,
+		'cfiUpdate_taken'		: 0,
+		'cfiUpdate_shift'		: 1,
+		'cfiUpdate_addIntoHist'	: 1
+	}
+
+	redirect_fold_hist_dict = {
+		'cfiUpdate_folded_hist_0'	: 0b011,
+		'cfiUpdate_folded_hist_1'	: 0b011,
+		'cfiUpdate_folded_hist_2'	: 0b011,
+		'cfiUpdate_folded_hist_3'	: 0b011,
+		'cfiUpdate_folded_hist_4'	: 0b011,
+		'cfiUpdate_folded_hist_5'	: 0b011,
+		'cfiUpdate_folded_hist_6'	: 0b011,
+		'cfiUpdate_folded_hist_7'	: 0b011,
+		'cfiUpdate_folded_hist_8'	: 0b011,
+		'cfiUpdate_folded_hist_9'	: 0b011,
+
+		'cfiUpdate_folded_hist_10': 0b111,
+		'cfiUpdate_folded_hist_11': 0b111,
+		'cfiUpdate_folded_hist_12': 0b111,
+		'cfiUpdate_folded_hist_13': 0b111,
+		'cfiUpdate_folded_hist_14': 0b111,
+		'cfiUpdate_folded_hist_15': 0b111,
+		'cfiUpdate_folded_hist_16': 0b111,
+		'cfiUpdate_folded_hist_17': 0b111
+	}
+
+	redirect_afhob_dict = {
+		'afhob_0_bits_0'	: 0b1,
+		'afhob_0_bits_1'	: 0b1,
+		'afhob_0_bits_2'	: 0b1,
+		'afhob_0_bits_3'	: 0b1,
+		'afhob_1_bits_0'	: 0b1,
+		'afhob_1_bits_1'	: 0b1,
+		'afhob_1_bits_2'	: 0b1,
+		'afhob_1_bits_3'	: 0b1,
+		'afhob_2_bits_0'	: 0b1,
+		'afhob_2_bits_1'	: 0b1,
+		'afhob_2_bits_2'	: 0b1,
+		'afhob_2_bits_3'	: 0b1,
+		'afhob_3_bits_0'	: 0b1,
+		'afhob_3_bits_1'	: 0b1,
+		'afhob_3_bits_2'	: 0b1,
+		'afhob_3_bits_3'	: 0b1,
+		'afhob_4_bits_0'	: 0b1,
+		'afhob_4_bits_1'	: 0b1,
+		'afhob_4_bits_2'	: 0b1,
+		'afhob_5_bits_0'	: 0b1,
+		'afhob_5_bits_1'	: 0b1,
+		'afhob_5_bits_2'	: 0b1,
+		'afhob_5_bits_3'	: 0b1
+	}
+	update_ftb_entry_dict = {
+		'ftb_entry_valid'	: 1,
+		'tailSlot_valid'	: 1,
+		'tailSlot_tarStat'	: 0b11,
+		'tailSlot_sharing'	: 1,
+		'tailSlot_offset'	: 0b1111,
+		'tailSlot_lower'	: 0x22,
+		'pftAddr'			: 0b1111,
+		'may_be_rvi_call'	: 1,
+		'isRet'				: 1,
+		'isJalr'			: 1,
+		'isCall'			: 1,
+		'carry'				: 1,
+		'always_taken_0'	: 1,
+		'always_taken_1'	: 1,
+		'brSlots_0_valid'	: 1,
+		'brSlots_0_tarStat' : 0b10,
+		'brSlots_0_sharing'	: 1,
+		'brSlots_0_offset'	: 0b0100,
+		'brSlots_0_lower'	: 0x200
+	}
+
+	## update_other_signals
+	update_other_dict = {
+		'cfi_idx_valid'		: 1,
+		'cfi_idx_bits'		: 0b0111,
+		'br_taken_mask_0'	: 1,
+		'br_taken_mask_1'	: 0,
+		'jmp_taken'			: 0,
+		'mispred_mask_0'	: 0,
+		'mispred_mask_1'	: 0,
+		'mispred_mask_2'	: 0,
+		'old_entry'			: 0,
+		'meta'				: 0,
+		'full_target'		: 0
+	}
+
+	update_fold_hist_dict = {
+		'folded_hist_1' 	: 0b1000,
+		'folded_hist_2' 	: 0b1001,
+		'folded_hist_3' 	: 0b1010,
+		'folded_hist_4' 	: 0b1100,
+		'folded_hist_5' 	: 0b0001,
+		'folded_hist_6' 	: 0b0000,
+		'folded_hist_7' 	: 0b0001,
+		'folded_hist_8' 	: 0b0010,
+		'folded_hist_9' 	: 0b0100,
+		'folded_hist_10' 	: 0b1000,
+		'folded_hist_11' 	: 0b1100,
+		'folded_hist_12' 	: 0b1110,
+		'folded_hist_13' 	: 0b1111,
+		'folded_hist_14' 	: 0b0000,
+		'folded_hist_15' 	: 0b1111,
+		'folded_hist_16' 	: 0b1001,
+		'folded_hist_17' 	: 0b1001
+	}
+
+	task_redirect_other_1 	= mlvp.create_task(env.redirect_other_agent.set_redirect_other_value(rediretc_ohter_dict))
+	task_redirect_fold_hist_1 = mlvp.create_task(env.redirect_fold_hist_agent.set_redirect_fold_hist_value(redirect_fold_hist_dict))
+	task_redirect_afhob_1 	= mlvp.create_task(env.redirect_afhob_agent.set_redirect_afhob_value(redirect_afhob_dict))
+
+	await task_redirect_other_1 
+	await task_redirect_fold_hist_1
+	await task_redirect_afhob_1
+
+	await env.redirect_other_agent.bundle.step(10)
+
+	task_update_ftb_entry_1 	= mlvp.create_task(env.update_ftb_entry_agent.set_update_ftb_entry_value(update_pc,update_ftb_entry_dict)) 
+	task_update_other_1 		= mlvp.create_task(env.update_other_agent.set_update_other_value(update_pc,update_other_dict))
+	task_update_foldedHist_1 	= mlvp.create_task(env.update_fold_hist_agent.set_update_fold_hist_value(update_pc,update_fold_hist_dict))
+
+	await task_update_ftb_entry_1
+	await task_update_other_1
+	await task_update_foldedHist_1
+
+
+	await task_clock
+	print("test_normal_sanity IS OVER")
+
+
+@pytest.mark.mlvp_async
+async def test_normal_redirect_cfi_twice_6(mlvp_request):
+	print(mlvp_request)
+	env: BpuEnv = mlvp_request()
+	update_pc = 0x2480
+
+	# set value
+	enable_dict = {
+		'ubtb_en' 	: 1,	
+		'btb_en'	: 1,
+		'tage_en'	: 1,
+		'sc_en'		: 1,
+		'ras_en'	: 1
+	}
+
+	rediretc_ohter_dict = {
+		'level'					: 1,
+		'cfiUpdate_pc'			: 0x2280,
+		'cfiUpdate_pd_isRVC'	: 1,
+		'cfiUpdate_pd_isCall'	: 1,
+		'cfiUpdate_pd_isRet'	: 1,
+		'cfiUpdate_ssp'			: 1,
+		'cfiUpdate_sctr'		: 1,
+		'cfiUpdate_TOSW_flag'	: 1,
+		'cfiUpdate_TOSW_value'	: 1,
+		'cfiUpdate_TOSR_flag'	: 1,
+		'cfiUpdate_TOSR_value'	: 1,
+		'cfiUpdate_NOS_flag'	: 1,
+		'cfiUpdate_NOS_value'	: 1,
+
+		'cfiUpdate_lastBrNumOH'	: 1, 
+		'cfiUpdate_histPtr_flag': 1, 
+		'cfiUpdate_histPtr_value':1, 
+		'cfiUpdate_target'		: 1,
+		'cfiUpdate_taken'		: 1,
+		'cfiUpdate_shift'		: 1,
+		'cfiUpdate_addIntoHist'	: 1
+	}
+
+	redirect_fold_hist_dict = {
+		'cfiUpdate_folded_hist_0'	: 0b100,
+		'cfiUpdate_folded_hist_1'	: 0b100,
+		'cfiUpdate_folded_hist_2'	: 0b100,
+		'cfiUpdate_folded_hist_3'	: 0b100,
+		'cfiUpdate_folded_hist_4'	: 0b100,
+		'cfiUpdate_folded_hist_5'	: 0b100,
+		'cfiUpdate_folded_hist_6'	: 0b100,
+		'cfiUpdate_folded_hist_7'	: 0b100,
+		'cfiUpdate_folded_hist_8'	: 0b100,
+		'cfiUpdate_folded_hist_9'	: 0b100,
+
+		'cfiUpdate_folded_hist_10': 0b100,
+		'cfiUpdate_folded_hist_11': 0b100,
+		'cfiUpdate_folded_hist_12': 0b100,
+		'cfiUpdate_folded_hist_13': 0b100,
+		'cfiUpdate_folded_hist_14': 0b100,
+		'cfiUpdate_folded_hist_15': 0b100,
+		'cfiUpdate_folded_hist_16': 0b100,
+		'cfiUpdate_folded_hist_17': 0b100
+	}
+
+	redirect_afhob_dict = {
+		'afhob_0_bits_0'	: 0b1,
+		'afhob_0_bits_1'	: 0b1,
+		'afhob_0_bits_2'	: 0b1,
+		'afhob_0_bits_3'	: 0b1,
+		'afhob_1_bits_0'	: 0b1,
+		'afhob_1_bits_1'	: 0b1,
+		'afhob_1_bits_2'	: 0b1,
+		'afhob_1_bits_3'	: 0b1,
+		'afhob_2_bits_0'	: 0b1,
+		'afhob_2_bits_1'	: 0b1,
+		'afhob_2_bits_2'	: 0b1,
+		'afhob_2_bits_3'	: 0b1,
+		'afhob_3_bits_0'	: 0b1,
+		'afhob_3_bits_1'	: 0b1,
+		'afhob_3_bits_2'	: 0b1,
+		'afhob_3_bits_3'	: 0b1,
+		'afhob_4_bits_0'	: 0b1,
+		'afhob_4_bits_1'	: 0b1,
+		'afhob_4_bits_2'	: 0b1,
+		'afhob_5_bits_0'	: 0b1,
+		'afhob_5_bits_1'	: 0b1,
+		'afhob_5_bits_2'	: 0b1,
+		'afhob_5_bits_3'	: 0b1
+	}
+
+	update_ftb_entry_dict = {
+		'ftb_entry_valid'	: 1,
+		'tailSlot_valid'	: 1,
+		'tailSlot_tarStat'	: 0b10,
+		'tailSlot_sharing'	: 1,
+		'tailSlot_offset'	: 0b0100,
+		'tailSlot_lower'	: 0x20,
+		'pftAddr'			: 0b1000,
+		'may_be_rvi_call'	: 1,
+		'isRet'				: 1,
+		'isJalr'			: 1,
+		'isCall'			: 1,
+		'carry'				: 1,
+		'always_taken_0'	: 1,
+		'always_taken_1'	: 1,
+		'brSlots_0_valid'	: 1,
+		'brSlots_0_tarStat' : 0b10,
+		'brSlots_0_sharing'	: 1,
+		'brSlots_0_offset'	: 0b0100,
+		'brSlots_0_lower'	: 0x200
+	}
+	## update_other_signals
+	update_other_dict = {
+		'cfi_idx_valid'		: 1,
+		'cfi_idx_bits'		: 0b1000,
+		'br_taken_mask_0'	: 1,
+		'br_taken_mask_1'	: 1,
+		'jmp_taken'			: 0,
+		'mispred_mask_0'	: 1,
+		'mispred_mask_1'	: 1,
+		'mispred_mask_2'	: 1,
+		'old_entry'			: 1,
+		'meta'				: 1,
+		'full_target'		: 1
+	}
+
+	update_fold_hist_dict = {
+		'folded_hist_1' 	: 0b1000,
+		'folded_hist_2' 	: 0b1001,
+		'folded_hist_3' 	: 0b1010,
+		'folded_hist_4' 	: 0b1100,
+		'folded_hist_5' 	: 0b0001,
+		'folded_hist_6' 	: 0b0000,
+		'folded_hist_7' 	: 0b0001,
+		'folded_hist_8' 	: 0b0010,
+		'folded_hist_9' 	: 0b0100,
+		'folded_hist_10' 	: 0b1000,
+		'folded_hist_11' 	: 0b1100,
+		'folded_hist_12' 	: 0b1110,
+		'folded_hist_13' 	: 0b1111,
+		'folded_hist_14' 	: 0b0000,
+		'folded_hist_15' 	: 0b1111,
+		'folded_hist_16' 	: 0b1001,
+		'folded_hist_17' 	: 0b1001
+	}
+
+
+	# reset
+	task_clock = mlvp.create_task(env.update_ftb_entry_agent.bundle.step(2200))
+	await env.redirect_other_agent.reset(4)
+	await env.sub_predi_ctrl_agent.set_sub_predic_ctrl_en(enable_dict)
+	await env.redirect_other_agent.bundle.step(2100)	#for the Initial ram
+	# set value
+	print("begin exec test_redirect_cfi_sanity test")
+
+#	await env.redirect_other_agent.set_redirect_other_value()
+	task_redirect_other 	= mlvp.create_task(env.redirect_other_agent.set_redirect_other_value(rediretc_ohter_dict))
+	task_redirect_fold_hist = mlvp.create_task(env.redirect_fold_hist_agent.set_redirect_fold_hist_value(redirect_fold_hist_dict))
+	task_redirect_afhob 	= mlvp.create_task(env.redirect_afhob_agent.set_redirect_afhob_value(redirect_afhob_dict))
+
+	await task_redirect_other 
+	await task_redirect_fold_hist
+	await task_redirect_afhob
+
+	await env.redirect_other_agent.bundle.step(10)
+
+
+	task_update_ftb_entry 	= mlvp.create_task(env.update_ftb_entry_agent.set_update_ftb_entry_value(update_pc,update_ftb_entry_dict)) 
+	task_update_other 		= mlvp.create_task(env.update_other_agent.set_update_other_value(update_pc,update_other_dict))
+	task_update_foldedHist 	= mlvp.create_task(env.update_fold_hist_agent.set_update_fold_hist_value(update_pc,update_fold_hist_dict))
+
+	await task_update_ftb_entry
+	await task_update_other
+	await task_update_foldedHist
+
+	####Second value
+	rediretc_ohter_dict = {
+		'level'					: 1,
+		'cfiUpdate_pc'			: 0x1480,
+		'cfiUpdate_pd_isRVC'	: 0,
+		'cfiUpdate_pd_isCall'	: 0,
+		'cfiUpdate_pd_isRet'	: 0,
+		'cfiUpdate_ssp'			: 0,
+		'cfiUpdate_sctr'		: 0,
+		'cfiUpdate_TOSW_flag'	: 0,
+		'cfiUpdate_TOSW_value'	: 0,
+		'cfiUpdate_TOSR_flag'	: 0,
+		'cfiUpdate_TOSR_value'	: 0,
+		'cfiUpdate_NOS_flag'	: 0,
+		'cfiUpdate_NOS_value'	: 0,
+
+		'cfiUpdate_lastBrNumOH'	: 1, 
+		'cfiUpdate_histPtr_flag': 1, 
+		'cfiUpdate_histPtr_value':0, 
+		'cfiUpdate_target'		: 0,
+		'cfiUpdate_taken'		: 0,
+		'cfiUpdate_shift'		: 1,
+		'cfiUpdate_addIntoHist'	: 1
+	}
+
+	redirect_fold_hist_dict = {
+		'cfiUpdate_folded_hist_0'	: 0b011,
+		'cfiUpdate_folded_hist_1'	: 0b011,
+		'cfiUpdate_folded_hist_2'	: 0b011,
+		'cfiUpdate_folded_hist_3'	: 0b011,
+		'cfiUpdate_folded_hist_4'	: 0b011,
+		'cfiUpdate_folded_hist_5'	: 0b011,
+		'cfiUpdate_folded_hist_6'	: 0b011,
+		'cfiUpdate_folded_hist_7'	: 0b011,
+		'cfiUpdate_folded_hist_8'	: 0b011,
+		'cfiUpdate_folded_hist_9'	: 0b011,
+
+		'cfiUpdate_folded_hist_10': 0b111,
+		'cfiUpdate_folded_hist_11': 0b111,
+		'cfiUpdate_folded_hist_12': 0b111,
+		'cfiUpdate_folded_hist_13': 0b111,
+		'cfiUpdate_folded_hist_14': 0b111,
+		'cfiUpdate_folded_hist_15': 0b111,
+		'cfiUpdate_folded_hist_16': 0b111,
+		'cfiUpdate_folded_hist_17': 0b111
+	}
+
+	redirect_afhob_dict = {
+		'afhob_0_bits_0'	: 0b0,
+		'afhob_0_bits_1'	: 0b0,
+		'afhob_0_bits_2'	: 0b0,
+		'afhob_0_bits_3'	: 0b0,
+		'afhob_1_bits_0'	: 0b0,
+		'afhob_1_bits_1'	: 0b0,
+		'afhob_1_bits_2'	: 0b0,
+		'afhob_1_bits_3'	: 0b0,
+		'afhob_2_bits_0'	: 0b0,
+		'afhob_2_bits_1'	: 0b0,
+		'afhob_2_bits_2'	: 0b0,
+		'afhob_2_bits_3'	: 0b0,
+		'afhob_3_bits_0'	: 0b0,
+		'afhob_3_bits_1'	: 0b0,
+		'afhob_3_bits_2'	: 0b0,
+		'afhob_3_bits_3'	: 0b0,
+		'afhob_4_bits_0'	: 0b0,
+		'afhob_4_bits_1'	: 0b0,
+		'afhob_4_bits_2'	: 0b0,
+		'afhob_5_bits_0'	: 0b0,
+		'afhob_5_bits_1'	: 0b0,
+		'afhob_5_bits_2'	: 0b0,
+		'afhob_5_bits_3'	: 0b0
+	}
+	update_ftb_entry_dict = {
+		'ftb_entry_valid'	: 1,
+		'tailSlot_valid'	: 1,
+		'tailSlot_tarStat'	: 0b11,
+		'tailSlot_sharing'	: 1,
+		'tailSlot_offset'	: 0b1111,
+		'tailSlot_lower'	: 0x22,
+		'pftAddr'			: 0b1111,
+		'may_be_rvi_call'	: 1,
+		'isRet'				: 1,
+		'isJalr'			: 1,
+		'isCall'			: 1,
+		'carry'				: 1,
+		'always_taken_0'	: 1,
+		'always_taken_1'	: 1,
+		'brSlots_0_valid'	: 1,
+		'brSlots_0_tarStat' : 0b10,
+		'brSlots_0_sharing'	: 1,
+		'brSlots_0_offset'	: 0b0100,
+		'brSlots_0_lower'	: 0x200
+	}
+
+	## update_other_signals
+	update_other_dict = {
+		'cfi_idx_valid'		: 1,
+		'cfi_idx_bits'		: 0b0111,
+		'br_taken_mask_0'	: 1,
+		'br_taken_mask_1'	: 0,
+		'jmp_taken'			: 0,
+		'mispred_mask_0'	: 0,
+		'mispred_mask_1'	: 0,
+		'mispred_mask_2'	: 0,
+		'old_entry'			: 0,
+		'meta'				: 0,
+		'full_target'		: 0
+	}
+
+	update_fold_hist_dict = {
+		'folded_hist_1' 	: 0b1000,
+		'folded_hist_2' 	: 0b1001,
+		'folded_hist_3' 	: 0b1010,
+		'folded_hist_4' 	: 0b1100,
+		'folded_hist_5' 	: 0b0001,
+		'folded_hist_6' 	: 0b0000,
+		'folded_hist_7' 	: 0b0001,
+		'folded_hist_8' 	: 0b0010,
+		'folded_hist_9' 	: 0b0100,
+		'folded_hist_10' 	: 0b1000,
+		'folded_hist_11' 	: 0b1100,
+		'folded_hist_12' 	: 0b1110,
+		'folded_hist_13' 	: 0b1111,
+		'folded_hist_14' 	: 0b0000,
+		'folded_hist_15' 	: 0b1111,
+		'folded_hist_16' 	: 0b1001,
+		'folded_hist_17' 	: 0b1001
+	}
+
+	task_redirect_other_1 	= mlvp.create_task(env.redirect_other_agent.set_redirect_other_value(rediretc_ohter_dict))
+	task_redirect_fold_hist_1 = mlvp.create_task(env.redirect_fold_hist_agent.set_redirect_fold_hist_value(redirect_fold_hist_dict))
+	task_redirect_afhob_1 	= mlvp.create_task(env.redirect_afhob_agent.set_redirect_afhob_value(redirect_afhob_dict))
+
+	await task_redirect_other_1 
+	await task_redirect_fold_hist_1
+	await task_redirect_afhob_1
+
+	await env.redirect_other_agent.bundle.step(10)
+
+	task_update_ftb_entry_1 	= mlvp.create_task(env.update_ftb_entry_agent.set_update_ftb_entry_value(update_pc,update_ftb_entry_dict)) 
+	task_update_other_1 		= mlvp.create_task(env.update_other_agent.set_update_other_value(update_pc,update_other_dict))
+	task_update_foldedHist_1 	= mlvp.create_task(env.update_fold_hist_agent.set_update_fold_hist_value(update_pc,update_fold_hist_dict))
+
+	await task_update_ftb_entry_1
+	await task_update_other_1
+	await task_update_foldedHist_1
+
+#	await env.redirect_afhob_agent.set_redirect_afhob_value()
+
+	enable_dict = {
+		'ubtb_en' 	: 1,	
+		'btb_en'	: 1,
+		'tage_en'	: 0,
+		'sc_en'		: 0,
+		'ras_en'	: 1
+	}
+
+	await env.sub_predi_ctrl_agent.set_sub_predic_ctrl_en(enable_dict)
+	await env.redirect_other_agent.bundle.step(20)	#for the Initial ram
+
+	####Third value
+	rediretc_ohter_dict = {
+		'level'					: 1,
+		'cfiUpdate_pc'			: 0x1480,
+		'cfiUpdate_pd_isRVC'	: 1,
+		'cfiUpdate_pd_isCall'	: 0,
+		'cfiUpdate_pd_isRet'	: 0,
+		'cfiUpdate_ssp'			: 0,
+		'cfiUpdate_sctr'		: 1,
+		'cfiUpdate_TOSW_flag'	: 0,
+		'cfiUpdate_TOSW_value'	: 1,
+		'cfiUpdate_TOSR_flag'	: 0,
+		'cfiUpdate_TOSR_value'	: 0,
+		'cfiUpdate_NOS_flag'	: 1,
+		'cfiUpdate_NOS_value'	: 0,
+
+		'cfiUpdate_lastBrNumOH'	: 1, 
+		'cfiUpdate_histPtr_flag': 1, 
+		'cfiUpdate_histPtr_value':0, 
+		'cfiUpdate_target'		: 1,
+		'cfiUpdate_taken'		: 0,
+		'cfiUpdate_shift'		: 1,
+		'cfiUpdate_addIntoHist'	: 1
+	}
+
+	redirect_fold_hist_dict = {
+		'cfiUpdate_folded_hist_0'	: 0b011,
+		'cfiUpdate_folded_hist_1'	: 0b011,
+		'cfiUpdate_folded_hist_2'	: 0b011,
+		'cfiUpdate_folded_hist_3'	: 0b011,
+		'cfiUpdate_folded_hist_4'	: 0b011,
+		'cfiUpdate_folded_hist_5'	: 0b011,
+		'cfiUpdate_folded_hist_6'	: 0b011,
+		'cfiUpdate_folded_hist_7'	: 0b011,
+		'cfiUpdate_folded_hist_8'	: 0b011,
+		'cfiUpdate_folded_hist_9'	: 0b011,
+
+		'cfiUpdate_folded_hist_10': 0b111,
+		'cfiUpdate_folded_hist_11': 0b111,
+		'cfiUpdate_folded_hist_12': 0b111,
+		'cfiUpdate_folded_hist_13': 0b111,
+		'cfiUpdate_folded_hist_14': 0b111,
+		'cfiUpdate_folded_hist_15': 0b111,
+		'cfiUpdate_folded_hist_16': 0b111,
+		'cfiUpdate_folded_hist_17': 0b111
+	}
+
+	redirect_afhob_dict = {
+		'afhob_0_bits_0'	: 0b1,
+		'afhob_0_bits_1'	: 0b1,
+		'afhob_0_bits_2'	: 0b1,
+		'afhob_0_bits_3'	: 0b1,
+		'afhob_1_bits_0'	: 0b1,
+		'afhob_1_bits_1'	: 0b1,
+		'afhob_1_bits_2'	: 0b1,
+		'afhob_1_bits_3'	: 0b1,
+		'afhob_2_bits_0'	: 0b1,
+		'afhob_2_bits_1'	: 0b1,
+		'afhob_2_bits_2'	: 0b1,
+		'afhob_2_bits_3'	: 0b1,
+		'afhob_3_bits_0'	: 0b1,
+		'afhob_3_bits_1'	: 0b1,
+		'afhob_3_bits_2'	: 0b1,
+		'afhob_3_bits_3'	: 0b1,
+		'afhob_4_bits_0'	: 0b1,
+		'afhob_4_bits_1'	: 0b1,
+		'afhob_4_bits_2'	: 0b1,
+		'afhob_5_bits_0'	: 0b1,
+		'afhob_5_bits_1'	: 0b1,
+		'afhob_5_bits_2'	: 0b1,
+		'afhob_5_bits_3'	: 0b1
+	}
+	update_ftb_entry_dict = {
+		'ftb_entry_valid'	: 1,
+		'tailSlot_valid'	: 1,
+		'tailSlot_tarStat'	: 0b11,
+		'tailSlot_sharing'	: 1,
+		'tailSlot_offset'	: 0b1111,
+		'tailSlot_lower'	: 0x22,
+		'pftAddr'			: 0b1111,
+		'may_be_rvi_call'	: 1,
+		'isRet'				: 1,
+		'isJalr'			: 1,
+		'isCall'			: 1,
+		'carry'				: 1,
+		'always_taken_0'	: 1,
+		'always_taken_1'	: 1,
+		'brSlots_0_valid'	: 1,
+		'brSlots_0_tarStat' : 0b10,
+		'brSlots_0_sharing'	: 1,
+		'brSlots_0_offset'	: 0b0100,
+		'brSlots_0_lower'	: 0x200
+	}
+
+	## update_other_signals
+	update_other_dict = {
+		'cfi_idx_valid'		: 1,
+		'cfi_idx_bits'		: 0b0111,
+		'br_taken_mask_0'	: 1,
+		'br_taken_mask_1'	: 0,
+		'jmp_taken'			: 0,
+		'mispred_mask_0'	: 0,
+		'mispred_mask_1'	: 0,
+		'mispred_mask_2'	: 0,
+		'old_entry'			: 0,
+		'meta'				: 0,
+		'full_target'		: 0
+	}
+
+	update_fold_hist_dict = {
+		'folded_hist_1' 	: 0b1000,
+		'folded_hist_2' 	: 0b1001,
+		'folded_hist_3' 	: 0b1010,
+		'folded_hist_4' 	: 0b1100,
+		'folded_hist_5' 	: 0b0001,
+		'folded_hist_6' 	: 0b0000,
+		'folded_hist_7' 	: 0b0001,
+		'folded_hist_8' 	: 0b0010,
+		'folded_hist_9' 	: 0b0100,
+		'folded_hist_10' 	: 0b1000,
+		'folded_hist_11' 	: 0b1100,
+		'folded_hist_12' 	: 0b1110,
+		'folded_hist_13' 	: 0b1111,
+		'folded_hist_14' 	: 0b0000,
+		'folded_hist_15' 	: 0b1111,
+		'folded_hist_16' 	: 0b1001,
+		'folded_hist_17' 	: 0b1001
+	}
+
+	task_redirect_other_1 	= mlvp.create_task(env.redirect_other_agent.set_redirect_other_value(rediretc_ohter_dict))
+	task_redirect_fold_hist_1 = mlvp.create_task(env.redirect_fold_hist_agent.set_redirect_fold_hist_value(redirect_fold_hist_dict))
+	task_redirect_afhob_1 	= mlvp.create_task(env.redirect_afhob_agent.set_redirect_afhob_value(redirect_afhob_dict))
+
+	await task_redirect_other_1 
+	await task_redirect_fold_hist_1
+	await task_redirect_afhob_1
+
+	await env.redirect_other_agent.bundle.step(10)
+
+	task_update_ftb_entry_1 	= mlvp.create_task(env.update_ftb_entry_agent.set_update_ftb_entry_value(update_pc,update_ftb_entry_dict)) 
+	task_update_other_1 		= mlvp.create_task(env.update_other_agent.set_update_other_value(update_pc,update_other_dict))
+	task_update_foldedHist_1 	= mlvp.create_task(env.update_fold_hist_agent.set_update_fold_hist_value(update_pc,update_fold_hist_dict))
+
+	await task_update_ftb_entry_1
+	await task_update_other_1
+	await task_update_foldedHist_1
+
+
+	await task_clock
+	print("test_normal_sanity IS OVER")
+
+
+@pytest.mark.mlvp_async
+async def test_normal_redirect_cfi_twice_7(mlvp_request):
+	print(mlvp_request)
+	env: BpuEnv = mlvp_request()
+	update_pc = 0x2480
+
+	# set value
+	enable_dict = {
+		'ubtb_en' 	: 1,	
+		'btb_en'	: 1,
+		'tage_en'	: 1,
+		'sc_en'		: 1,
+		'ras_en'	: 1
+	}
+
+	rediretc_ohter_dict = {
+		'level'					: 1,
+		'cfiUpdate_pc'			: 0x2280,
+		'cfiUpdate_pd_isRVC'	: 1,
+		'cfiUpdate_pd_isCall'	: 1,
+		'cfiUpdate_pd_isRet'	: 1,
+		'cfiUpdate_ssp'			: 1,
+		'cfiUpdate_sctr'		: 1,
+		'cfiUpdate_TOSW_flag'	: 1,
+		'cfiUpdate_TOSW_value'	: 1,
+		'cfiUpdate_TOSR_flag'	: 1,
+		'cfiUpdate_TOSR_value'	: 1,
+		'cfiUpdate_NOS_flag'	: 1,
+		'cfiUpdate_NOS_value'	: 1,
+
+		'cfiUpdate_lastBrNumOH'	: 1, 
+		'cfiUpdate_histPtr_flag': 1, 
+		'cfiUpdate_histPtr_value':1, 
+		'cfiUpdate_target'		: 1,
+		'cfiUpdate_taken'		: 1,
+		'cfiUpdate_shift'		: 1,
+		'cfiUpdate_addIntoHist'	: 1
+	}
+
+	redirect_fold_hist_dict = {
+		'cfiUpdate_folded_hist_0'	: 0b100,
+		'cfiUpdate_folded_hist_1'	: 0b100,
+		'cfiUpdate_folded_hist_2'	: 0b100,
+		'cfiUpdate_folded_hist_3'	: 0b100,
+		'cfiUpdate_folded_hist_4'	: 0b100,
+		'cfiUpdate_folded_hist_5'	: 0b100,
+		'cfiUpdate_folded_hist_6'	: 0b100,
+		'cfiUpdate_folded_hist_7'	: 0b100,
+		'cfiUpdate_folded_hist_8'	: 0b100,
+		'cfiUpdate_folded_hist_9'	: 0b100,
+
+		'cfiUpdate_folded_hist_10': 0b100,
+		'cfiUpdate_folded_hist_11': 0b100,
+		'cfiUpdate_folded_hist_12': 0b100,
+		'cfiUpdate_folded_hist_13': 0b100,
+		'cfiUpdate_folded_hist_14': 0b100,
+		'cfiUpdate_folded_hist_15': 0b100,
+		'cfiUpdate_folded_hist_16': 0b100,
+		'cfiUpdate_folded_hist_17': 0b100
+	}
+
+	redirect_afhob_dict = {
+		'afhob_0_bits_0'	: 0b1,
+		'afhob_0_bits_1'	: 0b1,
+		'afhob_0_bits_2'	: 0b1,
+		'afhob_0_bits_3'	: 0b1,
+		'afhob_1_bits_0'	: 0b1,
+		'afhob_1_bits_1'	: 0b1,
+		'afhob_1_bits_2'	: 0b1,
+		'afhob_1_bits_3'	: 0b1,
+		'afhob_2_bits_0'	: 0b1,
+		'afhob_2_bits_1'	: 0b1,
+		'afhob_2_bits_2'	: 0b1,
+		'afhob_2_bits_3'	: 0b1,
+		'afhob_3_bits_0'	: 0b1,
+		'afhob_3_bits_1'	: 0b1,
+		'afhob_3_bits_2'	: 0b1,
+		'afhob_3_bits_3'	: 0b1,
+		'afhob_4_bits_0'	: 0b1,
+		'afhob_4_bits_1'	: 0b1,
+		'afhob_4_bits_2'	: 0b1,
+		'afhob_5_bits_0'	: 0b1,
+		'afhob_5_bits_1'	: 0b1,
+		'afhob_5_bits_2'	: 0b1,
+		'afhob_5_bits_3'	: 0b1
+	}
+
+	update_ftb_entry_dict = {
+		'ftb_entry_valid'	: 1,
+		'tailSlot_valid'	: 1,
+		'tailSlot_tarStat'	: 0b10,
+		'tailSlot_sharing'	: 1,
+		'tailSlot_offset'	: 0b0100,
+		'tailSlot_lower'	: 0x20,
+		'pftAddr'			: 0b1000,
+		'may_be_rvi_call'	: 1,
+		'isRet'				: 1,
+		'isJalr'			: 1,
+		'isCall'			: 1,
+		'carry'				: 1,
+		'always_taken_0'	: 1,
+		'always_taken_1'	: 1,
+		'brSlots_0_valid'	: 1,
+		'brSlots_0_tarStat' : 0b10,
+		'brSlots_0_sharing'	: 1,
+		'brSlots_0_offset'	: 0b0100,
+		'brSlots_0_lower'	: 0x200
+	}
+	## update_other_signals
+	update_other_dict = {
+		'cfi_idx_valid'		: 1,
+		'cfi_idx_bits'		: 0b1000,
+		'br_taken_mask_0'	: 1,
+		'br_taken_mask_1'	: 1,
+		'jmp_taken'			: 0,
+		'mispred_mask_0'	: 1,
+		'mispred_mask_1'	: 1,
+		'mispred_mask_2'	: 1,
+		'old_entry'			: 1,
+		'meta'				: 1,
+		'full_target'		: 1
+	}
+
+	update_fold_hist_dict = {
+		'folded_hist_1' 	: 0b1000,
+		'folded_hist_2' 	: 0b1001,
+		'folded_hist_3' 	: 0b1010,
+		'folded_hist_4' 	: 0b1100,
+		'folded_hist_5' 	: 0b0001,
+		'folded_hist_6' 	: 0b0000,
+		'folded_hist_7' 	: 0b0001,
+		'folded_hist_8' 	: 0b0010,
+		'folded_hist_9' 	: 0b0100,
+		'folded_hist_10' 	: 0b1000,
+		'folded_hist_11' 	: 0b1100,
+		'folded_hist_12' 	: 0b1110,
+		'folded_hist_13' 	: 0b1111,
+		'folded_hist_14' 	: 0b0000,
+		'folded_hist_15' 	: 0b1111,
+		'folded_hist_16' 	: 0b1001,
+		'folded_hist_17' 	: 0b1001
+	}
+
+
+	# reset
+	task_clock = mlvp.create_task(env.update_ftb_entry_agent.bundle.step(2200))
+	await env.redirect_other_agent.reset(4)
+	await env.sub_predi_ctrl_agent.set_sub_predic_ctrl_en(enable_dict)
+	await env.redirect_other_agent.bundle.step(2100)	#for the Initial ram
+	# set value
+	print("begin exec test_redirect_cfi_sanity test")
+
+#	await env.redirect_other_agent.set_redirect_other_value()
+	task_redirect_other 	= mlvp.create_task(env.redirect_other_agent.set_redirect_other_value(rediretc_ohter_dict))
+	task_redirect_fold_hist = mlvp.create_task(env.redirect_fold_hist_agent.set_redirect_fold_hist_value(redirect_fold_hist_dict))
+	task_redirect_afhob 	= mlvp.create_task(env.redirect_afhob_agent.set_redirect_afhob_value(redirect_afhob_dict))
+
+	await task_redirect_other 
+	await task_redirect_fold_hist
+	await task_redirect_afhob
+
+	await env.redirect_other_agent.bundle.step(10)
+
+
+	task_update_ftb_entry 	= mlvp.create_task(env.update_ftb_entry_agent.set_update_ftb_entry_value(update_pc,update_ftb_entry_dict)) 
+	task_update_other 		= mlvp.create_task(env.update_other_agent.set_update_other_value(update_pc,update_other_dict))
+	task_update_foldedHist 	= mlvp.create_task(env.update_fold_hist_agent.set_update_fold_hist_value(update_pc,update_fold_hist_dict))
+
+	await task_update_ftb_entry
+	await task_update_other
+	await task_update_foldedHist
+
+	####Second value
+	rediretc_ohter_dict = {
+		'level'					: 1,
+		'cfiUpdate_pc'			: 0x1480,
+		'cfiUpdate_pd_isRVC'	: 0,
+		'cfiUpdate_pd_isCall'	: 0,
+		'cfiUpdate_pd_isRet'	: 0,
+		'cfiUpdate_ssp'			: 0,
+		'cfiUpdate_sctr'		: 0,
+		'cfiUpdate_TOSW_flag'	: 0,
+		'cfiUpdate_TOSW_value'	: 0,
+		'cfiUpdate_TOSR_flag'	: 0,
+		'cfiUpdate_TOSR_value'	: 0,
+		'cfiUpdate_NOS_flag'	: 0,
+		'cfiUpdate_NOS_value'	: 0,
+
+		'cfiUpdate_lastBrNumOH'	: 1, 
+		'cfiUpdate_histPtr_flag': 1, 
+		'cfiUpdate_histPtr_value':0, 
+		'cfiUpdate_target'		: 0,
+		'cfiUpdate_taken'		: 0,
+		'cfiUpdate_shift'		: 1,
+		'cfiUpdate_addIntoHist'	: 1
+	}
+
+	redirect_fold_hist_dict = {
+		'cfiUpdate_folded_hist_0'	: 0b011,
+		'cfiUpdate_folded_hist_1'	: 0b011,
+		'cfiUpdate_folded_hist_2'	: 0b011,
+		'cfiUpdate_folded_hist_3'	: 0b011,
+		'cfiUpdate_folded_hist_4'	: 0b011,
+		'cfiUpdate_folded_hist_5'	: 0b011,
+		'cfiUpdate_folded_hist_6'	: 0b011,
+		'cfiUpdate_folded_hist_7'	: 0b011,
+		'cfiUpdate_folded_hist_8'	: 0b011,
+		'cfiUpdate_folded_hist_9'	: 0b011,
+
+		'cfiUpdate_folded_hist_10': 0b111,
+		'cfiUpdate_folded_hist_11': 0b111,
+		'cfiUpdate_folded_hist_12': 0b111,
+		'cfiUpdate_folded_hist_13': 0b111,
+		'cfiUpdate_folded_hist_14': 0b111,
+		'cfiUpdate_folded_hist_15': 0b111,
+		'cfiUpdate_folded_hist_16': 0b111,
+		'cfiUpdate_folded_hist_17': 0b111
+	}
+
+	redirect_afhob_dict = {
+		'afhob_0_bits_0'	: 0b0,
+		'afhob_0_bits_1'	: 0b0,
+		'afhob_0_bits_2'	: 0b0,
+		'afhob_0_bits_3'	: 0b0,
+		'afhob_1_bits_0'	: 0b0,
+		'afhob_1_bits_1'	: 0b0,
+		'afhob_1_bits_2'	: 0b0,
+		'afhob_1_bits_3'	: 0b0,
+		'afhob_2_bits_0'	: 0b0,
+		'afhob_2_bits_1'	: 0b0,
+		'afhob_2_bits_2'	: 0b0,
+		'afhob_2_bits_3'	: 0b0,
+		'afhob_3_bits_0'	: 0b0,
+		'afhob_3_bits_1'	: 0b0,
+		'afhob_3_bits_2'	: 0b0,
+		'afhob_3_bits_3'	: 0b0,
+		'afhob_4_bits_0'	: 0b0,
+		'afhob_4_bits_1'	: 0b0,
+		'afhob_4_bits_2'	: 0b0,
+		'afhob_5_bits_0'	: 0b0,
+		'afhob_5_bits_1'	: 0b0,
+		'afhob_5_bits_2'	: 0b0,
+		'afhob_5_bits_3'	: 0b0
+	}
+	update_ftb_entry_dict = {
+		'ftb_entry_valid'	: 1,
+		'tailSlot_valid'	: 1,
+		'tailSlot_tarStat'	: 0b11,
+		'tailSlot_sharing'	: 1,
+		'tailSlot_offset'	: 0b1111,
+		'tailSlot_lower'	: 0x22,
+		'pftAddr'			: 0b1111,
+		'may_be_rvi_call'	: 1,
+		'isRet'				: 1,
+		'isJalr'			: 1,
+		'isCall'			: 1,
+		'carry'				: 1,
+		'always_taken_0'	: 1,
+		'always_taken_1'	: 1,
+		'brSlots_0_valid'	: 1,
+		'brSlots_0_tarStat' : 0b10,
+		'brSlots_0_sharing'	: 1,
+		'brSlots_0_offset'	: 0b0100,
+		'brSlots_0_lower'	: 0x200
+	}
+
+	## update_other_signals
+	update_other_dict = {
+		'cfi_idx_valid'		: 1,
+		'cfi_idx_bits'		: 0b0111,
+		'br_taken_mask_0'	: 1,
+		'br_taken_mask_1'	: 0,
+		'jmp_taken'			: 0,
+		'mispred_mask_0'	: 0,
+		'mispred_mask_1'	: 0,
+		'mispred_mask_2'	: 0,
+		'old_entry'			: 0,
+		'meta'				: 0,
+		'full_target'		: 0
+	}
+
+	update_fold_hist_dict = {
+		'folded_hist_1' 	: 0b1000,
+		'folded_hist_2' 	: 0b1001,
+		'folded_hist_3' 	: 0b1010,
+		'folded_hist_4' 	: 0b1100,
+		'folded_hist_5' 	: 0b0001,
+		'folded_hist_6' 	: 0b0000,
+		'folded_hist_7' 	: 0b0001,
+		'folded_hist_8' 	: 0b0010,
+		'folded_hist_9' 	: 0b0100,
+		'folded_hist_10' 	: 0b1000,
+		'folded_hist_11' 	: 0b1100,
+		'folded_hist_12' 	: 0b1110,
+		'folded_hist_13' 	: 0b1111,
+		'folded_hist_14' 	: 0b0000,
+		'folded_hist_15' 	: 0b1111,
+		'folded_hist_16' 	: 0b1001,
+		'folded_hist_17' 	: 0b1001
+	}
+
+	task_redirect_other_1 	= mlvp.create_task(env.redirect_other_agent.set_redirect_other_value(rediretc_ohter_dict))
+	task_redirect_fold_hist_1 = mlvp.create_task(env.redirect_fold_hist_agent.set_redirect_fold_hist_value(redirect_fold_hist_dict))
+	task_redirect_afhob_1 	= mlvp.create_task(env.redirect_afhob_agent.set_redirect_afhob_value(redirect_afhob_dict))
+
+	await task_redirect_other_1 
+	await task_redirect_fold_hist_1
+	await task_redirect_afhob_1
+
+	await env.redirect_other_agent.bundle.step(10)
+
+	task_update_ftb_entry_1 	= mlvp.create_task(env.update_ftb_entry_agent.set_update_ftb_entry_value(update_pc,update_ftb_entry_dict)) 
+	task_update_other_1 		= mlvp.create_task(env.update_other_agent.set_update_other_value(update_pc,update_other_dict))
+	task_update_foldedHist_1 	= mlvp.create_task(env.update_fold_hist_agent.set_update_fold_hist_value(update_pc,update_fold_hist_dict))
+
+	await task_update_ftb_entry_1
+	await task_update_other_1
+	await task_update_foldedHist_1
+
+#	await env.redirect_afhob_agent.set_redirect_afhob_value()
+
+	enable_dict = {
+		'ubtb_en' 	: 1,	
+		'btb_en'	: 0,
+		'tage_en'	: 0,
+		'sc_en'		: 0,
+		'ras_en'	: 0
+	}
+
+	await env.sub_predi_ctrl_agent.set_sub_predic_ctrl_en(enable_dict)
+	await env.redirect_other_agent.bundle.step(20)	#for the Initial ram
+
+	####Third value
+	rediretc_ohter_dict = {
+		'level'					: 1,
+		'cfiUpdate_pc'			: 0x1480,
+		'cfiUpdate_pd_isRVC'	: 1,
+		'cfiUpdate_pd_isCall'	: 0,
+		'cfiUpdate_pd_isRet'	: 0,
+		'cfiUpdate_ssp'			: 0,
+		'cfiUpdate_sctr'		: 1,
+		'cfiUpdate_TOSW_flag'	: 0,
+		'cfiUpdate_TOSW_value'	: 1,
+		'cfiUpdate_TOSR_flag'	: 0,
+		'cfiUpdate_TOSR_value'	: 0,
+		'cfiUpdate_NOS_flag'	: 1,
+		'cfiUpdate_NOS_value'	: 0,
+
+		'cfiUpdate_lastBrNumOH'	: 1, 
+		'cfiUpdate_histPtr_flag': 1, 
+		'cfiUpdate_histPtr_value':0, 
+		'cfiUpdate_target'		: 1,
+		'cfiUpdate_taken'		: 0,
+		'cfiUpdate_shift'		: 1,
+		'cfiUpdate_addIntoHist'	: 1
+	}
+
+	redirect_fold_hist_dict = {
+		'cfiUpdate_folded_hist_0'	: 0b011,
+		'cfiUpdate_folded_hist_1'	: 0b011,
+		'cfiUpdate_folded_hist_2'	: 0b011,
+		'cfiUpdate_folded_hist_3'	: 0b011,
+		'cfiUpdate_folded_hist_4'	: 0b011,
+		'cfiUpdate_folded_hist_5'	: 0b011,
+		'cfiUpdate_folded_hist_6'	: 0b011,
+		'cfiUpdate_folded_hist_7'	: 0b011,
+		'cfiUpdate_folded_hist_8'	: 0b011,
+		'cfiUpdate_folded_hist_9'	: 0b011,
+
+		'cfiUpdate_folded_hist_10': 0b111,
+		'cfiUpdate_folded_hist_11': 0b111,
+		'cfiUpdate_folded_hist_12': 0b111,
+		'cfiUpdate_folded_hist_13': 0b111,
+		'cfiUpdate_folded_hist_14': 0b111,
+		'cfiUpdate_folded_hist_15': 0b111,
+		'cfiUpdate_folded_hist_16': 0b111,
+		'cfiUpdate_folded_hist_17': 0b111
+	}
+
+	redirect_afhob_dict = {
+		'afhob_0_bits_0'	: 0b1,
+		'afhob_0_bits_1'	: 0b1,
+		'afhob_0_bits_2'	: 0b1,
+		'afhob_0_bits_3'	: 0b1,
+		'afhob_1_bits_0'	: 0b1,
+		'afhob_1_bits_1'	: 0b1,
+		'afhob_1_bits_2'	: 0b1,
+		'afhob_1_bits_3'	: 0b1,
+		'afhob_2_bits_0'	: 0b1,
+		'afhob_2_bits_1'	: 0b1,
+		'afhob_2_bits_2'	: 0b1,
+		'afhob_2_bits_3'	: 0b1,
+		'afhob_3_bits_0'	: 0b1,
+		'afhob_3_bits_1'	: 0b1,
+		'afhob_3_bits_2'	: 0b1,
+		'afhob_3_bits_3'	: 0b1,
+		'afhob_4_bits_0'	: 0b1,
+		'afhob_4_bits_1'	: 0b1,
+		'afhob_4_bits_2'	: 0b1,
+		'afhob_5_bits_0'	: 0b1,
+		'afhob_5_bits_1'	: 0b1,
+		'afhob_5_bits_2'	: 0b1,
+		'afhob_5_bits_3'	: 0b1
+	}
+	update_ftb_entry_dict = {
+		'ftb_entry_valid'	: 1,
+		'tailSlot_valid'	: 1,
+		'tailSlot_tarStat'	: 0b11,
+		'tailSlot_sharing'	: 1,
+		'tailSlot_offset'	: 0b1111,
+		'tailSlot_lower'	: 0x22,
+		'pftAddr'			: 0b1111,
+		'may_be_rvi_call'	: 1,
+		'isRet'				: 1,
+		'isJalr'			: 1,
+		'isCall'			: 1,
+		'carry'				: 1,
+		'always_taken_0'	: 1,
+		'always_taken_1'	: 1,
+		'brSlots_0_valid'	: 1,
+		'brSlots_0_tarStat' : 0b10,
+		'brSlots_0_sharing'	: 1,
+		'brSlots_0_offset'	: 0b0100,
+		'brSlots_0_lower'	: 0x200
+	}
+
+	## update_other_signals
+	update_other_dict = {
+		'cfi_idx_valid'		: 1,
+		'cfi_idx_bits'		: 0b0111,
+		'br_taken_mask_0'	: 1,
+		'br_taken_mask_1'	: 0,
+		'jmp_taken'			: 0,
+		'mispred_mask_0'	: 0,
+		'mispred_mask_1'	: 0,
+		'mispred_mask_2'	: 0,
+		'old_entry'			: 0,
+		'meta'				: 0,
+		'full_target'		: 0
+	}
+
+	update_fold_hist_dict = {
+		'folded_hist_1' 	: 0b1000,
+		'folded_hist_2' 	: 0b1001,
+		'folded_hist_3' 	: 0b1010,
+		'folded_hist_4' 	: 0b1100,
+		'folded_hist_5' 	: 0b0001,
+		'folded_hist_6' 	: 0b0000,
+		'folded_hist_7' 	: 0b0001,
+		'folded_hist_8' 	: 0b0010,
+		'folded_hist_9' 	: 0b0100,
+		'folded_hist_10' 	: 0b1000,
+		'folded_hist_11' 	: 0b1100,
+		'folded_hist_12' 	: 0b1110,
+		'folded_hist_13' 	: 0b1111,
+		'folded_hist_14' 	: 0b0000,
+		'folded_hist_15' 	: 0b1111,
+		'folded_hist_16' 	: 0b1001,
+		'folded_hist_17' 	: 0b1001
+	}
+
+	task_redirect_other_1 	= mlvp.create_task(env.redirect_other_agent.set_redirect_other_value(rediretc_ohter_dict))
+	task_redirect_fold_hist_1 = mlvp.create_task(env.redirect_fold_hist_agent.set_redirect_fold_hist_value(redirect_fold_hist_dict))
+	task_redirect_afhob_1 	= mlvp.create_task(env.redirect_afhob_agent.set_redirect_afhob_value(redirect_afhob_dict))
+
+	await task_redirect_other_1 
+	await task_redirect_fold_hist_1
+	await task_redirect_afhob_1
+
+	await env.redirect_other_agent.bundle.step(10)
+
+	task_update_ftb_entry_1 	= mlvp.create_task(env.update_ftb_entry_agent.set_update_ftb_entry_value(update_pc,update_ftb_entry_dict)) 
+	task_update_other_1 		= mlvp.create_task(env.update_other_agent.set_update_other_value(update_pc,update_other_dict))
+	task_update_foldedHist_1 	= mlvp.create_task(env.update_fold_hist_agent.set_update_fold_hist_value(update_pc,update_fold_hist_dict))
+
+	await task_update_ftb_entry_1
+	await task_update_other_1
+	await task_update_foldedHist_1
+
+
+	await task_clock
+	print("test_normal_sanity IS OVER")
diff --git a/tests/bpu_top/tests/test_sub_predi_enable.py b/tests/bpu_top/tests/test_sub_predi_enable.py
new file mode 100644
index 0000000..52ed21c
--- /dev/null
+++ b/tests/bpu_top/tests/test_sub_predi_enable.py
@@ -0,0 +1,202 @@
+"""
+Initialize before the test
+"""
+import os
+
+ENV_PATH = os.path.dirname(os.path.abspath(__file__))+"/../"
+os.sys.path.append(ENV_PATH)
+from env.config import *
+
+os.sys.path.append(TESTS_PATH)
+os.sys.path.append(DUT_PATH)
+
+import mlvp
+from mlvp import PreRequest
+from UT_Predictor import *
+import random
+
+
+"""
+Testcase
+"""
+
+from env import *
+from env.bpu_bundle import *
+from env.bpu_agent import *
+from env.bpu_env import *
+
+import pytest
+
+
+#########################################py test###################
+def bpu_cover_point(dut:DUTPredictor ):
+	g = CovGroup("BPU Addition Function")
+	
+	return g
+
+
+@pytest.fixture()
+def mlvp_request(mlvp_pre_request: PreRequest):
+	mlvp.setup_logging(mlvp.INFO)
+	dut = mlvp_pre_request.create_dut(DUTPredictor,"clock")
+
+	sub_predi_ctrl_bundle 	= SubPrediCtrlBundle()
+	sub_predi_ctrl_bundle.bind(dut)
+	update_ftb_entry_bundle = Ftq2BpuUpdateFtbEntryBundle()
+	update_ftb_entry_bundle.bind(dut)
+	update_other_bundle	= Ftq2BpuUpdateOtherBundle()
+	update_other_bundle.bind(dut)
+	update_fold_hist_bundle 	= Ftq2BpuUpdateFoldHistBundle()
+	update_fold_hist_bundle.bind(dut)	
+	redirect_other_bundle = Ftq2BpuRedirectOtherBundle()
+	redirect_other_bundle.bind(dut)
+	redirect_hist_fold_bundle = Ftq2BpuRedirectFoldHistBundle()
+	redirect_hist_fold_bundle.bind(dut)
+	redirect_afhob_bundle = Ftq2BpuRedirectAfhobBundle()
+	redirect_afhob_bundle.bind(dut)	
+
+	def start_code():
+		mlvp.start_clock(dut)
+		return BpuEnv(sub_predi_ctrl_bundle, update_ftb_entry_bundle, update_other_bundle, 
+					update_fold_hist_bundle, redirect_other_bundle,redirect_hist_fold_bundle, 
+					redirect_afhob_bundle)	
+
+	return start_code
+
+"""
+pytest --mlvp-report
+"""
+@pytest.mark.mlvp_async
+async def test_sub_predi_all_enable_reset(mlvp_request):
+	print(mlvp_request)
+	env: BpuEnv = mlvp_request()
+
+	task_clock = mlvp.create_task(env.sub_predi_ctrl_agent.bundle.step(2200))
+	# reset for reset
+	await env.sub_predi_ctrl_agent.reset(2)
+	# set value
+	enable_dict = {
+		'ubtb_en' 	: 1,	
+		'btb_en'	: 1,
+		'tage_en'	: 1,
+		'sc_en'		: 1,
+		'ras_en'	: 1
+	}
+	print("begin exec env test")
+	await env.sub_predi_ctrl_agent.set_sub_predic_ctrl_en(enable_dict)
+	print("test_sub_predi_all_enable Is Over!!!!!!!!!!!!!!!!!!!!!!!")
+
+	await env.sub_predi_ctrl_agent.bundle.step(2100)
+	await env.sub_predi_ctrl_agent.reset(2)
+	await task_clock
+
+
+@pytest.mark.mlvp_async
+async def test_sub_predi_UFTB_disable(mlvp_request):
+	print(mlvp_request)
+	env: BpuEnv = mlvp_request()
+
+	task_clock = mlvp.create_task(env.sub_predi_ctrl_agent.bundle.step(2200))
+	# reset for reset
+	await env.sub_predi_ctrl_agent.reset(2)
+	# set value ==similar to ref 
+	enable_dict = {
+		'ubtb_en' 	: 0,	
+		'btb_en'	: 1,
+		'tage_en'	: 1,
+		'sc_en'		: 1,
+		'ras_en'	: 1
+	}
+	print("begin exec test")
+	await env.sub_predi_ctrl_agent.set_sub_predic_ctrl_en(enable_dict)
+
+	print("test_sub_predi_uftb_enable Is Over!!!!!!!!!!!!!!!!!!!!!!!")
+	await task_clock
+
+@pytest.mark.mlvp_async
+async def test_sub_predi_FTB_disable(mlvp_request):
+	print(mlvp_request)
+	env: BpuEnv = mlvp_request()
+
+	task_clock = mlvp.create_task(env.sub_predi_ctrl_agent.bundle.step(2200))
+	# reset for reset
+	await env.sub_predi_ctrl_agent.reset(2)
+	# set value ==similar to ref 
+
+	enable_dict = {
+		'ubtb_en' 	: 1,	
+		'btb_en'	: 0,
+		'tage_en'	: 1,
+		'sc_en'		: 1,
+		'ras_en'	: 1
+	}
+	await env.sub_predi_ctrl_agent.set_sub_predic_ctrl_en(enable_dict)
+
+	print("test_sub_predi_uftb_enable Is Over!!!!!!!!!!!!!!!!!!!!!!!")
+	await task_clock
+
+
+@pytest.mark.mlvp_async
+async def test_sub_predi_TAGE_disable(mlvp_request):
+	print(mlvp_request)
+	env: BpuEnv = mlvp_request()
+
+	task_clock = mlvp.create_task(env.sub_predi_ctrl_agent.bundle.step(2200))
+	# reset for reset
+	await env.sub_predi_ctrl_agent.reset(2)
+	# set value ==similar to ref 
+
+	enable_dict = {
+		'ubtb_en' 	: 1,	
+		'btb_en'	: 1,
+		'tage_en'	: 0,
+		'sc_en'		: 1,
+		'ras_en'	: 1
+	}
+	await env.sub_predi_ctrl_agent.set_sub_predic_ctrl_en(enable_dict)
+
+	print("test_sub_predi_uftb_enable Is Over!!!!!!!!!!!!!!!!!!!!!!!")
+	await task_clock
+
+@pytest.mark.mlvp_async
+async def test_sub_predi_SC_disable(mlvp_request):
+	print(mlvp_request)
+	env: BpuEnv = mlvp_request()
+
+	task_clock = mlvp.create_task(env.sub_predi_ctrl_agent.bundle.step(2200))
+	# reset for reset
+	await env.sub_predi_ctrl_agent.reset(2)
+	# set value ==similar to ref 
+
+	enable_dict = {
+		'ubtb_en' 	: 1,	
+		'btb_en'	: 1,
+		'tage_en'	: 1,
+		'sc_en'		: 0,
+		'ras_en'	: 1
+	}
+	await env.sub_predi_ctrl_agent.set_sub_predic_ctrl_en(enable_dict)
+
+	print("test_sub_predi_uftb_enable Is Over!!!!!!!!!!!!!!!!!!!!!!!")
+	await task_clock
+
+@pytest.mark.mlvp_async
+async def test_sub_predi_RAS_disable(mlvp_request):
+	print(mlvp_request)
+	env: BpuEnv = mlvp_request()
+
+	task_clock = mlvp.create_task(env.sub_predi_ctrl_agent.bundle.step(2200))
+	# reset for reset
+	await env.sub_predi_ctrl_agent.reset(2)
+	# set value ==similar to ref 
+
+	enable_dict = {
+		'ubtb_en' 	: 1,	
+		'btb_en'	: 1,
+		'tage_en'	: 1,
+		'sc_en'		: 1,
+		'ras_en'	: 0
+	}
+	await env.sub_predi_ctrl_agent.set_sub_predic_ctrl_en(enable_dict)
+	print("test_sub_predi_uftb_enable Is Over!!!!!!!!!!!!!!!!!!!!!!!")
+	await task_clock
\ No newline at end of file
diff --git a/tests/bpu_top/tests/test_update_signals.py b/tests/bpu_top/tests/test_update_signals.py
new file mode 100644
index 0000000..c7621b8
--- /dev/null
+++ b/tests/bpu_top/tests/test_update_signals.py
@@ -0,0 +1,1247 @@
+"""
+Initialize before the test
+"""
+import os
+ENV_PATH = os.path.dirname(os.path.abspath(__file__))+"/../"
+os.sys.path.append(ENV_PATH)
+from env.config import *
+
+os.sys.path.append(TESTS_PATH)
+os.sys.path.append(DUT_PATH)
+
+import mlvp
+from mlvp import PreRequest
+from UT_Predictor import *
+import random
+
+"""
+Testcase
+"""
+
+from env import *
+from env.bpu_bundle import *
+from env.bpu_agent import *
+from env.bpu_env import *
+
+import pytest
+
+#########################################py test###################
+def bpu_cover_point(dut:DUTPredictor ):
+	g = CovGroup("BPU Addition Function")
+	
+	return g
+
+
+@pytest.fixture()
+def mlvp_request(mlvp_pre_request: PreRequest):
+	mlvp.setup_logging(mlvp.INFO)
+	dut = mlvp_pre_request.create_dut(DUTPredictor,"clock")
+
+	sub_predi_ctrl_bundle 	= SubPrediCtrlBundle()
+	sub_predi_ctrl_bundle.bind(dut)
+	update_ftb_entry_bundle = Ftq2BpuUpdateFtbEntryBundle()
+	update_ftb_entry_bundle.bind(dut)
+	update_other_bundle	= Ftq2BpuUpdateOtherBundle()
+	update_other_bundle.bind(dut)
+	update_fold_hist_bundle 	= Ftq2BpuUpdateFoldHistBundle()
+	update_fold_hist_bundle.bind(dut)	
+	redirect_other_bundle = Ftq2BpuRedirectOtherBundle()
+	redirect_other_bundle.bind(dut)
+	redirect_hist_fold_bundle = Ftq2BpuRedirectFoldHistBundle()
+	redirect_hist_fold_bundle.bind(dut)
+	redirect_afhob_bundle = Ftq2BpuRedirectAfhobBundle()
+	redirect_afhob_bundle.bind(dut)	
+
+	def start_code():
+		mlvp.start_clock(dut)
+		return BpuEnv(sub_predi_ctrl_bundle, update_ftb_entry_bundle, update_other_bundle, 
+					update_fold_hist_bundle, redirect_other_bundle,redirect_hist_fold_bundle, 
+					redirect_afhob_bundle)	
+
+	return start_code
+
+
+###########################################################################################################
+###########################################test_update#####################################################
+###########################################################################################################
+"""
+Way-2: pytest
+"""
+@pytest.mark.mlvp_async
+async def test_update_signals_sanity(mlvp_request):
+	print(mlvp_request)
+	env: BpuEnv = mlvp_request()
+	update_pc = 0x1248
+
+	# rese
+	task_clock = mlvp.create_task(env.update_ftb_entry_agent.bundle.step(2200))
+	await env.update_ftb_entry_agent.reset(4)
+	await env.update_ftb_entry_agent.bundle.step(2100)
+	# set value
+	print("begin exec test_update_signals_sanity test")
+
+	update_ftb_entry_dict = {
+		'ftb_entry_valid'	: 1,
+		'tailSlot_valid'	: 1,
+		'tailSlot_tarStat'	: 0b10,
+		'tailSlot_sharing'	: 1,
+		'tailSlot_offset'	: 0b0100,
+		'tailSlot_lower'	: 0x20,
+		'pftAddr'			: 0b1000,
+		'may_be_rvi_call'	: 1,
+		'isRet'				: 1,
+		'isJalr'			: 1,
+		'isCall'			: 1,
+		'carry'				: 1,
+		'always_taken_0'	: 1,
+		'always_taken_1'	: 1,
+		'brSlots_0_valid'	: 1,
+		'brSlots_0_tarStat' : 0b10,
+		'brSlots_0_sharing'	: 1,
+		'brSlots_0_offset'	: 0b0100,
+		'brSlots_0_lower'	: 0x200
+	}
+	## update_other_signals
+	update_other_dict = {
+		'cfi_idx_valid'		: 1,
+		'cfi_idx_bits'		: 0b1000,
+		'br_taken_mask_0'	: 1,
+		'br_taken_mask_1'	: 1,
+		'jmp_taken'			: 1,
+		'mispred_mask_0'	: 1,
+		'mispred_mask_1'	: 1,
+		'mispred_mask_2'	: 1,
+		'old_entry'			: 1,
+		'meta'				: 1,
+		'full_target'		: 1
+	}
+	## This is Serial exec
+#	await env.update_ftb_entry_agent.set_update_ftb_entry_value(update_ftb_entry_dict)
+#	await env.update_other_agent.set_update_other_value(update_other_dict)
+
+	## This is Parrel exec
+	task_update_ftb_entry 	= mlvp.create_task(env.update_ftb_entry_agent.set_update_ftb_entry_value(update_pc,update_ftb_entry_dict)) 
+	task_update_other 		= mlvp.create_task(env.update_other_agent.set_update_other_value(update_pc,update_other_dict))
+
+	await task_update_ftb_entry
+	await task_update_other
+
+	await task_clock
+	print("test_update_signals_sanity IS OVER")
+
+
+@pytest.mark.mlvp_async
+async def test_update_fold_hist_sanity(mlvp_request):
+	print(mlvp_request)
+	env: BpuEnv = mlvp_request()
+	update_pc = 0x1248
+
+	# rese
+	task_clock = mlvp.create_task(env.update_ftb_entry_agent.bundle.step(2200))
+	await env.update_ftb_entry_agent.reset(4)
+	await env.update_ftb_entry_agent.bundle.step(2100)
+	print("begin exec test_update_fold_hist_sanity test")
+
+	update_fold_hist_dict = {
+		'folded_hist_1' 	: 0b1000,
+		'folded_hist_2' 	: 0b1001,
+		'folded_hist_3' 	: 0b1010,
+		'folded_hist_4' 	: 0b1100,
+		'folded_hist_5' 	: 0b0001,
+		'folded_hist_6' 	: 0b0000,
+		'folded_hist_7' 	: 0b0001,
+		'folded_hist_8' 	: 0b0010,
+		'folded_hist_9' 	: 0b0100,
+		'folded_hist_10' 	: 0b1000,
+		'folded_hist_11' 	: 0b1100,
+		'folded_hist_12' 	: 0b1110,
+		'folded_hist_13' 	: 0b1111,
+		'folded_hist_14' 	: 0b0000,
+		'folded_hist_15' 	: 0b1111,
+		'folded_hist_16' 	: 0b1001,
+		'folded_hist_17' 	: 0b1001
+	}
+	await env.update_fold_hist_agent.set_update_fold_hist_value(update_pc,update_fold_hist_dict)
+
+	await task_clock
+	print("test_update_signals_sanity IS OVER")
+
+
+@pytest.mark.mlvp_async
+async def test_update_FtbEntry_foldHist_once_signals(mlvp_request):
+	print(mlvp_request)
+	env: BpuEnv = mlvp_request()
+	update_pc = 0x1248
+
+	# rese
+	task_clock = mlvp.create_task(env.update_ftb_entry_agent.bundle.step(2200))
+	await env.update_ftb_entry_agent.reset(4)
+	await env.update_ftb_entry_agent.bundle.step(2100)
+	print("begin exec test_update_fold_hist_sanity test")
+
+	update_ftb_entry_dict = {
+		'ftb_entry_valid'	: 1,
+		'tailSlot_valid'	: 1,
+		'tailSlot_tarStat'	: 0b10,
+		'tailSlot_sharing'	: 1,
+		'tailSlot_offset'	: 0b0100,
+		'tailSlot_lower'	: 0x20,
+		'pftAddr'			: 0b1000,
+		'may_be_rvi_call'	: 1,
+		'isRet'				: 1,
+		'isJalr'			: 1,
+		'isCall'			: 1,
+		'carry'				: 1,
+		'always_taken_0'	: 1,
+		'always_taken_1'	: 1,
+		'brSlots_0_valid'	: 1,
+		'brSlots_0_tarStat' : 0b10,
+		'brSlots_0_sharing'	: 1,
+		'brSlots_0_offset'	: 0b0100,
+		'brSlots_0_lower'	: 0x200
+	}
+	## update_other_signals
+	update_other_dict = {
+		'cfi_idx_valid'		: 1,
+		'cfi_idx_bits'		: 0b1000,
+		'br_taken_mask_0'	: 1,
+		'br_taken_mask_1'	: 1,
+		'jmp_taken'			: 1,
+		'mispred_mask_0'	: 1,
+		'mispred_mask_1'	: 1,
+		'mispred_mask_2'	: 1,
+		'old_entry'			: 1,
+		'meta'				: 1,
+		'full_target'		: 1
+	}
+
+	update_fold_hist_dict = {
+		'folded_hist_1' 	: 0b1000,
+		'folded_hist_2' 	: 0b1001,
+		'folded_hist_3' 	: 0b1010,
+		'folded_hist_4' 	: 0b1100,
+		'folded_hist_5' 	: 0b0001,
+		'folded_hist_6' 	: 0b0000,
+		'folded_hist_7' 	: 0b0001,
+		'folded_hist_8' 	: 0b0010,
+		'folded_hist_9' 	: 0b0100,
+		'folded_hist_10' 	: 0b1000,
+		'folded_hist_11' 	: 0b1100,
+		'folded_hist_12' 	: 0b1110,
+		'folded_hist_13' 	: 0b1111,
+		'folded_hist_14' 	: 0b0000,
+		'folded_hist_15' 	: 0b1111,
+		'folded_hist_16' 	: 0b1001,
+		'folded_hist_17' 	: 0b1001
+	}
+
+	task_update_ftb_entry 	= mlvp.create_task(env.update_ftb_entry_agent.set_update_ftb_entry_value(update_pc,update_ftb_entry_dict)) 
+	task_update_other 		= mlvp.create_task(env.update_other_agent.set_update_other_value(update_pc,update_other_dict))
+	task_update_foldedHist 	= mlvp.create_task(env.update_fold_hist_agent.set_update_fold_hist_value(update_pc,update_fold_hist_dict))
+
+	await task_update_ftb_entry
+	await task_update_other
+	await task_update_foldedHist
+
+	await task_clock
+	print("test_update_signals_sanity IS OVER")
+
+
+@pytest.mark.mlvp_async
+async def test_update_FtbEntry_foldHist_twice_signals(mlvp_request):
+	print(mlvp_request)
+	env: BpuEnv = mlvp_request()
+	update_pc = 0x1248
+
+	# rese
+	task_clock = mlvp.create_task(env.update_ftb_entry_agent.bundle.step(2200))
+	await env.update_ftb_entry_agent.reset(4)
+	await env.update_ftb_entry_agent.bundle.step(2100)
+	print("begin exec test_update_fold_hist_sanity test")
+
+	update_ftb_entry_dict = {
+		'ftb_entry_valid'	: 1,
+		'tailSlot_valid'	: 1,
+		'tailSlot_tarStat'	: 0b10,
+		'tailSlot_sharing'	: 1,
+		'tailSlot_offset'	: 0b0100,
+		'tailSlot_lower'	: 0x20,
+		'pftAddr'			: 0b1000,
+		'may_be_rvi_call'	: 1,
+		'isRet'				: 1,
+		'isJalr'			: 1,
+		'isCall'			: 1,
+		'carry'				: 1,
+		'always_taken_0'	: 1,
+		'always_taken_1'	: 1,
+		'brSlots_0_valid'	: 1,
+		'brSlots_0_tarStat' : 0b10,
+		'brSlots_0_sharing'	: 1,
+		'brSlots_0_offset'	: 0b0100,
+		'brSlots_0_lower'	: 0x200
+	}
+	## update_other_signals
+	update_other_dict = {
+		'cfi_idx_valid'		: 1,
+		'cfi_idx_bits'		: 0b1000,
+		'br_taken_mask_0'	: 1,
+		'br_taken_mask_1'	: 1,
+		'jmp_taken'			: 0,
+		'mispred_mask_0'	: 1,
+		'mispred_mask_1'	: 1,
+		'mispred_mask_2'	: 1,
+		'old_entry'			: 1,
+		'meta'				: 1,
+		'full_target'		: 1
+	}
+
+	update_fold_hist_dict = {
+		'folded_hist_1' 	: 0b1000,
+		'folded_hist_2' 	: 0b1001,
+		'folded_hist_3' 	: 0b1010,
+		'folded_hist_4' 	: 0b1100,
+		'folded_hist_5' 	: 0b0001,
+		'folded_hist_6' 	: 0b0000,
+		'folded_hist_7' 	: 0b0001,
+		'folded_hist_8' 	: 0b0010,
+		'folded_hist_9' 	: 0b0100,
+		'folded_hist_10' 	: 0b1000,
+		'folded_hist_11' 	: 0b1100,
+		'folded_hist_12' 	: 0b1110,
+		'folded_hist_13' 	: 0b1111,
+		'folded_hist_14' 	: 0b0000,
+		'folded_hist_15' 	: 0b1111,
+		'folded_hist_16' 	: 0b1001,
+		'folded_hist_17' 	: 0b1001
+	}
+
+	task_update_ftb_entry 	= mlvp.create_task(env.update_ftb_entry_agent.set_update_ftb_entry_value(update_pc,update_ftb_entry_dict)) 
+	task_update_other 		= mlvp.create_task(env.update_other_agent.set_update_other_value(update_pc,update_other_dict))
+	task_update_foldedHist 	= mlvp.create_task(env.update_fold_hist_agent.set_update_fold_hist_value(update_pc,update_fold_hist_dict))
+
+	await task_update_ftb_entry
+	await task_update_other
+	await task_update_foldedHist
+
+	await env.update_ftb_entry_agent.bundle.step(1)
+
+	update_ftb_entry_dict = {
+		'ftb_entry_valid'	: 1,
+		'tailSlot_valid'	: 1,
+		'tailSlot_tarStat'	: 0b11,
+		'tailSlot_sharing'	: 1,
+		'tailSlot_offset'	: 0b1111,
+		'tailSlot_lower'	: 0x22,
+		'pftAddr'			: 0b1111,
+		'may_be_rvi_call'	: 1,
+		'isRet'				: 1,
+		'isJalr'			: 1,
+		'isCall'			: 1,
+		'carry'				: 1,
+		'always_taken_0'	: 1,
+		'always_taken_1'	: 1,
+		'brSlots_0_valid'	: 1,
+		'brSlots_0_tarStat' : 0b10,
+		'brSlots_0_sharing'	: 1,
+		'brSlots_0_offset'	: 0b0100,
+		'brSlots_0_lower'	: 0x200
+	}
+
+	## update_other_signals
+	update_other_dict = {
+		'cfi_idx_valid'		: 1,
+		'cfi_idx_bits'		: 0b0111,
+		'br_taken_mask_0'	: 1,
+		'br_taken_mask_1'	: 0,
+		'jmp_taken'			: 1,
+		'mispred_mask_0'	: 1,
+		'mispred_mask_1'	: 1,
+		'mispred_mask_2'	: 1,
+		'old_entry'			: 1,
+		'meta'				: 1,
+		'full_target'		: 1
+	}
+
+	update_fold_hist_dict = {
+		'folded_hist_1' 	: 0b1000,
+		'folded_hist_2' 	: 0b1001,
+		'folded_hist_3' 	: 0b1010,
+		'folded_hist_4' 	: 0b1100,
+		'folded_hist_5' 	: 0b0001,
+		'folded_hist_6' 	: 0b0000,
+		'folded_hist_7' 	: 0b0001,
+		'folded_hist_8' 	: 0b0010,
+		'folded_hist_9' 	: 0b0100,
+		'folded_hist_10' 	: 0b1000,
+		'folded_hist_11' 	: 0b1100,
+		'folded_hist_12' 	: 0b1110,
+		'folded_hist_13' 	: 0b1111,
+		'folded_hist_14' 	: 0b0000,
+		'folded_hist_15' 	: 0b1111,
+		'folded_hist_16' 	: 0b1001,
+		'folded_hist_17' 	: 0b1001
+	}
+
+	task_update_ftb_entry_1		= mlvp.create_task(env.update_ftb_entry_agent.set_update_ftb_entry_value(update_pc,update_ftb_entry_dict)) 
+	task_update_other_1 		= mlvp.create_task(env.update_other_agent.set_update_other_value(update_pc,update_other_dict))
+	task_update_foldedHist_1 	= mlvp.create_task(env.update_fold_hist_agent.set_update_fold_hist_value(update_pc,update_fold_hist_dict))
+
+	await task_update_ftb_entry_1
+	await task_update_other_1
+	await task_update_foldedHist_1
+
+	await task_clock
+	print("test_update_signals_sanity IS OVER")
+
+
+@pytest.mark.mlvp_async
+async def test_update_FtbEntry_foldHist_signals_1(mlvp_request):
+	print(mlvp_request)
+	env: BpuEnv = mlvp_request()
+	update_pc = 0x1248
+
+	# rese
+	task_clock = mlvp.create_task(env.update_ftb_entry_agent.bundle.step(2200))
+	await env.update_ftb_entry_agent.reset(4)
+	await env.update_ftb_entry_agent.bundle.step(2100)
+	print("begin exec test_update_fold_hist_sanity test")
+
+	update_ftb_entry_dict = {
+		'ftb_entry_valid'	: 1,
+		'tailSlot_valid'	: 1,
+		'tailSlot_tarStat'	: 0b11,
+		'tailSlot_sharing'	: 1,
+		'tailSlot_offset'	: 0b1111,
+		'tailSlot_lower'	: 0x21,
+		'pftAddr'			: 0b1110,
+		'may_be_rvi_call'	: 0,
+		'isRet'				: 0,
+		'isJalr'			: 0,
+		'isCall'			: 0,
+		'carry'				: 0,
+		'always_taken_0'	: 0,
+		'always_taken_1'	: 0,
+		'brSlots_0_valid'	: 0,
+		'brSlots_0_tarStat' : 0b00,
+		'brSlots_0_sharing'	: 0,
+		'brSlots_0_offset'	: 0b0000,
+		'brSlots_0_lower'	: 0x000
+	}
+	## update_other_signals
+	update_other_dict = {
+		'cfi_idx_valid'		: 1,
+		'cfi_idx_bits'		: 0b1000,
+		'br_taken_mask_0'	: 1,
+		'br_taken_mask_1'	: 1,
+		'jmp_taken'			: 0,
+		'mispred_mask_0'	: 0,
+		'mispred_mask_1'	: 0,
+		'mispred_mask_2'	: 0,
+		'old_entry'			: 0,
+		'meta'				: 0,
+		'full_target'		: 0
+	}
+
+	update_fold_hist_dict = {
+		'folded_hist_1' 	: 0b1000,
+		'folded_hist_2' 	: 0b1001,
+		'folded_hist_3' 	: 0b1010,
+		'folded_hist_4' 	: 0b1100,
+		'folded_hist_5' 	: 0b0001,
+		'folded_hist_6' 	: 0b0000,
+		'folded_hist_7' 	: 0b0001,
+		'folded_hist_8' 	: 0b0010,
+		'folded_hist_9' 	: 0b0100,
+		'folded_hist_10' 	: 0b1000,
+		'folded_hist_11' 	: 0b1100,
+		'folded_hist_12' 	: 0b1110,
+		'folded_hist_13' 	: 0b1111,
+		'folded_hist_14' 	: 0b0000,
+		'folded_hist_15' 	: 0b1111,
+		'folded_hist_16' 	: 0b1001,
+		'folded_hist_17' 	: 0b1001
+	}
+
+	task_update_ftb_entry 	= mlvp.create_task(env.update_ftb_entry_agent.set_update_ftb_entry_value(update_pc,update_ftb_entry_dict)) 
+	task_update_other 		= mlvp.create_task(env.update_other_agent.set_update_other_value(update_pc,update_other_dict))
+	task_update_foldedHist 	= mlvp.create_task(env.update_fold_hist_agent.set_update_fold_hist_value(update_pc,update_fold_hist_dict))
+
+	await task_update_ftb_entry
+	await task_update_other
+	await task_update_foldedHist
+
+	await env.update_ftb_entry_agent.bundle.step(1)
+
+	update_ftb_entry_dict = {
+		'ftb_entry_valid'	: 1,
+		'tailSlot_valid'	: 1,
+		'tailSlot_tarStat'	: 0b11,
+		'tailSlot_sharing'	: 1,
+		'tailSlot_offset'	: 0b1111,
+		'tailSlot_lower'	: 0x22,
+		'pftAddr'			: 0b1111,
+		'may_be_rvi_call'	: 1,
+		'isRet'				: 1,
+		'isJalr'			: 1,
+		'isCall'			: 1,
+		'carry'				: 1,
+		'always_taken_0'	: 1,
+		'always_taken_1'	: 1,
+		'brSlots_0_valid'	: 1,
+		'brSlots_0_tarStat' : 0b10,
+		'brSlots_0_sharing'	: 1,
+		'brSlots_0_offset'	: 0b0100,
+		'brSlots_0_lower'	: 0x200
+	}
+
+	## update_other_signals
+	update_other_dict = {
+		'cfi_idx_valid'		: 1,
+		'cfi_idx_bits'		: 0b0111,
+		'br_taken_mask_0'	: 1,
+		'br_taken_mask_1'	: 0,
+		'jmp_taken'			: 1,
+		'mispred_mask_0'	: 1,
+		'mispred_mask_1'	: 1,
+		'mispred_mask_2'	: 1,
+		'old_entry'			: 1,
+		'meta'				: 1,
+		'full_target'		: 1
+	}
+
+	update_fold_hist_dict = {
+		'folded_hist_1' 	: 0b1000,
+		'folded_hist_2' 	: 0b1001,
+		'folded_hist_3' 	: 0b1010,
+		'folded_hist_4' 	: 0b1100,
+		'folded_hist_5' 	: 0b0001,
+		'folded_hist_6' 	: 0b0000,
+		'folded_hist_7' 	: 0b0001,
+		'folded_hist_8' 	: 0b0010,
+		'folded_hist_9' 	: 0b0100,
+		'folded_hist_10' 	: 0b1000,
+		'folded_hist_11' 	: 0b1100,
+		'folded_hist_12' 	: 0b1110,
+		'folded_hist_13' 	: 0b1111,
+		'folded_hist_14' 	: 0b0000,
+		'folded_hist_15' 	: 0b1111,
+		'folded_hist_16' 	: 0b1001,
+		'folded_hist_17' 	: 0b1001
+	}
+
+	task_update_ftb_entry_1		= mlvp.create_task(env.update_ftb_entry_agent.set_update_ftb_entry_value(update_pc,update_ftb_entry_dict)) 
+	task_update_other_1 		= mlvp.create_task(env.update_other_agent.set_update_other_value(update_pc,update_other_dict))
+	task_update_foldedHist_1 	= mlvp.create_task(env.update_fold_hist_agent.set_update_fold_hist_value(update_pc,update_fold_hist_dict))
+
+	await task_update_ftb_entry_1
+	await task_update_other_1
+	await task_update_foldedHist_1
+
+	await task_clock
+	print("test_update_signals_sanity IS OVER")
+
+
+@pytest.mark.mlvp_async
+async def test_update_FtbEntry_foldHist_signals_2(mlvp_request):
+	print(mlvp_request)
+	env: BpuEnv = mlvp_request()
+	update_pc = 0x1248
+
+	enable_dict = {
+		'ubtb_en' 	: 1,	
+		'btb_en'	: 1,
+		'tage_en'	: 1,
+		'sc_en'		: 1,
+		'ras_en'	: 1
+	}
+
+	# rese
+	task_clock = mlvp.create_task(env.update_ftb_entry_agent.bundle.step(2200))
+	await env.update_ftb_entry_agent.reset(4)
+	await env.sub_predi_ctrl_agent.set_sub_predic_ctrl_en(enable_dict)
+	await env.update_ftb_entry_agent.bundle.step(2100)
+	print("begin exec test_update_fold_hist_sanity test")
+
+	update_ftb_entry_dict = {
+		'ftb_entry_valid'	: 1,
+		'tailSlot_valid'	: 1,
+		'tailSlot_tarStat'	: 0b11,
+		'tailSlot_sharing'	: 1,
+		'tailSlot_offset'	: 0b1111,
+		'tailSlot_lower'	: 0x21,
+		'pftAddr'			: 0b1110,
+		'may_be_rvi_call'	: 0,
+		'isRet'				: 0,
+		'isJalr'			: 0,
+		'isCall'			: 0,
+		'carry'				: 0,
+		'always_taken_0'	: 0,
+		'always_taken_1'	: 0,
+		'brSlots_0_valid'	: 0,
+		'brSlots_0_tarStat' : 0b00,
+		'brSlots_0_sharing'	: 0,
+		'brSlots_0_offset'	: 0b0000,
+		'brSlots_0_lower'	: 0x000
+	}
+	## update_other_signals
+	update_other_dict = {
+		'cfi_idx_valid'		: 1,
+		'cfi_idx_bits'		: 0b1000,
+		'br_taken_mask_0'	: 1,
+		'br_taken_mask_1'	: 1,
+		'jmp_taken'			: 0,
+		'mispred_mask_0'	: 0,
+		'mispred_mask_1'	: 0,
+		'mispred_mask_2'	: 0,
+		'old_entry'			: 0,
+		'meta'				: 0,
+		'full_target'		: 0
+	}
+
+	update_fold_hist_dict = {
+		'folded_hist_1' 	: 0b1000,
+		'folded_hist_2' 	: 0b1001,
+		'folded_hist_3' 	: 0b1010,
+		'folded_hist_4' 	: 0b1100,
+		'folded_hist_5' 	: 0b0001,
+		'folded_hist_6' 	: 0b0000,
+		'folded_hist_7' 	: 0b0001,
+		'folded_hist_8' 	: 0b0010,
+		'folded_hist_9' 	: 0b0100,
+		'folded_hist_10' 	: 0b1000,
+		'folded_hist_11' 	: 0b1100,
+		'folded_hist_12' 	: 0b1110,
+		'folded_hist_13' 	: 0b1111,
+		'folded_hist_14' 	: 0b0000,
+		'folded_hist_15' 	: 0b1111,
+		'folded_hist_16' 	: 0b1001,
+		'folded_hist_17' 	: 0b1001
+	}
+
+	task_update_ftb_entry 	= mlvp.create_task(env.update_ftb_entry_agent.set_update_ftb_entry_value(update_pc,update_ftb_entry_dict)) 
+	task_update_other 		= mlvp.create_task(env.update_other_agent.set_update_other_value(update_pc,update_other_dict))
+	task_update_foldedHist 	= mlvp.create_task(env.update_fold_hist_agent.set_update_fold_hist_value(update_pc,update_fold_hist_dict))
+
+	await task_update_ftb_entry
+	await task_update_other
+	await task_update_foldedHist
+
+	await env.update_ftb_entry_agent.bundle.step(1)
+
+	update_ftb_entry_dict = {
+		'ftb_entry_valid'	: 1,
+		'tailSlot_valid'	: 1,
+		'tailSlot_tarStat'	: 0b11,
+		'tailSlot_sharing'	: 1,
+		'tailSlot_offset'	: 0b1111,
+		'tailSlot_lower'	: 0x22,
+		'pftAddr'			: 0b1111,
+		'may_be_rvi_call'	: 1,
+		'isRet'				: 1,
+		'isJalr'			: 1,
+		'isCall'			: 1,
+		'carry'				: 1,
+		'always_taken_0'	: 1,
+		'always_taken_1'	: 1,
+		'brSlots_0_valid'	: 1,
+		'brSlots_0_tarStat' : 0b10,
+		'brSlots_0_sharing'	: 1,
+		'brSlots_0_offset'	: 0b0100,
+		'brSlots_0_lower'	: 0x200
+	}
+
+	## update_other_signals
+	update_other_dict = {
+		'cfi_idx_valid'		: 1,
+		'cfi_idx_bits'		: 0b0111,
+		'br_taken_mask_0'	: 1,
+		'br_taken_mask_1'	: 0,
+		'jmp_taken'			: 1,
+		'mispred_mask_0'	: 1,
+		'mispred_mask_1'	: 1,
+		'mispred_mask_2'	: 1,
+		'old_entry'			: 1,
+		'meta'				: 1,
+		'full_target'		: 1
+	}
+
+	update_fold_hist_dict = {
+		'folded_hist_1' 	: 0b1000,
+		'folded_hist_2' 	: 0b1001,
+		'folded_hist_3' 	: 0b1010,
+		'folded_hist_4' 	: 0b1100,
+		'folded_hist_5' 	: 0b0001,
+		'folded_hist_6' 	: 0b0000,
+		'folded_hist_7' 	: 0b0001,
+		'folded_hist_8' 	: 0b0010,
+		'folded_hist_9' 	: 0b0100,
+		'folded_hist_10' 	: 0b1000,
+		'folded_hist_11' 	: 0b1100,
+		'folded_hist_12' 	: 0b1110,
+		'folded_hist_13' 	: 0b1111,
+		'folded_hist_14' 	: 0b0000,
+		'folded_hist_15' 	: 0b1111,
+		'folded_hist_16' 	: 0b1001,
+		'folded_hist_17' 	: 0b1001
+	}
+
+	task_update_ftb_entry_1		= mlvp.create_task(env.update_ftb_entry_agent.set_update_ftb_entry_value(update_pc,update_ftb_entry_dict)) 
+	task_update_other_1 		= mlvp.create_task(env.update_other_agent.set_update_other_value(update_pc,update_other_dict))
+	task_update_foldedHist_1 	= mlvp.create_task(env.update_fold_hist_agent.set_update_fold_hist_value(update_pc,update_fold_hist_dict))
+
+	await task_update_ftb_entry_1
+	await task_update_other_1
+	await task_update_foldedHist_1
+
+	await task_clock
+	print("test_update_signals_sanity IS OVER")
+
+
+@pytest.mark.mlvp_async
+async def test_update_FtbEntry_foldHist_signals_3(mlvp_request):
+	print(mlvp_request)
+	env: BpuEnv = mlvp_request()
+	update_pc = 0x1248
+
+	enable_dict = {
+		'ubtb_en' 	: 1,	
+		'btb_en'	: 0,
+		'tage_en'	: 0,
+		'sc_en'		: 0,
+		'ras_en'	: 0
+	}
+
+	# rese
+	task_clock = mlvp.create_task(env.update_ftb_entry_agent.bundle.step(2200))
+	await env.update_ftb_entry_agent.reset(4)
+	await env.sub_predi_ctrl_agent.set_sub_predic_ctrl_en(enable_dict)
+	await env.update_ftb_entry_agent.bundle.step(2100)
+	print("begin exec test_update_fold_hist_sanity test")
+
+	update_ftb_entry_dict = {
+		'ftb_entry_valid'	: 1,
+		'tailSlot_valid'	: 1,
+		'tailSlot_tarStat'	: 0b11,
+		'tailSlot_sharing'	: 1,
+		'tailSlot_offset'	: 0b1111,
+		'tailSlot_lower'	: 0x21,
+		'pftAddr'			: 0b1110,
+		'may_be_rvi_call'	: 0,
+		'isRet'				: 0,
+		'isJalr'			: 0,
+		'isCall'			: 0,
+		'carry'				: 0,
+		'always_taken_0'	: 0,
+		'always_taken_1'	: 0,
+		'brSlots_0_valid'	: 0,
+		'brSlots_0_tarStat' : 0b00,
+		'brSlots_0_sharing'	: 0,
+		'brSlots_0_offset'	: 0b0000,
+		'brSlots_0_lower'	: 0x000
+	}
+	## update_other_signals
+	update_other_dict = {
+		'cfi_idx_valid'		: 1,
+		'cfi_idx_bits'		: 0b1000,
+		'br_taken_mask_0'	: 1,
+		'br_taken_mask_1'	: 1,
+		'jmp_taken'			: 0,
+		'mispred_mask_0'	: 0,
+		'mispred_mask_1'	: 0,
+		'mispred_mask_2'	: 0,
+		'old_entry'			: 0,
+		'meta'				: 0,
+		'full_target'		: 0
+	}
+
+	update_fold_hist_dict = {
+		'folded_hist_1' 	: 0b1000,
+		'folded_hist_2' 	: 0b1001,
+		'folded_hist_3' 	: 0b1010,
+		'folded_hist_4' 	: 0b1100,
+		'folded_hist_5' 	: 0b0001,
+		'folded_hist_6' 	: 0b0000,
+		'folded_hist_7' 	: 0b0001,
+		'folded_hist_8' 	: 0b0010,
+		'folded_hist_9' 	: 0b0100,
+		'folded_hist_10' 	: 0b1000,
+		'folded_hist_11' 	: 0b1100,
+		'folded_hist_12' 	: 0b1110,
+		'folded_hist_13' 	: 0b1111,
+		'folded_hist_14' 	: 0b0000,
+		'folded_hist_15' 	: 0b1111,
+		'folded_hist_16' 	: 0b1001,
+		'folded_hist_17' 	: 0b1001
+	}
+
+	task_update_ftb_entry 	= mlvp.create_task(env.update_ftb_entry_agent.set_update_ftb_entry_value(update_pc,update_ftb_entry_dict)) 
+	task_update_other 		= mlvp.create_task(env.update_other_agent.set_update_other_value(update_pc,update_other_dict))
+	task_update_foldedHist 	= mlvp.create_task(env.update_fold_hist_agent.set_update_fold_hist_value(update_pc,update_fold_hist_dict))
+
+	await task_update_ftb_entry
+	await task_update_other
+	await task_update_foldedHist
+
+	await env.update_ftb_entry_agent.bundle.step(1)
+
+	update_ftb_entry_dict = {
+		'ftb_entry_valid'	: 1,
+		'tailSlot_valid'	: 1,
+		'tailSlot_tarStat'	: 0b11,
+		'tailSlot_sharing'	: 1,
+		'tailSlot_offset'	: 0b1111,
+		'tailSlot_lower'	: 0x22,
+		'pftAddr'			: 0b1111,
+		'may_be_rvi_call'	: 1,
+		'isRet'				: 1,
+		'isJalr'			: 1,
+		'isCall'			: 1,
+		'carry'				: 1,
+		'always_taken_0'	: 1,
+		'always_taken_1'	: 1,
+		'brSlots_0_valid'	: 1,
+		'brSlots_0_tarStat' : 0b10,
+		'brSlots_0_sharing'	: 1,
+		'brSlots_0_offset'	: 0b0100,
+		'brSlots_0_lower'	: 0x200
+	}
+
+	## update_other_signals
+	update_other_dict = {
+		'cfi_idx_valid'		: 1,
+		'cfi_idx_bits'		: 0b0111,
+		'br_taken_mask_0'	: 1,
+		'br_taken_mask_1'	: 0,
+		'jmp_taken'			: 1,
+		'mispred_mask_0'	: 1,
+		'mispred_mask_1'	: 1,
+		'mispred_mask_2'	: 1,
+		'old_entry'			: 1,
+		'meta'				: 1,
+		'full_target'		: 1
+	}
+
+	update_fold_hist_dict = {
+		'folded_hist_1' 	: 0b1000,
+		'folded_hist_2' 	: 0b1001,
+		'folded_hist_3' 	: 0b1010,
+		'folded_hist_4' 	: 0b1100,
+		'folded_hist_5' 	: 0b0001,
+		'folded_hist_6' 	: 0b0000,
+		'folded_hist_7' 	: 0b0001,
+		'folded_hist_8' 	: 0b0010,
+		'folded_hist_9' 	: 0b0100,
+		'folded_hist_10' 	: 0b1000,
+		'folded_hist_11' 	: 0b1100,
+		'folded_hist_12' 	: 0b1110,
+		'folded_hist_13' 	: 0b1111,
+		'folded_hist_14' 	: 0b0000,
+		'folded_hist_15' 	: 0b1111,
+		'folded_hist_16' 	: 0b1001,
+		'folded_hist_17' 	: 0b1001
+	}
+
+	task_update_ftb_entry_1		= mlvp.create_task(env.update_ftb_entry_agent.set_update_ftb_entry_value(update_pc,update_ftb_entry_dict)) 
+	task_update_other_1 		= mlvp.create_task(env.update_other_agent.set_update_other_value(update_pc,update_other_dict))
+	task_update_foldedHist_1 	= mlvp.create_task(env.update_fold_hist_agent.set_update_fold_hist_value(update_pc,update_fold_hist_dict))
+
+	await task_update_ftb_entry_1
+	await task_update_other_1
+	await task_update_foldedHist_1
+
+	await task_clock
+	print("test_update_signals_sanity IS OVER")
+
+
+@pytest.mark.mlvp_async
+async def test_update_FtbEntry_foldHist_signals_4(mlvp_request):
+	print(mlvp_request)
+	env: BpuEnv = mlvp_request()
+	update_pc = 0x1248
+
+	enable_dict = {
+		'ubtb_en' 	: 1,	
+		'btb_en'	: 1,
+		'tage_en'	: 1,
+		'sc_en'		: 1,
+		'ras_en'	: 1
+	}
+
+	# reset
+	task_clock = mlvp.create_task(env.update_ftb_entry_agent.bundle.step(2200))
+	await env.update_ftb_entry_agent.reset(4)
+	await env.sub_predi_ctrl_agent.set_sub_predic_ctrl_en(enable_dict)
+	await env.update_ftb_entry_agent.bundle.step(2100)
+	print("begin exec test_update_fold_hist_sanity test")
+
+	update_ftb_entry_dict = {
+		'ftb_entry_valid'	: 1,
+		'tailSlot_valid'	: 1,
+		'tailSlot_tarStat'	: 0b11,
+		'tailSlot_sharing'	: 1,
+		'tailSlot_offset'	: 0b1111,
+		'tailSlot_lower'	: 0x21,
+		'pftAddr'			: 0b1111,
+		'may_be_rvi_call'	: 0,
+		'isRet'				: 0,
+		'isJalr'			: 0,
+		'isCall'			: 0,
+		'carry'				: 0,
+		'always_taken_0'	: 0,
+		'always_taken_1'	: 0,
+		'brSlots_0_valid'	: 0,
+		'brSlots_0_tarStat' : 0b00,
+		'brSlots_0_sharing'	: 0,
+		'brSlots_0_offset'	: 0b0000,
+		'brSlots_0_lower'	: 0x000
+	}
+	## update_other_signals
+	update_other_dict = {
+		'cfi_idx_valid'		: 1,
+		'cfi_idx_bits'		: 0b1000,
+		'br_taken_mask_0'	: 1,
+		'br_taken_mask_1'	: 1,
+		'jmp_taken'			: 0,
+		'mispred_mask_0'	: 0,
+		'mispred_mask_1'	: 0,
+		'mispred_mask_2'	: 0,
+		'old_entry'			: 0,
+		'meta'				: 0,
+		'full_target'		: 0
+	}
+
+	update_fold_hist_dict = {
+		'folded_hist_1' 	: 0b1000,
+		'folded_hist_2' 	: 0b1001,
+		'folded_hist_3' 	: 0b1010,
+		'folded_hist_4' 	: 0b1100,
+		'folded_hist_5' 	: 0b0001,
+		'folded_hist_6' 	: 0b0000,
+		'folded_hist_7' 	: 0b0001,
+		'folded_hist_8' 	: 0b0010,
+		'folded_hist_9' 	: 0b0100,
+		'folded_hist_10' 	: 0b1000,
+		'folded_hist_11' 	: 0b1100,
+		'folded_hist_12' 	: 0b1110,
+		'folded_hist_13' 	: 0b1111,
+		'folded_hist_14' 	: 0b0000,
+		'folded_hist_15' 	: 0b1111,
+		'folded_hist_16' 	: 0b1001,
+		'folded_hist_17' 	: 0b1001
+	}
+
+	task_update_ftb_entry 	= mlvp.create_task(env.update_ftb_entry_agent.set_update_ftb_entry_value(update_pc,update_ftb_entry_dict)) 
+	task_update_other 		= mlvp.create_task(env.update_other_agent.set_update_other_value(update_pc,update_other_dict))
+	task_update_foldedHist 	= mlvp.create_task(env.update_fold_hist_agent.set_update_fold_hist_value(update_pc,update_fold_hist_dict))
+
+	await task_update_ftb_entry
+	await task_update_other
+	await task_update_foldedHist
+
+	await env.update_ftb_entry_agent.bundle.step(1)
+
+	update_ftb_entry_dict = {
+		'ftb_entry_valid'	: 1,
+		'tailSlot_valid'	: 1,
+		'tailSlot_tarStat'	: 0b11,
+		'tailSlot_sharing'	: 1,
+		'tailSlot_offset'	: 0b1111,
+		'tailSlot_lower'	: 0x22,
+		'pftAddr'			: 0b1111,
+		'may_be_rvi_call'	: 1,
+		'isRet'				: 1,
+		'isJalr'			: 1,
+		'isCall'			: 1,
+		'carry'				: 1,
+		'always_taken_0'	: 1,
+		'always_taken_1'	: 1,
+		'brSlots_0_valid'	: 1,
+		'brSlots_0_tarStat' : 0b10,
+		'brSlots_0_sharing'	: 1,
+		'brSlots_0_offset'	: 0b1111,
+		'brSlots_0_lower'	: 0x222
+	}
+
+	## update_other_signals
+	update_other_dict = {
+		'cfi_idx_valid'		: 1,
+		'cfi_idx_bits'		: 0b1111,
+		'br_taken_mask_0'	: 1,
+		'br_taken_mask_1'	: 1,
+		'jmp_taken'			: 1,
+		'mispred_mask_0'	: 1,
+		'mispred_mask_1'	: 1,
+		'mispred_mask_2'	: 1,
+		'old_entry'			: 1,
+		'meta'				: 1,
+		'full_target'		: 1
+	}
+
+	update_fold_hist_dict = {
+		'folded_hist_1' 	: 0b1111,
+		'folded_hist_2' 	: 0b1111,
+		'folded_hist_3' 	: 0b1111,
+		'folded_hist_4' 	: 0b1111,
+		'folded_hist_5' 	: 0b1111,
+		'folded_hist_6' 	: 0b1111,
+		'folded_hist_7' 	: 0b1111,
+		'folded_hist_8' 	: 0b1111,
+		'folded_hist_9' 	: 0b1111,
+		'folded_hist_10' 	: 0b1111,
+		'folded_hist_11' 	: 0b1111,
+		'folded_hist_12' 	: 0b1111,
+		'folded_hist_13' 	: 0b1111,
+		'folded_hist_14' 	: 0b1111,
+		'folded_hist_15' 	: 0b1111,
+		'folded_hist_16' 	: 0b1111,
+		'folded_hist_17' 	: 0b1111
+	}
+
+	task_update_ftb_entry_1		= mlvp.create_task(env.update_ftb_entry_agent.set_update_ftb_entry_value(update_pc,update_ftb_entry_dict)) 
+	task_update_other_1 		= mlvp.create_task(env.update_other_agent.set_update_other_value(update_pc,update_other_dict))
+	task_update_foldedHist_1 	= mlvp.create_task(env.update_fold_hist_agent.set_update_fold_hist_value(update_pc,update_fold_hist_dict))
+
+	await task_update_ftb_entry_1
+	await task_update_other_1
+	await task_update_foldedHist_1
+
+	await task_clock
+	print("test_update_signals_sanity IS OVER")
+
+
+@pytest.mark.mlvp_async
+async def test_update_FtbEntry_foldHist_signals_5(mlvp_request):
+	print(mlvp_request)
+	env: BpuEnv = mlvp_request()
+	update_pc = 0x2428
+
+	enable_dict = {
+		'ubtb_en' 	: 1,	
+		'btb_en'	: 1,
+		'tage_en'	: 1,
+		'sc_en'		: 1,
+		'ras_en'	: 1
+	}
+
+	# reset
+	task_clock = mlvp.create_task(env.update_ftb_entry_agent.bundle.step(2200))
+	await env.update_ftb_entry_agent.reset(4)
+	await env.sub_predi_ctrl_agent.set_sub_predic_ctrl_en(enable_dict)
+	await env.update_ftb_entry_agent.bundle.step(2100)
+	print("begin exec test_update_fold_hist_sanity test")
+
+	update_ftb_entry_dict = {
+		'ftb_entry_valid'	: 1,
+		'tailSlot_valid'	: 1,
+		'tailSlot_tarStat'	: 0b11,
+		'tailSlot_sharing'	: 1,
+		'tailSlot_offset'	: 0b1111,
+		'tailSlot_lower'	: 0x21,
+		'pftAddr'			: 0b1111,
+		'may_be_rvi_call'	: 0,
+		'isRet'				: 0,
+		'isJalr'			: 0,
+		'isCall'			: 0,
+		'carry'				: 0,
+		'always_taken_0'	: 0,
+		'always_taken_1'	: 0,
+		'brSlots_0_valid'	: 0,
+		'brSlots_0_tarStat' : 0b00,
+		'brSlots_0_sharing'	: 0,
+		'brSlots_0_offset'	: 0b0000,
+		'brSlots_0_lower'	: 0x000
+	}
+	## update_other_signals
+	update_other_dict = {
+		'cfi_idx_valid'		: 1,
+		'cfi_idx_bits'		: 0b1000,
+		'br_taken_mask_0'	: 1,
+		'br_taken_mask_1'	: 1,
+		'jmp_taken'			: 0,
+		'mispred_mask_0'	: 0,
+		'mispred_mask_1'	: 0,
+		'mispred_mask_2'	: 0,
+		'old_entry'			: 0,
+		'meta'				: 0,
+		'full_target'		: 0
+	}
+
+	update_fold_hist_dict = {
+		'folded_hist_1' 	: 0b1000,
+		'folded_hist_2' 	: 0b1001,
+		'folded_hist_3' 	: 0b1010,
+		'folded_hist_4' 	: 0b1100,
+		'folded_hist_5' 	: 0b0001,
+		'folded_hist_6' 	: 0b0000,
+		'folded_hist_7' 	: 0b0001,
+		'folded_hist_8' 	: 0b0010,
+		'folded_hist_9' 	: 0b0100,
+		'folded_hist_10' 	: 0b1000,
+		'folded_hist_11' 	: 0b1100,
+		'folded_hist_12' 	: 0b1110,
+		'folded_hist_13' 	: 0b1111,
+		'folded_hist_14' 	: 0b0000,
+		'folded_hist_15' 	: 0b1111,
+		'folded_hist_16' 	: 0b1001,
+		'folded_hist_17' 	: 0b1001
+	}
+
+	task_update_ftb_entry 	= mlvp.create_task(env.update_ftb_entry_agent.set_update_ftb_entry_value(update_pc,update_ftb_entry_dict)) 
+	task_update_other 		= mlvp.create_task(env.update_other_agent.set_update_other_value(update_pc,update_other_dict))
+	task_update_foldedHist 	= mlvp.create_task(env.update_fold_hist_agent.set_update_fold_hist_value(update_pc,update_fold_hist_dict))
+
+	await task_update_ftb_entry
+	await task_update_other
+	await task_update_foldedHist
+
+	await env.update_ftb_entry_agent.bundle.step(20)
+
+	update_ftb_entry_dict = {
+		'ftb_entry_valid'	: 1,
+		'tailSlot_valid'	: 1,
+		'tailSlot_tarStat'	: 0b11,
+		'tailSlot_sharing'	: 1,
+		'tailSlot_offset'	: 0b1111,
+		'tailSlot_lower'	: 0x22,
+		'pftAddr'			: 0b1111,
+		'may_be_rvi_call'	: 1,
+		'isRet'				: 1,
+		'isJalr'			: 1,
+		'isCall'			: 1,
+		'carry'				: 1,
+		'always_taken_0'	: 1,
+		'always_taken_1'	: 1,
+		'brSlots_0_valid'	: 1,
+		'brSlots_0_tarStat' : 0b10,
+		'brSlots_0_sharing'	: 1,
+		'brSlots_0_offset'	: 0b1111,
+		'brSlots_0_lower'	: 0x222
+	}
+
+	## update_other_signals
+	update_other_dict = {
+		'cfi_idx_valid'		: 1,
+		'cfi_idx_bits'		: 0b1111,
+		'br_taken_mask_0'	: 1,
+		'br_taken_mask_1'	: 1,
+		'jmp_taken'			: 1,
+		'mispred_mask_0'	: 1,
+		'mispred_mask_1'	: 1,
+		'mispred_mask_2'	: 1,
+		'old_entry'			: 1,
+		'meta'				: 1,
+		'full_target'		: 1
+	}
+
+	update_fold_hist_dict = {
+		'folded_hist_1' 	: 0b1111,
+		'folded_hist_2' 	: 0b1111,
+		'folded_hist_3' 	: 0b1111,
+		'folded_hist_4' 	: 0b1111,
+		'folded_hist_5' 	: 0b1111,
+		'folded_hist_6' 	: 0b1111,
+		'folded_hist_7' 	: 0b1111,
+		'folded_hist_8' 	: 0b1111,
+		'folded_hist_9' 	: 0b1111,
+		'folded_hist_10' 	: 0b1111,
+		'folded_hist_11' 	: 0b1111,
+		'folded_hist_12' 	: 0b1111,
+		'folded_hist_13' 	: 0b1111,
+		'folded_hist_14' 	: 0b1111,
+		'folded_hist_15' 	: 0b1111,
+		'folded_hist_16' 	: 0b1111,
+		'folded_hist_17' 	: 0b1111
+	}
+
+	task_update_ftb_entry_1		= mlvp.create_task(env.update_ftb_entry_agent.set_update_ftb_entry_value(update_pc,update_ftb_entry_dict)) 
+	task_update_other_1 		= mlvp.create_task(env.update_other_agent.set_update_other_value(update_pc,update_other_dict))
+	task_update_foldedHist_1 	= mlvp.create_task(env.update_fold_hist_agent.set_update_fold_hist_value(update_pc,update_fold_hist_dict))
+
+	await task_update_ftb_entry_1
+	await task_update_other_1
+	await task_update_foldedHist_1
+
+
+####################################
+	await env.update_ftb_entry_agent.bundle.step(20)
+
+	enable_dict = {
+		'ubtb_en' 	: 1,	
+		'btb_en'	: 1,
+		'tage_en'	: 1,
+		'sc_en'		: 1,
+		'ras_en'	: 1
+	}
+
+
+	await env.sub_predi_ctrl_agent.set_sub_predic_ctrl_en(enable_dict)
+	await env.update_ftb_entry_agent.bundle.step(2)
+
+	update_ftb_entry_dict = {
+		'ftb_entry_valid'	: 1,
+		'tailSlot_valid'	: 1,
+		'tailSlot_tarStat'	: 0b11,
+		'tailSlot_sharing'	: 1,
+		'tailSlot_offset'	: 0b1111,
+		'tailSlot_lower'	: 0x22,
+		'pftAddr'			: 0b1111,
+		'may_be_rvi_call'	: 1,
+		'isRet'				: 1,
+		'isJalr'			: 1,
+		'isCall'			: 1,
+		'carry'				: 1,
+		'always_taken_0'	: 1,
+		'always_taken_1'	: 1,
+		'brSlots_0_valid'	: 1,
+		'brSlots_0_tarStat' : 0b10,
+		'brSlots_0_sharing'	: 1,
+		'brSlots_0_offset'	: 0b1111,
+		'brSlots_0_lower'	: 0x222
+	}
+
+	## update_other_signals
+	update_other_dict = {
+		'cfi_idx_valid'		: 1,
+		'cfi_idx_bits'		: 0b1111,
+		'br_taken_mask_0'	: 1,
+		'br_taken_mask_1'	: 1,
+		'jmp_taken'			: 1,
+		'mispred_mask_0'	: 1,
+		'mispred_mask_1'	: 1,
+		'mispred_mask_2'	: 1,
+		'old_entry'			: 1,
+		'meta'				: 1,
+		'full_target'		: 1
+	}
+
+	update_fold_hist_dict = {
+		'folded_hist_1' 	: 0b1111,
+		'folded_hist_2' 	: 0b1111,
+		'folded_hist_3' 	: 0b1111,
+		'folded_hist_4' 	: 0b1111,
+		'folded_hist_5' 	: 0b1111,
+		'folded_hist_6' 	: 0b1111,
+		'folded_hist_7' 	: 0b1111,
+		'folded_hist_8' 	: 0b1111,
+		'folded_hist_9' 	: 0b1111,
+		'folded_hist_10' 	: 0b1111,
+		'folded_hist_11' 	: 0b1111,
+		'folded_hist_12' 	: 0b1111,
+		'folded_hist_13' 	: 0b1111,
+		'folded_hist_14' 	: 0b1111,
+		'folded_hist_15' 	: 0b1111,
+		'folded_hist_16' 	: 0b1111,
+		'folded_hist_17' 	: 0b1111
+	}
+
+	task_update_ftb_entry_1		= mlvp.create_task(env.update_ftb_entry_agent.set_update_ftb_entry_value(update_pc,update_ftb_entry_dict)) 
+	task_update_other_1 		= mlvp.create_task(env.update_other_agent.set_update_other_value(update_pc,update_other_dict))
+	task_update_foldedHist_1 	= mlvp.create_task(env.update_fold_hist_agent.set_update_fold_hist_value(update_pc,update_fold_hist_dict))
+
+	await task_update_ftb_entry_1
+	await task_update_other_1
+	await task_update_foldedHist_1
+
+
+	await task_clock
+	print("test_update_signals_sanity IS OVER")
\ No newline at end of file