diff --git a/README.md b/README.md
index f7d5108..e69de29 100644
--- a/README.md
+++ b/README.md
@@ -1,3 +0,0 @@
-# work
-This is the main responsitry for work.
-
diff --git a/Scripts/gen_sram_wrap/gen_sram_wrap.py b/Scripts/gen_sram_wrap/gen_sram_wrap.py
new file mode 100644
index 0000000..e69de29
diff --git a/Scripts/gen_sram_wrap/mem_list.xls b/Scripts/gen_sram_wrap/mem_list.xls
new file mode 100644
index 0000000..b1725e2
--- /dev/null
+++ b/Scripts/gen_sram_wrap/mem_list.xls
@@ -0,0 +1,8 @@
+SubSystem	Block	InstanceName	MaxFreq	Depth	Width	Async	CompilerName	ReferenceName	AssemblyDepth	AssemblyWidth
+pcie_system	pcie_bridge	comp_infor_table_spsram	1GHz	768	31	No	TS1N12FFCLLUVLTA768X31M4SWSHOCP	pcie_768x31_comp_infor_table_spsam	768	31
+pcie_system	pcie_bridge	mrd_infor_table_spsram	1GHz	768	25	No	TS1N12FFCLLUVLTA768X25M4SWSHOCP	pcie_768x25_mrd_infor_table_spsram	768	25
+pcie_system	pcie_bridge	waiting_mrd_fifo_spsram	1GHz	768	94	No	TS1N12FFCLLUVLTA768X94M4SWSHOCP	pcie_768x94_waiting_mrd_fifo_spsram	768	94
+pcie_system	pcie_bridge	h2d_dirrd_datamerge_spsram	1GHz	4608	72	No	TS1N12FFCLLUVLTA4608X72M8SWSHOCP	pcie_4608x72_h2d_dirrd_datamerge_spsram	4608	72
+pcie_system	pcie_bridge	entryid2mrdtag_spsram	1GHz	512	18	No	TS1N12FFCLLUVLTA512X18M4SWSHOCP	pcie_512x18_entryid2mrdtag_spsram	512	18
+pcie_system	pcie_bridge	msix_table_wrentry_spsram	1GHz	2048	112	No	TS1N12FFCLLSBULVTE2048X112WS4UWHSOCP	pcie_2048x112_msix_table_wrentry_spsram	2048	112
+pcie_system	pcie_bridge	infly_comp_timeout_ram	1GHz	256	34	No	TS1N12FFCLLUVLTA256X34M2SWSHOCP	pcie_256x34_infly_comp_timeout_ram	256	34
diff --git a/Scripts/gen_sram_wrap/template_sram_wrap.v b/Scripts/gen_sram_wrap/template_sram_wrap.v
new file mode 100644
index 0000000..3cfd0d6
--- /dev/null
+++ b/Scripts/gen_sram_wrap/template_sram_wrap.v
@@ -0,0 +1,149 @@
+
+module $moduleName$ #(
+  parameter WIDTH = $WIDTH$,
+  parameter DEPTH = $DEPTH$,
+  parameter IN_PIPE = 0,
+  parameter OUT_PIPE = 1
+)(
+  input  wire                     CLK,
+  input  wire                     CEB,
+  input  wire                     WEB,
+  input  wire [$clog2(DEPTH)-1:0] A,
+  input  wire [WIDTH-1:0]         D,
+  input  wire [WIDTH-1:0]         BWEB,
+  input  wire                     SD,
+  input  wire [1:0]               RTSEL,
+  input  wire [1:0]               WTSEL,
+  output wire [WIDTH-1:0]         Q
+);
+
+localparam ADDR_WIDTH = $clog2(DEPTH);
+wire sram_ceb;
+wire sram_web;
+wire [WIDTH-1:0] sram_bweb;
+wire [ADDR_WIDTH-1:0] sram_addr;
+wire [WIDTH-1:0] sram_rdata;
+wire [WIDTH-1:0] sram_wdata;
+
+`ifdef USE_N12_TSMC_SRAM
+    if(DEPTH==31 && WIDTH==768) begin : GEN_768X31_SRAM
+        TS1N12FFCLLULVTA768X31M4SWSH0CP u_sram (
+          .CLK   (CLK),
+          .CEB   (sram_ceb),
+          .WEB   (sram_web),
+          .BWEB  (sram_bweb),
+          .A     (sram_addr),
+          .D     (sram_wdata),
+          .Q     (sram_rdata),
+          .SLP   (1'b0),
+          .DSLP  (1'b0),
+          .SD    (SD),
+          .RTSEL (RTSEL),
+          .WTSEL (WTSEL),
+          .FADIO (9'b0),
+          .REDENIO (1'b0),
+          .PUDELAY (1'b0)
+        );
+    end
+    else begin : ILLEGAL_SRAM_SIZE
+        $display("Error: Unsupported SRAM size %d x %d for TSMC N12 SRAM", WIDTH, DEPTH);
+    end
+
+`elsif USE_N12_SNPS_SRAM
+
+`elsif USE_N7_TSMC_SRAM
+
+`elsif USE_N7_SNPS_SRAM
+
+`else
+
+    reg [WIDTH-1:0] ram [DEPTH-1:0];
+    reg [WIDTH-1:0] rdata_ff;
+    integer i;
+
+    always @(posedge CLK) begin
+      if (CEB == 1'b0) begin
+        if (WEB == 1'b0) begin // write
+          for (i = 0; i < WIDTH; i = i + 1) begin
+            if (BWEB[i] == 1'b0) ram[A][i] <= D[i];
+          end
+        end
+        else begin // read
+          rdata_ff <= ram[A];
+        end
+      end
+    end
+
+    assign sram_rdata = rdata_ff;
+`endif
+
+// Input PIPE
+generate
+  if(IN_PIPE==1) begin : GEN_IN_PIPE_1
+    reg          ceb_ff;
+    reg          web_ff;
+    reg [WIDTH-1:0]  bweb_ff;
+    reg [ADDR_WIDTH-1:0] a_ff;
+    reg [WIDTH-1:0]  d_ff;
+    
+    always @(posedge CLK) begin
+      if(CEB==1'b0) begin
+        ceb_ff <= 1'b0;
+        web_ff <= WEB;
+        bweb_ff <= BWEB;
+        a_ff <= A;
+        d_ff <= D;
+      end
+      else begin
+        ceb_ff <= 1'b1;
+      end
+    end
+    
+    assign sram_ceb  = ceb_ff;
+    assign sram_web  = web_ff;
+    assign sram_bweb = bweb_ff;
+    assign sram_addr = a_ff;
+    assign sram_wdata = d_ff;
+  end
+  else begin : GEN_IN_PIPE_0
+    assign sram_ceb  = CEB;
+    assign sram_web  = WEB;
+    assign sram_bweb = BWEB;
+    assign sram_addr = A;
+    assign sram_wdata = D;
+  end
+endgenerate
+
+// Output PIPE
+generate
+  if(OUT_PIPE==1) begin : GEN_OUT_PIPE_1
+    reg             sram_ren_ff;
+    reg [WIDTH-1:0] sram_rdata_ff;
+    
+    always @(posedge CLK) begin
+      if(CEB==1'b0 && WEB==1'b1) begin
+        sram_ren_ff <= 1'b1;  // flag indicating read operation
+      end
+      else begin
+        sram_ren_ff <= 1'b0;
+      end
+    end
+    
+    always @(posedge CLK) begin
+      if(sram_ren_ff==1'b1) begin
+        sram_rdata_ff <= sram_rdata;  // latch read data
+      end
+      else begin
+        sram_rdata_ff <= sram_rdata_ff;
+      end
+    end
+
+    assign Q = sram_rdata_ff;  // output latched data
+  end
+  else begin : GEN_OUT_PIPE_0
+    assign Q = sram_rdata;  // direct output
+  end
+
+endgenerate
+
+endmodule: $moduleName$
\ No newline at end of file
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diff --git a/xmlab/software_design_mind/Program_code_mind.md b/xmlab/software_design_mind/Program_code_mind.md
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@@ -0,0 +1,23 @@
+# work
+This is the main responsitry for work.
+
+常老师的软件示范设计: 带我认识设计的过程
+
+
+降晟栋、廖恒臻：常老师说，一个工程的设计是至关重要的。初识设计的我们，还不太理解这句话的重要性，只是在脑海里构想出大致的流程，便急不可耐地去编程，结果编程很长时间不能实现功能。
+
+于是，常老师给出了具体的软件示范设计，带我们学习如何设计。我们依照常老师总结出的五步法，从需求分析开始出发，一步一步地深入，初步体会到了设计的思想，知道了只有在设计阶段下足功夫，才能避免因没有充分思考而无休止地编程，浪费时间的情况。我们从五步法出发，在设计阶段就对程序的逻辑性和严谨性进行尽可能充分的考虑，为编程的实现打好基础，从而更好地实现程序的功能，同时也初步领略到了“程序设计的艺术”。
+
+下面，展示一组降晟栋做的某个研发项目的主要设计过程。
+
+![alt text](image.png)
+
+![alt text](image-1.png)
+
+![alt text](image-2.png)
+
+![alt text](image-3.png)
+
+![alt text](image-4.png)
+
+![alt text](image-5.png)
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