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diff --git a/mem_mcu_wrap/cfg_noc_bridge详细设计文档.md b/mem_mcu_wrap/cfg_noc_bridge详细设计文档.md
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+@[TOC](cfg_noc_bridge详细设计文档)
+# 1 需求分解支持
+需求实现noc req测到AXI测协议bridge；
+需求实现AXI测到APB测转换bridge；；
+需求实现AXI master 1to2 转换；；
+需求实现APB decoder功能；；
+# 2 功能概述
+该设计文档是实现noc总线协议到AMBA总线协议的转换，，用以配置不同Slave的CSR；大致模块框图结构如下图所示：：
+![alt text](企业微信截图_17512521592683.png)
+
+# 2 输入输出接口
+## 2.1 noc2AXI接口
+### 2.1.1 noc测接口： 
+Name            |       I/O   |     Width     |     Description
+----------------|-------------|---------------|-----------------
+noc_req_rdy            O           1               ready 
+noc_req_vld            I           1               valid
+noc_req_flit           I           64              flit
+----------------------------------------------------------------
+noc_rsp_rdy             I           1               ready      
+noc_rsp_vld             O           1               valid
+noc_rsp_flit            O           64              flit
+
+### 2.1.2 AXI接口
+Name            |       I/O   |     Width     |     Description
+----------------|-------------|---------------|-----------------
+awready
+awvalid
+awaddr
+awlen
+awsize
+awburst
+------------------------------------------------------------------
+wready            O           1               ready
+wavlid
+wdata
+wstrb
+wlast
+------------------------------------------------------------------
+bready
+bvalid
+bid
+bresp
+------------------------------------------------------------------
+arready
+arvalid
+araddr
+araid
+arlen
+arsize
+arburst
+------------------------------------------------------------------
+rready
+rvalid
+rid
+rdata
+rresp
+rlast
+------------------------------------------------------------------
+
+### 2.1.3 接口时序
+相关接口时序图如下图所示:
+![alt text](image-1.png)
+
+## 2.2 AXI2APB接口
+### 2.2.1 AXI接口
+如上节所示
+
+### 2.2.1 APB接口
+Name            |       I/O   |     Width     |     Description
+----------------|-------------|---------------|-----------------
+psel
+penable
+pwrite
+paddr
+pready
+prdata
+
+### 2.2.3 AXI2APB接口时序
+相关接口时序图如下图所示：
+1.write接口时序如下：：
+![alt text](image-2.png)
+
+必要描述：：
+2.read接口时序如下：：
+![alt text](image-3.png)
+必要描述：：
+
+# 3 设计详述
+## 3.1 noc2axi_bridge
+### 3.1.1 状态机
+该bridge设计模块的状态机如下图所示：：
+![alt text](企业微信截图_17518934275106.png)
+
+## 3.2 axi2apb_bridge
+该bridge设计模块的状态机如下图所示：：
+![alt text](企业微信截图_1751963678421.png)
+
+## 3.3 axi_1to2
+通过高位地址进行MUX；；
+## 3.4 apb_decoder
+通过高位地址进行MUX；；
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diff --git a/rtl/cfg_noc_bridge/axi2apb.json b/rtl/cfg_noc_bridge/axi2apb.json
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+{
+//  "signal": [
+//    { "name": "ACLK", "wave": "p.|..................", "period": 1 },
+//    
+//    // AXI写通道
+//    ['AW_CH',
+//        { "name": "AWVALID",    "wave": "0.|.1.0.............." },
+//        { "name": "AWREADY",    "wave": "0.|..10.............." },
+//        { "name": "AWADDR",     "wave": "x.|.3.x..............", "data": "awaddr" },
+//        {},
+//    ],
+//    ['W_CH',
+//        { "name": "WVALID",     "wave": "0..|...1..0.........." },
+//        { "name": "WREADY",     "wave": "0..|.....10.........." },
+//        { "name": "WDATA",      "wave": "x..|...3..x..........", "data": "wdata" },
+//        {},
+//    ],
+
+//    ['B_CH',
+//        { "name": "BVALID",     "wave": "0.|...........1.0...." },
+//        { "name": "BREADY",     "wave": "0.|............1.0..." },
+//        {},
+//    ],
+//    
+//    // FSM Idication
+//    { "name": "STATE", "wave": "=.|...3...33..3.3.xxx", "data": ["IDLE","WAIT_WDATA","SET","ACS","RESP_W","IDLE"] },
+
+//    ['APB',
+//        { "name": "PSEL",       "wave": "0.|.......1...0......" },
+//        { "name": "PENABLE",    "wave": "0.|........1..0......" },
+//        { "name": "PWRITE",     "wave": "0.|.......1...0......" },
+//        { "name": "PADDR",      "wave": "x.|.......3...x......", "data": ["addr",] },
+//        { "name": "PWDATA",     "wave": "x.|.......3...x......", "data": ["wdata",] },
+//        { "name": "PREADY",     "wave": "1.|........0.1......." },
+//        { "name": "PRDATA",     "wave": "x.|..................", "data": [""] },
+//    ],
+
+//    
+//  ],
+
+ "signal": [
+    { "name": "ACLK",           "wave": "p.|..............", "period": 1 },
+    // AXI读通道
+    ['AW_CH',
+        { "name": "ARVALID",    "wave": "0.|..1..0......." },
+        { "name": "ARREADY",    "wave": "0.|....10......." },
+        { "name": "ARADDR",     "wave": "x.|..3..x.......", "data": "araddr" },
+        {},
+    ],
+
+    ['R_CH',
+        { "name": "RVALID",     "wave": "0.|.........1.0." },
+        { "name": "RREADY",     "wave": "0.|..........10." },
+        { "name": "RDATA",      "wave": "x.|.........3.x.", "data": "rdata" },
+        {},
+    ],
+
+    // FSM Idication
+    { "name": "STATE", "wave": "=..|....33..3.=.", "data": ["IDLE","SET","ACS","RESP_R","IDLE"] },
+    {},
+
+    ['APB',
+        { "name": "PSEL",       "wave": "0.|.....1...0..." },
+        { "name": "PENABLE",    "wave": "0.|......1..0..." },
+        { "name": "PWRITE",     "wave": "0.|.....1...0..." },
+        { "name": "PADDR",      "wave": "x.|.....3...x...", "data": ["addr",] },
+        { "name": "PREADY",     "wave": "1.|......0.1...." },
+        { "name": "PRDATA",     "wave": "x.|........3x...", "data": ["prdata"] },
+        { "name": "PWDATA",     "wave": "x.|.........x...", "data": ["wdata",] },
+    ],
+
+
+],
+
+
+  "head": {
+    "text": "AXI4 to APB3 Bridge Timing",
+    "tick": 0,
+    "every": 1
+  },
+ // "foot": {
+ //   "text": "Cycle: 0  1  2  3  4  5  6  7  8  9",
+ //   "tick": 0
+ // }
+
+}
\ No newline at end of file