modify the cfg_noc_axi_bridge
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leeyunlong
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//======================================================================
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// Self-Defined Bus to AXI4.0 Protocol Bridge
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// Features:
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// - Full duplex read/write operations
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// - Pipeline optimization for back-to-back transactions
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// - AXI4.0 burst mode support (single transaction per request)
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// - Configurable address mapping
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// - Error handling with AXI-compatible response codes
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//======================================================================
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module cfg_noc_axi_bridge #(
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parameter DATA_WID = 32,
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parameter ID_WID = 5,
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parameter NODE_ID_WID = 5,
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parameter SUB_ADDR_WID = 22,
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parameter ERR_WID = 2,
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parameter ADDR_WID = 32,
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parameter REQ_FLIT_WID = 1
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+ ID_WID
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+ NODE_ID_WID
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+ SUB_ADDR_WID
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+ DATA_WID ,
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parameter RSP_FLIT_WID = 1
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+ ID_WID
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+ ERR_WID
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+ DATA_WID
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)(
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// Global signals
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input wire clk,
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input wire rst_n,
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// Self-defined Bus Request Interface
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output wire bridge_req_rdy,
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input wire bridge_req_vld,
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input wire [REQ_FLIT_WID-1:0] bridge_req_flit,
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// Self-defined Bus Response Interface
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input wire bridge_rsp_rdy,
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output wire bridge_rsp_vld,
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output wire [RSP_FLIT_WID-1:0] bridge_rsp_flit,
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// AXI4.0 Master Interface
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// Write Address Channel
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output wire m_axi_awvalid,
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output wire [ID_WID-1:0] m_axi_awid,
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output wire [ADDR_WID-1:0] m_axi_awaddr,
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output wire [7:0] m_axi_awlen,
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output wire [2:0] m_axi_awsize,
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output wire [1:0] m_axi_awburst,
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input wire m_axi_awready,
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// Write Data Channel
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output wire m_axi_wvalid,
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output wire [ID_WID-1:0] m_axi_wid,
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output wire [DATA_WID-1:0] m_axi_wdata,
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output wire [DATA_WID/8-1:0] m_axi_wstrb,
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output wire m_axi_wlast,
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input wire m_axi_wready,
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// Write Response Channel
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input wire m_axi_bvalid,
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input wire [ID_WID-1:0] m_axi_bid,
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input wire [1:0] m_axi_bresp,
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output wire m_axi_bready,
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// Read Address Channel
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output wire [ID_WID-1:0] m_axi_arid,
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output wire [ADDR_WID-1:0] m_axi_araddr,
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output wire [7:0] m_axi_arlen,
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output wire [2:0] m_axi_arsize,
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output wire [1:0] m_axi_arburst,
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output wire m_axi_arvalid,
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input wire m_axi_arready,
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// Read Data Channel
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input wire [ID_WID-1:0] m_axi_rid,
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input wire [DATA_WID-1:0] m_axi_rdata,
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input wire [1:0] m_axi_rresp,
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input wire m_axi_rlast,
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input wire m_axi_rvalid,
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output wire m_axi_rready
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);
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//----------------------------------------------------------------------
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// Parameters
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//----------------------------------------------------------------------
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localparam BYTE_EN_WID = DATA_WID/8;
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//----------------------------------------------------------------------
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// Request Flit Decomposition (Structure matching your spec)
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//----------------------------------------------------------------------
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wire bridge_req_type; // 0:Read, 1:Write
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wire [ID_WID-1:0] bridge_req_id;
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wire [NODE_ID_WID-1:0] bridge_req_node_id;
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wire [SUB_ADDR_WID-1:0] bridge_req_sub_addr;
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wire [DATA_WID-1:0] bridge_req_wdata; // Valid for write requests
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assign {
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bridge_req_type, // 1 bit
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bridge_req_id, // ID_WID
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bridge_req_node_id, // NODE_ID_WID
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bridge_req_sub_addr, // SUB_ADDR_WID
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bridge_req_wdata // DATA_WID
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} = bridge_req_flit;
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//----------------------------------------------------------------------
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// FSM Declaration (Handling read/write transactions)
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//----------------------------------------------------------------------
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localparam IDLE = 3'b000;
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localparam HOLD_REQ = 3'b001;
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localparam AW_W_CHAN = 3'b010;
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localparam AR_CHAN = 3'b011;
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localparam WR_RESP_CHAN = 3'b100;
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localparam RD_DATA_CHAN = 3'b110;
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//localparam ERROR = 3'b111;
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reg [2:0] curr_state;
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reg [2:0] next_state;
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//----------------------------------------------------------------------
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// FSM-1 FSM transition logic
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//----------------------------------------------------------------------
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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curr_state <= IDLE;
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end else begin
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curr_state <= next_state;
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end
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end
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//----------------------------------------------------------------------
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// FSM-2 FSM Jump condition logic
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//----------------------------------------------------------------------
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reg hold_req_vld; // Hold current request
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reg hold_req_type; // Hold current request
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reg [ID_WID-1:0] hold_req_id; // Transaction ID in progress
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reg [SUB_ADDR_WID-1:0] hold_req_sub_addr;
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reg [DATA_WID-1:0] hold_req_wdata; // Valid for write requests
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always @(*) begin
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if (!rst_n) begin
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next_state = IDLE;
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end else begin
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case (curr_state)
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IDLE: begin
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next_state = (bridge_req_vld) ? HOLD_REQ : IDLE;
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end
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HOLD_REQ: begin
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if(hold_req_type && m_axi_awready && m_axi_wready) begin
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next_state = AW_W_CHAN;
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end else if (!hold_req_type && m_axi_arready) begin
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next_state = AR_CHAN;
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end else begin
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next_state = HOLD_REQ;
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end
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end
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AW_W_CHAN: begin
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next_state = WR_RESP_CHAN;
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end
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AR_CHAN: begin
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next_state = RD_DATA_CHAN;
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end
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WR_RESP_CHAN: begin
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next_state = (m_axi_bvalid && m_axi_rlast) ? IDLE : WR_RESP_CHAN;
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end
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RD_DATA_CHAN: begin
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next_state = (m_axi_rvalid) ? IDLE : RD_DATA_CHAN;
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end
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endcase
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end
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end
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//----------------------------------------------------------------------
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// FSM-3 :FSM Action Logic
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//----------------------------------------------------------------------
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//reg req_vld;
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//reg req_type; // 0:Read, 1:Write
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//reg [ID_WID-1:0] req_id;
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//reg [NODE_ID_WID-1:0] req_node_id;
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//reg [SUB_ADDR_WID-1:0] req_sub_addr;
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//reg [DATA_WID-1:0] req_wdata; // Valid for write requests
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//
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//always @(posedge clk or negedge rst_n) begin
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// if (!rst_n) begin
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// req_vld <= 1'b0;
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// req_type <= 1'b0;
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// req_id <= 'b0;
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// req_sub_addr <= 'b0;
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// req_data <= 'b0;
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// req_err <= 'b0;
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// end else if (bridge_req_vld && !req_vld) begin
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// req_vld <= 1'b1;
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// req_type <= bridge_req_type;
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// req_id <= bridge_req_id;
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// req_addr <= bridge_req_sub_addr;
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// req_wdata <=bridge_req_wdata;
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// end else begin
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// req_vld <= 1'b0;
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// end
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//end
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assign bridge_req_rdy = (curr_state == IDLE);
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//----------------------------------------------------------------------
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// Transaction Processing
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//----------------------------------------------------------------------
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reg reg_rsp_vld;
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reg reg_rsp_type;
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reg [2 -1:0] reg_rsp_resp;
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reg [ID_WID -1:0] reg_rsp_id; // Transaction ID in progress
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reg [DATA_WID-1:0] reg_rsp_rdata;
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always_ff @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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hold_req_vld <= 1'b0;
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hold_req_type <= 1'b0;
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hold_req_id <= 'b0;
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reg_rsp_vld <= 'b0;
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reg_rsp_type <= 'b0;
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reg_rsp_id <= 'b0;
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reg_rsp_resp <= 'b0;
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reg_rsp_rdata <= 'b0;
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//====current_req
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end
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else begin
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case (curr_state)
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IDLE: begin
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if (bridge_req_vld) begin
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hold_req_vld <= 1'b1;
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hold_req_type <= bridge_req_type;
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hold_req_id <= bridge_req_id;
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hold_req_sub_addr<=bridge_req_sub_addr;
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hold_req_wdata <= bridge_req_wdata;
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end else begin
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hold_req_vld <= 'b0;
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hold_req_type <= 'b0;
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hold_req_id <= 'b0;
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hold_req_sub_addr<='b0;
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hold_req_wdata <= 'b0;
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end
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reg_rsp_vld <= 'b0;
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reg_rsp_type <= 'b0;
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reg_rsp_id <= 'b0;
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reg_rsp_resp <= 'b0;
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reg_rsp_rdata <= 'b0;
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end
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HOLD_REQ: begin
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hold_req_vld <= hold_req_vld;
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hold_req_type <= hold_req_vld;
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hold_req_id <= hold_req_id;
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hold_req_sub_addr<=hold_req_sub_addr;
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hold_req_wdata <= hold_req_wdata;
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end
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AW_W_CHAN: begin
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end
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AR_CHAN: begin
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end
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WR_RESP_CHAN: begin
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if (m_axi_bvalid==1'b1) begin
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reg_rsp_vld <= 1'b1;
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reg_rsp_type<= 'b1;
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reg_rsp_id <= m_axi_bid;
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reg_rsp_resp<= m_axi_bresp;
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reg_rsp_rdata<= 'b0;
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end else begin
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end
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end
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RD_DATA_CHAN: begin
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if (m_axi_rvalid==1'b1) begin
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reg_rsp_vld <= 1'b1;
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reg_rsp_type<= 1'b0;
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reg_rsp_id <= m_axi_rid;
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reg_rsp_resp<= m_axi_rresp;
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reg_rsp_rdata<=m_axi_rdata;
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end
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end
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default: begin
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end
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endcase
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end
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end
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//----------------------------------------------------------------------
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// AXI control signals
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//----------------------------------------------------------------------
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// AXI signal assignments
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assign m_axi_awvalid = (curr_state == AW_W_CHAN);
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assign m_axi_awaddr = (curr_state == AW_W_CHAN) ? {10'b0,hold_req_sub_addr} : 'b0;
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assign m_axi_awid = (curr_state == AW_W_CHAN) ? hold_req_id : 'b0;
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assign m_axi_awlen = 8'h00; // Single transaction
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assign m_axi_awsize = 3'b100; // 4 bytes (DATA_WID/8)
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assign m_axi_awburst = 2'b01; // INCR burst type
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assign m_axi_wvalid = (curr_state == AW_W_CHAN);
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assign m_axi_wid = (curr_state == AW_W_CHAN) ? hold_req_id : 'b0;
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assign m_axi_wdata = (curr_state == AW_W_CHAN) ? hold_req_wdata : 'b0;
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assign m_axi_wstrb = {BYTE_EN_WID{1'b1}}; // All bytes enabled
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assign m_axi_wlast = 1'b1;
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assign m_axi_arvalid = (curr_state == AR_CHAN);
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assign m_axi_arid = (curr_state == AR_CHAN) ? hold_req_id : 'b0;
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assign m_axi_araddr = (curr_state == AR_CHAN) ? {10'b0,hold_req_sub_addr} : 'b0;
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assign m_axi_arlen = 8'h00;
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assign m_axi_arsize = 3'b100;
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assign m_axi_arburst = 2'b01;
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assign m_axi_bready = 1'b1; // Always ready for write responses
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//assign m_axi_rready = 1'b1;
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assign m_axi_rready = bridge_rsp_rdy;
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//----------------------------------------------------------------------
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// Response Packet Formatting
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//----------------------------------------------------------------------
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assign bridge_rsp_vld = reg_rsp_vld;
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// Response format: [type(1)|ID(5)|ERR(2)|DATA(32)]
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assign bridge_rsp_flit = {
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reg_rsp_type, // type bit
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reg_rsp_id, // ID_WID
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reg_rsp_resp, // ERR_WID
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reg_rsp_rdata // DATA_WID
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};
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//----------------------------------------------------------------------
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// Timeout Protection (Prevent transaction hangs)
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//----------------------------------------------------------------------
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// localparam TIMEOUT_VALUE = 1023;
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// reg [9:0] timeout_counter;
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//
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// always_ff @(posedge clk or negedge rst_n) begin
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// if (!rst_n)
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// timeout_counter <= '0;
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// else if (curr_state != next_state)
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// timeout_counter <= '0;
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// else if (curr_state != IDLE)
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// timeout_counter <= timeout_counter + 1;
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// end
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endmodule
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