commit the new files
This commit is contained in:
leeyunlong
parent
c0d88e095b
commit
4382e0ffc4
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@ -38,7 +38,9 @@ def generate_files(xls_path, sheet_name=None):
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'AssemblyWidth' : headers.index('AssemblyWidth'),
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'CompileDepth' : headers.index('CompileDepth'),
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'CompileWidth' : headers.index('CompileWidth'),
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'ASYNC' : headers.index('Async')
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'ASYNC' : headers.index('Async'),
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'MUX' : headers.index('MUX') if 'MUX' in headers else -1,
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'CompilerName' : headers.index('CompilerName') if 'CompilerName' in headers else -1
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}
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# 新增列存在性检查
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@ -87,6 +89,10 @@ def generate_files(xls_path, sheet_name=None):
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else "template_sram_tp_async_wrap_asmbly.v"
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print(f"Generated {sram_port} wrapper for: {row[col_map['name']]}")
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# 获取WTSEL
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WTsel = get_mem_ctrl_bus_fields(row[col_map['CompilerName']], int(row[col_map['MUX']]),
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int(row[col_map['CompileWidth']]), int(row[col_map['CompileDepth']]))
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# 调用生成函数
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generate_sram_wrapper(
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# input file_path
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@ -99,6 +105,7 @@ def generate_files(xls_path, sheet_name=None):
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asmbly_width_nums = int(row[col_map['AssemblyWidth']]),
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compile_depth = int(row[col_map['CompileDepth']]),
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compile_width = int(row[col_map['CompileWidth']]),
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wtsel = WTsel ,
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output_dir = output_dir
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)
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@ -119,6 +126,7 @@ def generate_files(xls_path, sheet_name=None):
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def generate_sram_wrapper(template_file, sram_name, width, depth, ref_name,\
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asmbly_depth_nums,asmbly_width_nums,compile_depth,compile_width,\
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wtsel,\
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output_dir):
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"""生成单个SRAM包装文件"""
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with open(template_file, 'r') as f:
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@ -132,6 +140,7 @@ def generate_sram_wrapper(template_file, sram_name, width, depth, ref_name,\
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.replace('${AssemblyWidth}',str(asmbly_width_nums))\
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.replace('${CompileDepth}',str(compile_depth))\
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.replace('${CompileWidth}',str(compile_width))\
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.replace('${WTselRange}', str(wtsel))\
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.replace('${ReferenceName}', ref_name)
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# 写入输出文件
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@ -139,6 +148,20 @@ def generate_sram_wrapper(template_file, sram_name, width, depth, ref_name,\
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with open(output_path, 'w') as f:
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f.write(replaced)
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def get_mem_ctrl_bus_fields(i_compilerName,mux,width, depth):
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compilerName = i_compilerName.split('_')[0]
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# get WTSEL
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wtsel = '[45:44]'
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if compilerName == 'tsn12ffcllspsram':
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print(f"Compiler Name: {compilerName}, Mux: {mux}, Width: {width}, Depth: {depth}")
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if (mux == 4 and (depth>1024 and depth <= 4096)) or \
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(mux == 8 and (depth>2048 and depth <= 8192)) or \
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(mux == 16 and (depth>4096 and depth <= 16384)):
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wtsel = '[47:46]'
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return wtsel
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if __name__ == "__main__":
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args = parse_args()
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Binary file not shown.
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@ -11,8 +11,9 @@ module sram_sp_pcie_2048x112 #(
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input wire [$clog2(DEPTH)-1:0] A,
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input wire [WIDTH-1:0] D,
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input wire [WIDTH-1:0] BWEB,
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input wire mem_ctrl_bus_sd,
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input wire [64 -1:0] mem_ctrl_bus,
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input wire SD,
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input wire [1:0] RTSEL,
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input wire [1:0] WTSEL,
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output wire [WIDTH-1:0] Q
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);
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@ -24,10 +25,9 @@ wire [ADDR_WIDTH-1:0] sram_addr;
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wire [WIDTH-1:0] sram_rdata;
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wire [WIDTH-1:0] sram_wdata;
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wire SD = mem_ctrl_bus_sd;
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wire [2-1:0] RTSEL = mem_ctrl_bus[49:48];
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wire [2-1:0] WTSEL = mem_ctrl_bus[45:44];
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`ifdef USE_N12_TSMC_SRAM
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if(DEPTH==2048 && WIDTH==112) begin : GEN_2048x112_SRAM
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TS1N12FFCLLSBULVTE2048X112WS4UWHSOCP U_TS1N12FFCLLSBULVTE2048X112WS4UWHSOCP (
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@ -49,6 +49,7 @@ wire [2-1:0] WTSEL = mem_ctrl_bus[45:44];
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);
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end
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else begin : ILLEGAL_SRAM_SIZE
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$display("Error: Unsupported SRAM size %d x %d for TSMC N12 SRAM", WIDTH, DEPTH);
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end
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`elsif USE_N12_SNPS_SRAM
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@ -148,4 +149,4 @@ generate
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endgenerate
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endmodule
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endmodule: $moduleName$
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@ -11,8 +11,9 @@ module sram_sp_pcie_256x34 #(
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input wire [$clog2(DEPTH)-1:0] A,
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input wire [WIDTH-1:0] D,
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input wire [WIDTH-1:0] BWEB,
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input wire mem_ctrl_bus_sd,
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input wire [64 -1:0] mem_ctrl_bus,
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input wire SD,
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input wire [1:0] RTSEL,
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input wire [1:0] WTSEL,
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output wire [WIDTH-1:0] Q
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);
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@ -24,10 +25,9 @@ wire [ADDR_WIDTH-1:0] sram_addr;
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wire [WIDTH-1:0] sram_rdata;
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wire [WIDTH-1:0] sram_wdata;
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wire SD = mem_ctrl_bus_sd;
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wire [2-1:0] RTSEL = mem_ctrl_bus[49:48];
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wire [2-1:0] WTSEL = mem_ctrl_bus[45:44];
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`ifdef USE_N12_TSMC_SRAM
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if(DEPTH==256 && WIDTH==34) begin : GEN_256x34_SRAM
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TS1N12FFCLLUVLTA256X34M2SWSHOCP U_TS1N12FFCLLUVLTA256X34M2SWSHOCP (
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@ -49,6 +49,7 @@ wire [2-1:0] WTSEL = mem_ctrl_bus[45:44];
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);
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end
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else begin : ILLEGAL_SRAM_SIZE
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$display("Error: Unsupported SRAM size %d x %d for TSMC N12 SRAM", WIDTH, DEPTH);
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end
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`elsif USE_N12_SNPS_SRAM
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@ -148,4 +149,4 @@ generate
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endgenerate
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endmodule
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endmodule: $moduleName$
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@ -11,8 +11,9 @@ module sram_sp_pcie_4608x72 #(
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input wire [$clog2(DEPTH)-1:0] A,
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input wire [WIDTH-1:0] D,
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input wire [WIDTH-1:0] BWEB,
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input wire mem_ctrl_bus_sd,
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input wire [64 -1:0] mem_ctrl_bus,
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input wire SD,
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input wire [1:0] RTSEL,
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input wire [1:0] WTSEL,
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output wire [WIDTH-1:0] Q
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);
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@ -24,10 +25,9 @@ wire [ADDR_WIDTH-1:0] sram_addr;
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wire [WIDTH-1:0] sram_rdata;
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wire [WIDTH-1:0] sram_wdata;
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wire SD = mem_ctrl_bus_sd;
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wire [2-1:0] RTSEL = mem_ctrl_bus[49:48];
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wire [2-1:0] WTSEL = mem_ctrl_bus[45:44];
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`ifdef USE_N12_TSMC_SRAM
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if(DEPTH==4608 && WIDTH==72) begin : GEN_4608x72_SRAM
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TS1N12FFCLLUVLTA4608X72M8SWSHOCP U_TS1N12FFCLLUVLTA4608X72M8SWSHOCP (
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@ -49,6 +49,7 @@ wire [2-1:0] WTSEL = mem_ctrl_bus[45:44];
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);
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end
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else begin : ILLEGAL_SRAM_SIZE
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$display("Error: Unsupported SRAM size %d x %d for TSMC N12 SRAM", WIDTH, DEPTH);
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end
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`elsif USE_N12_SNPS_SRAM
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@ -148,4 +149,4 @@ generate
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endgenerate
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endmodule
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endmodule: $moduleName$
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@ -11,8 +11,9 @@ module sram_sp_pcie_512x18 #(
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input wire [$clog2(DEPTH)-1:0] A,
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input wire [WIDTH-1:0] D,
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input wire [WIDTH-1:0] BWEB,
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input wire mem_ctrl_bus_sd,
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input wire [64 -1:0] mem_ctrl_bus,
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input wire SD,
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input wire [1:0] RTSEL,
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input wire [1:0] WTSEL,
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output wire [WIDTH-1:0] Q
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);
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@ -24,10 +25,9 @@ wire [ADDR_WIDTH-1:0] sram_addr;
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wire [WIDTH-1:0] sram_rdata;
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wire [WIDTH-1:0] sram_wdata;
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wire SD = mem_ctrl_bus_sd;
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wire [2-1:0] RTSEL = mem_ctrl_bus[49:48];
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wire [2-1:0] WTSEL = mem_ctrl_bus[45:44];
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`ifdef USE_N12_TSMC_SRAM
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if(DEPTH==512 && WIDTH==18) begin : GEN_512x18_SRAM
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TS1N12FFCLLUVLTA512X18M4SWSHOCP U_TS1N12FFCLLUVLTA512X18M4SWSHOCP (
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@ -49,6 +49,7 @@ wire [2-1:0] WTSEL = mem_ctrl_bus[45:44];
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);
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end
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else begin : ILLEGAL_SRAM_SIZE
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$display("Error: Unsupported SRAM size %d x %d for TSMC N12 SRAM", WIDTH, DEPTH);
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end
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`elsif USE_N12_SNPS_SRAM
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@ -148,4 +149,4 @@ generate
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endgenerate
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endmodule
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endmodule: $moduleName$
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@ -11,8 +11,9 @@ module sram_sp_pcie_768x25 #(
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input wire [$clog2(DEPTH)-1:0] A,
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input wire [WIDTH-1:0] D,
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input wire [WIDTH-1:0] BWEB,
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input wire mem_ctrl_bus_sd,
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input wire [64 -1:0] mem_ctrl_bus,
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input wire SD,
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input wire [1:0] RTSEL,
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input wire [1:0] WTSEL,
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output wire [WIDTH-1:0] Q
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);
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@ -24,10 +25,9 @@ wire [ADDR_WIDTH-1:0] sram_addr;
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wire [WIDTH-1:0] sram_rdata;
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wire [WIDTH-1:0] sram_wdata;
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wire SD = mem_ctrl_bus_sd;
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wire [2-1:0] RTSEL = mem_ctrl_bus[49:48];
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wire [2-1:0] WTSEL = mem_ctrl_bus[45:44];
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`ifdef USE_N12_TSMC_SRAM
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if(DEPTH==768 && WIDTH==25) begin : GEN_768x25_SRAM
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TS1N12FFCLLUVLTA768X25M4SWSHOCP U_TS1N12FFCLLUVLTA768X25M4SWSHOCP (
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@ -49,6 +49,7 @@ wire [2-1:0] WTSEL = mem_ctrl_bus[45:44];
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);
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end
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else begin : ILLEGAL_SRAM_SIZE
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$display("Error: Unsupported SRAM size %d x %d for TSMC N12 SRAM", WIDTH, DEPTH);
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end
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`elsif USE_N12_SNPS_SRAM
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@ -148,4 +149,4 @@ generate
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endgenerate
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endmodule
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endmodule: $moduleName$
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@ -11,8 +11,9 @@ module sram_sp_pcie_768x31 #(
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input wire [$clog2(DEPTH)-1:0] A,
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input wire [WIDTH-1:0] D,
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input wire [WIDTH-1:0] BWEB,
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input wire mem_ctrl_bus_sd,
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input wire [64 -1:0] mem_ctrl_bus,
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input wire SD,
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input wire [1:0] RTSEL,
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input wire [1:0] WTSEL,
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output wire [WIDTH-1:0] Q
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);
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@ -24,10 +25,9 @@ wire [ADDR_WIDTH-1:0] sram_addr;
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wire [WIDTH-1:0] sram_rdata;
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wire [WIDTH-1:0] sram_wdata;
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wire SD = mem_ctrl_bus_sd;
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wire [2-1:0] RTSEL = mem_ctrl_bus[49:48];
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wire [2-1:0] WTSEL = mem_ctrl_bus[45:44];
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`ifdef USE_N12_TSMC_SRAM
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if(DEPTH==768 && WIDTH==31) begin : GEN_768x31_SRAM
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TS1N12FFCLLUVLTA768X31M4SWSHOCP U_TS1N12FFCLLUVLTA768X31M4SWSHOCP (
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@ -49,6 +49,7 @@ wire [2-1:0] WTSEL = mem_ctrl_bus[45:44];
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);
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end
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else begin : ILLEGAL_SRAM_SIZE
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$display("Error: Unsupported SRAM size %d x %d for TSMC N12 SRAM", WIDTH, DEPTH);
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end
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`elsif USE_N12_SNPS_SRAM
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@ -148,4 +149,4 @@ generate
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endgenerate
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endmodule
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endmodule: $moduleName$
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@ -11,8 +11,9 @@ module sram_sp_pcie_768x94 #(
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input wire [$clog2(DEPTH)-1:0] A,
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input wire [WIDTH-1:0] D,
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input wire [WIDTH-1:0] BWEB,
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input wire mem_ctrl_bus_sd,
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input wire [64 -1:0] mem_ctrl_bus,
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input wire SD,
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input wire [1:0] RTSEL,
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input wire [1:0] WTSEL,
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output wire [WIDTH-1:0] Q
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);
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@ -24,10 +25,9 @@ wire [ADDR_WIDTH-1:0] sram_addr;
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wire [WIDTH-1:0] sram_rdata;
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wire [WIDTH-1:0] sram_wdata;
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wire SD = mem_ctrl_bus_sd;
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wire [2-1:0] RTSEL = mem_ctrl_bus[49:48];
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wire [2-1:0] WTSEL = mem_ctrl_bus[45:44];
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`ifdef USE_N12_TSMC_SRAM
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if(DEPTH==768 && WIDTH==94) begin : GEN_768x94_SRAM
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TS1N12FFCLLUVLTA768X94M4SWSHOCP U_TS1N12FFCLLUVLTA768X94M4SWSHOCP (
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@ -49,6 +49,7 @@ wire [2-1:0] WTSEL = mem_ctrl_bus[45:44];
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);
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end
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else begin : ILLEGAL_SRAM_SIZE
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$display("Error: Unsupported SRAM size %d x %d for TSMC N12 SRAM", WIDTH, DEPTH);
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end
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`elsif USE_N12_SNPS_SRAM
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@ -148,4 +149,4 @@ generate
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endgenerate
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endmodule
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endmodule: $moduleName$
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@ -25,6 +25,9 @@ wire [ADDR_WIDTH-1:0] sram_addr;
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wire [WIDTH-1:0] sram_rdata;
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wire [WIDTH-1:0] sram_wdata;
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wire [2-1:0] WTSEL = mem_ctrl_bus${WTselRange};
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`ifdef USE_N12_TSMC_SRAM
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if(DEPTH==${Depth} && WIDTH==${Width}) begin : GEN_${Depth}x${Width}_SRAM
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${ReferenceName} U_${ReferenceName} (
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Binary file not shown.
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After Width: | Height: | Size: 149 KiB |
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@ -2,34 +2,66 @@
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@[TOC](mem_mcu_wrap详细设计文档)
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# 1 mem_mcu_wrap top
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在这里为了TOP集成的自动化和效率，使用verilog-mode来集成；
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在这里为了TOP集成的自动化和效率，使用verilog-mode来集成；主要是进行顶层集成工作；
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## 1.1 总体功能概述
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`mem_mcu_wrap`模块是一个顶层模块，主要负责将Corelink子模块和其他多master、多slave进行集成连接起来，它的主要功能是如下所示：
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## 1.2 总体结构框图
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该mem_mcu_wrap的总体结构框图如下所示:
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通过上述框架结构图，可以明确知道：
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### 1.2.1 master
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master-0: Cortex-M3的I AHB总线
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master-1: Cortex-M3的D AHB总线
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master-2: Cortex-M3的S AHB总线
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master-3: cfg_noc_cfg_axi
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master-4: data_noc_cfg_axi
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## 1.3
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### 1.2.2 slave
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slave-0: IMEM的AHB总线
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slave-1: DMEM的AHB总线
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slave-2: peri的apb总线
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slave-3: apb的decoder总线
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# 2 Corelink子模块
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## 2.1 功能概述
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该Corelink是由AMBA_de工具生成的nic400 switch模块；
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## 1.3 Corelink子模块
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### 1.3.1 功能概述
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该Corelink是由AMBA_de工具生成的nic400 switch模块，用以连接多master仲裁连接访问多slave;
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## 2.2 地址分配
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### 1.3.2 路由关系
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路由连接关系可以通过上述总体结构框图中获得；；在这里不在进行表述；；在图中主要获得：：master和slave、、总线协议、、配置时钟关系；；
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### 1.3.3 地址分配
|
||||
在这里对slave访问的地址优先是统一寻址，，即使不是在进行连接Corelink前进行map映射转换；；在这里也给出map的逻辑；；
|
||||
|
||||
在这里原则上是：：要给出统一的slave寻址；；
|
||||
|
||||
## 2.3 结构框图
|
||||
### 1.3.4 生成switch示意图
|
||||
在这里可以通过AMBA_de工具生成的switch示意图，可以获得Corelink的详细连接关系；；
|
||||
|
||||
最后生成该RTL代码结构；；
|
||||
|
||||
## 2.4 设计详述
|
||||
## 1.4 Cortex-M3模块
|
||||
在这里M3处理器是直接复用mcu_system里面的M3；；
|
||||
Note:可能会遇到的问题是：：不知道输入的那些不明确含义的信号可能有什么问题，，在这里是参照mcu_system里面的默认赋值；；
|
||||
|
||||
# 3 记录问题
|
||||
## 1.5 peri_apb外设模块
|
||||
在这里peri_apb外设模块是直接复用mcu_system里面的peri_apb，，只保留了timer,uart,mailbox和watchDog；；
|
||||
|
||||
## 1.6 IMEM和DMEM sram模块
|
||||
在这里是使用cmsdk_ahb_sram标准模块，，来配置32KB的sram；；
|
||||
|
||||
|
||||
|
||||
# 2 mem_mcu_apb_deocder
|
||||
在这里是按照图示的右边三个模块来进行生成；；apb_decoder的依据还是根据M3的访问地址而来；；
|
||||
apb_decoder是参考top_apb_decoder来进行设计而来；；
|
||||
apb_2to1是直接拿来用的；；
|
||||
async2sync_apb_bridge是直接拿来用的；
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
# Verilog-mode使用
|
||||
## 1.1 变量范例使用
|
||||
# 3 Verilog-mode使用
|
||||
## 3.1 变量范例使用
|
||||
// Local Variables:
|
||||
// verilog-library-flags:("-y ./")
|
||||
// verilog-auto-inst-param-value:t
|
||||
|
|
@ -45,7 +77,7 @@
|
|||
// verilog-auto-output-ignore-regexp:"mem_ctrl_bus_\\|cfg_die_crd_\\|_info_tmp\\|"
|
||||
// End:
|
||||
|
||||
## 1.2 带参数例化使用
|
||||
## 3.2 带参数例化使用
|
||||
带参数的例化是在 (/*AUTOINST*/）中进行使用
|
||||
```v
|
||||
/* sub_block AUTO_TEMPLATE(
|
||||
|
|
|
|||
|
|
@ -1,7 +1,97 @@
|
|||
{ signal: [
|
||||
{name: "clk", wave:"p.........|..."},
|
||||
{name: "noc_vld", wave:"0.1...0|101"},
|
||||
{},
|
||||
{name: "noc_rdy", wave:"0.1...0|101"},
|
||||
|
||||
]}
|
||||
// {signal: [
|
||||
// {name: 'clk', wave: 'p.....|...'},
|
||||
// {name: 'clk1', wave: 'p..P..|...', period: 2 },
|
||||
// {name: 'clk4', wave: 'n..N..|...', phase: -1 },
|
||||
// {name: 'dat', wave: 'x.345x|=.x', data: ['head', 'body', 'tail', 'data']},
|
||||
// {name: 'req', wave: '0.1..0|1.0'},
|
||||
// {},
|
||||
// {name: 'ack', wave: '1.....|01.'}
|
||||
// ]}
|
||||
|
||||
// {signal: [
|
||||
// {name: 'clk', wave: 'p...........|..'},
|
||||
// {name: 'noc_req_vld', wave: '0.10...10...'},
|
||||
// {name: 'noc_req_flit[63:0]', wave: 'x.2....4....', data: ['req_flit_1','req_flit_2' ]},
|
||||
// {name: 'noc_req_rdy', wave: '1..0..1.0..1'},
|
||||
// {},
|
||||
// {name: 'noc_rsp_vld', wave: '0...10....10...'},
|
||||
// {name: 'noc_rsp_flit[63:0]', wave: 'x...2....4....', data: ['rsp_flit_1','rsp_flit_2' ]},
|
||||
// {name: 'noc_rsp_rdy', wave: '1...0..1...0.1'},
|
||||
//
|
||||
// ]}
|
||||
|
||||
{signal: [
|
||||
{name: 'clk', wave: 'p..P.........|...'},
|
||||
['cfg_noc_req',
|
||||
{name: 'noc_req_rdy', wave: 'x1.0.....1..0..10',node:'.........f.....i'},
|
||||
{name: 'noc_req_vld', wave: 'x010.......10...',node:'..0........1.'},
|
||||
{name: 'noc_req_flit[63:0]', wave: 'x.2........4....', data: ['req_flit_wr','req_flit_rd' ]},
|
||||
{},
|
||||
],
|
||||
//AXI AW Channel
|
||||
['AXI_AW_CH',
|
||||
{name: 'axi_awready', wave: 'x0..1..0.1...', node:'....a...'},
|
||||
{name: 'axi_awvalid', wave: 'x0....10....00..', node: '......c'},
|
||||
{name: 'axi_awaddr[31:0]', wave: 'x..3.......2....', data: ['awaddr_1','' ]},
|
||||
{name: 'axi_awlen[7:0]', wave: 'x.2...........',data: ['8b0']},
|
||||
{name: 'axi_awsize[2:0]', wave: 'x.2...........',data: ['3b100']},
|
||||
{name: 'axi_burst[1:0]', wave: 'x.2...........',data: ['2b01']},
|
||||
{},
|
||||
],
|
||||
//AXI W Channel
|
||||
['AXI_W_CH',
|
||||
{name: 'axi_wready', wave: 'x.0..1.01....', node:'.....b'},
|
||||
{name: 'axi_wvalid', wave: 'x.0...10......',node:'......d'},
|
||||
{name: 'axi_wdata[31:0]' , wave: 'x..4....=.....', data: ['wdata_1']},
|
||||
{name: 'axi_wstrb[3:0]', wave: 'x.2......',data: ['4b1111']},
|
||||
{name: 'axi_wlast' , wave: 'x.1...........'},
|
||||
],
|
||||
{},
|
||||
//AXI B Channel
|
||||
['AXI_B_CH',
|
||||
{name: 'axi_bready', wave: 'x.1.........'},
|
||||
{name: 'axi_bvalid', wave: 'x.0.....10..',node:'........e'},
|
||||
{name: 'axi_bid', wave: 'x.2.........',data:['4b0000']},
|
||||
{name: 'axi_bresp[1:0]', wave: 'x.2........', data: ['bresp',]},
|
||||
{},
|
||||
],
|
||||
//AXI AR Channel
|
||||
['AXI_AR_CH',
|
||||
{name: 'axi_arready', wave: 'x.1............0.'},
|
||||
{name: 'axi_arvalid', wave: 'x.0...........10',node:'..............g'},
|
||||
{name: 'axi_araddr[31:0]', wave: 'x..3.........2..', data: ['araddr_1','araddr_2']},
|
||||
{name: 'axi_arid[3:0]', wave:'x.=.............',data: ['4b0000']},
|
||||
{name: 'axi_arlen[7:0]', wave: 'x.2.............',data: ['8b0']},
|
||||
{name: 'axi_arsize[2:0]', wave:'x.2.............',data: ['3b100']},
|
||||
{name: 'axi_arburst[1:0]', wave: 'x.2.............',data: ['2b01']},
|
||||
{},
|
||||
],
|
||||
//AXI R Channel
|
||||
['AXI_R_CH',
|
||||
{name: 'axi_rready', wave: 'x.1..............'},
|
||||
{name: 'axi_rvalid', wave: 'x.0............10',node:'...............h'},
|
||||
{name: 'axi_rid[3:0]', wave: 'x.2..............',data:['4b0000']},
|
||||
{name: 'axi_rdata[31:0]', wave: 'x..............2.', data: ['rdata_1','rdata_2']},
|
||||
{name: 'axi_rlast', wave: 'x.1.............'},
|
||||
{name: 'axi_rresp[1:0]', wave: 'x.x............2.', data: ['rresp']},
|
||||
],
|
||||
|
||||
|
||||
],
|
||||
|
||||
//--edge
|
||||
edge: [
|
||||
'a~->b','b~->c', 'b~->d','e~->f','1~->g','g~->h','h~>i'
|
||||
],
|
||||
|
||||
head: {
|
||||
text: "cfg_noc_write_and_read",
|
||||
tick: 0,
|
||||
},
|
||||
|
||||
//foot: {
|
||||
// text:"classic_cfg_noc_2_AXI_write",
|
||||
//}
|
||||
|
||||
}
|
||||
|
|
@ -0,0 +1,281 @@
|
|||
module axi_demux_1to2 (
|
||||
input wire clk,
|
||||
input wire rst_n,
|
||||
|
||||
// External selection signals
|
||||
input wire aw_sel, // 0: m0, 1: m1
|
||||
input wire ar_sel, // 0: m0, 1: m1
|
||||
|
||||
// Master interface (s_*)
|
||||
// Write Address Channel
|
||||
input wire [31:0] s_awaddr,
|
||||
input wire [7:0] s_awlen,
|
||||
input wire [2:0] s_awsize,
|
||||
input wire [1:0] s_awburst,
|
||||
input wire s_awvalid,
|
||||
output wire s_awready,
|
||||
|
||||
// Write Data Channel
|
||||
input wire [31:0] s_wdata,
|
||||
input wire [3:0] s_wstrb,
|
||||
input wire s_wlast,
|
||||
input wire s_wvalid,
|
||||
output wire s_wready,
|
||||
|
||||
// Write Response Channel
|
||||
output wire [1:0] s_bresp,
|
||||
output wire s_bvalid,
|
||||
input wire s_bready,
|
||||
|
||||
// Read Address Channel
|
||||
input wire [31:0] s_araddr,
|
||||
input wire [7:0] s_arlen,
|
||||
input wire [2:0] s_arsize,
|
||||
input wire [1:0] s_arburst,
|
||||
input wire s_arvalid,
|
||||
output wire s_arready,
|
||||
|
||||
// Read Data Channel
|
||||
output wire [31:0] s_rdata,
|
||||
output wire [1:0] s_rresp,
|
||||
output wire s_rlast,
|
||||
output wire s_rvalid,
|
||||
input wire s_rready,
|
||||
|
||||
// Slave 0 interface (m0_*)
|
||||
// Write Address Channel
|
||||
output wire [31:0] m0_awaddr,
|
||||
output wire [7:0] m0_awlen,
|
||||
output wire [2:0] m0_awsize,
|
||||
output wire [1:0] m0_awburst,
|
||||
output wire m0_awvalid,
|
||||
input wire m0_awready,
|
||||
|
||||
// Write Data Channel
|
||||
output wire [31:0] m0_wdata,
|
||||
output wire [3:0] m0_wstrb,
|
||||
output wire m0_wlast,
|
||||
output wire m0_wvalid,
|
||||
input wire m0_wready,
|
||||
|
||||
// Write Response Channel
|
||||
input wire [1:0] m0_bresp,
|
||||
input wire m0_bvalid,
|
||||
output wire m0_bready,
|
||||
|
||||
// Read Address Channel
|
||||
output wire [31:0] m0_araddr,
|
||||
output wire [7:0] m0_arlen,
|
||||
output wire [2:0] m0_arsize,
|
||||
output wire [1:0] m0_arburst,
|
||||
output wire m0_arvalid,
|
||||
input wire m0_arready,
|
||||
|
||||
// Read Data Channel
|
||||
input wire [31:0] m0_rdata,
|
||||
input wire [1:0] m0_rresp,
|
||||
input wire m0_rlast,
|
||||
input wire m0_rvalid,
|
||||
output wire m0_rready,
|
||||
|
||||
// Slave 1 interface (m1_*)
|
||||
// Write Address Channel
|
||||
output wire [31:0] m1_awaddr,
|
||||
output wire [7:0] m1_awlen,
|
||||
output wire [2:0] m1_awsize,
|
||||
output wire [1:0] m1_awburst,
|
||||
output wire m1_awvalid,
|
||||
input wire m1_awready,
|
||||
|
||||
// Write Data Channel
|
||||
output wire [31:0] m1_wdata,
|
||||
output wire [3:0] m1_wstrb,
|
||||
output wire m1_wlast,
|
||||
output wire m1_wvalid,
|
||||
input wire m1_wready,
|
||||
|
||||
// Write Response Channel
|
||||
input wire [1:0] m1_bresp,
|
||||
input wire m1_bvalid,
|
||||
output wire m1_bready,
|
||||
|
||||
// Read Address Channel
|
||||
output wire [31:0] m1_araddr,
|
||||
output wire [7:0] m1_arlen,
|
||||
output wire [2:0] m1_arsize,
|
||||
output wire [1:0] m1_arburst,
|
||||
output wire m1_arvalid,
|
||||
input wire m1_arready,
|
||||
|
||||
// Read Data Channel
|
||||
input wire [31:0] m1_rdata,
|
||||
input wire [1:0] m1_rresp,
|
||||
input wire m1_rlast,
|
||||
input wire m1_rvalid,
|
||||
output wire m1_rready
|
||||
);
|
||||
|
||||
//-------------------------------------------------------------------------
|
||||
// Write Channel Control Logic
|
||||
//-------------------------------------------------------------------------
|
||||
reg aw_active; // Active write transaction
|
||||
reg aw_sel_reg; // Registered selection for write data path
|
||||
wire aw_handshake = s_awvalid & s_awready;
|
||||
wire w_handshake = s_wvalid & s_wready;
|
||||
|
||||
// AW channel
|
||||
assign s_awready = ~aw_active & (aw_sel ? m1_awready : m0_awready);
|
||||
assign m0_awvalid = ~aw_sel & s_awvalid & ~aw_active;
|
||||
assign m1_awvalid = aw_sel & s_awvalid & ~aw_active;
|
||||
|
||||
// AW selection and active flag
|
||||
always @(posedge clk or negedge rst_n) begin
|
||||
if (!rst_n) begin
|
||||
aw_active <= 1'b0;
|
||||
aw_sel_reg <= 1'b0;
|
||||
end else begin
|
||||
if (aw_handshake) begin
|
||||
aw_active <= 1'b1;
|
||||
aw_sel_reg <= aw_sel;
|
||||
end else if (w_handshake && s_wlast) begin
|
||||
aw_active <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// W channel (routed based on registered selection)
|
||||
assign m0_wdata = s_wdata;
|
||||
assign m0_wstrb = s_wstrb;
|
||||
assign m0_wlast = s_wlast;
|
||||
assign m0_wvalid = ~aw_sel_reg & aw_active & s_wvalid;
|
||||
|
||||
assign m1_wdata = s_wdata;
|
||||
assign m1_wstrb = s_wstrb;
|
||||
assign m1_wlast = s_wlast;
|
||||
assign m1_wvalid = aw_sel_reg & aw_active & s_wvalid;
|
||||
|
||||
assign s_wready = aw_sel_reg ? (m1_wready & aw_active) : (m0_wready & aw_active);
|
||||
|
||||
//-------------------------------------------------------------------------
|
||||
// Read Address Channel (direct routing)
|
||||
//-------------------------------------------------------------------------
|
||||
assign s_arready = ar_sel ? m1_arready : m0_arready;
|
||||
assign m0_arvalid = ~ar_sel & s_arvalid;
|
||||
assign m1_arvalid = ar_sel & s_arvalid;
|
||||
|
||||
assign m0_araddr = s_araddr;
|
||||
assign m0_arlen = s_arlen;
|
||||
assign m0_arsize = s_arsize;
|
||||
assign m0_arburst = s_arburst;
|
||||
|
||||
assign m1_araddr = s_araddr;
|
||||
assign m1_arlen = s_arlen;
|
||||
assign m1_arsize = s_arsize;
|
||||
assign m1_arburst = s_arburst;
|
||||
|
||||
//-------------------------------------------------------------------------
|
||||
// Read Data Channel Arbitration (Round Robin)
|
||||
//-------------------------------------------------------------------------
|
||||
reg r_active; // Active read transaction
|
||||
reg r_sel_reg; // Current selected slave (0:m0, 1:m1)
|
||||
reg r_arb_state; // RR arbitration state
|
||||
wire r_handshake = s_rvalid & s_rready;
|
||||
wire r_finish = r_handshake & s_rlast;
|
||||
|
||||
// Arbitration and selection logic
|
||||
wire [1:0] r_request = {m1_rvalid, m0_rvalid};
|
||||
wire r_grant;
|
||||
|
||||
round_robin_arb #(.WIDTH(2)) r_arb (
|
||||
.clk (clk),
|
||||
.rst_n (rst_n),
|
||||
.enable (~r_active), // Only arbitrate when not active
|
||||
.request (r_request),
|
||||
.grant (r_grant)
|
||||
);
|
||||
|
||||
always @(posedge clk or negedge rst_n) begin
|
||||
if (!rst_n) begin
|
||||
r_active <= 1'b0;
|
||||
r_sel_reg <= 1'b0;
|
||||
end else begin
|
||||
if (~r_active && |r_request) begin
|
||||
r_active <= 1'b1;
|
||||
r_sel_reg <= r_grant; // 0 for m0, 1 for m1
|
||||
end else if (r_finish) begin
|
||||
r_active <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// Mux for read data channel
|
||||
assign s_rdata = r_sel_reg ? m1_rdata : m0_rdata;
|
||||
assign s_rresp = r_sel_reg ? m1_rresp : m0_rresp;
|
||||
assign s_rlast = r_sel_reg ? m1_rlast : m0_rlast;
|
||||
assign s_rvalid = r_sel_reg ? m1_rvalid : m0_rvalid;
|
||||
|
||||
assign m0_rready = (~r_sel_reg) & s_rready;
|
||||
assign m1_rready = r_sel_reg & s_rready;
|
||||
|
||||
//-------------------------------------------------------------------------
|
||||
// Write Response Arbitration (Round Robin)
|
||||
//-------------------------------------------------------------------------
|
||||
reg b_arb_state; // RR arbitration state
|
||||
wire [1:0] b_request = {m1_bvalid, m0_bvalid};
|
||||
wire b_grant;
|
||||
|
||||
round_robin_arb #(.WIDTH(2)) b_arb (
|
||||
.clk (clk),
|
||||
.rst_n (rst_n),
|
||||
.enable (1'b1), // Always arbitrate
|
||||
.request (b_request),
|
||||
.grant (b_grant)
|
||||
);
|
||||
|
||||
// Mux for write response channel
|
||||
assign s_bresp = b_grant ? m1_bresp : m0_bresp;
|
||||
assign s_bvalid = b_grant ? m1_bvalid : m0_bvalid;
|
||||
|
||||
assign m0_bready = (~b_grant) & s_bready;
|
||||
assign m1_bready = b_grant & s_bready;
|
||||
|
||||
endmodule
|
||||
|
||||
//-------------------------------------------------------------------------
|
||||
// Round Robin Arbiter Module
|
||||
//-------------------------------------------------------------------------
|
||||
module round_robin_arb #(
|
||||
parameter WIDTH = 2
|
||||
)(
|
||||
input wire clk,
|
||||
input wire rst_n,
|
||||
input wire enable, // Arbitration enable
|
||||
input wire [WIDTH-1:0] request, // Request vector
|
||||
output reg [WIDTH-1:0] grant // One-hot grant
|
||||
);
|
||||
|
||||
reg [WIDTH-1:0] pointer;
|
||||
|
||||
always @(posedge clk or negedge rst_n) begin
|
||||
if (!rst_n) begin
|
||||
pointer <= 1;
|
||||
end else if (enable && |request) begin
|
||||
pointer <= {pointer[0], pointer[WIDTH-1:1]}; // Rotate right
|
||||
end
|
||||
end
|
||||
|
||||
// Grant generation
|
||||
always @(*) begin
|
||||
grant = {WIDTH{1'b0}};
|
||||
if (|request) begin
|
||||
for (int i = 0; i < WIDTH; i++) begin
|
||||
int idx = (i + pointer) % WIDTH;
|
||||
if (request[idx]) begin
|
||||
grant = (1 << idx);
|
||||
break;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
|
||||
@[TOC](cfg_noc bridge详细设计文档)
|
||||
|
||||
# cfg_noc_bridge
|
||||
## 1.1 TOP总体功能概述
|
||||
该模块用于实现将cfg_noc的配置bus总线来转化成AXI总线进行发出,整体实现一个bridge功能；；
|
||||
|
||||
|
||||
## 1.2模块接口
|
||||
### 1.2.1 cfg_noc测接口
|
||||
在这里可以看到cfg_Noc测请求接口和rsp侧接口；
|
||||
|
||||
|
||||
### 1.2.2 AXI4接口
|
||||
转换测的接口为标准的AXI4接口;在这里不做展示；；
|
||||
|
||||
|
||||
## 1.2.3 写时序
|
||||
|
||||
|
||||
## 1.2.4 读时序
|
||||
|
||||
|
||||
## 1.3 模块结构
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
# axi_2_apb_bridg
|
||||
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Reference in New Issue