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ci the template_sram_sp_wrap

This commit is contained in:
leeyunlong 2025-06-23 15:21:35 +08:00
parent a1e40696c4
commit 81a438f142
5 changed files with 34 additions and 15 deletions
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9
Scripts/gen_sram_wrap/template_sram_sp_wrap.v
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@ -11,9 +11,8 @@ module ${SramWrapName} #(
input wire [$clog2(DEPTH)-1:0] A,
input wire [WIDTH-1:0] D,
input wire [WIDTH-1:0] BWEB,
input wire SD,
input wire [1:0] RTSEL,
input wire [1:0] WTSEL,
input wire mem_ctrl_sd,
input wire [64 -1:0] mem_ctrl_bus,
output wire [WIDTH-1:0] Q
);
@ -25,6 +24,10 @@ wire [ADDR_WIDTH-1:0] sram_addr;
wire [WIDTH-1:0] sram_rdata;
wire [WIDTH-1:0] sram_wdata;
wire SD = mem_ctrl_sd;
wire [2-1:0] RTSEL = mem_ctrl_bus[49:48];
wire [2-1:0] WTSEL = mem_ctrl_bus[45:44];
`ifdef USE_N12_TSMC_SRAM
if(DEPTH==${Depth} && WIDTH==${Width}) begin : GEN_${Depth}x${Width}_SRAM
${ReferenceName} U_${ReferenceName} (

10
Scripts/gen_sram_wrap/template_sram_sp_wrap_asmbly.v
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@ -11,9 +11,8 @@ module ${SramWrapName} #(
input wire [$clog2(DEPTH)-1:0] A,
input wire [WIDTH-1:0] D,
input wire [WIDTH-1:0] BWEB,
input wire SD,
input wire [1:0] RTSEL,
input wire [1:0] WTSEL,
input wire mem_ctrl_sd,
input wire [64 -1:0] mem_ctrl_bus,
output wire [WIDTH-1:0] Q
);
@ -33,6 +32,11 @@ localparam COMPILE_WIDTH = ${CompileWidth};
localparam ADDR_COMPILE_WIDTH = $clog2(COMPILE_DEPTH);
wire SD = mem_ctrl_sd;
wire [2-1:0] RTSEL = mem_ctrl_bus[49:48];
wire [2-1:0] WTSEL = mem_ctrl_bus[45:44];
`ifdef USE_N12_TSMC_SRAM
wire[ASSEMBLY_DEPTH_NUMS - 1:] sram_ceb_sub;

11
Scripts/gen_sram_wrap/template_sram_tp_wrap.v
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@ -13,10 +13,8 @@ module ${SramWrapName} #(
input wire REB, // Read Enable, Active-low
input wire [$clog2(DEPTH)-1:0] AB, // Read Address
input wire SD,
input wire [1:0] RTSEL,
input wire [1:0] WTSEL,
input wire [1:0] MTSEL,
input wire mem_ctrl_sd,
input wire mem_ctrl_bus,
output wire [WIDTH-1:0] Q // Read Data Output
);
@ -31,6 +29,11 @@ module ${SramWrapName} #(
wire [ADDR_WIDTH-1:0] sram_raddr;
wire [WIDTH-1:0] sram_rdata;
wire SD = mem_ctrl_sd;
wire [2 -1:0] RTSEL = mem_ctrl_bus[63:62];
wire [2 -1:0] MTSEL = mem_ctrl_bus[59:58];
wire [2 -1:0] WTSEL = mem_ctrl_bus[55:54];
`ifdef USE_N12_TSMC_SRAM
generate
if(DEPTH==${Depth} && WIDTH==${Width}) begin : GEN_${Depth}X${Width}_SRAM

12
Scripts/gen_sram_wrap/template_sram_tp_wrap_asmbly.v
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@ -13,14 +13,11 @@ module ${SramWrapName} #(
input wire REB, // Read Enable, Active-low
input wire [$clog2(DEPTH)-1:0] AB, // Read Address
input wire SD,
input wire [1:0] RTSEL,
input wire [1:0] WTSEL,
input wire [1:0] MTSEL,
input wire mem_ctrl_sd,
input wire mem_ctrl_bus,
output wire [WIDTH-1:0] Q // Read Data Output
);
localparam ADDR_WIDTH = $clog2(DEPTH);
wire sram_web;
@ -38,6 +35,11 @@ module ${SramWrapName} #(
localparam ADDR_COMPILE_WIDTH = $clog2(COMPILE_DEPTH);
wire SD = mem_ctrl_sd;
wire [2 -1:0] RTSEL = mem_ctrl_bus[63:62];
wire [2 -1:0] MTSEL = mem_ctrl_bus[59:58];
wire [2 -1:0] WTSEL = mem_ctrl_bus[55:54];
`ifdef USE_N12_TSMC_SRAM
wire[ASSEMBLY_DEPTH_NUMS - 1:0] sram_web_sub;

7
rtl/cfg_noc_bridge/cfg_noc_axi_bridge.json Normal file
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@ -0,0 +1,7 @@
{ signal: [
{name: "clk", wave:"p.........|..."},
{name: "noc_vld", wave:"0.1...0|101"},
{},
{name: "noc_rdy", wave:"0.1...0|101"},
]}