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ci the gen_sram_wrap.py

This commit is contained in:
leeyunlong 2025-06-19 09:11:47 +08:00
parent 0f1b7a9e24
commit 9ae9bc0215
13 changed files with 1338 additions and 8 deletions
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2
Scripts/do_apb_file.py
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@ -299,7 +299,7 @@ def parse_bits_sequences(file_path, sheet_name):
##############################################################################
if __name__ == "__main__":
check()
file_path = sys.argv[1]
file_path = sys.argv[1]
book = xlrd.open_workbook(file_path)
sheets_num = len(book.sheet_names())
print("This is OK,sheets_num is : %d" % sheets_num)

108
Scripts/gen_sram_wrap/gen_sram_wrap.py
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@ -0,0 +1,108 @@
import argparse
import sys
import xlrd
import os
def parse_args():
"""解析命令行参数"""
parser = argparse.ArgumentParser(description='Generate SRAM wrapper verilog files')
parser.add_argument('xls_file', help='Excel configuration file path')
parser.add_argument('-name', help='Specify sheet name to process')
return parser.parse_args()
def validate_sheet(rb, sheet_name):
"""验证Sheet是否存在"""
try:
return rb.sheet_by_name(sheet_name)
except xlrd.biffh.XLRDError:
print(f"[Error] Sheet '{sheet_name}' not found in {rb}")
sys.exit(1)
def generate_files(xls_path, sheet_name=None):
"""主生成函数"""
rb = xlrd.open_workbook(xls_path)
# 处理Sheet选择逻辑
sheets = [rb.sheet_by_name(sheet_name)] if sheet_name else rb.sheets()
for sheet in sheets:
# 获取列索引（根据模板参数）
headers = sheet.row_values(1)
col_map = {
'name' : headers.index('SramWrapName'),
'width': headers.index('Width'),
'depth': headers.index('Depth'),
'ref' : headers.index('ReferenceName'),
'port' : headers.index('PortType'),
'AssemblyDepth' : headers.index('AssemblyDepth'),
'AssemblyWidth' : headers.index('AssemblyWidth')
}
print(f"Processing sheet: {sheet.name} with columns: {col_map}")
# 创建输出目录
output_dir = f"output_{sheet.name}"
os.makedirs(output_dir, exist_ok=True)
# 处理每行数据
for row_idx in range(2, sheet.nrows):
row = sheet.row_values(row_idx)
# is Assembly or not
if int(row[col_map['AssemblyDepth']]) * int(row[col_map['AssemblyWidth']]) > 1:
print(f"[Note:Assembly] AssemblyDepth is {row[col_map['AssemblyDepth']]} and AssemblyWidth is {row[col_map['AssemblyWidth']]} in row {row_idx}, skipping.")
continue
# sp or tp
if row[col_map['port']] == 'SP':
print(f"Generating SRAM_SP wrapper for: {row[col_map['name']]}")
# 调用生成函数
generate_sram_wrapper(
# input file_path
template_file = 'template_sram_sp_wrap.v',
sram_name = row[col_map['name']],
width = int(row[col_map['width']]),
depth = int(row[col_map['depth']]),
ref_name = row[col_map['ref']],
output_dir = output_dir
)
elif row[col_map['port']] == 'TP':
print(f"Generating SRAM_TP wrapper for: {row[col_map['name']]} (TP)")
# 调用生成函数
generate_sram_wrapper(
template_file = 'template_sram_tp_wrap.v',
sram_name = row[col_map['name']],
width = int(row[col_map['width']]),
depth = int(row[col_map['depth']]),
ref_name = row[col_map['ref']],
output_dir = output_dir
)
else:
print(f"[Warning] Unknown port type '{row[col_map['port']]}' in row {row_idx}, skipping.")
continue
def generate_sram_wrapper(template_file, sram_name, width, depth, ref_name, output_dir):
"""生成单个SRAM包装文件"""
with open(template_file, 'r') as f:
template = f.read()
# 执行模板替换（根据您提供的模板结构）
replaced = template.replace('${SramWrapName}', sram_name)\
.replace('${Width}', str(width))\
.replace('${Depth}', str(depth))\
.replace('${ReferenceName}', ref_name)
# 写入输出文件
output_path = f"{output_dir}/{sram_name}.v"
with open(output_path, 'w') as f:
f.write(replaced)
if __name__ == "__main__":
args = parse_args()
# 必须参数检查
if not os.path.exists(args.xls_file):
print(f"[Error] File not found: {args.xls_file}")
sys.exit(1)
generate_files(args.xls_file, args.name)

BIN
Scripts/gen_sram_wrap/mem_list.xls
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149
Scripts/gen_sram_wrap/output_pcie/sram_sp_pcie_2048x112.v Normal file
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@ -0,0 +1,149 @@
module sram_sp_pcie_2048x112 #(
parameter WIDTH = 112,
parameter DEPTH = 2048,
parameter IN_PIPE = 0,
parameter OUT_PIPE = 1
)(
input wire CLK,
input wire CEB,
input wire WEB,
input wire [$clog2(DEPTH)-1:0] A,
input wire [WIDTH-1:0] D,
input wire [WIDTH-1:0] BWEB,
input wire SD,
input wire [1:0] RTSEL,
input wire [1:0] WTSEL,
output wire [WIDTH-1:0] Q
);
localparam ADDR_WIDTH = $clog2(DEPTH);
wire sram_ceb;
wire sram_web;
wire [WIDTH-1:0] sram_bweb;
wire [ADDR_WIDTH-1:0] sram_addr;
wire [WIDTH-1:0] sram_rdata;
wire [WIDTH-1:0] sram_wdata;
`ifdef USE_N12_TSMC_SRAM
if(DEPTH==2048 && WIDTH==112) begin : GEN_2048x112_SRAM
TS1N12FFCLLSBULVTE2048X112WS4UWHSOCP U_TS1N12FFCLLSBULVTE2048X112WS4UWHSOCP (
.CLK (CLK),
.CEB (sram_ceb),
.WEB (sram_web),
.BWEB (sram_bweb),
.A (sram_addr),
.D (sram_wdata),
.Q (sram_rdata),
.SLP (1'b0),
.DSLP (1'b0),
.SD (SD),
.RTSEL (RTSEL),
.WTSEL (WTSEL),
.FADIO (9'b0),
.REDENIO (1'b0),
.PUDELAY ( )
);
end
else begin : ILLEGAL_SRAM_SIZE
$display("Error: Unsupported SRAM size %d x %d for TSMC N12 SRAM", WIDTH, DEPTH);
end
`elsif USE_N12_SNPS_SRAM
`elsif USE_N7_TSMC_SRAM
`elsif USE_N7_SNPS_SRAM
`else
reg [WIDTH-1:0] ram [DEPTH-1:0];
reg [WIDTH-1:0] rdata_ff;
integer i;
always @(posedge CLK) begin
if (CEB == 1'b0) begin
if (WEB == 1'b0) begin // write
for (i = 0; i < WIDTH; i = i + 1) begin
if (BWEB[i] == 1'b0) ram[A][i] <= D[i];
end
end
else begin // read
rdata_ff <= ram[A];
end
end
end
assign sram_rdata = rdata_ff;
`endif
// Input PIPE
generate
if(IN_PIPE==1) begin : GEN_IN_PIPE_1
reg ceb_ff;
reg web_ff;
reg [WIDTH-1:0] bweb_ff;
reg [ADDR_WIDTH-1:0] a_ff;
reg [WIDTH-1:0] d_ff;
always @(posedge CLK) begin
if(CEB==1'b0) begin
ceb_ff <= 1'b0;
web_ff <= WEB;
bweb_ff <= BWEB;
a_ff <= A;
d_ff <= D;
end
else begin
ceb_ff <= 1'b1;
end
end
assign sram_ceb = ceb_ff;
assign sram_web = web_ff;
assign sram_bweb = bweb_ff;
assign sram_addr = a_ff;
assign sram_wdata = d_ff;
end
else begin : GEN_IN_PIPE_0
assign sram_ceb = CEB;
assign sram_web = WEB;
assign sram_bweb = BWEB;
assign sram_addr = A;
assign sram_wdata = D;
end
endgenerate
// Output PIPE
generate
if(OUT_PIPE==1) begin : GEN_OUT_PIPE_1
reg sram_ren_ff;
reg [WIDTH-1:0] sram_rdata_ff;
always @(posedge CLK) begin
if(CEB==1'b0 && WEB==1'b1) begin
sram_ren_ff <= 1'b1; // flag indicating read operation
end
else begin
sram_ren_ff <= 1'b0;
end
end
always @(posedge CLK) begin
if(sram_ren_ff==1'b1) begin
sram_rdata_ff <= sram_rdata; // latch read data
end
else begin
sram_rdata_ff <= sram_rdata_ff;
end
end
assign Q = sram_rdata_ff; // output latched data
end
else begin : GEN_OUT_PIPE_0
assign Q = sram_rdata; // direct output
end
endgenerate
endmodule: $moduleName$

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Scripts/gen_sram_wrap/output_pcie/sram_sp_pcie_256x34.v Normal file
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@ -0,0 +1,149 @@
module sram_sp_pcie_256x34 #(
parameter WIDTH = 34,
parameter DEPTH = 256,
parameter IN_PIPE = 0,
parameter OUT_PIPE = 1
)(
input wire CLK,
input wire CEB,
input wire WEB,
input wire [$clog2(DEPTH)-1:0] A,
input wire [WIDTH-1:0] D,
input wire [WIDTH-1:0] BWEB,
input wire SD,
input wire [1:0] RTSEL,
input wire [1:0] WTSEL,
output wire [WIDTH-1:0] Q
);
localparam ADDR_WIDTH = $clog2(DEPTH);
wire sram_ceb;
wire sram_web;
wire [WIDTH-1:0] sram_bweb;
wire [ADDR_WIDTH-1:0] sram_addr;
wire [WIDTH-1:0] sram_rdata;
wire [WIDTH-1:0] sram_wdata;
`ifdef USE_N12_TSMC_SRAM
if(DEPTH==256 && WIDTH==34) begin : GEN_256x34_SRAM
TS1N12FFCLLUVLTA256X34M2SWSHOCP U_TS1N12FFCLLUVLTA256X34M2SWSHOCP (
.CLK (CLK),
.CEB (sram_ceb),
.WEB (sram_web),
.BWEB (sram_bweb),
.A (sram_addr),
.D (sram_wdata),
.Q (sram_rdata),
.SLP (1'b0),
.DSLP (1'b0),
.SD (SD),
.RTSEL (RTSEL),
.WTSEL (WTSEL),
.FADIO (9'b0),
.REDENIO (1'b0),
.PUDELAY ( )
);
end
else begin : ILLEGAL_SRAM_SIZE
$display("Error: Unsupported SRAM size %d x %d for TSMC N12 SRAM", WIDTH, DEPTH);
end
`elsif USE_N12_SNPS_SRAM
`elsif USE_N7_TSMC_SRAM
`elsif USE_N7_SNPS_SRAM
`else
reg [WIDTH-1:0] ram [DEPTH-1:0];
reg [WIDTH-1:0] rdata_ff;
integer i;
always @(posedge CLK) begin
if (CEB == 1'b0) begin
if (WEB == 1'b0) begin // write
for (i = 0; i < WIDTH; i = i + 1) begin
if (BWEB[i] == 1'b0) ram[A][i] <= D[i];
end
end
else begin // read
rdata_ff <= ram[A];
end
end
end
assign sram_rdata = rdata_ff;
`endif
// Input PIPE
generate
if(IN_PIPE==1) begin : GEN_IN_PIPE_1
reg ceb_ff;
reg web_ff;
reg [WIDTH-1:0] bweb_ff;
reg [ADDR_WIDTH-1:0] a_ff;
reg [WIDTH-1:0] d_ff;
always @(posedge CLK) begin
if(CEB==1'b0) begin
ceb_ff <= 1'b0;
web_ff <= WEB;
bweb_ff <= BWEB;
a_ff <= A;
d_ff <= D;
end
else begin
ceb_ff <= 1'b1;
end
end
assign sram_ceb = ceb_ff;
assign sram_web = web_ff;
assign sram_bweb = bweb_ff;
assign sram_addr = a_ff;
assign sram_wdata = d_ff;
end
else begin : GEN_IN_PIPE_0
assign sram_ceb = CEB;
assign sram_web = WEB;
assign sram_bweb = BWEB;
assign sram_addr = A;
assign sram_wdata = D;
end
endgenerate
// Output PIPE
generate
if(OUT_PIPE==1) begin : GEN_OUT_PIPE_1
reg sram_ren_ff;
reg [WIDTH-1:0] sram_rdata_ff;
always @(posedge CLK) begin
if(CEB==1'b0 && WEB==1'b1) begin
sram_ren_ff <= 1'b1; // flag indicating read operation
end
else begin
sram_ren_ff <= 1'b0;
end
end
always @(posedge CLK) begin
if(sram_ren_ff==1'b1) begin
sram_rdata_ff <= sram_rdata; // latch read data
end
else begin
sram_rdata_ff <= sram_rdata_ff;
end
end
assign Q = sram_rdata_ff; // output latched data
end
else begin : GEN_OUT_PIPE_0
assign Q = sram_rdata; // direct output
end
endgenerate
endmodule: $moduleName$

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Scripts/gen_sram_wrap/output_pcie/sram_sp_pcie_4608x72.v Normal file
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module sram_sp_pcie_4608x72 #(
parameter WIDTH = 72,
parameter DEPTH = 4608,
parameter IN_PIPE = 0,
parameter OUT_PIPE = 1
)(
input wire CLK,
input wire CEB,
input wire WEB,
input wire [$clog2(DEPTH)-1:0] A,
input wire [WIDTH-1:0] D,
input wire [WIDTH-1:0] BWEB,
input wire SD,
input wire [1:0] RTSEL,
input wire [1:0] WTSEL,
output wire [WIDTH-1:0] Q
);
localparam ADDR_WIDTH = $clog2(DEPTH);
wire sram_ceb;
wire sram_web;
wire [WIDTH-1:0] sram_bweb;
wire [ADDR_WIDTH-1:0] sram_addr;
wire [WIDTH-1:0] sram_rdata;
wire [WIDTH-1:0] sram_wdata;
`ifdef USE_N12_TSMC_SRAM
if(DEPTH==4608 && WIDTH==72) begin : GEN_4608x72_SRAM
TS1N12FFCLLUVLTA4608X72M8SWSHOCP U_TS1N12FFCLLUVLTA4608X72M8SWSHOCP (
.CLK (CLK),
.CEB (sram_ceb),
.WEB (sram_web),
.BWEB (sram_bweb),
.A (sram_addr),
.D (sram_wdata),
.Q (sram_rdata),
.SLP (1'b0),
.DSLP (1'b0),
.SD (SD),
.RTSEL (RTSEL),
.WTSEL (WTSEL),
.FADIO (9'b0),
.REDENIO (1'b0),
.PUDELAY ( )
);
end
else begin : ILLEGAL_SRAM_SIZE
$display("Error: Unsupported SRAM size %d x %d for TSMC N12 SRAM", WIDTH, DEPTH);
end
`elsif USE_N12_SNPS_SRAM
`elsif USE_N7_TSMC_SRAM
`elsif USE_N7_SNPS_SRAM
`else
reg [WIDTH-1:0] ram [DEPTH-1:0];
reg [WIDTH-1:0] rdata_ff;
integer i;
always @(posedge CLK) begin
if (CEB == 1'b0) begin
if (WEB == 1'b0) begin // write
for (i = 0; i < WIDTH; i = i + 1) begin
if (BWEB[i] == 1'b0) ram[A][i] <= D[i];
end
end
else begin // read
rdata_ff <= ram[A];
end
end
end
assign sram_rdata = rdata_ff;
`endif
// Input PIPE
generate
if(IN_PIPE==1) begin : GEN_IN_PIPE_1
reg ceb_ff;
reg web_ff;
reg [WIDTH-1:0] bweb_ff;
reg [ADDR_WIDTH-1:0] a_ff;
reg [WIDTH-1:0] d_ff;
always @(posedge CLK) begin
if(CEB==1'b0) begin
ceb_ff <= 1'b0;
web_ff <= WEB;
bweb_ff <= BWEB;
a_ff <= A;
d_ff <= D;
end
else begin
ceb_ff <= 1'b1;
end
end
assign sram_ceb = ceb_ff;
assign sram_web = web_ff;
assign sram_bweb = bweb_ff;
assign sram_addr = a_ff;
assign sram_wdata = d_ff;
end
else begin : GEN_IN_PIPE_0
assign sram_ceb = CEB;
assign sram_web = WEB;
assign sram_bweb = BWEB;
assign sram_addr = A;
assign sram_wdata = D;
end
endgenerate
// Output PIPE
generate
if(OUT_PIPE==1) begin : GEN_OUT_PIPE_1
reg sram_ren_ff;
reg [WIDTH-1:0] sram_rdata_ff;
always @(posedge CLK) begin
if(CEB==1'b0 && WEB==1'b1) begin
sram_ren_ff <= 1'b1; // flag indicating read operation
end
else begin
sram_ren_ff <= 1'b0;
end
end
always @(posedge CLK) begin
if(sram_ren_ff==1'b1) begin
sram_rdata_ff <= sram_rdata; // latch read data
end
else begin
sram_rdata_ff <= sram_rdata_ff;
end
end
assign Q = sram_rdata_ff; // output latched data
end
else begin : GEN_OUT_PIPE_0
assign Q = sram_rdata; // direct output
end
endgenerate
endmodule: $moduleName$

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Scripts/gen_sram_wrap/output_pcie/sram_sp_pcie_512x18.v Normal file
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module sram_sp_pcie_512x18 #(
parameter WIDTH = 18,
parameter DEPTH = 512,
parameter IN_PIPE = 0,
parameter OUT_PIPE = 1
)(
input wire CLK,
input wire CEB,
input wire WEB,
input wire [$clog2(DEPTH)-1:0] A,
input wire [WIDTH-1:0] D,
input wire [WIDTH-1:0] BWEB,
input wire SD,
input wire [1:0] RTSEL,
input wire [1:0] WTSEL,
output wire [WIDTH-1:0] Q
);
localparam ADDR_WIDTH = $clog2(DEPTH);
wire sram_ceb;
wire sram_web;
wire [WIDTH-1:0] sram_bweb;
wire [ADDR_WIDTH-1:0] sram_addr;
wire [WIDTH-1:0] sram_rdata;
wire [WIDTH-1:0] sram_wdata;
`ifdef USE_N12_TSMC_SRAM
if(DEPTH==512 && WIDTH==18) begin : GEN_512x18_SRAM
TS1N12FFCLLUVLTA512X18M4SWSHOCP U_TS1N12FFCLLUVLTA512X18M4SWSHOCP (
.CLK (CLK),
.CEB (sram_ceb),
.WEB (sram_web),
.BWEB (sram_bweb),
.A (sram_addr),
.D (sram_wdata),
.Q (sram_rdata),
.SLP (1'b0),
.DSLP (1'b0),
.SD (SD),
.RTSEL (RTSEL),
.WTSEL (WTSEL),
.FADIO (9'b0),
.REDENIO (1'b0),
.PUDELAY ( )
);
end
else begin : ILLEGAL_SRAM_SIZE
$display("Error: Unsupported SRAM size %d x %d for TSMC N12 SRAM", WIDTH, DEPTH);
end
`elsif USE_N12_SNPS_SRAM
`elsif USE_N7_TSMC_SRAM
`elsif USE_N7_SNPS_SRAM
`else
reg [WIDTH-1:0] ram [DEPTH-1:0];
reg [WIDTH-1:0] rdata_ff;
integer i;
always @(posedge CLK) begin
if (CEB == 1'b0) begin
if (WEB == 1'b0) begin // write
for (i = 0; i < WIDTH; i = i + 1) begin
if (BWEB[i] == 1'b0) ram[A][i] <= D[i];
end
end
else begin // read
rdata_ff <= ram[A];
end
end
end
assign sram_rdata = rdata_ff;
`endif
// Input PIPE
generate
if(IN_PIPE==1) begin : GEN_IN_PIPE_1
reg ceb_ff;
reg web_ff;
reg [WIDTH-1:0] bweb_ff;
reg [ADDR_WIDTH-1:0] a_ff;
reg [WIDTH-1:0] d_ff;
always @(posedge CLK) begin
if(CEB==1'b0) begin
ceb_ff <= 1'b0;
web_ff <= WEB;
bweb_ff <= BWEB;
a_ff <= A;
d_ff <= D;
end
else begin
ceb_ff <= 1'b1;
end
end
assign sram_ceb = ceb_ff;
assign sram_web = web_ff;
assign sram_bweb = bweb_ff;
assign sram_addr = a_ff;
assign sram_wdata = d_ff;
end
else begin : GEN_IN_PIPE_0
assign sram_ceb = CEB;
assign sram_web = WEB;
assign sram_bweb = BWEB;
assign sram_addr = A;
assign sram_wdata = D;
end
endgenerate
// Output PIPE
generate
if(OUT_PIPE==1) begin : GEN_OUT_PIPE_1
reg sram_ren_ff;
reg [WIDTH-1:0] sram_rdata_ff;
always @(posedge CLK) begin
if(CEB==1'b0 && WEB==1'b1) begin
sram_ren_ff <= 1'b1; // flag indicating read operation
end
else begin
sram_ren_ff <= 1'b0;
end
end
always @(posedge CLK) begin
if(sram_ren_ff==1'b1) begin
sram_rdata_ff <= sram_rdata; // latch read data
end
else begin
sram_rdata_ff <= sram_rdata_ff;
end
end
assign Q = sram_rdata_ff; // output latched data
end
else begin : GEN_OUT_PIPE_0
assign Q = sram_rdata; // direct output
end
endgenerate
endmodule: $moduleName$

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Scripts/gen_sram_wrap/output_pcie/sram_sp_pcie_768x25.v Normal file
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module sram_sp_pcie_768x25 #(
parameter WIDTH = 25,
parameter DEPTH = 768,
parameter IN_PIPE = 0,
parameter OUT_PIPE = 1
)(
input wire CLK,
input wire CEB,
input wire WEB,
input wire [$clog2(DEPTH)-1:0] A,
input wire [WIDTH-1:0] D,
input wire [WIDTH-1:0] BWEB,
input wire SD,
input wire [1:0] RTSEL,
input wire [1:0] WTSEL,
output wire [WIDTH-1:0] Q
);
localparam ADDR_WIDTH = $clog2(DEPTH);
wire sram_ceb;
wire sram_web;
wire [WIDTH-1:0] sram_bweb;
wire [ADDR_WIDTH-1:0] sram_addr;
wire [WIDTH-1:0] sram_rdata;
wire [WIDTH-1:0] sram_wdata;
`ifdef USE_N12_TSMC_SRAM
if(DEPTH==768 && WIDTH==25) begin : GEN_768x25_SRAM
TS1N12FFCLLUVLTA768X25M4SWSHOCP U_TS1N12FFCLLUVLTA768X25M4SWSHOCP (
.CLK (CLK),
.CEB (sram_ceb),
.WEB (sram_web),
.BWEB (sram_bweb),
.A (sram_addr),
.D (sram_wdata),
.Q (sram_rdata),
.SLP (1'b0),
.DSLP (1'b0),
.SD (SD),
.RTSEL (RTSEL),
.WTSEL (WTSEL),
.FADIO (9'b0),
.REDENIO (1'b0),
.PUDELAY ( )
);
end
else begin : ILLEGAL_SRAM_SIZE
$display("Error: Unsupported SRAM size %d x %d for TSMC N12 SRAM", WIDTH, DEPTH);
end
`elsif USE_N12_SNPS_SRAM
`elsif USE_N7_TSMC_SRAM
`elsif USE_N7_SNPS_SRAM
`else
reg [WIDTH-1:0] ram [DEPTH-1:0];
reg [WIDTH-1:0] rdata_ff;
integer i;
always @(posedge CLK) begin
if (CEB == 1'b0) begin
if (WEB == 1'b0) begin // write
for (i = 0; i < WIDTH; i = i + 1) begin
if (BWEB[i] == 1'b0) ram[A][i] <= D[i];
end
end
else begin // read
rdata_ff <= ram[A];
end
end
end
assign sram_rdata = rdata_ff;
`endif
// Input PIPE
generate
if(IN_PIPE==1) begin : GEN_IN_PIPE_1
reg ceb_ff;
reg web_ff;
reg [WIDTH-1:0] bweb_ff;
reg [ADDR_WIDTH-1:0] a_ff;
reg [WIDTH-1:0] d_ff;
always @(posedge CLK) begin
if(CEB==1'b0) begin
ceb_ff <= 1'b0;
web_ff <= WEB;
bweb_ff <= BWEB;
a_ff <= A;
d_ff <= D;
end
else begin
ceb_ff <= 1'b1;
end
end
assign sram_ceb = ceb_ff;
assign sram_web = web_ff;
assign sram_bweb = bweb_ff;
assign sram_addr = a_ff;
assign sram_wdata = d_ff;
end
else begin : GEN_IN_PIPE_0
assign sram_ceb = CEB;
assign sram_web = WEB;
assign sram_bweb = BWEB;
assign sram_addr = A;
assign sram_wdata = D;
end
endgenerate
// Output PIPE
generate
if(OUT_PIPE==1) begin : GEN_OUT_PIPE_1
reg sram_ren_ff;
reg [WIDTH-1:0] sram_rdata_ff;
always @(posedge CLK) begin
if(CEB==1'b0 && WEB==1'b1) begin
sram_ren_ff <= 1'b1; // flag indicating read operation
end
else begin
sram_ren_ff <= 1'b0;
end
end
always @(posedge CLK) begin
if(sram_ren_ff==1'b1) begin
sram_rdata_ff <= sram_rdata; // latch read data
end
else begin
sram_rdata_ff <= sram_rdata_ff;
end
end
assign Q = sram_rdata_ff; // output latched data
end
else begin : GEN_OUT_PIPE_0
assign Q = sram_rdata; // direct output
end
endgenerate
endmodule: $moduleName$

149
Scripts/gen_sram_wrap/output_pcie/sram_sp_pcie_768x31.v Normal file
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@ -0,0 +1,149 @@
module sram_sp_pcie_768x31 #(
parameter WIDTH = 31,
parameter DEPTH = 768,
parameter IN_PIPE = 0,
parameter OUT_PIPE = 1
)(
input wire CLK,
input wire CEB,
input wire WEB,
input wire [$clog2(DEPTH)-1:0] A,
input wire [WIDTH-1:0] D,
input wire [WIDTH-1:0] BWEB,
input wire SD,
input wire [1:0] RTSEL,
input wire [1:0] WTSEL,
output wire [WIDTH-1:0] Q
);
localparam ADDR_WIDTH = $clog2(DEPTH);
wire sram_ceb;
wire sram_web;
wire [WIDTH-1:0] sram_bweb;
wire [ADDR_WIDTH-1:0] sram_addr;
wire [WIDTH-1:0] sram_rdata;
wire [WIDTH-1:0] sram_wdata;
`ifdef USE_N12_TSMC_SRAM
if(DEPTH==768 && WIDTH==31) begin : GEN_768x31_SRAM
TS1N12FFCLLUVLTA768X31M4SWSHOCP U_TS1N12FFCLLUVLTA768X31M4SWSHOCP (
.CLK (CLK),
.CEB (sram_ceb),
.WEB (sram_web),
.BWEB (sram_bweb),
.A (sram_addr),
.D (sram_wdata),
.Q (sram_rdata),
.SLP (1'b0),
.DSLP (1'b0),
.SD (SD),
.RTSEL (RTSEL),
.WTSEL (WTSEL),
.FADIO (9'b0),
.REDENIO (1'b0),
.PUDELAY ( )
);
end
else begin : ILLEGAL_SRAM_SIZE
$display("Error: Unsupported SRAM size %d x %d for TSMC N12 SRAM", WIDTH, DEPTH);
end
`elsif USE_N12_SNPS_SRAM
`elsif USE_N7_TSMC_SRAM
`elsif USE_N7_SNPS_SRAM
`else
reg [WIDTH-1:0] ram [DEPTH-1:0];
reg [WIDTH-1:0] rdata_ff;
integer i;
always @(posedge CLK) begin
if (CEB == 1'b0) begin
if (WEB == 1'b0) begin // write
for (i = 0; i < WIDTH; i = i + 1) begin
if (BWEB[i] == 1'b0) ram[A][i] <= D[i];
end
end
else begin // read
rdata_ff <= ram[A];
end
end
end
assign sram_rdata = rdata_ff;
`endif
// Input PIPE
generate
if(IN_PIPE==1) begin : GEN_IN_PIPE_1
reg ceb_ff;
reg web_ff;
reg [WIDTH-1:0] bweb_ff;
reg [ADDR_WIDTH-1:0] a_ff;
reg [WIDTH-1:0] d_ff;
always @(posedge CLK) begin
if(CEB==1'b0) begin
ceb_ff <= 1'b0;
web_ff <= WEB;
bweb_ff <= BWEB;
a_ff <= A;
d_ff <= D;
end
else begin
ceb_ff <= 1'b1;
end
end
assign sram_ceb = ceb_ff;
assign sram_web = web_ff;
assign sram_bweb = bweb_ff;
assign sram_addr = a_ff;
assign sram_wdata = d_ff;
end
else begin : GEN_IN_PIPE_0
assign sram_ceb = CEB;
assign sram_web = WEB;
assign sram_bweb = BWEB;
assign sram_addr = A;
assign sram_wdata = D;
end
endgenerate
// Output PIPE
generate
if(OUT_PIPE==1) begin : GEN_OUT_PIPE_1
reg sram_ren_ff;
reg [WIDTH-1:0] sram_rdata_ff;
always @(posedge CLK) begin
if(CEB==1'b0 && WEB==1'b1) begin
sram_ren_ff <= 1'b1; // flag indicating read operation
end
else begin
sram_ren_ff <= 1'b0;
end
end
always @(posedge CLK) begin
if(sram_ren_ff==1'b1) begin
sram_rdata_ff <= sram_rdata; // latch read data
end
else begin
sram_rdata_ff <= sram_rdata_ff;
end
end
assign Q = sram_rdata_ff; // output latched data
end
else begin : GEN_OUT_PIPE_0
assign Q = sram_rdata; // direct output
end
endgenerate
endmodule: $moduleName$

149
Scripts/gen_sram_wrap/output_pcie/sram_sp_pcie_768x94.v Normal file
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@ -0,0 +1,149 @@
module sram_sp_pcie_768x94 #(
parameter WIDTH = 94,
parameter DEPTH = 768,
parameter IN_PIPE = 0,
parameter OUT_PIPE = 1
)(
input wire CLK,
input wire CEB,
input wire WEB,
input wire [$clog2(DEPTH)-1:0] A,
input wire [WIDTH-1:0] D,
input wire [WIDTH-1:0] BWEB,
input wire SD,
input wire [1:0] RTSEL,
input wire [1:0] WTSEL,
output wire [WIDTH-1:0] Q
);
localparam ADDR_WIDTH = $clog2(DEPTH);
wire sram_ceb;
wire sram_web;
wire [WIDTH-1:0] sram_bweb;
wire [ADDR_WIDTH-1:0] sram_addr;
wire [WIDTH-1:0] sram_rdata;
wire [WIDTH-1:0] sram_wdata;
`ifdef USE_N12_TSMC_SRAM
if(DEPTH==768 && WIDTH==94) begin : GEN_768x94_SRAM
TS1N12FFCLLUVLTA768X94M4SWSHOCP U_TS1N12FFCLLUVLTA768X94M4SWSHOCP (
.CLK (CLK),
.CEB (sram_ceb),
.WEB (sram_web),
.BWEB (sram_bweb),
.A (sram_addr),
.D (sram_wdata),
.Q (sram_rdata),
.SLP (1'b0),
.DSLP (1'b0),
.SD (SD),
.RTSEL (RTSEL),
.WTSEL (WTSEL),
.FADIO (9'b0),
.REDENIO (1'b0),
.PUDELAY ( )
);
end
else begin : ILLEGAL_SRAM_SIZE
$display("Error: Unsupported SRAM size %d x %d for TSMC N12 SRAM", WIDTH, DEPTH);
end
`elsif USE_N12_SNPS_SRAM
`elsif USE_N7_TSMC_SRAM
`elsif USE_N7_SNPS_SRAM
`else
reg [WIDTH-1:0] ram [DEPTH-1:0];
reg [WIDTH-1:0] rdata_ff;
integer i;
always @(posedge CLK) begin
if (CEB == 1'b0) begin
if (WEB == 1'b0) begin // write
for (i = 0; i < WIDTH; i = i + 1) begin
if (BWEB[i] == 1'b0) ram[A][i] <= D[i];
end
end
else begin // read
rdata_ff <= ram[A];
end
end
end
assign sram_rdata = rdata_ff;
`endif
// Input PIPE
generate
if(IN_PIPE==1) begin : GEN_IN_PIPE_1
reg ceb_ff;
reg web_ff;
reg [WIDTH-1:0] bweb_ff;
reg [ADDR_WIDTH-1:0] a_ff;
reg [WIDTH-1:0] d_ff;
always @(posedge CLK) begin
if(CEB==1'b0) begin
ceb_ff <= 1'b0;
web_ff <= WEB;
bweb_ff <= BWEB;
a_ff <= A;
d_ff <= D;
end
else begin
ceb_ff <= 1'b1;
end
end
assign sram_ceb = ceb_ff;
assign sram_web = web_ff;
assign sram_bweb = bweb_ff;
assign sram_addr = a_ff;
assign sram_wdata = d_ff;
end
else begin : GEN_IN_PIPE_0
assign sram_ceb = CEB;
assign sram_web = WEB;
assign sram_bweb = BWEB;
assign sram_addr = A;
assign sram_wdata = D;
end
endgenerate
// Output PIPE
generate
if(OUT_PIPE==1) begin : GEN_OUT_PIPE_1
reg sram_ren_ff;
reg [WIDTH-1:0] sram_rdata_ff;
always @(posedge CLK) begin
if(CEB==1'b0 && WEB==1'b1) begin
sram_ren_ff <= 1'b1; // flag indicating read operation
end
else begin
sram_ren_ff <= 1'b0;
end
end
always @(posedge CLK) begin
if(sram_ren_ff==1'b1) begin
sram_rdata_ff <= sram_rdata; // latch read data
end
else begin
sram_rdata_ff <= sram_rdata_ff;
end
end
assign Q = sram_rdata_ff; // output latched data
end
else begin : GEN_OUT_PIPE_0
assign Q = sram_rdata; // direct output
end
endgenerate
endmodule: $moduleName$

14
Scripts/gen_sram_wrap/template_sram_wrap.v → Scripts/gen_sram_wrap/template_sram_sp_wrap.v
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@ -1,7 +1,7 @@
module $moduleName$ #(
parameter WIDTH = $WIDTH$,
parameter DEPTH = $DEPTH$,
module ${SramWrapName} #(
parameter WIDTH = ${Width},
parameter DEPTH = ${Depth},
parameter IN_PIPE = 0,
parameter OUT_PIPE = 1
)(
@ -26,8 +26,8 @@ wire [WIDTH-1:0] sram_rdata;
wire [WIDTH-1:0] sram_wdata;
`ifdef USE_N12_TSMC_SRAM
if(DEPTH==31 && WIDTH==768) begin : GEN_768X31_SRAM
TS1N12FFCLLULVTA768X31M4SWSH0CP u_sram (
if(DEPTH==${Depth} && WIDTH==${Width}) begin : GEN_${Depth}x${Width}_SRAM
${ReferenceName} U_${ReferenceName} (
.CLK (CLK),
.CEB (sram_ceb),
.WEB (sram_web),
@ -42,7 +42,7 @@ wire [WIDTH-1:0] sram_wdata;
.WTSEL (WTSEL),
.FADIO (9'b0),
.REDENIO (1'b0),
.PUDELAY (1'b0)
.PUDELAY ( )
);
end
else begin : ILLEGAL_SRAM_SIZE
@ -146,4 +146,4 @@ generate
endgenerate
endmodule: $moduleName$
endmodule

179
Scripts/gen_sram_wrap/template_sram_tp_wrap.v Normal file
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@ -0,0 +1,179 @@
module ${SramWrapName} #(
parameter WIDTH = ${Width},
parameter DEPTH = ${Depth},
parameter IN_PIPE = 0,
parameter OUT_PIPE = 1
)(
input wire CLK, // Write/Read Clock, Sync type SRAM
input wire WEB, // Write Enable, Active-low
input wire [$clog2(DEPTH)-1:0] AA, // Write Address
input wire [WIDTH-1:0] D, // Write Data
input wire [WIDTH-1:0] BWEB, // Bit mask Write Enable, Active-low
input wire REB, // Read Enable, Active-low
input wire [$clog2(DEPTH)-1:0] AB, // Read Address
input wire SD,
input wire [1:0] RTSEL,
input wire [1:0] WTSEL,
input wire [1:0] MTSEL,
output wire [WIDTH-1:0] Q // Read Data Output
);
localparam ADDR_WIDTH = $clog2(DEPTH);
wire sram_web;
wire [ADDR_WIDTH-1:0] sram_waddr;
wire [WIDTH-1:0] sram_wdata;
wire [WIDTH-1:0] sram_bweb;
wire sram_reb;
wire [ADDR_WIDTH-1:0] sram_raddr;
wire [WIDTH-1:0] sram_rdata;
`ifdef USE_N12_TSMC_SRAM
generate
if(DEPTH==${Depth} && WIDTH==${Width}) begin : GEN_${Depth}X${Width}_SRAM
localparam RTSEL_VAL = 2'b01;
localparam WTSEL_VAL = 2'b01;
localparam MTSEL_VAL = 2'b01;
${ReferenceName} U_${ReferenceName} (
.CLK (CLK),
.WEB (sram_web),
.AA (sram_waddr),
.D (sram_wdata[0 +: WIDTH/3]),
.BWEB (sram_bweb[0 +: WIDTH/3]),
.REB (sram_reb),
.AB (sram_raddr),
.Q (sram_rdata[0 +: WIDTH/3]),
//.BIST (1'b0),
//.WEBM (1'b0),
//.AMA ({ADDR_WIDTH{1'b0}}),
//.DM (0)
//.BWEBM (0),
//.REBM (1'b0),
//.AMB ({ADDR_WIDTH{1'b0}}),
.RTSEL (RTSEL),
.WTSEL (WTSEL),
.MTSEL (MTSEL),
.SLP (1'b0),
.DSLP (1'b0),
.SD (SD),
.PUDELAY ( ),
.FADIO (9'd0),
.REDENIO (1'b0)
);
end
else begin : ILLEAGAL_SIZE_SRAM
//$display("\tERROR %m : Illegal SRAM size. %t\n", $realtime);
end
endgenerate
`elsif USE_N12_SNPS_SRAM
`elsif USE_N7_TSMC_SRAM
`elsif USE_N7_SNPS_SRAM
`else
reg [WIDTH-1:0] ram [DEPTH-1:0];
reg [WIDTH-1:0] rdata_ff;
integer i;
always @(posedge CLK) begin
if (WEB == 1'b0) begin // write
for (i = 0; i < WIDTH; i = i + 1) begin
if (BWEB[i] == 1'b0)
ram[AA][i] <= D[i];
end
end
end
// 读操作
always @(posedge CLK) begin
if (REB == 1'b0) begin // read
rdata_ff <= ram[AB];
end
end
assign sram_rdata = rdata_ff;
`endif
// Input PIPE
generate
if(IN_PIPE==1) begin : GEN_IN_PIPE_1
reg web_ff;
reg [WIDTH-1:0] bweb_ff;
reg [ADDR_WIDTH-1:0] aa_ff;
reg [ADDR_WIDTH-1:0] ab_ff;
reg [WIDTH-1:0] d_ff;
reg reb_ff;
always @(posedge CLK) begin
if(WEB==1'b0) begin
web_ff <= 1'b0;
bweb_ff <= BWEB;
aa_ff <= AA;
d_ff <= D;
end
else begin
web_ff <= 1'b1;
end
end
always @(posedge CLK) begin
if(REB==1'b0) begin
reb_ff <= 1'b0;
ab_ff <= AB;
end
else begin
reb_ff <= 1'b1;
end
end
assign sram_web = web_ff;
assign sram_waddr = aa_ff;
assign sram_wdata = d_ff;
assign sram_bweb = bweb_ff;
assign sram_reb = reb_ff;
assign sram_raddr = ab_ff;
end
else begin : GEN_IN_PIPE_0
assign sram_web = WEB;
assign sram_waddr = AA;
assign sram_wdata = D;
assign sram_bweb = BWEB;
assign sram_reb = REB;
assign sram_raddr = AB;
end
endgenerate
generate
if(OUT_PIPE==1) begin : GEN_OUT_PIPE_1
reg sram_ren_ff;
reg [WIDTH-1:0] sram_rdata_ff;
always @(posedge CLK) begin
if(REB == 1'b0) begin
sram_ren_ff <= 1'b1;
end
else begin
sram_ren_ff <= 1'b0;
end
end
always @(posedge CLK) begin
if(sram_ren_ff == 1'b1) begin
sram_rdata_ff <= sram_rdata;
end
else begin
sram_rdata_ff <= sram_rdata_ff; // 保持上一个值
end
end
assign Q = sram_rdata_ff;
end
else begin : GEN_OUT_PIPE_0
assign Q = sram_rdata;
end
endgenerate
endmodule

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