This commit is contained in:
leeyunlong 2025-06-19 14:22:25 +08:00
parent 9ae9bc0215
commit b4f2c518f5
9 changed files with 26 additions and 9 deletions

3
.gitignore vendored
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@ -1,3 +1,4 @@
.vscode/
/Scripts/*.xls
test.*
test.*
output_*/

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@ -37,8 +37,20 @@ def generate_files(xls_path, sheet_name=None):
'AssemblyDepth' : headers.index('AssemblyDepth'),
'AssemblyWidth' : headers.index('AssemblyWidth')
}
# 新增列存在性检查
required_columns = ['SramWrapName', 'Width', 'Depth', 'ReferenceName',
'PortType', 'AssemblyDepth', 'AssemblyWidth']
missing_cols = [col for col in required_columns if col not in headers]
if missing_cols:
error_msg = f"[Error] Sheet '{sheet.name}' missing columns: {', '.join(missing_cols)}"
if sheet_name: # 指定特定sheet时直接退出
print(error_msg)
sys.exit(1)
print(error_msg + ", skipping...")
continue
print(f"Processing sheet: {sheet.name} with columns: {col_map}")
# 创建输出目录
output_dir = f"output_{sheet.name}"
os.makedirs(output_dir, exist_ok=True)
@ -46,6 +58,10 @@ def generate_files(xls_path, sheet_name=None):
# 处理每行数据
for row_idx in range(2, sheet.nrows):
row = sheet.row_values(row_idx)
# 检查必要列是否有值
if not row[col_map['name']] or not row[col_map['width']] or not row[col_map['depth']]:
print(f"[Warning] Missing required data in row {row_idx}, skipping.")
continue
# is Assembly or not
if int(row[col_map['AssemblyDepth']]) * int(row[col_map['AssemblyWidth']]) > 1:
print(f"[Note:Assembly] AssemblyDepth is {row[col_map['AssemblyDepth']]} and AssemblyWidth is {row[col_map['AssemblyWidth']]} in row {row_idx}, skipping.")

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@ -146,4 +146,4 @@ generate
endgenerate
endmodule: $moduleName$
endmodule

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@ -146,4 +146,4 @@ generate
endgenerate
endmodule: $moduleName$
endmodule

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@ -146,4 +146,4 @@ generate
endgenerate
endmodule: $moduleName$
endmodule

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@ -146,4 +146,4 @@ generate
endgenerate
endmodule: $moduleName$
endmodule

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@ -146,4 +146,4 @@ generate
endgenerate
endmodule: $moduleName$
endmodule

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@ -146,4 +146,4 @@ generate
endgenerate
endmodule: $moduleName$
endmodule

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@ -146,4 +146,4 @@ generate
endgenerate
endmodule: $moduleName$
endmodule