diff --git a/Scripts/blog/verilog-mode-2.md b/Scripts/blog/verilog-mode-2.md
index dd70d13..5d465b9 100644
--- a/Scripts/blog/verilog-mode-2.md
+++ b/Scripts/blog/verilog-mode-2.md
@@ -16,7 +16,6 @@
 ```
 
 Demo:
-```verilog
 /* mcu_crg	AUTO_TEMPLATE (
 		.i_scan_mode	(1'b0),
 		.i_scan_rst_n	(1'b1),
diff --git a/Scripts/do_apb_file.py b/Scripts/do_apb_file.py
index 1c79d19..24c5f53 100644
--- a/Scripts/do_apb_file.py
+++ b/Scripts/do_apb_file.py
@@ -48,7 +48,7 @@ def no_copy_workbook(file_path, sheet_name):
             regname_col = col
         if sheet.cell(0, col).value == 'Bits':
             bits_col = col
-        if sheet.cell(0, col).value == 'OffsetWidth':
+        if sheet.cell(0, col).value == 'FiledWidth':
             offsetWidth_col = col
         if offset_col is not None and regname_col is not None and bits_col is not None and offsetWidth_col is not None:
             break
@@ -294,7 +294,9 @@ def parse_bits_sequences(file_path, sheet_name):
 
 
 
+##############################################################################
 ####Main()
+##############################################################################
 if __name__ == "__main__":
     check()
     file_path = sys.argv[1]
@@ -303,7 +305,7 @@ if __name__ == "__main__":
     print("This is OK,sheets_num is : %d" % sheets_num)
 
 
-    for index in range(1):
+    for index in range(sheets_num):
         sheet = book.sheet_by_index(index)
         print("Sheet Name: %s"%(sheet.name))
         print("Rows: %d, Cols: %d"%(sheet.nrows, sheet.ncols))