diff --git a/GaoKao/李云鹤__高一下学期期末.png b/GaoKao/李云鹤__高一下学期期末.png
new file mode 100644
index 0000000..a129be7
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diff --git a/Scripts/gen_sram_wrap/template_sram_sp_wrap.v b/Scripts/gen_sram_wrap/template_sram_sp_wrap.v
index 22db248..3056c0a 100644
--- a/Scripts/gen_sram_wrap/template_sram_sp_wrap.v
+++ b/Scripts/gen_sram_wrap/template_sram_sp_wrap.v
@@ -11,8 +11,9 @@ module ${SramWrapName} #(
   input  wire [$clog2(DEPTH)-1:0] A,
   input  wire [WIDTH-1:0]         D,
   input  wire [WIDTH-1:0]         BWEB,
-  input  wire                     mem_ctrl_bus_sd,
-  input  wire [64 -1:0]           mem_ctrl_bus,
+  input  wire                     SD,
+  input  wire [1:0]               RTSEL,
+  input  wire [1:0]               WTSEL,
   output wire [WIDTH-1:0]         Q
 );
 
@@ -24,10 +25,6 @@ wire [ADDR_WIDTH-1:0] sram_addr;
 wire [WIDTH-1:0] sram_rdata;
 wire [WIDTH-1:0] sram_wdata;
 
-wire SD = mem_ctrl_bus_sd;
-wire [2-1:0] RTSEL = mem_ctrl_bus[49:48];
-wire [2-1:0] WTSEL = mem_ctrl_bus[45:44];
-
 `ifdef USE_N12_TSMC_SRAM
     if(DEPTH==${Depth} && WIDTH==${Width}) begin : GEN_${Depth}x${Width}_SRAM
         ${ReferenceName} U_${ReferenceName} (
@@ -49,6 +46,7 @@ wire [2-1:0] WTSEL = mem_ctrl_bus[45:44];
         );
     end
     else begin : ILLEGAL_SRAM_SIZE
+        $display("Error: Unsupported SRAM size %d x %d for TSMC N12 SRAM", WIDTH, DEPTH);
     end
 
 `elsif USE_N12_SNPS_SRAM
@@ -148,4 +146,4 @@ generate
 
 endgenerate
 
-endmodule
\ No newline at end of file
+endmodule: $moduleName$
\ No newline at end of file
diff --git a/mem_mcu_wrap/image.png b/mem_mcu_wrap/image.png
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diff --git a/mem_mcu_wrap/mem_mcu_wrap详细设计文档.md b/mem_mcu_wrap/mem_mcu_wrap详细设计文档.md
new file mode 100644
index 0000000..cfc9d56
--- /dev/null
+++ b/mem_mcu_wrap/mem_mcu_wrap详细设计文档.md
@@ -0,0 +1,62 @@
+
+@[TOC](mem_mcu_wrap详细设计文档)
+
+# 1 mem_mcu_wrap top
+在这里为了TOP集成的自动化和效率，使用verilog-mode来集成；
+## 1.1 总体功能概述
+`mem_mcu_wrap`模块是一个顶层模块，主要负责将Corelink子模块和其他多master、多slave进行集成连接起来，它的主要功能是如下所示：
+
+## 1.2 总体结构框图
+该mem_mcu_wrap的总体结构框图如下所示:
+![alt text](企业微信截图_17510086982428.png)
+
+## 1.3 
+
+# 2 Corelink子模块
+## 2.1 功能概述
+该Corelink是由AMBA_de工具生成的nic400 switch模块；
+
+## 2.2 地址分配
+
+## 2.3 结构框图
+
+## 2.4 设计详述
+
+# 3 记录问题
+
+
+
+
+
+# Verilog-mode使用
+## 1.1 变量范例使用
+// Local Variables:
+// verilog-library-flags:("-y ./")
+// verilog-auto-inst-param-value:t
+// verilog-auto-input-ignore-regexp:""
+// verilog-auto-output-ignore-regexp:""
+// End:
+
+---------------------------------------->
+// Local Variables:
+// verilog-library-flags:("-y ./ -y ../common/basic -y ../common/cfg_noc -y ../common/crg -y cortexm3/cortexm3_integration/verilog -y ./nic400_ahb_matrix/nic400/verilog ")
+// verilog-auto-inst-param-value:t
+// verilog-auto-input-ignore-regexp:"mcu_intisr \\|mcu_core_obs_internalstate_\\|cfg_noc_engine._err_info_clear"
+// verilog-auto-output-ignore-regexp:"mem_ctrl_bus_\\|cfg_die_crd_\\|_info_tmp\\|"
+// End:
+
+## 1.2 带参数例化使用
+带参数的例化是在 (/*AUTOINST*/）中进行使用
+```v
+/* sub_block AUTO_TEMPLATE(
+    .\(.*\)             (\1[]),
+);
+*/
+
+sub_block #(
+    .PARAM1(PARAM1_VALUE),
+    .PARAM2(PARAM2_VALUE),
+    .PARAM3(PARAM3_VALUE)
+)  u_sub_block( /*AUTOINST*/);
+
+```
\ No newline at end of file
diff --git a/mem_mcu_wrap/企业微信截图_17510086982428.png b/mem_mcu_wrap/企业微信截图_17510086982428.png
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