149 lines
3.4 KiB
Verilog
149 lines
3.4 KiB
Verilog
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module $moduleName$ #(
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parameter WIDTH = $WIDTH$,
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parameter DEPTH = $DEPTH$,
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parameter IN_PIPE = 0,
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parameter OUT_PIPE = 1
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)(
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input wire CLK,
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input wire CEB,
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input wire WEB,
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input wire [$clog2(DEPTH)-1:0] A,
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input wire [WIDTH-1:0] D,
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input wire [WIDTH-1:0] BWEB,
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input wire SD,
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input wire [1:0] RTSEL,
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input wire [1:0] WTSEL,
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output wire [WIDTH-1:0] Q
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);
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localparam ADDR_WIDTH = $clog2(DEPTH);
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wire sram_ceb;
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wire sram_web;
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wire [WIDTH-1:0] sram_bweb;
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wire [ADDR_WIDTH-1:0] sram_addr;
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wire [WIDTH-1:0] sram_rdata;
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wire [WIDTH-1:0] sram_wdata;
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`ifdef USE_N12_TSMC_SRAM
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if(DEPTH==31 && WIDTH==768) begin : GEN_768X31_SRAM
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TS1N12FFCLLULVTA768X31M4SWSH0CP u_sram (
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.CLK (CLK),
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.CEB (sram_ceb),
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.WEB (sram_web),
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.BWEB (sram_bweb),
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.A (sram_addr),
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.D (sram_wdata),
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.Q (sram_rdata),
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.SLP (1'b0),
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.DSLP (1'b0),
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.SD (SD),
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.RTSEL (RTSEL),
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.WTSEL (WTSEL),
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.FADIO (9'b0),
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.REDENIO (1'b0),
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.PUDELAY (1'b0)
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);
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end
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else begin : ILLEGAL_SRAM_SIZE
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$display("Error: Unsupported SRAM size %d x %d for TSMC N12 SRAM", WIDTH, DEPTH);
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end
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`elsif USE_N12_SNPS_SRAM
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`elsif USE_N7_TSMC_SRAM
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`elsif USE_N7_SNPS_SRAM
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`else
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reg [WIDTH-1:0] ram [DEPTH-1:0];
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reg [WIDTH-1:0] rdata_ff;
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integer i;
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always @(posedge CLK) begin
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if (CEB == 1'b0) begin
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if (WEB == 1'b0) begin // write
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for (i = 0; i < WIDTH; i = i + 1) begin
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if (BWEB[i] == 1'b0) ram[A][i] <= D[i];
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end
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end
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else begin // read
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rdata_ff <= ram[A];
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end
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end
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end
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assign sram_rdata = rdata_ff;
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`endif
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// Input PIPE
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generate
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if(IN_PIPE==1) begin : GEN_IN_PIPE_1
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reg ceb_ff;
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reg web_ff;
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reg [WIDTH-1:0] bweb_ff;
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reg [ADDR_WIDTH-1:0] a_ff;
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reg [WIDTH-1:0] d_ff;
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always @(posedge CLK) begin
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if(CEB==1'b0) begin
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ceb_ff <= 1'b0;
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web_ff <= WEB;
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bweb_ff <= BWEB;
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a_ff <= A;
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d_ff <= D;
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end
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else begin
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ceb_ff <= 1'b1;
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end
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end
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assign sram_ceb = ceb_ff;
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assign sram_web = web_ff;
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assign sram_bweb = bweb_ff;
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assign sram_addr = a_ff;
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assign sram_wdata = d_ff;
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end
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else begin : GEN_IN_PIPE_0
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assign sram_ceb = CEB;
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assign sram_web = WEB;
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assign sram_bweb = BWEB;
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assign sram_addr = A;
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assign sram_wdata = D;
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end
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endgenerate
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// Output PIPE
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generate
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if(OUT_PIPE==1) begin : GEN_OUT_PIPE_1
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reg sram_ren_ff;
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reg [WIDTH-1:0] sram_rdata_ff;
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always @(posedge CLK) begin
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if(CEB==1'b0 && WEB==1'b1) begin
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sram_ren_ff <= 1'b1; // flag indicating read operation
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end
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else begin
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sram_ren_ff <= 1'b0;
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end
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end
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always @(posedge CLK) begin
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if(sram_ren_ff==1'b1) begin
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sram_rdata_ff <= sram_rdata; // latch read data
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end
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else begin
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sram_rdata_ff <= sram_rdata_ff;
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end
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end
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assign Q = sram_rdata_ff; // output latched data
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end
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else begin : GEN_OUT_PIPE_0
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assign Q = sram_rdata; // direct output
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end
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endgenerate
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endmodule: $moduleName$ |