OSchip
/
llvm-project
mirror of https://github.com/THU-DSP-LAB/llvm-project.git
13
0
Fork 6
Code Issues Packages Projects Releases Wiki Activity

[AArch64] Simplify emitConditionalCompare calls. NFC. 

Now that both callsites are identical, we can simplify the
prototype and make it easier to reason about the 2-CC case.

llvm-svn: 258534
This commit is contained in:
Ahmed Bougacha 2016-01-22 19:43:57 +00:00
parent 99209b90a4
commit 78d6efdb93
1 changed files with 9 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
View File

@ -1287,7 +1287,8 @@ static SDValue emitComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC,
/// Create a conditional comparison; Use CCMP, CCMN or FCCMP as appropriate. /// Create a conditional comparison; Use CCMP, CCMN or FCCMP as appropriate.
static SDValue emitConditionalComparison(SDValue LHS, SDValue RHS, static SDValue emitConditionalComparison(SDValue LHS, SDValue RHS,
ISD::CondCode CC, SDValue CCOp, ISD::CondCode CC, SDValue CCOp,
SDValue Condition, unsigned NZCV, AArch64CC::CondCode Predicate,
AArch64CC::CondCode OutCC,
SDLoc DL, SelectionDAG &DAG) { SDLoc DL, SelectionDAG &DAG) {
unsigned Opcode = 0; unsigned Opcode = 0;
if (LHS.getValueType().isFloatingPoint()) if (LHS.getValueType().isFloatingPoint())
@ -1303,6 +1304,9 @@ static SDValue emitConditionalComparison(SDValue LHS, SDValue RHS,
if (Opcode == 0) if (Opcode == 0)
Opcode = AArch64ISD::CCMP; Opcode = AArch64ISD::CCMP;
SDValue Condition = DAG.getConstant(Predicate, DL, MVT_CC);
AArch64CC::CondCode InvOutCC = AArch64CC::getInvertedCondCode(OutCC);
unsigned NZCV = AArch64CC::getNZCVToSatisfyCondCode(InvOutCC);
SDValue NZCVOp = DAG.getConstant(NZCV, DL, MVT::i32); SDValue NZCVOp = DAG.getConstant(NZCV, DL, MVT::i32);
return DAG.getNode(Opcode, DL, MVT_CC, LHS, RHS, NZCVOp, Condition, CCOp); return DAG.getNode(Opcode, DL, MVT_CC, LHS, RHS, NZCVOp, Condition, CCOp);
} }
@ -1380,14 +1384,9 @@ static SDValue emitConjunctionDisjunctionTree(SelectionDAG &DAG, SDValue Val,
SDValue ExtraCmp; SDValue ExtraCmp;
if (!CCOp.getNode()) if (!CCOp.getNode())
ExtraCmp = emitComparison(LHS, RHS, CC, DL, DAG); ExtraCmp = emitComparison(LHS, RHS, CC, DL, DAG);
else { else
SDValue ConditionOp = DAG.getConstant(Predicate, DL, MVT_CC); ExtraCmp = emitConditionalComparison(LHS, RHS, CC, CCOp, Predicate,
AArch64CC::CondCode InvExtraCC = ExtraCC, DL, DAG);
AArch64CC::getInvertedCondCode(ExtraCC);
unsigned NZCV = AArch64CC::getNZCVToSatisfyCondCode(InvExtraCC);
ExtraCmp = emitConditionalComparison(LHS, RHS, CC, CCOp, ConditionOp,
NZCV, DL, DAG);
}
CCOp = ExtraCmp; CCOp = ExtraCmp;
Predicate = ExtraCC; Predicate = ExtraCC;
} }
@ -1397,10 +1396,7 @@ static SDValue emitConjunctionDisjunctionTree(SelectionDAG &DAG, SDValue Val,
if (!CCOp.getNode()) if (!CCOp.getNode())
return emitComparison(LHS, RHS, CC, DL, DAG); return emitComparison(LHS, RHS, CC, DL, DAG);
// Otherwise produce a ccmp. // Otherwise produce a ccmp.
SDValue ConditionOp = DAG.getConstant(Predicate, DL, MVT_CC); return emitConditionalComparison(LHS, RHS, CC, CCOp, Predicate, OutCC, DL,
AArch64CC::CondCode InvOutCC = AArch64CC::getInvertedCondCode(OutCC);
unsigned NZCV = AArch64CC::getNZCVToSatisfyCondCode(InvOutCC);
return emitConditionalComparison(LHS, RHS, CC, CCOp, ConditionOp, NZCV, DL,
DAG); DAG);
} else if ((Opcode != ISD::AND && Opcode != ISD::OR) || !Val->hasOneUse()) } else if ((Opcode != ISD::AND && Opcode != ISD::OR) || !Val->hasOneUse())
return SDValue(); return SDValue();