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llvm-svn: 131863
This commit is contained in:
Chris Lattner 2011-05-22 18:28:46 +00:00
parent 162dfc3e6b
commit bfe2c24c80
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10
llvm/lib/Target/README.txt
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@ -2346,3 +2346,13 @@ Note that bb1 and bb2 are the same. This doesn't happen at the IR level
because one call is passing an i32 and the other is passing an i64. because one call is passing an i32 and the other is passing an i64.
//===---------------------------------------------------------------------===// //===---------------------------------------------------------------------===//
I see this sort of pattern in 176.gcc in a few places (e.g. the start of
store_bit_field). The rem should be replaced with a multiply and subtract:
%3 = sdiv i32 %A, %B
%4 = srem i32 %A, %B
Similarly for udiv/urem.
//===---------------------------------------------------------------------===//