Commit Graph

2195 Commits

Author SHA1 Message Date
zhoujingya 0a45eabde0 Revert "[VENTUS][RISCV][feat] Legalized vector parameters"
This reverts commit 7bd98c0ff8.
2023-10-08 17:31:53 +08:00
zhoujingya 8bea355dbe Revert "[VENTUS][RISCV][feat] Legalized vector parameters"
This reverts commit 12195ac947.
2023-10-08 17:31:09 +08:00
qinfan 12195ac947 [VENTUS][RISCV][feat] Legalized vector parameters 2023-10-08 11:28:04 +08:00
qinfan 7bd98c0ff8 [VENTUS][RISCV][feat] Legalized vector parameters
Summary: LegaLegalized vector parameters, but not been added FileCheck now.

Test Plan: Legalized vector parameters

Differential Revision: http://www.tpt.com/D740
2023-10-08 11:28:04 +08:00
zhoujingya 0e5eef6abb [VENTUS][fix] fix add instruction
Summary:
fix addi instruction, there will be a hardware error when immediate is
negative number.

Test Plan: fix add instruction

Reviewers: zhoujing

Subscribers: zhoujing

Differential Revision: http://www.tpt.com/D722

Signed-off-by: qinfan <qinfan.wang@terapines.com>
2023-09-08 10:32:17 +08:00
zhoujing 826c4cb599 Revert "[VENTUS][fix] Insert barrier instruction for function calling"
This reverts commit 7e4b7a6ae1.
2023-08-16 14:50:42 +08:00
zhoujing c09d292fad [VENTUS][fix] Fix call IR codegen
Since printf is writtn in c, the function calling has address space mapping issue
2023-08-10 15:01:54 +08:00
zhoujing 700020da1e [VENTUS][fix] Fix vastart builtin codegen 2023-08-09 17:07:15 +08:00
zhoujing 50b23dc21a [VENTUS][fix] Deprecating vmv.s.x and use vmv.v.x instead
As required, vmv.s.x instruction may will later be deprecated
2023-08-01 13:25:24 +08:00
zhoujing f995792016 [VENTUS][test] Add resource usage information test file 2023-08-01 09:19:46 +08:00
zhoujing 7e4b7a6ae1 [VENTUS][fix] Insert barrier instruction for function calling
Stack space is shared between different warps, if two warps are executing
different functions, then the access to the return address will conflict,
which will lead the warp executing faster can not find the return address,
so we would like to add a barrier instruction after the lw and before the ret,
to ensure that the warps have the same scope of the sp pointer
2023-07-31 11:01:14 +08:00
zhoujing 3719c07dc0 [VENTUS][RISCV][fix] Modify JOIN instruction to use X0 rather than V0 2023-07-13 17:01:36 +08:00
yanming 4c099fb3d5 [VENTUS][RISCV] Move `regext insertion pass` after `insert join instruction pass`. 2023-07-07 17:22:27 +08:00
yanming d37e92610d [VENTUS][RISCV] Remove redundant code and enable regext insertion pass when verify machineinstrs. 2023-07-07 17:08:42 +08:00
yanming e2ef54c16b [VENTUS][RISCV] Fix rd,rs1,rs2,rs3 register ordering in regext insertion pass.
Summary: Encoding register ordering in tablegen.

Test Plan: llvm/test/CodeGen/RISCV/VentusGPGPU/builtin-noverify.ll

Reviewers: zhoujing, hualin

Reviewed By: zhoujing

Differential Revision: http://www.tpt.com/D638
2023-07-06 11:47:34 +08:00
yanming a5c8b18ce3 [VENTUS][RISCV] Fix setrpc instruction definition, use auipc + setrpc to set rpc.
It is able to solve address ranges to [-2^31, 2^31).
2023-06-30 11:26:58 +08:00
yanming 3f68eaab5b [VENTUS][RISCV][NFC] Fix testcases failture. 2023-06-27 16:30:44 +08:00
yanming 81c652183c [VENTUS][RISCV][fix] Delete source pseudo instruction in expandBarrier. 2023-06-27 16:27:11 +08:00
yanming 5ceac7f7a1 [VENTUS][RISCV] Fix insert setrpc/join instruction pass for VBranch. 2023-06-27 16:02:01 +08:00
zhoujing bfed578a87 [VENTUS][RISCV][fix] Fix illegal vmv instruction in libclc library
Other than atomic functions library, there are no illegal instructions

Signed-off-by: zhoujing <jing.zhou@terapines.com>
2023-06-27 15:53:51 +08:00
zhoujing 14e9011074 [VENTUS][RISCV][fix] Add divergent pattern for floating instructions
We just simply add zfinx support for floating instrionctions before,
now we add divergent analysis here to avoid illegal VGPR move to GPRF32
2023-06-26 15:09:14 +08:00
zhoujing 7b8402802a [VENTUS][RISCV][fix] Fix calling convention 2023-06-25 22:03:04 +08:00
zhoujing c30c837caa [VENTUS][RISCV][fix] Fix SP stack size calculation error 2023-06-15 18:12:34 +08:00
zhoujing 53a932e665 [VENTUS][RISCV][fix] Modify calling convention for non-kernel function arguments based on private memory address
In our previous calling convention design, all non-kernel arguments are passed
by VGPRS or TP stack, but when the arguments point to private memory address
space, the wrong memory access instructions will be generated, because private
memory based address is scalar register
2023-06-14 21:26:53 +08:00
zhoujing e5e7a0047a [VENTUS][RISCV][fix] Fix local memory access error in kernel function 2023-06-12 16:22:45 +08:00
zhoujing faf6a0bcd9 [VENTUS][RISCV][fix] Add initial Tp stack size calculation
Cause there are two stacks in Ventus, we need to seperate TP stack and SP stack,
this commit just add very initial support for TP stack size calculation
2023-06-11 12:18:39 +08:00
zhoujing 967cb725c8 [VENTUS][RISCV][feat] Set ventus kernel for OpenCL kernel functions 2023-06-05 13:10:35 +08:00
zhoujing 7d66e05b28 [VENTUS][RISCV][fix] Fix insert join instructions pass bug
After this fix, the vbeq/join instructions codegen are normal now

Signed-off-by: zhoujingya <jing.zhou@terapines.com>
2023-05-31 12:02:27 +08:00
zhoujingya ad23baaa51 [VENTUS][RISCV][feat] Add more floating point instructions pattern
Signed-off-by: zhoujing <jing.zhou@terapines.com>
2023-05-25 14:48:30 +08:00
zhoujingya 97a3f99e4c [VENTUS][RISCV][pass] Add insert join instruction pass for VBranch
we follow the following rules to insert join block and join instruction

 1: Legalize all the return block
    when there are one more return blocks in machine function, there must be
    branches, we need to reduce return blocks number down to 1
 1.1: If two return blocks have common nearest parent branch, this two blocks
    need to be joined, and we add a hasBeenJoined marker for this parent
    branch
 1.2: after we complete 1.1 process, there maybe one more return blocks, we
    need to further add join block, we recursively build dominator tree for
    these return blocks, first we find the nearest common dominator branch for
    two return blocks, and then get dominator tree path between dominator
    and each return block, we need to check this path in which whether any
    other branch blocks exists, ideally, the branch block in path should have
    been joined and marked, if not, this path is illegal, these two block can
    not be joined

 2: Insert join instructions
 2.1: we scan through the MachineBasic blocks and check what blocks to insert
    join instruction, below MBB represents MachineBasic Block
 2.2: The MBB must have one more predecessors and its nearest dominator must
     be a VBranch
 2.3: Then we analyze the the predecessor of MBB, if the predecessor
    has single successor, we add a join instruction to the predecessor end,
    other wise, we need to insert a join block between predecessor and MBB
2023-05-12 14:01:57 +08:00
zhoujingya ea75d078fb [VENTUS][RISCV][feat] Add zfinx support
Because there is no `F` extension and float registers in ventus, we need to
support `zfinx` to generate common float instructions
2023-04-23 11:29:09 +08:00
zhoujingya 9d9283fa7b [VENTUS][RISCV][fix] Fix ventus abi and calling convention
Kernel functions use sp as GPRs spill stack slots
Non-kernel functions use tp as VGPRs spill stack slots
2023-04-20 15:27:52 +08:00
zhoujingya f28e6c5e38 [VENTUS][RISCV][feat] Add vararg backend support in ventus
We adjust the stack growing direction early months for OpenCL, in order to be
compatible with current architecture, we need to do some modification to
support vararg
2023-04-18 10:03:53 +08:00
zhoujingya b01963690d [VENTUS][RISCV][fix] Fix vsw/vlw encoding bugs and update test cases
Fix vlw/vsw instructions' encoding since them have been updated
2023-04-17 18:07:33 +08:00
zhoujingya 553e65dcf7 Change barrier and work_group_barrier into builtin functions 2023-03-14 10:38:22 +08:00
zhoujingya ad550a1375 Update load/store instructions pattern && add test cases for load/store codegen 2023-03-03 11:41:13 +08:00
zhoujing a92723f212 Update barrier intrinsics' name and modify barrier's encoding 2023-02-10 14:50:40 +08:00
zhoujing 23fe611d6e Fix barriersub instruction pattern match bug 2023-02-10 10:44:22 +08:00
zhoujing 18810a86c0 Update barrier&barriersub instructions, codegen test cases for barrier builtins and intrinsics 2023-02-10 10:27:46 +08:00
zhoujing 47fc50bb92 Add pass to support VX/VF instruction generation
Summary: Add pass to support VX/VF instruction generation

Test Plan: none

Reviewers: hualin

Reviewed By: hualin

Subscribers: yanming

Differential Revision: http://www.tpt.com/D583
2023-02-07 14:00:15 +08:00
zhoujing 23821f9116 Change some patterns' format 2023-01-17 09:34:59 +08:00
zhoujing a81a56274f Update float point instructions test case 2023-01-12 16:43:47 +08:00
zhoujing 6df9308e35 Update int arithmetic test file 2023-01-12 11:15:56 +08:00
zhoujing 7e701d4ba1 Add support for float point trunc instruction match 2023-01-09 18:06:39 +08:00
zhoujing 899ca9fd8e Add support for 12 bits immediate 2023-01-09 11:59:45 +08:00
zhoujing cfc9476c48 Update pattern and test cases for floating-point sign-injection Instruction 2023-01-05 17:44:06 +08:00
zhoujing 02392af08a Update pattern and test cases for float/integer arithmetic instructions 2023-01-05 13:35:58 +08:00
zhoujing c635182266 Update pattern and test cases for float/integer convert instructions 2023-01-04 15:04:36 +08:00
Aries a173844ae5 Grow Ventus GPGPU stack upwards instead of downwards 2023-01-04 10:29:53 +08:00
zhoujing eb54dc382c Update pattern for float select instructions && update test cases 2023-01-04 10:21:49 +08:00