Commit Graph

33 Commits

Author SHA1 Message Date
Zachary Turner 97206d5727 Rename Error -> Status.
This renames the LLDB error class to Status, as discussed
on the lldb-dev mailing list.

A change of this magnitude cannot easily be done without
find and replace, but that has potential to catch unwanted
occurrences of common strings such as "Error".  Every effort
was made to find all the obvious things such as the word "Error"
appearing in a string, etc, but it's possible there are still
some lingering occurences left around.  Hopefully nothing too
serious.

llvm-svn: 302872
2017-05-12 04:51:55 +00:00
Zachary Turner 2f3df6137a iwyu fixes for lldbCore.
This adjusts header file includes for headers and source files
in Core.  In doing so, one dependency cycle is eliminated
because all the includes from Core to that project were dead
includes anyway.  In places where some files in other projects
were only compiling due to a transitive include from another
header, fixups have been made so that those files also include
the header they need.  Tested on Windows and Linux, and plan
to address failures on OSX and FreeBSD after watching the
bots.

llvm-svn: 299714
2017-04-06 21:28:29 +00:00
Zachary Turner 666cc0b291 Move DataBuffer / DataExtractor and friends from Core -> Utility.
llvm-svn: 296943
2017-03-04 01:30:05 +00:00
Zachary Turner bf9a77305f Move classes from Core -> Utility.
This moves the following classes from Core -> Utility.

ConstString
Error
RegularExpression
Stream
StreamString

The goal here is to get lldbUtility into a state where it has
no dependendencies except on itself and LLVM, so it can be the
starting point at which to start untangling LLDB's dependencies.
These are all low level and very widely used classes, and
previously lldbUtility had dependencies up to lldbCore in order
to use these classes.  So moving then down to lldbUtility makes
sense from both the short term and long term perspective in
solving this problem.

Differential Revision: https://reviews.llvm.org/D29427

llvm-svn: 293941
2017-02-02 21:39:50 +00:00
Mehdi Amini 36d33fc109 Use StringRef instead of raw pointers in MCAsmInfo/MCInstrInfo APIs (NFC)
llvm-svn: 283018
2016-10-01 06:46:33 +00:00
Nitesh Jain 817bc16d19 [LLDB][MIPS] Fix Emulation for JALR64 Instruction
Subscribers: jaydeep, bhushan, slthakur, sdardis, lldb-commits
llvm-svn: 281032
2016-09-09 10:46:25 +00:00
Kate Stone b9c1b51e45 *** This commit represents a complete reformatting of the LLDB source code
*** to conform to clang-format’s LLVM style.  This kind of mass change has
*** two obvious implications:

Firstly, merging this particular commit into a downstream fork may be a huge
effort.  Alternatively, it may be worth merging all changes up to this commit,
performing the same reformatting operation locally, and then discarding the
merge for this particular commit.  The commands used to accomplish this
reformatting were as follows (with current working directory as the root of
the repository):

    find . \( -iname "*.c" -or -iname "*.cpp" -or -iname "*.h" -or -iname "*.mm" \) -exec clang-format -i {} +
    find . -iname "*.py" -exec autopep8 --in-place --aggressive --aggressive {} + ;

The version of clang-format used was 3.9.0, and autopep8 was 1.2.4.

Secondly, “blame” style tools will generally point to this commit instead of
a meaningful prior commit.  There are alternatives available that will attempt
to look through this change and find the appropriate prior commit.  YMMV.

llvm-svn: 280751
2016-09-06 20:57:50 +00:00
Zachary Turner f343968f5d Delete Host/windows/win32.h
It's always hard to remember when to include this file, and
when you do include it it's hard to remember what preprocessor
check it needs to be behind, and then you further have to remember
whether it's windows.h or win32.h which you need to include.

This patch changes the name to PosixApi.h, which is more appropriately
named, and makes it independent of any preprocessor setting.

There's still the issue of people not knowing when to include this,
because there's not a well-defined set of things it exposes other
than "whatever is missing on Windows", but at least this should
make it less painful to fix when problems arise.

This patch depends on LLVM revision r278170.

llvm-svn: 278177
2016-08-09 23:06:08 +00:00
Nitesh Jain f5cadce1cd [LLVM][MIPS] Add (D)SUBU, (D)ADDU, LUI instructions emulation . Fix emulation for (D)ADDIU, SD/SW and LW/LD instructions
Reviewers: clayborg, jaydeep, bhushan

Subscribers: mohit.bhakkad, slthakur, sdardis, lldb-commits

Differential Revision: https://reviews.llvm.org/D20357

llvm-svn: 277426
2016-08-02 07:18:07 +00:00
Sagar Thakur 4a716226a5 [LLDB][MIPS] Fix Emulation of Compact branch and ADDIU instructions
Patch by Nitesh Jain.

This patch contains 2 changes:

  - Corrected target address calculation of compact branch instructions to reflect changes in disassembler (http://reviews.llvm.org/D17540).
  - Added emulation for (missing) 'Addiu' instruction.

Reviewers :jaydeep, bhushan, clayborg
Differential: http://reviews.llvm.org/D21064

llvm-svn: 273535
2016-06-23 06:40:37 +00:00
Ulrich Weigand b00ef10b70 Make Scalar::GetBytes and RegisterValue::GetBytes const
Scalar::GetBytes provides a non-const access to the underlying bytes
of the scalar value, supposedly allowing for modification of those
bytes.  However, even with the current implementation, this is not
really possible.  For floating-point scalars, the pointer returned
by GetBytes refers to a temporary copy; modifications to that copy
will be simply ignored.  For integer scalars, the pointer refers
to internal memory of the APInt implementation, which isn't
supposed to be directly modifyable; GetBytes simply casts aways
the const-ness of the pointer ...

With my upcoming patch to fix Scalar::GetBytes for big-endian
systems, this problem is going to get worse, since there we need
temporary copies even for some integer scalars.  Therefore, this
patch makes Scalar::GetBytes const, fixing all those problems.

As a follow-on change, RegisterValues::GetBytes must be made const
as well.  This in turn means that the way of initializing a
RegisterValue by doing a SetType followed by writing to GetBytes
no longer works.  Instead, I've changed SetValueFromData to do
the equivalent of SetType itself, and then re-implemented
SetFromMemoryData to work on top of SetValueFromData. 

There is still a need for RegisterValue::SetType, since some
platform-specific code uses it to reinterpret the contents of
an already filled RegisterValue.  To make this usage work in
all cases (even changing from a type implemented via Scalar
to a type implemented as a byte buffer), SetType now simply
copies the old contents out, and then reloads the RegisterValue
from this data using the new type via SetValueFromData.

This in turn means that there is no remaining caller of
Scalar::SetType, so it can be removed.

The only other follow-on change was in MIPS EmulateInstruction
code, where some uses of RegisterValue::GetBytes could be made
const trivially.

Differential Revision: http://reviews.llvm.org/D18980

llvm-svn: 266310
2016-04-14 14:31:08 +00:00
Benjamin Kramer 79dad1d056 Update for LLVM change
llvm-svn: 258819
2016-01-26 16:45:00 +00:00
Bhushan D. Attarde 2be2c9a6ce [LLDB][MIPS] Merge emulation of similar instructions for MIPS64
SUMMARY:
    This patch merges emulation of similar instructions into a single function (wherever possible) to remove code duplication.
    
    Reviewers: clayborg
    Subscribers: mohit.bhakkad, sagar, jaydeep, lldb-commits
    Differential Revision: http://reviews.llvm.org/D16051

llvm-svn: 257442
2016-01-12 03:56:58 +00:00
Mohit K. Bhakkad 87ef39a6a8 [LLDB][MIPS64] Adding mips64 reaturn address register for unwind plan
llvm-svn: 250267
2015-10-14 05:20:03 +00:00
Jason Molenda 63bd0db071 Clean up register naming conventions inside lldb.
"gcc" register numbers are now correctly referred to as "ehframe"
register numbers.  In almost all cases, ehframe and dwarf register
numbers are identical (the one exception is i386 darwin where ehframe
regnums were incorrect).

The old "gdb" register numbers, which I incorrectly thought were
stabs register numbers, are now referred to as "Process Plugin"
register numbers.  This is the register numbering scheme that the
remote process controller stub (lldb-server, gdbserver, core file
support, kdp server, remote jtag devices, etc) uses to refer to the
registers.  The process plugin register numbers may not be contiguous
- there are remote jtag devices that have gaps in their register
numbering schemes.

I removed all of the enums for "gdb" register numbers that we had
in lldb - these were meaningless - and I put LLDB_INVALID_REGNUM
in all of the register tables for the Process Plugin regnum slot.

This change is almost entirely mechnical; the one actual change in
here is to ProcessGDBRemote.cpp's ParseRegisters() which parses the
qXfer:features:read:target.xml response.  As it parses register
definitions from the xml, it will assign sequential numbers as the
eRegisterKindLLDB numbers (the lldb register numberings must be
sequential, without any gaps) and if the xml file specifies register
numbers, those will be used as the eRegisterKindProcessPlugin
register numbers (and those may have gaps).  A J-Link jtag device's
target.xml does contain a gap in register numbers, and it only 
specifies the register numbers for the registers after that gap.
The device supports many different ARM boards and probably selects
different part of its register file as appropriate.

http://reviews.llvm.org/D12791
<rdar://problem/22623262> 

llvm-svn: 247741
2015-09-15 23:20:34 +00:00
Mohit K. Bhakkad a73239f860 [LLDB][MIPS] MIPS load/store instruction emulation for hardware watchpoints
Reviewers: clayborg.
Subscribers: jaydeep, bhushan, sagar, nitesh.jain, lldb-commits.
Differential Revision: http://reviews.llvm.org/D12670

llvm-svn: 247129
2015-09-09 10:17:58 +00:00
Sagar Thakur 66089382d9 [MIPS64] Emulate MSA branch instructions
This patch adds MSA branch instruction emulation for MIPS64.

Reviewers: tberghammer, jaydeep
Subscribers: tberghammer, lldb-commits, nitesh.jain, mohit.bhakkad (Mohit Bhakkad), bhushan (Bhushan Attarde)
Differential: http://reviews.llvm.org/D12356
llvm-svn: 246745
2015-09-03 03:57:44 +00:00
Sagar Thakur 789da6678e [LLDB][MIPS] Fix offsets of all register sets and add MSA regset and FRE=1 mode support
This patch :

- Fixes offsets of all register sets for Mips.
- Adds MSA register set and FRE=1 mode support for FP register set.
- Separates lldb register numbers and register infos of freebsd/mips64 from linux/mips64.
- Re-orders the register numbers of all kinds for mips to be consistent with freebsd order of register numbers.

Reviewers: jaydeep, clayborg, jasonmolenda, ovyalov, emaste
Subscribers: tberghammer, ovyalov, emaste, mohit.bhakkad, nitesh.jain, bhushan
Differential: http://reviews.llvm.org/D10919
llvm-svn: 245217
2015-08-17 13:40:17 +00:00
Jaydeep Patil 831435042e [LLDB][MIPS] Handle false positives for MIPS hardware watchpoints
SUMMARY:
    Last 3bits of the watchpoint address are masked by the kernel. For example, n is 
    at 0x120010d00 and m is 0x120010d04. When a watchpoint is set at m, then watch 
    exception is generated even when n is read/written. To handle this case, instruction 
    at PC is emulated to find the base address of the load/store instruction. This address 
    is then appended to the description of the stop-info packet. Client then reads this 
    information to check whether the user has set a watchpoint on this address.
    
    Reviewers: jingham, clayborg
    Subscribers: nitesh.jain, mohit.bhakkad, sagar, bhushan and lldb-commits
    Differential Revision: http://reviews.llvm.org/D11672

llvm-svn: 244864
2015-08-13 03:44:09 +00:00
Oleksiy Vyalov 9dcdd2ee03 Revert r244308 since it's introducing test regressions on Linux:
- TestLldbGdbServer.py both clang & gcc, i386 and x86_64
 - TestConstVariables.py gcc, i386 and x86_64
 - 112 failures clang, i386

llvm-svn: 244514
2015-08-10 21:49:50 +00:00
Sagar Thakur d754890047 [LLDB][MIPS] Fix offsets of all register sets and add MSA regset and FRE=1 mode support
This change :

    - Fixes offsets of all register sets for Mips.
    - Adds MSA register set and FRE=1 mode support for FP register set.
    - Separates lldb register numbers and register infos of freebsd/mips64 from linux/mips64.
    - Re-orders the register numbers of all kinds for mips to be consistent with freebsd order of register numbers.
    - Eliminates ENABLE_128_BIT_SUPPORT and union ValueData from Scalar.cpp and uses llvm::APInt and llvm::APFloat for all integer and floating point types.

Reviewers : emaste, jaydeep, clayborg
Subscribers : emaste, mohit.bhakkad, nitesh.jain, bhushan
Differential : http://reviews.llvm.org/D10919

llvm-svn: 244308
2015-08-07 06:39:38 +00:00
Jaydeep Patil 501a781998 [LLDB][MIPS] Detect MIPS application specific extensions like micromips
SUMMARY:
    The patch detects MIPS application specific extensions (ASE) like micromips by reading 
    ELF header.e_flags and SHT_MIPS_ABIFLAGS section. MIPS triple does not contain ASE 
    information like micromips, mips16, DSP, MSA etc. These can be read from header.e_flags 
    or SHT_MIPS_ABIFLAGS section.
    
    Reviewers: clayborg
    Subscribers: mohit.bhakkad, sagar, lldb-commits
    Differential Revision: http://reviews.llvm.org/D11133

llvm-svn: 242381
2015-07-16 03:51:55 +00:00
Jaydeep Patil c60c94528c [LLDB][MIPS] MIPS32 branch emulation and single-stepping
SUMMARY:
    This patch implements
      1. Emulation of MIPS32 branch instructions
      2. Enable single-stepping for MIPS32 instructions
      3. Correction in emulation of MIPS64 branch instructions with delay slot
      4. Adjust breakpoint address when breakpoint is hit in a forbidden slot of compact branch instruction
    
    Reviewers: clayborg
    Subscribers: mohit.bhakkad, sagar, bhushan, lldb-commits, emaste, nitesh.jain
    Differential Revision: http://reviews.llvm.org/D10596

llvm-svn: 240373
2015-06-23 03:37:08 +00:00
Jaydeep Patil 30952b200b Test Commit
llvm-svn: 240280
2015-06-22 13:58:30 +00:00
Mohit K. Bhakkad 58975e82d4 A correction in rL239996
llvm-svn: 239998
2015-06-18 07:12:25 +00:00
Mohit K. Bhakkad 276a930eda [LLDB][MIPS] Emulation of MIPS64 floating-point branch instructions
Patch by Jaydeep Patil

SUMMARY:
1. Added emulation of MIPS64 floating-point branch instructions
2. Updated GetRegisterInfo to recognize floating-point registers
3. Provided CPU information while creating createMCSubtargetInfo in disassembler
4. Bug fix in emulation of JIC and JIALC
5. Correct identification of breakpoint when set in a delay slot of a branch instruction

Reviewers: clayborg
Subscribers: bhushan, mohit.bhakkad, sagar, nitesh.jain, lldb-commits.
Differential Revision: http://reviews.llvm.org/D10355

llvm-svn: 239996
2015-06-18 06:03:27 +00:00
Mohit K. Bhakkad d37be6374b [LLDB][MIPS] MIPS64 Branch instruction emulation for SW single stepping
Patch by Jaydeep Patil

Reviewers: clayborg, jasonmolenda
Subscribers: bhushan, mohit.bhakkad, sagar, lldb-commits.
Differential Revision: http://reviews.llvm.org/D10155

llvm-svn: 238820
2015-06-02 11:22:29 +00:00
Mohit K. Bhakkad 5bf047e5c4 A small fix in rL236696
llvm-svn: 236716
2015-05-07 11:43:23 +00:00
Mohit K. Bhakkad cdc22a889e [LLDB][MIPS] Software single stepping
Patch by Jaydeep Patil

Reviewers: clayborg, jasonmolenda
Subscribers: bhushan, mohit.bhakkad, sagar, lldb-commits.
Differential Revision: http://reviews.llvm.org/D9519

llvm-svn: 236696
2015-05-07 05:56:27 +00:00
Mohit K. Bhakkad 1c34f7cf18 [LLDB][MIPS] Emulate instruction using MCDisassembler
Patch by Jaydeep Patil

EmulateInstructionMIPS64 has been modified to use llvm::MCDisassembler instead of duplicating the decoding logic.
Added emulation of few branch instructions for software single stepping

Reviewers: clayborg, jasonmolenda
Subscribers: bhushan, mohit.bhakkad, sagar, lldb-commits.
Differential Revision: http://reviews.llvm.org/D9319

llvm-svn: 236411
2015-05-04 06:28:04 +00:00
Mohit K. Bhakkad e8659b5df6 [LLDB][MIPS] Add MIPS32 and MIPS64 core revisions
Patch by Jaydeep Patil

Added MIPS32 and MIPS64 core revisions. This would be followed by register context and emulate-instruction for MIPS32.

DYLDRendezvous.cpp:
On Linux link map struct does not contain extra load offset field.

Reviewers: clayborg
Subscribers: bhushan, mohit.bhakkad, sagar, lldb-commits.
Differential Revision: http://reviews.llvm.org/D9190

llvm-svn: 235574
2015-04-23 06:36:20 +00:00
Pavel Labath 61984d39d5 Fix a typo in EmulateInstructioinMIPS64
llvm-svn: 232620
2015-03-18 09:57:10 +00:00
Bhushan D. Attarde 29e5937cd9 Initial Assembly profiler for mips64
Summary:
This is initial implementation of assembly profiler which only scans prologue/epilogue assembly instructions to create CFI instructions.

Reviewers: clayborg, jasonmolenda

Differential Revision: http://reviews.llvm.org/D7696

llvm-svn: 232619
2015-03-18 09:21:29 +00:00