97d5cc165a
Making TableGen'd instruction selection code non-recursive. This fixes PR805.
...
llvm-svn: 29548
2006-08-07 22:17:58 +00:00
b359a7a69c
Remove some extraneous newlines.
...
llvm-svn: 29492
2006-08-03 00:42:26 +00:00
6379c96c07
Really add support for compilers without noinline
...
llvm-svn: 29491
2006-08-03 00:26:13 +00:00
70c4ae4bda
Pass N by reference to select functions to prevent gcc from allocating more stack.
...
llvm-svn: 29423
2006-08-01 01:07:48 +00:00
c1163d2fa7
Remove an unneeded match condition: the type check for root node has been
...
moved to outside the actual select routine.
llvm-svn: 29415
2006-07-31 19:01:58 +00:00
149130ad6b
Split each select function for a particular opcode into multiple ones. One
...
per possible ValueType of the node. e.g. Select_add is split into Select_add_i8,
Select_add_i16, etc.
For opcodes which do not produce a non-chain result, it is split on the
ValueType of its first non-chain operand. e.g. Select_store.
On X86 / Mac OS X, Select_store used to be the largest function. It had a stack
frame size of 8.5k. Now the largest one is Store_i32 with a frame size of 3.1k.
llvm-svn: 29404
2006-07-28 22:51:01 +00:00
75a22216f7
Clean up.
...
llvm-svn: 29378
2006-07-28 01:19:22 +00:00
e2a3f7014d
Rename IsFoldableBy to CanBeFoldedleBy
...
llvm-svn: 29376
2006-07-28 01:03:48 +00:00
b572401bea
Remove InFlightSet hack. No longer needed.
...
llvm-svn: 29373
2006-07-28 00:47:19 +00:00
7b0ed57543
Remove dead code.
...
llvm-svn: 29359
2006-07-27 19:59:34 +00:00
061aba35c1
Let each target specific isel provide routine to check if a chain producing node is foldable by another.
...
llvm-svn: 29335
2006-07-27 06:36:49 +00:00
9384400d83
Fix for bug 840. Only use noinline attribute if gcc version >= 3.4
...
llvm-svn: 29311
2006-07-26 23:06:27 +00:00
774d8fd1ef
Removed a hack intended to allow (store (op (load))) folding. Will handle this with preprocessing.
...
llvm-svn: 29258
2006-07-21 22:19:51 +00:00
4b49c23571
Eliminate data relocations by using NULL instead of global empty list.
...
llvm-svn: 29250
2006-07-21 21:15:20 +00:00
4e153f1b91
Use an enumeration to eliminate data relocations.
...
llvm-svn: 29249
2006-07-21 20:57:35 +00:00
c62c697955
Also checks for noResults field.
...
llvm-svn: 29235
2006-07-20 23:36:20 +00:00
2884b5cc93
Make sub- and super- register classes const.
...
llvm-svn: 29200
2006-07-19 05:58:18 +00:00
3650465273
Fix a bug handling instructions, like blr, which just consist of a text
...
string. The return value of printInstruction should be true for these.
llvm-svn: 29196
2006-07-19 01:39:06 +00:00
c767acd25a
Add code size to target instruction use it as the 3rd isel sorting tie-breaker.
...
llvm-svn: 29193
2006-07-19 00:24:41 +00:00
aeccc6e676
Make sub- super- reg-class tables static.
...
llvm-svn: 29190
2006-07-18 22:18:31 +00:00
68ee5cfe10
Fix case where identical cases were not detected across case #0 , because
...
instructions not handled would have a case value of #0 , throwing things off.
This marginally shrinks the X86 asmprinter, but shrinks the sparc asmwriter
by 25 lines.
llvm-svn: 29187
2006-07-18 19:27:30 +00:00
6e17208dff
Fix an accidentally duplicated line that caused tblgen to crash on itanium.
...
Add an assert that catches the real problem earlier.
llvm-svn: 29185
2006-07-18 19:06:01 +00:00
edee52570c
Maximally group commands. When all instructions within a command set have a
...
series of identical commands, handle them all with one switch. In the case
of the x86 at&t asm printer, only 3 switches are needed for all instructions.
llvm-svn: 29184
2006-07-18 18:28:27 +00:00
cb0c848d34
Change generator to remove operands as it processes them. No change in
...
generated file.
llvm-svn: 29183
2006-07-18 17:56:07 +00:00
9d250696b7
Handle the last operand more intelligently. When emitting the \n, also
...
return from the asmprinter to make the generated asmprinter both more
efficient and smaller.
llvm-svn: 29182
2006-07-18 17:50:22 +00:00
75dcf6cbd8
Emit switches with 1/2 cases as unconditional code or an if/then/else for
...
tidyness.
llvm-svn: 29181
2006-07-18 17:43:54 +00:00
66e288bec3
Steal bits from the asm string index to use for operand information. On both
...
x86 and ppc, this gets us 4 more bits to play with, since the string indices
both only use 12 bits.
llvm-svn: 29180
2006-07-18 17:38:46 +00:00
1ac0eb7f8b
Merge operand info and asmstr idx into a single 32-bit field. No other change.
...
llvm-svn: 29179
2006-07-18 17:32:27 +00:00
692374c748
Completely change the structure of the generated asmprinter to be more table
...
based and less switch-statements-with-hundreds-of-cases based. This shrinks
the x86 asmprinters to about 1/3 their previous size.
Other improvements coming.
llvm-svn: 29177
2006-07-18 17:18:03 +00:00
95454e7a2f
Use __attribute__((noinline)) only if compiled by gcc.
...
llvm-svn: 29161
2006-07-16 06:14:37 +00:00
87b2fe9474
Parameterize target node ValueType to allow more sharing of emit functions.
...
Also reduce the number of arguments passed to emit functions and removed a
hack.
llvm-svn: 29160
2006-07-16 06:12:52 +00:00
69367fedd2
Reduce instruction selection code size and stack frame size by factoring
...
code that emit target specific nodes into emit functions that are uniquified
and shared among selection routines.
e.g. This reduces X86ISelDAGToDAG.o (release) from ~2M to ~1.5M. Stack frame
size of Select_store from ~13k down to ~8k.
This is the first step. Further work to enable more sharing will follow.
llvm-svn: 29158
2006-07-15 08:45:20 +00:00
45fcadc9f0
The generated index array should be const.
...
llvm-svn: 29155
2006-07-14 23:14:02 +00:00
e32982cc52
Emit the string information for the asm writer as a single large string
...
and index into it, instead of emitting it like this:
static const char * const OpStrs[] = {
"PHINODE\n", // PHI
0, // INLINEASM
"adc ", // ADC32mi
"adc ", // ADC32mi8
...
The old way required thousands of relocations that slows down link time and
dynamic load times.
This also cuts about 10K off each of the X86 asmprinters, and should shrink
the others as well.
llvm-svn: 29152
2006-07-14 22:59:11 +00:00
10d4b040ac
Clean up.
...
llvm-svn: 29137
2006-07-13 22:17:08 +00:00
a44f6269bf
1. Simplfy bit operations.
...
2. Coalesce instruction cases.
llvm-svn: 29135
2006-07-13 21:02:53 +00:00
23bd480cea
Move base value of instruction to lookup table to prepare for case reduction.
...
llvm-svn: 29122
2006-07-12 19:15:43 +00:00
f7300b2706
It was pointed out that DEBUG() is only available with -debug.
...
llvm-svn: 29106
2006-07-11 18:25:13 +00:00
c3d341ea98
Ensure that dump calls that are associated with asserts are removed from
...
non-debug build.
llvm-svn: 29105
2006-07-11 17:58:07 +00:00
57e4363171
Reduce bloat in target libraries by removing per machine instruction assertion
...
from code emitter generation.
llvm-svn: 29097
2006-07-11 01:25:59 +00:00
f0858cb910
tblgen uses EH
...
llvm-svn: 29034
2006-07-07 00:21:17 +00:00
d19938834b
Ugly hack! Add helper functions InsertInFlightSetEntry and
...
RemoveInFlightSetEntry. They are used in place of direct set operators to
reduce instruction selection function stack size.
llvm-svn: 28987
2006-06-29 23:57:05 +00:00
3c71a13e06
Fix an error message regression. Print:
...
LI8: (LI8:i64 (imm:i64):$imm)
instead of:
LI8: (LI8:MVT::i64 (imm:MVT::i64):$imm)
llvm-svn: 28868
2006-06-20 00:56:37 +00:00
c23e641055
Don't require src/dst patterns to be able to fully resolve their types,
...
because information about one can help refine the other. This allows us to
write:
def : Pat<(i32 (extload xaddr:$src, i8)),
(LBZX xaddr:$src)>;
as:
def : Pat<(extload xaddr:$src, i8),
(LBZX xaddr:$src)>;
because tblgen knows LBZX returns i32.
llvm-svn: 28865
2006-06-20 00:31:27 +00:00
9500b343db
Make sure to use the result of the pattern to infer the result type of the
...
instruction, and the result type of the instruction to refine the pattern.
This allows us to write things like this:
def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
as:
def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (VR128:$src)>
and fixes a ppc64 issue.
llvm-svn: 28863
2006-06-20 00:18:02 +00:00
4b464768d1
Improve a comment.
...
llvm-svn: 28833
2006-06-16 18:25:06 +00:00
55772ccfd6
Instructions with variable operands (variable_ops) can have a number required
...
operands. e.g.
def CALL32r : I<0xFF, MRM2r, (ops GR32:$dst, variable_ops),
"call {*}$dst", [(X86call GR32:$dst)]>;
TableGen should emit operand informations for the "required" operands.
Added a target instruction info flag M_VARIABLE_OPS to indicate the target
instruction may have more operands in addition to the minimum required
operands.
llvm-svn: 28791
2006-06-15 07:22:16 +00:00
5d038cf802
Allow more use of iPTR in patterns.
...
llvm-svn: 28790
2006-06-15 00:16:37 +00:00
ff7c28dfdd
Added support for variable_ops.
...
llvm-svn: 28788
2006-06-14 22:22:20 +00:00
1ce02e4c49
Fix support for optional input flag.
...
llvm-svn: 28784
2006-06-14 19:27:50 +00:00
632ee8de55
getOperandNum(): error if specified operand number is out of range.
...
llvm-svn: 28775
2006-06-13 21:47:27 +00:00
deafba0325
Wrap to 80 cols
...
llvm-svn: 28743
2006-06-09 23:59:44 +00:00
5cb722f320
Don't build tblgen with -pedantic or -Wno-long-long
...
llvm-svn: 28638
2006-06-01 18:20:23 +00:00
cc8c0233b6
Can't trust NodeDepth when checking for possibility of load folding creating
...
a cycle. This increase the search space and will increase compile time (in
practice it appears to be small, e.g. 176.gcc goes from 62 sec to 65 sec)
that will be addressed later.
llvm-svn: 28476
2006-05-25 20:16:55 +00:00
07a4e5ceb1
Fixed a really ugly bug. The TableGen'd isel is not freeing the "inflight set"
...
correctly. That is causing non-deterministic behavior (and possibly preventing
some load folding from happening).
llvm-svn: 28458
2006-05-25 00:21:44 +00:00
e7549961cf
Don't make zero-sized static arrays
...
llvm-svn: 28448
2006-05-24 17:31:02 +00:00
aa2372562e
Patches to make the LLVM sources more -pedantic clean. Patch provided
...
by Anton Korobeynikov! This is a step towards closing PR786.
llvm-svn: 28447
2006-05-24 17:04:05 +00:00
886e8f35aa
Now that iPTR is a fully resolved type. We end up losing the type check for
...
patterns that look like this:
def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
InsertOneTypeCheck should copy the type from the resolved pattern to the
unresolved one as long as there types are different.
llvm-svn: 28389
2006-05-19 07:24:32 +00:00
d8e2f6ebc1
lib/Target/Target.td
...
llvm-svn: 28386
2006-05-18 20:42:07 +00:00
fe72285033
Don't generate getCalleeSaveReg and getCalleeSaveRegClasses anymore.
...
llvm-svn: 28376
2006-05-18 00:08:46 +00:00
318a68e1ee
Typo
...
llvm-svn: 28366
2006-05-17 20:55:51 +00:00
f5ef47fe74
Remove PointerType from target definition. Use abstract type MVT::iPTR to
...
represent pointer type.
llvm-svn: 28363
2006-05-17 20:37:59 +00:00
d985d66781
Allow patterns to refer to physical registers that belong to multiple
...
register classes.
llvm-svn: 28323
2006-05-16 07:05:30 +00:00
21c7c23d7e
Noop instruction
...
llvm-svn: 28241
2006-05-12 07:47:00 +00:00
e2c1aedc23
Unused instruction
...
llvm-svn: 28240
2006-05-12 07:42:01 +00:00
229a6d0026
Also add super- register classes info.
...
llvm-svn: 28221
2006-05-11 07:30:26 +00:00
32982836b6
Watch out for the following case:
...
1. Use expects a chain output.
2. Node is expanded into multiple target ops.
3. One of the inner node produces a chain, the outer most one doesn't.
llvm-svn: 28209
2006-05-10 02:47:57 +00:00
d2b8067748
Fix a load folding bug. It is exposed by a multi- resulting instructions
...
def : Pat<> pattern.
llvm-svn: 28208
2006-05-10 00:05:46 +00:00
5e7ba0b049
Add sub-register class information.
...
llvm-svn: 28195
2006-05-09 06:34:26 +00:00
386fb9b0fd
Set isStore of instructions with ISD::TRUNCSTORE root node.
...
llvm-svn: 28075
2006-05-03 02:08:34 +00:00
4b177f089e
Put instruction names into the first non TargetInstrInfo namespace found.
...
llvm-svn: 28043
2006-05-01 23:46:16 +00:00
017b93dd7c
instructions can be in different namespaces. Make sure to use the right
...
one for each instruction.
llvm-svn: 28038
2006-05-01 17:01:17 +00:00
8e63393bc3
Formating
...
llvm-svn: 28036
2006-05-01 09:30:17 +00:00
c2ef5e34a8
Mark instructions whose pattern is (store ...) isStore.
...
llvm-svn: 28032
2006-05-01 09:04:20 +00:00
c5e8ce8b8c
Remove the temporary option: -no-isel-fold-inflight
...
llvm-svn: 28012
2006-04-28 18:54:11 +00:00
54acf6eddc
When isel'ing a node, mark its operands "InFlight" before selecting them. These
...
nodes should not be folded into other nodes.
This fixes the miscompilation of PR 749.
Temporarily under flag control.
llvm-svn: 28002
2006-04-28 02:08:10 +00:00
4ca2ea5b43
JumpTable support! What this represents is working asm and jit support for
...
x86 and ppc for 100% dense switch statements when relocations are non-PIC.
This support will be extended and enhanced in the coming days to support
PIC, and less dense forms of jump tables.
llvm-svn: 27947
2006-04-22 18:53:45 +00:00
778509c844
Don't fill in fields that no longer exist.
...
llvm-svn: 27898
2006-04-20 18:32:22 +00:00
9235d848b7
Rename AddedCost to AddedComplexity.
...
llvm-svn: 27841
2006-04-19 20:36:09 +00:00
aa3325e925
Allow "let AddedCost = n in" to increase pattern complexity.
...
llvm-svn: 27834
2006-04-19 18:07:24 +00:00
56fdf9ed40
Add missing things to the distribution.
...
llvm-svn: 27650
2006-04-13 06:27:20 +00:00
989b16e488
Fix a typo: Instr* -> Intr*
...
llvm-svn: 27568
2006-04-10 22:02:59 +00:00
726df0bb82
Infer element types for shuffle masks
...
llvm-svn: 27456
2006-04-06 20:36:51 +00:00
09575a9b0a
rename a method, to avoid confusion with llvm intrinsics.
...
llvm-svn: 27455
2006-04-06 20:19:52 +00:00
89df307b61
Adjust the Intrinsics.gen interface a little bit
...
llvm-svn: 27345
2006-04-02 03:35:30 +00:00
470d0181e9
regenerate
...
llvm-svn: 27313
2006-03-31 21:54:11 +00:00
51ffbf18f0
Generalize the previous binary operator support and add a string concatenation
...
operation. This implements Regression/TableGen/strconcat.td.
llvm-svn: 27312
2006-03-31 21:53:49 +00:00
6b7ccbe4d8
Allow bits init values to be used in patterns, turn them into ints.
...
llvm-svn: 27286
2006-03-31 05:25:56 +00:00
03dfc41ba2
Final bugfix for PR724. GCC won't inline varargs functions, so use one to
...
validate the prototype of intrinsic functions. This prevents GCC from going
crazy and inlining too much stuff, eventually running out of memory.
llvm-svn: 27283
2006-03-31 04:48:26 +00:00
3abe174165
When emitting code for the verifier, instead of emitting each case statement
...
independently, batch up checks so that identically typed intrinsics share
verifier code. This dramatically reduces the size of the verifier function,
which should help avoid GCC running out of memory compiling Verifier.cpp.
llvm-svn: 27281
2006-03-31 04:24:58 +00:00
bab91842ba
regenerate
...
llvm-svn: 27264
2006-03-30 22:51:12 +00:00
b59cf3cff4
Implement Regression/TableGen/DagDefSubst.ll
...
llvm-svn: 27263
2006-03-30 22:50:40 +00:00
c2c8b58cf6
Don't sort the names before outputing the intrinsic name table. It causes a
...
mismatch against the enum table.
This is a part of Sabre's master plan to drive me nuts with subtle bugs that
happens to only affect x86 be. :-)
llvm-svn: 27237
2006-03-28 22:25:56 +00:00
7c9740a9ed
Tblgen doesn't like multiple SDNode<> definitions that map to the sameenum value. Split them into separate enums.
...
Also, don't emit dynamic checks when we can compute them statically
llvm-svn: 27202
2006-03-28 00:41:33 +00:00
8a2ae8b766
Only compute intrinsic valuetypes when in a target .td file.
...
llvm-svn: 27197
2006-03-28 00:15:00 +00:00
ac2512a261
revert this, it breaks things.
...
llvm-svn: 27196
2006-03-28 00:03:08 +00:00
c92f688ef3
Add support for decoding iPTR to the right pointer type.
...
llvm-svn: 27188
2006-03-27 22:48:18 +00:00
5386598187
Print error messages like this:
...
tblgen: In STVEBX: Intrinsic 'llvm.ppc.altivec.stvebx' expects 3 operands, not 2 operands!
instead of like this:
tblgen: In STVEBX: Intrinsic 'intrinsic_void expects 3 operands, not 2 operands!
llvm-svn: 27185
2006-03-27 22:21:18 +00:00
8c46ff2d12
Add a missing check which cause an invalid .td file to crash tblgen
...
llvm-svn: 27126
2006-03-25 22:12:44 +00:00
23555e3947
When failing selection for an intrinsic, print this:
...
Cannot yet select: intrinsic %llvm.ppc.altivec.lvx
instead of this:
Cannot yet select: 0x9b047e0: v4i32,ch = INTRINSIC 0x9b04540:1, 0x9b04710, 0x9b04790, 0x9b04540
llvm-svn: 27110
2006-03-25 06:47:53 +00:00
c8565ed651
Change approach so that we get codegen for free for intrinsics. With this,
...
intrinsics that don't take pointer arguments now work. For example, we can
compile this:
int test3( __m128d *A) {
return _mm_movemask_pd(*A);
}
int test4( __m128 *A) {
return _mm_movemask_ps(*A);
}
to this:
_test3:
movl 4(%esp), %eax
movapd (%eax), %xmm0
movmskpd %xmm0, %eax
ret
_test4:
movl 4(%esp), %eax
movaps (%eax), %xmm0
movmskps %xmm0, %eax
ret
llvm-svn: 27090
2006-03-24 23:10:39 +00:00
85586baee7
fix 80 column violations
...
llvm-svn: 27084
2006-03-24 21:52:20 +00:00
e352e7aa85
Parse intrinsics correctly and perform type propagation. This doesn't currently
...
emit the code to select intrinsics, but that is next :)
llvm-svn: 27082
2006-03-24 21:48:51 +00:00
f0729b4067
Add dwarf register numbering to register data.
...
llvm-svn: 27081
2006-03-24 21:15:58 +00:00
bbba823706
Make sure to initialize the TheDef field!
...
llvm-svn: 27078
2006-03-24 20:25:01 +00:00
2c58141fd9
Move CodeGenIntrinsic implementation to CodeGenTarget.cpp with the rest of
...
the CodeGen* implementations.
Parse the MVT::ValueType for each operand of the intrinsics.
llvm-svn: 27075
2006-03-24 19:49:31 +00:00
97b0d99651
extract some more information from the intrinsic table
...
llvm-svn: 27022
2006-03-24 01:13:55 +00:00
1e0552f838
Add new generated files to be ignored.
...
llvm-svn: 27011
2006-03-23 23:45:32 +00:00
eb0ce0c547
Allow result node to be a simple leaf node. This enable bitconvert patterns
...
like this:
def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
llvm-svn: 26968
2006-03-23 02:35:32 +00:00
c0af9c6478
Don't forget to promote xform function to an explicit node for def : Pat<>
...
patterns.
llvm-svn: 26929
2006-03-21 20:44:17 +00:00
02ad00ad93
minor code simplification
...
llvm-svn: 26918
2006-03-21 06:42:58 +00:00
af7de1fba8
The node wrapped in PatLeaf<> should be treated as a leaf even if it isn't
...
one, i.e. don't select it.
llvm-svn: 26909
2006-03-20 22:53:06 +00:00
5ece6fa3e0
It should be ok for a xform output type to be different from input type.
...
llvm-svn: 26899
2006-03-20 08:09:17 +00:00
a84bdebfd2
Copy matching pattern's output type info to instruction result pattern.
...
The instruction patterns do not contain enough information to resolve the
exact type of the destination if it of a generic vector type.
llvm-svn: 26892
2006-03-20 06:04:09 +00:00
c1b31d8a83
Add a new SDTCisIntVectorOfSameSize type constraint
...
llvm-svn: 26890
2006-03-20 05:39:48 +00:00
f9d75843f3
getEnumName() missed v8i8, v4i16, and v2i32 types
...
llvm-svn: 26869
2006-03-19 07:57:34 +00:00
f878f6aa54
Fix miscodegen of V_SET0 in PPC.
...
llvm-svn: 26836
2006-03-18 00:40:36 +00:00
09ffafcf54
allow the GCCBuiltinName field to be optional
...
llvm-svn: 26784
2006-03-15 19:15:26 +00:00
c4e2468251
Fix VC++ build error.
...
llvm-svn: 26773
2006-03-15 02:51:05 +00:00
1c32e04b5f
remove typo
...
llvm-svn: 26772
2006-03-15 02:05:38 +00:00
da1a4cc6a4
Autogenerate a table of intrinsic names, so we can map from intrinsic ID to
...
LLVM intrinsic function name.
llvm-svn: 26771
2006-03-15 01:55:21 +00:00
402a573764
Autogenerate code to map from GCC builtin to LLVM intrinsic.
...
llvm-svn: 26770
2006-03-15 01:33:26 +00:00
3eb12e9a2a
Add a newline at the end to avoid gcc warnings.
...
llvm-svn: 26749
2006-03-14 05:59:52 +00:00
fea17a9901
emit a mapping from LLVM intrinsic -> GCC builtins.
...
llvm-svn: 26736
2006-03-13 23:08:44 +00:00
5b6ec4a5ea
Verify that packed type operands have the right size and base type.
...
llvm-svn: 26735
2006-03-13 22:38:57 +00:00
69035f00e3
fix pasto in generate assertion msg
...
llvm-svn: 26706
2006-03-11 00:20:47 +00:00
e3c2db3955
generate side-effect info
...
llvm-svn: 26672
2006-03-09 22:37:52 +00:00
06c7300bf1
Parse mod/ref properties, autogen mod/ref information
...
llvm-svn: 26669
2006-03-09 22:30:49 +00:00
6efe863a70
parse intrinsic types
...
autogenerate an intrinsic verifier
llvm-svn: 26666
2006-03-09 22:05:04 +00:00
6d8104efd2
autogenerate the function name recognizer
...
llvm-svn: 26663
2006-03-09 20:34:19 +00:00
c47620b5d8
Temporary hack to enable more (store (op (load ...))) folding. This makes
...
it possible when a TokenFactor is between the load and store. But is still
missing some cases due to ordering issue.
llvm-svn: 26638
2006-03-09 08:19:11 +00:00
0fab08eae3
Don't generate silly matching code like this:
...
if (N1.getOpcode() == ISD::ADD &&
...)
if (... &&
(N1.getNumOperands() == 1 || !isNonImmUse(N1.Val, N10.Val))) &&
...)
TableGen knows N1 must have more than one operand.
llvm-svn: 26592
2006-03-07 08:31:27 +00:00
ae0f1512c9
Silence a warning.
...
llvm-svn: 26508
2006-03-03 19:34:28 +00:00
f6e846eee8
Fix pasteo
...
llvm-svn: 26499
2006-03-03 06:13:41 +00:00
94f300d15c
remove a bunch of long-dead testing code
...
llvm-svn: 26497
2006-03-03 02:34:28 +00:00
c313d0b712
initial implementation of intrinsic parsing
...
llvm-svn: 26495
2006-03-03 02:32:46 +00:00
73fbe145fd
remove out of date comment
...
llvm-svn: 26492
2006-03-03 02:04:07 +00:00
1edf15e48e
Add support for "-Ifoo" in addition to "-I foo"
...
llvm-svn: 26487
2006-03-03 01:53:40 +00:00
d7f6b55afa
Regenerate
...
llvm-svn: 26486
2006-03-03 01:47:37 +00:00
e7b74c5da1
add support for multiple include directories
...
llvm-svn: 26485
2006-03-03 01:47:14 +00:00
53a2d60bca
New vector type v2f32.
...
llvm-svn: 26437
2006-03-01 01:10:52 +00:00
dc445eadc0
Select inline asm memory operands.
...
llvm-svn: 26349
2006-02-24 02:13:31 +00:00
43070b7541
Added x86 integer vector types: 64-bit packed byte integer (v16i8), 64-bit
...
packed word integer (v8i16), and 64-bit packed doubleword integer (v2i32).
llvm-svn: 26294
2006-02-20 22:34:53 +00:00
0add83e969
Fix bugs identified by VC++.
...
llvm-svn: 26287
2006-02-18 03:20:33 +00:00
33f4156663
Bump up pattern cost if the resulting instruction is marked
...
usesCustomDAGSchedInserter.
llvm-svn: 26282
2006-02-18 02:33:09 +00:00
3e15eac81b
Check the new form for bison output into CVS
...
llvm-svn: 26208
2006-02-15 07:24:01 +00:00
ecd162d5cd
Adjust to new form of handling lexer dependencies, this way shouldn't have
...
the problems the old way did.
llvm-svn: 26161
2006-02-14 05:13:13 +00:00
5940bc210e
Call InsertISelMapEntry rather than map insertion operator to prevent overly
...
aggrssive inlining. This reduces Select_store frame size from 24k to 10k.
llvm-svn: 26095
2006-02-09 22:12:27 +00:00
9ce762d51f
Match getTargetNode() changes (now returns SDNode* instead of SDOperand).
...
llvm-svn: 26084
2006-02-09 07:16:09 +00:00
6dc90ca172
Change Select() from
...
SDOperand Select(SDOperand N);
to
void Select(SDOperand &Result, SDOperand N);
llvm-svn: 26067
2006-02-09 00:37:58 +00:00
1630c2848f
Hoist all SDOperand declarations within a Select_{opcode}() to the top level
...
to reduce stack memory usage. This is intended to work around the gcc bug.
llvm-svn: 26026
2006-02-07 00:37:41 +00:00
5c76b499aa
Add support for modifier strings in machine instr descriptions. This allows
...
us to avoid creating lots of "Operand" types with different printers, instead
we can fold several together and use modifiers. For example, we can now use:
${target:call} to say that the operand should be printed like a 'call' operand.
llvm-svn: 26024
2006-02-06 23:40:48 +00:00
033e32e5d9
Simplify the variant handling code, no functionality change.
...
llvm-svn: 26023
2006-02-06 22:43:28 +00:00
ebf05bea1b
At the end of isel, select a replacement node for each handle that does not
...
have one. This can happen if a load's real uses are dead (i.e. they do not
have uses themselves).
llvm-svn: 26014
2006-02-06 08:12:55 +00:00
308d0090e6
Name change.
...
llvm-svn: 26013
2006-02-06 06:03:35 +00:00
aa26555b25
Handle HANDLENODE: just return itself.
...
llvm-svn: 26011
2006-02-05 08:46:14 +00:00
368f20e53d
Allow more loads to be folded which were previously prevented from happening
...
due to ordering issue. i.e. they were selected for chain use first.
Now at load select time, check if it is being selected for a chain use and if
it has only a single real use. If so, return a HANDLENODE (with the load as
its operand) in its place and record it.
When it is folded or the load is selected for a real use, the isel records it
as the replacement for the HANDLENODE. The replacement is done when all nodes
are selected.
This scheme exposed a couple of problems where cycles can happen. (See comments
in EmitMatchCode() for descriptions of the problems and their workaround /
solutions.) These problems have been resolved with a small compile time
penality.
llvm-svn: 25995
2006-02-05 06:43:12 +00:00
7ab4579c68
Re-committing the last bit of change. It shouldn't break PPC this time.
...
llvm-svn: 25982
2006-02-05 05:22:18 +00:00
586b06281c
Temporarily revert the last change, which breaks PPC and other targets that
...
DO select things.
llvm-svn: 25970
2006-02-04 09:23:06 +00:00
ce87cac555
Complex pattern's custom matcher should not call Select() on any operands.
...
Select them afterwards if it returns true.
llvm-svn: 25968
2006-02-04 08:50:49 +00:00
2bcfc52af6
node predicates add to the complexity of a pattern. This ensures that the
...
X86 backend attempts to match small-immediate versions of instructions before
the full size immediate versions.
llvm-svn: 25937
2006-02-03 18:06:02 +00:00
717db484a5
(store (op (load ...))) folding problem. In the generated matching code,
...
Chain is initially set to the chain operand of store node, when it reaches
load, if it matches the load then Chain is set to the chain operand of the
load.
However, if the matching code that follows this fails, isel moves on to the
next pattern but it does not restore Chain to the chain operand of the store.
So when it tries to match the next store / op / load pattern it would fail on
the Chain == load.getOperand(0) test.
The solution is for each chain operand to get a unique name. e.g. Chain10.
llvm-svn: 25931
2006-02-03 06:22:41 +00:00
244e800c19
add a note, ya knoe
...
llvm-svn: 25880
2006-02-01 19:12:23 +00:00
88e616d803
If a pattern's root node is a constant, its size should be 3 rather than 2.
...
llvm-svn: 25870
2006-02-01 06:06:31 +00:00
0d3ef40656
implement test/Regression/TableGen/DagIntSubst.ll
...
llvm-svn: 25836
2006-01-31 06:02:35 +00:00
a8821624d4
simplify some code
...
llvm-svn: 25791
2006-01-29 20:01:35 +00:00
1af077c0c7
it is nice not to chop off bits for those blessed with lots of bits
...
llvm-svn: 25766
2006-01-29 05:22:37 +00:00
49f323a90e
make the casts actually cast to the variable type
...
llvm-svn: 25765
2006-01-29 05:17:22 +00:00
c438c51e82
start of the 64bit safety cleanup
...
llvm-svn: 25764
2006-01-29 05:07:04 +00:00
0e352963fd
Emit series of conditionals with &&, emitting stuff like this:
...
if (N1.getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
!CodeGenMap.count(N1.getValue(0)) &&
!CodeGenMap.count(N1.getValue(1))) {
instead of this:
if (N1.getOpcode() == ISD::LOAD) {
if (N1.hasOneUse()) {
if (!CodeGenMap.count(N1.getValue(0))) {
if (!CodeGenMap.count(N1.getValue(1))) {
llvm-svn: 25763
2006-01-29 04:41:05 +00:00
7c0149d1d6
Factor matching code that is common between patterns. This works around
...
GCC not jump-threading across this common code, and produces far nicer
output.
llvm-svn: 25762
2006-01-29 04:25:26 +00:00
d3a63de91e
Split out code generation from analysis from emission
...
llvm-svn: 25759
2006-01-29 02:57:39 +00:00
afe9baeb69
move some code around, no change in the generated code
...
llvm-svn: 25758
2006-01-29 02:43:35 +00:00
5255c6c627
now that we have control over emission of the code, emit the code using nested
...
"if" statements (indenting it appropriately, of course) instead of using goto's.
This inverts the logic for all of the if statements, which makes things simpler
to understand in addition to making the generated code easier to read.
llvm-svn: 25757
2006-01-28 20:43:52 +00:00
4c4da201bf
Change PatternCodeEmitter to emit code into a buffer instead of emitting it
...
directly to the output file. This makes things simple because the code doesn't
have to worry about indentation or the case when there is no goto. It also
allows us to indent the code better without touching everything :)
llvm-svn: 25756
2006-01-28 20:31:24 +00:00
a7d6bbff00
Fit to 80 columns, no functionality change
...
llvm-svn: 25752
2006-01-28 19:06:51 +00:00
e251e92c23
Teach tablegen to generate code that is VC++ warning-free.
...
llvm-svn: 25709
2006-01-27 22:22:28 +00:00
e555a92c8d
(store (op (load ...)), ...)
...
If store's chain operand is load, then use load's chain operand instead. If
it isn't (likely a TokenFactor), then do not allow the folding.
llvm-svn: 25708
2006-01-27 22:13:45 +00:00
d98701c639
Subtarget feature can now set any variable to any value
...
llvm-svn: 25678
2006-01-27 08:09:42 +00:00
4d5a93ed28
Use printInlineAsm to, well, print inline asm's.
...
llvm-svn: 25677
2006-01-27 02:10:50 +00:00
543fe4b6aa
PHI and INLINEASM are now builtin instructions provided by Target.td
...
llvm-svn: 25673
2006-01-27 01:45:06 +00:00
db2a5f09f1
If we want to emit things in enum order, use getInstructionsByEnumValue to
...
get the order, don't compute it ourselves.
Don't emit stuff like (14<<0), emit 14 instead.
Don't attempt to get target properties for builtin instructions.
llvm-svn: 25672
2006-01-27 01:44:09 +00:00
ac8b13b32b
There is at least a 'noitinerary' itinerary now
...
llvm-svn: 25671
2006-01-27 01:41:55 +00:00
ec249a3d30
Don't emit JIT code for these instructions
...
llvm-svn: 25669
2006-01-27 01:39:38 +00:00
5815669251
Teach the dag selectors to select InlineAsm nodes.
...
Aren't we happy the pattern selectors are almost all gone?
llvm-svn: 25666
2006-01-26 23:08:55 +00:00
e9025f1f3b
Another folding problem: if a node r/w chain or flag, don't fold it if it
...
has already been selected. The number of use check is not strong enough since
a node can be replaced with newly created target node. e.g. If the original
node has two uses, when it is selected for one of the uses it is replaced with
another. Each node now has a single use but isel still should not fold it.
llvm-svn: 25651
2006-01-26 19:13:45 +00:00
dc8365d4f3
Add a FIXME comment.
...
llvm-svn: 25635
2006-01-26 02:13:31 +00:00
ecfaa0a1c9
Incoming (and optional) flag bugs. They may be embedded inside a inner node of
...
a pattern. Also, nodes which take incoming flag should not be folded if it has
more than one use.
llvm-svn: 25627
2006-01-26 00:22:25 +00:00
c5c228fa59
Fix an optional in flag bug.
...
llvm-svn: 25590
2006-01-24 20:46:50 +00:00
295e196558
Optional InFlag was not being included in node.
...
llvm-svn: 25588
2006-01-24 20:07:38 +00:00
e272b4ec17
Prevent folding of a node with multiple uses if the node already folds a load!
...
Here is an example where the load ended up being done twice:
%A = global uint 0
uint %test(uint %B, ubyte %C) {
%tmp = load uint *%A;
%X = shl uint %tmp, ubyte %C
%Cv = sub ubyte 32, %C
%Y = shr uint %B, ubyte %Cv
%Z = or uint %Y, %X
store uint %Z, uint* %A
ret uint %Z
}
==>
subl $4, %esp
movl %ebx, (%esp)
movl 8(%esp), %edx
movl A, %eax
movb 12(%esp), %bl
movb %bl, %cl
shldl %cl, %edx, %eax
movb %bl, %cl
shldl %cl, %edx, A
movl (%esp), %ebx
addl $4, %esp
ret
llvm-svn: 25471
2006-01-20 01:11:03 +00:00
9e7fb7b2fc
Bug fix. Flag operand number may be calculated incorrectly.
...
llvm-svn: 25465
2006-01-19 21:57:10 +00:00
a15731cd50
Use pattern information to determine whether the use expects this
...
instruction to produce a result. e.g MUL8m, the instruction does not
produce a explicit result. However it produces an implicit result in
AL which would be copied to a temp. The root operator of the matching
pattern is a mul so the use would expect it to produce a result.
llvm-svn: 25458
2006-01-19 10:12:58 +00:00
acec02ebf5
Prevent unnecessary CopyToReg when the same HW register appears in two spots
...
in the pattern.
llvm-svn: 25437
2006-01-19 01:55:45 +00:00
dce31c8d70
fix a broken comment
...
llvm-svn: 25411
2006-01-17 21:31:18 +00:00
5ed803256d
Regenerated the Lex and Yacc output files on Linux. It seems that our
...
Linux machines don't like the source code generated on MacOS X for some
reason.
llvm-svn: 25394
2006-01-17 17:01:34 +00:00
61864ec3fe
Emit a type matching check for ComplexPatterns.
...
llvm-svn: 25392
2006-01-17 07:36:41 +00:00
a039d439dc
Type inferencing bug
...
llvm-svn: 25337
2006-01-15 10:04:45 +00:00
bd1de84121
Allow transformation from GlobalAddress to TargetGlobalAddress and
...
ExternalSymbol to TargetExternalSymbol.
llvm-svn: 25252
2006-01-12 19:35:54 +00:00
e6300aaabc
GlobalAddress -> TargetGlobalAddress; ExternalSymbol -> TargetExternalSymbol
...
llvm-svn: 25245
2006-01-12 07:54:57 +00:00
Evan Cheng