fe6e405e8c
Fix the ridiculous SubtargetFeatures API where it implicitly expects CPU name to
...
be the first encoded as the first feature. It then uses the CPU name to look up
features / scheduling itineray even though clients know full well the CPU name
being used to query these properties.
The fix is to just have the clients explictly pass the CPU name!
llvm-svn: 134127
2011-06-30 01:53:36 +00:00
eaf77dc2bd
Update comment for getRegForInlineAsmConstraint for Mips.
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llvm-svn: 134087
2011-06-29 19:33:04 +00:00
9519c08a43
Remove getRegClassForInlineAsmConstraint for Mips.
...
Part of rdar://9643582
llvm-svn: 134084
2011-06-29 19:04:31 +00:00
8264e272a9
Sink SubtargetFeature and TargetInstrItineraries (renamed MCInstrItineraries) into MC.
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llvm-svn: 134049
2011-06-29 01:14:12 +00:00
194c3dc01f
Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo.
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llvm-svn: 134030
2011-06-28 21:14:33 +00:00
0beca53a29
Hide more details in tablegen generated MCRegisterInfo ctor function.
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llvm-svn: 134027
2011-06-28 20:44:22 +00:00
1e210d08d8
Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.inc
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llvm-svn: 134024
2011-06-28 20:07:07 +00:00
6cc775f905
- Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and
...
sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.
llvm-svn: 134021
2011-06-28 19:10:37 +00:00
d9997acd14
Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.inc
...
into XXXGenRegisterInfo.inc.
llvm-svn: 133922
2011-06-27 18:32:37 +00:00
35792089e7
Change the chain input of nodes that load the address of a function. This change
...
enables SelectionDAG::getLoad at MipsISelLowering.cpp:1914 to return a
pre-existing node instead of redundantly create a new node every time it is
called.
llvm-svn: 133811
2011-06-24 19:01:25 +00:00
ca88b4abec
Prevent generation of redundant addiu instructions that compute address of
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static variables or functions.
llvm-svn: 133803
2011-06-24 17:55:19 +00:00
247533179a
Starting to refactor Target to separate out code that's needed to fully describe
...
target machine from those that are only needed by codegen. The goal is to
sink the essential target description into MC layer so we can start building
MC based tools without needing to link in the entire codegen.
First step is to refactor TargetRegisterInfo. This patch added a base class
MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to
separate register description from the rest of the stuff.
llvm-svn: 133782
2011-06-24 01:44:41 +00:00
27029885f0
Add A0 and A1 to the list of registers used for returning a value in order to
...
handle functions with return type Complex long long.
llvm-svn: 133497
2011-06-21 01:28:11 +00:00
5b350be79d
Coding style fixes.
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llvm-svn: 133496
2011-06-21 01:02:03 +00:00
4c406e7457
Re-apply 132758 and 132768 which were speculatively reverted in 132777.
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llvm-svn: 133494
2011-06-21 00:40:49 +00:00
5444a7b4cd
Silence warnings in non assert builds. Patch by David Blaikie
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llvm-svn: 133118
2011-06-16 00:40:02 +00:00
99f35eab45
Use set operations instead of plain lists to enumerate register classes.
...
This simplifies many of the target description files since it is common
for register classes to be related or contain sequences of numbered
registers.
I have verified that this doesn't change the files generated by TableGen
for ARM and X86. It alters the allocation order of MBlaze GPR and Mips
FGR32 registers, but I believe the change is benign.
llvm-svn: 133105
2011-06-15 23:28:14 +00:00
5750ca7089
Remove custom allocation order boilerplate that is no longer needed.
...
The register allocators automatically filter out reserved registers and
place the callee saved registers last in the allocation order, so custom
methods are no longer necessary just for that.
Some targets still use custom allocation orders:
ARM/Thumb: The high registers are removed from GPR in thumb mode. The
NEON allocation orders prefer to use non-VFP2 registers first.
X86: The GR8 classes omit AH-DH in x86-64 mode to avoid REX trouble.
SystemZ: Some of the allocation orders are omitting R12 aliases without
explanation. I don't understand this target well enough to fix that. It
looks like all the boilerplate could be removed by reserving the right
registers.
llvm-svn: 132781
2011-06-09 16:56:59 +00:00
f15601f19a
Speculatively revert 132758 and 132768 to try to fix the Windows buildbots.
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llvm-svn: 132777
2011-06-09 16:03:19 +00:00
0683a7212e
Initial support for inline asm memory operand constraints.
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llvm-svn: 132768
2011-06-09 03:31:05 +00:00
0713a9d8fc
Add a parameter to CCState so that it can access the MachineFunction.
...
No functional change.
Part of PR6965
llvm-svn: 132763
2011-06-08 23:55:35 +00:00
4e9af454f7
Fix bug in lowering of DYNAMIC_STACKALLOC nodes. The correct offset of the
...
dynamically allocated stack area was not set.
llvm-svn: 132758
2011-06-08 21:28:09 +00:00
195a1e2184
Reorganize code in MipsTargetLowering::LowerCall to improve readability.
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llvm-svn: 132756
2011-06-08 17:39:33 +00:00
41956cf6e3
Refactor MipsTargetLowering::EmitInstrWithCustomInserter.
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llvm-svn: 132726
2011-06-07 19:28:39 +00:00
e99b08d6c3
Put back removed line.
...
llvm-svn: 132725
2011-06-07 19:03:14 +00:00
1550678765
Coding style fixes.
...
- Fix indentation.
- Move comments.
- Fit lines in 80 columns.
- Remove dead code.
llvm-svn: 132724
2011-06-07 18:58:42 +00:00
dde4aac02b
Use tabs to separate opcode and operand strings.
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llvm-svn: 132718
2011-06-07 18:16:51 +00:00
d8373a4680
Add comments for wrapper node patterns in MipsInstrInfo.td.
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llvm-svn: 132717
2011-06-07 18:00:14 +00:00
08b7a779ef
Add test case for C++ exception handling and fix the following mistakes in MipsFrameLowering::emitPrologue:
...
- cfi directives are not inserted at the right location or in the right order.
- The source MachineLocation for the cfi directive that changes the cfa register
to $fp should be MachineLocation::VirtualFP.
- A PROLOG_LABEL that marks the beginning of cfi_offset directives for
callee-saved register is emitted even when no callee-saved registers are
saved.
- When a callee-saved double precision register is saved, two cfi_offset
directives, one for each of the paired single precision registers, should be
emitted.
llvm-svn: 132703
2011-06-07 02:17:21 +00:00
2446869410
Detect FI|cst pattern in MipsDAGToDAGISel::SelectAddr. Patch by Sasa Stankovic.
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llvm-svn: 132448
2011-06-02 01:03:14 +00:00
6627752050
Custom-lower FRAMEADDR. Patch by Sasa Stankovic.
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llvm-svn: 132444
2011-06-02 00:24:44 +00:00
f771a0f490
Fix uninitialized variables and silence warnings
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llvm-svn: 132355
2011-05-31 20:25:26 +00:00
98fc4c8bbc
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor,
...
nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions.
The intrinsics are implemented by creating pseudo-instructions, which are
then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter.
Patch by Sasa Stankovic.
llvm-svn: 132323
2011-05-31 02:54:07 +00:00
bf3c1251e0
This patch implements the thread local storage. Implemented are General
...
Dynamic, Initial Exec and Local Exec TLS models.
Patch by Sasa Stankovic
llvm-svn: 132322
2011-05-31 02:53:58 +00:00
08600bcf65
Use the dwarf->llvm mapping to print register names in the cfi
...
directives.
Fixes PR9826.
llvm-svn: 132317
2011-05-30 20:20:15 +00:00
fd75d45b88
Remove the dwarf numbers from the D registers. They don't have dwarf numbers
...
and should probably be encoded as
DW_OP_reg 32 DW_OP_piece 4 DW_OP_reg 33
llvm-svn: 132274
2011-05-29 02:21:01 +00:00
a6664cdbf0
Change the set of callee-saved registers for non-MIPS32 architectures specified
...
in MipsRegisterInfo::getCalleeSavedRegs so that both registers paired for a
double precision register get saved.
llvm-svn: 132243
2011-05-28 01:41:05 +00:00
b406843fe5
Define a wrapper node for target constant nodes (tglobaladdr, etc.).
...
Need this to prevent emitting illegal conditional move instructions.
llvm-svn: 132240
2011-05-28 01:07:07 +00:00
077964a03c
Use MachineFrameInfo::hasCalls instead of MipsFunctionInfo::hasCall to check if
...
a function has any function calls.
llvm-svn: 132140
2011-05-26 20:30:31 +00:00
e3a07a3b42
Fix some dwarf register numbers.
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llvm-svn: 132136
2011-05-26 19:25:47 +00:00
aa560006ed
Add support for C++ exception handling.
...
llvm-svn: 132131
2011-05-26 18:59:03 +00:00
8062bf36b4
Set HasSetDirective to true.
...
llvm-svn: 132127
2011-05-26 18:16:18 +00:00
fa63d3096d
Define WeakRefDirective.
...
llvm-svn: 132098
2011-05-25 23:30:30 +00:00
f1412e4d2f
Remove MipsTargetLowering::LowerFP_TO_SINT. Patterns for fp_to_sint have already
...
been defined in MipsInstrFPU.td.
llvm-svn: 132076
2011-05-25 20:08:05 +00:00
44eba3ac49
Custom-lower FCOPYSIGN nodes.
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llvm-svn: 132074
2011-05-25 19:32:07 +00:00
d72cc55fcc
Update MaxCallFrameSize regardless of the relocation model selected.
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llvm-svn: 132070
2011-05-25 18:08:32 +00:00
92a26d4e18
Change initial value of MaxCallFrameSize. MipsFI::getMaxCallFrameSize() should
...
return 0 if there are no function calls made.
llvm-svn: 132065
2011-05-25 17:52:48 +00:00
46662e0f91
Coding style fixes. Added comments.
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llvm-svn: 132063
2011-05-25 17:32:06 +00:00
aac670c1c8
Fix lowering of DYNAMIC_STACKALLOC nodes.
...
llvm-svn: 132030
2011-05-25 02:20:00 +00:00
2db176c4c1
Enable printing of immediates that do not fit in 16-bit. .cprestore can have
...
offsets that are larger than 0x10000.
llvm-svn: 132003
2011-05-24 21:22:21 +00:00
5e16c6a9b2
Implement byval structure argument passing. The following limitations or
...
deficiencies exist:
- Works only if ABI is o32.
- Zero-sized structures cannot be passed.
- There is a lot of redundancy in generated code.
llvm-svn: 131986
2011-05-24 19:18:33 +00:00
cb4a1a8d3f
Simplify offset calculation of stack frame objects for $gp restore location and
...
variable arguments in LowerCall and LowerFormalArguments. This should also fix
the bug in which handling of variable arguments is incorrect when the front-end
optimizes away unused fixed arguments.
llvm-svn: 131942
2011-05-24 00:23:52 +00:00
dfb8cda11f
Expand f64 FPOW.
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llvm-svn: 131928
2011-05-23 22:23:58 +00:00
6af5bd2537
Add pattern for double-to-integer conversion. Patch by Sasa Stankovic.
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llvm-svn: 131927
2011-05-23 22:16:43 +00:00
9dbb45b596
Fixes related to coding style.
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llvm-svn: 131922
2011-05-23 21:13:59 +00:00
90d96f44ce
Fix MipsAsmPrinter::printSavedRegsBitmaskChange. Remove functions and variables
...
in MipsFunctionInfo that are no longer used.
llvm-svn: 131917
2011-05-23 20:34:30 +00:00
f9e5750fc8
Change StackDirection from StackGrowsUp to StackGrowsDown.
...
The following improvements are accomplished as a result of applying this patch:
- Fixed frame objects' offsets (relative to either the virtual frame pointer or
the stack pointer) are set before instruction selection is completed. There is
no need to wait until Prologue/Epilogue Insertion is run to set them.
- Calculation of final offsets of fixed frame objects is straightforward. It is
no longer necessary to assign negative offsets to fixed objects for incoming
arguments in order to distinguish them from the others.
- Since a fixed object has its relative offset set during instruction
selection, there is no need to conservatively set its alignment to 4.
- It is no longer necessary to reorder non-fixed frame objects in
MipsFrameLowering::adjustMipsStackFrame.
llvm-svn: 131915
2011-05-23 20:16:59 +00:00
2df6c010aa
Use the correct register to access stack frame objects.
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llvm-svn: 131785
2011-05-21 03:01:03 +00:00
f084fcd7fe
Insert instructions that copy $sp to or from $fp at the right locations.
...
llvm-svn: 131784
2011-05-21 02:29:26 +00:00
0837692ac6
Change the order fixed objects are created in MipsTargetLowering::LowerCall in
...
preparation for reversing StackDirection.
Fixed objects are created in the following order:
1. Incoming arguments passed on stack.
2. va_arg objects (include both arguments that are passed in registers and
pointer to the location of the first va_arg argument).
3. $gp restore slot.
4. Outgoing arguments passed on stack.
5. Pointer to alloca'd space.
llvm-svn: 131767
2011-05-20 23:22:14 +00:00
7c619f174a
In CC_MipsO32, allocate a stack space regardless of whether the argument is
...
passed in register or on the stack.
llvm-svn: 131758
2011-05-20 21:39:54 +00:00
cae19e8671
Define functions that get/set maximum call frame size.
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llvm-svn: 131752
2011-05-20 20:11:17 +00:00
43407fe633
Make $fp and $ra callee-saved registers and let PrologEpilogInserter handle
...
saving and restoring them.
llvm-svn: 131745
2011-05-20 18:39:33 +00:00
cc7a928885
Remove noisy semicolons.
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llvm-svn: 131724
2011-05-20 09:20:25 +00:00
fe4f9d5977
Fix bug in which nodes that write to argument registers do not get glued with the JALR node. Patch by Sasa Stankovic
...
llvm-svn: 131714
2011-05-20 02:30:51 +00:00
7489faa0c1
Remove code that creates unnecessary frame objects.
...
llvm-svn: 131711
2011-05-20 01:45:06 +00:00
d738c0f7c9
Define variables and functions in MipsFunctionInfo.
...
This is the first of a series of patches that attempt to simplify handling of
stack frame objects.
llvm-svn: 131710
2011-05-20 01:17:58 +00:00
9e6a8cca5d
Align i64 arguments to 64 bit boundaries.
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llvm-svn: 131668
2011-05-19 20:29:48 +00:00
05fd5aa1d0
Increase number of available registers when target is MIPS32.
...
llvm-svn: 131660
2011-05-19 18:25:03 +00:00
92ab6db6c8
Simplify CC_MipsO32 and merge it with CC_MipsO32_VarArgs. Patch by Sasa Stankovic.
...
llvm-svn: 131657
2011-05-19 18:06:05 +00:00
d1465bd68b
Fix data layout string. i64 is aligned to 64 bit boundaries.
...
llvm-svn: 131642
2011-05-19 17:21:09 +00:00
e50a3d16e9
Fix setting of isCommutable flag.
...
llvm-svn: 131233
2011-05-12 17:42:08 +00:00
5dc19f916c
Fix td file comments for Mips.
...
Patch by Liu <proljc@gmail.com>!
llvm-svn: 131086
2011-05-09 18:16:46 +00:00
cbb7fa68ed
1. Keep lines in 80 columns.
...
2. Remove unused function.
3. Correct indentation.
llvm-svn: 131028
2011-05-06 22:11:29 +00:00
2518f8376d
Make the logic for determining function alignment more explicit. No functionality change.
...
llvm-svn: 131012
2011-05-06 20:34:06 +00:00
2998e6ce46
Fix cmake build.
...
llvm-svn: 130850
2011-05-04 18:46:56 +00:00
23e8ecf125
Prevent instructions using $gp from being placed between a jalr and the instruction that restores the clobbered $gp.
...
llvm-svn: 130847
2011-05-04 17:54:27 +00:00
22fc723818
Fix function MipsRegisterInfo::getRegisterNumbering.
...
llvm-svn: 130774
2011-05-03 18:41:54 +00:00
0e7ee666b7
Lower BlockAddress node when relocation-model is static.
...
llvm-svn: 130131
2011-04-25 17:10:45 +00:00
56ca6292dc
Fix comment typo. Noticed by Liu.
...
llvm-svn: 130120
2011-04-25 06:21:43 +00:00
e24891251c
Reverse unnecessary changes made in r129606 and r129608. There is no change in functionality.
...
llvm-svn: 129612
2011-04-15 21:51:11 +00:00
d56f2d910b
Fix lines that exceed 80 columns. There is no change in functionality.
...
llvm-svn: 129608
2011-04-15 21:06:38 +00:00
aef55c8801
Fix lines that have incorrect indentation or exceed 80 columns. There is no change in functionality.
...
llvm-svn: 129606
2011-04-15 21:00:26 +00:00
7583dbdc88
Fix cmake build.
...
llvm-svn: 129601
2011-04-15 20:34:45 +00:00
279169771b
Add pass that expands pseudo instructions into target instructions after register allocation. Define pseudos that get expanded into mtc1 or mfc1 instructions.
...
llvm-svn: 129594
2011-04-15 19:52:08 +00:00
0ab5e2cded
Fix a ton of comment typos found by codespell. Patch by
...
Luis Felipe Strano Moraes!
llvm-svn: 129558
2011-04-15 05:18:47 +00:00
052163e6d3
Fix indentation.
...
llvm-svn: 129105
2011-04-07 20:25:10 +00:00
94ee37e487
Update ATUsed every time after expandRegLargeImmPair is called.
...
llvm-svn: 129104
2011-04-07 20:23:26 +00:00
d6f1c58914
Fix handling of functions with internal linkage.
...
llvm-svn: 129099
2011-04-07 19:51:44 +00:00
5ec2ead9b0
Move transformation of JmpLink and related nodes done during instruction selection to Legalize phase.
...
llvm-svn: 128830
2011-04-04 17:11:07 +00:00
4111db6575
Undo changes mistakenly made in revision 128750.
...
llvm-svn: 128751
2011-04-02 00:26:12 +00:00
977f555a76
Insert space before ';' to prevent warnings.
...
llvm-svn: 128750
2011-04-02 00:15:58 +00:00
3d9df607ba
Remove redundant code. There are assignments to variables Base and Offset right after the code that is removed.
...
llvm-svn: 128742
2011-04-01 21:56:02 +00:00
56d9ef53a2
Simplifies logic for printing target flags.
...
llvm-svn: 128741
2011-04-01 21:41:06 +00:00
e625ba46b7
Modifies MipsAsmPrinter::isBlockOnlyReachableByFallthrough so that it handles delay slots correctly.
...
llvm-svn: 128724
2011-04-01 18:57:38 +00:00
93f898f643
Add code for analyzing FP branches. Clean up branch Analysis functions.
...
llvm-svn: 128718
2011-04-01 17:39:08 +00:00
a535270d91
Added support for FP conditional move instructions and fixed bugs in handling of FP comparisons.
...
llvm-svn: 128650
2011-03-31 18:26:17 +00:00
4e9ca1b3ba
fixed typo
...
llvm-svn: 128574
2011-03-30 21:15:35 +00:00
05a23b1e61
silence a conditional assignment -Wuninitialized warning.
...
llvm-svn: 127453
2011-03-11 02:12:51 +00:00
048ffabe78
Improve varags handling, with testcases. Patch by Sasa Stankovic
...
llvm-svn: 127349
2011-03-09 19:22:22 +00:00
Evan Cheng