6f9bf658a7
treat conditional branches the same way as conditional moves (giving them
...
an operand that contains the condcode), making things significantly simpler.
llvm-svn: 25840
2006-01-31 06:56:30 +00:00
21ec192419
compactify all of the integer conditional moves into one instruction that takes
...
a CC as an operand. Much smaller, much happier.
llvm-svn: 25839
2006-01-31 06:49:09 +00:00
196d58373c
Add immediate forms of integer cmovs
...
llvm-svn: 25838
2006-01-31 06:24:29 +00:00
283492b4fe
Shrinkify
...
llvm-svn: 25837
2006-01-31 06:18:16 +00:00
70c9e42593
Add the full complement of conditional moves of integer registers.
...
llvm-svn: 25834
2006-01-31 05:26:36 +00:00
b6493b3165
Compile this:
...
void %X(int %A) {
%C = setlt int %A, 123 ; <bool> [#uses=1]
br bool %C, label %T, label %F
T: ; preds = %0
call int %main( int 0 ) ; <int>:0 [#uses=0]
ret void
F: ; preds = %0
ret void
}
to this:
X:
save -96, %o6, %o6
subcc %i0, 122, %l0
bg .LBBX_2 ! F
nop
...
not this:
X:
save -96, %o6, %o6
sethi 0, %l0
or %g0, 1, %l1
subcc %i0, 122, %l2
bg .LBBX_4 !
nop
.LBBX_3: !
or %g0, %l0, %l1
.LBBX_4: !
subcc %l1, 0, %l0
bne .LBBX_2 ! F
nop
llvm-svn: 25833
2006-01-31 05:05:52 +00:00
2dd217b88f
Added custom lowering of fabs
...
llvm-svn: 25831
2006-01-31 03:14:29 +00:00
a9bfca8d1e
add the 'lucas' optimization
...
llvm-svn: 25830
2006-01-31 02:55:28 +00:00
0e70729e83
I don't see why this optimization isn't safe, but it isn't, so disable it
...
llvm-svn: 25829
2006-01-31 02:45:52 +00:00
d916e78b0a
Another high-prio selection performance bug
...
llvm-svn: 25828
2006-01-31 02:10:06 +00:00
2b70a6f853
more mumbling
...
llvm-svn: 25826
2006-01-31 00:45:37 +00:00
b521361fb9
add some notes
...
llvm-svn: 25825
2006-01-31 00:20:38 +00:00
45df7f84ff
Don't generate complex sequence for SETOLE, SETOLT, SETULT, and SETUGT. Flip
...
the order of the compare operands and generate SETOGT, SETOGE, SETUGE, and
SETULE instead.
llvm-svn: 25824
2006-01-30 23:41:35 +00:00
9a90572374
Fix FP constants, and the SparcV8/2006-01-22-BitConvertLegalize.ll failure from last night
...
llvm-svn: 25819
2006-01-30 22:20:49 +00:00
08390f6a21
i64 -> f32, f32 -> i64 and some clean up.
...
llvm-svn: 25818
2006-01-30 22:13:22 +00:00
5b97fcf0f5
Always use FP stack instructions to perform i64 to f64 as well as f64 to i64
...
conversions. SSE does not have instructions to handle these tasks.
llvm-svn: 25817
2006-01-30 08:02:57 +00:00
37faeb2b02
Revamp the ICC/FCC reading instructions to be parameterized in terms of the
...
SPARC condition codes, not in terms of the DAG condcodes. This allows us to
write nice clean patterns for cmovs/branches.
llvm-svn: 25815
2006-01-30 07:43:04 +00:00
33a79cae7c
Compile:
...
uint %test(uint %X) {
%Y = call uint %llvm.ctpop.i32(uint %X)
ret uint %Y
}
to:
test:
save -96, %o6, %o6
sll %i0, 0, %l0
popc %l0, %i0
restore %g0, %g0, %g0
retl
nop
instead of to 40 logical ops. Note the shift-by-zero that clears the top
part of the 64-bit V9 register.
Testcase here: CodeGen/SparcV8/ctpop.ll
llvm-svn: 25814
2006-01-30 06:14:02 +00:00
321e337d95
If the target has V9 instructions, this pass is a noop, don't bother
...
running it.
llvm-svn: 25811
2006-01-30 05:51:14 +00:00
90d3fd9e7c
When in v9 mode, emit fabsd/fnegd/fmovd
...
llvm-svn: 25810
2006-01-30 05:48:37 +00:00
99dcb95e14
First step towards V9 instructions in the V8 backend, two conditional move
...
patterns. This allows emission of this code:
t1:
save -96, %o6, %o6
subcc %i0, %i1, %l0
move %icc, %i0, %i2
or %g0, %i2, %i0
restore %g0, %g0, %g0
retl
nop
instead of this:
t1:
save -96, %o6, %o6
subcc %i0, %i1, %l0
be .LBBt1_2 !
nop
.LBBt1_1: !
or %g0, %i2, %i0
.LBBt1_2: !
restore %g0, %g0, %g0
retl
nop
for this:
int %t1(int %a, int %b, int %c) {
%tmp.2 = seteq int %a, %b
%tmp3 = select bool %tmp.2, int %a, int %c
ret int %tmp3
}
llvm-svn: 25809
2006-01-30 05:35:57 +00:00
238fe93242
Two changes:
...
1. Default to having V9 instructions, instead of just V8.
2. unless -enable-sparc-v9-insts is passed, disable V9 (for use with llcbeta)
llvm-svn: 25807
2006-01-30 04:57:43 +00:00
af209b8b13
When lowering SELECT_CC, see if the input is a lowered SETCC. If so, fold
...
the two operations together. This allows us to compile this:
void %two(int %a, int* %b) {
%tmp.2 = seteq int %a, 0
%tmp.0.0 = select bool %tmp.2, int 10, int 20
store int %tmp.0.0, int* %b
ret void
}
into:
two:
save -96, %o6, %o6
or %g0, 20, %l0
or %g0, 10, %l1
subcc %i0, 0, %l2
be .LBBtwo_2 ! entry
nop
.LBBtwo_1: ! entry
or %g0, %l0, %l1
.LBBtwo_2: ! entry
st %l1, [%i1]
restore %g0, %g0, %g0
retl
nop
instead of:
two:
save -96, %o6, %o6
sethi 0, %l0
or %g0, 1, %l1
or %g0, 20, %l2
or %g0, 10, %l3
subcc %i0, 0, %l4
be .LBBtwo_2 ! entry
nop
.LBBtwo_1: ! entry
or %g0, %l0, %l1
.LBBtwo_2: ! entry
subcc %l1, 0, %l0
bne .LBBtwo_4 ! entry
nop
.LBBtwo_3: ! entry
or %g0, %l2, %l3
.LBBtwo_4: ! entry
st %l3, [%i1]
restore %g0, %g0, %g0
retl
nop
llvm-svn: 25806
2006-01-30 04:34:44 +00:00
f0b24d2dc0
Move MaskedValueIsZero from the DAGCombiner to the TargetLowering interface,making isMaskedValueZeroForTargetNode simpler, and useable from other partsof the compiler.
...
llvm-svn: 25803
2006-01-30 04:09:27 +00:00
4ac0fa2aa5
Implement isMaskedValueZeroForTargetNode for the various v8 selectcc nodes,
...
allowing redundant and's to be eliminated by the dag combiner.
llvm-svn: 25800
2006-01-30 03:51:45 +00:00
c6fa0282d2
adjust prototype
...
llvm-svn: 25798
2006-01-30 03:49:07 +00:00
32058cfb7b
Functions that are lazily streamed in from the .bc file are *not* external.
...
This fixes llvm-test/SingleSource/UnitTests/2006-01-29-SimpleIndirectCall.c
and PR704
llvm-svn: 25793
2006-01-29 20:49:17 +00:00
3c6a950653
add another note
...
llvm-svn: 25789
2006-01-29 09:46:06 +00:00
dabee1f655
add some performance notes from looking at sgefa
...
llvm-svn: 25788
2006-01-29 09:42:20 +00:00
7c7cbde0e5
add a high-priority SSE issue from sgefa
...
llvm-svn: 25787
2006-01-29 09:14:47 +00:00
5a7a22c9dd
add a missed optimization
...
llvm-svn: 25786
2006-01-29 09:08:15 +00:00
3072af4d4f
Now that OpActions is big enough, we can specify actions for vector types
...
llvm-svn: 25784
2006-01-29 08:41:37 +00:00
8a4a3deaf9
clean up interface to ValueTypeActions
...
llvm-svn: 25783
2006-01-29 08:41:12 +00:00
d7738e6b32
disable this for now
...
llvm-svn: 25778
2006-01-29 07:31:33 +00:00
0c05a2c99c
Add a note about lowering llvm.memset, llvm.memcpy, and llvm.memmove to a
...
few stores under certain conditions.
llvm-svn: 25777
2006-01-29 06:48:25 +00:00
35d20a4c00
remove now-dead code, the legalizer takes care of this for us
...
llvm-svn: 25776
2006-01-29 06:45:31 +00:00
132177e103
The FP stack doesn't support UNDEF, ask the legalizer to legalize it
...
instead of lying and saying we have it.
llvm-svn: 25775
2006-01-29 06:44:22 +00:00
d33c60b52b
Request expansion of ConstantVec nodes.
...
llvm-svn: 25773
2006-01-29 06:32:58 +00:00
61c9a8e942
Targets all now request ConstantFP to be legalized into TargetConstantFP.
...
'fpimm' in .td files is now TargetConstantFP.
llvm-svn: 25771
2006-01-29 06:26:08 +00:00
b5f0ba6051
Update alpha to reflect recent constantfp legalize changes. It's not clear
...
why all this code isn't autogenerated. :(
llvm-svn: 25770
2006-01-29 06:25:22 +00:00
1b09c6ba87
cmovle != cmovlt
...
llvm-svn: 25761
2006-01-29 03:47:30 +00:00
4ab39e43e8
Fix typo.
...
llvm-svn: 25760
2006-01-29 03:45:35 +00:00
8643ea67b1
Flesh out AMD family/models.
...
llvm-svn: 25755
2006-01-28 20:30:18 +00:00
58ca0be9af
Correctly determine CPU vendor.
...
llvm-svn: 25754
2006-01-28 19:48:34 +00:00
71287085a1
Use union instead of reinterpret_cast.
...
llvm-svn: 25751
2006-01-28 18:47:32 +00:00
b5de47cd9a
Fix recognition of Intel CPUs.
...
llvm-svn: 25750
2006-01-28 18:38:20 +00:00
b3ab2d3a42
Is64Bit reflects the capability of the chip, not an aspect of the target os
...
llvm-svn: 25749
2006-01-28 18:23:48 +00:00
be08957dc5
Fix a bunch of JIT failures with the new isel
...
llvm-svn: 25748
2006-01-28 18:19:37 +00:00
e128d5f724
Improve X86 subtarget support for Windows and AMD.
...
llvm-svn: 25747
2006-01-28 18:09:06 +00:00
ccd2a20c4b
silence a warning
...
llvm-svn: 25745
2006-01-28 10:34:47 +00:00
30432e07f0
Fix a bug in my elimination of ISD::CALL this morning. PPC now has to
...
provide the expansion for i64 calls itself
llvm-svn: 25735
2006-01-28 07:33:03 +00:00
dc8bbb6527
make this work on non-native hosts
...
llvm-svn: 25734
2006-01-28 06:05:41 +00:00
0c7b4666a3
add a note about how we should implement this FIXME from the legalizer:
...
// FIXME: revisit this when we have some kind of mechanism by which targets
// can decided legality of vector constants, of which there may be very
// many.
llvm-svn: 25733
2006-01-28 05:40:47 +00:00
595ec734fc
Implement Promote for VAARG, and allow it to be custom promoted for people
...
who don't want the default behavior (Alpha).
llvm-svn: 25726
2006-01-28 03:14:31 +00:00
6c82262289
Add a couple more things to the readme.
...
llvm-svn: 25724
2006-01-28 01:22:10 +00:00
b292de6703
Remove some dead code
...
llvm-svn: 25719
2006-01-28 00:02:51 +00:00
2c00db82bd
Switch to AlphaISD::CALL instead of ISD::CALL
...
llvm-svn: 25718
2006-01-27 23:39:00 +00:00
f424a66524
Use PPCISD::CALL instead of ISD::CALL
...
llvm-svn: 25717
2006-01-27 23:34:02 +00:00
a9382ca59e
Use V8ISD::CALL instead of ISD::CALL
...
llvm-svn: 25716
2006-01-27 23:30:03 +00:00
18243826fd
A bit of wisdom from Chris on the last entry.
...
llvm-svn: 25715
2006-01-27 22:54:32 +00:00
63045d221b
AT&T assembly convention: registers are in lower case.
...
llvm-svn: 25714
2006-01-27 22:53:29 +00:00
a502b93fae
initialize member vars
...
llvm-svn: 25712
2006-01-27 22:38:36 +00:00
dbfc299915
initialize all instance vars
...
llvm-svn: 25711
2006-01-27 22:37:09 +00:00
4d967a4cbb
Make llvm.frame/returnaddr not crash on ppc
...
llvm-svn: 25710
2006-01-27 22:25:06 +00:00
9857d075b5
Added notes about a x86 isel deficiency.
...
llvm-svn: 25706
2006-01-27 22:11:01 +00:00
1073ae07b0
Added a temporary option -enable-x86-sse to enable sse support. It is used by
...
llc-beta.
llvm-svn: 25701
2006-01-27 21:49:34 +00:00
a814f0b31c
Bye bye Pattern ISel, hello DAG ISel.
...
llvm-svn: 25700
2006-01-27 21:26:54 +00:00
8c47c3a3b1
Remove TLI.LowerReturnTo, and just let targets custom lower ISD::RET for
...
the same functionality. This addresses another piece of bug 680. Next,
on to fixing Alpha VAARG, which I broke last time.
llvm-svn: 25696
2006-01-27 21:09:22 +00:00
afab7aa8f2
A better workaround
...
llvm-svn: 25692
2006-01-27 19:30:30 +00:00
4be147f456
force sse/3dnow off until they work. This fixes all the x86 failures last night
...
llvm-svn: 25690
2006-01-27 18:30:50 +00:00
ed2bb8562f
Unbreak the JIT with SSE
...
llvm-svn: 25688
2006-01-27 18:27:18 +00:00
cde9e30bc6
x86 CPU detection and proper subtarget support
...
llvm-svn: 25679
2006-01-27 08:10:46 +00:00
d98701c639
Subtarget feature can now set any variable to any value
...
llvm-svn: 25678
2006-01-27 08:09:42 +00:00
1240574609
PHI and INLINEASM are now built-in instructions provided by Target.td
...
llvm-svn: 25674
2006-01-27 01:46:15 +00:00
1c341ac1fe
Add a default NoItinerary class for targets to use.
...
llvm-svn: 25670
2006-01-27 01:41:38 +00:00
15a8c15a1f
Improve compatibility with VC2005, patch by Morten Ofstad!
...
llvm-svn: 25661
2006-01-26 20:41:32 +00:00
32fef53f5c
Implement a method for inline asm support
...
llvm-svn: 25660
2006-01-26 20:37:03 +00:00
0bbdc55333
Set up MachineDebugInfo to scan for debug information form "llvm.db"g globals.
...
Global Variable information is now pulled from "llvm.dbg.globals"
llvm-svn: 25655
2006-01-26 20:21:46 +00:00
ebbfb386a5
Improve compatibility with VC2005, patch by Morten Ofstad!
...
llvm-svn: 25653
2006-01-26 19:55:20 +00:00
54c13da29c
Added preliminary x86 subtarget support.
...
llvm-svn: 25645
2006-01-26 09:53:06 +00:00
0ebb0b1c5c
fix stack corruption! Previously, 16-byte whole-FP-register stores were
...
being treated as needing only 8 bytes (though they were 16 byte aligned.)
This should fix a bunch of tests - anyone have any comments, though?
- in Target.td , SpillSize and SpillAlignment seem dead - is this what
Size and Alignment do now?
- in CodeGenRegisters.h/CodeGenTarget.cpp , DeclaredSpillSize and
DeclaredSpillAlignment seem dead.
- there are a bunch of comments here and there that don't clearly
distinguish between 'size' and 'spillsize' etc. hmm.
llvm-svn: 25644
2006-01-26 09:45:03 +00:00
c090ac13bd
some hoovering
...
llvm-svn: 25643
2006-01-26 09:08:31 +00:00
dbc2aac1e7
Rest of subtarget support, remove references to ppc
...
llvm-svn: 25642
2006-01-26 07:22:22 +00:00
e6842a9da6
Add trivial subtarget support
...
llvm-svn: 25641
2006-01-26 06:51:21 +00:00
0a01374299
minor renaming
...
llvm-svn: 25640
2006-01-26 03:24:15 +00:00
153f808f53
allow R28 to be used for frame calculations without entirely removing it from circulation
...
llvm-svn: 25639
2006-01-26 03:22:07 +00:00
fcdce6d26f
Work around some x86 Darwin assembler bugs
...
llvm-svn: 25638
2006-01-26 02:27:43 +00:00
944d1e91ea
When trying to fold X86::SETCC into a Select, make a copy if it has more than
...
one use. This allows more CMOV instructions.
llvm-svn: 25634
2006-01-26 02:13:10 +00:00
97c68f0f5c
Remove the uses of STATUS flag register. Rely on node property SDNPInFlag,
...
SDNPOutFlag, and SDNPOptInFlag instead.
llvm-svn: 25629
2006-01-26 00:29:36 +00:00
5c3dd5fafd
oops
...
llvm-svn: 25623
2006-01-25 23:33:32 +00:00
a852660e74
forgot one
...
llvm-svn: 25620
2006-01-25 22:28:07 +00:00
93fd315292
make things compile again
...
llvm-svn: 25614
2006-01-25 21:54:38 +00:00
d07c86465d
initialize an instance var, apparently I forgot to commit this long ago
...
llvm-svn: 25609
2006-01-25 18:57:15 +00:00
030e002fb9
Set SchedulingForLatency to be the default scheduling preference for all.
...
llvm-svn: 25607
2006-01-25 18:52:42 +00:00
e74795cd70
First part of bug 680:
...
Remove TLI.LowerVA* and replace it with SDNodes that are lowered the same
way as everything else.
llvm-svn: 25606
2006-01-25 18:21:52 +00:00
1092a02619
Default scheduling preference is SchedulingForLatency.
...
llvm-svn: 25603
2006-01-25 09:15:54 +00:00
83eeefbbd1
X86 prefer scheduling for reduced register pressure.
...
llvm-svn: 25602
2006-01-25 09:15:17 +00:00
aff0800fd1
Fix a selectcc lowering bug. Make a copy of X86ISD::CMP when folding it.
...
llvm-svn: 25596
2006-01-25 09:05:09 +00:00
bc7226a7cc
Loosen up these checks to allow direct uses of ESP
...
llvm-svn: 25595
2006-01-25 08:00:36 +00:00
5ea06a9f13
add bundling! well not really, for now it's just stop-insertion.
...
llvm-svn: 25593
2006-01-25 02:23:38 +00:00
94150f0666
maintaining stackpointer alignment. Perhaps it doesn't matter
...
llvm-svn: 25592
2006-01-25 01:51:08 +00:00
27d30a5f42
use ESP directly, not a copy of ESP into some other register for fastcc calls
...
llvm-svn: 25584
2006-01-24 06:14:44 +00:00
6f33eaeb81
Emit the copies out of call return registers *after* the ISD::CALLSEQ_END
...
node, fixing fastcc and the case where a function has a frame pointer due
to dynamic allocas.
llvm-svn: 25580
2006-01-24 05:17:12 +00:00
68e62a5184
Allow jit-beta to work
...
llvm-svn: 25578
2006-01-24 04:50:48 +00:00
3e65f28ffe
Crude Dwarf global variable debugging.
...
llvm-svn: 25569
2006-01-24 00:49:18 +00:00
c0bf377f98
bye bye Pattern ISEL
...
llvm-svn: 25553
2006-01-23 21:56:07 +00:00
fef7dec9cc
added stores to lsmark
...
llvm-svn: 25552
2006-01-23 21:51:33 +00:00
208bbe9ca9
fix up more lsmark stuff
...
llvm-svn: 25550
2006-01-23 21:23:26 +00:00
ba97ea52d4
yea, lowering this stuff will basically work
...
llvm-svn: 25549
2006-01-23 20:59:50 +00:00
8935e3eb7d
remove the V8 simple isel
...
llvm-svn: 25534
2006-01-23 07:20:15 +00:00
37c8ad14f4
die, die!! r15, you are not callee-saved
...
llvm-svn: 25527
2006-01-23 06:11:45 +00:00
cc87402925
fix register corruption! (my god.) r15 is a scratch reg, using that as
...
a frame pointer is a pretty doofus thing to do. use r5 instead, and
mark it callee-saved, coz that's what it is!
llvm-svn: 25526
2006-01-23 06:08:46 +00:00
de02d7727f
Add explicit #includes of <iostream>
...
llvm-svn: 25515
2006-01-22 23:41:00 +00:00
469640e506
Add explicit #includes of <iostream>
...
llvm-svn: 25509
2006-01-22 22:53:01 +00:00
4204e02fc6
insignificant, but next up is proper stack frame layout!
...
llvm-svn: 25497
2006-01-21 14:27:19 +00:00
468fecdc99
Rename fcmovae to fcmovnb and fcmova to fcmovnbe (following Intel manual).
...
Some assemblers can't recognize the aliases.
llvm-svn: 25494
2006-01-21 02:55:41 +00:00
9436aa74a9
trivial formatting improvement: don't insert extra blank lines between .comm
...
vars.
llvm-svn: 25492
2006-01-21 01:35:26 +00:00
4b41c8e929
Make the C writer work with packed types. printContainedStructs is
...
still not quite right and will be fixed later.
llvm-svn: 25488
2006-01-20 20:43:57 +00:00
f54c9395e7
remove RET hack, add proper support for rets (watching out for ret voids)
...
llvm-svn: 25486
2006-01-20 20:24:31 +00:00
eca87342b4
Simplify CWriter::printContainedStructs, also allowing it to work with
...
PackedTypes as a side-effect.
llvm-svn: 25485
2006-01-20 18:57:03 +00:00
335b46dd20
LowerReturn now doesn't have to handle f32 returns.
...
llvm-svn: 25484
2006-01-20 18:41:25 +00:00
4026e12e85
fix sext breakage: now we correctly deal with functions that return
...
int vs uint
llvm-svn: 25478
2006-01-20 16:10:05 +00:00
9a8fb20689
fix storing bools! eek!
...
llvm-svn: 25476
2006-01-20 03:40:25 +00:00
0c5de2864f
Stop doing that accidental commit.
...
llvm-svn: 25474
2006-01-20 01:14:05 +00:00
cce748d316
A few more SH{L|R}D peepholes.
...
llvm-svn: 25473
2006-01-20 01:13:30 +00:00
9c30bd5e25
Didn't mean to commit the last one.
...
llvm-svn: 25469
2006-01-19 23:27:08 +00:00
8591b9f254
Added i16 SH{L|R}D patterns.
...
llvm-svn: 25468
2006-01-19 23:26:24 +00:00
5df67bcd50
typo
...
llvm-svn: 25464
2006-01-19 21:10:38 +00:00
688ea707d8
nasty nasty patterns
...
llvm-svn: 25463
2006-01-19 20:49:37 +00:00
550d8ec1ad
fix boolean XOR (which fixes up comparisons..)
...
llvm-svn: 25462
2006-01-19 15:18:56 +00:00
4d69a01254
BOOM!
...
llvm-svn: 25460
2006-01-19 14:14:11 +00:00
bcbcfac6ea
click click
...
llvm-svn: 25459
2006-01-19 14:13:11 +00:00
3d2cc7e2e9
Avoid generating a redundant setcc.
...
llvm-svn: 25457
2006-01-19 08:52:46 +00:00
29b9d7cdff
fix calls that return f32
...
llvm-svn: 25455
2006-01-19 08:31:51 +00:00
2efef3d6f1
implement support for f32 arguments past the first 6 words
...
llvm-svn: 25450
2006-01-19 07:22:29 +00:00
91007126c2
adc and sbb need an incoming flag to ensure it reads the carry flag
...
from add / sub.
llvm-svn: 25444
2006-01-19 06:53:20 +00:00
c3c27032d0
add a note
...
llvm-svn: 25439
2006-01-19 02:09:38 +00:00
a7bfbe996e
Two peepholes:
...
(or (x >> c) | (y << (32 - c))) ==> (shrd x, y, c)
(or (x << c) | (y >> (32 - c))) ==> (shld x, y, c)
llvm-svn: 25438
2006-01-19 01:56:29 +00:00
6135a7a546
Didn't mean to check that in.
...
llvm-svn: 25436
2006-01-19 01:52:56 +00:00
267ba5965e
A obvious typo
...
llvm-svn: 25435
2006-01-19 01:46:14 +00:00
ce5066c863
Don't assert on 'select_cc SETUO'
...
llvm-svn: 25423
2006-01-18 19:42:35 +00:00
36eba3a49b
fix out of date comment
...
llvm-svn: 25422
2006-01-18 19:37:44 +00:00
15e7642ab1
Fix Regression/CodeGen/PowerPC/2006-01-18-InvalidBranchOpcodeAssert.ll
...
llvm-svn: 25421
2006-01-18 19:35:21 +00:00
194a5268cb
Added minimum Dwarf aranges. Cleaned up some section headers. Line number
...
support now works in gdb.
llvm-svn: 25417
2006-01-18 16:54:26 +00:00
621674a19d
SRA shift amount must be in i8
...
llvm-svn: 25416
2006-01-18 09:26:46 +00:00
4b3774e0a2
If a call return type is i1, insert a truncate from X86::AL to i1.
...
llvm-svn: 25415
2006-01-18 08:08:38 +00:00
feaed4d107
Fix lowering of calls which return f32 values.
...
llvm-svn: 25413
2006-01-17 21:58:21 +00:00
cc9dfecf81
Add frame work for additional dwarf sections. Comments will improve as code
...
is added.
llvm-svn: 25410
2006-01-17 20:41:40 +00:00
b9966029fe
Adding basic support for Dwarf line number debug information.
...
I promise to keep future commits smaller.
llvm-svn: 25396
2006-01-17 17:31:53 +00:00
14417ed99c
Zero extending load from i1 to i8.
...
llvm-svn: 25391
2006-01-17 07:02:46 +00:00
e08a95d3c1
oops, this shouldn't have gotten in
...
llvm-svn: 25388
2006-01-17 03:09:48 +00:00
0d5b69f734
SSE does not support i64 SINT_TO_FP (FP stack doesn't either, but we custom
...
expand it), so ask legalizer to expand i32 UINT_TO_FP.
llvm-svn: 25386
2006-01-17 02:32:49 +00:00
266ff6056a
use proper (82-bit) spills/fills when spilling FP regs, so that
...
divides don't get broken. this fixes obsequi, smg2000, and probably
a bunch of other stuff (tm)
llvm-svn: 25385
2006-01-17 02:04:52 +00:00
c261469ad9
fixing divides
...
llvm-svn: 25383
2006-01-17 01:19:49 +00:00
561881f30a
Added a FIXME comment about why FST is currently flagged to fpGETRESULT.
...
llvm-svn: 25381
2006-01-17 00:37:42 +00:00
bec9d720b0
Bug fixes: fpGETRESULT should produces a flag result and X86ISD::FST should
...
read a flag.
llvm-svn: 25378
2006-01-17 00:19:47 +00:00
c14bb1026b
More typo's
...
llvm-svn: 25375
2006-01-16 23:26:53 +00:00
64eeed27d9
Some typo's
...
llvm-svn: 25374
2006-01-16 22:48:46 +00:00
cfd9c6e526
fix short immediate loads
...
llvm-svn: 25371
2006-01-16 21:41:39 +00:00
34380b7675
stack and rpcc
...
llvm-svn: 25369
2006-01-16 21:22:38 +00:00
911c68d7a8
Fix FP_TO_INT**_IN_MEM lowering.
...
llvm-svn: 25368
2006-01-16 21:21:29 +00:00
81b108c54d
Friendly names
...
llvm-svn: 25364
2006-01-16 19:53:25 +00:00
7c76290038
add notes from my *other* email acct.
...
llvm-svn: 25362
2006-01-16 17:58:54 +00:00
b2eacf48aa
transfer some notes from my email to somewhere useful.
...
llvm-svn: 25361
2006-01-16 17:53:00 +00:00
e995910e64
fixing divides: FP should now be 100%, and integers are fine too
...
unless you try to div/mod 0 by anything, in which case you will
get some cute number, and not 0, which is bad.
llvm-svn: 25358
2006-01-16 14:33:04 +00:00
ba187774fe
fix division! again!! pattern isel, prepare to die.
...
llvm-svn: 25353
2006-01-16 06:33:38 +00:00
e636ba84b5
Silly Sparc is big endian. If we have to load args out of incoming stack slots
...
that are smaller than an int, make sure to adjust the frame pointer to take
this into consideration.
llvm-svn: 25351
2006-01-16 01:40:00 +00:00
9d41ecc95b
Make sure that bool,byte and short arguments are the right type when loaded
...
from memory.
llvm-svn: 25346
2006-01-15 22:22:01 +00:00
53312c6342
Disable a broken optimization
...
llvm-svn: 25340
2006-01-15 19:15:46 +00:00
2494ce49f0
Added patterns for 8-bit multiply
...
llvm-svn: 25338
2006-01-15 10:05:20 +00:00
c8817d2857
explain that r12 is the stack pointer reg
...
llvm-svn: 25336
2006-01-15 09:45:23 +00:00
e96523474b
Don't print a label for the first MBB in a function.
...
Compile this:
%_2E_str_8 = external global [75 x sbyte]
implementation ; Functions:
declare int %printf(sbyte*, ...)
void %test()
%tmp.101 = call int (sbyte*, ...)* %printf( sbyte* getelementptr ([75 x sbyte]* %_2E_str_8, int 0, int 0) ) ; <int> [#uses=0]
unreachable
}
to this:
main_endif_2E_8:
save -96, %o6, %o6
sethi %hi(_2E_str_8), %l0
add %l0, %lo(_2E_str_8), %o0
call printf
nop
instead of this:
main_endif_2E_8:
save -96, %o6, %o6
sethi %hi(_2E_str_8), %l0
or %g0, %lo(_2E_str_8), %l1 ;; extra instruction
add %l1, %l0, %o0
call printf
nop
llvm-svn: 25335
2006-01-15 09:26:27 +00:00
5bd514d7b0
Use the default impl of DYNAMIC_STACKALLOC, allowing us to delete some code.
...
llvm-svn: 25334
2006-01-15 09:02:48 +00:00
78c358d1ad
Use the default lowering of ISD::DYNAMIC_STACKALLOC, delete now dead code.
...
llvm-svn: 25333
2006-01-15 09:00:21 +00:00
aea3cccd55
Have legalize take care of DYNAMIC_STACKALLOC for us, implement llvm.stacksave/stackrestore.
...
llvm-svn: 25332
2006-01-15 08:55:25 +00:00
c5101b4ffa
Implement DYNAMIC_STACKALLOC for V8
...
llvm-svn: 25330
2006-01-15 08:43:57 +00:00
e5ca28b74d
reorder passes
...
llvm-svn: 25326
2006-01-15 07:19:53 +00:00
c17b41c3ba
Cleanup IA64ISD, tell the graph drawer what the symbolic names for the enums are.
...
llvm-svn: 25324
2006-01-14 22:27:21 +00:00
8869c6f782
silence a warning
...
llvm-svn: 25322
2006-01-14 20:11:13 +00:00
2fba8a3aaa
bswap implementation
...
llvm-svn: 25312
2006-01-14 03:14:10 +00:00
f2b38dbdc7
Remove some redundant stuff out of the readme.
...
llvm-svn: 25308
2006-01-14 01:24:22 +00:00
3bc25e8a54
A typo.
...
llvm-svn: 25307
2006-01-14 01:18:49 +00:00
a4de9baf40
Implement a new InvalidateStructLayoutInfo method and add some comments
...
llvm-svn: 25304
2006-01-14 00:07:34 +00:00
392c7d2779
Add truncstore i1 patterns.
...
llvm-svn: 25296
2006-01-13 21:45:19 +00:00
5f9c134bac
Fix a bug in my last X86 checkin, pointed out by cozmic
...
llvm-svn: 25293
2006-01-13 20:19:44 +00:00
dba84bbc1e
LHS = X86ISD::CMOVcc LHS, RHS means LHS = RHS if cc. So the operands must be
...
flipped around.
llvm-svn: 25290
2006-01-13 19:51:46 +00:00
045371a744
make DAG isel the default
...
llvm-svn: 25282
2006-01-13 18:49:47 +00:00
1a8d918ef1
Enable X86 support for savestack/restorestack
...
llvm-svn: 25278
2006-01-13 18:00:54 +00:00
776c326c96
implement stacksave/stackrestore on PPC
...
llvm-svn: 25277
2006-01-13 17:52:03 +00:00
0b94324c5e
don't be a doofus - this fixes storing bools
...
llvm-svn: 25274
2006-01-13 10:28:25 +00:00
8e2f52e645
expand unsupported stacksave/stackrestore nodes
...
llvm-svn: 25272
2006-01-13 02:42:53 +00:00
fdc6d1ea69
new nodes
...
llvm-svn: 25271
2006-01-13 02:40:58 +00:00
f00374e4a8
Minor update.
...
llvm-svn: 25263
2006-01-13 01:20:42 +00:00
d7faa4bae1
More typo's. I need new eye glasses...
...
llvm-svn: 25261
2006-01-13 01:17:24 +00:00
731423f36a
Oops. Typo.
...
llvm-svn: 25260
2006-01-13 01:06:49 +00:00
fb22e86c4d
Fix a SETCC / BRCOND folding bug.
...
llvm-svn: 25259
2006-01-13 01:03:02 +00:00
6305e50ee1
Fix sint_to_fp (fild*) support.
...
llvm-svn: 25257
2006-01-12 22:54:21 +00:00
c993d4522d
Specify transformation from GlobalAddress to TargetGlobalAddress and
...
ExternalSymbol to TargetExternalSymbol.
llvm-svn: 25253
2006-01-12 19:36:31 +00:00
556f14a6cb
Fix branches on FP compares
...
llvm-svn: 25249
2006-01-12 17:05:32 +00:00
84dc9b55f0
X86ISD::SETCC (e.g. SETEr) produces a flag (so multiple SETCC can be
...
linked together).
llvm-svn: 25247
2006-01-12 08:27:59 +00:00
b94db9e9a4
* Materialize GlobalAddress and ExternalSym with MOV32ri rather than
...
LEA32r.
* Do not lower GlobalAddress to TargetGlobalAddress. Let isel does it.
llvm-svn: 25246
2006-01-12 07:56:47 +00:00
fd41d94486
fix a bug in my previous checkin
...
llvm-svn: 25244
2006-01-12 07:38:04 +00:00
071c9637c3
Give V8ISD nodes symbolic names in dumps
...
llvm-svn: 25243
2006-01-12 07:31:15 +00:00
84be729a56
sabre's (correct) fix means these guys need to be flagged as well (else
...
the scheduler will complain)
llvm-svn: 25241
2006-01-12 03:28:40 +00:00
268d3584fc
ahem :)
...
llvm-svn: 25239
2006-01-12 02:05:36 +00:00
1014b38404
these cases are autogenerated
...
llvm-svn: 25238
2006-01-12 02:01:45 +00:00
44416f92f1
remove dead code
...
llvm-svn: 25237
2006-01-12 01:54:15 +00:00
33792a483a
Goodbye PPC pattern isel. You have served us well, but it is now time for
...
you to ride off into the sunset.
llvm-svn: 25236
2006-01-12 01:46:07 +00:00
9d5e4e8f3c
Fix an itanium call lowering bug for duraid
...
llvm-svn: 25235
2006-01-12 01:33:08 +00:00
504b63c873
invert the sense of this switch and its name
...
llvm-svn: 25234
2006-01-12 01:28:56 +00:00
6b9e00dedc
Missed a spot.
...
llvm-svn: 25233
2006-01-11 23:20:28 +00:00
6d2ab04463
Added ROTL and ROTR.
...
llvm-svn: 25232
2006-01-11 23:20:05 +00:00
2812e79c23
Fix an off-by-one error that Nate's eagle eyes caught
...
llvm-svn: 25231
2006-01-11 23:16:29 +00:00
dc43a3f237
Use the auto-insert BuildMI constructor to avoid an explicit insert. No
...
functionality change, just code cleanup.
llvm-svn: 25230
2006-01-11 23:07:57 +00:00
3280da3cda
If a function has a non-zero sized frame, use an add to adjust the stack
...
pointer in the epilog, not a load.
llvm-svn: 25229
2006-01-11 23:03:54 +00:00
ae986f1f1e
Support for MEMCPY and MEMSET.
...
llvm-svn: 25226
2006-01-11 22:15:48 +00:00
2ae799aff0
Select DYNAMIC_STACKALLOC
...
llvm-svn: 25225
2006-01-11 22:15:18 +00:00
1b8121b227
Add bswap, rotl, and rotr nodes
...
Add dag combiner code to recognize rotl, rotr
Add ppc code to match rotl
Targets should add rotl/rotr patterns if they have them
llvm-svn: 25222
2006-01-11 21:21:00 +00:00
602dfea79c
Fix calls that need to store values in stack slots, to not copy the stack
...
pointer. This allows us to emit stuff like this:
li r10, 0
stw r10, 56(r1)
or r3, r10, r10
or r4, r10, r10
or r5, r10, r10
or r6, r10, r10
or r7, r10, r10
or r8, r10, r10
or r9, r10, r10
bl L_bar$stub
instead of this:
or r2, r1, r1 ;; Extraneous copy.
li r10, 0
stw r10, 56(r2)
or r3, r10, r10
or r4, r10, r10
or r5, r10, r10
or r6, r10, r10
or r7, r10, r10
or r8, r10, r10
or r9, r10, r10
bl L_bar$stub
wowness.
llvm-svn: 25221
2006-01-11 19:55:07 +00:00
eaf94a8d2e
tblgen does this now
...
llvm-svn: 25220
2006-01-11 19:53:22 +00:00
b41e92b04c
This is no longer needed
...
llvm-svn: 25219
2006-01-11 19:52:46 +00:00
66f63f72f3
Dead FP arguments still use an incoming FP reg. This fixes
...
Regression/CodeGen/PowerPC/2006-01-11-darwin-fp-argument.ll, which was
distilled from a miscompilation in 252.eon.
llvm-svn: 25217
2006-01-11 18:21:25 +00:00
41c7f4a9ce
Use Evan's outflag stuff to implement V8cmpicc. This allows us to write a
...
pattern for SUBCCrr, and makes it trivial to add support for SUBCCri, eliminating
an instruction in the common "setcc X, imm" case.
llvm-svn: 25212
2006-01-11 07:49:38 +00:00
caf4d92f85
Fix a bug in i32->f64 conversion lowering
...
llvm-svn: 25211
2006-01-11 07:27:40 +00:00
d3839c74d6
Unbreak ret void :-/
...
llvm-svn: 25210
2006-01-11 07:15:43 +00:00
8e0bee11e3
Write this pattern in canonical form, allowing more patterns to match.
...
This implements Regression/CodeGen/SparcV8/xnor.ll
llvm-svn: 25209
2006-01-11 07:14:01 +00:00
bc7a0f44bd
* Add special entry code main() (to set x87 to 64-bit precision).
...
* Allow a register node as SelectAddr() base.
* ExternalSymbol -> TargetExternalSymbol as direct function callee.
* Use X86::ESP register rather than CopyFromReg(X86::ESP) as stack ptr for
call parmater passing.
llvm-svn: 25207
2006-01-11 06:09:51 +00:00
0302e62296
cleanup GETFD
...
llvm-svn: 25198
2006-01-11 03:50:40 +00:00
91eda00a7a
this pattern was bogus
...
llvm-svn: 25197
2006-01-11 03:33:06 +00:00
c712fd6b4e
this just might work
...
llvm-svn: 25195
2006-01-11 01:38:07 +00:00
0d5d08b26e
add support for selecting bools
...
FIXME: this is commented out because it makes tblgen go a bit fruity
llvm-svn: 25193
2006-01-11 01:21:12 +00:00
7c551268d0
implement FP_REG_KILL insertion for the dag-dag instruction selector
...
llvm-svn: 25192
2006-01-11 01:15:34 +00:00
29852a58b0
Fit into 80 cols
...
llvm-svn: 25191
2006-01-11 00:46:55 +00:00
339edad775
SSE cmov support.
...
llvm-svn: 25190
2006-01-11 00:33:36 +00:00
efaf5c56fd
* fp to sint patterns.
...
* fiadd, fisub, etc.
llvm-svn: 25189
2006-01-10 22:22:02 +00:00
73a1ad975e
FP_TO_INT*_IN_MEM and x87 FP Select support.
...
llvm-svn: 25188
2006-01-10 20:26:56 +00:00
0fb2ae7d17
silence a bogus warning
...
llvm-svn: 25185
2006-01-10 19:45:18 +00:00
599e73f21c
Int immediate loading fix
...
llvm-svn: 25182
2006-01-10 19:12:47 +00:00
014e8ee806
heh, 'sif it'd be a legalizer bug.
...
llvm-svn: 25172
2006-01-10 05:26:01 +00:00
e977a93bd5
support functions that return bool (this "should" work but doesn't,
...
*maybe* due to a legalizer bug.)
llvm-svn: 25171
2006-01-10 05:08:25 +00:00
477933cfbd
Remove a comment that no longer applies.
...
llvm-svn: 25167
2006-01-10 00:15:59 +00:00
347ed8a581
Give PPCISD:: nodes legible names in dumps.
...
llvm-svn: 25166
2006-01-09 23:52:17 +00:00
bfb2de9030
add ret void support back
...
llvm-svn: 25164
2006-01-09 23:20:37 +00:00
7c4486215f
* Added undef patterns.
...
* Some reorg.
llvm-svn: 25163
2006-01-09 23:10:28 +00:00
12181af0c7
More typos
...
llvm-svn: 25162
2006-01-09 22:29:54 +00:00
77fa9195cd
typo
...
llvm-svn: 25160
2006-01-09 20:49:21 +00:00
32e7d1ed4a
proper branch not equal sequence
...
llvm-svn: 25159
2006-01-09 19:49:58 +00:00
9c249c37f8
Support for ADD_PARTS, SUB_PARTS, SHL_PARTS, SHR_PARTS, and SRA_PARTS.
...
llvm-svn: 25158
2006-01-09 18:33:28 +00:00
7785e5b3a4
New DAG node properties SNDPInFlag, SNDPOutFlag, and SNDPOptInFlag to replace
...
hasInFlag, hasOutFlag.
llvm-svn: 25155
2006-01-09 18:28:21 +00:00
1185e73cc9
Fix the PPC JIT failures last night, which were due to mishandling of linkonce globals
...
llvm-svn: 25141
2006-01-07 06:22:16 +00:00
92e2797ce2
* Added integer div / rem.
...
* Fixed a load folding bug.
llvm-svn: 25136
2006-01-06 23:19:29 +00:00
10d2790d50
ISEL code for MULHU, MULHS, and UNDEF.
...
llvm-svn: 25132
2006-01-06 20:36:21 +00:00
346b4120af
make 0 codegen much better
...
llvm-svn: 25131
2006-01-06 19:41:51 +00:00
efbb8da3f5
silence a bogus gcc warning
...
llvm-svn: 25129
2006-01-06 17:56:38 +00:00
53dd0ac226
Addd (shl x, 1) ==> (shl x, x) peepholes.
...
llvm-svn: 25123
2006-01-06 02:31:59 +00:00
b03f9b32d2
fold (shl x, 1) -> (add x, x)
...
llvm-svn: 25120
2006-01-06 01:06:31 +00:00
b87030358d
linkonce symbols have an extra indirection, just like weak ones do. This fixes
...
Prolangs-C++/family and Prolangs-C++/primes.
llvm-svn: 25119
2006-01-06 01:04:03 +00:00
172fce7050
* Fast call support.
...
* FP cmp, setcc, etc.
llvm-svn: 25117
2006-01-06 00:43:03 +00:00
20c88dfd1b
Fix a compile crash building MultiSource/Applications/d with the new front-end.
...
The PPC backend was generating random shift counts in this case, due to an
uninitialized variable.
llvm-svn: 25114
2006-01-05 18:32:49 +00:00
da56ae98a9
unbreak the build, these are now in TargetSelectionDAG.td
...
llvm-svn: 25109
2006-01-05 04:48:15 +00:00
a5ae6e8320
Added ConstantFP patterns.
...
llvm-svn: 25108
2006-01-05 02:08:37 +00:00
e0d1b65d24
Added fpimm node for ConstantFP.
...
llvm-svn: 25107
2006-01-05 02:07:49 +00:00
deeafa0f00
Had expand logic backward.
...
llvm-svn: 25105
2006-01-05 01:47:43 +00:00
762e9ec06c
Added initial support for DEBUG_LABEL allowing debug specific labels to be
...
inserted in the code.
llvm-svn: 25104
2006-01-05 01:25:28 +00:00
45e19098a6
DAG based isel call support.
...
llvm-svn: 25103
2006-01-05 00:27:02 +00:00
779dd94721
Remove some dead code.
...
llvm-svn: 25102
2006-01-05 00:26:14 +00:00
219d559824
Applied some recommend changes from sabre. The dominate one beginning "let the
...
pass manager do it's thing." Fixes crash when compiling -g files and suppresses
dwarf statements if no debug info is present.
llvm-svn: 25100
2006-01-04 22:28:25 +00:00
0da76a676a
Add unique id to debug location for debug label use (work in progress.)
...
llvm-svn: 25096
2006-01-04 15:04:11 +00:00
b0609d91c3
Tie dwarf generation to darwin assembler.
...
llvm-svn: 25093
2006-01-04 13:52:30 +00:00
eaf5ed1438
typeo
...
llvm-svn: 25060
2006-01-02 21:15:53 +00:00
38e0b281da
Remove a 'using namespace std'.
...
llvm-svn: 25059
2006-01-01 22:20:31 +00:00
f99c338278
Add support for brcond
...
llvm-svn: 25058
2006-01-01 22:16:43 +00:00
6bec63aac9
Move brcond over and fix some imm patterns. This may be the last change before changing the default alpha isel.
...
llvm-svn: 25057
2006-01-01 22:16:14 +00:00
f0545f7c48
clean this function up some
...
llvm-svn: 25055
2006-01-01 22:13:54 +00:00
60ab61fcfc
improve constant loading. Still sucks, but oh well
...
llvm-svn: 25047
2005-12-30 02:30:02 +00:00
336dba6fb1
Add support for generating v4i32 altivec code
...
llvm-svn: 25046
2005-12-30 00:12:56 +00:00
c2c8a6202f
Remove a fixme
...
llvm-svn: 25045
2005-12-30 00:11:07 +00:00
50d9caf6a4
let us get some do what I meant not what I said stuff checked in. You would think the alpha backend would be 64bit clean
...
llvm-svn: 25040
2005-12-29 01:06:12 +00:00
34e4782c95
Fix up immediate handling
...
llvm-svn: 25039
2005-12-29 00:50:08 +00:00
3f5aaf55b8
yet more C++ standards-compliance stuff.
...
llvm-svn: 25028
2005-12-27 10:40:34 +00:00
69ac08c683
nasty paste-o, calls passing more than 8 arguments along were having
...
args >8 put into the wrong place
llvm-svn: 25027
2005-12-27 10:17:03 +00:00
5bd1c2783b
Restore some happiness to the JIT
...
llvm-svn: 25026
2005-12-27 06:25:50 +00:00
962dcbd572
Fix alpha regressions.
...
llvm-svn: 25025
2005-12-27 03:53:58 +00:00
8258489ca4
Fix a problem duraid pointed out to me compiling kc++ with -enable-x86-fastcc
...
llvm-svn: 25024
2005-12-27 03:02:18 +00:00
14c53b45f5
Added field noResults to Instruction.
...
Currently tblgen cannot tell which operands in the operand list are results so
it assumes the first one is a result. This is bad. Ideally we would fix this
by separating results from inputs, e.g. (res R32:$dst),
(ops R32:$src1, R32:$src2). But that's a more distruptive change. Adding
'let noResults = 1' is the workaround to tell tblgen that the instruction does
not produces a result. It works for now since tblgen does not support
instructions which produce multiple results.
llvm-svn: 25017
2005-12-26 09:11:45 +00:00
f520093eb3
add br pattern, unify JSR and BSR ISel instrs, and add BSR support for DAG
...
llvm-svn: 25011
2005-12-25 17:36:48 +00:00
6b240e55d1
unbreak calls, a few more tests should run. Tomorrow: bugpoint!
...
llvm-svn: 25010
2005-12-25 14:09:08 +00:00
06dcc199f0
we don't feed our call instructions extra operands
...
llvm-svn: 25009
2005-12-25 14:07:01 +00:00
0fce613eff
All that just to lower div and rem
...
llvm-svn: 25008
2005-12-25 01:34:27 +00:00
0dc12c38e5
support targetexternalsym
...
llvm-svn: 25005
2005-12-24 23:36:59 +00:00
782b654e6f
Let the helper functions know about X86::FR32RegClass and X86::FR64RegClass.
...
llvm-svn: 25004
2005-12-24 09:48:35 +00:00
5b18ed9e60
All addressing modes are now exposed. The only remaining relocated forms
...
are for function prologue.
TODO: move external symbols over to using RelLit.
: have a pattern that matches constpool|globaladdr
: have a pattern that matches (add x imm) -> x, imm or (...) -> ..., 0
llvm-svn: 25003
2005-12-24 08:29:32 +00:00
b9aaea3564
Unify the patterns for loads and stores. Now offset addressing should be
...
supported. This almost completes memory operations.
llvm-svn: 25002
2005-12-24 07:34:33 +00:00
4621488965
Let's see if we can break things.
...
Lower GOT relative addresses to Lo and HI.
Update both ISels to select them when they can.
Saves instructions here and there.
llvm-svn: 25001
2005-12-24 05:36:33 +00:00
636e1aed43
move loads and stores over. Smart addr selection comming
...
llvm-svn: 25000
2005-12-24 03:41:56 +00:00
9aea6e4691
Fix one of the things in the todo file, and get a bit closer to folding
...
constant offsets from statics into the address arithmetic.
llvm-svn: 24999
2005-12-24 01:00:15 +00:00
9ae486047e
* Removed the use of FLAG. Now use hasFlagIn and hasFlagOut instead.
...
* Added a pseudo instruction (for each target) that represent "return void".
This is a workaround for lack of optional flag operand (return void is not
lowered so it does not have a flag operand.)
llvm-svn: 24997
2005-12-23 22:14:32 +00:00
4f52796f79
not a good idea
...
llvm-svn: 24991
2005-12-23 07:37:47 +00:00
5c59d49630
More X86 floating point patterns.
...
llvm-svn: 24990
2005-12-23 07:31:11 +00:00
8be8067b19
Operand 1 of TRUNCSTORE can be any of integer and floating point types.
...
llvm-svn: 24989
2005-12-23 07:30:30 +00:00
55823ae03f
fix something-o
...
llvm-svn: 24987
2005-12-23 07:08:39 +00:00
5427aab5f8
implement vaarg. Varargs now should work.
...
llvm-svn: 24986
2005-12-23 06:37:38 +00:00
5ee896aad9
implement vastart. The dag isel compiles this:
...
void test3(va_list Y);
void test2(int F, ...) {
va_list X;
va_start(X, F);
test3(X);
}
into this:
test2:
save -104, %o6, %o6
st %i5, [%i6+88]
st %i4, [%i6+84]
st %i3, [%i6+80]
st %i2, [%i6+76]
st %i1, [%i6+72]
add %i6, 72, %o0
st %o0, [%i6+-4]
call test3
nop
restore %g0, %g0, %g0
retl
nop
The simple isel emits:
test2:
save -96, %o6, %o6
st %i0, [%i6+68]
st %i1, [%i6+72]
st %i2, [%i6+76]
st %i3, [%i6+80]
st %i4, [%i6+84]
st %i5, [%i6+88]
or %g0, 1, %l0
or %g0, 4, %l1
umul %l0, %l1, %l0
add %l0, 7, %l0
and %l0, -8, %l0
sub %o6, %l0, %o6
add %o6, 96, %l0
add %i6, 72, %l1
st %l1, [%l0]
ld [%l0], %o0
call test3
nop
restore %g0, %g0, %g0
retl
nop
llvm-svn: 24985
2005-12-23 06:24:04 +00:00
6e6d5a1fa1
remove benchmark list, remove issues addressed by the dag-dag isel
...
llvm-svn: 24984
2005-12-23 06:09:30 +00:00
30107e65c8
make sure bit_convert's are expanded
...
llvm-svn: 24979
2005-12-23 05:15:23 +00:00
c46fc2482c
make sure bit_converts are expanded
...
llvm-svn: 24978
2005-12-23 05:13:35 +00:00
5ce81edbf6
fix the int<->fp instructions, which apparently take a single float register
...
to represent the int part (because it's always 32-bits)
llvm-svn: 24976
2005-12-23 05:00:16 +00:00
c9849274bd
Use BIT_CONVERT to simplify this code
...
llvm-svn: 24975
2005-12-23 02:31:39 +00:00
f474034432
Simplify some code by using BIT_CONVERT
...
llvm-svn: 24974
2005-12-23 00:59:59 +00:00
4c141d047c
clean up .td file by using evan's new FLAG thing
...
llvm-svn: 24967
2005-12-22 21:18:39 +00:00
177d7af5d5
remove dead code
...
llvm-svn: 24965
2005-12-22 21:16:08 +00:00
6b0325aa26
fix handling of weak linkage
...
llvm-svn: 24964
2005-12-22 21:15:17 +00:00
ffe3542726
move some random notes out of my email into someplace useful
...
llvm-svn: 24956
2005-12-22 17:19:28 +00:00
644e7db818
this is a hack, which may or may not hang around. In short:
...
whimper out of doing things the Right Way, and hack up a generic
'BRCALL' instruction, that gets generated when calls are lowered.
This gets selected by hand in the DAG isel, where it gets turned
into real (i.e. in tablegen) br.call instructions.
BUG: this dies on void calls, but seems to work otherwise?
llvm-svn: 24952
2005-12-22 13:29:14 +00:00
3692fa14b8
we can't do this directly in lowering, so we need this case
...
llvm-svn: 24951
2005-12-22 07:14:45 +00:00
3608ab87c0
oops, back this out
...
llvm-svn: 24950
2005-12-22 07:13:51 +00:00
b1d57fb175
we can't all have brains now, can we
...
llvm-svn: 24948
2005-12-22 06:41:39 +00:00
d0c146d59f
this should take care of calls to varadic functions, but it doesn.,t
...
BUG: calling printf(string, float) will load the float into the wrong
register, completely forget about loading the string, etce
llvm-svn: 24947
2005-12-22 06:39:57 +00:00
a8de8a5db4
we need to emit the getf.d instruction in lowering, so add it
...
to IA64ISD
llvm-svn: 24946
2005-12-22 06:38:38 +00:00
5ccf76fed3
I shoulda done this a *long* time ago (tm): implement calls properly,
...
i.e. r1/r12/rp are saved/restored regardless of scheduling/luck
TODO: calls to external symbols, indirect (function descriptor) calls,
performance (we're being paranoid right now)
BUG: the code for handling calls to vararg functions breaks if FP
args are passed (this will make printf() go haywire so a bunch of
tests will fail)
BUG: this seems to trigger some legalize nastiness
llvm-svn: 24942
2005-12-22 04:07:40 +00:00
8f6c86fe3b
kill SelectCALL() in the DAG isel, we handle this in lowering now, like
...
SPARCv8. (we copy sparcv8's workaround for tablegen not being nice about
ISD::CALL/TAILCALL)
llvm-svn: 24941
2005-12-22 03:58:17 +00:00
a743e00e7a
update tablegen files - nothing to see here
...
llvm-svn: 24939
2005-12-22 03:56:03 +00:00
dfad8ed54e
Bye bye HACKTROCITY.
...
llvm-svn: 24935
2005-12-22 02:26:21 +00:00
62fef13143
Added special flag node FLAG.
...
llvm-svn: 24934
2005-12-22 02:25:14 +00:00
1872908f3b
Lefted out TargetLowering::
...
llvm-svn: 24922
2005-12-21 23:14:54 +00:00
9cdc16c6d3
* Fix a GlobalAddress lowering bug.
...
* Teach DAG combiner about X86ISD::SETCC by adding a TargetLowering hook.
llvm-svn: 24921
2005-12-21 23:05:39 +00:00
02767195bb
Oops. Accidentally deleted RET pattern. It's still needed for return void;
...
llvm-svn: 24920
2005-12-21 22:22:16 +00:00
9e296bee9a
Disengage DEBUG_LOC from non-PPC targets.
...
llvm-svn: 24919
2005-12-21 20:51:37 +00:00
c1583dbd63
* Added support for X86 RET with an additional operand to specify number of
...
bytes to pop off stack.
* Added support for X86 SETCC.
llvm-svn: 24917
2005-12-21 20:21:51 +00:00
81f2653e45
add some nodes, forgot to commit this last night :(
...
llvm-svn: 24901
2005-12-21 16:22:46 +00:00
0dcdd83c0e
This was meant to go in
...
llvm-svn: 24900
2005-12-21 07:50:26 +00:00
f431ad4477
Rewrite FP stackifier support in the X86InstrInfo.td file, splitting patterns
...
that were overloaded to work before and after the stackifier runs. With the
new clean world, it is possible to write patterns for these instructions: woo!
This also adds a few simple patterns here and there, though there are a lot
still missing. These should be easy to add though. :)
See the comments under "Floating Point Stack Support" for more details on
the new world order.
This patch as absolutely no effect on the generated code, woo!
llvm-svn: 24899
2005-12-21 07:47:04 +00:00
988827a482
Wrap some long lines: no functionality change
...
llvm-svn: 24898
2005-12-21 05:34:58 +00:00
72575d882b
remove dead code
...
llvm-svn: 24896
2005-12-21 05:27:51 +00:00
a2f308fc3e
Remove ISD::RET select code. Now tblgen'd.
...
llvm-svn: 24889
2005-12-21 02:41:57 +00:00
a74ce62746
* Added lowering hook for external weak global address. It inserts a load
...
for Darwin.
* Added lowering hook for ISD::RET. It inserts CopyToRegs for the return
value (or store / fld / copy to ST(0) for floating point value). This
eliminate the need to write C++ code to handle RET with variable number
of operands.
llvm-svn: 24888
2005-12-21 02:39:21 +00:00
5c0b4df483
SSE2 floating point load / store patterns. SSE2 fp to int conversion patterns.
...
llvm-svn: 24886
2005-12-20 22:59:51 +00:00
82285c55aa
Flip the meaning of FPContractions to reflect Requires<[]> change.
...
llvm-svn: 24884
2005-12-20 20:08:53 +00:00
fc94dff7dc
Run lower-switch after lower-invoke.
...
Only run lower-allocations and lower-select for the simple isel
llvm-svn: 24881
2005-12-20 08:00:11 +00:00
10c7f67d78
Reserve G1 for frame offset stuff and use it to handle large stack frames.
...
For example, instead of emitting this:
test:
save -40112, %o6, %o6 ;; imm too large
add %i6, -40016, %o0 ;; imm too large
call caller
nop
restore %g0, %g0, %g0
retl
nop
emit this:
test:
sethi 4194264, %g1
or %g1, 848, %g1
save %o6, %g1, %o6
sethi 4194264, %g1
add %g1, %i6, %g1
add %i1, 944, %o0
call caller
nop
restore %g0, %g0, %g0
retl
nop
which doesn't cause the assembler to barf.
llvm-svn: 24880
2005-12-20 07:56:31 +00:00
5815a6e455
Added X86 readport patterns.
...
llvm-svn: 24879
2005-12-20 07:38:38 +00:00
6af02635a7
Added a hook to print out names of target specific DAG nodes.
...
llvm-svn: 24877
2005-12-20 06:22:03 +00:00
b11b8e44fa
Pattern-match return. Includes gross hack!
...
llvm-svn: 24874
2005-12-20 00:26:01 +00:00
c126397a69
Fix a couple of the FIXMEs, thanks to suggestion from Chris. This allows
...
us to load and store vectors directly at a pointer (offset of zero) by
using r0 as the base register. This also requires some asm printer work
to satisfy the darwin assembler.
For
void %foo(<4 x float> * %a) {
entry:
%tmp1 = load <4 x float> * %a;
%tmp2 = add <4 x float> %tmp1, %tmp1
store <4 x float> %tmp2, <4 x float> *%a
ret void
}
We now produce:
_foo:
lvx v0, 0, r3
vaddfp v0, v0, v0
stvx v0, 0, r3
blr
Instead of:
_foo:
li r2, 0
lvx v0, r2, r3
vaddfp v0, v0, v0
stvx v0, r2, r3
blr
llvm-svn: 24872
2005-12-19 23:40:42 +00:00
8e6a8af205
Convert load/store over to being pattern matched
...
llvm-svn: 24871
2005-12-19 23:25:09 +00:00
6fc31046aa
X86 conditional branch support.
...
llvm-svn: 24870
2005-12-19 23:12:38 +00:00
1d9b671de0
It's essential we clear CodeGenMap after isel every basic block!
...
llvm-svn: 24867
2005-12-19 22:36:02 +00:00
7767a654b0
Fix pifft by correcting the case when a i64/f64 straddles O5 and memory:
...
we were storing into [FP+88] instead of [FP+92].
Improve codegen by emitting [FP+92], instead of emitting a copy of FP into
another GPR which wouldn't be coallesced because FP isn't register allocated.
llvm-svn: 24859
2005-12-19 07:57:53 +00:00
631c9df853
don't emit 'add %o6, 0, %o6' instructions
...
llvm-svn: 24857
2005-12-19 02:51:12 +00:00
5b9c9f9d36
Fix calls to functions returning i64
...
llvm-svn: 24856
2005-12-19 02:15:51 +00:00
655fac2c95
Correct bool truncstore operand order
...
llvm-svn: 24855
2005-12-19 02:06:50 +00:00
2c792ccc62
add the other bool zextload as well
...
llvm-svn: 24854
2005-12-19 01:44:58 +00:00
766170c6ee
implement zextload bool
...
llvm-svn: 24853
2005-12-19 01:43:04 +00:00
9be456300e
mark some unsupported ops as unsupported
...
llvm-svn: 24852
2005-12-19 01:39:40 +00:00
e59941810a
Fix syntax for indirect calls. This fixes Olden/mst
...
llvm-svn: 24850
2005-12-19 01:22:53 +00:00
bead785656
Keep stack frames 8-byte aligned. This fixes olden/voronoi
...
llvm-svn: 24849
2005-12-19 01:15:13 +00:00
9078c84654
apparently rdy isn't actually a psuedo instruction. Use rd %y
...
llvm-svn: 24848
2005-12-19 00:53:02 +00:00
d2e885e321
add fneg/fabs support for doubles
...
llvm-svn: 24847
2005-12-19 00:50:12 +00:00
14ee61ef00
Various cleanups to this pass, no functionality change
...
llvm-svn: 24846
2005-12-19 00:46:20 +00:00
d2a07eebcd
add bool truncstores
...
llvm-svn: 24845
2005-12-19 00:19:21 +00:00
15bd5ea92f
Elimiante SP and FP, which weren't members of the IntRegs register class
...
llvm-svn: 24844
2005-12-19 00:06:52 +00:00
f5f80cb947
The sun assembler only supports .xword in V9 mode.
...
llvm-svn: 24842
2005-12-18 23:36:45 +00:00
1ac15547d6
Configure the asmwriter to allow constant pools to be printed correctly
...
llvm-svn: 24841
2005-12-18 23:35:05 +00:00
030672f16b
add support for integer extloads
...
llvm-svn: 24840
2005-12-18 23:18:37 +00:00
c70ed7721b
Add support for undef
...
llvm-svn: 24839
2005-12-18 23:10:57 +00:00
4c3c3ac218
Add support for calls to external symbols
...
llvm-svn: 24838
2005-12-18 23:07:11 +00:00
388f3043b0
we have no memcpy
...
llvm-svn: 24837
2005-12-18 23:00:27 +00:00
c65cd5a03e
Fix a crash on a call with no arguments
...
llvm-svn: 24836
2005-12-18 22:57:47 +00:00
2f5fb6a720
This is handled by the autogen'd code
...
llvm-svn: 24834
2005-12-18 21:06:11 +00:00
1958690ff2
Change return lowering so that we can autogen the matching code.
...
llvm-svn: 24832
2005-12-18 21:03:04 +00:00
02e9904ee5
Implement Calls for V8. This would be completely autogenerated except for
...
a small bug in tblgen. When that is fixed, we can remove the ISD::Call case
in Select.
llvm-svn: 24830
2005-12-18 15:55:15 +00:00
a0be18c9a4
Implement the full V8 ABI for incoming arguments.
...
llvm-svn: 24825
2005-12-18 13:33:06 +00:00
8d1db078cb
Push ops list, asm string, and pattern all the way up to InstV8. Move the
...
InstV8 class to the InstrFormats file where it belongs.
llvm-svn: 24824
2005-12-18 08:21:00 +00:00
7cee2c9a5b
Give V8 select_cc, in the spirit of the PPC backend
...
llvm-svn: 24823
2005-12-18 08:13:54 +00:00
9de2958138
remove some unused instructions
...
llvm-svn: 24822
2005-12-18 07:15:17 +00:00
a9f0d108b1
V8 doesn't have FP extload
...
llvm-svn: 24821
2005-12-18 07:13:32 +00:00
d6806875d0
simplifications, fix typo
...
llvm-svn: 24820
2005-12-18 07:09:06 +00:00
c5609aab11
add a node, for completeness
...
llvm-svn: 24819
2005-12-18 07:05:21 +00:00
4492b1b7a0
Add frameindex support
...
Add support for copying (e.g. returning) doubles
Add support for F<->I instructions
llvm-svn: 24818
2005-12-18 06:59:57 +00:00
9dcfe37e76
Tighten up some checks
...
llvm-svn: 24817
2005-12-18 06:40:34 +00:00
53c1f75090
Since extload can also be used by FP, split STDIntExtLoad into two parts,
...
one for use with extload, one for use with sextload and zextload, which
are integer only.
llvm-svn: 24814
2005-12-18 02:48:48 +00:00
5580e69df6
Add constant pool support, including folding into addresses.
...
Pretty print addresses a bit, to not print [%r1+%g0]: just print [%r1]
llvm-svn: 24813
2005-12-18 02:37:35 +00:00
726075fdf8
Teach the addressing mode stuff to fold "%lo" into 'ri' addressing modes,
...
allowing us to compile this:
to this:
%G1 = external global int
%G2 = external global int
void %test() {
%X = load int* %G1
store int %X, int* %G2
ret void
}
test:
save -96, %sp, %sp
sethi %hi(G1), %l0
ld [%l0+%lo(G1)], %l0
sethi %hi(G2), %l1
st %l0, [%l1+%lo(G2)]
restore %g0, %g0, %g0
retl
nop
instead of this:
test:
save -96, %sp, %sp
sethi %hi(G1), %l0
or %g0, %lo(G1), %l1
ld [%l1+%l0], %l0
sethi %hi(G2), %l1
or %g0, %lo(G2), %l2
st %l0, [%l2+%l1]
restore %g0, %g0, %g0
retl
nop
llvm-svn: 24812
2005-12-18 02:27:00 +00:00
a983c3df1c
Add initial support for global variables, and fix a bug in addr mode selection
...
where we didn't select the operands.
llvm-svn: 24811
2005-12-18 02:10:39 +00:00
a49b652a62
Claiming that branch targets are registers is not very wholesome. Change them
...
to be basic blocks. Also, add uncond branches.
llvm-svn: 24810
2005-12-18 01:46:58 +00:00
b29957500e
Add unordered comparisons
...
llvm-svn: 24809
2005-12-18 01:41:39 +00:00
e58481be36
Add patterns to the rest of the int condbranches and some of the fp branches
...
llvm-svn: 24808
2005-12-18 01:38:19 +00:00
9cf4bb2867
Add initial conditional branch support. This doesn't actually work yet due
...
to a bug in the scheduler.
llvm-svn: 24807
2005-12-18 01:20:35 +00:00
00759eac78
Eliminate CMPri, which is a synonym for SUBCCri
...
llvm-svn: 24805
2005-12-17 23:52:08 +00:00
5a6b03c1b8
add fneg,fabs,fsqrt instructions
...
llvm-svn: 24803
2005-12-17 23:20:27 +00:00
32f19262d5
Add patterns for fround/fextend and the funny fsmuld instruction
...
llvm-svn: 24802
2005-12-17 23:14:30 +00:00
06952dfced
Add FP +,-,*,/
...
llvm-svn: 24801
2005-12-17 23:10:46 +00:00
89078880f2
Give patterns to F3_3 instructions
...
llvm-svn: 24800
2005-12-17 23:05:35 +00:00
829572cdca
Implement 64-bit add/sub, make sure to receive and return 64-bit args with
...
the right halves in the right regs
llvm-svn: 24799
2005-12-17 22:55:57 +00:00
ebfa06a2de
implement div and rem
...
llvm-svn: 24798
2005-12-17 22:39:19 +00:00
8eaf9f4cb3
implement MULHU/MULHS for 64-bit multiplies
...
llvm-svn: 24797
2005-12-17 22:30:00 +00:00
4abe9528f9
Add patterns for multiply, simplify Y register handling stuff, add RDY instruction
...
llvm-svn: 24796
2005-12-17 22:22:53 +00:00
2616a0b56f
Make the addressing modes smarter
...
llvm-svn: 24795
2005-12-17 21:25:27 +00:00
19ff62dc67
remove some unused instructions
...
llvm-svn: 24794
2005-12-17 21:13:50 +00:00
e39ab718c0
add andn/orn/xorn patterns. This allows us to compile this:
...
long %test(ubyte, short, long %X, long %Y) {
%A = xor long %X, -1
%B = and long %Y, %A
ret long %B
}
to this:
test:
save -96, %sp, %sp
andn %i4, %i2, %i0
andn %i5, %i3, %i1
restore %g0, %g0, %g0
retl
nop
instead of this:
test:
save -96, %sp, %sp
xor %i2, -1, %l0
xor %i3, -1, %l1
and %i4, %l0, %i0
and %i5, %l1, %i1
restore %g0, %g0, %g0
retl
nop
The simpleisel emits: :(
test:
save -96, %sp, %sp
or %g0, -1, %l0
or %g0, -1, %l0
or %g0, -1, %l0
or %g0, -1, %l1
xor %i2, %l0, %l0
xor %i3, %l1, %l1
and %i4, %l0, %i0
and %i5, %l1, %i1
restore %g0, %g0, %g0
retl
nop
llvm-svn: 24793
2005-12-17 21:05:49 +00:00
ea752cc50a
Add support for 64-bit arguments
...
llvm-svn: 24792
2005-12-17 20:59:06 +00:00
6be83f9959
Sparc doesn't have sext_inreg
...
llvm-svn: 24791
2005-12-17 20:50:42 +00:00
d10995cb26
add patterns for FP stores
...
llvm-svn: 24790
2005-12-17 20:47:16 +00:00
490a6edf52
Add [reg+reg] integer stores
...
llvm-svn: 24789
2005-12-17 20:44:36 +00:00
b57bb13253
Add store patterns
...
llvm-svn: 24788
2005-12-17 20:42:55 +00:00
233e044738
add truncstore
...
llvm-svn: 24787
2005-12-17 20:42:29 +00:00
7e7c355154
add fp load patterns, switch rest of loads and stores to use addrmodes
...
llvm-svn: 24786
2005-12-17 20:32:47 +00:00
c4f3a7adea
Add integer load[r+r] forms.
...
llvm-svn: 24785
2005-12-17 20:26:45 +00:00
1c02c45f18
Rename load/store instructions to include an RI suffix
...
llvm-svn: 24784
2005-12-17 20:18:49 +00:00
4fa86e1d55
Add patterns for the rest of the loads. Add 'ri' suffixes to the load and store insts
...
llvm-svn: 24783
2005-12-17 20:18:24 +00:00
5d15f9ed60
Add basic addressing mode support and one load.
...
llvm-svn: 24782
2005-12-17 20:04:49 +00:00
db8e888fb5
eliminate some redundancy
...
llvm-svn: 24781
2005-12-17 19:47:05 +00:00
5e68639009
Use a combination of sethi and or to build arbitrary immediates.
...
llvm-svn: 24780
2005-12-17 19:41:43 +00:00
8546257435
Use sethi to build large immediates with zeros at the bottom
...
llvm-svn: 24779
2005-12-17 19:37:00 +00:00
7b6f2e879d
Add shift and small immediate support
...
llvm-svn: 24778
2005-12-17 19:07:57 +00:00
30f924e3ca
Add some basic reg-reg instructions
...
llvm-svn: 24777
2005-12-17 18:53:33 +00:00
2edb4b7f99
Add empty patterns to all F3_1 instructions
...
llvm-svn: 24776
2005-12-17 18:49:14 +00:00
1d71248392
Darwin API issue: indirect load of external and weak symbols.
...
llvm-svn: 24775
2005-12-17 09:13:43 +00:00
866cef563b
Add some simple integer patterns. This allows us to compile this:
...
int %test(int %A) {
%B = add int %A, 1
%C = xor int %B, 123
ret int %C
}
into this:
test:
save -96, %sp, %sp
add %i0, 1, %l0
xor %l0, 123, %i0
restore %g0, %g0, %g0
retl
nop
for example. I guess it would make sense to add reg/reg versions too.
llvm-svn: 24774
2005-12-17 08:26:38 +00:00
80a3875bc1
Implement ret with operand, giving us this:
...
int %test(int %A) {
ret int %A
}
llvm-svn: 24773
2005-12-17 08:15:09 +00:00
1136b7a2e0
Add a pattern for 'ret'. This now compiles:
...
void %test() { ret void }
:)
llvm-svn: 24772
2005-12-17 08:08:42 +00:00
1549e4d590
Add empty patterns for F3_2 instructions
...
llvm-svn: 24771
2005-12-17 08:06:43 +00:00
9f1c860e1e
Implement LowerArguments, at least for the first 6 integer args
...
llvm-svn: 24770
2005-12-17 08:03:24 +00:00
4f34e9f7ff
Add the framework for a dag-dag isel
...
llvm-svn: 24769
2005-12-17 07:47:01 +00:00
f3b16bc5a0
Remove a few lines of dead code.
...
llvm-svn: 24768
2005-12-17 07:18:44 +00:00
69b5d17f92
asmprinter done, added crucial missing step
...
llvm-svn: 24767
2005-12-17 07:17:59 +00:00
55f9dbe1ea
Use the AsmPrinter for global variable init printing. This eliminates a
...
bunch of code and causes V8 to start using the fancy .asciz directive that
the sun assembler supports.
llvm-svn: 24766
2005-12-17 07:17:08 +00:00
fb7fd98cd4
Switch constant pool printing over to use the Shared AsmPrinter version
...
llvm-svn: 24765
2005-12-17 07:11:43 +00:00
b808c8e2e4
Use the shared AsmPrinter code for some basic stuff. No functionality
...
change except for fewer .section directives emitted
llvm-svn: 24764
2005-12-17 07:04:29 +00:00
7087cd275b
Added an idea about any_extend for performance tuning.
...
llvm-svn: 24763
2005-12-17 06:54:43 +00:00
9e2af046e4
Convert the remaining instructions over, branches and calls. Fix a couple
...
minor bugs
llvm-svn: 24762
2005-12-17 06:54:41 +00:00
6b669e2680
convert FP instructions to use an asmstring and operand list, allowing FP
...
programs to work on V8 again
llvm-svn: 24761
2005-12-17 06:32:52 +00:00
bc7708c0e8
Added truncate.
...
llvm-svn: 24760
2005-12-17 02:02:50 +00:00
b06925d1dd
Added anyext, modelled as zext on X86.
...
llvm-svn: 24759
2005-12-17 01:47:57 +00:00
6b76009393
Added some isel ideas.
...
llvm-svn: 24757
2005-12-17 01:25:19 +00:00
cb19390ead
Added support for cmp, test, and conditional move instructions.
...
llvm-svn: 24756
2005-12-17 01:24:02 +00:00
0f68322992
Only lower SELECT when using DAG based isel.
...
llvm-svn: 24755
2005-12-17 01:22:13 +00:00
225a4d0d6d
X86 lowers SELECT to a cmp / test followed by a conditional move.
...
llvm-svn: 24754
2005-12-17 01:21:05 +00:00
7c462768ed
Added source file/line correspondence for dwarf (PowerPC only at this point.)
...
llvm-svn: 24748
2005-12-16 22:45:29 +00:00
887af88ce3
Weak and linkonce global vars should still have a .globl emitted for them
...
llvm-svn: 24747
2005-12-16 21:46:14 +00:00
672578bd94
Add a second vector type to the VRRC register class, and fix some patterns
...
so that tablegen can infer all types.
llvm-svn: 24746
2005-12-16 09:19:13 +00:00
9f2c3a7c4e
add some notes
...
llvm-svn: 24745
2005-12-16 07:20:53 +00:00
fa55745cbc
Add a couple more instrs
...
llvm-svn: 24744
2005-12-16 07:18:48 +00:00
e082426ae7
remove some dead code
...
llvm-svn: 24743
2005-12-16 07:16:02 +00:00
70310906e7
asmprint pseudo instrs
...
llvm-svn: 24742
2005-12-16 07:13:26 +00:00
68d064a3a6
Autogenerate asmprinter for F3_2 instructions
...
llvm-svn: 24741
2005-12-16 07:10:02 +00:00
1e777082a0
Switch F3_1 instructions over to use AsmStrings
...
llvm-svn: 24740
2005-12-16 06:52:00 +00:00
4870224a56
Plug in basic hooks for an autogenerated asm printer to fill in.
...
llvm-svn: 24739
2005-12-16 06:34:17 +00:00
34e80f0114
Add operand info for F3_[12] instructions, getting V8 back to basic functionality.
...
With this, Regression/CodeGen/SparcV8/basictest.ll now passes. Lets hear it
for regression tests :)
llvm-svn: 24738
2005-12-16 06:25:42 +00:00
b527f48acd
Remove JIT support, which doesn't work.
...
llvm-svn: 24736
2005-12-16 06:06:07 +00:00
1e1ca1e9a5
add some simple operand info
...
llvm-svn: 24735
2005-12-16 06:02:58 +00:00
575751151c
Update the darwin handling of linkonce & weak functions and GV stubs. This
...
should work in all permutations.
llvm-svn: 24728
2005-12-16 00:22:14 +00:00
9f62a2a51d
Don't globalize internal functions
...
llvm-svn: 24727
2005-12-16 00:07:30 +00:00
74151ba279
* Promote all 1 bit entities to 8 bit.
...
* Handling extload (1 bit -> 8 bit) and remove C++ code that handle 1 bit
zextload.
llvm-svn: 24726
2005-12-15 19:49:23 +00:00
305c6a73b5
Added frameindex, constpool, globaladdr, and externalsym as root nodes of
...
leaaddr.
llvm-svn: 24724
2005-12-15 08:31:04 +00:00
a2ebc62862
Added constpool, frameindex, and externalsym nodes.
...
llvm-svn: 24723
2005-12-15 08:29:48 +00:00
00fcb0017e
Handling zero extension of 1 bit value.
...
llvm-svn: 24722
2005-12-15 01:02:48 +00:00
bc9344477e
Use MOV8rm to load 1 bit value.
...
llvm-svn: 24721
2005-12-15 00:59:17 +00:00
808f7a8abb
Remove a now unused statistic.
...
llvm-svn: 24720
2005-12-14 22:56:16 +00:00
e37cb604c1
Use the new predicate support that Evan Cheng added to remove some code
...
from the DAGToDAG cpp file. This adds pattern support for vector and
scalar fma, which passes test/Regression/CodeGen/PowerPC/fma.ll, and
does the right thing in the presence of -disable-excess-fp-precision.
Allows us to match:
void %foo(<4 x float> * %a) {
entry:
%tmp1 = load <4 x float> * %a;
%tmp2 = mul <4 x float> %tmp1, %tmp1
%tmp3 = add <4 x float> %tmp2, %tmp1
store <4 x float> %tmp3, <4 x float> *%a
ret void
}
As:
_foo:
li r2, 0
lvx v0, r2, r3
vmaddfp v0, v0, v0, v0
stvx v0, r2, r3
blr
Or, with llc -disable-excess-fp-precision,
_foo:
li r2, 0
lvx v0, r2, r3
vxor v1, v1, v1
vmaddfp v1, v0, v0, v1
vaddfp v0, v1, v0
stvx v0, r2, r3
blr
llvm-svn: 24719
2005-12-14 22:54:33 +00:00
023aef2f31
Fixed a typo: line 2323: MOVSX16rm8 -> MOVZX16rm8. This was the cause fo 12/14/2005 hbd failure.
...
llvm-svn: 24717
2005-12-14 22:28:18 +00:00
3db275d996
Added predicate !NoExcessFPPrecision to FMADD, FMADDS, FMSUB, and FMSUBS.
...
llvm-svn: 24716
2005-12-14 22:07:12 +00:00
d296a43f96
Added support to specify predicates.
...
llvm-svn: 24715
2005-12-14 22:02:59 +00:00
b8be9d1596
Fixed extload type profile. The 4th operand is a ValueType node with type
...
OtherVT, it cannot be compare to type of 1st operand which is an integer type.
llvm-svn: 24713
2005-12-14 19:40:54 +00:00
c273900dd8
Added sext and zext patterns.
...
llvm-svn: 24705
2005-12-14 02:22:27 +00:00
683d8515b1
Added sextld + zextld DAG nodes.
...
llvm-svn: 24703
2005-12-14 02:21:01 +00:00
40f081d8e0
Add support for fmul node of type v4f32.
...
void %foo(<4 x float> * %a) {
entry:
%tmp1 = load <4 x float> * %a;
%tmp2 = mul <4 x float> %tmp1, %tmp1
store <4 x float> %tmp2, <4 x float> *%a
ret void
}
Is selected to:
_foo:
li r2, 0
lvx v0, r2, r3
vxor v1, v1, v1
vmaddfp v0, v0, v0, v1
stvx v0, r2, r3
blr
llvm-svn: 24701
2005-12-14 00:34:09 +00:00
69caef2b78
Prepare support for AltiVec multiply, divide, and sqrt.
...
llvm-svn: 24700
2005-12-13 22:55:22 +00:00
229f0ee6d7
Add load + store folding srl and sra patterns.
...
llvm-svn: 24696
2005-12-13 07:24:22 +00:00
87079884d1
Use the shared asmprinter code for printing special llvm globals
...
llvm-svn: 24695
2005-12-13 06:32:50 +00:00
4d80f6e52e
Add ELF and darwin support for static ctors and dtors
...
llvm-svn: 24693
2005-12-13 04:53:51 +00:00
54a11df95d
reindent a loop, unswitch a loop. No functionality changes
...
llvm-svn: 24692
2005-12-13 04:33:58 +00:00
acec857b1a
Beautify a few patterns.
...
llvm-svn: 24690
2005-12-13 02:40:18 +00:00
89c6db4baf
Some shl patterns which do load + store folding.
...
llvm-svn: 24689
2005-12-13 02:34:51 +00:00
108beceb0f
A few helper fragments for loads. e.g. (i8 (load addr:$src)) -> (loadi8 addr:$src). Only to improve readibility.
...
llvm-svn: 24688
2005-12-13 01:57:51 +00:00
ddd5ae5a22
Add and, or, and xor patterns which fold load + stores.
...
llvm-svn: 24687
2005-12-13 01:41:36 +00:00
e5a94a03e2
Add inc + dec patterns which fold load + stores.
...
llvm-svn: 24686
2005-12-13 01:02:47 +00:00
bde9e6fca6
Add neg and not patterns which fold load + stores.
...
llvm-svn: 24685
2005-12-13 00:54:44 +00:00
c414d563f0
Missed a couple redundant explicit type casts.
...
llvm-svn: 24684
2005-12-13 00:25:07 +00:00
62e6808aa5
Fix some bad choice of names: i16SExt8 ->i16immSExt8, etc.
...
llvm-svn: 24683
2005-12-13 00:14:11 +00:00
86b2cf22d2
* Split immSExt8 to i16SExt8 and i32SExt8 for i16 and i32 immediate operands.
...
This enables the removal of some explicit type casts.
* Rename immZExt8 to i16ZExt8 as well.
llvm-svn: 24682
2005-12-13 00:01:09 +00:00
3e52756928
Add some integer mul patterns.
...
llvm-svn: 24681
2005-12-12 23:47:46 +00:00
af3fe8217a
Add some sub patterns.
...
llvm-svn: 24675
2005-12-12 21:54:05 +00:00
67ed58e22b
When SelectLEAAddr() fails, it shouldn't cause the side effect of having the
...
base or index operands being selected.
llvm-svn: 24674
2005-12-12 21:49:40 +00:00
bfd259a2b7
For ISD::RET, if # of operands >= 2, try selection the real data dep. operand
...
first before the chain.
e.g.
int X;
int foo(int x)
{
x += X + 37;
return x;
}
If chain operand is selected first, we would generate:
movl X, %eax
movl 4(%esp), %ecx
leal 37(%ecx,%eax), %eax
rather than
movl $37, %eax
addl 4(%esp), %eax
addl X, %eax
which does not require %ecx. (Due to ADD32rm not matching.)
llvm-svn: 24673
2005-12-12 20:32:18 +00:00
cd54254af3
fix FP selects
...
llvm-svn: 24672
2005-12-12 20:30:09 +00:00
d6b17765e4
remove some never-completed and now-obsolete code.
...
llvm-svn: 24671
2005-12-12 20:12:20 +00:00
e80248b378
Add a few more add / store patterns. e.g. ADD32mi8.
...
llvm-svn: 24670
2005-12-12 19:45:23 +00:00
b8296181e0
restore a more restricted select
...
llvm-svn: 24668
2005-12-12 17:43:52 +00:00
a4c6cc5af4
Fix typo :(
...
llvm-svn: 24664
2005-12-11 18:43:13 +00:00
254e0a842f
add selectcc
...
llvm-svn: 24662
2005-12-11 08:35:54 +00:00
090eed0483
Remove type casts that are no longer needed
...
llvm-svn: 24661
2005-12-11 07:45:47 +00:00
e6f2c82073
Realize the constant pool & global addrs must always be ptr type
...
llvm-svn: 24660
2005-12-11 07:45:04 +00:00
3d9559fedc
Fix the JIT failures from last night.
...
llvm-svn: 24659
2005-12-11 07:37:41 +00:00
20d0b81c04
FP select improvements (and likely breakage), oh and crazy people might want to *return* floating point values. Don't see why myself
...
llvm-svn: 24658
2005-12-11 03:54:31 +00:00
4e56db674c
Add support for TargetConstantPool nodes to the dag isel emitter, and use
...
them in the PPC backend, to simplify some logic out of Select and
SelectAddr.
llvm-svn: 24657
2005-12-10 02:36:00 +00:00
3c5198336c
Use SDTCisPtrTy type property for store address.
...
llvm-svn: 24656
2005-12-10 01:59:36 +00:00
0d6cfee704
* Added X86 store patterns.
...
* Added X86 dec patterns.
llvm-svn: 24654
2005-12-10 00:48:20 +00:00
ade6f9a255
Add support patterns to many load and store instructions which will
...
hopefully use patterns in the near future.
llvm-svn: 24651
2005-12-09 23:54:18 +00:00
27656ac89c
Add SDTCisPtrTy and use it for loads, to indicate that the operand of a load
...
must be a pointer. This removes a type check out of the code generated by
tblgen for load matching.
llvm-svn: 24650
2005-12-09 22:58:42 +00:00
275a3ed80c
Added patterns for ADD8rm, etc. These fold load operands. e.g. addb 4(%esp), %al
...
llvm-svn: 24648
2005-12-09 22:48:48 +00:00
e0f5f8e43c
Teach the PPC backend about the ctor and dtor list when not using __main and
...
linking the entire program into one bc file.
llvm-svn: 24645
2005-12-09 18:24:29 +00:00
87bf2234b5
it helps if your conditionals are not reversed
...
llvm-svn: 24641
2005-12-09 00:45:42 +00:00
29e6c3dbf9
Add another important case we miss
...
llvm-svn: 24639
2005-12-08 07:13:28 +00:00
790af6d18f
Added support for ComplexPattern.
...
llvm-svn: 24638
2005-12-08 04:28:48 +00:00
f039648614
Added explicit type field to ComplexPattern.
...
llvm-svn: 24637
2005-12-08 02:15:07 +00:00
c9fab31098
* Added intelligence to X86 LEA addressing mode matching routine so it returns
...
false if the match is not profitable. e.g. leal 1(%eax), %eax.
* Added patterns for X86 integer loads and LEA32.
llvm-svn: 24635
2005-12-08 02:01:35 +00:00
3225733e65
X86 doesn't support sextinreg for 8-bit things either.
...
llvm-svn: 24631
2005-12-07 17:59:14 +00:00
26473b6b58
fix divide and remainder
...
llvm-svn: 24628
2005-12-06 23:27:39 +00:00
de085f0165
Silence another annoying GCC warning
...
llvm-svn: 24627
2005-12-06 20:56:18 +00:00
973cd1c845
more decent branches for FP. I might have to make some intermediate nodes to actually be able to use the DAG for FPcmp
...
llvm-svn: 24625
2005-12-06 20:43:30 +00:00
29b7ef0065
OK, this does wonders for broken stuff
...
llvm-svn: 24624
2005-12-06 20:40:34 +00:00
fea33f7e64
Use new PPC-specific nodes to represent shifts which require the 6-bit
...
amount handling that PPC provides. These are generated by the lowering code
and prevents the dag combiner from assuming (rightfully) that the shifts
don't only look at 5 bits. This fixes a miscompilation of crafty with
the new front-end.
llvm-svn: 24615
2005-12-06 02:10:38 +00:00
e788bbf6ef
added instructions with inverted immediates
...
llvm-svn: 24614
2005-12-06 00:33:53 +00:00
08c4a775e6
yea, it helps to have your path set right when testing
...
llvm-svn: 24613
2005-12-05 23:41:45 +00:00
3c7c4d7508
These never trigger, but whatever
...
llvm-svn: 24612
2005-12-05 23:19:44 +00:00
c0c190239d
Remove unnecessary let hasCtrlDep=1 now it can be inferred.
...
llvm-svn: 24611
2005-12-05 23:09:43 +00:00
5bfcd1e63a
move this over to the dag
...
llvm-svn: 24609
2005-12-05 20:50:53 +00:00
9410433966
fix constant pool loads
...
llvm-svn: 24607
2005-12-05 17:51:02 +00:00
3c0b8f577d
Several things:
...
1. Remove redundant type casts now that PR673 is implemented.
2. Implement the OUT*ir instructions correctly. The port number really
*is* a 16-bit value, but the patterns should only match if the number
is 0-255. Update the patterns so they now match.
3. Fix patterns for shifts to reflect that the shift amount is always an
i8, not an i16 as they were believed to be before. This previous fib
stopped working when we started knowing that CL has type i8.
4. Change use of i16i8imm in SH*ri patterns to all be imm.
llvm-svn: 24599
2005-12-05 02:40:25 +00:00
282c2af4d8
On some targets (e.g. X86), shift amounts are not the same as the value
...
being shifted. Don't assume they are.
llvm-svn: 24598
2005-12-05 02:37:26 +00:00
c54cddd25b
Add some explicit type casts so that tblgen knows the type of the shiftamount, which is not necessarily the same as the type being shifted.
...
llvm-svn: 24595
2005-12-05 02:34:29 +00:00
f3322af5c6
Add some explicit type casts so that tblgen knows the type of the shift
...
amount, which is not necessarily the same as the type being shifted.
llvm-svn: 24594
2005-12-05 02:34:05 +00:00
efc86f5f7a
The basic fneg cases are already autogen'd
...
llvm-svn: 24592
2005-12-04 19:04:38 +00:00
f979794717
Autogen matching code for ADJCALLSTACK[UP|DOWN], thanks to Evan's tblgen
...
improvements.
llvm-svn: 24591
2005-12-04 19:01:59 +00:00
fd857daa0d
Finish moving uncond br over to .td file, remove from .cpp file.
...
llvm-svn: 24590
2005-12-04 18:48:01 +00:00
d9d18aff6a
Define BR in the .td file now that Evan made tblgen smarter.
...
llvm-svn: 24589
2005-12-04 18:42:54 +00:00
95cb763818
Added isel patterns for RET, JMP, and WRITEPORT.
...
llvm-svn: 24588
2005-12-04 08:19:43 +00:00
e8531381e2
* Added instruction property hasCtrlDep for those which r/w control-flow
...
chains.
* Added DAG node property SDNPHasChain for nodes which r/w control-flow
chains.
* Renamed SDTVT to SDTOther.
* Added several new SDTypeProfiles for BR, BRCOND, RET, and WRITEPORT.
* Added SDNode definitions for BR, BRCOND, RET, and WRITEPORT.
llvm-svn: 24586
2005-12-04 08:13:17 +00:00
7e79292fef
Fix PR672 another way which should be more robust
...
llvm-svn: 24585
2005-12-04 06:03:50 +00:00
ecfc7e56c5
Fix test/Regression/ExecutionEngine/2005-12-02-TailCallBug.ll and PR672.
...
This also fixes 177.mesa, the only program that fails with --enable-x86-fastcc
turned on. Given a clean nightly tester run, we should be able to turn it
on by default!
llvm-svn: 24578
2005-12-03 07:15:55 +00:00
986cb40953
add a note
...
llvm-svn: 24572
2005-12-02 00:11:20 +00:00
93feffb4ed
IA64 doesn't support the LOCATION node, and for some reason the ISelPattern
...
stuff isn't using ISelLowering.cpp
llvm-svn: 24567
2005-12-01 18:19:53 +00:00
df9287836e
Make sure these get added into the codegenmap when appropriate
...
llvm-svn: 24566
2005-12-01 18:09:22 +00:00
7bb09912c8
major think-o
...
llvm-svn: 24564
2005-12-01 17:48:51 +00:00
006bb04f3a
Support multiple ValueTypes per RegisterClass, needed for upcoming vector
...
work. This change has no effect on generated code.
llvm-svn: 24563
2005-12-01 04:51:06 +00:00
aa5f8f2a26
Cosmetic change, better reflects actual values
...
llvm-svn: 24562
2005-12-01 04:48:26 +00:00
bd099102f0
Fix a regression caused by a patch earlier today
...
llvm-svn: 24561
2005-12-01 03:50:19 +00:00
ce68ef8073
Flags where I think I need them, quick, before the nightly tester starts
...
llvm-svn: 24560
2005-12-01 01:53:10 +00:00
4b02426130
Proper support for shifts with register shift value.
...
llvm-svn: 24559
2005-12-01 00:43:55 +00:00
d94aa71e1a
Use a getCopyToReg() variant to generate a flaggy CopyToReg node.
...
llvm-svn: 24558
2005-12-01 00:41:50 +00:00
4b25924d2a
SelectNodeTo now returns its result, we must pay attention to it.
...
llvm-svn: 24552
2005-11-30 23:04:38 +00:00
a75694aa16
Pay attn to the node returned by SelectNodeTo
...
llvm-svn: 24551
2005-11-30 23:02:08 +00:00
af2e0373dd
SelectNodeTo now returns its result, we must pay attention to it.
...
llvm-svn: 24550
2005-11-30 22:59:19 +00:00
e318977940
SelectNodeTo now returns N. Use it instead of return N directly.
...
llvm-svn: 24549
2005-11-30 22:53:06 +00:00
3713e6b49c
Fix Regression/CodeGen/PowerPC/2005-11-30-vastart-crash.ll
...
llvm-svn: 24547
2005-11-30 20:40:54 +00:00
11695c0537
Fix a typo in my latest change
...
llvm-svn: 24542
2005-11-30 18:57:39 +00:00
6f8c1ace6e
No longer track value types for asm printer operands, and remove them as
...
an argument to every operand printing function. Requires some slight
tweaks to x86, the only user.
llvm-svn: 24541
2005-11-30 18:54:35 +00:00
7ffe3affda
remove redundant code
...
llvm-svn: 24538
2005-11-30 17:14:11 +00:00
ede966e8ee
Make typesafe that which isn't: FCMOVxx
...
llvm-svn: 24536
2005-11-30 17:11:20 +00:00
873ed82a36
FPSelect and more custom lowering
...
llvm-svn: 24535
2005-11-30 16:10:29 +00:00
1064d6ec43
First chunk of actually generating vector code for packed types. These
...
changes allow us to generate the following code:
_foo:
li r2, 0
lvx v0, r2, r3
vaddfp v0, v0, v0
stvx v0, r2, r3
blr
for this llvm:
void %foo(<4 x float>* %a) {
entry:
%tmp1 = load <4 x float>* %a
%tmp2 = add <4 x float> %tmp1, %tmp1
store <4 x float> %tmp2, <4 x float>* %a
ret void
}
llvm-svn: 24534
2005-11-30 08:22:07 +00:00
6db615df14
All sorts of stuff.
...
Getting in on the custom lowering thing, yay
evilness with fp setcc, yuck
trivial int select, hmmm
in memory args for functions, yay
DIV and REM, always handy. They should be custom lowered though.
Lots more stuff compiles now (go go single source!). Of course, none of it
probably works, but that is what the nightly tester can find out :)
llvm-svn: 24533
2005-11-30 07:19:56 +00:00
9c7af08bc9
Fix a bug in a recent patch that broke shifts
...
llvm-svn: 24526
2005-11-30 05:11:18 +00:00
4eb7af9bc9
Added support to STORE and shifts to DAG to DAG isel.
...
llvm-svn: 24525
2005-11-30 02:51:20 +00:00
d2cb70513d
Fixed a minor bug: - -offset != offset iff offset == MININT
...
llvm-svn: 24522
2005-11-30 01:59:00 +00:00
048b26387b
Represent the encoding of the SPR instructions as they actually are, so
...
that we can use the correct SPR numbers in the InstrInfo.td file. This is
necessary to support VRsave.
llvm-svn: 24521
2005-11-29 22:42:50 +00:00
72ab335858
Add more X86 ISel patterns.
...
llvm-svn: 24520
2005-11-29 19:38:52 +00:00
3e7db9c6d5
Hook up one type, v4f32, to the VR RegisterClass for now.
...
llvm-svn: 24517
2005-11-29 08:17:20 +00:00
c138118cdb
Add the remainder of the AltiVec 4 x float instructions. Further
...
enhancements will be necessary to teach the code generator that since
there is no fmul, it will have to do vmaddfp, adding +0.0.
llvm-svn: 24516
2005-11-29 08:04:45 +00:00
9c415364cf
No targets support line number info yet.
...
llvm-svn: 24513
2005-11-29 06:16:21 +00:00
89b049af90
Add the majority of the vector machien value types we expect to support,
...
and make a few changes to the legalization machinery to support more than
16 types.
llvm-svn: 24511
2005-11-29 05:45:29 +00:00
1d4af53444
Fixed a comment bug:
...
createPPCPatternInstructionSelector -> createPPCISelPattern
llvm-svn: 24510
2005-11-29 04:59:46 +00:00
c418b5d938
refix typo
...
llvm-svn: 24505
2005-11-29 00:42:30 +00:00
7a18a25d33
don't say this is i128, because it isn't yet. Hopefully nate will change
...
this to be something sane, but in the mean time it is unused, so safe to
make something bogus.
llvm-svn: 24504
2005-11-29 00:41:40 +00:00
d3bc8cb26d
revert my change for the time being, which broke the build
...
llvm-svn: 24503
2005-11-29 00:24:08 +00:00
50986909dc
fix a typo :)
...
llvm-svn: 24501
2005-11-28 22:42:15 +00:00
820c94e467
Add a missed optimization
...
llvm-svn: 24495
2005-11-28 04:52:39 +00:00
11fd6b22b1
Small tweaks noticed while on the plane.
...
llvm-svn: 24492
2005-11-26 22:39:34 +00:00
0c88f150c6
add support for dynamic_stackalloc to the dag isel (thanks andrew ;)
...
next up: support argument passing in memory, not just registers
llvm-svn: 24490
2005-11-25 07:49:25 +00:00
8492fd30ab
Some first bits of AltiVec stuff: Instruction Formats, Encodings, and
...
Registers. Apologies to Jim if the scheduling info so far isn't accurate.
There's a few more things like VRsave support that need to be finished up
in my local tree before I can commit code that Does The Right Thing for
turning 4 x float into the various altivec packed float instructions.
llvm-svn: 24489
2005-11-23 05:29:52 +00:00
d6a0308470
Fix warning, the better way. Really, this is what this instruction is for, so use it
...
llvm-svn: 24486
2005-11-22 20:59:00 +00:00
03390557fa
Fix warning
...
llvm-svn: 24485
2005-11-22 20:56:05 +00:00
0294e33ea4
massive DAGISel patch. lots and lots more stuff compiles now
...
llvm-svn: 24483
2005-11-22 04:20:06 +00:00
07890bbec4
Rather than attempting to legalize 1 x float, make sure the SD ISel never
...
generates it. Make MVT::Vector expand-only, and remove the code in
Legalize that attempts to legalize it.
The plan for supporting N x Type is to continually epxand it in ExpandOp
until it gets down to 2 x Type, where it will be scalarized into a pair of
scalars.
llvm-svn: 24482
2005-11-22 01:29:36 +00:00
ac6cb46429
Use HasDotTypeDotSizeDirective instead of forELF
...
llvm-svn: 24481
2005-11-21 23:06:54 +00:00
78161dbc84
Remove a level of indentation by using a continue.
...
llvm-svn: 24479
2005-11-21 22:48:18 +00:00
40f8c8450d
Simplify the subtarget info, allow the asmwriter to do some target sensing
...
based on TargetType.
llvm-svn: 24478
2005-11-21 22:43:58 +00:00
99be8f766f
Use subtarget information computed by X86Subtarget instead of rolling our own.
...
llvm-svn: 24477
2005-11-21 22:39:40 +00:00
3eb876117a
Make the X86 subtarget compute the basic target type: ELF, Cygwin, Darwin,
...
or native Win32
llvm-svn: 24476
2005-11-21 22:31:58 +00:00
ebc39f5a9c
Add a forELF flag, allowing the removal of forCygwin and simplification of
...
conditionals.
llvm-svn: 24475
2005-11-21 22:19:48 +00:00
7df25ab429
simplify and genericize this code
...
llvm-svn: 24473
2005-11-21 19:50:31 +00:00
8edbf805d7
add support for div/rem to the dag->dag isel. yay.
...
llvm-svn: 24472
2005-11-21 14:14:54 +00:00
b9db67a045
Eliminate unneeded intermediate class. Move doFinalizeMethod to bottom of
...
file.
llvm-svn: 24470
2005-11-21 08:40:17 +00:00
b55de47595
Start using shared asmprinter Constant Pool emitter, use shorter cpi names.
...
llvm-svn: 24469
2005-11-21 08:38:26 +00:00
4a7eb5132b
prune #include
...
llvm-svn: 24468
2005-11-21 08:33:17 +00:00
8a5f3c1b68
Switch to using the shared constant pool printer, along with using shorter
...
CPI ids
llvm-svn: 24467
2005-11-21 08:32:23 +00:00
882b9fa977
Switch to using the generic constant pool emitter impl, use shorter
...
CPI names
llvm-svn: 24466
2005-11-21 08:29:17 +00:00
ef83ebd45d
Use generic constant pool emission code in the AsmPrinter class.
...
llvm-svn: 24465
2005-11-21 08:26:15 +00:00
ffbfa71866
Use the FunctionNumber provided by the AsmPrinter class
...
llvm-svn: 24462
2005-11-21 08:14:07 +00:00
dd3bf8e4a2
Use CommentString where possible, fix a bug where aix mode wouldn't assemble
...
due to basic blocks being misnamed.
llvm-svn: 24459
2005-11-21 08:02:41 +00:00
a0222a1698
unify the darwin and aix constant pool printers
...
llvm-svn: 24458
2005-11-21 07:57:37 +00:00
99946fb63f
Adjust to capitalized AsmPrinter method names
...
llvm-svn: 24456
2005-11-21 07:51:23 +00:00
d365627d3e
Use PrivateGlobalPrefix for basic block labels. This allows the x86 darwin
...
port to properly use L for the bb prefix instead of .
llvm-svn: 24454
2005-11-21 07:43:59 +00:00
c2bc19af57
use PrivateGlobalPrefix for basic blocks
...
llvm-svn: 24453
2005-11-21 07:41:05 +00:00
2b53ea99b0
Use PrivateGlobalPrefix for basic block labels
...
llvm-svn: 24452
2005-11-21 07:39:22 +00:00
9885c97088
Use PrivateGlobalPrefix for basic blocks
...
llvm-svn: 24451
2005-11-21 07:38:08 +00:00
a43b832f7f
Switch to the new shared SwitchSection
...
llvm-svn: 24450
2005-11-21 07:30:28 +00:00
2bccd73dbb
Start using SwitchSection, allowing globals and functions to be emitted
...
to specific sections. Delete some dead functions copied from the X86 backend.
llvm-svn: 24449
2005-11-21 07:26:04 +00:00
050bf2faf8
convert the rest of this over to use SwitchSection
...
llvm-svn: 24448
2005-11-21 07:16:34 +00:00
024e32e118
Start using the AsmPrinter shared SwitchSection code. This allows the X86
...
backend to implement global variables in sections.
llvm-svn: 24447
2005-11-21 07:11:11 +00:00
b650241f8b
This is now implemented in common codegen code
...
llvm-svn: 24446
2005-11-21 07:06:58 +00:00
2c0b435ba6
Rename SwitchSection -> switchSection to avoid conflicting with a future
...
change.
llvm-svn: 24443
2005-11-21 06:55:27 +00:00
8a4995e42a
Start using PrivateGlobalPrefix correctly
...
llvm-svn: 24442
2005-11-21 06:51:52 +00:00
41cb115afb
set PrivateGlobalPrefix on darwin, use it when printing out CP references
...
llvm-svn: 24441
2005-11-21 06:47:58 +00:00
618981fd03
Naturally align doubles in the constant pool, set PrivateGlobalPrefix on
...
darwin, use it when printing the constant pool indices so the labels are
appropriately private, emit cp entries to .const instead of .data on darwin
and only emit a single .section for the constant pool, not one for each
entry.
llvm-svn: 24440
2005-11-21 06:46:22 +00:00
6c1ca888d4
Lower READCYCLECOUNTER correctly, preserving the chain result
...
llvm-svn: 24438
2005-11-20 22:57:19 +00:00
d1061ac8d1
encode rdtsc correctly
...
llvm-svn: 24435
2005-11-20 22:13:18 +00:00
6df9e11989
use chain operands to ensure the copies don't wander from the rdtsc instruction.
...
llvm-svn: 24434
2005-11-20 22:01:40 +00:00
0bf68ae434
The second patch of X86 support for read cycle counter.
...
llvm-svn: 24430
2005-11-20 21:41:10 +00:00
d7102c4980
Teach the x86 backend about the register constraints of its addressing mode.
...
Patch by Evan Cheng
llvm-svn: 24423
2005-11-19 07:01:30 +00:00
252d88c68e
Capture more operand info, patch by Evan Cheng
...
llvm-svn: 24422
2005-11-19 07:00:10 +00:00
3f0f71b92b
Add load and other support to the dag-dag isel. Patch contributed by Evan
...
Cheng!
llvm-svn: 24419
2005-11-19 02:11:08 +00:00
6bc51c6f34
prevent latent switch creation
...
llvm-svn: 24413
2005-11-18 13:57:03 +00:00
57ce97862d
add more patterns, patch by Evan Cheng.
...
llvm-svn: 24406
2005-11-18 01:04:42 +00:00
227f1bdd2f
Also add the new vector value type here, for completeness.
...
llvm-svn: 24405
2005-11-18 00:53:32 +00:00
cdde9990b7
only use dyld stubs if not in ppc-static mode. This completes support for
...
non-static codegen.
llvm-svn: 24403
2005-11-17 19:40:30 +00:00
6ab87fa360
refactor call operand handling to eliminate special cases from printOp.
...
llvm-svn: 24401
2005-11-17 19:25:59 +00:00
bd9efdb64c
disentangle call operands from branch operands a bit
...
llvm-svn: 24400
2005-11-17 19:16:08 +00:00
3570cf456b
add an option to generate completely non-pic code, corresponding to what
...
gcc -static produces on PPC. This is used for building kexts and other things.
With this, materializing the address of a global looks like:
lis r2, ha16(L_H$non_lazy_ptr)
la r3, lo16(L_H$non_lazy_ptr)(r2)
we're still emitting stubs for functions, which is wrong. That is next.
llvm-svn: 24399
2005-11-17 18:55:48 +00:00
8f8ed28a64
Fix a bug that resistor on IRC hit where we tried to create token factor
...
nodes of load results, not of their chain results.
llvm-svn: 24398
2005-11-17 18:30:17 +00:00
5aba6ae3b3
Enable global address legalization, fixing a todo and allowing the removal
...
of some code. This exposes the implicit load from the stubs to the DAG, allowing
them to be optimized by the dag combiner. It also moves darwin specific stuff
out of the isel into the legalizer, and allows more to be moved to the .td file.
llvm-svn: 24397
2005-11-17 18:26:56 +00:00
0fe88e3f32
Teach the selector to fold lo(g) into load instruction immediate fields
...
llvm-svn: 24396
2005-11-17 18:02:16 +00:00
4b11fa284d
Generate LA and ADDIS when possible.
...
llvm-svn: 24395
2005-11-17 17:52:01 +00:00
3648c20472
Use the right accessor to create this node
...
llvm-svn: 24394
2005-11-17 17:51:38 +00:00
595088aa0f
Add an initial hack at legalizing GlobalAddress into the appropriate nodes
...
on Darwin to remove smarts from the isel. This is currently disabled by
default (uncomment setOperationAction(ISD::GlobalAddress to enable it).
tblgen needs to become smarter about tglobaladdr nodes and bigger patterns
needed to be added to the .td file. However, we can currently emit stuff like
this: :)
li r2, lo16(L_x$non_lazy_ptr)
lis r3, ha16(L_x$non_lazy_ptr)
lwzx r2, r3, r2
The obvious improvements will follow.
llvm-svn: 24390
2005-11-17 07:30:41 +00:00
840458276c
Add globaladdress and targetglobaladdress nodes for dag patterns
...
llvm-svn: 24389
2005-11-17 07:20:15 +00:00
63ed749ce0
LI could theoretically be used for the lo-part of a global address, just like
...
lis can be used for the high part.
llvm-svn: 24388
2005-11-17 07:04:43 +00:00
b7025749e1
When lowering direct calls, lower them to use a targetglobaladress directly
...
instead of a globaladdress. This has no effect on the generated code at all.
llvm-svn: 24386
2005-11-17 05:56:14 +00:00
2bf458af92
Add patterns for some 16-bit immediate instructions, patch contributed by
...
Evan Cheng.
llvm-svn: 24384
2005-11-17 02:01:55 +00:00
5930d3df3d
Add patterns for several simple instructions that take i32 immediates.
...
Patch contributed by Evan Cheng!
llvm-svn: 24382
2005-11-16 22:59:19 +00:00
59eefd4787
who would have thought you would want to write into globals too
...
llvm-svn: 24381
2005-11-16 21:15:53 +00:00
655e7dfd0d
initial step at adding a dag-to-dag isel for X86 backend. Patch contributed
...
by Evan Cheng!
llvm-svn: 24371
2005-11-16 01:54:32 +00:00
a171f6b20c
Patch to clean up function call pseudos and support the BLA instruction,
...
which branches to an absolute address. This is required to support objc
direct dispatch.
llvm-svn: 24370
2005-11-16 00:48:01 +00:00
63985e2892
Make sure to use SwitchSection to switch sections so that we don't accidentally emit
...
functions into the .const section. Whoops.
llvm-svn: 24363
2005-11-15 01:45:01 +00:00
76ac068568
Separate X86ISelLowering stuff out from the X86ISelPattern.cpp file. Patch
...
contributed by Evan Cheng.
llvm-svn: 24358
2005-11-15 00:40:23 +00:00
1a4adc7aee
Handle globals with explicit alignment requests
...
llvm-svn: 24355
2005-11-14 19:00:30 +00:00
0aacd2ab9b
Teach the PPC asmwriter to honor globals with explicit section requests.
...
llvm-svn: 24353
2005-11-14 18:52:46 +00:00
76034f95f6
add FP select. next up - divide!
...
llvm-svn: 24346
2005-11-14 01:17:30 +00:00
54c8fcf303
unbreak the build
...
llvm-svn: 24339
2005-11-13 01:45:23 +00:00
ab72424488
enable LSR by default on alpha
...
llvm-svn: 24337
2005-11-12 19:21:08 +00:00
2ba45d1ee9
fix more regressions
...
llvm-svn: 24335
2005-11-12 19:06:28 +00:00
56526ec1a9
fix READCYCLECOUNTER
...
llvm-svn: 24334
2005-11-12 19:04:09 +00:00
97e8207a05
fix yet more regressions
...
llvm-svn: 24308
2005-11-11 23:08:46 +00:00
fab772045e
generate chain result
...
llvm-svn: 24307
2005-11-11 23:02:55 +00:00
5b3b9d7052
Fix a bunch more alpha regressions
...
llvm-svn: 24304
2005-11-11 19:52:25 +00:00
01aa56397d
continued readcyclecounter support
...
llvm-svn: 24300
2005-11-11 16:47:30 +00:00
fafff9ba1d
Make BB and CPI labels use the function number, not the function name as a
...
uniquing id. This makes things happy when the function name is quoted,
preventing labels like LBB"foo"_2.
llvm-svn: 24295
2005-11-10 21:59:25 +00:00
4b3b9192b2
do not allow '.' in symbol names
...
llvm-svn: 24292
2005-11-10 21:39:29 +00:00
9eb7dfa15a
Darwin supports quoted labels. This implements:
...
test/Regression/CodeGen/PowerPC/darwin-labels.ll
llvm-svn: 24287
2005-11-10 19:33:43 +00:00
369b61f068
Call this method with the object we have
...
llvm-svn: 24279
2005-11-10 18:53:25 +00:00
59e44ff3d3
Make the aix asm printer interface properly with the parent class
...
llvm-svn: 24274
2005-11-10 18:20:29 +00:00
e373163e95
fix a bunch of regressions
...
llvm-svn: 24269
2005-11-10 16:59:55 +00:00
97a7fcfd2b
whatever. Intermediate patch to see what breaks. Seems ok.
...
llvm-svn: 24260
2005-11-09 19:17:08 +00:00
88e234dd49
Add a new option to indicate we want the code generator to emit code quickly,
...
not spending tons of time microoptimizing it. This is useful for an -O0
style of build.
llvm-svn: 24235
2005-11-08 02:12:47 +00:00
b28f214033
Add a new option to indicate we want the code generator to emit code quickly,not spending tons of time microoptimizing it. This is useful for an -O0style of build.
...
llvm-svn: 24233
2005-11-08 02:11:51 +00:00
3c1c8c55c3
add support for storing and returning bools
...
llvm-svn: 24228
2005-11-07 03:11:02 +00:00
4a30d4a460
just some random hacking - calls (particularly indirect) need a lot of
...
love (especially with -sched=simple)
llvm-svn: 24225
2005-11-06 13:43:30 +00:00
3ee3e69556
Add the necessary support to the ISel to allow targets to codegen the new
...
alignment information appropriately. Includes code for PowerPC to support
fixed-size allocas with alignment larger than the stack. Support for
arbitrarily aligned dynamic allocas coming soon.
llvm-svn: 24224
2005-11-06 09:00:38 +00:00
4645db0948
ask for 16-byte aligned jmpbufs. This should unbreak C++ on IA64 (and
...
a bunch of other things) but is currently ignored by the code
generator.
llvm-svn: 24206
2005-11-06 04:29:30 +00:00
75fe59c4ea
add a case Nate sent me
...
llvm-svn: 24195
2005-11-05 08:57:56 +00:00
31071b7471
oops, forgot to load GP for indirect calls, though the old code now commented
...
out failed (e.g. methcall) - now the code compiles, though it's not quite
right just yet (tm) ;)
would fix this but it's 3am! :O
llvm-svn: 24186
2005-11-04 17:55:53 +00:00
d3260128af
kill redundant SP/GP/RP save/restores across calls
...
llvm-svn: 24183
2005-11-04 10:01:10 +00:00
fc1d1b2499
add support for loading bools
...
llvm-svn: 24182
2005-11-04 09:59:06 +00:00
7ac646ef95
fun with predicates! (add TRUNC i64->i1, AND i1 i1, fix XOR i1 i1)
...
llvm-svn: 24175
2005-11-04 00:57:56 +00:00
f0f22a55b0
add pattern to load constant 0 into a predicate reg
...
llvm-svn: 24164
2005-11-03 10:09:32 +00:00
674660ff03
Fix a bug that prevented this pattern from matching
...
llvm-svn: 24161
2005-11-03 05:45:34 +00:00
9b9a839605
Fix a QOI issue noticed by Markus F.X.J. Oberhumer.
...
This fixes PR641
llvm-svn: 24154
2005-11-02 17:42:58 +00:00
955ffafd79
"fix" support for FP constants (this code asserts in the scheduler,
...
though)
llvm-svn: 24152
2005-11-02 07:32:59 +00:00
4480dcdcea
add F0 and F1 to the FP register class
...
llvm-svn: 24151
2005-11-02 07:30:39 +00:00
b5310bdbe9
This works now
...
llvm-svn: 24150
2005-11-02 06:49:37 +00:00
17decbb253
add support for SELECT to TargetSelectionDAG.td, add support for
...
selecting ints to IA64, and a few other ia64 bits and pieces
llvm-svn: 24147
2005-11-02 02:37:18 +00:00
9abf1650ed
add support for loading FP constants +0.0 and +1.0 to the dag isel,
...
stop pretending -0.0 and -1.0 are machine constants
llvm-svn: 24146
2005-11-02 02:35:04 +00:00
802748cd61
Allow itineraries to be passed through the Target Machine.
...
llvm-svn: 24139
2005-11-01 20:06:59 +00:00
5a087ff8c3
heh, scheduling was easy?
...
need to send chris, jim and sampo a box of fish each
llvm-svn: 24135
2005-11-01 05:49:08 +00:00
9b61d3c1e2
FORTRAN!!! :( and other similarly unfortunate things mean that on ia64
...
one sometimes needs to pass FP args in both FP *and* integer registers.
llvm-svn: 24134
2005-11-01 05:46:16 +00:00
b81b61330e
so tablegen was thinking I might want to convert FPs to predicates.
...
clever little tablegen!
llvm-svn: 24133
2005-11-01 03:32:15 +00:00
6c912bffd6
add support for int->FP and FP->int ops, and add ia64 patterns for these
...
llvm-svn: 24132
2005-11-01 03:07:25 +00:00
a284b6636f
add zeroextend predicate->integer
...
llvm-svn: 24131
2005-11-01 01:29:55 +00:00
7432ceef5c
Add a flag to enable a darwin linker optimization
...
llvm-svn: 24130
2005-11-01 00:12:36 +00:00
6b63e0c6fd
Make constant pool entries use private labels. This is important when you're
...
not compiling a whole program at a time :)
llvm-svn: 24129
2005-10-31 22:12:06 +00:00
88fc69f627
add FP compares and implicit register defs to the dag isel
...
llvm-svn: 24118
2005-10-31 01:42:11 +00:00
5c7d731832
If the module has no t-t and the host is an alpha, default to using the Alpha BE
...
llvm-svn: 24110
2005-10-30 16:44:01 +00:00
57b7ee9da8
fix some broken comparisons, this affected the Pattern isel too.
...
llvm-svn: 24109
2005-10-30 10:14:19 +00:00
e507a15184
This is implemented
...
llvm-svn: 24107
2005-10-30 06:42:12 +00:00
85b184b292
Make -time-passes output prettier
...
llvm-svn: 24096
2005-10-29 16:45:02 +00:00
7abaf906e2
add some FP stuff, some mix.* stuff, and constant pool support to the
...
DAG instruction selector, which should be destroyed one day (in the pattern
isel also) since ia64 can pack any constant in the instruction stream
llvm-svn: 24094
2005-10-29 16:08:30 +00:00
dcceae104e
remove reference to this pass
...
llvm-svn: 24088
2005-10-29 05:28:34 +00:00
c252f33fdb
add shladd
...
llvm-svn: 24080
2005-10-29 04:13:40 +00:00
00cea9b2e0
New case to handle someday
...
llvm-svn: 24075
2005-10-28 23:26:57 +00:00
7ca53a5783
Don't emit "32" for unordered comparison
...
llvm-svn: 24073
2005-10-28 22:58:07 +00:00
f8899a6877
add a hack to get code with ordered comparisons working. This hack is
...
tracked as PR642
llvm-svn: 24068
2005-10-28 20:49:47 +00:00
5d6cb604de
add support for branch on ordered/unordered.
...
llvm-svn: 24067
2005-10-28 20:32:44 +00:00
97d72c80e4
Do not globalize internal symbols
...
llvm-svn: 24064
2005-10-28 18:44:07 +00:00
12fca42062
These are autogenerated
...
llvm-svn: 24063
2005-10-28 18:26:52 +00:00
f221c261f3
DAG->DAG instruction selection for ia64! "hello world" works, not much else.
...
use -enable-ia64-dag-isel to turn this on
TODO: delete lowering stuff from the pattern isel
: get operations on predicate bits working
: get other bits of pseudocode going
: use sampo's mulh/mull-using divide-by-constant magic
: *so* many patterns ("extr", "tbit" and "dep" will be fun :)
: add FP
: add a JIT!
: get it working 100%
in short: this'll be happier in a couple of weeks, but it's here now so
the tester can make me feel guilty sooner.
OTHER: there are a couple of fixes to the pattern isel, in particular
making the linker happy with big blobs of fun like pypy.
llvm-svn: 24058
2005-10-28 17:46:35 +00:00
529169cab2
remove dead stuff
...
llvm-svn: 24054
2005-10-28 04:58:24 +00:00
e68a807025
Eliminate getClass, it is not needed
...
llvm-svn: 24053
2005-10-28 04:57:11 +00:00
a0dfc67ae6
a bad case for bitfield insert
...
llvm-svn: 24051
2005-10-28 00:20:45 +00:00
381cab36ed
int comparison patterns
...
llvm-svn: 24020
2005-10-26 18:44:45 +00:00
75eab3ca63
Typo made worse x 2 - take 2.
...
llvm-svn: 24018
2005-10-26 18:07:50 +00:00
f718a9e17b
Fix an assert compiling MallocBench/gs
...
llvm-svn: 24017
2005-10-26 18:01:11 +00:00
b1f2cedbaa
Typo x 2
...
llvm-svn: 24016
2005-10-26 17:50:22 +00:00
7ac194560e
Simplify instinfo, set random bits on more fp insts, and fix 1 opcode
...
llvm-svn: 24014
2005-10-26 17:41:46 +00:00
a2b5235fac
Give full control of subtarget features over to table generated code.
...
llvm-svn: 24013
2005-10-26 17:30:34 +00:00
53ad110490
Add attribute name and type to SubtargetFeatures.
...
llvm-svn: 24012
2005-10-26 17:28:23 +00:00
ce9580fce4
Add nodes for CondCodeSDNode and setcc, and add a bunch of pattern fragments
...
to make it easy to use them. This lets you write patterns like:
(set PRRC:$rd, (setne GPRC:$rS, imm:$SH))
and stuff.
llvm-svn: 24009
2005-10-26 17:00:25 +00:00
ff1796534f
Add a note about some bitfield stuff we could be doing better.
...
llvm-svn: 23994
2005-10-25 23:50:02 +00:00
762bf809b5
Correctly Expand or Promote FP_TO_UINT based on the capabilities of the
...
machine. This allows us to generate great code for i32 FP_TO_UINT now on
targets with 64 bit extensions.
llvm-svn: 23993
2005-10-25 23:48:36 +00:00
81ff73ec46
autogen undef
...
llvm-svn: 23991
2005-10-25 21:03:41 +00:00
3a4b141e8c
Add undef
...
llvm-svn: 23990
2005-10-25 21:03:14 +00:00
b439dad538
Allow pseudos to have patterns, no functionality change
...
llvm-svn: 23988
2005-10-25 20:58:43 +00:00
261009a4df
Autogen fsel
...
llvm-svn: 23987
2005-10-25 20:55:47 +00:00
65845a2f7c
Expose the fextend on the DAG instead of doing it in the matcher
...
llvm-svn: 23986
2005-10-25 20:54:57 +00:00
cd7f101c9a
Autogen a few new ppc-specific nodes
...
llvm-svn: 23985
2005-10-25 20:41:46 +00:00
26ee5953f7
The dag isel generator generates this now
...
llvm-svn: 23984
2005-10-25 20:36:10 +00:00
c0a201c318
Be a bit more paranoid about calling SelectNodeTo
...
llvm-svn: 23982
2005-10-25 20:26:41 +00:00
e1fd05ebde
Fix a couple of minor bugs. The first fixes povray, the second fixes things
...
if the dag combiner isn't run
llvm-svn: 23981
2005-10-25 19:32:37 +00:00
db4621a5f5
Preparation of supporting scheduling info. Need to find info based on selected
...
CPU.
llvm-svn: 23974
2005-10-25 15:15:28 +00:00
76b12c4d95
do not wrap this whole file in namespace llvm
...
llvm-svn: 23962
2005-10-24 06:38:35 +00:00
2a65d7b633
Make this build with GCC 4.1, patch contributed by Vladimir A. Merzliakov!
...
llvm-svn: 23956
2005-10-24 04:51:35 +00:00
bde3845548
DONT_BUILD_RELINKED is gone and implied by BUILD_ARCHIVE now
...
llvm-svn: 23940
2005-10-24 02:26:13 +00:00
df88d79c08
only build .a version of this library
...
llvm-svn: 23938
2005-10-24 02:14:49 +00:00
437b6116c9
There is no need to build an archive version of this library
...
llvm-svn: 23936
2005-10-24 02:09:03 +00:00
87d4e1c130
This file is hopelessly out of date
...
llvm-svn: 23935
2005-10-24 02:07:08 +00:00
d36c34822e
Simplify this, matching changes in the tblgen emitter
...
llvm-svn: 23909
2005-10-23 22:34:25 +00:00
03bf3a1763
Simplify this due to changes in the tblgen side
...
llvm-svn: 23908
2005-10-23 22:33:22 +00:00
abcce5c4b3
mark this as beta
...
llvm-svn: 23906
2005-10-23 22:23:45 +00:00
8ff9df29a9
If a user requests help, give them help on both features and processors
...
llvm-svn: 23905
2005-10-23 22:23:13 +00:00
766361e8f4
Autogen subtarget information from .td files.
...
llvm-svn: 23904
2005-10-23 22:15:34 +00:00
4b5921d4d8
Add subtarget feature/processor defns to the .td file
...
llvm-svn: 23903
2005-10-23 22:08:45 +00:00
a389f0d8fa
rearrange things a bit so that instructions can use subtarget features in the
...
future.
llvm-svn: 23902
2005-10-23 22:08:13 +00:00
437fd559d7
add a marker
...
llvm-svn: 23901
2005-10-23 22:07:20 +00:00
b54070745e
add a note that Nate mentioned last week
...
llvm-svn: 23898
2005-10-23 21:44:59 +00:00
2e81fba9cd
Put some of my random notes somewhere public
...
llvm-svn: 23897
2005-10-23 19:52:42 +00:00
f64f8407c2
Improve help output.
...
llvm-svn: 23893
2005-10-23 05:33:39 +00:00
0d4923b975
improve -help output
...
llvm-svn: 23892
2005-10-23 05:28:51 +00:00
18a70c35b8
Move static functions from .h file, reduce #includes, pass strings by const&,
...
use LowercaseString from StringExtras.h, remove extraneous space from help
output.
llvm-svn: 23891
2005-10-23 05:26:26 +00:00
c6072af580
Add several things.
...
loads
branches
setcc
working calls
Global address
External addresses
now I can manage malloc calls.
llvm-svn: 23887
2005-10-23 03:43:48 +00:00
5a990417f8
Well, the Constant matching pattern works. Can't say much about calls or globals yet.
...
llvm-svn: 23884
2005-10-22 22:06:58 +00:00
42b3a5d596
This file is entirely ifdef'd out
...
llvm-svn: 23882
2005-10-22 19:37:08 +00:00
13a19453d2
Add g3 back to the mix and reorder to irritate them anal folk. Actually, it's
...
to group appropriately and provide cues to maintainers that the lists don't
need to be ordered.
llvm-svn: 23880
2005-10-22 08:04:24 +00:00
c5d511c4d9
64-bit reg support should not be enabled by default, as support isn't complete.
...
llvm-svn: 23878
2005-10-21 22:15:43 +00:00
e296949fbe
Instead of aborting if not a case we can handle specially, break out and
...
let the generic code handle it. This fixes CodeGen/Generic/2005-10-21-longlonggtu.ll on ppc.
also, reindent this code
llvm-svn: 23874
2005-10-21 21:17:10 +00:00
9ed9032e22
Plugin new subtarget backend into the build.
...
llvm-svn: 23870
2005-10-21 19:05:19 +00:00
229878b7bc
silence a release mode warning
...
llvm-svn: 23868
2005-10-21 16:01:26 +00:00
fd0d55ec69
Match rotate. This does actually match the rotates in an rc5 cipher, but I
...
haven't seen it fire on our testsuite.
llvm-svn: 23863
2005-10-21 06:36:18 +00:00
ae5d9bd65b
Don't generate operations that aren't yet supported
...
llvm-svn: 23858
2005-10-21 01:52:45 +00:00
62e9e5462c
Kill some now-dead code.
...
llvm-svn: 23857
2005-10-21 01:52:20 +00:00
a099c0131e
byte zap not immediate goodness
...
llvm-svn: 23855
2005-10-21 01:24:05 +00:00
Chris Lattner