36f06c80e6
Add promote operand support for [su]int_to_fp.
...
llvm-svn: 43204
2007-10-20 22:57:56 +00:00
2ba4b148f3
Add result promotion of FP_TO_*INT, fixing CodeGen/X86/trunc-to-bool.ll
...
with the new legalizer.
llvm-svn: 43199
2007-10-20 04:32:38 +00:00
1c87f0c620
simplify some code.
...
llvm-svn: 43198
2007-10-20 04:09:48 +00:00
2bcac640b7
Implement promote and expand for operands of memcpy and friends.
...
This fixes CodeGen/X86/mem*.ll.
llvm-svn: 43197
2007-10-20 04:07:07 +00:00
f12967124c
Added missing curly braces which renders the if clause useless in debug build.
...
llvm-svn: 43196
2007-10-20 04:01:47 +00:00
771188cf60
Fix a few places vector operations were not getting
...
the operand's type from the right place.
llvm-svn: 43195
2007-10-20 00:07:52 +00:00
35ff79370b
Local spiller optimization:
...
Turn a store folding instruction into a load folding instruction. e.g.
xorl %edi, %eax
movl %eax, -32(%ebp)
movl -36(%ebp), %eax
orl %eax, -32(%ebp)
=>
xorl %edi, %eax
orl -36(%ebp), %eax
mov %eax, -32(%ebp)
This enables the unfolding optimization for a subsequent instruction which will
also eliminate the newly introduced store instruction.
llvm-svn: 43192
2007-10-19 21:23:22 +00:00
ac5c93040f
Don't branch fold inline asm statements.
...
llvm-svn: 43191
2007-10-19 21:09:55 +00:00
a87c9e4b75
Add support for a few more nodes.
...
llvm-svn: 43190
2007-10-19 20:29:48 +00:00
6802d0c96f
Redo "last ppc long double fix" as Chris wants.
...
llvm-svn: 43189
2007-10-19 20:29:00 +00:00
064c31ebac
Fix a really nasty vector miscompilation bill recently introduced.
...
llvm-svn: 43181
2007-10-19 16:47:35 +00:00
3ea519e56d
rename ExpandOperation to ExpandOperationResult, as suggested
...
by Duncan
llvm-svn: 43177
2007-10-19 15:28:47 +00:00
a9953e4d0a
Support for expanding ADDE and SUBE.
...
llvm-svn: 43175
2007-10-19 13:06:17 +00:00
d9834b29dd
If the value types are equal then this routine
...
asserts in later checks rather than producing
the ordinary load it is supposed to. Avoid all
such hassles by directly returning an ordinary
load in this case.
llvm-svn: 43174
2007-10-19 13:05:40 +00:00
846c19dd70
Add support for byval function whose argument is not 32 bit aligned.
...
To do this it is necessary to add a "always inline" argument to the
memcpy node. For completeness I have also added this node to memmove
and memset. I have also added getMem* functions, because the extra
argument makes it cumbersome to use getNode and because I get confused
by it :-)
llvm-svn: 43172
2007-10-19 10:41:11 +00:00
e5a6448533
Implement a few new operations.
...
llvm-svn: 43171
2007-10-19 04:46:45 +00:00
e31365eecc
Implement expansion of SINT_TO_FP and UINT_TO_FP operands.
...
llvm-svn: 43170
2007-10-19 04:32:47 +00:00
9081d08083
implement support for custom expansion of any node type, in one place.
...
llvm-svn: 43169
2007-10-19 04:14:36 +00:00
d01b8ea4a5
Make use of TLI.ExpandOperation, remove softfloat stuff.
...
llvm-svn: 43167
2007-10-19 03:58:25 +00:00
3c7ee41c78
add expand support for bit_convert result, even allowing custom expansion.
...
llvm-svn: 43166
2007-10-19 03:33:14 +00:00
579db81f1c
add a new target hook.
...
llvm-svn: 43165
2007-10-19 03:31:45 +00:00
de16ad1446
Negative indices aren't allowed here.
...
llvm-svn: 43161
2007-10-19 01:10:49 +00:00
10432e5a67
More ppcf128 issues (maybe the last)?
...
llvm-svn: 43160
2007-10-19 00:59:18 +00:00
070aca5d25
Pointer arithmetic should be done with the index the same size as the pointer.
...
llvm-svn: 43120
2007-10-18 08:32:37 +00:00
cb7aca0dcb
Support for ADDC/SUBC.
...
llvm-svn: 43119
2007-10-18 08:22:16 +00:00
e6a41c066a
Really fix PR1734. Carefully track which register uses are sub-register uses by
...
traversing inverse register coalescing map.
llvm-svn: 43118
2007-10-18 07:49:59 +00:00
8f518b9875
Add support for ISD::SELECT in SplitVectorOp.
...
llvm-svn: 43072
2007-10-17 14:48:28 +00:00
d42c812f4a
Return Expand from getOperationAction for all extended
...
types. This is needed for SIGN_EXTEND_INREG at least.
It is not clear if this is correct for other operations.
On the other hand, for the various load/store actions
it seems to correct to return the type action, as is
currently done.
Also, it seems that SelectionDAG::getValueType can be
called for extended value types; introduce a map for
holding these, since we don't really want to extend
the vector to be 2^32 pointers long!
Generalize DAGTypeLegalizer::PromoteResult_TRUNCATE
and DAGTypeLegalizer::PromoteResult_INT_EXTEND to handle
the various funky possibilities that apints introduce,
for example that you can promote to a type that needs
to be expanded.
llvm-svn: 43071
2007-10-17 13:49:58 +00:00
0dde6e5761
Apply Chris' suggestions.
...
llvm-svn: 43069
2007-10-17 06:53:44 +00:00
c8b5397000
One more extract_subreg coalescing bug fix.
...
llvm-svn: 43065
2007-10-17 05:29:37 +00:00
9b0a44a2ce
Fix MergeValueInAsValue(). It allows overlapping live ranges but should replace
...
their value numbers with the specified value number.
llvm-svn: 43062
2007-10-17 02:13:29 +00:00
a6fd8bc97e
Clean up code that calculate MBB live-in's.
...
llvm-svn: 43061
2007-10-17 02:12:22 +00:00
8b8c7c9927
Clean up code that calculate MBB live-in's.
...
llvm-svn: 43060
2007-10-17 02:10:22 +00:00
e5facd51cb
Disable attempts to constant fold PPC f128.
...
Remove the assumption that this will happen from
various places.
llvm-svn: 43053
2007-10-16 23:38:29 +00:00
8f644cef0f
Some clean up.
...
llvm-svn: 43043
2007-10-16 21:09:14 +00:00
fab7ca89d5
Fix PR1734.
...
llvm-svn: 43035
2007-10-16 19:29:47 +00:00
bbbfbe95f7
Initial infrastructure for arbitrary precision integer
...
codegen support. This should have no effect on codegen
for other types. Debatable bits: (1) the use (abuse?)
of a set in SDNode::getValueTypeList; (2) the length of
getTypeToTransformTo, which maybe should be refactored
with a non-inline part for extended value types.
llvm-svn: 43030
2007-10-16 09:56:48 +00:00
052c843559
Fixes due to lack of type-safety for ValueType: (1) ValueType
...
being passed instead of an opcode; (2) ValueType being passed
for isVolatile (!) in getLoad.
llvm-svn: 43028
2007-10-16 09:07:20 +00:00
ecf62cb763
Code clean up.
...
llvm-svn: 43026
2007-10-16 08:04:24 +00:00
cece03dd89
implement promotion of select and select_cc, allowing MallocBench/gs to
...
work with type promotion on x86.
llvm-svn: 43025
2007-10-16 03:00:22 +00:00
9aa4fc5cd6
Teach IntrinsicLowering.cpp about the sin, cos, and pow intrinsics.
...
llvm-svn: 43020
2007-10-15 22:07:31 +00:00
04c44712d3
Make CalcLatency() non-recursive.
...
llvm-svn: 43017
2007-10-15 21:33:22 +00:00
a5abba65b6
Fix PR1729: watch out for val# with no def.
...
llvm-svn: 42996
2007-10-15 18:33:50 +00:00
d6f7d44eae
Move CreateStackTemporary out to SelectionDAG
...
llvm-svn: 42995
2007-10-15 17:48:57 +00:00
9eb7a829e6
add a new CreateStackTemporary helper method.
...
llvm-svn: 42994
2007-10-15 17:47:20 +00:00
9d5b131e70
implement promotion of BR_CC operands, fixing bisort on ppc.
...
llvm-svn: 42992
2007-10-15 17:16:12 +00:00
8555e69def
updates from duncan
...
llvm-svn: 42991
2007-10-15 16:46:29 +00:00
f6977d9842
Fix some typos. Call getTypeToTransformTo rather than
...
getTypeToExpandTo. The difference is that
getTypeToExpandTo gives the final result of expansion
(eg: i128 -> i32 on a 32 bit machine) while
getTypeToTransformTo does just one step (i128 -> i64).
llvm-svn: 42982
2007-10-15 13:30:18 +00:00
3cfb56d489
One mundane change: Change ReplaceAllUsesOfValueWith to *optionally*
...
take a deleted nodes vector, instead of requiring it.
One more significant change: Implement the start of a legalizer that
just works on types. This legalizer is designed to run before the
operation legalizer and ensure just that the input dag is transformed
into an output dag whose operand and result types are all legal, even
if the operations on those types are not.
This design/impl has the following advantages:
1. When finished, this will *significantly* reduce the amount of code in
LegalizeDAG.cpp. It will remove all the code related to promotion and
expansion as well as splitting and scalarizing vectors.
2. The new code is very simple, idiomatic, and modular: unlike
LegalizeDAG.cpp, it has no 3000 line long functions. :)
3. The implementation is completely iterative instead of recursive, good
for hacking on large dags without blowing out your stack.
4. The implementation updates nodes in place when possible instead of
deallocating and reallocating the entire graph that points to some
mutated node.
5. The code nicely separates out handling of operations with invalid
results from operations with invalid operands, making some cases
simpler and easier to understand.
6. The new -debug-only=legalize-types option is very very handy :),
allowing you to easily understand what legalize types is doing.
This is not yet done. Until the ifdef added to SelectionDAGISel.cpp is
enabled, this does nothing. However, this code is sufficient to legalize
all of the code in 186.crafty, olden and freebench on an x86 machine. The
biggest issues are:
1. Vectors aren't implemented at all yet
2. SoftFP is a mess, I need to talk to Evan about it.
3. No lowering to libcalls is implemented yet.
4. Various operations are missing etc.
5. There are FIXME's for stuff I hax0r'd out, like softfp.
Hey, at least it is a step in the right direction :). If you'd like to help,
just enable the #ifdef in SelectionDAGISel.cpp and compile code with it. If
this explodes it will tell you what needs to be implemented. Help is
certainly appreciated.
Once this goes in, we can do three things:
1. Add a new pass of dag combine between the "type legalizer" and "operation
legalizer" passes. This will let us catch some long-standing isel issues
that we miss because operation legalization often obfuscates the dag with
target-specific nodes.
2. We can rip out all of the type legalization code from LegalizeDAG.cpp,
making it much smaller and simpler. When that happens we can then
reimplement the core functionality left in it in a much more efficient and
non-recursive way.
3. Once the whole legalizer is non-recursive, we can implement whole-function
selectiondags maybe...
llvm-svn: 42981
2007-10-15 06:10:22 +00:00
b193517eed
One xform performed by LegalizeDAG is transformation of "store of fp" to "store of int".
...
Make two changes:
1) only xform "store of f32" if i32 is a legal type for the target.
2) only xform "store of f64" if either i64 or i32 are legal for the target.
3) if i64 isn't legal, manually lower to 2 stores of i32 instead of letting a
later pass of legalize do it. This is ugly, but helps future changes I'm
about to commit.
llvm-svn: 42980
2007-10-15 05:46:06 +00:00
90e0b271df
Add a (disabled by default) way to view the ID of a node.
...
llvm-svn: 42978
2007-10-15 05:32:43 +00:00
fbbe570994
remove misleading comment.
...
llvm-svn: 42970
2007-10-14 20:35:12 +00:00
ebe491ea9c
If a target doesn't have HasMULHU or HasUMUL_LOHI, ExpandOp would return
...
without lo/hi set. Fall through to making a libcall instead.
llvm-svn: 42969
2007-10-14 18:35:05 +00:00
8d6da9142c
When coalescing an EXTRACT_SUBREG and the dst register is a physical register,
...
the source register will be coalesced to the super register of the LHS. Properly
merge in the live ranges of the resulting coalesced interval that were part of
the original source interval to the live interval of the super-register.
llvm-svn: 42961
2007-10-14 10:08:34 +00:00
cdf3609130
Revert 42908 for now.
...
llvm-svn: 42960
2007-10-14 05:57:21 +00:00
19db093b35
Disable some compile-time optimizations on PPC
...
long double.
llvm-svn: 42958
2007-10-14 01:56:47 +00:00
f47e30627a
Enhance the truncstore optimization code to handle shifted
...
values and propagate demanded bits through them in simple cases.
This allows this code:
void foo(char *P) {
strcpy(P, "abc");
}
to compile to:
_foo:
ldrb r3, [r1]
ldrb r2, [r1, #+1]
ldrb r12, [r1, #+2]!
ldrb r1, [r1, #+1]
strb r1, [r0, #+3]
strb r2, [r0, #+1]
strb r12, [r0, #+2]
strb r3, [r0]
bx lr
instead of:
_foo:
ldrb r3, [r1, #+3]
ldrb r2, [r1, #+2]
orr r3, r2, r3, lsl #8
ldrb r2, [r1, #+1]
ldrb r1, [r1]
orr r2, r1, r2, lsl #8
orr r3, r2, r3, lsl #16
strb r3, [r0]
mov r2, r3, lsr #24
strb r2, [r0, #+3]
mov r2, r3, lsr #16
strb r2, [r0, #+2]
mov r3, r3, lsr #8
strb r3, [r0, #+1]
bx lr
testcase here: test/CodeGen/ARM/truncstore-dag-combine.ll
This also helps occasionally for X86 and other cases not involving
unaligned load/stores.
llvm-svn: 42954
2007-10-13 06:58:48 +00:00
5e6fe054a2
Add a simple optimization to simplify the input to
...
truncate and truncstore instructions, based on the
knowledge that they don't demand the top bits.
llvm-svn: 42952
2007-10-13 06:35:54 +00:00
b63076504e
Local spiller optimization:
...
Turn this:
movswl %ax, %eax
movl %eax, -36(%ebp)
xorl %edi, -36(%ebp)
into
movswl %ax, %eax
xorl %edi, %eax
movl %eax, -36(%ebp)
by unfolding the load / store xorl into an xorl and a store when we know the
value in the spill slot is available in a register. This doesn't change the
number of instructions but reduce the number of times memory is accessed.
Also unfold some load folding instructions and reuse the value when similar
situation presents itself.
llvm-svn: 42947
2007-10-13 02:50:24 +00:00
9490e0d078
Optionally create a MachineInstr without default implicit operands.
...
llvm-svn: 42945
2007-10-13 02:23:01 +00:00
1f0da1fefb
Corrected many typing errors. And removed 'nest' parameter handling
...
for fastcc from X86CallingConv.td. This means that nested functions
are not supported for calling convention 'fastcc'.
llvm-svn: 42934
2007-10-12 21:30:57 +00:00
61c574fc51
ppc long double. Implement fabs and fneg.
...
llvm-svn: 42924
2007-10-12 19:02:17 +00:00
a1a4a9ebfa
Implement i64->ppcf128 conversions.
...
llvm-svn: 42919
2007-10-12 17:52:03 +00:00
1410b8512c
Did mean to leave this in. INSERT_SUBREG isn't being coalesced yet.
...
llvm-svn: 42916
2007-10-12 17:16:50 +00:00
dc35bd79ca
Change the names used for internal labels to use the current
...
function symbol name instead of a codegen-assigned function
number.
Thanks Evan! :-)
llvm-svn: 42908
2007-10-12 14:53:36 +00:00
e3583817ac
Fix some corner cases with vectors in copyToRegs and copyFromRegs.
...
llvm-svn: 42907
2007-10-12 14:33:11 +00:00
4f056f3c10
Add support to SplitVectorOp for powi, where the second operand
...
is a scalar integer.
llvm-svn: 42906
2007-10-12 14:13:46 +00:00
11330f7526
Restrict EXTRACT_SUBREG coalescing to avoid negative performance impact.
...
llvm-svn: 42903
2007-10-12 09:15:53 +00:00
aa2d6ef81d
EXTRACT_SUBREG coalescing support. The coalescer now treats EXTRACT_SUBREG like
...
(almost) a register copy. However, it always coalesced to the register of the
RHS (the super-register). All uses of the result of a EXTRACT_SUBREG are sub-
register uses which adds subtle complications to load folding, spiller rewrite,
etc.
llvm-svn: 42899
2007-10-12 08:50:34 +00:00
89d5916921
Some clean up.
...
llvm-svn: 42898
2007-10-12 08:45:27 +00:00
05ff9e8cda
PPC long double. Implement a couple more conversions.
...
llvm-svn: 42888
2007-10-12 01:37:08 +00:00
be37007e64
Add intrinsics for sin, cos, and pow. These use llvm_anyfloat_ty, and so
...
may be overloaded with vector types. And add a testcase for codegen for
these.
llvm-svn: 42885
2007-10-12 00:01:22 +00:00
2a7de41682
Codegen support for vector intrinsics.
...
Factor out the code that expands the "nasty scalar code" for unrolling
vectors into a separate routine, teach it how to handle mixed
vector/scalar operands, as seen in powi, and use it for several operators,
including sin, cos, powi, and pow.
Add support in SplitVectorOp for fpow, fpowi and for several unary
operators.
llvm-svn: 42884
2007-10-11 23:57:53 +00:00
6472eb63c2
Implement ppc long double->uint conversion.
...
Make ppc long double constants print.
llvm-svn: 42882
2007-10-11 23:32:15 +00:00
fd66486950
Add runtime library names for pow.
...
llvm-svn: 42880
2007-10-11 23:09:10 +00:00
daee002438
Add an ISD::FPOW node type.
...
llvm-svn: 42879
2007-10-11 23:06:37 +00:00
9ccea99165
Added tail call optimization to the x86 back end. It can be
...
enabled by passing -tailcallopt to llc. The optimization is
performed if the following conditions are satisfied:
* caller/callee are fastcc
* elf/pic is disabled OR
elf/pic enabled + callee is in module + callee has
visibility protected or hidden
llvm-svn: 42870
2007-10-11 19:40:01 +00:00
007aa378ad
Next PPC long double bits. First cut at constants.
...
No compile-time support for constant operations yet,
just format transformations. Make readers and
writers work. Split constants into 2 doubles in
Legalize.
llvm-svn: 42865
2007-10-11 18:07:22 +00:00
56ab90d3ad
Correct swapped arguments to getConstant.
...
llvm-svn: 42824
2007-10-10 09:54:50 +00:00
666323eacd
Next PPC long double bits: ppcf128->i32 conversion.
...
Surprisingly complicated.
Adds getTargetNode for 2 outputs, no inputs (missing).
llvm-svn: 42822
2007-10-10 01:01:31 +00:00
a9830a04eb
Bad choice of variable name.
...
llvm-svn: 42821
2007-10-10 00:11:40 +00:00
ad55a6079a
Fix an extremely stupid bug that prevented first round of coalescing (physical registers only) from happening.
...
llvm-svn: 42820
2007-10-09 23:36:27 +00:00
5942e5a5fb
Call getFunctionNumber() instead of referencing FunctionNumber directly,
...
for consistency.
llvm-svn: 42769
2007-10-08 21:27:12 +00:00
a160361c85
Migrate X86 and ARM from using X86ISD::{,I}DIV and ARMISD::MULHILO{U,S} to
...
use ISD::{S,U}DIVREM and ISD::{S,U}MUL_HIO. Move the lowering code
associated with these operators into target-independent in LegalizeDAG.cpp
and TargetLowering.cpp.
llvm-svn: 42762
2007-10-08 18:33:35 +00:00
5c6d0c3b99
DAGCombiner support for UDIVREM/SDIVREM and UMUL_LOHI/SMUL_LOHI.
...
Check if one of the two results unneeded so see if a simpler operator
could bs used. Also check to see if each of the two computations could be
simplified if they were split into separate operators. Factor out the code
that calls visit() so that it can be used for this purpose.
llvm-svn: 42759
2007-10-08 17:57:15 +00:00
b08c8bfe41
Add convenience overloads of SelectionDAG::getNode that take a SDVTList
...
and individual SDOperand operands.
llvm-svn: 42753
2007-10-08 15:49:58 +00:00
fadf40a655
In -debug mode, dump SelectionDAGs both before and after the
...
optimization passes.
llvm-svn: 42749
2007-10-08 15:12:17 +00:00
21a58a72c5
Kill cycle of an live range is always the last use index + 1.
...
llvm-svn: 42742
2007-10-08 06:59:30 +00:00
5f00973393
convertFromInteger, as originally written, expected sign-extended
...
input. APInt unfortunately zero-extends signed integers, so Dale
modified the function to expect zero-extended input. Make this
assumption explicit in the function name.
llvm-svn: 42732
2007-10-07 11:45:55 +00:00
0de312dd7d
Reapply 42677.
...
llvm-svn: 42692
2007-10-06 08:19:55 +00:00
82217bd155
revert evan's patch until the header is committed
...
llvm-svn: 42686
2007-10-06 06:08:17 +00:00
f4b5d491df
Added DAG xforms. e.g.
...
(vextract (v4f32 s2v (f32 load $addr)), 0) -> (f32 load $addr)
(vextract (v4i32 bc (v4f32 s2v (f32 load $addr))), 0) -> (i32 load $addr)
Remove x86 specific patterns.
llvm-svn: 42677
2007-10-06 02:46:29 +00:00
f864ac96d8
Next powerpc long double bits. Comparisons work,
...
although not well, and shortening FP converts.
llvm-svn: 42672
2007-10-06 01:24:11 +00:00
c0154c06d6
First round of ppc long double. call/return and
...
basic arithmetic works.
Rename RTLIB long double functions to distinguish
different flavors of long double; the lib functions
have different names, alas.
llvm-svn: 42644
2007-10-05 20:04:43 +00:00
12334acbfb
Legalize support for MUL_LOHI and DIVREM.
...
llvm-svn: 42636
2007-10-05 14:17:22 +00:00
2682bb6df2
Fix a typo in a comment.
...
llvm-svn: 42635
2007-10-05 14:11:58 +00:00
1a77dfba15
Provide names for MUL_LOHI and DIVREM operators.
...
llvm-svn: 42634
2007-10-05 14:11:04 +00:00
84d0ebc10a
Chain producing nodes cannot be moved, not chain reading nodes.
...
llvm-svn: 42627
2007-10-05 01:42:35 +00:00
991cf47221
Oops. Didn't mean to leave this in.
...
llvm-svn: 42626
2007-10-05 01:39:40 +00:00
79e9713b11
If a node that defines a physical register that is expensive to copy. The
...
scheduler will try a number of tricks in order to avoid generating the
copies. This may not be possible in case the node produces a chain value
that prevent movement. Try unfolding the load from the node before to allow
it to be moved / cloned.
llvm-svn: 42625
2007-10-05 01:39:18 +00:00
4852303bdb
Add a variant of getTargetNode() that takes a vector of MVT::ValueType.
...
llvm-svn: 42620
2007-10-05 01:10:49 +00:00
fd11ef4665
Silence a warning.
...
llvm-svn: 42619
2007-10-05 01:09:32 +00:00
c731c97fac
Use empty() member functions when that's what's being tested for instead
...
of comparing begin() and end().
llvm-svn: 42585
2007-10-03 19:26:29 +00:00
4d4e77af8e
Rewrite sqrt and powi to use anyfloat. By popular demand.
...
llvm-svn: 42537
2007-10-02 17:43:59 +00:00
b6c05b1f90
Fix stride computations for long double arrays.
...
llvm-svn: 42508
2007-10-01 23:08:35 +00:00
9765cc3bbb
Move the code that emits the .file directives so that it runs after the
...
SourceFiles list is fully filled in so that it sees all of the files.
llvm-svn: 42506
2007-10-01 22:40:20 +00:00
a3a67596f6
Remove simple scheduler.
...
llvm-svn: 42499
2007-10-01 20:44:07 +00:00
c0855f8a88
remove dup comment
...
llvm-svn: 42486
2007-09-30 19:08:12 +00:00
9150652b21
Constant fold int-to-long-double conversions;
...
use APFloat for int-to-float/double; use
round-to-nearest for these (implementation-defined,
seems to match gcc).
llvm-svn: 42484
2007-09-30 18:19:03 +00:00
f5aa229ede
This is done already.
...
llvm-svn: 42467
2007-09-29 02:23:08 +00:00
37ca83d4e9
Collector is the base class for garbage collection code generators.
...
This version enhances the previous patch to add root initialization
as discussed here:
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20070910/053455.html
Collector gives its subclasses control over generic algorithms:
unsigned NeededSafePoints; //< Bitmask of required safe points.
bool CustomReadBarriers; //< Default is to insert loads.
bool CustomWriteBarriers; //< Default is to insert stores.
bool CustomRoots; //< Default is to pass through to backend.
bool InitRoots; //< If set, roots are nulled during lowering.
It also has callbacks which collectors can hook:
/// If any of the actions are set to Custom, this is expected to
/// be overriden to create a transform to lower those actions to
/// LLVM IR.
virtual Pass *createCustomLoweringPass() const;
/// beginAssembly/finishAssembly - Emit module metadata as
/// assembly code.
virtual void beginAssembly(Module &M, std::ostream &OS,
AsmPrinter &AP,
const TargetAsmInfo &TAI) const;
virtual void finishAssembly(Module &M,
CollectorModuleMetadata &CMM,
std::ostream &OS, AsmPrinter &AP,
const TargetAsmInfo &TAI) const;
Various other independent algorithms could be implemented, but were
not necessary for the initial two collectors. Some examples are
listed here:
http://llvm.org/docs/GarbageCollection.html#collector-algos
llvm-svn: 42466
2007-09-29 02:13:43 +00:00
a90183e7d1
Teach SplitVectorOp how to split INSERT_VECTOR_ELT.
...
llvm-svn: 42457
2007-09-28 23:53:40 +00:00
a5e595d23a
If two instructions are both two-address code, favors (schedule closer to
...
terminator) the one that has a CopyToReg use. This fixes
2006-05-11-InstrSched.ll with -new-cc-modeling-scheme.
llvm-svn: 42453
2007-09-28 22:32:30 +00:00
f72693f36e
Remove a poor scheduling heuristic.
...
llvm-svn: 42443
2007-09-28 19:37:35 +00:00
038dcc5136
Trim some unneeded fields.
...
llvm-svn: 42442
2007-09-28 19:24:24 +00:00
789b5a505b
Fix long double -> uint64 conversion.
...
llvm-svn: 42440
2007-09-28 18:44:17 +00:00
6bf69ed3cc
minor long double related changes
...
llvm-svn: 42439
2007-09-28 18:06:58 +00:00
25d506c41b
Make the checks for DW_FORM_data4 consistent with the others, and
...
add more such code for DIEDwarfLabel::SizeOf and DIEObjectLabel::SizeOf.
llvm-svn: 42435
2007-09-28 16:50:28 +00:00
0d23d63b9e
Use 32-bit data directives for DW_FORM_data4 format data, even on
...
targets with 64-bit addresses.
llvm-svn: 42434
2007-09-28 15:43:33 +00:00
25a00a63eb
Add sqrt and powi intrinsics for long double.
...
llvm-svn: 42423
2007-09-28 01:08:20 +00:00
a1d46c7d0a
TargetAsmInfo::getAddressSize() was incorrect for x86-64 and 64-bit targets
...
other than PPC64. Instead of fixing it, just remove it and fix all the
places that use it to use TargetData::getPointerSize() instead, as there
aren't very many. Most of the references were in DwarfWriter.cpp.
llvm-svn: 42419
2007-09-27 23:12:31 +00:00
613afce430
CollectorMetadata abstractly describes stack maps for a function.
...
It includes:
- location and of each safe point in machine code (identified by a
label)
- location of each root within the stack frame (identified by an
offset), including the metadata tag provided to llvm.gcroot in
the user program
- size of the stack frame (for collectors which want to cheat on
stack crawling :)
- and eventually will include liveness
It is to be populated by back-ends during code-generation.
CollectorModuleMetadata aggregates this information across the
entire module.
llvm-svn: 42418
2007-09-27 22:18:46 +00:00
658c57eb66
My previous Registry.h header, as well as Collectors.h, which is the
...
registry for dynamically-loaded garbage collection compiler plugins.
llvm-svn: 42415
2007-09-27 19:34:27 +00:00
e6f92253f5
Avoid inserting a live register more than once.
...
llvm-svn: 42410
2007-09-27 18:46:06 +00:00
75439b3b78
Silence a compiler warning.
...
llvm-svn: 42389
2007-09-27 07:35:39 +00:00
bde499be60
Boogs.
...
llvm-svn: 42388
2007-09-27 07:29:27 +00:00
1ec79b41db
Be smarter about which node to force schedule. Reduce # of duplications + copies; Added statistics.
...
llvm-svn: 42387
2007-09-27 07:09:03 +00:00
cfd5f82890
Backtracking only when it won't create a cycle.
...
llvm-svn: 42384
2007-09-27 00:25:29 +00:00
34aa41c475
Make temporaries explicit to avoid premature
...
destruction of compiler-created ones.
llvm-svn: 42383
2007-09-26 23:20:33 +00:00
8e136a9dc4
- Move getPhysicalRegisterRegClass() from ScheduleDAG to MRegisterInfo.
...
- Added ability to emit cross class register copies to the BBRU scheduler.
- More aggressive backtracking.
llvm-svn: 42375
2007-09-26 21:36:17 +00:00
b6d56401aa
Enable codegen for long double abs, sin, cos
...
llvm-svn: 42368
2007-09-26 21:10:55 +00:00
f04d37d3a9
Fix f80 UNDEF.
...
llvm-svn: 42359
2007-09-26 17:26:49 +00:00
c1e4e3743b
Allow copyRegToReg to emit cross register classes copies.
...
Tested with "make check"!
llvm-svn: 42346
2007-09-26 06:25:56 +00:00
5e1a428344
Move the setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand) and
...
the check to see if the assembler supports .loc from X86TargetLowering
into the superclass TargetLowering.
llvm-svn: 42297
2007-09-25 15:10:49 +00:00
5924bf7d3b
Added major new capabilities to scheduler (only BURR for now) to support physical register dependency. The BURR scheduler can now backtrace and duplicate instructions in order to avoid "expensive / impossible to copy" values (e.g. status flag EFLAGS for x86) from being clobbered.
...
llvm-svn: 42284
2007-09-25 01:54:36 +00:00
3165699e4b
Don't emit .debug_line header data if there aren't any lines to put in it,
...
such as will happen when .loc directives are used.
llvm-svn: 42277
2007-09-24 21:43:52 +00:00
9b00c07be5
Move the Asm->EOL() call for EmitDebugARanges outside the #ifdef for
...
consistency with the other currently empty sections.
llvm-svn: 42276
2007-09-24 21:36:21 +00:00
0baf84b2e1
Add support for emitting .file directives to set up file numbers for
...
use with .loc directives.
llvm-svn: 42275
2007-09-24 21:32:18 +00:00
bd8331da87
Add a routine for emitting .file directives, for setting up
...
file numbers to use with .loc directives.
llvm-svn: 42272
2007-09-24 20:58:13 +00:00
6002818999
Use the correct result value type instead of using getValueType(0)
...
in ExpandEXTRACT_VECTOR_ELT and SplitVectorOp. This fixes an abort
in the included testcase.
llvm-svn: 42264
2007-09-24 15:54:53 +00:00
7d98b23f1a
When emitting .set directives, make sure the EH and Debug labels can't conflict.
...
llvm-svn: 42257
2007-09-24 03:35:37 +00:00
10671ad650
initialize isstore/isload fields in ctor, fixing PR1695
...
llvm-svn: 42222
2007-09-22 07:02:12 +00:00
4230512f32
Change APFloat::convertFromInteger to take the incoming
...
bit width instead of number of words allocated, which
makes it actually work for int->APF conversions.
Adjust callers. Add const to one of the APInt constructors
to prevent surprising match when called with const
argument.
llvm-svn: 42210
2007-09-21 22:09:37 +00:00
51ce795c92
don't read Block after it is freed. This fixes PR1684
...
llvm-svn: 42204
2007-09-21 18:25:53 +00:00
b3d01d2f56
initialize SetCCResultContents, fixing PR1693
...
llvm-svn: 42193
2007-09-21 17:06:39 +00:00
7d67e547b5
More long double fixes. x86_64 should build now.
...
llvm-svn: 42155
2007-09-19 23:55:34 +00:00
b59d25fe54
Fix longdouble -> uint conversion.
...
llvm-svn: 42143
2007-09-19 17:53:26 +00:00
0effc3a6b8
Use struct SDep instead of std::pair for SUnit pred and succ lists. First step
...
in tracking physical register output dependencies.
llvm-svn: 42125
2007-09-19 01:38:40 +00:00
e2e8f2d96b
Fix a bogus splat xform:
...
shuffle <undef, undef, x, undef>, <undef, undef, undef, undef>, <2, 2, 2, 2>
!=
<undef, undef, x, undef>
llvm-svn: 42111
2007-09-18 21:54:37 +00:00
af12b57405
Prevent crash on long double.
...
llvm-svn: 42103
2007-09-18 18:36:59 +00:00
e8c885f261
Don't pass back a reference to a temporary.
...
llvm-svn: 42086
2007-09-18 09:10:16 +00:00
69833b61ac
The exception handling function info should be reset for each new
...
function. The information isn't used heavily -- it's only used at the end
of exception handling emission -- so there's no need to cache it.
llvm-svn: 42078
2007-09-18 05:03:44 +00:00
067f1d8e95
Objective-C was generating EH frame info like this:
...
"_-[NSString(local) isNullOrNil]".eh = 0
.no_dead_strip "_-[NSString(local) isNullOrNil]".eh
The ".eh" should be inside the quotes.
llvm-svn: 42074
2007-09-18 01:47:22 +00:00
00064e1bab
Do not hide APInt::dump() inside #ifndef NDEBUG.
...
llvm-svn: 42068
2007-09-17 22:24:00 +00:00
77ae4d358f
This is not ideal but unbreaks build failure.
...
APInt::dump() is inside #ifndef NDEBUG, however SelectionDAG dump() routines are not.
llvm-svn: 42047
2007-09-17 20:03:03 +00:00
0625bd6472
Merge DenseMapKeyInfo & DenseMapValueInfo into DenseMapInfo
...
Add a new DenseMapInfo::isEqual method to allow clients to redefine
the equality predicate used when probing the hash table.
llvm-svn: 42042
2007-09-17 18:34:04 +00:00
7f724e9b94
Adjust per revew comments.
...
llvm-svn: 42002
2007-09-16 16:51:49 +00:00
98d3a08d8f
Remove the assumption that FP's are either float or
...
double from some of the many places in the optimizers
it appears, and do something reasonable with x86
long double.
Make APInt::dump() public, remove newline, use it to
dump ConstantSDNode's.
Allow APFloats in FoldingSet.
Expand X86 backend handling of long doubles (conversions
to/from int, mostly).
llvm-svn: 41967
2007-09-14 22:26:36 +00:00
9da02f5ee2
Remove isReg, isImm, and isMBB, and change all their users to use
...
isRegister, isImmediate, and isMachineBasicBlock, which are equivalent,
and more popular.
llvm-svn: 41958
2007-09-14 20:33:02 +00:00
58c468fb09
Remove spurious consts. This fixes warnings with compilers that
...
are strict about such things.
llvm-svn: 41956
2007-09-14 20:08:19 +00:00
7955bbd9fd
Fix build problems on Cygwin (PR1652), patch by Patrick Walton.
...
llvm-svn: 41923
2007-09-13 06:09:48 +00:00
100c8d6c8f
Bug fixes.
...
llvm-svn: 41900
2007-09-13 00:06:00 +00:00
57ff158255
Remove dead code.
...
llvm-svn: 41899
2007-09-12 23:45:46 +00:00
bb6a574def
Yet another getTargetNode variant.
...
llvm-svn: 41898
2007-09-12 23:39:49 +00:00
d8317967aa
Fixed a typo that's causing a missing kill marker.
...
llvm-svn: 41893
2007-09-12 23:02:04 +00:00
028084efe5
Revise previous patch per review comments.
...
Next round of x87 long double stuff.
Getting close now, basically works.
llvm-svn: 41875
2007-09-12 03:30:33 +00:00
c16847b157
Sometimes a MI can define a register as well as defining a super-register at the
...
same time. Do not mark the "smaller" def as dead.
llvm-svn: 41871
2007-09-11 22:34:47 +00:00
245dceb06d
Add APInt interfaces to APFloat (allows directly
...
access to bits). Use them in place of float and
double interfaces where appropriate.
First bits of x86 long double constants handling
(untested, probably does not work).
llvm-svn: 41858
2007-09-11 18:32:33 +00:00
74fb0f1a1c
Add a bool to indicate if we should set the "indirect encoding" bit in the Dwarf
...
information for EH.
llvm-svn: 41852
2007-09-11 17:20:55 +00:00
86e0119822
Fold the adjust_trampoline intrinsic into
...
init_trampoline. There is now only one
trampoline intrinsic.
llvm-svn: 41841
2007-09-11 14:10:23 +00:00
2b8fc31df9
The personality function on Darwin needs a global stub. We then refer to
...
that global stub instead of doing the ".set" thingy we were doing before.
llvm-svn: 41838
2007-09-11 08:27:17 +00:00
3b9f777f47
Observation of rematerialization.
...
llvm-svn: 41809
2007-09-10 22:11:18 +00:00
58c227bd09
Emit:
...
cmpl %eax, %ecx
setae %al
movzbl %al, %eax
instead of:
cmpl %eax, %ecx
setb %al
xorb $1, %al
movzbl %al, %eax
when using logical not of a C comparison.
llvm-svn: 41807
2007-09-10 21:39:07 +00:00
33a7f51412
1. Don't call Value::getName(), which is slow.
...
2. Lower calls to fabs and friends to FABS nodes etc unless the function has
internal linkage. Before we wouldn't lower if it had a definition, which
is incorrect. This allows us to compile:
define double @fabs(double %f) {
%tmp2 = tail call double @fabs( double %f )
ret double %tmp2
}
into:
_fabs:
fabs f1, f1
blr
llvm-svn: 41805
2007-09-10 21:15:22 +00:00
29e6ac4281
Implement misaligned FP loads and stores.
...
llvm-svn: 41786
2007-09-08 19:29:23 +00:00
1de0c86717
Add support for having different alignment for objects on call frames.
...
The x86-64 ABI states that objects passed on the stack have
8 byte alignment. Implement that.
llvm-svn: 41768
2007-09-07 14:52:14 +00:00
122bf4be7e
Split eh.select / eh.typeid.for intrinsics into i32/i64 versions. This is needed, because they just "mark" register
...
liveins and we let frontend solve type issue, not lowering code :)
llvm-svn: 41763
2007-09-07 11:39:35 +00:00
e2f23a3abf
Add lengthof and endof templates that hide a lot of sizeof computations.
...
Patch by Sterling Stein!
llvm-svn: 41758
2007-09-07 04:06:50 +00:00
517d5d8ebe
Constify to catch bugs.
...
llvm-svn: 41751
2007-09-06 19:46:46 +00:00
bed9dc423c
Next round of APFloat changes.
...
Use APFloat in UpgradeParser and AsmParser.
Change all references to ConstantFP to use the
APFloat interface rather than double. Remove
the ConstantFP double interfaces.
Use APFloat functions for constant folding arithmetic
and comparisons.
(There are still way too many places APFloat is
just a wrapper around host float/double, but we're
getting there.)
llvm-svn: 41747
2007-09-06 18:13:44 +00:00
a07765b8f4
Proper handle case, when aliasee is external weak symbol referenced only by alias itself.
...
Also, fix a case, when target doesn't have weak symbols supported.
llvm-svn: 41746
2007-09-06 17:21:48 +00:00
a6d5d2a6a0
Add instruction dump output. This helps find bugs.
...
llvm-svn: 41744
2007-09-06 16:36:39 +00:00
65d2a697dc
Pluggable coalescers inplementation.
...
llvm-svn: 41743
2007-09-06 16:18:45 +00:00
d059eed1c1
Fix a memory leak.
...
llvm-svn: 41739
2007-09-06 01:07:24 +00:00
db53aef53e
Use pool allocator for all the VNInfo's to improve memory access locality. This reduces coalescing time on siod Mac OS X PPC by 35%. Also remove the back ptr from VNInfo to LiveInterval and other tweaks.
...
llvm-svn: 41729
2007-09-05 21:46:51 +00:00
2c0a0fb725
Due to label merging, the last label for an invoke
...
may be the same as the first label for the following
invoke. Remove a micro-optimization which was wrong
in this case.
llvm-svn: 41720
2007-09-05 14:12:46 +00:00
3c1b7fc056
Fix PR1628. When exception handling is turned on,
...
labels are generated bracketing each call (not just
invokes). This is used to generate entries in
the exception table required by the C++ personality.
However it gets in the way of tail-merging. This
patch solves the problem by no longer placing labels
around ordinary calls. Instead we generate entries
in the exception table that cover every instruction
in the function that wasn't covered by an invoke
range (the range given by the labels around the invoke).
As an optimization, such entries are only generated for
parts of the function that contain a call, since for
the moment those are the only instructions that can
throw an exception [1]. As a happy consequence, we
now get a smaller exception table, since the same
region can cover many calls. While there, I also
implemented folding of invoke ranges - successive
ranges are merged when safe to do so. Finally, if
a selector contains only a cleanup, there's a special
shorthand for it - place a 0 in the call-site entry.
I implemented this while there. As a result, the
exception table output (excluding filters) is now
optimal - it cannot be made smaller [2]. The
problem with throw filters is that folding them
optimally is hard, and the benefit of folding them is
minimal.
[1] I tested that having trapping instructions (eg
divide by zero) in such a region doesn't cause trouble.
[2] It could be made smaller with the help of higher
layers, eg by having branch folding reorder basic blocks
ending in invokes with the same landing pad so they
follow each other. I don't know if this is worth doing.
llvm-svn: 41718
2007-09-05 11:27:52 +00:00
e0cb6bb8da
Fix for PR1632. EHSELECTION always produces a i32 value.
...
llvm-svn: 41712
2007-09-04 20:39:26 +00:00
35322d745c
Silence warning while compiling with gcc 4.2
...
llvm-svn: 41676
2007-09-02 22:11:14 +00:00
38ce90fd44
Emit proper "secrel" directive, where possible. This fixes invalid asm syntax of debug info on mingw32. Also, cleanup
...
some stuff.
llvm-svn: 41675
2007-09-02 22:07:21 +00:00
2089a21360
More tweaks to improve compile time.
...
llvm-svn: 41669
2007-09-01 02:03:17 +00:00
446b900192
Add mod, copysign, abs operations to APFloat.
...
Implement some constant folding in SelectionDAG and
DAGCombiner using APFloat. Remove double versions
of constructor and getValue from ConstantFPSDNode.
llvm-svn: 41664
2007-08-31 23:34:27 +00:00
7bef79a1c3
std::map -> DenseMap for slight compile time benefit.
...
llvm-svn: 41650
2007-08-31 21:23:06 +00:00
da7469f2b5
Revise per review of previous patch.
...
llvm-svn: 41645
2007-08-31 17:03:33 +00:00
91becf4ffa
Remove an unnecessary element, saving 4 bytes per LiveInterval.
...
llvm-svn: 41641
2007-08-31 08:26:44 +00:00
262596e76a
Use std::map instead of a (potentially very sparse) array to track val# defined by copy from the other live range. Minor compile time win when number of val# is large.
...
llvm-svn: 41640
2007-08-31 08:04:17 +00:00
3cf889f75e
Enhance APFloat to retain bits of NaNs (fixes oggenc).
...
Use APFloat interfaces for more references, mostly
of ConstantFPSDNode.
llvm-svn: 41632
2007-08-31 04:03:46 +00:00
32a0a995c6
Try fold re-materialized load instructions into its uses.
...
llvm-svn: 41598
2007-08-30 05:53:02 +00:00
d246b2ca5c
Change LegalFPImmediates to use APFloat.
...
Add APFloat interfaces to ConstantFP, SelectionDAG.
Fix integer bit in double->APFloat conversion.
Convert LegalizeDAG to use APFloat interface in
ConstantFPSDNode uses.
llvm-svn: 41587
2007-08-30 00:23:21 +00:00
2bdec2a5ee
Fix use of declaration inside case block
...
llvm-svn: 41584
2007-08-29 23:18:48 +00:00
1ad4a6117b
Change LiveRange so it keeps a pointer to the VNInfo rather than an index.
...
Changes related modules so VNInfo's are not copied. This decrease
copy coalescing time by 45% and overall compilation time by 10% on siod.
llvm-svn: 41579
2007-08-29 20:45:00 +00:00
830b1cb4e9
Lower FRAME_TO_ADDR_OFFSET to zero by default (if not custom lowered)
...
llvm-svn: 41578
2007-08-29 19:28:29 +00:00
81b62e1218
Add an option, -view-sunit-dags, for viewing the actual SUnit DAGs used by
...
scheduling.
llvm-svn: 41556
2007-08-28 20:32:58 +00:00
a5b10b334f
Recover most of the compile time regression due to recent live interval changes.
...
1. Eliminate the costly live interval "swapping".
2. Change ValueNumberInfo container from SmallVector to std::vector. The former
performs slowly when the vector size is very large.
llvm-svn: 41536
2007-08-28 08:28:51 +00:00
9625d812c9
Make DAGCombiner's global alias analysis query more precise in the case
...
where both pointers have non-zero offsets.
llvm-svn: 41491
2007-08-27 16:32:11 +00:00
8dc0b93151
If the source and destination pointers in an llvm.memmove are known
...
to not alias each other, it can be translated as an llvm.memcpy.
llvm-svn: 41489
2007-08-27 16:26:13 +00:00
ef5a654216
There is an impedance matching problem between LLVM and
...
gcc exception handling: if an exception unwinds through
an invoke, then execution must branch to the invoke's
unwind target. We previously tried to enforce this by
appending a cleanup action to every selector, however
this does not always work correctly due to an optimization
in the C++ unwinding runtime: if only cleanups would be
run while unwinding an exception, then the program just
terminates without actually executing the cleanups, as
invoke semantics would require. I was hoping this
wouldn't be a problem, but in fact it turns out to be the
cause of all the remaining failures in the LLVM testsuite
(these also fail with -enable-correct-eh-support, so turning
on -enable-eh didn't make things worse!). Instead we need
to append a full-blown catch-all to the end of each
selector. The correct way of doing this depends on the
personality function, i.e. it is language dependent, so
can only be done by gcc. Thus this patch which generalizes
the eh.selector intrinsic so that it can handle all possible
kinds of action table entries (before it didn't accomodate
cleanups): now 0 indicates a cleanup, and filters have to be
specified using the number of type infos plus one rather than
the number of type infos. Related gcc patches will cause
Ada to pass a cleanup (0) to force the selector to always
fire, while C++ will use a C++ catch-all (null).
llvm-svn: 41484
2007-08-27 15:47:50 +00:00
032d89828e
Add explicit keywords and remove spurious trailing semicolons.
...
llvm-svn: 41482
2007-08-27 14:50:10 +00:00
b6d2bec418
Revise per review comments.
...
llvm-svn: 41409
2007-08-26 01:18:27 +00:00
2cfcf70f82
Add APFloat interface to ConstantFPSDNode. Change
...
over uses in DAGCombiner. Fix interfaces to work
with APFloats.
llvm-svn: 41407
2007-08-25 22:10:57 +00:00
2ed652f11d
Allow target constants to be illegal types. The target should
...
know how to handle them. This fixes
test/CodeGen/Generic/asm-large-immediate.ll
llvm-svn: 41388
2007-08-25 01:00:22 +00:00
dbfc4e4b07
Teach the dag scheduler to handle inline asm nodes with multi-value immediate operands.
...
llvm-svn: 41386
2007-08-25 00:53:07 +00:00
48597b4ff8
The personality function might need to be declared as:
...
.set Lset0,___gxx_personality_v0-.
.long Lset0
on some targets. Make it so!
llvm-svn: 41385
2007-08-25 00:51:55 +00:00
d8c9cb9182
rename isOperandValidForConstraint to LowerAsmOperandForConstraint,
...
changing the interface to allow for future changes.
llvm-svn: 41384
2007-08-25 00:47:38 +00:00
bdea32d812
Poison APFloat::operator==. Replace existing uses with bitwiseIsEqual.
...
This means backing out the preceding change to Constants.cpp, alas.
llvm-svn: 41378
2007-08-24 22:09:56 +00:00
7891d8edf0
Use APFloat internally for ConstantFPSDNode.
...
llvm-svn: 41372
2007-08-24 20:59:15 +00:00
97cdac8d19
Perform correct codegen for eh_dwarf_cfa intrinsic.
...
llvm-svn: 41316
2007-08-23 07:21:06 +00:00
beb80a9832
move this check. ppc outputs .no_dead_strip properly
...
llvm-svn: 41286
2007-08-22 19:33:11 +00:00
54a187ea8b
Minor cleanups to reduce some spurious differences between different
...
scheduler implementations.
llvm-svn: 41191
2007-08-20 19:28:38 +00:00
9c3d20d823
Partial implementation of calling functions with byval arguments:
...
*) The needed information is propagated to the DAG
*) The X86-64 backend detects it and aborts
llvm-svn: 41179
2007-08-20 15:18:24 +00:00
f5a23abf37
Fold C ? 0 : 1 to ~C or zext(~C) or trunc(~C) depending the types.
...
llvm-svn: 41163
2007-08-18 05:57:05 +00:00
cb6d65e1bf
Avoid issue on 64-bit hosts.
...
llvm-svn: 41143
2007-08-17 18:02:22 +00:00
81db5acab0
Fix GLIBCXX_DEBUG error of comparing two singular iterators
...
llvm-svn: 41139
2007-08-17 15:13:55 +00:00
631ccc6144
If dynamic_stackalloc alignment is > stack alignment, first issue an instruction to align the stack ptr before the decrement.
...
llvm-svn: 41133
2007-08-16 23:50:06 +00:00
95667c532c
- If a dynamic_stackalloc alignment requirement is <= stack alignment, then the alignment argument is ignored.
...
- *Always* round up the size of the allocation to multiples of stack
alignment to ensure the stack ptr is never left in an invalid state after a dynamic_stackalloc.
llvm-svn: 41132
2007-08-16 23:46:29 +00:00
70c2de7bf1
Fix some kill info update bugs; add hidden option -disable-rematerialization to turn off remat for debugging.
...
llvm-svn: 41118
2007-08-16 07:24:22 +00:00
a392cd2fde
Implement FPOWI ExpandOp.
...
Fix PR1287.
llvm-svn: 41112
2007-08-15 22:13:27 +00:00
958cf3d43e
If the source of a move is in spill slot, the reload may be folded to essentially a load from stack slot. It's ok to mark the stack slot value as available for reuse. But it should not be clobbered since the destination of the move is live.
...
llvm-svn: 41109
2007-08-15 20:20:34 +00:00
3f22fffe94
- If a def is dead, do not spill it.
...
- If the defs of a spilled rematerializable MI are dead after the spill store is deleted, delete
the def MI as well.
llvm-svn: 41086
2007-08-14 23:25:37 +00:00
94168a4ed0
Fix for PR1596: AdjustCopiesBackFrom() should conservatively check if any of its sub-registers may overlap with the interval of the copy that's being coalesced.
...
llvm-svn: 41084
2007-08-14 23:19:28 +00:00
6cb9fd7be5
If a MI's def is remat as well as spilled, and the store is later deemed dead, mark the def operand as isDead.
...
llvm-svn: 41083
2007-08-14 20:23:13 +00:00
234386509b
If a spilled value is being reused and the use is a kill, that means there are
...
no more uses within the MBB and the spilled value isn't live out of the MBB.
Then it's safe to delete the spill store.
llvm-svn: 41069
2007-08-14 09:11:18 +00:00
78a8806f4f
If a rematerializable def is not deleted, i.e. it is also spilled, check if the
...
spilled value is available for reuse.
llvm-svn: 41067
2007-08-14 05:42:54 +00:00
74c69f7588
Kill info update bugs.
...
llvm-svn: 41064
2007-08-14 01:56:58 +00:00
33820da1da
Re-implement trivial rematerialization. This allows def MIs whose live intervals that are coalesced to be rematerialized.
...
llvm-svn: 41060
2007-08-13 23:45:17 +00:00
5ca98c657d
Kill info update bugs.
...
llvm-svn: 41043
2007-08-13 07:12:23 +00:00
af21e9550e
No need to remove dead range from soon-to-be-dead live interval. Its val# may be out of whack.
...
llvm-svn: 41024
2007-08-12 01:26:19 +00:00
05cc486c7b
Code to maintain kill information during register coalescing.
...
llvm-svn: 41016
2007-08-11 00:59:19 +00:00
e081928f49
Move isSubRegOf into MRegisterInfo. Fix a missed move elimination in LowerSubregs and add more debugging output there.
...
llvm-svn: 41005
2007-08-10 21:11:55 +00:00
a17799a3bd
Fix EXTRACT_ELEMENT, EXTRACT_SUBVECTOR, and EXTRACT_VECTOR_ELT to
...
use an intptr ValueType instead of i32 for the index operand in
getCopyToParts.
llvm-svn: 40987
2007-08-10 14:59:38 +00:00
66011c17d5
propagate struct size and alignment of byval arguments to the DAG
...
llvm-svn: 40986
2007-08-10 14:44:42 +00:00
2b9fe84b07
unbreak the build
...
llvm-svn: 40976
2007-08-09 23:55:17 +00:00
1115a2b412
Bug fix. ~1U marks the val# dead.
...
llvm-svn: 40975
2007-08-09 23:14:39 +00:00
c339e45274
Update per review comments.
...
llvm-svn: 40965
2007-08-09 17:27:48 +00:00
ba1a98a4e0
long double 9 of N. This finishes up the X86-32 bits
...
(constants are still not handled). Adds ConvertActions
to control fp-to-fp conversions (these are currently
defaulted for all other targets, so no changes there).
llvm-svn: 40958
2007-08-09 01:04:01 +00:00
9d09c5ccda
If a target really needs to custom lower constants, it should be allowed
...
to do so.
llvm-svn: 40955
2007-08-08 23:23:31 +00:00
d771b793fe
Adding kill info to val#.
...
llvm-svn: 40925
2007-08-08 07:03:29 +00:00
103947125c
Clean up and bug fix.
...
llvm-svn: 40921
2007-08-08 05:56:18 +00:00
a8c2f38617
- Each val# can have multiple kills.
...
- Fix some minor bugs related to special markers on val# def. ~0U means
undefined, ~1U means dead val#.
llvm-svn: 40916
2007-08-08 03:00:28 +00:00
c236617ea0
Remove a dead assertion.
...
llvm-svn: 40914
2007-08-08 01:00:21 +00:00
0d0fee269a
- LiveInterval value#'s now have 3 components: def instruction #,
...
kill instruction #, and source register number (iff the value# is defined by a
copy).
- Now def instruction # is set for every value#, not just for copy defined ones.
- Update some outdated code related inactive live ranges.
- Kill info not yet set. That's next patch.
llvm-svn: 40913
2007-08-07 23:49:57 +00:00
99905f16f8
Add a missing forward declaration.
...
llvm-svn: 40896
2007-08-07 16:34:05 +00:00
079ebcfae5
Fix a regression compiling 2005-05-11-Popcount-ffs-fls with the CBE,
...
introduced by chandler's patch.
llvm-svn: 40864
2007-08-06 16:36:18 +00:00
2e5fb9f71e
Implement review feedback. No functionality change.
...
llvm-svn: 40863
2007-08-06 16:33:56 +00:00
446282ae3d
Fix minor doxygen nits.
...
llvm-svn: 40854
2007-08-05 20:06:04 +00:00
6299a45277
shorten this name
...
llvm-svn: 40843
2007-08-05 18:45:33 +00:00
7132e00de7
This is the patch to provide clean intrinsic function overloading support in LLVM. It cleans up the intrinsic definitions and generally smooths the process for more complicated intrinsic writing. It will be used by the upcoming atomic intrinsics as well as vector and float intrinsics in the future.
...
This also changes the syntax for llvm.bswap, llvm.part.set, llvm.part.select, and llvm.ct* intrinsics. They are automatically upgraded by both the LLVM ASM reader and the bitcode reader. The test cases have been updated, with special tests added to ensure the automatic upgrading is supported.
llvm-svn: 40807
2007-08-04 01:51:18 +00:00
5f6a9da530
More explicit keywords.
...
llvm-svn: 40757
2007-08-02 21:21:54 +00:00
3ffe7187db
don't redefine a parameter
...
llvm-svn: 40748
2007-08-02 18:08:16 +00:00
358c3d1dac
Do not emit copies for physical register output if it's not used.
...
llvm-svn: 40722
2007-08-02 05:29:38 +00:00
5b80ecbcf5
Style police: Expand the tabs to spaces!
...
llvm-svn: 40712
2007-08-02 02:22:46 +00:00
c5549fc3a0
Instead of adding copyfromreg's to handle physical definitions. Now isel can
...
simply specify them as results and let scheduledag handle them. That
is, instead of
SDOperand Flag = DAG.getTargetNode(Opc, MVT::i32, MVT::Flag, ...)
SDOperand Result = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, Flag)
Just write:
SDOperand Result = DAG.getTargetNode(Opc, MVT::i32, MVT::i32, ...)
And let scheduledag emit the move from X86::EAX to a virtual register.
llvm-svn: 40710
2007-08-02 00:28:15 +00:00
d8ded48468
Bugs: missing partial uses and redundant partial defs.
...
llvm-svn: 40688
2007-08-01 20:18:21 +00:00
0db4418a5f
Expand unaligned loads/stores when the target doesn't support them. (PR1548)
...
llvm-svn: 40682
2007-08-01 19:34:21 +00:00
17a5dfe6f7
New CallInst interface to address GLIBCXX_DEBUG errors caused by
...
indexing an empty std::vector.
Updates to all clients.
llvm-svn: 40660
2007-08-01 03:43:44 +00:00
e02b2d7e69
simpleregistercoalescing -> regcoalescing. It's too long for me to handle.
...
llvm-svn: 40654
2007-07-31 22:37:44 +00:00
34e2d22d63
- Allow custom lowering for CTPOP, CTTZ, CTLZ.
...
- Fixed an existing unexpanded tab.
llvm-svn: 40605
2007-07-30 21:00:31 +00:00
4ff9fb14f6
Fix a bug in getCopyFromParts turned up in the testcase for PR1132.
...
llvm-svn: 40598
2007-07-30 19:09:17 +00:00
33d0ea2597
Print a space between the comment character and the basic block name,
...
for prettiness.
llvm-svn: 40593
2007-07-30 15:06:25 +00:00
644f917358
Support for trampolines, except for X86 codegen which is
...
still under discussion.
llvm-svn: 40549
2007-07-27 12:58:54 +00:00
14bbb15f07
Move subreg lowering pass to be right after regalloc, per feedback.
...
llvm-svn: 40548
2007-07-27 07:36:14 +00:00
30f060be80
Fix the alias analysis query in DAGCombiner to not add in two
...
offsets. The SrcValueOffset values are the real offsets from the
SrcValue base pointers.
llvm-svn: 40534
2007-07-26 16:14:06 +00:00
e9d738cefc
Add a MachineFunction pass, which runs post register allocation, that turns subreg insert/extract instruction into register copies. This ensures correct code gen if the coalescer isn't able to remove all subreg instructions.
...
llvm-svn: 40521
2007-07-26 08:18:32 +00:00
18603b03e1
Teach DAG scheduling how to properly emit subreg insert/extract machine instructions. PR1350
...
llvm-svn: 40520
2007-07-26 08:12:07 +00:00
a8fc0e527b
Add selection DAG nodes for subreg insert/extract. PR1350
...
llvm-svn: 40516
2007-07-26 07:34:40 +00:00
0dbc152d2e
Remove subreg index from MachineInstr's and also keep vregs as unsigned when adding operands.
...
llvm-svn: 40514
2007-07-26 07:00:46 +00:00
3fead96121
Fix infinite recursion for when extract_vector_elt is legal. Unfortunately no public targets use this code-path, so no test.
...
llvm-svn: 40510
2007-07-26 03:33:13 +00:00
86eb3fd97d
EmitAlignment() also emits optional fill value.
...
llvm-svn: 40500
2007-07-25 23:35:07 +00:00
64b64ae591
Minor cleanup:
...
- Split EH and debug infiormation
- Make DwarfWriter more verbose in some cases
llvm-svn: 40481
2007-07-25 00:06:28 +00:00
f0bb12848f
Add const to CanBeFoldedBy, CheckAndMask, and CheckOrMask.
...
llvm-svn: 40480
2007-07-24 23:00:27 +00:00
b6a8ae20c7
Fix some uses of dyn_cast to be uses of cast.
...
llvm-svn: 40443
2007-07-23 20:24:29 +00:00
147d9fa57d
Don't assume that only Uses can be kills. Defs are marked as kills initially
...
when there are no uses. This fixes a dangling-pointer bug, where pointers to
deleted instructions were not removed from kills lists. More info here:
http://lists.cs.uiuc.edu/pipermail/llvmdev/2007-July/009749.html
llvm-svn: 40131
2007-07-20 23:17:34 +00:00
9d5df0a5f6
Added -print-emitted-asm to print out JIT generated asm to cerr.
...
llvm-svn: 40123
2007-07-20 21:56:13 +00:00
85ec2af554
As pointed out by g++-4.2, the original code didn't do
...
what it thought it was doing.
llvm-svn: 40044
2007-07-19 07:31:58 +00:00
a8d152a22a
Add comment.
...
llvm-svn: 40022
2007-07-18 23:34:48 +00:00
a7b65c30a3
It's not necessary to do rounding for alloca operations when the requested
...
alignment is equal to the stack alignment.
llvm-svn: 40004
2007-07-18 16:29:46 +00:00
f9ef70560e
Dead code.
...
llvm-svn: 39979
2007-07-17 20:01:19 +00:00
06c60b6032
Fix comments about vectors to use the current wording.
...
llvm-svn: 39921
2007-07-16 14:29:03 +00:00
d20f485866
Fix the build. Patch from Holger Schurig.
...
llvm-svn: 39856
2007-07-14 15:11:14 +00:00
383a324735
Long live the exception handling!
...
This patch fills the last necessary bits to enable exceptions
handling in LLVM. Currently only on x86-32/linux.
In fact, this patch adds necessary intrinsics (and their lowering) which
represent really weird target-specific gcc builtins used inside unwinder.
After corresponding llvm-gcc patch will land (easy) exceptions should be
more or less workable. However, exceptions handling support should not be
thought as 'finished': I expect many small and not so small glitches
everywhere.
llvm-svn: 39855
2007-07-14 14:06:15 +00:00
ff72788863
Fix the comment for LegalizeOp to more accurately reflect what it does.
...
llvm-svn: 39827
2007-07-13 20:14:11 +00:00
80f9f077e3
Don't call SimplifyVBinOp for non-vector operations, following earlier review
...
feedback. This theoretically makes the common (scalar) case more efficient.
llvm-svn: 39823
2007-07-13 20:03:40 +00:00
4dc35dbd3e
Modify previous patch per review comments.
...
llvm-svn: 39817
2007-07-13 17:31:29 +00:00
2182f06f2d
Skeleton of post-RA scheduler; doesn't do anything yet.
...
Change name of -sched option and DEBUG_TYPE to
pre-RA-sched; adjust testcases.
llvm-svn: 39816
2007-07-13 17:13:54 +00:00
0263dd1d7f
The type ids making up a filter are unsigned, and
...
should be output as unsigned values. Checked against
gcc.
llvm-svn: 39775
2007-07-12 13:51:39 +00:00
6b6d1f685f
Missed a couple of places where new instructions are added due to spill / restore.
...
llvm-svn: 39748
2007-07-11 19:17:18 +00:00
03b274911f
Exception handling has been implemented.
...
llvm-svn: 39732
2007-07-11 16:59:20 +00:00
d5ea194b6c
If assertions are not enabled, we should return False here.
...
llvm-svn: 38535
2007-07-11 08:47:55 +00:00
74a541024f
No longer need to track last def / use.
...
llvm-svn: 38534
2007-07-11 08:47:44 +00:00
bec7a20c5e
Fix for PR1545: Revamp code that update kill information due to register reuse.
...
llvm-svn: 38525
2007-07-11 05:28:39 +00:00
d9034f717a
Make this work with GLIBCXX_DEBUG.
...
llvm-svn: 38516
2007-07-10 22:00:30 +00:00
60d6f96da3
Change the peep for EXTRACT_VECTOR_ELT of BUILD_PAIR to look for
...
the new CONCAT_VECTORS node type instead, as that's what legalize
uses now. And add a peep for EXTRACT_VECTOR_ELT of INSERT_VECTOR_ELT.
llvm-svn: 38503
2007-07-10 18:20:44 +00:00
5e9084207f
If the operand is marked M_OPTIONAL_DEF_OPERAND, then it's a def.
...
llvm-svn: 38496
2007-07-10 17:52:20 +00:00
fbc73099dc
Somehow this wasn't committed last time. M_CLOBBERS_PRED is gone.
...
llvm-svn: 38495
2007-07-10 17:50:43 +00:00
adb3d37c07
Fix a bug in the folding of binary operators to undef.
...
Thanks to Lauro for spotting this!
llvm-svn: 38491
2007-07-10 15:19:29 +00:00
fa91282dbf
Fix the folding of undef in several binary operators to recognize
...
undef in either the left or right operand.
llvm-svn: 38489
2007-07-10 14:20:37 +00:00
ff6f279adf
When a node value is only used by a CopyToReg, use the user's dest. This should not be restricted to nodes that produce only a single value.
...
llvm-svn: 38485
2007-07-10 07:08:32 +00:00
32aad49b24
Move DenseMapKeyInfo<SDOperand> from LegalizeDAG.cpp to SelectionDAGNodes.h
...
llvm-svn: 38484
2007-07-10 06:59:55 +00:00
2af3063337
Preserve volatililty and alignment information when lowering or
...
simplifying loads and stores.
llvm-svn: 38473
2007-07-09 22:18:38 +00:00
f8f531bf69
Change getCopyToParts and getCopyFromParts to always use target-endian
...
register ordering, for both physical and virtual registers. Update the PPC
target lowering for calls to expect registers for the call result to
already be in target order.
llvm-svn: 38471
2007-07-09 20:59:04 +00:00
6decfbf133
Initialize the IndexedModeActions array with memset before
...
updating it with calls to setIndexedLoadAction/setIndexedStoreAction,
which only update a few bits at a time. This avoids ostensible
undefined behavior of operationg on values which may be
trap-representations, and as a practical matter fixes errors from
valgrind, which doesn't track uninitialized memory with bit
granularity.
llvm-svn: 38468
2007-07-09 20:49:44 +00:00
6caf8fdd04
Fix this warning:
...
DAGCombiner.cpp: In member function 'llvm::SDOperand<unnamed>::DAGCombiner::visitOR(llvm::SDNode*)':
DAGCombiner.cpp:1608: warning: passing negative value '-0x00000000000000001' for argument 1 to 'llvm::SDOperand llvm::SelectionDAG::getConstant(uint64_t, llvm::MVT::ValueType, bool)'
oiy.
llvm-svn: 38458
2007-07-09 16:16:34 +00:00
ef3d8362a3
fix typos
...
llvm-svn: 38453
2007-07-09 12:00:59 +00:00
96c1457bff
Teach if-conversion about instructions that were already predicated, e.g. conditional move.
...
llvm-svn: 37964
2007-07-06 23:24:39 +00:00
9d97420473
The exception handling intrinsics return values,
...
so must be lowered to a value, not nothing at all.
Subtle point: I made eh_selector return 0 and
eh_typeid_for return 1. This means that only
cleanups (destructors) will be run as the exception
unwinds [if eh_typeid_for returned 0 then it would
be as if the first catch always matched, and the
corresponding handler would be run], which is
probably want you want in the CBE.
llvm-svn: 37947
2007-07-06 14:46:23 +00:00
c5b1984f57
Indexes into the list of filter ids cannot be output
...
directly: they need to be turned into byte offsets
(often the same, but may not be if there are many
type infos).
llvm-svn: 37942
2007-07-06 12:46:24 +00:00
b567e3ffb0
Add the byval attribute
...
llvm-svn: 37940
2007-07-06 10:57:03 +00:00
003c0b1f90
Remove propagateEHRegister in favour of a more limited
...
fix, that is adequate while PR1508 remains unresolved.
llvm-svn: 37938
2007-07-06 09:18:59 +00:00
81df18a50a
Remove ExtractGlobalVariable - use StripPointerCasts
...
instead.
llvm-svn: 37937
2007-07-06 09:10:03 +00:00
fc7010d962
Workaround of getCopyToRegs and getCopyFromRegs bugs for big-endian machines.
...
llvm-svn: 37935
2007-07-06 01:47:35 +00:00
642be16bbf
Change CalculateHeights and CalculateDepths to be non-recursive.
...
llvm-svn: 37934
2007-07-06 01:37:28 +00:00
a282694acf
Make the debug string for ISD::MERGE_VALUES consistent with the others.
...
llvm-svn: 37922
2007-07-05 20:15:43 +00:00
d258e80583
Add a parameter to getCopyToParts and getCopyFromParts to specify whether
...
endian swapping should be done, and update the code to use it. This fixes
some register ordering issues on big-endian systems, such as PowerPC,
introduced by the recent illegal by-val arguments changes.
llvm-svn: 37921
2007-07-05 20:12:34 +00:00
e16561cd5d
Here is the bulk of the sanitizing.
...
Almost all occurrences of "bytecode" in the sources have been eliminated.
llvm-svn: 37913
2007-07-05 17:07:56 +00:00
4836e3a6f8
Make sure only one copy of a filter is placed in the
...
exception handling table if we encounter it multiple
times. Filters could be folded harder than this, but
that would mean a lot more work for not much gain.
llvm-svn: 37908
2007-07-05 15:15:01 +00:00
bb6ecf0067
Better assertion messages.
...
llvm-svn: 37890
2007-07-05 07:05:38 +00:00
fe80638417
Extend eh.selector to support both catches and filters.
...
Drop the eh.filter intrinsic.
llvm-svn: 37875
2007-07-04 20:52:51 +00:00
06563a8702
Fix several over-aggressive folds for undef nodes in dagcombine, to
...
follow the rules for undef used in instcombine.
llvm-svn: 37851
2007-07-03 14:03:57 +00:00
a2b3c175db
Fix for PR 1505 (and 1489). Rewrite X87 register
...
model to include f32 variants. Some factoring
improvments forthcoming.
llvm-svn: 37847
2007-07-03 00:53:03 +00:00
533dd16a7f
Replace ExpandScalarFormalArgs and ExpandScalarCallArgs with the newly
...
refactored getCopyFromParts and getCopyToParts, which are more general.
This effectively adds support for lowering illegal by-val vector call
arguments.
llvm-svn: 37843
2007-07-02 16:18:06 +00:00
9a70823375
Teach GetNegatedExpression to negate 0-B to B in UnsafeFPMath mode, and
...
visitFSUB to fold 0-B to -B in UnsafeFPMath mode. Also change visitFNEG
to use isNegatibleForFree/GetNegatedExpression instead of doing a subset
of the same thing manually.
This fixes test/CodeGen/X86/negative-sin.ll.
llvm-svn: 37842
2007-07-02 15:48:56 +00:00
fa68d069ad
Only do FNEG xform when the vector type is a floating point type.
...
llvm-svn: 37818
2007-06-29 21:44:35 +00:00
cf2a51e8db
Remove unused variables.
...
llvm-svn: 37816
2007-06-29 21:42:03 +00:00
9458e6a551
Fix a vector FP constant CSE bug.
...
llvm-svn: 37814
2007-06-29 21:36:04 +00:00
4c1e6f3804
Remove unnecessary attributions in comments.
...
llvm-svn: 37799
2007-06-29 03:42:23 +00:00
9468bfd932
Fix reference to cached end iterator invalidated by an erase operation.
...
Uncovered by _GLIBCXX_DEBUG.
llvm-svn: 37795
2007-06-29 02:49:11 +00:00
5b6f755575
Remove the "special tie breaker" because it resulted in inconsistent
...
ordering and thus violated the strict weak ordering requirement of
priority_queue. Uncovered by _GLIBCXX_DEBUG.
llvm-svn: 37794
2007-06-29 02:48:09 +00:00
451d1a6ecd
Fix misue of iterator pointing to erased object. Uncovered by
...
_GLIBCXX_DEBUG.
llvm-svn: 37793
2007-06-29 02:45:24 +00:00
0de7694de6
Fix an assertion failure in legalizing bitcast operators on targets where
...
vectors are split down to single elements as part of legalization.
llvm-svn: 37785
2007-06-29 00:09:08 +00:00
7867793aff
Add new TargetLowering code to provide the final register type that an
...
illegal value type will be transformed to, for code that needs the
register type after all transformations instead of just after the first
transformation.
Factor out the code that uses this information to do copy-from-regs and
copy-to-regs for various purposes into separate functions so that they
are done consistently.
llvm-svn: 37781
2007-06-28 23:29:44 +00:00
df0c705d7d
If a livein is not used in the block. It's live through.
...
llvm-svn: 37764
2007-06-27 18:47:28 +00:00
77f541ddfd
Partial fix for PR1502: If a EH register is needed in a successor of landing pad, add it as livein to all the blocks in the paths between the landing pad and the specified block.
...
llvm-svn: 37763
2007-06-27 18:45:32 +00:00
3b62d7265d
Rename ("shrinkify") MVT::isExtendedValueType to MVT::isExtendedVT.
...
llvm-svn: 37758
2007-06-27 16:08:04 +00:00
7139a48057
Use getVectorTypeBreakdown in FunctionLoweringInfo::CreateRegForValue
...
to compute the number and type of registers needed for vector values
instead of computing it manually. This fixes PR1529.
llvm-svn: 37755
2007-06-27 14:34:07 +00:00
f4e86da3a6
Make the comment for ScalarizeVectorOp mention that it is only for use
...
with single-element vectors.
llvm-svn: 37752
2007-06-27 14:06:22 +00:00
95759c0e78
ok, this is something of a dirty hack, but it seems to work. (fixes e.g.
...
the SPASS miscompilation)
llvm-svn: 37750
2007-06-27 09:01:14 +00:00
89183dcc14
ok, this much doesn't seem to bork anything
...
llvm-svn: 37749
2007-06-27 08:31:07 +00:00
a415dcaa2a
revert evan's fixes (and my doofusness) since they had a huge code
...
quality hit. will look at this soon.
llvm-svn: 37748
2007-06-27 08:11:59 +00:00
540d329542
pull evan's fixes - should help the nightly tester (but there are still
...
some issues)
llvm-svn: 37747
2007-06-27 07:07:13 +00:00
e66f822ecc
Replace std::set with SmallPtrSet.
...
llvm-svn: 37746
2007-06-27 05:23:00 +00:00
6cf1371456
Fix an obvious bug. Old code only worked for the entry block.
...
llvm-svn: 37743
2007-06-27 01:16:36 +00:00
4bf87f1f44
Correctly handle implcit def / use operands.
...
llvm-svn: 37740
2007-06-26 21:05:13 +00:00
d8417d9199
Properly handle kills of a physical register which has sub-registers that are read by later instructions.
...
llvm-svn: 37739
2007-06-26 21:03:35 +00:00
f4dc5b26e2
tidy this file up a bit
...
llvm-svn: 37725
2007-06-26 00:21:58 +00:00
77416383e8
A bunch of fixes to the BigBlock allocator improve compile-time by ~20%
...
and code quality by ~2% on my tests.
A big thank you to Roman Levenstein for this patch! See
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20070618/050717.html
for more details.
llvm-svn: 37724
2007-06-25 23:46:54 +00:00
a866514528
Generalize MVT::ValueType and associated functions to be able to represent
...
extended vector types. Remove the special SDNode opcodes used for pre-legalize
vector operations, and the special MVT::Vector type used with them. Adjust
lowering and legalize to work with the normal SDNode kinds instead, and to
use the normal MVT functions to work with vector types instead of using the
two special operands that the pre-legalize nodes held.
This allows pre-legalize and post-legalize DAGs, and the code that operates
on them, to be more consistent. Pre-legalize vector operators can be handled
more consistently with scalar operators. And, -view-dag-combine1-dags and
-view-legalize-dags now look prettier for vector code.
llvm-svn: 37719
2007-06-25 16:23:39 +00:00
309d3d51b3
Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from
...
TargetLowering to SelectionDAG so that they have more convenient
access to the current DAG, in preparation for the ValueType routines
being changed from standalone functions to members of SelectionDAG for
the pre-legalize vector type changes.
llvm-svn: 37704
2007-06-22 14:59:07 +00:00
81a752aa95
check in the BigBlock local register allocator
...
llvm-svn: 37703
2007-06-22 08:27:12 +00:00
e3c4419953
std::set is really really terrible. Switch to SmallPtrSet to reduce compile time. For Duraid's example. The overall isel time is reduced from 0.6255 sec to 0.1876 sec.
...
llvm-svn: 37701
2007-06-22 01:35:51 +00:00
8e8d34b220
Tidy up ValueType names in comments.
...
llvm-svn: 37688
2007-06-21 14:48:26 +00:00
04deef3a49
Rename TargetLowering::getNumElements and friends to
...
TargetLowering::getNumRegisters and similar, to avoid confusion with
the actual number of elements for vector types.
llvm-svn: 37687
2007-06-21 14:42:22 +00:00
aa5f5d960d
Xforms:
...
(add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
(sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
llvm-svn: 37685
2007-06-21 07:39:16 +00:00
a955c02c9b
Avoid if-converting simple block that ends with unconditional branch or fallthrough unless it branches / falls to the 'false' block. Not profitable, may end up increasing code size.
...
llvm-svn: 37660
2007-06-19 21:45:13 +00:00
a7644dd9b9
Pass a SelectionDAG into SDNode::dump everywhere it's used, in prepration
...
for needing the DAG node to print pre-legalize extended value types, and
to get better debug messages with target-specific nodes.
llvm-svn: 37656
2007-06-19 14:13:56 +00:00
37228f6ce5
document and hide two options.
...
llvm-svn: 37651
2007-06-19 05:47:49 +00:00
9e82064924
Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad
...
with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.
llvm-svn: 37644
2007-06-19 01:48:05 +00:00
a7ca624028
Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit.
...
llvm-svn: 37643
2007-06-19 01:26:51 +00:00
26be02febf
add isVarArg to CCState
...
llvm-svn: 37640
2007-06-19 00:11:09 +00:00
0598b2d5eb
Fix some fragile code wrt CFG edge updating.
...
llvm-svn: 37634
2007-06-18 22:44:57 +00:00
2afd702c20
Move CorrectExtraCFGEdges() from BranchFolding.cpp to a MachineBasicBlock method.
...
llvm-svn: 37633
2007-06-18 22:43:58 +00:00
e31adc8ab9
make ComputeTopDownOrdering significantly faster and use less stack space
...
by making it non-recursive
llvm-svn: 37629
2007-06-18 21:28:10 +00:00
8c7333266c
Make chain dependencies blue, in addition to being dashed.
...
llvm-svn: 37626
2007-06-18 15:30:16 +00:00
51eb2c3bbe
Properly remove duplicate instructions as result of diamond if-conversion. Other bug fixes.
...
llvm-svn: 37623
2007-06-18 08:37:25 +00:00
3a51c854d0
Really turn if-converter loose:
...
1. Consider all possible ifcvt cases at once. No longer restricted to bottom
up iterative approach.
2. Sort all possible cases based on a cost function. Perform the most profitable
ones first invalidate others that target the same blocks.
3. Fixed a number of bugs related to block duplication.
llvm-svn: 37613
2007-06-16 09:34:52 +00:00
e199f97fa8
Codegen support (stripped out) for the annotate attribute.
...
llvm-svn: 37608
2007-06-15 22:26:58 +00:00
23402fcaef
Not every predicable block can be safely duplicated.
...
llvm-svn: 37607
2007-06-15 21:18:05 +00:00
f852e339b6
Fix CodeGen/X86/inline-asm-x-scalar.ll:test4, by retaining regclass info
...
for tied register constraints.
llvm-svn: 37601
2007-06-15 19:11:01 +00:00
234a90e83e
MachineInstr::isPredicable() is no longer needed.
...
llvm-svn: 37599
2007-06-15 19:06:07 +00:00
92bf2c628c
Workaround for PR1508.
...
llvm-svn: 37597
2007-06-15 19:04:19 +00:00
cd5f5e3ecd
Extra edges are deleted later if needed.
...
llvm-svn: 37593
2007-06-15 17:34:48 +00:00
92fb5453c3
Allow small blocks to be duplicated to enable if-conversion.
...
llvm-svn: 37590
2007-06-15 07:36:12 +00:00
add977670f
No really, clear predcessors states.
...
llvm-svn: 37581
2007-06-14 23:34:09 +00:00
9fc56c079d
If BB is predicated, invalidate its predecessor(s) which would if-convert it. It needs to be re-analyzed.
...
llvm-svn: 37580
2007-06-14 23:13:19 +00:00
5c4413120f
Rename MVT::getVectorBaseType to MVT::getVectorElementType.
...
llvm-svn: 37579
2007-06-14 22:58:02 +00:00
e08f0eefa6
Fix typo.
...
llvm-svn: 37577
2007-06-14 21:26:08 +00:00
4a4a8eb00e
Add a target hook to allow loads from constant pools to be rematerialized, and an
...
implementation for x86.
llvm-svn: 37576
2007-06-14 20:50:44 +00:00
1e6f08b2a2
Fix some stupid bugs that have effectively disabled if-conversion.
...
llvm-svn: 37575
2007-06-14 20:28:52 +00:00
7413736a7e
Only correctly lower exception handing intrinsics if exception handling is
...
turned on. Likewise for scanning of invokes to mark landing pads.
llvm-svn: 37570
2007-06-13 16:53:21 +00:00
26455c4ae0
Introduce new SelectionDAG node opcodes VEXTRACT_SUBVECTOR and
...
VCONCAT_VECTORS. Use these for CopyToReg and CopyFromReg legalizing in
the case that the full register is to be split into subvectors instead
of scalars. This replaces uses of VBIT_CONVERT to present values as
vector-of-vector types in order to make whole subvectors accessible via
BUILD_VECTOR and EXTRACT_VECTOR_ELT.
This is in preparation for adding extended ValueType values, where
having vector-of-vector types is undesirable.
llvm-svn: 37569
2007-06-13 15:12:02 +00:00
cbd51c8b60
When creating CopyFromReg nodes, always use legal types. And use the
...
correct types for the result vector, even though it is currently bitcasted
to a different type immediately.
llvm-svn: 37568
2007-06-13 14:55:16 +00:00
97f7236e70
The fix that was applied for PR1224 stops the compiler
...
crashing but breaks exception handling. The problem
described in PR1224 is that invoke is a terminator that
can produce a value. The value may be needed in other
blocks. The code that writes to registers values needed
in other blocks runs before terminators are lowered (in
this case invoke) so asserted because the value was not
yet available. The fix that was applied was to do invoke
lowering earlier, before writing values to registers.
The problem this causes is that the code to copy values
to registers can be output after the invoke call. If
an exception is raised and control is passed to the
landing pad then this copy-code will never execute. If
the value is needed in some code path reached via the
landing pad then that code will get something bogus.
So revert the original fix and simply skip invoke values
in the general copying to registers code. Instead copy
the invoke value to a register in the invoke lowering code.
llvm-svn: 37567
2007-06-13 05:51:31 +00:00
cbaaff58bf
Typo
...
llvm-svn: 37566
2007-06-13 00:04:00 +00:00
9acfa7b063
Now if-converting all 4 variants of triangles.
...
llvm-svn: 37565
2007-06-12 23:54:05 +00:00
4c2f003971
Fix a typo in bswap lowering.
...
llvm-svn: 37544
2007-06-11 23:16:16 +00:00
4dd31a7b1b
Restructure code to reduce ifcvt compile time cost.
...
llvm-svn: 37543
2007-06-11 22:26:22 +00:00
14b62a553e
Fix the build.
...
llvm-svn: 37537
2007-06-10 00:19:17 +00:00
2117d1f20e
Don't change CFG during analysis stage. Do so during ifcvt and invalidate predecessors accordingly.
...
llvm-svn: 37531
2007-06-09 01:03:43 +00:00
288f1545a6
Carefully remove extraneous CFG edges after each ifcvt.
...
llvm-svn: 37529
2007-06-08 22:01:07 +00:00
df1a42935b
Correct transfer predicate information.
...
llvm-svn: 37524
2007-06-08 19:17:12 +00:00
e93ccc013f
Hidden options to help debugging ifcvt issues.
...
llvm-svn: 37523
2007-06-08 19:10:51 +00:00
02f6e9b621
Factor live variable analysis so it does not do register coalescing
...
simultaneously. Move that pass to SimpleRegisterCoalescing.
This makes it easier to implement alternative register allocation and
coalescing strategies while maintaining reuse of the existing live
interval analysis.
llvm-svn: 37520
2007-06-08 17:18:56 +00:00
7783f82e21
Allow more cmp / bcc to be predicated; clean up triangle ifcvt checking code.
...
llvm-svn: 37518
2007-06-08 09:36:04 +00:00
dc8fc1550e
Use more realistically sized vectors. Reserve capacity if we know in advance
...
how much will be used.
llvm-svn: 37515
2007-06-08 08:59:11 +00:00
86798e5e11
Make throttle a hidden parameter, per review.
...
llvm-svn: 37511
2007-06-08 01:08:52 +00:00
52fcf022f7
Throttle tail merging; handling blocks with large numbers of predecessors
...
is too slow.
llvm-svn: 37509
2007-06-08 00:34:27 +00:00
1236ef7bcc
Only remove the edge from entry to false if false block is merged.
...
llvm-svn: 37503
2007-06-07 22:31:28 +00:00
9a4d987a5f
Do not change the size of function arguments. PR 1489.
...
llvm-svn: 37496
2007-06-07 21:07:15 +00:00
d3f3f0adad
ifcvt a triangle: don't merge ifcvt block with rejoin block if it can fall through to it. If merged, the resulting block is not a candidate for iterative ifcvting since it contains both predicated and non-predicated code.
...
llvm-svn: 37487
2007-06-07 08:13:00 +00:00
be9859eea2
Lots of bug fixes. Now finally in a reasonable state.
...
llvm-svn: 37485
2007-06-07 02:12:15 +00:00
cfb6f40424
Quick patch to fix the build, based on what it appears Evan meant to write.
...
Evan, please check that this is in fact correct.
llvm-svn: 37471
2007-06-06 16:22:00 +00:00
29d1dc6f1a
Fold the exception actions table harder: if two typeid lists start the
...
same, only output one copy of the common part.
llvm-svn: 37470
2007-06-06 15:37:31 +00:00
9030b98aca
Lots of bug fixes.
...
llvm-svn: 37467
2007-06-06 10:16:17 +00:00
61166501a1
Additional fix for PR1422: make sure the landing pad label is placed in the
...
correct machine basic block - do not rely on the eh.exception intrinsic
being in the landing pad: the loop optimizers can move it out.
llvm-svn: 37463
2007-06-06 10:05:18 +00:00
e4ec918be0
If a unconditional branch is added to branch to the false path during ifcvt, the predicated block cannot be iteratively ifcvted.
...
llvm-svn: 37456
2007-06-06 02:08:52 +00:00
b30a89457c
Minor statistics counting bug.
...
llvm-svn: 37451
2007-06-06 01:12:44 +00:00
30565998bb
Fix a couple of typos and be smarter about order of blocks when ifcvt a diamond.
...
llvm-svn: 37449
2007-06-06 00:57:55 +00:00
7948422b78
Fix diamond shape ifcvt bugs.
...
llvm-svn: 37444
2007-06-05 23:46:14 +00:00
c1a0b8ce1d
ReplaceUsesOfBlockWith() can modify the predecessors list.
...
llvm-svn: 37441
2007-06-05 22:03:53 +00:00
3e5bf0827c
Do not ifcvt if either true / false path is a backedge. Not profitable in almost all cases.
...
llvm-svn: 37440
2007-06-05 20:38:42 +00:00
2c1acd6d9e
I had a senior moment.
...
llvm-svn: 37433
2007-06-05 07:05:25 +00:00
6e4babe8cc
If the predicated block requires an early exit, end the block there and add a unconditional branch to false block. AnalyzeBranch() does not understand early exits.
...
llvm-svn: 37430
2007-06-05 01:31:40 +00:00
17aad8164e
Fix some subtle bugs: bug during succeessor copying; incorrectly updating states of ifcvted blocks.
...
llvm-svn: 37429
2007-06-05 00:07:37 +00:00
0558dda319
Tail merging wasn't working for predecessors of landing pads. PR 1496.
...
llvm-svn: 37427
2007-06-04 23:52:54 +00:00
53ce7de03b
Global ctors / dtors alignment shouldn't be hard-coded at 4. e.g. It could be 8 for 64-bit targets.
...
llvm-svn: 37421
2007-06-04 20:39:18 +00:00
91233153bf
Forgot to check for if iterator reached the end.
...
llvm-svn: 37420
2007-06-04 20:33:36 +00:00
b4c2690446
Pass the DAG to SDNode::dump to let it do more detailed dumps in some cases.
...
llvm-svn: 37413
2007-06-04 16:17:33 +00:00
92a7f3a65e
Resolve implicit alignment before computing the FoldingSet information so
...
that the CSE map always contains explicit alignment information. This allows
more loads to be CSE'd when there is a mix of explicit-alignment loads and
implicit-alignment loads.
Also, in SelectionDAG::FindModifiedNodeSlot, add the operands to the
FoldingSetNodeID before the load/store information instead of after, so
that it matches what is done elsewhere.
llvm-svn: 37411
2007-06-04 15:49:41 +00:00
312b723af2
Let IfConverter loose. Allow more aggressive subsumptions; reorder basic blocks to expose more ifcvt opportunities; code clean up and fixes.
...
llvm-svn: 37409
2007-06-04 06:47:22 +00:00
df75785594
Move ReplaceUsesOfBlockWith() out of BranchFolding into a MachineBasicBlock general facility.
...
llvm-svn: 37408
2007-06-04 06:44:01 +00:00
f708f73a1b
The semantics of invoke require that we always jump to the unwind block
...
(landing pad) when an exception unwinds through the call. This doesn't
quite match the way the dwarf unwinder works: by default it only jumps to
the landing pad if the catch or filter specification matches, and otherwise
it keeps on unwinding. There are two ways of specifying to the unwinder
that it should "always" (more on why there are quotes here later) jump to
the landing pad: follow the specification by a 0 typeid, or follow it by
the typeid for the NULL typeinfo. GCC does the first, and this patch makes
LLVM do the same as gcc. However there is a problem: the unwinder performs
optimizations based on C++ semantics (it only expects destructors to be
run if the 0 typeid fires - known as "cleanups"), meaning it assumes that no
exceptions will be raised and that the raised exception will be reraised
at the end of the cleanup code. So if someone writes their own LLVM code
using the exception intrinsics they will get a nasty surprise if they don't
follow these rules. The other possibility of using the typeid corresponding
to NULL (catch-all) causes the unwinder to make no assumptions, so this is
probably what we should use in the long-run. However since we are still
having trouble getting exception handling working properly, for the moment
it seems best to closely imitate GCC.
llvm-svn: 37399
2007-06-02 17:16:06 +00:00
c063f5f362
Integrate exception filter support and exception catch support. This
...
simplifies the code in DwarfWriter, allows for multiple filters and
makes it trivial to specify filters accompanied by cleanups or catch-all
specifications (see next patch). What a deal! Patch blessed by Anton.
llvm-svn: 37398
2007-06-02 16:53:42 +00:00
0a0ae932ca
Make LowerCTPOP() support arbitrary bitwidth integer type.
...
llvm-svn: 37397
2007-06-02 04:10:33 +00:00
6e7cdce773
Fix CorrectExtraCFGEdges to allow for multiple LandingPad targets.
...
llvm-svn: 37394
2007-06-02 00:08:15 +00:00
9746e3a22b
Fancier algorithm in tail-merge comment implemented, so remove comment.
...
llvm-svn: 37393
2007-06-01 23:04:28 +00:00
3c0a13762d
Implement smarter algorithm for choosing which blocks to tail-merge.
...
See test/CodeGen/X86/test-pic-jtbl.ll for a case where it works well;
shaves another 10K off our favorite benchmark. I was hesitant about
this because of compile speed, but seems to do OK on a bootstrap.
llvm-svn: 37392
2007-06-01 23:02:45 +00:00
4dcf1e8582
Correctly mark early-exit on the false path.
...
llvm-svn: 37387
2007-06-01 20:29:21 +00:00
706421e712
Since TypeInfos are passed as i8 pointers, a NULL TypeInfo should be passed
...
as a null i8 pointer not as a 0 i32.
llvm-svn: 37383
2007-06-01 08:18:30 +00:00
6a2cf070cc
Ifcvt triangle: don't ifcvt 'true' BB if it has other predecessors; don't merge 'false' BB if it has other predecessors.
...
llvm-svn: 37382
2007-06-01 07:41:07 +00:00
95c7917d92
Remove a bogus check. Even terminators in a ifcvt need to be predicated. Unconditional branches can usually be converted to conditional ones.
...
llvm-svn: 37380
2007-06-01 00:55:26 +00:00
20e05997f5
Allow multiple ifcvt candidates to share children blocks; add some debugging code.
...
llvm-svn: 37379
2007-06-01 00:12:12 +00:00
1a401e68a8
Arrange for only 1 of multiple branches to landing pad to be kept.
...
Do not remove empty landing pads (EH table needs to be updated)
llvm-svn: 37375
2007-05-31 21:54:00 +00:00
e6ccb6c5ed
Fix a typo.
...
llvm-svn: 37374
2007-05-31 20:53:33 +00:00
3e3ff30aa2
Fix the asmprinter so that a globalvalue can specify an explicit alignment
...
smaller than the preferred alignment, but so that the target can actually
specify a minimum alignment if needed. This fixes some objc protocol
failures Devang tracked down.
llvm-svn: 37373
2007-05-31 18:57:45 +00:00
5b0757a401
Fix PR1424.
...
When a function has FP, the register scavenging spill slot offset already
was calculated.
llvm-svn: 37371
2007-05-31 18:27:58 +00:00
905a8f4940
Change traversal order to bottom up in preparation for more aggressive if-conversion.
...
llvm-svn: 37365
2007-05-30 19:49:19 +00:00
397c4d9ef6
Fix CodeGen/PowerPC/2007-05-30-dagcombine-miscomp.ll, and PR1473.
...
llvm-svn: 37362
2007-05-30 16:30:06 +00:00
d14ad078c6
Changed per review comment.
...
llvm-svn: 37355
2007-05-30 00:32:01 +00:00
a69ebdbebc
Make stable_sort in tail merging actually be stable (it never was, but didn't
...
matter until my last change). Reenable tail merging by default.
llvm-svn: 37354
2007-05-29 23:47:50 +00:00
20f7d30f92
Don't merge in tail block of a diamond if it has more than one predecessors after if-conversion.
...
llvm-svn: 37353
2007-05-29 23:37:20 +00:00
c2237ce217
If there is an empty block between a source and its successor block, it still requires a unconditional branch.
...
llvm-svn: 37344
2007-05-29 22:31:16 +00:00
5983bdbb2c
Add missing const qualifiers.
...
llvm-svn: 37341
2007-05-29 18:35:22 +00:00
d7dc1ed64c
Correct the logic in LowerPartSet which cleared the bits from 0 to low-1.
...
llvm-svn: 37331
2007-05-26 03:43:13 +00:00
4698083b96
tighten up recursion depth again
...
llvm-svn: 37330
2007-05-25 02:19:06 +00:00
13f5f7df95
Silly boog.
...
llvm-svn: 37328
2007-05-25 00:59:01 +00:00
1409b6a59b
Blocks that cond-br and uncond-br/fallthrough to same block should have
...
only one successor.
llvm-svn: 37324
2007-05-24 18:31:55 +00:00
1af8c870c7
Fix for PR1444: do not create two successors to the same block.
...
Temporarily, this breaks CodeGen/Generic/2006-02-12-InsertLibraryCall.ll
by exposing an unrelated latent problem; working on that.
llvm-svn: 37323
2007-05-24 17:39:32 +00:00
30978078bf
Minor comment cleanups.
...
llvm-svn: 37321
2007-05-24 14:36:04 +00:00
703e0f8608
Add explicit qualification for namespace MVT members.
...
llvm-svn: 37320
2007-05-24 14:33:05 +00:00
a4d187b8ce
Fix a typo that caused combiner to create mal-formed pre-indexed store where value store is the same as the base pointer.
...
llvm-svn: 37318
2007-05-24 02:35:39 +00:00
f4a77d2481
Two tail merging improvements:
...
When considering blocks with more than 2 predecessors, merge the block with
the largest number of matching insns, rather than the first block found.
Considering that 1 matching insn is enough to show a win for candidates that
already end with a branch.
llvm-svn: 37315
2007-05-23 21:07:20 +00:00
3b327826db
Mark all calls as "could throw", when exceptions are enabled. Emit necessary LP info too. This fixes PR1439
...
llvm-svn: 37311
2007-05-23 11:08:31 +00:00
6509c0673f
prevent exponential recursion in isNegatibleForFree
...
llvm-svn: 37310
2007-05-23 07:35:22 +00:00
d0e669199b
Preliminary iterative if-conversion support.
...
llvm-svn: 37309
2007-05-23 07:23:16 +00:00
f9cbdc676c
name change requested by review of previous patch
...
llvm-svn: 37289
2007-05-22 18:31:04 +00:00
0ae7eb5e7c
Silence a warning.
...
llvm-svn: 37288
2007-05-22 18:13:40 +00:00
82810c8a13
Make tail merging the default, except on powerPC. There was no prior art
...
for a target-dependent default with a command-line override; this way
should be generally usable.
llvm-svn: 37285
2007-05-22 17:14:46 +00:00
e26c0916a3
If-convert early exit blocks (returns, etc.); bug fixes, etc.
...
llvm-svn: 37270
2007-05-21 22:22:58 +00:00
34e82a4508
Only emit one entry in the exception action table for each action, even if
...
it occurs for multiple landing pads.
llvm-svn: 37267
2007-05-21 18:50:28 +00:00
1fa8276e70
same patch as the previous one, but the symmetric case
...
llvm-svn: 37249
2007-05-19 00:46:51 +00:00
b08cbbd737
Disable the (A == (B-A)) -> 2*A == B xform when the sub has multiple uses (in
...
this case, the xform introduces an extra operation). This compiles
PowerPC/compare-duplicate.ll into:
_test:
subf r2, r3, r4
cmplw cr0, r2, r3
bne cr0, LBB1_2 ;F
instead of:
_test:
slwi r2, r3, 1
subf r3, r3, r4
cmplw cr0, r4, r2
bne cr0, LBB1_2 ;F
This is target independent of course.
llvm-svn: 37246
2007-05-19 00:43:44 +00:00
018cffbca4
Clean up.
...
llvm-svn: 37237
2007-05-18 19:32:08 +00:00
faaf716540
Change to depth-first traversal.
...
llvm-svn: 37236
2007-05-18 19:26:33 +00:00
dafda82755
Document an inefficiency in tail merging.
...
llvm-svn: 37235
2007-05-18 18:46:40 +00:00
b539df3389
Qualify calls to getTypeForValueType with MVT:: too.
...
llvm-svn: 37233
2007-05-18 18:41:29 +00:00
2e82cefd24
Some restructuring in preparation for most aggressive if-conversion.
...
llvm-svn: 37231
2007-05-18 18:14:37 +00:00
1796f1f8e9
Qualify several calls to functions in the MVT namespace, for consistency.
...
llvm-svn: 37230
2007-05-18 17:52:13 +00:00
f25d3a5d73
Watch out for blocks that end with a return.
...
llvm-svn: 37227
2007-05-18 17:06:53 +00:00
478b805956
If true / false blocks fallthrough before ifcvt, add unconditional branches to ifcvt'd block.
...
llvm-svn: 37200
2007-05-18 01:55:58 +00:00
f8956178af
Remove some unneeded branches. (spotted by Evan, thanks)
...
llvm-svn: 37198
2007-05-18 01:28:58 +00:00
0f745da4fe
Make use of target specific block size limits; bug fixes.
...
llvm-svn: 37195
2007-05-18 00:20:58 +00:00
a92b2b38ff
Move isSuccessor() offline, change it to use std::find.
...
llvm-svn: 37190
2007-05-17 23:58:53 +00:00
0184f88deb
disable MaskedValueIsZero, ComputeMaskedBits, and SimplifyDemandedBits for
...
i128 integers. The 64-bit masks are not wide enough to represent the results.
These should be converted to APInt someday.
llvm-svn: 37169
2007-05-17 18:19:23 +00:00
2135bc08d6
add expand support for ADDC/SUBC/ADDE/SUBE so we can codegen 128-bit add/sub on 32-bit (or less) targets
...
llvm-svn: 37168
2007-05-17 18:15:41 +00:00
429178d727
Add target hook to specify block size limit for if-conversion.
...
llvm-svn: 37134
2007-05-16 23:45:53 +00:00
7a6c175e7a
Don't fold bitconvert(load) for preinc/postdec loads. Likewise stores.
...
llvm-svn: 37130
2007-05-16 22:45:30 +00:00
af71610429
isBlockPredicable() always ignore terminal instructions; add comments.
...
llvm-svn: 37126
2007-05-16 21:54:37 +00:00
5ea933a009
Rename M_PREDICATED to M_PREDICABLE; Moved isPredicable() to MachineInstr.
...
llvm-svn: 37121
2007-05-16 20:56:08 +00:00
59ae77486c
Output exception call-sites in address order, as required by the unwinding
...
runtime.
llvm-svn: 37104
2007-05-16 12:12:23 +00:00
48fb92f75d
Use a ptr set instead of a linear search to unique TokenFactor operands.
...
This fixes PR1423
llvm-svn: 37102
2007-05-16 06:37:59 +00:00
35fc2119b0
Devang points out that we need an assertion here.
...
llvm-svn: 37097
2007-05-16 05:11:10 +00:00
288f133c71
Bug fix: should check ABI alignment, not pref. alignment.
...
llvm-svn: 37094
2007-05-16 02:04:50 +00:00
f5e53a58db
Initial commit of (very basic) if converter.
...
llvm-svn: 37092
2007-05-16 02:00:57 +00:00
420a85d0cf
Remove extra CFG edges before doing these passes; it makes them happier.
...
llvm-svn: 37089
2007-05-15 21:19:17 +00:00
3f142cbca2
Fix an infinite recursion in GetNegatedExpression.
...
llvm-svn: 37086
2007-05-15 17:05:43 +00:00
750e8c5d4d
The index into the actions table is a ULEB128 not a SLEB128.
...
llvm-svn: 37084
2007-05-15 13:54:14 +00:00
daed139420
Un-brain-dead-ify the lowering of part set for the reverse case.
...
llvm-svn: 37071
2007-05-15 02:26:52 +00:00
c7596efdad
Fix some subtle issues handling immediate values. This fixes
...
test/CodeGen/ARM/2007-05-14-InlineAsmCstCrash.ll
llvm-svn: 37069
2007-05-15 01:33:58 +00:00
4d728b0419
Added getNumExplicitOperands and findFirstPredOperand.
...
llvm-svn: 37064
2007-05-15 01:26:09 +00:00
e49c974a7c
implement a simple fneg optimization/propagation thing. This compiles:
...
CodeGen/PowerPC/fneg.ll into:
_t4:
fmul f0, f3, f4
fmadd f1, f1, f2, f0
blr
instead of:
_t4:
fneg f0, f3
fmul f0, f0, f4
fmsub f1, f1, f2, f0
blr
llvm-svn: 37054
2007-05-14 22:04:50 +00:00
e1595b6859
Only worry about intervening kill if there are more than one live ranges in the interval.
...
llvm-svn: 37052
2007-05-14 21:23:51 +00:00
c690cba7d9
Fix for PR1406:
...
v1 =
r2 = move v1
= op r2<kill>
...
r2 = move v1
= op r2<kill>
Clear the first r2 kill if v1 and r2 are joined.
llvm-svn: 37050
2007-05-14 21:10:05 +00:00
fc2377d4ed
When marking a register as being implicitly defined, make sure to clear its partial use info as well.
...
llvm-svn: 37046
2007-05-14 20:39:18 +00:00
764ae2a21b
Give names to the final result values of the part_set computations. This
...
just aids in readability and debugability of the output. No functional change.
llvm-svn: 37037
2007-05-14 17:21:17 +00:00
1ee0c8d563
Emit function debug frames in one atom. This will prevent us from generating incorrect assembler in case of both
...
debug information & exception information presented.
llvm-svn: 37019
2007-05-13 17:30:11 +00:00
bbaf55448b
Emit multiple common EH frames for multiple (including blank) personality
...
functions. This partly fixes PR1414: now we're restricted only to one
personality function per eh frame, not per module. Further work on
"multiple personalities" topic needs representative example.
llvm-svn: 37018
2007-05-13 15:42:26 +00:00
13da17843c
More DWARF-related things cleanup:
...
1. Fix PR1380
2. Apply Duncan's patch from PR1410
3. Insert workaround for "one personality function per module" as noted in PR1414
4. Emit correct debug frames for x86/linux. This partly fixes DebugInfo/2006-11-06-StackTrace.cpp: stack trace is
shown correctly, but arguments for function on top of stack are displayed incorrectly.
llvm-svn: 37015
2007-05-12 22:36:25 +00:00
bf283708f7
Get the size of auto arrays right, regardless of its changing size.
...
llvm-svn: 37006
2007-05-12 11:07:40 +00:00
79a71ec3ad
Fix http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20070507/049516.html
...
llvm-svn: 36998
2007-05-11 23:14:43 +00:00
67286b1266
Perform correct actions numbers/sizes computation
...
llvm-svn: 36988
2007-05-11 08:47:35 +00:00
00d02442b0
Fix action No calculation in multiple-invoke-one-LP mode
...
llvm-svn: 36987
2007-05-11 08:23:57 +00:00
cc8f571bc8
Do not generate branches to entry block. This fixes several test suite
...
failures on PPC (can happen only when prologue code is null)
llvm-svn: 36979
2007-05-10 23:59:23 +00:00
ee02c7d2fb
Ooops. Some debugging stuff :)
...
llvm-svn: 36978
2007-05-10 22:38:46 +00:00
96142de3f0
Allow multiple invokes per landing pad. This (probably) fixes PR1410.
...
llvm-svn: 36977
2007-05-10 22:34:59 +00:00
b43fe52136
Later computations assume we are aligned at this point.
...
llvm-svn: 36975
2007-05-10 18:40:24 +00:00
ed5dad4306
TypeIds are indexed by j, not i
...
llvm-svn: 36974
2007-05-10 15:10:34 +00:00
6e16d09252
Make tail merging handle many more cases (all it can, I think).
...
llvm-svn: 36966
2007-05-10 01:01:49 +00:00
f325c2a65e
Can't fold the bit_convert is the store is a truncating store.
...
llvm-svn: 36962
2007-05-09 21:49:47 +00:00
192d09c2d9
Do not assert, when case range split metric is zero and JTs are not allowed: just emit binary tree in this case. This
...
fixes PR1403.
llvm-svn: 36959
2007-05-09 20:07:08 +00:00
31fd60ba0c
Change names from RA to something unique to get rid of naming conflicts with
...
certain linkers...
llvm-svn: 36944
2007-05-08 19:02:46 +00:00
9e17872c1d
Eliminate MarkVirtRegAliveInBlock recursion.
...
llvm-svn: 36943
2007-05-08 19:00:00 +00:00
562e45692e
Forgot a check.
...
llvm-svn: 36910
2007-05-07 21:36:06 +00:00
a4cf58a103
Enable a couple of xforms:
...
- (store (bitconvert v)) -> (store v) if resultant store does not require
higher alignment
- (bitconvert (load v)) -> (load (bitconvert*)v) if resultant load does not
require higher alignment
llvm-svn: 36908
2007-05-07 21:27:48 +00:00
9a25b3afcd
Handle some non-exit blocks in tail merging.
...
llvm-svn: 36907
2007-05-07 20:57:21 +00:00
671e8c4444
Parameter attributes on invoke calls were being lost due to the wrong
...
attribute index being used. Fix proposed by Anton Korobeynikov, who
asked me to implement and commit it for him. This is PR1398.
llvm-svn: 36906
2007-05-07 20:49:28 +00:00
a8fd7fdc25
Detabify
...
llvm-svn: 36891
2007-05-06 20:14:21 +00:00
e7da2d6ac3
Fix typo in comment.
...
llvm-svn: 36873
2007-05-06 13:37:16 +00:00
00282a21a5
Use the personality function that was registered with MMI rather than
...
hardwiring in the C++ one.
llvm-svn: 36789
2007-05-05 20:27:00 +00:00
07e6f3257c
Propagate alignment/volatility in two places.
...
Implement support for expanding a bitcast from an illegal vector type to
a legal one (e.g. 4xi32 -> 4xf32 in SSE1). This fixes PR1371 and
CodeGen/X86/2007-05-05-VecCastExpand.ll
llvm-svn: 36787
2007-05-05 19:39:05 +00:00
02528f5425
Spelling fix.
...
llvm-svn: 36781
2007-05-05 16:32:57 +00:00
4db0090339
Emit sections/directives in the proper order. This fixes PR1376. Also,
...
some small cleanup was made.
llvm-svn: 36780
2007-05-05 09:04:50 +00:00
4cb9eb81ef
A bitcast of a global variable may have been constant folded to a GEP -
...
handle this case too.
llvm-svn: 36745
2007-05-04 17:12:26 +00:00
044a0a8cfb
Don't create indexed load / store with zero offset!
...
llvm-svn: 36716
2007-05-03 23:52:19 +00:00
44a2ed66b1
Allow i/s to match (gv+c). This fixes CodeGen/PowerPC/2007-05-03-InlineAsm-S-Constraint.ll
...
and PR1382
llvm-svn: 36672
2007-05-03 16:54:34 +00:00
8c78a0bff0
Drop 'const'
...
llvm-svn: 36662
2007-05-03 01:11:54 +00:00
11940fbba3
Properly set arguments bitwidth of EHSELECT node
...
llvm-svn: 36654
2007-05-02 22:15:48 +00:00
e95c6ad802
Use 'static const char' instead of 'static const int'.
...
Due to darwin gcc bug, one version of darwin linker coalesces
static const int, which defauts PassID based pass identification.
llvm-svn: 36652
2007-05-02 21:39:20 +00:00
41223586a2
Fix build error.
...
llvm-svn: 36648
2007-05-02 20:37:47 +00:00
b538f67b1a
Fix couple of bugs connected with eh info:
...
1. Correct output offsets on Linux
2. Fix "style" of personality function. It shouldn't be indirect.
llvm-svn: 36633
2007-05-01 22:23:12 +00:00
09f162ca6a
Do not use typeinfo to identify pass in pass manager.
...
llvm-svn: 36632
2007-05-01 21:15:47 +00:00
8cd28f0fb1
If call frame is not part of stack frame and no dynamic alloc, eliminateFrameIndex() must adjust SP offset with size of call frames.
...
llvm-svn: 36625
2007-05-01 09:01:42 +00:00
b68343cdd8
Forgot about chain result; also UNDEF cannot have multiple values.
...
llvm-svn: 36622
2007-05-01 08:53:39 +00:00
27a625a74b
llvm bug #1350 , parts 1, 2, and 3.
...
llvm-svn: 36618
2007-05-01 05:57:02 +00:00
77c545e6b8
Under normal circumstances, when a frame pointer is not required, we reserve
...
argument space for call sites in the function immediately on entry to the
current function. This eliminates the need for add/sub sp brackets around call
sites. However, this is not always a good idea. If the "call frame" is large and
the target load / store instructions have small immediate field to encode sp
offset, this can cause poor codegen. In the worst case, this can make it
impossible to scavenge a register if the reserved spill slot is pushed too far
apart from sp / fp.
llvm-svn: 36607
2007-05-01 00:52:08 +00:00
a684cd23a5
* Only turn a load to UNDEF if all of its outputs have no uses (indexed loads
...
produce two results.)
* Do not touch volatile loads.
llvm-svn: 36604
2007-05-01 00:38:21 +00:00
4dbbace4ff
Fix PR1228 and CodeGen/Generic/2007-04-30-LandingPadBranchFolding.ll
...
llvm-svn: 36602
2007-04-30 23:35:00 +00:00
f90c8fbd2b
print isLandingPad() for MBBs
...
llvm-svn: 36600
2007-04-30 23:12:53 +00:00
8cfd33b647
Continue refactoring inline asm code. If there is an earlyclobber output
...
register, preallocate all input registers and the early clobbered output.
This fixes PR1357 and CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll
llvm-svn: 36599
2007-04-30 21:11:17 +00:00
6b77c3ed52
Updates.
...
llvm-svn: 36594
2007-04-30 18:42:09 +00:00
4333f8b1cf
refactor GetRegistersForValue to take OpInfo as an argument instead of various
...
pieces of it. No functionality change.
llvm-svn: 36592
2007-04-30 17:29:31 +00:00
ef07332504
refactor some code, no functionality change
...
llvm-svn: 36590
2007-04-30 17:16:27 +00:00
b58f93f273
Clean up multi-line asam string printing. Instead of printing:
...
# InlineAsm Start
subfc r3,r5,r4
subfze r4,r3
# InlineAsm End
print:
# InlineAsm Start
subfc r3,r5,r4
subfze r4,r3
# InlineAsm End
llvm-svn: 36589
2007-04-30 17:00:18 +00:00
412d61af43
generalize aggregate handling
...
llvm-svn: 36568
2007-04-29 18:58:03 +00:00
546ea7ea88
Implement review feedback
...
llvm-svn: 36564
2007-04-29 18:02:48 +00:00
401d8db381
memory operands that have a direct operand should have their stores created
...
before the copies into physregs are done. This avoids having flag operands
skip the store, causing cycles in the dag at sched time. This fixes infinite
loops on these tests:
test/CodeGen/Generic/2007-04-08-MultipleFrameIndices.ll for PR1308
test/CodeGen/PowerPC/2007-01-29-lbrx-asm.ll
test/CodeGen/PowerPC/2007-01-31-InlineAsmAddrMode.ll
test/CodeGen/X86/2006-07-12-InlineAsmQConstraint.ll for PR828
llvm-svn: 36547
2007-04-28 21:12:06 +00:00
de339fa55d
eliminate more redundant constraint type analysis
...
llvm-svn: 36546
2007-04-28 21:03:16 +00:00
b2e55562ed
merge constraint type analysis stuff together.
...
llvm-svn: 36545
2007-04-28 21:01:43 +00:00
d7e3b6c442
Significant refactoring of the inline asm stuff, to support future changes.
...
No functionality change.
llvm-svn: 36544
2007-04-28 20:49:53 +00:00
b18f8f85e9
Implement review feedback. Aliasees can be either GlobalValue's or
...
bitcasts of them.
llvm-svn: 36537
2007-04-28 13:45:00 +00:00
1deacd61f4
memory inputs to an inline asm are required to have an address available.
...
If the operand is not already an indirect operand, spill it to a constant
pool entry or a stack slot.
This fixes PR1356 and CodeGen/X86/2007-04-27-InlineAsm-IntMemInput.ll
llvm-svn: 36536
2007-04-28 06:42:38 +00:00
d102ed0ac6
Fix CodeGen/Generic/2007-04-27-LargeMemObject.ll and
...
CodeGen/Generic/2007-04-27-InlineAsm-X-Dest.ll
llvm-svn: 36534
2007-04-28 06:08:13 +00:00
4df3e8093b
Fix this to match change to InlineAsm class.
...
llvm-svn: 36524
2007-04-28 04:05:59 +00:00
1cbe208cda
Fix incorrect legalization of EHSELECTOR. This fixes
...
CodeGen/Generic/2007-04-14-EHSelectorCrash.ll and PR1326
llvm-svn: 36510
2007-04-27 17:12:52 +00:00
bf535fc8bd
Expand UINT_TO_FP in turns of SINT_TO_FP when UINTTOFP_* libcalls are not available.
...
llvm-svn: 36501
2007-04-27 07:33:31 +00:00
784fe9dbbb
improve EH global handling, patch by Duncan Sands.
...
llvm-svn: 36499
2007-04-27 01:20:11 +00:00
8131ab7c0f
enable Anton's shift/and switch lowering stuff! It now passes ppc bootstrap
...
successfully! woohoo...
llvm-svn: 36496
2007-04-26 21:09:43 +00:00
d7ae7f1659
Fixx off-by-one bug, which prevents llvm-gcc bootstrap on ppc32
...
llvm-svn: 36490
2007-04-26 20:44:04 +00:00
e131e3ac02
Fix a typo in a comment.
...
llvm-svn: 36485
2007-04-26 19:40:56 +00:00
910c80851e
Rename findRegisterUseOperand to findRegisterUseOperandIdx to avoid confusion.
...
llvm-svn: 36483
2007-04-26 19:00:32 +00:00
ed23a1387e
Minor bug.
...
llvm-svn: 36473
2007-04-26 08:24:22 +00:00
43a17fe826
Be careful when to add implicit kill / dead operands. Don't add them during / post reg-allocation.
...
llvm-svn: 36458
2007-04-26 01:40:09 +00:00
0ba174534c
Match MachineFunction::UsedPhysRegs changes.
...
llvm-svn: 36452
2007-04-25 22:13:27 +00:00
d21968d11a
Change UsedPhysRegs from array bool to BitVector to save some space. Setting / getting its states now go through MachineFunction.
...
llvm-svn: 36451
2007-04-25 22:10:09 +00:00
d4549c5527
Clean up.
...
llvm-svn: 36449
2007-04-25 21:34:08 +00:00
0fbe14ab87
Data structure change to improve compile time (especially in debug mode).
...
llvm-svn: 36447
2007-04-25 19:34:00 +00:00
15f269afa3
This was lefted out. Fixed sumarray-dbl.
...
llvm-svn: 36445
2007-04-25 18:33:21 +00:00
a97b694c82
Implement aliases. This fixes PR1017 and it's dependent bugs. CFE part
...
will follow.
llvm-svn: 36435
2007-04-25 14:27:10 +00:00
7818c03c6b
Fix for PR1306.
...
- A register def / use now implicitly affects sub-register liveness but does
not affect liveness information of super-registers.
- Def of a larger register (if followed by a use later) is treated as
read/mod/write of a smaller register.
llvm-svn: 36434
2007-04-25 07:30:23 +00:00
11dc5abde1
Clean up.
...
llvm-svn: 36431
2007-04-25 07:18:20 +00:00
b975bebec1
support for >4G stack frames
...
llvm-svn: 36425
2007-04-25 04:30:24 +00:00
9bd98ea4c1
support > 4G stack objects
...
llvm-svn: 36422
2007-04-25 04:20:54 +00:00
cb0ed0cfbd
allow support for 64-bit stack objects
...
llvm-svn: 36420
2007-04-25 04:08:28 +00:00
01a26c74ae
Be more careful about folding op(x, undef) when we have vector operands.
...
This fixes CodeGen/X86/2007-04-24-VectorCrash.ll
llvm-svn: 36413
2007-04-25 00:00:45 +00:00
47917b697f
Assertion when using a 1-element vector for an add operation. Get the
...
real vector type in this case.
llvm-svn: 36402
2007-04-24 21:13:23 +00:00
4cfa616cee
Use '-1U' where '-1UL' is obvious overkill, eliminating gcc warnings about
...
tests always being true in the process.
llvm-svn: 36387
2007-04-24 01:24:20 +00:00
8653d29b45
modify per review commentary
...
llvm-svn: 36383
2007-04-23 23:33:31 +00:00
14a28f13c8
make EmitAlignment work the way Chris says it should
...
llvm-svn: 36368
2007-04-23 19:58:54 +00:00
8af6d5896f
PR400 phase 2. Propagate attributed load/store information through DAGs.
...
llvm-svn: 36356
2007-04-22 23:15:30 +00:00
4e91908f17
X86 TLS: Implement review feedback.
...
llvm-svn: 36318
2007-04-21 20:56:26 +00:00
0c1349e6bc
Revert Christopher Lamb's load/store alignment changes.
...
llvm-svn: 36309
2007-04-21 18:36:27 +00:00
bff50208c8
add support for alignment attributes on load/store instructions
...
llvm-svn: 36301
2007-04-21 08:16:25 +00:00
94314be0e0
Allow the lowering of ISD::GLOBAL_OFFSET_TABLE.
...
llvm-svn: 36290
2007-04-20 23:02:39 +00:00
2518889872
Implement "general dynamic", "initial exec" and "local exec" TLS models for
...
X86 32 bits.
llvm-svn: 36283
2007-04-20 21:38:10 +00:00
4c53d321aa
VarInfo::UsedBlocks is no longer used. Remove.
...
llvm-svn: 36250
2007-04-18 05:04:38 +00:00
f03c90bee6
allow SRL to simplify its operands, as it doesn't demand all bits as input.
...
llvm-svn: 36245
2007-04-18 03:06:49 +00:00
bf14f20632
When replacing a node in SimplifyDemandedBits, if the old node used any
...
single-use nodes, they will be dead soon. Make sure to remove them before
processing other nodes. This implements CodeGen/X86/shl_elim.ll
llvm-svn: 36244
2007-04-18 03:05:22 +00:00
15c1b820cc
fix a pasto
...
llvm-svn: 36242
2007-04-18 03:01:40 +00:00
b408e8f11d
Don't populate TryAgainList when coalescing only physical registers with virtual registers.
...
llvm-svn: 36240
2007-04-18 02:30:19 +00:00
a5a0c7c909
Increment use count of new virtuals created during PHI elimination.
...
llvm-svn: 36233
2007-04-18 00:36:11 +00:00
4aff52bf3d
Fix a bug in my previous patch, grabbing the shift amount width from the
...
wrong operand.
llvm-svn: 36223
2007-04-17 22:53:02 +00:00
9a861a8550
Fold (x << c1)>> c2 into a single shift if the bits shifted out aren't used.
...
This compiles:
int baz(long long a) { return (short)(((int)(a >>24)) >> 9); }
into:
_baz:
srwi r2, r3, 1
extsh r3, r2
blr
on PPC, instead of:
_baz:
slwi r2, r3, 8
srwi r2, r2, 9
extsh r3, r2
blr
GCC produces:
_baz:
srwi r10,r4,24
insrwi r10,r3,24,0
srawi r9,r3,24
srawi r3,r10,9
extsh r3,r3
blr
This implements CodeGen/PowerPC/shl_elim.ll
llvm-svn: 36221
2007-04-17 21:14:16 +00:00
b881bdabd9
Copy coalescing change to prevent a physical register from being pin to a
...
long live interval that has low usage density.
1. Change order of coalescing to join physical registers with virtual
registers first before virtual register intervals become too long.
2. Check size and usage density to determine if it's worthwhile to join.
3. If joining is aborted, assign virtual register live interval allocation
preference field to the physical register.
4. Register allocator should try to allocate to the preferred register
first (if available) to create identify moves that can be eliminated.
llvm-svn: 36218
2007-04-17 20:32:26 +00:00
57b5214d59
Add a register allocation preference field; add a method to compute size of a live interval.
...
llvm-svn: 36216
2007-04-17 20:25:11 +00:00
8387cf1100
Keep track of number of uses within the function per virtual register.
...
llvm-svn: 36214
2007-04-17 20:22:11 +00:00
9ad5915559
SIGN_EXTEND_INREG does not demand its top bits. Give SimplifyDemandedBits
...
a chance to hack on it. This compiles:
int baz(long long a) { return (short)(((int)(a >>24)) >> 9); }
into:
_baz:
slwi r2, r3, 8
srwi r2, r2, 9
extsh r3, r2
blr
instead of:
_baz:
srwi r2, r4, 24
rlwimi r2, r3, 8, 0, 23
srwi r2, r2, 9
extsh r3, r2
blr
This implements CodeGen/PowerPC/sign_ext_inreg1.ll
llvm-svn: 36212
2007-04-17 19:03:21 +00:00
58ec791b4c
Fix problems in the PartSet lowering having to do with incorrect bit width.
...
llvm-svn: 36180
2007-04-16 22:21:14 +00:00
fb80151c42
Removed tabs everywhere except autogenerated & external files. Add make
...
target for tabs checking.
llvm-svn: 36146
2007-04-16 18:10:23 +00:00
6bd7b7b30b
disable switch lowering using shift/and. It still breaks ppc bootstrap for
...
some reason. :( Will investigate.
llvm-svn: 36011
2007-04-14 19:39:41 +00:00
8a1a84f96e
Fix PR1325: Case range optimization was performed in the case it
...
shouldn't. Also fix some "latent" bug on 64-bit platforms
llvm-svn: 35990
2007-04-14 13:25:55 +00:00
7196f09edc
disable shift/and lowering to work around PR1325 for now.
...
llvm-svn: 35985
2007-04-14 02:26:56 +00:00
e288040abf
Fix PR1323 : we haven't updated phi nodes in good manner :)
...
llvm-svn: 35963
2007-04-13 06:53:51 +00:00
1b9213730f
Make sure intrinsics that are lowered to functions make the function weak
...
linkage so we only end up with one of them in a program. These are, after
all overloaded and templatish in nature.
llvm-svn: 35956
2007-04-12 21:53:38 +00:00
0f2f65f723
Fix bugs in generated code for part_select and part_set so that llc doesn't
...
barf when CBE is run with a program that contains these intrinsics.
llvm-svn: 35946
2007-04-12 13:30:14 +00:00
83faeb7611
Fix a bug in PartSet. The replacement value needs to be zext or trunc to
...
the size of the value, not just zext. Also, give better names to two BBs.
llvm-svn: 35945
2007-04-12 12:46:33 +00:00
5111499136
the result of an inline asm copy can be an arbitrary VT that the register
...
class supports. In the case of vectors, this means we often get the wrong
type (e.g. we get v4f32 instead of v8i16). Make sure to convert the vector
result to the right type. This fixes CodeGen/X86/2007-04-11-InlineAsmVectorResult.ll
llvm-svn: 35944
2007-04-12 06:00:20 +00:00
a77cb3ce68
fold noop vbitconvert instructions
...
llvm-svn: 35943
2007-04-12 05:58:43 +00:00
784a68a702
Fix weirdness handling single element vectors.
...
llvm-svn: 35941
2007-04-12 04:44:28 +00:00
c6251a7dfd
For PR1284:
...
Implement the "part_set" intrinsic.
llvm-svn: 35938
2007-04-12 02:48:46 +00:00
18e4ac4107
fix an infinite loop compiling ldecod, notice by JeffC.
...
llvm-svn: 35910
2007-04-11 16:51:53 +00:00
a083ffcad7
Fix this harder.
...
llvm-svn: 35888
2007-04-11 06:50:51 +00:00
c5f85d3738
don't create shifts by zero, fix some problems with my previous patch
...
llvm-svn: 35887
2007-04-11 06:43:25 +00:00
65786b078c
Teach the codegen to turn [aez]ext (setcc) -> selectcc of 1/0, which often
...
allows other simplifications. For example, this compiles:
int isnegative(unsigned int X) {
return !(X < 2147483648U);
}
Into this code:
x86:
movl 4(%esp), %eax
shrl $31, %eax
ret
arm:
mov r0, r0, lsr #31
bx lr
thumb:
lsr r0, r0, #31
bx lr
instead of:
x86:
cmpl $0, 4(%esp)
sets %al
movzbl %al, %eax
ret
arm:
mov r3, #0
cmp r0, #0
movlt r3, #1
mov r0, r3
bx lr
thumb:
mov r2, #1
mov r1, #0
cmp r0, #0
blt LBB1_2 @entry
LBB1_1: @entry
cpy r2, r1
LBB1_2: @entry
cpy r0, r2
bx lr
Testcase here: test/CodeGen/Generic/ispositive.ll
llvm-svn: 35883
2007-04-11 05:32:27 +00:00
41189c63cc
Codegen integer abs more efficiently using the trick from the PPC CWG. This
...
improves codegen on many architectures. Tests committed as CodeGen/*/iabs.ll
X86 Old: X86 New:
_test: _test:
movl 4(%esp), %ecx movl 4(%esp), %eax
movl %ecx, %eax movl %eax, %ecx
negl %eax sarl $31, %ecx
testl %ecx, %ecx addl %ecx, %eax
cmovns %ecx, %eax xorl %ecx, %eax
ret ret
PPC Old: PPC New:
_test: _test:
cmpwi cr0, r3, -1 srawi r2, r3, 31
neg r2, r3 add r3, r3, r2
bgt cr0, LBB1_2 ; xor r3, r3, r2
LBB1_1: ; blr
mr r3, r2
LBB1_2: ;
blr
ARM Old: ARM New:
_test: _test:
rsb r3, r0, #0 add r3, r0, r0, asr #31
cmp r0, #0 eor r0, r3, r0, asr #31
movge r3, r0 bx lr
mov r0, r3
bx lr
Thumb Old: Thumb New:
_test: _test:
neg r2, r0 asr r2, r0, #31
cmp r0, #0 add r0, r0, r2
bge LBB1_2 eor r0, r2
LBB1_1: @ bx lr
cpy r0, r2
LBB1_2: @
bx lr
Sparc Old: Sparc New:
test: test:
save -96, %o6, %o6 save -96, %o6, %o6
sethi 0, %l0 sra %i0, 31, %l0
sub %l0, %i0, %l0 add %i0, %l0, %l1
subcc %i0, -1, %l1 xor %l1, %l0, %i0
bg .BB1_2 restore %g0, %g0, %g0
nop retl
.BB1_1: nop
or %g0, %l0, %i0
.BB1_2:
restore %g0, %g0, %g0
retl
nop
It also helps alpha/ia64 :)
llvm-svn: 35881
2007-04-11 05:11:38 +00:00
a472f66dd0
For PR1146:
...
Put the parameter attributes in their own ParamAttr name space. Adjust the
rest of llvm as a result.
llvm-svn: 35877
2007-04-11 02:44:20 +00:00
f269d84ca0
apparently some people commit without building the tree, or they forget to
...
commit a LOT of files.
llvm-svn: 35858
2007-04-10 03:20:39 +00:00
e0bbbd3774
No longer needed.
...
llvm-svn: 35850
2007-04-09 23:42:32 +00:00
35f0417ec1
remove dead target hooks.
...
llvm-svn: 35847
2007-04-09 23:34:08 +00:00
39f65335d5
remove some dead target hooks, subsumed by isLegalAddressingMode
...
llvm-svn: 35840
2007-04-09 22:27:04 +00:00
da964a2852
Use integer log for metric calculation
...
llvm-svn: 35834
2007-04-09 21:57:03 +00:00
0475f3b4e9
Unbreak VC++ build.
...
llvm-svn: 35817
2007-04-09 14:32:59 +00:00
506eaf7915
Next stage into switch lowering refactoring
...
1. Fix some bugs in the jump table lowering threshold
2. Implement much better metric for optimal pivot selection
3. Tune thresholds for different lowering methods
4. Implement shift-and trick for lowering small (<machine word
length) cases with few destinations. Good testcase will follow.
llvm-svn: 35816
2007-04-09 12:31:58 +00:00
71b79e3d99
For PR1146:
...
Adapt handling of parameter attributes to use the new ParamAttrsList class.
llvm-svn: 35814
2007-04-09 06:17:21 +00:00
7b2decfa0a
implement CodeGen/X86/inline-asm-x-scalar.ll:test3
...
llvm-svn: 35802
2007-04-09 05:31:20 +00:00
18d6718e78
add some assertions
...
llvm-svn: 35800
2007-04-09 05:23:13 +00:00
f73d215023
Fix a bug introduced with my previous patch, where it didn't correctly handle
...
instructions which replace themselves when FI's are rewritten (common on ppc).
This fixes CodeGen/PowerPC/2006-10-17-ppc64-alloca.ll
llvm-svn: 35789
2007-04-09 01:19:33 +00:00
0df5357436
Fix CodeGen/Generic/2007-04-08-MultipleFrameIndices.ll and PR1308:
...
some instructions can have multiple frame indices in them. If this happens,
rewrite all of them.
llvm-svn: 35785
2007-04-09 00:46:10 +00:00
b49917da92
Fix PR1316
...
llvm-svn: 35783
2007-04-09 00:33:58 +00:00
e55ecfb870
Fix for CodeGen/X86/2007-04-08-InlineAsmCrash.ll and PR1314
...
llvm-svn: 35779
2007-04-08 22:23:26 +00:00
1c741e95d3
minor comment fix
...
llvm-svn: 35696
2007-04-06 17:47:14 +00:00
85460acfbf
Change the bit_part_select (non)implementation from "return 0" to abort.
...
llvm-svn: 35679
2007-04-05 01:20:18 +00:00
cce90f55ed
Implement the llvm.bit.part_select.iN.iN.iN overloaded intrinsic.
...
llvm-svn: 35678
2007-04-04 23:48:25 +00:00
915e61736b
Properly emit range comparisons for switch cases, where neighbour cases
...
go to the same destination. Now we're producing really good code for
switch-lower-feature.ll testcase
llvm-svn: 35672
2007-04-04 21:14:49 +00:00
8be98c1572
Re-materialize all loads from fixed stack slots.
...
llvm-svn: 35660
2007-04-04 07:40:01 +00:00
2bf2aadd9a
Trivially re-materializable instructions have spill weights that are half of what it would be otherwise.
...
llvm-svn: 35658
2007-04-04 07:04:55 +00:00
06a7041ff9
Bad bad bug. findRegisterUseOperand() returns -1 if a use if not found.
...
llvm-svn: 35618
2007-04-03 06:43:29 +00:00
16627a542f
1. Insert custom lowering hooks for ISD::ROTR and ISD::ROTL.
...
2. Help DAGCombiner recognize zero/sign/any-extended versions of ROTR and ROTL
patterns. This was motivated by the X86/rotate.ll testcase, which should now
generate code for other platforms (and soon-to-come platforms.) Rewrote code
slightly to make it easier to read.
llvm-svn: 35605
2007-04-02 21:36:32 +00:00
476fb6a5c9
Ugh. Copy coalescer does not update register numbers.
...
llvm-svn: 35600
2007-04-02 18:49:18 +00:00
fad9bd6b92
For PR1297:
...
Make sure that the CTPOP result is casted to i32 as the bit counting
intrinsics all return i32 now (this affects CTLZ and CTTZ as well).
llvm-svn: 35567
2007-04-02 01:01:49 +00:00
6bba6c8143
For PR1297:
...
Support overloaded intrinsics bswap, ctpop, cttz, ctlz.
llvm-svn: 35547
2007-04-01 07:35:23 +00:00
3a0843e734
For PR1297:
...
Adjust for changes in the bit counting intrinsics. They all return i32
now so we have to trunc/zext the DAG node accordingly.
llvm-svn: 35546
2007-04-01 07:34:11 +00:00
a090ffb2ab
For PR1297:
...
Change getOperationName to return std::string instead of const char*
llvm-svn: 35545
2007-04-01 07:32:19 +00:00
f6a6d3c8b0
move a bunch of code out of the sdisel pass into its own opt pass "codegenprepare".
...
llvm-svn: 35529
2007-03-31 04:18:03 +00:00
f2d71d49e2
switch TL::getValueType to use MVT::getValueType.
...
llvm-svn: 35527
2007-03-31 04:05:24 +00:00
bafc837c83
Add a -print-lsr-output option to LLC, to print the output of the LSR pass.
...
llvm-svn: 35522
2007-03-31 00:24:43 +00:00
ac3f81508c
add one addressing mode description hook to rule them all.
...
llvm-svn: 35520
2007-03-30 23:14:50 +00:00
4bbd2eefba
Fix incorrect combination of different loads. Reenable zext-over-truncate
...
combination.
llvm-svn: 35517
2007-03-30 21:38:07 +00:00
9a2a7b174a
Don't add the same MI to register reuse "last def/use" twice if it reads the
...
register more than once.
llvm-svn: 35513
2007-03-30 20:21:35 +00:00
48dd5e7d44
Bug fix for PR1279. When isDead is propagate by copy coalescing, we keep length
...
of dead def live interval at 1 to avoid multiple def's targeting the same
register. The previous patch missed a case where the source operand is live-in.
In that case, remove the whole interval.
llvm-svn: 35512
2007-03-30 20:18:35 +00:00
ccee35fd0d
Disable load width reduction xform of variant (zext (truncate load x)) for
...
big endian targets until llvm-gcc build issue has been resolved.
llvm-svn: 35449
2007-03-29 07:56:46 +00:00
86de3a009d
New entries.
...
llvm-svn: 35445
2007-03-29 02:48:56 +00:00
d771485d89
Notes on re-materialization.
...
llvm-svn: 35420
2007-03-28 08:30:04 +00:00
603e49c6da
Move rematerialization out of beta.
...
llvm-svn: 35419
2007-03-28 08:26:40 +00:00
4388043b25
Scale 1 is always ok.
...
llvm-svn: 35407
2007-03-28 01:55:52 +00:00
c2cba18f2b
Remove isLegalAddressImmediate.
...
llvm-svn: 35406
2007-03-28 01:53:55 +00:00
07c42d43a2
GEP index sinking fixes:
...
1) Take address scale into consideration. e.g. i32* -> scale 4.
2) Examine all the users of GEP.
3) Generalize to inter-block GEP's (no longer uses loopinfo).
4) Don't do xform if GEP has other variable index(es).
llvm-svn: 35403
2007-03-28 01:49:39 +00:00
b41697c006
Fix for PR1279. Dead def has a live interval of length 1. Copy coalescing should
...
not violate that.
llvm-svn: 35396
2007-03-28 01:30:37 +00:00
37a0bfe128
Remove dead code
...
llvm-svn: 35380
2007-03-27 12:05:48 +00:00
3a9d68181a
Split big monster into small helpers. No functionality change.
...
llvm-svn: 35379
2007-03-27 11:29:11 +00:00
c42406b5ad
SDISel does not preserve all, it changes CFG and other info.
...
llvm-svn: 35376
2007-03-27 00:53:36 +00:00
fdbdf43632
Don't call getOperandConstraint() if operand index is greater than
...
TID->numOperands.
llvm-svn: 35375
2007-03-27 00:48:28 +00:00
4a09b1b5be
Fix for PR1266. Don't mark a two address operand IsKill.
...
llvm-svn: 35365
2007-03-26 22:40:42 +00:00
ec3ac316e2
Change findRegisterUseOperand() to return operand index instead.
...
llvm-svn: 35363
2007-03-26 22:37:45 +00:00
fd18a0cdf4
Fix reversed logic in getRegsUsed. Rename RegStates to RegsAvailable to
...
hopefully forestall similar errors.
llvm-svn: 35362
2007-03-26 22:23:54 +00:00
8275f0e0af
SIGN_EXTEND_INREG requires one extra operand, a ValueType node.
...
llvm-svn: 35350
2007-03-26 07:12:51 +00:00
7037826c86
First step of switch lowering refactoring: perform worklist-driven
...
strategy, emit JT's where possible.
llvm-svn: 35338
2007-03-25 15:07:15 +00:00
77f0479833
Implement support for vector operands to inline asm, implementing
...
CodeGen/X86/2007-03-24-InlineAsmVectorOp.ll
llvm-svn: 35332
2007-03-25 05:00:54 +00:00
3d7efa2586
implement initial support for the silly X constraint. Testcase here: CodeGen/X86/2007-03-24-InlineAsmXConstraint.ll
...
llvm-svn: 35327
2007-03-25 04:35:41 +00:00
843e44503c
Implement CodeGen/X86/2007-03-24-InlineAsmMultiRegConstraint.ll
...
llvm-svn: 35324
2007-03-25 02:18:14 +00:00
d685514e2e
switch TargetLowering::getConstraintType to take the entire constraint,
...
not just the first letter. No functionality change.
llvm-svn: 35322
2007-03-25 02:14:49 +00:00
2a991268f7
don't rely on ADL
...
llvm-svn: 35299
2007-03-24 17:37:03 +00:00
b7051f596a
Adjust offset to compensate for big endian machines.
...
llvm-svn: 35293
2007-03-24 00:02:43 +00:00
a883b58caf
Make sure SEXTLOAD of the specific type is supported on the target.
...
llvm-svn: 35289
2007-03-23 22:13:36 +00:00
e2f5f24e8e
Also replace uses of SRL if that's also folded during ReduceLoadWidth().
...
llvm-svn: 35286
2007-03-23 20:55:21 +00:00
a824e79f06
A couple of bug fixes for reducing load width xform:
...
1. Address offset is in bytes.
2. Make sure truncate node uses are replaced with new load.
llvm-svn: 35274
2007-03-23 02:16:52 +00:00
dcb291faa4
Change uses of Function::front to Function::getEntryBlock for readability.
...
llvm-svn: 35265
2007-03-22 16:38:57 +00:00
464dc9b74c
More opportunities to reduce load size.
...
llvm-svn: 35254
2007-03-22 01:54:19 +00:00
a20815e157
Fix for PR1257. Bug in live range shortening as a result of copy coalescing
...
where the destination is dead.
llvm-svn: 35252
2007-03-22 01:26:05 +00:00
0c6bb5eab7
repair x86 performance, dejagnu problems from previous change
...
llvm-svn: 35245
2007-03-21 21:51:52 +00:00
d63baead9b
fold (truncate (srl (load x), c)) -> (smaller load (x+c/vt bits))
...
llvm-svn: 35239
2007-03-21 20:14:05 +00:00
3578dd61c6
Potential spiller improvement.
...
llvm-svn: 35228
2007-03-20 22:22:38 +00:00
bacf4acf65
do not share old induction variables when this would result in invalid
...
instructions (that would have to be split later)
llvm-svn: 35227
2007-03-20 21:54:54 +00:00
d05a1a2ade
maintain LiveIn when splitting blocks (register scavenging needs it)
...
llvm-svn: 35226
2007-03-20 21:35:06 +00:00
1baf5c84ab
Fix some VC++ warnings.
...
llvm-svn: 35224
2007-03-20 20:43:18 +00:00
971aa18867
Code clean up.
...
llvm-svn: 35220
2007-03-20 20:09:03 +00:00
550cf0369c
Minor bug.
...
llvm-svn: 35219
2007-03-20 19:32:11 +00:00
25878b45f5
CopyToReg source operand can be a physical register.
...
llvm-svn: 35213
2007-03-20 16:46:44 +00:00
0e3278e505
First cut trivial re-materialization support.
...
llvm-svn: 35208
2007-03-20 08:13:50 +00:00
25d00d545d
Remove -reduce-joining-phys-regs options. Make it on by default.
...
llvm-svn: 35165
2007-03-19 18:08:26 +00:00
c5e74f6404
Minor bug fix.
...
llvm-svn: 35153
2007-03-19 04:22:35 +00:00
d8f2e4fe4c
- Merge UsedBlocks info after two virtual registers are coalesced.
...
- Use distance to closest use to determine whether to abort coalescing.
llvm-svn: 35141
2007-03-18 09:05:55 +00:00
5382426577
Keep UsedBlocks info accurate.
...
llvm-svn: 35140
2007-03-18 09:02:31 +00:00
f6f043332f
Track the BB's where each virtual register is used.
...
llvm-svn: 35135
2007-03-17 09:29:54 +00:00
7b2a001669
Joining a live interval of a physical register with a virtual one can turn out
...
to be really bad. Once they are joined they are not broken apart. Also, physical
intervals cannot be spilled!
Added a heuristic as a workaround for this. Be careful coalescing with a
physical register if the virtual register uses are "far". Check if there are
uses in the same loop as the source (copy instruction). Check if it is in the
loop preheader, etc.
llvm-svn: 35134
2007-03-17 09:27:35 +00:00
a2465dfc07
Use SmallSet instead of std::set.
...
llvm-svn: 35133
2007-03-17 08:53:30 +00:00
be22235790
If sdisel has decided to sink GEP index expression into any BB. Replace all uses
...
in that BB.
llvm-svn: 35132
2007-03-17 08:22:49 +00:00
c5bc763f50
Turn on GEP index sinking by default.
...
llvm-svn: 35127
2007-03-16 18:32:30 +00:00
0a9d0cabaf
Stupid bug.
...
llvm-svn: 35126
2007-03-16 17:50:20 +00:00
009ea54262
Sink a binary expression into its use blocks if it is a loop invariant
...
computation used as GEP indexes and if the expression can be folded into
target addressing mode of GEP load / store use types.
llvm-svn: 35123
2007-03-16 08:46:27 +00:00
a2a2fd1e55
Added isLegalAddressExpression hook to test if the given expression can be
...
folded into target addressing mode for the given type.
llvm-svn: 35121
2007-03-16 08:42:32 +00:00
88de94a4fb
Debugging output stuff.
...
llvm-svn: 35117
2007-03-15 21:19:28 +00:00
b9e3db67fb
Estimate a cost using the possible number of scratch registers required and use
...
it as a late BURR scheduling tie-breaker.
Intuitively, it's good to push down instructions whose results are liveout so
their long live ranges won't conflict with other values which are needed inside
the BB. Further prioritize liveout instructions by the number of operands which
are calculated within the BB.
llvm-svn: 35109
2007-03-14 22:43:40 +00:00
2874855302
Try schedule def + use closer whne Sethi-Ullman numbers are the same.
...
e.g.
t1 = op t2, c1
t3 = op t4, c2
and the following instructions are both ready.
t2 = op c3
t4 = op c4
Then schedule t2 = op first.
i.e.
t4 = op c4
t2 = op c3
t1 = op t2, c1
t3 = op t4, c2
This creates more short live intervals which work better with the register
allocator.
llvm-svn: 35089
2007-03-13 23:25:11 +00:00
b7004fd889
More flexible TargetLowering LSR hooks for testing whether an immediate is a legal target address immediate or scale.
...
llvm-svn: 35076
2007-03-12 23:37:10 +00:00
df7949a8d0
If a virtual register is already marked alive in this block, that means it is
...
alive in one of the successor block. Do not add it to the kill list.
llvm-svn: 35041
2007-03-09 09:48:56 +00:00
9bc8d4b6f2
Print preds / succs BB numbers.
...
llvm-svn: 35040
2007-03-09 08:29:08 +00:00
91b0790297
Avoid variable shadowing.
...
llvm-svn: 35039
2007-03-09 06:02:17 +00:00
ce8aba03ee
implement support for floating point constants used as inline asm memory operands.
...
llvm-svn: 35033
2007-03-08 22:29:47 +00:00
b7bc3f2d30
make this fail even in non-assert builds.
...
llvm-svn: 35025
2007-03-08 07:07:03 +00:00
ed4b303c10
Refactoring of formal parameter flags. Enable properly use of
...
zext/sext/aext stuff.
llvm-svn: 35008
2007-03-07 16:25:09 +00:00
dd6ce6900e
Cleanup: make SetCounter an instance variable
...
llvm-svn: 35007
2007-03-07 08:25:02 +00:00
8a1d09d079
Avoid combining indexed load further.
...
llvm-svn: 35005
2007-03-07 08:07:03 +00:00
942fda027f
Fix DWARF debugging information on x86/Linux and (hopefully)
...
Mingw32/Cygwin targets. This fixes PR978
llvm-svn: 35000
2007-03-07 02:47:57 +00:00
24f65cc91e
Minor bug fix.
...
llvm-svn: 34985
2007-03-06 21:58:15 +00:00
b0743b5d6a
Now LoopStrengthReduce is a LoopPass.
...
llvm-svn: 34984
2007-03-06 21:14:09 +00:00
13780ac7db
big endian 32-bit systems (e.g. ppc32) want to return the high reg first, not
...
the lo-reg first. This is fallout from my ppc calling conv change yesterday,
it fixes test/ExecutionEngine/2003-05-06-LivenessClobber.llx
llvm-svn: 34983
2007-03-06 20:01:06 +00:00
6c5e0ad71c
Small eye-candy: use asciz directive everywhere, where possible.
...
llvm-svn: 34981
2007-03-06 19:25:02 +00:00
c1b21857a4
If target decides to create an emergency spill slot, make sure it's closest to SP or frame pointer.
...
llvm-svn: 34965
2007-03-06 10:02:38 +00:00
372c2c69f8
Register scavenger is now capable of scavenging. It spills a register whose use of furthest away to make it available.
...
llvm-svn: 34964
2007-03-06 10:01:25 +00:00
f0b9316552
Enumerate SDISel formal parameter attributes. Make use of new
...
enumeration.
llvm-svn: 34960
2007-03-06 06:10:33 +00:00
b622c11f77
Unbreak VC++ build.
...
llvm-svn: 34917
2007-03-05 00:00:42 +00:00
47206667c0
fold away addc nodes when we know there cannot be a carry-out.
...
llvm-svn: 34913
2007-03-04 20:40:38 +00:00
2dcc6e7f58
generalize
...
llvm-svn: 34910
2007-03-04 20:08:45 +00:00
e2e13caeb2
canonicalize constants to the RHS of addc/adde. If nothing uses the carry out of
...
addc, turn it into add.
This allows us to compile:
long long test(long long A, unsigned B) {
return (A + ((long long)B << 32)) & 123;
}
into:
_test:
movl $123, %eax
andl 4(%esp), %eax
xorl %edx, %edx
ret
instead of:
_test:
xorl %edx, %edx
movl %edx, %eax
addl 4(%esp), %eax ;; add of zero
andl $123, %eax
ret
llvm-svn: 34909
2007-03-04 20:03:15 +00:00
362621c7ae
eliminate some ops if they have an undef RHS
...
llvm-svn: 34908
2007-03-04 20:01:46 +00:00
b8825b8c04
Remove unneeded header file.
...
llvm-svn: 34903
2007-03-04 04:41:04 +00:00
ca401aac31
Fix CodeGen/Generic/fpowi-promote.ll and PR1239
...
llvm-svn: 34893
2007-03-03 23:43:21 +00:00
567b9254cd
Add an expand action for ISD label which just deletes the label.
...
This "fixes" PR1238.
llvm-svn: 34890
2007-03-03 19:21:38 +00:00
d74cb0e194
Only propagate IsKill if the last use is a kill.
...
llvm-svn: 34878
2007-03-03 06:32:37 +00:00
323cf8f602
http://llvm.org/bugs/show_bug.cgi?id=1237
...
llvm-svn: 34875
2007-03-03 06:18:18 +00:00
3fd728596e
Watch out for cases like this:
...
entry (0x8b056f0, LLVM BB @0x8b01b30, ID#0):
Live Ins: %r0 %r1 %r2 %r3
%reg1032 = tMOVrr %r3<kill>
%reg1033 = tMOVri8 1
%reg1034 = tMOVri8 0
tCMPi8 %reg1029<kill>, 0
tBcc mbb<entry,0x8b06a10>, 0
Successors according to CFG: 0x8b06980 0x8b06a10
entry (0x8b06980, LLVM BB @0x8b01b30, ID#12):
Predecessors according to CFG: 0x8b056f0
%reg1036 = tMOVrr %reg1034<kill>
Successors according to CFG: 0x8b06a10
entry (0x8b06a10, LLVM BB @0x8b01b30, ID#13):
Predecessors according to CFG: 0x8b056f0 0x8b06980
%reg1024<dead> = tMOVrr %reg1030<kill>
...
reg1030 and r1 have already been joined. When reg1024 and reg1030 are joined,
r1 live range from function entry to the tMOVrr instruction are dead. Eliminate
r1 from the livein set of the entry BB, not the BB where the copy is.
llvm-svn: 34866
2007-03-03 02:18:00 +00:00
155ede21e0
Mark dead def as unused.
...
llvm-svn: 34844
2007-03-02 10:43:16 +00:00
9d615d1e70
Dead live-in detection bug.
...
llvm-svn: 34843
2007-03-02 10:41:15 +00:00
6605c5dbee
- Keep track all def and uses of stack slot available in register.
...
- Available value use may be deleted (e.g. noop move).
llvm-svn: 34841
2007-03-02 08:52:00 +00:00
08f2f0d145
Invalidate last use of a reused register if the use is a deleted noop copy.
...
llvm-svn: 34839
2007-03-02 05:41:42 +00:00
82af5943d1
Emit eh filter info.
...
llvm-svn: 34805
2007-03-01 20:26:43 +00:00
6458e6acb9
Collect eh filter info.
...
llvm-svn: 34804
2007-03-01 20:25:32 +00:00
d5453d7b56
Lower eh filter intrinsic.
...
llvm-svn: 34802
2007-03-01 20:24:30 +00:00
105fb1e0dd
Delete register scavenger when done with it.
...
llvm-svn: 34786
2007-03-01 10:23:33 +00:00
27bc565497
Add a version of FindUnusedReg that restrict search to a specific set of registers.
...
llvm-svn: 34784
2007-03-01 08:56:24 +00:00
d6450ba1dc
A restore is promoted to copy (or deleted entirely), remove the kill from the last use of the targetted register.
...
llvm-svn: 34773
2007-03-01 02:27:30 +00:00
31215d1395
Interface clean up.
...
llvm-svn: 34772
2007-03-01 02:25:51 +00:00
428eaa0059
Interface clean up.
...
llvm-svn: 34770
2007-03-01 02:19:39 +00:00
9be123c568
Oops.
...
llvm-svn: 34768
2007-03-01 02:05:35 +00:00
8a703ad4b6
Track all joined registers and eliminate unneeded kills after all joining are done.
...
llvm-svn: 34767
2007-03-01 02:03:03 +00:00
644af6b68f
Chain is on second operand.
...
llvm-svn: 34759
2007-02-28 20:43:58 +00:00
c46bf3577d
Handle mix of personalities.
...
llvm-svn: 34752
2007-02-28 18:38:31 +00:00
c114990526
Provide a more meaningful name.
...
llvm-svn: 34751
2007-02-28 18:37:50 +00:00
cf465fcebc
MERGE_VALUES unnecessary.
...
llvm-svn: 34750
2007-02-28 18:37:04 +00:00
37dc4b5bb3
Fix a typo, thanks Bill!
...
llvm-svn: 34741
2007-02-28 09:16:38 +00:00
e0232ec706
More Mach-O writer improvements.
...
llvm-svn: 34740
2007-02-28 07:40:50 +00:00
74bb92902e
add methods for analysis of call results and return nodes.
...
llvm-svn: 34738
2007-02-28 07:09:40 +00:00
e74744143f
add methods to analyze calls and formals.
...
llvm-svn: 34736
2007-02-28 06:56:37 +00:00
b5582bf984
add a newline at end of file
...
llvm-svn: 34735
2007-02-28 06:42:11 +00:00
e8af69632f
Make requiresRegisterScavenging determination on a per MachineFunction basis.
...
llvm-svn: 34711
2007-02-28 00:59:19 +00:00
589ba3964b
MRegisterInfo disowns RegScavenger. It's immutable.
...
llvm-svn: 34706
2007-02-28 00:17:36 +00:00
a7e4b60b85
Some more code clean up.
...
llvm-svn: 34700
2007-02-27 22:58:43 +00:00
8a8dc04e7e
Oops.
...
llvm-svn: 34698
2007-02-27 22:10:52 +00:00
e50a994cba
Let MRegisterInfo now owns RegScavenger.
...
llvm-svn: 34691
2007-02-27 21:10:33 +00:00
51f54640de
RegScavenger interface change to make it more flexible.
...
llvm-svn: 34690
2007-02-27 21:09:48 +00:00
9f059194a7
Minor refactoring of CC Lowering interfaces
...
llvm-svn: 34656
2007-02-27 05:13:54 +00:00
dc3adc83e7
move CC Lowering stuff to its own public interface
...
llvm-svn: 34655
2007-02-27 04:43:02 +00:00
ca25c0ee0d
forward() should not increment internal iterator. Its client may insert instruction between now and next forward() call.
...
llvm-svn: 34649
2007-02-27 01:58:48 +00:00
bdec83e4d2
Joining an interval with a dead copy instruction. Shorten the live range to the last use.
...
llvm-svn: 34645
2007-02-26 21:37:37 +00:00
fce448f856
Fold (sext (truncate x)) more aggressively, by avoiding creation of a
...
sextinreg if not needed. This is useful in two cases: before legalize,
it avoids creating a sextinreg that will be trivially removed. After legalize
if the target doesn't support sextinreg, the trunc/sext would not have been
removed before.
llvm-svn: 34621
2007-02-26 03:13:59 +00:00
ab5d0ac02c
track signedness of formal argument, though we have a fixme here.
...
llvm-svn: 34620
2007-02-26 02:56:58 +00:00
14059d958a
Fix for PR1224.
...
llvm-svn: 34610
2007-02-25 21:43:59 +00:00
8c504cf9a0
optimize duplicate ValueMap lookups
...
llvm-svn: 34599
2007-02-25 18:40:32 +00:00
38fd9b074f
A couple of more places where a register liveness has been extended and its last kill should be updated accordingly.
...
llvm-svn: 34597
2007-02-25 09:51:27 +00:00
fb2333a333
Add an assertion.
...
llvm-svn: 34596
2007-02-25 09:47:31 +00:00
0577b51538
Fix a couple of bugs related IsDead back propagation during coalescing.
...
llvm-svn: 34595
2007-02-25 09:46:31 +00:00
e54eb80720
If the liveinterval of the source instruction has been extended, remove the IsKill marker.
...
llvm-svn: 34594
2007-02-25 09:41:59 +00:00
220a7af107
Only add liveinterval to livein set if it isn't assigned a stack slot.
...
llvm-svn: 34593
2007-02-25 09:39:02 +00:00
387f464121
fold trivial token factor nodes. This allows us to compile
...
test/CodeGen/X86/fp-stack-ret.ll into:
movl 4(%esp), %eax
fldl (%eax)
ret
instead of:
subl $12, %esp
movl 16(%esp), %eax
movsd (%eax), %xmm0
movsd %xmm0, (%esp)
fldl (%esp)
addl $12, %esp
ret
by eliminating a token factor that blocked a check.
llvm-svn: 34584
2007-02-25 08:24:27 +00:00
168c5856bf
initialize a instance variable
...
llvm-svn: 34567
2007-02-25 01:28:05 +00:00
e1d1c0590f
Deal with cases when MMI is not requested.
...
llvm-svn: 34556
2007-02-24 09:45:44 +00:00
b869ab6f31
Drop unused operand.
...
llvm-svn: 34555
2007-02-24 09:44:17 +00:00
d7ef3f804d
Fix CodeGen/Generic/2007-02-23-DAGCombine-Miscompile.ll and PR1219
...
llvm-svn: 34551
2007-02-24 02:09:29 +00:00
520b20d3b7
Reuse extends the liveness of a register. Transfer the kill to the operand that reuse it.
...
llvm-svn: 34536
2007-02-23 21:47:50 +00:00
31fef788eb
Handle improper cast.
...
llvm-svn: 34535
2007-02-23 21:45:01 +00:00
97cc93841d
Handle cases when joining live intervals of two virtual registers.
...
llvm-svn: 34534
2007-02-23 20:40:13 +00:00
584e051c28
Mark livein registers as being in used.
...
llvm-svn: 34525
2007-02-23 08:41:19 +00:00
f7e320c9e0
A spill kills the register being stored. But it is later being reused by spiller, its live range has to be extended.
...
llvm-svn: 34517
2007-02-23 01:13:26 +00:00
1e56453585
First potential client of register scavenger.
...
llvm-svn: 34516
2007-02-23 01:11:26 +00:00
9965aebd5d
Use findRegisterUseOperand to find a kill of particular register.
...
llvm-svn: 34512
2007-02-23 01:04:26 +00:00
956fdeb694
Initial check in of register scavenger. Its only current functionality is tracking live registers per MBB.
...
llvm-svn: 34511
2007-02-23 01:01:19 +00:00
cc607daac1
Remove unnecessary isKill properties if a live range has been lengthened due to coalescing.
...
llvm-svn: 34503
2007-02-22 23:03:39 +00:00
5cbb4262ab
Update comment.
...
llvm-svn: 34502
2007-02-22 18:51:19 +00:00
66aa84d12f
Missing end of abbreviations - correction
...
llvm-svn: 34501
2007-02-22 18:48:52 +00:00
4e3d2b9acc
Missing end of abbreviations.
...
llvm-svn: 34500
2007-02-22 18:22:42 +00:00
3e3a65b764
Need to init.
...
llvm-svn: 34499
2007-02-22 18:04:49 +00:00
9df1a1d8d8
Remove isAccessable.
...
llvm-svn: 34497
2007-02-22 16:39:03 +00:00
69bd45c1d2
Use exception flag.
...
llvm-svn: 34496
2007-02-22 16:22:15 +00:00
46dbe12b32
Remove assertion.
...
llvm-svn: 34494
2007-02-22 16:12:17 +00:00
44c37e7dbf
Tighten up error checking of args.
...
llvm-svn: 34493
2007-02-22 16:10:05 +00:00
504e99479c
Handle lowering invoke to call correctly.
...
llvm-svn: 34492
2007-02-22 15:38:06 +00:00
7f5872c455
Simplify lowering and selection of exception ops.
...
llvm-svn: 34491
2007-02-22 15:37:19 +00:00
4b37a4c712
Selection and lowering for exception handling.
...
llvm-svn: 34481
2007-02-21 22:53:45 +00:00
09953e6482
Exception handling support.
...
llvm-svn: 34479
2007-02-21 22:48:45 +00:00
18fc09723c
Add support for changes in DwarfWriter.
...
llvm-svn: 34478
2007-02-21 22:47:38 +00:00
2dc5245c4a
Make branch folding behave in the presence of landing pads.
...
llvm-svn: 34476
2007-02-21 22:42:20 +00:00
5b2b7c1024
Allow for live in registers for eh landing pads.
...
llvm-svn: 34475
2007-02-21 22:41:17 +00:00
88dd2fd332
Add structures used for collecting eh information.
...
llvm-svn: 34473
2007-02-21 22:38:31 +00:00
e563c7eb27
Out of bound reference.
...
llvm-svn: 34461
2007-02-21 02:27:39 +00:00
de037a821a
Use BitVector instead. No functionality change.
...
llvm-svn: 34460
2007-02-21 02:22:03 +00:00
61cd0914ed
Dead code.
...
llvm-svn: 34435
2007-02-20 01:29:10 +00:00
f7ed82da10
Re-apply my liveintervalanalysis changes. Now with PR1207 fixes.
...
llvm-svn: 34428
2007-02-19 21:49:54 +00:00
da81bf4d3e
For PR1207:
...
Revert patches that caused the problem. Evan, please investigate and reapply
when you've discovered the problem.
llvm-svn: 34399
2007-02-19 03:20:00 +00:00
2605082f0e
- Changes how function livein's are handled, they now have a start index of 0.
...
- When coalescing a copy MI, if its destination is "dead", propagate the
property to the source MI's destination if there are no intervening uses.
- Detect dead function live-in's and remove them.
llvm-svn: 34383
2007-02-17 11:15:40 +00:00
a3d3599210
Do not add livein's to entry MBB twice.
...
llvm-svn: 34382
2007-02-17 11:11:27 +00:00
41d2a1d8bf
Added removeLiveIn.
...
llvm-svn: 34381
2007-02-17 11:10:48 +00:00
6accd480a2
Added findRegisterDefOperand().
...
llvm-svn: 34380
2007-02-17 11:10:18 +00:00
ef932b067d
- Use MRegister::regsOverlap().
...
- Allow LiveVariables to track liveness of more registers.
llvm-svn: 34379
2007-02-17 11:09:47 +00:00
56e5fea163
print target nodes nicely
...
llvm-svn: 34369
2007-02-17 06:38:37 +00:00
a9f917af59
Implement i/n/s constraints correctly. This fixes
...
test/CodeGen/PowerPC/2007-02-16-InlineAsmNConstraint.ll
llvm-svn: 34368
2007-02-17 06:00:35 +00:00
12920dda9e
Fixes PR 1200
...
llvm-svn: 34359
2007-02-17 00:44:34 +00:00
66cb162f92
Print <dead> def operands.
...
llvm-svn: 34343
2007-02-16 09:49:18 +00:00
7238410766
Add live-ins to every BB.
...
llvm-svn: 34342
2007-02-16 09:05:02 +00:00
915e15481e
test commit (blank line)
...
llvm-svn: 34337
2007-02-16 01:54:53 +00:00
68dcec6fea
fix indentation
...
llvm-svn: 34307
2007-02-15 18:19:15 +00:00
21ebae3394
Apply B Scott Michel's patch for PR1184, which improves diagnostics in an
...
abort case.
llvm-svn: 34306
2007-02-15 18:17:56 +00:00
14edd1989b
Use BitVector instead of vector<bool> which can be extremely slow.
...
llvm-svn: 34302
2007-02-15 05:59:24 +00:00
09575bac2e
For PR1195:
...
Change use of "packed" term to "vector" in comments, strings, variable
names, etc.
llvm-svn: 34300
2007-02-15 03:39:18 +00:00
d84d35ba70
For PR1195:
...
Rename PackedType -> VectorType, ConstantPacked -> ConstantVector, and
PackedTyID -> VectorTyID. No functional changes.
llvm-svn: 34293
2007-02-15 02:26:10 +00:00
ab1812f806
fix a warning
...
llvm-svn: 34272
2007-02-14 07:34:56 +00:00
1cf84d2745
Refix CodeGen/Generic/switch-lower.ll. In contrast to my previous patch,
...
this doesn't miscompile lots of programs :)
llvm-svn: 34268
2007-02-14 07:18:16 +00:00
945e437c65
Generalize TargetData strings, to support more interesting forms of data.
...
Patch by Scott Michel.
llvm-svn: 34266
2007-02-14 05:52:17 +00:00
59b27fa371
implement expand of truncate. This allows truncates from i128 to i64 to
...
be supported on 32-bit hosts.
llvm-svn: 34257
2007-02-13 23:55:16 +00:00
d08d31f68a
Fix PR1198, by adding initial i128 support. Patch by Dan Gohman.
...
llvm-svn: 34256
2007-02-13 23:41:38 +00:00
2fbff4d2dc
revert my previous switch lowering change, which miscompiles a few programs.
...
This will break a dj test until I have time to investigate.
llvm-svn: 34247
2007-02-13 20:09:07 +00:00
abde3cc16c
Add a space between // and the comment.
...
llvm-svn: 34244
2007-02-13 18:10:13 +00:00
9956dcffbe
Add "original alignment" to function arguments flags.
...
llvm-svn: 34240
2007-02-13 13:50:08 +00:00
6ea07f178c
eliminate vector-related allocations
...
llvm-svn: 34223
2007-02-13 06:01:22 +00:00
b612316f20
Allow any MachineBasicBlock (not just the entry block) to have live-in physical
...
registers. Make sure liveinterval analysis is correctly creating live ranges
for them.
llvm-svn: 34217
2007-02-13 01:30:55 +00:00
9056bae3be
Fix switch lowering to order cases in zext order, which is how we emit the
...
comparisons. This fixes an infinite loop on CodeGen/Generic/switch-lower.ll
and PR1197
llvm-svn: 34216
2007-02-13 01:05:56 +00:00
83dfca816c
eliminate temporary vectors.
...
llvm-svn: 34161
2007-02-10 20:31:59 +00:00
b84892d2d2
encapsulate the rest of the StructLayout members.
...
llvm-svn: 34157
2007-02-10 19:59:22 +00:00
c473d8e431
Privatize StructLayout::MemberOffsets, adding an accessor
...
llvm-svn: 34156
2007-02-10 19:55:17 +00:00
276b44b0f9
Add function live-ins to entry block live-in set.
...
llvm-svn: 34112
2007-02-10 02:43:39 +00:00
bcf1d7faef
Add live-ins to MachineBasicBlock.
...
llvm-svn: 34111
2007-02-10 02:38:19 +00:00
de6083463d
Rename some variables to avoid confusion with SelectionDAGISel::BB.
...
llvm-svn: 34110
2007-02-10 01:08:18 +00:00
93049457ee
Make use of TLI.SimplifySetCC() in LegalizeSetCCOperands().
...
llvm-svn: 34066
2007-02-08 22:16:19 +00:00
92658d5648
Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer.
...
llvm-svn: 34065
2007-02-08 22:13:59 +00:00
6ad6fdb70b
Fixed a long standing spiller bug that's exposed by Thumb:
...
The code sequence before the spiller is something like:
= tMOVrr
%reg1117 = tMOVrr
%reg1078 = tLSLri %reg1117, 2
The it starts spilling:
%r0 = tRestore <fi#5>, 0
%r1 = tRestore <fi#7>, 0
%r1 = tMOVrr %r1<kill>
tSpill %r1, <fi#5>, 0
%reg1078 = tLSLri %reg1117, 2
It restores the value while processing the first tMOVrr. At this point, the
spiller remembers fi#5 is available in %r0. Next it processes the second move.
It restores the source before the move and spills the result afterwards. The
move becomes a noop and is deleted. However, a spill has been inserted and that
should invalidate reuse of %r0 for fi#5 and add reuse of %r1 for fi#5.
Therefore, %reg1117 (which is also assigned fi#5) should get %r1, not %r0.
llvm-svn: 34039
2007-02-08 06:04:54 +00:00
523048ecde
Split the addPassesToEmitFile method up into two. This is so that we can
...
do some common stuff, then on our own add an object file writer (by calling
a concrete function), and then do some finishing stuff, if need be.
llvm-svn: 34032
2007-02-08 01:36:53 +00:00
3c4d37a531
Add function to create a file writer.
...
llvm-svn: 34031
2007-02-08 01:35:27 +00:00
860ce1b82e
Moved from include/llvm/CodeGen to lib/CodeGen.
...
llvm-svn: 34027
2007-02-08 01:30:50 +00:00
3cc886add8
Fix a fixme by correctly calculating preferred alignments for functions,
...
based on the alignment of the symbol and the target data's preferred align
for that type.
Also, rename some arguments for consistency.
llvm-svn: 33984
2007-02-07 05:47:16 +00:00
dc0a9a7b4a
Two fixes:
...
1. Memset takes an i32 for the value to set, not i8. This was causing GCC to
ICE all over the place (PR1183).
2. memcpy/memmove were not properly zext/trunc'ing the size in some cases.
llvm-svn: 33970
2007-02-06 19:06:38 +00:00
1b4b054cba
Fix PR1181 and CodeGen/CBackend/2007-02-05-memset.ll
...
llvm-svn: 33957
2007-02-06 06:07:51 +00:00
89e66e0c26
Oops, swap this. This fixes a regression I introduced in the ARM backend.
...
llvm-svn: 33946
2007-02-06 01:56:31 +00:00
a9428c4f9d
Fix PR1178
...
llvm-svn: 33924
2007-02-05 21:23:52 +00:00
465c0253c3
Fixing silly "not-implemented" bug in AsmPrinter. This fixes PR1169.
...
llvm-svn: 33888
2007-02-04 23:27:42 +00:00
19083a4671
switch the VRBaseMap in the scheduler from an std::map to a DenseMap. This
...
speeds up the isel pass from 2.5570s to 2.4722s on kc++ (3.4%).
llvm-svn: 33879
2007-02-04 08:47:20 +00:00
9af2c86bc8
Introduce new UnarySDNode/BinarySDNode/TernarySDNode nodes, which coallocate
...
their operands with the node itself. This reduces malloc traffic for operand
lists. This reduces isel time on kc++ from 2.6164 to 2.5570s, about 2.3%.
llvm-svn: 33878
2007-02-04 08:35:21 +00:00
22639f3d90
eliminate the SDNode::setValueTypes method.
...
llvm-svn: 33876
2007-02-04 07:37:24 +00:00
f17b4222e2
eliminate a bunch of duplicate ctors and helper functions.
...
llvm-svn: 33875
2007-02-04 07:28:00 +00:00
edfc7e5fa2
move MorphNode to out of line and merge setNodeOperands into it. There is
...
no behavior or performance change here.
llvm-svn: 33869
2007-02-04 02:49:29 +00:00
3bf17b6fa5
simplify MorphNodeTo to take a VTList operand.
...
llvm-svn: 33868
2007-02-04 02:41:42 +00:00
486edfbc6f
eliminate some extraneous methods in SDNode
...
llvm-svn: 33867
2007-02-04 02:32:44 +00:00
20754cc579
Give each selectiondag node class a home for it's vtable and rtti info
...
llvm-svn: 33866
2007-02-04 02:23:32 +00:00
289aa4495c
Switch VAlueMap from std::map to DenseMap.
...
llvm-svn: 33863
2007-02-04 01:35:11 +00:00
79084305ee
Switch NodeMap from std::map to DenseMap, this speeds up isel by 2.3%
...
llvm-svn: 33862
2007-02-04 01:31:47 +00:00
94c44c96d3
swtich vector-> smallvector, speeding up selectiondag stuff 1%
...
llvm-svn: 33861
2007-02-04 01:20:02 +00:00
4b0ddb22e9
Switch promoted/expanded ops over to using a DenseMap. Vector related maps
...
aren't worth it.
llvm-svn: 33860
2007-02-04 01:17:38 +00:00
ed39c86176
switch LegalizedNodes from std::map to a DenseMap. This speeds up isel
...
time as a whole on kc++ by 11%.
llvm-svn: 33857
2007-02-04 00:50:02 +00:00
ebeb48d4bc
Eliminate some malloc traffic from LegalizeAllNodesNotLeadingTo, speeding
...
up isel on kimwitu by 0.7%.
llvm-svn: 33853
2007-02-04 00:27:56 +00:00
cba058ce51
Eliminate some std::sets. This speeds up isel of kimwitu by about 0.9%
...
llvm-svn: 33852
2007-02-04 00:24:41 +00:00
feec7137ce
Switch SelectionDAG::ReplaceAllUsesOfValueWith to use a SmallSetVector for
...
the users set (most nodes have 1 or 2 users). This speeds up the isel pass
3.2% on kimwitu.
llvm-svn: 33849
2007-02-04 00:14:31 +00:00
c27c70dc3d
Pass in non-Mach-O-specific parameters to the GetTargetRelocation method.
...
llvm-svn: 33816
2007-02-03 02:39:40 +00:00
0a30b1f00f
switch the sched unit map over to use a DenseMap instead of std::map. This
...
speeds up isel as a whole time by 2.6%.
llvm-svn: 33810
2007-02-03 01:34:13 +00:00
e83030b9c8
Switch ComputeTopDownOrdering over to using a densemap. This speeds up
...
isel as a whole by 3.3%.
llvm-svn: 33809
2007-02-03 01:12:36 +00:00
f309d13677
Pasto
...
llvm-svn: 33806
2007-02-03 00:43:46 +00:00
5dc84cdab7
Use short form of BinaryOperator create function.
...
llvm-svn: 33784
2007-02-02 14:09:34 +00:00
2341c22ec7
Changes to support making the shift instructions be true BinaryOperators.
...
This feature is needed in order to support shifts of more than 255 bits
on large integer types. This changes the syntax for llvm assembly to
make shl, ashr and lshr instructions look like a binary operator:
shl i32 %X, 1
instead of
shl i32 %X, i8 1
Additionally, this should help a few passes perform additional optimizations.
llvm-svn: 33776
2007-02-02 02:16:23 +00:00
f970221c4d
Slip up
...
llvm-svn: 33758
2007-02-01 17:48:20 +00:00
894ceb1c6f
Emit labels as label_n and not as debug_n
...
llvm-svn: 33757
2007-02-01 17:46:10 +00:00
c3de9b4b14
Support for non-landing pad exception handling.
...
llvm-svn: 33755
2007-02-01 16:31:34 +00:00
1b4e6015b4
Fixed uninitialized stuff inside LegalizeDAG. Fortunately, the only
...
affected part is codegen of "memove" inside x86 backend. This fixes
PR1144
llvm-svn: 33752
2007-02-01 08:39:52 +00:00
1003dc72b4
rename DenseMap to IndexedMap.
...
llvm-svn: 33749
2007-02-01 05:32:05 +00:00
296a83cefb
Fit in 80 columns
...
llvm-svn: 33745
2007-02-01 04:55:59 +00:00
e3eeb24a86
Emit a better assertion message for PR1133
...
llvm-svn: 33736
2007-02-01 01:21:12 +00:00
53026f1d5a
Allow the target to override the ISD::CondCode that's to be used to test the
...
result of the comparison libcall against zero.
llvm-svn: 33701
2007-01-31 09:29:11 +00:00
5301e7c605
For PR1136: Rename GlobalVariable::isExternal as isDeclaration to avoid
...
confusion with external linkage types.
llvm-svn: 33663
2007-01-30 20:08:39 +00:00
d27f95e08d
add initial support for handling inline asms with multiple constraints.
...
This doesn't do the "right thing" but will probably work in most cases.
This implements CodeGen/PowerPC/2007-01-29-lbrx-asm.ll.
llvm-svn: 33643
2007-01-29 23:45:14 +00:00
ee23de6c36
Out of line function.
...
llvm-svn: 33641
2007-01-29 23:40:33 +00:00
3f9f250928
Only gather frame info if debug or eh.
...
llvm-svn: 33639
2007-01-29 23:20:22 +00:00
eda5997cc8
Finish off bug 680, allowing targets to custom lower frame and return
...
address nodes.
llvm-svn: 33636
2007-01-29 22:58:52 +00:00
2a562ba47b
Properly support cstrings
...
llvm-svn: 33629
2007-01-29 21:20:42 +00:00
d1154860a4
Flag to control exception handling.
...
llvm-svn: 33628
2007-01-29 20:48:32 +00:00
18c3b5267d
Disable zero landing pads for now.
...
llvm-svn: 33625
2007-01-29 20:01:41 +00:00
b4a2f05d1c
Landing pad-less eh for PPC.
...
llvm-svn: 33622
2007-01-29 18:51:14 +00:00
d7035b654b
Use TargetData to obtain the correct size of the "size_t" argument for
...
functions like memcpy, memmove and memset. Ensure only one prototype is
used for these functions and that it matches the system definition by
using the appropriate type for the size argument.
llvm-svn: 33618
2007-01-29 17:42:06 +00:00
c7765617d2
For PR1138:
...
Force memcpy to be the 32-bit variant. Since this is only used with
CBE and lli which both target 32-bit machines, this should be okay.
llvm-svn: 33608
2007-01-28 22:28:00 +00:00
06f7d4bec7
Arguments are counting from 1. not from 0. Maybe we should change
...
numbering somehow? E.g. make return argument the last?
llvm-svn: 33606
2007-01-28 18:01:49 +00:00
9fa3839d29
More cleanup
...
llvm-svn: 33605
2007-01-28 16:04:40 +00:00
037c867b54
Propagate changes from my local tree. This patch includes:
...
1. New parameter attribute called 'inreg'. It has meaning "place this
parameter in registers, if possible". This is some generalization of
gcc's regparm(n) attribute. It's currently used only in X86-32 backend.
2. Completely rewritten CC handling/lowering code inside X86 backend.
Merged stdcall + c CCs and fastcall + fast CC.
3. Dropped CSRET CC. We cannot add struct return variant for each
target-specific CC (e.g. stdcall + csretcc and so on).
4. Instead of CSRET CC introduced 'sret' parameter attribute. Setting in
on first attribute has meaning 'This is hidden pointer to structure
return. Handle it gently'.
5. Fixed small bug in llvm-extract + add new feature to
FunctionExtraction pass, which relinks all internal-linkaged callees
from deleted function to external linkage. This will allow further
linking everything together.
NOTEs: 1. Documentation will be updated soon.
2. llvm-upgrade should be improved to translate csret => sret.
Before this, there will be some unexpected test fails.
llvm-svn: 33597
2007-01-28 13:31:35 +00:00
3814e72ed1
Use TargetELFWriterInfo class.
...
llvm-svn: 33573
2007-01-27 02:55:44 +00:00
f209495e93
Handle multiple functions, properly mangle symbols, and fix support for
...
scattered relocations.
llvm-svn: 33555
2007-01-26 22:39:48 +00:00
5a1df9748b
rename files
...
llvm-svn: 33552
2007-01-26 21:38:26 +00:00
c56315c2b5
Change the MachineDebugInfo to MachineModuleInfo to better reflect usage
...
for debugging and exception handling.
llvm-svn: 33550
2007-01-26 21:22:28 +00:00
f9e5445ed4
Make LABEL a builtin opcode.
...
llvm-svn: 33537
2007-01-26 14:34:52 +00:00
f773e14547
Clarify some constants.
...
llvm-svn: 33536
2007-01-26 14:19:17 +00:00
ae4ea45eaf
Added a MRegisterInfo hook that tells PEI the target is responsible for
...
rounding the stack frame to a multiple of stack alignment.
llvm-svn: 33504
2007-01-25 22:12:41 +00:00
ee132b5fce
1. Remove dwarf-verbose option (now asm-verbose.)
...
2. Clean up end of lines.
llvm-svn: 33499
2007-01-25 15:45:58 +00:00
1c055e8d14
Migrate print routines to asm to be shared by exception handling.
...
llvm-svn: 33498
2007-01-25 15:12:02 +00:00
f6c63fec92
Repair debug frames as a prelude to eh_frames. Switched to using MachineMoves
...
by value so that clean up is less confusing (these vectors tend to be small.)
llvm-svn: 33488
2007-01-24 18:45:13 +00:00
f6487ec894
Use asm printer to emit alignment
...
llvm-svn: 33485
2007-01-24 13:12:32 +00:00
06a03210af
Make ivars private and use getters. Have the MachOWriter return "Mach-O
...
Writer" for the pass name.
llvm-svn: 33483
2007-01-24 07:13:56 +00:00
f5c96fabf9
Renamed getTypeAlignmentShift() to getPreferredTypeAlignmentShift().
...
llvm-svn: 33482
2007-01-24 07:03:39 +00:00
4905a473e8
Use the TargetMachOWriterInfo class to get this information.
...
llvm-svn: 33478
2007-01-24 03:38:47 +00:00
6730e12ae4
PEI is now responsible for adding MaxCallFrameSize to frame size and align the stack. Each target can further adjust the frame size if necessary.
...
llvm-svn: 33460
2007-01-23 09:38:11 +00:00
199818475b
Switch this to use SmallSet to avoid mallocs in the common case.
...
llvm-svn: 33457
2007-01-23 00:59:48 +00:00
d39e38848b
Fix a bunch of inline asm failures
...
llvm-svn: 33454
2007-01-23 00:36:17 +00:00
be48a47d9d
Remove the DoubleTy special case.
...
llvm-svn: 33449
2007-01-22 23:13:55 +00:00
2eadb5310d
For PR970:
...
Clean up handling of isFloatingPoint() and dealing with PackedType.
Patch by Gordon Henriksen!
llvm-svn: 33415
2007-01-21 00:29:26 +00:00
50ee0e40e5
Teach TargetData to handle 'preferred' alignment for each target, and use
...
these alignment amounts to align scalars when we can. Patch by Scott Michel!
llvm-svn: 33409
2007-01-20 22:35:55 +00:00
00a640dbe0
Fix for PR1108: type of insert_vector_elt index operand is PtrVT, not MVT::i32.
...
llvm-svn: 33398
2007-01-20 10:10:26 +00:00
887f75ac0a
Remove an unused variable.
...
llvm-svn: 33396
2007-01-20 09:21:54 +00:00
7ab6fa3a67
We not align the final stack slot but instead let the target do so in emitPrologue(). Each target can make adjustments to the stack frame and re-align the stack as it deem appropriate. Do not align it twice which can end up wasting stack space.
...
llvm-svn: 33387
2007-01-20 02:07:13 +00:00
fc74e2de26
GetRegForReload() now keeps track which registers have been considered and rejected during its quest to find a suitable reload register. This avoids an infinite loop in case like this:
...
t1 := op t2, t3
t2 <- assigned r0 for use by the reload but ended up reuse r1
t3 <- assigned r1 for use by the reload but ended up reuse r0
t1 <- desires r1
sees r1 is taken by t2, tries t2's reload register r0
sees r0 is taken by t3, tries t3's reload register r1
sees r1 is taken by t2, tries t2's reload register r0 ...
llvm-svn: 33382
2007-01-19 22:40:14 +00:00
a94d394ad2
For PR1043:
...
This is the final patch for this PR. It implements some minor cleanup
in the use of IntegerType, to wit:
1. Type::getIntegerTypeMask -> IntegerType::getBitMask
2. Type::Int*Ty changed to IntegerType* from Type*
3. ConstantInt::getType() returns IntegerType* now, not Type*
This also fixes PR1120.
Patch by Sheng Zhou.
llvm-svn: 33370
2007-01-19 21:13:56 +00:00
9201100b29
Remove this xform:
...
(shl (add x, c1), c2) -> (add (shl x, c2), c1<<c2)
Replace it with:
(add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
This fixes test/CodeGen/ARM/smul.ll
llvm-svn: 33361
2007-01-19 17:51:44 +00:00
e750f61ac5
Have the OutputBuffer take the is64Bit and isLittleEndian booleans.
...
llvm-svn: 33316
2007-01-18 01:23:11 +00:00
0ee2d46cfe
add new JumpTableSpecialLabelPrefix hook to asmprinter for jumptable emission.
...
llvm-svn: 33314
2007-01-18 01:12:56 +00:00
cd9c1f035a
Changed to use the OutputBuffer instead of the methods in MachO and ELF
...
writers.
llvm-svn: 33311
2007-01-17 22:22:31 +00:00
38ee6519b7
Revert patch.
...
llvm-svn: 33298
2007-01-17 09:06:13 +00:00
dcc324b15b
Use the methods in the TargetObjInfo object instead of internal methods.
...
llvm-svn: 33289
2007-01-17 03:49:21 +00:00
4dc4489286
Fix PR1114 and CodeGen/Generic/2007-01-15-LoadSelectCycle.ll by being
...
careful when folding "c ? load p : load q" that C doesn't reach either load.
If so, folding this into load (c ? p : q) will induce a cycle in the graph.
llvm-svn: 33251
2007-01-16 05:59:59 +00:00
f70c5cd5db
add options to view the dags before the first or second pass of dag combine.
...
llvm-svn: 33249
2007-01-16 04:55:25 +00:00
e21237e59a
Fix for PR1095:
...
LLVM would miscompile ASM dialects when compiling for PPC. Added dialects for
the X86 and PPC backends. It defaults to "0", the first variant of a compound
inline asm expression.
llvm-svn: 33246
2007-01-16 03:42:04 +00:00
03c4953cdd
rename Type::isIntegral to Type::isInteger, eliminating the old Type::isInteger.
...
rename Type::getIntegralTypeMask to Type::getIntegerTypeMask.
This makes naming much more consistent. For example, there are now no longer any
instances of IntegerType that are not considered isInteger! :)
llvm-svn: 33225
2007-01-15 02:27:26 +00:00
c69c6c4db2
eliminate calls to Type::isInteger, preferring isIntegral instead.
...
llvm-svn: 33222
2007-01-15 02:03:16 +00:00
a8a0f2cf68
Compensate for loss of DerivedTypes.h in TargetLowering.h
...
llvm-svn: 33159
2007-01-12 23:31:12 +00:00
ddf1421b8e
Move a function out of line.
...
llvm-svn: 33158
2007-01-12 23:30:31 +00:00
61a4be88b4
Minor fix.
...
llvm-svn: 33149
2007-01-12 22:51:10 +00:00
7f6fac4bb5
Simplify code
...
llvm-svn: 33123
2007-01-12 18:15:09 +00:00
7a9c62baa6
For PR1064:
...
Implement the arbitrary bit-width integer feature. The feature allows
integers of any bitwidth (up to 64) to be defined instead of just 1, 8,
16, 32, and 64 bit integers.
This change does several things:
1. Introduces a new Derived Type, IntegerType, to represent the number of
bits in an integer. The Type classes SubclassData field is used to
store the number of bits. This allows 2^23 bits in an integer type.
2. Removes the five integer Type::TypeID values for the 1, 8, 16, 32 and
64-bit integers. These are replaced with just IntegerType which is not
a primitive any more.
3. Adjust the rest of LLVM to account for this change.
Note that while this incremental change lays the foundation for arbitrary
bit-width integers, LLVM has not yet been converted to actually deal with
them in any significant way. Most optimization passes, for example, will
still only deal with the byte-width integer types. Future increments
will rectify this situation.
llvm-svn: 33113
2007-01-12 07:05:14 +00:00
cddc9dfe97
Implement review feedback for the ConstantBool->ConstantInt merge. Chris
...
recommended that getBoolValue be replaced with getZExtValue and that
get(bool) be replaced by get(const Type*, uint64_t). This implements
those changes.
llvm-svn: 33110
2007-01-12 04:24:46 +00:00
31cbddf28a
Store default libgcc routine names and allow them to be redefined by target.
...
llvm-svn: 33105
2007-01-12 02:11:51 +00:00
542964f55b
Rename BoolTy as Int1Ty. Patch by Sheng Zhou.
...
llvm-svn: 33076
2007-01-11 18:21:29 +00:00
75b871fb1e
For PR1043:
...
Merge ConstantIntegral and ConstantBool into ConstantInt.
Remove ConstantIntegral and ConstantBool from LLVM.
llvm-svn: 33073
2007-01-11 12:24:14 +00:00
6730f03370
Naming consistency.
...
llvm-svn: 33026
2007-01-08 23:55:53 +00:00
961bbd393b
Fix for PR1075: bottom-up register-reduction scheduling actually increases register pressure.
...
- Fixed bugs in sethi-ullman number computation and priority queue comparison
functions.
- Separate code that handles priority computation special cases from SU number computation.
llvm-svn: 33025
2007-01-08 23:50:38 +00:00
0199fd6d59
Implement some trivial FP foldings when -enable-unsafe-fp-math is specified.
...
This implements CodeGen/PowerPC/unsafe-math.ll
llvm-svn: 33024
2007-01-08 23:04:05 +00:00
3106724a03
Need to handle static declarations properly.
...
llvm-svn: 33022
2007-01-08 22:15:18 +00:00
2a116abf3a
llvm 2.0 doesn't support llvm.isunordered.*
...
llvm-svn: 32994
2007-01-07 08:52:43 +00:00
10cae15d8e
remove support for llvm.isunordered
...
llvm-svn: 32992
2007-01-07 08:37:22 +00:00
34acba48cc
Change the interface to Module::getOrInsertFunction to be easier to use,to resolve PR1088, and to help PR411.
...
This simplifies many clients also
llvm-svn: 32989
2007-01-07 08:12:01 +00:00
5f80c450f3
Expand fcopysign to the bitwise sequence if select is marked as expensive.
...
llvm-svn: 32940
2007-01-05 23:33:44 +00:00
3b841ddbe0
Bug in ExpandFCOPYSIGNToBitwiseOps(). Clear the old sign bit of operand 0
...
before or'ing in the sign bit of operand 1.
llvm-svn: 32930
2007-01-05 21:31:51 +00:00
376c9c4c97
CopyToReg source operand can be a register as well. e.g. Copy from GlobalBaseReg.
...
llvm-svn: 32929
2007-01-05 20:59:06 +00:00
8ec5283dc4
GEP subscript is interpreted as a signed value.
...
llvm-svn: 32888
2007-01-05 01:46:20 +00:00
96035bed51
fix PowerPC/2007-01-04-ArgExtension.ll, a bug handling K&R prototypes with
...
the recent signless changes.
llvm-svn: 32884
2007-01-04 22:22:37 +00:00
003feb03d5
Expand fcopysign to a series of bitwise of operations when it's profitable to
...
do so.
llvm-svn: 32881
2007-01-04 21:56:39 +00:00
e6f81876eb
Legalizer doesn't do an ANY_EXTEND if we don't ask for one so make sure
...
that we default to an ANY_EXTEND if no parameter attribute is set on the
result value of a function.
llvm-svn: 32836
2007-01-03 16:49:33 +00:00
7601f2f36e
NULL names should pass validation.
...
llvm-svn: 32835
2007-01-03 13:46:20 +00:00
751314fab9
Silence warning.
...
llvm-svn: 32834
2007-01-03 13:36:40 +00:00
2a34b91666
Restore previous behavior of defaulting to ZEXT. This works around two
...
things: (1) preventing PR1071 and (2) working around missing parameter
attributes for bool type. (2) will be fixed shortly. When PR1071 is fixed,
this patch should be undone.
llvm-svn: 32831
2007-01-03 05:03:05 +00:00
0917adf614
Two changes:
...
1. Switch expression and cases are compared signed and are sign extended.
2. For function results needing extended, do SIGN_EXTEND if the SExtAttribute
is set and ZERO_EXTEND if the ZExtAttribute is set, otherwise just let
the Legalizer do ANY_EXTEND.
This fixes the recent regression in kimwitu++ and probably the llvm-gcc
bootstrap issue we had today.
llvm-svn: 32830
2007-01-03 04:25:33 +00:00
791864c6a5
Clean up from recent changes. Comment the new parameter to ExpandLibCall.
...
Consolidate some lines of code and remove duplication.
llvm-svn: 32829
2007-01-03 04:22:32 +00:00
92484c2aa4
- Fixing naming inconsistency: calleesave -> calleesaved.
...
- Make use of spillCalleeSavedRegisters() and restoreCalleeSavedRegisters().
llvm-svn: 32822
2007-01-02 21:31:15 +00:00
e63b6518fa
For PR950:
...
Three changes:
1. Convert signed integer types to signless versions.
2. Implement the @sext and @zext parameter attributes. Previously the
type of an function parameter was used to determine whether it should
be sign extended or zero extended before the call. This information is
now communicated via the function type's parameter attributes.
3. The interface to LowerCallTo had to be changed in order to accommodate
the parameter attribute information. Although it would have been
convenient to pass in the FunctionType itself, there isn't always one
present in the caller. Consequently, a signedness indication for the
result type and for each parameter was provided for in the interface
to this method. All implementations were changed to make the adjustment
necessary.
llvm-svn: 32788
2006-12-31 05:55:36 +00:00
266e42b312
For PR950:
...
This patch removes the SetCC instructions and replaces them with the ICmp
and FCmp instructions. The SetCondInst instruction has been removed and
been replaced with ICmpInst and FCmpInst.
llvm-svn: 32751
2006-12-23 06:05:41 +00:00
d7a090ffc4
Need to walk the derived chain of typedefs to get actual size.
...
llvm-svn: 32744
2006-12-22 20:03:42 +00:00
763550323d
Debug dump error.
...
llvm-svn: 32743
2006-12-22 02:04:05 +00:00
4e0c2a0e41
Just print integer constants as signed values. The actual signedness
...
doesn't matter as it is determined in the way the constant is used.
llvm-svn: 32733
2006-12-21 19:04:23 +00:00
6156b02dd3
Simplify all the casting business and get rid of isSigned().
...
llvm-svn: 32731
2006-12-21 08:28:31 +00:00
258657e64e
getLoad() and getStore() calls missed SVOffset operand. Thanks to Dan Gohman
...
for pointing it out!
llvm-svn: 32712
2006-12-20 01:27:29 +00:00
aee775a6b7
Eliminate static ctors from Statistics
...
llvm-svn: 32698
2006-12-19 22:41:21 +00:00
44ef93449a
Fix for PR1059: http://llvm.org/PR1059
...
llvm-svn: 32685
2006-12-19 21:04:20 +00:00
9ad6edf2ec
May need to promote the operand (either sign_extend_inreg or and) before
...
expanding a {s|u}int_to_fp.
llvm-svn: 32665
2006-12-19 01:44:04 +00:00
adc80f98cf
LegalizeSetCCOperands() may end up inserting libcalls. They need to be
...
properly serialized. Do not clear LastCallSEQ_END until that is done.
llvm-svn: 32659
2006-12-18 22:55:34 +00:00
668d90f289
Convert the last uses of CastInst::createInferredCast to a normal cast
...
creation. These changes are still temporary but at least this pushes
knowledge of signedness out closer to where it can be determined properly
and allows signedness to be removed from VMCore.
llvm-svn: 32654
2006-12-18 08:47:13 +00:00
d7998d0e6d
move ExtWeakSymbols to AsmPrinter
...
llvm-svn: 32648
2006-12-18 03:37:18 +00:00
e33ce528da
Fixed so that it dereferences the ostream pointer.
...
llvm-svn: 32640
2006-12-17 11:15:53 +00:00
a77f14265b
Added an automatic cast to "std::ostream*" etc. from OStream. We then can
...
rework the hacks that had us passing OStream in. We pass in std::ostream*
instead, check for null, and then dispatch to the correct print() method.
llvm-svn: 32636
2006-12-17 05:15:13 +00:00
9bd5ed636c
Fix PR1049 and CodeGen/Generic/2006-12-16-InlineAsmCrash.ll
...
by producing target constants instead of constants. Constants can get
selected to li/movri instructions, which causes the scheduler to explode.
llvm-svn: 32633
2006-12-16 21:14:48 +00:00
28cf4277bb
Cannot combine an indexed load / store any further.
...
llvm-svn: 32629
2006-12-16 06:25:23 +00:00
851e589eda
Expand FP undef
...
llvm-svn: 32623
2006-12-16 02:20:50 +00:00
29192e6274
The best unbreakage yet, addressing Bill's concerns.
...
llvm-svn: 32622
2006-12-16 02:15:42 +00:00
860004688a
Allow promoted FP_TO_UINT / FP_TO_SINT to expand operand.
...
llvm-svn: 32621
2006-12-16 02:10:30 +00:00
388cbbf000
Expand fabs / fneg to and / xor.
...
llvm-svn: 32619
2006-12-16 00:52:40 +00:00
b82309f1ab
An even better unbreakage...
...
llvm-svn: 32617
2006-12-15 22:57:14 +00:00
884bc09d10
Fix select_cc, select expansion to soft-fp bugs.
...
llvm-svn: 32616
2006-12-15 22:42:55 +00:00
26df19ace6
This code was usurping the sextload expand in teh legalizer. Just make
...
sure the right conditions are checked.
llvm-svn: 32611
2006-12-15 21:38:30 +00:00
b1a9492ed7
silence a bogus warning
...
llvm-svn: 32597
2006-12-15 07:36:19 +00:00
54c4ab8524
Minor clean up.
...
llvm-svn: 32593
2006-12-15 06:41:01 +00:00
35fdd5ffe1
Expand FP compares to soft-fp call(s)
...
llvm-svn: 32590
2006-12-15 02:59:56 +00:00
70323a8146
1. Tidy up jump table info.
...
2. Allow the jit to handle PIC relocable jump tables.
llvm-svn: 32581
2006-12-14 19:17:33 +00:00
4c306ae0c2
Fix a long-standing spiller bug:
...
If a spillslot value is available in a register, and there is a noop copy that
targets that register, the spiller correctly decide not to invalidate the
spillslot register.
However, even though the noop copy does not clobbers the value. It does start a
new intersecting live range. That means the spillslot register is available for
use but should not be reused for a two-address instruction modref operand which
would clobber the new live range.
When we remove the noop copy, update the available information by clearing the
canClobber bit.
llvm-svn: 32576
2006-12-14 07:54:05 +00:00
22cf89967b
More soft-fp work.
...
llvm-svn: 32559
2006-12-13 20:57:08 +00:00
e370e0eb09
Expand (f64 extload f32) to (f64 fp_ext (load f32)) if f64 type action is expand.
...
llvm-svn: 32527
2006-12-13 03:19:57 +00:00
f3a80c6235
Expand fsqrt, fsin, and fcos to libcalls.
...
llvm-svn: 32526
2006-12-13 02:38:13 +00:00
0a5b805f6d
Expand f32 / f64 to i32 / i64 conversion to soft-fp library calls.
...
llvm-svn: 32523
2006-12-13 01:57:55 +00:00
bfe26ffcfc
Replace CastInst::createInferredCast calls with more accurate cast
...
creation calls.
llvm-svn: 32521
2006-12-13 00:50:17 +00:00
3766fc60da
Expand FP constant to integers if FP types are not legal.
...
llvm-svn: 32497
2006-12-12 22:19:28 +00:00
97a750fc47
Soft fp FNEG, SINT_TO_FP, UINT_TO_FP libcall expansion.
...
llvm-svn: 32495
2006-12-12 21:51:17 +00:00
47833a1d28
Expand ConstantFP to load from CP if float types are being expanded.
...
llvm-svn: 32494
2006-12-12 21:32:44 +00:00
634885f71e
Expand i32/i64 CopyToReg f32/f64 to BIT_CONVERT + CopyToReg.
...
llvm-svn: 32493
2006-12-12 21:21:32 +00:00
0076ca0da9
- When expanding a bit_convert whose src operand is also to be expanded and
...
its expansion result type is equal to the result type of the bit_convert,
e.g. (i64 bit_convert (f64 op)) if FP is not legal
returns the result of the expanded source operand.
- Store f32 / f64 may be expanded to a single store i32/i64.
llvm-svn: 32490
2006-12-12 19:53:13 +00:00
0c0b78c18e
Expand formal arguments and call arguments recursively: e.g. f64 -> i64 -> 2 x i32.
...
llvm-svn: 32476
2006-12-12 07:27:38 +00:00
2f96e7d241
fit in 80 cols
...
llvm-svn: 32474
2006-12-12 05:22:21 +00:00
080881614d
this can only be fptrunc.
...
llvm-svn: 32473
2006-12-12 05:21:51 +00:00
6801f02557
This case isn't needed with recent changes to ConstantInt::get
...
llvm-svn: 32472
2006-12-12 05:19:46 +00:00
0c537dae55
split up inttoptr from ptrtoint handling, the cases aren't similar at all.
...
llvm-svn: 32471
2006-12-12 05:18:19 +00:00
b9e41f5559
the operand of a bitcast is always the right size, just emit it in place.
...
llvm-svn: 32470
2006-12-12 05:14:13 +00:00
6ba11fbd75
Revert Nate's patch to fix X86/store-fp-constant.ll. With the dag combiner
...
and legalizer separated like they currently are, I don't see a way to handle
this xform.
llvm-svn: 32466
2006-12-12 04:18:56 +00:00
b7524b6d0e
make this code more aggressive about turning store fpimm into store int imm.
...
This is not sufficient to fix X86/store-fp-constant.ll
llvm-svn: 32465
2006-12-12 04:16:14 +00:00
38dbe1ca14
Tidy up a bit.
...
llvm-svn: 32462
2006-12-12 01:32:02 +00:00
3c49edcaa1
Change inferred cast creation calls to more specific cast creations.
...
llvm-svn: 32460
2006-12-12 01:17:41 +00:00
3432ab97c1
Re-apply changes that were backed out and fix a naughty typo.
...
llvm-svn: 32442
2006-12-11 19:27:14 +00:00
b3b285185f
It seems the llvm::OStream class does not handle stream manipulators.
...
For now, just grab the stream and perform the output on it directly.
llvm-svn: 32441
2006-12-11 19:15:36 +00:00
e9a203c4e5
Revert changes that broke oggenc on ppc
...
llvm-svn: 32440
2006-12-11 18:53:38 +00:00
218369881f
Don't convert store double C, Ptr to store long C, Ptr if i64 is not a legal type.
...
llvm-svn: 32434
2006-12-11 17:25:19 +00:00
f4bec95b58
f32 / f64 node is expanded to one i32 / i64 node.
...
llvm-svn: 32433
2006-12-11 06:50:04 +00:00
f6b01fdb48
Clean up some bad code.
...
llvm-svn: 32432
2006-12-11 06:25:26 +00:00
8e20c760fa
Move something that should be in the dag combiner from the legalizer to the
...
dag combiner.
llvm-svn: 32431
2006-12-11 02:23:46 +00:00
e8da58b3f9
Properly mangles symbol table names
...
Supports constant pools
Supports relocations to jump tables
Supports relocations within the data segment (global = address of global)
Allocates memory in a non-hacky for all non-code objects.
llvm-svn: 32430
2006-12-11 02:20:45 +00:00
3b7c257cae
Cleaned setjmp/longjmp lowering interfaces. Now we're producing right
...
code (both asm & cbe) for Mingw32 target.
Removed autoconf checks for underscored versions of setjmp/longjmp.
llvm-svn: 32415
2006-12-10 23:12:42 +00:00
4eee72471c
Preliminary soft float support.
...
llvm-svn: 32394
2006-12-09 02:42:38 +00:00
78cb08d082
Move findTiedToSrcOperand to TargetInstrDescriptor.
...
llvm-svn: 32366
2006-12-08 18:45:48 +00:00
bb4e6d4d12
Proper fix for PR1037: to determine is a VR is a modref, check 1) whether it is
...
tied to another oeprand, 2) whether is is being tied to by another operand. So
the destination operand of a two-address MI can be correctly identified.
llvm-svn: 32354
2006-12-08 08:02:34 +00:00
4539418a7b
findTiedToSrcOperand() changed.
...
llvm-svn: 32353
2006-12-08 07:59:51 +00:00
d9f04e4875
Fix CodeGen/PowerPC/2006-12-07-SelectCrash.ll on PPC64
...
llvm-svn: 32336
2006-12-07 22:36:47 +00:00
355fc5ad50
Removed more <iostream> includes
...
llvm-svn: 32321
2006-12-07 20:28:15 +00:00
22e978a736
Removing even more <iostream> includes.
...
llvm-svn: 32320
2006-12-07 20:04:42 +00:00
e44aa812b4
Revision 1.83 causes PR1037.
...
Reverted.
llvm-svn: 32305
2006-12-07 16:21:19 +00:00
c41ed4e0e1
Initialize {Min|Max}CSFrameIndex properly.
...
llvm-svn: 32299
2006-12-07 02:25:34 +00:00
f3baad3ee1
Changed llvm_ostream et all to OStream. llvm_cerr, llvm_cout, llvm_null, are
...
now cerr, cout, and NullStream resp.
llvm-svn: 32298
2006-12-07 01:30:32 +00:00
e312c152d2
MI keeps a ptr of TargetInstrDescriptor, use it.
...
llvm-svn: 32296
2006-12-07 01:21:59 +00:00
7074cbd449
getOperandConstraint returns -1 if the operand does have the specific constraint. This bug was causing excessive spills.
...
llvm-svn: 32295
2006-12-07 00:46:04 +00:00
700b873130
Detemplatize the Statistic class. The only type it is instantiated with
...
is 'unsigned'.
llvm-svn: 32279
2006-12-06 17:46:33 +00:00
acbb456dde
Some addresssed should be 64-bit and some shouldn't.
...
llvm-svn: 32278
2006-12-06 17:43:18 +00:00
75c2194b1a
Move copyKillDeadInfo out-of-line. Add findRegisterUseOperand().
...
llvm-svn: 32273
2006-12-06 08:27:42 +00:00
979804d800
eliminate fp statistic
...
llvm-svn: 32251
2006-12-06 01:48:55 +00:00
cc08c83186
Unbreak VC++ build.
...
llvm-svn: 32113
2006-12-02 02:22:01 +00:00
67fc141db5
Match TargetInstrInfo changes.
...
llvm-svn: 32098
2006-12-01 21:52:58 +00:00
f52337299a
better check for version
...
llvm-svn: 32045
2006-11-30 18:29:23 +00:00
b5b14060a8
Change global descriptor names to provide name, full name and linkage name.
...
llvm-svn: 32036
2006-11-30 14:35:45 +00:00
aa2843ad4a
Temp fix to deal gdb issue.
...
llvm-svn: 32035
2006-11-30 11:09:42 +00:00
3c3ce98530
- MachineInstr now keeps a ptr to TargetInstrDescriptor instead of Opcode.
...
- Remove the ugly TargetInstrDescriptors hack.
llvm-svn: 32032
2006-11-30 07:08:44 +00:00
a743fada65
Avoid inifinite looping if READCYCLECOUNTER isn't custom lowered.
...
llvm-svn: 32022
2006-11-29 19:13:47 +00:00
01b74b6f7b
Eliminate unnecessary scopes.
...
llvm-svn: 32020
2006-11-29 16:55:57 +00:00
6973993e9c
Allow target to custom lower READCYCLECOUNTER (when it doesn't have to be expanded).
...
llvm-svn: 32016
2006-11-29 08:26:18 +00:00
feba507a97
Fix for PR1023 by Dan Gohman.
...
llvm-svn: 32003
2006-11-29 01:58:12 +00:00
6e12a052ff
Fix for PR1022 (folding loads of static initializers) by Dan Gohman.
...
llvm-svn: 32000
2006-11-29 01:38:07 +00:00
90f4238c38
add a hook to allow targets to hack on inline asms to lower them to llvm
...
when they want to.
llvm-svn: 31997
2006-11-29 01:12:32 +00:00
5c3966aa68
Converted to using llvm streams instead of <iostream>s
...
llvm-svn: 31992
2006-11-29 00:39:47 +00:00
787b77320f
Use llvm streams instead of <iostream>
...
llvm-svn: 31985
2006-11-28 22:48:48 +00:00
bc0d5f8bcb
Put the #include for a module first.
...
llvm-svn: 31958
2006-11-28 03:31:29 +00:00
b2a6b0dbad
Clean up.
...
llvm-svn: 31957
2006-11-28 02:25:34 +00:00
3f6f0fd028
Changed to using llvm streams.
...
llvm-svn: 31954
2006-11-28 02:08:17 +00:00
3abb63651b
Fix PR1016
...
llvm-svn: 31950
2006-11-28 01:03:30 +00:00
20350c4025
Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead
...
of opcode and number of operands.
llvm-svn: 31947
2006-11-27 23:37:22 +00:00
5d5916b4d1
Fix the dag combiner bug corresponding to PR1014.
...
llvm-svn: 31943
2006-11-27 21:50:02 +00:00
3da631f29a
For better or worse, load from i1 is assumed to be zero extended. Do not
...
form a load from i1 from larger loads that may not be zext'd.
llvm-svn: 31933
2006-11-27 04:40:53 +00:00
db18938355
If a brcond condition is promoted, make sure to zero extend it, even if not
...
expanded into BR_CC.
llvm-svn: 31932
2006-11-27 04:39:56 +00:00
6c38f0bb07
For PR950:
...
The long awaited CAST patch. This introduces 12 new instructions into LLVM
to replace the cast instruction. Corresponding changes throughout LLVM are
provided. This passes llvm-test, llvm/test, and SPEC CPUINT2000 with the
exception of 175.vpr which fails only on a slight floating point output
difference.
llvm-svn: 31931
2006-11-27 01:05:10 +00:00
d7f53cdaec
Global label not handled correctly.
...
llvm-svn: 31883
2006-11-20 20:29:06 +00:00
3676a994ca
Fix PR1011 and CodeGen/Generic/2006-11-20-DAGCombineCrash.ll
...
llvm-svn: 31878
2006-11-20 18:05:46 +00:00
539df43e4b
setOperand should not zap the operand list or add implicit operands to an
...
instruction. Doing so breaks the FP stackifier, the alpha branch selector
the sparc fpmover.
This fixes PR1012 and CodeGen/X86/fp-stack-compare.ll
llvm-svn: 31876
2006-11-20 17:57:22 +00:00
d9436b6837
For PR950:
...
First in a series of patches to convert SetCondInst into ICmpInst and
FCmpInst using only two opcodes and having the instructions contain their
predicate value. Nothing uses these classes yet. More patches to follow.
llvm-svn: 31867
2006-11-20 01:22:35 +00:00
ea017f66f7
Don't transform in another bad case: if the block is empty, it should be
...
simplified before we do this xform so that our cost model is accurate.
llvm-svn: 31864
2006-11-18 22:25:39 +00:00
56ec81ff73
Fix another case we *don't* want to do this xform.
...
llvm-svn: 31861
2006-11-18 21:56:39 +00:00
ace542fa6c
Implement operator<< for machine basic blocks to make it easier to dump them.
...
llvm-svn: 31857
2006-11-18 21:47:36 +00:00
7acdc17fe4
make the previous change more aggressive, moving any block with no fallthrough.
...
This speeds up yacr2 by 7% on a core2.
llvm-svn: 31856
2006-11-18 21:30:35 +00:00
47ce26158f
Minor code layout tweak: if we have something like this:
...
if (cond) goto BB2
BB1:
...
return;
BB2:
...
Move BB1 to the end of the function so that the code falls through in the
non-return case. This has the effect of moving assert (and other no-return
call) bodies and return blocks out of loops.
llvm-svn: 31855
2006-11-18 20:47:54 +00:00
da0add3fd0
Fixing the ENABLE_OPTIMIZED=1 DISABLE_ASSERTIONS=1 build.
...
llvm-svn: 31822
2006-11-17 13:07:55 +00:00
9d46fcd59c
More removal of std::cerr and DEBUG, replacing with DOUT instead.
...
llvm-svn: 31806
2006-11-17 02:09:07 +00:00
d108b9a60d
Replace std::cerr uses of the "DEBUG" macro with "DOUT" instead. Removes
...
a #include of iostream.
llvm-svn: 31800
2006-11-17 00:50:36 +00:00
8969ebca44
*** empty log message ***
...
llvm-svn: 31789
2006-11-16 20:11:33 +00:00
9fd73b8a7f
Match MachineCodeEmitter changes.
...
llvm-svn: 31787
2006-11-16 20:04:04 +00:00
d811cc6818
Don't recompute getNumOperands for each iteration.
...
llvm-svn: 31783
2006-11-16 07:35:18 +00:00
c7969fd1e7
Added a new method "CreateNewLiveInterval" which, given a list of
...
LiveRanges, creates a new LiveInterval from them. The LiveRanges should
have existed already in another LiveInterval, but removed.
llvm-svn: 31780
2006-11-16 02:41:50 +00:00
e0a70388c2
enable the branch folding pass for the JIT.
...
llvm-svn: 31777
2006-11-16 01:00:07 +00:00
f64da389f8
Fix an incorrectly inverted condition.
...
llvm-svn: 31773
2006-11-16 00:08:20 +00:00
0ffff1c629
Match live variable changes.
...
llvm-svn: 31762
2006-11-15 20:55:15 +00:00
ebb0357b4c
Minor updates.
...
llvm-svn: 31761
2006-11-15 20:54:29 +00:00
12ea213de9
A register def can be partially dead when the whole register has use(s) but a subreg does not.
...
llvm-svn: 31760
2006-11-15 20:54:11 +00:00
70ec52896e
Do away with kill / dead maps. Move kill / dead info onto MI's.
...
llvm-svn: 31759
2006-11-15 20:51:59 +00:00
2775aba51d
Simplify IntrinsicLowering and clarify that it is only for use by the
...
CBE and interpreter.
llvm-svn: 31755
2006-11-15 18:00:10 +00:00
30d08801ef
remove dead #include
...
llvm-svn: 31753
2006-11-15 17:51:15 +00:00
dbd3d294e6
Matches MachineInstr changes.
...
llvm-svn: 31712
2006-11-13 23:36:35 +00:00
77af6ac5e8
- Let MachineInstr ctors add implicit def and use operands. Other operands
...
will be inserted before these operands. If the opcode changes (by
setOpcode), the implicit operands are updated as well.
- Added IsKill, IsDead fields to MachineOperand in preparation for changes
that move kill / dead info to MachineInstr's.
llvm-svn: 31711
2006-11-13 23:34:06 +00:00
2230144a75
Make an assert comment match the tested assertion.
...
llvm-svn: 31686
2006-11-11 20:07:59 +00:00
979bbf48d5
Add methods to add implicit def use operands to a MI.
...
llvm-svn: 31675
2006-11-11 10:20:02 +00:00
a0a8003f59
disallow preinc of a frameindex. This is not profitable and causes 2-addr
...
pass to explode. This fixes a bunch of llc-beta failures on ppc last night.
llvm-svn: 31661
2006-11-11 01:00:15 +00:00
eabc15c1d8
reduce indentation by using early exits. No functionality change.
...
llvm-svn: 31660
2006-11-11 00:56:29 +00:00
ffad2166e1
move big chunks of code out-of-line, no functionality change.
...
llvm-svn: 31658
2006-11-11 00:39:41 +00:00
4eac5f59e6
Fix a dag combiner bug exposed by my recent instcombine patch. This fixes
...
CodeGen/Generic/2006-11-10-DAGCombineMiscompile.ll and PPC gsm/toast
llvm-svn: 31644
2006-11-10 21:37:15 +00:00
8c9c6d71ed
Add implicit def / use operands to MachineInstr.
...
llvm-svn: 31633
2006-11-10 08:43:01 +00:00
13440b025c
When forming a pre-indexed store, make sure ptr isn't the same or is a pred of value being stored. It would cause a cycle.
...
llvm-svn: 31631
2006-11-10 08:28:11 +00:00
d5e604dbb2
commentate
...
llvm-svn: 31627
2006-11-10 04:41:34 +00:00
6878378390
Don't attempt expensive pre-/post- indexed dag combine if target does not support them.
...
llvm-svn: 31598
2006-11-09 19:10:46 +00:00
d550248f2c
Add a mechanism to specify whether a target supports a particular indexed load / store.
...
llvm-svn: 31597
2006-11-09 18:56:43 +00:00
c034f14fbe
Rename ISD::MemOpAddrMode to ISD::MemIndexedMode
...
llvm-svn: 31596
2006-11-09 18:44:21 +00:00
b15000736c
Rename ISD::MemOpAddrMode to ISD::MemIndexedMode
...
llvm-svn: 31595
2006-11-09 17:55:04 +00:00
f1606b80f1
Allows debugging llc self hosted.
...
llvm-svn: 31594
2006-11-09 16:32:26 +00:00
97f89b11b3
Merging dwarf info to a single compile unit.
...
llvm-svn: 31593
2006-11-09 14:52:14 +00:00
b58e06bc9e
getPostIndexedAddressParts change: passes in load/store instead of its loaded / stored VT.
...
llvm-svn: 31584
2006-11-09 04:29:46 +00:00
1698c2999c
Remove M_2_ADDR_FLAG.
...
llvm-svn: 31583
2006-11-09 02:22:54 +00:00
85e54223cd
Match more post-indexed ops.
...
llvm-svn: 31569
2006-11-08 20:27:27 +00:00
61feeb90f9
Remove redundant <cmath>.
...
llvm-svn: 31561
2006-11-08 19:16:44 +00:00
62bbc9ef58
Now can re-enable debug label folding.
...
llvm-svn: 31549
2006-11-08 14:17:45 +00:00
0303cb9b33
- When performing pre-/post- indexed load/store transformation, do not worry
...
about whether the new base ptr would be live below the load/store. Let two
address pass split it back to non-indexed ops.
- Minor tweaks / fixes.
llvm-svn: 31544
2006-11-08 08:30:28 +00:00
6072435756
Fixed a minor bug preventing some pre-indexed load / store transformation.
...
llvm-svn: 31543
2006-11-08 06:56:05 +00:00
fdff938a7e
For PR950:
...
This patch converts the old SHR instruction into two instructions,
AShr (Arithmetic) and LShr (Logical). The Shr instructions now are not
dependent on the sign of their operands.
llvm-svn: 31542
2006-11-08 06:47:33 +00:00
d48f7dd250
Fix a obscure post-indexed load / store dag combine bug.
...
llvm-svn: 31537
2006-11-08 02:38:55 +00:00
bf3b57f221
optimize single MBB loops better. In particular, produce:
...
LBB1_57: #bb207.i
movl 72(%esp), %ecx
movb (%ecx,%eax), %cl
movl 80(%esp), %edx
movb %cl, 1(%edx,%eax)
incl %eax
cmpl $143, %eax
jne LBB1_57 #bb207.i
jmp LBB1_64 #cond_next255.i
intead of:
LBB1_57: #bb207.i
movl 72(%esp), %ecx
movb (%ecx,%eax), %cl
movl 80(%esp), %edx
movb %cl, 1(%edx,%eax)
incl %eax
cmpl $143, %eax
je LBB1_64 #cond_next255.i
jmp LBB1_57 #bb207.i
This eliminates a branch per iteration of the loop. This hurted PPC
particularly, because the extra branch meant another dispatch group for each
iteration of the loop.
llvm-svn: 31530
2006-11-08 01:03:21 +00:00
21d4d895ca
Accidently reran commit.
...
llvm-svn: 31516
2006-11-07 21:58:55 +00:00
a919ba9abd
Missed a label map, reverting till covered.
...
llvm-svn: 31514
2006-11-07 21:37:31 +00:00
21ce53b94e
Missed a label map, reverting till covered.
...
llvm-svn: 31512
2006-11-07 20:53:05 +00:00
6ea4fae838
1. Add a pass to fold debug label instructions so a debug info client can detect
...
empty ranges.
2. Reorg how MachineDebugInfo maintains changes to debug labels.
3. Have dwarf writer use debug label info to simplify scopes and source line
coorespondence.
4. Revert the merging of compile units until I can get the bugs ironed out.
llvm-svn: 31507
2006-11-07 19:33:46 +00:00
b18177bfab
Enable improved spilling costs by default. This speeds up viterbi on x86
...
by 40%, FreeBench/fourinarow by 20%, and many other programs 10-25%.
On PPC, this speeds up fourinarow by 18%, and probably other things as well.
llvm-svn: 31504
2006-11-07 18:04:58 +00:00
6a9342166b
Use correct value for float HUGH_VAL.
...
llvm-svn: 31500
2006-11-07 12:25:45 +00:00
60c6846d21
Add post-indexed load / store transformations.
...
llvm-svn: 31498
2006-11-07 09:03:05 +00:00
01d039cc44
Add a new llcbeta option. This speeds up viterbi from 12.34 to 8.76s on
...
X86. If happy, I'll enable this by default.
llvm-svn: 31493
2006-11-07 07:18:40 +00:00
78c84a0328
Unbreak X86/ELF Debugging. Somehow this line got lost in Jim's cleanup.
...
llvm-svn: 31492
2006-11-07 06:36:36 +00:00
94c231f453
Fix PR988 and CodeGen/Generic/2006-11-06-MemIntrinsicExpand.ll.
...
The low part goes in the first operand of expandop, not the second one.
llvm-svn: 31487
2006-11-07 04:11:44 +00:00
f24d15f969
Remove dead code; added a missing null ptr check.
...
llvm-svn: 31478
2006-11-06 21:33:46 +00:00
235aeef9e1
Tab interferes with uniqueness.
...
NOTE: There doesn't seem to be consistency for whether a leading tab
is present in a section heading.
llvm-svn: 31475
2006-11-06 16:23:59 +00:00
f39064c2de
D'oh - reversed logic.
...
llvm-svn: 31474
2006-11-06 13:20:29 +00:00
eb99bd736a
Add comment.
...
llvm-svn: 31473
2006-11-06 08:14:30 +00:00
7d6f3db3e2
Unbreak VC++ build.
...
llvm-svn: 31464
2006-11-05 19:31:28 +00:00
33157700d9
Added pre-indexed store support.
...
llvm-svn: 31459
2006-11-05 09:31:14 +00:00
1a1e23eff7
Added getIndexedStore.
...
llvm-svn: 31458
2006-11-05 09:30:09 +00:00
01c55a50b1
Live local variables are being dropped because the begin or end labels marking
...
their scope are being deleted. Workaround is to widen scope to full function.
llvm-svn: 31454
2006-11-04 10:48:07 +00:00
fd2c5dd806
Changes to use operand constraints to process two-address instructions.
...
llvm-svn: 31453
2006-11-04 09:44:31 +00:00
51733ed4a3
Fixed some spiller bugs exposed by the recent two-address code changes. Now
...
there may be other def(s) apart from the use&def two-address operand. We need
to check if the register reuse for a use&def operand may conflicts with another
def. Provide a mean to recover from the conflict if it is detected when the
defs are processed later.
llvm-svn: 31439
2006-11-04 00:21:55 +00:00
bb3ea2a437
this will work better
...
llvm-svn: 31419
2006-11-03 19:15:55 +00:00
a35f8c16c4
Fix the build on xcode < 2.4
...
llvm-svn: 31417
2006-11-03 19:13:59 +00:00
9456dd8b81
Fix comments.
...
llvm-svn: 31414
2006-11-03 07:31:32 +00:00
1dfd26a151
Rename
...
llvm-svn: 31413
2006-11-03 07:21:16 +00:00
52f958741a
Remove dead variable. Fix 80 column violations.
...
llvm-svn: 31412
2006-11-03 03:30:34 +00:00
357017f4a9
Added DAG combiner transformation to generate pre-indexed loads.
...
llvm-svn: 31410
2006-11-03 03:06:21 +00:00
c176f038b9
Added isPredecessor.
...
llvm-svn: 31409
2006-11-03 03:05:24 +00:00
299022d514
Proper check for two-addressness.
...
llvm-svn: 31408
2006-11-03 03:04:46 +00:00
cd7b92251d
silence warning
...
llvm-svn: 31397
2006-11-03 01:28:29 +00:00
cb67d99001
Make CodeGen libs -pedantic clean.
...
llvm-svn: 31387
2006-11-02 23:56:21 +00:00
15d166ba8f
1. Hash not quite right for DIEValues.
...
2. Not going to use Usage (no significant benefit.)
llvm-svn: 31384
2006-11-02 21:48:18 +00:00
9ec8a7555b
Remove unused variable.
...
llvm-svn: 31382
2006-11-02 20:55:40 +00:00
de46e48420
For PR786:
...
Turn on -Wunused and -Wno-unused-parameter. Clean up most of the resulting
fall out by removing unused variables. Remaining warnings have to do with
unused functions (I didn't want to delete code without review) and unused
variables in generated code. Maintainers should clean up the remaining
issues when they see them. All changes pass DejaGnu tests and Olden.
llvm-svn: 31380
2006-11-02 20:25:50 +00:00
936d546eca
General clean up of teh dwarf writer.
...
1. Most significant is the folding of debug information entries. This
reduced self hosted -g SelectionDAGISel.s from 120M to 13M and pretty
close to matching .o file sizes with gcc.
2. Debug information entry printing for debugging the dwarf code.
3. Bring all the code closer to llvm standards.
4. Misc. fixes and doc clean ups.
llvm-svn: 31379
2006-11-02 20:12:39 +00:00
7eb55b395f
For PR950:
...
Replace the REM instruction with UREM, SREM and FREM.
llvm-svn: 31369
2006-11-02 01:53:59 +00:00
55402d4403
Allow the getRegForInlineAsmConstraint method to return a register class with
...
no fixes physreg. Treat this as permission to use any register in the register
class. When this happens and it is safe, allow the llvm register allcoator to
allocate the register instead of doing it at isel time. This eliminates a ton
of copies around common inline asms. For example:
int test2(int Y, int X) {
asm("foo %0, %1" : "=r"(X): "r"(X));
return X;
}
now compiles to:
_test2:
foo r3, r4
blr
instead of:
_test2:
mr r2, r4
foo r2, r2
mr r3, r2
blr
GCC produces:
_test2:
foo r4, r4
mr r3,r4
blr
llvm-svn: 31366
2006-11-02 01:41:49 +00:00
93cdd149f7
Rename
...
llvm-svn: 31364
2006-11-01 23:18:32 +00:00
d8697deca3
Two-address instructions no longer have to be A := A op C. Now any pair of dest / src operands can be tied together.
...
llvm-svn: 31363
2006-11-01 23:06:55 +00:00
1359196c4e
Clean up.
...
llvm-svn: 31359
2006-11-01 22:39:30 +00:00
47218fab42
CopyFromReg starts a live range so its use should not be considered a floater.
...
llvm-svn: 31356
2006-11-01 22:17:06 +00:00
7cee6ddcd8
give branch folding a simple heuristic to decide which block to split so that
...
it inserts an uncond branch where it is less likely to cause a problem. This
fixes some perf issues on ppc.
llvm-svn: 31354
2006-11-01 19:36:29 +00:00
91f120f4fa
Add a printSetLabel that takes two id's.
...
llvm-svn: 31347
2006-11-01 09:23:08 +00:00
415f365e5c
Print jumptable index.
...
llvm-svn: 31340
2006-11-01 04:48:30 +00:00
f505a5a063
make tail merging more aggressive. If two blocks share a common tail, but the
...
tail is not an entire block for either of them, pick one, split it, then
merge the common part.
llvm-svn: 31336
2006-11-01 01:16:12 +00:00
3ac71b31f0
enable branch folding with an option
...
llvm-svn: 31335
2006-11-01 00:38:31 +00:00
fe43befeda
Compile CodeGen/PowerPC/fp-branch.ll to:
...
_intcoord_cond_next55:
LBB1_3: ;cond_next55
lis r2, ha16(LCPI1_0)
lfs f0, lo16(LCPI1_0)(r2)
fcmpu cr0, f1, f0
blt cr0, LBB1_2 ;cond_next62.exitStub
LBB1_1: ;bb72.exitStub
li r3, 1
blr
LBB1_2: ;cond_next62.exitStub
li r3, 0
blr
instead of:
_intcoord_cond_next55:
LBB1_3: ;cond_next55
lis r2, ha16(LCPI1_0)
lfs f0, lo16(LCPI1_0)(r2)
fcmpu cr0, f1, f0
bge cr0, LBB1_1 ;bb72.exitStub
LBB1_4: ;cond_next55
lis r2, ha16(LCPI1_0)
lfs f0, lo16(LCPI1_0)(r2)
fcmpu cr0, f1, f0
bnu cr0, LBB1_2 ;cond_next62.exitStub
LBB1_1: ;bb72.exitStub
li r3, 1
blr
LBB1_2: ;cond_next62.exitStub
li r3, 0
blr
llvm-svn: 31330
2006-10-31 23:06:00 +00:00
427301fdae
look through isunordered to inline it into branch blocks.
...
llvm-svn: 31328
2006-10-31 22:37:42 +00:00
1fd360e13a
handle global address constant sdnodes
...
llvm-svn: 31323
2006-10-31 20:01:56 +00:00
6f043b90ea
TargetLowering::isOperandValidForConstraint
...
llvm-svn: 31319
2006-10-31 19:41:18 +00:00
8c6949e5b2
Change the prototype for TargetLowering::isOperandValidForConstraint
...
llvm-svn: 31318
2006-10-31 19:40:43 +00:00
aa4c0f9374
1. Clean up code due to changes in SwitchTo*Section(2)
...
2. Added partial debug support for mingw\cygwin targets (the same as
Linux\ELF). Please note, that currently mingw\cygwin uses 'stabs' format
for storing debug info by default, thus many (runtime) libraries has
this information included. These formats shouldn't be mixed in one binary
('stabs' & 'DWARF'), otherwise binutils tools will be confused.
llvm-svn: 31311
2006-10-31 08:31:24 +00:00
968f803928
Turn an assert into an error message. This is commonly triggered when
...
we don't support a specific constraint yet. When this happens, print the
unsupported constraint.
llvm-svn: 31310
2006-10-31 07:33:13 +00:00
e6d584765f
Fix a typo which can break jumptables.
...
llvm-svn: 31305
2006-10-31 02:31:00 +00:00
7eda51d4cf
Fix a problem introduced by a last-minute change (logic negation).
...
llvm-svn: 31302
2006-10-30 23:34:32 +00:00
b51b5c0b1f
Add debug support for X86/ELF targets (Linux). This allows llvm-gcc4
...
generated object modules to be debugged with gdb. Hopefully this helps
pre-release debugging.
llvm-svn: 31299
2006-10-30 22:32:30 +00:00
ad2f5b7d18
Switch abbreviations to use the folding set.a.
...
llvm-svn: 31296
2006-10-30 15:59:54 +00:00
43c19124bb
Simplify DwarfWriter header.
...
llvm-svn: 31295
2006-10-30 13:35:07 +00:00
84a28d4e76
Lower jumptable to BR_JT. The legalizer can lower it to a BRIND or let the target custom lower it.
...
llvm-svn: 31293
2006-10-30 08:00:44 +00:00
c3e695137d
Added a new SDNode type: BR_JT for jumptable branch.
...
llvm-svn: 31292
2006-10-30 07:59:36 +00:00
504eeda365
Make CanFallThrough more intelligent (so it can handle blocks with (e.g.) no
...
successors), and make island block movement more general.
This compiles CodeGen/X86/2006-04-27-ISelFoldingBug.ll to:
_loadAndRLEsource_no_exit_2E_1_label_2E_0:
subl $8, %esp
movl %esi, 4(%esp)
movl %ebx, (%esp)
movl 16(%esp), %eax
movl 12(%esp), %ecx
LBB1_3: #label.0
movl _last, %edx
movl %edx, %esi
incl %esi
movl %esi, _last
movl %ecx, %ebx
# TRUNCATE movb %bl, %bl
movl _block, %esi
movb %bl, 1(%esi,%edx)
cmpl %eax, _last
jge LBB1_2 #codeRepl5.exitStub
LBB1_4: #label.0
cmpl $257, %ecx
je LBB1_2 #codeRepl5.exitStub
LBB1_1: #label.0.no_exit.1_crit_edge.exitStub
movl $1, %eax
movl (%esp), %ebx
movl 4(%esp), %esi
addl $8, %esp
ret
LBB1_2: #codeRepl5.exitStub
xorl %eax, %eax
movl (%esp), %ebx
movl 4(%esp), %esi
addl $8, %esp
ret
instead of:
_loadAndRLEsource_no_exit_2E_1_label_2E_0:
subl $8, %esp
movl %esi, 4(%esp)
movl %ebx, (%esp)
movl 16(%esp), %eax
movl 12(%esp), %ecx
jmp LBB1_3 #label.0
LBB1_1: #label.0.no_exit.1_crit_edge.exitStub
movl $1, %eax
movl (%esp), %ebx
movl 4(%esp), %esi
addl $8, %esp
ret
LBB1_2: #codeRepl5.exitStub
xorl %eax, %eax
movl (%esp), %ebx
movl 4(%esp), %esi
addl $8, %esp
ret
LBB1_3: #label.0
movl _last, %edx
movl %edx, %esi
incl %esi
movl %esi, _last
movl %ecx, %ebx
# TRUNCATE movb %bl, %bl
movl _block, %esi
movb %bl, 1(%esi,%edx)
cmpl %eax, _last
jge LBB1_2 #codeRepl5.exitStub
LBB1_4: #label.0
cmpl $257, %ecx
jne LBB1_1 #label.0.no_exit.1_crit_edge.exitStub
jmp LBB1_2 #codeRepl5.exitStub
... which is much better layout :)
llvm-svn: 31282
2006-10-29 21:05:41 +00:00
e60ae823e8
fix Generic/2006-10-29-Crash.ll
...
llvm-svn: 31281
2006-10-29 21:01:20 +00:00
f31b9ef458
Fix a load folding issue that Evan noticed: there is no need to export values
...
used by comparisons in the main block.
llvm-svn: 31279
2006-10-29 18:23:37 +00:00
7ab6123c42
VLOAD is not the LoadSDNode opcode.
...
llvm-svn: 31276
2006-10-29 06:14:47 +00:00
dc146a9fb9
Remove spurious case. EXTLOAD is not one of the node opcodes.
...
llvm-svn: 31275
2006-10-29 02:26:30 +00:00
bba52191fa
split critical edges more carefully and intelligently. In particular, critical
...
edges whose destinations are not phi nodes don't bother us. Also, share
split edges, since the split edge can't have a phi. This significantly
reduces the complexity of generated code in some cases.
llvm-svn: 31274
2006-10-28 19:22:10 +00:00
c07657f59b
Teach branch folding to fold identical jump tables together and to delete
...
jump tables that are dead.
llvm-svn: 31273
2006-10-28 18:34:47 +00:00
cde339cf1e
const'ify jump table stuff
...
llvm-svn: 31269
2006-10-28 18:17:09 +00:00
28328f9a0a
add an assert
...
llvm-svn: 31267
2006-10-28 18:11:20 +00:00
28bfe389d1
don't print dead jump tables
...
llvm-svn: 31266
2006-10-28 18:10:06 +00:00
af8383806b
improve deletion of blocks that just contain branches by knowing that
...
the pred block doesn't fall through into them if it's a jumptable.
llvm-svn: 31263
2006-10-28 17:32:47 +00:00
eef273a16f
Load and stores have not been uniqued properly.
...
llvm-svn: 31261
2006-10-28 17:25:28 +00:00
3e6b1c6157
Split *all* critical edges before isel. This resolves issues with spill code
...
being inserted on unsplit critical edges, which introduces (sometimes large
amounts of) partially dead spill code.
This also fixes PR925 + CodeGen/Generic/switch-crit-edge-constant.ll
llvm-svn: 31260
2006-10-28 17:04:37 +00:00
b78eb6c8d1
Fix a serious bug that caused any x86 vector stuff to infinite loop
...
llvm-svn: 31254
2006-10-28 06:15:26 +00:00
bd0f088743
Clean up.
...
llvm-svn: 31243
2006-10-27 23:52:51 +00:00
84a035056e
Fix a bug in merged condition handling (CodeGen/Generic/2006-10-27-CondFolding.ll).
...
Add many fewer CFG edges and PHI node entries. If there is a switch which has
the same block as multiple destinations, only add that block once as a successor/phi
node (in the jumptable case)
llvm-svn: 31242
2006-10-27 23:50:33 +00:00
f576b42bb2
Switch over from SelectionNodeCSEMap to FoldingSet.
...
llvm-svn: 31240
2006-10-27 23:46:08 +00:00
b9392fb635
remove debug code
...
llvm-svn: 31233
2006-10-27 21:58:03 +00:00
f1b54fd7a5
Codegen cond&cond with two branches. This compiles (f.e.) PowerPC/and-branch.ll to:
...
cmpwi cr0, r4, 4
bgt cr0, LBB1_2 ;UnifiedReturnBlock
LBB1_3: ;entry
cmplwi cr0, r3, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
instead of:
cmpwi cr7, r4, 4
mfcr r2
addic r4, r3, -1
subfe r3, r4, r3
rlwinm r2, r2, 30, 31, 31
or r2, r2, r3
cmplwi cr0, r2, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
LBB1_1: ;cond_true
llvm-svn: 31232
2006-10-27 21:54:23 +00:00
ed0110b949
Turn conditions like x<Y|z==q into multiple blocks.
...
This compiles Regression/CodeGen/X86/or-branch.ll into:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $5, %eax
jl LBB1_1 #cond_true
LBB1_3: #entry
testl %ecx, %ecx
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
instead of:
_foo:
subl $12, %esp
call L_bar$stub
movl 20(%esp), %eax
movl 16(%esp), %ecx
cmpl $4, %eax
setg %al
testl %ecx, %ecx
setne %cl
testb %cl, %al
jne LBB1_2 #UnifiedReturnBlock
LBB1_1: #cond_true
call L_bar$stub
addl $12, %esp
ret
LBB1_2: #UnifiedReturnBlock
addl $12, %esp
ret
And on ppc to:
cmpwi cr0, r29, 5
blt cr0, LBB1_1 ;cond_true
LBB1_3: ;entry
cmplwi cr0, r30, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
instead of:
cmpwi cr7, r4, 4
mfcr r2
addic r4, r3, -1
subfe r30, r4, r3
rlwinm r29, r2, 30, 31, 31
and r2, r29, r30
cmplwi cr0, r2, 0
bne cr0, LBB1_2 ;UnifiedReturnBlock
llvm-svn: 31230
2006-10-27 21:36:01 +00:00
96d6bf50ae
getPreIndexedLoad -> getIndexedLoad.
...
llvm-svn: 31209
2006-10-26 21:53:40 +00:00
7e80b0b31e
For PR950:
...
Make necessary changes to support DIV -> [SUF]Div. This changes llvm to
have three division instructions: signed, unsigned, floating point. The
bytecode and assembler are bacwards compatible, however.
llvm-svn: 31195
2006-10-26 06:15:43 +00:00
0d4479b77d
simplify code
...
llvm-svn: 31188
2006-10-25 22:21:37 +00:00
9feb308d51
turn off tail merging for now
...
llvm-svn: 31180
2006-10-25 18:08:50 +00:00
7a7835deb4
be more aggressive about matching identical instructions.
...
llvm-svn: 31179
2006-10-25 18:08:14 +00:00
71b99297aa
Move getPreferredAlignmentLog from AsmPrinter to TargetData
...
llvm-svn: 31171
2006-10-24 20:32:14 +00:00
61bcf9154d
visitSwitchCase knows how to insert conditional branches well. Change
...
visitBr to just call visitSwitchCase, eliminating duplicate logic.
llvm-svn: 31167
2006-10-24 18:07:37 +00:00
963ddad31a
Generalize CaseBlock a bit more:
...
Rename LHSBB/RHSBB to TrueBB/FalseBB. Allow the RHS value to be null,
in which case the LHS is treated as a bool.
llvm-svn: 31166
2006-10-24 17:57:59 +00:00
3f179d24c6
generalize 'CaseBlock'. It really allows any comparison to be inserted.
...
llvm-svn: 31161
2006-10-24 17:03:35 +00:00
1941bfa361
Don't do dead block elimination in fast mode.
...
llvm-svn: 31155
2006-10-24 16:11:49 +00:00
a916192267
LinearScanner hotspot.
...
llvm-svn: 31153
2006-10-24 14:35:25 +00:00
516cd40b5c
Tighter data structure for deleted debug labels.
...
llvm-svn: 31152
2006-10-24 11:50:43 +00:00
ceb51d8427
move single basic blocks that are neither fallen into nor fall out of into
...
a place more useful. In particular, if we can put them in a place where code
will be able to fall into it, do so. Otherwise, put it in a place it can fall
through into a successor. Otherwise, if preventing a fallthrough, move to the
end of the function, out of the way.
This deletes several hundred unconditional branches from spass.
llvm-svn: 31149
2006-10-24 01:12:32 +00:00
94866bef35
add moveBefore/moveAfter helper methods
...
llvm-svn: 31145
2006-10-24 00:02:26 +00:00
ebdb1d6724
Enable tail merging by default.
...
llvm-svn: 31140
2006-10-23 22:10:12 +00:00
4c931502cc
Minor tweak. Instead of generating:
...
movl 32(%esp), %eax
cmpl $1, %eax
je LBB1_1 #bb
LBB1_4: #entry
cmpl $2, %eax
je LBB1_2 #bb2
jmp LBB1_3 #UnifiedReturnBlock
LBB1_1: #bb
notice that we would miss the fall through and emit this instead:
movl 32(%esp), %eax
cmpl $2, %eax
je LBB1_2 #bb2
LBB1_4: #entry
cmpl $1, %eax
jne LBB1_3 #UnifiedReturnBlock
LBB1_1: #bb
llvm-svn: 31130
2006-10-23 18:38:22 +00:00
5e1a34032b
More complete solution to deleting blocks and debug info.
...
llvm-svn: 31129
2006-10-23 14:56:37 +00:00
76a7bc8c55
Fix phi node updating for switches lowered to linear sequences of branches.
...
llvm-svn: 31125
2006-10-22 23:00:53 +00:00
4c3ef4782d
disable this code for now, it's not yet safely updating phi nodes
...
llvm-svn: 31124
2006-10-22 22:47:10 +00:00
6d6fc26257
Implement PR964 and Regression/CodeGen/Generic/SwitchLowering.ll
...
llvm-svn: 31119
2006-10-22 21:36:53 +00:00
9f5a129543
don't break infinite loops
...
llvm-svn: 31102
2006-10-21 06:11:43 +00:00
28f17f45be
Use branch reversal to do stuff like this:
...
call L_strcmp$stub
testl %eax, %eax
- jne LBB26_208 #cond_true6020
- jmp LBB26_227 #bb7119
+ je LBB26_227 #bb7119
LBB26_208: #cond_true6020
movl $l31_str14, 4(%esp)
testl %eax, %eax
- jne LBB26_704 #cond_true13042
- jmp LBB26_713 #bb13151
+ je LBB26_713 #bb13151
LBB26_704: #cond_true13042
movl $_str52, 4(%esp)
cmpl 76(%ecx), %eax
- jge LBB26_1628 #cond_false63.i.i
- jmp LBB26_1769 #_Z8makeGridP13mrSurfaceListidiidd.exit.i
+ jl LBB26_1769 #_Z8makeGridP13mrSurfaceListidiidd.exit.i
LBB26_1628: #cond_false63.i.i
movl $0, 48964(%esp)
llvm-svn: 31100
2006-10-21 05:54:00 +00:00
3ca52185af
Transform code like:
...
jle FOO
jmp BAR
BAR:
into:
jle FOO
BAR:
... whoa!
llvm-svn: 31098
2006-10-21 05:43:30 +00:00
4fe01c42ca
Three changes:
...
1. Remove a bunch of ifdef'd code.
2. When a block just contains an uncond branch, change all blocks branching
to it to jump to the destination instead.
3. If branch analysis tells us some edges in the machinecfg are not actually
possible, remove them.
#2 triggers a suprisingly large number of times.
llvm-svn: 31094
2006-10-21 05:08:28 +00:00
60c9d4dc76
Add an experimental cross-jumping implementation.
...
This is currently disabled by default and limited in several ways, but does
have a positive effect.
llvm-svn: 31090
2006-10-21 00:47:49 +00:00
33f5af09e4
implement MachineOperand::isIdenticalTo
...
llvm-svn: 31088
2006-10-20 22:39:59 +00:00
c5ab6ce613
Make flag and chain edges visually distinguishable from value edges in DOT
...
output.
llvm-svn: 31067
2006-10-20 18:06:09 +00:00
e0fc4dfc22
For PR950:
...
This patch implements the first increment for the Signless Types feature.
All changes pertain to removing the ConstantSInt and ConstantUInt classes
in favor of just using ConstantInt.
llvm-svn: 31063
2006-10-20 07:07:24 +00:00
be96e1cd09
Partially in response to PR926: insert the newly created machine basic
...
blocks into the basic block list when lowering the switch inst. into a
binary tree of if-then statements. This allows the "visitSwitchCase" func
to allow for fall-through behavior.
llvm-svn: 31057
2006-10-19 21:46:38 +00:00
55e4dcad36
Add option for controlling inclusion of global AA.
...
llvm-svn: 31040
2006-10-18 19:08:31 +00:00
a15b0ebb5e
Use global info for alias analysis.
...
llvm-svn: 31035
2006-10-18 12:29:57 +00:00
73da320e50
Teach the branch folder to update debug info if it removes blocks with line
...
# notes in it.
llvm-svn: 31026
2006-10-17 23:17:27 +00:00
34136d0cc1
add a method to remove a line # record.
...
llvm-svn: 31025
2006-10-17 23:16:42 +00:00
145f6b3ec8
Do not leak all of the SourceLineInfo objects. Do not bother mallocing each
...
one separately.
llvm-svn: 31022
2006-10-17 22:06:46 +00:00
78fd0f83ff
Trivial patch to speed up legalizing common i64 constants.
...
llvm-svn: 31020
2006-10-17 21:47:13 +00:00
327b88b102
Fix CodeGen/PowerPC/2006-10-17-brcc-miscompile.ll
...
llvm-svn: 31019
2006-10-17 21:24:15 +00:00
2f4ddce75c
Fix printer for StoreSDNode.
...
llvm-svn: 31017
2006-10-17 21:18:26 +00:00
1839d76f69
Reflect MemOpAddrMode change; added a helper to create pre-indexed load.
...
llvm-svn: 31016
2006-10-17 21:14:32 +00:00
e7d2c24a7d
Make it simplier to dump DAGs while in DAGCombiner. Remove a nasty optimization.
...
llvm-svn: 31009
2006-10-17 19:33:52 +00:00
bca3e297fe
Enable deleting branches to successor blocks. With the previous patches,
...
branch folding can now compile stuff like this:
void foo(int W, int X, int Y, int Z) {
if (W & 1) {
for (; X;--X) bar();
} else if (W & 2) {
for (; Y;--Y) bar();
} else if (W & 4) {
for (; Z;--Z) bar();
} else if (W & 8) {
for (; W;--W) bar();
}
if (W) {
bar();
}
}
contrived testcase where loops exits all end up merging together. To have
the loop merges be:
...
cmplw cr0, r30, r27
bne cr0, LBB1_14 ;bb38
LBB1_16: ;cond_next48.loopexit
mr r27, r29
LBB1_20: ;cond_next48
cmplwi cr0, r27, 0
beq cr0, LBB1_22 ;UnifiedReturnBlock
...
instead of:
...
cmplw cr0, r30, r27
bne cr0, LBB1_14 ;bb38
LBB1_16: ;cond_next48.loopexit
mr r27, r29
b LBB1_20 ;cond_next48
LBB1_17: ;cond_next48.loopexit1
b LBB1_20 ;cond_next48
LBB1_18: ;cond_next48.loopexit2
b LBB1_20 ;cond_next48
LBB1_19: ;cond_next48.loopexit3
LBB1_20: ;cond_next48
cmplwi cr0, r27, 0
beq cr0, LBB1_22 ;UnifiedReturnBlock
...
This is CodeGen/PowerPC/branch-opt.ll
llvm-svn: 31006
2006-10-17 18:16:40 +00:00
d24b913a61
Clean up interface to getGlobalLinkName.
...
llvm-svn: 31001
2006-10-17 17:17:24 +00:00
56c9d2597e
Reenable this pass, fixing the bugs in it.
...
It now correctly deletes unreachable blocks and blocks that are empty.
llvm-svn: 31000
2006-10-17 17:13:52 +00:00
1e3a39cd08
Make sure operand does have size and element type operands.
...
llvm-svn: 30999
2006-10-17 17:06:35 +00:00
7126254a0e
Basic support for getGlobalLinkName.
...
llvm-svn: 30997
2006-10-17 13:41:07 +00:00
f3ae00a64a
Be careful when looking through a vbit_convert. Optimizing this:
...
(vector_shuffle
(vbitconvert (vbuildvector (copyfromreg v4f32), 1, v4f32), 4, f32),
(undef, undef, undef, undef), (0, 0, 0, 0), 4, f32)
to the
vbitconvert
is a very bad idea.
llvm-svn: 30989
2006-10-16 22:49:37 +00:00
dcb2b83886
Pass AliasAnalysis thru to DAGCombiner.
...
llvm-svn: 30984
2006-10-16 20:52:31 +00:00
9db3a08864
Global name regression.
...
llvm-svn: 30982
2006-10-16 19:38:41 +00:00
3bf4f3bd60
Tidy up after truncstore changes.
...
llvm-svn: 30961
2006-10-14 12:14:27 +00:00
47fbeda5ce
Debug tweak.
...
llvm-svn: 30959
2006-10-14 08:34:06 +00:00
6a1b2de8c4
Make sure that the node returned by SimplifySetCC is added to the worklist
...
so that it can be deleted if unused.
llvm-svn: 30955
2006-10-14 03:52:46 +00:00
0626bd2fbc
fold setcc of a setcc.
...
llvm-svn: 30953
2006-10-14 01:02:29 +00:00
bd9acad805
When SimplifySetCC was moved to the DAGCombiner, it was never removed from
...
SelectionDAG and it has since bitrotted. Remove the copy from SelectionDAG.
Next, remove the constant folding piece of DAGCombiner::SimplifySetCC into
a new FoldSetCC method which can be used by getNode() and SimplifySetCC.
This fixes obscure bugs.
llvm-svn: 30952
2006-10-14 00:41:01 +00:00
47db29a405
disable this pass for now, it's causing issues
...
llvm-svn: 30951
2006-10-14 00:30:06 +00:00
3218e0eed5
falling off the end of a function is ok with an unreachable instruction.
...
llvm-svn: 30950
2006-10-14 00:21:48 +00:00
dcf983ce41
Reduce the workload by not adding chain users to work list.
...
llvm-svn: 30948
2006-10-13 23:32:28 +00:00
45ffb1eb70
Fix a bug where we incorrectly turned '(X & 0) == 0' into '(X & 0) >> -1',
...
which is undefined. "0" isn't a power of 2.
llvm-svn: 30947
2006-10-13 22:46:18 +00:00
ab51cf2e78
Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode.
...
llvm-svn: 30945
2006-10-13 21:14:26 +00:00
55ad08a59b
add the branch folding pass as a late cleanup pass for all targets. For now
...
it just deletes empty MBB's. Soon it will do more :)
llvm-svn: 30941
2006-10-13 20:45:56 +00:00
3e8e57c771
disable some objectionable code, maybe we can bring this pass to life
...
llvm-svn: 30939
2006-10-13 20:43:10 +00:00
ccee9baebe
Workaround for templates
...
llvm-svn: 30927
2006-10-13 13:02:19 +00:00
13d3373e72
Clean up dump.
...
llvm-svn: 30926
2006-10-13 13:01:34 +00:00
d0620d2773
Lower X%C into X/C+stuff. This allows the 'division by a constant' logic to
...
apply to rems as well as divs. This fixes PR945 and speeds up ReedSolomon
from 14.57s to 10.90s (which is now faster than gcc).
It compiles CodeGen/X86/rem.ll into:
_test1:
subl $4, %esp
movl %esi, (%esp)
movl $2155905153, %ecx
movl 8(%esp), %esi
movl %esi, %eax
imull %ecx
addl %esi, %edx
movl %edx, %eax
shrl $31, %eax
sarl $7, %edx
addl %eax, %edx
imull $255, %edx, %eax
subl %eax, %esi
movl %esi, %eax
movl (%esp), %esi
addl $4, %esp
ret
_test2:
movl 4(%esp), %eax
movl %eax, %ecx
sarl $31, %ecx
shrl $24, %ecx
addl %eax, %ecx
andl $4294967040, %ecx
subl %ecx, %eax
ret
_test3:
subl $4, %esp
movl %esi, (%esp)
movl $2155905153, %ecx
movl 8(%esp), %esi
movl %esi, %eax
mull %ecx
shrl $7, %edx
imull $255, %edx, %eax
subl %eax, %esi
movl %esi, %eax
movl (%esp), %esi
addl $4, %esp
ret
instead of div/idiv instructions.
llvm-svn: 30920
2006-10-12 20:58:32 +00:00
a731cb674a
Add RemoveDeadNode to remove a dead node and its (potentially) dead operands.
...
llvm-svn: 30916
2006-10-12 20:34:05 +00:00
2e33fb453b
add a minor dag combine noticed when looking at PR945
...
llvm-svn: 30915
2006-10-12 20:23:19 +00:00
c040e53372
restore my previous patch, now that the X86 backend bug has been fixed:
...
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20061009/038518.html
llvm-svn: 30906
2006-10-12 17:45:38 +00:00
df2ccc395e
D'oh - need to use the rigth kind of store.
...
llvm-svn: 30903
2006-10-12 15:22:24 +00:00
c935741b1d
Backing out Chris' last commit. It's breaking llvm-gcc bootstrapping.
...
It's turning:
movl -24(%ebp), %esp
subl $16, %esp
movl -24(%ebp), %ecx
into
movl -24(%ebp), %esp
subl $16, %esp
movl %esp, (%esp)
llvm-svn: 30902
2006-10-12 08:00:47 +00:00
86a012ab61
If we see a load from a stack slot into a physreg, consider it as providing
...
the stack slot. This fixes PR943.
llvm-svn: 30898
2006-10-12 02:34:07 +00:00
a13b9c7aa4
Alias analysis of TRUNCSTORE.
...
llvm-svn: 30889
2006-10-11 18:55:16 +00:00
6a4c6d3a7a
Typo
...
llvm-svn: 30884
2006-10-11 17:52:19 +00:00
0f7c328ae7
Handle aliasing of loadext.
...
llvm-svn: 30883
2006-10-11 17:47:52 +00:00
08edf332ed
Fix regression in combiner alias analysis.
...
llvm-svn: 30880
2006-10-11 13:47:09 +00:00
d35734bd1f
Naming consistency.
...
llvm-svn: 30878
2006-10-11 07:10:22 +00:00
a6bbf33cbf
Jimptables working again on alpha.
...
As a bonus, use the GOT node instead of the AlphaISD::GOT for internal stuff.
llvm-svn: 30873
2006-10-11 04:29:42 +00:00
6df349676e
add two helper methods.
...
llvm-svn: 30869
2006-10-11 03:58:02 +00:00
2da4671e05
FindModifiedNodeSlot needs to add LoadSDNode ivars to create proper SelectionDAGCSEMap ID.
...
llvm-svn: 30866
2006-10-11 01:47:58 +00:00
7994aec7b5
Also update getNodeLabel for LoadSDNode.
...
llvm-svn: 30861
2006-10-10 20:11:26 +00:00
fe858538c0
SDNode::dump should also print out extension type and VT.
...
llvm-svn: 30860
2006-10-10 20:05:10 +00:00
8438429c96
Fix another bug in extload promotion.
...
llvm-svn: 30857
2006-10-10 18:54:19 +00:00
dc6a3aab71
Fix a bug introduced by my LOAD/LOADX changes.
...
llvm-svn: 30853
2006-10-10 07:51:21 +00:00
e71fe34d75
Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes.
...
llvm-svn: 30844
2006-10-09 20:57:25 +00:00
5ab6d8b3fc
Eliminate more token factors by taking advantage of transitivity:
...
if TF depends on A and B, and A depends on B, TF just needs to depend on
A. With Jim's alias-analysis stuff enabled, this compiles the testcase in
PR892 into:
__Z4test3Val:
subl $44, %esp
call L__Z3foov$stub
movl %edx, 28(%esp)
movl %eax, 32(%esp)
movl %eax, 24(%esp)
movl %edx, 36(%esp)
movl 52(%esp), %ecx
movl %ecx, 4(%esp)
movl %eax, 8(%esp)
movl %edx, 12(%esp)
movl 48(%esp), %eax
movl %eax, (%esp)
call L__Z3bar3ValS_$stub
addl $44, %esp
ret
instead of:
__Z4test3Val:
subl $44, %esp
call L__Z3foov$stub
movl %eax, 24(%esp)
movl %edx, 28(%esp)
movl 24(%esp), %eax
movl %eax, 32(%esp)
movl 28(%esp), %eax
movl %eax, 36(%esp)
movl 32(%esp), %eax
movl 36(%esp), %ecx
movl 52(%esp), %edx
movl %edx, 4(%esp)
movl %eax, 8(%esp)
movl %ecx, 12(%esp)
movl 48(%esp), %eax
movl %eax, (%esp)
call L__Z3bar3ValS_$stub
addl $44, %esp
ret
llvm-svn: 30821
2006-10-08 22:57:01 +00:00
0463e08005
Combiner alias analysis passes Multisource (release-asserts.)
...
llvm-svn: 30818
2006-10-07 23:37:56 +00:00
f9f90bc239
Fix a bug legalizing zero-extending i64 loads into 32-bit loads. The bottom
...
part was always forced to be sextload, even when we needed an zextload.
llvm-svn: 30782
2006-10-07 00:58:36 +00:00
a389a612bb
initialize ivar
...
llvm-svn: 30780
2006-10-06 22:52:08 +00:00
9043823cf4
If a target uses a GOT, put it in the jt data section, not the text
...
section. This will fix alpha when Andrew implements
AlphaTargetMachine::getTargetLowering().
llvm-svn: 30779
2006-10-06 22:50:56 +00:00
9d75324ddf
jump tables handle pic
...
llvm-svn: 30776
2006-10-06 22:32:29 +00:00
4e107aa0b6
print labels even if a MBB doesn't have a corresponding LLVM BB, just don't
...
print the LLVM BB label.
llvm-svn: 30775
2006-10-06 21:28:17 +00:00
f5839a0816
Fix a miscompilation of:
...
long long foo(long long X) {
return (long long)(signed char)(int)X;
}
Instead of:
_foo:
extsb r2, r4
srawi r3, r4, 31
mr r4, r2
blr
we now produce:
_foo:
extsb r4, r4
srawi r3, r4, 31
blr
This fixes a miscompilation in ConstantFolding.cpp.
llvm-svn: 30768
2006-10-06 17:34:12 +00:00
16ae43e901
MachineBasicBlock::splice was incorrectly updating parent pointers on
...
instructions.
llvm-svn: 30760
2006-10-06 01:12:44 +00:00
df9ac47e5e
Make use of getStore().
...
llvm-svn: 30759
2006-10-05 23:01:46 +00:00
af309d29b1
Add getStore() helper function to create ISD::STORE nodes.
...
llvm-svn: 30758
2006-10-05 22:57:11 +00:00
8b1a59a272
Don't crash if an MBB doesn't have an LLVM BB
...
llvm-svn: 30757
2006-10-05 21:40:14 +00:00
6549d22ef9
Alias analysis code clean ups.
...
llvm-svn: 30753
2006-10-05 15:07:25 +00:00
66c1625a37
Emit pic jumptables to the same section that the function is emitted to,
...
allowing label differences to work. This fixes CodeGen/X86/pic_jumptable.ll
llvm-svn: 30744
2006-10-05 03:13:28 +00:00
a6a570e02f
Pass the MachineFunction into EmitJumpTableInfo.
...
llvm-svn: 30742
2006-10-05 03:01:21 +00:00
dc82241182
move getSectionForFunction to AsmPrinter
...
llvm-svn: 30736
2006-10-05 02:42:47 +00:00
f80dfa83a0
Fix some typos that can cause a flag value to have more than one use.
...
llvm-svn: 30727
2006-10-04 22:23:53 +00:00
708d0db2d8
More extensive alias analysis.
...
llvm-svn: 30721
2006-10-04 16:53:27 +00:00
0d5a0eae57
More long term solution
...
llvm-svn: 30720
2006-10-04 10:40:15 +00:00
66b0b55816
Work around for some problems with templates.
...
llvm-svn: 30715
2006-10-04 01:43:13 +00:00
5d9fd977d3
Combine ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD into ISD::LOADX. Add an
...
extra operand to LOADX to specify the exact value extension type.
llvm-svn: 30714
2006-10-04 00:56:09 +00:00
fc416faaa0
Use $( $| $) to represent alternatives in asm blocks instead of {|}. This
...
is needed to support targets where {|} aren't special symbols.
llvm-svn: 30712
2006-10-03 23:27:09 +00:00
91d76cb27f
Fix an obvious typo.
...
llvm-svn: 30711
2006-10-03 23:08:27 +00:00
bd7286e606
Bugfixes
...
llvm-svn: 30709
2006-10-03 20:19:23 +00:00
de154b1737
Print the MBB ID # along with the bb tag in the -print-machine-instrs output.
...
llvm-svn: 30708
2006-10-03 20:17:24 +00:00
64fd9487bd
Provide a function that ensures MBB numbering is dense and inorder. This
...
can be used by MachineFunctionPasses who need this property.
llvm-svn: 30706
2006-10-03 19:18:57 +00:00
984f0ce06b
Fix for PR929. The PHI nodes were being gone through for each instruction
...
in a successor block for every block...resulting in some O(N^k) algorithm
which wasn't very good for performance. Calculating this information up
front and keeping it in a map made it much faster.
llvm-svn: 30697
2006-10-03 07:20:20 +00:00
e73a22514d
Debugging kruft
...
llvm-svn: 30688
2006-10-02 13:01:17 +00:00
1368c265da
Add ability to annotate (color) nodes in a viewGraph.
...
llvm-svn: 30686
2006-10-02 12:26:53 +00:00
eea983eb5d
simplify code
...
llvm-svn: 30659
2006-09-28 23:17:41 +00:00
bcf1b4120f
TargetRegisterClass specifies the desired spill alignment. However, it cannot be honored if stack alignment is smaller.
...
llvm-svn: 30648
2006-09-28 18:52:32 +00:00
5d409822d6
"Once more into the breach, dear friends, once more, or fill the wall up
...
with our English dead."
No! Really! Serious this time...It was how the vreg uses were being
adjusted that was causing hte Olden tests to fail. I corrected this and
the Olden and Regression tests all passed.
llvm-svn: 30644
2006-09-28 07:10:24 +00:00
a9caf95591
refactor critical edge breaking out into the SplitCritEdgesForPHIConstants method.
...
This is a baby step towards fixing PR925.
llvm-svn: 30643
2006-09-28 06:17:10 +00:00
764caf6129
re-re-revert this, back to the right revision. It currently breaks bisort/mst
...
in olden among others.
llvm-svn: 30637
2006-09-28 00:11:54 +00:00
d31f55c236
PEI now place callee save spills closest to the address pointed to by the
...
incoming stack. This allows X86 backend to use push / pop in epilogue /
prologue.
llvm-svn: 30636
2006-09-28 00:10:27 +00:00
9f7d0d1dc5
re-revert this patch, bisort and mst are still broken in Olden.
...
llvm-svn: 30634
2006-09-28 00:04:21 +00:00
1f29e6c5c5
Reapplying this patch. With the newest commits, the error in Olden/bisort
...
has disappeared.
llvm-svn: 30633
2006-09-27 22:37:35 +00:00
5f6c93701b
Temporarily revert this. This breaks Olden/bisort on PPC
...
llvm-svn: 30628
2006-09-27 16:59:16 +00:00
0a7f617a6c
PR878: Instead of calculating the vreg to PHI use count everytime we get
...
a function, do it up front in linear time (going through all of the
instructions once). We create a map out of them. Then it's no problem to
use the information in it during elimination...
llvm-svn: 30624
2006-09-27 09:04:15 +00:00
30b4708df2
Add support for ${:private} which prints "L" on darwin.
...
llvm-svn: 30620
2006-09-27 00:06:07 +00:00
a32814b033
Add support for ${:comment}, which expands to the current target's comment
...
character, and ${:uid} which expands to a unique ID for the MachineInstr.
More can be added if/when they are needed.
llvm-svn: 30619
2006-09-26 23:59:50 +00:00
5405c06737
Rename function. It's determining which callee-save registers to save.
...
llvm-svn: 30616
2006-09-26 22:29:31 +00:00
c19ef92403
Comments on JumpTableness
...
llvm-svn: 30615
2006-09-26 20:02:30 +00:00
60832693a7
Load chain check is not needed
...
llvm-svn: 30613
2006-09-26 17:44:58 +00:00
dde51671e5
Chain can be any operand
...
llvm-svn: 30611
2006-09-26 09:32:41 +00:00
5f3e0af9d0
Wrong size for load
...
llvm-svn: 30610
2006-09-26 08:14:06 +00:00
b4a864d533
Can't move a load node if it's chain is not used.
...
llvm-svn: 30609
2006-09-26 07:37:42 +00:00
9a1e91b107
print the preds of each MBB
...
llvm-svn: 30606
2006-09-26 03:41:59 +00:00
66af390631
Add support for targets that want to do something with the llvm.used list,
...
because they have an aggressive linker that does dead code stripping.
llvm-svn: 30604
2006-09-26 03:38:18 +00:00
7aa0638aa9
Accidental enable of bad code
...
llvm-svn: 30601
2006-09-25 21:11:32 +00:00
b5534e5c28
Fix chain dropping in load and drop unused stores in ret blocks.
...
llvm-svn: 30600
2006-09-25 19:32:58 +00:00
d07be232ba
Core antialiasing for load and store.
...
llvm-svn: 30597
2006-09-25 16:29:54 +00:00
783a4a9d86
Add support for other relocation bases to jump tables, as well as custom asm directives
...
llvm-svn: 30593
2006-09-24 19:45:58 +00:00
77c0757f8b
PIC jump table entries are always 32-bit. This fixes PIC jump table support on X86-64.
...
llvm-svn: 30590
2006-09-24 05:22:38 +00:00
449a0c7e33
Make it work for DAG combine of multi-value nodes.
...
llvm-svn: 30573
2006-09-21 19:04:05 +00:00
35f7eebb49
core corrections
...
llvm-svn: 30570
2006-09-21 17:35:47 +00:00
5d19d59017
Basic "in frame" alias analysis.
...
llvm-svn: 30568
2006-09-21 16:28:59 +00:00
082db3f9aa
fold (aext (and (trunc x), cst)) -> (and x, cst).
...
llvm-svn: 30561
2006-09-21 06:40:43 +00:00
fa9f92cf65
Check the right value type. This fixes 186.crafty on x86
...
llvm-svn: 30560
2006-09-21 06:17:39 +00:00
8d8a3bf9c9
Compile:
...
int %test(ulong *%tmp) {
%tmp = load ulong* %tmp ; <ulong> [#uses=1]
%tmp.mask = shr ulong %tmp, ubyte 50 ; <ulong> [#uses=1]
%tmp.mask = cast ulong %tmp.mask to ubyte
%tmp2 = and ubyte %tmp.mask, 3 ; <ubyte> [#uses=1]
%tmp2 = cast ubyte %tmp2 to int ; <int> [#uses=1]
ret int %tmp2
}
to:
_test:
movl 4(%esp), %eax
movl 4(%eax), %eax
shrl $18, %eax
andl $3, %eax
ret
instead of:
_test:
movl 4(%esp), %eax
movl 4(%eax), %eax
shrl $18, %eax
# TRUNCATE movb %al, %al
andb $3, %al
movzbl %al, %eax
ret
llvm-svn: 30558
2006-09-21 06:14:31 +00:00
a31f0a622b
Generalize (zext (truncate x)) and (sext (truncate x)) folding to work when
...
the src/dst are not the same size. This catches things like "truncate
32-bit X to 8 bits, then zext to 16", which happens a bit on X86.
llvm-svn: 30557
2006-09-21 06:00:20 +00:00
c8cd62d381
Compile:
...
int test3(int a, int b) { return (a < 0) ? a : 0; }
to:
_test3:
srawi r2, r3, 31
and r3, r2, r3
blr
instead of:
_test3:
cmpwi cr0, r3, 1
li r2, 0
blt cr0, LBB2_2 ;entry
LBB2_1: ;entry
mr r3, r2
LBB2_2: ;entry
blr
This implements: PowerPC/select_lt0.ll:seli32_a_a
llvm-svn: 30517
2006-09-20 06:41:35 +00:00
8746e2cd57
Fold the full generality of (any_extend (truncate x))
...
llvm-svn: 30514
2006-09-20 06:29:17 +00:00
8b68decb27
Two things:
...
1. teach SimplifySetCC that '(srl (ctlz x), 5) == 0' is really x != 0.
2. Teach visitSELECT_CC to use SimplifySetCC instead of calling it and
ignoring the result. This allows us to compile:
bool %test(ulong %x) {
%tmp = setlt ulong %x, 4294967296
ret bool %tmp
}
to:
_test:
cntlzw r2, r3
cmplwi cr0, r3, 1
srwi r2, r2, 5
li r3, 0
beq cr0, LBB1_2 ;
LBB1_1: ;
mr r3, r2
LBB1_2: ;
blr
instead of:
_test:
addi r2, r3, -1
cntlzw r2, r2
cntlzw r3, r3
srwi r2, r2, 5
cmplwi cr0, r2, 0
srwi r2, r3, 5
li r3, 0
bne cr0, LBB1_2 ;
LBB1_1: ;
mr r3, r2
LBB1_2: ;
blr
This isn't wonderful, but it's an improvement.
llvm-svn: 30513
2006-09-20 06:19:26 +00:00
875ea0cdbd
Expand 64-bit shifts more optimally if we know that the high bit of the
...
shift amount is one or zero. For example, for:
long long foo1(long long X, int C) {
return X << (C|32);
}
long long foo2(long long X, int C) {
return X << (C&~32);
}
we get:
_foo1:
movb $31, %cl
movl 4(%esp), %edx
andb 12(%esp), %cl
shll %cl, %edx
xorl %eax, %eax
ret
_foo2:
movb $223, %cl
movl 4(%esp), %eax
movl 8(%esp), %edx
andb 12(%esp), %cl
shldl %cl, %eax, %edx
shll %cl, %eax
ret
instead of:
_foo1:
subl $4, %esp
movl %ebx, (%esp)
movb $32, %bl
movl 8(%esp), %eax
movl 12(%esp), %edx
movb %bl, %cl
orb 16(%esp), %cl
shldl %cl, %eax, %edx
shll %cl, %eax
xorl %ecx, %ecx
testb %bl, %bl
cmovne %eax, %edx
cmovne %ecx, %eax
movl (%esp), %ebx
addl $4, %esp
ret
_foo2:
subl $4, %esp
movl %ebx, (%esp)
movb $223, %cl
movl 8(%esp), %eax
movl 12(%esp), %edx
andb 16(%esp), %cl
shldl %cl, %eax, %edx
shll %cl, %eax
xorl %ecx, %ecx
xorb %bl, %bl
testb %bl, %bl
cmovne %eax, %edx
cmovne %ecx, %eax
movl (%esp), %ebx
addl $4, %esp
ret
llvm-svn: 30506
2006-09-20 03:38:48 +00:00
698000b0da
Fix UnitTests/2005-05-12-Int64ToFP.c with llc-beta. In particular, do not
...
allow it to go into an infinite loop, filling up the disk!
llvm-svn: 30494
2006-09-19 18:02:01 +00:00
5a42ebcff3
Fold extract_element(cst) to cst
...
llvm-svn: 30478
2006-09-19 05:02:39 +00:00
4c059f4962
Minor speedup for legalize by avoiding some malloc traffic
...
llvm-svn: 30477
2006-09-19 04:51:23 +00:00
1fc7c363e6
Fix a typo.
...
llvm-svn: 30474
2006-09-18 23:28:33 +00:00
4bfaf0bd2c
Allow i32 UDIV, SDIV, UREM, SREM to be expanded into libcalls.
...
llvm-svn: 30470
2006-09-18 21:49:04 +00:00
51ad73c98c
oops
...
llvm-svn: 30462
2006-09-18 18:00:18 +00:00
c50458fb90
absolute addresses must match pointer size
...
llvm-svn: 30461
2006-09-18 17:59:35 +00:00
d30bba331f
Sort out mangled names for globals
...
llvm-svn: 30460
2006-09-18 14:47:26 +00:00
e50f5d1fb1
Oh yeah, this is needed too
...
llvm-svn: 30407
2006-09-16 05:08:34 +00:00
1b63391fdf
simplify control flow, no functionality change
...
llvm-svn: 30403
2006-09-16 00:21:44 +00:00
fbadbda6ba
Allow custom expand of mul
...
llvm-svn: 30402
2006-09-16 00:09:24 +00:00
8fb3d445f5
Keep track of the start of MBB's in a separate map from instructions. This
...
is faster and is needed for future improvements.
llvm-svn: 30383
2006-09-15 03:57:23 +00:00
46d710e6ea
Fold (X & C1) | (Y & C2) -> (X|Y) & C3 when possible.
...
This implements CodeGen/X86/and-or-fold.ll
llvm-svn: 30379
2006-09-14 21:11:37 +00:00
97614c86ce
Split rotate matching code out to its own function. Make it stronger, by
...
matching things like ((x >> c1) & c2) | ((x << c3) & c4) to (rot x, c5) & c6
llvm-svn: 30376
2006-09-14 20:50:57 +00:00
616aa548b2
Use getOffset() instead.
...
llvm-svn: 30327
2006-09-14 07:41:12 +00:00
2ad050fb3e
Use MachineConstantPoolEntry getOffset() and getType() accessors.
...
llvm-svn: 30326
2006-09-14 07:35:00 +00:00
4f9299552b
A MachineConstantPool may have mixed Constant* and MachineConstantPoolValue* values.
...
llvm-svn: 30316
2006-09-14 05:50:57 +00:00
84cc1f7cb8
If LSR went through a lot of trouble to put constants (e.g. the addr of a global
...
in a specific BB, don't undo this!). This allows us to compile
CodeGen/X86/loop-hoist.ll into:
_foo:
xorl %eax, %eax
*** movl L_Arr$non_lazy_ptr, %ecx
movl 4(%esp), %edx
LBB1_1: #cond_true
movl %eax, (%ecx,%eax,4)
incl %eax
cmpl %edx, %eax
jne LBB1_1 #cond_true
LBB1_2: #return
ret
instead of:
_foo:
xorl %eax, %eax
movl 4(%esp), %ecx
LBB1_1: #cond_true
*** movl L_Arr$non_lazy_ptr, %edx
movl %eax, (%edx,%eax,4)
incl %eax
cmpl %ecx, %eax
jne LBB1_1 #cond_true
LBB1_2: #return
ret
This was noticed in 464.h264ref. This doesn't usually affect PPC,
but strikes X86 all the time.
llvm-svn: 30290
2006-09-13 06:02:42 +00:00
72b503bcad
Compile X << 1 (where X is a long-long) to:
...
addl %ecx, %ecx
adcl %eax, %eax
instead of:
movl %ecx, %edx
addl %edx, %edx
shrl $31, %ecx
addl %eax, %eax
orl %ecx, %eax
and to:
addc r5, r5, r5
adde r4, r4, r4
instead of:
slwi r2,r9,1
srwi r0,r11,31
slwi r3,r11,1
or r2,r0,r2
on PPC.
llvm-svn: 30284
2006-09-13 03:50:39 +00:00
45fe3bc72c
Added support for machine specific constantpool values. These are useful for
...
representing expressions that can only be resolved at link time, etc.
llvm-svn: 30278
2006-09-12 21:00:35 +00:00
a0d95a8da9
Behold, more work on relocations. Things are looking pretty good now.
...
llvm-svn: 30240
2006-09-10 23:03:44 +00:00
2e0dfb0b16
This code was trying too hard. By eliminating redundant edges in the CFG
...
due to switch cases going to the same place, it make #pred != #phi entries,
breaking live interval analysis.
This fixes 458.sjeng on x86 with llc.
llvm-svn: 30236
2006-09-10 06:36:57 +00:00
f0359b343a
Implement the fpowi now by lowering to a libcall
...
llvm-svn: 30225
2006-09-09 06:03:30 +00:00
e4bbb6c341
Allow targets to custom lower expanded BIT_CONVERT's
...
llvm-svn: 30217
2006-09-09 00:20:27 +00:00
69df6132d7
First pass at supporting relocations. Relocations are written correctly to
...
the file now, however the relocated address is currently wrong. Fixing
that will require some deep pondering.
llvm-svn: 30207
2006-09-08 22:42:09 +00:00
b2e7316b2d
Non-allocatable physregs can be killed and dead, but don't treat them as
...
safe for later allocation. This fixes McCat/18-imp with llc-beta.
llvm-svn: 30204
2006-09-08 20:21:31 +00:00
050c64c51d
This fixes Benchmarks/Prolangs-C/unix-smail
...
llvm-svn: 30198
2006-09-08 19:11:11 +00:00
9b1a6ebf20
Fix a bunch of llc-beta failures on x86 yesterday. Don't allow selection
...
of unallocatable registers, just because an alias is allocatable. We were
picking registers like SIL just because ESI was being used.
llvm-svn: 30197
2006-09-08 19:03:30 +00:00
261779bb45
Make target asm info a property of the target machine.
...
llvm-svn: 30162
2006-09-07 22:06:40 +00:00
95b3dde8bb
Fix pasto that was breaking x86 tests.
...
llvm-svn: 30151
2006-09-07 18:50:20 +00:00
707339a57b
Fix CodeGen/Generic/2006-09-06-SwitchLowering.ll, a bug where SDIsel inserted
...
too many phi operands when lowering a switch to branches in some cases.
llvm-svn: 30142
2006-09-07 01:59:34 +00:00
a6211dcdad
Separate target specific asm properties from the asm printers.
...
llvm-svn: 30126
2006-09-06 18:34:40 +00:00
ddfb10b5af
Only call isUse/isDef on register operands
...
llvm-svn: 30122
2006-09-05 20:32:06 +00:00
2cb238320d
Only call isUse/isDef on register operands
...
llvm-svn: 30118
2006-09-05 20:19:27 +00:00
45456d44e3
Don't call isDef on non-registers
...
llvm-svn: 30117
2006-09-05 20:02:51 +00:00
0dce3311c4
Change the default to 0, which means 'default'.
...
llvm-svn: 30114
2006-09-05 17:39:15 +00:00
af23f9b5f6
Completely eliminate def&use operands. Now a register operand is EITHER a
...
def operand or a use operand.
llvm-svn: 30109
2006-09-05 02:31:13 +00:00
13a5dcddce
Fix a long-standing wart in the code generator: two-address instruction lowering
...
actually *removes* one of the operands, instead of just assigning both operands
the same register. This make reasoning about instructions unnecessarily complex,
because you need to know if you are before or after register allocation to match
up operand #'s with the target description file.
Changing this also gets rid of a bunch of hacky code in various places.
This patch also includes changes to fold loads into cmp/test instructions in
the X86 backend, along with a significant simplification to the X86 spill
folding code.
llvm-svn: 30108
2006-09-05 02:12:02 +00:00
1eed04d1fb
Correct fix for a crasher on functions with live in values
...
llvm-svn: 30099
2006-09-04 18:27:40 +00:00
bff0b5969f
Hack around a regression I introduced yesterday
...
llvm-svn: 30098
2006-09-04 18:20:15 +00:00
373be1d1a2
forgot this
...
llvm-svn: 30097
2006-09-04 07:44:11 +00:00
cf6749e4c0
add setJumpBufSize() and setJumpBufAlignment() to target-lowering.
...
Call these from your backend to enjoy setjmp/longjmp goodness, see
lib/Target/IA64/IA64ISelLowering.cpp for an example
llvm-svn: 30095
2006-09-04 06:21:35 +00:00
a916db12e4
new file
...
llvm-svn: 30082
2006-09-04 04:16:09 +00:00
8584e940b8
Avoid beating on the mi2i map when we know the answer already.
...
llvm-svn: 30066
2006-09-03 08:07:11 +00:00
774785a79d
minor speedup
...
llvm-svn: 30065
2006-09-03 07:53:50 +00:00
7cc20d418b
Fix Regression/CodeGen/Generic/2006-09-02-LocalAllocCrash.ll on X86.
...
Just because an alias of a register is available, it doesn't mean that we
can arbitrarily evict the register.
llvm-svn: 30064
2006-09-03 07:15:37 +00:00
bd79458b0e
When deleting a machine instruction, make sure to remove it from the
...
livevariables information. This fixes several regalloc=local failures on x86
llvm-svn: 30062
2006-09-03 00:06:08 +00:00
f8f724a2b1
Move two methods out of line, make them work when the record for a machine
...
instruction includes physregs.
llvm-svn: 30061
2006-09-03 00:05:09 +00:00
f2ce949ae9
improve compat with certain versions of GCC (on cygwin?)
...
llvm-svn: 30054
2006-09-02 17:37:30 +00:00
75742e532a
Iteration is required for some cases, even if they don't occur in crafty.
...
Restore it, which re-fixes X86/2006-08-21-ExtraMovInst.ll
llvm-svn: 30050
2006-09-02 05:32:53 +00:00
5a56d30906
When joining two intervals where the RHS is really simple, use a light-weight
...
method for joining the live ranges instead of the fully-general one.
llvm-svn: 30049
2006-09-02 05:26:59 +00:00
e93762d36e
Allow legalizer to expand ISD::MUL using only MULHS in the rare case that is
...
possible and the target only supports MULHS.
llvm-svn: 30022
2006-09-01 18:17:58 +00:00
5352d0cc4d
Corrections.
...
llvm-svn: 30021
2006-09-01 12:55:05 +00:00
93c067dc2d
Pull some code out of a hot recursive function because the common case doesn't
...
need recursion.
llvm-svn: 30015
2006-09-01 07:00:23 +00:00
3eac2c87aa
Reserve space in the ValueNumberInfo vector. This speeds up live interval
...
analysis 16% on crafty.
Wrap long lines.
llvm-svn: 30012
2006-09-01 06:10:18 +00:00
f765351978
Iterative coallescing doesn't buy us anything (we get identical results on
...
crafty with and without it). Removing it speeds up live intervals 6%.
llvm-svn: 30010
2006-09-01 04:02:42 +00:00
31305c45da
DAG combiner fix for rotates. Previously the outer-most condition checks
...
for ROTL availability. This prevents it from forming ROTR for targets that
has ROTR only.
llvm-svn: 29997
2006-08-31 07:41:12 +00:00
a700a19d04
Add a special case that speeds up coallescing a bit, but not enough.
...
llvm-svn: 29996
2006-08-31 06:48:26 +00:00
78cca7243c
Delete copies as they are coallesced instead of waiting until the end.
...
llvm-svn: 29995
2006-08-31 05:58:59 +00:00
aa36808fd3
avoid calling the virtual isMoveInstr method endlessly by caching its results.
...
llvm-svn: 29994
2006-08-31 05:54:43 +00:00
cb74860cce
Fix a compiler crash bootstrapping llvm-gcc.
...
llvm-svn: 29989
2006-08-30 23:02:29 +00:00
34434e97c9
Teach the coallescer to coallesce live intervals joined by an arbitrary
...
number of copies, potentially defining live ranges that appear to have
differing value numbers that become identical when coallsced. Among other
things, this fixes CodeGen/X86/shift-coalesce.ll and PR687.
llvm-svn: 29968
2006-08-29 23:18:15 +00:00
2eebe8b05e
Handle callee saved registers in dwarf frame info (lead up to exception
...
handling.)
llvm-svn: 29954
2006-08-29 16:24:26 +00:00
e5570a4c3f
Move isCommutativeBinOp from SelectionDAG.cpp and DAGCombiner.cpp out. Make it a static method of SelectionDAG.
...
llvm-svn: 29951
2006-08-29 06:42:35 +00:00
c2d3d3112e
eliminate RegisterOpt. It does the same thing as RegisterPass.
...
llvm-svn: 29925
2006-08-27 22:42:52 +00:00
3c9b2420df
Eliminate RegisterAnalysis. RegisterPass now does all that is necessary.
...
llvm-svn: 29921
2006-08-27 22:30:17 +00:00
3d27be1333
s|llvm/Support/Visibility.h|llvm/Support/Compiler.h|
...
llvm-svn: 29911
2006-08-27 12:54:02 +00:00
2c3683a901
typo fix
...
llvm-svn: 29910
2006-08-27 12:47:48 +00:00
849f4bf8dd
Eliminate SelectNodeTo() and getTargetNode() variants which take more than
...
3 SDOperand operands. They are replaced by versions which take an array
of SDOperand and the number of operands.
llvm-svn: 29905
2006-08-27 08:08:54 +00:00
7851db75d9
Properly size the string table, and emit symbol table and string table
...
entries in the correct order, fixing several fixmes.
llvm-svn: 29902
2006-08-26 15:46:34 +00:00
34b70eea5c
SelectNodeTo now returns a SDNode*.
...
llvm-svn: 29901
2006-08-26 08:00:10 +00:00
122f2bcdc2
Simplifications to liveinterval analysis, no functionality change.
...
llvm-svn: 29896
2006-08-26 01:28:16 +00:00
f4f0b1995c
Completely change the way that joining with physregs is implemented. This
...
paves the way for future changes, increases coallescing opportunities (in
theory, not witnessed in practice), and eliminates the really expensive
LiveIntervals::overlapsAliases method.
llvm-svn: 29890
2006-08-25 23:41:24 +00:00
fb96c74874
Tidy up.
...
llvm-svn: 29888
2006-08-25 22:56:30 +00:00
92206f9404
Consolidate callee saved register information so that it can me used by debug
...
information and exception handling.
llvm-svn: 29881
2006-08-25 19:45:51 +00:00
f8bf1e6034
Allow for register numbers > 31.
...
llvm-svn: 29879
2006-08-25 19:39:52 +00:00
89fa9c7d65
Get closer to handling globals correctly. We now generally get them in the
...
right section.
llvm-svn: 29871
2006-08-25 06:36:58 +00:00
24d4208c97
When replacing value numbers, make sure to compactify the value # space.
...
llvm-svn: 29865
2006-08-24 23:22:59 +00:00
bdf121060c
Take advantage of the recent improvements to the liveintervals set (tracking
...
instructions which define each value#) to simplify and improve the coallescer.
In particular, this patch:
1. Implements iterative coallescing.
2. Reverts an unsafe hack from handlePhysRegDef, superceeding it with a
better solution.
3. Implements PR865, "coallescing" away the second copy in code like:
A = B
...
B = A
This also includes changes to symbolically print registers in intervals
when possible.
llvm-svn: 29862
2006-08-24 22:43:55 +00:00
3cb3921a60
Initial checkin of the Mach-O emitter. There's plenty of fixmes, but it
...
does emit linkable .o files in very simple cases.
llvm-svn: 29850
2006-08-23 21:08:52 +00:00
2e9f1bc056
Improve the LiveInterval class to keep track of which machine instruction
...
defines each value# tracked by the interval. This will be used to improve
coallescing.
llvm-svn: 29830
2006-08-22 18:19:46 +00:00
1d77a0ff88
Print physreg names symbolically in dumps
...
llvm-svn: 29805
2006-08-21 23:03:54 +00:00
213159a6ee
Print debug info as:
...
*** Register mapping ***
reg 1024 -> %reg1028
reg 1026 -> EAX
reg 1027 -> %reg1028
instead of:
*** Register mapping ***
reg 1024 -> reg 1028
reg 1026 -> reg 15
reg 1027 -> reg 1028
llvm-svn: 29803
2006-08-21 22:56:29 +00:00
b6ac11e120
Adding C++ member support.
...
llvm-svn: 29799
2006-08-21 21:20:18 +00:00
451b099113
Fix PR861
...
llvm-svn: 29796
2006-08-21 20:24:53 +00:00
04f2246400
Added a check so that if we have two machine instructions in this form
...
MOV R0, R1
MOV R1, R0
the second machine instruction is removed. Added a regression test.
llvm-svn: 29792
2006-08-21 07:33:33 +00:00
d86418ab20
switch the SUnit pred/succ sets from being std::sets to being smallvectors.
...
This reduces selectiondag time on kc++ from 5.43s to 4.98s (9%). More
significantly, this speeds up the default ppc scheduler from ~1571ms to 1063ms,
a 33% speedup.
llvm-svn: 29743
2006-08-17 00:09:56 +00:00
65879caf07
minor changes.
...
llvm-svn: 29740
2006-08-16 22:57:46 +00:00
a4f3625c23
Use the appropriate typedef
...
llvm-svn: 29730
2006-08-16 20:59:32 +00:00
a5a3eafbd0
Start using SDVTList more consistently
...
llvm-svn: 29711
2006-08-15 19:11:05 +00:00
f98411a220
add a new SDVTList type and new SelectionDAG::getVTList methods to streamline
...
the creation of canonical VTLists.
llvm-svn: 29709
2006-08-15 17:46:01 +00:00
bd8877744b
eliminate use of getNode that takes vector of valuetypes.
...
llvm-svn: 29687
2006-08-14 23:53:35 +00:00
3bf4be453f
Add a new getNode() method that takes a pointer to an already-intern'd list
...
of value-type nodes. This avoids having to do mallocs for std::vectors of
valuetypes when a node returns more than one type.
llvm-svn: 29685
2006-08-14 23:31:51 +00:00
e93a39f2d7
remove SelectionDAG::InsertISelMapEntry, it is dead
...
llvm-svn: 29677
2006-08-14 22:24:39 +00:00
63268f0672
Add code to resize the CSEMap hash table. This doesn't speedup codegen of
...
kimwitu, but seems like a good idea from a "avoid performance cliffs" standpoint :)
llvm-svn: 29675
2006-08-14 22:19:25 +00:00
8e37283d8b
Add the actual constant to the hash for ConstantPool nodes. Thanks to
...
Rafael Espindola for pointing this out.
llvm-svn: 29669
2006-08-14 20:12:44 +00:00
984c1a4a8f
Emit .set directives for jump table entries when possible, which reduces
...
the number of relocations in object files, shrinkifying them.
llvm-svn: 29650
2006-08-12 21:29:52 +00:00
167ea3eb5f
Fix an obvious bug, noticed by inspection. No current targets trigger this.
...
llvm-svn: 29648
2006-08-12 05:41:39 +00:00
0a60294fa0
Switch to using SuperFastHash instead of adding all elements together. This
...
doesn't significantly improve performance but it helps a small amount.
llvm-svn: 29642
2006-08-12 01:07:10 +00:00
04aa034f38
Switch NodeID to track 32-bit chunks instead of 8-bit chunks, for a 2.5%
...
speedup in isel time.
llvm-svn: 29640
2006-08-11 23:55:53 +00:00
0c2e5412bb
Remove 8 more std::map's.
...
llvm-svn: 29631
2006-08-11 21:55:30 +00:00
3f16b201e2
Move the BBNodes, GlobalValues, TargetGlobalValues, Constants, TargetConstants,
...
RegNodes, and ValueNodes maps into the CSEMap.
llvm-svn: 29626
2006-08-11 21:01:22 +00:00
fcb16470ec
eliminate the NullaryOps map, use CSEMap instead.
...
llvm-svn: 29621
2006-08-11 18:38:11 +00:00
6f22ebd8be
change internal impl of dag combiner so that calls to CombineTo never have to
...
make a temporary vector.
llvm-svn: 29618
2006-08-11 17:56:38 +00:00
a2f4086828
Change one ReplaceAllUsesWith method to take an array of operands to replace
...
instead of a vector of operands.
llvm-svn: 29616
2006-08-11 17:46:28 +00:00
c24a1d3093
Start eliminating temporary vectors used to create DAG nodes. Instead, pass
...
in the start of an array and a count of operands where applicable. In many
cases, the number of operands is known, so this static array can be allocated
on the stack, avoiding the heap. In many other cases, a SmallVector can be
used, which has the same benefit in the common cases.
I updated a lot of code calling getNode that takes a vector, but ran out of
time. The rest of the code should be updated, and these methods should be
removed.
We should also do the same thing to eliminate the methods that take a
vector of MVT::ValueTypes.
It would be extra nice to convert the dagiselemitter to avoid creating vectors
for operands when calling getTargetNode.
llvm-svn: 29566
2006-08-08 02:23:42 +00:00
97af9d5d3a
Eliminate some malloc traffic by allocating vectors on the stack. Change some
...
method that took std::vector<SDOperand> to take a pointer to a first operand
and #operands.
This speeds up isel on kc++ by about 3%.
llvm-svn: 29561
2006-08-08 01:09:31 +00:00
1ee75ce65d
Revamp the "CSEMap" datastructure used in the SelectionDAG class. This
...
eliminates a bunch of std::map's in the SelectionDAG, replacing them with a
home-grown hashtable.
This is still a work in progress: not all the maps have been moved over and the
hashtable never resizes. That said, this still speeds up llc 20% on kimwitu++
with -fast -regalloc=local using a release build.
llvm-svn: 29550
2006-08-07 23:03:03 +00:00
445b91a041
Clear TopOrder before assigning topological order. Some clean ups.
...
llvm-svn: 29546
2006-08-07 22:13:29 +00:00
1640ae5a84
Reverse the FlaggedNodes after scanning up for flagged preds or else the order would be reversed.
...
llvm-svn: 29545
2006-08-07 22:12:12 +00:00
8927c875bb
Make SelectionDAG::RemoveDeadNodes iterative instead of recursive, which
...
also make it simpler.
llvm-svn: 29524
2006-08-04 17:45:20 +00:00
a5b707e3ad
Copy the liveins for the first block. PR859
...
llvm-svn: 29511
2006-08-03 20:51:06 +00:00
524c1a21f2
Work around a GCC 3.3.5 bug noticed by a user.
...
llvm-svn: 29490
2006-08-03 00:18:59 +00:00
6efe304ec8
Work around a bug in gcc 3.3.5, reported by a user
...
llvm-svn: 29489
2006-08-03 00:16:56 +00:00
bba1ebda32
- Change AssignTopologicalOrder to return vector of SDNode* by reference.
...
- Tweak implementation to avoid using std::map.
llvm-svn: 29479
2006-08-02 22:00:34 +00:00
29e635d3c9
Final polish on machine pass registries.
...
llvm-svn: 29471
2006-08-02 12:30:23 +00:00
17c67efe8a
Now that the ISel is available, it's possible to create a default instruction
...
scheduler creator.
llvm-svn: 29452
2006-08-01 19:14:14 +00:00
03593f72db
1. Change use of "Cache" to "Default".
...
2. Added argument to instruction scheduler creators so the creators can do
special things.
3. Repaired target hazard code.
4. Misc.
More to follow.
llvm-svn: 29450
2006-08-01 18:29:48 +00:00
0ec39ee28e
Forgot the added files for plugable machine passes.
...
llvm-svn: 29436
2006-08-01 16:31:08 +00:00
95eda5b1f3
Introducing plugable register allocators and instruction schedulers.
...
llvm-svn: 29434
2006-08-01 14:21:23 +00:00
9631a60020
Added AssignTopologicalOrder() to assign each node an unique id based on their topological order.
...
llvm-svn: 29431
2006-08-01 08:20:41 +00:00
6ae6ac1216
PIC jump table entries are always 32-bit even in 64-bit mode.
...
llvm-svn: 29422
2006-08-01 01:03:13 +00:00
85492427f2
Instead of blindly looking past constantexpr casts, actually constant
...
fold them. This correctly truncates constants that are too large for the
destination slot and makes the code easier to understand. This fixes PR853
and Regression/CodeGen/X86/2006-07-28-AsmPrint-Long-As-Pointer.ll
llvm-svn: 29408
2006-07-29 01:57:19 +00:00
b572401bea
Remove InFlightSet hack. No longer needed.
...
llvm-svn: 29373
2006-07-28 00:47:19 +00:00
3390cbed2c
Print empty inline asms as a blank line instead of:
...
# InlineAsm Start
# InlineAsm End
llvm-svn: 29372
2006-07-28 00:17:20 +00:00
d1a714e503
Working toward registration of register allocators.
...
llvm-svn: 29360
2006-07-27 20:05:00 +00:00
efc312a5c7
Code cleanups, per review
...
llvm-svn: 29347
2006-07-27 16:46:58 +00:00
acb606ff33
AssignNodeIds should return unsigned.
...
llvm-svn: 29343
2006-07-27 07:36:47 +00:00
29eefc164c
AssignNodeIds assign each node in the DAG an unique id.
...
llvm-svn: 29337
2006-07-27 06:39:06 +00:00
85ea83e821
Add some advice
...
llvm-svn: 29324
2006-07-27 04:24:14 +00:00
787565024a
Support jump tables when in PIC relocation model
...
llvm-svn: 29318
2006-07-27 01:13:04 +00:00
4488f0c303
Fix a case where LegalizeAllNodesNotLeadingTo could take exponential time.
...
This manifested itself as really long time to compile
Regression/CodeGen/Generic/2003-05-28-ManyArgs.ll on ppc.
This is PR847.
llvm-svn: 29313
2006-07-26 23:55:56 +00:00
421475cd3b
For PR780:
...
1. Move IncludeFile.h to System library
2. Move IncludeFile.cpp to System library
3. #1 and #2 required to prevent cyclic library dependencies for libSystem
4. Convert all existing uses of Support/IncludeFile.h to System/IncludeFile.h
5. Add IncludeFile support to various lib/System classes.
6. Add new lib/System classes to LinkAllVMCore.h
All this in an attempt to pull in lib/System to what's required for VMCore
llvm-svn: 29287
2006-07-26 16:18:00 +00:00
658b9476f0
Initialize some variables the compiler warns about.
...
llvm-svn: 29277
2006-07-25 20:44:41 +00:00
4b49c23571
Eliminate data relocations by using NULL instead of global empty list.
...
llvm-svn: 29250
2006-07-21 21:15:20 +00:00
4e153f1b91
Use an enumeration to eliminate data relocations.
...
llvm-svn: 29249
2006-07-21 20:57:35 +00:00
7c970b98d0
If a shuffle is a splat, check if the argument is a build_vector with all elements being the same. If so, return the argument.
...
llvm-svn: 29242
2006-07-21 08:25:53 +00:00
55782c6c41
Build more debugger/selectiondag libraries as archives instead of .o files.
...
This works around bugs in some versions of the cygwin linker.
Patch contributed by Anton Korobeynikov.
llvm-svn: 29239
2006-07-21 00:10:47 +00:00
8472e0c4af
If a shuffle is unary, i.e. one of the vector argument is not needed, turn the
...
operand into a undef and adjust mask accordingly.
llvm-svn: 29232
2006-07-20 22:44:41 +00:00
b030532910
Mems can be in the output list also. This is the second half of a fix for
...
PR833
llvm-svn: 29224
2006-07-20 19:02:21 +00:00
ec104a2b41
80 cols
...
llvm-svn: 29221
2006-07-20 17:43:27 +00:00
c496b418b5
Reduce number of exported symbols
...
llvm-svn: 29220
2006-07-20 17:28:38 +00:00
2b0baddc33
Fix linking on Alpha
...
llvm-svn: 29219
2006-07-20 17:27:58 +00:00
4238ca55ef
Move MVT::getVectorType out of line, it is large and shouldn't be inlined.
...
llvm-svn: 29195
2006-07-19 00:40:45 +00:00
c0973edc69
Add an out-of-line virtual method for the sdnode class to give it a home.
...
llvm-svn: 29192
2006-07-19 00:00:37 +00:00
fd5a8ebb74
On 64-bit targets like ppc64, we should use .quad to output pointer directives,
...
not .long.
llvm-svn: 29157
2006-07-15 01:34:12 +00:00
436c2dd927
Add an out-of-line virtual function to home class.
...
llvm-svn: 29154
2006-07-14 23:08:47 +00:00
194bef7ff4
Fixed a bug handling void function types.
...
Requires rebuild of llvm-gcc4 (touch llvm-debug.cpp.)
llvm-svn: 29131
2006-07-13 15:27:42 +00:00
f7300b2706
It was pointed out that DEBUG() is only available with -debug.
...
llvm-svn: 29106
2006-07-11 18:25:13 +00:00
c3d341ea98
Ensure that dump calls that are associated with asserts are removed from
...
non-debug build.
llvm-svn: 29105
2006-07-11 17:58:07 +00:00
6c72aa7411
1. Support for c++ mangled names.
...
2. Support for private/protected class members.
llvm-svn: 29104
2006-07-11 15:58:09 +00:00
1b8ea1f5ba
Fix CodeGen/Alpha/2006-07-03-ASMFormalLowering.ll and PR818.
...
llvm-svn: 29099
2006-07-11 01:40:09 +00:00
d19938834b
Ugly hack! Add helper functions InsertInFlightSetEntry and
...
RemoveInFlightSetEntry. They are used in place of direct set operators to
reduce instruction selection function stack size.
llvm-svn: 28987
2006-06-29 23:57:05 +00:00
ec1d60bd98
Add support to print 4-, 8-, and 16- byte constant literals in special
...
sections. e.g. On Darwin that would be .literal4 and .literal8.
llvm-svn: 28977
2006-06-29 00:26:09 +00:00
996795b0dd
Use hidden visibility to make symbols in an anonymous namespace get
...
dropped. This shrinks libllvmgcc.dylib another 67K
llvm-svn: 28975
2006-06-28 23:17:24 +00:00
e097e6f7c7
Shave another 27K off libllvmgcc.dylib with visibility hidden
...
llvm-svn: 28973
2006-06-28 22:17:39 +00:00
54a34cd20b
Mark these two classes as hidden, shrinking libllbmgcc.dylib by 25K
...
llvm-svn: 28970
2006-06-28 21:58:30 +00:00
710b3d5ea1
Fix CodeGen/Generic/2006-06-28-SimplifySetCCCrash.ll
...
llvm-svn: 28965
2006-06-28 18:29:47 +00:00
ee7eaa25cf
For PR801:
...
Refactor the Graph writing code to use a common implementation which is
now in lib/Support/GraphWriter.cpp. This completes the PR.
Patch by Anton Korobeynikov. Thanks, Anton!
llvm-svn: 28925
2006-06-27 16:49:46 +00:00
a7b2bd5997
Add and sort "sections" in debug lines. This always stepping through
...
code in sections other than ".text", including weak sections like ctors and
dtors.
llvm-svn: 28909
2006-06-23 12:51:53 +00:00
0a9e837b6f
Add support for function types.
...
llvm-svn: 28874
2006-06-20 19:41:06 +00:00
2837e3204f
References need to be section relative.
...
llvm-svn: 28861
2006-06-19 19:49:42 +00:00
f32058a2b7
References need to be section relative.
...
llvm-svn: 28858
2006-06-19 15:48:00 +00:00
90cd68acc6
Handle versioning of compile unit.
...
llvm-svn: 28855
2006-06-19 12:54:15 +00:00
b2ff2d481e
1. Revise vector debug support.
...
2. Update docs for vector debug support and new version control.
3. Simplify serialization of DebugDescInfo subclasses.
llvm-svn: 28816
2006-06-16 13:14:03 +00:00
4ff6c1646f
Teach the local allocator to know that live-in values (e.g. arguments) are
...
live at function entry. This prevents it from using arg registers for other
purposes before the arguments are used.
llvm-svn: 28809
2006-06-15 22:21:53 +00:00
19f964e048
1. Support standard dwarf format (was bootstrapping in Apple format.)
...
2. Add vector support.
llvm-svn: 28807
2006-06-15 20:51:43 +00:00
3519b87758
Was pointed out that structure alignment and type alignment are not the same
...
thing. Doubles still need to be special cased.
llvm-svn: 28806
2006-06-15 19:37:14 +00:00
dce07568f2
Alignment of globals has not been quite right. Needed to drop the pointer type
...
to get the alignment of the element type.
llvm-svn: 28799
2006-06-15 13:10:58 +00:00
ef9e07d3f0
Consistency. EXTRACT_ELEMENT index operand should have ptr type.
...
llvm-svn: 28795
2006-06-15 08:11:54 +00:00
df63179d95
Assert. Rather than silently stop printing.
...
llvm-svn: 28794
2006-06-15 08:10:56 +00:00
55772ccfd6
Instructions with variable operands (variable_ops) can have a number required
...
operands. e.g.
def CALL32r : I<0xFF, MRM2r, (ops GR32:$dst, variable_ops),
"call {*}$dst", [(X86call GR32:$dst)]>;
TableGen should emit operand informations for the "required" operands.
Added a target instruction info flag M_VARIABLE_OPS to indicate the target
instruction may have more operands in addition to the minimum required
operands.
llvm-svn: 28791
2006-06-15 07:22:16 +00:00
f0a7a1a117
Change versioning to per debug info descriptor (merged with tag.)
...
llvm-svn: 28782
2006-06-14 14:45:39 +00:00
f67bec0579
Place dwarf headers at earliest possible point. Well behaved when skipping
...
functions.
llvm-svn: 28781
2006-06-14 11:35:03 +00:00
32d92e004d
Make sure to update the CFG correctly if a switch only has a default dest.
...
This fixes CodeGen/Generic/2006-06-12-LowerSwitchCrash.ll
llvm-svn: 28755
2006-06-12 18:25:29 +00:00
0e57b2cb92
Start on my todo list
...
llvm-svn: 28752
2006-06-12 16:07:18 +00:00
c03a9259c0
Fix X86/inline-asm.ll:test2, a case where an input value was implicitly
...
truncated.
llvm-svn: 28733
2006-06-08 18:27:11 +00:00
705948d742
Fix Regression/CodeGen/X86/inline-asm.ll, a case where inline asm causes
...
implement extension of a register.
llvm-svn: 28731
2006-06-08 18:22:48 +00:00
8f8b5e4631
Fix an assert-on-inline-inline-asm bug.
...
llvm-svn: 28727
2006-06-08 18:00:47 +00:00
614cb2ff82
For PR798:
...
Provide GraphViz support for MingW32. Patch provided by Anton Korobeynikov
llvm-svn: 28688
2006-06-05 16:26:06 +00:00
7c77323e1d
For PR798:
...
Add support for Graphviz. Patch contributed by Anton Korobeynikov.
llvm-svn: 28684
2006-06-05 15:44:46 +00:00
cd8f67a106
Prevent the -pedantic option from causing Mac OS/X build problems:
...
LiveIntervalAnalysis.cpp:218: error: floating constant exceeds range of 'double'
llvm-svn: 28620
2006-06-01 06:12:21 +00:00
a647c7ff42
Use archive libraries instead of object files for VMCore, BCReader,
...
BCWriter, and bzip2 libraries. Adjust the various makefiles to accommodate
these changes. This was done to speed up link times.
llvm-svn: 28610
2006-06-01 01:30:27 +00:00
0c0996a97b
commuteInstruction() does not always create a new MI!
...
llvm-svn: 28592
2006-05-31 18:03:39 +00:00
9d91caa053
Eliminate a memory leak.
...
llvm-svn: 28585
2006-05-31 07:13:03 +00:00
64d2846017
visitVBinOp: Can't fold divide by zero!
...
llvm-svn: 28584
2006-05-31 06:08:35 +00:00
d12c97d23a
Make sure the register pressure reduction schedulers work for non-uniform
...
latency targets, e.g. PPC32.
llvm-svn: 28561
2006-05-30 18:05:39 +00:00
61e9f0d680
When a priority_queue is empty, the behavior of top() operator is
...
non-deterministic. Returns NULL when it's empty!
llvm-svn: 28560
2006-05-30 18:04:34 +00:00
8f872d2091
Fix a nasty dag combiner bug that caused nondeterminstic crashes (MY FAVORITE!):
...
SimplifySelectOps would eliminate a Select, delete it, then return true.
The clients would see that it did something and return null.
The top level would see a null return, and decide that nothing happened,
proceeding to process the node in other ways: boom.
The fix is simple: clients of SimplifySelectOps should return the select
node itself.
In order to catch really obnoxious boogs like this in the future, add an
assert that nodes are not deleted. We do this by checking for a sentry node
type that the SDNode dtor sets when a node is destroyed.
llvm-svn: 28514
2006-05-27 00:43:02 +00:00
21dee4e0b2
Make CALL node consistent with RET node. Signness of value has type MVT::i32
...
instead of MVT::i1. Either is fine except MVT::i32 is probably a legal type
for most (if not all) platforms while MVT::i1 is not.
llvm-svn: 28511
2006-05-26 23:13:20 +00:00
a2e9953c54
Change RET node to include signness information of the return values. e.g.
...
RET chain, value1, sign1, value2, sign2
llvm-svn: 28509
2006-05-26 23:09:09 +00:00
0f5c7936e7
Remove a bogus cast.
...
llvm-svn: 28492
2006-05-26 08:00:14 +00:00
009f5f55f7
Turn on -sched-commute-nodes by default.
...
llvm-svn: 28465
2006-05-25 08:37:31 +00:00
4582771f3f
CALL node change: now including signness of every argument.
...
llvm-svn: 28461
2006-05-25 00:55:32 +00:00
aa2372562e
Patches to make the LLVM sources more -pedantic clean. Patch provided
...
by Anton Korobeynikov! This is a step towards closing PR786.
llvm-svn: 28447
2006-05-24 17:04:05 +00:00
ac4f66ff24
-enable-unsafe-fp-math implies -enable-finite-only-fp-math
...
llvm-svn: 28437
2006-05-23 18:18:46 +00:00
df1d439849
Fix missing include
...
llvm-svn: 28435
2006-05-23 13:43:15 +00:00
1c5b7d12df
Incorrect SETCC CondCode used for FP comparisons.
...
llvm-svn: 28433
2006-05-23 06:40:47 +00:00
d8e2f6ebc1
lib/Target/Target.td
...
llvm-svn: 28386
2006-05-18 20:42:07 +00:00
7949c2e8b2
Fix the result of the call to use a correct vbitconvert. There is no need to
...
use getPackedTypeBreakdown at all here.
llvm-svn: 28365
2006-05-17 20:49:36 +00:00
938155ca57
Correct a previous patch which broke CodeGen/PowerPC/vec_call.ll
...
llvm-svn: 28364
2006-05-17 20:43:21 +00:00
751cd7653d
Fixed a LowerCallTo and LowerArguments bug. They were introducing illegal
...
VBIT_VECTOR nodes. There were some confusion about the semantics of
getPackedTypeBreakdown(). e.g. for <4 x f32> it returns 1 and v4f32, not 4,
and f32.
llvm-svn: 28352
2006-05-17 18:16:39 +00:00
62f1b83c0e
When we legalize target nodes, do not use getNode to create a new node,
...
use UpdateNodeOperands to just update the operands! This is important because
getNode will allocate a new node if the node returns a flag and this breaks
assumptions in the legalizer that you can legalize some things multiple times
and get exactly the same results.
This latent bug was exposed by my ppc patch last night, and this fixes
gsm/toast.
llvm-svn: 28348
2006-05-17 18:00:08 +00:00
a1cec0106a
Add an assertion, avoid some unneeded work for each call. No functionality
...
change.
llvm-svn: 28347
2006-05-17 17:55:45 +00:00
b77ba73a29
Add support for calls that pass and return legal vectors.
...
llvm-svn: 28340
2006-05-16 23:39:44 +00:00
aaa23d953f
Add a new ISD::CALL node, make the default impl of TargetLowering::LowerCallTo
...
produce it.
llvm-svn: 28338
2006-05-16 22:53:20 +00:00
1dc9ec5874
Move this code to a common place
...
llvm-svn: 28329
2006-05-16 17:42:15 +00:00
3d82699605
Add a chain to FORMAL_ARGUMENTS. This is a minimal port of the X86 backend,
...
it doesn't currently use/maintain the chain properly. Also, make the
X86ISelLowering.cpp file 80-col clean.
llvm-svn: 28320
2006-05-16 06:45:34 +00:00
957cb6733a
Move function-live-in-handling code from the sdisel code to the scheduler.
...
This code should be emitted after legalize, so it can't be in sdisel.
Note that the EmitFunctionEntryCode hook should be updated to operate on the
DAG. The X86 backend is the only one currently using this hook.
llvm-svn: 28315
2006-05-16 06:10:58 +00:00
52d0c78de8
Print the vreg that livein physregs are live in
...
llvm-svn: 28314
2006-05-16 05:55:30 +00:00
5f0edfb849
Legalize FORMAL_ARGUMENTS nodes correctly, we don't want to legalize them once
...
for each argument.
llvm-svn: 28313
2006-05-16 05:49:56 +00:00
99f2f79e2f
Fixing 2006-05-01-SchedCausingSpills.ll; some clean up
...
llvm-svn: 28279
2006-05-13 08:22:24 +00:00
d1915cfa6f
Revert an un-intended change
...
llvm-svn: 28278
2006-05-13 05:53:47 +00:00
69a0ce6261
Merge identical code.
...
llvm-svn: 28274
2006-05-13 02:11:14 +00:00
a726fc6dbf
If the register allocator cannot find a register to spill, try the aliases. If
...
that still fails (because all the register spill weights are inf), just grab
one.
llvm-svn: 28262
2006-05-12 19:07:46 +00:00
53cdb2f2b0
Remove dead vars
...
llvm-svn: 28255
2006-05-12 18:06:45 +00:00
da076e41ab
remove dead vars
...
llvm-svn: 28254
2006-05-12 18:04:28 +00:00
fe211deedf
Remove dead variable
...
llvm-svn: 28253
2006-05-12 18:02:04 +00:00
afe72481f6
Comment out dead variables
...
llvm-svn: 28252
2006-05-12 17:57:54 +00:00
936cd3390d
Remove dead var
...
llvm-svn: 28250
2006-05-12 17:50:35 +00:00
8c02c3f41a
Compile:
...
%tmp152 = setgt uint %tmp144, %tmp149 ; <bool> [#uses=1]
%tmp159 = setlt uint %tmp144, %tmp149 ; <bool> [#uses=1]
%bothcond2 = or bool %tmp152, %tmp159 ; <bool> [#uses=1]
To setne, not setune, which causes an assertion fault.
llvm-svn: 28244
2006-05-12 17:03:46 +00:00
8c2c1e90c4
Refactor a bunch of includes so that TargetMachine.h doesn't have to include
...
TargetData.h. This should make recompiles a bit faster with my current
TargetData tinkering.
llvm-svn: 28238
2006-05-12 06:33:49 +00:00
6a6886185b
Backing out fix for PR770. Need to re-apply it after live range splitting is possible
...
llvm-svn: 28236
2006-05-12 06:06:34 +00:00
095c9d9b7f
Duh. That could take a long time.
...
llvm-svn: 28235
2006-05-12 06:05:18 +00:00
66adee93aa
Two simplifications for token factor nodes: simplify tf(x,x) -> x.
...
simplify tf(x,y,y,z) -> tf(x,y,z).
llvm-svn: 28233
2006-05-12 05:01:37 +00:00
afed73eebe
Add capability to scheduler to commute nodes for profit.
...
If a two-address code whose first operand has uses below, it should be commuted
when possible.
llvm-svn: 28230
2006-05-12 01:58:24 +00:00
d38c22bdd3
Refactor scheduler code. Move register-reduction list scheduler to a
...
separate file. Added an initial implementation of top-down register pressure
reduction list scheduler.
llvm-svn: 28226
2006-05-11 23:55:42 +00:00
47926aff96
Set weight of zero length intervals to infinite to prevent them from being
...
spilled.
llvm-svn: 28220
2006-05-11 07:29:24 +00:00
db6aa4896b
Backing out previous check-in.
...
llvm-svn: 28219
2006-05-11 07:28:16 +00:00
6ad040a6bc
If the live interval legnth is essentially zero, i.e. in every live range
...
the use follows def immediately, it doesn't make sense to spill it and
hope it will be easier to allocate for this LI.
llvm-svn: 28217
2006-05-10 22:30:41 +00:00
9665ba053f
Templatify RegReductionPriorityQueue
...
llvm-svn: 28212
2006-05-10 06:16:44 +00:00
1a225d23ae
Fix PR773
...
llvm-svn: 28207
2006-05-09 18:20:51 +00:00
f801792e08
Fix a regression in my patch from last night that broke the llvmgcc4 build on
...
ppc
llvm-svn: 28205
2006-05-09 16:41:59 +00:00
7d693898ee
Add pseudo dependency to force a def&use operand to be scheduled last (unless
...
the distance between the def and another use is much longer). This is under
option control for now "-sched-lower-defnuse".
llvm-svn: 28201
2006-05-09 07:13:34 +00:00
2c74848af1
Debugging info
...
llvm-svn: 28200
2006-05-09 06:55:15 +00:00
ae45020720
PR 770 - permit coallescing of registers in subset register classes.
...
llvm-svn: 28197
2006-05-09 06:37:48 +00:00
4ebc6a2311
Implement MASM sections correctly, without a "has masm sections flag" and a bunch of special case code.
...
llvm-svn: 28194
2006-05-09 05:33:48 +00:00
8c2bfc0659
Oh yeah, there are two of these now, unify both.
...
llvm-svn: 28192
2006-05-09 05:24:50 +00:00
6341df8069
Setting SwitchToSectionDirective properly in the MASM backend permits a bunch
...
of code to be unified.
llvm-svn: 28191
2006-05-09 05:23:12 +00:00
d36cc2b610
Don't prefix section directives with a tab. Doing so causes blank lines to
...
be emitted to the .s file.
llvm-svn: 28189
2006-05-09 05:19:59 +00:00
e64f764d25
Make the masm codepath work like the normal code path.
...
llvm-svn: 28188
2006-05-09 05:15:58 +00:00
c0f0dfa56f
The MASM asmprinter has been fixed, these hacks are no longer needed.
...
llvm-svn: 28186
2006-05-09 05:13:34 +00:00
8488ba2e41
Split SwitchSection into SwitchTo{Text|Data}Section methods.
...
llvm-svn: 28184
2006-05-09 04:59:56 +00:00
446e1ef26a
Make the case I just checked in stronger. Now we compile this:
...
short test2(short X, short x) {
int Y = (short)(X+x);
return Y >> 1;
}
to:
_test2:
add r2, r3, r4
extsh r2, r2
srawi r3, r2, 1
blr
instead of:
_test2:
add r2, r3, r4
extsh r2, r2
srwi r2, r2, 1
extsh r3, r2
blr
llvm-svn: 28175
2006-05-08 21:18:59 +00:00
29062da0ac
Implement and_sext.ll:test3, generating:
...
_test4:
srawi r3, r3, 16
blr
instead of:
_test4:
srwi r2, r3, 16
extsh r3, r2
blr
for:
short test4(unsigned X) {
return (X >> 16);
}
llvm-svn: 28174
2006-05-08 20:59:41 +00:00
2935d8190c
Compile this:
...
short test4(unsigned X) {
return (X >> 16);
}
to:
_test4:
movl 4(%esp), %eax
sarl $16, %eax
ret
instead of:
_test4:
movl $-65536, %eax
andl 4(%esp), %eax
sarl $16, %eax
ret
llvm-svn: 28171
2006-05-08 20:51:54 +00:00
78da6792e7
Fold shifts with undef operands.
...
llvm-svn: 28167
2006-05-08 17:29:49 +00:00
d7a19102d1
Make emission of jump tables a bit less conservative; they are now required
...
to be only 31.25% dense, rather than 75% dense.
llvm-svn: 28165
2006-05-08 16:51:36 +00:00
e5ce5bb6da
Fix PR772
...
llvm-svn: 28161
2006-05-08 01:35:01 +00:00
7e7bcf3a54
Simplify some code, add a couple minor missed folds
...
llvm-svn: 28152
2006-05-06 23:06:26 +00:00
751817c54f
constant fold sign_extend_inreg
...
llvm-svn: 28151
2006-05-06 23:05:41 +00:00
2a4d7b845b
remove cases handled elsewhere
...
llvm-svn: 28150
2006-05-06 22:43:44 +00:00
ce9b9fe6eb
Fix some loose ends in MASM support.
...
llvm-svn: 28148
2006-05-06 21:27:14 +00:00
1ecb2a2dac
Use the new TargetLowering::ComputeNumSignBits method to eliminate
...
sign_extend_inreg operations. Though ComputeNumSignBits is still rudimentary,
this is enough to compile this:
short test(short X, short x) {
int Y = X+x;
return (Y >> 1);
}
short test2(short X, short x) {
int Y = (short)(X+x);
return Y >> 1;
}
into:
_test:
add r2, r3, r4
srawi r3, r2, 1
blr
_test2:
add r2, r3, r4
extsh r2, r2
srawi r3, r2, 1
blr
instead of:
_test:
add r2, r3, r4
srawi r2, r2, 1
extsh r3, r2
blr
_test2:
add r2, r3, r4
extsh r2, r2
srawi r2, r2, 1
extsh r3, r2
blr
llvm-svn: 28146
2006-05-06 09:30:03 +00:00
21cd99024a
When inserting casts, be careful of where we put them. We cannot insert
...
a cast immediately before a PHI node.
This fixes Regression/CodeGen/Generic/2006-05-06-GEP-Cast-Sink-Crash.ll
llvm-svn: 28143
2006-05-06 09:10:37 +00:00
907e392dba
Fold trunc(any_ext). This gives stuff like:
...
27,28c27
< movzwl %di, %edi
< movl %edi, %ebx
---
> movw %di, %bx
llvm-svn: 28137
2006-05-05 22:56:26 +00:00
57f8c5a387
Shrink shifts when possible.
...
llvm-svn: 28136
2006-05-05 22:53:17 +00:00
a633c31319
Indent multiline asm strings more nicely
...
llvm-svn: 28132
2006-05-05 21:47:05 +00:00
3d26577396
Fold (fpext (load x)) -> (extload x)
...
llvm-svn: 28130
2006-05-05 21:34:35 +00:00
3e3f2c63c3
More aggressively sink GEP offsets into loops. For example, before we
...
generated:
movl 8(%esp), %eax
movl %eax, %edx
addl $4316, %edx
cmpb $1, %cl
ja LBB1_2 #cond_false
LBB1_1: #cond_true
movl L_QuantizationTables720$non_lazy_ptr, %ecx
movl %ecx, (%edx)
movl L_QNOtoQuantTableShift720$non_lazy_ptr, %edx
movl %edx, 4460(%eax)
ret
...
Now we generate:
movl 8(%esp), %eax
cmpb $1, %cl
ja LBB1_2 #cond_false
LBB1_1: #cond_true
movl L_QuantizationTables720$non_lazy_ptr, %ecx
movl %ecx, 4316(%eax)
movl L_QNOtoQuantTableShift720$non_lazy_ptr, %ecx
movl %ecx, 4460(%eax)
ret
... which uses one fewer register.
llvm-svn: 28129
2006-05-05 21:17:49 +00:00
25a5283a86
Fold some common code.
...
llvm-svn: 28124
2006-05-05 06:32:04 +00:00
002ee91457
Implement:
...
// fold (and (sext x), (sext y)) -> (sext (and x, y))
// fold (or (sext x), (sext y)) -> (sext (or x, y))
// fold (xor (sext x), (sext y)) -> (sext (xor x, y))
// fold (and (aext x), (aext y)) -> (aext (and x, y))
// fold (or (aext x), (aext y)) -> (aext (or x, y))
// fold (xor (aext x), (aext y)) -> (aext (xor x, y))
llvm-svn: 28123
2006-05-05 06:31:05 +00:00
5ac4293606
Pull and through and/or/xor. This compiles some bitfield code to:
...
mov EAX, DWORD PTR [ESP + 4]
mov ECX, DWORD PTR [EAX]
mov EDX, ECX
add EDX, EDX
or EDX, ECX
and EDX, -2147483648
and ECX, 2147483647
or EDX, ECX
mov DWORD PTR [EAX], EDX
ret
instead of:
sub ESP, 4
mov DWORD PTR [ESP], ESI
mov EAX, DWORD PTR [ESP + 8]
mov ECX, DWORD PTR [EAX]
mov EDX, ECX
add EDX, EDX
mov ESI, ECX
and ESI, -2147483648
and EDX, -2147483648
or EDX, ESI
and ECX, 2147483647
or EDX, ECX
mov DWORD PTR [EAX], EDX
mov ESI, DWORD PTR [ESP]
add ESP, 4
ret
llvm-svn: 28122
2006-05-05 06:10:43 +00:00
812646aa0c
Implement a variety of simplifications for ANY_EXTEND.
...
llvm-svn: 28121
2006-05-05 05:58:59 +00:00
8d6fc20181
Factor some code, add these transformations:
...
// fold (and (trunc x), (trunc y)) -> (trunc (and x, y))
// fold (or (trunc x), (trunc y)) -> (trunc (or x, y))
// fold (xor (trunc x), (trunc y)) -> (trunc (xor x, y))
llvm-svn: 28120
2006-05-05 05:51:50 +00:00
78a7f0e05e
Fix VC++ compilation error.
...
llvm-svn: 28117
2006-05-05 01:47:05 +00:00
7a3ecf7993
Sink noop copies into the basic block that uses them. This reduces the number
...
of cross-block live ranges, and allows the bb-at-a-time selector to always
coallesce these away, at isel time.
This reduces the load on the coallescer and register allocator. For example
on a codec on X86, we went from:
1643 asm-printer - Number of machine instrs printed
419 liveintervals - Number of loads/stores folded into instructions
1144 liveintervals - Number of identity moves eliminated after coalescing
1022 liveintervals - Number of interval joins performed
282 liveintervals - Number of intervals after coalescing
1304 liveintervals - Number of original intervals
86 regalloc - Number of times we had to backtrack
1.90232 regalloc - Ratio of intervals processed over total intervals
40 spiller - Number of values reused
182 spiller - Number of loads added
121 spiller - Number of stores added
132 spiller - Number of register spills
6 twoaddressinstruction - Number of instructions commuted to coalesce
360 twoaddressinstruction - Number of two-address instructions
to:
1636 asm-printer - Number of machine instrs printed
403 liveintervals - Number of loads/stores folded into instructions
1155 liveintervals - Number of identity moves eliminated after coalescing
1033 liveintervals - Number of interval joins performed
279 liveintervals - Number of intervals after coalescing
1312 liveintervals - Number of original intervals
76 regalloc - Number of times we had to backtrack
1.88998 regalloc - Ratio of intervals processed over total intervals
1 spiller - Number of copies elided
41 spiller - Number of values reused
191 spiller - Number of loads added
114 spiller - Number of stores added
128 spiller - Number of register spills
4 twoaddressinstruction - Number of instructions commuted to coalesce
356 twoaddressinstruction - Number of two-address instructions
On this testcase, this change provides a modest reduction in spill code,
regalloc iterations, and total instructions emitted. It increases the number
of register coallesces.
llvm-svn: 28115
2006-05-05 01:04:50 +00:00
abdf4d569c
Final pass of minor cleanups for MachineInstr
...
llvm-svn: 28110
2006-05-04 19:36:09 +00:00
9add880566
Initial support for register pressure aware scheduling. The register reduction
...
scheduler can go into a "vertical mode" (i.e. traversing up the two-address
chain, etc.) when the register pressure is low.
This does seem to reduce the number of spills in the cases I've looked at. But
with x86, it's no guarantee the performance of the code improves.
It can be turned on with -sched-vertically option.
llvm-svn: 28108
2006-05-04 19:16:39 +00:00
53af9da363
Remove redundancy and a level of indirection when creating machine operands
...
llvm-svn: 28107
2006-05-04 19:14:44 +00:00
469647bf38
Remove and simplify some more machineinstr/machineoperand stuff.
...
llvm-svn: 28105
2006-05-04 18:16:01 +00:00
10b71c0d08
Rename MO_VirtualRegister -> MO_Register. Clean up immediate handling.
...
llvm-svn: 28104
2006-05-04 18:05:43 +00:00
10d6341618
Move some methods out of MachineInstr into MachineOperand
...
llvm-svn: 28102
2006-05-04 17:52:23 +00:00
fef7a2d0f5
There shalt be only one "immediate" operand type!
...
llvm-svn: 28099
2006-05-04 17:21:20 +00:00
15c52bda1d
Change "value" in MachineOperand to be a GlobalValue, as that is the only
...
thing that can be in it. Remove a dead method.
llvm-svn: 28098
2006-05-04 17:02:51 +00:00
ee64b6b40f
Remove a bunch more dead V9 specific stuff
...
llvm-svn: 28094
2006-05-04 01:26:39 +00:00
940cc978ef
Remove a bunch more SparcV9 specific stuff
...
llvm-svn: 28093
2006-05-04 01:15:02 +00:00
6e663f1c1e
Remove some more V9-specific stuff.
...
llvm-svn: 28092
2006-05-04 00:49:59 +00:00
9f6639b64d
Remove some more unused stuff from MachineInstr that was leftover from V9.
...
llvm-svn: 28091
2006-05-04 00:44:25 +00:00
1d8ee1fc80
Suck block address tracking out of targets into the JIT Emitter. This
...
simplifies the MachineCodeEmitter interface just a little bit and makes
BasicBlocks work like constant pools and jump tables.
llvm-svn: 28082
2006-05-03 17:10:41 +00:00
df4883971e
Finish up the initial jump table implementation by allowing jump tables to
...
not be 100% dense. Increase the minimum threshold for the number of cases
in a switch statement from 4 to 6 in order to create a jump table.
llvm-svn: 28079
2006-05-03 03:48:02 +00:00
ffef8b9412
Bottom up register pressure reduction work: clean up some hacks and enhanced
...
the heuristic to further reduce spills for several test cases. (Note, it may
not necessarily translate to runtime win!)
llvm-svn: 28076
2006-05-03 02:10:45 +00:00
20a631fde7
Refactor TargetMachine, pushing handling of TargetData into the target-specific subclasses. This has one caller-visible change: getTargetData() now returns a pointer instead of a reference.
...
This fixes PR 759.
llvm-svn: 28074
2006-05-03 01:29:57 +00:00
d8b192ba3b
Change the BasicBlockAddrs map to be a vector, indexed by MBB number.
...
llvm-svn: 28069
2006-05-03 00:32:55 +00:00
b8065a9a3a
Several related changes:
...
1. Change several methods in the MachineCodeEmitter class to be pure virtual.
2. Suck emitConstantPool/initJumpTableInfo into startFunction, removing them
from the MachineCodeEmitter interface, and reducing the amount of target-
specific code.
3. Change the JITEmitter so that it allocates constantpools and jump tables
*right* next to the functions that they belong to, instead of in a separate
pool of memory. This makes all memory for a function be contiguous, and
means the JITEmitter only tracks one block of memory now.
llvm-svn: 28065
2006-05-02 23:22:24 +00:00
23621fe8f4
Do not make the JIT memory manager manage the memory for globals. Instead
...
just have the JIT malloc them.
llvm-svn: 28062
2006-05-02 21:57:51 +00:00
c9aa3715e8
Refactor the machine code emitter interface to pull the pointers for the current
...
code emission location into the base class, instead of being in the derived classes.
This change means that low-level methods like emitByte/emitWord now are no longer
virtual (yaay for speed), and we now have a framework to support growable code
segments. This implements feature request #1 of PR469.
llvm-svn: 28059
2006-05-02 18:27:26 +00:00
4971ba5f41
Print function number instead of name
...
llvm-svn: 28057
2006-05-02 17:36:46 +00:00
67a3aa2aaa
Remove dead method
...
llvm-svn: 28055
2006-05-02 17:20:28 +00:00
bb1c345ec6
Remove the debug machine code emitter. The "FilePrinterEmitter" is more
...
useful for debugging.
llvm-svn: 28051
2006-05-02 16:59:24 +00:00
b9d4f8324d
Extend printBasicBlockLabel a bit so that it can be used to print all
...
basic block labels, consolidating the code to do so in one place for each
target.
llvm-svn: 28050
2006-05-02 05:37:32 +00:00
470f431f44
De-virtualize SwitchSection.
...
llvm-svn: 28047
2006-05-02 03:58:45 +00:00
f34ddb1e0d
De-virtualize EmitZeroes.
...
llvm-svn: 28046
2006-05-02 03:46:13 +00:00
24a62a9bc1
Make Intel syntax mode friendlier to Microsoft ML assembler (still needs more work).
...
llvm-svn: 28044
2006-05-02 01:16:28 +00:00
fd0a5478a1
Fix a latent bug that my spiller patch last week exposed: we were leaving
...
instructions in the virtregfolded map that were deleted. Because they
were deleted, newly allocated instructions could end up at the same address,
magically finding themselves in the map. The solution is to remove entries
from the map when we delete the instructions.
llvm-svn: 28041
2006-05-01 22:03:24 +00:00
ab7dbe0cc9
When promoting a load to a reg-reg copy, where the load was a previous
...
instruction folded with spill code, make sure the remove the load from
the virt reg folded map.
llvm-svn: 28040
2006-05-01 21:17:10 +00:00
4dee67c2cd
Remove previous patch, which wasn't quite right.
...
llvm-svn: 28039
2006-05-01 21:16:03 +00:00
0d084fb9ca
Dis-favor stores more
...
llvm-svn: 28035
2006-05-01 09:20:44 +00:00
24e795496d
Bottom up register-pressure reduction scheduler now pushes store operations
...
up the schedule. This helps code that looks like this:
loads ...
computations (first set) ...
stores (first set) ...
loads
computations (seccond set) ...
stores (seccond set) ...
Without this change, the stores and computations are more likely to
interleave:
loads ...
loads ...
computations (first set) ...
computations (second set) ...
computations (first set) ...
stores (first set) ...
computations (second set) ...
stores (stores set) ...
This can increase the number of spills if we are unlucky.
llvm-svn: 28033
2006-05-01 09:14:40 +00:00
10ff7b27ce
Didn't mean ScheduleDAGList.cpp to make the last checkin.
...
llvm-svn: 28030
2006-05-01 08:56:34 +00:00
a656242690
Remove temp. option -spiller-check-liveout, it didn't cause any failure nor performance regressions.
...
llvm-svn: 28029
2006-05-01 08:54:57 +00:00
25f55ae74a
Format #APP lines a bit nicer
...
llvm-svn: 28026
2006-05-01 04:11:03 +00:00
f71f0f2e0b
Local spiller kills a store if the folded restore is turned into a copy.
...
But this is incorrect if the spilled value live range extends beyond the
current BB.
It is currently controlled by a temporary option -spiller-check-liveout.
llvm-svn: 28024
2006-04-30 08:41:47 +00:00
2b48a94413
Remove a bogus transformation. This fixes SingleSource/UnitTests/2006-01-23-InitializedBitField.c
...
with some changes I have to the new CFE.
llvm-svn: 28022
2006-04-28 23:33:20 +00:00
c5e8ce8b8c
Remove the temporary option: -no-isel-fold-inflight
...
llvm-svn: 28012
2006-04-28 18:54:11 +00:00
d43c5c6046
TargetLowering::LowerArguments should return a VBIT_CONVERT of
...
FORMAL_ARGUMENTS SDOperand in the return result vector.
llvm-svn: 28009
2006-04-28 05:25:15 +00:00
79c50d96c9
Mapping of physregs can make it so that the designated and input physregs are
...
the same. In this case, don't emit a noop copy.
llvm-svn: 28008
2006-04-28 04:43:18 +00:00
51ab4498e7
Added a temporary option -no-isel-fold-inflight to control whether a "inflight"
...
node can be folded.
llvm-svn: 28003
2006-04-28 02:09:19 +00:00
84e95d00b5
When we have a two-address instruction where the input cannot be clobbered
...
and is already available, instead of falling back to emitting a load, fall
back to emitting a reg-reg copy. This generates significantly better code
for some SSE testcases, as SSE has lots of two-address instructions and
none of them are read/modify/write. As one example, this change does:
pshufd %XMM5, XMMWORD PTR [%ESP + 84], 255
xorps %XMM2, %XMM5
cmpltps %XMM1, %XMM0
- movaps XMMWORD PTR [%ESP + 52], %XMM0
- movapd %XMM6, XMMWORD PTR [%ESP + 52]
+ movaps %XMM6, %XMM0
cmpltps %XMM6, XMMWORD PTR [%ESP + 68]
movapd XMMWORD PTR [%ESP + 52], %XMM6
movaps %XMM6, %XMM0
cmpltps %XMM6, XMMWORD PTR [%ESP + 36]
cmpltps %XMM3, %XMM0
- movaps XMMWORD PTR [%ESP + 20], %XMM0
- movapd %XMM7, XMMWORD PTR [%ESP + 20]
+ movaps %XMM7, %XMM0
cmpltps %XMM7, XMMWORD PTR [%ESP + 4]
movapd XMMWORD PTR [%ESP + 20], %XMM7
cmpltps %XMM4, %XMM0
... which is far better than a store followed by a load!
llvm-svn: 28001
2006-04-28 01:46:50 +00:00
3784f3c57c
Insert a VBIT_CONVERT between a FORMAL_ARGUMENT node and its vector uses
...
(VAND, VADD, etc.). Legalizer will assert otherwise.
llvm-svn: 27991
2006-04-27 08:29:42 +00:00
393d96a56c
Fix Regression/CodeGen/Generic/2006-04-26-SetCCAnd.ll and
...
PR748.
llvm-svn: 27987
2006-04-27 05:01:07 +00:00
9618df1190
Don't forget return void.
...
llvm-svn: 27974
2006-04-25 23:03:35 +00:00
866b4b4d45
Fix the updating of the machine CFG when a PHI node was in a successor of
...
the jump table's range check block. This re-enables 100% dense jump tables
by default on PPC & x86
llvm-svn: 27952
2006-04-23 06:26:20 +00:00
3e04bb482b
Code cleanup associated with jump tables, thanks to Chris for noticing
...
these.
llvm-svn: 27950
2006-04-22 23:52:35 +00:00
ecb1dafd3d
Turn of jump tables for a bit, there are still some issues to work out with
...
updating the machine CFG.
llvm-svn: 27949
2006-04-22 23:51:56 +00:00
4ca2ea5b43
JumpTable support! What this represents is working asm and jit support for
...
x86 and ppc for 100% dense switch statements when relocations are non-PIC.
This support will be extended and enhanced in the coming days to support
PIC, and less dense forms of jump tables.
llvm-svn: 27947
2006-04-22 18:53:45 +00:00
b21d3bfd1f
The BFS scheduler is apparently nondeterminstic (causes many llvmgcc bootstrap
...
miscompares). Switch RISC targets to use the list-td scheduler, which isn't.
llvm-svn: 27933
2006-04-21 17:16:16 +00:00
662e940f73
Fix a couple more memory issues
...
llvm-svn: 27930
2006-04-21 15:32:26 +00:00
cc47ab3305
Fix a really subtle and obnoxious memory bug that caused issues with an
...
llvm-gcc4 boostrap. Whenever a node is deleted by the dag combiner, it
*must* be returned by the visit function, or the dag combiner will not
know that the node has been processed (and will, e.g., send it to the
target dag combine xforms).
llvm-svn: 27922
2006-04-20 23:55:59 +00:00
dcc1f995eb
This field no longer exists
...
llvm-svn: 27899
2006-04-20 18:32:41 +00:00
a38c3580bd
Remove some of the obvious V9-specific cruft
...
llvm-svn: 27893
2006-04-20 18:08:53 +00:00
a320abc494
Turn a VAND into a VECTOR_SHUFFLE is applicable.
...
DAG combiner can turn a VAND V, <-1, 0, -1, -1>, i.e. vector clear elements,
into a vector shuffle with a zero vector. It only does so when TLI tells it
the xform is profitable.
llvm-svn: 27874
2006-04-20 08:56:16 +00:00
bc1b262725
Implement folding of a bunch of binops with undef
...
llvm-svn: 27863
2006-04-20 05:39:12 +00:00
73eb58e1a2
Simplify some code
...
llvm-svn: 27846
2006-04-19 23:17:50 +00:00
916ae0775e
Fix handling of calls in functions that use vectors. This fixes a crash on
...
the code in GCC PR26546.
llvm-svn: 27780
2006-04-17 22:10:08 +00:00
bec79b4a59
Add a MachineInstr::eraseFromParent convenience method.
...
llvm-svn: 27775
2006-04-17 21:35:41 +00:00
326870b40b
Codegen insertelement with constant insertion points as scalar_to_vector
...
and a shuffle. For this:
void %test2(<4 x float>* %F, float %f) {
%tmp = load <4 x float>* %F ; <<4 x float>> [#uses=2]
%tmp3 = add <4 x float> %tmp, %tmp ; <<4 x float>> [#uses=1]
%tmp2 = insertelement <4 x float> %tmp3, float %f, uint 2 ; <<4 x float>> [#uses=2]
%tmp6 = add <4 x float> %tmp2, %tmp2 ; <<4 x float>> [#uses=1]
store <4 x float> %tmp6, <4 x float>* %F
ret void
}
we now get this on X86 (which will get better):
_test2:
movl 4(%esp), %eax
movaps (%eax), %xmm0
addps %xmm0, %xmm0
movaps %xmm0, %xmm1
shufps $3, %xmm1, %xmm1
movaps %xmm0, %xmm2
shufps $1, %xmm2, %xmm2
unpcklps %xmm1, %xmm2
movss 8(%esp), %xmm1
unpcklps %xmm1, %xmm0
unpcklps %xmm2, %xmm0
addps %xmm0, %xmm0
movaps %xmm0, (%eax)
ret
instead of:
_test2:
subl $28, %esp
movl 32(%esp), %eax
movaps (%eax), %xmm0
addps %xmm0, %xmm0
movaps %xmm0, (%esp)
movss 36(%esp), %xmm0
movss %xmm0, 8(%esp)
movaps (%esp), %xmm0
addps %xmm0, %xmm0
movaps %xmm0, (%eax)
addl $28, %esp
ret
llvm-svn: 27765
2006-04-17 19:21:01 +00:00
91226e5799
Add support for promoting stores from one legal type to another, allowing us
...
to write one pattern for vector stores instead of 4.
llvm-svn: 27730
2006-04-16 01:36:45 +00:00
7e7ad593cc
Make these predicates return true for bit_convert(buildvector)'s as well as
...
buildvectors.
llvm-svn: 27723
2006-04-15 23:38:00 +00:00
086e986e94
Make this assertion better
...
llvm-svn: 27695
2006-04-14 06:08:35 +00:00
709eaacb36
Expand some code with temporary variables to rid ourselves of the warning
...
about "dereferencing type-punned pointer will break strict-aliasing rules"
llvm-svn: 27671
2006-04-13 18:29:58 +00:00
119266ea92
Promote vector AND, OR, and XOR
...
llvm-svn: 27632
2006-04-12 21:20:24 +00:00
be8a8933e6
Vector type promotion for ISD::LOAD and ISD::SELECT
...
llvm-svn: 27606
2006-04-12 16:33:18 +00:00
d3b504ae10
Implement support for the formal_arguments node. To get this, targets shouldcustom legalize it and remove their XXXTargetLowering::LowerArguments overload
...
llvm-svn: 27604
2006-04-12 16:20:43 +00:00
417b96b6dd
Don't memoize vloads in the load map! Don't memoize them anywhere here, let
...
getNode do it. This fixes CodeGen/Generic/2006-04-11-vecload.ll
llvm-svn: 27602
2006-04-12 03:25:41 +00:00
7256b0ae05
Only get Tmp2 for cases where number of operands is > 1. Fixed return void.
...
llvm-svn: 27586
2006-04-11 06:33:39 +00:00
6cf3bbbe17
add some todos
...
llvm-svn: 27580
2006-04-11 02:00:08 +00:00
2eb22eef7d
Add basic support for legalizing returns of vectors
...
llvm-svn: 27578
2006-04-11 01:31:51 +00:00
dca2655daa
Use existing information.
...
llvm-svn: 27574
2006-04-10 23:09:19 +00:00
cb73b8d419
Missing break
...
llvm-svn: 27559
2006-04-10 18:54:36 +00:00
02274a5265
Add code generator support for VSELECT
...
llvm-svn: 27542
2006-04-08 22:22:57 +00:00
e1401e3610
Canonicalize vvector_shuffle(x,x) -> vvector_shuffle(x,undef) to enable patterns
...
to match again :)
llvm-svn: 27533
2006-04-08 05:34:25 +00:00
098c01e94e
Codegen shufflevector as VVECTOR_SHUFFLE
...
llvm-svn: 27529
2006-04-08 04:15:24 +00:00
101ea66813
add a sanity check: LegalizeOp should return a value that is the same type
...
as its input.
llvm-svn: 27528
2006-04-08 04:13:17 +00:00
78e3d565af
INSERT_VECTOR_ELT lowering bug:
...
store vector to $esp
store element to $esp + sizeof(VT) * index
load vector from $esp
The bug is VT is the type of the vector element, not the type of the vector!
llvm-svn: 27517
2006-04-08 01:46:37 +00:00
aa3185f12e
Stub out shufflevector
...
llvm-svn: 27514
2006-04-08 01:19:25 +00:00
7d4592733c
Remove section change in function end, preventing override of function's real
...
section.
llvm-svn: 27503
2006-04-08 00:35:59 +00:00
c0d6518f27
Make sure that debug labels are defined within the same section and after the
...
entry point of a function.
llvm-svn: 27494
2006-04-07 20:44:42 +00:00
2d7298c362
Foundation for call frame information.
...
llvm-svn: 27491
2006-04-07 16:34:46 +00:00
613996c55e
1. If both vector operands of a vector_shuffle are undef, turn it into an undef.
...
2. A shuffle mask element can also be an undef.
llvm-svn: 27472
2006-04-06 23:20:43 +00:00
4a2413a590
Make a vector live across blocks have the correct Vec type. This fixes
...
CodeGen/X86/2006-04-04-CrossBlockCrash.ll
llvm-svn: 27436
2006-04-05 06:54:42 +00:00
9fa8959dce
Exapnd a VECTOR_SHUFFLE to a BUILD_VECTOR if target asks for it to be expanded
...
or custom lowering fails.
llvm-svn: 27432
2006-04-05 06:07:11 +00:00
4ea52cac01
Do not create ZEXTLOAD's unless we are before legalize or the operation is
...
legal.
llvm-svn: 27402
2006-04-04 17:39:18 +00:00
6be79823e7
* Add supprot for SCALAR_TO_VECTOR operations where the input needs to be
...
promoted/expanded (e.g. SCALAR_TO_VECTOR from i8/i16 on PPC).
* Add support for targets to request that VECTOR_SHUFFLE nodes be promoted
to a canonical type, for example, we only want v16i8 shuffles on PPC.
* Move isShuffleLegal out of TLI into Legalize.
* Teach isShuffleLegal to allow shuffles that need to be promoted.
llvm-svn: 27399
2006-04-04 17:23:26 +00:00
a9e77d14c7
Constant fold bitconvert(undef)
...
llvm-svn: 27391
2006-04-04 01:02:22 +00:00
b710a81e54
The stack alignment is now computed dynamically, just verify it is correct.
...
llvm-svn: 27380
2006-04-03 21:39:57 +00:00
6bc4b9c7f8
Remove unused method
...
llvm-svn: 27379
2006-04-03 21:39:03 +00:00
e1e3adf802
Add a missing check, this fixes UnitTests/Vector/sumarray.c
...
llvm-svn: 27375
2006-04-03 17:29:28 +00:00
04c00fc844
Add a missing check, which broke a bunch of vector tests.
...
llvm-svn: 27374
2006-04-03 17:21:50 +00:00
94f012f606
back this out
...
llvm-svn: 27367
2006-04-03 03:16:50 +00:00
015eaf5f33
This should be a win of every arch
...
llvm-svn: 27364
2006-04-02 21:42:45 +00:00
4993249a04
Add a little dag combine to compile this:
...
int %AreSecondAndThirdElementsBothNegative(<4 x float>* %in) {
entry:
%tmp1 = load <4 x float>* %in ; <<4 x float>> [#uses=1]
%tmp = tail call int %llvm.ppc.altivec.vcmpgefp.p( int 1, <4 x float> < float 0x7FF8000000000000, float 0.000000e+00, float 0.000000e+00, float 0x7FF8000000000000 >, <4 x float> %tmp1 ) ; <int> [#uses=1]
%tmp = seteq int %tmp, 0 ; <bool> [#uses=1]
%tmp3 = cast bool %tmp to int ; <int> [#uses=1]
ret int %tmp3
}
into this:
_AreSecondAndThirdElementsBothNegative:
mfspr r2, 256
oris r4, r2, 49152
mtspr 256, r4
li r4, lo16(LCPI1_0)
lis r5, ha16(LCPI1_0)
lvx v0, 0, r3
lvx v1, r5, r4
vcmpgefp. v0, v1, v0
mfcr r3, 2
rlwinm r3, r3, 27, 31, 31
mtspr 256, r2
blr
instead of this:
_AreSecondAndThirdElementsBothNegative:
mfspr r2, 256
oris r4, r2, 49152
mtspr 256, r4
li r4, lo16(LCPI1_0)
lis r5, ha16(LCPI1_0)
lvx v0, 0, r3
lvx v1, r5, r4
vcmpgefp. v0, v1, v0
mfcr r3, 2
rlwinm r3, r3, 27, 31, 31
xori r3, r3, 1
cntlzw r3, r3
srwi r3, r3, 5
mtspr 256, r2
blr
llvm-svn: 27356
2006-04-02 06:11:11 +00:00
42a5fca47e
Implement promotion for EXTRACT_VECTOR_ELT, allowing v16i8 multiplies to work with PowerPC.
...
llvm-svn: 27349
2006-04-02 05:06:04 +00:00
87f080949b
Implement the Expand action for binary vector operations to break the binop
...
into elements and operate on each piece. This allows generic vector integer
multiplies to work on PPC, though the generated code is horrible.
llvm-svn: 27347
2006-04-02 03:57:31 +00:00
a9c59156be
Intrinsics that just load from memory can be treated like loads: they don't
...
have to serialize against each other. This allows us to schedule lvx's
across each other, for example.
llvm-svn: 27346
2006-04-02 03:41:14 +00:00
0442a18758
Constant fold all of the vector binops. This allows us to compile this:
...
"vector unsigned char mergeLowHigh = (vector unsigned char)
( 8, 9, 10, 11, 16, 17, 18, 19, 12, 13, 14, 15, 20, 21, 22, 23 );
vector unsigned char mergeHighLow = vec_xor( mergeLowHigh, vec_splat_u8(8));"
aka:
void %test2(<16 x sbyte>* %P) {
store <16 x sbyte> cast (<4 x int> xor (<4 x int> cast (<16 x ubyte> < ubyte 8, ubyte 9, ubyte 10, ubyte 11, ubyte 16, ubyte 17, ubyte 18, ubyte 19, ubyte 12, ubyte 13, ubyte 14, ubyte 15, ubyte 20, ubyte 21, ubyte 22, ubyte 23 > to <4 x int>), <4 x int> cast (<16 x sbyte> < sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8 > to <4 x int>)) to <16 x sbyte>), <16 x sbyte> * %P
ret void
}
into this:
_test2:
mfspr r2, 256
oris r4, r2, 32768
mtspr 256, r4
li r4, lo16(LCPI2_0)
lis r5, ha16(LCPI2_0)
lvx v0, r5, r4
stvx v0, 0, r3
mtspr 256, r2
blr
instead of this:
_test2:
mfspr r2, 256
oris r4, r2, 49152
mtspr 256, r4
li r4, lo16(LCPI2_0)
lis r5, ha16(LCPI2_0)
vspltisb v0, 8
lvx v1, r5, r4
vxor v0, v1, v0
stvx v0, 0, r3
mtspr 256, r2
blr
... which occurs here:
http://developer.apple.com/hardware/ve/calcspeed.html
llvm-svn: 27343
2006-04-02 03:25:57 +00:00
ef598059f2
Add a new -view-legalize-dags command line option
...
llvm-svn: 27342
2006-04-02 03:07:27 +00:00
e4e64b6b85
Implement constant folding of bit_convert of arbitrary constant vbuild_vector nodes.
...
llvm-svn: 27341
2006-04-02 02:53:43 +00:00
1c22728787
These entries already exist
...
llvm-svn: 27340
2006-04-02 02:51:27 +00:00
1985e1cbb8
Add some missing node names
...
llvm-svn: 27339
2006-04-02 02:41:18 +00:00
bec582f4cd
Prefer larger register classes over smaller ones when a register occurs in
...
multiple register classes. This fixes PowerPC/2006-04-01-FloatDoubleExtend.ll
llvm-svn: 27334
2006-04-02 00:24:45 +00:00
39dcf1a9e2
Delete identity shuffles, implementing CodeGen/Generic/vector-identity-shuffle.ll
...
llvm-svn: 27317
2006-03-31 22:16:43 +00:00
d9e4daabd2
Do not endian swap split vector loads. This fixes UnitTests/Vector/sumarray-dbl on PPC.
...
Now all UnitTests/Vector/* tests pass on PPC.
llvm-svn: 27299
2006-03-31 18:22:37 +00:00
8d90f526d7
Do not endian swap the operands to a store if the operands came from a vector.
...
This fixes UnitTests/Vector/simple.c with altivec.
llvm-svn: 27298
2006-03-31 18:20:46 +00:00
7e30af3887
Remove dead *extloads. This allows us to codegen vector.ll:test_extract_elt
...
to:
test_extract_elt:
alloc r3 = ar.pfs,0,1,0,0
adds r8 = 12, r32
;;
ldfs f8 = [r8]
mov ar.pfs = r3
br.ret.sptk.many rp
instead of:
test_extract_elt:
alloc r3 = ar.pfs,0,1,0,0
adds r8 = 28, r32
adds r9 = 24, r32
adds r10 = 20, r32
adds r11 = 16, r32
;;
ldfs f6 = [r8]
;;
ldfs f6 = [r9]
adds r8 = 12, r32
adds r9 = 8, r32
adds r14 = 4, r32
;;
ldfs f6 = [r10]
;;
ldfs f6 = [r11]
ldfs f8 = [r8]
;;
ldfs f6 = [r9]
;;
ldfs f6 = [r14]
;;
ldfs f6 = [r32]
mov ar.pfs = r3
br.ret.sptk.many rp
llvm-svn: 27297
2006-03-31 18:10:41 +00:00
2d8551c85b
Delete dead loads in the dag. This allows us to compile
...
vector.ll:test_extract_elt2 into:
_test_extract_elt2:
lfd f1, 32(r3)
blr
instead of:
_test_extract_elt2:
lfd f0, 56(r3)
lfd f0, 48(r3)
lfd f0, 40(r3)
lfd f1, 32(r3)
lfd f0, 24(r3)
lfd f0, 16(r3)
lfd f0, 8(r3)
lfd f0, 0(r3)
blr
llvm-svn: 27296
2006-03-31 18:06:18 +00:00
6f42325dca
Implement PromoteOp for VEXTRACT_VECTOR_ELT. Thsi fixes
...
Generic/vector.ll:test_extract_elt on non-sse X86 systems.
llvm-svn: 27294
2006-03-31 17:55:51 +00:00
8e1fcab2bc
Scalarized vector stores need not be legal, e.g. if the vector element type
...
needs to be promoted or expanded. Relegalize the scalar store once created.
This fixes CodeGen/Generic/vector.ll:test1 on non-SSE x86 targets.
llvm-svn: 27293
2006-03-31 17:37:22 +00:00
ba38035e21
Make sure to pass enough values to phi nodes when we are dealing with
...
decimated vectors. This fixes UnitTests/Vector/sumarray-dbl.c
llvm-svn: 27280
2006-03-31 02:12:18 +00:00
5fe1f54c17
Significantly improve handling of vectors that are live across basic blocks,
...
handling cases where the vector elements need promotion, expansion, and when
the vector type itself needs to be decimated.
llvm-svn: 27278
2006-03-31 02:06:56 +00:00
168e45b0b3
Expand INSERT_VECTOR_ELT to store vec, sp; store elt, sp+k; vec = load sp;
...
llvm-svn: 27274
2006-03-31 01:27:51 +00:00
67271869a8
Bug fixes: handle constantexpr insert/extract element operations
...
Handle constantpacked vectors with constantexpr elements.
This fixes CodeGen/Generic/vector-constantexpr.ll
llvm-svn: 27241
2006-03-29 00:11:43 +00:00
20e619fba3
When building a VVECTOR_SHUFFLE node from extract_element operations, make
...
sure to build it as SHUFFLE(X, undef, mask), not SHUFFLE(X, X, mask).
The later is not canonical form, and prevents the PPC splat pattern from
matching. For a particular splat, we go from generating this:
li r10, lo16(LCPI1_0)
lis r11, ha16(LCPI1_0)
lvx v3, r11, r10
vperm v3, v2, v2, v3
to generating:
vspltw v3, v2, 3
llvm-svn: 27236
2006-03-28 22:19:47 +00:00
a46dfe80c8
Canonicalize VECTOR_SHUFFLE(X, X, Y) -> VECTOR_SHUFFLE(X,undef,Y')
...
llvm-svn: 27235
2006-03-28 22:11:53 +00:00
c9992548fc
Turn a series of extract_element's feeding a build_vector into a
...
vector_shuffle node. For this:
void test(__m128 *res, __m128 *A, __m128 *B) {
*res = _mm_unpacklo_ps(*A, *B);
}
we now produce this code:
_test:
movl 8(%esp), %eax
movaps (%eax), %xmm0
movl 12(%esp), %eax
unpcklps (%eax), %xmm0
movl 4(%esp), %eax
movaps %xmm0, (%eax)
ret
instead of this:
_test:
subl $76, %esp
movl 88(%esp), %eax
movaps (%eax), %xmm0
movaps %xmm0, (%esp)
movaps %xmm0, 32(%esp)
movss 4(%esp), %xmm0
movss 32(%esp), %xmm1
unpcklps %xmm0, %xmm1
movl 84(%esp), %eax
movaps (%eax), %xmm0
movaps %xmm0, 16(%esp)
movaps %xmm0, 48(%esp)
movss 20(%esp), %xmm0
movss 48(%esp), %xmm2
unpcklps %xmm0, %xmm2
unpcklps %xmm1, %xmm2
movl 80(%esp), %eax
movaps %xmm2, (%eax)
addl $76, %esp
ret
GCC produces this (with -fomit-frame-pointer):
_test:
subl $12, %esp
movl 20(%esp), %eax
movaps (%eax), %xmm0
movl 24(%esp), %eax
unpcklps (%eax), %xmm0
movl 16(%esp), %eax
movaps %xmm0, (%eax)
addl $12, %esp
ret
llvm-svn: 27233
2006-03-28 20:28:38 +00:00
f6f94d3bce
Teach Legalize how to pack VVECTOR_SHUFFLE nodes into VECTOR_SHUFFLE nodes.
...
llvm-svn: 27232
2006-03-28 20:24:43 +00:00
8d57da2ffc
new node
...
llvm-svn: 27231
2006-03-28 19:54:42 +00:00
b7163598f9
Don't crash on X^X if X is a vector. Instead, produce a vector of zeros.
...
llvm-svn: 27229
2006-03-28 19:11:05 +00:00
ffec47ebff
Add an assertion
...
llvm-svn: 27228
2006-03-28 19:04:49 +00:00
dea0348853
Refactor address attributes. Add base register to frame info.
...
llvm-svn: 27226
2006-03-28 14:58:32 +00:00
67a636c587
More bulletproofing of llvm.dbg.declare.
...
llvm-svn: 27224
2006-03-28 13:45:20 +00:00
8374e9c4eb
More bulletproofing of DebugInfoDesc verify.
...
llvm-svn: 27203
2006-03-28 01:30:18 +00:00
e55d171ccd
Tblgen doesn't like multiple SDNode<> definitions that map to the sameenum value. Split them into separate enums.
...
llvm-svn: 27201
2006-03-28 00:40:33 +00:00
d387cc5cde
Reactivate llvm.dbg.declare.
...
llvm-svn: 27192
2006-03-27 23:31:10 +00:00
5bb1d90afd
Disable dbg_declare, it currently breaks the CFE build
...
llvm-svn: 27182
2006-03-27 21:36:03 +00:00
d5f94c9574
Fix legalization of intrinsics with chain and result values
...
llvm-svn: 27181
2006-03-27 20:28:29 +00:00
0e84f1e532
Unbreak the build on non-apple compilers :-(
...
llvm-svn: 27173
2006-03-27 16:10:59 +00:00
d09b05b0bc
Try again
...
llvm-svn: 27171
2006-03-27 08:10:26 +00:00
64efb35c32
Incorrect check for FP all one's
...
llvm-svn: 27169
2006-03-27 07:26:17 +00:00
c70e33cd6e
Change isBuildVectorAllOnesInteger to isBuildVectorAllOnes. Also check for
...
floating point cases.
llvm-svn: 27165
2006-03-27 06:58:47 +00:00
52fcad3a37
Instead of printing "INTRINSIC" on intrinsic node, print the intrinsic name.
...
llvm-svn: 27164
2006-03-27 06:45:25 +00:00
6e792f9ff8
Pass llvm/test/Regression/CodeGen/Generic/debug-info.ll.
...
llvm-svn: 27158
2006-03-27 01:51:47 +00:00
ed728c1291
SelectionDAGISel can now natively handle Switch instructions, in the same
...
manner that the LowerSwitch LLVM to LLVM pass does: emitting a binary
search tree of basic blocks. The new approach has several advantages:
it is faster, it generates significantly smaller code in many cases, and
it paves the way for implementing dense switch tables as a jump table by
handling switches directly in the instruction selector.
This functionality is currently only enabled on x86, but should be safe for
every target. In anticipation of making it the default, the cfg is now
properly updated in the x86, ppc, and sparc select lowering code.
llvm-svn: 27156
2006-03-27 01:32:24 +00:00
7092888bcc
Bullet proof against undefined args produced by upgrading ols-style debug info.
...
llvm-svn: 27155
2006-03-26 22:46:27 +00:00
84c2f0a705
How to be dumb on $5/day. Need a tri-state to track valid debug descriptors.
...
llvm-svn: 27154
2006-03-26 22:45:20 +00:00
a67899195f
Add ISD::isBuildVectorAllZeros predicate
...
llvm-svn: 27147
2006-03-26 09:50:58 +00:00
30ee72586d
Allow targets to custom lower their own intrinsics if desired.
...
llvm-svn: 27146
2006-03-26 09:12:51 +00:00
b6e2d0027a
Add some comments.
...
llvm-svn: 27133
2006-03-25 23:00:56 +00:00
f6e3b957b8
Fix a bug in ISD::isBuildVectorAllOnesInteger that caused it to always return
...
false
llvm-svn: 27131
2006-03-25 22:59:28 +00:00
c2d2811a07
Implement the ISD::isBuildVectorAllOnesInteger predicate
...
llvm-svn: 27130
2006-03-25 22:57:01 +00:00
dc1eab5886
Don't call SimplifyDemandedBits on vectors
...
llvm-svn: 27128
2006-03-25 22:19:00 +00:00
313229c74b
fix inverted conditional
...
llvm-svn: 27089
2006-03-24 22:49:42 +00:00
3324c7236f
Hack no more.
...
llvm-svn: 27079
2006-03-24 21:10:36 +00:00
68d9bf26c8
Only to vector shuffle for {x,x,y,y} cases when SCALAR_TO_VECTOR is free.
...
llvm-svn: 27071
2006-03-24 18:45:20 +00:00
53f1ecc560
Rename for truth in advertising.
...
llvm-svn: 27063
2006-03-24 09:50:27 +00:00
77e271cb4e
prefer to generate constant pool loads over splats. This prevents us from
...
using a splat for {1.0,1.0,1.0,1.0}
llvm-svn: 27055
2006-03-24 07:29:17 +00:00
87b1dddb1c
fix spello
...
llvm-svn: 27053
2006-03-24 07:15:07 +00:00
a4f6805a86
legalize vbit_convert nodes whose result is a legal type.
...
Legalize intrinsic nodes.
llvm-svn: 27036
2006-03-24 02:26:29 +00:00
d96b09a7b9
Lower target intrinsics into an INTRINSIC node
...
llvm-svn: 27035
2006-03-24 02:22:33 +00:00
6b05290922
fix some bogus assertions: noop bitconverts are legal
...
llvm-svn: 27032
2006-03-24 02:20:47 +00:00
1d2e995fc1
Lower BUILD_VECTOR to VECTOR_SHUFFLE if there are two distinct nodes (and if
...
the target can handle it). Issue two SCALAR_TO_VECTOR ops followed by a
VECTOR_SHUFFLE to select from the two vectors.
llvm-svn: 27023
2006-03-24 01:17:21 +00:00
ebac9a4adf
Identify the INTRINSIC node
...
llvm-svn: 27020
2006-03-24 01:04:30 +00:00
fb39d2a7f7
Unneeded forward.
...
llvm-svn: 27004
2006-03-23 23:05:52 +00:00
f7cfa52e7a
Make sure types are allocated in the scope of their use.
...
llvm-svn: 27002
2006-03-23 23:02:34 +00:00
d7c4e7d255
add support for splitting casts. This implements
...
CodeGen/Generic/vector.ll:test_cast_2.
llvm-svn: 26999
2006-03-23 21:16:34 +00:00
2b74656f25
Generate local variable and scope information and equivalent dwarf forms.
...
llvm-svn: 26989
2006-03-23 18:07:55 +00:00
a8bdac875d
Handle new forms of llvm.dbg intrinsics.
...
llvm-svn: 26988
2006-03-23 18:06:46 +00:00
9ea1b3f9fd
simplify some code
...
llvm-svn: 26972
2006-03-23 05:29:04 +00:00
b893d04a67
Fix a typo
...
llvm-svn: 26965
2006-03-22 22:20:49 +00:00
2f4119a608
Implement simple support for vector casting. This can currently only handle
...
casts between legal vector types.
llvm-svn: 26961
2006-03-22 20:09:35 +00:00
8fa445a89d
Endianness does not affect the order of vector fields. This fixes
...
SingleSource/UnitTests/Vector/build.c
llvm-svn: 26936
2006-03-22 01:46:54 +00:00
5be4352124
Enclose some variables in a scope to avoid error with some gcc versions
...
llvm-svn: 26934
2006-03-22 00:12:37 +00:00
340a6b5c26
add expand support for extractelement
...
llvm-svn: 26931
2006-03-21 21:02:03 +00:00
7c0cd8cafc
add some trivial support for extractelement.
...
llvm-svn: 26928
2006-03-21 20:44:12 +00:00
672a42d731
Add a hacky workaround for crashes due to vectors live across blocks.
...
Note that this code won't work for vectors that aren't legal on the
target. Improvements coming.
llvm-svn: 26925
2006-03-21 19:20:37 +00:00
21e68c8001
If a target supports splatting with SHUFFLE_VECTOR, lower to it from BUILD_VECTOR(x,x,x,x)
...
llvm-svn: 26885
2006-03-20 01:52:29 +00:00
6b20104410
TargetData doesn't know the alignment of vectors :(
...
llvm-svn: 26884
2006-03-20 01:51:46 +00:00
00f0589bc0
Add very basic support for VECTOR_SHUFFLE
...
llvm-svn: 26880
2006-03-19 23:56:04 +00:00
79fb91cc69
Allow SCALAR_TO_VECTOR to be custom lowered.
...
llvm-svn: 26867
2006-03-19 06:47:21 +00:00
9cdc5a0ce7
Add SCALAR_TO_VECTOR support
...
llvm-svn: 26866
2006-03-19 06:31:19 +00:00
eb5b2e705c
Don't bother storing undef elements of BUILD_VECTOR's
...
llvm-svn: 26858
2006-03-19 05:46:04 +00:00
5d3ff12c8f
Implement expand of BUILD_VECTOR containing variable elements.
...
This implements CodeGen/Generic/vector.ll:test_variable_buildvector
llvm-svn: 26852
2006-03-19 04:18:56 +00:00
5336a59e4b
fold insertelement(buildvector) -> buildvector if the inserted element # is
...
a constant. This implements test_constant_insert in CodeGen/Generic/vector.ll
llvm-svn: 26851
2006-03-19 01:27:56 +00:00
29b2301460
implement basic support for INSERT_VECTOR_ELT.
...
llvm-svn: 26849
2006-03-19 01:17:20 +00:00
f4e1a53647
Rename ConstantVec -> BUILD_VECTOR and VConstant -> VBUILD_VECTOR. Allow*BUILD_VECTOR to take variable inputs.
...
llvm-svn: 26847
2006-03-19 00:52:58 +00:00
c16b05e67d
implement vector.ll:test_undef
...
llvm-svn: 26845
2006-03-19 00:20:20 +00:00
93640543a9
Fix the remaining bugs in the vector expansion rework I commited yesterday.
...
This fixes CodeGen/Generic/vector.ll
llvm-svn: 26843
2006-03-19 00:07:49 +00:00
32206f54c6
Change the structure of lowering vector stuff. Note: This breaks some
...
things.
llvm-svn: 26840
2006-03-18 01:44:44 +00:00
98931bc381
add a couple enum values
...
llvm-svn: 26830
2006-03-17 19:53:59 +00:00
bb01d4f272
Remove BRTWOWAY*
...
Make the PPC backend not dependent on BRTWOWAY_CC and make the branch
selector smarter about the code it generates, fixing a case in the
readme.
llvm-svn: 26814
2006-03-17 01:40:33 +00:00
7ececaad83
Fix a problem fully scalarizing values.
...
llvm-svn: 26811
2006-03-16 23:05:19 +00:00
8471b15706
Add support for CopyFromReg from vector values. Note: this doesn't support
...
illegal vector types yet!
llvm-svn: 26799
2006-03-16 19:57:50 +00:00
49409cb925
Teach CreateRegForValue how to handle vector types.
...
llvm-svn: 26798
2006-03-16 19:51:18 +00:00
4024c00ce7
add support for vector->vector casts
...
llvm-svn: 26788
2006-03-15 22:19:46 +00:00
cad70c3e46
Add a note, this code should be moved to the dag combiner.
...
llvm-svn: 26787
2006-03-15 22:19:18 +00:00
71050ba709
Expand subprogram and added block descriptor.
...
llvm-svn: 26782
2006-03-15 19:09:58 +00:00
b8e155567a
1. Use null for serialized empty strings.
...
2. Allow for user defined debug descriptors.
3. Allow for user augmented fields on debug descriptors.
llvm-svn: 26760
2006-03-14 18:37:57 +00:00
68ac09d5cb
make sure dead token factor nodes are removed by the dag combiner.
...
llvm-svn: 26731
2006-03-13 18:37:30 +00:00
acb6e34277
Handle the removal of the debug chain.
...
llvm-svn: 26729
2006-03-13 13:07:37 +00:00
d8c2a48d58
Fold X+Y -> X|Y when safe. This implements:
...
Regression/CodeGen/PowerPC/and_add.ll
a case that occurs with dynamic allocas of constant size.
llvm-svn: 26727
2006-03-13 06:51:27 +00:00
8bb6cb7d7b
add a couple of missing folds
...
llvm-svn: 26724
2006-03-13 06:26:26 +00:00
994d8e6bd4
For targets with FABS/FNEG support, lower copysign to an integer load,
...
a select and FABS/FNEG.
This speeds up a trivial (aka stupid) copysign benchmark I wrote from 6.73s
to 2.64s, woo.
llvm-svn: 26723
2006-03-13 06:08:38 +00:00
a767dbf197
Don't advance the hazard recognizer when there are no hazards and no instructions
...
to be emitted.
Don't add one to the latency of a completed instruction if the latency of the
op is 0.
llvm-svn: 26718
2006-03-12 09:01:41 +00:00
86a9b60a25
Chain operands aren't real uses: they don't require the full latency of the
...
predecessor to finish before they can start.
llvm-svn: 26717
2006-03-12 03:52:09 +00:00
572003ca15
As a pending queue data structure to keep track of instructions whose
...
operands have all issued, but whose results are not yet available. This
allows us to compile:
int G;
int test(int A, int B, int* P) {
return (G+A)*(B+1);
}
to:
_test:
lis r2, ha16(L_G$non_lazy_ptr)
addi r4, r4, 1
lwz r2, lo16(L_G$non_lazy_ptr)(r2)
lwz r2, 0(r2)
add r2, r2, r3
mullw r3, r2, r4
blr
instead of this, which has a stall between the lis/lwz:
_test:
lis r2, ha16(L_G$non_lazy_ptr)
lwz r2, lo16(L_G$non_lazy_ptr)(r2)
addi r4, r4, 1
lwz r2, 0(r2)
add r2, r2, r3
mullw r3, r2, r4
blr
llvm-svn: 26716
2006-03-12 00:38:57 +00:00
356183d91e
rename priorityqueue -> availablequeue. When a node is scheduled, remember
...
which cycle it lands on.
llvm-svn: 26714
2006-03-11 22:44:37 +00:00
063086b0f4
Make CurrCycle a local var instead of an instance var
...
llvm-svn: 26713
2006-03-11 22:34:41 +00:00
9995a0c019
Move some methods around so that BU specific code is together, TD specific code
...
is together, and direction independent code is together.
llvm-svn: 26712
2006-03-11 22:28:35 +00:00
578d8fcb59
merge preds/chainpreds -> preds set
...
merge succs/chainsuccs -> succs set
This has no functionality change, simplifies the code, and reduces the size
of sunits.
llvm-svn: 26711
2006-03-11 22:24:20 +00:00
38280c0020
Added a parameter to control whether Constant::getStringValue() would chop
...
off the result string at the first null terminator.
llvm-svn: 26704
2006-03-10 23:52:03 +00:00
d3ef6c290a
scrape out bits of llvm-db
...
llvm-svn: 26701
2006-03-10 22:48:19 +00:00
f918e15362
Move simple-selector-specific types to the simple selector.
...
llvm-svn: 26693
2006-03-10 07:51:18 +00:00
5255d04357
Simplify the interface to the schedulers, to not pass the selected heuristicin.
...
llvm-svn: 26692
2006-03-10 07:49:12 +00:00
a5b93b8c6d
Move some simple-sched-specific instance vars to the simple scheduler.
...
llvm-svn: 26690
2006-03-10 07:42:02 +00:00
e015178de1
prune #includes
...
llvm-svn: 26689
2006-03-10 07:37:35 +00:00
4b70ff7876
move some simple scheduler methods into the simple scheduler
...
llvm-svn: 26688
2006-03-10 07:35:21 +00:00
dc2f135f5c
Make EmitNode take a SDNode instead of a NodeInfo*
...
llvm-svn: 26687
2006-03-10 07:28:36 +00:00
b9d8fa0342
Move the VRBase field from NodeInfo to being a separate, explicit, map.
...
llvm-svn: 26686
2006-03-10 07:25:12 +00:00
c48cfba44b
no need to build groups anymore
...
llvm-svn: 26684
2006-03-10 07:15:58 +00:00
6f82fe8106
Create SUnits directly from the SelectionDAG.
...
llvm-svn: 26683
2006-03-10 07:13:32 +00:00
2f8c7c3d55
Push PrepareNodeInfo/IdentifyGroups down the inheritance hierarchy
...
llvm-svn: 26682
2006-03-10 06:34:51 +00:00
349e9ddccc
Teach the latency scheduler some new tricks. In particular, to break ties,
...
keep track of a sense of "mobility", i.e. how many other nodes scheduling one
node will free up. For something like this:
float testadd(float *X, float *Y, float *Z, float *W, float *V) {
return (*X+*Y)*(*Z+*W)+*V;
}
For example, this makes us schedule *X then *Y, not *X then *Z. The former
allows us to issue the add, the later only lets us issue other loads.
This turns the above code from this:
_testadd:
lfs f0, 0(r3)
lfs f1, 0(r6)
lfs f2, 0(r4)
lfs f3, 0(r5)
fadds f0, f0, f2
fadds f1, f3, f1
lfs f2, 0(r7)
fmadds f1, f0, f1, f2
blr
into this:
_testadd:
lfs f0, 0(r6)
lfs f1, 0(r5)
fadds f0, f1, f0
lfs f1, 0(r4)
lfs f2, 0(r3)
fadds f1, f2, f1
lfs f2, 0(r7)
fmadds f1, f1, f0, f2
blr
llvm-svn: 26680
2006-03-10 05:51:05 +00:00
25e2556b71
add an aggregate method for reinserting scheduled nodes, add a callback for
...
priority impls that want to be notified when a node is scheduled
llvm-svn: 26678
2006-03-10 04:32:49 +00:00
6ce97687f7
Fix VC++ build breakage.
...
llvm-svn: 26676
2006-03-10 03:57:45 +00:00
213209a248
remove dbg_declare, it's not used yet.
...
llvm-svn: 26659
2006-03-09 20:02:42 +00:00
f0fc6bbaf3
back out my previous hack
...
llvm-svn: 26650
2006-03-09 17:48:46 +00:00
c6c9e65301
remove temporary option
...
llvm-svn: 26646
2006-03-09 17:31:22 +00:00
c44be2c4ef
temporary hack to get the build working again, apparently a header
...
commit was forgotten
llvm-svn: 26642
2006-03-09 17:11:08 +00:00
4b0e1d9e6c
Move bit field endianness to backend.
...
llvm-svn: 26639
2006-03-09 13:28:47 +00:00
d17d77aa1d
yes yes, enabled debug output is bad
...
llvm-svn: 26637
2006-03-09 07:39:25 +00:00
6398c13128
switch the t-d scheduler to use a really dumb and trivial critical path
...
latency priority function.
llvm-svn: 26636
2006-03-09 07:38:27 +00:00
d4130375c0
Pull latency information for target instructions out of the latency tables. :)
...
Only enable this with -use-sched-latencies, I'll enable it by default with a
clean nightly tester run tonight.
PPC is the only target that provides latency info currently.
llvm-svn: 26634
2006-03-09 07:15:18 +00:00
da6aafeef4
don't copy all itinerary data
...
llvm-svn: 26633
2006-03-09 07:13:00 +00:00
399bee27f0
PriorityQueue is an instance var, use it.
...
llvm-svn: 26632
2006-03-09 06:48:37 +00:00
9e95accf4e
add some comments
...
llvm-svn: 26631
2006-03-09 06:37:29 +00:00
9df647539d
Refactor the priority mechanism one step further: now that it is a separate
...
class, sever its implementation from the interface. Now we can provide new
implementations of the same interface (priority computation) without touching
the scheduler itself.
llvm-svn: 26630
2006-03-09 06:35:14 +00:00
2698f0de7a
Get rid of the multiple copies of getStringValue. Now a Constant:: method.
...
llvm-svn: 26616
2006-03-08 18:11:07 +00:00
fd22d42945
Split the priority function computation and priority queue management out
...
of the ScheduleDAGList class into a new SchedulingPriorityQueue class.
llvm-svn: 26613
2006-03-08 05:18:27 +00:00
42e2026cb0
switch from an explicitly managed list of SUnits to a simple vector of sunits
...
llvm-svn: 26612
2006-03-08 04:54:34 +00:00
12c6d89204
Shrinkify some fields, fit to 80 columns
...
llvm-svn: 26611
2006-03-08 04:41:06 +00:00
3fe975b846
revert the previous patch, didn't mean to check it in yet
...
llvm-svn: 26610
2006-03-08 04:39:05 +00:00
af5e26c980
remove "Slot", it is dead
...
llvm-svn: 26609
2006-03-08 04:37:58 +00:00
543832d39d
Change the interface for getting a target HazardRecognizer to be more clean.
...
llvm-svn: 26608
2006-03-08 04:25:59 +00:00
2370265550
libstdc++-v3 was failing to build. Needed to handle composite types with empty
...
members (running into a zero initializer.)
llvm-svn: 26607
2006-03-08 02:07:02 +00:00
313570fb17
Use "llvm.metadata" section for debug globals. Filter out these globals in the
...
asm printer.
llvm-svn: 26599
2006-03-07 22:00:35 +00:00
69effa2325
Switch to using a numeric id for anchors.
...
llvm-svn: 26598
2006-03-07 20:53:47 +00:00
3bad199894
Bitfield support.
...
llvm-svn: 26593
2006-03-07 15:51:33 +00:00
0c801bd1cf
Fix some formatting, when looking for hazards, prefer target nodes over
...
things like copyfromreg.
llvm-svn: 26586
2006-03-07 05:40:43 +00:00
01aa752a36
update file comment
...
llvm-svn: 26573
2006-03-06 17:58:04 +00:00
a00c61932d
Remove some code that doesn't make sense
...
llvm-svn: 26572
2006-03-06 07:31:44 +00:00
c5c0658aa6
Remove SUnit::Priority1: it is re-calculated on demand as number of live
...
range to be generated.
llvm-svn: 26570
2006-03-06 06:08:54 +00:00
47639dbb93
Hoist the HazardRecognizer out of the ScheduleDAGList.cpp file to where
...
targets can implement them. Make the top-down scheduler non-g5-specific.
Remove the old testing hazard recognizer.
llvm-svn: 26569
2006-03-06 00:22:00 +00:00
00b52ea8f9
Comment fixes
...
llvm-svn: 26567
2006-03-05 23:59:20 +00:00
80268aaeed
Don't depend on the C99 copysign function, implement it ourselves.
...
llvm-svn: 26566
2006-03-05 23:57:58 +00:00
2d945ba4c7
When a hazard recognizer needs noops to be inserted, do so. This represents
...
noops as null pointers in the instruction sequence.
llvm-svn: 26564
2006-03-05 23:51:47 +00:00
fa5e1c9c26
Implement G5HazardRecognizer as a trivial thing that wants 5 cycles between
...
copyfromreg nodes. Clearly useful!
llvm-svn: 26559
2006-03-05 23:13:56 +00:00
e50c092b7c
Add basic hazard recognizer support. noop insertion isn't complete yet though.
...
llvm-svn: 26558
2006-03-05 22:45:01 +00:00
55e2aac24b
Fix VC++ compilation error.
...
llvm-svn: 26554
2006-03-05 21:43:37 +00:00
98ecb8ec61
Split the list scheduler into top-down and bottom-up pieces. The priority
...
function of the top-down scheduler are completely bogus currently, and
having (future) PPC specific in this file is also wrong, but this is a
small incremental step.
llvm-svn: 26552
2006-03-05 21:10:33 +00:00
7a36d97518
Move the available queue to being inside the ListSchedule method, since it
...
bounds its lifetime.
llvm-svn: 26550
2006-03-05 20:21:55 +00:00
bdaf4f38b5
Reinstate this now that the offending opposite xform has been removed.
...
llvm-svn: 26548
2006-03-05 19:53:55 +00:00
c610e62e46
print arbitrary constant pool entries
...
llvm-svn: 26545
2006-03-05 09:38:03 +00:00
d428e22c07
Back out fold (shl (add x, c1), c2) -> (add (shl x, c2), c1<<c2) for now.
...
It's causing an infinite loop compiling ldecod on x86 / Darwin.
llvm-svn: 26544
2006-03-05 07:30:16 +00:00
3bc4050217
Add some simple copysign folds
...
llvm-svn: 26543
2006-03-05 05:30:57 +00:00
5c1ba2ac08
Codegen copysign[f] into a FCOPYSIGN node
...
llvm-svn: 26542
2006-03-05 05:09:38 +00:00
f29f5204cc
fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
...
fold (shl (add x, c1), c2) -> (add (shl x, c2), c1<<c2)
This allows us to compile CodeGen/PowerPC/addi-reassoc.ll into:
_test1:
slwi r2, r4, 4
add r2, r2, r3
lwz r3, 36(r2)
blr
_test2:
mulli r2, r4, 5
add r2, r2, r3
lbz r2, 11(r2)
extsb r3, r2
blr
instead of:
_test1:
addi r2, r4, 2
slwi r2, r2, 4
add r2, r3, r2
lwz r3, 4(r2)
blr
_test2:
addi r2, r4, 2
mulli r2, r2, 5
add r2, r3, r2
lbz r2, 1(r2)
extsb r3, r2
blr
llvm-svn: 26535
2006-03-04 23:33:26 +00:00
c44f05d624
Added support for dwarf block data entries.
...
llvm-svn: 26509
2006-03-03 21:00:14 +00:00
88f0fe15a2
Adding basic structure support.
...
llvm-svn: 26505
2006-03-03 15:06:57 +00:00
3bf916ddd9
Add more vector NodeTypes: VSDIV, VUDIV, VAND, VOR, and VXOR.
...
llvm-svn: 26504
2006-03-03 07:01:07 +00:00
23e75f5b49
SDOperand::isOperand should not be a forwarding. It must check *this against N's operands.
...
llvm-svn: 26502
2006-03-03 06:42:32 +00:00
6b08ae8497
Added isOperand(N): true if this is an operand of N
...
llvm-svn: 26501
2006-03-03 06:24:54 +00:00
5e9a695026
A bit more tweaking
...
llvm-svn: 26500
2006-03-03 06:23:43 +00:00
55c1173a6c
Fix VC++ compilation errors.
...
llvm-svn: 26498
2006-03-03 03:25:07 +00:00
993e9cf26e
Move #include "llvm/CodeGen/AsmPrinter.h" to top since it's the interface.
...
llvm-svn: 26493
2006-03-03 02:04:29 +00:00
ad3c974a77
remove the read/write port/io intrinsics.
...
llvm-svn: 26479
2006-03-03 00:19:58 +00:00
093c159efb
Split memcpy/memset/memmove intrinsics into i32/i64 versions, resolving
...
PR709, and paving the way for future progress.
llvm-svn: 26476
2006-03-03 00:00:25 +00:00
4e3904f637
- Fixed some priority calculation bugs that were causing bug 478. Among them:
...
a predecessor appearing more than once in the operand list was counted as
multiple predecessor; priority1 should be updated during scheduling;
CycleBound was updated after the node is inserted into priority queue; one
of the tie breaking condition was flipped.
- Take into consideration of two address opcodes. If a predecessor is a def&use
operand, it should have a higher priority.
- Scheduler should also favor floaters, i.e. nodes that do not have real
predecessors such as MOV32ri.
- The scheduling fixes / tweaks fixed bug 478:
.text
.align 4
.globl _f
_f:
movl 4(%esp), %eax
movl 8(%esp), %ecx
movl %eax, %edx
imull %ecx, %edx
imull %eax, %eax
imull %ecx, %ecx
addl %eax, %ecx
leal (%ecx,%edx,2), %eax
ret
It is also a slight performance win (1% - 3%) for most tests.
llvm-svn: 26470
2006-03-02 21:38:29 +00:00
862001ad75
Support for enumerations.
...
llvm-svn: 26466
2006-03-01 23:52:37 +00:00
38d5e768b2
Don't print llvm constant in assmebly file. Assembler won't like comments that
...
span multiple lines.
llvm-svn: 26463
2006-03-01 22:18:09 +00:00
0db2f2c689
Fix CodeGen/Generic/2006-03-01-dagcombineinfloop.ll, an infinite loop
...
in the dag combiner on 176.gcc on x86.
llvm-svn: 26459
2006-03-01 21:47:21 +00:00
4e71db13d6
Switch back to using actual dwarf tags. Simplifies code without loss to other
...
debug forms.
llvm-svn: 26455
2006-03-01 20:39:36 +00:00
232024edb8
Fix a typo evan noticed
...
llvm-svn: 26454
2006-03-01 19:55:35 +00:00
f770cf5b90
Use context and not compile unit.
...
llvm-svn: 26453
2006-03-01 18:20:30 +00:00
1246d5c054
I guess I can handle large type sizes.
...
llvm-svn: 26452
2006-03-01 18:13:05 +00:00
b9ac4cba66
Basic array support.
...
llvm-svn: 26451
2006-03-01 17:53:02 +00:00
bc1c85beea
Add support for target-specific dag combines
...
llvm-svn: 26443
2006-03-01 04:53:38 +00:00
fbcd62d3bb
Add a new AddToWorkList method, start using it
...
llvm-svn: 26441
2006-03-01 04:03:14 +00:00
324871ef1a
Pull shifts by a constant through multiplies (a form of reassociation),
...
implementing Regression/CodeGen/X86/mul-shift-reassoc.ll
llvm-svn: 26440
2006-03-01 03:44:24 +00:00
b97aab4371
Vector ops lowering.
...
llvm-svn: 26436
2006-03-01 01:09:54 +00:00
be85e89ec4
- Added VConstant as an abstract version of ConstantVec.
...
- All abstrct vector nodes must have # of elements and element type as their
first two operands.
llvm-svn: 26432
2006-03-01 00:51:13 +00:00
716edb9754
Add const, volatile, restrict support.
...
Add array of debug descriptor support.
llvm-svn: 26428
2006-02-28 20:15:07 +00:00
f0032b350c
Compile:
...
unsigned foo4(unsigned short *P) { return *P & 255; }
unsigned foo5(short *P) { return *P & 255; }
to:
_foo4:
lbz r3,1(r3)
blr
_foo5:
lbz r3,1(r3)
blr
not:
_foo4:
lhz r2, 0(r3)
rlwinm r3, r2, 0, 24, 31
blr
_foo5:
lhz r2, 0(r3)
rlwinm r3, r2, 0, 24, 31
blr
llvm-svn: 26419
2006-02-28 06:49:37 +00:00
bdbc4476d9
Fold "and (LOAD P), 255" -> zextload. This allows us to compile:
...
unsigned foo3(unsigned *P) { return *P & 255; }
as:
_foo3:
lbz r3, 3(r3)
blr
instead of:
_foo3:
lwz r2, 0(r3)
rlwinm r3, r2, 0, 24, 31
blr
and:
unsigned short foo2(float a) { return a; }
as:
_foo2:
fctiwz f0, f1
stfd f0, -8(r1)
lhz r3, -2(r1)
blr
instead of:
_foo2:
fctiwz f0, f1
stfd f0, -8(r1)
lwz r2, -4(r1)
rlwinm r3, r2, 0, 16, 31
blr
llvm-svn: 26417
2006-02-28 06:35:35 +00:00
0f8a727c49
fold (sra (sra x, c1), c2) -> (sra x, c1+c2)
...
llvm-svn: 26416
2006-02-28 06:23:04 +00:00
9fed5b6122
Add support for output memory constraints.
...
llvm-svn: 26410
2006-02-27 23:45:39 +00:00
6d5c2a0156
Qualify dwarf namespace inside llvm namespace.
...
llvm-svn: 26409
2006-02-27 22:37:23 +00:00
bc7a3832e8
Partial enabling of functions.
...
llvm-svn: 26404
2006-02-27 20:37:42 +00:00
72b66d6d8a
Supporting multiple compile units.
...
llvm-svn: 26402
2006-02-27 17:27:12 +00:00
22e47b9f4e
Re-orging file.
...
llvm-svn: 26401
2006-02-27 12:43:29 +00:00
47ee42829d
remove some completed notes
...
llvm-svn: 26390
2006-02-27 00:39:31 +00:00
9f9662b86e
Print ConstantPoolSDNode offset field.
...
llvm-svn: 26381
2006-02-26 08:36:57 +00:00
ed169db8a5
Added an offset field to ConstantPoolSDNode.
...
llvm-svn: 26371
2006-02-25 09:54:52 +00:00
7d01f95a57
Fix a bug that Evan exposed with some changes he's making, and that was
...
exposed with a fastcc problem (breaking pcompress2 on x86 with -enable-x86-fastcc).
When reloading a reused reg, make sure to invalidate the reloaded reg, and
check to see if there are any other pending uses of the same register.
llvm-svn: 26369
2006-02-25 02:17:31 +00:00
28a0b8bec7
Remove debugging printout :)
...
Add a minor compile time win, no codegen change.
llvm-svn: 26368
2006-02-25 02:03:40 +00:00
525522e429
Refactor some code from being inline to being out in a new class with methods.
...
This gets rid of two gotos, which is always nice, and also adds some comments.
No functionality change, this is just a refactor.
llvm-svn: 26367
2006-02-25 01:51:33 +00:00
1d08c6534c
Use the PrintAsmMemoryOperand to print addressing modes.
...
llvm-svn: 26364
2006-02-24 20:21:58 +00:00
5af3fdec12
Pass all the flags to the asm printer, not just the # operands.
...
llvm-svn: 26362
2006-02-24 19:50:58 +00:00
2f8a794b13
rename NumOps -> NumVals to avoid shadowing a NumOps var in an outer scope.
...
Add support for addressing modes.
llvm-svn: 26361
2006-02-24 19:18:20 +00:00
86c51000db
Refactor operand adding out to a new AddOperand method
...
llvm-svn: 26358
2006-02-24 18:54:03 +00:00
723d3e0746
Add pointer and reference types. Added short-term code to ignore NULL types
...
(to allow llvm-gcc4 to build.)
llvm-svn: 26355
2006-02-24 16:46:40 +00:00
83c22e0d75
Get VC++ building again.
...
llvm-svn: 26351
2006-02-24 02:52:40 +00:00
dcf785bf46
Implement (most of) selection of inline asm memory operands.
...
llvm-svn: 26350
2006-02-24 02:13:54 +00:00
7ef7a64ebb
Lower C_Memory operands.
...
llvm-svn: 26346
2006-02-24 01:11:24 +00:00
e5386d4d98
Added basic support for typedefs.
...
llvm-svn: 26339
2006-02-23 22:37:30 +00:00
e7c0ffb3a0
Fix an endianness problem on big-endian targets with expanded operands
...
to inline asms. Mark some methods const.
llvm-svn: 26334
2006-02-23 20:06:57 +00:00
571d9647c6
Record all of the expanded registers in the DAG and machine instr, fixing
...
several bugs in inline asm expanded operands.
llvm-svn: 26332
2006-02-23 19:21:04 +00:00
69b9e26186
DwarfWriter reading basic type information from llvm-gcc4 code.
...
llvm-svn: 26331
2006-02-23 16:58:18 +00:00
2988921dc4
Code cleanups, no functionality change
...
llvm-svn: 26328
2006-02-23 06:44:17 +00:00
b1124f3c76
This fixes a couple of problems with expansion
...
llvm-svn: 26318
2006-02-22 23:09:03 +00:00
6f87d18be9
Change a whole bunch of code to be built around RegsForValue instead of
...
a single register number. This fully implements promotion for inline asms,
expand is close but not quite right yet.
llvm-svn: 26316
2006-02-22 22:37:12 +00:00
2fa33a989d
Coordinate activities with llvm-gcc4 and dwarf.
...
llvm-svn: 26314
2006-02-22 19:02:11 +00:00
7ad77dfc2a
split register class handling from explicit physreg handling.
...
llvm-svn: 26308
2006-02-22 00:56:39 +00:00
5c79f98f15
Adjust to changes in getRegForInlineAsmConstraint prototype
...
llvm-svn: 26306
2006-02-21 23:12:12 +00:00
43070b7541
Added x86 integer vector types: 64-bit packed byte integer (v16i8), 64-bit
...
packed word integer (v8i16), and 64-bit packed doubleword integer (v2i32).
llvm-svn: 26294
2006-02-20 22:34:53 +00:00
301f45cf6f
Fix a problem Nate and Duraid reported where simplifying nodes can cause
...
them to get ressurected, in which case, deleting the undead nodes is
unfriendly.
llvm-svn: 26291
2006-02-20 06:51:04 +00:00
486d1bc5ed
Fix a problem on itanium with memset. The value to set has been promoted to
...
i64 before this code, so zero_ext doesn't work.
llvm-svn: 26290
2006-02-20 06:38:35 +00:00
abac61603f
Add checks to make sure we don't create bogus extend nodes, and fix a bug
...
where we were doing exactly that which was causing failures on x86 and
alpha.
llvm-svn: 26284
2006-02-18 02:40:58 +00:00
375e1a71cc
Fix a tricky issue in the SimplifyDemandedBits code where CombineTo wasn't
...
exactly the API we wanted to call into. This fixes the crash on crafty last
night.
llvm-svn: 26269
2006-02-17 21:58:01 +00:00
fb5dbadf15
Clean up DemandedBitsAreZero interface
...
Make more use of the new mask helpers in valuetypes.h
Combine (sra (srl x, c1), c1) -> sext_inreg if legal
llvm-svn: 26263
2006-02-17 19:54:08 +00:00
57b3567552
Don't expand sdiv by power of two before legalize, since it will likely
...
generate illegal nodes.
llvm-svn: 26261
2006-02-17 07:26:20 +00:00
5965bd19f8
kill ADD_PARTS & SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBC
...
and SUBE nodes that actually expose what's going on and allow for
significant simplifications in the targets.
llvm-svn: 26255
2006-02-17 05:43:56 +00:00
9ec392b2aa
Fix another miscompilation exposed by lencode, where we lowered i64->f32
...
conversions to __floatdidf instead of __floatdisf on targets that support
f32 but not i64 (e.g. sparc).
llvm-svn: 26254
2006-02-17 04:32:33 +00:00
c3dcf5a4d7
Dumb bug. Code sees a memcpy from X+c so it increments src offset. But it
...
turns out not to point to a constant string but it forgot change the offset
back.
llvm-svn: 26242
2006-02-16 23:11:42 +00:00
8a77efe4f7
Rework the SelectionDAG-based implementations of SimplifyDemandedBits
...
and ComputeMaskedBits to match the new improved versions in instcombine.
Tested against all of multisource/benchmarks on ppc.
llvm-svn: 26238
2006-02-16 21:11:51 +00:00
42c01c8d39
If the false case is the current basic block, then this is a self loop.
...
We do not want to emit "Loop: ... brcond Out; br Loop", as it adds an extra
instruction in the loop. Instead, invert the condition and emit
"Loop: ... br!cond Loop; br Out.
Generalize the fix by moving it from PPCDAGToDAGISel to SelectionDAGLowering.
llvm-svn: 26231
2006-02-16 08:27:56 +00:00
471627c49d
Lowering of sdiv X, pow2 was broken, this fixes it. This patch is written
...
by Nate, I'm just committing it for him.
llvm-svn: 26230
2006-02-16 08:02:36 +00:00
93e4865d4b
Remove an unused function parameter.
...
llvm-svn: 26221
2006-02-15 22:12:35 +00:00
6781b6e62e
Turn a memcpy from string constant into a series of stores of constant values.
...
llvm-svn: 26219
2006-02-15 21:59:04 +00:00
2eea436192
Should not combine ISD::LOCATIONs until we have scheme to remove from
...
MachineDebugInfo tables.
llvm-svn: 26216
2006-02-15 19:34:44 +00:00
e2038bdeee
Lower memcpy with small constant size operand into a series of load / store
...
ops.
llvm-svn: 26195
2006-02-15 01:54:51 +00:00
0451499b3c
Doh again!
...
llvm-svn: 26188
2006-02-14 23:05:54 +00:00
ebb50a61d2
Using wrong DW_FORM.
...
llvm-svn: 26184
2006-02-14 22:01:57 +00:00
db2a7a736a
Keep to < 80 cols
...
llvm-svn: 26177
2006-02-14 20:12:38 +00:00
038521ef76
Missed a break so memcpy cases fell through to memset. Doh.
...
llvm-svn: 26176
2006-02-14 19:45:56 +00:00
d502610604
Fixed a build breakage.
...
llvm-svn: 26175
2006-02-14 09:11:59 +00:00
4b40a42653
Rename maxStoresPerMemSet to maxStoresPerMemset, etc.
...
llvm-svn: 26174
2006-02-14 08:38:30 +00:00
81fcea8aa2
Expand memset dst, c, size to a series of stores if size falls below the
...
target specific theshold, e.g. 16 for x86.
llvm-svn: 26171
2006-02-14 08:22:34 +00:00
1784a9d267
now that libcalls don't suck, we can remove this hack
...
llvm-svn: 26164
2006-02-14 05:39:35 +00:00
8e2ee7358f
Fix a latent bug in the call sequence handling stuff. Some targets (e.g. x86)
...
create these nodes with flag results. Remember that we legalized them.
llvm-svn: 26156
2006-02-14 00:55:02 +00:00
390c63e9d9
Rename to better reflect usage (current and planned.)
...
llvm-svn: 26145
2006-02-13 12:50:39 +00:00
462505fc5f
Completely rewrite libcall insertion by the legalizer, providing the
...
following handy-dandy properties:
1. it is always correct now
2. it is much faster than before
3. it is easier to understand
This implementation builds off of the recent simplifications of the
legalizer that made it single-pass instead of iterative.
This fixes JM/lencod, JM/ldecod, and
CodeGen/Generic/2006-02-12-InsertLibcall.ll (at least on PPC).
llvm-svn: 26144
2006-02-13 09:18:02 +00:00
5995d0160c
Reorg for integration with gcc4. Old style debug info will not be passed though
...
to SelIDAG.
llvm-svn: 26115
2006-02-11 01:01:30 +00:00
a1ef3ec5b5
Added SelectionDAG::InsertISelMapEntry(). This is used to workaround the gcc
...
problem where it inline the map insertion call too aggressively. Before this
change it was producing a frame size of 24k for Select_store(), now it's down
to 10k (by calling this method rather than calling the map insertion operator).
llvm-svn: 26094
2006-02-09 22:11:03 +00:00
d3f1db93c1
More changes to reduce frame size.
...
Move all getTargetNode() out of SelectionDAG.h into SelectionDAG.cpp. This
prevents them from being inlined.
Change getTargetNode() so they return SDNode * instead of SDOperand to prevent
copying. It should also help compilation speed.
llvm-svn: 26083
2006-02-09 07:15:23 +00:00
f6190821da
Adjust to MachineConstantPool interface change: instead of keeping a
...
value/alignment pair for each constant, keep a value/offset pair.
llvm-svn: 26078
2006-02-09 04:46:04 +00:00
ba97264e72
rename fields of constant pool entries
...
llvm-svn: 26076
2006-02-09 04:22:52 +00:00
47f7319f00
Simplify code, alignment must be specified now.
...
llvm-svn: 26074
2006-02-09 02:26:04 +00:00
4576bb74d5
Make MachineConstantPool entries alignments explicit
...
llvm-svn: 26071
2006-02-09 02:23:13 +00:00
ed87dcd45f
Add support for assembler directives that wrap inline asm
...
llvm-svn: 26065
2006-02-08 23:41:56 +00:00
a10e23c19f
Compile this:
...
xori r6, r2, 1
rlwinm r6, r6, 0, 31, 31
cmpwi cr0, r6, 0
bne cr0, LBB1_3 ; endif
to this:
rlwinm r6, r2, 0, 31, 31
cmpwi cr0, r6, 0
beq cr0, LBB1_3 ; endif
llvm-svn: 26047
2006-02-08 02:13:15 +00:00
34f74c180a
Add support for modifier characters to operand printers
...
llvm-svn: 26021
2006-02-06 22:17:23 +00:00
0458fb76fd
Goodbye nasty macro.
...
llvm-svn: 26019
2006-02-06 21:54:05 +00:00
b643ff5546
Edit requests from Sabre.
...
llvm-svn: 26018
2006-02-06 19:12:02 +00:00
85263234a8
Changing model for the construction of debug information.
...
llvm-svn: 26016
2006-02-06 15:33:21 +00:00
8c9cd461df
Back out previous commit, it isn't safe.
...
llvm-svn: 26006
2006-02-05 08:23:00 +00:00
3dc8b89493
fold c1 << (x + c2) into (c1 << c2) << x. fix a warning.
...
llvm-svn: 26005
2006-02-05 08:07:24 +00:00
c89fdf1eb3
Handle urem by shifted powers of 2.
...
llvm-svn: 26001
2006-02-05 07:36:48 +00:00
25d178bece
handle combining A / (B << N) into A >>u (log2(B)+N) when B is a power of 2
...
llvm-svn: 26000
2006-02-05 07:20:23 +00:00
d37645c07d
* Added SDNode::isOnlyUse().
...
* Fix hasNUsesOfValue(), it should be const.
llvm-svn: 25990
2006-02-05 06:29:23 +00:00
cbab28414e
make sure that global doubles are aligned to 8 bytes
...
llvm-svn: 25981
2006-02-05 01:46:49 +00:00
a9b2525d3e
Implement the AsmPrinter::getPreferredAlignmentLog method.
...
llvm-svn: 25978
2006-02-05 01:29:18 +00:00
95ae171d5b
Fix VC++ warning.
...
llvm-svn: 25975
2006-02-04 16:20:31 +00:00
f9adce90bf
Get rid of some memory leaks identified by Valgrind
...
llvm-svn: 25960
2006-02-04 06:49:00 +00:00
57a004abfe
Fix VC++ warning.
...
llvm-svn: 25957
2006-02-04 03:27:39 +00:00
3b48431333
Add initial support for immediates. This allows us to compile this:
...
int %rlwnm(int %A, int %B) {
%C = call int asm "rlwnm $0, $1, $2, $3, $4", "=r,r,r,n,n"(int %A, int %B, int 4, int 17)
ret int %C
}
into:
_rlwnm:
or r2, r3, r3
or r3, r4, r4
rlwnm r2, r2, r3, 4, 17 ;; note the immediates :)
or r3, r2, r2
blr
llvm-svn: 25955
2006-02-04 02:26:14 +00:00
65ad53feb3
Initial early support for non-register operands, like immediates
...
llvm-svn: 25952
2006-02-04 02:16:44 +00:00
c93403a7fb
Handle another case exposed on X86.
...
llvm-svn: 25949
2006-02-03 23:50:46 +00:00
71d20c4e18
Fix a nasty problem on two-address machines in the following situation:
...
store EAX -> [ss#0]
[ss#0] += 1
...
use(EAX)
In this case, it is not valid to rewrite this as:
store EAX -> [ss#0]
EAX += 1
store EAX -> [ss#0] ;;; this would also delete the store above
...
use(EAX)
... because EAX is not a dead at that point. Keep track of which registers
we are allowed to clobber, and which ones we aren't, and don't clobber the
ones we're not supposed to. :)
This should resolve the issues on X86 last night.
llvm-svn: 25948
2006-02-03 23:28:46 +00:00
507a3a7bd1
significantly simplify the VirtRegMap code by pulling the SpillSlotsAvailable
...
and PhysRegsAvailable maps out into a new AvailableSpills struct. No
functionality change.
This paves the way for a bugfix, coming up next.
llvm-svn: 25947
2006-02-03 23:13:58 +00:00
dc7bba9ffe
Add a framework for eliminating instructions that produces undemanded bits.
...
llvm-svn: 25945
2006-02-03 22:24:05 +00:00
f68fd20286
remove some #ifdef'd out code, which should properly be in the dag combiner anyway.
...
llvm-svn: 25941
2006-02-03 20:13:59 +00:00
6091407783
remove dead fn
...
llvm-svn: 25935
2006-02-03 06:51:34 +00:00
22e251abf1
Add common code for reassociating ops in the dag combiner
...
llvm-svn: 25934
2006-02-03 06:46:56 +00:00
3276ff7ac6
Fix VC++ compilation error caused by using a std::map iterator variable to receive
...
a std::multimap iterator value. For some reason, GCC doesn't have a problem with this.
llvm-svn: 25927
2006-02-03 03:48:54 +00:00
e18ef0d4a6
Remove move copies and dead stuff by not clobbering the result reg of a noop copy.
...
llvm-svn: 25926
2006-02-03 03:16:14 +00:00
774d4a190b
Simplify some code
...
llvm-svn: 25924
2006-02-03 03:06:49 +00:00
1ef239afb4
Add code that checks for noop copies, which triggers when either:
...
1. a target doesn't know how to fold load/stores into copies, or
2. the spiller rewrites the input to a copy to the same register as the dest
instead of to the reloaded reg.
This will be moved/improved in the near future, but allows elimination of
some ancient x86 hacks. This eliminates 92 copies from SMG2000 on X86 and
163 copies from 252.eon.
llvm-svn: 25922
2006-02-03 02:02:59 +00:00
02b5b9cdd6
Added case HANDLENODE to getOperationName().
...
llvm-svn: 25920
2006-02-03 01:33:01 +00:00
b7f24de4c8
Physregs may hold multiple stack slot values at the same time. Keep track
...
of this, and use it to our advantage (bwahahah). This allows us to eliminate another
60 instructions from smg2000 on PPC (probably significantly more on X86). A common
old-new diff looks like this:
stw r2, 3304(r1)
- lwz r2, 3192(r1)
stw r2, 3300(r1)
- lwz r2, 3192(r1)
stw r2, 3296(r1)
- lwz r2, 3192(r1)
stw r2, 3200(r1)
- lwz r2, 3192(r1)
stw r2, 3196(r1)
- lwz r2, 3192(r1)
+ or r2, r2, r2
stw r2, 3188(r1)
and
- lwz r31, 604(r1)
- lwz r13, 604(r1)
- lwz r14, 604(r1)
- lwz r15, 604(r1)
- lwz r16, 604(r1)
- lwz r30, 604(r1)
+ or r31, r30, r30
+ or r13, r30, r30
+ or r14, r30, r30
+ or r15, r30, r30
+ or r16, r30, r30
+ or r30, r30, r30
Removal of the R = R copies is coming next...
llvm-svn: 25919
2006-02-03 00:36:31 +00:00
f3aef1b004
Fix a deficiency in the spiller that Evan noticed. In particular, consider
...
this code:
store [stack slot #0 ], R10
= add R14, [stack slot #0 ]
The spiller didn't know that the store made the value of [stackslot#0] available
in R10 *IF* the store came from a copy instruction with the store folded into it.
This patch teaches VirtRegMap to look at these stores and recognize the values
they make available. In one case Evan provided, this code:
divsd %XMM0, %XMM1
movsd %XMM1, QWORD PTR [%ESP + 40]
1) movsd QWORD PTR [%ESP + 48], %XMM1
2) movsd %XMM1, QWORD PTR [%ESP + 48]
addsd %XMM1, %XMM0
3) movsd QWORD PTR [%ESP + 48], %XMM1
movsd QWORD PTR [%ESP + 4], %XMM0
turns into:
divsd %XMM0, %XMM1
movsd %XMM1, QWORD PTR [%ESP + 40]
addsd %XMM1, %XMM0
3) movsd QWORD PTR [%ESP + 48], %XMM1
movsd QWORD PTR [%ESP + 4], %XMM0
In this case, instruction #2 was removed because of the value made
available by #1 , and inst #1 was later deleted because it is now
never used before the stack slot is redefined by #3 .
This occurs here and there in a lot of code with high spilling, on PPC
most of the removed loads/stores are LSU-reject-causing loads, which is
nice.
On X86, things are much better (because it spills more), where we nuke
about 1% of the instructions from SMG2000 and several hundred from eon.
More improvements to come...
llvm-svn: 25917
2006-02-02 23:29:36 +00:00
bb53acd03c
Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far more logical place. Other methods should also be moved if anyoneis interested. :)
...
llvm-svn: 25913
2006-02-02 20:12:32 +00:00
49beaf40fc
Turn any_extend nodes into zero_extend nodes when it allows us to remove an
...
and instruction. This allows us to compile stuff like this:
bool %X(int %X) {
%Y = add int %X, 14
%Z = setne int %Y, 12345
ret bool %Z
}
to this:
_X:
cmpl $12331, 4(%esp)
setne %al
movzbl %al, %eax
ret
instead of this:
_X:
cmpl $12331, 4(%esp)
setne %al
movzbl %al, %eax
andl $1, %eax
ret
This occurs quite a bit with the X86 backend. For example, 25 times in
lambda, 30 times in 177.mesa, 14 times in galgel, 70 times in fma3d,
25 times in vpr, several hundred times in gcc, ~45 times in crafty,
~60 times in parser, ~140 times in eon, 110 times in perlbmk, 55 on gap,
16 times on bzip2, 14 times on twolf, and 1-2 times in many other SPEC2K
programs.
llvm-svn: 25901
2006-02-02 07:17:31 +00:00
49ce35542f
add two dag combines:
...
(C1-X) == C2 --> X == C1-C2
(X+C1) == C2 --> X == C2-C1
This allows us to compile this:
bool %X(int %X) {
%Y = add int %X, 14
%Z = setne int %Y, 12345
ret bool %Z
}
into this:
_X:
cmpl $12331, 4(%esp)
setne %al
movzbl %al, %eax
andl $1, %eax
ret
not this:
_X:
movl $14, %eax
addl 4(%esp), %eax
cmpl $12345, %eax
setne %al
movzbl %al, %eax
andl $1, %eax
ret
Testcase here: Regression/CodeGen/X86/compare-add.ll
nukage of the and coming up next.
llvm-svn: 25898
2006-02-02 06:36:13 +00:00
0bd74558ae
make -debug output less newliney
...
llvm-svn: 25895
2006-02-02 00:38:08 +00:00
7f5880b1c7
Implement matching constraints. We can now say things like this:
...
%C = call int asm "xyz $0, $1, $2, $3", "=r,r,r,0"(int %A, int %B, int 4)
and get:
xyz r2, r3, r4, r2
note that the r2's are pinned together. Yaay for 2-address instructions.
2342 ----------------------------------------------------------------------
llvm-svn: 25893
2006-02-02 00:25:23 +00:00
aa23fa9f43
Implement smart printing of inline asm strings, handling variants and
...
substituted operands. For this testcase:
int %test(int %A, int %B) {
%C = call int asm "xyz $0, $1, $2", "=r,r,r"(int %A, int %B)
ret int %C
}
we now emit:
_test:
or r2, r3, r3
or r3, r4, r4
xyz r2, r2, r3 ;; look here
or r3, r2, r2
blr
... note the substituted operands. :)
llvm-svn: 25886
2006-02-01 22:41:11 +00:00
01bd9d9911
*** empty log message ***
...
llvm-svn: 25879
2006-02-01 19:05:15 +00:00
1558fc64f9
Implement simple register assignment for inline asms. This allows us to compile:
...
int %test(int %A, int %B) {
%C = call int asm "xyz $0, $1, $2", "=r,r,r"(int %A, int %B)
ret int %C
}
into:
(0x8906130, LLVM BB @0x8902220):
%r2 = OR4 %r3, %r3
%r3 = OR4 %r4, %r4
INLINEASM <es:xyz $0, $1, $2>, %r2<def>, %r2, %r3
%r3 = OR4 %r2, %r2
BLR
which asmprints as:
_test:
or r2, r3, r3
or r3, r4, r4
xyz $0, $1, $2 ;; need to print the operands now :)
or r3, r2, r2
blr
llvm-svn: 25878
2006-02-01 18:59:47 +00:00
7e7f439f85
Fix some of the stuff in the PPC README file, and clean up legalization
...
of the SELECT_CC, BR_CC, and BRTWOWAY_CC nodes.
llvm-svn: 25875
2006-02-01 07:19:44 +00:00
3a5ed55187
adjust to changes in InlineAsm interface. Fix a few minor bugs.
...
llvm-svn: 25865
2006-02-01 01:28:23 +00:00
32be2dc0af
Allow the specification of explicit alignments for constant pool entries.
...
llvm-svn: 25855
2006-01-31 22:23:14 +00:00
2443ab932d
Allow custom lowering of fabs. I forgot to check in this change which
...
caused several test failures.
llvm-svn: 25852
2006-01-31 18:14:25 +00:00
e9721b2984
Only insert an AND when converting from BR_COND to BRCC if needed.
...
llvm-svn: 25832
2006-01-31 05:04:52 +00:00
2e56e89452
Handle physreg input/outputs. We now compile this:
...
int %test_cpuid(int %op) {
%B = alloca int
%C = alloca int
%D = alloca int
%A = call int asm "cpuid", "=eax,==ebx,==ecx,==edx,eax"(int* %B, int* %C, int* %D, int %op)
%Bv = load int* %B
%Cv = load int* %C
%Dv = load int* %D
%x = add int %A, %Bv
%y = add int %x, %Cv
%z = add int %y, %Dv
ret int %z
}
to this:
_test_cpuid:
sub %ESP, 16
mov DWORD PTR [%ESP], %EBX
mov %EAX, DWORD PTR [%ESP + 20]
cpuid
mov DWORD PTR [%ESP + 8], %ECX
mov DWORD PTR [%ESP + 12], %EBX
mov DWORD PTR [%ESP + 4], %EDX
mov %ECX, DWORD PTR [%ESP + 12]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 8]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 4]
add %EAX, %ECX
mov %EBX, DWORD PTR [%ESP]
add %ESP, 16
ret
... note the proper register allocation. :)
it is unclear to me why the loads aren't folded into the adds.
llvm-svn: 25827
2006-01-31 02:03:41 +00:00
57ecb561c6
Print the most trivial inline asms.
...
llvm-svn: 25822
2006-01-30 23:00:08 +00:00
f263a23735
Fix a bug in my legalizer reworking that caused the X86 backend to not get
...
a chance to custom legalize setcc, which broke a bunch of C++ Codes.
Testcase here: CodeGen/X86/2006-01-30-LongSetcc.ll
llvm-svn: 25821
2006-01-30 22:43:50 +00:00
d6f5ae4455
don't insert an and node if it isn't needed here, this can prevent folding
...
of lowered target nodes.
llvm-svn: 25804
2006-01-30 04:22:28 +00:00
f0b24d2dc0
Move MaskedValueIsZero from the DAGCombiner to the TargetLowering interface,making isMaskedValueZeroForTargetNode simpler, and useable from other partsof the compiler.
...
llvm-svn: 25803
2006-01-30 04:09:27 +00:00
3b40e64aa3
pass the address of MaskedValueIsZero into isMaskedValueZeroForTargetNode,
...
to permit recursion
llvm-svn: 25799
2006-01-30 03:49:37 +00:00
4d1ea71a31
Fix RET of promoted values on targets that custom expand RET to a target node.
...
llvm-svn: 25794
2006-01-29 21:02:23 +00:00
2c748afd6c
cleanups to the ValueTypeActions interface
...
llvm-svn: 25785
2006-01-29 08:42:06 +00:00
ccb4476c87
Remove some special case hacks for CALLSEQ_*, using UpdateNodeOperands
...
instead.
llvm-svn: 25780
2006-01-29 07:58:15 +00:00
2f292789dc
Allow custom expansion of ConstantVec nodes. PPC will use this in the future.
...
llvm-svn: 25774
2006-01-29 06:34:16 +00:00
758b0ac54b
Legalize ConstantFP into TargetConstantFP when the target allows. Implement
...
custom expansion of ConstantFP nodes.
llvm-svn: 25772
2006-01-29 06:26:56 +00:00
678da98835
eliminate uses of SelectionDAG::getBR2Way_CC
...
llvm-svn: 25767
2006-01-29 06:00:45 +00:00
d02b05473c
Use the new "UpdateNodeOperands" method to simplify LegalizeDAG and make it
...
faster. This cuts about 120 lines of code out of the legalizer (mostly code
checking to see if operands have changed).
It also fixes an ugly performance issue, where the legalizer cloned the entire
graph after any change. Now the "UpdateNodeOperands" method gives it a chance
to reuse nodes if the operands of a node change but not its opcode or valuetypes.
This speeds up instruction selection time on kimwitu++ by about 8.2% with a
release build.
llvm-svn: 25746
2006-01-28 10:58:55 +00:00
580b12ad34
add another method variant
...
llvm-svn: 25744
2006-01-28 10:09:25 +00:00
f34156e8cb
add some methods for updating nodes
...
llvm-svn: 25742
2006-01-28 09:32:45 +00:00
eb63751499
minor tweaks
...
llvm-svn: 25740
2006-01-28 08:31:04 +00:00
689bdcc9cf
move a bunch of code, no other change.
...
llvm-svn: 25739
2006-01-28 08:25:58 +00:00
fcfda5a174
remove a couple more now-extraneous legalizeop's
...
llvm-svn: 25738
2006-01-28 08:22:56 +00:00
364b89a784
fix a bug
...
llvm-svn: 25737
2006-01-28 07:42:08 +00:00
9dcce6da8e
Several major changes:
...
1. Pull out the expand cases for BSWAP and CT* into a separate function,
reducing the size of LegalizeOp.
2. Fix a bug where expand(bswap i64) was wrong when i64 is legal.
3. Changed LegalizeOp/PromoteOp so that the legalizer never needs to be
iterative. It now operates in a single pass over the nodes.
4. Simplify a LOT of code, with a net reduction of ~280 lines.
llvm-svn: 25736
2006-01-28 07:39:30 +00:00
fd4a7f76a9
Eliminate the need for ExpandOp to set 'needsanotheriteration', as it already
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relegalizes the stuff it returns.
Add the ability to custom expand ADD/SUB, so that targets don't need to deal
with ADD_PARTS/SUB_PARTS if they don't want.
Fix some obscure potential bugs and simplify code.
llvm-svn: 25732
2006-01-28 05:07:51 +00:00
10f677508f
Instead of making callers of ExpandLibCall legalize the result, make
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ExpandLibCall do it itself.
llvm-svn: 25731
2006-01-28 04:28:26 +00:00
a593acfe66
Eliminate the need to do another iteration of the legalizer after inserting
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a libcall.
llvm-svn: 25730
2006-01-28 04:23:12 +00:00
98ed05c81d
remove method I just added
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llvm-svn: 25728
2006-01-28 03:43:09 +00:00
43b867dd3b
add a new callback
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llvm-svn: 25727
2006-01-28 03:37:03 +00:00
595ec734fc
Implement Promote for VAARG, and allow it to be custom promoted for people
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who don't want the default behavior (Alpha).
llvm-svn: 25726
2006-01-28 03:14:31 +00:00
af397cec0b
Add a missing case to the dag combiner.
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llvm-svn: 25723
2006-01-28 01:06:30 +00:00
fb16a62fba
Remove the ISD::CALL and ISD::TAILCALL nodes
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llvm-svn: 25721
2006-01-28 00:18:58 +00:00
8c47c3a3b1
Remove TLI.LowerReturnTo, and just let targets custom lower ISD::RET for
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the same functionality. This addresses another piece of bug 680. Next,
on to fixing Alpha VAARG, which I broke last time.
llvm-svn: 25696
2006-01-27 21:09:22 +00:00
0cda006a69
Using bit size of integers instead of ambiguous "long" et all.
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llvm-svn: 25694
2006-01-27 20:31:25 +00:00
4a84e97421
Sorry - really folowing convention.
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llvm-svn: 25691
2006-01-27 18:32:41 +00:00
116bb15473
Following convention.
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llvm-svn: 25689
2006-01-27 18:28:31 +00:00
fc3eca9023
fix build
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llvm-svn: 25687
2006-01-27 18:16:17 +00:00
ecd7e61a1f
Fix build error that is apparently only a warning with some compilers.
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llvm-svn: 25686
2006-01-27 17:31:30 +00:00
2b6efa9d41
Forgot the version number.
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llvm-svn: 25685
2006-01-27 15:46:54 +00:00
f98fc8441c
Improve visibility/correctness of operand indices in "llvm.db" objects.
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Handle 64 in DIEs.
llvm-svn: 25684
2006-01-27 15:20:54 +00:00
061d9e2cf0
Stub out a method
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llvm-svn: 25676
2006-01-27 02:10:10 +00:00
4df279cfda
Teach the scheduler to emit the appropriate INLINEASM MachineInstr for an
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ISD::INLINEASM node.
llvm-svn: 25668
2006-01-26 23:28:04 +00:00
476e67be14
initial selectiondag support for new INLINEASM node. Note that inline asms
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with outputs or inputs are not supported yet. :)
llvm-svn: 25664
2006-01-26 22:24:51 +00:00
0689dfad23
Use global information to fill out Dwarf compile units.
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llvm-svn: 25662
2006-01-26 21:22:49 +00:00
0bbdc55333
Set up MachineDebugInfo to scan for debug information form "llvm.db"g globals.
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Global Variable information is now pulled from "llvm.dbg.globals"
llvm-svn: 25655
2006-01-26 20:21:46 +00:00
c4c339c3d0
Clean up some code; improve efficiency; and fixed a potential bug involving
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chain successors.
llvm-svn: 25630
2006-01-26 00:30:29 +00:00
5edde66863
Don't break the optimized build (by incorrect placement of #endif)
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llvm-svn: 25613
2006-01-25 21:49:13 +00:00
1880f8db02
No need to keep track of top and bottom nodes in a group since the vector is
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already in order. Thanks Jim for pointing it out.
llvm-svn: 25608
2006-01-25 18:54:24 +00:00
e74795cd70
First part of bug 680:
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Remove TLI.LowerVA* and replace it with SDNodes that are lowered the same
way as everything else.
llvm-svn: 25606
2006-01-25 18:21:52 +00:00
c3cafb8a67
Make it even more portable.
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llvm-svn: 25605
2006-01-25 17:18:50 +00:00
fb20616aa6
Fix VC++ compilation error.
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llvm-svn: 25604
2006-01-25 17:17:49 +00:00
ab49556cf4
Bottom up register usage reducing list scheduler.
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llvm-svn: 25601
2006-01-25 09:14:32 +00:00
fbc88a624a
Keep track of bottom / top element of a set of flagged nodes.
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llvm-svn: 25600
2006-01-25 09:13:41 +00:00
a6eff8a432
If scheduler choice is the default (-sched=default), use target scheduling
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preference to determine which scheduler to use. SchedulingForLatency ==
Breadth first; SchedulingForRegPressure == bottom up register reduction list
scheduler.
llvm-svn: 25599
2006-01-25 09:12:57 +00:00
a292744ecc
Portably cast a pointer to an integer.
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llvm-svn: 25594
2006-01-25 02:40:10 +00:00
1dbc389ad2
fix build on 64 bit hosts
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llvm-svn: 25591
2006-01-24 21:26:43 +00:00
f9a1e3aadc
Fix an infinite loop I caused by making sure to legalize the flag operand
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of CALLSEQ_* nodes
llvm-svn: 25582
2006-01-24 05:48:21 +00:00
12f8441c03
Fix VC++ compilation error.
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llvm-svn: 25577
2006-01-24 04:43:17 +00:00
b56a80061a
Remove unused variables.
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llvm-svn: 25576
2006-01-24 04:42:53 +00:00
00fcdfef0d
rename method
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llvm-svn: 25572
2006-01-24 04:16:34 +00:00
3e65f28ffe
Crude Dwarf global variable debugging.
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llvm-svn: 25569
2006-01-24 00:49:18 +00:00
e3a79268a2
Print file-scope inline asm blocks at the start of the output file.
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llvm-svn: 25565
2006-01-23 23:47:53 +00:00
683352382e
another couple selects
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llvm-svn: 25551
2006-01-23 21:51:14 +00:00
c28563874c
another selectto
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llvm-svn: 25548
2006-01-23 20:59:12 +00:00
b8566fa10a
Typo.
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llvm-svn: 25545
2006-01-23 13:34:04 +00:00
31272347d4
Skeleton of the list schedule.
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llvm-svn: 25544
2006-01-23 08:26:10 +00:00
421cfe8006
Minor clean up.
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llvm-svn: 25543
2006-01-23 08:25:34 +00:00
763dfd7723
Fix Regression/CodeGen/SparcV8/2006-01-22-BitConvertLegalize.ll by making
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sure that the result of expanding a BIT_CONVERT node is itself legalized.
llvm-svn: 25538
2006-01-23 07:30:46 +00:00
87063b9986
Remove a couple of unnecessary #include's
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llvm-svn: 25535
2006-01-23 07:21:01 +00:00
c1e1d9724d
Factor out more instruction scheduler code to the base class.
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llvm-svn: 25532
2006-01-23 07:01:07 +00:00
deda32a786
Fix bugs lowering stackrestore, fixing 2004-08-12-InlinerAndAllocas.c on
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PPC.
llvm-svn: 25522
2006-01-23 05:22:07 +00:00
de02d7727f
Add explicit #includes of <iostream>
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llvm-svn: 25515
2006-01-22 23:41:00 +00:00
e23928c67f
Fix a bug in a recent refactor that caused a bunch of programs to miscompile
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or the compiler to crash.
llvm-svn: 25503
2006-01-21 19:12:11 +00:00
44cab00045
Fix CodeGen/PowerPC/2006-01-20-ShiftPartsCrash.ll
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llvm-svn: 25496
2006-01-21 04:27:00 +00:00
739a6a456e
Do some code refactoring on Jim's scheduler in preparation of the new list
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scheduler.
llvm-svn: 25493
2006-01-21 02:32:06 +00:00
3d8f3a55b7
Simplify search for abbreviations.
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llvm-svn: 25491
2006-01-21 01:13:18 +00:00
45900baadb
Correct some simple errors.
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llvm-svn: 25490
2006-01-21 00:59:54 +00:00
b17434dc1d
Right size integer values before emitting.
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llvm-svn: 25489
2006-01-20 21:02:36 +00:00
7a3e9aa282
Reworked how Dwarf debug info entries and abbreviations are handled. Added
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pubnames and debuy str sections.
llvm-svn: 25487
2006-01-20 20:34:06 +00:00
15afe462a8
remove some unintentionally committed code
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llvm-svn: 25483
2006-01-20 18:40:10 +00:00
222ceabbee
If the target doesn't support f32 natively, insert the FP_EXTEND in target-indep
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code, so that the LowerReturn code doesn't have to handle it.
llvm-svn: 25482
2006-01-20 18:38:32 +00:00
13e8c9d6de
Another typo
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llvm-svn: 25440
2006-01-19 04:54:52 +00:00
7599b6e4af
was ignoring the legalized chain in this case, fixed SPASS on alpha
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llvm-svn: 25428
2006-01-18 23:19:08 +00:00
569c439567
Get rid of code in the DAGCombiner that is duplicated in SelectionDAG.cpp
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Now all constant folding in the code generator is in one place.
llvm-svn: 25426
2006-01-18 22:35:16 +00:00
e2ee190821
Temporary work around for a libcall insertion bug: If a target doesn't
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support FSIN/FCOS nodes, do not lower sin/cos to them.
llvm-svn: 25425
2006-01-18 21:50:14 +00:00
5fee908be5
Fix a backwards conditional that caused an inf loop in some cases. This
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fixes: test/Regression/CodeGen/Generic/2005-01-18-SetUO-InfLoop.ll
llvm-svn: 25419
2006-01-18 19:13:41 +00:00
194a5268cb
Added minimum Dwarf aranges. Cleaned up some section headers. Line number
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support now works in gdb.
llvm-svn: 25417
2006-01-18 16:54:26 +00:00
cc9dfecf81
Add frame work for additional dwarf sections. Comments will improve as code
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is added.
llvm-svn: 25410
2006-01-17 20:41:40 +00:00
03e95af9f7
Support for the insertelement operation.
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llvm-svn: 25405
2006-01-17 20:06:42 +00:00
6f86a7db07
Bug fix: missing LegalizeOp() on newly created nodes.
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llvm-svn: 25401
2006-01-17 19:47:13 +00:00
b9966029fe
Adding basic support for Dwarf line number debug information.
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I promise to keep future commits smaller.
llvm-svn: 25396
2006-01-17 17:31:53 +00:00
b4f9a6f110
For PR411:
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This patch is an incremental step towards supporting a flat symbol table.
It de-overloads the intrinsic functions by providing type-specific intrinsics
and arranging for automatically upgrading from the old overloaded name to
the new non-overloaded name. Specifically:
llvm.isunordered -> llvm.isunordered.f32, llvm.isunordered.f64
llvm.sqrt -> llvm.sqrt.f32, llvm.sqrt.f64
llvm.ctpop -> llvm.ctpop.i8, llvm.ctpop.i16, llvm.ctpop.i32, llvm.ctpop.i64
llvm.ctlz -> llvm.ctlz.i8, llvm.ctlz.i16, llvm.ctlz.i32, llvm.ctlz.i64
llvm.cttz -> llvm.cttz.i8, llvm.cttz.i16, llvm.cttz.i32, llvm.cttz.i64
New code should not use the overloaded intrinsic names. Warnings will be
emitted if they are used.
llvm-svn: 25366
2006-01-16 21:12:35 +00:00
1e1eb5ee6c
Constant fold ctpop/ctlz/cttz, and a couple other small cleanups
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llvm-svn: 25357
2006-01-16 08:07:10 +00:00
2642a35f4c
Expand case for 64b Legalize, even though no one should end up using this
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(itanium supports bswap natively, alpha should custom lower it using the
VAX floating point swapload, ha ha).
llvm-svn: 25356
2006-01-16 07:59:13 +00:00
7d831fa5b9
Add BSWAP stuff to intrinsic lowering for CBE & friends.
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llvm-svn: 25355
2006-01-16 07:57:00 +00:00
fcdb420baf
Disable two transformations that contribute to bus errors on SparcV8.
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llvm-svn: 25339
2006-01-15 18:58:59 +00:00
59b82f9848
Allow the target to specify 'expand' if they just require the amount to
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be subtracted from the stack pointer.
llvm-svn: 25331
2006-01-15 08:54:32 +00:00
2d59142613
Fix custom lowering of dynamic_stackalloc
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llvm-svn: 25329
2006-01-15 08:43:08 +00:00
Chris Lattner