2753955fc0
Change CALLSEQ_BEGIN and CALLSEQ_END to take TargetConstant's as
...
parameters instead of raw Constants. This prevents the constants from
being selected by the isel pass, fixing PR2735.
llvm-svn: 57385
2008-10-11 22:08:30 +00:00
fb1f4a1329
simplify comparison
...
llvm-svn: 57371
2008-10-11 00:08:02 +00:00
4f2791617e
Remove some overzealous checks that were rejecting
...
valid comments in inline assembly.
gcc.target/i386/20011009-1.c
llvm-svn: 57365
2008-10-10 21:04:42 +00:00
dfcc1ff8f8
Added missing print functions that take a raw_ostream
...
llvm-svn: 57339
2008-10-10 01:43:55 +00:00
4f0bd68cfe
Add a "loses information" return value to APFloat::convert
...
and APFloat::convertToInteger. Restore return value to
IEEE754. Adjust all users accordingly.
llvm-svn: 57329
2008-10-09 23:00:39 +00:00
54306fe499
Rename APFloat::convertToAPInt to bitcastToAPInt to
...
make it clearer what the function does. No functional
change.
llvm-svn: 57325
2008-10-09 18:53:47 +00:00
d796164e89
Align EH tables before label is emitted, not after,
...
thus aligning the label.
llvm-svn: 57310
2008-10-08 21:50:21 +00:00
bfe12ee668
Fix the case where an instruction is not properly marked as using all registers that alias its inputs.
...
llvm-svn: 57286
2008-10-08 04:30:51 +00:00
60ad173dfe
Remove -disable-fast-isel. Use cl::boolOrDefault with -fast-isel
...
instead.
So now: -fast-isel or -fast-isel=true enable fast-isel, and
-fast-isel=false disables it. Fast-isel is also on by default
with -fast, and off by default otherwise.
llvm-svn: 57270
2008-10-07 23:00:56 +00:00
c1d47c56f9
Avoid emitting redundant materializations of integer constants
...
for things like null pointers, which at this level aren't
different from regular integer constants.
llvm-svn: 57265
2008-10-07 22:03:27 +00:00
1d338fc6a4
Add an option to enable StrongPHIElimination, for ease of testing.
...
llvm-svn: 57259
2008-10-07 20:22:28 +00:00
21dca9cbb1
Use Dan's supperior check
...
llvm-svn: 57255
2008-10-07 18:27:23 +00:00
d69bdaef64
No need for |=
...
llvm-svn: 57249
2008-10-07 17:11:29 +00:00
6d409f08be
Use ADDC if it is valid at any smaller size. Do it right this time
...
llvm-svn: 57248
2008-10-07 17:09:16 +00:00
6606f17e50
Use ADDC if it is valid at any smaller size. fixes test/Codegen/Generic/i128-addsub.ll on x86
...
llvm-svn: 57247
2008-10-07 17:03:15 +00:00
3a9be150be
Expand arith on machines without carry flags
...
llvm-svn: 57243
2008-10-07 14:15:42 +00:00
bef9b0bef0
Correctly handle calls with no return values. This fixes
...
2006-01-23-UnionInit on x86-64 when inlining is not enabled.
llvm-svn: 57223
2008-10-07 00:12:37 +00:00
dfe979bcb0
Don't dereference the end() iterator. Thanks to
...
ENABLE_EXPENSIVE_CHECKS for finding this.
llvm-svn: 57181
2008-10-06 18:00:07 +00:00
ab379c905b
Remove unncessary isDeclaration() checks.
...
llvm-svn: 57179
2008-10-06 17:30:07 +00:00
7875876e46
reorder #include order, patch by Kenneth Boyd!
...
llvm-svn: 57148
2008-10-06 03:54:25 +00:00
0c41861f39
Add #include to get alloca, patch by Kenneth Boyd!
...
llvm-svn: 57147
2008-10-06 03:53:16 +00:00
2416896b3c
wrap some long lines and expand i32 mul's to libcalls, inspired by a
...
patch by Mikael Lepisto!
llvm-svn: 57077
2008-10-04 21:27:46 +00:00
b5abd78ab5
CMake: Reflected changes on source file structure. New plugin support
...
for llvmc2 incomplete.
llvm-svn: 57076
2008-10-04 21:18:50 +00:00
68fec886ed
Fix compilation error on MSVC.
...
llvm-svn: 57046
2008-10-04 08:11:49 +00:00
13b048268b
Fix fast-isel's handling of atomic instructions. They may
...
expand to multiple basic blocks, in which case fast-isel
needs to informed of which block to use as it resumes
inserting instructions.
llvm-svn: 57040
2008-10-04 00:56:36 +00:00
78bb44fcd4
Fix a bug in the local allocator's liveness computation where it
...
was setting kill flags on tied uses in two-address instructions.
The kill flags were causing the allocator to think it could
allocate the use and its tied def in different registers.
llvm-svn: 57039
2008-10-04 00:31:14 +00:00
5d60c1ebb1
Pass MemOperand through for 64-bit atomics on 32-bit,
...
incidentally making the case where the memop is a
pointer deref work. Fix cmp-and-swap regression.
llvm-svn: 57027
2008-10-03 19:41:08 +00:00
b62cd7ea98
Use -1ULL instead of uint64_t(-1), at Anton's suggestion.
...
llvm-svn: 57021
2008-10-03 17:56:45 +00:00
8428cfc93b
Fix typos pointed out by Duncan. Also untabify these files.
...
llvm-svn: 57018
2008-10-03 17:11:58 +00:00
0d1e9a8e04
Switch the MachineOperand accessors back to the short names like
...
isReg, etc., from isRegister, etc.
llvm-svn: 57006
2008-10-03 15:45:36 +00:00
6e42742d2d
The result of getSetCCResultType (eg: i32) may be larger
...
than the type an i1 is promoted to (eg: i8). Account
for this. Noticed by Tilmann Scheller on CellSPU; he
will hopefully take care of fixing this in LegalizeDAG
and adding a testcase!
llvm-svn: 56997
2008-10-03 07:41:46 +00:00
4e072a75cc
Implement fast-isel support for zero-extending from i1.
...
It turns out that this is a fairly common operation,
and it's easy enough to handle.
llvm-svn: 56990
2008-10-03 01:28:47 +00:00
1ab1d31f7a
Optimize conditional branches in X86FastISel. This replaces
...
sequences like this:
sete %al
testb %al, %al
jne LBB11_1
with this:
je LBB11_1
llvm-svn: 56969
2008-10-02 22:15:21 +00:00
a78bae34a5
Add a new MachineBasicBlock utility function, isLayoutSuccessor, that
...
can be used when deciding if a block can transfer control to another
via a fall-through instead of a branch.
llvm-svn: 56968
2008-10-02 22:09:09 +00:00
72a9e7367c
fix build gcc 4.3
...
llvm-svn: 56965
2008-10-02 20:15:08 +00:00
c5b45fec6b
Use a multimap rather than a map for holding the list of copies to insert, so we don't lose copies when two of them have
...
the same source. I don't know what I was thinking when I wrote this originally.
Note: There's probably a more efficient way to do this, but I need to think about it some more, and about what determinism
guarantees need to be present.
llvm-svn: 56964
2008-10-02 19:40:33 +00:00
867d549fce
Handle some 64-bit atomics on x86-32, some of the time.
...
llvm-svn: 56963
2008-10-02 18:53:47 +00:00
b25f4637dd
A Partitioned Boolean Quadratic Programming (PBQP) based register allocator.
...
Contributed by Lang Hames.
llvm-svn: 56959
2008-10-02 18:29:27 +00:00
88536398ff
Fix a think-o in isSafeToMove. This fixes it from thinking that
...
volatile memory references are safe to move.
llvm-svn: 56948
2008-10-02 15:04:30 +00:00
1b76f2c40b
Remove OptimizeForSize global. Use function attribute optsize.
...
llvm-svn: 56937
2008-10-01 23:18:38 +00:00
3b88f10f46
Enable FastISel by default (on x86 and x86-64) with the -fast option.
...
llvm-svn: 56930
2008-10-01 20:39:19 +00:00
1dd27578dd
Make some implicit conversions explicit, to avoid compiler warnings.
...
llvm-svn: 56927
2008-10-01 19:58:59 +00:00
94798d31dd
Fold trivial two-operand tokenfactors where the operands are equal
...
immediately.
llvm-svn: 56921
2008-10-01 15:11:19 +00:00
3a293e7404
Fix typos in comments.
...
llvm-svn: 56919
2008-10-01 15:07:49 +00:00
68f12ee567
Implement the -fno-builtin option in the front-end, not in the back-end.
...
llvm-svn: 56900
2008-10-01 00:59:58 +00:00
15e6be8cc5
Mark merged-in VNInfo's as being PHIKilled.
...
llvm-svn: 56893
2008-09-30 23:58:47 +00:00
f4a36407c7
Fix a simple error in renumbering kill markaers, that took an inordinant amount of time to track down.
...
llvm-svn: 56889
2008-09-30 22:51:54 +00:00
e818bc159f
- Initialize "--no-builtin" to "false".
...
- Testcase for r56885.
llvm-svn: 56886
2008-09-30 21:40:30 +00:00
bd09262e97
Add the new `-no-builtin' flag. This flag is meant to mimic the GCC
...
`-fno-builtin' flag. Currently, it's used to replace "memset" with "_bzero"
instead of "__bzero" on Darwin10+. This arguably violates the meaning of this
flag, but is currently sufficient. The meaning of this flag should become more
specific over time.
llvm-svn: 56885
2008-09-30 21:22:07 +00:00
b486350b15
Move the primary fast-isel top-level comments to FastISel.cpp, where
...
they'll be a little more visible. Also, update and reword them a bit.
llvm-svn: 56877
2008-09-30 20:48:29 +00:00
86aa16a69a
Optimize SelectionDAG's AssignTopologicalOrder even further.
...
Completely eliminate the TopOrder std::vector. Instead, sort
the AllNodes list in place. This also eliminates the need to
call AllNodes.size(), a linear-time operation, before
performing the sort.
Also, eliminate the Sources temporary std::vector, since it
essentially duplicates the sorted result as it is being
built.
This also changes the direction of the topological sort
from bottom-up to top-down. The AllNodes list starts out in
roughly top-down order, so this reduces the amount of
reordering needed. Top-down is also more convenient for
Legalize, and ISel needed only minor adjustments.
llvm-svn: 56867
2008-09-30 18:30:35 +00:00
9156bd2f48
Re-apply 56835 along with header file changes.
...
llvm-svn: 56848
2008-09-30 15:44:16 +00:00
2b9adce1d0
Revert commit 56835 since it breaks the build.
...
"If a re-materializable instruction has a register
operand, the spiller will change the register operand's
spill weight to HUGE_VAL to avoid it being spilled.
However, if the operand is already in the queue ready
to be spilled, avoid re-materializing it".
llvm-svn: 56837
2008-09-30 10:00:30 +00:00
9469049f7d
If a re-materializable instruction has a register operand, the spiller will change the register operand's spill weight to HUGE_VAL to avoid it being spilled. However, if the operand is already in the queue ready to be spilled, avoid re-materializing it.
...
llvm-svn: 56835
2008-09-30 06:36:58 +00:00
f61a84ec43
Remove misuse of ReplaceNodeResults for atomics with
...
valid types. No functional change.
llvm-svn: 56808
2008-09-29 22:25:26 +00:00
4aa9095398
Fix FastISel to not initialize the PIC-base register multiple times
...
in functions with PIC references from more than one basic block.
llvm-svn: 56807
2008-09-29 21:55:50 +00:00
c966a737c5
Temporarily reverting r56683. This is causing a failure during the build of llvm-gcc:
...
/Volumes/Gir/devel/llvm/clean/llvm-gcc.obj/./gcc/xgcc -B/Volumes/Gir/devel/llvm/clean/llvm-gcc.obj/./gcc/ -B/Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/bin/ -B/Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/lib/ -isystem /Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/include -isystem /Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/sys-include -mmacosx-version-min=10.4 -O2 -O2 -g -O2 -DIN_GCC -W -Wall -Wwrite-strings -Wstrict-prototypes -Wmissing-prototypes -Wold-style-definition -isystem ./include -fPIC -pipe -g -DHAVE_GTHR_DEFAULT -DIN_LIBGCC2 -D__GCC_FLOAT_NOT_NEEDED -I. -I. -I../../llvm-gcc.src/gcc -I../../llvm-gcc.src/gcc/. -I../../llvm-gcc.src/gcc/../include -I./../intl -I../../llvm-gcc.src/gcc/../libcpp/include -I../../llvm-gcc.src/gcc/../libdecnumber -I../libdecnumber -I/Volumes/Gir/devel/llvm/clean/llvm.obj/include -I/Volumes/Gir/devel/llvm/clean/llvm.src/include -fexceptions -fvisibility=hidden -DHIDE_EXPORTS -c ../../llvm-gcc.src/gcc/unwind-dw2-fde-darwin.c -o libgcc/./unwind-dw2-fde-darwin.o
Assertion failed: (TargetRegisterInfo::isVirtualRegister(regA) && TargetRegisterInfo::isVirtualRegister(regB) && "cannot update physical register live information"), function runOnMachineFunction, file /Volumes/Gir/devel/llvm/clean/llvm.src/lib/CodeGen/TwoAddressInstructionPass.cpp, line 311.
../../llvm-gcc.src/gcc/unwind-dw2.c:1527: internal compiler error: Abort trap
Please submit a full bug report,
with preprocessed source if appropriate.
See <URL:http://developer.apple.com/bugreporter > for instructions.
{standard input}:3521:non-relocatable subtraction expression, "_dwarf_reg_size_table" minus "L20$pb"
{standard input}:3521:symbol: "_dwarf_reg_size_table" can't be undefined in a subtraction expression
{standard input}:3520:non-relocatable subtraction expression, "_dwarf_reg_size_table" minus "L20$pb"
...
llvm-svn: 56703
2008-09-26 22:10:44 +00:00
6e0548336a
Rename ConstantSDNode's getSignExtended to getSExtValue, for
...
consistancy with ConstantInt, and re-implement it in terms
of ConstantInt's getSExtValue.
llvm-svn: 56700
2008-09-26 21:54:37 +00:00
d77cbe8947
Fix @llvm.frameaddress codegen. FP elimination optimization should be disabled when frame address is desired. Also add support for depth > 0.
...
llvm-svn: 56683
2008-09-26 19:48:35 +00:00
0e32a2c935
Add "inreg" field to CallSDNode (doesn't increase
...
its size). Adjust various lowering functions to
pass this info through from CallInst. Use it to
implement sseregparm returns on X86. Remove
X86_ssecall calling convention.
llvm-svn: 56677
2008-09-26 19:31:26 +00:00
a381313d98
We don't need to insert copies for implicit_def's.
...
llvm-svn: 56674
2008-09-26 18:50:46 +00:00
374d7f2b16
If we have a function with an unreachable statement such that the ending debug
...
information is in an unreachable block, then it's possible that the high/low pc
values won't be set for the dwarf information. E.g., this function:
void abort(void) __attribute__((__noreturn__));
void dead_beef(void) __attribute__ ((noreturn));
int *b;
void dead_beef(void) {
*b=0xdeadbeef;
abort();
}
has a call to "@llvm.dbg.region.end" only in the unreachable block:
define void @dead_beef() noreturn nounwind {
entry:
call void @llvm.dbg.func.start(...)
call void @llvm.dbg.stoppoint(...)
...
call void @abort( ) noreturn nounwind
unreachable
return: ; No predecessors!
call void @llvm.dbg.stoppoint(...)
call void @llvm.dbg.region.end(...)
ret void
}
The dwarf information emitted is something like:
0x00000084: TAG_subprogram [5]
AT_name( "dead_beef" )
AT_external( 0x01 )
AT_prototyped( 0x01 )
AT_decl_file( 0x01 )
AT_decl_line( 0x08 )
Note that this is *not* the best fix for this problem, but a band-aid for an
gaping wound. This code needs to be changed when we revamp our debugging
information.
llvm-svn: 56628
2008-09-26 00:28:12 +00:00
4c758ea3e0
Large mechanical patch.
...
s/ParamAttr/Attribute/g
s/PAList/AttrList/g
s/FnAttributeWithIndex/AttributeWithIndex/g
s/FnAttr/Attribute/g
This sets the stage
- to implement function notes as function attributes and
- to distinguish between function attributes and return value attributes.
This requires corresponding changes in llvm-gcc and clang.
llvm-svn: 56622
2008-09-25 21:00:45 +00:00
c50ada2f56
Accept 'inreg' attribute on x86 functions as
...
meaning sse_regparm (i.e. float/double values go
in XMM0 instead of ST0). Update documentation
to reflect reality.
llvm-svn: 56619
2008-09-25 20:47:45 +00:00
5e490a7567
Support for i1 XOR in FastISel. It is actually safe because
...
i1 operands are assumed to already by zero-extended.
llvm-svn: 56615
2008-09-25 17:22:52 +00:00
6975c36c43
Don't print fast-isel debug messages by default. Thanks Chris!
...
llvm-svn: 56614
2008-09-25 17:21:42 +00:00
dd920bf3f0
Don't forget the newline in debug output.
...
llvm-svn: 56613
2008-09-25 17:17:27 +00:00
32a733e2c7
FastISel support for debug info.
...
llvm-svn: 56610
2008-09-25 17:05:24 +00:00
4b35e64504
bug 2812: Segmentation fault on a big emdiam processor.
...
llvm-svn: 56609
2008-09-25 16:15:10 +00:00
3663f156f7
Fix a recent fast-isel coverage regression - don't bail out before
...
giving the target a chance to materialize constants.
llvm-svn: 56605
2008-09-25 01:28:51 +00:00
b8e69f1755
Enable DeadMachineInstructionElim when Fast-ISel is enabled.
...
llvm-svn: 56604
2008-09-25 01:14:49 +00:00
b873aa632c
Add debug output to this pass.
...
llvm-svn: 56602
2008-09-25 01:06:50 +00:00
acb0554842
Refactor the code that adds standard LLVM codegen passes into
...
a separate function, eliminating duplication between the
add-passes-for-file and add-passes-for-machine-code code.
llvm-svn: 56599
2008-09-25 00:37:07 +00:00
2e7450716a
<rdar://problem/6234798> Assertion failed: (!OpInfo.AssignedRegs.Regs.empty() && "Couldn't allocate input reg!")
...
llvm-svn: 56597
2008-09-25 00:14:04 +00:00
382e2ec6b7
Give LowerSubregs.cpp a top-level description.
...
llvm-svn: 56596
2008-09-24 23:44:12 +00:00
86d421df23
Remove SelectionDag early allocation of registers
...
for earlyclobbers. Teach Local RA about earlyclobber,
and add some tests for it.
llvm-svn: 56592
2008-09-24 23:13:09 +00:00
fd7faecfc2
Use helper
...
llvm-svn: 56584
2008-09-24 22:21:04 +00:00
d19e91e5a8
SmallPtrSet will be better
...
llvm-svn: 56583
2008-09-24 22:20:46 +00:00
123afb88c4
Use generic section-handling stuff to emit constant pool entries
...
llvm-svn: 56579
2008-09-24 22:17:59 +00:00
7497762606
Get rid of duplicate char*/Section* DataSection
...
llvm-svn: 56575
2008-09-24 22:16:16 +00:00
f8dc8aac3c
Get rid of duplicate char*/Section* TextSection
...
llvm-svn: 56574
2008-09-24 22:15:21 +00:00
076e905b94
Move actual section printing stuff to AsmPrinter from TAI reducing heap traffic.
...
llvm-svn: 56573
2008-09-24 22:14:23 +00:00
69ff51baa0
Drop obsolete hook and change all usage to new interface
...
llvm-svn: 56572
2008-09-24 22:13:07 +00:00
7d002fa77b
Provide direct function to switch to Section
...
llvm-svn: 56571
2008-09-24 22:12:10 +00:00
4ef4b1a7c1
Fix off-by-one error when updating live intervals.
...
llvm-svn: 56567
2008-09-24 21:30:38 +00:00
dea91308ae
Reapplying r56550
...
llvm-svn: 56553
2008-09-24 10:25:02 +00:00
162c26dee3
Forgot this part with my last patch. Sorry about the breakage.
...
llvm-svn: 56552
2008-09-24 10:16:24 +00:00
4e26a81371
Temporarily revert r56550 until missing commit can be added.
...
llvm-svn: 56551
2008-09-24 08:30:44 +00:00
7c31464a0b
Refactor the constant folding code into it's own function. And call it from both
...
the SelectionDAG and DAGCombiner code. The only functionality change is that now
the DAG combiner is performing the constant folding for these operations instead
of being a no-op.
This is *not* in response to a bug, so there isn't a testcase.
llvm-svn: 56550
2008-09-24 07:11:26 +00:00
c36660d756
Next round of earlyclobber handling. Approach the
...
RA problem by expanding the live interval of an
earlyclobber def back one slot. Remove
overlap-earlyclobber throughout. Remove
earlyclobber bits and their handling from
live internals.
llvm-svn: 56539
2008-09-24 01:07:17 +00:00
6b33aa4d96
Refactor the logic for testing if an instruction is dead into a
...
separate method.
llvm-svn: 56531
2008-09-24 00:27:38 +00:00
1e2b282be3
Set SetStore to false, to allow this pass to delete
...
dead loads.
llvm-svn: 56529
2008-09-24 00:07:08 +00:00
7c59ed6ff8
Add a method to MachineInstr for testing whether it makes
...
any volatile memory references.
llvm-svn: 56528
2008-09-24 00:06:15 +00:00
e0add20c1b
Properly handle 'm' inline asm constraints. If a GV is being selected for the addressing mode, it requires the same logic for PIC relative addressing, etc.
...
llvm-svn: 56526
2008-09-24 00:05:32 +00:00
ba3fa6c6e1
s/ParameterAttributes/Attributes/g
...
llvm-svn: 56513
2008-09-23 23:03:40 +00:00
676145f02d
Now that DeadMachineInstructionElim is basically working
...
correctly, it's not necessary to explicitly remove registers
from their use-def lists.
llvm-svn: 56509
2008-09-23 22:04:18 +00:00
918fe08a56
Arrange for FastISel code to have access to the MachineModuleInfo
...
object. This will be needed to support debug info.
llvm-svn: 56508
2008-09-23 21:53:34 +00:00
269999cb03
Track local physical register liveness. This is not the most
...
efficient implementation possible, but it's pretty simple and
good enough for the time being.
llvm-svn: 56504
2008-09-23 21:40:44 +00:00
c07f686665
Replace the LiveRegs SmallSet with a simple counter that keeps
...
track of the number of live registers, which is all the set was
being used for.
llvm-svn: 56498
2008-09-23 18:50:48 +00:00
4cdc18ad80
Add initial support for inserting last minute copies.
...
llvm-svn: 56485
2008-09-23 04:37:10 +00:00
e2947e1e07
Fix the alignment of loads from constant pool entries when the
...
load address has an offset from the base of the constant pool
entry.
llvm-svn: 56479
2008-09-22 22:40:08 +00:00
bab5988017
Livestacks really does preserve everything.
...
llvm-svn: 56476
2008-09-22 22:26:15 +00:00
962c2cf17a
Instead of setPreservesAll, just mark them preseving machine loop info and machine dominators.
...
llvm-svn: 56475
2008-09-22 22:21:38 +00:00
97364655dc
Significant improvements to the logic for merging live intervals. This code can't
...
just use LI::MergeValueAsValue, as its behavior in the presence of overlapping ranges
isn't what StrongPHIElimination wants.
llvm-svn: 56472
2008-09-22 21:58:58 +00:00
7a74e71489
Make log, log2, log10, exp, exp2 use Expand by
...
default.
llvm-svn: 56471
2008-09-22 21:57:32 +00:00
168f8f3916
Mark several codegen passes as preserving all analysis.
...
llvm-svn: 56469
2008-09-22 20:58:04 +00:00
f1acc4d610
More refactoring. Yawn.
...
llvm-svn: 56468
2008-09-22 20:51:30 +00:00
7beddb8680
Refactor FP intrinisic setup. Per review feedback.
...
llvm-svn: 56456
2008-09-22 19:51:58 +00:00
13beeeb128
Per review feedback: Only perform
...
(srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), c))
etc. when both "trunc" and "and" have single uses.
llvm-svn: 56452
2008-09-22 18:19:24 +00:00
a229b3c9a7
Initial support for the CMake build system.
...
llvm-svn: 56419
2008-09-22 01:08:49 +00:00
91ef8fcd29
Add helper function to get a 32-bit floating point constant. No functionality change.
...
llvm-svn: 56418
2008-09-22 00:44:35 +00:00
ae9d9f4d3f
Factor out code into HandleVirtRegDef, for consistency with
...
Handle{Virt,Phys}Reg{Def,Use}. Remove a redundant check
for register zero, and redundant checks for isPhysicalRegister.
llvm-svn: 56412
2008-09-21 21:11:41 +00:00
df8f1cb995
Fetch the starting index of the block when assigning intervals. This gets live-in indices
...
correct in the presence of things like EH labels.
llvm-svn: 56410
2008-09-21 20:43:24 +00:00
43f5449c48
don't print GlobalAddressSDNode's with an offset of zero as "foo0".
...
llvm-svn: 56399
2008-09-21 18:38:31 +00:00
9af7b3daec
Teach coalescer about earlyclobber bits.
...
Check bits for preferred register.
llvm-svn: 56384
2008-09-20 02:03:04 +00:00
c042000649
Fix PR2808. When regalloc runs out of register, it spill a physical register around the live interval being allocated. Do not continue to try to spill another register, just grab the physical register and move on.
...
llvm-svn: 56381
2008-09-20 01:28:05 +00:00
29e4c9192d
Continue after removing the current MI.
...
llvm-svn: 56372
2008-09-19 22:49:39 +00:00
9801ba451a
Refactor X86SelectConstAddr, folding it into X86SelectAddress. This
...
results in better code for globals. Also, unbreak the local CSE for
GlobalValue stub loads.
llvm-svn: 56371
2008-09-19 22:16:54 +00:00
436aae627d
Make earlyclobber stuff work when virtual regs
...
have previously been assigned conflicting physreg.
llvm-svn: 56364
2008-09-19 18:52:31 +00:00
4c0197043c
Re-materalized definition instructions may be dead. Whack them.
...
llvm-svn: 56352
2008-09-19 17:38:47 +00:00
e519bd4183
Remove AsmThatEarlyClobber etc. from LiveIntervalAnalysis
...
and redo as linked list walk. Logic moved into RA.
Per review feedback.
llvm-svn: 56326
2008-09-19 01:02:35 +00:00
3d9416cf24
Somehow RegAllocLinearScan is keeping two pointers to MachineRegisterInfo.
...
llvm-svn: 56314
2008-09-18 22:38:47 +00:00
f3d647e00b
Don't consider instructions with implicit physical register
...
defs to be necessarily live.
llvm-svn: 56310
2008-09-18 18:22:32 +00:00
95be7d7b85
Add a new "fast" scheduler. This is currently basically just a
...
copy of the BURRList scheduler, but with several parts ripped
out, such as backtracking, online topological sort maintenance
(needed by backtracking), the priority queue, and Sethi-Ullman
number computation and maintenance (needed by the priority
queue). As a result of all this, it generates somewhat lower
quality code, but that's its tradeoff for running about 30%
faster than list-burr in -fast mode in many cases.
This is somewhat experimental. Moving forward, major pieces of
this can be refactored with pieces in common with
ScheduleDAGRRList.cpp.
llvm-svn: 56307
2008-09-18 16:26:26 +00:00
f8610ebebc
Add a bit to mark operands of asm's that conflict
...
with an earlyclobber operand elsewhere. Propagate
this bit and the earlyclobber bit through SDISel.
Change linear-scan RA not to allocate regs in a way
that conflicts with an earlyclobber. See also comments.
llvm-svn: 56290
2008-09-17 21:13:11 +00:00
f3fcd7a464
Unallocatable registers do not have live intervals.
...
llvm-svn: 56287
2008-09-17 18:36:25 +00:00
6ab52a8018
Don't worry about clobbering physical register defs that aren't used.
...
llvm-svn: 56281
2008-09-17 15:25:49 +00:00
c24cd015a7
Add a new MachineInstr-level DCE pass. It is very simple, and is intended to
...
be used with fast-isel.
llvm-svn: 56268
2008-09-17 00:43:24 +00:00
a904f466e8
When converting a CopyFromReg to a copy instruction, use the register class of its uses to determine the right destination register class of the copy. This is important for targets where a physical register may belong to multiple register classes.
...
llvm-svn: 56258
2008-09-16 23:12:11 +00:00
64d6c6fe30
Change SelectionDAG::getConstantPool to always set the alignment of the
...
ConstantPoolSDNode, using the target's preferred alignment for the
constant type.
In LegalizeDAG, when performing loads from the constant pool, the
ConstantPoolSDNode's alignment is used in the calls to getLoad and
getExtLoad.
This change prevents SelectionDAG::getLoad/getExtLoad from incorrectly
choosing the ABI alignment for constant pool loads when Alignment == 0.
The incorrect alignment is only a performance issue when ABI alignment
does not equal preferred alignment (i.e., on x86 it was generating
MOVUPS instead of MOVAPS for v4f32 constant loads when the default ABI
alignment for 128bit vectors is forced to 1 byte.)
Patch by Paul Redmond!
llvm-svn: 56253
2008-09-16 22:05:41 +00:00
24c79f28b1
Reverting r56249. On further investigation, this functionality isn't needed.
...
Apologies for the thrashing.
llvm-svn: 56251
2008-09-16 21:48:12 +00:00
ab26f20d44
Include the alignment value when displaying ConstantPoolSDNodes.
...
llvm-svn: 56250
2008-09-16 21:18:22 +00:00
8bc392fb1d
- Change "ExternalSymbolSDNode" to "SymbolSDNode".
...
- Add linkage to SymbolSDNode (default to external).
- Change ISD::ExternalSymbol to ISD::Symbol.
- Change ISD::TargetExternalSymbol to ISD::TargetSymbol
These changes pave the way to allowing SymbolSDNodes with non-external linkage.
llvm-svn: 56249
2008-09-16 21:12:30 +00:00
5cf6120a7c
Fix these comments to reflect current reality. Surprisingly,
...
MachineConstantPool::getConstantPoolIndex actually expects
a log2-encoded alignment.
llvm-svn: 56248
2008-09-16 20:45:53 +00:00
050d7835c6
Don't take the time to CheckDAGForTailCallsAndFixThem when tail calls
...
are not enabled. Instead just omit the tail call flag when calls are
created.
llvm-svn: 56235
2008-09-16 01:42:28 +00:00
82ab1e7280
Live intervals for live-in registers should begin at the beginning of a basic block, not at the first
...
instruction. Also, their valno's should have an unknown def. This has no effect currently, but was
causing issues when StrongPHIElimination was enabled.
llvm-svn: 56231
2008-09-15 22:00:38 +00:00
3c7b9ba547
Re-enable SelectionDAG CSE for calls. It matters in the case of
...
libcalls, as in this testcase on ARM.
llvm-svn: 56226
2008-09-15 19:46:03 +00:00
02acc35abd
Correctly update kill infos after extending a live range and merge 2 val#'s; fix 56165 - do not mark val# copy field if the copy does not define the val#.
...
llvm-svn: 56199
2008-09-15 06:28:41 +00:00
c0d712d9ed
adjust last patch per review feedback
...
llvm-svn: 56194
2008-09-14 01:44:36 +00:00
38453eebdc
Remove isImm(), isReg(), and friends, in favor of
...
isImmediate(), isRegister(), and friends, to avoid confusion
about having two different names with the same meaning. I'm
not attached to the longer names, and would be ok with
changing to the shorter names if others prefer it.
llvm-svn: 56189
2008-09-13 17:58:21 +00:00
d3fe174c53
Define CallSDNode, an SDNode subclass for use with ISD::CALL.
...
Currently it just holds the calling convention and flags
for isVarArgs and isTailCall.
And it has several utility methods, which eliminate magic
5+2*i and similar index computations in several places.
CallSDNodes are not CSE'd. Teach UpdateNodeOperands to handle
nodes that are not CSE'd gracefully.
llvm-svn: 56183
2008-09-13 01:54:27 +00:00
3c12fc4342
On some targets, non-move instructions can become move instructions because of coalescing. e.g.
...
vr2 = OR vr0, vr1
=>
vr2 = OR vr1, vr1 // after coalescing vr0 with vr1
Update the value# of the destination register with the copy instruction if that happens.
llvm-svn: 56165
2008-09-12 18:13:14 +00:00
ec270fb640
Change ConstantSDNode and ConstantFPSDNode to use ConstantInt* and
...
ConstantFP* instead of APInt and APFloat directly.
This reduces the amount of time to create ConstantSDNode
and ConstantFPSDNode nodes when ConstantInt* and ConstantFP*
respectively are already available, as is the case in
SelectionDAGBuild.cpp. Also, it reduces the amount of time
to legalize constants into constant pools, and the amount of
time to add ConstantFP operands to MachineInstrs, due to
eliminating ConstantInt::get and ConstantFP::get calls.
It increases the amount of work needed to create new constants
in cases where the client doesn't already have a ConstantInt*
or ConstantFP*, such as legalize expanding 64-bit integer constants
to 32-bit constants. And it adds a layer of indirection for the
accessor methods. But these appear to be outweight by the benefits
in most cases.
It will also make it easier to make ConstantSDNode and
ConstantFPNode more consistent with ConstantInt and ConstantFP.
llvm-svn: 56162
2008-09-12 18:08:03 +00:00
1f3ab86804
Pass "earlyclobber" bit through to machine
...
representation; coalescer and RA need to know
about it. No functional change.
llvm-svn: 56161
2008-09-12 17:49:03 +00:00
effb894453
Rename ConstantSDNode::getValue to getZExtValue, for consistency
...
with ConstantInt. This led to fixing a bug in TargetLowering.cpp
using getValue instead of getAPIntValue.
llvm-svn: 56159
2008-09-12 16:56:44 +00:00
baf6762e26
The sequence for ppcf128 compares was not IEEE
...
safe in the presence of NaNs.
llvm-svn: 56136
2008-09-12 00:30:56 +00:00
5456a37280
Fix PR2748. Avoid coalescing physical register with virtual register which would create illegal extract_subreg. e.g.
...
vr1024 = extract_subreg vr1025, 1
...
vr1024 = mov8rr AH
If vr1024 is coalesced with AH, the extract_subreg is now illegal since AH does not have a super-reg whose sub-register 1 is AH.
llvm-svn: 56118
2008-09-11 20:07:10 +00:00
4c9fbbb511
Fix PR2783 - coalescer bug. Missing a TargetRegisterInfo::isVirtualRegister check.
...
llvm-svn: 56112
2008-09-11 18:40:32 +00:00
783ed9ead1
Fix a 80 column violation.
...
llvm-svn: 56097
2008-09-11 05:58:06 +00:00
b401449ceb
Propagate subreg index when promoting a load to a copy.
...
llvm-svn: 56085
2008-09-11 01:02:12 +00:00
1dc9b0514f
FastISel support for i1 PHI nodes.
...
llvm-svn: 56069
2008-09-10 21:01:31 +00:00
940bafb687
FastISel support for i1 constants.
...
llvm-svn: 56068
2008-09-10 21:01:08 +00:00
7591130946
Fix a bug in the coalescer where it didn't check if a live interval existed before trying to manipulate it. This
...
was exposed by fast isel's handling of shifts on X86-64. With this, FreeBench/pcompress2 passes on X86-64 in fast isel.
llvm-svn: 56067
2008-09-10 20:41:13 +00:00
39d82f902a
Add X86FastISel support for static allocas, and refences
...
to static allocas. As part of this change, refactor the
address mode code for laods and stores.
llvm-svn: 56066
2008-09-10 20:11:02 +00:00
534fe1c405
Fix PR2664 - spiller GetRegForReload wasn't respecting sub-register indices on machine operands.
...
llvm-svn: 56065
2008-09-10 20:08:45 +00:00
222018da7b
Add a break statement that I accidentally deleted when
...
I shuffled the fast-isel command-line options around. This fixes
a bunch of fast-isel failures.
llvm-svn: 56057
2008-09-10 15:52:34 +00:00
6987fec11c
Remove unnecessary bit-wise AND from the limited precision work.
...
llvm-svn: 56049
2008-09-10 06:26:10 +00:00
999096065f
Fix 80 col violation.
...
llvm-svn: 56048
2008-09-10 04:16:29 +00:00
c6db3ad15f
Fix typo.
...
llvm-svn: 56037
2008-09-10 00:30:50 +00:00
eb1db169bf
Check that both operands are f32 before attempting to lower.
...
llvm-svn: 56036
2008-09-10 00:24:59 +00:00
648930b9ba
Implement "visitPow". This is mainly used to see if we have a pow() call of this
...
form:
powf(10.0f, x);
If this is the case, and also we want limited precision floating-point
calculations, then lower to do the limited-precision stuff.
llvm-svn: 56035
2008-09-10 00:20:20 +00:00
0fff397a13
A few more places where FPOW is being ignored.
...
llvm-svn: 56032
2008-09-09 23:35:53 +00:00
b4c0295b8e
Change -fast-isel-no-abort to -fast-isel-abort, which now defaults
...
to being off by default. Also, add assertion checks to check that
the various fast-isel-related command-line options are only used
when -fast-isel itself is enabled.
llvm-svn: 56029
2008-09-09 23:05:00 +00:00
f4e5de4583
Legalizer was missing code that expand fpow to a libcall.
...
llvm-svn: 56028
2008-09-09 23:02:14 +00:00
ab6676a46a
Adding 6-, 12-, and 18-bit limited-precision floating-point support for exp2
...
function.
llvm-svn: 56025
2008-09-09 22:39:21 +00:00
abb1e7770b
Move the uglier parts of deciding not to emit a
...
UsedDirective for some symbols in llvm.used into
Darwin-specific code. I've decided LessPrivateGlobal
is potentially a useful abstraction and left it in
the target-independent area, with improved comment.
llvm-svn: 56024
2008-09-09 22:29:13 +00:00
48217d89b4
Add support for 6-, 12-, and 18-bit limited precision calculations of exp for
...
floating-point numbers.
llvm-svn: 56023
2008-09-09 22:13:54 +00:00
91491b51e2
Add a new option, -fast-isel-verbose, that can be used with
...
-fast-isel-no-abort to get a dump of all unhandled instructions,
without an abort.
llvm-svn: 56021
2008-09-09 22:06:46 +00:00
93945287b8
Clear preference when it no longer makes sense.
...
llvm-svn: 56019
2008-09-09 21:44:23 +00:00
4a58bd331b
Clean this up, based on Evan's suggestions.
...
llvm-svn: 56009
2008-09-09 20:47:17 +00:00
ed3bb7888d
- Add support for 6-, 12-, and 18-bit limited precision floating-point "log"
...
values.
- Refactored some of the code.
llvm-svn: 56008
2008-09-09 20:39:27 +00:00
53b728c27c
Fix PR2757. Ignore liveinterval register allocation preference if the preference register is not in the right register class. This can happen due to sub-register coalescing.
...
llvm-svn: 56006
2008-09-09 20:22:01 +00:00
1a1140429e
Make safer variant of alias resolution routine to be default
...
llvm-svn: 56005
2008-09-09 20:05:04 +00:00
faeb4b6755
Add limited precision floating-point conversions of log10 for 6- and 18-bit
...
precisions.
llvm-svn: 56000
2008-09-09 18:42:23 +00:00
8529085f4f
Check for type legality before materializing integer constants in fast isel. With this change,
...
all of MultiSource/Applications passes on Darwin/X86 under FastISel.
llvm-svn: 55982
2008-09-09 06:32:02 +00:00
b6aef419b4
Remove the code that protected FastISel from aborting in
...
the case of loads, stores, and conditional branches. It can
handle those now, so any that aren't handled should trigger
the abort.
llvm-svn: 55977
2008-09-09 02:40:04 +00:00
1e97901388
Fix a constant lowering bug. Now we can do load and store instructions with funky getelementptr embedded in the address operand.
...
llvm-svn: 55975
2008-09-09 01:26:59 +00:00
f080225490
Fix logic for not emitting no-dead-strip for some
...
objects in llvm.used (thanks Anton). Makes visible
the magic 'l' prefix for symbols on Darwin which are
to be passed through the assembler, then removed at
linktime (previously all references to this had been
hidden in the ObjC FE code, oh well).
llvm-svn: 55973
2008-09-09 01:21:22 +00:00
484167851a
Add support for floating-point calculations of log2 with limited precisions of 6
...
and 18.
llvm-svn: 55968
2008-09-09 00:28:24 +00:00
ea9285e643
Don't suppress no-dead-strip for used static functions.
...
llvm-svn: 55962
2008-09-08 21:21:49 +00:00
45165ed1ac
Reapply 55904: Unbreak and fix indentation
...
llvm-svn: 55958
2008-09-08 21:13:56 +00:00
a333f3ccb8
Fix a few I's that were meant to be renamed to BI's.
...
llvm-svn: 55942
2008-09-08 20:37:59 +00:00
67f99f1454
Redo the 3 existing low-precision expansions to
...
use float constants. An oversight by the numerics
people who supplied this.
llvm-svn: 55930
2008-09-08 18:00:26 +00:00
99b83712f3
Reverting r55898 to r55909. One of these patches was causing an ICE during the full bootstrap on Darwin:
...
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/xgcc
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/bin/
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/lib/
-isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/include
-isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/sys-include
-O2 -O2 -g -O2 -DIN_GCC -W -Wall -Wwrite-strings
-Wstrict-prototypes -Wmissing-prototypes -Wold-style-definition
-isystem ./include -fPIC -pipe -g -DHAVE_GTHR_DEFAULT -DIN_LIBGCC2
-D__GCC_FLOAT_NOT_NEEDED -I. -I. -I../../llvm-gcc.src/gcc
-I../../llvm-gcc.src/gcc/. -I../../llvm-gcc.src/gcc/../include
-I./../intl -I../../llvm-gcc.src/gcc/../libcpp/include
-I../../llvm-gcc.src/gcc/../libdecnumber -I../libdecnumber
-I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.obj/include
-I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/include
-DSHARED -m64 -DL_negdi2 -c ../../llvm-gcc.src/gcc/libgcc2.c -o
libgcc/x86_64/_negdi2_s.o
Assertion failed: (TargetRegisterInfo::isVirtualRegister(regA) &&
TargetRegisterInfo::isVirtualRegister(regB) && "cannot update physical
register live information"), function runOnMachineFunction, file
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/lib/CodeGen/TwoAddressInstructionPass.cpp,
line 311.
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/xgcc
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/bin/
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/lib/
-isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/include
-isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/sys-include
-O2 -O2 -g -O2 -DIN_GCC -W -Wall -Wwrite-strings
-Wstrict-prototypes -Wmissing-prototypes -Wold-style-definition
-isystem ./include -fPIC -pipe -g -DHAVE_GTHR_DEFAULT -DIN_LIBGCC2
-D__GCC_FLOAT_NOT_NEEDED -I. -I. -I../../llvm-gcc.src/gcc
-I../../llvm-gcc.src/gcc/. -I../../llvm-gcc.src/gcc/../include
-I./../intl -I../../llvm-gcc.src/gcc/../libcpp/include
-I../../llvm-gcc.src/gcc/../libdecnumber -I../libdecnumber
-I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.obj/include
-I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/include
-DSHARED -m64 -DL_lshrdi3 -c ../../llvm-gcc.src/gcc/libgcc2.c -o
libgcc/x86_64/_lshrdi3_s.o
../../llvm-gcc.src/gcc/unwind-dw2.c:1527: internal compiler error: Abort trap
Please submit a full bug report,
with preprocessed source if appropriate.
See <URL:http://developer.apple.com/bugreporter > for instructions.
{standard input}:unknown:Undefined local symbol LBB21_11
{standard input}:unknown:Undefined local symbol LBB21_12
{standard input}:unknown:Undefined local symbol LBB21_13
{standard input}:unknown:Undefined local symbol LBB21_8
llvm-svn: 55928
2008-09-08 17:59:12 +00:00
1df80f6b1c
In visitUREM, arrange for the temporary UDIV node to be
...
revisited, consistent with the code in visitSREM.
llvm-svn: 55923
2008-09-08 16:59:01 +00:00
ede2d7d745
Add VISIBILITY_HIDDEN on SDISelAsmOperandInfo
...
llvm-svn: 55922
2008-09-08 16:56:08 +00:00
f9b2054df1
Add AsmPrinter support for i128 and larger static initializer data.
...
llvm-svn: 55919
2008-09-08 16:40:13 +00:00
e19bc1844f
Fix the string for ISD::UDIVREM.
...
llvm-svn: 55917
2008-09-08 16:30:29 +00:00
24776b554d
Avoid redefinition and nnbreak windows build.
...
llvm-svn: 55911
2008-09-08 16:01:27 +00:00
6a73698a85
Unbreak and fix indentation
...
llvm-svn: 55904
2008-09-08 14:23:34 +00:00
e775d3526c
Add fast isel physical register definition support.
...
llvm-svn: 55892
2008-09-08 08:38:20 +00:00
5f7371d7b1
Revert my previous change -- the subtraction of two constants was a no-op
...
before. This is taken care of in the selection DAG pass. In my opinion, this
should be in one place or the other. I.e., it should probably be removed from
the DAG combiner (along with the other arithmetic transformations on constants
that are essentially no-ops).
llvm-svn: 55889
2008-09-08 01:56:32 +00:00
df81749886
Convert
...
// fold (sub c1, c2) -> c1-c2
from a no-op into an actual transformation.
llvm-svn: 55886
2008-09-07 11:34:47 +00:00
b9a0abb129
Indentation.
...
llvm-svn: 55880
2008-09-07 09:04:52 +00:00
615739b991
- Doh. Pass vector by value is bad.
...
- Add a AnalyzeCallResult specialized for calls which produce a single value. This is used by fastisel.
llvm-svn: 55879
2008-09-07 09:02:18 +00:00
36d532abd6
Next limited float precision expansion (log2 12 bits)
...
llvm-svn: 55866
2008-09-05 23:49:37 +00:00
1dd2e40521
Revert r55859. This is breaking the build in the abscence of its companion commit.
...
llvm-svn: 55865
2008-09-05 23:36:01 +00:00
f17a2f3602
Move the code that inserts copies for function livein registers
...
out of ScheduleDAGEmit.cpp and into SelectionDAGISel.cpp. This
allows it to be run exactly once per function, even if multiple
SelectionDAG iterations happen in the entry block, as may happen
with FastISel.
llvm-svn: 55863
2008-09-05 22:59:21 +00:00
d4dac0e9ea
Add the next limited-precision expansion.
...
llvm-svn: 55856
2008-09-05 21:27:19 +00:00
fd634599dc
FastISel support for AND and OR with type i1.
...
llvm-svn: 55846
2008-09-05 18:44:22 +00:00
520143e563
Add hooks for other intrinsics to get low-precision expansions.
...
llvm-svn: 55845
2008-09-05 18:38:42 +00:00
fcf545690c
FastISel support for ConstantExprs.
...
llvm-svn: 55843
2008-09-05 18:18:20 +00:00
677c3afbd1
Revert r55817. It broke PIC. FastISel will need to find a different
...
approach here.
llvm-svn: 55842
2008-09-05 18:13:01 +00:00
6b8fae1777
Add a variant of AnalyzeCallOperands that can be used by fast isel.
...
llvm-svn: 55838
2008-09-05 16:59:26 +00:00
4d50e984bb
"Fix" PR2762. The testcase now crashes codegen
...
elsewhere due to a missing pattern for
v2f64 = sint_to_fp v2i32. That is PR2687.
llvm-svn: 55828
2008-09-05 08:13:35 +00:00
921ddd69ba
Fix a search+replace-o.
...
llvm-svn: 55824
2008-09-05 01:58:21 +00:00
f2a52bbee5
Add -flimit-float-precision to enable some faster,
...
but less accurate (non-IEEE) code sequences for
certain math library functions. Add the first of
several such expansions. Don't worry, if you don't
turn it on it won't affect you.
llvm-svn: 55823
2008-09-05 01:48:15 +00:00
ea56bdde34
FastISel support for unreachable.
...
llvm-svn: 55818
2008-09-05 01:08:41 +00:00
5b4a9f4a69
In FastISel mode, the scheduler may be invoked multiple times
...
in the same block. Fix the entry-block handling to only run at
at the beginning of the entry block, and not any other times.
llvm-svn: 55817
2008-09-05 01:07:48 +00:00
50288e3c99
Add initial support for selecting constant materializations that require constant
...
pool loads on X86 in fast isel. This isn't actually used yet.
llvm-svn: 55814
2008-09-05 00:06:23 +00:00
5eba3bcac6
Add an include of SmallSet.h.
...
llvm-svn: 55793
2008-09-04 20:49:27 +00:00
a79db30d28
Tidy up several unbeseeming casts from pointer to intptr_t.
...
llvm-svn: 55779
2008-09-04 17:05:41 +00:00
634412fe35
Clean up uses of TargetLowering::getTargetMachine.
...
llvm-svn: 55769
2008-09-04 15:39:15 +00:00
93d40ae1e1
Fix an overly strict assertion. Source register of a copy may not be killed, it may be killed by an implicit super-register use.
...
llvm-svn: 55762
2008-09-04 05:43:55 +00:00
da2d80688b
Add intrinsics for log, log2, log10, exp, exp2.
...
No functional change (and no FE change to generate them).
llvm-svn: 55753
2008-09-04 00:47:13 +00:00
e039d5580e
Do trivial local CSE for constants and other non-Instruction values
...
in FastISel.
llvm-svn: 55748
2008-09-03 23:32:19 +00:00
45df9951f5
Put RegsForValue in the llvm namespace to avoid warnings about
...
classes in the llvm namespace having members with types from
anonymous namespaces.
llvm-svn: 55747
2008-09-03 23:18:39 +00:00
7bda51f5a4
Create HandlePHINodesInSuccessorBlocksFast, a version of
...
HandlePHINodesInSuccessorBlocks that works FastISel-style. This
allows PHI nodes to be updated correctly while using FastISel.
This also involves some code reorganization; ValueMap and
MBBMap are now members of the FastISel class, so they needn't
be passed around explicitly anymore. Also, SelectInstructions
is changed to SelectInstruction, and only does one instruction
at a time.
llvm-svn: 55746
2008-09-03 23:12:08 +00:00
5c1ff11fc3
Do not emit a UsedDirective for things in the llvm.used
...
list that have internal linkage; the linker doesn't need
or want this. (These objects must still be preserved
at compile time, so just removing them from the llvm.used
list doesn't work.) Should affect only Darwin.
llvm-svn: 55722
2008-09-03 20:34:58 +00:00
b1b9398ea7
Oops, I accidentally broke the fallback case with my last commit.
...
llvm-svn: 55704
2008-09-03 17:51:57 +00:00
ea666816c2
Fix an issue where we were reusing materializations of constants in blocks not dominated by the materialization. This is
...
the simple fix, materializing the constant before every use. It might be better to either track domination of uses or
to materialize all constants and the beginning of the function and let remat sort when to do materialization at uses.
llvm-svn: 55703
2008-09-03 17:37:03 +00:00
575fad337c
Split the SelectionDAG-building code, including the FunctionLoweringInfo
...
and SelectionDAGLowering classes, out of SelectionDAGISel.cpp and put
it in a separate file, SelectionDAGBuild.cpp.
llvm-svn: 55701
2008-09-03 16:12:24 +00:00
b10f1a5c60
Separate MachineInstr-emitting routines from actual scheduling
...
routines and move them into a separate file, ScheduleDAGEmit.cpp.
llvm-svn: 55699
2008-09-03 16:01:59 +00:00
c7367b4546
Fix addRegisterDead and addRegisterKilled to be more thorough
...
when searching for redundant subregister dead/kill bits.
Previously it was common to see instructions marked like this:
"RET %EAX<imp-use,kill>, %AX<imp-use,kill>"
With this change, addRegisterKilled continues scanning after
finding the %EAX operand, so it proceeds to discover the
redundant %AX kill and eliminates it, producing this:
"RET %EAX<imp-use,kill>"
This currently has no effect on the generated code.
llvm-svn: 55698
2008-09-03 15:56:16 +00:00
31ddd09f4a
If TargetSelectInstruction returns true, move to next instruction.
...
llvm-svn: 55692
2008-09-03 06:43:41 +00:00
09ff2e7372
80 col violations.
...
llvm-svn: 55668
2008-09-02 21:59:13 +00:00
115267fdc6
Ensure that HandlePHINodesInSuccessorBlocks is run for all blocks,
...
even in FastISel mode in the case where FastISel successfully
selects all the instructions.
llvm-svn: 55641
2008-09-02 20:17:56 +00:00
9c64e61176
Provide two overloads of AnalyzeNewNode.
...
The first can update the SDNode in an SDValue
while the second is called with SDNode* and
returns a possibly updated SDNode*.
This patch has no intended functional impact,
but helps eliminating ugly temporary SDValues.
llvm-svn: 55608
2008-09-01 15:10:19 +00:00
4b31a2a7ce
Even though no caller actually uses the new value
...
(what matters is that it is added to the worklist),
it seems more logical to return it.
llvm-svn: 55606
2008-09-01 13:11:13 +00:00
58bb4f1bf0
Cosmetic changes to Machine LICM. No functionality change.
...
llvm-svn: 55578
2008-08-31 02:30:23 +00:00
11284ea499
Another situation where ROTR is cheaper than ROTL.
...
llvm-svn: 55577
2008-08-31 01:13:31 +00:00
4822a7ac8a
For this pattern, ROTR is the cheaper option.
...
llvm-svn: 55576
2008-08-31 01:04:56 +00:00
fc72416447
- Fix comment so that it describes how the code really works:
...
// fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
// (rotl x, y)
// fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
// (rotr x, (sub 32, y))
Example: (x == 0xDEADBEEF and y == 4)
(x << 4) | (x >> 28)
=> 0xEADBEEF0 | 0x0000000D
=> 0xEADBEEFD
(rotl x, 4)
=> 0xEADBEEFD
(rotr x, 28)
=> 0xEADBEEFD
- Fix comment and code for second version. It wasn't using the rot* propertly.
// fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) ->
// (rotr x, y)
// fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) ->
// (rotl x, (sub 32, y))
(x << 28) | (x >> 4)
=> 0xD0000000 | 0x0DEADBEE
=> 0xDDEADBEE
(rotl x, 4)
=> 0xEADBEEFD
(rotr x, 28)
=> (0xEADBEEFD)
llvm-svn: 55575
2008-08-31 00:37:27 +00:00
66ccf603a9
typo
...
llvm-svn: 55574
2008-08-30 22:16:05 +00:00
e12264bf41
fix some 80-col violations
...
llvm-svn: 55571
2008-08-30 19:29:20 +00:00
a3771d5bd9
Re-apply 55467 with fix. If copy is being replaced by remat'ed def, transfer the implicit defs onto the remat'ed instruction.
...
llvm-svn: 55564
2008-08-30 09:09:33 +00:00
542ac62971
Fold isRematerializable checks into isSafeToReMat.
...
llvm-svn: 55563
2008-08-30 09:07:18 +00:00
cfb7f3abdf
Transform (x << (y&31)) -> (x << y). This takes advantage of the fact x86 shift instructions 2nd operand (shift count) is limited to 0 to 31 (or 63 in the x86-64 case).
...
llvm-svn: 55558
2008-08-30 02:03:58 +00:00
6f0c51d9da
Fix an issue where a use might be selected before a def, and then we didn't respect the pre-chosen vreg
...
assignment when selecting the def. This is the naive solution to the problem: insert a copy to the pre-chosen
vreg. Other solutions might be preferable, such as:
1) Passing the dest reg into FastEmit_. However, this would require the higher level code to know about reg classes, which they don't currently.
2) Selecting blocks in reverse postorder. This has some compile time cost for computing the order, and we'd need to measure its impact.
llvm-svn: 55555
2008-08-30 00:38:46 +00:00
894be333f1
Fix 80 col. violations.
...
llvm-svn: 55551
2008-08-29 23:20:46 +00:00
5e7658c2e4
Back out 55498. It broken Apple style bootstrapping.
...
llvm-svn: 55549
2008-08-29 22:21:44 +00:00
d58f3e36d0
Add a target callback for FastISel.
...
llvm-svn: 55512
2008-08-28 23:21:34 +00:00
f304a7aa4d
erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics
...
llvm-svn: 55504
2008-08-28 21:40:38 +00:00
c45733f194
Implement null and undef values for FastISel.
...
llvm-svn: 55500
2008-08-28 21:19:07 +00:00
f27e33baa7
Optimize DAGCombiner's worklist processing. Previously it started
...
its work by putting all nodes in the worklist, requiring a big
dynamic allocation. Now, DAGCombiner just iterates over the AllNodes
list and maintains a worklist for nodes that are newly created or
need to be revisited. This allows the worklist to stay small in most
cases, so it can be a SmallVector.
This has the side effect of making DAGCombine not miss a folding
opportunity in alloca-align-rounding.ll.
llvm-svn: 55498
2008-08-28 21:01:56 +00:00
17da671922
Move CaseBlock, JumpTable, and BitTestBlock to be members of
...
SelectionDAGLowering instead of being in an anonymous namespace.
This fixes warnings about SelectionDAGLowering having fields
using anonymous namespaces.
llvm-svn: 55497
2008-08-28 20:38:18 +00:00
360c57f683
Fix a FastISel bug where the instructions from lowering the arguments
...
were being emitted after the first instructions of the entry block.
llvm-svn: 55496
2008-08-28 20:28:56 +00:00
6c8a99a778
Reduce the size of the Parts vector.
...
llvm-svn: 55483
2008-08-28 18:29:58 +00:00
d8a82b75e2
Hook up support for fast-isel of trunc instructions, using the newly working support for EXTRACT_SUBREG.
...
llvm-svn: 55482
2008-08-28 18:26:01 +00:00
9cd1a5e530
FastEmitInst_extractsubreg doesn't need to be passed the register class. It can get it from MachineRegisterInfo instead.
...
llvm-svn: 55476
2008-08-28 17:47:37 +00:00
04cf2e4540
Revert r55467; it causes regressions in UnitTests/Vector/divides,
...
Benchmarks/sim/sim, and others on x86-64.
llvm-svn: 55475
2008-08-28 17:22:54 +00:00
029c1c8460
Correctly resize the Parts array.
...
llvm-svn: 55471
2008-08-28 14:24:45 +00:00
6975602024
If a copy isn't coalesced, but its src is defined by trivial computation. Re-materialize the src to replace the copy.
...
llvm-svn: 55467
2008-08-28 07:53:51 +00:00
41be0d4445
Split the ATOMIC NodeType's to include the size, e.g.
...
ATOMIC_LOAD_ADD_{8,16,32,64} instead of ATOMIC_LOAD_ADD.
Increased the Hardcoded Constant OpActionsCapacity to match.
Large but boring; no functional change.
This is to support partial-word atomics on ppc; i8 is
not a valid type there, so by the time we get to lowering, the
ATOMIC_LOAD nodes looks the same whether the type was i8 or i32.
The information can be added to the AtomicSDNode, but that is the
largest SDNode; I don't fully understand the SDNode allocation,
but it is sensitive to the largest node size, so increasing
that must be bad. This is the alternative.
llvm-svn: 55457
2008-08-28 02:44:49 +00:00
e1a9a780a5
Reorganize the lifetimes of the major objects SelectionDAGISel
...
works with.
SelectionDAG, FunctionLoweringInfo, and SelectionDAGLowering
objects now get created once per SelectionDAGISel instance, and
can be reused across blocks and across functions. Previously,
they were created and destroyed each time they were needed.
This reorganization simplifies the handling of PHI nodes, and
also SwitchCases, JumpTables, and BitTestBlocks. This
simplification has the side effect of fixing a bug in FastISel
where successor PHI nodes weren't being updated correctly.
This is also a step towards making the transition from FastISel
into and out of SelectionDAG faster, and also making
plain SelectionDAG faster on code with lots of little blocks.
llvm-svn: 55450
2008-08-27 23:52:12 +00:00
5f57bc2247
Add a helper method that will be used to support EXTRACT_SUBREG for selecting trunc's in fast-isel.
...
llvm-svn: 55439
2008-08-27 22:30:02 +00:00
f016b263e2
Move the check whether it's worth remating to caller.
...
llvm-svn: 55434
2008-08-27 20:58:54 +00:00
61cfa3095d
Fix FastISel's bitcast code for the case where getRegForValue fails.
...
llvm-svn: 55431
2008-08-27 20:41:38 +00:00
57dc078570
Refactor isSafeToReMat out of 2addr pass.
...
llvm-svn: 55430
2008-08-27 20:33:50 +00:00
90609850b2
Use TargetLowering to get the types in fast isel, which handles pointer types correctly for our purposes.
...
llvm-svn: 55428
2008-08-27 18:58:30 +00:00
d01789be23
Don't check TLI.getOperationAction. The FastISel way is to
...
just try to do the action and let the tablegen-generated code
determine if there is target-support for an operation.
llvm-svn: 55427
2008-08-27 18:15:05 +00:00
b0b5a27438
Add a new FastISel method, getRegForValue, which takes care of
...
the details of materializing constants and other values into
registers, and make use of it in several places.
llvm-svn: 55426
2008-08-27 18:10:19 +00:00
f2a6c1579f
Add a comment about the current floating-point constant code in FastISel.
...
llvm-svn: 55425
2008-08-27 18:01:42 +00:00
3a3a52de58
Optimize ScheduleDAGRRList's topological sort to use one pass instead
...
of two, and to not need a scratch std::vector. Also, compute the ordering
immediately in the result array, instead of in another scratch std::vector
that is copied to the result array.
llvm-svn: 55421
2008-08-27 16:29:48 +00:00
9cbdedcbcf
Optimize ScheduleDAG's ComputeDepths and ComputeHeights to not need
...
a scratch std::vector.
llvm-svn: 55420
2008-08-27 16:27:25 +00:00
a5b15bd09b
Remove the std::ostream form of PseudoSourceValue's print,
...
which isn't needed anymore.
llvm-svn: 55419
2008-08-27 16:19:44 +00:00
5ca269e684
Basic FastISel support for floating-point constants.
...
llvm-svn: 55401
2008-08-27 01:09:54 +00:00
54aff7bb23
Fix handling of inttoptr and ptrtoint when unhandled operands are present.
...
llvm-svn: 55400
2008-08-27 00:35:37 +00:00
140549256f
Add support for fast isel of inttoptr and ptrtoint in the cases where truncation is not needed.
...
llvm-svn: 55399
2008-08-27 00:31:01 +00:00
ca1711a5b5
Factor out a large amoutn of the cast handling code in fast isel into helper methods.
...
This simultaneously makes the code simpler and adds support for sext as well.
llvm-svn: 55398
2008-08-26 23:46:32 +00:00
343310a715
Add support for fast isel of zext.
...
llvm-svn: 55396
2008-08-26 23:14:49 +00:00
abfdf928d8
disallow direct access to SDValue::ResNo, provide a getter instead
...
llvm-svn: 55394
2008-08-26 22:36:50 +00:00
655c1dc63d
Add support for fptosi of constants in fast isel.
...
llvm-svn: 55393
2008-08-26 22:34:28 +00:00
d56f73f2f2
Optimize SelectionDAG's topological sort to use one pass instead
...
of two, and to not need a scratch std::vector. Also, use the
SelectionDAG's topological sort in LegalizeDAG instead of having
a separate implementation.
llvm-svn: 55389
2008-08-26 21:42:18 +00:00
6fda9208d9
Refactor the bitcast code into its own function.
...
llvm-svn: 55387
2008-08-26 21:28:54 +00:00
b5e04bfb18
Make FastISel use the correct argument type when casting GEP indices.
...
llvm-svn: 55384
2008-08-26 20:57:08 +00:00
3bcbbece19
Don't select binary instructions with illegal types.
...
llvm-svn: 55383
2008-08-26 20:52:40 +00:00
3c4dc434ee
Add support for fast isel of sitofp, and remove some unnecessary and imprecise legality checks.
...
llvm-svn: 55381
2008-08-26 20:37:00 +00:00
e0ac9765b2
Use a combination of copyRegToReg and ISD::BIT_CONVERT when doing fast isel of bitcasts,
...
allowing it to support the full range of conversions people might ask for in a correct manner.
llvm-svn: 55378
2008-08-26 18:51:24 +00:00
27fb3dcbc7
Make TargetInstrInfo::copyRegToReg return a bool indicating whether the copy requested
...
was inserted or not. This allows bitcast in fast isel to properly handle the case
where an appropriate reg-to-reg copy is not available.
llvm-svn: 55375
2008-08-26 18:03:31 +00:00
bf05ebaccf
Add support for fast isel of non-constant fptosi instructions.
...
llvm-svn: 55373
2008-08-26 17:44:42 +00:00
54ef9f5831
typo fix.
...
llvm-svn: 55355
2008-08-26 06:07:47 +00:00
2e834906b9
Actually recycle SDNode allocations. SelectionDAG is using
...
RecyclingAllocator, but this change is needed for the nodes
to actually be recycled. This cuts SelectionDAG's memory
usage high-water-mark in half in some cases.
llvm-svn: 55351
2008-08-26 01:44:34 +00:00
8dd01ccdd8
Add a RetVT parameter to emitted FastISel methods, so that we will be able to pass the desired return
...
type down. This is not currently used.
llvm-svn: 55345
2008-08-25 23:58:18 +00:00
2c067325d6
Unbreak build.
...
llvm-svn: 55342
2008-08-25 22:20:39 +00:00
126afc5cb9
Expand bitcast support in fast isel to support bitcasts of non-constant values by emitting reg-reg copies.
...
llvm-svn: 55340
2008-08-25 21:32:34 +00:00
32635dbfb2
Add support for fast isel of (integer) immediate materialization pattens, and use them to support
...
bitcast of constants in fast isel.
llvm-svn: 55325
2008-08-25 20:20:32 +00:00
a078d83e17
simplify PseudoSourceValue printing a bit. Unnest all of PseudoSourceValue.cpp from the llvm namespace.
...
llvm-svn: 55293
2008-08-24 20:37:32 +00:00
72e7d91591
Print PseudoSourceValue.
...
llvm-svn: 55291
2008-08-24 18:51:20 +00:00
f4bd5cf3dd
make sure to flush the stream after dumping, to make sure it goes out immediately.
...
llvm-svn: 55288
2008-08-24 18:28:30 +00:00
838aff36dd
get MachineConstantPool off std::ostream, onto raw_ostream. It would be
...
really nice if someone converted MachineFunction::print to raw_ostream.
llvm-svn: 55268
2008-08-23 22:53:13 +00:00
0c19df4871
Switch the asmprinter (.ll) and all the stuff it requires over to
...
use raw_ostream instead of std::ostream. Among other goodness,
this speeds up llvm-dis of kc++ with a release build from 0.85s
to 0.49s (88% faster).
Other interesting changes:
1) This makes Value::print be non-virtual.
2) AP[S]Int and ConstantRange can no longer print to ostream directly,
use raw_ostream instead.
3) This fixes a bug in raw_os_ostream where it didn't flush itself
when destroyed.
4) This adds a new SDNode::print method, instead of only allowing "dump".
A lot of APIs have both std::ostream and raw_ostream versions, it would
be useful to go through and systematically anihilate the std::ostream
versions.
This passes dejagnu, but there may be minor fallout, plz let me know if
so and I'll fix it.
llvm-svn: 55263
2008-08-23 22:23:09 +00:00
48a3623591
Make MBBMap a DenseMap instead of a std::map.
...
llvm-svn: 55220
2008-08-23 02:44:46 +00:00
eb0cee91f6
Move the point at which FastISel taps into the SelectionDAGISel
...
process up to a higher level. This allows FastISel to leverage
more of SelectionDAGISel's infastructure, such as updating Machine
PHI nodes.
Also, implement transitioning from SDISel back to FastISel in
the middle of a block, so it's now possible to go back and
forth. This allows FastISel to hand individual CallInsts and other
complicated things off to SDISel to handle, while handling the rest
of the block itself.
To help support this, reorganize the SelectionDAG class so that it
is allocated once and reused throughout a function, instead of
being completely reallocated for each block.
llvm-svn: 55219
2008-08-23 02:25:05 +00:00
95d1056831
Avoid creating shift-by-zero SDNodes in the common case of
...
i8* getelementptr. DAGCombine eliminates these, but this is
a fairly common case.
llvm-svn: 55214
2008-08-23 01:06:51 +00:00
ac37f9a9be
Move SelectionDAG's constructor out of line.
...
llvm-svn: 55212
2008-08-23 00:50:30 +00:00
2db3f8a095
Reapply r55191 and r55192.
...
llvm-svn: 55205
2008-08-22 21:28:19 +00:00
fc4f64eed0
Reverting r55190, r55191, and r55192. They broke the build with this error message:
...
{standard input}:17:bad register name `%sil'
make[4]: *** [libgcc/./_addvsi3.o] Error 1
make[4]: *** Waiting for unfinished jobs....
{standard input}:23:bad register name `%dil'
{standard input}:28:bad register name `%dil'
make[4]: *** [libgcc/./_addvdi3.o] Error 1
{standard input}:18:bad register name `%sil'
make[4]: *** [libgcc/./_subvsi3.o] Error 1
llvm-svn: 55200
2008-08-22 20:51:05 +00:00
04968da460
Fix the InsertBranch call.
...
llvm-svn: 55192
2008-08-22 19:26:10 +00:00
87ff7058e7
Support non-fallthrough unconditional branches in FastISel.
...
llvm-svn: 55191
2008-08-22 19:21:41 +00:00
a2292c0d34
Add FastISel support for PHINodes. Machine PHI nodes
...
are not yet updated properly, but that's a separate
task.
llvm-svn: 55187
2008-08-22 17:37:48 +00:00
14714cb4fa
Fix SmallVector's size calculation so that a size of 0 is
...
handled correctly, and change a few SmallVector uses to use
size 0 to more clearly reflect their intent.
llvm-svn: 55181
2008-08-22 16:07:55 +00:00
5fc8ab6d18
consolidate DenseMapInfo implementations, and add one for std::pair.
...
Patch contributed by m-s.
llvm-svn: 55167
2008-08-22 05:08:25 +00:00
49e19e906f
Factor out the predicate check code from DAGISelEmitter.cpp
...
and use it in FastISelEmitter.cpp, and make FastISel
subtarget aware. Among other things, this lets it work
properly on x86 targets that don't have SSE, where it
successfully selects x87 instructions.
llvm-svn: 55156
2008-08-22 00:20:26 +00:00
25084af26a
Remove tabs.
...
llvm-svn: 55154
2008-08-22 00:04:26 +00:00
893ce348a7
Remove unneeded #include.
...
llvm-svn: 55134
2008-08-21 19:51:25 +00:00
2af34bd309
Add libcalls for the new rounding opcodes.
...
llvm-svn: 55133
2008-08-21 18:38:14 +00:00
c6337ac069
Add libm-oriented ISD opcodes for rounding operations.
...
llvm-svn: 55130
2008-08-21 17:55:02 +00:00
6a7461ad9b
Have FastISel skip the multiply by 1 for getelementptr on i8*.
...
llvm-svn: 55129
2008-08-21 17:37:05 +00:00
efb7d2d03d
MVT::getMVT uses iPTR for pointer types, while we need the actual
...
intptr_t type in this case. FastISel can now select simple
getelementptr instructions.
llvm-svn: 55125
2008-08-21 17:25:26 +00:00
75ea0b83c5
Elements in DeadNodeSet are checked for use_empty() before they
...
are actually deleted, so it's not necessary to remove re-used
nodes from the set.
llvm-svn: 55123
2008-08-21 16:24:54 +00:00
fe9056584b
Basic fast-isel support for instructions with constant int operands.
...
llvm-svn: 55099
2008-08-21 01:41:07 +00:00
4b5c038cd0
Type of first GEP operand is always the same as the target pointer type.
...
llvm-svn: 55097
2008-08-21 01:19:11 +00:00
9371964f47
Use raw_ostream throughout the AsmPrinter.
...
llvm-svn: 55092
2008-08-21 00:14:44 +00:00
6a0780cdd7
Fix unused variable warnings.
...
llvm-svn: 55089
2008-08-20 23:53:10 +00:00
864fcc198d
First cut, un-optimized (and untested) fast isel lowering of GetElementPtrInst.
...
llvm-svn: 55085
2008-08-20 22:45:34 +00:00
a4305cec93
Simplify the BuildMI calls even more.
...
llvm-svn: 55077
2008-08-20 21:10:53 +00:00
02c84b8910
Simplify FastISel's constructor argument list, make the FastISel
...
class hold a MachineRegisterInfo member, and make the
MachineBasicBlock be passed in to SelectInstructions rather
than the FastISel constructor.
llvm-svn: 55076
2008-08-20 21:05:57 +00:00
43d1c7c607
Dump the instruction that foiled ISel even when -debug is not used.
...
llvm-svn: 55075
2008-08-20 20:47:32 +00:00
cd01e89852
Don't hoist instructions that define a physical register.
...
llvm-svn: 55074
2008-08-20 20:32:05 +00:00
07a34a5f69
Make more use of the BuildMI API.
...
llvm-svn: 55072
2008-08-20 18:16:32 +00:00
24e8f0cfe6
Minor code reorganization.
...
llvm-svn: 55071
2008-08-20 18:10:48 +00:00
2471f6ce0f
Minor whitespace cleanup.
...
llvm-svn: 55070
2008-08-20 18:09:38 +00:00
39a5ffb03f
Fix 80 column violation.
...
llvm-svn: 55069
2008-08-20 18:09:02 +00:00
7b9cd58596
Kill off SimpleBBISel, it's replaced by FastISel.
...
llvm-svn: 55067
2008-08-20 17:50:32 +00:00
837c13a029
Disable DAGCombine's alignment inference in "fast" codegen mode.
...
llvm-svn: 55059
2008-08-20 16:30:28 +00:00
2da2bedc72
Change the FoldingSetNodeID usage for objects which carry
...
alignment and volatility information, such as loads and
stores, to reduce the number of integer values added to
the FoldingSetNodeID.
llvm-svn: 55058
2008-08-20 15:58:01 +00:00
f6aa60ff71
Use BitVector instead of std::vector<unsigned char>.
...
llvm-svn: 55054
2008-08-20 14:58:41 +00:00
c63a46ef39
Avoid an empty-if-body warning in release builds.
...
llvm-svn: 55050
2008-08-20 14:00:56 +00:00
1ed0681284
Fix indentation.
...
llvm-svn: 55049
2008-08-20 13:50:12 +00:00
e8f9a00424
Fix FastISel to recognize that the last block in the function does
...
not have a fall-through successor.
llvm-svn: 55033
2008-08-20 01:17:01 +00:00
98265cae87
Fix a leak in the FastISel code that Chris pointed out.
...
llvm-svn: 55031
2008-08-20 00:56:17 +00:00
847ebb90b8
Add support for running SelectionDAG if FastISel fails. This is under
...
a command-line option, so that the default behavior is an abort, which
is useful for exposing code that isn't supported yet.
llvm-svn: 55028
2008-08-20 00:47:54 +00:00
f6884373c2
Fix FastISel to recognize unhandled operands, such as constants
...
that aren't available as virtual registers (for now).
llvm-svn: 55026
2008-08-20 00:35:17 +00:00
b16a7783c5
Add FastISel support for floating-point operations.
...
llvm-svn: 55021
2008-08-20 00:23:20 +00:00
a3e4d5a5e1
Add FastISel support for several more binary operators.
...
llvm-svn: 55020
2008-08-20 00:11:48 +00:00
697284fe0a
Add code to call FastISel, and a command-line option to enable it.
...
llvm-svn: 55015
2008-08-19 22:33:34 +00:00
214343fbbe
Support unconditional fall-through branches in FastISel.
...
llvm-svn: 55014
2008-08-19 22:31:46 +00:00
2a458775db
Allow the fast-path spilling code to attempt folding, but still leaving out remat and splitting.
...
llvm-svn: 55012
2008-08-19 22:12:11 +00:00
547ce65467
Use the BuildMI overload that sets up a destination register
...
instead of the one that doesn't and then adding it manually.
llvm-svn: 55006
2008-08-19 20:46:54 +00:00
c55fdcc935
Handle the case where target-specific fastisel code doesn't have
...
a desired opcode.
llvm-svn: 55005
2008-08-19 20:43:22 +00:00
c75ae13566
The fast-path still needs to set kill markers and spill/restore points as appropriate.
...
With this patch, all of MultiSource/Applications and all of SPEC2000/2006 pass with
the SimpleSpiller and this fast-path enabled.
llvm-svn: 55000
2008-08-19 20:09:52 +00:00
1298fb90d3
Delete a dead field.
...
llvm-svn: 54995
2008-08-19 17:09:26 +00:00
72bd9dfdad
[PR2327] Leverage TargetRegisterInfo to compute frame offsets for GC metadata.
...
llvm-svn: 54994
2008-08-19 17:06:35 +00:00
5d2a9a4ae6
don't use the result of WriteTypeSymbolic or WriteAsOperand.
...
llvm-svn: 54978
2008-08-19 04:44:30 +00:00
7f3bfbd23b
Make SimpleSpiller respect subregister indices.
...
llvm-svn: 54968
2008-08-19 01:05:33 +00:00
442dc6fed0
Add a flag to enable the fast spilling path.
...
llvm-svn: 54958
2008-08-19 00:17:30 +00:00
a57c57067d
Fix a few more bugs:
...
1) Assign stack slots to new temporaries.
2) Don't insert an interval into the return vector more than once.
llvm-svn: 54956
2008-08-18 23:41:04 +00:00
60f6b2cac0
Fix several bugs in the new fast-path:
...
1) Remove an incorrect assertion.
2) Set the stack slot weight properly.
3) Resize the VirtRegMap when needed.
llvm-svn: 54949
2008-08-18 21:20:32 +00:00
e996a12f27
Clients of addIntervalForSpills expect the added intervals to be returned sorted by starting index.
...
llvm-svn: 54939
2008-08-18 19:52:22 +00:00
75e27d2402
Simplify the fast-patch interval spilling by using MachineRegisterInfo::reg_iterator.
...
llvm-svn: 54930
2008-08-18 18:38:12 +00:00
cc9314ba32
Resurrect some ancient code to add spill ranges without attempting folding, remat, or splitting. This code has been updated to current APIs
...
in so far as it compiles and, in theory, works, but does not take advantage of recent advancements. For instance, it could be improved by using
MachineRegisterInfo::use_iterator.
llvm-svn: 54924
2008-08-18 18:05:32 +00:00
cf596eb12f
Don't hoist instructions that have implicit uses or defines. Before, it was
...
hoisting out some "test" and "cmp" instructions. This was obvious badness.
llvm-svn: 54908
2008-08-18 00:33:49 +00:00
aa8ab4501a
Don't require Registry specializations to define random static variables.
...
llvm-svn: 54902
2008-08-17 19:08:34 +00:00
86e7d0a1df
Drop an unnecessary include.
...
llvm-svn: 54901
2008-08-17 18:54:05 +00:00
d930f913e6
Rename some GC classes so that their roll will hopefully be clearer.
...
In particular, Collector was confusing to implementors. Several
thought that this compile-time class was the place to implement
their runtime GC heap. Of course, it doesn't even exist at runtime.
Specifically, the renames are:
Collector -> GCStrategy
CollectorMetadata -> GCFunctionInfo
CollectorModuleMetadata -> GCModuleInfo
CollectorRegistry -> GCRegistry
Function::getCollector -> getGC (setGC, hasGC, clearGC)
Several accessors and nested types have also been renamed to be
consistent. These changes should be obvious.
llvm-svn: 54899
2008-08-17 18:44:35 +00:00
e431adbfc7
Don't instantiate GC metadata for declarations.
...
llvm-svn: 54895
2008-08-17 16:18:50 +00:00
afbc02ba50
Fix merge error
...
llvm-svn: 54891
2008-08-17 13:56:03 +00:00
9cb0e94dc7
Move all assembler printing related stuff into new libAsmPrinter
...
llvm-svn: 54885
2008-08-17 13:53:04 +00:00
f01991a0d4
Factor out asmprinters from collector interface.
...
llvm-svn: 54884
2008-08-17 13:52:35 +00:00
bcef14d2e4
Factor GC metadata table assembly generation out of Collector in preparation for splitting AsmPrinter into its own library.
...
llvm-svn: 54881
2008-08-17 12:56:54 +00:00
dbe06d3b69
Factor GC metadata table assembly generation out of Collector in preparation for splitting AsmPrinter into its own library.
...
llvm-svn: 54880
2008-08-17 12:08:44 +00:00
17f7165f84
Rework the routines that convert AP[S]Int into a string. Now, instead of
...
returning an std::string by value, it fills in a SmallString/SmallVector
passed in. This significantly reduces string thrashing in some cases.
More specifically, this:
- Adds an operator<< and a print method for APInt that allows you to
directly send them to an ostream.
- Reimplements APInt::toString to be much simpler and more efficient
algorithmically in addition to not thrashing strings quite as much.
This speeds up llvm-dis on kc++ by 7%, and may also slightly speed up the
asmprinter. This also fixes a bug I introduced into the asmwriter in a
previous patch w.r.t. alias printing.
llvm-svn: 54873
2008-08-17 07:19:36 +00:00
bd890b1faf
Move SLEB/ULEB size calculation routines from AsmPrinter to TargetAsmInfo. This makes JIT asmprinter-free.
...
llvm-svn: 54843
2008-08-16 12:57:46 +00:00
d669b9b671
Convert several std::vectors over to SmallVector, and use reserve() as appropriate for cases where std::vector is still used.
...
llvm-svn: 54820
2008-08-15 18:49:41 +00:00
14738120ba
Use SmallSet instead of std::set to save allocations.
...
llvm-svn: 54810
2008-08-14 23:41:38 +00:00
96631091df
Move MachineInstr::getOpcode inline.
...
llvm-svn: 54807
2008-08-14 23:25:30 +00:00
4f6bf04616
Convert uses of std::vector in TargetInstrInfo to SmallVector. This change had to be propoagated down into all the targets and up into all clients of this API.
...
llvm-svn: 54802
2008-08-14 22:49:33 +00:00
c44423853a
Make FastISel's constructor protected, and give it a destructor.
...
llvm-svn: 54793
2008-08-14 21:51:29 +00:00
1b351d42bb
Remove more uses of std::set.
...
llvm-svn: 54787
2008-08-14 21:01:00 +00:00
550c9af91f
Improve support for vector casts in LLVM IR and CodeGen.
...
llvm-svn: 54784
2008-08-14 20:04:46 +00:00
fa8b2ea41b
Speed up addRegisterDead by adding more fast checks before performing the expensive
...
subregister query, and by increasing the size of the subregister hashtable so
that there are fewer collisions.
llvm-svn: 54781
2008-08-14 18:34:18 +00:00
8de6d22392
Use empty() instead of begin() == end().
...
llvm-svn: 54780
2008-08-14 18:13:49 +00:00
99e911fb16
Get rid of a use of std::map.
...
llvm-svn: 54770
2008-08-13 23:36:23 +00:00
6134fbccef
Fix a bogus srem rule - a negative value srem'd by a power-of-2
...
can have a non-negative result; for example, -16%16 is 0. Also,
clarify the related comments. This fixes PR2670.
llvm-svn: 54767
2008-08-13 23:12:35 +00:00
706f6b7899
Expunge the last uses of std::map from LiveIntervals.
...
llvm-svn: 54766
2008-08-13 22:28:50 +00:00
767b5cc7fd
Move r2iMap_ over to DenseMap from std::map.
...
llvm-svn: 54765
2008-08-13 22:08:30 +00:00
7e3c392248
Allow SelectionDAG to create EXTRACT_VECTOR_ELT nodes with
...
non-constant indices. Only a few of the peephole checks require
a constant index.
llvm-svn: 54764
2008-08-13 21:51:37 +00:00
51f689a652
Make the allocation of LiveIntervals explicit, rather than holding them in the r2iMap_ by value. This will prevent references to them from being invalidated
...
if the map is changed.
llvm-svn: 54763
2008-08-13 21:49:13 +00:00
b2226e21c3
Initial checkin of the new "fast" instruction selection support. See
...
the comments in FastISelEmitter.cpp for details on what this is.
This is currently experimental and unusable.
llvm-svn: 54751
2008-08-13 20:19:35 +00:00
a7b8aed469
Rename SelectionDAGISel's FastISel to Fast, to begin to make
...
room for the new FastISel instruction selection code.
llvm-svn: 54749
2008-08-13 19:47:40 +00:00
ef96ac4f95
Get rid of unused variable.
...
llvm-svn: 54742
2008-08-13 17:44:52 +00:00
65fce4d813
1) Merge entire live intervals instead of parts of them.
...
2) Conditionalize temporary insertion if we don't need it.
llvm-svn: 54741
2008-08-13 17:25:42 +00:00
23785a1679
Correct the filename in the top-of-file comment.
...
llvm-svn: 54688
2008-08-12 17:42:33 +00:00
127bb03b8c
Take the FrameOffset into account when computing the alignment
...
of stack objects. This fixes PR2656.
llvm-svn: 54646
2008-08-11 18:27:03 +00:00
ada201c8c1
Fix some typos. Apparently I think C needs a power-of operator.
...
llvm-svn: 54574
2008-08-09 03:48:46 +00:00
5927883970
Have IRBuilder take a template argument on whether or not to preserve
...
names. This can save a lot of allocations if you aren't going to be
looking at the output.
llvm-svn: 54546
2008-08-08 19:39:37 +00:00
ed47329174
Handle visibility printing with all generality. Remove bunch of duplicate code.
...
llvm-svn: 54540
2008-08-08 18:25:07 +00:00
dfb0b6952a
Reduce the entries in a phi before testing it for deadness, because removing the entries might make it dead.
...
llvm-svn: 54535
2008-08-08 18:00:05 +00:00
38aa7de6e9
Add skeleton of simple basic block instruction selector.
...
llvm-svn: 54522
2008-08-08 07:27:28 +00:00
42a19b6933
Don't crash printing the asm for a ConstantExpr PtrToInt just because the int
...
is narrower than the pointer. This testcase emits:
.byte (((17) - 16) & 255)
llvm-svn: 54517
2008-08-08 06:34:07 +00:00
de5161fdf2
Add the remaining fp_round libcalls:
...
FPROUND_F80_F32, FPROUND_PPCF128_F32,
FPROUND_F80_F64, FPROUND_PPCF128_F64
Support for soften float fp_round operands is added, Mips
needs this to round f64->f32.
Also added support to soften float FABS result, Mips doesn't
support double fabs results while in 'single float only' mode.
llvm-svn: 54484
2008-08-07 19:01:24 +00:00
d172c15ab0
Do a dominator walk when scheduling copies, rather than a DFS on the CFG. Also, fix a few problems when creating
...
live intervals for temporaries created by phi elimination.
llvm-svn: 54483
2008-08-07 18:28:07 +00:00
527ca7e253
Re-enable elimination of unnecessary SUBREG_TO_REG instructions in
...
LowerSubregs, and fix an x86-64 isel bug that this exposed.
SUBREG_TO_REG for x86-64 implicit zero extension is only safe for
isel to generate when the source is known to always have zeros in
the high 32 bits. The EXTRACT_SUBREG instruction does not clear
the high 32 bits.
llvm-svn: 54444
2008-08-07 02:54:50 +00:00
0638115a6e
Factor code that finalize PHI nodes, jump tables, etc. out of SelectBasicBlock. No functionality changes.
...
llvm-svn: 54438
2008-08-07 00:43:25 +00:00
c6d527067b
SDISel's constant branch folding can fold away self-loops, which doesn't result in any dead blocks, but
...
rather an incorrect phi input. Add code to UnreachableMachineBlockElim to get rid of these entries.
llvm-svn: 54432
2008-08-06 23:16:52 +00:00
8a8d6f0a78
Correct handle cases where two phis are coalesced together, and correct break up the case where two different
...
phis want to coalesce with the same vreg.
llvm-svn: 54426
2008-08-06 22:08:58 +00:00
d184929176
Oops, didn't mean to commit this.
...
llvm-svn: 54425
2008-08-06 20:58:38 +00:00
987b5057d3
We don't need to try to coalesce input vregs that are the same as the output vreg.
...
llvm-svn: 54422
2008-08-06 20:29:20 +00:00
f9fca2f2dc
Only trim a live interval if the register is not used after the PHI node.
...
llvm-svn: 54421
2008-08-06 18:36:17 +00:00
03dddbbed5
Only remap each VNInfo once when doing renumbering.
...
llvm-svn: 54420
2008-08-06 18:35:45 +00:00
3d4c06dd54
Fix breakage on ARM/2008-04-10-ScavengerAssert.ll.
...
llvm-svn: 54378
2008-08-05 22:24:40 +00:00
aa33b932bd
Fix PR2596: out of bound reference.
...
llvm-svn: 54375
2008-08-05 21:51:46 +00:00
bdaed55ef3
Correctly handle replacement and removal of PHIs with one incoming register.
...
llvm-svn: 54374
2008-08-05 21:40:45 +00:00
d9b88a85f2
Oops, we were already checking for dead phis. Handle this the proper way, then.
...
llvm-svn: 54371
2008-08-05 21:18:51 +00:00
d4ffa4eb57
We don't need to update live intervals for dead PHIs.
...
llvm-svn: 54369
2008-08-05 20:51:26 +00:00
7c42ac4133
Remove the -disable-correct-folding option, which was ugly and is no longer needed.
...
llvm-svn: 54361
2008-08-05 18:27:54 +00:00
e955c481fd
Fix several const-correctness issues, resolving some -Wcast-qual warnings.
...
llvm-svn: 54349
2008-08-05 14:45:15 +00:00
a4d6d884d6
Remove #if 0.
...
llvm-svn: 54347
2008-08-05 07:20:57 +00:00
0ca10c9572
Fix PR2568: Fix bug that cause redudant kill marker after its live interval has been extended due to coalescing.
...
llvm-svn: 54346
2008-08-05 07:10:38 +00:00
9f515394d3
Remove unneeded iteration. Thanks to Dan for the feedback.
...
llvm-svn: 54337
2008-08-05 00:30:10 +00:00
bbeb8f0807
This option doesn't need to be a target option. It can be in SDISel instead.
...
llvm-svn: 54336
2008-08-05 00:27:28 +00:00
a102290bdc
- Fix SelectionDAG to generate correct CFGs.
...
- Add a basic machine-level dead block eliminator.
These two have to go together, since many other parts of the code generator are unable to handle the unreachable blocks otherwise created.
llvm-svn: 54333
2008-08-04 23:54:43 +00:00
90c724cadc
Fix SDISel lowering of PHI nodes to use ComputeValueVTs.
...
This allows it to work correctly on aggregate values.
This fixes PR2623.
llvm-svn: 54331
2008-08-04 23:42:46 +00:00
6e023e63cd
Fix SDISel lowering of zeroinitializer and undef to use ComputeValueVTs.
...
This allows it to work correctly on nested aggregate values.
This fixes PR2625.
llvm-svn: 54330
2008-08-04 23:30:41 +00:00
c31eb205c1
Add a flag to disable jump table generation (all
...
switches use the binary search algorithm) for
environments that don't support it. PPC64 JIT
is such an environment; turn the flag on for that.
llvm-svn: 54248
2008-07-31 18:13:12 +00:00
345d63ccf2
Improve dagcombining for sext-loads and sext-in-reg nodes.
...
llvm-svn: 54239
2008-07-31 00:50:31 +00:00
88e0df0c91
Move SelectionDAG::viewGraph() out of line; as an inline function
...
it isn't always visible to gdb.
llvm-svn: 54228
2008-07-30 18:48:53 +00:00
2fe4352691
Don't look for leaf values to store when lowering stores of
...
empty structs. This fixes PR2612.
llvm-svn: 54226
2008-07-30 18:36:51 +00:00
c818c01539
Use existing LiveInterval methods to simplify live interval merging. Thanks to Evan for pointing these out.
...
llvm-svn: 54225
2008-07-30 18:27:35 +00:00
7b5f535590
Value numbers whose def index is a special sentinel value should not be remapped.
...
llvm-svn: 54218
2008-07-30 17:42:47 +00:00
e9a0bae238
More fixes for corner cases when remapping live range indices.
...
llvm-svn: 54186
2008-07-30 00:22:56 +00:00
1aebe49ae7
When merging live intervals, we also need to merge in any live ranges that are inputs to two-address instructions
...
that themselves define a range we already care about.
llvm-svn: 54185
2008-07-30 00:21:16 +00:00
6b1cc46fee
When merging a PHI operand's live interval into the PHI's live interval, we need to merge over all liveranges in
...
the operand's interval that share the relevant value number, not just the range that immediately precedes the PHI.
llvm-svn: 54174
2008-07-29 21:17:08 +00:00
2532e75933
Don't decrement the BB remap when we don't need to.
...
llvm-svn: 54173
2008-07-29 21:15:44 +00:00
fa4120530e
Fix PR2609. If a label is deleted, then it needs
...
to be marked invalid regardless of whether it is
a debug, an exception handling or (hopefully) a
GC label.
llvm-svn: 54172
2008-07-29 20:56:02 +00:00
82f1925708
Fix broken CellSPU lowering, re-instate braces in Legalize
...
llvm-svn: 54168
2008-07-29 19:07:27 +00:00
d63495ff25
Disable a fix in the previous patch, since it breaks CellSPU.
...
The CellSPU codegen is broken, but needs to be fixed before we can
put this back in.
llvm-svn: 54164
2008-07-29 18:28:31 +00:00
fecbc8cff1
Add vector shifts to the IR, patch by Eli Friedman.
...
CodeGen & Clang work coming next.
llvm-svn: 54161
2008-07-29 15:49:41 +00:00
804c95df52
Fold the useful features of alist and alist_node into ilist, and
...
a new ilist_node class, and remove them. Unlike alist_node,
ilist_node doesn't attempt to manage storage itself, so it avoids
the associated problems, including being opaque in gdb.
Adjust the Recycler class so that it doesn't depend on alist_node.
Also, change it to use explicit Size and Align parameters, allowing
it to work when the largest-sized node doesn't have the greatest
alignment requirement.
Change MachineInstr's MachineMemOperand list from a pool-backed
alist to a std::list for now.
llvm-svn: 54146
2008-07-28 21:51:04 +00:00
24b3ce1db6
Fix a typo in a comment.
...
llvm-svn: 54136
2008-07-28 18:43:51 +00:00
68e45a361b
Make the ScheduleDAG's GraphRoot edge be blue and dashed too, like
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the SelectionDAG's.
llvm-svn: 54129
2008-07-27 22:46:49 +00:00
2ce6f2ad5e
Rename SDOperand to SDValue.
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llvm-svn: 54128
2008-07-27 21:46:04 +00:00
91e5dcb680
Tidy SDNode::use_iterator, and complete the transition to have it
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parallel its analogue, Value::value_use_iterator. The operator* method
now returns the user, rather than the use.
llvm-svn: 54127
2008-07-27 20:43:25 +00:00
bb5f43ed4d
Rename isOnlyUseOf to isOnlyUserOf.
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llvm-svn: 54124
2008-07-27 18:06:42 +00:00
d9374421ea
Some binary operations were being treated as
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unary operations! Add support for softening
some additional unary operations like fp_to_sint.
llvm-svn: 54122
2008-07-27 12:28:43 +00:00
54912b3e8d
Fix the issues originally addressed in r54070. After thinking about it some more, I realized that the right thing to do
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is to have StrongPHIElimination use its knowledge of the PHIs before they're erased to update the intervals appropriate. This is
both simpler and more accurate than the alternative, which was having LIA figure it out when it renumbered things, plus it's just
the right thing to do!
llvm-svn: 54077
2008-07-25 23:38:08 +00:00
7a45b168ac
Revert my previous patch. In retrospect, this is completely the wrong way to fix this problem.
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llvm-svn: 54072
2008-07-25 23:06:59 +00:00
074f9db2fd
Special cases are needed in renumbering when dealing with renumbering after a PHI has been removed. The interval previously defined
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by the PHI needs to be extended to the beginning of its basic block, and the intervals that were inputs need to be trimmed to the end
of their basic blocks.
llvm-svn: 54070
2008-07-25 22:32:01 +00:00
0346aba5c2
In order to avoid reprocessing a register more than once, we need to add it
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to the handled set so it will get filtered out in future iterations.
llvm-svn: 54065
2008-07-25 21:35:43 +00:00
d9c8711d70
Remove live interval entries for an interval if we're eliminating its only VN.
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llvm-svn: 54062
2008-07-25 21:08:41 +00:00
88499a3503
Properly remap live ranges whose end indices are the end of the function.
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llvm-svn: 54061
2008-07-25 21:07:13 +00:00
c7d53fd331
Make the remapping of interval indices (particularly ending indices) more robust.
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This is tricky business, and will probably take a few more iterations to get
the last kinks out of it.
llvm-svn: 54043
2008-07-25 19:50:48 +00:00
394ec3ab5a
Disable the new aggressive remat logic introduced in 54000; it causes some
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regressions, such as PR2595. Also, there is a significant code-quality
issue in SPEC 464.h264ref and a few others.
llvm-svn: 54014
2008-07-25 15:08:37 +00:00
7334350d31
When splitting a vector shuffle, fixed which type we used for the hi part
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llvm-svn: 54007
2008-07-25 01:30:26 +00:00
9268601d8a
Use AliasAnalysis::pointsToConstantMemory in SDISel to avoid unnecessary
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dependencies with constant load nodes. This allows them to be scheduled
freely.
llvm-svn: 54001
2008-07-25 00:04:14 +00:00
09b0448dbc
Enable rematerialization of constants using AliasAnalysis::pointsToConstantMemory,
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and knowledge of PseudoSourceValues. This unfortunately isn't sufficient to allow
constants to be rematerialized in PIC mode -- the extra indirection is a
complication.
llvm-svn: 54000
2008-07-25 00:02:30 +00:00
79b66966b8
Store the predecessor MBB in the PHIUnion, rather than an index, since the indices will change after renumbering.
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llvm-svn: 53985
2008-07-24 17:12:16 +00:00
50d393a68d
Enable the insertion of empty indices into LiveInterals, thereby making renumbering possible.
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llvm-svn: 53961
2008-07-23 21:37:49 +00:00
7c800ad977
Fix a compile-time regression introduced by my heuristic-changing patch. I forgot
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to multiply the instruction count by a constant factor in a few places, which
caused the register allocator to require many more iterations.
llvm-svn: 53959
2008-07-23 19:47:27 +00:00
Chris Lattner