2d0175e8fb
Add MC assembly/disassembly support for VCVT{A, N, P, M} to V8FP.
...
llvm-svn: 185922
2013-07-09 09:59:04 +00:00
2efaa733a2
Add MC support for the v8fp instructions: vmaxnm and vminnm.
...
llvm-svn: 185767
2013-07-06 20:50:18 +00:00
cc4ff9e907
Add support for MC assembling and disassembling of vsel{ge, gt, eq, vs} instructions.
...
This adds a new decoder table/namespace 'VFPV8', as these instructions have their
top 4 bits as 0b1111, while other Thumb instructions have 0b1110.
llvm-svn: 185642
2013-07-04 14:57:20 +00:00
39f7488294
Add a V8FP instruction 'vcvt{b,t}' to convert between half and double precision.
...
llvm-svn: 185620
2013-07-04 10:04:08 +00:00
d36cbaa423
This corrects the implementation of Thumb ADR instruction. There are three issues:
...
1. it should accept only 4-byte aligned addresses
2. the maximum offset should be 1020
3. it should be encoded with the offset scaled by two bits
llvm-svn: 185528
2013-07-03 09:21:44 +00:00
263c6af8f3
[mips] Increase the number of floating point control registers available to 32.
...
Create a dedicated register class for floating point condition code registers and
move FCC0 from register class CCR to the new register class.
llvm-svn: 185373
2013-07-01 20:31:44 +00:00
253777fdc3
[Mips Disassembler] Have the DecodeCCRRegisterClass function use the getReg
...
function to lookup the proper tablegen'ed register enumeration. Previously,
it was using the encoded value directly.
llvm-svn: 185026
2013-06-26 22:23:32 +00:00
a6f5542be4
ARM: operands should be explicit when disassembled
...
llvm-svn: 184943
2013-06-26 13:39:07 +00:00
8449c0d5ed
ARM: check predicate bits for thumb instructions
...
When encoded to thumb, VFP instruction and VMOV/VDUP between scalar and
core registers, must have their predicate bit to 0b1110.
llvm-svn: 184707
2013-06-24 09:15:01 +00:00
8175bda3db
ARM: rGPR is meant to be unpredictable, not undefined
...
llvm-svn: 184706
2013-06-24 09:14:54 +00:00
f2f00b4e28
ARM: fix thumb1 nop decoding
...
In thumb1, NOP is a pseudo-instruction equivalent to mov r8, r8.
However the disassembler should not use this alias.
llvm-svn: 184703
2013-06-24 09:11:53 +00:00
2f0ac8d961
ARM: fix IT decoding
...
mask == 0 -> UNPRED
llvm-svn: 184702
2013-06-24 09:11:45 +00:00
4b6c076da3
ARM: enable decoding of pc-relative PLD/PLI
...
llvm-svn: 184701
2013-06-24 09:11:38 +00:00
35fd79237f
Update the X86 disassembler to use xacquire and xrelease when appropriate.
...
This is a bit tricky as the xacquire and xrelease hints use the same bytes,
0xf2 and 0xf3, as the repne and rep prefixes.
Fortunately llvm has different llvm MCInst Opcode enums for rep/xrelease
and repne/xacquire. So to make this work a boolean was added the
InternalInstruction struct as part of the Prefix state which is set with the
added logic in readPrefixes() when decoding an instruction to determine
if these prefix bytes are to be disassembled as xacquire or xrelease. Then
we let the matcher pick the normal prefix instructionID and we change the
Opcode after that when it is set into the MCInst being created.
rdar://11019859
llvm-svn: 184490
2013-06-20 22:32:18 +00:00
f81d036ea7
This reverts r155000.
...
The cdp2 instruction should have the same restrictions as cdp on the
co-processor registers.
VFP instructions on v8/AArch32 share the same encoding space as cdp2.
llvm-svn: 184445
2013-06-20 17:42:36 +00:00
aa7fdf8741
ARM: add operands pre-writeback variants when needed
...
llvm-svn: 184181
2013-06-18 08:12:51 +00:00
4d3e3f279e
ARM: fix thumb literal loads decoding
...
This fixes two previous issues:
- Negative offsets were not correctly disassembled
- The decoded opcodes were not the right one
llvm-svn: 184180
2013-06-18 08:03:06 +00:00
e2bb1d150c
ARM: thumb stores cannot use PC as dest register
...
llvm-svn: 184179
2013-06-18 08:02:56 +00:00
e804ae1188
ARM: fix thumb coprocessor instruction with pre-writeback disassembly
...
was stc2 p0, c0, [r0]!
instead of stc2 p0, c0, [r0,#0]!
llvm-svn: 183975
2013-06-14 11:21:35 +00:00
bd2b610eba
ARM: fix B decoding
...
llvm-svn: 183914
2013-06-13 16:41:55 +00:00
1c7be576c5
This patch adds support for FPINST/FPINST2 as operands to vmsr/vmrs. These are optional registers that may be supported some ARM implementations to aid with resolution of floating point exceptions. The manual pages for vmsr and vmrs do not detail their use. Encodings and other information can be found in ARM Architecture Reference Manual section F, chapter 6, paragraph 3.
...
llvm-svn: 183733
2013-06-11 09:39:51 +00:00
064546cbfe
ARM: Enforce decoding rules for VLDn instructions
...
llvm-svn: 183731
2013-06-11 08:14:14 +00:00
53ff029d62
ARM: Fix STREX/LDREX reecoding
...
The decoded MCInst wasn't reencoded as the same instruction
llvm-svn: 183729
2013-06-11 08:03:20 +00:00
43cb13a5c9
ARM: ISB cannot be passed the same options as DMB
...
ISB should only accepts full system sync, other options are reserved
llvm-svn: 183656
2013-06-10 14:17:08 +00:00
f4ec0c8510
ARM: fix VMOVvnf32 decoding when ambiguous with VCVT
...
Enforce Table A7-15 (op=1, cmode=0b111) -> UNDEF
llvm-svn: 183612
2013-06-08 13:54:05 +00:00
68bcd021fd
ARM: enforce SRS decoding constraints
...
llvm-svn: 183611
2013-06-08 13:43:59 +00:00
631df63e54
ARM: fix CPS decoding when ambiguous with QADD
...
Handle the case when the disassembler table can't tell
the difference between some encodings of QADD and CPS.
Add some necessary safe guards in CPS decoding as well.
llvm-svn: 183610
2013-06-08 13:38:52 +00:00
ea7bb57058
ARM: fix VCVT decoding
...
UNPRED was reported instead of UNDEF
llvm-svn: 183608
2013-06-08 13:29:11 +00:00
0e9892fe3a
This is a simple patch that changes RRX and RRXS to accept all registers as operands.
...
According to the ARM reference manual, RRX(S) have defined encodings for lr, pc and sp.
llvm-svn: 183307
2013-06-05 13:23:51 +00:00
4173e29a98
ARM: add fstmx and fldmx instructions for assembly
...
These instructions are deprecated oddities, but we still need to be able to
disassemble (and reassemble) them if and when they're encountered.
Patch by Amaury de la Vieuville.
llvm-svn: 183011
2013-05-31 15:55:51 +00:00
1bb672da81
ARM: fix VEXT encoding corner case
...
The disassembly of VEXT instructions was too lax in the bits checked. This
fixes the case where the instruction affects Q-registers but a misaligned lane
was specified (should be UNDEFINED).
Patch by Amaury de la Vieuville
llvm-svn: 183003
2013-05-31 13:47:25 +00:00
e1d9f00f09
[SystemZ] Immediate compare-and-branch support
...
This patch adds support for the CIJ and CGIJ instructions.
llvm-svn: 182846
2013-05-29 11:58:52 +00:00
0fb90ab0cb
[SystemZ] Register compare-and-branch support
...
This patch adds support for the CRJ and CGRJ instructions. Support for
the immediate forms will be a separate patch.
The architecture has a large number of comparison instructions. I think
it's generally better to concentrate on using the "best" comparison
instruction first and foremost, then only use something like CRJ if
CR really was the natual choice of comparison instruction. The patch
therefore opportunistically converts separate CR and BRC instructions
into a single CRJ while emitting instructions in ISelLowering.
llvm-svn: 182764
2013-05-28 10:41:11 +00:00
f41e3f56a5
VSTn instructions have a number of encoding constraints which are not implemented. I have added these using wrapper methods around the original custom decoder (incidentally - this is a huge poorly written method that should be cleaned up. I have left it as is since the changes would be much to hard to review).
...
llvm-svn: 182281
2013-05-20 14:57:05 +00:00
dcf0922720
Q registers are encoded in fields of the same length as D registers. As Q registers are half as many, the ARM reference manual mandates the least significant bit to be zeroed out. Failure to do so should result in an undefined instruction. With this change test/MC/Disassembler/ARM/invalid-VQADD-arm.txt is passing (removed XFAIL).
...
llvm-svn: 182279
2013-05-20 14:42:43 +00:00
ffd144174d
[SystemZ] Make use of SUBTRACT HALFWORD
...
Thanks to Ulrich Weigand for noticing that this instruction was missing.
llvm-svn: 181893
2013-05-15 15:05:29 +00:00
78a8ef87ca
[SystemZ] Consolidate disassembler tests for valid input into 2 big tests
...
llvm-svn: 181879
2013-05-15 11:00:31 +00:00
eb9af29426
[SystemZ] Add disassembler support
...
llvm-svn: 181777
2013-05-14 10:17:52 +00:00
dc1764c5a4
The purpose of the patch is to fix the syntax of ARM mrc and mrc2 instructions when they are used to write to the APSR. In this case, the destination operand should be APSR_nzcv, and the encoding of the target should be 0b1111 (same as for PC). In pre-UAL syntax, this form used the PC register as a textual target. This is still allowed for backward compatibility.
...
llvm-svn: 181705
2013-05-13 14:10:04 +00:00
4498bd352f
[XCore] Add LDAPB instructions.
...
With the change the disassembler now supports the XCore ISA in its
entirety.
llvm-svn: 181155
2013-05-05 13:36:53 +00:00
4d3514ee94
[XCore] Add BLRB instructions.
...
llvm-svn: 181152
2013-05-05 13:24:16 +00:00
af22d91af0
s tightens up the encoding description for ARM post-indexed ldr instructions. All instructions in this class have bit 4 cleared. It turns out that there is a test case for this, but it was marked XFAIL.
...
llvm-svn: 180778
2013-04-30 09:00:12 +00:00
a83d5e9f91
ARM: Fix encoding of hint instruction for Thumb.
...
"hint" space for Thumb actually overlaps the encoding space of the CPS
instruction. In actuality, hints can be defined as CPS instructions where imod
and M bits are all nil.
Handle decoding of permitted nop-compatible hints (i.e. nop, yield, wfi, wfe,
sev) in DecodeT2CPSInstruction.
This commit adds a proper diagnostic message for Imm0_4 and updates all tests.
Patch by Mihail Popa <Mihail.Popa@arm.com>.
llvm-svn: 180617
2013-04-26 17:54:54 +00:00
27ff504653
ARM: Permit "sp" in ARM variant of STREXD instructions
...
Patch from Mihail Popa
llvm-svn: 179854
2013-04-19 15:44:32 +00:00
a155ab2dd2
ARM: permit "sp" in ARM variants of MOVW/MOVT instructions
...
llvm-svn: 179847
2013-04-19 09:58:09 +00:00
59bfaf774b
[mips] DSP-ASE move from HI/LO register instructions.
...
llvm-svn: 179739
2013-04-18 00:52:44 +00:00
334c7bc7eb
Use object file specific section type for initial text section
...
llvm-svn: 179494
2013-04-14 21:18:36 +00:00
c313220b18
ARM: Correct printing of pre-indexed operands.
...
According to the ARM reference manual, constant offsets are mandatory for pre-indexed addressing modes.
The MC disassembler was not obeying this when the offset is 0.
It was producing instructions like: str r0, [r1]!.
Correct syntax is: str r0, [r1, #0 ]!.
This change modifies the dumping of operands so that the offset is always printed, regardless of its value, when pre-indexed addressing mode is used.
Patch by Mihail Popa <Mihail.Popa@arm.com>
llvm-svn: 179398
2013-04-12 18:47:25 +00:00
95d9440348
Add CLAC/STAC instruction encoding/decoding support
...
As these two instructions in AVX extension are privileged instructions for
special purpose, it's only expected to be used in inlined assembly.
llvm-svn: 179266
2013-04-11 04:52:28 +00:00
394bf1482b
fixed xsave, xsaveopt, xrstor mnemonics with intel syntax; added test cases
...
llvm-svn: 179223
2013-04-10 21:52:25 +00:00
c6047655a7
ARM: Make "SMC" instructions conditional on new TrustZone architecture feature.
...
These instructions aren't universally available, but depend on a specific
extension to the normal ARM architecture (rather than, say, v6/v7/...) so a new
feature is appropriate.
This also enables the feature by default on A-class cores which usually have
these extensions, to avoid breaking existing code and act as a sensible
default.
llvm-svn: 179171
2013-04-10 12:08:35 +00:00
0c12d1851e
[XCore] Add bru instruction.
...
llvm-svn: 178783
2013-04-04 20:05:35 +00:00
f18d95f756
[XCore] The RRegs register class is a superset of GRRegs.
...
At the time when the XCore backend was added there were some issues with
with overlapping register classes but these all seem to be fixed now.
Describing the register classes correctly allow us to get rid of a
codegen only instruction (LDAWSP_lru6_RRegs) and it means we can
disassemble ru6 instructions that use registers above r11.
llvm-svn: 178782
2013-04-04 19:57:46 +00:00
122acb216c
[XCore] Check disassembly of the st8 instruction.
...
llvm-svn: 178689
2013-04-03 20:07:11 +00:00
fb0b4ea3a7
[XCore] Update disassembler test to improve coverage of the instructions.
...
Previously some instructions were unintentionally covered twice and
others were not covered at all.
llvm-svn: 178688
2013-04-03 20:07:06 +00:00
5816ca117b
AArch64: implement ETMv4 trace system registers.
...
llvm-svn: 178637
2013-04-03 12:31:29 +00:00
772cf466da
Fix issue with disassembler decoding CBZ/CBNZ immediates as negatives when the upper bit is set.
...
They should always be zero-extended, not sign extended. Added test case.
llvm-svn: 178275
2013-03-28 19:22:28 +00:00
08bb3ce383
AArch64: implement GICv3 system registers
...
llvm-svn: 178236
2013-03-28 14:30:46 +00:00
f686be4674
Patch by Gordon Keiser!
...
If PC or SP is the destination, the disassembler erroneously failed with the
invalid encoding, despite the manual saying that both are fine.
This patch addresses failure to decode encoding T4 of LDR (A8.8.62) which is a
postindexed load, where the offset 0xc is applied to SP after the load occurs.
llvm-svn: 178017
2013-03-26 13:58:53 +00:00
07fabeecad
x86 -- disassemble the REP/REPNE prefix when needed
...
This fixes Apple bug: 13493622
llvm-svn: 177887
2013-03-25 18:59:38 +00:00
f15856ebb4
Fixes disassembler crashes on 2013 Haswell RTM instructions.
...
rdar://13318048
llvm-svn: 176828
2013-03-11 21:17:13 +00:00
ce17020c97
AArch64: remove post-encoder method from FCMP (immediate) instructions.
...
The work done by the post-encoder (setting architecturally unused bits to 0 as
required) can be done by the existing operand that covers the "#0.0". This
removes at least one use of the discouraged PostEncoderMethod uses.
llvm-svn: 176261
2013-02-28 14:46:14 +00:00
0ba797e8f7
Make ARMAsmPrinter generate the correct alignment specifier syntax in instructions.
...
The Printer will now print instructions with the correct alignment specifier syntax, like
vld1.8 {d16}, [r0:64]
llvm-svn: 175884
2013-02-22 10:01:33 +00:00
53fff94527
[XCore] Add missing 2r instructions.
...
These instructions are not targeted by the compiler but it is needed for
the MC layer.
llvm-svn: 175407
2013-02-17 22:38:05 +00:00
f5a3ffcba9
[XCore] Add TSETR instruction.
...
This instruction is not targeted by the compiler but it is needed for the
MC layer.
llvm-svn: 175406
2013-02-17 22:32:41 +00:00
2192615d9f
[XCore] Add missing u10 / lu10 instructions.
...
These instructions are not targeted by the compiler but they are
needed for the MC layer.
llvm-svn: 175404
2013-02-17 20:44:48 +00:00
3814491fb1
[XCore] Add missing u6 / lu6 instructions.
...
These instructions are not targeted by the compiler but they are
needed for the MC layer.
llvm-svn: 175403
2013-02-17 20:43:17 +00:00
7b564da474
death to extra whitespace
...
llvm-svn: 175200
2013-02-14 19:15:14 +00:00
f809c6491d
added basic support for Intel ADX instructions
...
-feature flag, instructions definitions, test cases
llvm-svn: 175196
2013-02-14 19:08:21 +00:00
2efb59a719
Make ARMAsmParser accept the correct alignment specifier syntax in instructions.
...
The parser will now accept instructions with alignment specifiers written like
vld1.8 {d16}, [r0:64]
, while also still accepting the incorrect syntax
vld1.8 {d16}, [r0, :64]
llvm-svn: 175164
2013-02-14 14:46:12 +00:00
c5c9713fcf
added test cases for r174920 (prefetch disassembly)
...
llvm-svn: 174979
2013-02-12 17:07:44 +00:00
d30b1a2ac7
*fixed disassembly of some i386 system insts with intel syntax
...
*added file for test cases for i386 intel syntax
llvm-svn: 174900
2013-02-11 19:46:36 +00:00
a80c4c1a08
Add AArch64 CRC32 instructions
...
These instructions are a late addition to the architecture, and may
yet end up behind an optional attribute, but for now they're available
at all times.
llvm-svn: 174496
2013-02-06 09:13:13 +00:00
91a51c5a7c
Add icache prefetch operations to AArch64
...
This adds hints to the various "prfm" instructions so that they can
affect the instruction cache as well as the data cache.
llvm-svn: 174495
2013-02-06 09:04:56 +00:00
e0e3aefdd3
Add AArch64 as an experimental target.
...
This patch adds support for AArch64 (ARM's 64-bit architecture) to
LLVM in the "experimental" category. Currently, it won't be built
unless requested explicitly.
This initial commit should have support for:
+ Assembly of all scalar (i.e. non-NEON, non-Crypto) instructions
(except the late addition CRC instructions).
+ CodeGen features required for C++03 and C99.
+ Compilation for the "small" memory model: code+static data <
4GB.
+ Absolute and position-independent code.
+ GNU-style (i.e. "__thread") TLS.
+ Debugging information.
The principal omission, currently, is performance tuning.
This patch excludes the NEON support also reviewed due to an outbreak of
batshit insanity in our legal department. That will be committed soon bringing
the changes to precisely what has been approved.
Further reviews would be gratefully received.
llvm-svn: 174054
2013-01-31 12:12:40 +00:00
038d24f90c
[XCore] Add missing l2rus instructions.
...
These instructions are not targeted by the compiler but they are
needed for the MC layer.
llvm-svn: 173634
2013-01-27 22:28:30 +00:00
f2ecd40929
[XCore] Add missing l2r instructions.
...
These instructions are not targeted by the compiler but they are
needed for the MC layer.
llvm-svn: 173629
2013-01-27 21:26:02 +00:00
7fe8f63544
[XCore] Add missing 1r instructions.
...
These instructions are not targeted by the compiler but they are
needed for the MC layer.
llvm-svn: 173624
2013-01-27 20:46:21 +00:00
8f56317287
[XCore] Add missing 0r instructions.
...
These instructions are not targeted by the compiler but they are
needed for the MC layer.
llvm-svn: 173623
2013-01-27 20:42:57 +00:00
6b86eec819
Add instruction encodings / disassembly support for l4r instructions.
...
llvm-svn: 173501
2013-01-25 21:55:32 +00:00
a19fa86a70
Add instruction encodings / disassembly support for l5r instructions.
...
llvm-svn: 173479
2013-01-25 20:20:07 +00:00
54e311821f
Add instruction encodings / disassembly support for l6r instructions.
...
llvm-svn: 173288
2013-01-23 20:08:11 +00:00
1a06479f46
Add instruction encodings / disassembly support for u10 / lu10 instructions.
...
llvm-svn: 173204
2013-01-22 22:55:04 +00:00
9d3ec06ef8
Add instruction encodings / disassembly support for u6 / lu6 instructions.
...
llvm-svn: 173086
2013-01-21 20:44:17 +00:00
6e58c6d86d
Add instruction encoding / disassembly support for ru6 / lru6 instructions.
...
llvm-svn: 173085
2013-01-21 20:42:16 +00:00
4e69724869
Add instruction encodings / disassembly support for l2rus instructions.
...
llvm-svn: 172987
2013-01-20 18:51:15 +00:00
9fbf57b26c
Add instruction encodings / disassembly support for l3r instructions.
...
llvm-svn: 172986
2013-01-20 18:37:49 +00:00
f063fcee7a
Add instruction encodings / disassembler support for 2rus instructions.
...
llvm-svn: 172985
2013-01-20 17:22:43 +00:00
3fb7395233
Add instruction encodings / disassembly support 3r instructions.
...
It is not possible to distinguish 3r instructions from 2r / rus instructions
using only the fixed bits. Therefore if an instruction doesn't match the
2r / rus format try to decode it as a 3r instruction before returning Fail.
llvm-svn: 172984
2013-01-20 17:18:47 +00:00
2a74a87b71
This is a resubmittal. For some reason it broke the bots yesterday
...
but I cannot reproduce the problem and have scrubed my sources and
even tested with llvm-lit -v --vg.
The Mips RDHWR (Read Hardware Register) instruction was not
tested for assembler or dissassembler consumption. This patch
adds that functionality.
Contributer: Vladimir Medic
llvm-svn: 172685
2013-01-17 00:28:20 +00:00
5619f91bf7
reverting 172579
...
llvm-svn: 172594
2013-01-16 01:29:10 +00:00
e0c1e1a47e
Akira,
...
Hope you are feeling better.
The Mips RDHWR (Read Hardware Register) instruction was not
tested for assembler or dissassembler consumption. This patch
adds that functionality.
Contributer: Vladimir Medic
llvm-svn: 172579
2013-01-16 00:07:45 +00:00
4f1c7256f9
Fix suffix handling for parsing and printing of cvtsi2ss, cvtsi2sd, cvtss2si, cvttss2si, cvtsd2si, and cvttsd2si to match gas behavior.
...
cvtsi2* should parse with an 'l' or 'q' suffix or no suffix at all. No suffix should be treated the same as 'l' suffix. Printing should always print a suffix. Previously we didn't parse or print an 'l' suffix.
cvtt*2si/cvt*2si should parse with an 'l' or 'q' suffix or not suffix at all. No suffix should use the destination register size to choose encoding. Printing should not print a suffix.
Original 'l' suffix issue with cvtsi2* pointed out by Michael Kuperstein.
llvm-svn: 171668
2013-01-06 20:39:29 +00:00
e3d323052f
Remove edis - the enhanced disassembler. Fixes PR14654.
...
llvm-svn: 170578
2012-12-19 19:55:47 +00:00
459e35c261
Add instruction encodings / disassembly support for l2r instructions.
...
llvm-svn: 170345
2012-12-17 16:28:02 +00:00
51bf1b269a
Add instruction encodings for PEEK and ENDIN.
...
Previously these were marked with the wrong format.
llvm-svn: 170334
2012-12-17 14:23:54 +00:00
041071c558
Add instruction encodings / disassembly support for rus instructions.
...
llvm-svn: 170330
2012-12-17 13:50:04 +00:00
e405e58639
Add instruction encodings for ZEXT and SEXT.
...
Previously these were marked with the wrong format.
llvm-svn: 170327
2012-12-17 13:20:37 +00:00
3a0d5cc314
Add instruction encodings / disassembly support for 2r instructions.
...
llvm-svn: 170323
2012-12-17 12:29:31 +00:00
016967e4ff
Add instruction encodings / disassembly support for 0r instructions.
...
llvm-svn: 170322
2012-12-17 12:26:29 +00:00
c5287b8889
Add tests for disassembly of 1r XCore instructions.
...
llvm-svn: 170295
2012-12-16 18:06:30 +00:00
168ffb36a5
Added a option to the disassembler to print immediates as hex.
...
This is for the lldb team so most of but not all of the values are
to be printed as hex with this option. Some small values like the
scale in an X86 address were requested to printed in decimal
without the leading 0x.
There may be some tweaks need to places that may still be in
decimal that they want in hex. Specially for arm. I made my best
guess. Any tweaks from here should be simple.
I also did the best I know now with help from the C++ gurus
creating the cleanest formatImm() utility function and containing
the changes. But if someone has a better idea to make something
cleaner I'm all ears and game for changing the implementation.
rdar://8109283
llvm-svn: 169393
2012-12-05 18:13:19 +00:00
136d6746c5
Fixed the arm disassembly of invalid BFI instructions to not build a bad MCInst
...
which would then cause an assert when printed. rdar://11437956
llvm-svn: 168960
2012-11-29 23:47:11 +00:00
e66c51d111
Make this test less sensitive.
...
It currently assumes register numbering and any harmless change in the X86
register naming makes it fail. It's enough to match the register names.
llvm-svn: 168632
2012-11-26 23:27:09 +00:00
0c4468b5e6
Remove DOS line endings.
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llvm-svn: 167968
2012-11-14 20:18:34 +00:00
d0836fd20a
[mips] Fix disassembler test cases.
...
llvm-svn: 167326
2012-11-02 22:20:10 +00:00
4739f2eb19
ARM: Better disassembly for pc-relative LDR.
...
When the operand is a plain immediate rather than a label, print it
as [pc, #imm] like we do for the Thumb2 wide encoding variant.
rdar://12154503
llvm-svn: 166991
2012-10-30 01:04:51 +00:00
6fd9624843
Fix ARM's b.w instruction for thumb 2 and the encoding T4. The branch target
...
is 24 bits not 20 and the decoding needed to correctly handle converting the
J1 and J2 bits to their I1 and I2 values to reconstruct the displacement.
llvm-svn: 166982
2012-10-29 23:27:20 +00:00
62183c4e18
Add support for annotated disassembly output for X86 and arm.
...
Per the October 12, 2012 Proposal for annotated disassembly output sent out by
Jim Grosbach this set of changes implements this for X86 and arm. The llvm-mc
tool now has a -mdis option to produced the marked up disassembly and a couple
of small example test cases have been added.
rdar://11764962
llvm-svn: 166445
2012-10-22 22:31:46 +00:00
00e071ad52
Diagnose invalid alignments on duplicating VLDn instructions.
...
Patch by Chris Lidbury.
llvm-svn: 163323
2012-09-06 15:27:12 +00:00
fb3cdd83b0
Check for invalid alignment values when decoding VLDn/VSTn (single ln) instructions.
...
Patch by Chris Lidbury.
llvm-svn: 163321
2012-09-06 15:17:49 +00:00
262f6f564f
Use correct part of complex operand to encode VST1 alignment.
...
Patch by Chris Lidbury.
llvm-svn: 163318
2012-09-06 14:36:55 +00:00
b4e1ba7191
ARM: Move Thumb2 tests to Thumb2 test file and fix CHECK lines.
...
These tests weren't actually being run before (missing ':' after CHECK).
llvm-svn: 161800
2012-08-13 22:25:44 +00:00
6a43bf7d74
Fix #13035 , a bug around Thumb instruction LDRD/STRD with negative #0 offset index issue.
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llvm-svn: 161162
2012-08-02 08:29:50 +00:00
288e1af8c8
Fix #13138 , a bug around ARM instruction DSB encoding and decoding issue.
...
llvm-svn: 161161
2012-08-02 08:21:27 +00:00
10dd40e42d
Fix #13241 , a bug around shift immediate operand for ARM instruction ADR.
...
llvm-svn: 161159
2012-08-02 08:13:13 +00:00
c7690ac7ac
Make l/q suffixes on AVX forms of scalar convert instructions consistent with their non-AVX forms.
...
llvm-svn: 160775
2012-07-26 07:48:28 +00:00
01deb5f2df
Make x86 asm parser to check for xmm vs ymm for index register in gather instructions. Also fix Intel syntax for gather instructions to use 'DWORD PTR' or 'QWORD PTR' to match gas.
...
llvm-svn: 160420
2012-07-18 04:11:12 +00:00
a13cd0666e
Fix check strings in test/MC/Disassembler/Mips/* and run FileCheck.
...
Patch by Vladimir Medic.
llvm-svn: 160143
2012-07-12 21:19:32 +00:00
1dc44dcedd
Fix instruction description of VMOV (between two ARM core registers and two single-precision resiters) (and do it properly this time!
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llvm-svn: 159989
2012-07-10 12:51:09 +00:00
be41e2daa6
Reverse assembler/disassembler operand order for gather instructions.
...
llvm-svn: 159983
2012-07-10 06:38:33 +00:00
9bf2b5677d
Reapply r158846.
...
Access mips register classes via MCRegisterInfo's functions instead of via the
TargetRegisterClasses defined in MipsGenRegisterInfo.inc.
llvm-svn: 159953
2012-07-09 18:46:47 +00:00
b577ff116d
revert r159851.
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llvm-svn: 159854
2012-07-06 20:16:48 +00:00
cfa35fa0ff
Reapply r158846.
...
Include file MipsGenRegisterInfo.inc.
llvm-svn: 159851
2012-07-06 19:29:11 +00:00
ff123d5c63
Fix the remaining TCL-style quotes found in the testsuite. This is
...
another mechanical change accomplished though the power of terrible Perl
scripts.
I have manually switched some "s to 's to make escaping simpler.
While I started this to fix tests that aren't run in all configurations,
the massive number of tests is due to a really frustrating fragility of
our testing infrastructure: things like 'grep -v', 'not grep', and
'expected failures' can mask broken tests all too easily.
Essentially, I'm deeply disturbed that I can change the testsuite so
radically without causing any change in results for most platforms. =/
llvm-svn: 159547
2012-07-02 19:09:46 +00:00
5da53436d5
Convert the uses of '|&' to use '2>&1 |' instead, which works on old
...
versions of Bash. In addition, I can back out the change to the lit
built-in shell test runner to support this.
This should fix the majority of fallout on Darwin, but I suspect there
will be a few straggling issues.
llvm-svn: 159544
2012-07-02 18:37:59 +00:00
a5a29f970e
Convert all tests using TCL-style quoting to use shell-style quoting.
...
This was done through the aid of a terrible Perl creation. I will not
paste any of the horrors here. Suffice to say, it require multiple
staged rounds of replacements, state carried between, and a few
nested-construct-parsing hacks that I'm not proud of. It happens, by
luck, to be able to deal with all the TCL-quoting patterns in evidence
in the LLVM test suite.
If anyone is maintaining large out-of-tree test trees, feel free to poke
me and I'll send you the steps I used to convert things, as well as
answer any painful questions etc. IRC works best for this type of thing
I find.
Once converted, switch the LLVM lit config to use ShTests the same as
Clang. In addition to being able to delete large amounts of Python code
from 'lit', this will also simplify the entire test suite and some of
lit's architecture.
Finally, the test suite runs 33% faster on Linux now. ;]
For my 16-hardware-thread (2x 4-core xeon e5520): 36s -> 24s
llvm-svn: 159525
2012-07-02 12:47:22 +00:00
98a5bf24a9
X86: add more GATHER intrinsics in LLVM
...
Corrected type for index of llvm.x86.avx2.gather.d.pd.256
from 256-bit to 128-bit.
Corrected types for src|dst|mask of llvm.x86.avx2.gather.q.ps.256
from 256-bit to 128-bit.
Support the following intrinsics:
llvm.x86.avx2.gather.d.q, llvm.x86.avx2.gather.q.q
llvm.x86.avx2.gather.d.q.256, llvm.x86.avx2.gather.q.q.256
llvm.x86.avx2.gather.d.d, llvm.x86.avx2.gather.q.d
llvm.x86.avx2.gather.d.d.256, llvm.x86.avx2.gather.q.d.256
llvm-svn: 159402
2012-06-29 00:54:20 +00:00
a09820414a
X86: add GATHER intrinsics (AVX2) in LLVM
...
Support the following intrinsics:
llvm.x86.avx2.gather.d.pd, llvm.x86.avx2.gather.q.pd
llvm.x86.avx2.gather.d.pd.256, llvm.x86.avx2.gather.q.pd.256
llvm.x86.avx2.gather.d.ps, llvm.x86.avx2.gather.q.ps
llvm.x86.avx2.gather.d.ps.256, llvm.x86.avx2.gather.q.ps.256
Modified Disassembler to handle VSIB addressing mode.
llvm-svn: 159221
2012-06-26 19:47:59 +00:00
87505f46ac
Revert r158846.
...
llvm-svn: 158855
2012-06-20 21:19:39 +00:00
da448fe0b1
In MipsDisassembler.cpp, instead of defining register class tables, use the ones
...
that are generated by TableGen and are already available in
MipsGenRegisterInfo.inc. Suggested by Jakob Stoklund Olesen.
Also, fix bug in function DecodeAFGR64RegisterClass.
Patch by Vladimir Medic.
llvm-svn: 158846
2012-06-20 20:39:23 +00:00
f1ef87ddbb
Correct decoder for T1 conditional B encoding
...
llvm-svn: 158055
2012-06-06 09:12:53 +00:00
c13ed945aa
Add lit.local.cfg to run the tests in test/MC/Disassembler/Mips.
...
llvm-svn: 157725
2012-05-31 00:49:56 +00:00
ef479ea854
Add intrinsics, code gen, assembler and disassembler support for the SSE4a extrq and insertq instructions.
...
This required light surgery on the assembler and disassembler
because the instructions use an uncommon encoding. They are
the only two instructions in x86 that use register operands
and two immediates.
llvm-svn: 157634
2012-05-29 19:05:25 +00:00
ddc67a7655
Added the missing bit definition for the 4th bit of the STR (post reg) instruction. It is now set to 0. The patch also sets the unpredictable mask for SEL and SXTB-type instructions.
...
llvm-svn: 156609
2012-05-11 09:28:27 +00:00
914223010c
Fix issues with the ARM bl and blx thumb instructions and the J1 and J2 bits
...
for the assembler and disassembler. Which were not being set/read correctly
for offsets greater than 22 bits in some cases.
Changes to lib/Target/ARM/ARMAsmBackend.cpp from Gideon Myles!
llvm-svn: 156118
2012-05-03 22:41:56 +00:00
9560af848c
Fixed disassembler for vstm/vldm ARM VFP instructions.
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llvm-svn: 156077
2012-05-03 16:38:40 +00:00
0fc56890ba
Disallow YIELD and other allocated nop hints in pre-ARMv6 architectures.
...
llvm-svn: 155983
2012-05-02 09:43:18 +00:00
6cff5ad411
Missed some register numbers.
...
llvm-svn: 155706
2012-04-27 12:21:46 +00:00
b1a17c425a
Update edis test for r155704.
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llvm-svn: 155705
2012-04-27 12:14:03 +00:00
8a8e9d1b63
Specify cpu to unbreak tests.
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llvm-svn: 155604
2012-04-26 01:38:10 +00:00
70be447e5c
Add missing test cases for ARM VLD3 (single 3-element structure to all lanes)
...
instructions.
llvm-svn: 155453
2012-04-24 17:45:56 +00:00
c8d223e41e
Add missing test cases for ARM VLD4 (single 4-element structure to all lanes)
...
instructions.
llvm-svn: 155444
2012-04-24 15:55:00 +00:00
ca45af9a75
Added support for disassembling unpredictable swp/swpb ARM instructions.
...
llvm-svn: 155004
2012-04-18 14:18:57 +00:00
d5c6a63a50
Fix the bahavior of the disassembler when decoding unpredictable mrs instructions on ARM. Now the diasassembler emmits warnings instead of errors.
...
llvm-svn: 155002
2012-04-18 14:09:07 +00:00
41f1fcd80e
Added support for unpredictable mcrr/mcrr2/mrrc/mrrc2 ARM instruction in the disassembler. Since the upredicability conditions are complex, C++ code was added to handle them.
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llvm-svn: 155001
2012-04-18 13:12:50 +00:00
a2944116dc
Fixed decoding for the ARM cdp2 instruction. The restriction on the coprocessor number was removed for this instruction.
...
llvm-svn: 155000
2012-04-18 13:02:55 +00:00
9da1918c84
Add suport for unpredicatble cases of the cmp, tst, teq and cmnz ARM instructions in the disassembler.
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llvm-svn: 154999
2012-04-18 12:48:43 +00:00
71928e681b
Add disassembler to MIPS.
...
Patch by Vladimir Medic.
llvm-svn: 154935
2012-04-17 18:03:21 +00:00
29ae538647
Fix ARM disassembly of VLD2 (single 2-element structure to all lanes)
...
instructions with writebacks. And add test a case for all opcodes handed by
DecodeVLD2DupInstruction() in ARMDisassembler.cpp .
llvm-svn: 154884
2012-04-17 00:49:27 +00:00
def81b9155
Add -disassemble support for -show-inst and -show-encode capability llvm-mc. Also refactor so all MC paraphernalia are created once for all uses as much as possible.
...
The test change is to account for the fact that the default disassembler behaviour has changed with regards to specifying the assembly syntax to use.
llvm-svn: 154809
2012-04-16 11:32:10 +00:00
72f18bbcff
Fixed a case of ARM disassembly getting an assert on a bad encoding
...
of a VST instruction.
llvm-svn: 154544
2012-04-11 22:40:17 +00:00
74c282b5ef
Add retw and lretw instructions. Also, fix Intel syntax parsing for all
...
ret instructions.
llvm-svn: 154468
2012-04-11 01:10:53 +00:00
d2980cd041
Fix ARM disassembly of VLD instructions with writebacks. And add test a case
...
for all opcodes handed by DecodeVLDInstruction() in ARMDisassembler.cpp .
llvm-svn: 154459
2012-04-11 00:25:40 +00:00
aca6c822e6
Fix a number of problems with ARM fused multiply add/subtract instructions.
...
1. The new instruction itinerary entries are not properly described.
2. The asm parser can't handle vfms and vfnms.
3. There were no assembler, disassembler test cases.
4. HasNEON2 has the wrong assembler predicate.
rdar://10139676
llvm-svn: 154456
2012-04-11 00:13:00 +00:00
4eb9616b24
Add the tests that were supposed to go with r153935 that I forgot svn add
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llvm-svn: 154165
2012-04-06 07:09:59 +00:00
af3c79f0ac
Added support for unpredictable ADC/SBC instructions on ARM, and also fixed some corner cases involving the PC register as an operand for these instructions.
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llvm-svn: 154101
2012-04-05 16:19:29 +00:00
d365397daa
Added support for handling unpredictable arithmetic instructions on ARM.
...
llvm-svn: 154100
2012-04-05 16:13:15 +00:00
7629d63bc4
Add support for AVX enhanced comparison predicates. Patch from Kay Tiong Khoo.
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llvm-svn: 153935
2012-04-03 05:20:24 +00:00
d19f025374
Revert r153924. Delete test/MC/Disassembler/Mips and lib/Target/Mips/Disassembler.
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llvm-svn: 153926
2012-04-03 03:01:13 +00:00
55059262aa
Revert r153924. There were buildbot failures.
...
llvm-svn: 153925
2012-04-03 02:51:09 +00:00
e2498d014b
MIPS disassembler support.
...
Patch by Vladimir Medic.
llvm-svn: 153924
2012-04-03 02:20:58 +00:00
ac37acd31b
Added fix in TableGen instruction decoder generation. The decoder now breaks for every leaf node.
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llvm-svn: 153874
2012-04-02 15:20:39 +00:00
f33086052d
Continue cleanup of LIT, getting rid of the remaining artifacts from dejagnu
...
* Removed test/lib/llvm.exp - it is no longer needed
* Deleted the dg.exp reading code from test/lit.cfg. There are no dg.exp files
left in the test suite so this code is no longer required. test/lit.cfg is
now much shorter and clearer
* Removed a lot of duplicate code in lit.local.cfg files that need access to
the root configuration, by adding a "root" attribute to the TestingConfig
object. This attribute is dynamically computed to provide the same
information as was previously provided by the custom getRoot functions.
* Documented the config.root attribute in docs/CommandGuide/lit.pod
llvm-svn: 153408
2012-03-25 09:02:19 +00:00
4afd7d2316
Added soft fail checks for the disassembler when decoding some corner cases of the STRD, STRH, LDRD, LDRH, LDRSH and LDRSB instructions on ARM.
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llvm-svn: 153252
2012-03-22 14:14:49 +00:00
d213f2111a
Added soft fail cases for the disassembler when decoding LDRSBT, LDRHT or LDRSHT instruction on ARM
...
llvm-svn: 153251
2012-03-22 13:24:43 +00:00
a6ea32afdd
Added soft fail cases for the disassembler when decoding MUL instructions on ARM.
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llvm-svn: 153250
2012-03-22 13:14:39 +00:00
7e7d5eefb2
Fix ARM disassembly of VST1 and VST2 instructions with writeback. And add test
...
case for all opcodes handed by DecodeVSTInstruction() in ARMDisassembler.cpp .
llvm-svn: 153218
2012-03-21 20:54:32 +00:00
32a49333ec
The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this.
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llvm-svn: 153089
2012-03-20 15:54:56 +00:00
987cef1fe2
Change the second line of the test added for r152414 to use CHECK-NEXT.
...
Suggestion by Bill Wendling!
llvm-svn: 152582
2012-03-12 21:38:09 +00:00
ebb10df441
Fix disasm of iret, sysexit, and sysret when displayed with Intel syntax.
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Patch by Kay Tiong Khoo!
llvm-svn: 152487
2012-03-10 07:37:27 +00:00
014e1cde5f
Fix the x86 disassembler to at least print the lock prefix if it is the first
...
prefix. Added a FIXME to remind us this still does not work when it is not the
first prefix.
llvm-svn: 152414
2012-03-09 17:52:49 +00:00
520eb3ba8a
Fix a bug in the ARM disassembly of the neon VLD2 all lanes instruction.
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llvm-svn: 152127
2012-03-06 18:33:12 +00:00
f0269b4270
Change ARMInstPrinter::printPredicateOperand() so it will not abort if it
...
runs into the undefined 15 condition code value.
llvm-svn: 151844
2012-03-01 22:13:02 +00:00
6491c8020e
X86 disassembler support for jcxz, jecxz, and jrcxz. Fixes PR11643. Patch by Kay Tiong Khoo.
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llvm-svn: 151510
2012-02-27 01:54:29 +00:00
66a3597a4a
Add vmfunc instruction to X86 assembler and disassembler.
...
llvm-svn: 150899
2012-02-19 01:39:49 +00:00
ed7aa46366
Add X86 assembler and disassembler support for AMD SVM instructions. Original patch by Kay Tiong Khoo. Few tweaks by me for code density and to reduce replication.
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llvm-svn: 150873
2012-02-18 08:19:49 +00:00
924f9a671d
Replace all instances of dg.exp file with lit.local.cfg, since all tests are run with LIT now and now Dejagnu. dg.exp is no longer needed.
...
Patch reviewed by Daniel Dunbar. It will be followed by additional cleanup patches.
llvm-svn: 150664
2012-02-16 06:28:33 +00:00
d9ba4fd48f
Teach the MC and disassembler about SoftFail, and hook it up to UNPREDICTABLE on ARM. Wire this to tBLX in order to provide test coverage.
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llvm-svn: 150169
2012-02-09 10:56:31 +00:00
2ba766ae84
Add disassembler support for VPERMIL2PD and VPERMIL2PS.
...
llvm-svn: 147368
2011-12-30 06:23:39 +00:00
03a0beda88
Add FMA4 instructions to disassembler.
...
llvm-svn: 147367
2011-12-30 05:20:36 +00:00
d773607eee
Fix execution domains for PS/PD FMA3 instructions. Add SS/SD forms o FMA3 instructions.
...
llvm-svn: 147353
2011-12-29 20:43:40 +00:00
8cab06a214
Expose FMA3 instructions to the disassembler.
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llvm-svn: 147351
2011-12-29 20:03:14 +00:00
8d24618975
ARM NEON VST2 assembly parsing and encoding.
...
Work in progress. Parsing for non-writeback, single spaced register lists
works now. The rest have the representations better factored, but still
need more to be able to parse properly.
llvm-svn: 146579
2011-12-14 19:35:22 +00:00
97b3da5433
Add several new instructions supported by the latest MicroBlaze.
...
These instructions are not generated by the backend yet, this will come in a later commit.
llvm-svn: 145161
2011-11-27 05:16:58 +00:00
0ac9058f89
Fix an ambiguous decoding where we failed to properly decode VMOVv2f32 and VMOVv4f32.
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llvm-svn: 144683
2011-11-15 19:55:00 +00:00
3e2c6f380c
ARM VLDR/VSTR instructions don't need a size suffix.
...
Canonicallize on the non-suffixed form, but continue to accept assembly that
has any correctly sized type suffix.
llvm-svn: 144583
2011-11-14 23:03:21 +00:00
69d57cf9c4
Simplify some uses of utohexstr.
...
As a side effect hex is printed lowercase instead of uppercase now.
llvm-svn: 144013
2011-11-07 21:00:59 +00:00
fbb704f551
Fix the issue that r143552 was trying to address the _right_ way. One-register lists are legal on LDM/STM instructions, but we should not print the PUSH/POP aliases when they appear. This fixes round tripping on this instruction.
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llvm-svn: 143557
2011-11-02 18:03:14 +00:00
69e54a740c
Fix disassembly of some VST1 instructions.
...
llvm-svn: 143507
2011-11-01 22:18:13 +00:00
40703f4252
More not-crashing NEON disassembly updates for the vld refactoring.
...
llvm-svn: 143351
2011-10-31 17:17:32 +00:00
5524ce7d82
Fix illegal disassembly testcase.
...
llvm-svn: 143231
2011-10-28 21:45:09 +00:00
dde461c8b1
Reapply r143202, with a manual decoding hook for SWP. This change inadvertantly exposed a decoding ambiguity between SWP and CPS that the auto-generated decoder can't handle.
...
llvm-svn: 143208
2011-10-28 18:02:13 +00:00
f211416dde
Add testcase for r143162.
...
llvm-svn: 143163
2011-10-27 22:54:14 +00:00
295b1e84ce
Fix a NEON disassembly case that was broken in the recent refactorings. As more of this code gets refactored, a lot of these manual decoding hooks should get smaller and/or go away entirely.
...
llvm-svn: 142817
2011-10-24 18:04:29 +00:00
b05d9e9bea
Add X86 SARX, SHRX, and SHLX instructions.
...
llvm-svn: 142779
2011-10-23 22:18:24 +00:00
980d59832a
Add X86 RORX instruction
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llvm-svn: 142741
2011-10-23 07:34:00 +00:00
e94d277db8
Add X86 MULX instruction for disassembler.
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llvm-svn: 142738
2011-10-23 00:33:32 +00:00
16c8fc5191
Revert r142618, r142622, and r142624, which were based on an incorrect reading of the ARMv7 docs.
...
llvm-svn: 142626
2011-10-20 22:23:58 +00:00
608c60c773
Fix decoding tests for fixed MSR encodings.
...
llvm-svn: 142624
2011-10-20 22:01:48 +00:00
ef309c3384
Rename PEXTR to PEXT. Add intrinsics for BMI instructions.
...
llvm-svn: 142480
2011-10-19 07:48:35 +00:00
96fa597828
Add X86 PEXTR and PDEP instructions.
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llvm-svn: 142141
2011-10-16 16:50:08 +00:00
aea148c366
Add X86 BZHI instruction as well as BMI2 feature detection.
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llvm-svn: 142122
2011-10-16 07:55:05 +00:00
0ae8d4d738
Add X86 INVPCID instruction. Add 32/64-bit predicates to INVEPT, INVVPID, VMREAD, and VMWRITE to remove hack from X86RecognizableInstr.
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llvm-svn: 142117
2011-10-16 07:05:40 +00:00
25ea4e5ad3
Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen
...
llvm-svn: 142105
2011-10-16 03:51:13 +00:00
27ad12539d
Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension.
...
llvm-svn: 142082
2011-10-15 20:46:47 +00:00
965de2c197
Add X86 ANDN instruction. Including instruction selection.
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llvm-svn: 141947
2011-10-14 07:06:56 +00:00
3657fe4b17
Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell.
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llvm-svn: 141939
2011-10-14 03:21:46 +00:00
063f55ffdd
Revert r141854 because it was causing failures:
...
http://lab.llvm.org:8011/builders/llvm-x86_64-linux/builds/101
--- Reverse-merging r141854 into '.':
U test/MC/Disassembler/X86/x86-32.txt
U test/MC/Disassembler/X86/simple-tests.txt
D test/CodeGen/X86/bmi.ll
U lib/Target/X86/X86InstrInfo.td
U lib/Target/X86/X86ISelLowering.cpp
U lib/Target/X86/X86.td
U lib/Target/X86/X86Subtarget.h
llvm-svn: 141857
2011-10-13 07:48:07 +00:00
8cc9388073
Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell.
...
llvm-svn: 141854
2011-10-13 07:09:14 +00:00
54a20ed0f1
Thumb2 assembly parsing and encoding for LDC/STC.
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llvm-svn: 141811
2011-10-12 20:54:17 +00:00
8c799c9826
Update test for r141704.
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llvm-svn: 141705
2011-10-11 20:18:50 +00:00
271064e873
Add X86 LZCNT instruction. Including instruction selection support.
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llvm-svn: 141651
2011-10-11 06:44:02 +00:00
a697852386
Fix disassembling of popcntw. Also remove some code that says it accounts for 64BIT_REXW_XD not existing, but it does exist.
...
llvm-svn: 141642
2011-10-11 04:34:23 +00:00
b253f490c3
Insert dummy ED table entries for pseudo-instructions.
...
The table is indexed by opcode, so simply removing pseudo-instructions
creates a wrong mapping from opcode to table entry.
Add a test case for xorps which has a very high opcode that exposes this
problem.
llvm-svn: 141562
2011-10-10 18:30:16 +00:00
fe9179fa4f
Add Ivy Bridge 16-bit floating point conversion instructions for the X86 disassembler.
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llvm-svn: 141505
2011-10-09 07:31:39 +00:00
d9cfddc5cd
Add X86 disassembler support for RDFSBASE, RDGSBASE, WRFSBASE, and WRGSBASE.
...
llvm-svn: 141358
2011-10-07 07:02:24 +00:00
bf136764ae
Add X86 disassembler support for XSAVE, XRSTOR, and XSAVEOPT.
...
llvm-svn: 141354
2011-10-07 05:53:50 +00:00
f18c896337
Add support in the disassembler for ignoring the L-bit on certain VEX instructions. Mark instructions that have this behavior. Fixes PR10676.
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llvm-svn: 141065
2011-10-04 06:30:42 +00:00
786bdb9e14
Add support for MOVBE and RDRAND instructions for the assembler and disassembler. Includes feature flag checking, but no instrinsic support. Fixes PR10832, PR11026 and PR11027.
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llvm-svn: 141007
2011-10-03 17:28:23 +00:00
0d0be47d03
Treat VEX.vvvv as a 3-bit field outside of 64-bit mode. Prevents access to registers xmm8-xmm15 outside 64-bit mode.
...
llvm-svn: 140997
2011-10-03 08:14:29 +00:00
285bc34089
Test updates that were supposed to go with r140993.
...
llvm-svn: 140994
2011-10-03 07:53:59 +00:00
7aea69d949
Fix some Intel syntax disassembly issues with instructions that implicitly use AL/AX/EAX/RAX such as ADD/SUB/ADC/SUBB/XOR/OR/AND/CMP/MOV/TEST.
...
llvm-svn: 140974
2011-10-02 21:08:12 +00:00
21c33657d6
Special case disassembler handling of REX.B prefix on NOP instruction to decode as XCHG R8D, EAX instead. Fixes PR10344.
...
llvm-svn: 140971
2011-10-02 16:56:09 +00:00
d07a59f288
Fix disassembling of INVEPT and INVVPID to take operands
...
llvm-svn: 140955
2011-10-01 21:20:14 +00:00
88cb33e0d4
Fix disassembler handling of CRC32 which is an odd instruction that uses 0xf2 as an opcode extension and allows the opsize prefix. This necessitated adding IC_XD_OPSIZE and IC_64BIT_XD_OPSIZE contexts. Unfortunately, this increases the size of the disassembler tables. Fixes PR10702.
...
llvm-svn: 140954
2011-10-01 19:54:56 +00:00
21efa7d6e1
Check in a patch that has already been code reviewed by Owen that I'd forgotten to commit.
...
Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format.
Add decoder and disassembler tests.
Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT.
llvm-svn: 140696
2011-09-28 14:21:38 +00:00
287d6ef088
Fix an incorrect decoder test.
...
llvm-svn: 140579
2011-09-26 23:08:34 +00:00
45faba98b4
Fix VEX decoding in i386 mode. Fixes PR11008.
...
llvm-svn: 140515
2011-09-26 05:12:43 +00:00
b75772201f
Fix incorrect disassembly test.
...
llvm-svn: 140423
2011-09-23 22:05:54 +00:00
737beaf86d
Post-index loads/stores in still need to print the post-indexed immediate, even if it's zero, to distinguish them from non-post-indexed instructions.
...
llvm-svn: 140420
2011-09-23 21:26:40 +00:00
987a878946
Reapply r140412 (Thumb2 reg-reg loads cannot target SP or PC), with invalid testcases updated.
...
llvm-svn: 140415
2011-09-23 21:07:25 +00:00
526adabe87
Don't allow 32-bit only instructions to be disassembled in 64-bit mode. Fixes part of PR10700.
...
llvm-svn: 140370
2011-09-23 06:57:25 +00:00
6d1872b77a
Fix register printing in disassembling of push/pop of segment registers and in/out in Intel syntax mode. Fixes PR10960
...
llvm-svn: 140299
2011-09-22 07:01:50 +00:00
f52c68f0ca
Print out immediate offset versions of PC-relative load/store instructions as [pc, #123 ] rather than simply #123 .
...
llvm-svn: 140283
2011-09-21 23:44:46 +00:00
2b35d7cff1
Port over more Thumb2 encoding tests to decoding tests.
...
llvm-svn: 140152
2011-09-20 17:44:48 +00:00
ddfcec92d9
Handle STRT (and friends) like LDRT (and friends) for decoding purposes. Port over additional encoding tests to decoding tests.
...
llvm-svn: 140032
2011-09-19 18:07:10 +00:00
09a9b6b953
Add a testcase for another corner-case decoding.
...
llvm-svn: 139970
2011-09-16 23:15:29 +00:00
3ca958cd19
Fix disassembly of Thumb2 BFI instructions with bit range of [0, 32).
...
llvm-svn: 139964
2011-09-16 22:29:48 +00:00
9764bced10
Add fixed bits to correctly distinguish Thumb2 SSAT/SSAT16's.
...
llvm-svn: 139958
2011-09-16 22:17:02 +00:00
fe82365cb0
Fix disassembly of Thumb2 LDRSH with a #-0 offset.
...
llvm-svn: 139943
2011-09-16 21:08:33 +00:00
30fc19a6dd
Port over more Thumb2 assembly tests to disassembly tests.
...
llvm-svn: 139915
2011-09-16 17:56:04 +00:00
b489e3b408
Port over more Thumb2 assembly tests to disassembly tests.
...
llvm-svn: 139912
2011-09-16 17:22:48 +00:00
ee8157cb41
Fix mem type for VEX.128 form of VROUNDP*. Remove filter preventing VROUND from being recognized by disassembler.
...
llvm-svn: 139691
2011-09-14 06:41:26 +00:00
96e00e5a24
Make disassembling of VBLEND* print immediate as a XMM/YMM register name. Fixes PR10917.
...
llvm-svn: 139690
2011-09-14 05:55:28 +00:00
503eef7641
Add test case for PR10851.
...
llvm-svn: 139689
2011-09-14 04:36:54 +00:00
3eb2470eed
Make use of Eli's FileCheck sorcery to improve this test.
...
llvm-svn: 139645
2011-09-13 21:37:50 +00:00
7f0e98fd7f
Correct disassembly printing of Thumb2 post-incremented LDRD and STRD.
...
llvm-svn: 139639
2011-09-13 20:46:26 +00:00
e98d8a5c84
Remove filter that was preventing MOVDQU/MOVDQA and their VEX forms from being disassembled. Also added encodings for the other register/register form of these instructions. Fixes PR10848.
...
llvm-svn: 139588
2011-09-13 06:54:58 +00:00
2a206c44b7
Thumb2 POP's don't allow the PC as an operand, and PUSH's don't allow the SP either.
...
llvm-svn: 139542
2011-09-12 21:28:46 +00:00
a9ebf6fb64
Port more encoding tests to decoding tests, and correct an improper Thumb2 pre-indexed load decoding this uncovered.
...
llvm-svn: 139522
2011-09-12 18:56:30 +00:00
48f2b36911
Fix disassembling of one of the register/register forms of MOVUPS/MOVUPD/MOVAPS/MOVAPD/MOVSS/MOVSD and their VEX equivalents. Fixes PR10877.
...
llvm-svn: 139486
2011-09-11 23:19:54 +00:00
a88e356017
Fix disassembling of reverse register/register forms of ADD/SUB/XOR/OR/AND/SBB/ADC/CMP/MOV.
...
llvm-svn: 139485
2011-09-11 21:41:45 +00:00
a948cb9058
Fix disassembling of PAUSE instruction. Fixes PR10900. Also fixed NOP disassembling to ignore OpSize and REX.W.
...
llvm-svn: 139484
2011-09-11 20:23:20 +00:00
53db43b560
LDM writeback is not allowed if Rn is in the target register list.
...
llvm-svn: 139432
2011-09-09 23:13:33 +00:00
5bfb0e0a85
Fix assembly/disassembly of Thumb2 ADR instructions with immediate operands.
...
llvm-svn: 139422
2011-09-09 22:24:36 +00:00
e812f9eed5
Add disassembler test for Intel syntax. Tests r139353.
...
llvm-svn: 139356
2011-09-09 06:35:44 +00:00
2fefa427d5
Soft fail CBZ/CBNZ in the disassembler if they appear inside an IT block.
...
llvm-svn: 139328
2011-09-08 22:42:49 +00:00
7db8d697cf
Thumb2 assembly parsing and encoding for LDRD(immediate).
...
Refactor operand handling for STRD as well. Tests for that forthcoming.
llvm-svn: 139322
2011-09-08 22:07:06 +00:00
18d17aa6b7
Create Thumb2 versions of STC/LDC, and reenable the relevant tests.
...
llvm-svn: 139256
2011-09-07 21:10:42 +00:00
8067df9503
Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler.
...
llvm-svn: 139250
2011-09-07 19:42:28 +00:00
5d5f4862eb
Update test for 139243
...
llvm-svn: 139244
2011-09-07 18:40:06 +00:00
cd5612d3a5
Port more assembler tests over to disassembler tests, and fix a minor logic error that exposed.
...
llvm-svn: 139240
2011-09-07 17:55:19 +00:00
b041e866b0
Port more encoding tests over to Thumb2 decoding tests.
...
llvm-svn: 139171
2011-09-06 20:26:34 +00:00
5b03f72292
Change X86 disassembly to print immediates values as signed by default. Special
...
case those instructions that the immediate is not sign-extend. radr://8795217
llvm-svn: 139028
2011-09-02 20:01:23 +00:00
54e09b4799
Fix the disassembly of the X86 "crc32w %ax, %eax" instruction. Bug 10702.
...
llvm-svn: 139014
2011-09-02 18:03:03 +00:00
94ce535647
Make IC_VEX* not inherit from IC_*. Prevents instructions with no VEX form from disassembling to their non-VEX form. Also prevents weak filter collisons that were keeping valid VEX instructions from decoding properly. Make VEX_L* not inherit from VEX_* because the VEX.L bit always important. This stops packed int VEX encodings from being disassembled when specified with VEX.L=1. Fixes PR10831 and PR10806.
...
llvm-svn: 138997
2011-09-02 04:17:54 +00:00
2fa06a7226
Fix issues with disassembly of IT instructions involving condition codes other the EQ/NE. Discovered by roundtrip testing.
...
llvm-svn: 138840
2011-08-30 22:58:27 +00:00
2e282257ed
Port Thumb2 assembler tests over to disassembler tests.
...
llvm-svn: 138822
2011-08-30 20:03:11 +00:00
4f2fba1108
Add vvvv support to disassembling of instructions with MRMDestMem and MRMDestReg form. Needed to support mem dest form of vmaskmovps/d. Fixes PR10807.
...
llvm-svn: 138795
2011-08-30 07:09:35 +00:00
7e2489a7c9
Fix the disassembly of the X86 crc32 instruction. Bug 10702 and rdar://8795217
...
llvm-svn: 138771
2011-08-29 22:06:28 +00:00
b205c029a4
Improve encoding support for BLX with immediat eoperands, and fix a BLX decoding bug this uncovered.
...
llvm-svn: 138675
2011-08-26 23:32:08 +00:00
16d33f36d5
invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits. This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure.
...
llvm-svn: 138653
2011-08-26 20:43:14 +00:00
a01bcbfc80
Support an extension of ARM asm syntax to allow immediate operands to ADR instructions. This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here.
...
llvm-svn: 138635
2011-08-26 18:09:22 +00:00
f3b6507e26
Add a testcase for r138625.
...
llvm-svn: 138626
2011-08-26 06:45:08 +00:00
c66d50d1a2
Fix disassembling of VCVTSD2SI
...
llvm-svn: 138623
2011-08-26 04:49:29 +00:00
5e30972cff
Port over additional encoding tests to decoding tests, and fix an operand ordering bug this exposed.
...
llvm-svn: 138575
2011-08-25 18:30:18 +00:00
76e3e0b554
Give ATTR_VEX higher priority when generating the disassembler context table. Fixes disassembling of VEX instructions with 'pp'=00. Fixes subset of PR10678.
...
llvm-svn: 138552
2011-08-25 07:42:00 +00:00
e1541838f9
Add TB encoding to VEROALL, VZEROUPPER, and VCVTPS2PD to allow them to be disassembled. Fixes PR10723.
...
llvm-svn: 138551
2011-08-25 06:57:46 +00:00
16fd0d96f2
Port over more encoding tests to decoding tests.
...
llvm-svn: 138441
2011-08-24 17:08:34 +00:00
924bcfc92f
Fix decoding of Thumb2 prefetch instructions, which account for all the remaining Thumb2 decoding failures found by randomized testing so far.
...
llvm-svn: 138341
2011-08-23 17:51:38 +00:00
041dba6dec
Fix two more instances of mis-matched operand names breaking disassembly. Found by randomized testing.
...
llvm-svn: 138337
2011-08-23 17:37:32 +00:00
dcea63236e
Port more assemble tests over to disassembly tests.
...
llvm-svn: 138336
2011-08-23 17:26:35 +00:00
1346d79b4b
t2SMLAD is a four-register instruction, not a three-register one.
...
llvm-svn: 138301
2011-08-22 23:31:45 +00:00
f94b7b7d57
Correct operand naming of t2USAT16 to allow proper decoding.
...
llvm-svn: 138300
2011-08-22 23:27:47 +00:00
5e9989a920
Match operand naming to allow correct decoding of t2LDRSH_POST.
...
llvm-svn: 138298
2011-08-22 23:22:05 +00:00
a743409ec8
Provide a correct decoder hook for Thumb2 shifted registers. Found by randomized testing.
...
llvm-svn: 138292
2011-08-22 23:10:16 +00:00
061738a680
Provide operand encoding information for half-precision VCVT instructions. Found by randomized testing.
...
llvm-svn: 138273
2011-08-22 21:34:00 +00:00
df698b032c
Fix decoding of VMOVSRR and VMOVRRS, which account for the overwhelming majority of decoder crashes detected by randomized testing.
...
llvm-svn: 138269
2011-08-22 20:27:12 +00:00
721c3704da
Fix another batch of VLD/VST decoding crashes discovered by randomized testing.
...
llvm-svn: 138255
2011-08-22 18:42:13 +00:00
ac92e77bb8
Correct writeback handling of duplicating VLD instructions. Discovered by randomized testing.
...
llvm-svn: 138251
2011-08-22 18:22:06 +00:00
fe29fe431d
Port another swathe of Thumb1 encoding tests over to decoding tests.
...
llvm-svn: 138250
2011-08-22 18:05:49 +00:00
b49813206b
Fix an incorrect shift when decoding SP-relative stores in Thumb1-mode. Add more tests.
...
llvm-svn: 138246
2011-08-22 17:56:58 +00:00
ba6c2a52c7
Add TB encoding to VEX versions of SSE fp logical operations to fix disassembler
...
llvm-svn: 138034
2011-08-19 05:28:50 +00:00
96b7ad2e17
STC2L_POST and STC2L_POST should be handled the same as STCL_POST/LDC_POST for the purposes of decoding all operands except the predicate.
...
Found by randomized testing.
llvm-svn: 138003
2011-08-18 22:47:44 +00:00
192a760b54
Fix the decoding of RFE instruction. RFEs have the load bit set, while SRSs have it unset.
...
llvm-svn: 138000
2011-08-18 22:31:17 +00:00
67d6f11974
Improve handling of failure and unpredictable cases for CPS, STR, and SMLA instructions.
...
Fixes a large class of disassembler crashes found by randomized testing.
llvm-svn: 137995
2011-08-18 22:11:02 +00:00
90103ccc05
Thumb assembly parsing and encoding for LDM instruction.
...
Fix base register type and canonicallize to the "ldm" spelling rather than
"ldmia." Add diagnostics for incorrect writeback token and out-of-range
registers.
llvm-svn: 137986
2011-08-18 21:50:53 +00:00
627021d7c0
More Thumb1 decoding tests.
...
llvm-svn: 137974
2011-08-18 20:05:06 +00:00
9f9371ccb3
Test commit; adding test for invalid LDRD which was part of the patch for r137647 but seemingly didn't get svn add'ed.
...
llvm-svn: 137960
2011-08-18 18:03:02 +00:00
ec3884c50a
Port over BL/BLX to disassembly tests.
...
llvm-svn: 137954
2011-08-18 17:43:52 +00:00
a90896397b
Port new Thumb1 encoding tests over to decoding tests.
...
llvm-svn: 137902
2011-08-17 23:37:33 +00:00
d40d838cc4
Start building a Thumb1 decoding test file based on the Thumb1 parsing/encoding test file.
...
llvm-svn: 137840
2011-08-17 18:21:36 +00:00
a4043c4b32
Allow the MCDisassembler to return a "soft fail" status code, indicating an instruction that is disassemblable, but invalid. Only used for ARM UNPREDICTABLE instructions at the moment.
...
Patch by James Molloy.
llvm-svn: 137830
2011-08-17 17:44:15 +00:00
53440984b3
Add a test file for Thumb2 NEON.
...
llvm-svn: 137687
2011-08-15 23:42:20 +00:00
5286bd2d01
Add some more comprehensive VFP decoding tests.
...
llvm-svn: 137657
2011-08-15 21:29:01 +00:00
1d5d2cac8c
Enforce the constraint that Rt must be even on LDRD/STRD instructions in ARM mode. Update tests to reflect this fact.
...
Patch by James Molloy.
llvm-svn: 137647
2011-08-15 20:51:32 +00:00
944f4923a4
Add a test for Thumb1 LDRSH decoding.
...
llvm-svn: 137645
2011-08-15 20:15:43 +00:00
f746b0ec53
Add testcase for STRH. Patch by James Molloy.
...
llvm-svn: 137644
2011-08-15 20:12:03 +00:00
61a3ece665
Fix incorrect encoding of UMAAL and friends. Patch by James Molloy.
...
llvm-svn: 137641
2011-08-15 20:08:25 +00:00
3157f2eebe
Fix decoding LDRSB and LDRSH in Thumb1 mode. Patch by James Molloy.
...
llvm-svn: 137636
2011-08-15 19:00:06 +00:00
b9d82f411c
Fix problems decoding the to/from-lane NEON memory instructions, and add a comprehensive NEON decoding testcase.
...
llvm-svn: 137635
2011-08-15 18:44:44 +00:00
2d1d7a11f8
Fix some remaining issues with decoding ARM-mode memory instructions, and add another batch of tests.
...
llvm-svn: 137502
2011-08-12 20:36:11 +00:00
ed6d3e813e
Port over the basic ARM encodings test file to a decoding test file. Greatly increases our test coverage of basic ARM-mode instructions.
...
llvm-svn: 137495
2011-08-12 19:42:45 +00:00
3a850f28d0
Fix decoding for indexed STRB and LDRB. Fixes <rdar://problem/9926161>.
...
llvm-svn: 137347
2011-08-11 20:47:56 +00:00
887c0b1358
Improve operand validation for Thumb2 addressing modes.
...
llvm-svn: 137344
2011-08-11 20:40:40 +00:00
6066340301
Continue to tighten decoding by performing more operand validation.
...
llvm-svn: 137340
2011-08-11 20:21:46 +00:00
3477f2cea5
Tighten decoding of addrmode2 instructions to reject more UNPREDICTABLE cases.
...
llvm-svn: 137325
2011-08-11 19:00:18 +00:00
0e15b48f3c
Tighten operand decoding of addrmode2 instruction. The offset register cannot be PC.
...
llvm-svn: 137323
2011-08-11 18:55:42 +00:00
e33c95d39b
Correct immediate range for shifter operands. Patch by James Molloy, with additional encoding fixes added by me.
...
llvm-svn: 137322
2011-08-11 18:41:59 +00:00
ed25385227
Improve error checking in the new ARM disassembler. Patch by James Molloy.
...
llvm-svn: 137320
2011-08-11 18:24:51 +00:00
c86a5bd219
Add initial support for decoding NEON instructions in Thumb2 mode.
...
llvm-svn: 137236
2011-08-10 19:01:10 +00:00
8059f0cf8d
Push GPRnopc through a large number of instruction definitions to tighten operand decoding.
...
llvm-svn: 137189
2011-08-10 00:03:03 +00:00
92b942b1b5
Tighten operand checking of register-shifted-register operands.
...
llvm-svn: 137180
2011-08-09 23:33:27 +00:00
e008931bf6
Tighten operand checking on memory barrier instructions.
...
llvm-svn: 137176
2011-08-09 23:25:42 +00:00
3d2e0e9db6
Tighten operand checking on CPS instructions.
...
llvm-svn: 137172
2011-08-09 23:05:39 +00:00
042619f97d
Create a new register class for the set of all GPRs except the PC. Use it to tighten our decoding of BFI.
...
llvm-svn: 137168
2011-08-09 22:48:45 +00:00
406dc1755f
ARM Disassembler: sign extend branch immediates.
...
Not sure about BLXi, but this is what the old disassembler did.
llvm-svn: 137156
2011-08-09 22:02:50 +00:00
7a2401dbf0
Tighten Thumb1 branch predicate decoding.
...
llvm-svn: 137146
2011-08-09 21:07:45 +00:00
e0152a73c2
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter.
...
This new disassembler can correctly decode all the testcases that the old one did, though
some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in
operand checking as the old one was.
llvm-svn: 137144
2011-08-09 20:55:18 +00:00
d359571120
ARM refactoring assembly parsing of memory address operands.
...
Memory operand parsing is a bit haphazzard at the moment, in no small part
due to the even more haphazzard representations of memory operands in the .td
files. Start cleaning that all up, at least a bit.
The addressing modes in the .td files will be being simplified to not be
so monolithic, especially with regards to immediate vs. register offsets
and post-indexed addressing. addrmode3 is on its way with this patch, for
example.
This patch is foundational to enable going back to smaller incremental patches
for the individual memory referencing instructions themselves. It does just
enough to get the basics in place and handle the "make check" regression tests
we already have.
Follow-up work will be fleshing out the details and adding more robust test
cases for the individual instructions, starting with ARM mode and moving from
there into Thumb and Thumb2.
llvm-svn: 136845
2011-08-03 23:50:40 +00:00
51726e2147
ARM SRS instruction parsing, diassembly and encoding support.
...
Fix the instruction encoding for operands. Refactor mode to use explicit
instruction definitions per FIXME to be more consistent with loads/stores.
Fix disassembler accordingly. Add tests.
llvm-svn: 136509
2011-07-29 20:26:09 +00:00
d25c2cdad7
Tweak ARM assembly parsing and printing of MSR instruction.
...
The system register spec should be case insensitive. The preferred form for
output with mask values of 4, 8, and 12 references APSR rather than CPSR.
Update and tidy up tests accordingly.
llvm-svn: 135532
2011-07-19 22:45:10 +00:00
0318036c4d
Make the disassembler able to disassemble a bunch of instructions with names in the TableGen files containing "64" on x86-32. This includes a bunch of x87 instructions, like fld, and a bunch of SSSE3 instructions on MMX registers like pshufb. Part of PR8873.
...
llvm-svn: 135337
2011-07-16 02:41:28 +00:00
454e1c7abb
Remove VMOVDneon and VMOVQ, which are just aliases for VORR. This continues to simplify the path towards an auto-generated disassembler.
...
llvm-svn: 135290
2011-07-15 18:46:47 +00:00
581da64241
Simplify printing of ARM shifted immediates.
...
Print shifted immediate values directly rather than as a payload+shifter
value pair. This makes for more readable output assembly code, simplifies
the instruction printer, and is consistent with how Thumb immediates are
displayed.
llvm-svn: 134902
2011-07-11 16:48:36 +00:00
a0c9c75df2
Fix Bug 9386 - ARM disassembler failed to disassemble conditional bx
...
Modified the patch to .td file supplied by Jyun-Yan You. Add a test case and
modified ARMDisassemblerCore.cpp a little bit.
llvm-svn: 131859
2011-05-22 17:51:04 +00:00
071634612d
Disassembly of tBcc was wrongly adding 4 to the SignExtend'ed imm8:'0' immediate operand.
...
llvm-svn: 131565
2011-05-18 20:32:41 +00:00
c3c7001844
Add tests for A8.6.110 NOP.
...
llvm-svn: 130345
2011-04-27 23:29:21 +00:00
57c892860e
Disassembly of A8.6.59 LDR (literal) Encoding T1 (16-bit thumb instruction) should
...
print out ldr, not ldr.n.
rdar://problem/9267772
llvm-svn: 130008
2011-04-22 19:12:43 +00:00
48592ee5af
Thumb2 BFC was insufficiently encoded.
...
rdar://problem/9292717
llvm-svn: 129619
2011-04-15 22:52:15 +00:00
761e1e3512
A8.6.315 VLD3 (single 3-element structure to all lanes)
...
The a bit must be encoded as 0.
rdar://problem/9292625
llvm-svn: 129618
2011-04-15 22:49:08 +00:00
421316178e
The ARM disassembler did not handle the alignment correctly for VLD*DUP* instructions
...
(single element or n-element structure to all lanes).
llvm-svn: 129550
2011-04-15 00:10:45 +00:00
4251b151b1
Add sanity checkings for Thumb2 Load/Store Register Exclusive family of operations.
...
llvm-svn: 129531
2011-04-14 19:13:28 +00:00
d0fb04f437
Thumb disassembler did not handle tBRIND (indirect branch) properly.
...
rdar://problem/9280370
llvm-svn: 129480
2011-04-13 21:59:01 +00:00
b6a37bff21
Check for unallocated instruction encodings when disassembling Thumb Branch instructions (tBcc and t2Bcc).
...
rdar://problem/9280470
llvm-svn: 129471
2011-04-13 21:35:49 +00:00
ffa6378fd6
The LDR*T/STR*T (unpriviledged load/store) operations don't take SP or PC as Rt.
...
rdar://problem/9279440
llvm-svn: 129469
2011-04-13 21:04:32 +00:00
70591cbc60
Check the corner cases for t2LDRSHi12 correctly and mark invalid encodings as such.
...
rdar://problem/9276651
llvm-svn: 129462
2011-04-13 19:46:05 +00:00
0d306a7840
Fix a bug where for t2MOVCCi disassembly, the TIED_TO register operand was not properly handled.
...
rdar://problem/9276427
llvm-svn: 129456
2011-04-13 17:51:02 +00:00
3c2f74c9f3
Add sanity check for Ld/St Dual forms of Thumb2 instructions.
...
rdar://problem/9273947
llvm-svn: 129411
2011-04-12 23:31:00 +00:00
960eef3db3
The Thumb2 RFE instructions need to have their second halfword fully specified.
...
In addition, the base register is not rGPR, but GPR with th exception that:
if n == 15 then UNPREDICTABLE
rdar://problem/9273836
llvm-svn: 129391
2011-04-12 21:41:51 +00:00
01637b9acb
Add bad register checks for Thumb2 Ld/St instructions.
...
rdar://problem/9269047
llvm-svn: 129387
2011-04-12 21:17:51 +00:00
ab86a519f8
The Thumb2 Ld, St, and Preload instructions with the i12 forms should have its Inst{23}
...
be specified as '1' (add = TRUE).
Also add a utility function for Thumb2.
llvm-svn: 129377
2011-04-12 18:48:00 +00:00
d0e2be39ea
Print out a debug message when the reglist fails the sanity check for Thumb Ld/St Multiple.
...
llvm-svn: 129365
2011-04-12 17:09:04 +00:00
f130b7f0f5
Add one test case (svc).
...
llvm-svn: 129327
2011-04-12 00:21:48 +00:00
672ef14a62
A8.6.16 B
...
Encoding T1 (tBcc)
if cond == '1110' then UNDEFINED;
rdar://problem/9268681
llvm-svn: 129325
2011-04-12 00:14:49 +00:00
dc8bf9ec08
Thumb disassembler was erroneously rejecting "blx sp" instruction.
...
rdar://problem/9267838
llvm-svn: 129320
2011-04-11 23:33:30 +00:00
f79d5365de
Fix the bug where the immediate shift amount for Thumb logical shift instructions are incorrectly disassembled.
...
rdar://problem/9266265
llvm-svn: 129298
2011-04-11 21:14:35 +00:00
66fab75920
Check invalid register encodings for LdFrm/StFrm ARM instructions and flag them as
...
invalid instructions.
llvm-svn: 129286
2011-04-11 18:34:12 +00:00
a9570f77d5
Hanlde the checking of bad regs for SMMLAR properly, instead of asserting.
...
PR9650
rdar://problem/9257565
llvm-svn: 129147
2011-04-08 19:41:22 +00:00
875e0e4626
Sanity check the option operand for DMB/DSB.
...
PR9648
rdar://problem/9257634
llvm-svn: 129146
2011-04-08 19:18:07 +00:00
74c74ba81c
MOVi16 and MOVTi16 does not allow pc as the dest register, while MOVi allows it.
...
Add tests for that.
llvm-svn: 129137
2011-04-08 17:29:58 +00:00
7e51b4640f
Add sanity checking for bad register specifier(s) for the DPFrm instructions.
...
Add more test cases to exercise the logical branches related to the above change.
llvm-svn: 129117
2011-04-08 00:29:09 +00:00
165a07adf9
Add a VEXT test.
...
llvm-svn: 129111
2011-04-07 22:04:01 +00:00
04efb8f6ce
Add sanity checking for invalid register encodings for signed/unsigned extend instructions.
...
Add some test cases.
llvm-svn: 129098
2011-04-07 19:28:58 +00:00
07606661f9
Add sanity checking for invalid register encodings for saturating instructions.
...
llvm-svn: 129096
2011-04-07 19:02:08 +00:00
194a2267ad
Add some more comments about checkings of invalid register numbers.
...
And two test cases.
llvm-svn: 129090
2011-04-07 18:33:19 +00:00
313ec7953a
Sanity check MSRi for invalid mask values and reject it as invalid.
...
rdar://problem/9246844
llvm-svn: 129050
2011-04-07 01:37:34 +00:00
c0e86fb965
The ARM disassembler was not recognizing USADA8 instruction. Need to add checking for register values
...
for USAD8 and USADA8.
rdar://problem/9247060
llvm-svn: 129047
2011-04-07 01:05:52 +00:00
d4cced54b3
Should also check SMLAD for invalid register values.
...
rdar://problem/9246650
llvm-svn: 129042
2011-04-07 00:50:25 +00:00
bd9a4f8d07
A8.6.393
...
The ARM disassembler should reject invalid (type, align) encodings as invalid instructions.
So, instead of:
Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1|
-------------------------------------------------------------------------------------------------
vst2.32 {d0, d2}, [r3, :256], r3
we now have:
Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1|
-------------------------------------------------------------------------------------------------
mc-input.txt:1:1: warning: invalid instruction encoding
0xb3 0x9 0x3 0xf4
^
llvm-svn: 129033
2011-04-06 22:14:48 +00:00
2ac486e387
A8.6.92 MCR (Encoding A1): if coproc == '101x' then SEE "Advanced SIMD and VFP"
...
Since these "Advanced SIMD and VFP" instructions have more specfic encoding bits
specified, if coproc == 10 or 11, we should reject the insn as invalid.
rdar://problem/9239922
rdar://problem/9239596
llvm-svn: 129027
2011-04-06 20:49:02 +00:00
8bca174f48
Fix a bug in the disassembly of VGETLNs8 where the lane index was wrong.
...
Also set the encoding bits (for A8.6.303, A8.6.328, A8.6.329) Inst{3-0} = 0b0000,
in class NVLaneOp.
rdar://problem/9240648
llvm-svn: 129015
2011-04-06 18:27:46 +00:00
0ec0e98a6a
Add a missing opcode (SMLSLDX) to BadRegsMulFrm() function.
...
Add more complete sanity check for LdStFrm instructions where if IBit (Inst{25})
is 1, Inst{4} should be 0. Otherwise, we should reject the insn as invalid.
rdar://problem/9239347
rdar://problem/9239467
llvm-svn: 128977
2011-04-06 01:18:32 +00:00
f6e327c6a3
Fix a typo in the handling of PKHTB opcode, plus add sanity check for illegal register
...
encodings for DisassembleArithMiscFrm().
rdar://problem/9238659
llvm-svn: 128958
2011-04-05 23:28:00 +00:00
c3656d29f6
A7.3 register encoding
...
Qd -> bit[12] == 0
Qn -> bit[16] == 0
Qm -> bit[0] == 0
If one of these bits is 1, the instruction is UNDEFINED.
rdar://problem/9238399
rdar://problem/9238445
llvm-svn: 128949
2011-04-05 22:57:07 +00:00
9da60e016b
ARM disassembler was erroneously accepting an invalid RSC instruction.
...
Added checks for regs which should not be 15.
rdar://problem/9237734
llvm-svn: 128945
2011-04-05 22:18:07 +00:00
25883487a1
ARM disassembler was erroneously accepting an invalid LSL instruction.
...
For register-controlled shifts, we should check that the encoding constraint
Inst{7} = 0 and Inst{4} = 1 is satisfied.
rdar://problem/9237693
llvm-svn: 128941
2011-04-05 21:49:44 +00:00
e9c644d4a0
The r128085 checkin modified the operand ordering for MRC/MRC2 instructions.
...
Modify DisassembleCoprocessor() of ARMDisassemblerCore.cpp to react to the change.
rdar://problem/9236873
llvm-svn: 128922
2011-04-05 20:32:23 +00:00
151582492d
ARM disassembler should flag (rGPRRegClassID, r13|r15) as an error.
...
llvm-svn: 128913
2011-04-05 19:42:11 +00:00
56c15c64b0
LDRD now prints out two dst registers.
...
llvm-svn: 128909
2011-04-05 18:53:14 +00:00
33d3a9fadc
Constants with multiple encodings (ARM):
...
An alternative syntax is available for a modified immediate constant that permits the programmer to specify
the encoding directly. In this syntax, #<const> is instead written as #<byte>,#<rot>, where:
<byte> is the numeric value of abcdefgh, in the range 0-255
<rot> is twice the numeric value of rotation, an even number in the range 0-30.
llvm-svn: 128897
2011-04-05 18:02:46 +00:00
268d63f307
Check for invalid register encodings for UMAAL and friends where:
...
if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE;
if dHi == dLo then UNPREDICTABLE;
rdar://problem/9230202
llvm-svn: 128895
2011-04-05 17:43:10 +00:00
9b3ccba636
Fix SRS/SRSW encoding bits.
...
rdar://problem/9230801 ARM disassembler discrepancy: erroneously accepting SRS
Plus add invalid-RFEorLDMIA-arm.txt test which should have been checked in with
http://llvm.org/viewvc/llvm-project?view=rev&revision=128859 .
llvm-svn: 128864
2011-04-05 00:16:18 +00:00
8372006296
Fix incorrect alignment for NEON VST2b32_UPD.
...
rdar://problem/9225433
llvm-svn: 128841
2011-04-04 20:35:31 +00:00
8904cc49db
Fixed a bug in disassembly of STR_POST, where the immediate is the second operand in am2offset;
...
instead of the second operand in addrmode_imm12.
rdar://problem/9225289
llvm-svn: 128757
2011-04-02 02:24:54 +00:00
387b36eaae
Fixed MOVr for "should be" encoding bits for Inst{19-16} = 0b0000.
...
rdar://problem/9224276
llvm-svn: 128749
2011-04-01 23:30:25 +00:00
6615fa1de0
MOVs should have Inst{19-16} as 0b0000, otherwise, the instruction is UNPREDICTABLE.
...
rdar://problem/9224120
llvm-svn: 128748
2011-04-01 23:15:50 +00:00
1e1010f56f
Fix the instruction table entries for AI1_adde_sube_s_irs multiclass definition so that
...
all the instruction have:
let Inst{31-27} = 0b1110; // non-predicated
Before, the ARM decoder was confusing:
> 0x40 0xf3 0xb8 0x80
as:
Opcode=16 Name=ADCSSrs Format=ARM_FORMAT_DPSOREGFRM(5)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------------------------------------------------------------------------------------------------
| 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0|
-------------------------------------------------------------------------------------------------
adcs pc, r8, r0, asr #6
since the cond field for ADCSSrs is a wild card, and so is ADCrs, with the ADCSSrs having Inst{20} as '1'.
Now, the AR decoder behaves correctly:
> 0x40 0xf3 0xb8 0x80
> END
Executing command: /Volumes/data/lldb/llvm/Debug+Asserts/bin/llvm-mc -disassemble -triple=arm-apple-darwin -debug-only=arm-disassembler mc-input.txt
Opcode=19 Name=ADCrs Format=ARM_FORMAT_DPSOREGFRM(5)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------------------------------------------------------------------------------------------------
| 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0|
-------------------------------------------------------------------------------------------------
adcshi pc, r8, r0, asr #6
>
rdar://problem/9223094
llvm-svn: 128746
2011-04-01 22:32:51 +00:00
3dfb80afbf
Fix a LDRT/LDRBT decoding bug where for Encoding A2, if Inst{4} != 0, we should reject the instruction
...
as invalid.
llvm-svn: 128734
2011-04-01 20:21:38 +00:00
fe6fba3fe6
Fix LDRi12 immediate operand, which was changed to be the second operand in $addrmode_imm12 => (ops GPR:$base, i32imm:$offsimm).
...
rdar://problem/9219356
llvm-svn: 128722
2011-04-01 18:26:38 +00:00
9cd9c4e5c9
Add a test case for a malformed LDC/LDC2 instructions with PUDW = 0b0000, which
...
amounts to an UNDEFINED instruction.
llvm-svn: 128668
2011-03-31 20:54:30 +00:00
7b203f9cae
Fix single word and unsigned byte data transfer instruction encodings so that
...
Inst{4} = 0.
rdar://problem/9213022
llvm-svn: 128662
2011-03-31 19:28:35 +00:00
13baa0e650
Add BLXi to the instruction table for disassembly purpose.
...
A8.6.23 BLX (immediate)
rdar://problem/9212921
llvm-svn: 128644
2011-03-31 17:53:50 +00:00
0ae2501fd2
Add a test case for thumb stc2 instruction.
...
llvm-svn: 128517
2011-03-30 01:02:06 +00:00
a0f0b5d9f0
Add a test case for MSRi.
...
llvm-svn: 128494
2011-03-29 21:52:02 +00:00
dcb29ae8ee
Add a thumb test file for printf (iOS 4.3).
...
llvm-svn: 128487
2011-03-29 21:09:30 +00:00
4bc2baeb28
A8.6.188 STC, STC2
...
The STC_OPTION and STC2_OPTION instructions should have their coprocessor option enclosed in {}.
rdar://problem/9200661
llvm-svn: 128478
2011-03-29 19:49:38 +00:00
7927569f05
Rename invalid-VLDMSDB-arm.txt to be invalid-VLDMSDB_UPD-arm.txt.
...
llvm-svn: 128477
2011-03-29 19:10:06 +00:00
ec6f76ed38
Add and modify some tests.
...
llvm-svn: 128476
2011-03-29 19:08:52 +00:00
d6c5a741b5
Get rid of the non-writeback versions VLDMDB and VSTMDB, which don't actually exist.
...
llvm-svn: 128461
2011-03-29 16:45:53 +00:00
f9cd139369
Fix ARM disassembly for PLD/PLDW/PLI which suffers from code rot and add some test cases.
...
Add comments to ThumbDisassemblerCore.h for recent change made for t2PLD disassembly.
llvm-svn: 128417
2011-03-28 18:41:58 +00:00
923f3dac01
Fixed the t2PLD and friends disassembly and add two test cases.
...
llvm-svn: 128322
2011-03-26 01:32:48 +00:00
1572bf40b4
Add test for A8.6.246 UMULL to both arm-tests.txt amd thumb-tests.txt.
...
llvm-svn: 128306
2011-03-25 23:02:58 +00:00
6e31bf1f6f
Add two test cases t2SMLABT and t2SMMULR for DisassembleThumb2Mul().
...
llvm-svn: 128305
2011-03-25 22:43:28 +00:00
49316e40ba
Fix DisassembleThumb2DPReg()'s handling of RegClass. Cannot hardcode GPRRegClassID.
...
Also add some test cases.
rdar://problem/9189829
llvm-svn: 128304
2011-03-25 22:19:07 +00:00
aaf2c69400
DisassembleThumb2LdSt() did not handle t2LDRs correctly with respect to RegClass. Add two test cases.
...
rdar://problem/9182892
llvm-svn: 128299
2011-03-25 19:35:37 +00:00
4fd2194638
A8.6.226 TBB, TBH:
...
Add two test cases.
llvm-svn: 128295
2011-03-25 18:40:21 +00:00
b35548f44d
Modify DisassembleThumb2LdStEx() to be more robust/correct in light of recent change to
...
t2LDREX/t2STREX instructions. Add two test cases.
llvm-svn: 128293
2011-03-25 18:29:49 +00:00
aa84d41dfc
Instruction formats of SWP/SWPB were changed from LdStExFrm to MiscFrm. Modify the disassembler to handle that.
...
rdar://problem/9184053
llvm-svn: 128285
2011-03-25 17:31:16 +00:00
757ca69770
Also need to handle invalid imod values for CPS2p.
...
rdar://problem/9186136
llvm-svn: 128283
2011-03-25 17:03:12 +00:00
a52143bff3
Modify the wrong logic in the assert of DisassembleThumb2LdStDual() (the register classes were changed),
...
modify the comment to be up-to-date, and add a test case for A8.6.66 LDRD (immediate) Encoding T1.
llvm-svn: 128252
2011-03-25 01:09:48 +00:00
72f4a95144
delegate the disassembly of t2ADR to the more generic t2ADDri12/t2SUBri12 instructions, and add a test case for that.
...
llvm-svn: 128249
2011-03-25 00:17:42 +00:00
ceef55466a
The opcode names ("tLDM", "tLDM_UPD") used for conflict resolution have been stale since
...
the change to ("tLDMIA", "tLDMIA_UPD"). Update the conflict resolution code and add
test cases for that.
llvm-svn: 128247
2011-03-24 23:42:31 +00:00
73193f2475
The ARM disassembler was confused with the 16-bit tSTMIA instruction.
...
According to A8.6.189 STM/STMIA/STMEA (Encoding T1), there's only tSTMIA_UPD available.
Ignore tSTMIA for the decoder emitter and add a test case for that.
llvm-svn: 128246
2011-03-24 23:21:14 +00:00
9302df0ad9
Handle the added VBICiv*i* NEON instructions, too.
...
llvm-svn: 128243
2011-03-24 22:04:39 +00:00
6469ca0c33
T2 Load/Store Multiple:
...
These instructions were changed to not embed the addressing mode within the MC instructions
We also need to update the corresponding assert stmt. Also add a test case.
llvm-svn: 128240
2011-03-24 21:36:56 +00:00
dd9eb21c3f
Plug a leak in the arm disassembler and put the tests back.
...
llvm-svn: 128238
2011-03-24 21:14:28 +00:00
471f5aa233
Remove these two test files as they cause llvm-i686-linux-vg_leak build to fail 'test-llvm'.
...
These two are test cases which should result in 'invalid instruction encoding' from running llvm-mc -disassemble.
llvm-svn: 128235
2011-03-24 20:56:23 +00:00
8bbc12824a
ADR was added with the wrong encoding for inst{24-21}, and the ARM decoder was fooled.
...
Set the encoding bits to {0,?,?,0}, not 0. Plus delegate the disassembly of ADR to
the more generic ADDri/SUBri instructions, and add a test case for that.
llvm-svn: 128234
2011-03-24 20:42:48 +00:00
c5207f7167
The r118201 added support for VORR (immediate). Update ARMDisassemblerCore.cpp to disassemble the
...
VORRiv*i* instructions properly within the DisassembleN1RegModImmFrm() function. Add a test case.
llvm-svn: 128226
2011-03-24 18:40:38 +00:00
1dd041083d
Add comments to the handling of opcode CPS3p to reject invalid instruction encoding,
...
a test case of invalid CPS3p encoding and one for invalid VLDMSDB due to regs out of range.
llvm-svn: 128220
2011-03-24 17:04:22 +00:00
0f5d52d658
Load/Store Multiple:
...
These instructions were changed to not embed the addressing mode within the MC instructions
We also need to update the corresponding assert stmt. Also add two test cases.
llvm-svn: 128191
2011-03-24 01:40:42 +00:00
1de8cc6f95
STRT and STRBT was incorrectly tagged as IndexModeNone during the refactorings (r119821).
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We now tag them as IndexModePost.
llvm-svn: 128189
2011-03-24 01:07:26 +00:00
f949d8e13d
The r128103 fix to cope with the removal of addressing modes from the MC instructions
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were incomplete. The assert stmt needs to be updated and the operand index incrment is wrong.
Fix the bad logic and add some sanity checking to detect bad instruction encoding;
and add a test case.
llvm-svn: 128186
2011-03-24 00:28:38 +00:00
122a6304ef
Add disassembly test cases for:
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A8.6.292 VCMPE
llvm-svn: 128120
2011-03-22 23:08:56 +00:00
30350cdbdf
LDRT and LDRBT was incorrectly tagged as IndexModeNone during the refactorings (r119821).
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We now tag them as IndexModePost.
This fixed http://llvm.org/bugs/show_bug.cgi?id=9530 .
llvm-svn: 128113
2011-03-22 22:28:49 +00:00
0cf62f5045
Add one more test case for VFP Load/Store Multiple (vpop).
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llvm-svn: 128106
2011-03-22 20:21:08 +00:00
230268261b
A8.6.399 VSTM:
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VFP Load/Store Multiple Instructions used to embed the IA/DB addressing mode within the
MC instruction; that has been changed so that now, for example, VSTMDDB_UPD and VSTMDIA_UPD
are two instructions. Update the ARMDisassemblerCore.cpp's DisassembleVFPLdStMulFrm()
to reflect the change.
Also add a test case.
llvm-svn: 128103
2011-03-22 20:00:10 +00:00
0c5f670fe7
Fixed an assert by the ARM disassembler for LDRD_PRE/POST.
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The relevant instruction table entries were changed sometime ago to no longer take
<Rt2> as an operand. Modify ARMDisassemblerCore.cpp to accomodate the change and
add a test case.
llvm-svn: 127935
2011-03-19 01:16:20 +00:00
e387f8a5e9
The disassembler for Thumb was wrongly adding 4 to the computed imm32 offset.
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Remove the offending logic and update the test cases.
llvm-svn: 127843
2011-03-18 00:38:03 +00:00
221a014ea3
It used to be that t_addrmode_s4 was used for both:
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o A8.6.195 STR (register) -- Encoding T1
o A8.6.193 STR (immediate, Thumb) -- Encoding T1
It has been changed so that now they use different addressing modes
and thus different MC representation (Operand Infos). Modify the
disassembler to reflect the change, and add relevant tests.
llvm-svn: 127833
2011-03-17 22:04:05 +00:00
a4c3154fca
There were two issues fixed:
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1. The ARM Darwin *r9 call instructions were pseudo-ized recently.
Modify the ARMDisassemblerCore.cpp file to accomodate the change.
2. The disassembler was unnecessarily adding 8 to the sign-extended imm24:
imm32 = SignExtend(imm24:'00', 32); // A8.6.23 BL, BLX (immediate)
// Encoding A1
It has no business doing such. Removed the offending logic.
Add test cases to arm-tests.txt.
llvm-svn: 127707
2011-03-15 22:27:33 +00:00
f2f4837de3
Basic sanity checks to ensure that 2- and 3-byte
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VEX prefixes are working for triadic AVX
instructions. This concludes the patch set to
enable AVX support for the X86 disassebler.
llvm-svn: 127647
2011-03-15 01:32:46 +00:00
7a2873dfbe
Fixed an ARM disassembler bug where it does not handle STRi12 correctly because an extra
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register operand was erroneously added. Remove an incorrect assert which triggers the bug.
rdar://problem/9131529
llvm-svn: 127642
2011-03-15 01:13:17 +00:00
9363d41f14
LLVM combines the offset mode of A8.6.199 A1 & A2 into STRBT.
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The insufficient encoding information of the combined instruction confuses the decoder wrt
UQADD16. Add extra logic to recover from that.
Fixed an assert reported by Sean Callanan
llvm-svn: 127354
2011-03-09 20:01:14 +00:00
6f6d739b6e
TableGen should not ignore BX instructions for the ARM disassembler. pr9368.
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llvm-svn: 126931
2011-03-03 07:19:52 +00:00
ec84568904
pr9367: Add missing predicated BLX instructions.
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Patch by Jyun-Yan You, with some minor adjustments and a testcase from me.
llvm-svn: 126915
2011-03-03 01:41:01 +00:00
b8b6041734
Fixes an assertion failure while disassembling ARM rsbs reg/reg form.
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Patch by Ted Kremenek!
llvm-svn: 126895
2011-03-02 23:08:33 +00:00
58775fea6f
Fix the arm's disassembler for blx that was building an MCInst without the
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needed two predicate operands before the imm operand.
llvm-svn: 126662
2011-02-28 18:46:31 +00:00
34770edf43
Fixed a bug in the enhanced disassembler that caused
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it to ignore valid uses of FS and GS as additional
base registers in address computations. Added a test
case for this.
llvm-svn: 126302
2011-02-23 03:31:28 +00:00
c1b7775e0f
Added a testcase for the enhanced disassembly bug
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fixed in r126147, where a field in the X86 decode
structure was being read as bits, not bytes.
llvm-svn: 126182
2011-02-22 02:19:18 +00:00
9cd43977c3
Add assembly parsing support for "msr" and also fix its encoding. Also add
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testcases for the disassembler to make sure it still works for "msr".
llvm-svn: 125948
2011-02-18 19:45:59 +00:00
90d1dfe4c6
Fix encoding and add parsing support for the arm/thumb CPS instruction:
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- Add custom operand matching for imod and iflags.
- Rename SplitMnemonicAndCC to SplitMnemonic since it splits more than CC
from mnemonic.
- While adding ".w" as an operand, don't change "Head" to avoid passing the
wrong mnemonic to ParseOperand.
- Add asm parser tests.
- Add disassembler tests just to make sure it can catch all cps versions.
llvm-svn: 125489
2011-02-14 13:09:44 +00:00
4ebf471c9b
Revert both r121082 (which broke a bunch of constant pool stuff) and r125074 (which worked around it). This should get us back to the old, correct behavior, though it will make the integrated assembler unhappy for the time being.
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llvm-svn: 125127
2011-02-08 22:39:40 +00:00
775eec2280
PR9030: Fix disassembly of ARM "mov pc, lr" instruction.
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Patch by Jyun-Yan You.
llvm-svn: 124492
2011-01-28 17:50:30 +00:00
ec47597ecd
As far as I can tell, unified syntax uses c0-c15 instead of cr0-cr15 for mcr and friends.
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llvm-svn: 123407
2011-01-13 22:38:16 +00:00
9f9a10691a
Correctly disassemble truncated asm.
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Patch by Richard Simth.
llvm-svn: 122962
2011-01-06 16:48:42 +00:00
ae58e7b179
Teach the MBlaze disassembler to disassemble special purpose registers.
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llvm-svn: 122269
2010-12-20 21:18:04 +00:00
99ea8a3510
Second attempt at converting Thumb2's LDRpci, including updating the gazillion places that need to know about it.
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llvm-svn: 121082
2010-12-07 00:45:21 +00:00
Joey Gouly