976c93a110
implemented sub
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correctly update the stack pointer in the prologue and epilogue
llvm-svn: 29244
2006-07-21 12:26:16 +00:00
74065bedf2
This opt is now handled in DAG combine.
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llvm-svn: 29243
2006-07-21 08:26:46 +00:00
4cf0238720
A splat of a vector constant of all zero or all one is the vector constant.
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llvm-svn: 29234
2006-07-20 23:09:47 +00:00
f98bc5288e
Missing a space.
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llvm-svn: 29233
2006-07-20 22:52:28 +00:00
683b966485
Clean up.
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llvm-svn: 29228
2006-07-20 21:37:39 +00:00
8a881f2309
New entry.
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llvm-svn: 29215
2006-07-19 21:29:30 +00:00
181fb1c4d7
Do once flag never set to true.
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llvm-svn: 29214
2006-07-19 19:33:08 +00:00
7c860afec6
Tidy up a few things.
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llvm-svn: 29213
2006-07-19 19:32:06 +00:00
18debc21db
Reduce size of routine. Shrinks .o by 37%.
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llvm-svn: 29210
2006-07-19 17:53:32 +00:00
4f8eb5ccaf
bswapped load/store instructions are only availble in indexed addressing form.
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As such, use xoaddr (indexed only), not xaddr for address selection.
This fixes CodeGen/PowerPC/2006-07-19-stwbrx-crash.ll, a crash compiling lencod.
llvm-svn: 29208
2006-07-19 17:15:36 +00:00
5ba7c23cdd
Bug#834 ICE (crash in code generator?) when building PCH .
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Missing Darwin check in Intel ATT ASM printer.
llvm-svn: 29204
2006-07-19 11:54:50 +00:00
968a0b0309
Misc. new entry.
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llvm-svn: 29202
2006-07-19 06:06:24 +00:00
02d8836cd5
INC / DEC instructions have shorter code size than ADD32ri8, etc.
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llvm-svn: 29194
2006-07-19 00:27:29 +00:00
c767acd25a
Add code size to target instruction use it as the 3rd isel sorting tie-breaker.
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llvm-svn: 29193
2006-07-19 00:24:41 +00:00
bf3a17cd32
initial prologue and epilogue implementation. Need to define add and sub before finishing it :-)
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llvm-svn: 29175
2006-07-18 17:00:30 +00:00
b00b6c2e86
Make the implicit def instructions look like other instrs.
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llvm-svn: 29174
2006-07-18 16:33:26 +00:00
75269be065
skeleton of a lowerCall implementation for ARM
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llvm-svn: 29159
2006-07-16 01:02:57 +00:00
e1758d4cef
Remove what little AIX support we have. It has never been tested and isn't
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complete.
llvm-svn: 29156
2006-07-15 01:24:23 +00:00
2e1d01541a
Add an out-of-line virtual method for X86DwarfWriter to give it a home.
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llvm-svn: 29153
2006-07-14 23:05:05 +00:00
96aecb5d76
Add missing PPC64 extload/truncstores
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llvm-svn: 29140
2006-07-14 04:42:02 +00:00
950dffaed6
Add a note
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llvm-svn: 29139
2006-07-14 04:07:29 +00:00
077b86a078
Another fix in the rotate encodings, needed when the first two operands are not
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the same.
llvm-svn: 29136
2006-07-13 21:52:41 +00:00
b42a945fd2
Print negative immediates as negative values instead of large constants
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when using the immshifted addressing mode.
llvm-svn: 29130
2006-07-12 23:24:02 +00:00
dd57ac4871
Fix encoding of rotates, such as rldicl
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llvm-svn: 29128
2006-07-12 22:08:13 +00:00
5b17dee741
Implement PPC64 relocations types
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llvm-svn: 29125
2006-07-12 21:23:20 +00:00
1ec5e73b32
An overaggressive #ifdef allows a function to fall off the bottom of the
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function instead of returning a value. This sometimes allowed the ppc32 jit
to be used in 64-bit mode.
llvm-svn: 29123
2006-07-12 20:42:10 +00:00
c8db10725b
Add information preventing several register class constraints from working.
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This implements PR828 and CodeGen/X86/2006-07-12-InlineAsmQConstraint.ll
llvm-svn: 29118
2006-07-12 16:59:49 +00:00
6e662083d9
The PPC64 JIT needs register numbers to encode instructions.
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llvm-svn: 29114
2006-07-11 20:53:55 +00:00
d5a086ab12
Emit inc / dec of registers as one byte instruction.
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llvm-svn: 29110
2006-07-11 19:49:49 +00:00
f7300b2706
It was pointed out that DEBUG() is only available with -debug.
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llvm-svn: 29106
2006-07-11 18:25:13 +00:00
c3d341ea98
Ensure that dump calls that are associated with asserts are removed from
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non-debug build.
llvm-svn: 29105
2006-07-11 17:58:07 +00:00
185c5c2bdf
add the memri memory operand
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this makes it possible for ldr instructions with non-zero immediate
llvm-svn: 29103
2006-07-11 11:36:48 +00:00
298ef37e02
Implement the inline asm 'A' constraint. This implements PR825 and
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CodeGen/X86/2006-07-10-InlineAsmAConstraint.ll
llvm-svn: 29101
2006-07-11 02:54:03 +00:00
71227c23b1
In 64-bit mode, 64-bit GPRs are callee saved, not 32-bit ones.
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llvm-svn: 29096
2006-07-11 00:48:23 +00:00
32860f42bb
New entry.
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llvm-svn: 29091
2006-07-10 21:42:16 +00:00
79cf9a5342
Fixed stack objects do not specify alignments, but their offsets are known.
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Use that information when doing the transformation to merge multiple loads
into a 128-bit load.
llvm-svn: 29090
2006-07-10 21:37:44 +00:00
a7976d329e
Implement Regression/CodeGen/PowerPC/bswap-load-store.ll by folding bswaps
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into i16/i32 load/stores.
llvm-svn: 29089
2006-07-10 20:56:58 +00:00
9aabc1e16f
Mark internal function static
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llvm-svn: 29085
2006-07-10 19:53:12 +00:00
e40a7e2aa2
create the raddr addressing mode that matches any register and the frame index
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use raddr for the ldr instruction. This removes a dummy mov from the assembly output
remove SelectFrameIndex
remove isLoadFromStackSlot
remove isStoreToStackSlot
llvm-svn: 29079
2006-07-10 01:41:35 +00:00
af5ae57333
Fix a typo that causes 2006-07-07-ComputeMaskedBits.ll to fail.
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llvm-svn: 29072
2006-07-07 21:37:21 +00:00
5987cfb7b1
X86 target specific DAG combine: turn build_vector (load x), (load x+4),
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(load x+8), (load x+12), <0, 1, 2, 3> to a single 128-bit load (aligned and
unaligned).
e.g.
__m128 test(float a, float b, float c, float d) {
return _mm_set_ps(d, c, b, a);
}
_test:
movups 4(%esp), %xmm0
ret
llvm-svn: 29042
2006-07-07 08:33:52 +00:00
59b6e8a683
Undisable ppc64 jit
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llvm-svn: 29011
2006-07-06 17:10:42 +00:00
0441746468
Added option -code-model to set code model (only used in 64-bit) mode. Valid
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values include small, kernel, medium, large, and default.
llvm-svn: 29009
2006-07-06 01:53:36 +00:00
0261242aa6
Reorg. No functionality change.
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llvm-svn: 28999
2006-07-05 22:17:51 +00:00
41816100f4
Fix JIT on non MacOS X i386 systems.
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llvm-svn: 28992
2006-07-05 07:09:13 +00:00
01078dc60b
These are already implemented
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llvm-svn: 28990
2006-07-03 18:00:29 +00:00
042f5076ed
0 offsets for memory operands
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llvm-svn: 28989
2006-07-03 17:57:34 +00:00
390922f979
Should just use xorps to clear XMM registers for all data types. pxor is also one byte longer.
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llvm-svn: 28984
2006-06-29 18:04:54 +00:00
28a95491d9
Let X86CompilationCallback pass previous frame and return address to X86CompilationCallback2. Remove alloca hack.
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llvm-svn: 28982
2006-06-29 01:48:36 +00:00
fa9e60895b
Add shift and rotate by 1 instructions / patterns.
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llvm-svn: 28980
2006-06-29 00:36:51 +00:00
Rafael Espindola