798493285c
In LowerEXTRACT_VECTOR_ELT, force an i32 value type for PEXTWR instead of
...
incrementing the simple value type of the 16-bit type, which would give the
wrong type if an intemediate MVT (such as i24) were introduced.
llvm-svn: 91602
2009-12-17 15:31:52 +00:00
7f30b64dce
Renamed "tCMNZ" to "tCMNz" to be consistent with other similar namings.
...
llvm-svn: 91571
2009-12-16 23:36:52 +00:00
30f2ac714b
Silence a clang warning about the deprecated (but perfectly reasonable in
...
context) increment-of-bool idiom.
llvm-svn: 91564
2009-12-16 20:31:50 +00:00
69461f50c1
Mark STREX* as earlyclobber for the success result register.
...
llvm-svn: 91555
2009-12-16 19:44:06 +00:00
466231ab92
Add encoding bits for some Thumb instructions. Plus explicitly set the top two
...
bytes of Inst to 0x0000 for the benefit of the Thumb decoder.
llvm-svn: 91496
2009-12-16 02:32:54 +00:00
1be6286028
Re-enable 91381 with fixes.
...
llvm-svn: 91489
2009-12-16 00:53:11 +00:00
826ca5630e
Every anonymous namespace is different. Caught by clang++.
...
llvm-svn: 91481
2009-12-16 00:15:28 +00:00
e0d8e14e11
Change indirect-globals to use a dedicated allocIndirectGV. This lets us
...
remove start/finishGVStub and the BufferState helper class from the
MachineCodeEmitter interface. It has the side-effect of not setting the
indirect global writable and then executable on ARM, but that shouldn't be
necessary.
llvm-svn: 91464
2009-12-15 22:42:46 +00:00
c28e629c2d
Added encoding bits for the Thumb ISA. Initial checkin.
...
llvm-svn: 91434
2009-12-15 17:24:14 +00:00
b3032962ef
Fix an encoding bug.
...
llvm-svn: 91417
2009-12-15 06:49:02 +00:00
792f0913ee
For fastcc on x86, let ECX be used as a return register after EAX and EDX
...
llvm-svn: 91410
2009-12-15 03:27:52 +00:00
fcb5453dc7
Disable 91381 for now. It's miscompiling ARMISelDAG2DAG.cpp.
...
llvm-svn: 91405
2009-12-15 03:07:11 +00:00
0e8b9e32d1
Use sbb x, x to materialize carry bit in a GPR. The result is all one's or all zero's.
...
llvm-svn: 91381
2009-12-15 00:53:42 +00:00
ea8f6e31a0
nand atomic requires opposite operand ordering
...
llvm-svn: 91371
2009-12-15 00:12:35 +00:00
cecad35728
Fix integer cast code to handle vector types.
...
llvm-svn: 91362
2009-12-14 23:40:38 +00:00
bee6f16fed
Add encoding bits "let Inst{11-4} = 0b00000000;" to BR_JTr to disambiguate
...
between BR_JTr and STREXD.
llvm-svn: 91339
2009-12-14 21:51:34 +00:00
3974a80307
v6 sync insn copy/paste error
...
llvm-svn: 91333
2009-12-14 21:33:32 +00:00
3c4f04112a
Add ARMv6 memory and sync barrier instructions
...
llvm-svn: 91329
2009-12-14 21:24:16 +00:00
acba3b0ae2
Fixed encoding bits typo of ldrexd/strexd.
...
llvm-svn: 91327
2009-12-14 21:01:46 +00:00
57ccc19617
Thumb2 atomic operations
...
llvm-svn: 91321
2009-12-14 20:14:59 +00:00
726e452ccb
fix an obvious bug found by clang++ and collapse a redundant if.
...
Here's the diagnostic from clang:
/Volumes/Data/dgregor/Projects/llvm/lib/Target/CppBackend/CPPBackend.cpp:989:23: warning: 'gv' is always NULL in this context
printConstant(gv);
^
1 diagnostic generated.
llvm-svn: 91318
2009-12-14 19:34:32 +00:00
fed3d088ce
correct selection requirements for thumb2 vs. arm versions of the barrier intrinsics
...
llvm-svn: 91313
2009-12-14 19:24:11 +00:00
20ac87de13
add Thumb2 atomic and memory barrier instruction definitions
...
llvm-svn: 91310
2009-12-14 18:56:47 +00:00
3cdb555e0f
whitespace
...
llvm-svn: 91307
2009-12-14 18:36:32 +00:00
5e0d2a2df6
ARM memory barrier instructions are not predicable
...
llvm-svn: 91305
2009-12-14 18:31:20 +00:00
9d6410d040
add ldrexd/strexd instructions
...
llvm-svn: 91284
2009-12-14 17:02:55 +00:00
277381f69a
Whitespace changes, comment clarification. No functional changes.
...
llvm-svn: 91274
2009-12-14 06:51:19 +00:00
8f3c70e909
atomic binary operations up to 32-bits wide.
...
llvm-svn: 91260
2009-12-14 04:22:04 +00:00
45800ce646
Do not allow uninitialize access during debug printing
...
llvm-svn: 91232
2009-12-13 01:00:32 +00:00
96cf7f42b0
More info on this transformation.
...
llvm-svn: 91230
2009-12-12 23:23:43 +00:00
8eada9f580
Remove some stuff that's already implemented. Also, remove the note about
...
merging x >u 5 and x <s 20 because it's impossible to implement.
llvm-svn: 91228
2009-12-12 21:41:48 +00:00
26fdd7265b
Disable r91104 for x86. It causes partial register stall which pessimize code in 32-bit.
...
llvm-svn: 91223
2009-12-12 20:03:14 +00:00
d8f320947f
Implement variable-width shifts.
...
No testcase yet - it seems we're exposing generic codegen bugs.
llvm-svn: 91221
2009-12-12 18:55:37 +00:00
3974c8de51
Add comment about potential partial register stall.
...
llvm-svn: 91220
2009-12-12 18:55:26 +00:00
6d6eaafa8c
Fix an obvious bug. No test case since LEA16r is not being used.
...
llvm-svn: 91219
2009-12-12 18:51:56 +00:00
8f9a3ac12c
Framework for atomic binary operations. The emitter for the pseudo instructions
...
just issues an error for the moment. The front end won't yet generate these
intrinsics for ARM, so this is behind the scenes until complete.
llvm-svn: 91200
2009-12-12 01:40:06 +00:00
e27e028cdd
Lower setcc branchless, if this is profitable.
...
Based on the patch by Brian Lucas!
llvm-svn: 91175
2009-12-11 23:01:29 +00:00
1d459e4937
Implement vector widening, splitting, and scalarizing for SIGN_EXTEND_INREG.
...
llvm-svn: 91158
2009-12-11 21:31:27 +00:00
22a4ea8690
memory barrier instructions by definition have side effects. This prevents the post-RA scheduler from moving them around.
...
llvm-svn: 91150
2009-12-11 20:29:53 +00:00
fc51282cbe
Honour setHasCalls() set from isel.
...
This is used in some weird cases like general dynamic TLS model.
This fixes PR5723
llvm-svn: 91144
2009-12-11 19:39:55 +00:00
098bd1bbea
Store Register Exclusive should leave the source register Inst{3-0} unspecified.
...
llvm-svn: 91143
2009-12-11 19:37:26 +00:00
afdddaed55
Update properties.
...
llvm-svn: 91140
2009-12-11 18:52:41 +00:00
766a73fb04
Add support to 3-addressify 16-bit instructions.
...
llvm-svn: 91104
2009-12-11 06:01:48 +00:00
5c4e99fca6
Rough first pass at compare_and_swap atomic builtins for ARM mode. Work in progress.
...
llvm-svn: 91090
2009-12-11 01:42:04 +00:00
fed78ccfb5
Add instruction encoding for DMB/DSB
...
llvm-svn: 91053
2009-12-10 18:35:32 +00:00
53e8854443
Add memory barrier intrinsic support for ARM. Moving towards adding the atomic operations intrinsics.
...
llvm-svn: 91003
2009-12-10 00:11:09 +00:00
493b882f80
Optimize splat of a scalar load into a shuffle of a vector load when it's legal. e.g.
...
vector_shuffle (scalar_to_vector (i32 load (ptr + 4))), undef, <0, 0, 0, 0>
=>
vector_shuffle (v4i32 load ptr), undef, <1, 1, 1, 1>
iff ptr is 16-byte aligned (or can be made into 16-byte aligned).
llvm-svn: 90984
2009-12-09 21:00:30 +00:00
d938faff4b
Teach InferPtrAlignment to infer GV+cst alignment and use it to simplify x86 isl lowering code.
...
llvm-svn: 90925
2009-12-09 01:53:58 +00:00
f5938d5d27
Move isConsecutiveLoad to SelectionDAG. It's not target dependent and it's primary used by selectdag passes.
...
llvm-svn: 90922
2009-12-09 01:36:00 +00:00
0c2544fd6b
- Support inline asm 'w' constraint for 128-bit vector types.
...
- Also support the 'q' NEON registers asm code.
llvm-svn: 90894
2009-12-08 23:06:22 +00:00
dd2b2f8cba
Reduce (cmp 0, and_su (foo, bar)) into (bit foo, bar). This saves extra instruction. Patch inspired by Brian Lucas!
...
llvm-svn: 90819
2009-12-08 01:03:04 +00:00
9528ccdd77
Don't enable the post-RA scheduler on x86 except at -O3. In its
...
current form, it is too expensive in compile time.
llvm-svn: 90781
2009-12-07 19:04:31 +00:00
24a6316aaa
Some pretty-printing
...
llvm-svn: 90742
2009-12-07 02:28:41 +00:00
ff4ab51400
Add lowering of returnaddr and frameaddr intrinsics. Shamelessly stolen from x86 :)
...
llvm-svn: 90740
2009-12-07 02:28:10 +00:00
b4be8ce537
Initial codegen support for MSP430 ISRs
...
llvm-svn: 90739
2009-12-07 02:27:53 +00:00
28d3c733aa
Add ability to select hw multiplier mode and select appropriate libcalls.
...
llvm-svn: 90737
2009-12-07 02:27:08 +00:00
75dfed4fa5
Dynamic stack realignment use of sp register as source/dest register
...
in "bic sp, sp, #15" leads to unpredicatble behaviour in Thumb2 mode.
Emit the following code instead:
mov r4, sp
bic r4, r4, #15
mov sp, r4
llvm-svn: 90724
2009-12-06 22:39:50 +00:00
29d6390249
Calling InvalidateEntry during the refinement was breaking the bootstrap.
...
llvm-svn: 90656
2009-12-05 07:59:04 +00:00
fa3f115ec4
Final cleanups:
...
- Privatize a typedef.
- Call the InvalidateEntry when refining a type.
llvm-svn: 90655
2009-12-05 07:46:49 +00:00
4968774280
Inline methods which are called only once.
...
llvm-svn: 90640
2009-12-05 01:46:01 +00:00
da95e13750
Refactor some code. No functionality change.
...
llvm-svn: 90639
2009-12-05 01:43:33 +00:00
047a767d74
Remove the target hook TargetInstrInfo::BlockHasNoFallThrough in favor of
...
MachineBasicBlock::canFallThrough(), which is target-independent and more
thorough.
llvm-svn: 90634
2009-12-05 00:44:40 +00:00
86bafa29a3
Remove an unneeded include.
...
llvm-svn: 90625
2009-12-04 23:55:07 +00:00
0508e435c3
Have hasLoad/StoreFrom/ToStackSlot return the relevant MachineMemOperand.
...
llvm-svn: 90608
2009-12-04 22:38:46 +00:00
4ea0d2b8ee
Some code cleanup. No functionality change.
...
llvm-svn: 90588
2009-12-04 21:03:02 +00:00
5f9f721e95
remove out of date FIXME.
...
llvm-svn: 90490
2009-12-03 21:55:01 +00:00
f05330a5c8
expand note.
...
llvm-svn: 90429
2009-12-03 07:43:46 +00:00
d1e4ee3c2b
add a note
...
llvm-svn: 90428
2009-12-03 07:41:54 +00:00
c831fac043
fix a build problem with VC++, PR5664, patch by Alp Toker!
...
llvm-svn: 90419
2009-12-03 06:58:32 +00:00
0bbd3077ce
Recognize canonical forms of vector shuffles where the same vector is used for
...
both source operands. In the canonical form, the 2nd operand is changed to an
undef and the shuffle mask is adjusted to only reference elements from the 1st
operand. Radar 7434842.
llvm-svn: 90417
2009-12-03 06:40:55 +00:00
aba7d48764
Revert r90371. It was causing build failures.
...
llvm-svn: 90383
2009-12-03 01:54:07 +00:00
693969eb35
Further improvements: refactoring code that does the same thing into one
...
function, converting "dyn_cast" to "cast", asserting the correct things, and
other general cleanups.
llvm-svn: 90371
2009-12-03 01:15:46 +00:00
765ac33a1a
yay for case insensitive file systems (?)
...
llvm-svn: 90370
2009-12-03 01:10:05 +00:00
73570673de
remove some dead std::ostream using code.
...
llvm-svn: 90366
2009-12-03 00:55:04 +00:00
a48f44d9ee
improve portability to avoid conflicting with std::next in c++'0x.
...
Patch by Howard Hinnant!
llvm-svn: 90365
2009-12-03 00:50:42 +00:00
1ed59c63e3
This initial code is meant to convert TargetData to use an AbstractTypesUser so
...
that it doesn't have dangling pointers when abstract types are resolved. This
modifies it somewhat to address comments: making the "StructLayoutMap" an
anonymous structure, calling "removeAbstractTypeUser" when appropriate, and
adding asserts where helpful.
llvm-svn: 90362
2009-12-03 00:17:12 +00:00
2c3a6c6589
Factor the stack alignment calculations out into a target independent pass.
...
No functionality change.
llvm-svn: 90336
2009-12-02 19:30:24 +00:00
36d4dec28a
Thumb1 exception handling setjmp
...
llvm-svn: 90246
2009-12-01 18:10:36 +00:00
86fc920742
For VLDM/VSTM (Advanced SIMD), set encoding bits Inst{11-8} to 0b1011.
...
llvm-svn: 90243
2009-12-01 17:37:06 +00:00
ee536b0ea4
For VMOV (immediate), make some of the encoding bits (cmode and op) unspecified.
...
For VMOVv*i[16,32], op bit is don't care, and some cmode bits vary depending on
the immediate values.
Ref: Table A7-15 Modified immediate values for Advanced SIMD instructions.
llvm-svn: 90173
2009-12-01 00:02:02 +00:00
3ee8bc9b35
Minor whitespace fixes.
...
llvm-svn: 90166
2009-11-30 23:33:53 +00:00
6f51309021
Fix a minor inconsistency.
...
llvm-svn: 90165
2009-11-30 23:33:37 +00:00
505ddaa4dc
Remove isProfitableToDuplicateIndirectBranch target hook. It is profitable
...
for all the processors where I have tried it, and even when it might not help
performance, the cost is quite low. The opportunities for duplicating
indirect branches are limited by other factors so code size does not change
much due to tail duplicating indirect branches aggressively.
llvm-svn: 90144
2009-11-30 18:35:03 +00:00
c168a52627
Fix some more ARM unified syntax warnings.
...
llvm-svn: 90141
2009-11-30 17:47:19 +00:00
32f8bb9ed4
Added support to allow clients to custom widen. For X86, custom widen vectors for
...
divide/remainder since these operations can trap by unroll them and adding undefs
for the resulting vector.
llvm-svn: 90108
2009-11-30 02:42:02 +00:00
58ccf88c36
update and consolidate the load pre notes.
...
llvm-svn: 90050
2009-11-29 02:19:52 +00:00
83a4a9868f
add a deadargelim note.
...
llvm-svn: 90009
2009-11-27 17:12:30 +00:00
ca9e0e83b3
This testcase is actually only partially redundant, and requires
...
the FIXME I added yesterday to be implemented.
llvm-svn: 90008
2009-11-27 16:53:57 +00:00
cc6d29286c
this (and probably several others) are now done.
...
llvm-svn: 89982
2009-11-27 00:35:04 +00:00
9bd2136ca3
Teach memdep to phi translate bitcasts. This allows us to compile
...
the example in GCC PR16799 to:
LBB1_2: ## %bb1
movl %eax, %eax
subq %rax, %rdi
movq %rdi, (%rcx)
movl (%rdi), %eax
testl %eax, %eax
je LBB1_2
instead of:
LBB1_2: ## %bb1
movl (%rdi), %ecx
subq %rcx, %rdi
movq %rdi, (%rax)
cmpl $0, (%rdi)
je LBB1_2
llvm-svn: 89978
2009-11-26 23:41:07 +00:00
29bc8a91d3
Teach basicaa that x|c == x+c when the c bits of x are clear. This
...
allows us to compile the example in readme.txt into:
LBB1_1: ## %bb
movl 4(%rdx,%rax), %ecx
movl %ecx, %esi
imull (%rdx,%rax), %esi
imull %esi, %ecx
movl %esi, 8(%rdx,%rax)
imull %ecx, %esi
movl %ecx, 12(%rdx,%rax)
movl %esi, 16(%rdx,%rax)
imull %ecx, %esi
movl %esi, 20(%rdx,%rax)
addq $16, %rax
cmpq $4000, %rax
jne LBB1_1
instead of:
LBB1_1:
movl (%rdx,%rax), %ecx
imull 4(%rdx,%rax), %ecx
movl %ecx, 8(%rdx,%rax)
imull 4(%rdx,%rax), %ecx
movl %ecx, 12(%rdx,%rax)
imull 8(%rdx,%rax), %ecx
movl %ecx, 16(%rdx,%rax)
imull 12(%rdx,%rax), %ecx
movl %ecx, 20(%rdx,%rax)
addq $16, %rax
cmpq $4000, %rax
jne LBB1_1
GCC (4.2) doesn't seem to be able to eliminate the loads in this
testcase either, it generates:
L2:
movl (%rdx), %eax
imull 4(%rdx), %eax
movl %eax, 8(%rdx)
imull 4(%rdx), %eax
movl %eax, 12(%rdx)
imull 8(%rdx), %eax
movl %eax, 16(%rdx)
imull 12(%rdx), %eax
movl %eax, 20(%rdx)
addl $4, %ecx
addq $16, %rdx
cmpl $1002, %ecx
jne L2
llvm-svn: 89952
2009-11-26 16:26:43 +00:00
12dacdd359
teach basicaa that A[i] != A[i+1].
...
llvm-svn: 89951
2009-11-26 16:18:10 +00:00
8e09ad6f3c
update some notes slightly
...
llvm-svn: 89913
2009-11-26 01:51:18 +00:00
8981b3abe5
Rollback changes r89516: Added two SubtargetFeatures::AddFeatures methods, which accept a comma-separated string or already parsed command line parameters as input, and some code re-factoring to use these new methods.
...
llvm-svn: 89893
2009-11-25 22:44:18 +00:00
4419301d81
Tail duplicate indirect branches for PowerPC, too.
...
With the testcase for pr3120, the "threaded interpreter" runtime decreases
from 1788 to 1413 with this change.
llvm-svn: 89877
2009-11-25 19:57:14 +00:00
4cd30817d3
Avoid some possibly unsafe uses of StringRef::data().
...
llvm-svn: 89873
2009-11-25 18:26:09 +00:00
2d9caf9fe5
Use StringRef (again) in DebugInfo interface.
...
llvm-svn: 89866
2009-11-25 17:36:49 +00:00
120f729eca
Based on the testcase for pr3120, running on my MacPro with Xeon processors,
...
it is definitely profitable to tail duplicate indirect branches for x86.
This is likely to be true to various degrees for all modern x86 processors.
llvm-svn: 89865
2009-11-25 17:27:53 +00:00
2db07581b7
Support PIC loading of constant pool entries
...
llvm-svn: 89863
2009-11-25 12:17:58 +00:00
900f2ce31c
Sketch structure for X86 disassembler.
...
llvm-svn: 89850
2009-11-25 06:53:08 +00:00
Ken Dyck