dd2b2f8cba
Reduce (cmp 0, and_su (foo, bar)) into (bit foo, bar). This saves extra instruction. Patch inspired by Brian Lucas!
...
llvm-svn: 90819
2009-12-08 01:03:04 +00:00
9528ccdd77
Don't enable the post-RA scheduler on x86 except at -O3. In its
...
current form, it is too expensive in compile time.
llvm-svn: 90781
2009-12-07 19:04:31 +00:00
24a6316aaa
Some pretty-printing
...
llvm-svn: 90742
2009-12-07 02:28:41 +00:00
ff4ab51400
Add lowering of returnaddr and frameaddr intrinsics. Shamelessly stolen from x86 :)
...
llvm-svn: 90740
2009-12-07 02:28:10 +00:00
b4be8ce537
Initial codegen support for MSP430 ISRs
...
llvm-svn: 90739
2009-12-07 02:27:53 +00:00
28d3c733aa
Add ability to select hw multiplier mode and select appropriate libcalls.
...
llvm-svn: 90737
2009-12-07 02:27:08 +00:00
75dfed4fa5
Dynamic stack realignment use of sp register as source/dest register
...
in "bic sp, sp, #15" leads to unpredicatble behaviour in Thumb2 mode.
Emit the following code instead:
mov r4, sp
bic r4, r4, #15
mov sp, r4
llvm-svn: 90724
2009-12-06 22:39:50 +00:00
29d6390249
Calling InvalidateEntry during the refinement was breaking the bootstrap.
...
llvm-svn: 90656
2009-12-05 07:59:04 +00:00
fa3f115ec4
Final cleanups:
...
- Privatize a typedef.
- Call the InvalidateEntry when refining a type.
llvm-svn: 90655
2009-12-05 07:46:49 +00:00
4968774280
Inline methods which are called only once.
...
llvm-svn: 90640
2009-12-05 01:46:01 +00:00
da95e13750
Refactor some code. No functionality change.
...
llvm-svn: 90639
2009-12-05 01:43:33 +00:00
047a767d74
Remove the target hook TargetInstrInfo::BlockHasNoFallThrough in favor of
...
MachineBasicBlock::canFallThrough(), which is target-independent and more
thorough.
llvm-svn: 90634
2009-12-05 00:44:40 +00:00
86bafa29a3
Remove an unneeded include.
...
llvm-svn: 90625
2009-12-04 23:55:07 +00:00
0508e435c3
Have hasLoad/StoreFrom/ToStackSlot return the relevant MachineMemOperand.
...
llvm-svn: 90608
2009-12-04 22:38:46 +00:00
4ea0d2b8ee
Some code cleanup. No functionality change.
...
llvm-svn: 90588
2009-12-04 21:03:02 +00:00
5f9f721e95
remove out of date FIXME.
...
llvm-svn: 90490
2009-12-03 21:55:01 +00:00
f05330a5c8
expand note.
...
llvm-svn: 90429
2009-12-03 07:43:46 +00:00
d1e4ee3c2b
add a note
...
llvm-svn: 90428
2009-12-03 07:41:54 +00:00
c831fac043
fix a build problem with VC++, PR5664, patch by Alp Toker!
...
llvm-svn: 90419
2009-12-03 06:58:32 +00:00
0bbd3077ce
Recognize canonical forms of vector shuffles where the same vector is used for
...
both source operands. In the canonical form, the 2nd operand is changed to an
undef and the shuffle mask is adjusted to only reference elements from the 1st
operand. Radar 7434842.
llvm-svn: 90417
2009-12-03 06:40:55 +00:00
aba7d48764
Revert r90371. It was causing build failures.
...
llvm-svn: 90383
2009-12-03 01:54:07 +00:00
693969eb35
Further improvements: refactoring code that does the same thing into one
...
function, converting "dyn_cast" to "cast", asserting the correct things, and
other general cleanups.
llvm-svn: 90371
2009-12-03 01:15:46 +00:00
765ac33a1a
yay for case insensitive file systems (?)
...
llvm-svn: 90370
2009-12-03 01:10:05 +00:00
73570673de
remove some dead std::ostream using code.
...
llvm-svn: 90366
2009-12-03 00:55:04 +00:00
a48f44d9ee
improve portability to avoid conflicting with std::next in c++'0x.
...
Patch by Howard Hinnant!
llvm-svn: 90365
2009-12-03 00:50:42 +00:00
1ed59c63e3
This initial code is meant to convert TargetData to use an AbstractTypesUser so
...
that it doesn't have dangling pointers when abstract types are resolved. This
modifies it somewhat to address comments: making the "StructLayoutMap" an
anonymous structure, calling "removeAbstractTypeUser" when appropriate, and
adding asserts where helpful.
llvm-svn: 90362
2009-12-03 00:17:12 +00:00
2c3a6c6589
Factor the stack alignment calculations out into a target independent pass.
...
No functionality change.
llvm-svn: 90336
2009-12-02 19:30:24 +00:00
36d4dec28a
Thumb1 exception handling setjmp
...
llvm-svn: 90246
2009-12-01 18:10:36 +00:00
86fc920742
For VLDM/VSTM (Advanced SIMD), set encoding bits Inst{11-8} to 0b1011.
...
llvm-svn: 90243
2009-12-01 17:37:06 +00:00
ee536b0ea4
For VMOV (immediate), make some of the encoding bits (cmode and op) unspecified.
...
For VMOVv*i[16,32], op bit is don't care, and some cmode bits vary depending on
the immediate values.
Ref: Table A7-15 Modified immediate values for Advanced SIMD instructions.
llvm-svn: 90173
2009-12-01 00:02:02 +00:00
3ee8bc9b35
Minor whitespace fixes.
...
llvm-svn: 90166
2009-11-30 23:33:53 +00:00
6f51309021
Fix a minor inconsistency.
...
llvm-svn: 90165
2009-11-30 23:33:37 +00:00
505ddaa4dc
Remove isProfitableToDuplicateIndirectBranch target hook. It is profitable
...
for all the processors where I have tried it, and even when it might not help
performance, the cost is quite low. The opportunities for duplicating
indirect branches are limited by other factors so code size does not change
much due to tail duplicating indirect branches aggressively.
llvm-svn: 90144
2009-11-30 18:35:03 +00:00
c168a52627
Fix some more ARM unified syntax warnings.
...
llvm-svn: 90141
2009-11-30 17:47:19 +00:00
32f8bb9ed4
Added support to allow clients to custom widen. For X86, custom widen vectors for
...
divide/remainder since these operations can trap by unroll them and adding undefs
for the resulting vector.
llvm-svn: 90108
2009-11-30 02:42:02 +00:00
58ccf88c36
update and consolidate the load pre notes.
...
llvm-svn: 90050
2009-11-29 02:19:52 +00:00
83a4a9868f
add a deadargelim note.
...
llvm-svn: 90009
2009-11-27 17:12:30 +00:00
ca9e0e83b3
This testcase is actually only partially redundant, and requires
...
the FIXME I added yesterday to be implemented.
llvm-svn: 90008
2009-11-27 16:53:57 +00:00
cc6d29286c
this (and probably several others) are now done.
...
llvm-svn: 89982
2009-11-27 00:35:04 +00:00
9bd2136ca3
Teach memdep to phi translate bitcasts. This allows us to compile
...
the example in GCC PR16799 to:
LBB1_2: ## %bb1
movl %eax, %eax
subq %rax, %rdi
movq %rdi, (%rcx)
movl (%rdi), %eax
testl %eax, %eax
je LBB1_2
instead of:
LBB1_2: ## %bb1
movl (%rdi), %ecx
subq %rcx, %rdi
movq %rdi, (%rax)
cmpl $0, (%rdi)
je LBB1_2
llvm-svn: 89978
2009-11-26 23:41:07 +00:00
29bc8a91d3
Teach basicaa that x|c == x+c when the c bits of x are clear. This
...
allows us to compile the example in readme.txt into:
LBB1_1: ## %bb
movl 4(%rdx,%rax), %ecx
movl %ecx, %esi
imull (%rdx,%rax), %esi
imull %esi, %ecx
movl %esi, 8(%rdx,%rax)
imull %ecx, %esi
movl %ecx, 12(%rdx,%rax)
movl %esi, 16(%rdx,%rax)
imull %ecx, %esi
movl %esi, 20(%rdx,%rax)
addq $16, %rax
cmpq $4000, %rax
jne LBB1_1
instead of:
LBB1_1:
movl (%rdx,%rax), %ecx
imull 4(%rdx,%rax), %ecx
movl %ecx, 8(%rdx,%rax)
imull 4(%rdx,%rax), %ecx
movl %ecx, 12(%rdx,%rax)
imull 8(%rdx,%rax), %ecx
movl %ecx, 16(%rdx,%rax)
imull 12(%rdx,%rax), %ecx
movl %ecx, 20(%rdx,%rax)
addq $16, %rax
cmpq $4000, %rax
jne LBB1_1
GCC (4.2) doesn't seem to be able to eliminate the loads in this
testcase either, it generates:
L2:
movl (%rdx), %eax
imull 4(%rdx), %eax
movl %eax, 8(%rdx)
imull 4(%rdx), %eax
movl %eax, 12(%rdx)
imull 8(%rdx), %eax
movl %eax, 16(%rdx)
imull 12(%rdx), %eax
movl %eax, 20(%rdx)
addl $4, %ecx
addq $16, %rdx
cmpl $1002, %ecx
jne L2
llvm-svn: 89952
2009-11-26 16:26:43 +00:00
12dacdd359
teach basicaa that A[i] != A[i+1].
...
llvm-svn: 89951
2009-11-26 16:18:10 +00:00
8e09ad6f3c
update some notes slightly
...
llvm-svn: 89913
2009-11-26 01:51:18 +00:00
8981b3abe5
Rollback changes r89516: Added two SubtargetFeatures::AddFeatures methods, which accept a comma-separated string or already parsed command line parameters as input, and some code re-factoring to use these new methods.
...
llvm-svn: 89893
2009-11-25 22:44:18 +00:00
4419301d81
Tail duplicate indirect branches for PowerPC, too.
...
With the testcase for pr3120, the "threaded interpreter" runtime decreases
from 1788 to 1413 with this change.
llvm-svn: 89877
2009-11-25 19:57:14 +00:00
4cd30817d3
Avoid some possibly unsafe uses of StringRef::data().
...
llvm-svn: 89873
2009-11-25 18:26:09 +00:00
2d9caf9fe5
Use StringRef (again) in DebugInfo interface.
...
llvm-svn: 89866
2009-11-25 17:36:49 +00:00
120f729eca
Based on the testcase for pr3120, running on my MacPro with Xeon processors,
...
it is definitely profitable to tail duplicate indirect branches for x86.
This is likely to be true to various degrees for all modern x86 processors.
llvm-svn: 89865
2009-11-25 17:27:53 +00:00
2db07581b7
Support PIC loading of constant pool entries
...
llvm-svn: 89863
2009-11-25 12:17:58 +00:00
900f2ce31c
Sketch structure for X86 disassembler.
...
llvm-svn: 89850
2009-11-25 06:53:08 +00:00
2c6d498ccc
Use endianess dependent offsets for load/store of doubles when
...
using two swc/lwc instead of sdc/ldc.
llvm-svn: 89826
2009-11-25 01:05:25 +00:00
e0eb336588
Fix compiler warnings.
...
llvm-svn: 89824
2009-11-25 00:58:21 +00:00
fa2741e0d3
Only include in the callee saved regs the sub registers to avoid
...
unnecessary save/restore.
llvm-svn: 89823
2009-11-25 00:47:43 +00:00
dce6f66cf0
Add proper emission of load/store double to stack slots for mips1 targets!
...
llvm-svn: 89821
2009-11-25 00:36:00 +00:00
d23ea6a33b
Revert r89803.
...
llvm-svn: 89819
2009-11-25 00:31:13 +00:00
d4d40670e8
Refactor target hook for tail duplication as requested by Chris.
...
Make tail duplication of indirect branches much more aggressive (for targets
that indicate that it is profitable), based on further experience with
this transformation. I compiled 3 large applications with and without
this more aggressive tail duplication and measured minimal changes in code
size. ("size" on Darwin seems to round the text size up to the nearest
page boundary, so I can only say that any code size increase was less than
one 4k page.) Radar 7421267.
llvm-svn: 89814
2009-11-24 23:35:49 +00:00
5ece8f0a20
Do not store R31 into the caller's link area on PPC.
...
This violates the ABI (that area is "reserved"), and
while it is safe if all code is generated with current
compilers, there is some very old code around that uses
that slot for something else, and breaks if it is stored
into. Adjust testcases looking for current behavior.
I've verified that the stack frame size is right in all
testcases, whether it changed or not. 7311323.
llvm-svn: 89811
2009-11-24 22:59:02 +00:00
29c9b709e3
Enable debug info for ppc-darwin.
...
llvm-svn: 89803
2009-11-24 21:38:54 +00:00
184ec26fcd
Enable predication of NEON instructions in Thumb2 mode.
...
llvm-svn: 89748
2009-11-24 08:06:15 +00:00
86dcae106d
Make capitalization of names starting "is" more consistent.
...
No functional change.
llvm-svn: 89724
2009-11-24 01:09:07 +00:00
ece825dc4f
Data type suffix must come after predicate.
...
llvm-svn: 89723
2009-11-24 01:05:23 +00:00
2522908653
Materialize global addresses via movt/movw pair, this is always better
...
than doing the same via constpool:
1. Load from constpool costs 3 cycles on A9, movt/movw pair - just 2.
2. Load from constpool might stall up to 300 cycles due to cache miss.
3. Movt/movw does not use load/store unit.
4. Less constpool entries => better compiler performance.
This is only enabled on ELF systems, since darwin does not have needed
relocations (yet).
llvm-svn: 89720
2009-11-24 00:44:37 +00:00
f890f51666
80 column violations
...
llvm-svn: 89718
2009-11-24 00:20:27 +00:00
f2ad571443
* Move stub allocation inside the JITEmitter, instead of exposing a
...
way for each TargetJITInfo subclass to allocate its own stubs. This
means stubs aren't as exactly-sized anymore, but it lets us get rid of
TargetJITInfo::emitFunctionStubAtAddr(), which lets ARM and PPC
support the eager JIT, fixing http://llvm.org/PR4816 .
* Rename the JITEmitter's stub creation functions to describe the kind
of stub they create. So far, all of them create lazy-compilation
stubs, but they sometimes get used when far-call stubs are needed.
Fixing http://llvm.org/PR5201 will involve fixing this.
llvm-svn: 89715
2009-11-23 23:35:19 +00:00
de5dea869f
Remove ISD::DEBUG_LOC and ISD::DBG_LABEL, which are no longer used.
...
Note that "hasDotLocAndDotFile"-style debug info was already broken;
people wanting this functionality should implement it in the
AsmPrinter/DwarfWriter code.
llvm-svn: 89711
2009-11-23 23:20:51 +00:00
19b48370fb
Allow more than one stub to be being generated at the same time.
...
It's probably better in the long run to replace the
indirect-GlobalVariable system. That'll be done after a subsequent
patch.
llvm-svn: 89708
2009-11-23 22:49:00 +00:00
738a97a1db
Massive refactoring of NEON instructions. Separate opcode from data size specifier suffix, move \t up stream to instruction format, and fix more 80 column violations.
...
This fixes the NEON asm printing so the "predicate" field is printed between the opcode and the data type suffix.
llvm-svn: 89706
2009-11-23 21:57:23 +00:00
dbb4140f37
move fconst[sd] to UAL. <rdar://7414913>
...
llvm-svn: 89700
2009-11-23 21:08:25 +00:00
b6528d3244
Partially revert r84730 by removing N2VDup from ARMInstrFormats.td and modifying
...
VDUPLND and VDUPLNQ to derive from N2V instead of N2VDup. VDUPLND and VDUPLNQ
now expect op19_18 and op17_16 as the first two args.
llvm-svn: 89699
2009-11-23 21:00:43 +00:00
04c0e76772
fold immediate of a + Const into the user as a subtract if it can fit as a negated two-part immediate.
...
llvm-svn: 89694
2009-11-23 20:35:53 +00:00
5ad7416260
Revert r84572 by removing N3VImm from ARMInstrFormats.td now that we can specify
...
{?,?,?,?} as op11_8 for VEXTd and VEXTq.
llvm-svn: 89693
2009-11-23 20:09:13 +00:00
e97457afbc
Partially revert r89377 by removing NLdStLN class definition from
...
ARMInstrFormats.td and fixing VLD[234]LN* and VST[234]LN* to derive from NLdSt
instead of NLdStLN.
llvm-svn: 89684
2009-11-23 18:16:16 +00:00
ebc60ef80c
Make it clear that the index bit(s) of Vector Get Lane and Vector Set Lane
...
should be left unspecified now that Bob Wilson has fixed pr5470.
llvm-svn: 89676
2009-11-23 17:48:17 +00:00
1f2457f8aa
Minor itinerary fixes for FP instructions.
...
llvm-svn: 89672
2009-11-23 17:34:12 +00:00
fd963e11f5
Move default FrameReg val to getFrameIndexReference(). Otherwise, debug info can get bogus values.
...
llvm-svn: 89618
2009-11-22 20:05:32 +00:00
90e9062e96
Generate more correct debug info for frame indices.
...
llvm-svn: 89576
2009-11-22 02:32:29 +00:00
abdf86d2be
Minor optimization: when doing eq/ne comparions and RHS is a constant - swap operands, this will allow us to fold imm into comparison.
...
llvm-svn: 89574
2009-11-22 01:14:08 +00:00
3a31644c7a
Drop unsupported imm operands
...
llvm-svn: 89573
2009-11-22 01:13:54 +00:00
a9c7bb724a
Use 2-byte alignment for functions. 4 bytes are clear overkill here.
...
llvm-svn: 89572
2009-11-22 01:13:39 +00:00
d099b578e4
Use semicolon as assembler comment string
...
llvm-svn: 89571
2009-11-22 01:12:49 +00:00
e09e95b35c
Revert 89562. We're being sneakier than I was giving us credit for, and this
...
isn't necessary.
llvm-svn: 89568
2009-11-21 23:34:09 +00:00
43fd822249
Darwin requires a frame pointer for all non-leaf functions to support correct
...
backtraces.
llvm-svn: 89562
2009-11-21 21:40:08 +00:00
a33fc86be3
Add predicate operand to NEON instructions. Fix lots (but not all) 80 col violations in ARMInstrNEON.td.
...
llvm-svn: 89542
2009-11-21 06:21:52 +00:00
ed85e12da6
We are not using DBG_STOPPOINT anymore.
...
llvm-svn: 89536
2009-11-21 02:46:55 +00:00
7dcca8f7fc
Added two SubtargetFeatures::AddFeatures methods, which accept a comma-separated string or already parsed command line parameters as input, and some code re-factoring to use these new methods.
...
llvm-svn: 89516
2009-11-21 00:00:02 +00:00
312971513f
Fix a thinko that caused spurious @GOTOFFs.
...
llvm-svn: 89509
2009-11-20 23:30:32 +00:00
e14b347176
Update for new getBlockAddress signature.
...
llvm-svn: 89507
2009-11-20 23:21:00 +00:00
7a6611793f
Target-independent support for TargetFlags on BlockAddress operands,
...
and support for blockaddresses in x86-32 PIC mode.
llvm-svn: 89506
2009-11-20 23:18:13 +00:00
c1f532e930
Recommitting PALIGNR shift width fixes.
...
Thanks to Daniel Dunbar for fixing clang intrinsics:
http://llvm.org/viewvc/llvm-project?view=rev&revision=89499
llvm-svn: 89500
2009-11-20 22:28:42 +00:00
8495a506eb
Remove an incorrect overaggressive optimization
...
(PPC specific).
llvm-svn: 89496
2009-11-20 22:16:40 +00:00
19d92728d0
Reverting PALIGNR fix until I figure out how this
...
broke the Clang testsuite.
llvm-svn: 89495
2009-11-20 22:09:28 +00:00
fbed130173
Fixed PALIGNR to take 8-bit rotations in all cases.
...
Also fixed the corresponding testcase, and the PALIGNR
intrinsic (tested for correctness with llvm-gcc).
llvm-svn: 89491
2009-11-20 21:40:28 +00:00
bdb43a9d99
Remat VLDRD from constpool. Clean up some instruction property specifications.
...
llvm-svn: 89478
2009-11-20 19:57:15 +00:00
6c3b71195a
The verify() call of CPEIsInRange() isn't right for the assertion check of
...
constant pool ranges, as CPEIsInRange() makes conservative assumptions about
the potential alignment changes from branch adjustments. The verification,
on the other hand, runs after those branch adjustments are made, so the
effects on alignment are known and already taken into account. The sanity
check in verify should check the range directly instead.
llvm-svn: 89473
2009-11-20 19:37:38 +00:00
fc81352e3f
Remove verifySizes() since it's not adding much value.
...
llvm-svn: 89443
2009-11-20 02:32:06 +00:00
bbd50b0f78
Also CSE non-pic load from constant pools.
...
llvm-svn: 89440
2009-11-20 02:10:27 +00:00
81a2851bcb
Fix codegen of conditional move of immediates. We were not making use of the immediate forms of cmov instructions at all.
...
llvm-svn: 89423
2009-11-20 00:54:03 +00:00
a6380af658
Update comment to reflect instruction.
...
llvm-svn: 89414
2009-11-20 00:21:55 +00:00
b73918c42d
When placing constant islands and adjusting for alignment padding, inline
...
assembly can confuse things utterly, as it's assumed that instructions in
inline assembly are 4 bytes wide. For Thumb mode, that's often not true,
so the calculations for when alignment padding will be present get thrown off,
ultimately leading to out of range constant pool entry references. Making
more conservative assumptions that padding may be necessary when inline asm
is present avoids this situation.
llvm-svn: 89403
2009-11-19 23:10:28 +00:00
b6c7704a8d
Refactor cmov selection code out to a separate function. No functionality change.
...
llvm-svn: 89396
2009-11-19 21:45:22 +00:00
31c74dbb10
Reverting the EH table patches.
...
$ svn merge -c -89279 https://llvm.org/svn/llvm-project/llvm/trunk
--- Reverse-merging r89279 into '.':
U lib/CodeGen/AsmPrinter/DwarfException.cpp
U lib/Target/TargetLoweringObjectFile.cpp
$ svn merge -c -89270 https://llvm.org/svn/llvm-project/llvm/trunk
--- Reverse-merging r89270 into '.':
G lib/CodeGen/AsmPrinter/DwarfException.cpp
G lib/Target/TargetLoweringObjectFile.cpp
llvm-svn: 89379
2009-11-19 19:21:09 +00:00
b3b8209d77
Added NLdStLN which is similar to NLdSt with the exception that op7_4 is not
...
fully specified at this level. Subclasses of NLdStLN can specify selective
bit(s) for Inst{7-4}, as is done for VLD[234]LN* and VST[234]LN* inside
ARMInstrNEON.td.
llvm-svn: 89377
2009-11-19 19:20:17 +00:00
36a5bf82bf
fix typo
...
llvm-svn: 89369
2009-11-19 18:23:19 +00:00
91431b008b
Fix a typo in a comment.
...
llvm-svn: 89360
2009-11-19 16:35:11 +00:00
82adca8373
80 col violation.
...
llvm-svn: 89337
2009-11-19 08:16:50 +00:00
b18525937c
More consistent thumb1 asm printing.
...
llvm-svn: 89328
2009-11-19 06:57:41 +00:00
2a6c92fcb6
Shrink ldr / str [sp, imm0-1024] to 16-bit instructions.
...
llvm-svn: 89326
2009-11-19 06:32:27 +00:00
547abae38d
Eliminate more * 4 in Thumb1 asm printing for consistency sake.
...
llvm-svn: 89325
2009-11-19 06:31:26 +00:00
4713b282ce
- Add sugregister logic to handle f64=(f32,f32).
...
- Support mips1 like load/store of doubles:
Instead of:
sdc $f0, X($3)
Generate:
swc $f0, X($3)
swc $f1, X+4($3)
llvm-svn: 89322
2009-11-19 06:06:13 +00:00
8bd87239d7
Only use small sections for non linux targets!
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llvm-svn: 89316
2009-11-19 05:28:18 +00:00
4b384b0294
The "ReadOnlyWithRel" enum seems to apply more to what Darwin does with the EH
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exception table than DataRel.
llvm-svn: 89279
2009-11-19 00:09:14 +00:00
3bd09434a6
Add XCore support for indirectbr / blockaddress.
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llvm-svn: 89273
2009-11-18 23:20:42 +00:00
07e6e2c6f8
Attempt #2 :
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Place the EH table in the __TEXT section on MachO. It saves space.
llvm-svn: 89270
2009-11-18 23:18:46 +00:00
c3e2b6bcf5
Added getDefaultSubtargetFeatures method to SubtargetFeatures class which returns a correct feature string for given triple.
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llvm-svn: 89236
2009-11-18 20:20:05 +00:00
1fd5fdaa7b
Add ARMv6 itineraries.
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llvm-svn: 89218
2009-11-18 18:39:57 +00:00
9dea05d724
Fix a few places that were missed when we converted to unified syntax.
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llvm-svn: 89214
2009-11-18 18:10:35 +00:00
290e9a47a9
Add a target hook to allow changing the tail duplication limit based on the
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contents of the block to be duplicated. Use this for ARM Cortex A8/9 to
be more aggressive tail duplicating indirect branches, since it makes it
much more likely that they will be predicted in the branch target buffer.
Testcase coming soon.
llvm-svn: 89187
2009-11-18 03:34:27 +00:00
dfd8daaf61
The llvm-gcc front-end and the pass manager use two separate TargetData objects.
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This is probably not confined to *just* these two things.
Anyway, the llvm-gcc front-end may look up the structure layout information for
an abstract type. That information will be stored into a table with the FE's
TD. Instruction combine can come along and also ask for information on that
abstract type, but for a separate TD (the one associated with the pass manager).
After the type is refined, the old structure layout information in the pass
manager's TD file is out of date. If a new type is allocated in the same space
as the old-unrefined type, then the structure type information in the pass
manager's TD file will be wrong, but won't know it.
Fix this by making the TD's structure type information an abstract type user.
llvm-svn: 89176
2009-11-18 01:03:56 +00:00
cdde77c6a3
Enable arm jumpt table adjustment.
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llvm-svn: 89143
2009-11-17 21:24:11 +00:00
f24804413d
Both Darwin as and GNU as violate ARM docs wrt printing of addrmode6
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alignment imm (in the same way). Fix asmprinting for non-darwin platforms.
llvm-svn: 89137
2009-11-17 20:04:59 +00:00
14b25eb87b
Set Inst{15-12} (Rd/Rt) to 0b1111 (PC) for BR_JTadd, BR_JTr, and BR_JTm to
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distinguish between them and the more generic instructions (add, mov, and ldr).
llvm-svn: 89108
2009-11-17 17:17:50 +00:00
5392cc9d14
Re-apply 89011. It's not to be blamed.
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llvm-svn: 89081
2009-11-17 09:51:18 +00:00
05938e819b
Revert 89011. Buildbot thinks it might be breaking stuff.
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llvm-svn: 89076
2009-11-17 09:20:28 +00:00
af1ad30a23
When moving a block for table jumps, make sure the prior block terminator
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is analyzable so it can be updated. If it's not, be safe and don't move the
block.
llvm-svn: 89022
2009-11-17 01:21:04 +00:00
d33400e636
MOV64rm should be marked isReMaterializable.
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llvm-svn: 89019
2009-11-17 00:55:55 +00:00
ce28f6f478
A few more instructions that should be marked re-materializable.
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llvm-svn: 89011
2009-11-17 00:23:22 +00:00
18183b6d8e
Set Rm bits of BX_RET to 0b1110 (R14); and set condition code bits of BRIND to
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0b1110 (ALways). This is so that the disassembler decoder can distinguish among
BX_RET, BRIND, and BXr9.
llvm-svn: 89000
2009-11-16 23:57:56 +00:00
10d3604a9e
Make X86-64 in the Large model always emit 64-bit calls.
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The large code model is documented at
http://www.x86-64.org/documentation/abi.pdf and says that calls should
assume their target doesn't live within the 32-bit pc-relative offset
that fits in the call instruction.
To do this, we turn off the global-address->target-global-address
conversion in X86TargetLowering::LowerCall(). The first attempt at
this broke the lazy JIT because it can separate the movabs(imm->reg)
from the actual call instruction. The lazy JIT receives the address of
the movabs as a relocation and needs to record the return address from
the call; and then when that call happens, it needs to patch the
movabs with the newly-compiled target. We could thread the call
instruction into the relocation and record the movabs<->call mapping
explicitly, but that seems to require at least as much new
complication in the code generator as this change.
To fix this, we make lazy functions _always_ go through a call
stub. You'd think we'd only have to force lazy calls through a stub on
difficult platforms, but that turns out to break indirect calls
through a function pointer. The right fix for that is to distinguish
between calls and address-of operations on uncompiled functions, but
that's complex enough to leave for someone else to do.
Another attempt at this defined a new CALL64i pseudo-instruction,
which expanded to a 2-instruction sequence in the assembly output and
was special-cased in the X86CodeEmitter's emitInstruction()
function. That broke indirect calls in the same way as above.
This patch also removes a hack forcing Darwin to the small code model.
Without far-call-stubs, the small code model requires things of the
JITMemoryManager that the DefaultJITMemoryManager can't provide.
Thanks to echristo for lots of testing!
llvm-svn: 88984
2009-11-16 22:41:33 +00:00
f25ef4ffb0
- Check memoperand alignment instead of checking stack alignment. Most load / store folding instructions are not referencing spill stack slots.
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- Mark MOVUPSrm re-materializable.
llvm-svn: 88974
2009-11-16 21:56:03 +00:00
56ee15c162
Make the pass class name more explicit.
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llvm-svn: 88964
2009-11-16 21:13:22 +00:00
544b15cbc3
make pass name a bit more clear
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llvm-svn: 88961
2009-11-16 21:03:58 +00:00
9785e5914f
Simplify thumb2 jump table adjustments. Remove unnecessary calculation and
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usage of block sizes and offsets.
llvm-svn: 88935
2009-11-16 18:58:52 +00:00
87b0f0d95c
clarify comment
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llvm-svn: 88933
2009-11-16 18:55:47 +00:00
9c148c2163
back off for a bit. tracking down weirdness
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llvm-svn: 88919
2009-11-16 17:17:48 +00:00
47d5e333ff
Analyze has to be before checking the condition, obviously. Properly construct an iterator for prior.
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llvm-svn: 88917
2009-11-16 17:10:56 +00:00
5bf807688e
Disable ldc1/sdc1 instructions for mips1 targets.
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llvm-svn: 88887
2009-11-16 04:35:29 +00:00
537e409c58
- Fix a small bug while handling target constant pools (one param was missing).
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- Add a smarter constant pool loading, instead of:
lui $2, %hi($CPI1_0)
addiu $2, $2, %lo($CPI1_0)
lwc1 $f0, 0($2)
Generate:
lui $2, %hi($CPI1_0)
lwc1 $f0, %lo($CPI1_0)($2)
llvm-svn: 88886
2009-11-16 04:33:42 +00:00
01c1cae34d
Detect need for autoalignment of the stack earlier to catch spills more
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conservatively. eliminateFrameIndex() machinery adjust to handle addr mode
6 (vld1/vst1) used for spills. Fix tests to expect aligned Q-reg spilling
llvm-svn: 88874
2009-11-15 21:45:34 +00:00
74ae3e5b0e
set the def of the VLD1q64 properly
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llvm-svn: 88873
2009-11-15 21:05:07 +00:00
ef4ea9a2a9
Add a complex missed optimization opportunity I came across while investigating
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bug 5438.
llvm-svn: 88855
2009-11-15 17:51:23 +00:00
e07594df45
cleanup.
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llvm-svn: 88812
2009-11-14 21:33:37 +00:00
43d2108546
Cleanup flow, and only update the jump table we're analyzing when replacing a destination MBB.
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llvm-svn: 88805
2009-11-14 20:10:18 +00:00
d5f2745965
Add XCore support for arbitrary-sized aggregate returns.
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llvm-svn: 88802
2009-11-14 19:33:35 +00:00
fd0c7bae2a
Temporary disable the error - it seems to be too conservative.
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llvm-svn: 88800
2009-11-14 18:01:41 +00:00
241d01b590
Add llvm::sys::getHostCPUName, for detecting the LLVM name for the host CPU.
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- This is an initial step towards -march=native support in Clang, and towards
eliminating host dependencies in the targets. See PR5389.
- Patch by Roman Divacky!
llvm-svn: 88768
2009-11-14 10:09:12 +00:00
d03742a122
revert 88761 as it fails builds.
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llvm-svn: 88762
2009-11-14 07:22:25 +00:00
8f9c22646b
Fix debug info crashes for PIC16.
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llvm-svn: 88761
2009-11-14 06:19:49 +00:00
6ad7da96fe
- Change TargetInstrInfo::reMaterialize to pass in TargetRegisterInfo.
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- If destination is a physical register and it has a subreg index, use the
sub-register instead.
This fixes PR5423.
llvm-svn: 88745
2009-11-14 02:55:43 +00:00
66401c90da
When expanding t2STRDi8 r, r to two stores, add kill markers correctly.
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llvm-svn: 88734
2009-11-14 01:50:00 +00:00
ff0302489b
The instruction pointer %RIP is a reserved register on x86_64.
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llvm-svn: 88705
2009-11-13 21:56:01 +00:00
Anton Korobeynikov