Commit Graph

7 Commits

Author SHA1 Message Date
Sam Elliott 7c9c2a2ea5 Revert "[RISCV] Legalize select when Zbt extension available"
We found issues with this patch in additional testing. Backing out while
we work on a fix.

This reverts commit 71ed4b6ce5.
2021-01-14 16:44:34 +00:00
Michael Munday 71ed4b6ce5 [RISCV] Legalize select when Zbt extension available
The custom expansion of select operations in the RISC-V backend
interferes with the matching of cmov instructions. Legalizing
select when the Zbt extension is available solves that problem.

Reviewed By: lenary, craig.topper

Differential Revision: https://reviews.llvm.org/D93767
2021-01-12 21:24:38 +00:00
Craig Topper 98bca0a605 [RISCV] Add isel patterns for SBCLRI/SBSETI/SBINVI(W) instruction
We can use these instructions for single bit immediates that are too large for ANDI/ORI/CLRI.

The _10 test cases are to make sure that we still use ANDI/ORI/CLRI for small immediates.

Differential Revision: https://reviews.llvm.org/D92262
2020-12-08 12:22:40 -08:00
Craig Topper 5836e52063 [RISCV] Add isel patterns to use SBSET for (1 << X) by using X0 as the input. 2020-11-26 15:35:13 -08:00
Craig Topper c0dd22e44a [RISCV] Add isel patterns to match sbset/sbclr/sbinv/sbext even if the shift amount isn't masked.
This uses the shiftop PatFrags to handle the masked shift amount
and unmasked shift amount cases. That also checks XLen as part
of the masked amount check so we don't need separate RV32 and RV64
patterns.

Differential Revision: https://reviews.llvm.org/D91016
2020-11-09 09:55:26 -08:00
Craig Topper b94763d524 [RISCV] Add test cases showing missed opportunities to use sbset/sbclr/sbinv/sbext when the shift amount isn't masked to log2(xlen) bits. NFC
Out of bounds shifts are undefined and these instructions mask
their shift amount before use. So we don't need to see a mask
in order to select the instructions.
2020-11-07 14:25:16 -08:00
lewis-revill d4be33374c [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbs asm instructions
This patch provides optimization of bit manipulation operations by
enabling the +experimental-b target feature.
It adds matching of single block patterns of instructions to specific
bit-manip instructions from the single-bit subset (zbs subextension) of
the experimental B extension of RISC-V.
It adds also the correspondent codegen tests.

This patch is based on Claire Wolf's proposal for the bit manipulation
extension of RISCV:
https://github.com/riscv/riscv-bitmanip/blob/master/bitmanip-0.92.pdf

Differential Revision: https://reviews.llvm.org/D79874
2020-07-15 12:19:34 +01:00