e63b6518fa
For PR950:
...
Three changes:
1. Convert signed integer types to signless versions.
2. Implement the @sext and @zext parameter attributes. Previously the
type of an function parameter was used to determine whether it should
be sign extended or zero extended before the call. This information is
now communicated via the function type's parameter attributes.
3. The interface to LowerCallTo had to be changed in order to accommodate
the parameter attribute information. Although it would have been
convenient to pass in the FunctionType itself, there isn't always one
present in the caller. Consequently, a signedness indication for the
result type and for each parameter was provided for in the interface
to this method. All implementations were changed to make the adjustment
necessary.
llvm-svn: 32788
2006-12-31 05:55:36 +00:00
64493fb30d
fix comment
...
llvm-svn: 32767
2006-12-29 14:28:12 +00:00
8ab8f7df6f
Define StaticCtorsSection and StaticDtorsSection for ARM.
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llvm-svn: 32763
2006-12-28 13:13:00 +00:00
7251e57ff8
Implement SELECT_CC (f32/f64) for ARM.
...
llvm-svn: 32762
2006-12-28 13:11:14 +00:00
865b979833
remove duplicated line
...
bug noticed by Lauro
llvm-svn: 32761
2006-12-28 12:51:40 +00:00
d0ced3f1e8
This patch defines extloadi1 and fixes an internal compiler error on
...
arm.
llvm-svn: 32760
2006-12-26 19:30:42 +00:00
5cfa5ef912
Fix for ARM weak symbols, patch by Lauro Ramos Venancio!
...
llvm-svn: 32740
2006-12-21 22:59:58 +00:00
1ef9cd400d
eliminate static ctors for Statistic objects.
...
llvm-svn: 32703
2006-12-19 22:59:26 +00:00
3ab9256d19
macros -> Inline functions
...
Lauros's patch
llvm-svn: 32656
2006-12-18 11:07:09 +00:00
d7998d0e6d
move ExtWeakSymbols to AsmPrinter
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llvm-svn: 32648
2006-12-18 03:37:18 +00:00
3b7544e24c
avoid using a constant table when a constant can be used inline
...
llvm-svn: 32580
2006-12-14 18:58:37 +00:00
09e2921d9a
Avoid creating invalid sub/add instructions on the prolog/epilog
...
patch by Lauro
llvm-svn: 32577
2006-12-14 13:31:27 +00:00
67d1c8ae0e
more general matching of the MVN instruction
...
llvm-svn: 32484
2006-12-12 17:10:13 +00:00
470d61d82c
don't use "ordinary" addressing mode 1 when mvn is appropriate
...
llvm-svn: 32482
2006-12-12 14:03:29 +00:00
9fa0a26808
use MVN to handle small negative constants
...
llvm-svn: 32459
2006-12-12 01:03:11 +00:00
1bbe581d0f
add mvn
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llvm-svn: 32454
2006-12-12 00:37:38 +00:00
eb3e8d75df
add note
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llvm-svn: 32452
2006-12-11 23:56:10 +00:00
b8ada08b26
.align is in bits
...
.comm is in bytes
:-(
llvm-svn: 32408
2006-12-10 02:53:14 +00:00
d12d2250a7
%progbits not @progbits
...
llvm-svn: 32376
2006-12-08 22:06:02 +00:00
94f29f129d
add \"aw\",@progbits" to ctors and dtors
...
llvm-svn: 32373
2006-12-08 21:24:58 +00:00
87f4382163
fix truncstorei1
...
llvm-svn: 32364
2006-12-08 18:41:21 +00:00
265fa68bd8
fix alignment
...
llvm-svn: 32337
2006-12-07 22:38:06 +00:00
9bfb1e1f29
What should be the last unnecessary <iostream>s in the library.
...
llvm-svn: 32333
2006-12-07 22:21:48 +00:00
219a796475
make sure that we don't use a common symbol if a section was specified
...
llvm-svn: 32310
2006-12-07 18:33:58 +00:00
700b873130
Detemplatize the Statistic class. The only type it is instantiated with
...
is 'unsigned'.
llvm-svn: 32279
2006-12-06 17:46:33 +00:00
776abee608
print weak references
...
llvm-svn: 32276
2006-12-06 13:35:10 +00:00
81cf22d873
These asm printers shouldn't use assembly/writer.h
...
llvm-svn: 32262
2006-12-06 06:13:25 +00:00
b5dee63958
expand memmove and memcpy
...
llvm-svn: 32226
2006-12-05 17:57:23 +00:00
96fd6447c7
add support for the "r" asm constraint
...
patch by Lauro Ramos Venancio
llvm-svn: 32224
2006-12-05 17:37:31 +00:00
2369a024d7
add support for weak linkage
...
llvm-svn: 32222
2006-12-05 17:00:17 +00:00
20350c4025
Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead
...
of opcode and number of operands.
llvm-svn: 31947
2006-11-27 23:37:22 +00:00
5f7ab1b964
implement load effective address similar to the alpha backend
...
remove lea_addri and the now unused memri addressing mode
llvm-svn: 31592
2006-11-09 13:58:55 +00:00
6cd0909da7
Match tblegen changes.
...
llvm-svn: 31571
2006-11-08 20:34:28 +00:00
708cb60588
initial implementation of addressing mode 2
...
TODO: fix lea_addri
llvm-svn: 31552
2006-11-08 17:07:32 +00:00
9ac6442db6
remove dead/redundant vars
...
llvm-svn: 31435
2006-11-03 23:48:56 +00:00
4ece5c04f4
revert previous patch
...
llvm-svn: 31411
2006-11-03 03:08:28 +00:00
38b162c1d2
add createCFGSimplificationPass to ARMTargetMachine::addInstSelector
...
llvm-svn: 31400
2006-11-03 01:39:25 +00:00
ac8668d62f
move ARMCondCodeToString to ARMAsmPrinter.cpp
...
remove unused variables from lowerCall
llvm-svn: 31378
2006-11-02 15:00:02 +00:00
3576405a26
print null values in bss
...
llvm-svn: 31349
2006-11-01 14:26:44 +00:00
0cd8d14c7c
implement zextload bool and truncstore bool
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llvm-svn: 31348
2006-11-01 14:13:27 +00:00
4e825336a0
add support for calling functions when the caller has variable sized objects
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llvm-svn: 31312
2006-10-31 13:03:26 +00:00
0d41d19427
All targets expand BR_JT for now.
...
llvm-svn: 31294
2006-10-30 08:02:39 +00:00
a23166d6a4
initial support for frame pointers
...
llvm-svn: 31197
2006-10-26 13:31:26 +00:00
bd29281e97
expand ISD::VACOPY
...
llvm-svn: 31170
2006-10-24 20:15:21 +00:00
ed32883b27
fix warning about missing newline at end of file
...
llvm-svn: 31162
2006-10-24 17:07:11 +00:00
aaeede0aa2
implement uncond branch insertion, mark branches with isBranch.
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llvm-svn: 31160
2006-10-24 16:47:57 +00:00
b43efe86f5
implement STRB and STRH
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llvm-svn: 31138
2006-10-23 20:34:27 +00:00
cd5f662c7b
expand ISD::MEMSET
...
llvm-svn: 31137
2006-10-23 20:08:22 +00:00
e0fc4dfc22
For PR950:
...
This patch implements the first increment for the Signless Types feature.
All changes pertain to removing the ConstantSInt and ConstantUInt classes
in favor of just using ConstantInt.
llvm-svn: 31063
2006-10-20 07:07:24 +00:00
336d62e99a
use Pat to implement extloadi8 and extloadi16
...
llvm-svn: 31052
2006-10-19 17:05:03 +00:00
f8274c0318
implement undef
...
llvm-svn: 31049
2006-10-19 13:45:00 +00:00
ea67b973c2
print common symbols
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llvm-svn: 31048
2006-10-19 13:30:40 +00:00
ff62819e2f
implement extloadi8 and extloadi16
...
llvm-svn: 31047
2006-10-19 12:45:04 +00:00
3c563c5072
expand SIGN_EXTEND_INREG
...
llvm-svn: 31046
2006-10-19 12:06:50 +00:00
b260306625
expand brind so that we don't have to implement jump tables right now
...
llvm-svn: 31045
2006-10-19 10:56:43 +00:00
bad440742e
add blx
...
llvm-svn: 31037
2006-10-18 16:21:43 +00:00
01dd97a8aa
add isTerminatortto b and bcond
...
llvm-svn: 31036
2006-10-18 16:20:57 +00:00
b21e8d2e12
implement CallingConv::Fast as CallingConv::C
...
llvm-svn: 31034
2006-10-18 12:03:07 +00:00
ba8f296167
expand ISD::SDIV, ISD::UDIV, ISD::SREM and ISD::UREM
...
llvm-svn: 31014
2006-10-17 21:05:33 +00:00
3968263ca8
add the FPUnaryOp and DFPUnaryOp classes
...
llvm-svn: 31013
2006-10-17 20:45:22 +00:00
99bf133d58
add FABSS and FABSD
...
llvm-svn: 31012
2006-10-17 20:33:13 +00:00
2d7d14262a
remove extra [] in stores
...
llvm-svn: 31008
2006-10-17 18:29:14 +00:00
19398ec86e
initial implementation of addressing mode 5
...
llvm-svn: 31002
2006-10-17 18:04:53 +00:00
feb50708eb
add the immediate to the Offset in eliminateFrameIndex
...
llvm-svn: 30998
2006-10-17 14:34:02 +00:00
418c8e69bb
add FSTD and FSTS
...
llvm-svn: 30996
2006-10-17 13:36:07 +00:00
c31ee94920
add FCPYS and FCPYD
...
llvm-svn: 30995
2006-10-17 13:13:23 +00:00
afdd47ace4
add fdivs e fdivd
...
llvm-svn: 30988
2006-10-16 21:50:04 +00:00
f719c5f43d
expand ISD::SHL_PARTS, ISD::SRA_PARTS and ISD::SRL_PARTS
...
llvm-svn: 30987
2006-10-16 21:10:32 +00:00
e341d60f53
define the DFPBinOp class
...
llvm-svn: 30981
2006-10-16 18:39:22 +00:00
f63752f94b
add the FPBinOp class
...
llvm-svn: 30980
2006-10-16 18:32:36 +00:00
b23dc14135
define the Addr1BinOp class
...
llvm-svn: 30979
2006-10-16 18:18:14 +00:00
203922d083
define the IntBinOp class and use it to implement the multiply instructions
...
llvm-svn: 30978
2006-10-16 17:57:20 +00:00
c4abf8dc5b
fix assembly syntax
...
llvm-svn: 30977
2006-10-16 17:38:12 +00:00
677ee8390d
implement LDRB, LDRSB, LDRH and LDRSH
...
llvm-svn: 30976
2006-10-16 17:17:22 +00:00
595dc4c884
implement smull and umull
...
llvm-svn: 30975
2006-10-16 16:33:29 +00:00
2b7f635951
expand ISD::BRCOND
...
llvm-svn: 30963
2006-10-14 17:59:54 +00:00
4c1baf1528
fix some fp condition codes
...
use non trapping comparison instructions
llvm-svn: 30962
2006-10-14 13:42:53 +00:00
ab51cf2e78
Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode.
...
llvm-svn: 30945
2006-10-13 21:14:26 +00:00
5ab3166f74
add FNEGS and FNEGD
...
llvm-svn: 30932
2006-10-13 17:37:35 +00:00
d6050c3149
add SBCS and SUBS
...
llvm-svn: 30930
2006-10-13 17:19:20 +00:00
79d9807c87
implement calls to functions that return long
...
llvm-svn: 30929
2006-10-13 16:47:22 +00:00
3874a168d0
implement unordered floating point compares
...
llvm-svn: 30928
2006-10-13 13:14:59 +00:00
8c9422c4b8
mark call adjustments as modifying the SP
...
llvm-svn: 30911
2006-10-12 18:00:26 +00:00
577ef7694e
Add properties to ComplexPattern.
...
llvm-svn: 30891
2006-10-11 21:03:53 +00:00
8429e1f6c3
uint <-> double conversion
...
llvm-svn: 30862
2006-10-10 20:38:57 +00:00
b5f1ff336a
add fp sub
...
llvm-svn: 30859
2006-10-10 19:35:01 +00:00
57d109fb08
add double <-> int conversion
...
llvm-svn: 30858
2006-10-10 18:55:14 +00:00
d1a4ea41c9
compare doubles
...
llvm-svn: 30856
2006-10-10 16:33:47 +00:00
d15c892433
initial support for fp compares. Unordered compares not implemented yet
...
llvm-svn: 30854
2006-10-10 12:56:00 +00:00
e71fe34d75
Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes.
...
llvm-svn: 30844
2006-10-09 20:57:25 +00:00
9e29ec371a
add float -> double and double -> float conversion
...
llvm-svn: 30835
2006-10-09 17:50:29 +00:00
396b4a6b7b
add ADDS and ADCS
...
llvm-svn: 30830
2006-10-09 17:18:28 +00:00
e4c3276afc
expand ISD::SELECT
...
llvm-svn: 30829
2006-10-09 16:28:33 +00:00
c154dacb2f
add a note
...
llvm-svn: 30828
2006-10-09 14:18:33 +00:00
41730922bb
expand ISD::EXTLOAD
...
llvm-svn: 30827
2006-10-09 14:13:40 +00:00
78d6c2bf59
most ARM targets are little endian
...
llvm-svn: 30826
2006-10-09 14:12:15 +00:00
b50938866b
implement FUITOS and FUITOD
...
llvm-svn: 30803
2006-10-07 14:24:52 +00:00
58c368bc4f
implement FLDD
...
llvm-svn: 30802
2006-10-07 14:03:39 +00:00
40f5dd27f0
implement fadds, faddd, fmuls and fmuld
...
llvm-svn: 30801
2006-10-07 13:46:42 +00:00
aa2a12f1a2
add optional input flag to FMRRD
...
llvm-svn: 30774
2006-10-06 20:33:26 +00:00
671f25281d
add support for calling functions that return double
...
llvm-svn: 30771
2006-10-06 19:10:05 +00:00
ef01656ea4
fix some bugs affecting functions with no arguments
...
llvm-svn: 30767
2006-10-06 17:26:30 +00:00
6024ea8383
fix the stack alignment
...
llvm-svn: 30766
2006-10-06 14:29:47 +00:00
5fe7909e18
add support for calling functions that have double arguments
...
llvm-svn: 30765
2006-10-06 12:50:22 +00:00
df9ac47e5e
Make use of getStore().
...
llvm-svn: 30759
2006-10-05 23:01:46 +00:00
decfeca52d
use a const ref for passing the vector to ArgumentLayout
...
llvm-svn: 30756
2006-10-05 17:46:48 +00:00
e04df41ca2
implement a ArgumentLayout class to factor code common to LowerFORMAL_ARGUMENTS and LowerCALL
...
implement FMDRR
add support for f64 function arguments
llvm-svn: 30754
2006-10-05 16:48:49 +00:00
a6a570e02f
Pass the MachineFunction into EmitJumpTableInfo.
...
llvm-svn: 30742
2006-10-05 03:01:21 +00:00
4431699187
Use getSectionForFunction.
...
llvm-svn: 30740
2006-10-05 02:49:23 +00:00
68d238801c
Implement floating point constants
...
llvm-svn: 30704
2006-10-03 17:27:58 +00:00
d55c0a41df
fix the names of the 64bit fp register
...
initial support for returning 64bit floating point numbers
llvm-svn: 30692
2006-10-02 19:30:56 +00:00
53f78be49e
add floating point registers
...
implement SINT_TO_FP
llvm-svn: 30673
2006-09-29 21:20:16 +00:00
72d4c070c0
add a note
...
llvm-svn: 30581
2006-09-22 11:36:17 +00:00
7b700e517a
more condition codes
...
llvm-svn: 30567
2006-09-21 13:06:26 +00:00
0c71a5adc8
if a constant can't be an immediate, add it to the constant pool
...
llvm-svn: 30566
2006-09-21 11:29:52 +00:00
fa7217f970
fix header
...
add comments
untabify
llvm-svn: 30486
2006-09-19 16:41:40 +00:00
f7d4a9900c
Implement a MachineFunctionPass to fix the mul instruction
...
llvm-svn: 30485
2006-09-19 15:49:25 +00:00
3130a756ef
add shifts to addressing mode 1
...
llvm-svn: 30291
2006-09-13 12:09:43 +00:00
9a083a4121
Reflects MachineConstantPoolEntry changes.
...
llvm-svn: 30279
2006-09-12 21:04:05 +00:00
c7829d62c0
implement SRL and MUL
...
llvm-svn: 30262
2006-09-11 19:24:19 +00:00
bccf9c2f1b
add the correct fallback for ARMDAGToDAGISel::SelectAddrMode1
...
llvm-svn: 30261
2006-09-11 19:23:32 +00:00
e45a79a9e2
partial implementation of the ARM Addressing Mode 1
...
llvm-svn: 30252
2006-09-11 17:25:40 +00:00
ecb0d686f8
call AsmPrinter::doInitialization in ARMAsmPrinter::doInitialization
...
llvm-svn: 30246
2006-09-11 12:49:38 +00:00
fbee8bfe48
Removed unnecessary Mangler creation.
...
llvm-svn: 30239
2006-09-10 21:17:03 +00:00
d11fb5d13b
implement shl and sra
...
llvm-svn: 30191
2006-09-08 17:36:23 +00:00
4443c7d60a
add the eor (xor) instruction
...
llvm-svn: 30189
2006-09-08 16:59:47 +00:00
778769aafb
implement unconditional branches
...
fix select.ll
llvm-svn: 30186
2006-09-08 12:47:03 +00:00
ae92ce8798
1. Remove condition on delete.
...
2. Protect and outline createTargetAsmInfo.
3. Misc. kruft.
llvm-svn: 30169
2006-09-07 23:39:26 +00:00
261779bb45
Make target asm info a property of the target machine.
...
llvm-svn: 30162
2006-09-07 22:06:40 +00:00
0e83541f8b
Break out target asm info into separate files.
...
llvm-svn: 30161
2006-09-07 22:05:02 +00:00
a6211dcdad
Separate target specific asm properties from the asm printers.
...
llvm-svn: 30126
2006-09-06 18:34:40 +00:00
abd8bcbe5e
add the orr instruction
...
llvm-svn: 30125
2006-09-06 18:03:12 +00:00
af23f9b5f6
Completely eliminate def&use operands. Now a register operand is EITHER a
...
def operand or a use operand.
llvm-svn: 30109
2006-09-05 02:31:13 +00:00
8386105f3f
add support for returning 64bit values
...
llvm-svn: 30103
2006-09-04 19:05:01 +00:00
12e97307a1
Completely rearchitect the interface between targets and the pass manager.
...
This pass:
1. Splits TargetMachine into TargetMachine (generic targets, can be implemented
any way, like the CBE) and LLVMTargetMachine (subclass of TM that is used by
things using libcodegen and other support).
2. Instead of having each target fully populate the passmgr for file or JIT
output, move all this to common code, and give targets hooks they can
implement.
3. Commonalize the target population stuff between file emission and JIT
emission.
4. All (native code) codegen stuff now happens in a FunctionPassManager, which
paves the way for "fast -O0" stuff in the CFE later, and now LLC could
lazily stream .bc files from disk to use less memory.
5. There are now many fewer #includes and the targets don't depend on the
scalar xforms or libanalysis anymore (but codegen does).
6. Changing common code generator pass ordering stuff no longer requires
touching all targets.
7. The JIT now has the option of "-fast" codegen or normal optimized codegen,
which is now orthogonal to the fact that JIT'ing is being done.
llvm-svn: 30081
2006-09-04 04:14:57 +00:00
0fc4541c67
Simplify target construction.
...
llvm-svn: 30070
2006-09-03 18:44:02 +00:00
5328ba96e1
add the SETULT condition code
...
llvm-svn: 30067
2006-09-03 13:19:16 +00:00
c585b6919b
add more condition codes
...
llvm-svn: 30056
2006-09-02 20:24:25 +00:00
61413a3d72
Select() no longer require Result operand by reference.
...
llvm-svn: 29898
2006-08-26 05:34:46 +00:00
98dc23fd1f
use @ for comments
...
store LR in an arbitrary stack slot
add support for writing varargs functions
llvm-svn: 29876
2006-08-25 17:55:16 +00:00
29e4875f57
add the "eq" condition code
...
implement a movcond instruction
llvm-svn: 29857
2006-08-24 17:19:08 +00:00
fe03fe9bf4
create a generic bcond instruction that has a conditional code argument
...
llvm-svn: 29856
2006-08-24 16:13:15 +00:00
e08b9853cc
initial support for branches
...
llvm-svn: 29854
2006-08-24 13:45:55 +00:00
ea500426d6
add a README.txt
...
llvm-svn: 29814
2006-08-22 12:22:46 +00:00
d0dee77718
initial support for select
...
llvm-svn: 29802
2006-08-21 22:00:32 +00:00
9d77f9fd24
add the and instruction
...
llvm-svn: 29793
2006-08-21 13:58:59 +00:00
8a675a5d09
call computeRegisterProperties
...
llvm-svn: 29780
2006-08-20 01:49:49 +00:00
60f1eecd3a
Constify some methods. Patch provided by Anton Vayvod, thanks!
...
llvm-svn: 29756
2006-08-17 22:00:08 +00:00
c3ed77e1b9
add a "load effective address"
...
llvm-svn: 29748
2006-08-17 17:09:40 +00:00
bf8e751488
Declare the callee saved regs
...
Remove the hard coded store and load of the link register
Implement ARMFrameInfo
llvm-svn: 29727
2006-08-16 14:43:33 +00:00
157971b04a
select code like
...
ldr rx, [ry, #offset]
llvm-svn: 29664
2006-08-14 19:01:24 +00:00
ed728e8dc9
Eliminate use of getNode that takes a vector.
...
llvm-svn: 29614
2006-08-11 17:38:39 +00:00
c62914880f
elimiante use of getNode that takes vector of operands.
...
llvm-svn: 29612
2006-08-11 17:22:35 +00:00
bd1c5a8fb8
Match tablegen changes.
...
llvm-svn: 29604
2006-08-11 09:08:15 +00:00
81b645a76b
CALLSEQ_* produces chain even if that's not needed.
...
llvm-svn: 29603
2006-08-11 09:03:33 +00:00
1c41fc9b06
correctly set LocalAreaOffset of TargetFrameInfo
...
llvm-svn: 29589
2006-08-09 17:37:45 +00:00
f5ce475540
fix the spill code
...
llvm-svn: 29583
2006-08-09 16:41:12 +00:00
58159b36a3
fix the loading of the link register in emitepilogue
...
llvm-svn: 29580
2006-08-09 13:15:47 +00:00
8c41f99e6f
change the addressing mode of the str instruction to reg+imm
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llvm-svn: 29571
2006-08-08 20:35:03 +00:00
39083e7836
initial support for variable number of arguments
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llvm-svn: 29567
2006-08-08 13:02:29 +00:00
b9d34bd098
Match tablegen isel changes.
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llvm-svn: 29549
2006-08-07 22:28:20 +00:00
2bcb8c0f05
use a 'register pressure reducing' scheduler
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make sure only one move is used in a hello world
llvm-svn: 29520
2006-08-04 12:48:42 +00:00
e19f6fde2d
Bug fix: always generate a RET_FLAG in LowerRET
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fixes ret_null.ll and call.ll
llvm-svn: 29519
2006-08-03 22:50:11 +00:00
a94b9e33af
add and use ARMISD::RET_FLAG
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llvm-svn: 29499
2006-08-03 17:02:20 +00:00
8b7bd8264b
start comments with #
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move the constant pool to .text
correctly print loads of labels
mark R0, R1, R2 and R3 as caller save
llvm-svn: 29451
2006-08-01 18:53:10 +00:00
95035cf001
implement LowerConstantPool and LowerGlobalAddress
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llvm-svn: 29433
2006-08-01 12:58:43 +00:00
7cc2d19fc1
handle GlobalValue::InternalLinkage in doFinalization
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llvm-svn: 29417
2006-07-31 20:38:13 +00:00
b572401bea
Remove InFlightSet hack. No longer needed.
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llvm-svn: 29373
2006-07-28 00:47:19 +00:00
89e5cbd897
emit global constants
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llvm-svn: 29344
2006-07-27 11:38:51 +00:00
8902fd702b
implement function calling of functions with up to 4 arguments
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llvm-svn: 29274
2006-07-25 20:17:20 +00:00
976c93a110
implemented sub
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correctly update the stack pointer in the prologue and epilogue
llvm-svn: 29244
2006-07-21 12:26:16 +00:00
bf3a17cd32
initial prologue and epilogue implementation. Need to define add and sub before finishing it :-)
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llvm-svn: 29175
2006-07-18 17:00:30 +00:00
75269be065
skeleton of a lowerCall implementation for ARM
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llvm-svn: 29159
2006-07-16 01:02:57 +00:00
185c5c2bdf
add the memri memory operand
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this makes it possible for ldr instructions with non-zero immediate
llvm-svn: 29103
2006-07-11 11:36:48 +00:00
e40a7e2aa2
create the raddr addressing mode that matches any register and the frame index
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use raddr for the ldr instruction. This removes a dummy mov from the assembly output
remove SelectFrameIndex
remove isLoadFromStackSlot
remove isStoreToStackSlot
llvm-svn: 29079
2006-07-10 01:41:35 +00:00
f6f5aff038
handle the "mov reg1, reg2" case in isMoveInstr
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llvm-svn: 28945
2006-06-27 21:52:45 +00:00
a88966fd5e
initial implementation of ARMRegisterInfo::eliminateFrameIndex
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fixes test/Regression/CodeGen/ARM/ret_arg5.ll
llvm-svn: 28854
2006-06-18 00:08:07 +00:00
f3b5b92e58
Don't pass target name into TargetData anymore, it is never used or needed.
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Remove explicit casts to std::string now that there is no overload resolution
issues in the TargetData ctors.
llvm-svn: 28830
2006-06-16 18:22:52 +00:00
4e76015e0b
lower more then 4 formal arguments. The offset is currently hard coded.
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implement SelectFrameIndex
llvm-svn: 28751
2006-06-12 12:28:08 +00:00
6306becc49
add R0 to liveout
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expand "ret null" (implements test/Regression/CodeGen/ARM/ret_void.ll)
note that a Flag link is missing between the copy and the branch
llvm-svn: 28691
2006-06-05 22:26:14 +00:00
5bc60da112
Expand ret into "CopyToReg;BRIND"
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llvm-svn: 28559
2006-05-30 17:33:19 +00:00
64d8692dee
Ignore generated files
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llvm-svn: 28520
2006-05-27 01:23:30 +00:00
a3add0fea8
Change RET node to include signness information of the return values. i.e.
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RET chain, value1, sign1, value2, sign2, ...
llvm-svn: 28510
2006-05-26 23:10:12 +00:00
87bc1a9b0b
On ARM, alignment is in bits
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Add lr as a hard coded operand of bx
llvm-svn: 28494
2006-05-26 10:56:17 +00:00
91df1ef41f
implement initial version of ARMAsmPrinter::printOperand
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llvm-svn: 28470
2006-05-25 12:57:06 +00:00
4781610886
port the ARM backend to use ISD::CALL instead of LowerCallTo
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llvm-svn: 28469
2006-05-25 11:00:18 +00:00
4af59dac0b
Assert if InflightSet is not cleared after instruction selecting a BB.
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llvm-svn: 28459
2006-05-25 00:24:28 +00:00
1a8e74d113
Clear HandleMap and ReplaceMap after instruction selection. Or it may cause
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non-deterministic behavior.
llvm-svn: 28454
2006-05-24 20:46:25 +00:00
aa2372562e
Patches to make the LLVM sources more -pedantic clean. Patch provided
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by Anton Korobeynikov! This is a step towards closing PR786.
llvm-svn: 28447
2006-05-24 17:04:05 +00:00
27f8bdc7e5
implement minimal versions of
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ARMAsmPrinter::runOnMachineFunction
LowerFORMAL_ARGUMENTS
ARMInstrInfo::isMoveInstr
llvm-svn: 28431
2006-05-23 02:48:20 +00:00
88812b5c0a
Make all of the TargetMachine subclasses use the new string TargetData methods.
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This is part of the on-going work on PR 761.
llvm-svn: 28414
2006-05-20 00:24:56 +00:00
b15597b59a
implement movri
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add a stub LowerFORMAL_ARGUMENTS
llvm-svn: 28388
2006-05-18 21:45:49 +00:00
305c49579c
getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd.
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llvm-svn: 28378
2006-05-18 00:12:58 +00:00
dcec882286
Remove PointerType from class Target
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llvm-svn: 28368
2006-05-17 21:20:27 +00:00
4abf33f56e
add an abort after every assert(0)
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llvm-svn: 28310
2006-05-15 22:34:39 +00:00
ffdc24b847
added a skeleton of the ARM backend
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llvm-svn: 28301
2006-05-14 22:18:28 +00:00
Reid Spencer