157971b04a
select code like
...
ldr rx, [ry, #offset]
llvm-svn: 29664
2006-08-14 19:01:24 +00:00
ed728e8dc9
Eliminate use of getNode that takes a vector.
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llvm-svn: 29614
2006-08-11 17:38:39 +00:00
c62914880f
elimiante use of getNode that takes vector of operands.
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llvm-svn: 29612
2006-08-11 17:22:35 +00:00
bd1c5a8fb8
Match tablegen changes.
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llvm-svn: 29604
2006-08-11 09:08:15 +00:00
81b645a76b
CALLSEQ_* produces chain even if that's not needed.
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llvm-svn: 29603
2006-08-11 09:03:33 +00:00
1c41fc9b06
correctly set LocalAreaOffset of TargetFrameInfo
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llvm-svn: 29589
2006-08-09 17:37:45 +00:00
f5ce475540
fix the spill code
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llvm-svn: 29583
2006-08-09 16:41:12 +00:00
58159b36a3
fix the loading of the link register in emitepilogue
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llvm-svn: 29580
2006-08-09 13:15:47 +00:00
8c41f99e6f
change the addressing mode of the str instruction to reg+imm
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llvm-svn: 29571
2006-08-08 20:35:03 +00:00
39083e7836
initial support for variable number of arguments
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llvm-svn: 29567
2006-08-08 13:02:29 +00:00
b9d34bd098
Match tablegen isel changes.
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llvm-svn: 29549
2006-08-07 22:28:20 +00:00
2bcb8c0f05
use a 'register pressure reducing' scheduler
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make sure only one move is used in a hello world
llvm-svn: 29520
2006-08-04 12:48:42 +00:00
e19f6fde2d
Bug fix: always generate a RET_FLAG in LowerRET
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fixes ret_null.ll and call.ll
llvm-svn: 29519
2006-08-03 22:50:11 +00:00
a94b9e33af
add and use ARMISD::RET_FLAG
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llvm-svn: 29499
2006-08-03 17:02:20 +00:00
8b7bd8264b
start comments with #
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move the constant pool to .text
correctly print loads of labels
mark R0, R1, R2 and R3 as caller save
llvm-svn: 29451
2006-08-01 18:53:10 +00:00
95035cf001
implement LowerConstantPool and LowerGlobalAddress
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llvm-svn: 29433
2006-08-01 12:58:43 +00:00
7cc2d19fc1
handle GlobalValue::InternalLinkage in doFinalization
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llvm-svn: 29417
2006-07-31 20:38:13 +00:00
b572401bea
Remove InFlightSet hack. No longer needed.
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llvm-svn: 29373
2006-07-28 00:47:19 +00:00
89e5cbd897
emit global constants
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llvm-svn: 29344
2006-07-27 11:38:51 +00:00
8902fd702b
implement function calling of functions with up to 4 arguments
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llvm-svn: 29274
2006-07-25 20:17:20 +00:00
976c93a110
implemented sub
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correctly update the stack pointer in the prologue and epilogue
llvm-svn: 29244
2006-07-21 12:26:16 +00:00
bf3a17cd32
initial prologue and epilogue implementation. Need to define add and sub before finishing it :-)
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llvm-svn: 29175
2006-07-18 17:00:30 +00:00
75269be065
skeleton of a lowerCall implementation for ARM
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llvm-svn: 29159
2006-07-16 01:02:57 +00:00
185c5c2bdf
add the memri memory operand
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this makes it possible for ldr instructions with non-zero immediate
llvm-svn: 29103
2006-07-11 11:36:48 +00:00
e40a7e2aa2
create the raddr addressing mode that matches any register and the frame index
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use raddr for the ldr instruction. This removes a dummy mov from the assembly output
remove SelectFrameIndex
remove isLoadFromStackSlot
remove isStoreToStackSlot
llvm-svn: 29079
2006-07-10 01:41:35 +00:00
f6f5aff038
handle the "mov reg1, reg2" case in isMoveInstr
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llvm-svn: 28945
2006-06-27 21:52:45 +00:00
a88966fd5e
initial implementation of ARMRegisterInfo::eliminateFrameIndex
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fixes test/Regression/CodeGen/ARM/ret_arg5.ll
llvm-svn: 28854
2006-06-18 00:08:07 +00:00
f3b5b92e58
Don't pass target name into TargetData anymore, it is never used or needed.
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Remove explicit casts to std::string now that there is no overload resolution
issues in the TargetData ctors.
llvm-svn: 28830
2006-06-16 18:22:52 +00:00
4e76015e0b
lower more then 4 formal arguments. The offset is currently hard coded.
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implement SelectFrameIndex
llvm-svn: 28751
2006-06-12 12:28:08 +00:00
6306becc49
add R0 to liveout
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expand "ret null" (implements test/Regression/CodeGen/ARM/ret_void.ll)
note that a Flag link is missing between the copy and the branch
llvm-svn: 28691
2006-06-05 22:26:14 +00:00
5bc60da112
Expand ret into "CopyToReg;BRIND"
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llvm-svn: 28559
2006-05-30 17:33:19 +00:00
64d8692dee
Ignore generated files
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llvm-svn: 28520
2006-05-27 01:23:30 +00:00
a3add0fea8
Change RET node to include signness information of the return values. i.e.
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RET chain, value1, sign1, value2, sign2, ...
llvm-svn: 28510
2006-05-26 23:10:12 +00:00
87bc1a9b0b
On ARM, alignment is in bits
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Add lr as a hard coded operand of bx
llvm-svn: 28494
2006-05-26 10:56:17 +00:00
91df1ef41f
implement initial version of ARMAsmPrinter::printOperand
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llvm-svn: 28470
2006-05-25 12:57:06 +00:00
4781610886
port the ARM backend to use ISD::CALL instead of LowerCallTo
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llvm-svn: 28469
2006-05-25 11:00:18 +00:00
4af59dac0b
Assert if InflightSet is not cleared after instruction selecting a BB.
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llvm-svn: 28459
2006-05-25 00:24:28 +00:00
1a8e74d113
Clear HandleMap and ReplaceMap after instruction selection. Or it may cause
...
non-deterministic behavior.
llvm-svn: 28454
2006-05-24 20:46:25 +00:00
aa2372562e
Patches to make the LLVM sources more -pedantic clean. Patch provided
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by Anton Korobeynikov! This is a step towards closing PR786.
llvm-svn: 28447
2006-05-24 17:04:05 +00:00
27f8bdc7e5
implement minimal versions of
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ARMAsmPrinter::runOnMachineFunction
LowerFORMAL_ARGUMENTS
ARMInstrInfo::isMoveInstr
llvm-svn: 28431
2006-05-23 02:48:20 +00:00
88812b5c0a
Make all of the TargetMachine subclasses use the new string TargetData methods.
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This is part of the on-going work on PR 761.
llvm-svn: 28414
2006-05-20 00:24:56 +00:00
b15597b59a
implement movri
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add a stub LowerFORMAL_ARGUMENTS
llvm-svn: 28388
2006-05-18 21:45:49 +00:00
305c49579c
getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd.
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llvm-svn: 28378
2006-05-18 00:12:58 +00:00
dcec882286
Remove PointerType from class Target
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llvm-svn: 28368
2006-05-17 21:20:27 +00:00
4abf33f56e
add an abort after every assert(0)
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llvm-svn: 28310
2006-05-15 22:34:39 +00:00
ffdc24b847
added a skeleton of the ARM backend
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llvm-svn: 28301
2006-05-14 22:18:28 +00:00
Rafael Espindola