0521493aa9
Use the new -o tablegen option
...
llvm-svn: 6572
2003-06-03 05:06:33 +00:00
2712333e5f
Constants are laid out in memory in PC-relative form.
...
llvm-svn: 6568
2003-06-03 03:24:12 +00:00
c8728a147e
Added opcode conversion for conditional move of integers.
...
llvm-svn: 6567
2003-06-03 03:23:35 +00:00
cdf6256940
* Convert load/store opcodes from register to immediate forms.
...
* Stop code from wrapping to the next line.
llvm-svn: 6566
2003-06-03 03:21:58 +00:00
3cdf52a644
Convert load/store opcodes from register to immediate forms, if necessary.
...
llvm-svn: 6565
2003-06-03 03:20:57 +00:00
b54bf54065
Store instructions are different from other Format 3.1/3.2 instructions in that
...
they prefer the destination register to be last. Thus, two new classes were made
for them that accomodate for having this layout of operands (F3_1rd, F3_2rd).
llvm-svn: 6564
2003-06-03 03:20:14 +00:00
bbd10f96a2
* Added section A.34: Move FP register on int reg condition (FMOVr)
...
* Labeled sections that are not currently used in the Sparc backend as not
requiring completion at this time.
llvm-svn: 6562
2003-06-03 01:16:27 +00:00
e9465fc1d4
* Removed unused classes (rd field is always mentioned last); fixed comments.
...
* Added instruction classes which start building from rs1, then rs2, and rd.
* Fixed order of operands in classes 4.1 and 4.2; added 4.6 .
llvm-svn: 6561
2003-06-03 01:13:53 +00:00
ace89ff224
* Removed unused classes: the rd field is always mentioned as the last reg.
...
* Added new classes which start building from rs1, adding rs2, and then rd.
* Fixed order of operands in classes 3.11, 3.12, 3.16, and 3.17 .
* Fixed comments to reflect Real Life (tm).
* Removed "don't care" commented out assignments and dead classes (#if 0).
llvm-svn: 6560
2003-06-03 01:11:58 +00:00
4485c795a9
The rd field goes after the immediate field in format 2.1 instructions.
...
llvm-svn: 6559
2003-06-03 01:04:04 +00:00
f545b2402f
Added MOVR (move int reg on register condition), aka comparison with zero.
...
None of these instructions are actually used in the Sparc backend, so no changes
were required in the instruction selector.
llvm-svn: 6549
2003-06-02 21:16:54 +00:00
843d6933a0
SparcInstr.def: added 'r' and 'i' versions of MOV(F)cc instructions
...
SparcInstrSelection.cpp:
* Fixed opcodes to return correct 'i' version since the two functions are each
only used in one place.
* Changed name of function to have an 'i' in the name to signify that they each
return an immediate form of the opcode.
* Added a warning if either of the functions is ever used in a context which
requires a register-version opcode.
SparcV9_F4.td: fixed class F4_3, added F4_4 and notes that F4_{1,2} need fixing
SparcV9.td: added the MOV(F)cc instructions
llvm-svn: 6548
2003-06-02 20:55:14 +00:00
609b55c255
* Added casts to/from floating-point to integers.
...
* Changed // comments to #ifdef 0 to maintain syntax highlighting.
llvm-svn: 6546
2003-06-02 19:08:37 +00:00
55c6331637
Clean up after merging in SparcEmitter.cpp; branches and return work again.
...
llvm-svn: 6536
2003-06-02 05:24:46 +00:00
7b66a726f8
Minor cleanups
...
llvm-svn: 6535
2003-06-02 05:21:06 +00:00
f9162dc713
Eliminated a compiler warning due to casting to a different-sized datatype.
...
llvm-svn: 6531
2003-06-02 04:13:58 +00:00
ce62d36615
Merged in tools/lli/JIT/SparcEmitter.cpp, coupled with the JITResolver taken
...
from lib/Target/X86/X86CodeEmitter.cpp .
llvm-svn: 6530
2003-06-02 04:12:39 +00:00
29848417f3
Renamed MachineCodeEmitter.cpp -> X86CodeEmitter.cpp as it conflicts with the
...
target-independent lib/CodeGen/MachineCodeEmitter.cpp; preserved CVS history.
llvm-svn: 6528
2003-06-02 03:28:00 +00:00
bca71e4735
Deal with %lo/%lm/%hm/%hh flags in getMachineOpValue().
...
llvm-svn: 6522
2003-06-02 02:13:26 +00:00
3bb2a00849
Move X86 specific code out of the JIT into the X86 backend
...
llvm-svn: 6516
2003-06-01 23:23:50 +00:00
13dffdefef
Make the .inc file depend on $(TBLGEN), so that changes to TableGen followed
...
by a re-link of TableGen will notify Make to rebuild the .inc file.
llvm-svn: 6512
2003-06-01 04:52:51 +00:00
4536fcd57b
* Implement cast (long|ulong) to bool
...
* Fix cast of (short|ushort|int|uint) to bool to work right
llvm-svn: 6510
2003-06-01 03:38:24 +00:00
bf37f7de1b
Add RR forms of test instruction
...
llvm-svn: 6509
2003-06-01 03:37:46 +00:00
e6c3ee6b07
Add map info for arguments to call (copies)
...
llvm-svn: 6503
2003-06-01 02:48:23 +00:00
372086c87b
Add support for shl and shr for 64 bit integer types
...
llvm-svn: 6499
2003-06-01 01:56:54 +00:00
ea447da8a8
Add definitions for TEST instructions
...
llvm-svn: 6498
2003-06-01 01:56:39 +00:00
70f158330c
Add new cmovne32 instruction
...
llvm-svn: 6496
2003-06-01 00:05:15 +00:00
ba6f8e274a
Several bug fixes: globals in call operands were not being pulled out;
...
globals in some other places may not have been pulled out either;
globals in phi operands were being put just before the phi instead of
in the predecessor basic blocks.
llvm-svn: 6466
2003-05-31 07:34:57 +00:00
a83804a29a
Extensive changes to the way code generation occurs for function
...
call arguments and return values:
Now all copy operations before and after a call are generated during
selection instead of during register allocation.
The values are copied to virtual registers (or to the stack), but
in the former case these operands are marked with the correct physical
registers according to the calling convention.
Although this complicates scheduling and does not work well with
live range analysis, it simplifies the machine-dependent part of
register allocation.
llvm-svn: 6465
2003-05-31 07:32:01 +00:00
96b801ab56
Reverting previous beautification changes.
...
llvm-svn: 6464
2003-05-31 07:27:17 +00:00
bf69b7fe69
Removed useless code -- the byte order of output code is correct as is.
...
llvm-svn: 6462
2003-05-31 06:26:06 +00:00
23937091f0
The 'rd' register is consistently mentioned last in instruction definitions.
...
Created new classes from which instructions inherit their ordering of fields.
llvm-svn: 6461
2003-05-31 06:25:19 +00:00
c4f029f8ba
* Put back into action SLL/SRL/SRA{r,i}6 instructions
...
* Fixed page numbers referring to the Sparc manual
llvm-svn: 6460
2003-05-31 06:24:29 +00:00
8d5316769f
Code beautification, no functional changes.
...
llvm-svn: 6459
2003-05-31 06:22:37 +00:00
0b3a70c25b
Enabling some of these passes causes lli to break
...
llvm-svn: 6457
2003-05-31 04:23:04 +00:00
87cbd97710
The actual order of parameters in a 2-reg-immediate assembly instructions is
...
"rs1, imm, rd": most importantly, rd goes last.
llvm-svn: 6456
2003-05-31 04:22:26 +00:00
5bf351c880
Added:
...
* ability to save BasicBlock references to be resolved later
* register remappings from the enum values to the real hardware numbers
llvm-svn: 6449
2003-05-30 20:17:33 +00:00
0757de607a
Fixed the namespace to match SparcInternals.h; added notes on some missing
...
sections of instructions.
llvm-svn: 6448
2003-05-30 20:15:59 +00:00
8747377292
The register types need to be visible outside of the class to be useful.
...
For one, converting register numbers based on class in the code emitter.
llvm-svn: 6447
2003-05-30 20:12:42 +00:00
a853af587a
Moved and expanded convertOpcodeFromRegToImm() to conver more opcodes.
...
Code beautification for the rest of the code: changed layout to match the rest
of the code base.
llvm-svn: 6446
2003-05-30 20:11:56 +00:00
c1830a472a
Make LLI behave just like LLC with regard to the compile passes it uses.
...
llvm-svn: 6444
2003-05-30 20:00:13 +00:00
39dfa6a920
Made the register and immediate versions of instructions consecutive.
...
llvm-svn: 6439
2003-05-30 19:14:01 +00:00
f6e4dce74c
Because the format of the shift instructions is `shift r, shcnt, r', the
...
instructions of format 3.12 and 3.13 cannot inherit from F3rdrs1, because that
implies that the two registers are the first two parameters to the instruction.
Thus I made the instructions inherit from F3rd again, and manually added an rs1
field AFTER the shcnt field in the instruction, which maps to the appropriate
place in the instruction.
The other changes are just elimination of unnecessary spaces.
llvm-svn: 6437
2003-05-30 18:06:10 +00:00
d380f29377
Makefile: Make SparcV9CodeEmitter.inc depend on SparcV9_F*.td as well.
...
SparcV9_F3.td: F3_12 and F3_13 instructions have rd and rs1 fields. Also,
their fields were totally screwed up. This seems to fix the problem.
llvm-svn: 6429
2003-05-30 08:02:14 +00:00
6ada87e6eb
Since there is now another derived .inc file, ignore them all.
...
llvm-svn: 6411
2003-05-29 20:15:27 +00:00
9175a5de53
Use an absolute path to TableGen because not everyone (e.g. automatic tester)
...
has their path set up by this point.
llvm-svn: 6410
2003-05-29 20:09:56 +00:00
bb053cefe8
Added the target-independent part of TableGen data.
...
llvm-svn: 6403
2003-05-29 18:48:17 +00:00
35d5512f34
When TableGen finds an error in the SparcV9.td file, it exits with a non-zero
...
exit code. This, in turn, makes an empty file SparcV9CodeEmitter.inc, and only
much later, produces a link error because the key function that TableGen creates
isn't found.
Using a temporary file in the middle forces a good .INC file to be generated by
TableGen, and it will keep trying until you fix the input file.
llvm-svn: 6392
2003-05-29 05:29:22 +00:00
794c8a1334
Fixed to use the correct format of the instruction.
...
llvm-svn: 6390
2003-05-29 04:53:56 +00:00
376dac2eed
This should work better with re-generating the SparcV9CodeEmitter.inc file.
...
Also, added a rule to delete the generated .inc file on `make clean'.
llvm-svn: 6389
2003-05-29 03:32:49 +00:00
ea4f498395
* Broke up SparcV9.td into separate files as it was getting unmanageable
...
* Added some Format 4 classes, but not instructions
* Added notes on missing sections with FIXMEs
* Added RDCCR instr
llvm-svn: 6388
2003-05-29 03:31:43 +00:00
fded35952a
Fixed ordering of elements in instructions: although the binary instructions
...
list (rd, rs1, imm), in that order (bit-wise), the actual assembly syntax is
instr rd, imm, rs1, and that is how they are constructed in the instruction
selector. This fixes the discrepancy.
Also fixed some comments along the same lines and fixed page numbers referring
to where instructions are described in the Sparc manual.
llvm-svn: 6384
2003-05-28 17:49:29 +00:00
2c35144ce5
Add dependency to make TableGen rule fire.
...
llvm-svn: 6383
2003-05-28 17:41:09 +00:00
07b60f8e2e
Fixed an error preventing compilation.
...
llvm-svn: 6381
2003-05-27 22:48:28 +00:00
481dfdb523
Added the 'r' and 'i' annotations to instructions as their opcode names have
...
changed.
llvm-svn: 6380
2003-05-27 22:44:44 +00:00
7975661a8e
Keep track of the current BasicBlock being processed so that a referencing
...
MachineInstr can later be patched up correctly.
llvm-svn: 6378
2003-05-27 22:41:44 +00:00
af96d39c04
Added 'r' and 'i' annotations to instructions as SparcInstr.def has changed.
...
llvm-svn: 6377
2003-05-27 22:40:34 +00:00
96ce62a105
Added 'r' or 'i' annotations to instructions, as SparcInstr.def has changed.
...
Non-obvious change: since I have changed ST and STD to be STF and STDF to
(a) closer resemble their name (NOT assembly text) in the Sparc manual, and
(b) clearly specify that they they are floating-point opcodes,
I made the same changes in this file.
llvm-svn: 6376
2003-05-27 22:39:01 +00:00
da83883ef1
Added 'r' or 'i' annotations to instructions, as SparcInstr.def has changed.
...
Here I had to make one non-trivial change: add a function to get a version of
the opcode that takes an immediate, given an opcode that takes all registers.
This is required because sometimes it is not known at construction time which
opcode is used because opcodes are passed around between functions.
llvm-svn: 6375
2003-05-27 22:37:00 +00:00
8bde6a688c
Added 'r' or 'i' annotations to instructions, as SparcInstr.def has changed.
...
llvm-svn: 6373
2003-05-27 22:35:43 +00:00
cb801a6884
Added entries for each of the instructions with annotations ('r' or 'i').
...
llvm-svn: 6372
2003-05-27 22:33:39 +00:00
db69bebc89
One of the first major changes to make the work of JITting easier: adding
...
annotations on instructions to specify which format they are (i.e., do they take
2 registers and 1 immediate or just 3 registers) as that changes their binary
representation and hence, code emission.
This makes instructions more like how X86 defines them to be. Now, writers of
instruction selection must choose the correct opcode based on what instruction
type they are building, which they already know. Thus, the JIT doesn't have to
do the same work by `discovering' which operands an instruction really has.
As this involves lots of small changes to a lot of files in lib/target/Sparc,
I'll commit them individually because otherwise the diffs will be unreadable.
llvm-svn: 6371
2003-05-27 22:32:38 +00:00
8110439ff6
* Allow passing in an unsigned configuration to allocateSparcTargetMachine()
...
a default value is set in the header file.
* Fixed some code layout to make it more consistent with the rest of codebase
* Added addPassesToJITCompile() with relevant passes
llvm-svn: 6369
2003-05-27 22:24:48 +00:00
8b28140662
Moved generation of the SparcV9CodeEmitter.inc file higher in the Makefile so
...
that Makefile.common would see it.
llvm-svn: 6367
2003-05-27 22:04:38 +00:00
5641434438
Add prototypes to add passes to JIT compilation and code emission.
...
Also, added annotations to how instructions are modified (reg/imm operands).
Added prototype for adding register numbers to values pass for interfacing with
the target-independent register allocators in the JIT.
llvm-svn: 6366
2003-05-27 22:01:10 +00:00
e195b7c0fc
Broke out class definition from SparcV9CodeEmitter, and added ability to take a
...
MachineCodeEmitter to make a pass-through debugger -- output to memory and to
std::cerr.
llvm-svn: 6363
2003-05-27 21:45:05 +00:00
3e9272fb29
SparcV9CodeEmitter.cpp is a part of the Sparc code emitter. The main function
...
that assembles instructions is generated via TableGen (and hence must be built
before building this directory, but that's already the case in the top-level
Makefile).
Also added is .cvsignore to ignore the generated file `SparcV9CodeEmitter.inc',
which is included by SparcV9CodeEmitter.cpp .
llvm-svn: 6357
2003-05-27 20:07:58 +00:00
d452b60678
Added definitions for a bunch of floating-point instructions.
...
llvm-svn: 6356
2003-05-27 20:03:29 +00:00
631006ba48
Renamed opIsDef to opIsDefOnly.
...
llvm-svn: 6340
2003-05-27 00:03:17 +00:00
8adb9944aa
Added special register class containing (for now) %fsr.
...
Fixed spilling of %fcc[0-3] which are part of %fsr.
Moved some machine-independent reg-class code to class TargetRegInfo
from SparcReg{Class,}Info.
llvm-svn: 6339
2003-05-27 00:02:22 +00:00
3ee4e2a3c1
Bug fix: right shift for int divide-by-power-of-2 was incorrect for
...
negative values. Need to add one to a negative value before right shift!
llvm-svn: 6334
2003-05-25 21:59:47 +00:00
5f36d741db
Bug fix: padding bytes within a structure should go after each field!
...
llvm-svn: 6333
2003-05-25 21:59:09 +00:00
5b941461b1
Bug fix: sign-extension was not happening for C = -MININT since C == -C!
...
llvm-svn: 6332
2003-05-25 21:58:11 +00:00
c9a0a1d728
Add support for compiling varargs functions.
...
llvm-svn: 6325
2003-05-25 15:59:47 +00:00
e2402c65d0
Reword to remove reference to how things worked in the past.
...
llvm-svn: 6323
2003-05-24 01:08:43 +00:00
d21a02ad58
Implement the TargetInstrInfo's createNOPinstr() and isNOPinstr() interface.
...
llvm-svn: 6320
2003-05-24 00:09:50 +00:00
39968bbc46
Cleaned up code layout; no functional changes.
...
llvm-svn: 6312
2003-05-23 19:20:57 +00:00
c42dc745db
Fixed `volatile' typo.
...
llvm-svn: 6266
2003-05-21 19:34:28 +00:00
f865cc44ab
Cleaned up code layout, spacing, etc. for readability purposes and to be more
...
consistent with the style of LLVM's code base (and itself! it's inconsistent in
some places.)
No functional changes were made.
llvm-svn: 6265
2003-05-21 18:48:06 +00:00
6532e427b4
* Fix divide by zero error with empty structs
...
* Empty structs should have ALIGNMENT 1, not SIZE 1.
llvm-svn: 6263
2003-05-21 18:08:44 +00:00
2a651d7a0e
Cleaned up code layout, spacing, etc. for readability purposes and to be more
...
consistent with the style of LLVM's code base (and itself! it's inconsistent in
some places.)
No functional changes were made.
llvm-svn: 6262
2003-05-21 18:05:35 +00:00
352f7ac072
Namespacified `vector' and `cerr' to always use the `std::' namespace.
...
Eliminated `using' directives.
llvm-svn: 6261
2003-05-21 17:59:06 +00:00
56f4fa10fd
Sparc instruction opcodes now all live under the `V9' namespace.
...
llvm-svn: 6249
2003-05-20 20:32:24 +00:00
9c105cd27f
Clean up #includes
...
llvm-svn: 6173
2003-05-13 20:21:19 +00:00
3fa7b77ddf
Make abort more explicit
...
llvm-svn: 6151
2003-05-12 21:16:26 +00:00
d4e5409f35
Remove the assertion failure of course... doh
...
llvm-svn: 6150
2003-05-12 20:39:39 +00:00
5069283493
Implement casts from unsigned integers to floating point
...
llvm-svn: 6148
2003-05-12 20:36:13 +00:00
6c906adb73
Make error messages more useful than jsut an abort
...
llvm-svn: 6146
2003-05-12 20:16:58 +00:00
b1eee00034
Remove wierd printout
...
llvm-svn: 6145
2003-05-12 20:10:12 +00:00
786bd8849a
Do not insert multiple initializations for the same value in a PHI node
...
llvm-svn: 6113
2003-05-12 14:22:21 +00:00
74b65ee219
This blank line has GOT to go.
...
llvm-svn: 6057
2003-05-09 03:28:13 +00:00
93c8eddd75
Add support for Add, Sub, And, Or, & Xor constant exprs
...
llvm-svn: 6049
2003-05-08 20:49:25 +00:00
b257aab658
Add support for variable argument functions!
...
llvm-svn: 6046
2003-05-08 19:44:13 +00:00
25e907dae4
Added the initial version of the TableGen description for the Sparc backend.
...
llvm-svn: 6021
2003-05-07 21:52:39 +00:00
d964c3b9fd
IMPLICIT_DEF was not the beautiful elegant solution I thought it was going
...
to be. In fact, it made stuff worse. :(
llvm-svn: 6013
2003-05-07 19:21:28 +00:00
37ffac92d5
Emit pseudo instructions to indicate that some registers are live on entrance
...
and exit of the function. This fixes bug: Jello/2003-05-06-LivenessClobber.llx
and the Fhourstones benchmark
llvm-svn: 6010
2003-05-06 21:32:22 +00:00
4b1e02df8f
Don't have a cow with new pseudo instructions
...
llvm-svn: 6009
2003-05-06 21:31:47 +00:00
8788d6e122
Add two new pseudo instructions
...
llvm-svn: 6008
2003-05-06 21:31:31 +00:00
effa5ba1ac
The Hyphenation-Adding Committee is now in session.
...
llvm-svn: 5986
2003-05-03 02:18:17 +00:00
3ed86610cd
Eliminate use of NonCopyable so that doxygen documentation doesn't link
...
the Annotation classes with the noncopyable classes for no reason
llvm-svn: 5973
2003-05-01 20:28:45 +00:00
4f6cdbdf81
Remove two fields from TargetData which are target specific.
...
llvm-svn: 5963
2003-04-26 20:11:09 +00:00
25900cf220
The promotion rules are the same for all targets, they are set by the C standard.
...
llvm-svn: 5962
2003-04-26 19:47:36 +00:00
21d4509d76
IntegerRegSize is always 8 for sparc
...
llvm-svn: 5961
2003-04-26 19:44:35 +00:00
2a2338f1ba
Fix bogus assert
...
llvm-svn: 5949
2003-04-25 21:58:54 +00:00
b05f851d59
Whoops, 32 bit targets have _4_ byte pointers, not _32_ byte pointers!
...
llvm-svn: 5937
2003-04-25 06:06:43 +00:00
afdf01ef62
Fix compatibility bug: X86 aligns doubles to 4 bytes, not 8!
...
llvm-svn: 5935
2003-04-25 06:05:57 +00:00
efbae9cff1
Fix obvious type-o
...
llvm-svn: 5932
2003-04-25 05:23:10 +00:00
e483398516
Allow for easy detection of when a "default" TargetData is created by the
...
passmanager, which is never the right thing to do.
llvm-svn: 5922
2003-04-25 02:50:45 +00:00
42516baf76
add a new targetdata ctor to create a target data appropriate to the module
...
llvm-svn: 5903
2003-04-24 19:09:05 +00:00
13cafd041a
Trivial cleanup
...
llvm-svn: 5899
2003-04-24 18:35:51 +00:00
ec6f16eae6
Fix iterator invalidation problem with cast instructions
...
llvm-svn: 5876
2003-04-23 17:57:48 +00:00
2670371c9a
Implement the constantexpr CAST instruction correctly
...
llvm-svn: 5875
2003-04-23 17:22:12 +00:00
524608ab79
Add support for the Switch instruction by running the lowerSwitch pass first
...
llvm-svn: 5867
2003-04-23 16:24:55 +00:00
dd4745241f
It's "necessary"...
...
llvm-svn: 5848
2003-04-22 20:20:11 +00:00
e569e992d8
It's "necessary" to spell "necessarily" correctly.
...
llvm-svn: 5833
2003-04-22 17:54:23 +00:00
5b348718df
Add support for a simple constantexpr: cast of one ptr type to another
...
llvm-svn: 5829
2003-04-21 21:33:44 +00:00
379a8d2d1c
Add new linkage types to support a real frontend
...
llvm-svn: 5786
2003-04-16 20:28:45 +00:00
30f40d94cc
Rename -no-* to -disable-*
...
llvm-svn: 5642
2003-02-26 20:00:41 +00:00
ae1f73b4f5
Remove wierd case that can never happen
...
llvm-svn: 5623
2003-02-25 20:27:09 +00:00
76e9f774dd
Don't emit unneccesary branch instructions!
...
llvm-svn: 5328
2003-01-16 18:07:23 +00:00
4769c1bef8
Fix problem with invalidated iterator
...
llvm-svn: 5327
2003-01-16 18:07:13 +00:00
2f983fcce3
Implement optimization folding setcc into branch.
...
llvm-svn: 5324
2003-01-16 16:43:00 +00:00
8c59d64041
Add more flavors of branch instructions
...
llvm-svn: 5323
2003-01-16 16:42:45 +00:00
b2809dc6b5
Implement code to keep the stack pointer aligned to an 8 byte boundary.
...
This improves the performance of the power benchmark by a few percent.
This will be neccesary for SSE code, which requires 16 byte alignment of
the stack.
llvm-svn: 5320
2003-01-16 02:20:12 +00:00
9e75444c8b
Handle frame offset due to return address pushed on the stack
...
llvm-svn: 5319
2003-01-15 22:57:35 +00:00
dea36ca100
Move sparc specific code into the Sparc backend
...
llvm-svn: 5317
2003-01-15 21:36:50 +00:00
4f596d7a2c
Fix warnings
...
llvm-svn: 5316
2003-01-15 21:36:30 +00:00
f9fd59148c
Adjust to simpler interfaces
...
Eliminate dependency on RegClass.h
llvm-svn: 5315
2003-01-15 21:14:32 +00:00
a23969b669
#include RegClass.h explicitly
...
llvm-svn: 5307
2003-01-15 19:57:07 +00:00
90fc665489
Move private header to private directory
...
llvm-svn: 5305
2003-01-15 19:50:44 +00:00
d840ccd2e0
Prune #includes
...
llvm-svn: 5303
2003-01-15 19:48:13 +00:00
e58cd301cd
Use BuildMI more
...
llvm-svn: 5299
2003-01-15 19:23:34 +00:00
8145abb99e
Fix bug found by regtests
...
llvm-svn: 5294
2003-01-15 18:11:11 +00:00
1ebaa90f48
Use BuildMI more, Create*Instruction less
...
llvm-svn: 5291
2003-01-15 17:47:49 +00:00
33be2a23ee
X86 backend should never use addMReg
...
llvm-svn: 5288
2003-01-15 00:04:14 +00:00
71aa7afc27
* Elimiante a bunch of functions from InstrSelectionSupport.h, replacing users
...
of them with BUildMI calls instead.
* Fix def information in instructions generated by prologepilog inserter
llvm-svn: 5287
2003-01-15 00:03:28 +00:00
24c1d5e551
Rename llvm/Analysis/LiveVar/FunctionLiveVarInfo.h -> llvm/CodeGen/FunctionLiveVarInfo.h
...
llvm-svn: 5284
2003-01-14 23:05:08 +00:00
b4d58d7f9e
Rename MachineInstrInfo -> TargetInstrInfo
...
llvm-svn: 5272
2003-01-14 22:00:31 +00:00
c49ca9ce58
Minor cleanups
...
llvm-svn: 5266
2003-01-14 20:32:10 +00:00
cf53bcf8e4
New files
...
llvm-svn: 5260
2003-01-13 01:01:59 +00:00
962d5befb3
* No longer need lowerallocation pass
...
* Add X86 Stackifier pass
* Add peephole optimizer pass
llvm-svn: 5233
2003-01-13 00:51:23 +00:00
c39dc9e648
rename FP -> fp*
...
llvm-svn: 5232
2003-01-13 00:50:46 +00:00
06e07162fc
* Move frame and constant pool indexes to first argument of memory reference
...
so we can put an offset in there as well...
* Fix long/ulong stuff
llvm-svn: 5231
2003-01-13 00:50:33 +00:00
9fe3518dc0
* Some instructions take 64 bit integers, add an Arg type for it
...
* Add flags for different types of FP pseudo instrs
llvm-svn: 5230
2003-01-13 00:49:24 +00:00
5cc425a8e1
* Function calls clobber fp registers
...
* Use new M_TERMINATOR_FLAG flag
* Add ::Void flag on several instructions so def-use info is correct!
* Implement MANY FP instructions
* Finalize pseudo FP instructions
* Add set of Pseudo FP instruction description flags
* Add support for MOVim instrs
* Add support for 64 bit support instrs, like adc sbb, etc
* Add conditional move
llvm-svn: 5229
2003-01-13 00:48:46 +00:00
7878563ff9
Add support for frame and constant pool references
...
llvm-svn: 5228
2003-01-13 00:45:53 +00:00
61e1195e89
Move passes out to Passes.h
...
llvm-svn: 5227
2003-01-13 00:45:29 +00:00
888a8084b6
Add speculation
...
llvm-svn: 5226
2003-01-13 00:35:08 +00:00
956e8379f9
* Implement rudimentary output of the constant pool
...
* Implement support for MRMS?m instructions
* Add Arg64 support
* Add support for frame indexes and constant pool indexes
*
llvm-svn: 5225
2003-01-13 00:35:03 +00:00
d4ba62218e
* Add support for FP registers ST*
...
* Add support for the constant pool & constant pool indices
* Add support for MRMS?m instructions
* Fix FP Prefix emission
* Add support for global addresses and external symbols
llvm-svn: 5224
2003-01-13 00:33:59 +00:00
6c0daf795a
* Adjust to use new interfaces, eliminating CurReg stuff
...
* Support arbitrary FP constants
* Fix bugs in frame layout for function calls and incoming arguments
* Insert copies for constant arguments to PHI nodes into the BOTTOM of
predecessor blocks, not the top.
* Implement _floating point_ support: setcc, return, load, store, cast
* Fix several bugs in the cast instruction
* Abstract out call emission and load/store for FP
* Implement malloc/free without previous lowering pass.
* Make use of new forms of MachineOperand
* Implement _long_ support!
* Fix many bugs in FP support
* Change branch from je/jne to je/jmp
* Simplify code generated for GEP instructions
llvm-svn: 5223
2003-01-13 00:32:26 +00:00
0d5644bb6d
Start renaming MachineInstrInfo -> TargetInstrInfo
...
llvm-svn: 5221
2003-01-13 00:26:36 +00:00
f9781b59ab
More renamings of Target/Machine*Info to Target/Target*Info
...
llvm-svn: 5204
2002-12-29 03:13:05 +00:00
42d59219c7
Rename MachineOptInfo to TargetoptInfo
...
Rename MachineCacheInfo to TargetCacheInfo
llvm-svn: 5203
2002-12-29 02:50:35 +00:00
83d835da2a
Rename MachineOptInfo to TargetoptInfo
...
Rename MachineCacheInfo to TargetCacheInfo
llvm-svn: 5202
2002-12-29 02:50:33 +00:00
26c23467c5
Rename FunctionFrameInfo to MachineFrameInfo
...
llvm-svn: 5201
2002-12-28 21:08:28 +00:00
871e591e34
Rename MachineFrameInfo to TargetFrameInfo.h
...
llvm-svn: 5199
2002-12-28 21:00:25 +00:00
2ca5e23403
Put class in anonymous namespace
...
llvm-svn: 5197
2002-12-28 20:42:56 +00:00
0ccedc254c
Eliminate unneccesary file
...
llvm-svn: 5191
2002-12-28 20:34:47 +00:00
d2577010d5
Capture more information in ctor
...
llvm-svn: 5190
2002-12-28 20:34:18 +00:00
362b26c37e
Implement the TargetFrameInfo interface
...
llvm-svn: 5189
2002-12-28 20:33:52 +00:00
9a81e69439
* Initialize new FrameInfo member
...
* most pass ctors no longer take TM arguments
* New prolog/epilog insertion pass
llvm-svn: 5188
2002-12-28 20:33:32 +00:00
e6fb194716
Changes to match new MRegisterInfo api
...
llvm-svn: 5187
2002-12-28 20:32:54 +00:00
1d79b4ce86
*** Implement frame pointer elimination on X86!
...
* Include contents of X86RegisterClasses.cpp into here
* Adjustments to register api to work with new frame manager
* Eliminate moveImm2Reg, getFramePointer, and getStackPointer
* Cleanup and simplify prolog/epilog code generation
* Prolog/epilog are MUCH more efficient now.
llvm-svn: 5186
2002-12-28 20:32:28 +00:00
9a9739e517
Contents merged with X86RegisterInfo.cpp
...
llvm-svn: 5185
2002-12-28 20:30:15 +00:00
59a20d7b6d
* Remove implementations of previously pure virtual functions that are not any longer.
...
llvm-svn: 5184
2002-12-28 20:29:41 +00:00
365ede3748
* Minor reformatting
...
* Remove some size suffixes [bwl]
* Add new ADJCALLSTACKDOWN & ADJCALLSTACKUP pseudo instrs
* Call instructions are M_CALL not M_BRANCH!
* Disable push and pop instructions
* Add new ANDri32 instr
llvm-svn: 5183
2002-12-28 20:29:14 +00:00
ef5a8f912c
New addFrameReference function
...
llvm-svn: 5182
2002-12-28 20:26:58 +00:00
4937643df9
* Most pass ctor functions don't take TM arguments anymore
...
* New createPrologEpilogCodeInserter() function
llvm-svn: 5181
2002-12-28 20:26:16 +00:00
1520c5ab2a
* Convert to a MachineFunctionPass
...
* Don't take a TM as a ctor parameter
* Print [X - Y] instead of [X + -Y] when possible
llvm-svn: 5180
2002-12-28 20:25:38 +00:00
d24f633394
* Convert to a MachineFunctionPass
...
* ctor doesn't take TM argument
* handle direct ESP references correctly!
llvm-svn: 5179
2002-12-28 20:24:48 +00:00
51553e0700
* Use the new Abstract Frame Manager to handle incoming arguments and
...
fixed size allocas
* Revamp call emission to work with new frame manager
llvm-svn: 5178
2002-12-28 20:24:02 +00:00
d47aac9d4b
* Rename machineFrameInfo to targetFrameInfo
...
* Constant pool and frame info is no longer directly in MachineFunction
llvm-svn: 5177
2002-12-28 20:21:29 +00:00
fe9b705bed
* Rename MachineFrameInfo to TargetFrameInfo
...
* Move some sparc specific code here from Target files
llvm-svn: 5176
2002-12-28 20:20:24 +00:00
b9feac398f
* TargetData is no longer directly accessable from TM
...
* s/unsigned int/unsigned/
llvm-svn: 5175
2002-12-28 20:19:44 +00:00
a41b89a829
* TargetData is no longer directly accessable from TargetMachine
...
* Constpool & frame info is no longer directly in MachineFunction
llvm-svn: 5174
2002-12-28 20:18:21 +00:00
525e3af36c
* Frame & const pool info is no longer directly in MachineFunction
...
llvm-svn: 5173
2002-12-28 20:17:43 +00:00
d2a67df791
* Changes to be a MachineFunctionPass
...
* Frame information is now stuck in MachineFunctionInfo instead of directly
in MachineFunction.
* Don't require a TM as an argument to the ctor
llvm-svn: 5172
2002-12-28 20:16:08 +00:00
4d84d49f75
* Don't access TargetData directly
...
* Changes because frame info is not in MachineFunction directly anymore
llvm-svn: 5171
2002-12-28 20:15:01 +00:00
a76f456a60
* Simplify Value classes
...
* Add initial support for FP constants
* Add initial FP support for several instructions
llvm-svn: 5154
2002-12-25 05:13:53 +00:00
6ecc6a72c9
* Use new pseudo instr form for instructions
...
* Mark CALLpcrel as a RawFrm instruction as required
* Eliminate invalid BSWAP16 instruction
* Add xchg instructions
* Add initial support for FP instructions
llvm-svn: 5153
2002-12-25 05:11:46 +00:00
e98ca19112
Add FP instr prefix byte support
...
Add Pseudo instr class
llvm-svn: 5152
2002-12-25 05:09:59 +00:00
36703cd02a
Add support for FP prefixes
...
llvm-svn: 5151
2002-12-25 05:09:21 +00:00
7c10f4f5d4
Add printer support for Pseudo instructions
...
llvm-svn: 5150
2002-12-25 05:09:01 +00:00
c9f3bbb5d2
Initial support for FP registers
...
llvm-svn: 5149
2002-12-25 05:08:03 +00:00
dafa31658f
New simpler spill interface
...
llvm-svn: 5148
2002-12-25 05:07:09 +00:00
4997a840bc
Adjustments to match new simpler spill interface
...
llvm-svn: 5147
2002-12-25 05:06:43 +00:00
55aaff5590
Free machine code
...
llvm-svn: 5146
2002-12-25 05:06:21 +00:00
a32b4055be
Changes to allow for a configurable target machine that allows big endian and/or long pointer operation
...
llvm-svn: 5131
2002-12-24 00:04:01 +00:00
cfcd0603d0
Changes to compile with GCC 2.96
...
Changes to support configurable pointer size and endianness
llvm-svn: 5130
2002-12-24 00:03:11 +00:00
ccc2c7e8a7
Sparc is not little endian
...
llvm-svn: 5129
2002-12-24 00:02:38 +00:00
d8201972bf
Fix compilation on gcc 2.96
...
llvm-svn: 5116
2002-12-23 23:46:55 +00:00
871abd8187
Add definition for the bswap instruction
...
*** FIX: the encoding of the SUB instruction
llvm-svn: 5115
2002-12-23 23:46:31 +00:00
e218f7924c
Add support for the bswap instruction
...
llvm-svn: 5114
2002-12-23 23:46:00 +00:00
6e7c821dc0
Fix warning
...
llvm-svn: 5109
2002-12-20 04:13:28 +00:00
5526b21e93
CBW doesn't modify AL
...
llvm-svn: 5108
2002-12-20 04:13:11 +00:00
67e555d1ec
fix warning
...
llvm-svn: 5107
2002-12-20 04:12:48 +00:00
b437b7de1a
Don't force setCC instructions into AL
...
llvm-svn: 5104
2002-12-18 01:44:31 +00:00
b54343a64f
Add comments, switch uses/defs to match InstrInfo.def file
...
llvm-svn: 5102
2002-12-18 01:05:54 +00:00
fc9af85395
Add reg clobber list for direct calls
...
Represent empty use/def list as a null pointer
llvm-svn: 5101
2002-12-18 01:05:31 +00:00
4cb8af96b3
Update to use new interface for register info
...
llvm-svn: 5098
2002-12-17 04:19:17 +00:00
0eece84186
New file
...
llvm-svn: 5097
2002-12-17 04:03:08 +00:00
eaf58b03b2
Round number of bytes allocated on the stack up to a multiple of 4 so that the
...
stack remains aligned
llvm-svn: 5095
2002-12-17 03:15:26 +00:00
d9c6f2a6d3
Local register allocator is now stable enough for use, it passes all tests
...
llvm-svn: 5094
2002-12-17 02:51:15 +00:00
5afbc4c387
Register allocator is responsible for spilling callee saved regs
...
llvm-svn: 5092
2002-12-17 02:48:57 +00:00
2e6f17f136
Build add instructions of the correct form!
...
llvm-svn: 5090
2002-12-16 23:36:57 +00:00
e92fb346d3
Two fixes:
...
* Only load incoming arguments into virtual registers once at the
beginning of the function
* Assign different virtual registers to each reference to constants/globals
llvm-svn: 5088
2002-12-16 22:54:46 +00:00
c87fcde854
Fix prolog/epilog in the presence of alloca
...
llvm-svn: 5087
2002-12-16 22:29:30 +00:00
e92f1bb011
Make sure stack manipulation refers to ESP the right number of times
...
llvm-svn: 5086
2002-12-16 22:29:06 +00:00
5c59014a1b
Add some special cases to make common getelementptr cases easier to read/faster
...
llvm-svn: 5084
2002-12-16 19:32:50 +00:00
6b5ca53493
Finish implementation of alias list impl
...
llvm-svn: 5083
2002-12-16 19:31:48 +00:00
e0c25aaf99
Add mechanism to select register allocator to use
...
llvm-svn: 5079
2002-12-16 16:15:51 +00:00
d44d25323d
Try #2 to get alias set stuff to work
...
llvm-svn: 5077
2002-12-16 16:14:51 +00:00
9b83781030
Add comments
...
llvm-svn: 5076
2002-12-16 15:57:44 +00:00
36d6f4a303
Add info about register aliases, add prototype for createLocalRegisterAllocator
...
llvm-svn: 5075
2002-12-16 15:55:51 +00:00
4cf76c23e8
Add info about register file aliasing
...
llvm-svn: 5074
2002-12-16 15:55:25 +00:00
855b784523
Add information about register file aliasing
...
llvm-svn: 5073
2002-12-16 15:54:59 +00:00
e5bbc24516
Add call clobber info
...
llvm-svn: 5072
2002-12-16 15:54:42 +00:00
0b9f0b5faf
Rename createSimpleX86RegisterAllocator to createSimpleRegisterAllocator
...
llvm-svn: 5071
2002-12-16 14:38:13 +00:00
6ebe959530
brg
...
Fix some bugs in use of MBB vs. BB and iterators that are invalidated before
we use them.
Reference targetClass by enum name, not by number.
llvm-svn: 5069
2002-12-16 04:23:29 +00:00
3c1b59ca59
Correct the setting of Def flags on registers that are modified!
...
llvm-svn: 5065
2002-12-15 22:38:47 +00:00
d06650ade1
Give passes nice names!
...
llvm-svn: 5059
2002-12-15 21:13:40 +00:00
e2533336f5
Simplify interfaces used by regalloc to insert code
...
llvm-svn: 5052
2002-12-15 20:06:35 +00:00
094fd5e758
Changes to make new TargetRegisterClass interface.
...
llvm-svn: 5050
2002-12-15 19:29:34 +00:00
0d1447d64a
* Simplify TargetRegisterClass implementations
...
* Change regclass iterators to use an extra level of pointers
llvm-svn: 5047
2002-12-15 18:40:36 +00:00
3263e5787f
Add support to cast from a bool type
...
Add support for boolean constants
add getClassB method
llvm-svn: 5034
2002-12-15 08:02:15 +00:00
ce35108606
Use MachineOperand::isFoo methods instead of our own global functions
...
llvm-svn: 5033
2002-12-15 08:01:39 +00:00
c4eb1ed23c
Implement indirect function calls
...
llvm-svn: 5024
2002-12-13 14:13:27 +00:00
ca8eb8af18
Make function code generation printing debug-only.
...
llvm-svn: 5023
2002-12-13 13:16:14 +00:00
a1cf9a7c0a
Fix bork in doMultiply
...
llvm-svn: 5021
2002-12-13 13:07:42 +00:00
f1874b0677
Add sanity checks
...
llvm-svn: 5020
2002-12-13 13:04:04 +00:00
3374ec7c1b
Cleaned up the code: factored out switch/case into a separate function, put
...
constants in an array for quick lookup. Stole the idea from elsewhere in
Jello.
llvm-svn: 5017
2002-12-13 12:00:06 +00:00
d4c5013c04
Insert phi code at top of block
...
llvm-svn: 5015
2002-12-13 11:52:34 +00:00
61edd534b4
lib/Target/X86/InstSelectSimple.cpp:
...
The MachineBasicBlock variable name patrol hereby fines Chris Lattner
one bag of nachos, for shadowing global names while his license to do so
was under suspension.
llvm-svn: 5014
2002-12-13 11:39:18 +00:00
0a37046358
Implement cast bool to X
...
llvm-svn: 5012
2002-12-13 11:31:59 +00:00
85b78b7372
Rename all BMI MachineBasicBlock operands to MBB.
...
Try to mess around with emitGEPOperation's elementSizeReg to make it work,
again.
llvm-svn: 5011
2002-12-13 11:22:48 +00:00
825be9ad5d
Finish up iterator stuph
...
llvm-svn: 5009
2002-12-13 10:50:40 +00:00
121ae7d3a7
Treat longs as ints => pretend they're all 32-bit values and squeeze them into
...
32-bit registers.
llvm-svn: 5008
2002-12-13 10:43:09 +00:00
e189edf272
Code gen phi's correctly
...
llvm-svn: 5004
2002-12-13 10:09:43 +00:00
2889d2e50c
Print X86 PHI nodes in a sane manner
...
llvm-svn: 5003
2002-12-13 09:59:26 +00:00
78401cbb3c
Added moveReg2Reg() and moveImm2Reg() to accomodate moving data around due to
...
PHI nodes.
llvm-svn: 5001
2002-12-13 09:54:12 +00:00
eaeacc5872
lib/Target/X86/InstSelectSimple.cpp: Start counting arguments with 2,
...
because arguments start two stack slots off of EBP. Break out of the
for loop once the argument is found. Increment the counter at the end
of the loop instead of the beginning. Use addRegOffset and compute
the scale * index part at compile time instead of using the fancy
load instruction. Just because an instruction set has wacky addressing
modes doesn't mean we ought to use them (at least, if you believe Dave
Patterson).
lib/Target/X86/X86InstrBuilder.h: Add some comments.
test/Regression/Jello/test-loadstore.ll: Let main return int 0.
llvm-svn: 4999
2002-12-13 09:28:50 +00:00
44876fdee4
InstSelectSimple.cpp: Give promote32 a comment. Add initial
...
implementation of getReg() for arguments.
MachineCodeEmitter.cpp: Fix using EBP with index, scale and no
displacement (whew!) due to Chris.
Printer.cpp: Fix printing out index and scale in memory references.
llvm-svn: 4998
2002-12-13 07:56:18 +00:00
179519bf77
Implement getelementptr constant exprs
...
Implement ConstantPointerRefs
Treat long/ulongs as if they were integers. A hack, but an effective one
llvm-svn: 4995
2002-12-13 06:56:29 +00:00
4e2c30d894
brg
...
InstSelectSimple.cpp: Add stub implementation of visitFreeInst.
Add comments that mention how we are failing to implement malloc/free.
Add initial implementation of visitAllocaInst.
X86TargetMachine.cpp: Include llvm/Transforms/Scalar.h.
Add LowerAllocations pass before instruction selection.
jello/Makefile: Add scalaropts.a.
llvm-svn: 4994
2002-12-13 06:46:31 +00:00
e791322602
Emit the right form of mod/rm mod field
...
llvm-svn: 4986
2002-12-13 05:05:05 +00:00
e600a4ebe8
Nicify a bit
...
llvm-svn: 4985
2002-12-13 05:04:37 +00:00
82f1580ee8
Fix encoding of CBW instruction
...
llvm-svn: 4983
2002-12-13 04:41:31 +00:00
862f3ef8bc
Moves now select correct opcode based on the data size.
...
llvm-svn: 4981
2002-12-13 04:24:53 +00:00
1176170c16
Remove extranous #include
...
llvm-svn: 4980
2002-12-13 04:12:24 +00:00
Chris Lattner