ea4f498395
* Broke up SparcV9.td into separate files as it was getting unmanageable
...
* Added some Format 4 classes, but not instructions
* Added notes on missing sections with FIXMEs
* Added RDCCR instr
llvm-svn: 6388
2003-05-29 03:31:43 +00:00
fded35952a
Fixed ordering of elements in instructions: although the binary instructions
...
list (rd, rs1, imm), in that order (bit-wise), the actual assembly syntax is
instr rd, imm, rs1, and that is how they are constructed in the instruction
selector. This fixes the discrepancy.
Also fixed some comments along the same lines and fixed page numbers referring
to where instructions are described in the Sparc manual.
llvm-svn: 6384
2003-05-28 17:49:29 +00:00
2c35144ce5
Add dependency to make TableGen rule fire.
...
llvm-svn: 6383
2003-05-28 17:41:09 +00:00
07b60f8e2e
Fixed an error preventing compilation.
...
llvm-svn: 6381
2003-05-27 22:48:28 +00:00
481dfdb523
Added the 'r' and 'i' annotations to instructions as their opcode names have
...
changed.
llvm-svn: 6380
2003-05-27 22:44:44 +00:00
7975661a8e
Keep track of the current BasicBlock being processed so that a referencing
...
MachineInstr can later be patched up correctly.
llvm-svn: 6378
2003-05-27 22:41:44 +00:00
af96d39c04
Added 'r' and 'i' annotations to instructions as SparcInstr.def has changed.
...
llvm-svn: 6377
2003-05-27 22:40:34 +00:00
96ce62a105
Added 'r' or 'i' annotations to instructions, as SparcInstr.def has changed.
...
Non-obvious change: since I have changed ST and STD to be STF and STDF to
(a) closer resemble their name (NOT assembly text) in the Sparc manual, and
(b) clearly specify that they they are floating-point opcodes,
I made the same changes in this file.
llvm-svn: 6376
2003-05-27 22:39:01 +00:00
da83883ef1
Added 'r' or 'i' annotations to instructions, as SparcInstr.def has changed.
...
Here I had to make one non-trivial change: add a function to get a version of
the opcode that takes an immediate, given an opcode that takes all registers.
This is required because sometimes it is not known at construction time which
opcode is used because opcodes are passed around between functions.
llvm-svn: 6375
2003-05-27 22:37:00 +00:00
8bde6a688c
Added 'r' or 'i' annotations to instructions, as SparcInstr.def has changed.
...
llvm-svn: 6373
2003-05-27 22:35:43 +00:00
cb801a6884
Added entries for each of the instructions with annotations ('r' or 'i').
...
llvm-svn: 6372
2003-05-27 22:33:39 +00:00
db69bebc89
One of the first major changes to make the work of JITting easier: adding
...
annotations on instructions to specify which format they are (i.e., do they take
2 registers and 1 immediate or just 3 registers) as that changes their binary
representation and hence, code emission.
This makes instructions more like how X86 defines them to be. Now, writers of
instruction selection must choose the correct opcode based on what instruction
type they are building, which they already know. Thus, the JIT doesn't have to
do the same work by `discovering' which operands an instruction really has.
As this involves lots of small changes to a lot of files in lib/target/Sparc,
I'll commit them individually because otherwise the diffs will be unreadable.
llvm-svn: 6371
2003-05-27 22:32:38 +00:00
8110439ff6
* Allow passing in an unsigned configuration to allocateSparcTargetMachine()
...
a default value is set in the header file.
* Fixed some code layout to make it more consistent with the rest of codebase
* Added addPassesToJITCompile() with relevant passes
llvm-svn: 6369
2003-05-27 22:24:48 +00:00
8b28140662
Moved generation of the SparcV9CodeEmitter.inc file higher in the Makefile so
...
that Makefile.common would see it.
llvm-svn: 6367
2003-05-27 22:04:38 +00:00
5641434438
Add prototypes to add passes to JIT compilation and code emission.
...
Also, added annotations to how instructions are modified (reg/imm operands).
Added prototype for adding register numbers to values pass for interfacing with
the target-independent register allocators in the JIT.
llvm-svn: 6366
2003-05-27 22:01:10 +00:00
e195b7c0fc
Broke out class definition from SparcV9CodeEmitter, and added ability to take a
...
MachineCodeEmitter to make a pass-through debugger -- output to memory and to
std::cerr.
llvm-svn: 6363
2003-05-27 21:45:05 +00:00
3e9272fb29
SparcV9CodeEmitter.cpp is a part of the Sparc code emitter. The main function
...
that assembles instructions is generated via TableGen (and hence must be built
before building this directory, but that's already the case in the top-level
Makefile).
Also added is .cvsignore to ignore the generated file `SparcV9CodeEmitter.inc',
which is included by SparcV9CodeEmitter.cpp .
llvm-svn: 6357
2003-05-27 20:07:58 +00:00
d452b60678
Added definitions for a bunch of floating-point instructions.
...
llvm-svn: 6356
2003-05-27 20:03:29 +00:00
631006ba48
Renamed opIsDef to opIsDefOnly.
...
llvm-svn: 6340
2003-05-27 00:03:17 +00:00
8adb9944aa
Added special register class containing (for now) %fsr.
...
Fixed spilling of %fcc[0-3] which are part of %fsr.
Moved some machine-independent reg-class code to class TargetRegInfo
from SparcReg{Class,}Info.
llvm-svn: 6339
2003-05-27 00:02:22 +00:00
3ee4e2a3c1
Bug fix: right shift for int divide-by-power-of-2 was incorrect for
...
negative values. Need to add one to a negative value before right shift!
llvm-svn: 6334
2003-05-25 21:59:47 +00:00
5f36d741db
Bug fix: padding bytes within a structure should go after each field!
...
llvm-svn: 6333
2003-05-25 21:59:09 +00:00
5b941461b1
Bug fix: sign-extension was not happening for C = -MININT since C == -C!
...
llvm-svn: 6332
2003-05-25 21:58:11 +00:00
c9a0a1d728
Add support for compiling varargs functions.
...
llvm-svn: 6325
2003-05-25 15:59:47 +00:00
e2402c65d0
Reword to remove reference to how things worked in the past.
...
llvm-svn: 6323
2003-05-24 01:08:43 +00:00
d21a02ad58
Implement the TargetInstrInfo's createNOPinstr() and isNOPinstr() interface.
...
llvm-svn: 6320
2003-05-24 00:09:50 +00:00
39968bbc46
Cleaned up code layout; no functional changes.
...
llvm-svn: 6312
2003-05-23 19:20:57 +00:00
c42dc745db
Fixed `volatile' typo.
...
llvm-svn: 6266
2003-05-21 19:34:28 +00:00
f865cc44ab
Cleaned up code layout, spacing, etc. for readability purposes and to be more
...
consistent with the style of LLVM's code base (and itself! it's inconsistent in
some places.)
No functional changes were made.
llvm-svn: 6265
2003-05-21 18:48:06 +00:00
6532e427b4
* Fix divide by zero error with empty structs
...
* Empty structs should have ALIGNMENT 1, not SIZE 1.
llvm-svn: 6263
2003-05-21 18:08:44 +00:00
2a651d7a0e
Cleaned up code layout, spacing, etc. for readability purposes and to be more
...
consistent with the style of LLVM's code base (and itself! it's inconsistent in
some places.)
No functional changes were made.
llvm-svn: 6262
2003-05-21 18:05:35 +00:00
352f7ac072
Namespacified `vector' and `cerr' to always use the `std::' namespace.
...
Eliminated `using' directives.
llvm-svn: 6261
2003-05-21 17:59:06 +00:00
56f4fa10fd
Sparc instruction opcodes now all live under the `V9' namespace.
...
llvm-svn: 6249
2003-05-20 20:32:24 +00:00
9c105cd27f
Clean up #includes
...
llvm-svn: 6173
2003-05-13 20:21:19 +00:00
3fa7b77ddf
Make abort more explicit
...
llvm-svn: 6151
2003-05-12 21:16:26 +00:00
d4e5409f35
Remove the assertion failure of course... doh
...
llvm-svn: 6150
2003-05-12 20:39:39 +00:00
5069283493
Implement casts from unsigned integers to floating point
...
llvm-svn: 6148
2003-05-12 20:36:13 +00:00
6c906adb73
Make error messages more useful than jsut an abort
...
llvm-svn: 6146
2003-05-12 20:16:58 +00:00
b1eee00034
Remove wierd printout
...
llvm-svn: 6145
2003-05-12 20:10:12 +00:00
786bd8849a
Do not insert multiple initializations for the same value in a PHI node
...
llvm-svn: 6113
2003-05-12 14:22:21 +00:00
74b65ee219
This blank line has GOT to go.
...
llvm-svn: 6057
2003-05-09 03:28:13 +00:00
93c8eddd75
Add support for Add, Sub, And, Or, & Xor constant exprs
...
llvm-svn: 6049
2003-05-08 20:49:25 +00:00
b257aab658
Add support for variable argument functions!
...
llvm-svn: 6046
2003-05-08 19:44:13 +00:00
25e907dae4
Added the initial version of the TableGen description for the Sparc backend.
...
llvm-svn: 6021
2003-05-07 21:52:39 +00:00
d964c3b9fd
IMPLICIT_DEF was not the beautiful elegant solution I thought it was going
...
to be. In fact, it made stuff worse. :(
llvm-svn: 6013
2003-05-07 19:21:28 +00:00
37ffac92d5
Emit pseudo instructions to indicate that some registers are live on entrance
...
and exit of the function. This fixes bug: Jello/2003-05-06-LivenessClobber.llx
and the Fhourstones benchmark
llvm-svn: 6010
2003-05-06 21:32:22 +00:00
4b1e02df8f
Don't have a cow with new pseudo instructions
...
llvm-svn: 6009
2003-05-06 21:31:47 +00:00
8788d6e122
Add two new pseudo instructions
...
llvm-svn: 6008
2003-05-06 21:31:31 +00:00
effa5ba1ac
The Hyphenation-Adding Committee is now in session.
...
llvm-svn: 5986
2003-05-03 02:18:17 +00:00
3ed86610cd
Eliminate use of NonCopyable so that doxygen documentation doesn't link
...
the Annotation classes with the noncopyable classes for no reason
llvm-svn: 5973
2003-05-01 20:28:45 +00:00
4f6cdbdf81
Remove two fields from TargetData which are target specific.
...
llvm-svn: 5963
2003-04-26 20:11:09 +00:00
25900cf220
The promotion rules are the same for all targets, they are set by the C standard.
...
llvm-svn: 5962
2003-04-26 19:47:36 +00:00
21d4509d76
IntegerRegSize is always 8 for sparc
...
llvm-svn: 5961
2003-04-26 19:44:35 +00:00
2a2338f1ba
Fix bogus assert
...
llvm-svn: 5949
2003-04-25 21:58:54 +00:00
b05f851d59
Whoops, 32 bit targets have _4_ byte pointers, not _32_ byte pointers!
...
llvm-svn: 5937
2003-04-25 06:06:43 +00:00
afdf01ef62
Fix compatibility bug: X86 aligns doubles to 4 bytes, not 8!
...
llvm-svn: 5935
2003-04-25 06:05:57 +00:00
efbae9cff1
Fix obvious type-o
...
llvm-svn: 5932
2003-04-25 05:23:10 +00:00
e483398516
Allow for easy detection of when a "default" TargetData is created by the
...
passmanager, which is never the right thing to do.
llvm-svn: 5922
2003-04-25 02:50:45 +00:00
42516baf76
add a new targetdata ctor to create a target data appropriate to the module
...
llvm-svn: 5903
2003-04-24 19:09:05 +00:00
13cafd041a
Trivial cleanup
...
llvm-svn: 5899
2003-04-24 18:35:51 +00:00
ec6f16eae6
Fix iterator invalidation problem with cast instructions
...
llvm-svn: 5876
2003-04-23 17:57:48 +00:00
2670371c9a
Implement the constantexpr CAST instruction correctly
...
llvm-svn: 5875
2003-04-23 17:22:12 +00:00
524608ab79
Add support for the Switch instruction by running the lowerSwitch pass first
...
llvm-svn: 5867
2003-04-23 16:24:55 +00:00
dd4745241f
It's "necessary"...
...
llvm-svn: 5848
2003-04-22 20:20:11 +00:00
e569e992d8
It's "necessary" to spell "necessarily" correctly.
...
llvm-svn: 5833
2003-04-22 17:54:23 +00:00
5b348718df
Add support for a simple constantexpr: cast of one ptr type to another
...
llvm-svn: 5829
2003-04-21 21:33:44 +00:00
379a8d2d1c
Add new linkage types to support a real frontend
...
llvm-svn: 5786
2003-04-16 20:28:45 +00:00
30f40d94cc
Rename -no-* to -disable-*
...
llvm-svn: 5642
2003-02-26 20:00:41 +00:00
ae1f73b4f5
Remove wierd case that can never happen
...
llvm-svn: 5623
2003-02-25 20:27:09 +00:00
76e9f774dd
Don't emit unneccesary branch instructions!
...
llvm-svn: 5328
2003-01-16 18:07:23 +00:00
4769c1bef8
Fix problem with invalidated iterator
...
llvm-svn: 5327
2003-01-16 18:07:13 +00:00
2f983fcce3
Implement optimization folding setcc into branch.
...
llvm-svn: 5324
2003-01-16 16:43:00 +00:00
8c59d64041
Add more flavors of branch instructions
...
llvm-svn: 5323
2003-01-16 16:42:45 +00:00
b2809dc6b5
Implement code to keep the stack pointer aligned to an 8 byte boundary.
...
This improves the performance of the power benchmark by a few percent.
This will be neccesary for SSE code, which requires 16 byte alignment of
the stack.
llvm-svn: 5320
2003-01-16 02:20:12 +00:00
9e75444c8b
Handle frame offset due to return address pushed on the stack
...
llvm-svn: 5319
2003-01-15 22:57:35 +00:00
dea36ca100
Move sparc specific code into the Sparc backend
...
llvm-svn: 5317
2003-01-15 21:36:50 +00:00
4f596d7a2c
Fix warnings
...
llvm-svn: 5316
2003-01-15 21:36:30 +00:00
f9fd59148c
Adjust to simpler interfaces
...
Eliminate dependency on RegClass.h
llvm-svn: 5315
2003-01-15 21:14:32 +00:00
a23969b669
#include RegClass.h explicitly
...
llvm-svn: 5307
2003-01-15 19:57:07 +00:00
90fc665489
Move private header to private directory
...
llvm-svn: 5305
2003-01-15 19:50:44 +00:00
d840ccd2e0
Prune #includes
...
llvm-svn: 5303
2003-01-15 19:48:13 +00:00
e58cd301cd
Use BuildMI more
...
llvm-svn: 5299
2003-01-15 19:23:34 +00:00
8145abb99e
Fix bug found by regtests
...
llvm-svn: 5294
2003-01-15 18:11:11 +00:00
1ebaa90f48
Use BuildMI more, Create*Instruction less
...
llvm-svn: 5291
2003-01-15 17:47:49 +00:00
33be2a23ee
X86 backend should never use addMReg
...
llvm-svn: 5288
2003-01-15 00:04:14 +00:00
71aa7afc27
* Elimiante a bunch of functions from InstrSelectionSupport.h, replacing users
...
of them with BUildMI calls instead.
* Fix def information in instructions generated by prologepilog inserter
llvm-svn: 5287
2003-01-15 00:03:28 +00:00
24c1d5e551
Rename llvm/Analysis/LiveVar/FunctionLiveVarInfo.h -> llvm/CodeGen/FunctionLiveVarInfo.h
...
llvm-svn: 5284
2003-01-14 23:05:08 +00:00
b4d58d7f9e
Rename MachineInstrInfo -> TargetInstrInfo
...
llvm-svn: 5272
2003-01-14 22:00:31 +00:00
c49ca9ce58
Minor cleanups
...
llvm-svn: 5266
2003-01-14 20:32:10 +00:00
cf53bcf8e4
New files
...
llvm-svn: 5260
2003-01-13 01:01:59 +00:00
962d5befb3
* No longer need lowerallocation pass
...
* Add X86 Stackifier pass
* Add peephole optimizer pass
llvm-svn: 5233
2003-01-13 00:51:23 +00:00
c39dc9e648
rename FP -> fp*
...
llvm-svn: 5232
2003-01-13 00:50:46 +00:00
06e07162fc
* Move frame and constant pool indexes to first argument of memory reference
...
so we can put an offset in there as well...
* Fix long/ulong stuff
llvm-svn: 5231
2003-01-13 00:50:33 +00:00
9fe3518dc0
* Some instructions take 64 bit integers, add an Arg type for it
...
* Add flags for different types of FP pseudo instrs
llvm-svn: 5230
2003-01-13 00:49:24 +00:00
5cc425a8e1
* Function calls clobber fp registers
...
* Use new M_TERMINATOR_FLAG flag
* Add ::Void flag on several instructions so def-use info is correct!
* Implement MANY FP instructions
* Finalize pseudo FP instructions
* Add set of Pseudo FP instruction description flags
* Add support for MOVim instrs
* Add support for 64 bit support instrs, like adc sbb, etc
* Add conditional move
llvm-svn: 5229
2003-01-13 00:48:46 +00:00
7878563ff9
Add support for frame and constant pool references
...
llvm-svn: 5228
2003-01-13 00:45:53 +00:00
61e1195e89
Move passes out to Passes.h
...
llvm-svn: 5227
2003-01-13 00:45:29 +00:00
888a8084b6
Add speculation
...
llvm-svn: 5226
2003-01-13 00:35:08 +00:00
956e8379f9
* Implement rudimentary output of the constant pool
...
* Implement support for MRMS?m instructions
* Add Arg64 support
* Add support for frame indexes and constant pool indexes
*
llvm-svn: 5225
2003-01-13 00:35:03 +00:00
d4ba62218e
* Add support for FP registers ST*
...
* Add support for the constant pool & constant pool indices
* Add support for MRMS?m instructions
* Fix FP Prefix emission
* Add support for global addresses and external symbols
llvm-svn: 5224
2003-01-13 00:33:59 +00:00
6c0daf795a
* Adjust to use new interfaces, eliminating CurReg stuff
...
* Support arbitrary FP constants
* Fix bugs in frame layout for function calls and incoming arguments
* Insert copies for constant arguments to PHI nodes into the BOTTOM of
predecessor blocks, not the top.
* Implement _floating point_ support: setcc, return, load, store, cast
* Fix several bugs in the cast instruction
* Abstract out call emission and load/store for FP
* Implement malloc/free without previous lowering pass.
* Make use of new forms of MachineOperand
* Implement _long_ support!
* Fix many bugs in FP support
* Change branch from je/jne to je/jmp
* Simplify code generated for GEP instructions
llvm-svn: 5223
2003-01-13 00:32:26 +00:00
0d5644bb6d
Start renaming MachineInstrInfo -> TargetInstrInfo
...
llvm-svn: 5221
2003-01-13 00:26:36 +00:00
f9781b59ab
More renamings of Target/Machine*Info to Target/Target*Info
...
llvm-svn: 5204
2002-12-29 03:13:05 +00:00
42d59219c7
Rename MachineOptInfo to TargetoptInfo
...
Rename MachineCacheInfo to TargetCacheInfo
llvm-svn: 5203
2002-12-29 02:50:35 +00:00
83d835da2a
Rename MachineOptInfo to TargetoptInfo
...
Rename MachineCacheInfo to TargetCacheInfo
llvm-svn: 5202
2002-12-29 02:50:33 +00:00
26c23467c5
Rename FunctionFrameInfo to MachineFrameInfo
...
llvm-svn: 5201
2002-12-28 21:08:28 +00:00
871e591e34
Rename MachineFrameInfo to TargetFrameInfo.h
...
llvm-svn: 5199
2002-12-28 21:00:25 +00:00
2ca5e23403
Put class in anonymous namespace
...
llvm-svn: 5197
2002-12-28 20:42:56 +00:00
0ccedc254c
Eliminate unneccesary file
...
llvm-svn: 5191
2002-12-28 20:34:47 +00:00
d2577010d5
Capture more information in ctor
...
llvm-svn: 5190
2002-12-28 20:34:18 +00:00
362b26c37e
Implement the TargetFrameInfo interface
...
llvm-svn: 5189
2002-12-28 20:33:52 +00:00
9a81e69439
* Initialize new FrameInfo member
...
* most pass ctors no longer take TM arguments
* New prolog/epilog insertion pass
llvm-svn: 5188
2002-12-28 20:33:32 +00:00
e6fb194716
Changes to match new MRegisterInfo api
...
llvm-svn: 5187
2002-12-28 20:32:54 +00:00
1d79b4ce86
*** Implement frame pointer elimination on X86!
...
* Include contents of X86RegisterClasses.cpp into here
* Adjustments to register api to work with new frame manager
* Eliminate moveImm2Reg, getFramePointer, and getStackPointer
* Cleanup and simplify prolog/epilog code generation
* Prolog/epilog are MUCH more efficient now.
llvm-svn: 5186
2002-12-28 20:32:28 +00:00
9a9739e517
Contents merged with X86RegisterInfo.cpp
...
llvm-svn: 5185
2002-12-28 20:30:15 +00:00
59a20d7b6d
* Remove implementations of previously pure virtual functions that are not any longer.
...
llvm-svn: 5184
2002-12-28 20:29:41 +00:00
365ede3748
* Minor reformatting
...
* Remove some size suffixes [bwl]
* Add new ADJCALLSTACKDOWN & ADJCALLSTACKUP pseudo instrs
* Call instructions are M_CALL not M_BRANCH!
* Disable push and pop instructions
* Add new ANDri32 instr
llvm-svn: 5183
2002-12-28 20:29:14 +00:00
ef5a8f912c
New addFrameReference function
...
llvm-svn: 5182
2002-12-28 20:26:58 +00:00
4937643df9
* Most pass ctor functions don't take TM arguments anymore
...
* New createPrologEpilogCodeInserter() function
llvm-svn: 5181
2002-12-28 20:26:16 +00:00
1520c5ab2a
* Convert to a MachineFunctionPass
...
* Don't take a TM as a ctor parameter
* Print [X - Y] instead of [X + -Y] when possible
llvm-svn: 5180
2002-12-28 20:25:38 +00:00
d24f633394
* Convert to a MachineFunctionPass
...
* ctor doesn't take TM argument
* handle direct ESP references correctly!
llvm-svn: 5179
2002-12-28 20:24:48 +00:00
51553e0700
* Use the new Abstract Frame Manager to handle incoming arguments and
...
fixed size allocas
* Revamp call emission to work with new frame manager
llvm-svn: 5178
2002-12-28 20:24:02 +00:00
d47aac9d4b
* Rename machineFrameInfo to targetFrameInfo
...
* Constant pool and frame info is no longer directly in MachineFunction
llvm-svn: 5177
2002-12-28 20:21:29 +00:00
fe9b705bed
* Rename MachineFrameInfo to TargetFrameInfo
...
* Move some sparc specific code here from Target files
llvm-svn: 5176
2002-12-28 20:20:24 +00:00
b9feac398f
* TargetData is no longer directly accessable from TM
...
* s/unsigned int/unsigned/
llvm-svn: 5175
2002-12-28 20:19:44 +00:00
a41b89a829
* TargetData is no longer directly accessable from TargetMachine
...
* Constpool & frame info is no longer directly in MachineFunction
llvm-svn: 5174
2002-12-28 20:18:21 +00:00
525e3af36c
* Frame & const pool info is no longer directly in MachineFunction
...
llvm-svn: 5173
2002-12-28 20:17:43 +00:00
d2a67df791
* Changes to be a MachineFunctionPass
...
* Frame information is now stuck in MachineFunctionInfo instead of directly
in MachineFunction.
* Don't require a TM as an argument to the ctor
llvm-svn: 5172
2002-12-28 20:16:08 +00:00
4d84d49f75
* Don't access TargetData directly
...
* Changes because frame info is not in MachineFunction directly anymore
llvm-svn: 5171
2002-12-28 20:15:01 +00:00
a76f456a60
* Simplify Value classes
...
* Add initial support for FP constants
* Add initial FP support for several instructions
llvm-svn: 5154
2002-12-25 05:13:53 +00:00
6ecc6a72c9
* Use new pseudo instr form for instructions
...
* Mark CALLpcrel as a RawFrm instruction as required
* Eliminate invalid BSWAP16 instruction
* Add xchg instructions
* Add initial support for FP instructions
llvm-svn: 5153
2002-12-25 05:11:46 +00:00
e98ca19112
Add FP instr prefix byte support
...
Add Pseudo instr class
llvm-svn: 5152
2002-12-25 05:09:59 +00:00
36703cd02a
Add support for FP prefixes
...
llvm-svn: 5151
2002-12-25 05:09:21 +00:00
7c10f4f5d4
Add printer support for Pseudo instructions
...
llvm-svn: 5150
2002-12-25 05:09:01 +00:00
c9f3bbb5d2
Initial support for FP registers
...
llvm-svn: 5149
2002-12-25 05:08:03 +00:00
dafa31658f
New simpler spill interface
...
llvm-svn: 5148
2002-12-25 05:07:09 +00:00
4997a840bc
Adjustments to match new simpler spill interface
...
llvm-svn: 5147
2002-12-25 05:06:43 +00:00
55aaff5590
Free machine code
...
llvm-svn: 5146
2002-12-25 05:06:21 +00:00
a32b4055be
Changes to allow for a configurable target machine that allows big endian and/or long pointer operation
...
llvm-svn: 5131
2002-12-24 00:04:01 +00:00
cfcd0603d0
Changes to compile with GCC 2.96
...
Changes to support configurable pointer size and endianness
llvm-svn: 5130
2002-12-24 00:03:11 +00:00
ccc2c7e8a7
Sparc is not little endian
...
llvm-svn: 5129
2002-12-24 00:02:38 +00:00
d8201972bf
Fix compilation on gcc 2.96
...
llvm-svn: 5116
2002-12-23 23:46:55 +00:00
871abd8187
Add definition for the bswap instruction
...
*** FIX: the encoding of the SUB instruction
llvm-svn: 5115
2002-12-23 23:46:31 +00:00
e218f7924c
Add support for the bswap instruction
...
llvm-svn: 5114
2002-12-23 23:46:00 +00:00
6e7c821dc0
Fix warning
...
llvm-svn: 5109
2002-12-20 04:13:28 +00:00
5526b21e93
CBW doesn't modify AL
...
llvm-svn: 5108
2002-12-20 04:13:11 +00:00
67e555d1ec
fix warning
...
llvm-svn: 5107
2002-12-20 04:12:48 +00:00
b437b7de1a
Don't force setCC instructions into AL
...
llvm-svn: 5104
2002-12-18 01:44:31 +00:00
b54343a64f
Add comments, switch uses/defs to match InstrInfo.def file
...
llvm-svn: 5102
2002-12-18 01:05:54 +00:00
fc9af85395
Add reg clobber list for direct calls
...
Represent empty use/def list as a null pointer
llvm-svn: 5101
2002-12-18 01:05:31 +00:00
4cb8af96b3
Update to use new interface for register info
...
llvm-svn: 5098
2002-12-17 04:19:17 +00:00
0eece84186
New file
...
llvm-svn: 5097
2002-12-17 04:03:08 +00:00
eaf58b03b2
Round number of bytes allocated on the stack up to a multiple of 4 so that the
...
stack remains aligned
llvm-svn: 5095
2002-12-17 03:15:26 +00:00
d9c6f2a6d3
Local register allocator is now stable enough for use, it passes all tests
...
llvm-svn: 5094
2002-12-17 02:51:15 +00:00
5afbc4c387
Register allocator is responsible for spilling callee saved regs
...
llvm-svn: 5092
2002-12-17 02:48:57 +00:00
2e6f17f136
Build add instructions of the correct form!
...
llvm-svn: 5090
2002-12-16 23:36:57 +00:00
e92fb346d3
Two fixes:
...
* Only load incoming arguments into virtual registers once at the
beginning of the function
* Assign different virtual registers to each reference to constants/globals
llvm-svn: 5088
2002-12-16 22:54:46 +00:00
c87fcde854
Fix prolog/epilog in the presence of alloca
...
llvm-svn: 5087
2002-12-16 22:29:30 +00:00
e92f1bb011
Make sure stack manipulation refers to ESP the right number of times
...
llvm-svn: 5086
2002-12-16 22:29:06 +00:00
5c59014a1b
Add some special cases to make common getelementptr cases easier to read/faster
...
llvm-svn: 5084
2002-12-16 19:32:50 +00:00
6b5ca53493
Finish implementation of alias list impl
...
llvm-svn: 5083
2002-12-16 19:31:48 +00:00
e0c25aaf99
Add mechanism to select register allocator to use
...
llvm-svn: 5079
2002-12-16 16:15:51 +00:00
d44d25323d
Try #2 to get alias set stuff to work
...
llvm-svn: 5077
2002-12-16 16:14:51 +00:00
9b83781030
Add comments
...
llvm-svn: 5076
2002-12-16 15:57:44 +00:00
36d6f4a303
Add info about register aliases, add prototype for createLocalRegisterAllocator
...
llvm-svn: 5075
2002-12-16 15:55:51 +00:00
4cf76c23e8
Add info about register file aliasing
...
llvm-svn: 5074
2002-12-16 15:55:25 +00:00
855b784523
Add information about register file aliasing
...
llvm-svn: 5073
2002-12-16 15:54:59 +00:00
e5bbc24516
Add call clobber info
...
llvm-svn: 5072
2002-12-16 15:54:42 +00:00
0b9f0b5faf
Rename createSimpleX86RegisterAllocator to createSimpleRegisterAllocator
...
llvm-svn: 5071
2002-12-16 14:38:13 +00:00
6ebe959530
brg
...
Fix some bugs in use of MBB vs. BB and iterators that are invalidated before
we use them.
Reference targetClass by enum name, not by number.
llvm-svn: 5069
2002-12-16 04:23:29 +00:00
3c1b59ca59
Correct the setting of Def flags on registers that are modified!
...
llvm-svn: 5065
2002-12-15 22:38:47 +00:00
d06650ade1
Give passes nice names!
...
llvm-svn: 5059
2002-12-15 21:13:40 +00:00
e2533336f5
Simplify interfaces used by regalloc to insert code
...
llvm-svn: 5052
2002-12-15 20:06:35 +00:00
094fd5e758
Changes to make new TargetRegisterClass interface.
...
llvm-svn: 5050
2002-12-15 19:29:34 +00:00
0d1447d64a
* Simplify TargetRegisterClass implementations
...
* Change regclass iterators to use an extra level of pointers
llvm-svn: 5047
2002-12-15 18:40:36 +00:00
3263e5787f
Add support to cast from a bool type
...
Add support for boolean constants
add getClassB method
llvm-svn: 5034
2002-12-15 08:02:15 +00:00
ce35108606
Use MachineOperand::isFoo methods instead of our own global functions
...
llvm-svn: 5033
2002-12-15 08:01:39 +00:00
c4eb1ed23c
Implement indirect function calls
...
llvm-svn: 5024
2002-12-13 14:13:27 +00:00
ca8eb8af18
Make function code generation printing debug-only.
...
llvm-svn: 5023
2002-12-13 13:16:14 +00:00
a1cf9a7c0a
Fix bork in doMultiply
...
llvm-svn: 5021
2002-12-13 13:07:42 +00:00
f1874b0677
Add sanity checks
...
llvm-svn: 5020
2002-12-13 13:04:04 +00:00
3374ec7c1b
Cleaned up the code: factored out switch/case into a separate function, put
...
constants in an array for quick lookup. Stole the idea from elsewhere in
Jello.
llvm-svn: 5017
2002-12-13 12:00:06 +00:00
d4c5013c04
Insert phi code at top of block
...
llvm-svn: 5015
2002-12-13 11:52:34 +00:00
61edd534b4
lib/Target/X86/InstSelectSimple.cpp:
...
The MachineBasicBlock variable name patrol hereby fines Chris Lattner
one bag of nachos, for shadowing global names while his license to do so
was under suspension.
llvm-svn: 5014
2002-12-13 11:39:18 +00:00
0a37046358
Implement cast bool to X
...
llvm-svn: 5012
2002-12-13 11:31:59 +00:00
85b78b7372
Rename all BMI MachineBasicBlock operands to MBB.
...
Try to mess around with emitGEPOperation's elementSizeReg to make it work,
again.
llvm-svn: 5011
2002-12-13 11:22:48 +00:00
825be9ad5d
Finish up iterator stuph
...
llvm-svn: 5009
2002-12-13 10:50:40 +00:00
121ae7d3a7
Treat longs as ints => pretend they're all 32-bit values and squeeze them into
...
32-bit registers.
llvm-svn: 5008
2002-12-13 10:43:09 +00:00
e189edf272
Code gen phi's correctly
...
llvm-svn: 5004
2002-12-13 10:09:43 +00:00
2889d2e50c
Print X86 PHI nodes in a sane manner
...
llvm-svn: 5003
2002-12-13 09:59:26 +00:00
78401cbb3c
Added moveReg2Reg() and moveImm2Reg() to accomodate moving data around due to
...
PHI nodes.
llvm-svn: 5001
2002-12-13 09:54:12 +00:00
eaeacc5872
lib/Target/X86/InstSelectSimple.cpp: Start counting arguments with 2,
...
because arguments start two stack slots off of EBP. Break out of the
for loop once the argument is found. Increment the counter at the end
of the loop instead of the beginning. Use addRegOffset and compute
the scale * index part at compile time instead of using the fancy
load instruction. Just because an instruction set has wacky addressing
modes doesn't mean we ought to use them (at least, if you believe Dave
Patterson).
lib/Target/X86/X86InstrBuilder.h: Add some comments.
test/Regression/Jello/test-loadstore.ll: Let main return int 0.
llvm-svn: 4999
2002-12-13 09:28:50 +00:00
44876fdee4
InstSelectSimple.cpp: Give promote32 a comment. Add initial
...
implementation of getReg() for arguments.
MachineCodeEmitter.cpp: Fix using EBP with index, scale and no
displacement (whew!) due to Chris.
Printer.cpp: Fix printing out index and scale in memory references.
llvm-svn: 4998
2002-12-13 07:56:18 +00:00
179519bf77
Implement getelementptr constant exprs
...
Implement ConstantPointerRefs
Treat long/ulongs as if they were integers. A hack, but an effective one
llvm-svn: 4995
2002-12-13 06:56:29 +00:00
4e2c30d894
brg
...
InstSelectSimple.cpp: Add stub implementation of visitFreeInst.
Add comments that mention how we are failing to implement malloc/free.
Add initial implementation of visitAllocaInst.
X86TargetMachine.cpp: Include llvm/Transforms/Scalar.h.
Add LowerAllocations pass before instruction selection.
jello/Makefile: Add scalaropts.a.
llvm-svn: 4994
2002-12-13 06:46:31 +00:00
e791322602
Emit the right form of mod/rm mod field
...
llvm-svn: 4986
2002-12-13 05:05:05 +00:00
e600a4ebe8
Nicify a bit
...
llvm-svn: 4985
2002-12-13 05:04:37 +00:00
82f1580ee8
Fix encoding of CBW instruction
...
llvm-svn: 4983
2002-12-13 04:41:31 +00:00
862f3ef8bc
Moves now select correct opcode based on the data size.
...
llvm-svn: 4981
2002-12-13 04:24:53 +00:00
1176170c16
Remove extranous #include
...
llvm-svn: 4980
2002-12-13 04:12:24 +00:00
ec0bc92146
Rename MemArg* to Arg*
...
llvm-svn: 4979
2002-12-13 03:51:55 +00:00
343e4b1810
Make mem size an assert
...
Add mem size flags to all instructions using an imm
llvm-svn: 4978
2002-12-13 03:50:13 +00:00
2ef75daf78
This is supposed to provide correct size for datatypes. Supposedly.
...
llvm-svn: 4977
2002-12-13 02:13:15 +00:00
7b21678aed
Added the flag to mark instructions which are really 2-address instructions in
...
X86, but would be 3-address in any normail architecture.
llvm-svn: 4974
2002-12-12 23:19:11 +00:00
5e91d38ecb
This checkin is brought to you by the brian gaeke allnighter fund.
...
(lib/Target/X86) InstSelectSimple.cpp:
Include llvm/DerivedTypes.h and iostream.
Refactor visitMul out into a wrapper around doMultiply(), so that we
can do multiplications on temporary values when we are doing
getelementptrs.
Refactor part of getReg out into makeAnotherReg, so that we can create
registers willy-nilly to hold temporary values, when we are doing
getelementptrs.
Add stub implementations of visitMallocInst and visitAllocaInst.
Add initial implementation of visitGetElementPtrInst.
In copyConstantToRegister:
We throw a *lot* of our asserts here. So, when we want to throw an
assert, print out to stderr whatever expr or whatever constant made
us barf.
Support copying ConstantPointerNull to register, using a move immediate
of zero.
Rename FLDr4 and FLDr8 to FLDr32 and FLDr64, so that they match the meanings
of the numbers in the other instruction names. All uses modified.
Teach visitCallInst to extract byte- and short-class return values
from subregs of EAX. Add a FIXME note about how we would do it for
float-class return values.
Add a FIXME note about how we would cast float to int and back.
X86InstrInfo.def:
Rename FLDr4 and FLDr8 to FLDr32 and FLDr64, so that they match the meanings
of the numbers in the other instruction names. All uses modified.
(tools/jello) GlobalVars.cpp:
Include iostream.
If we have to emit a floating-point constant to memory, gamble and use
the same method as for ints.
If we have to emit a ConstantPointerNull to memory, try using a "void *"
and "NULL".
Otherwise, if we are going to throw an assert, print out whatever constant
made us barf, first.
llvm-svn: 4973
2002-12-12 15:33:40 +00:00
9cf5718665
Implement a lot of cast functionality (no FP or 64)
...
llvm-svn: 4944
2002-12-06 10:49:33 +00:00
a4a10fe88b
Target/X86/Printer.cpp: Add sizePtr function, and use it instead of
...
" <SIZE> PTR " string when emitting assembly.
Target/X86/X86InstrInfo.def: Tidy up a bit:
Squashed everything down to 118 chars wide, wrapping lines so that
comment is at the same point on each line. Rename "NoImpRegs" as
"NoIR". (most instructions have NoImpRegs twice on a line, so this
saves 10 columns).
Also, annotate various instructions with flags for size of memory operand.
(MemArg16, MemArg32, MemArg64, etc.)
Target/X86/X86InstrInfo.h: Define flags for size of memory operand.
(MemArg16, MemArg32, MemArg64, etc.)
llvm-svn: 4932
2002-12-05 08:30:40 +00:00
83e62f14dd
Implemented functions for emitting prologues and epilogues;
...
removed EBP from the list of callee-saved registers (it isn't one).
llvm-svn: 4929
2002-12-04 23:57:03 +00:00
ab2ffedb38
Added push and pop instructions.
...
llvm-svn: 4928
2002-12-04 23:56:26 +00:00
e21336000b
Fix handling of function calls that return void
...
llvm-svn: 4925
2002-12-04 23:50:28 +00:00
4859c65d48
Implement initial support for return values from call instructions
...
llvm-svn: 4924
2002-12-04 23:45:28 +00:00
81c7a3a84c
Adjust the stack pointer after a function call, proportional to the number of
...
arguments pushed onto the stack.
llvm-svn: 4922
2002-12-04 19:22:53 +00:00
dfa9cfa67f
Added instructions to add/subtract imm32 to/from a reg32.
...
llvm-svn: 4921
2002-12-04 19:15:22 +00:00
fb8032dc84
Fix bogus assertion failures
...
llvm-svn: 4919
2002-12-04 17:32:52 +00:00
8d79e5c9d9
Avoid bad assertion
...
llvm-svn: 4918
2002-12-04 17:28:40 +00:00
82cc643401
Remove think-o assertion
...
llvm-svn: 4917
2002-12-04 17:18:30 +00:00
ccf17c6564
Avoid crashing on Arguments, just silently miscompile
...
llvm-svn: 4916
2002-12-04 17:15:34 +00:00
1af9bebcda
storeReg2RegOffset() and loadRegOffset2Reg() now take the iterator by value
...
instead of by reference, since they return the modified iterator.
llvm-svn: 4914
2002-12-04 17:14:13 +00:00
0d28502c32
Moved buildReg2RegClassMap() into from X86RegisterInfo to MRegisterInfo, since
...
it is target-independent.
llvm-svn: 4911
2002-12-04 16:47:04 +00:00
7b1ec5ed3a
Add a "Lazy Function Resolution in Jello" section
...
Remove some todo's
llvm-svn: 4910
2002-12-04 16:12:54 +00:00
bc98081090
Fix a bug I introduced in a previous change
...
llvm-svn: 4909
2002-12-04 06:56:56 +00:00
6425a502a6
Add support for referencing global variables/functions
...
llvm-svn: 4907
2002-12-04 06:45:19 +00:00
d9522256d3
Added support for callee- and caller-save registers.
...
llvm-svn: 4897
2002-12-03 23:11:21 +00:00
64261741c7
Fix broken ret opcode, grr...
...
llvm-svn: 4895
2002-12-03 22:50:02 +00:00
645b7548bf
Fix instsel for calls
...
llvm-svn: 4891
2002-12-03 20:30:12 +00:00
6a0874071b
Fix the build
...
llvm-svn: 4884
2002-12-03 18:15:59 +00:00
b676857358
brg
...
Add support for cast ... to bool in visitCastInst (it's a start, anyways...)
llvm-svn: 4883
2002-12-03 07:36:03 +00:00
8052f8006b
Split the machine code emitter completely out of the printer
...
llvm-svn: 4882
2002-12-03 06:34:06 +00:00
0d80874f6c
* Move information about Implicit Defs/Uses into X86InstrInfo.def.
...
* Expose information about implicit defs/uses of register through the
MachineInstrInfo.h file.
llvm-svn: 4877
2002-12-03 05:42:53 +00:00
c6d6d62c8e
Initialize implicit uses/defs fields for sparc backend to empty list
...
llvm-svn: 4876
2002-12-03 05:41:54 +00:00
5485c079d1
brg
...
X86Implicit.cpp, X86Implicit.h: New files.
InstSelectSimple.cpp: Add some clarifications in visitCallInst comments.
llvm-svn: 4874
2002-12-03 00:51:09 +00:00
15fbd61664
More support for machine code emission: raw instructions
...
llvm-svn: 4872
2002-12-02 21:56:18 +00:00
1207ccdbc1
Expose explicit type
...
llvm-svn: 4871
2002-12-02 21:50:41 +00:00
db31bbad6b
Start implementing MachineCodeEmitter
...
llvm-svn: 4870
2002-12-02 21:44:34 +00:00
58743b9f78
Eliminate OtherFrm
...
llvm-svn: 4868
2002-12-02 21:40:58 +00:00
d5823603fa
Remove comment
...
Remove handling of OtherFrm
llvm-svn: 4867
2002-12-02 21:40:46 +00:00
787a9de685
Initial support for machine code emission
...
llvm-svn: 4866
2002-12-02 21:24:12 +00:00
aa15563510
Fix order of operands on a store from reg to [reg+offset].
...
llvm-svn: 4857
2002-12-02 21:10:35 +00:00
08cd1edaa9
Add rawfrm flags
...
llvm-svn: 4841
2002-12-01 23:25:59 +00:00
7dcb1436da
Don't add implicit regs
...
llvm-svn: 4840
2002-12-01 23:24:58 +00:00
2ad3501d3f
brg
...
InstSelectSimple.cpp: Refactor out conversion of byte, short -> int
from visitReturnInst() to new method, promote32().
Use it in both visitReturnInst() and visitCallInst().
llvm-svn: 4839
2002-11-30 11:57:28 +00:00
23953e0f8a
brg
...
InstSelectSimple.cpp: First draft of visitCallInst method, handling
int/float args.
X86InstrInfo.def: Add entries for CALL with 32-bit pc relative arg, and
PUSH with 32-bit reg arg.
llvm-svn: 4838
2002-11-29 12:01:58 +00:00
4ba2cb110a
brg
...
InstSelectSimple.cpp: Add some comments that say what I'm going to do for
calls and casts.
llvm-svn: 4832
2002-11-26 10:43:30 +00:00
5014e38273
Oops. Got the MOVrm and MOVmr mixed up. Fixed. We can now print out
...
instructions correctly.
llvm-svn: 4830
2002-11-22 23:15:27 +00:00
55cf6bfae4
Enable the register allocator pass.
...
llvm-svn: 4829
2002-11-22 22:45:07 +00:00
bde217d7a9
Added methods to read/write values to stack in .h, fixed implementation in
...
.cpp to return the iterator correctly.
llvm-svn: 4827
2002-11-22 22:43:47 +00:00
1a72c637fb
Added -*- C++ -*- mode to the comments.
...
llvm-svn: 4826
2002-11-22 22:42:50 +00:00
4ea94a4be0
Add a simple way to add memory locations of format [reg+offset]
...
llvm-svn: 4825
2002-11-22 22:42:12 +00:00
aa91eae6af
lib/Target/X86/InstSelectSimple.cpp: Add visitCallInst, visitCastInst.
...
llvm-svn: 4821
2002-11-22 11:07:01 +00:00
e5330c4adf
Handle cmp Reg, 0 correctly
...
llvm-svn: 4819
2002-11-21 23:30:00 +00:00
f435afc268
Printing support for more stuff
...
llvm-svn: 4818
2002-11-21 22:49:46 +00:00
174a94007d
Don't add implicit operands
...
llvm-svn: 4817
2002-11-21 22:49:20 +00:00
b35341ee25
Fix off by one bug
...
llvm-svn: 4816
2002-11-21 22:48:15 +00:00
af7bd2c6b5
Add fixme
...
llvm-svn: 4815
2002-11-21 22:48:01 +00:00
1c80d37765
Minor code cleanups
...
llvm-svn: 4814
2002-11-21 21:04:50 +00:00
4fbd8a2f78
Implement printing of store instructions
...
llvm-svn: 4813
2002-11-21 21:03:39 +00:00
61fafd35f5
The big change here is to handle printing/emission of X86II::MRMSrcMem
...
instructions. Right now the only users are load instructions, and Misha's
spill code
llvm-svn: 4812
2002-11-21 20:44:15 +00:00
cf7c225e06
Remove implicit information from instruction selector
...
llvm-svn: 4811
2002-11-21 18:54:29 +00:00
e8885d949a
Add printing information for MUL and DIV
...
llvm-svn: 4810
2002-11-21 18:54:14 +00:00
5e50475adb
Fix a bug that prevented compilation of multiple functions
...
llvm-svn: 4809
2002-11-21 17:26:58 +00:00
7939ecc8eb
Remove opcode information for instructions that are completely defined now
...
llvm-svn: 4805
2002-11-21 17:12:55 +00:00
1f9530508b
Add printing support for sahf & setcc
...
llvm-svn: 4804
2002-11-21 17:10:57 +00:00
c868841ad6
Add printing support for /0 /1 type instructions
...
llvm-svn: 4803
2002-11-21 17:09:01 +00:00
a6eb52fcf7
Add support for /0 /1, etc type instructions
...
llvm-svn: 4802
2002-11-21 17:08:49 +00:00
41e2d4cdcf
Rename the SetCC X86 instructions to reflect the fact that they are the
...
register versions
llvm-svn: 4800
2002-11-21 16:19:42 +00:00
45ddd59da5
Simplify setcc code a bit
...
llvm-svn: 4799
2002-11-21 15:52:38 +00:00
177e928a46
Support Registers of the form (B8+ rd) for example
...
llvm-svn: 4798
2002-11-21 02:00:20 +00:00
3a3ac9d225
Dont' set flags
...
llvm-svn: 4797
2002-11-21 01:59:50 +00:00
6985c19b61
Implement printing more, implement opcode output more
...
llvm-svn: 4796
2002-11-21 01:33:44 +00:00
dfbfd81217
Huge diff do to reindeinting comments.
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Basically just adds OpSize flags for instructions that need them.
llvm-svn: 4795
2002-11-21 01:33:28 +00:00
c48d0fa9a2
Add new prefix flag
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llvm-svn: 4794
2002-11-21 01:32:55 +00:00
f03132f014
Print another class of instructions correctly, giving us: xorl EDX, EDX
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for example.
llvm-svn: 4793
2002-11-21 00:30:01 +00:00
95e6287734
Booleans are types too. And they get stored in bytes. And InstructionSelection
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doesn't assert fail. And everyone's happy. Yay!
llvm-svn: 4792
2002-11-21 00:25:56 +00:00
c4841a7738
X86 target builds fine now
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llvm-svn: 4786
2002-11-20 20:17:03 +00:00
53d2de923a
Add definitions for function headers from MRegisterInfo.h:
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Some functions are in X86RegisterInfo.cpp, others, because of the data they
need, are in X86RegisterClasses.cpp, which also defines some register classes:
byte, short, and int.
llvm-svn: 4784
2002-11-20 18:59:43 +00:00
6e5d493e0f
Check not only for MO_VirtualRegister, but MO_MachineRegister as well when
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printing out assembly. After all, we want the real thing too.
llvm-svn: 4783
2002-11-20 18:56:41 +00:00
55d5f15a40
Don't build X86 target yet
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llvm-svn: 4780
2002-11-20 18:37:37 +00:00
eaaceb1210
Add mapping in MachineFunction from SSA regs to Register Classes. Also,
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uncovered a bug where registers were not being put in a map if they were not
found...
llvm-svn: 4776
2002-11-20 00:58:23 +00:00
ade1143692
Sigh. Fixed some speling.
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llvm-svn: 4775
2002-11-20 00:56:42 +00:00
310afc5f8c
Thanks to the R8, R16, and R32 macros, I can now deal with registers that
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belong to different register classes easier.
llvm-svn: 4773
2002-11-20 00:47:40 +00:00
a648bc6674
Brian Gaeke says:
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lib/Target/X86/InstSelectSimple.cpp: Add a little something to
visitBranchInst which supports conditional branches.
lib/Target/X86/X86InstrInfo.def: Add defs of JNE, JE, CMPri8
llvm-svn: 4755
2002-11-19 09:08:47 +00:00
5812f06b30
Start trying to print instructions more correctly. For now we also print out the opcode for each instruction as well.
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llvm-svn: 4743
2002-11-18 06:56:51 +00:00
cf72e52df3
Expose base opcode
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llvm-svn: 4742
2002-11-18 06:56:24 +00:00
0018e8d5fc
Start to add more information to instr.def
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llvm-svn: 4741
2002-11-18 05:37:11 +00:00
f2e00c62ab
Add instruction annotation about whether it has a 0x0F opcode prefix
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llvm-svn: 4740
2002-11-18 01:59:28 +00:00
c6f7457e90
Add more void flags
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llvm-svn: 4739
2002-11-18 01:37:48 +00:00
dbdacac022
Set the void flag on instructions that should get it
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llvm-svn: 4738
2002-11-18 01:34:36 +00:00
63d8375f80
Pass on a targetmachine
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llvm-svn: 4736
2002-11-17 23:22:03 +00:00
5fd53046b0
Arrange to have a TargetMachine available in X86InstrInfo::print
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llvm-svn: 4734
2002-11-17 23:20:37 +00:00
b79ccae887
Wow, I'm incapable of the simplest things today...
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llvm-svn: 4732
2002-11-17 23:05:21 +00:00
afce16dec8
Rename registers to follow the intel style of all caps
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llvm-svn: 4731
2002-11-17 23:03:46 +00:00
5961102d31
Fix misleading indentation
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llvm-svn: 4730
2002-11-17 22:57:23 +00:00
9289d7d693
Reorganize printing interface a bit
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llvm-svn: 4728
2002-11-17 22:53:13 +00:00
8693803b48
Add default implementation of printing interface
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llvm-svn: 4727
2002-11-17 22:53:03 +00:00
64c3bb99ed
Fix minor detail
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llvm-svn: 4725
2002-11-17 22:33:26 +00:00
cb57e5ca17
Fix Mul/Div clobbers
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llvm-svn: 4718
2002-11-17 21:56:38 +00:00
ecdb49d74a
Fix a few typos, implement load/store
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llvm-svn: 4716
2002-11-17 21:11:55 +00:00
c682b4a9ab
Add functions to buld X86 specific constructs
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llvm-svn: 4714
2002-11-17 21:03:35 +00:00
6fd0ef303d
Add information about memory index representation
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llvm-svn: 4712
2002-11-17 20:33:26 +00:00
e86f98e06c
Add load/store instructions
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llvm-svn: 4711
2002-11-17 20:33:12 +00:00
Misha Brukman