llvm-project/llvm/test/CodeGen
Simon Pilgrim 64687f2cc3 [X86][SSE] canonicalizeShuffleWithBinOps - add PERMILPS/PERMILPD + PERMPD/PERMQ + INSERTPS handling.
Bail if the INSERTPS would introduce zeros across the binop.
2021-03-16 13:52:08 +00:00
..
AArch64 [AArch64][GlobalISel] Fix crash on lowering <1 x half> types. 2021-03-15 23:27:43 -07:00
AMDGPU [AMDGPU] Fix copyPhysReg to not produce unalined vgpr access 2021-03-15 14:14:30 -07:00
ARC
ARM Test cases for rem-seteq fold with illegal types 2021-03-12 16:28:04 +02:00
AVR [AVR] Fix lifeness issues in the AVR backend 2021-03-04 14:04:39 +01:00
BPF [BPF] Add support for floats and doubles 2021-03-05 15:10:11 +01:00
Generic [PowerPC] Removing _massv place holder 2021-03-08 21:43:24 +00:00
Hexagon
Inputs
Lanai
M68k [M68k][test](6/8) Add all of the tests 2021-03-08 12:30:57 -08:00
MIR [AMDGPU] Use single cache policy operand 2021-03-15 13:00:59 -07:00
MSP430
Mips Test cases for rem-seteq fold with illegal types 2021-03-12 16:28:04 +02:00
NVPTX [NVPTX] CUDA does provide malloc/free since compute capability 2.X 2021-03-15 22:45:56 -05:00
PowerPC [NFC][PowerPC] Add additional load/store test cases 2021-03-15 08:54:38 -05:00
RISCV [RISCV] Add RISCVISD::BR_CC similar to RISCVISD::SELECT_CC. 2021-03-15 11:54:01 -07:00
SPARC [LegalizeTypes] Improve ExpandIntRes_XMULO codegen. 2021-03-01 09:54:32 -08:00
SystemZ [SystemZ] Reimplement the i8/i16 compare-and-swap logic. 2021-03-03 14:04:32 -06:00
Thumb Test cases for rem-seteq fold with illegal types 2021-03-12 16:28:04 +02:00
Thumb2 Test cases for rem-seteq fold with illegal types 2021-03-12 16:28:04 +02:00
VE [test] Fix CodeGen/VE/Scalar tests 2021-03-02 15:30:44 -08:00
WebAssembly [WebAssembly] Fix ExceptionInfo grouping again 2021-03-04 15:05:13 -08:00
WinCFGuard
WinEH
X86 [X86][SSE] canonicalizeShuffleWithBinOps - add PERMILPS/PERMILPD + PERMPD/PERMQ + INSERTPS handling. 2021-03-16 13:52:08 +00:00
XCore [CodeGen] Report a normal instead of fatal error for label redefinition 2021-03-09 10:54:41 +00:00