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llvm-project/llvm/test/CodeGen/MIR
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Stanislav Mekhanoshin 3bffb1cd0e [AMDGPU] Use single cache policy operand 
Replace individual operands GLC, SLC, and DLC with a single cache_policy
bitmask operand. This will reduce the number of operands in MIR and I hope
the amount of code. These operands are mostly 0 anyway.

Additional advantage that parser will accept these flags in any order unlike
now.

Differential Revision: https://reviews.llvm.org/D96469
 		2021-03-15 13:00:59 -07:00
..
AArch64 [mir] Change 'undef' for MMO base addresses to 'unknown-address' 2021-03-10 16:46:44 -08:00
AMDGPU [AMDGPU] Use single cache policy operand 2021-03-15 13:00:59 -07:00
ARM [ARM] Track epilogue instructions with FrameDestroy flag (NFC) 2020-03-18 13:32:59 +00:00
Generic Revert "[DebugInfo] Add new instruction and DIExpression operator for variadic debug values" 2021-03-04 11:59:21 +00:00
Hexagon Reland D73534: [DebugInfo] Enable the debug entry values feature by default 2020-03-19 13:57:30 +01:00
Mips [MIParser] Set RegClassOrRegBank during instruction parsing 2019-10-22 14:25:37 +00:00
NVPTX
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PowerPC
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WebAssembly [WebAssembly] Fix tests missed in rL374235 2019-10-09 23:06:38 +00:00
X86 Reapply "[DebugInfo] Add new instruction and DIExpression operator for variadic debug values" 2021-03-05 12:32:05 +00:00
README
…

README 

This directory contains tests for the MIR file format parser and printer. It
was necessary to split the tests across different targets as no single target
covers all features available in machine IR.

Tests for codegen passes should NOT be here but in test/CodeGen/sometarget. As
a rule of thumb this directory should only contain tests using
'llc -run-pass none'.