149 lines
6.5 KiB
LLVM
149 lines
6.5 KiB
LLVM
; RUN: llc -O0 -global-isel -global-isel-abort=2 -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o %t.out 2> %t.err
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; RUN: FileCheck %s --check-prefix=FALLBACK-WITH-REPORT-OUT < %t.out
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; RUN: FileCheck %s --check-prefix=FALLBACK-WITH-REPORT-ERR < %t.err
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; RUN: not --crash llc -global-isel -mtriple aarch64_be %s -o - 2>&1 | FileCheck %s --check-prefix=BIG-ENDIAN
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; This file checks that the fallback path to selection dag works.
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; The test is fragile in the sense that it must be updated to expose
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; something that fails with global-isel.
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; When we cannot produce a test case anymore, that means we can remove
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; the fallback path.
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target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64--"
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; BIG-ENDIAN: unable to translate in big endian mode
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; Make sure we don't mess up metadata arguments.
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declare void @llvm.write_register.i64(metadata, i64)
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; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: G_WRITE_REGISTER !0, %0:_(s64) (in function: test_write_register_intrin)
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; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for test_write_register_intrin
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; FALLBACK-WITH-REPORT-LABEL: test_write_register_intrin:
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define void @test_write_register_intrin() {
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call void @llvm.write_register.i64(metadata !{!"sp"}, i64 0)
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ret void
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}
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@_ZTIi = external global i8*
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declare i32 @__gxx_personality_v0(...)
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; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: %2:_(<2 x p0>) = G_INSERT_VECTOR_ELT %0:_, %{{[0-9]+}}:_(p0), %{{[0-9]+}}:_(s32) (in function: vector_of_pointers_insertelement)
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; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for vector_of_pointers_insertelement
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; FALLBACK-WITH-REPORT-OUT-LABEL: vector_of_pointers_insertelement:
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define void @vector_of_pointers_insertelement() {
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br label %end
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block:
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%dummy = insertelement <2 x i16*> %vec, i16* null, i32 0
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store <2 x i16*> %dummy, <2 x i16*>* undef
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ret void
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end:
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%vec = load <2 x i16*>, <2 x i16*>* undef
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br label %block
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}
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; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: cannot select: RET_ReallyLR implicit $x0 (in function: strict_align_feature)
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; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for strict_align_feature
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; FALLBACK-WITH-REPORT-OUT-LABEL: strict_align_feature
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define i64 @strict_align_feature(i64* %p) #0 {
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%x = load i64, i64* %p, align 1
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ret i64 %x
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}
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attributes #0 = { "target-features"="+strict-align" }
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; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to translate instruction: call
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; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for direct_mem
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; FALLBACK-WITH-REPORT-OUT-LABEL: direct_mem
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define void @direct_mem(i32 %x, i32 %y) {
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entry:
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tail call void asm sideeffect "", "imr,imr,~{memory}"(i32 %x, i32 %y)
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ret void
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}
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; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to lower function{{.*}}scalable_arg
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; FALLBACK-WITH-REPORT-OUT-LABEL: scalable_arg
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define <vscale x 16 x i8> @scalable_arg(<vscale x 16 x i1> %pred, i8* %addr) #1 {
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%res = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1.nxv16i8(<vscale x 16 x i1> %pred, i8* %addr)
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ret <vscale x 16 x i8> %res
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}
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; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to lower function{{.*}}scalable_ret
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; FALLBACK-WITH-REPORT-OUT-LABEL: scalable_ret
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define <vscale x 16 x i8> @scalable_ret(i8* %addr) #1 {
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%pred = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 0)
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%res = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1.nxv16i8(<vscale x 16 x i1> %pred, i8* %addr)
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ret <vscale x 16 x i8> %res
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}
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; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to translate instruction{{.*}}scalable_call
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; FALLBACK-WITH-REPORT-OUT-LABEL: scalable_call
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define i8 @scalable_call(i8* %addr) #1 {
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%pred = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 0)
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%vec = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1.nxv16i8(<vscale x 16 x i1> %pred, i8* %addr)
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%res = extractelement <vscale x 16 x i8> %vec, i32 0
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ret i8 %res
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}
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; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to translate instruction{{.*}}scalable_alloca
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; FALLBACK-WITH-REPORT-OUT-LABEL: scalable_alloca
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define void @scalable_alloca() #1 {
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%local0 = alloca <vscale x 16 x i8>
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load volatile <vscale x 16 x i8>, <vscale x 16 x i8>* %local0
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ret void
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}
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; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to translate instruction{{.*}}asm_indirect_output
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; FALLBACK-WITH-REPORT-OUT-LABEL: asm_indirect_output
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define void @asm_indirect_output() {
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entry:
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%ap = alloca i8*, align 8
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%0 = load i8*, i8** %ap, align 8
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call void asm sideeffect "", "=*r|m,0,~{memory}"(i8** elementtype(i8*) %ap, i8* %0)
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ret void
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}
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%struct.foo = type { [8 x i64] }
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; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to translate instruction:{{.*}}ld64b{{.*}}asm_output_ls64
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; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for asm_output_ls64
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; FALLBACK-WITH-REPORT-OUT-LABEL: asm_output_ls64
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define void @asm_output_ls64(%struct.foo* %output, i8* %addr) #2 {
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entry:
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%val = call i512 asm sideeffect "ld64b $0,[$1]", "=r,r,~{memory}"(i8* %addr)
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%outcast = bitcast %struct.foo* %output to i512*
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store i512 %val, i512* %outcast, align 8
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ret void
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}
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; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to translate instruction:{{.*}}st64b{{.*}}asm_input_ls64
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; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for asm_input_ls64
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; FALLBACK-WITH-REPORT-OUT-LABEL: asm_input_ls64
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define void @asm_input_ls64(%struct.foo* %input, i8* %addr) #2 {
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entry:
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%incast = bitcast %struct.foo* %input to i512*
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%val = load i512, i512* %incast, align 8
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call void asm sideeffect "st64b $0,[$1]", "r,r,~{memory}"(i512 %val, i8* %addr)
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ret void
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}
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; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: %4:_(s128), %5:_(s1) = G_UMULO %0:_, %6:_ (in function: umul_s128)
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; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for umul_s128
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; FALLBACK-WITH-REPORT-OUT-LABEL: umul_s128
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declare {i128, i1} @llvm.umul.with.overflow.i128(i128, i128) nounwind readnone
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define zeroext i1 @umul_s128(i128 %v1, i128* %res) {
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entry:
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%t = call {i128, i1} @llvm.umul.with.overflow.i128(i128 %v1, i128 2)
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%val = extractvalue {i128, i1} %t, 0
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%obit = extractvalue {i128, i1} %t, 1
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store i128 %val, i128* %res
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ret i1 %obit
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}
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attributes #1 = { "target-features"="+sve" }
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attributes #2 = { "target-features"="+ls64" }
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declare <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 %pattern)
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declare <vscale x 16 x i8> @llvm.aarch64.sve.ld1.nxv16i8(<vscale x 16 x i1>, i8*)
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