500 lines
12 KiB
YAML
500 lines
12 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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--- |
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target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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define void @anyext_s64_from_s32() { ret void }
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define void @anyext_s32_from_s8() { ret void }
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define void @anyext_v8s16_from_v8s8() { ret void }
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define void @anyext_v4s32_from_v4s16() { ret void }
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define void @anyext_v2s64_from_v2s32() { ret void }
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define void @zext_s64_from_s32() { ret void }
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define void @zext_s32_from_s16() { ret void }
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define void @zext_s32_from_s8() { ret void }
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define void @zext_s16_from_s8() { ret void }
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define void @zext_v8s16_from_v8s8() { ret void }
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define void @zext_v4s32_from_v4s16() { ret void }
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define void @zext_v2s64_from_v2s32() { ret void }
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define void @sext_s64_from_s32() { ret void }
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define void @sext_s32_from_s16() { ret void }
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define void @sext_s32_from_s8() { ret void }
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define void @sext_s16_from_s8() { ret void }
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define void @sext_v8s16_from_v8s8() { ret void }
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define void @sext_v4s32_from_v4s16() { ret void }
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define void @sext_v2s64_from_v2s32() { ret void }
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...
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---
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name: anyext_s64_from_s32
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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body: |
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bb.0:
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liveins: $w0
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; CHECK-LABEL: name: anyext_s64_from_s32
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
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; CHECK: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gpr64all = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32
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; CHECK: $x0 = COPY [[INSERT_SUBREG]]
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%0(s32) = COPY $w0
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%1(s64) = G_ANYEXT %0
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$x0 = COPY %1(s64)
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...
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---
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name: anyext_s32_from_s8
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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body: |
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bb.0:
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liveins: $w0
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; CHECK-LABEL: name: anyext_s32_from_s8
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
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; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[COPY]]
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; CHECK: $w0 = COPY [[COPY1]]
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%2:gpr(s32) = COPY $w0
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%0(s8) = G_TRUNC %2
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%1(s32) = G_ANYEXT %0
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$w0 = COPY %1(s32)
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...
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---
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name: anyext_v8s16_from_v8s8
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: anyext_v8s16_from_v8s8
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; CHECK: liveins: $d0
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[USHLLv8i8_shift:%[0-9]+]]:fpr128 = USHLLv8i8_shift [[COPY]], 0
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; CHECK: $q0 = COPY [[USHLLv8i8_shift]]
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; CHECK: RET_ReallyLR implicit $q0
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%0:fpr(<8 x s8>) = COPY $d0
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%1:fpr(<8 x s16>) = G_ANYEXT %0(<8 x s8>)
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$q0 = COPY %1(<8 x s16>)
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RET_ReallyLR implicit $q0
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...
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---
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name: anyext_v4s32_from_v4s16
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: anyext_v4s32_from_v4s16
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; CHECK: liveins: $d0
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[USHLLv4i16_shift:%[0-9]+]]:fpr128 = USHLLv4i16_shift [[COPY]], 0
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; CHECK: $q0 = COPY [[USHLLv4i16_shift]]
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; CHECK: RET_ReallyLR implicit $q0
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%0:fpr(<4 x s16>) = COPY $d0
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%1:fpr(<4 x s32>) = G_ANYEXT %0(<4 x s16>)
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$q0 = COPY %1(<4 x s32>)
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RET_ReallyLR implicit $q0
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...
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---
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name: anyext_v2s64_from_v2s32
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alignment: 4
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tracksRegLiveness: true
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: anyext_v2s64_from_v2s32
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; CHECK: liveins: $d0
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[USHLLv2i32_shift:%[0-9]+]]:fpr128 = USHLLv2i32_shift [[COPY]], 0
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; CHECK: $q0 = COPY [[USHLLv2i32_shift]]
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; CHECK: RET_ReallyLR implicit $q0
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%0:fpr(<2 x s32>) = COPY $d0
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%1:fpr(<2 x s64>) = G_ANYEXT %0(<2 x s32>)
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$q0 = COPY %1(<2 x s64>)
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RET_ReallyLR implicit $q0
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...
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---
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name: zext_s64_from_s32
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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body: |
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bb.0:
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liveins: $w0
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; CHECK-LABEL: name: zext_s64_from_s32
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
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; CHECK: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, [[COPY]], 0
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32
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; CHECK: $x0 = COPY [[SUBREG_TO_REG]]
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%0(s32) = COPY $w0
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%1(s64) = G_ZEXT %0
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$x0 = COPY %1(s64)
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...
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---
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name: zext_s32_from_s16
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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body: |
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bb.0:
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liveins: $w0
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; CHECK-LABEL: name: zext_s32_from_s16
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
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; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY]], 0, 15
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; CHECK: $w0 = COPY [[UBFMWri]]
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%2:gpr(s32) = COPY $w0
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%0(s16) = G_TRUNC %2
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%1(s32) = G_ZEXT %0
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$w0 = COPY %1
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...
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---
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name: zext_s32_from_s8
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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body: |
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bb.0:
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liveins: $w0
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; CHECK-LABEL: name: zext_s32_from_s8
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
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; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY]], 0, 15
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; CHECK: $w0 = COPY [[UBFMWri]]
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%2:gpr(s32) = COPY $w0
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%0(s16) = G_TRUNC %2
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%1(s32) = G_ZEXT %0
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$w0 = COPY %1(s32)
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...
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---
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name: zext_s16_from_s8
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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body: |
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bb.0:
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liveins: $w0
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; CHECK-LABEL: name: zext_s16_from_s8
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
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; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY]], 0, 7
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; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[UBFMWri]]
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; CHECK: $w0 = COPY [[COPY1]]
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%2:gpr(s32) = COPY $w0
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%0(s8) = G_TRUNC %2
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%1(s16) = G_ZEXT %0
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%3:gpr(s32) = G_ANYEXT %1
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$w0 = COPY %3(s32)
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...
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---
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name: zext_v8s16_from_v8s8
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: zext_v8s16_from_v8s8
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; CHECK: liveins: $d0
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[USHLLv8i8_shift:%[0-9]+]]:fpr128 = USHLLv8i8_shift [[COPY]], 0
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; CHECK: $q0 = COPY [[USHLLv8i8_shift]]
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; CHECK: RET_ReallyLR implicit $q0
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%0:fpr(<8 x s8>) = COPY $d0
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%1:fpr(<8 x s16>) = G_ZEXT %0(<8 x s8>)
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$q0 = COPY %1(<8 x s16>)
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RET_ReallyLR implicit $q0
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...
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---
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name: zext_v4s32_from_v4s16
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: zext_v4s32_from_v4s16
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; CHECK: liveins: $d0
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[USHLLv4i16_shift:%[0-9]+]]:fpr128 = USHLLv4i16_shift [[COPY]], 0
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; CHECK: $q0 = COPY [[USHLLv4i16_shift]]
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; CHECK: RET_ReallyLR implicit $q0
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%0:fpr(<4 x s16>) = COPY $d0
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%1:fpr(<4 x s32>) = G_ZEXT %0(<4 x s16>)
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$q0 = COPY %1(<4 x s32>)
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RET_ReallyLR implicit $q0
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...
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---
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name: zext_v2s64_from_v2s32
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: zext_v2s64_from_v2s32
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; CHECK: liveins: $d0
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[USHLLv2i32_shift:%[0-9]+]]:fpr128 = USHLLv2i32_shift [[COPY]], 0
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; CHECK: $q0 = COPY [[USHLLv2i32_shift]]
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; CHECK: RET_ReallyLR implicit $q0
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%0:fpr(<2 x s32>) = COPY $d0
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%1:fpr(<2 x s64>) = G_ZEXT %0(<2 x s32>)
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$q0 = COPY %1(<2 x s64>)
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RET_ReallyLR implicit $q0
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...
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---
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name: sext_s64_from_s32
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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body: |
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bb.0:
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liveins: $w0
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; CHECK-LABEL: name: sext_s64_from_s32
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
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; CHECK: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gpr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32
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; CHECK: [[SBFMXri:%[0-9]+]]:gpr64 = SBFMXri [[INSERT_SUBREG]], 0, 31
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; CHECK: $x0 = COPY [[SBFMXri]]
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%0(s32) = COPY $w0
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%1(s64) = G_SEXT %0
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$x0 = COPY %1(s64)
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...
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---
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name: sext_s32_from_s16
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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body: |
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bb.0:
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liveins: $w0
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; CHECK-LABEL: name: sext_s32_from_s16
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
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; CHECK: [[SBFMWri:%[0-9]+]]:gpr32 = SBFMWri [[COPY]], 0, 15
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; CHECK: $w0 = COPY [[SBFMWri]]
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%2:gpr(s32) = COPY $w0
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%0(s16) = G_TRUNC %2
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%1(s32) = G_SEXT %0
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$w0 = COPY %1
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...
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---
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name: sext_s32_from_s8
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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body: |
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bb.0:
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liveins: $w0
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; CHECK-LABEL: name: sext_s32_from_s8
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
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; CHECK: [[SBFMWri:%[0-9]+]]:gpr32 = SBFMWri [[COPY]], 0, 7
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; CHECK: $w0 = COPY [[SBFMWri]]
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%2:gpr(s32) = COPY $w0
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%0(s8) = G_TRUNC %2
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%1(s32) = G_SEXT %0
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$w0 = COPY %1(s32)
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...
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---
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name: sext_s16_from_s8
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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body: |
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bb.0:
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liveins: $w0
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; CHECK-LABEL: name: sext_s16_from_s8
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
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; CHECK: [[SBFMWri:%[0-9]+]]:gpr32 = SBFMWri [[COPY]], 0, 7
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; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[SBFMWri]]
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; CHECK: $w0 = COPY [[COPY1]]
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%2:gpr(s32) = COPY $w0
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%0(s8) = G_TRUNC %2
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%1(s16) = G_SEXT %0
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%3:gpr(s32) = G_ANYEXT %1
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$w0 = COPY %3(s32)
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...
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---
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name: sext_v8s16_from_v8s8
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: sext_v8s16_from_v8s8
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; CHECK: liveins: $d0
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[SSHLLv8i8_shift:%[0-9]+]]:fpr128 = SSHLLv8i8_shift [[COPY]], 0
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; CHECK: $q0 = COPY [[SSHLLv8i8_shift]]
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; CHECK: RET_ReallyLR implicit $q0
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%0:fpr(<8 x s8>) = COPY $d0
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%1:fpr(<8 x s16>) = G_SEXT %0(<8 x s8>)
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$q0 = COPY %1(<8 x s16>)
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RET_ReallyLR implicit $q0
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...
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---
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name: sext_v4s32_from_v4s16
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: sext_v4s32_from_v4s16
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; CHECK: liveins: $d0
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|
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
|
|
; CHECK: [[SSHLLv4i16_shift:%[0-9]+]]:fpr128 = SSHLLv4i16_shift [[COPY]], 0
|
|
; CHECK: $q0 = COPY [[SSHLLv4i16_shift]]
|
|
; CHECK: RET_ReallyLR implicit $q0
|
|
%0:fpr(<4 x s16>) = COPY $d0
|
|
%1:fpr(<4 x s32>) = G_SEXT %0(<4 x s16>)
|
|
$q0 = COPY %1(<4 x s32>)
|
|
RET_ReallyLR implicit $q0
|
|
...
|
|
|
|
---
|
|
name: sext_v2s64_from_v2s32
|
|
alignment: 4
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
registers:
|
|
- { id: 0, class: fpr }
|
|
- { id: 1, class: fpr }
|
|
machineFunctionInfo: {}
|
|
body: |
|
|
bb.0:
|
|
liveins: $d0
|
|
|
|
; CHECK-LABEL: name: sext_v2s64_from_v2s32
|
|
; CHECK: liveins: $d0
|
|
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
|
|
; CHECK: [[SSHLLv2i32_shift:%[0-9]+]]:fpr128 = SSHLLv2i32_shift [[COPY]], 0
|
|
; CHECK: $q0 = COPY [[SSHLLv2i32_shift]]
|
|
; CHECK: RET_ReallyLR implicit $q0
|
|
%0:fpr(<2 x s32>) = COPY $d0
|
|
%1:fpr(<2 x s64>) = G_SEXT %0(<2 x s32>)
|
|
$q0 = COPY %1(<2 x s64>)
|
|
RET_ReallyLR implicit $q0
|