108 lines
3.3 KiB
LLVM
108 lines
3.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi=ilp32 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32F %s
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; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi=lp64 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64F %s
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@gd = external global double
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define double @constraint_f_double(double %a) nounwind {
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; RV32F-LABEL: constraint_f_double:
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; RV32F: # %bb.0:
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; RV32F-NEXT: addi sp, sp, -16
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; RV32F-NEXT: sw a0, 8(sp)
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; RV32F-NEXT: sw a1, 12(sp)
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; RV32F-NEXT: fld ft0, 8(sp)
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; RV32F-NEXT: lui a0, %hi(gd)
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; RV32F-NEXT: fld ft1, %lo(gd)(a0)
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; RV32F-NEXT: #APP
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; RV32F-NEXT: fadd.d ft0, ft0, ft1
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; RV32F-NEXT: #NO_APP
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; RV32F-NEXT: fsd ft0, 8(sp)
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; RV32F-NEXT: lw a0, 8(sp)
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; RV32F-NEXT: lw a1, 12(sp)
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; RV32F-NEXT: addi sp, sp, 16
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; RV32F-NEXT: ret
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;
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; RV64F-LABEL: constraint_f_double:
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; RV64F: # %bb.0:
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; RV64F-NEXT: lui a1, %hi(gd)
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; RV64F-NEXT: fld ft0, %lo(gd)(a1)
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; RV64F-NEXT: fmv.d.x ft1, a0
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; RV64F-NEXT: #APP
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; RV64F-NEXT: fadd.d ft0, ft1, ft0
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; RV64F-NEXT: #NO_APP
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; RV64F-NEXT: fmv.x.d a0, ft0
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; RV64F-NEXT: ret
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%1 = load double, double* @gd
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%2 = tail call double asm "fadd.d $0, $1, $2", "=f,f,f"(double %a, double %1)
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ret double %2
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}
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define double @constraint_f_double_abi_name(double %a) nounwind {
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; RV32F-LABEL: constraint_f_double_abi_name:
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; RV32F: # %bb.0:
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; RV32F-NEXT: addi sp, sp, -16
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; RV32F-NEXT: sw a0, 8(sp)
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; RV32F-NEXT: sw a1, 12(sp)
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; RV32F-NEXT: fld fa1, 8(sp)
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; RV32F-NEXT: lui a0, %hi(gd)
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; RV32F-NEXT: fld fs0, %lo(gd)(a0)
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; RV32F-NEXT: #APP
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; RV32F-NEXT: fadd.d ft0, fa1, fs0
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; RV32F-NEXT: #NO_APP
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; RV32F-NEXT: fsd ft0, 8(sp)
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; RV32F-NEXT: lw a0, 8(sp)
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; RV32F-NEXT: lw a1, 12(sp)
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; RV32F-NEXT: addi sp, sp, 16
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; RV32F-NEXT: ret
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;
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; RV64F-LABEL: constraint_f_double_abi_name:
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; RV64F: # %bb.0:
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; RV64F-NEXT: lui a1, %hi(gd)
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; RV64F-NEXT: fld fs0, %lo(gd)(a1)
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; RV64F-NEXT: fmv.d.x fa1, a0
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; RV64F-NEXT: #APP
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; RV64F-NEXT: fadd.d ft0, fa1, fs0
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; RV64F-NEXT: #NO_APP
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; RV64F-NEXT: fmv.x.d a0, ft0
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; RV64F-NEXT: ret
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%1 = load double, double* @gd
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%2 = tail call double asm "fadd.d $0, $1, $2", "={ft0},{fa1},{fs0}"(double %a, double %1)
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ret double %2
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}
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define double @constraint_gpr(double %x) {
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; RV32F-LABEL: constraint_gpr:
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; RV32F: # %bb.0:
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; RV32F-NEXT: addi sp, sp, -32
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; RV32F-NEXT: .cfi_def_cfa_offset 32
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; RV32F-NEXT: sw a0, 8(sp)
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; RV32F-NEXT: sw a1, 12(sp)
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; RV32F-NEXT: fld ft0, 8(sp)
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; RV32F-NEXT: fsd ft0, 24(sp)
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; RV32F-NEXT: lw a0, 24(sp)
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; RV32F-NEXT: lw a1, 28(sp)
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; RV32F-NEXT: #APP
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; RV32F-NEXT: mv a0, a0
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; RV32F-NEXT: #NO_APP
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; RV32F-NEXT: sw a1, 20(sp)
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; RV32F-NEXT: sw a0, 16(sp)
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; RV32F-NEXT: fld ft0, 16(sp)
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; RV32F-NEXT: fsd ft0, 8(sp)
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; RV32F-NEXT: lw a0, 8(sp)
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; RV32F-NEXT: lw a1, 12(sp)
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; RV32F-NEXT: addi sp, sp, 32
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; RV32F-NEXT: ret
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;
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; RV64F-LABEL: constraint_gpr:
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; RV64F: # %bb.0:
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; RV64F-NEXT: .cfi_def_cfa_offset 0
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; RV64F-NEXT: #APP
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; RV64F-NEXT: mv a0, a0
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; RV64F-NEXT: #NO_APP
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; RV64F-NEXT: ret
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%1 = tail call double asm sideeffect alignstack "mv $0, $1", "={x10},{x10}"(double %x)
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ret double %1
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}
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