..
GlobalISel
…
intrinsics
…
rvv
[VP] Add splitting for VP_STRIDED_STORE and VP_STRIDED_LOAD
2022-08-19 18:15:56 -07:00
MachineSink-implicit-x0.mir
…
O0-pipeline.ll
[RISCV] Move Pre-RA pseudo expansion from addMachineSSAOptimization to addPreRegAlloc.
2022-08-01 13:44:43 -07:00
O3-pipeline.ll
[RISCV] Pre-RA expand pseudos pass
2022-07-31 23:19:00 +02:00
add-before-shl.ll
…
add-imm.ll
…
addc-adde-sube-subc.ll
…
addcarry.ll
…
addimm-mulimm.ll
…
addrspacecast.ll
…
aext-to-sext.ll
…
align-loops.ll
…
align.ll
…
alloca.ll
…
alu8.ll
[SelectionDAG][RISCV][AMDGPU][ARM] Improve SimplifyDemandedBits for SHL with variable shift amount.
2022-07-14 16:10:14 -07:00
alu16.ll
[SelectionDAG][RISCV][AMDGPU][ARM] Improve SimplifyDemandedBits for SHL with variable shift amount.
2022-07-14 16:10:14 -07:00
alu32.ll
…
alu64.ll
…
analyze-branch.ll
…
and.ll
…
arith-with-overflow.ll
…
atomic-cmpxchg-branch-on-result.ll
[RISCV] Avoid redundant branch-to-branch when expanding cmpxchg
2022-08-17 13:49:15 +01:00
atomic-cmpxchg-flag.ll
…
atomic-cmpxchg.ll
…
atomic-fence.ll
…
atomic-load-store.ll
…
atomic-rmw.ll
…
atomic-signext.ll
[RISCV] Teach ComputeNumSignBitsForTargetNode about masked atomic intrinsics
2022-08-03 13:41:58 +01:00
attributes.ll
[RISCV] Add zihintntl instructions
2022-08-22 12:06:30 +08:00
bitreverse-shift.ll
…
bittest.ll
[RISCV] Combine (select_cc (srl (and X, 1<<C), C), 0, eq/ne, true, fale)
2022-07-20 22:32:11 -07:00
blockaddress.ll
…
branch-relaxation.ll
[RISCV][test] Update branch-relaxation.ll with update_llc_test_checks.py [NFC]
2022-08-25 17:01:34 +08:00
branch.ll
…
bswap-bitreverse.ll
[DAG] Enable ISD::SRL SimplifyMultipleUseDemandedBits handling inside SimplifyDemandedBits
2022-07-28 14:10:44 +01:00
bswap-shift.ll
…
byval.ll
…
callee-saved-fpr32s.ll
…
callee-saved-fpr64s.ll
…
callee-saved-gprs.ll
…
calling-conv-half.ll
…
calling-conv-ilp32-ilp32f-common.ll
…
calling-conv-ilp32-ilp32f-ilp32d-common.ll
…
calling-conv-ilp32.ll
…
calling-conv-ilp32d.ll
…
calling-conv-ilp32f-ilp32d-common.ll
…
calling-conv-lp64-lp64f-common.ll
…
calling-conv-lp64-lp64f-lp64d-common.ll
…
calling-conv-lp64.ll
…
calling-conv-rv32f-ilp32.ll
…
calling-conv-sext-zext.ll
…
calling-conv-vector-float.ll
…
calls.ll
…
cmp-bool.ll
…
codemodel-lowering.ll
[RISCV] Extend the Merge Base Offset pass to handle AUIPC+ADDI
2022-08-01 11:30:02 +02:00
compress-float.ll
…
compress-inline-asm.ll
…
compress.ll
…
copy-frameindex.mir
…
copysign-casts.ll
…
ctlz-cttz-ctpop.ll
[DAG] Emit table lookup from TargetLowering::expandCTTZ()
2022-08-08 12:08:05 +01:00
disable-tail-calls.ll
…
disjoint.ll
…
div-by-constant.ll
[RISCV] Refine the heuristics for our custom (mul (and X, C2), C1) isel.
2022-07-14 18:24:10 -07:00
div-pow2.ll
…
div.ll
[RISCV] Implement isUsedByReturnOnly TargetLowering hook in order to tailcall more libcalls
2022-08-10 10:50:29 +01:00
div_minsize.ll
[RISCV]Enable isIntDivCheap when attribute is minsize
2022-07-27 18:22:51 +08:00
double-arith-strict.ll
…
double-arith.ll
…
double-bitmanip-dagcombines.ll
…
double-br-fcmp.ll
…
double-calling-conv.ll
…
double-convert-strict.ll
…
double-convert.ll
[RISCV] Explicitly select second operand of branch condition to X0.
2022-08-01 11:16:48 -07:00
double-fcmp-strict.ll
…
double-fcmp.ll
…
double-frem.ll
[RISCV] Implement isUsedByReturnOnly TargetLowering hook in order to tailcall more libcalls
2022-08-10 10:50:29 +01:00
double-imm.ll
…
double-intrinsics-strict.ll
…
double-intrinsics.ll
[RISCV] Implement isUsedByReturnOnly TargetLowering hook in order to tailcall more libcalls
2022-08-10 10:50:29 +01:00
double-isnan.ll
…
double-mem.ll
…
double-previous-failure.ll
…
double-round-conv-sat.ll
…
double-round-conv.ll
[RISCV] Implement isUsedByReturnOnly TargetLowering hook in order to tailcall more libcalls
2022-08-10 10:50:29 +01:00
double-select-fcmp.ll
[RISCV] Fold (sub C, (xor (setcc), 1)) -> (add (setcc), C-1).
2022-08-17 09:50:08 -07:00
double-select-icmp.ll
[RISCV] Add test coverage for (select (icmp X, Y), float, float). NFC
2022-08-16 21:28:26 -07:00
double-stack-spill-restore.ll
…
dwarf-eh.ll
…
early-clobber-tied-def-subreg-liveness.ll
…
early-clobber-tied-def-subreg-liveness.mir
…
eh-dwarf-cfa.ll
…
elf-preemption.ll
[RISCV] Pre-RA expand pseudos pass
2022-07-31 23:19:00 +02:00
exception-pointer-register.ll
…
fastcc-float.ll
…
fastcc-int.ll
…
fixed-vectors-vadd-vp-mask.ll
…
fixed-vectors-vmul-vp-mask.ll
…
fixed-vectors-vsub-vp-mask.ll
…
fixups-diff.ll
…
fixups-relax-diff.ll
…
float-arith-strict.ll
…
float-arith.ll
…
float-bit-preserving-dagcombines.ll
…
float-bitmanip-dagcombines.ll
…
float-br-fcmp.ll
…
float-convert-strict.ll
…
float-convert.ll
[RISCV] Explicitly select second operand of branch condition to X0.
2022-08-01 11:16:48 -07:00
float-fcmp-strict.ll
…
float-fcmp.ll
…
float-frem.ll
…
float-imm.ll
…
float-intrinsics-strict.ll
…
float-intrinsics.ll
[RISCV] Implement isUsedByReturnOnly TargetLowering hook in order to tailcall more libcalls
2022-08-10 10:50:29 +01:00
float-isnan.ll
…
float-mem.ll
…
float-round-conv-sat.ll
…
float-round-conv.ll
[RISCV] Implement isUsedByReturnOnly TargetLowering hook in order to tailcall more libcalls
2022-08-10 10:50:29 +01:00
float-select-fcmp.ll
[RISCV] Fold (sub C, (xor (setcc), 1)) -> (add (setcc), C-1).
2022-08-17 09:50:08 -07:00
float-select-icmp.ll
[RISCV] Add test coverage for (select (icmp X, Y), float, float). NFC
2022-08-16 21:28:26 -07:00
flt-rounds.ll
…
fmax-fmin.ll
…
fold-addi-loadstore.ll
[RISCV] Extend the Merge Base Offset pass to handle AUIPC+ADDI
2022-08-01 11:30:02 +02:00
fold-vector-cmp.ll
…
forced-atomics.ll
[RISCV] Optimize x <s -1 ? x : -1. Improve x >u 1 ? x : 1.
2022-08-21 11:48:28 -07:00
fp-imm.ll
…
fp16-promote.ll
[RISCV] Implement isUsedByReturnOnly TargetLowering hook in order to tailcall more libcalls
2022-08-10 10:50:29 +01:00
fp128.ll
…
fpclamptosat.ll
[RISCV] Move xori creation for scalar setccs to lowering.
2022-08-19 13:51:53 -07:00
fpclamptosat_vec.ll
[RISCV] Move xori creation for scalar setccs to lowering.
2022-08-19 13:51:53 -07:00
fpenv.ll
…
frame-info.ll
…
frame.ll
…
frameaddr-returnaddr.ll
…
frm-dependency.ll
…
get-register-invalid.ll
…
get-register-noreserve.ll
…
get-register-reserve.ll
…
get-setcc-result-type.ll
Recommit "[RISCV] Use setcc's original SDLoc when inverting it in performSUBCombine."
2022-08-16 15:51:07 -07:00
ghccc-rv32.ll
…
ghccc-rv64.ll
…
half-arith-strict.ll
…
half-arith.ll
…
half-bitmanip-dagcombines.ll
…
half-br-fcmp.ll
…
half-convert-strict.ll
…
half-convert.ll
[RISCV] Explicitly select second operand of branch condition to X0.
2022-08-01 11:16:48 -07:00
half-fcmp-strict.ll
…
half-fcmp.ll
…
half-frem.ll
…
half-imm.ll
…
half-intrinsics.ll
…
half-isnan.ll
…
half-mem.ll
…
half-round-conv-sat.ll
…
half-round-conv.ll
[RISCV] Add codegen coverage for ceil/floor/trunc/round/roundeven within FPR
2022-07-26 08:48:46 -07:00
half-select-fcmp.ll
[RISCV] Fold (sub C, (xor (setcc), 1)) -> (add (setcc), C-1).
2022-08-17 09:50:08 -07:00
half-select-icmp.ll
[RISCV] Add test coverage for (select (icmp X, Y), float, float). NFC
2022-08-16 21:28:26 -07:00
hoist-global-addr-base.ll
[RISCV] Simplify test case from D130931. NFC
2022-08-01 16:50:56 -07:00
i32-icmp.ll
[RISCV] Use SLTIU X, -1 for (setne X, -1).
2022-08-11 15:36:04 -07:00
i64-icmp.ll
[RISCV] Use SLTIU X, -1 for (setne X, -1).
2022-08-11 15:36:04 -07:00
iabs.ll
[DAG] canCreateUndefOrPoison - add freeze(sign_extend_inreg(x,vt)) -> sign_extend_inreg(freeze(x),vt) support
2022-08-15 12:18:59 +01:00
imm-cse.ll
…
imm.ll
…
indirectbr.ll
…
init-array.ll
…
inline-asm-S-constraint.ll
…
inline-asm-abi-names.ll
…
inline-asm-clobbers.ll
…
inline-asm-d-abi-names.ll
…
inline-asm-d-constraint-f.ll
…
inline-asm-f-abi-names.ll
…
inline-asm-f-constraint-f.ll
…
inline-asm-i-constraint-i1.ll
…
inline-asm-invalid.ll
…
inline-asm-zfh-constraint-f.ll
…
inline-asm.ll
…
interrupt-attr-args-error.ll
…
interrupt-attr-callee.ll
…
interrupt-attr-invalid.ll
…
interrupt-attr-nocall.ll
…
interrupt-attr-ret-error.ll
…
interrupt-attr.ll
…
isel-optnone.ll
…
jumptable.ll
[RISCV] Pre-RA expand pseudos pass
2022-07-31 23:19:00 +02:00
large-stack.ll
…
legalize-fneg.ll
[RISCV] Teach targetShrinkDemandedConstant to handle OR and XOR.
2022-07-17 12:36:33 -07:00
libcall-tail-calls.ll
[RISCV] Implement isUsedByReturnOnly TargetLowering hook in order to tailcall more libcalls
2022-08-10 10:50:29 +01:00
lit.local.cfg
…
live-sp.mir
…
loop-strength-reduce-add-cheaper-than-mul.ll
…
loop-strength-reduce-loop-invar.ll
…
lsr-legaladdimm.ll
…
machine-cp.mir
…
machine-cse.ll
…
machine-outliner-cfi.mir
…
machine-outliner-patchable.ll
…
machine-outliner-position.mir
…
machine-outliner-throw.ll
…
machinelicm-address-pseudos.ll
[RISCV] Extend the Merge Base Offset pass to handle AUIPC+ADDI
2022-08-01 11:30:02 +02:00
machineoutliner-jumptable.mir
…
machineoutliner-pcrel-lo.mir
[RISCV] Don't outline pcrel-lo operand.
2022-08-24 21:47:46 +08:00
machineoutliner.mir
…
macro-fusion-lui-addi.ll
…
make-compressible-for-store-address.mir
…
make-compressible-rv64.mir
…
make-compressible.mir
…
mattr-invalid-combination.ll
…
mem.ll
…
mem64.ll
…
memcpy-inline.ll
…
min-max.ll
[RISCV] Optimize x <s -1 ? x : -1. Improve x >u 1 ? x : 1.
2022-08-21 11:48:28 -07:00
mir-target-flags.ll
[RISCV] Pre-RA expand pseudos pass
2022-07-31 23:19:00 +02:00
miss-sp-restore-eh.ll
…
module-target-abi.ll
…
module-target-abi2.ll
…
mul.ll
[RISCV] Implement isUsedByReturnOnly TargetLowering hook in order to tailcall more libcalls
2022-08-10 10:50:29 +01:00
musttail-call.ll
…
narrow-shl-cst.ll
[RISCV] Reorder (and/or/xor (shl X, C1), C2) if we can form ANDI/ORI/XORI.
2022-07-27 17:35:26 -07:00
neg-abs.ll
…
nomerge.ll
…
option-nopic.ll
…
option-norelax.ll
…
option-norvc.ll
…
option-pic.ll
…
option-relax.ll
…
option-rvc.ll
…
optnone-store-no-combine.ll
…
out-of-reach-emergency-slot.mir
…
overflow-intrinsic-optimizations.ll
…
patchable-function-entry.ll
…
pic-models.ll
[RISCV] Pre-RA expand pseudos pass
2022-07-31 23:19:00 +02:00
pr40333.ll
…
pr51206.ll
…
pr53662.mir
…
pr55201.ll
…
pr56110.ll
…
pr56457.ll
…
prefetch.ll
[IR] Update llvm.prefetch to match docs
2022-08-19 09:11:17 +01:00
readcyclecounter.ll
…
regalloc-last-chance-recoloring-failure.ll
…
rem.ll
[RISCV] Implement isUsedByReturnOnly TargetLowering hook in order to tailcall more libcalls
2022-08-10 10:50:29 +01:00
remat.ll
…
reserved-reg-errors.ll
…
reserved-regs.ll
…
riscv-codegenprepare-asm.ll
[RISCV] Teach RISCVCodeGenPrepare to optimize (i64 (and (zext/sext (i32 X), C1)))
2022-07-17 11:00:56 -07:00
riscv-codegenprepare.ll
[RISCV] Teach RISCVCodeGenPrepare to optimize (i64 (and (zext/sext (i32 X), C1)))
2022-07-17 11:00:56 -07:00
rotl-rotr.ll
[DAGCombine] Mask doesn't have to be (EltSize - 1) exactly when combining rotation
2022-07-26 21:14:45 +08:00
rv32e.ll
…
rv32i-rv64i-float-double.ll
…
rv32i-rv64i-half.ll
…
rv32zba.ll
[RISCV] Don't use li+sh3add for constants that can use lui+add.
2022-08-05 12:47:03 -07:00
rv32zbb-intrinsic.ll
…
rv32zbb-zbp-zbkb.ll
[RISCV] Explicitly select second operand of branch condition to X0.
2022-08-01 11:16:48 -07:00
rv32zbb.ll
[DAG] Emit table lookup from TargetLowering::expandCTTZ()
2022-08-08 12:08:05 +01:00
rv32zbc-intrinsic.ll
…
rv32zbc-zbkc-intrinsic.ll
…
rv32zbe-intrinsic.ll
…
rv32zbf-intrinsic.ll
…
rv32zbkb-intrinsic.ll
…
rv32zbkx-intrinsic.ll
…
rv32zbp-intrinsic.ll
…
rv32zbp-zbkb.ll
…
rv32zbp.ll
[DAG] SimplifyDemandedBits - don't early-out for multiple use values
2022-07-27 10:54:06 +01:00
rv32zbr.ll
…
rv32zbs.ll
[RISCV] Recognize bexti from (srl (and X, 1<<C), C).
2022-07-20 15:03:52 -07:00
rv32zbt-intrinsic.ll
…
rv32zbt.ll
[RISCV] Move xori creation for scalar setccs to lowering.
2022-08-19 13:51:53 -07:00
rv32zknd-intrinsic.ll
…
rv32zkne-intrinsic.ll
…
rv32zknh-intrinsic.ll
…
rv32zksed-intrinsic.ll
…
rv32zksh-intrinsic.ll
…
rv64-large-stack.ll
…
rv64d-double-convert-strict.ll
…
rv64d-double-convert.ll
…
rv64f-float-convert-strict.ll
…
rv64f-float-convert.ll
…
rv64i-complex-float.ll
…
rv64i-demanded-bits.ll
[RISCV] Teach targetShrinkDemandedConstant to handle OR and XOR.
2022-07-17 12:36:33 -07:00
rv64i-double-softfloat.ll
…
rv64i-exhaustive-w-insts.ll
…
rv64i-shift-sext.ll
[RISCV] Relax another one use restriction in performSRACombine.
2022-08-04 14:32:31 -07:00
rv64i-single-softfloat.ll
…
rv64i-tricky-shifts.ll
…
rv64i-w-insts-legalization.ll
…
rv64m-exhaustive-w-insts.ll
…
rv64m-w-insts-legalization.ll
…
rv64zba.ll
[RISCV] Don't use li+sh3add for constants that can use lui+add.
2022-08-05 12:47:03 -07:00
rv64zbb-intrinsic.ll
…
rv64zbb-zbp-zbkb.ll
[DAG] Enable ISD::SRL SimplifyMultipleUseDemandedBits handling inside SimplifyDemandedBits
2022-07-28 14:10:44 +01:00
rv64zbb.ll
[DAG] canCreateUndefOrPoison - add freeze(assertsext/zext(x,bt)) -> assertsext/zext(freeze(x),vt) support
2022-08-15 11:13:43 +01:00
rv64zbc-intrinsic.ll
…
rv64zbc-zbkc-intrinsic.ll
…
rv64zbe-intrinsic.ll
…
rv64zbf-intrinsic.ll
…
rv64zbkb-intrinsic.ll
…
rv64zbkx-intrinsic.ll
…
rv64zbp-intrinsic.ll
…
rv64zbp-zbkb.ll
…
rv64zbp.ll
[DAG] Enable ISD::SRL SimplifyMultipleUseDemandedBits handling inside SimplifyDemandedBits
2022-07-28 14:10:44 +01:00
rv64zbr.ll
…
rv64zbs.ll
[RISCV] Recognize bexti from (srl (and X, 1<<C), C).
2022-07-20 15:03:52 -07:00
rv64zbt-intrinsic.ll
…
rv64zbt.ll
…
rv64zfh-half-convert-strict.ll
…
rv64zfh-half-convert.ll
…
rv64zfh-half-intrinsics-strict.ll
…
rv64zfh-half-intrinsics.ll
…
rv64zknd-intrinsic.ll
…
rv64zknd-zkne-intrinsic.ll
…
rv64zkne-intrinsic.ll
…
rv64zknh-intrinsic.ll
…
rv64zksed-intrinsic.ll
…
rv64zksh-intrinsic.ll
…
sadd_sat.ll
…
sadd_sat_plus.ll
…
saverestore.ll
…
scalable-vector-struct.ll
…
sdata-limit-0.ll
…
sdata-limit-4.ll
…
sdata-limit-8.ll
…
sdata-local-sym.ll
…
select-and.ll
…
select-bare.ll
…
select-binop-identity.ll
…
select-cc.ll
[RISCV] Move xori creation for scalar setccs to lowering.
2022-08-19 13:51:53 -07:00
select-const.ll
[RISCV] Remove C!=0 restriction from (sub C, (setcc x, y, eq/neq)) -> (add C-1, (setcc x, y, neq/eq)).
2022-08-16 14:49:52 -07:00
select-constant-xor.ll
…
select-optimize-multiple.ll
…
select-optimize-multiple.mir
…
select-or.ll
…
selectcc-to-shiftand.ll
…
setcc-logic.ll
[RISCV] Pre-commit tests for D132614. NFC
2022-08-24 15:31:17 -07:00
sext-zext-trunc.ll
[RISCV] Remove C!=0 restriction from (sub C, (setcc x, y, eq/neq)) -> (add C-1, (setcc x, y, neq/eq)).
2022-08-16 14:49:52 -07:00
sextw-removal.ll
[DAG] Enable ISD::SRL SimplifyMultipleUseDemandedBits handling inside SimplifyDemandedBits
2022-07-28 14:10:44 +01:00
shadowcallstack.ll
…
shift-and.ll
…
shift-masked-shamt.ll
[RISCV] Explicitly select second operand of branch condition to X0.
2022-08-01 11:16:48 -07:00
shifts.ll
[RISCV] Explicitly select second operand of branch condition to X0.
2022-08-01 11:16:48 -07:00
shl-demanded.ll
[SelectionDAG][RISCV][AMDGPU][ARM] Improve SimplifyDemandedBits for SHL with variable shift amount.
2022-07-14 16:10:14 -07:00
shlimm-addimm.ll
…
shrinkwrap.ll
…
sink-icmp.ll
…
spill-fpr-scalar.ll
…
split-offsets.ll
…
split-sp-adjust.ll
…
split-udiv-by-constant.ll
[X86][RISCV] Pre-commit tests for D130862. NFC
2022-08-14 16:31:15 -07:00
split-urem-by-constant.ll
[X86][RISCV] Pre-commit tests for D130862. NFC
2022-08-14 16:31:15 -07:00
srem-lkk.ll
[RISCV] Implement isUsedByReturnOnly TargetLowering hook in order to tailcall more libcalls
2022-08-10 10:50:29 +01:00
srem-seteq-illegal-types.ll
Recommit "[RISCV] Use setcc's original SDLoc when inverting it in performSUBCombine."
2022-08-16 15:51:07 -07:00
srem-vector-lkk.ll
…
ssub_sat.ll
…
ssub_sat_plus.ll
…
stack-folding.ll
[RISCV] Add sext.b/h and zext.b/h/w to RISCVInstrInfo::foldMemoryOperandImpl.
2022-07-21 14:54:58 -07:00
stack-realignment-with-variable-sized-objects.ll
…
stack-realignment.ll
…
stack-slot-size.ll
…
stack-store-check.ll
…
subtarget-features-std-ext.ll
…
switch-width.ll
…
tail-calls.ll
…
target-abi-invalid.ll
…
target-abi-valid.ll
…
thread-pointer.ll
…
tls-models.ll
[RISCV] Pre-RA expand pseudos pass
2022-07-31 23:19:00 +02:00
trunc-free.ll
[RISCV] Enable isTruncateFree in SDAG for i64->i32 on rv64.
2022-08-15 08:32:51 -07:00
uadd_sat.ll
…
uadd_sat_plus.ll
…
umulo-128-legalisation-lowering.ll
…
unaligned-load-store.ll
…
unfold-masked-merge-scalar-variablemask.ll
…
unroll-loop-cse.ll
…
urem-lkk.ll
[RISCV] Implement isUsedByReturnOnly TargetLowering hook in order to tailcall more libcalls
2022-08-10 10:50:29 +01:00
urem-seteq-illegal-types.ll
[RISCV] Move xori creation for scalar setccs to lowering.
2022-08-19 13:51:53 -07:00
urem-vector-lkk.ll
…
usub_sat.ll
…
usub_sat_plus.ll
…
vadd-vp-mask.ll
…
vararg.ll
…
vec3-setcc-crash.ll
[RISCV] Pin a test to scalar lowering to preserve test intent [nfc]
2022-08-09 10:12:18 -07:00
vector-abi.ll
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verify-instr.mir
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vlenb.ll
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vmul-vp-mask.ll
…
vsub-vp-mask.ll
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wide-mem.ll
…
xaluo.ll
[RISCV] Move xori creation for scalar setccs to lowering.
2022-08-19 13:51:53 -07:00
zext-with-load-is-free.ll
…
zfh-half-intrinsics-strict.ll
…
zfh-half-intrinsics.ll
…
zfh-imm.ll
…
zmmul.ll
[RISCV][Clang] Add support for Zmmul extension
2022-07-18 20:26:08 -04:00
