66 lines
2.4 KiB
LLVM
66 lines
2.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zfh \
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; RUN: -verify-machineinstrs -target-abi ilp32f -disable-strictnode-mutation \
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; RUN: | FileCheck -check-prefix=RV32IZFH %s
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; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zfh \
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; RUN: -verify-machineinstrs -target-abi lp64f -disable-strictnode-mutation \
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; RUN: | FileCheck -check-prefix=RV64IZFH %s
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; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d \
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; RUN: -mattr=+zfh -verify-machineinstrs -target-abi ilp32d \
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; RUN: -disable-strictnode-mutation | FileCheck -check-prefix=RV32IDZFH %s
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; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d \
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; RUN: -mattr=+zfh -verify-machineinstrs -target-abi lp64d \
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; RUN: -disable-strictnode-mutation | FileCheck -check-prefix=RV64IDZFH %s
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declare iXLen @llvm.experimental.constrained.lrint.iXLen.f16(half, metadata, metadata)
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define iXLen @lrint_f16(half %a) nounwind strictfp {
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; RV32IZFH-LABEL: lrint_f16:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: fcvt.w.h a0, fa0
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: lrint_f16:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fcvt.l.h a0, fa0
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; RV64IZFH-NEXT: ret
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;
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; RV32IDZFH-LABEL: lrint_f16:
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; RV32IDZFH: # %bb.0:
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; RV32IDZFH-NEXT: fcvt.w.h a0, fa0
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; RV32IDZFH-NEXT: ret
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;
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; RV64IDZFH-LABEL: lrint_f16:
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; RV64IDZFH: # %bb.0:
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; RV64IDZFH-NEXT: fcvt.l.h a0, fa0
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; RV64IDZFH-NEXT: ret
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%1 = call iXLen @llvm.experimental.constrained.lrint.iXLen.f16(half %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
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ret iXLen %1
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}
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declare iXLen @llvm.experimental.constrained.lround.iXLen.f16(half, metadata)
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define iXLen @lround_f16(half %a) nounwind strictfp {
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; RV32IZFH-LABEL: lround_f16:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rmm
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: lround_f16:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rmm
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; RV64IZFH-NEXT: ret
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;
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; RV32IDZFH-LABEL: lround_f16:
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; RV32IDZFH: # %bb.0:
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; RV32IDZFH-NEXT: fcvt.w.h a0, fa0, rmm
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; RV32IDZFH-NEXT: ret
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;
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; RV64IDZFH-LABEL: lround_f16:
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; RV64IDZFH: # %bb.0:
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; RV64IDZFH-NEXT: fcvt.l.h a0, fa0, rmm
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; RV64IDZFH-NEXT: ret
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%1 = call iXLen @llvm.experimental.constrained.lround.iXLen.f16(half %a, metadata !"fpexcept.strict") strictfp
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ret iXLen %1
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}
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