315 lines
7.5 KiB
YAML
315 lines
7.5 KiB
YAML
# RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2,+hwdiv -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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--- |
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define void @test_add_regs() { ret void }
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define void @test_add_fold_imm() { ret void }
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define void @test_add_fold_imm12() { ret void }
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define void @test_add_no_fold_imm() { ret void }
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define void @test_sub_imm_lhs() { ret void }
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define void @test_sub_imm_rhs() { ret void }
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define void @test_mul() { ret void }
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define void @test_mla() { ret void }
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define void @test_sdiv() { ret void }
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define void @test_udiv() { ret void }
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...
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---
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name: test_add_regs
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# CHECK-LABEL: name: test_add_regs
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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body: |
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bb.0:
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liveins: $r0, $r1
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%0(s32) = COPY $r0
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; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0
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%1(s32) = COPY $r1
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; CHECK: [[VREGY:%[0-9]+]]:rgpr = COPY $r1
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%2(s32) = G_ADD %0, %1
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; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = t2ADDrr [[VREGX]], [[VREGY]], 14, $noreg, $noreg
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$r0 = COPY %2(s32)
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; CHECK: $r0 = COPY [[VREGRES]]
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BX_RET 14, $noreg, implicit $r0
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; CHECK: BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_add_fold_imm
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# CHECK-LABEL: name: test_add_fold_imm
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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body: |
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bb.0:
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liveins: $r0
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%0(s32) = COPY $r0
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; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0
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%1(s32) = G_CONSTANT i32 786444 ; 0x000c000c
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%2(s32) = G_ADD %0, %1
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; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = t2ADDri [[VREGX]], 786444, 14, $noreg, $noreg
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$r0 = COPY %2(s32)
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; CHECK: $r0 = COPY [[VREGRES]]
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BX_RET 14, $noreg, implicit $r0
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; CHECK: BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_add_fold_imm12
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# CHECK-LABEL: name: test_add_fold_imm12
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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body: |
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bb.0:
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liveins: $r0
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%0(s32) = COPY $r0
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; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
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%1(s32) = G_CONSTANT i32 4093
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%2(s32) = G_ADD %0, %1
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; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = t2ADDri12 [[VREGX]], 4093, 14, $noreg
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$r0 = COPY %2(s32)
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; CHECK: $r0 = COPY [[VREGRES]]
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BX_RET 14, $noreg, implicit $r0
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; CHECK: BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_add_no_fold_imm
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# CHECK-LABEL: name: test_add_no_fold_imm
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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body: |
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bb.0:
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liveins: $r0
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%0(s32) = COPY $r0
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; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0
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%1(s32) = G_CONSTANT i32 185470479 ; 0x0b0e0e0f
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; CHECK: [[VREGY:%[0-9]+]]:rgpr = t2MOVi32imm 185470479
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%2(s32) = G_ADD %0, %1
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; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = t2ADDrr [[VREGX]], [[VREGY]], 14, $noreg, $noreg
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$r0 = COPY %2(s32)
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; CHECK: $r0 = COPY [[VREGRES]]
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BX_RET 14, $noreg, implicit $r0
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; CHECK: BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_sub_imm_lhs
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# CHECK-LABEL: name: test_sub_imm_lhs
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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body: |
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bb.0:
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liveins: $r0
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%0(s32) = COPY $r0
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; CHECK: [[VREGX:%[0-9]+]]:rgpr = COPY $r0
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%1(s32) = G_CONSTANT i32 786444 ; 0x000c000c
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%2(s32) = G_SUB %1, %0
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; CHECK: [[VREGRES:%[0-9]+]]:rgpr = t2RSBri [[VREGX]], 786444, 14, $noreg, $noreg
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$r0 = COPY %2(s32)
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; CHECK: $r0 = COPY [[VREGRES]]
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BX_RET 14, $noreg, implicit $r0
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; CHECK: BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_sub_imm_rhs
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# CHECK-LABEL: name: test_sub_imm_rhs
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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body: |
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bb.0:
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liveins: $r0
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%0(s32) = COPY $r0
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; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0
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%1(s32) = G_CONSTANT i32 786444 ; 0x000c000c
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%2(s32) = G_SUB %0, %1
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; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = t2SUBri [[VREGX]], 786444, 14, $noreg, $noreg
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$r0 = COPY %2(s32)
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; CHECK: $r0 = COPY [[VREGRES]]
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BX_RET 14, $noreg, implicit $r0
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; CHECK: BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_mul
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# CHECK-LABEL: name: test_mul
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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body: |
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bb.0:
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liveins: $r0, $r1
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%0(s32) = COPY $r0
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; CHECK: [[VREGX:%[0-9]+]]:rgpr = COPY $r0
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%1(s32) = COPY $r1
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; CHECK: [[VREGY:%[0-9]+]]:rgpr = COPY $r1
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%2(s32) = G_MUL %0, %1
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; CHECK: [[VREGRES:%[0-9]+]]:rgpr = t2MUL [[VREGX]], [[VREGY]], 14, $noreg
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$r0 = COPY %2(s32)
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; CHECK: $r0 = COPY [[VREGRES]]
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BX_RET 14, $noreg, implicit $r0
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; CHECK: BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_mla
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# CHECK-LABEL: name: test_mla
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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- { id: 3, class: gprb }
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- { id: 4, class: gprb }
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body: |
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bb.0:
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liveins: $r0, $r1, $r2
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%0(s32) = COPY $r0
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; CHECK: [[VREGX:%[0-9]+]]:rgpr = COPY $r0
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%1(s32) = COPY $r1
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; CHECK: [[VREGY:%[0-9]+]]:rgpr = COPY $r1
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%2(s32) = COPY $r2
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; CHECK: [[VREGZ:%[0-9]+]]:rgpr = COPY $r2
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%3(s32) = G_MUL %0, %1
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%4(s32) = G_ADD %3, %2
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; CHECK: [[VREGRES:%[0-9]+]]:rgpr = t2MLA [[VREGX]], [[VREGY]], [[VREGZ]], 14, $noreg
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$r0 = COPY %4(s32)
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; CHECK: $r0 = COPY [[VREGRES]]
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BX_RET 14, $noreg, implicit $r0
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; CHECK: BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_sdiv
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# CHECK-LABEL: name: test_sdiv
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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body: |
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bb.0:
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liveins: $r0, $r1
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%0(s32) = COPY $r0
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; CHECK: [[VREGX:%[0-9]+]]:rgpr = COPY $r0
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%1(s32) = COPY $r1
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; CHECK: [[VREGY:%[0-9]+]]:rgpr = COPY $r1
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%2(s32) = G_SDIV %0, %1
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; CHECK: [[VREGRES:%[0-9]+]]:rgpr = t2SDIV [[VREGX]], [[VREGY]], 14, $noreg
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$r0 = COPY %2(s32)
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; CHECK: $r0 = COPY [[VREGRES]]
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BX_RET 14, $noreg, implicit $r0
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; CHECK: BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_udiv
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# CHECK-LABEL: name: test_udiv
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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body: |
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bb.0:
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liveins: $r0, $r1
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%0(s32) = COPY $r0
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; CHECK: [[VREGX:%[0-9]+]]:rgpr = COPY $r0
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%1(s32) = COPY $r1
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; CHECK: [[VREGY:%[0-9]+]]:rgpr = COPY $r1
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%2(s32) = G_UDIV %0, %1
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; CHECK: [[VREGRES:%[0-9]+]]:rgpr = t2UDIV [[VREGX]], [[VREGY]], 14, $noreg
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$r0 = COPY %2(s32)
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; CHECK: $r0 = COPY [[VREGRES]]
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BX_RET 14, $noreg, implicit $r0
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; CHECK: BX_RET 14, $noreg, implicit $r0
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...
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