462 lines
19 KiB
C++
462 lines
19 KiB
C++
//===-- AArch64ELFObjectWriter.cpp - AArch64 ELF Writer -------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file handles ELF-specific object emission, converting LLVM's internal
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// fixups into the appropriate relocations.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/AArch64FixupKinds.h"
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#include "MCTargetDesc/AArch64MCExpr.h"
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#include "MCTargetDesc/AArch64MCTargetDesc.h"
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#include "llvm/BinaryFormat/ELF.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCELFObjectWriter.h"
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#include "llvm/MC/MCFixup.h"
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#include "llvm/MC/MCObjectWriter.h"
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#include "llvm/MC/MCValue.h"
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#include "llvm/Support/ErrorHandling.h"
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#include <cassert>
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#include <cstdint>
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using namespace llvm;
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namespace {
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class AArch64ELFObjectWriter : public MCELFObjectTargetWriter {
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public:
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AArch64ELFObjectWriter(uint8_t OSABI, bool IsILP32);
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~AArch64ELFObjectWriter() override = default;
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protected:
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unsigned getRelocType(MCContext &Ctx, const MCValue &Target,
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const MCFixup &Fixup, bool IsPCRel) const override;
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bool IsILP32;
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};
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} // end anonymous namespace
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AArch64ELFObjectWriter::AArch64ELFObjectWriter(uint8_t OSABI, bool IsILP32)
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: MCELFObjectTargetWriter(/*Is64Bit*/ !IsILP32, OSABI, ELF::EM_AARCH64,
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/*HasRelocationAddend*/ true),
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IsILP32(IsILP32) {}
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#define R_CLS(rtype) \
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IsILP32 ? ELF::R_AARCH64_P32_##rtype : ELF::R_AARCH64_##rtype
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#define BAD_ILP32_MOV(lp64rtype) \
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"ILP32 absolute MOV relocation not " \
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"supported (LP64 eqv: " #lp64rtype ")"
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// assumes IsILP32 is true
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static bool isNonILP32reloc(const MCFixup &Fixup,
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AArch64MCExpr::VariantKind RefKind,
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MCContext &Ctx) {
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if (Fixup.getTargetKind() != AArch64::fixup_aarch64_movw)
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return false;
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switch (RefKind) {
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case AArch64MCExpr::VK_ABS_G3:
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Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_UABS_G3));
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return true;
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case AArch64MCExpr::VK_ABS_G2:
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Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_UABS_G2));
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return true;
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case AArch64MCExpr::VK_ABS_G2_S:
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Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_SABS_G2));
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return true;
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case AArch64MCExpr::VK_ABS_G2_NC:
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Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_UABS_G2_NC));
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return true;
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case AArch64MCExpr::VK_ABS_G1_S:
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Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_SABS_G1));
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return true;
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case AArch64MCExpr::VK_ABS_G1_NC:
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Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_UABS_G1_NC));
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return true;
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case AArch64MCExpr::VK_DTPREL_G2:
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Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSLD_MOVW_DTPREL_G2));
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return true;
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case AArch64MCExpr::VK_DTPREL_G1_NC:
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Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSLD_MOVW_DTPREL_G1_NC));
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return true;
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case AArch64MCExpr::VK_TPREL_G2:
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Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSLE_MOVW_TPREL_G2));
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return true;
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case AArch64MCExpr::VK_TPREL_G1_NC:
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Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSLE_MOVW_TPREL_G1_NC));
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return true;
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case AArch64MCExpr::VK_GOTTPREL_G1:
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Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSIE_MOVW_GOTTPREL_G1));
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return true;
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case AArch64MCExpr::VK_GOTTPREL_G0_NC:
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Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSIE_MOVW_GOTTPREL_G0_NC));
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return true;
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default:
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return false;
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}
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return false;
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}
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unsigned AArch64ELFObjectWriter::getRelocType(MCContext &Ctx,
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const MCValue &Target,
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const MCFixup &Fixup,
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bool IsPCRel) const {
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unsigned Kind = Fixup.getTargetKind();
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if (Kind >= FirstLiteralRelocationKind)
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return Kind - FirstLiteralRelocationKind;
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AArch64MCExpr::VariantKind RefKind =
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static_cast<AArch64MCExpr::VariantKind>(Target.getRefKind());
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AArch64MCExpr::VariantKind SymLoc = AArch64MCExpr::getSymbolLoc(RefKind);
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bool IsNC = AArch64MCExpr::isNotChecked(RefKind);
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assert((!Target.getSymA() ||
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Target.getSymA()->getKind() == MCSymbolRefExpr::VK_None ||
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Target.getSymA()->getKind() == MCSymbolRefExpr::VK_PLT) &&
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"Should only be expression-level modifiers here");
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assert((!Target.getSymB() ||
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Target.getSymB()->getKind() == MCSymbolRefExpr::VK_None) &&
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"Should only be expression-level modifiers here");
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if (IsPCRel) {
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switch (Kind) {
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case FK_Data_1:
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Ctx.reportError(Fixup.getLoc(), "1-byte data relocations not supported");
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return ELF::R_AARCH64_NONE;
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case FK_Data_2:
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return R_CLS(PREL16);
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case FK_Data_4: {
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return Target.getAccessVariant() == MCSymbolRefExpr::VK_PLT
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? R_CLS(PLT32)
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: R_CLS(PREL32);
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}
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case FK_Data_8:
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if (IsILP32) {
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Ctx.reportError(Fixup.getLoc(),
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"ILP32 8 byte PC relative data "
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"relocation not supported (LP64 eqv: PREL64)");
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return ELF::R_AARCH64_NONE;
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} else
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return ELF::R_AARCH64_PREL64;
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case AArch64::fixup_aarch64_pcrel_adr_imm21:
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if (SymLoc != AArch64MCExpr::VK_ABS)
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Ctx.reportError(Fixup.getLoc(),
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"invalid symbol kind for ADR relocation");
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return R_CLS(ADR_PREL_LO21);
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case AArch64::fixup_aarch64_pcrel_adrp_imm21:
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if (SymLoc == AArch64MCExpr::VK_ABS && !IsNC)
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return R_CLS(ADR_PREL_PG_HI21);
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if (SymLoc == AArch64MCExpr::VK_ABS && IsNC) {
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if (IsILP32) {
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Ctx.reportError(Fixup.getLoc(),
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"invalid fixup for 32-bit pcrel ADRP instruction "
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"VK_ABS VK_NC");
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return ELF::R_AARCH64_NONE;
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} else {
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return ELF::R_AARCH64_ADR_PREL_PG_HI21_NC;
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}
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}
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if (SymLoc == AArch64MCExpr::VK_GOT && !IsNC)
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return R_CLS(ADR_GOT_PAGE);
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if (SymLoc == AArch64MCExpr::VK_GOTTPREL && !IsNC)
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return R_CLS(TLSIE_ADR_GOTTPREL_PAGE21);
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if (SymLoc == AArch64MCExpr::VK_TLSDESC && !IsNC)
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return R_CLS(TLSDESC_ADR_PAGE21);
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Ctx.reportError(Fixup.getLoc(),
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"invalid symbol kind for ADRP relocation");
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return ELF::R_AARCH64_NONE;
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case AArch64::fixup_aarch64_pcrel_branch26:
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return R_CLS(JUMP26);
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case AArch64::fixup_aarch64_pcrel_call26:
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return R_CLS(CALL26);
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case AArch64::fixup_aarch64_ldr_pcrel_imm19:
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if (SymLoc == AArch64MCExpr::VK_GOTTPREL)
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return R_CLS(TLSIE_LD_GOTTPREL_PREL19);
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if (SymLoc == AArch64MCExpr::VK_GOT)
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return R_CLS(GOT_LD_PREL19);
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return R_CLS(LD_PREL_LO19);
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case AArch64::fixup_aarch64_pcrel_branch14:
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return R_CLS(TSTBR14);
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case AArch64::fixup_aarch64_pcrel_branch19:
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return R_CLS(CONDBR19);
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default:
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Ctx.reportError(Fixup.getLoc(), "Unsupported pc-relative fixup kind");
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return ELF::R_AARCH64_NONE;
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}
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} else {
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if (IsILP32 && isNonILP32reloc(Fixup, RefKind, Ctx))
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return ELF::R_AARCH64_NONE;
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switch (Fixup.getTargetKind()) {
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case FK_Data_1:
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Ctx.reportError(Fixup.getLoc(), "1-byte data relocations not supported");
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return ELF::R_AARCH64_NONE;
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case FK_Data_2:
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return R_CLS(ABS16);
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case FK_Data_4:
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return R_CLS(ABS32);
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case FK_Data_8:
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if (IsILP32) {
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Ctx.reportError(Fixup.getLoc(),
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"ILP32 8 byte absolute data "
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"relocation not supported (LP64 eqv: ABS64)");
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return ELF::R_AARCH64_NONE;
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} else
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return ELF::R_AARCH64_ABS64;
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case AArch64::fixup_aarch64_add_imm12:
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if (RefKind == AArch64MCExpr::VK_DTPREL_HI12)
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return R_CLS(TLSLD_ADD_DTPREL_HI12);
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if (RefKind == AArch64MCExpr::VK_TPREL_HI12)
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return R_CLS(TLSLE_ADD_TPREL_HI12);
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if (RefKind == AArch64MCExpr::VK_DTPREL_LO12_NC)
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return R_CLS(TLSLD_ADD_DTPREL_LO12_NC);
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if (RefKind == AArch64MCExpr::VK_DTPREL_LO12)
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return R_CLS(TLSLD_ADD_DTPREL_LO12);
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if (RefKind == AArch64MCExpr::VK_TPREL_LO12_NC)
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return R_CLS(TLSLE_ADD_TPREL_LO12_NC);
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if (RefKind == AArch64MCExpr::VK_TPREL_LO12)
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return R_CLS(TLSLE_ADD_TPREL_LO12);
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if (RefKind == AArch64MCExpr::VK_TLSDESC_LO12)
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return R_CLS(TLSDESC_ADD_LO12);
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if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)
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return R_CLS(ADD_ABS_LO12_NC);
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Ctx.reportError(Fixup.getLoc(),
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"invalid fixup for add (uimm12) instruction");
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return ELF::R_AARCH64_NONE;
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case AArch64::fixup_aarch64_ldst_imm12_scale1:
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if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)
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return R_CLS(LDST8_ABS_LO12_NC);
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if (SymLoc == AArch64MCExpr::VK_DTPREL && !IsNC)
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return R_CLS(TLSLD_LDST8_DTPREL_LO12);
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if (SymLoc == AArch64MCExpr::VK_DTPREL && IsNC)
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return R_CLS(TLSLD_LDST8_DTPREL_LO12_NC);
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if (SymLoc == AArch64MCExpr::VK_TPREL && !IsNC)
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return R_CLS(TLSLE_LDST8_TPREL_LO12);
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if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC)
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return R_CLS(TLSLE_LDST8_TPREL_LO12_NC);
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Ctx.reportError(Fixup.getLoc(),
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"invalid fixup for 8-bit load/store instruction");
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return ELF::R_AARCH64_NONE;
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case AArch64::fixup_aarch64_ldst_imm12_scale2:
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if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)
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return R_CLS(LDST16_ABS_LO12_NC);
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if (SymLoc == AArch64MCExpr::VK_DTPREL && !IsNC)
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return R_CLS(TLSLD_LDST16_DTPREL_LO12);
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if (SymLoc == AArch64MCExpr::VK_DTPREL && IsNC)
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return R_CLS(TLSLD_LDST16_DTPREL_LO12_NC);
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if (SymLoc == AArch64MCExpr::VK_TPREL && !IsNC)
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return R_CLS(TLSLE_LDST16_TPREL_LO12);
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if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC)
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return R_CLS(TLSLE_LDST16_TPREL_LO12_NC);
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Ctx.reportError(Fixup.getLoc(),
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"invalid fixup for 16-bit load/store instruction");
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return ELF::R_AARCH64_NONE;
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case AArch64::fixup_aarch64_ldst_imm12_scale4:
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if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)
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return R_CLS(LDST32_ABS_LO12_NC);
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if (SymLoc == AArch64MCExpr::VK_DTPREL && !IsNC)
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return R_CLS(TLSLD_LDST32_DTPREL_LO12);
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if (SymLoc == AArch64MCExpr::VK_DTPREL && IsNC)
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return R_CLS(TLSLD_LDST32_DTPREL_LO12_NC);
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if (SymLoc == AArch64MCExpr::VK_TPREL && !IsNC)
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return R_CLS(TLSLE_LDST32_TPREL_LO12);
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if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC)
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return R_CLS(TLSLE_LDST32_TPREL_LO12_NC);
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if (SymLoc == AArch64MCExpr::VK_GOT && IsNC) {
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if (IsILP32) {
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return ELF::R_AARCH64_P32_LD32_GOT_LO12_NC;
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} else {
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Ctx.reportError(Fixup.getLoc(),
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"LP64 4 byte unchecked GOT load/store relocation "
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"not supported (ILP32 eqv: LD32_GOT_LO12_NC");
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return ELF::R_AARCH64_NONE;
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}
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}
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if (SymLoc == AArch64MCExpr::VK_GOT && !IsNC) {
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if (IsILP32) {
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Ctx.reportError(Fixup.getLoc(),
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"ILP32 4 byte checked GOT load/store relocation "
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"not supported (unchecked eqv: LD32_GOT_LO12_NC)");
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} else {
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Ctx.reportError(Fixup.getLoc(),
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"LP64 4 byte checked GOT load/store relocation "
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"not supported (unchecked/ILP32 eqv: "
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"LD32_GOT_LO12_NC)");
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}
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return ELF::R_AARCH64_NONE;
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}
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if (SymLoc == AArch64MCExpr::VK_GOTTPREL && IsNC) {
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if (IsILP32) {
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return ELF::R_AARCH64_P32_TLSIE_LD32_GOTTPREL_LO12_NC;
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} else {
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Ctx.reportError(Fixup.getLoc(),
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"LP64 32-bit load/store "
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"relocation not supported (ILP32 eqv: "
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"TLSIE_LD32_GOTTPREL_LO12_NC)");
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return ELF::R_AARCH64_NONE;
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}
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}
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if (SymLoc == AArch64MCExpr::VK_TLSDESC && !IsNC) {
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if (IsILP32) {
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return ELF::R_AARCH64_P32_TLSDESC_LD32_LO12;
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} else {
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Ctx.reportError(Fixup.getLoc(),
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"LP64 4 byte TLSDESC load/store relocation "
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"not supported (ILP32 eqv: TLSDESC_LD64_LO12)");
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return ELF::R_AARCH64_NONE;
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}
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}
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Ctx.reportError(Fixup.getLoc(),
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"invalid fixup for 32-bit load/store instruction "
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"fixup_aarch64_ldst_imm12_scale4");
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return ELF::R_AARCH64_NONE;
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case AArch64::fixup_aarch64_ldst_imm12_scale8:
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if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)
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return R_CLS(LDST64_ABS_LO12_NC);
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if (SymLoc == AArch64MCExpr::VK_GOT && IsNC) {
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AArch64MCExpr::VariantKind AddressLoc =
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AArch64MCExpr::getAddressFrag(RefKind);
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if (!IsILP32) {
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if (AddressLoc == AArch64MCExpr::VK_LO15)
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return ELF::R_AARCH64_LD64_GOTPAGE_LO15;
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return ELF::R_AARCH64_LD64_GOT_LO12_NC;
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} else {
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Ctx.reportError(Fixup.getLoc(), "ILP32 64-bit load/store "
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"relocation not supported (LP64 eqv: "
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"LD64_GOT_LO12_NC)");
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return ELF::R_AARCH64_NONE;
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}
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}
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if (SymLoc == AArch64MCExpr::VK_DTPREL && !IsNC)
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return R_CLS(TLSLD_LDST64_DTPREL_LO12);
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if (SymLoc == AArch64MCExpr::VK_DTPREL && IsNC)
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return R_CLS(TLSLD_LDST64_DTPREL_LO12_NC);
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if (SymLoc == AArch64MCExpr::VK_TPREL && !IsNC)
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return R_CLS(TLSLE_LDST64_TPREL_LO12);
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if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC)
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return R_CLS(TLSLE_LDST64_TPREL_LO12_NC);
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if (SymLoc == AArch64MCExpr::VK_GOTTPREL && IsNC) {
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if (!IsILP32) {
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return ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC;
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} else {
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Ctx.reportError(Fixup.getLoc(), "ILP32 64-bit load/store "
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"relocation not supported (LP64 eqv: "
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"TLSIE_LD64_GOTTPREL_LO12_NC)");
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return ELF::R_AARCH64_NONE;
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}
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}
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if (SymLoc == AArch64MCExpr::VK_TLSDESC) {
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if (!IsILP32) {
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return ELF::R_AARCH64_TLSDESC_LD64_LO12;
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} else {
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Ctx.reportError(Fixup.getLoc(), "ILP32 64-bit load/store "
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"relocation not supported (LP64 eqv: "
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"TLSDESC_LD64_LO12)");
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return ELF::R_AARCH64_NONE;
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}
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}
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Ctx.reportError(Fixup.getLoc(),
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"invalid fixup for 64-bit load/store instruction");
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return ELF::R_AARCH64_NONE;
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case AArch64::fixup_aarch64_ldst_imm12_scale16:
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if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)
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return R_CLS(LDST128_ABS_LO12_NC);
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if (SymLoc == AArch64MCExpr::VK_DTPREL && !IsNC)
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return R_CLS(TLSLD_LDST128_DTPREL_LO12);
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if (SymLoc == AArch64MCExpr::VK_DTPREL && IsNC)
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return R_CLS(TLSLD_LDST128_DTPREL_LO12_NC);
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if (SymLoc == AArch64MCExpr::VK_TPREL && !IsNC)
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return R_CLS(TLSLE_LDST128_TPREL_LO12);
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if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC)
|
|
return R_CLS(TLSLE_LDST128_TPREL_LO12_NC);
|
|
|
|
Ctx.reportError(Fixup.getLoc(),
|
|
"invalid fixup for 128-bit load/store instruction");
|
|
return ELF::R_AARCH64_NONE;
|
|
// ILP32 case not reached here, tested with isNonILP32reloc
|
|
case AArch64::fixup_aarch64_movw:
|
|
if (RefKind == AArch64MCExpr::VK_ABS_G3)
|
|
return ELF::R_AARCH64_MOVW_UABS_G3;
|
|
if (RefKind == AArch64MCExpr::VK_ABS_G2)
|
|
return ELF::R_AARCH64_MOVW_UABS_G2;
|
|
if (RefKind == AArch64MCExpr::VK_ABS_G2_S)
|
|
return ELF::R_AARCH64_MOVW_SABS_G2;
|
|
if (RefKind == AArch64MCExpr::VK_ABS_G2_NC)
|
|
return ELF::R_AARCH64_MOVW_UABS_G2_NC;
|
|
if (RefKind == AArch64MCExpr::VK_ABS_G1)
|
|
return R_CLS(MOVW_UABS_G1);
|
|
if (RefKind == AArch64MCExpr::VK_ABS_G1_S)
|
|
return ELF::R_AARCH64_MOVW_SABS_G1;
|
|
if (RefKind == AArch64MCExpr::VK_ABS_G1_NC)
|
|
return ELF::R_AARCH64_MOVW_UABS_G1_NC;
|
|
if (RefKind == AArch64MCExpr::VK_ABS_G0)
|
|
return R_CLS(MOVW_UABS_G0);
|
|
if (RefKind == AArch64MCExpr::VK_ABS_G0_S)
|
|
return R_CLS(MOVW_SABS_G0);
|
|
if (RefKind == AArch64MCExpr::VK_ABS_G0_NC)
|
|
return R_CLS(MOVW_UABS_G0_NC);
|
|
if (RefKind == AArch64MCExpr::VK_PREL_G3)
|
|
return ELF::R_AARCH64_MOVW_PREL_G3;
|
|
if (RefKind == AArch64MCExpr::VK_PREL_G2)
|
|
return ELF::R_AARCH64_MOVW_PREL_G2;
|
|
if (RefKind == AArch64MCExpr::VK_PREL_G2_NC)
|
|
return ELF::R_AARCH64_MOVW_PREL_G2_NC;
|
|
if (RefKind == AArch64MCExpr::VK_PREL_G1)
|
|
return R_CLS(MOVW_PREL_G1);
|
|
if (RefKind == AArch64MCExpr::VK_PREL_G1_NC)
|
|
return ELF::R_AARCH64_MOVW_PREL_G1_NC;
|
|
if (RefKind == AArch64MCExpr::VK_PREL_G0)
|
|
return R_CLS(MOVW_PREL_G0);
|
|
if (RefKind == AArch64MCExpr::VK_PREL_G0_NC)
|
|
return R_CLS(MOVW_PREL_G0_NC);
|
|
if (RefKind == AArch64MCExpr::VK_DTPREL_G2)
|
|
return ELF::R_AARCH64_TLSLD_MOVW_DTPREL_G2;
|
|
if (RefKind == AArch64MCExpr::VK_DTPREL_G1)
|
|
return R_CLS(TLSLD_MOVW_DTPREL_G1);
|
|
if (RefKind == AArch64MCExpr::VK_DTPREL_G1_NC)
|
|
return ELF::R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC;
|
|
if (RefKind == AArch64MCExpr::VK_DTPREL_G0)
|
|
return R_CLS(TLSLD_MOVW_DTPREL_G0);
|
|
if (RefKind == AArch64MCExpr::VK_DTPREL_G0_NC)
|
|
return R_CLS(TLSLD_MOVW_DTPREL_G0_NC);
|
|
if (RefKind == AArch64MCExpr::VK_TPREL_G2)
|
|
return ELF::R_AARCH64_TLSLE_MOVW_TPREL_G2;
|
|
if (RefKind == AArch64MCExpr::VK_TPREL_G1)
|
|
return R_CLS(TLSLE_MOVW_TPREL_G1);
|
|
if (RefKind == AArch64MCExpr::VK_TPREL_G1_NC)
|
|
return ELF::R_AARCH64_TLSLE_MOVW_TPREL_G1_NC;
|
|
if (RefKind == AArch64MCExpr::VK_TPREL_G0)
|
|
return R_CLS(TLSLE_MOVW_TPREL_G0);
|
|
if (RefKind == AArch64MCExpr::VK_TPREL_G0_NC)
|
|
return R_CLS(TLSLE_MOVW_TPREL_G0_NC);
|
|
if (RefKind == AArch64MCExpr::VK_GOTTPREL_G1)
|
|
return ELF::R_AARCH64_TLSIE_MOVW_GOTTPREL_G1;
|
|
if (RefKind == AArch64MCExpr::VK_GOTTPREL_G0_NC)
|
|
return ELF::R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC;
|
|
Ctx.reportError(Fixup.getLoc(),
|
|
"invalid fixup for movz/movk instruction");
|
|
return ELF::R_AARCH64_NONE;
|
|
case AArch64::fixup_aarch64_tlsdesc_call:
|
|
return R_CLS(TLSDESC_CALL);
|
|
default:
|
|
Ctx.reportError(Fixup.getLoc(), "Unknown ELF relocation type");
|
|
return ELF::R_AARCH64_NONE;
|
|
}
|
|
}
|
|
|
|
llvm_unreachable("Unimplemented fixup -> relocation");
|
|
}
|
|
|
|
std::unique_ptr<MCObjectTargetWriter>
|
|
llvm::createAArch64ELFObjectWriter(uint8_t OSABI, bool IsILP32) {
|
|
return std::make_unique<AArch64ELFObjectWriter>(OSABI, IsILP32);
|
|
}
|