88 lines
3.1 KiB
YAML
88 lines
3.1 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc %s -o - -run-pass=machine-sink -mtriple=arm-none-eabi | FileCheck %s
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--- |
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target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "arm-none-unknown-eabi"
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%struct.anon = type { i32, i32 }
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@e = external constant [2 x %struct.anon], align 4
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define arm_aapcscc void @g(i32 * noalias %a, i32 *%b, i32 %x) {
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entry:
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%c = getelementptr inbounds [2 x %struct.anon], [2 x %struct.anon]* @e, i32 0, i32 %x, i32 0
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%l1 = load i32, i32* %c, align 4
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%d = getelementptr inbounds [2 x %struct.anon], [2 x %struct.anon]* @e, i32 0, i32 %x, i32 1
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%l2 = load i32, i32* %d, align 4
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br i1 undef, label %land.lhs.true, label %if.end
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land.lhs.true: ; preds = %entry
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br label %if.end
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if.end: ; preds = %land.lhs.true, %entry
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%h.0 = phi i32 [ %l1, %entry ], [ 0, %land.lhs.true ]
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ret void
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}
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...
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---
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name: g
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gpr, preferred-register: '' }
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- { id: 1, class: gpr, preferred-register: '' }
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- { id: 2, class: gpr, preferred-register: '' }
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- { id: 6, class: gpr, preferred-register: '' }
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- { id: 7, class: gpr, preferred-register: '' }
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- { id: 8, class: gpr, preferred-register: '' }
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- { id: 9, class: gprnopc, preferred-register: '' }
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liveins:
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- { reg: '$r0', virtual-reg: '%8' }
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- { reg: '$r1', virtual-reg: '%9' }
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liveins: []
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body: |
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; CHECK-LABEL: name: g
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; CHECK: bb.0:
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; CHECK: successors: %bb.1(0x40000000), %bb.3(0x40000000)
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; CHECK: liveins: $r0, $r1
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; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r1
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; CHECK: [[COPY1:%[0-9]+]]:gprnopc = COPY $r0
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; CHECK: [[LDR_PRE_REG:%[0-9]+]]:gpr, [[LDR_PRE_REG1:%[0-9]+]]:gpr = LDR_PRE_REG [[COPY]], killed [[COPY1]], 16387, 14 /* CC::al */, $noreg :: (load 4 from %ir.c)
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; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 /* CC::al */, $noreg, $noreg
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; CHECK: CMPri [[MOVi]], 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
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; CHECK: Bcc %bb.1, 0 /* CC::eq */, $cpsr
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; CHECK: bb.3:
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; CHECK: successors: %bb.2(0x80000000)
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; CHECK: B %bb.2
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; CHECK: bb.1:
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; CHECK: successors: %bb.2(0x80000000)
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; CHECK: bb.2:
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; CHECK: [[PHI:%[0-9]+]]:gpr = PHI [[LDR_PRE_REG]], %bb.3, [[MOVi]], %bb.1
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; CHECK: CMPri [[MOVi]], 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
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; CHECK: [[LDRi12_:%[0-9]+]]:gpr = LDRi12 killed [[LDR_PRE_REG1]], 4, 14 /* CC::al */, $noreg :: (load 4 from %ir.d)
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; CHECK: MOVPCLR 14 /* CC::al */, $noreg
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bb.0:
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liveins: $r0, $r1
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successors: %bb.1(0x40000000), %bb.2(0x40000000)
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%8:gpr = COPY $r1
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%9:gprnopc = COPY $r0
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%0:gpr, %6:gpr = LDR_PRE_REG %8, killed %9, 16387, 14, $noreg :: (load 4 from %ir.c)
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%7:gpr = MOVi 0, 14, $noreg, $noreg
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CMPri %7, 0, 14, $noreg, implicit-def $cpsr
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Bcc %bb.2, 1, $cpsr
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B %bb.1
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bb.1:
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successors: %bb.2(0x80000000)
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bb.2:
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%2:gpr = PHI %0, %bb.0, %7, %bb.1
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CMPri %7, 0, 14, $noreg, implicit-def $cpsr
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%1:gpr = LDRi12 killed %6, 4, 14, $noreg :: (load 4 from %ir.d)
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MOVPCLR 14, $noreg
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...
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