174 lines
4.1 KiB
LLVM
174 lines
4.1 KiB
LLVM
; RUN: llc -mtriple armv6t2 %s -o - | FileCheck %s
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; RUN: llc -mtriple thumbv6t2 %s -o - | FileCheck %s --check-prefix=CHECK-T2
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; RUN: llc -mtriple armv7 %s -o - | FileCheck %s
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; RUN: llc -mtriple thumbv7 %s -o - | FileCheck %s --check-prefix=CHECK-T2
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; RUN: llc -mtriple thumbv7m %s -o - | FileCheck %s --check-prefix=CHECK-T2
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; RUN: llc -mtriple thumbv8m.main %s -o - | FileCheck %s --check-prefix=CHECK-T2
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; CHECK-LABEL: unfold1
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; CHECK-NOT: mov
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; CHECK: orr r0, r0, #255
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; CHECK: add r0, r1, r0, lsl #1
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; CHECK-T2-NOT: mov
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; CHECK-T2: orr r0, r0, #255
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; CHECK-T2: add.w r0, r1, r0, lsl #1
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define arm_aapcscc i32 @unfold1(i32 %a, i32 %b) {
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entry:
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%or = shl i32 %a, 1
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%shl = or i32 %or, 510
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%add = add nsw i32 %shl, %b
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ret i32 %add
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}
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; CHECK-LABEL: unfold2
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; CHECK-NOT: mov
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; CHECK: orr r0, r0, #4080
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; CHECK: sub r0, r1, r0, lsl #2
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; CHECK-T2-NOT: mov
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; CHECK-T2: orr r0, r0, #4080
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; CHECK-T2: sub.w r0, r1, r0, lsl #2
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define arm_aapcscc i32 @unfold2(i32 %a, i32 %b) {
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entry:
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%or = shl i32 %a, 2
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%shl = or i32 %or, 16320
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%sub = sub nsw i32 %b, %shl
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ret i32 %sub
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}
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; CHECK-LABEL: unfold3
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; CHECK-NOT: mov
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; CHECK: orr r0, r0, #65280
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; CHECK: and r0, r1, r0, lsl #4
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; CHECK-T2-NOT: mov
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; CHECK-T2: orr r0, r0, #65280
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; CHECK-T2: and.w r0, r1, r0, lsl #4
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define arm_aapcscc i32 @unfold3(i32 %a, i32 %b) {
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entry:
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%or = shl i32 %a, 4
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%shl = or i32 %or, 1044480
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%and = and i32 %shl, %b
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ret i32 %and
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}
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; CHECK-LABEL: unfold4
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; CHECK-NOT: mov
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; CHECK: orr r0, r0, #1044480
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; CHECK: eor r0, r1, r0, lsl #5
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; CHECK-T2-NOT: mov
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; CHECK-T2: orr r0, r0, #1044480
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; CHECK-T2: eor.w r0, r1, r0, lsl #5
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define arm_aapcscc i32 @unfold4(i32 %a, i32 %b) {
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entry:
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%or = shl i32 %a, 5
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%shl = or i32 %or, 33423360
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%xor = xor i32 %shl, %b
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ret i32 %xor
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}
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; CHECK-LABEL: unfold5
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; CHECK-NOT: mov
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; CHECK: add r0, r0, #496
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; CHECK: orr r0, r1, r0, lsl #6
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; CHECK-T2: add.w r0, r0, #496
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; CHECK-T2: orr.w r0, r1, r0, lsl #6
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define arm_aapcscc i32 @unfold5(i32 %a, i32 %b) {
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entry:
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%add = shl i32 %a, 6
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%shl = add i32 %add, 31744
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%or = or i32 %shl, %b
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ret i32 %or
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}
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; CHECK-LABEL: unfold6
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; CHECK-NOT: mov
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; CHECK: add r0, r0, #7936
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; CHECK: and r0, r1, r0, lsl #8
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; CHECK-T2-NOT: mov
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; CHECK-T2: add.w r0, r0, #7936
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; CHECK-T2: and.w r0, r1, r0, lsl #8
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define arm_aapcscc i32 @unfold6(i32 %a, i32 %b) {
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entry:
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%add = shl i32 %a, 8
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%shl = add i32 %add, 2031616
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%and = and i32 %shl, %b
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ret i32 %and
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}
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; CHECK-LABEL: unfold7
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; CHECK-NOT: mov
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; CHECK: and r0, r0, #256
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; CHECK: add r0, r1, r0, lsl #1
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; CHECK-T2-NOT: mov
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; CHECK-T2: and r0, r0, #256
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; CHECK-T2: add.w r0, r1, r0, lsl #1
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define arm_aapcscc i32 @unfold7(i32 %a, i32 %b) {
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entry:
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%shl = shl i32 %a, 1
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%and = and i32 %shl, 512
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%add = add nsw i32 %and, %b
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ret i32 %add
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}
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; CHECK-LABEL: unfold8
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; CHECK-NOT: mov
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; CHECK: add r0, r0, #126976
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; CHECK: eor r0, r1, r0, lsl #9
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; CHECK-T2-NOT: mov
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; CHECK-T2: add.w r0, r0, #126976
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; CHECK-T2: eor.w r0, r1, r0, lsl #9
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define arm_aapcscc i32 @unfold8(i32 %a, i32 %b) {
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entry:
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%add = shl i32 %a, 9
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%shl = add i32 %add, 65011712
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%xor = xor i32 %shl, %b
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ret i32 %xor
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}
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; CHECK-LABEL: unfold9
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; CHECK-NOT: mov
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; CHECK: eor r0, r0, #255
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; CHECK: add r0, r1, r0, lsl #1
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; CHECK-T2-NOT: mov
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; CHECK-T2: eor r0, r0, #255
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; CHECK-T2: add.w r0, r1, r0, lsl #1
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define arm_aapcscc i32 @unfold9(i32 %a, i32 %b) {
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entry:
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%shl = shl i32 %a, 1
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%xor = xor i32 %shl, 510
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%add = add nsw i32 %xor, %b
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ret i32 %add
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}
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; CHECK-LABEL: unfold10
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; CHECK-NOT: mov r2
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; CHECK: orr r2, r0, #4080
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; CHECK: cmp r1, r2, lsl #10
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; CHECK-T2-NOT: mov.w r2
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; CHECK-T2: orr r2, r0, #4080
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; CHECK-T2: cmp.w r1, r2, lsl #10
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define arm_aapcscc i32 @unfold10(i32 %a, i32 %b) {
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entry:
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%or = shl i32 %a, 10
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%shl = or i32 %or, 4177920
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%cmp = icmp sgt i32 %shl, %b
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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; CHECK-LABEL: unfold11
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; CHECK-NOT: mov r2
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; CHECK: add r2, r0, #7936
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; CHECK: cmp r1, r2, lsl #11
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; CHECK-T2-NOT: mov.w r2
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; CHECK-T2: add.w r2, r0, #7936
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; CHECK-T2: cmp.w r1, r2, lsl #11
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define arm_aapcscc i32 @unfold11(i32 %a, i32 %b) {
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entry:
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%add = shl i32 %a, 11
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%shl = add i32 %add, 16252928
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%cmp = icmp sgt i32 %shl, %b
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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